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ixgbe: consolidate all setting of MRQC into one function
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
134MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515exit:
516 return;
517}
518
5eba3699
AV		 519static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520{
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 527}
528
529static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530{
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 537}
9a799d71 538
e8e26350
PW		 539/*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
9a799d71
AK		 549{
550 u32 ivar, index;
e8e26350
PW		 551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
9a799d71
AK		 586}
587
fe49f04a
AD		 588static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590{
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602}
603
9a799d71 604static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
9a799d71 607{
e5a43549
AD		 608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
1b507730 610 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 611 tx_buffer_info->dma,
612 tx_buffer_info->length,
1b507730 613 DMA_TO_DEVICE);
e5a43549 614 else
1b507730 615 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 616 tx_buffer_info->dma,
617 tx_buffer_info->length,
1b507730 618 DMA_TO_DEVICE);
e5a43549
AD		 619 tx_buffer_info->dma = 0;
620 }
9a799d71
AK		 621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
44df32c5 625 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 626 /* tx_buffer_info must be completely set up in the transmit path */
627}
628
26f23d82 629/**
7483d9dd 630 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
7483d9dd 637 * Returns : true if in xon state (currently not paused)
26f23d82 638 */
7483d9dd 639static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
26f23d82
YZ		 640 struct ixgbe_ring *tx_ring)
641{
26f23d82
YZ		 642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644#ifdef CONFIG_IXGBE_DCB
ca739481 645 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 646 int tc;
26f23d82
YZ		 647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
6837e895
PW		 650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
26f23d82
YZ		 652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 654 break;
655 case ixgbe_mac_82599EB:
26f23d82
YZ		 656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
6837e895
PW		 674 break;
675 default:
676 tc = 0;
26f23d82
YZ		 677 }
678 txoff <<= tc;
679 }
680#endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682}
683
9a799d71 684static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
9a799d71 687{
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
9a799d71 690 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 691 * check with the clearing of time_stamp and movement of eop */
9a799d71 692 adapter->detect_tx_hung = false;
44df32c5 693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 695 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 696 /* detected Tx unit hang */
e01c31a5
JB		 697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
396e799c 699 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 712 return true;
713 }
714
715 return false;
716}
717
b4617240
PW		 718#define IXGBE_MAX_TXD_PWR 14
719#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 720
721/* Tx Descriptors needed, worst case */
722#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 726
e01c31a5
JB		 727static void ixgbe_tx_timeout(struct net_device *netdev);
728
9a799d71
AK		 729/**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 731 * @q_vector: structure containing interrupt and ring information
e01c31a5 732 * @tx_ring: tx ring to clean
9a799d71 733 **/
fe49f04a 734static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 735 struct ixgbe_ring *tx_ring)
9a799d71 736{
fe49f04a 737 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 738 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
e01c31a5 742 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 743
744 i = tx_ring->next_to_clean;
12207e49
PWJ		 745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 749 (count < tx_ring->work_limit)) {
12207e49 750 bool cleaned = false;
2d0bb1c1 751 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
9a799d71
AK		 754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 756 cleaned = (i == eop);
e01c31a5 757 skb = tx_buffer_info->skb;
9a799d71 758
12207e49 759 if (cleaned && skb) {
e092be60 760 unsigned int segs, bytecount;
3d8fd385 761 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 762
763 /* gso_segs is currently only valid for tcp */
e092be60 764 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 765#ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776#endif /* IXGBE_FCOE */
e092be60 777 /* multiply data chunks by size of headers */
3d8fd385 778 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 779 total_packets += segs;
780 total_bytes += bytecount;
e092be60 781 }
e01c31a5 782
9a799d71 783 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 784 tx_buffer_info);
9a799d71 785
12207e49
PWJ		 786 tx_desc->wb.status = 0;
787
9a799d71
AK		 788 i++;
789 if (i == tx_ring->count)
790 i = 0;
e01c31a5 791 }
12207e49
PWJ		 792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
795 }
796
9a799d71
AK		 797 tx_ring->next_to_clean = i;
798
e092be60 799#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
30eba97a
AV		 806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 809 ++tx_ring->restart_queue;
30eba97a 810 }
e092be60 811 }
9a799d71 812
e01c31a5
JB		 813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
396e799c
ET		 816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
9a799d71 821
e01c31a5 822 /* re-arm the interrupt */
fe49f04a
AD		 823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 825
e01c31a5
JB		 826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
e01c31a5 828 tx_ring->stats.packets += total_packets;
12207e49 829 tx_ring->stats.bytes += total_bytes;
9a1a69ad 830 return (count < tx_ring->work_limit);
9a799d71
AK		 831}
832
5dd2d332 833#ifdef CONFIG_IXGBE_DCA
bd0362dd 834static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 835 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 836{
837 u32 rxctrl;
838 int cpu = get_cpu();
4a0b9ca0 839 int q = rx_ring->reg_idx;
bd0362dd 840
3a581073 841 if (rx_ring->cpu != cpu) {
bd0362dd 842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
bd0362dd
JC		 851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 857 rx_ring->cpu = cpu;
bd0362dd
JC		 858 }
859 put_cpu();
860}
861
862static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 863 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 864{
865 u32 txctrl;
866 int cpu = get_cpu();
4a0b9ca0 867 int q = tx_ring->reg_idx;
ee5f784a 868 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 869
3a581073 870 if (tx_ring->cpu != cpu) {
e8e26350 871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 884 }
3a581073 885 tx_ring->cpu = cpu;
bd0362dd
JC		 886 }
887 put_cpu();
888}
889
890static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891{
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
e35ec126
AD		 897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
bd0362dd 900 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 907 }
908}
909
910static int __ixgbe_notify_dca(struct device *dev, void *data)
911{
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
652f093f 921 if (dca_add_requester(dev) == 0) {
96b0e0f6 922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
652f093f 936 return 0;
bd0362dd
JC		 937}
938
5dd2d332 939#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 940/**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
177db6ff
MC		 944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
9a799d71 947 **/
78b6f4ce 948static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 949 struct sk_buff *skb, u8 status,
fdaff1ce 950 struct ixgbe_ring *ring,
177db6ff 951 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 952{
78b6f4ce
HX		 953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 957
182ff8df 958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 961 else
78b6f4ce 962 napi_gro_receive(napi, skb);
177db6ff 963 } else {
8a62babf 964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
966 else
967 netif_rx(skb);
9a799d71
AK		 968 }
969}
970
e59bd25d
AV		 971/**
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
976 **/
9a799d71 977static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 978 union ixgbe_adv_rx_desc *rx_desc,
979 struct sk_buff *skb)
9a799d71 980{
8bae1b2b
DS		 981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
982
9a799d71
AK		 983 skb->ip_summed = CHECKSUM_NONE;
984
712744be
JB		 985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 987 return;
e59bd25d
AV		 988
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 992 adapter->hw_csum_rx_error++;
993 return;
994 }
e59bd25d
AV		 995
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
997 return;
998
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002 /*
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 * checksum errors.
1005 */
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008 return;
1009
e59bd25d
AV		 1010 adapter->hw_csum_rx_error++;
1011 return;
1012 }
1013
9a799d71 1014 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1016}
1017
e8e26350
PW		 1018static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1020{
1021 /*
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1025 * such as IA-64).
1026 */
1027 wmb();
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029}
1030
9a799d71
AK		 1031/**
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1034 **/
1035static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 1036 struct ixgbe_ring *rx_ring,
1037 int cleaned_count)
9a799d71 1038{
d716a7d8 1039 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1042 struct ixgbe_rx_buffer *bi;
9a799d71 1043 unsigned int i;
d716a7d8 1044 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1045
1046 i = rx_ring->next_to_use;
3a581073 1047 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1048
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
762f4c57 1052 if (!bi->page_dma &&
6e455b89 1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1054 if (!bi->page) {
d716a7d8 1055 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1056 if (!bi->page) {
1057 adapter->alloc_rx_page_failed++;
1058 goto no_buffers;
1059 }
1060 bi->page_offset = 0;
1061 } else {
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1064 }
762f4c57 1065
1b507730 1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 1067 bi->page_offset,
1068 (PAGE_SIZE / 2),
1b507730 1069 DMA_FROM_DEVICE);
9a799d71
AK		 1070 }
1071
3a581073 1072 if (!bi->skb) {
d716a7d8
AD		 1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074 bufsz);
1075 bi->skb = skb;
9a799d71
AK		 1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
d716a7d8
AD		 1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1083 }
9a799d71 1084
d716a7d8
AD		 1085 if (!bi->dma) {
1086 bi->dma = dma_map_single(&pdev->dev,
1087 bi->skb->data,
4f57ca6e 1088 rx_ring->rx_buf_len,
1b507730 1089 DMA_FROM_DEVICE);
9a799d71
AK		 1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
6e455b89 1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1096 } else {
3a581073 1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
3a581073 1103 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1104 }
7c6e0a43 1105
9a799d71
AK		 1106no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
e8e26350 1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1113 }
1114}
1115
7c6e0a43
JB		 1116static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117{
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119}
1120
1121static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122{
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124}
1125
f8212f97
AD		 1126static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127{
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131}
1132
1133/**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
94b982b2 1136 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
94b982b2
MC		 1142static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
f8212f97
AD		 1144{
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
94b982b2 1152 *count += 1;
f8212f97
AD		 1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161}
1162
43634e82
MC		 1163struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
e8171aaa 1165 bool delay_unmap;
43634e82
MC		 1166};
1167
1168#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
78b6f4ce 1170static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
9a799d71 1173{
78b6f4ce 1174 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1175 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
f8212f97 1180 unsigned int i, rsc_count = 0;
7c6e0a43 1181 u32 len, staterr;
177db6ff
MC		 1182 u16 hdr_info;
1183 bool cleaned = false;
9a799d71 1184 int cleaned_count = 0;
d2f4fbe2 1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1186#ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188#endif /* IXGBE_FCOE */
9a799d71
AK		 1189
1190 i = rx_ring->next_to_clean;
9a799d71
AK		 1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1196 u32 upper_len = 0;
9a799d71
AK		 1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
3c945e5b 1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1210 } else {
9a799d71 1211 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1212 }
9a799d71
AK		 1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
7ca3bc58 1216 prefetch(skb->data);
9a799d71
AK		 1217 rx_buffer_info->skb = NULL;
1218
21fa4e66 1219 if (rx_buffer_info->dma) {
43634e82
MC		 1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1222 (!(skb->prev))) {
43634e82
MC		 1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
e8171aaa 1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1232 } else {
1b507730 1233 dma_unmap_single(&pdev->dev,
e8171aaa 1234 rx_buffer_info->dma,
43634e82 1235 rx_ring->rx_buf_len,
e8171aaa
MC		 1236 DMA_FROM_DEVICE);
1237 }
4f57ca6e 1238 rx_buffer_info->dma = 0;
9a799d71
AK		 1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1b507730
NN		 1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
9a799d71
AK		 1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
9a799d71
AK		 1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
9a799d71 1268 cleaned_count++;
f8212f97 1269
0c19d6af 1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
9a799d71 1281 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1282 if (skb->prev)
94b982b2
MC		 1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
43634e82 1288 rx_ring->rx_buf_len,
1b507730 1289 DMA_FROM_DEVICE);
fd3686a8 1290 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1292 }
94b982b2
MC		 1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
9a799d71
AK		 1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
6e455b89 1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
7ca3bc58 1311 rx_ring->non_eop_descs++;
9a799d71
AK		 1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
8bae1b2b 1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
74ce8dd2 1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1327#ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
332d4a7d 1332 goto next_desc;
3d8fd385 1333 }
332d4a7d 1334#endif /* IXGBE_FCOE */
fdaff1ce 1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1336
1337next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
f8212f97 1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1351 }
1352
9a799d71
AK		 1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
3d8fd385
YZ		 1359#ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372#endif /* IXGBE_FCOE */
1373
f494e8fa
AV		 1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1378
9a799d71
AK		 1379 return cleaned;
1380}
1381
021230d4 1382static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1383/**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391{
021230d4
AV		 1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
9a799d71 1395
021230d4 1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1397
4df10466
JB		 1398 /*
1399 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1403 q_vector = adapter->q_vector[v_idx];
984b3f57 1404 /* XXX for_each_set_bit(...) */
021230d4 1405 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1406 adapter->num_rx_queues);
021230d4
AV		 1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1409 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1411 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1412 adapter->num_rx_queues,
1413 r_idx + 1);
021230d4
AV		 1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1416 adapter->num_tx_queues);
021230d4
AV		 1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1419 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1421 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1422 adapter->num_tx_queues,
1423 r_idx + 1);
021230d4
AV		 1424 }
1425
021230d4 1426 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1429 else if (q_vector->rxr_count)
f7554a2b
NS		 1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1432
fe49f04a 1433 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1434 }
1435
e8e26350
PW		 1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438 v_idx);
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
41fb9248 1443 /* set up to autoclear timer, and the vectors */
021230d4 1444 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1448 IXGBE_EIMS_LSC);
1449 else
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1452}
1453
f494e8fa
AV		 1454enum latency_range {
1455 lowest_latency = 0,
1456 low_latency = 1,
1457 bulk_latency = 2,
1458 latency_invalid = 255
1459};
1460
1461/**
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1468 *
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1478 **/
1479static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
f494e8fa
AV		 1482{
1483 unsigned int retval = itr_setting;
1484 u32 timepassed_us;
1485 u64 bytes_perint;
1486
1487 if (packets == 0)
1488 goto update_itr_done;
1489
1490
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1495 */
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1504 break;
1505 case low_latency:
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1510 break;
1511 case bulk_latency:
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1514 break;
1515 }
1516
1517update_itr_done:
1518 return retval;
1519}
1520
509ee935
JB		 1521/**
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1523 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1524 *
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1528 */
fe49f04a 1529void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1530{
fe49f04a 1531 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1532 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
509ee935
JB		 1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1540 /*
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1544 */
1545 if (itr_reg == 8 &&
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547 itr_reg = 0;
1548
509ee935
JB		 1549 /*
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1552 */
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554 }
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556}
1557
f494e8fa
AV		 1558static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559{
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1561 u32 new_itr;
1562 u8 current_itr, ret_itr;
fe49f04a 1563 int i, r_idx;
f494e8fa
AV		 1564 struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1568 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1570 q_vector->tx_itr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
f494e8fa
AV		 1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
30efa5a3 1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1576 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1578 r_idx + 1);
f494e8fa
AV		 1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1583 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1585 q_vector->rx_itr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
f494e8fa
AV		 1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
30efa5a3 1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1591 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1593 r_idx + 1);
f494e8fa
AV		 1594 }
1595
30efa5a3 1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1597
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1601 new_itr = 100000;
1602 break;
1603 case low_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1605 break;
1606 case bulk_latency:
1607 default:
1608 new_itr = 8000;
1609 break;
1610 }
1611
1612 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1615
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
fe49f04a
AD		 1618
1619 ixgbe_write_eitr(q_vector);
f494e8fa 1620 }
f494e8fa
AV		 1621}
1622
119fc60a
MC		 1623/**
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1626 **/
1627static void ixgbe_check_overtemp_task(struct work_struct *work)
1628{
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1634
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1638 u32 autoneg;
1639 bool link_up = false;
1640
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648 break;
1649 }
1650 return;
1651 default:
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653 return;
1654 break;
1655 }
396e799c
ET		 1656 e_crit(drv, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
849c4542
ET		 1658 "persists, power off the system and replace the "
1659 "adapter\n");
119fc60a
MC		 1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662 }
1663}
1664
0befdb3e
JB		 1665static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666{
1667 struct ixgbe_hw *hw = &adapter->hw;
1668
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1671 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674 }
1675}
cf8280ee 1676
e8e26350
PW		 1677static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678{
1679 struct ixgbe_hw *hw = &adapter->hw;
1680
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1689 } else {
1690 /* Interrupt isn't for us... */
1691 return;
1692 }
1693}
1694
cf8280ee
JB		 1695static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696{
1697 struct ixgbe_hw *hw = &adapter->hw;
1698
1699 adapter->lsc_int++;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1704 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1705 schedule_work(&adapter->watchdog_task);
1706 }
1707}
1708
9a799d71
AK		 1709static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710{
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1714 u32 eicr;
1715
1716 /*
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1721 */
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1724
cf8280ee
JB		 1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
d4f80882 1727
1cdd1ec8
GR		 1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1730
e8e26350
PW		 1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1733
c4cf55e5 1734 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1735 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1740
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743 int i;
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
4a0b9ca0 1749 adapter->tx_ring[i];
c4cf55e5
PWJ		 1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1753 }
1754 }
1755 }
d4f80882
AV		 1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1758
1759 return IRQ_HANDLED;
1760}
1761
fe49f04a
AD		 1762static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763 u64 qmask)
1764{
1765 u32 mask;
1766
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770 } else {
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775 }
1776 /* skip the flush */
1777}
1778
1779static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780 u64 qmask)
1781{
1782 u32 mask;
1783
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787 } else {
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792 }
1793 /* skip the flush */
1794}
1795
9a799d71
AK		 1796static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797{
021230d4
AV		 1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1800 struct ixgbe_ring *tx_ring;
021230d4
AV		 1801 int i, r_idx;
1802
1803 if (!q_vector->txr_count)
1804 return IRQ_HANDLED;
1805
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1808 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
021230d4 1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1812 r_idx + 1);
021230d4 1813 }
9a799d71 1814
9b471446 1815 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1816 napi_schedule(&q_vector->napi);
1817
9a799d71
AK		 1818 return IRQ_HANDLED;
1819}
1820
021230d4
AV		 1821/**
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @irq: unused
1824 * @data: pointer to our q_vector struct for this interrupt vector
1825 **/
9a799d71
AK		 1826static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827{
021230d4
AV		 1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1830 struct ixgbe_ring *rx_ring;
021230d4 1831 int r_idx;
30efa5a3 1832 int i;
021230d4
AV		 1833
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1835 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1836 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840 r_idx + 1);
1841 }
1842
021230d4
AV		 1843 if (!q_vector->rxr_count)
1844 return IRQ_HANDLED;
1845
021230d4 1846 /* disable interrupts on this vector only */
9b471446 1847 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1848 napi_schedule(&q_vector->napi);
021230d4
AV		 1849
1850 return IRQ_HANDLED;
1851}
1852
1853static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854{
91281fd3
AD		 1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1858 int r_idx;
1859 int i;
1860
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1862 return IRQ_HANDLED;
1863
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1866 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870 r_idx + 1);
1871 }
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1875 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
9b471446 1882 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1883 napi_schedule(&q_vector->napi);
9a799d71 1884
9a799d71
AK		 1885 return IRQ_HANDLED;
1886}
1887
021230d4
AV		 1888/**
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1892 *
f0848276
JB		 1893 * This function is optimized for cleaning one queue only on a single
1894 * q_vector!!!
021230d4 1895 **/
9a799d71
AK		 1896static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897{
021230d4 1898 struct ixgbe_q_vector *q_vector =
b4617240 1899 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1900 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1901 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1902 int work_done = 0;
021230d4 1903 long r_idx;
9a799d71 1904
021230d4 1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1906 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1907#ifdef CONFIG_IXGBE_DCA
bd0362dd 1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1909 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1910#endif
9a799d71 1911
78b6f4ce 1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1913
021230d4
AV		 1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
288379f0 1916 napi_complete(napi);
f7554a2b 1917 if (adapter->rx_itr_setting & 1)
f494e8fa 1918 ixgbe_set_itr_msix(q_vector);
9a799d71 1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1922 }
1923
1924 return work_done;
1925}
1926
f0848276 1927/**
91281fd3 1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1931 *
1932 * This function will clean more than one rx queue associated with a
1933 * q_vector.
1934 **/
91281fd3 1935static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1936{
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1940 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1941 int work_done = 0, i;
1942 long r_idx;
91281fd3
AD		 1943 bool tx_clean_complete = true;
1944
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1947 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1948#ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1951#endif
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954 r_idx + 1);
1955 }
f0848276
JB		 1956
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1963 ring = adapter->rx_ring[r_idx];
5dd2d332 1964#ifdef CONFIG_IXGBE_DCA
f0848276 1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1966 ixgbe_update_rx_dca(adapter, ring);
f0848276 1967#endif
91281fd3 1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970 r_idx + 1);
1971 }
1972
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1974 ring = adapter->rx_ring[r_idx];
f0848276 1975 /* If all Rx work done, exit the polling mode */
7f821875 1976 if (work_done < budget) {
288379f0 1977 napi_complete(napi);
f7554a2b 1978 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1983 return 0;
1984 }
1985
1986 return work_done;
1987}
91281fd3
AD		 1988
1989/**
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1993 *
1994 * This function is optimized for cleaning one queue only on a single
1995 * q_vector!!!
1996 **/
1997static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998{
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2003 int work_done = 0;
2004 long r_idx;
2005
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2007 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2008#ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2011#endif
2012
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014 work_done = budget;
2015
f7554a2b 2016 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2017 if (work_done < budget) {
2018 napi_complete(napi);
f7554a2b 2019 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023 }
2024
2025 return work_done;
2026}
2027
021230d4 2028static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 2029 int r_idx)
021230d4 2030{
7a921c93
AD		 2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
021230d4
AV		 2035}
2036
2037static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 2038 int t_idx)
021230d4 2039{
7a921c93
AD		 2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
021230d4
AV		 2044}
2045
9a799d71 2046/**
021230d4
AV		 2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
9a799d71 2050 *
021230d4
AV		 2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
9a799d71 2056 **/
021230d4 2057static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 2058 int vectors)
021230d4
AV		 2059{
2060 int v_start = 0;
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2064 int i, j;
2065 int rqpv, tqpv;
2066 int err = 0;
2067
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070 goto out;
9a799d71 2071
021230d4
AV		 2072 /*
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2075 */
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2079
021230d4
AV		 2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2082
9a799d71 2083 goto out;
021230d4 2084 }
9a799d71 2085
021230d4
AV		 2086 /*
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2090 */
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2096 rxr_idx++;
2097 rxr_remaining--;
2098 }
2099 }
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2104 txr_idx++;
2105 txr_remaining--;
9a799d71 2106 }
9a799d71
AK		 2107 }
2108
021230d4
AV		 2109out:
2110 return err;
2111}
2112
2113/**
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2116 *
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2119 **/
2120static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121{
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
cb13fc20 2125 int ri=0, ti=0;
021230d4
AV		 2126
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132 if (err)
2133 goto out;
2134
2135#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
021230d4 2138 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2139 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 2140
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2144 }
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2148 }
2149 else
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2152
021230d4 2153 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 2154 handler, 0, adapter->name[vector],
7a921c93 2155 adapter->q_vector[vector]);
9a799d71 2156 if (err) {
396e799c 2157 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2158 "Error: %d\n", err);
021230d4 2159 goto free_queue_irqs;
9a799d71 2160 }
9a799d71
AK		 2161 }
2162
021230d4
AV		 2163 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2165 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2166 if (err) {
396e799c 2167 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2168 goto free_queue_irqs;
9a799d71
AK		 2169 }
2170
9a799d71
AK		 2171 return 0;
2172
021230d4
AV		 2173free_queue_irqs:
2174 for (i = vector - 1; i >= 0; i--)
2175 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 2176 adapter->q_vector[i]);
021230d4
AV		 2177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2179 kfree(adapter->msix_entries);
2180 adapter->msix_entries = NULL;
021230d4 2181out:
9a799d71
AK		 2182 return err;
2183}
2184
f494e8fa
AV		 2185static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186{
7a921c93 2187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2188 u8 current_itr;
2189 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2190 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2192
30efa5a3 2193 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2194 q_vector->tx_itr,
2195 tx_ring->total_packets,
2196 tx_ring->total_bytes);
30efa5a3 2197 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2198 q_vector->rx_itr,
2199 rx_ring->total_packets,
2200 rx_ring->total_bytes);
f494e8fa 2201
30efa5a3 2202 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2203
2204 switch (current_itr) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency:
2207 new_itr = 100000;
2208 break;
2209 case low_latency:
2210 new_itr = 20000; /* aka hwitr = ~200 */
2211 break;
2212 case bulk_latency:
2213 new_itr = 8000;
2214 break;
2215 default:
2216 break;
2217 }
2218
2219 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2220 /* do an exponential smoothing */
2221 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2222
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector->eitr = new_itr;
fe49f04a
AD		 2225
2226 ixgbe_write_eitr(q_vector);
f494e8fa 2227 }
f494e8fa
AV		 2228}
2229
79aefa45
AD		 2230/**
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2233 **/
2234static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235{
2236 u32 mask;
835462fc
NS		 2237
2238 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2239 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2241 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2243 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2244 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2245 mask |= IXGBE_EIMS_GPI_SDP1;
2246 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2247 if (adapter->num_vfs)
2248 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2249 }
c4cf55e5
PWJ		 2250 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2253
79aefa45 2254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2255 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2256 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2257
2258 if (adapter->num_vfs > 32) {
2259 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261 }
79aefa45 2262}
021230d4 2263
9a799d71 2264/**
021230d4 2265 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
9a799d71
AK		 2268 **/
2269static irqreturn_t ixgbe_intr(int irq, void *data)
2270{
2271 struct net_device *netdev = data;
2272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2274 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2275 u32 eicr;
2276
54037505
DS		 2277 /*
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2280 */
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
021230d4
AV		 2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2286 if (!eicr) {
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter);
9a799d71 2291 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2292 }
9a799d71 2293
cf8280ee
JB		 2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
021230d4 2296
e8e26350
PW		 2297 if (hw->mac.type == ixgbe_mac_82599EB)
2298 ixgbe_check_sfp_event(adapter, eicr);
2299
0befdb3e 2300 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2301 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2304
7a921c93 2305 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2306 adapter->tx_ring[0]->total_packets = 0;
2307 adapter->tx_ring[0]->total_bytes = 0;
2308 adapter->rx_ring[0]->total_packets = 0;
2309 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2310 /* would disable interrupts here but EIAM disabled it */
7a921c93 2311 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2312 }
2313
2314 return IRQ_HANDLED;
2315}
2316
021230d4
AV		 2317static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318{
2319 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321 for (i = 0; i < q_vectors; i++) {
7a921c93 2322 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2323 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325 q_vector->rxr_count = 0;
2326 q_vector->txr_count = 0;
2327 }
2328}
2329
9a799d71
AK		 2330/**
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2333 *
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2336 **/
021230d4 2337static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2338{
2339 struct net_device *netdev = adapter->netdev;
021230d4 2340 int err;
9a799d71 2341
021230d4
AV		 2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 err = ixgbe_request_msix_irqs(adapter);
2344 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2345 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 2346 netdev->name, netdev);
021230d4 2347 } else {
a0607fd3 2348 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 2349 netdev->name, netdev);
9a799d71
AK		 2350 }
2351
9a799d71 2352 if (err)
396e799c 2353 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2354
9a799d71
AK		 2355 return err;
2356}
2357
2358static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359{
2360 struct net_device *netdev = adapter->netdev;
2361
2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2363 int i, q_vectors;
9a799d71 2364
021230d4
AV		 2365 q_vectors = adapter->num_msix_vectors;
2366
2367 i = q_vectors - 1;
9a799d71 2368 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2369
021230d4
AV		 2370 i--;
2371 for (; i >= 0; i--) {
2372 free_irq(adapter->msix_entries[i].vector,
7a921c93 2373 adapter->q_vector[i]);
021230d4
AV		 2374 }
2375
2376 ixgbe_reset_q_vectors(adapter);
2377 } else {
2378 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2379 }
2380}
2381
22d5a71b
JB		 2382/**
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2385 **/
2386static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387{
835462fc
NS		 2388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390 } else {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2394 if (adapter->num_vfs > 32)
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2396 }
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
2398 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399 int i;
2400 for (i = 0; i < adapter->num_msix_vectors; i++)
2401 synchronize_irq(adapter->msix_entries[i].vector);
2402 } else {
2403 synchronize_irq(adapter->pdev->irq);
2404 }
2405}
2406
9a799d71
AK		 2407/**
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409 *
2410 **/
2411static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412{
9a799d71
AK		 2413 struct ixgbe_hw *hw = &adapter->hw;
2414
021230d4 2415 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2416 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2417
e8e26350
PW		 2418 ixgbe_set_ivar(adapter, 0, 0, 0);
2419 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2420
2421 map_vector_to_rxq(adapter, 0, 0);
2422 map_vector_to_txq(adapter, 0, 0);
2423
396e799c 2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2425}
2426
43e69bf0
AD		 2427/**
2428 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429 * @adapter: board private structure
2430 * @ring: structure containing ring specific data
2431 *
2432 * Configure the Tx descriptor ring after a reset.
2433 **/
2434 static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435 struct ixgbe_ring *ring)
2436{
2437 struct ixgbe_hw *hw = &adapter->hw;
2438 u64 tdba = ring->dma;
2439 u16 reg_idx = ring->reg_idx;
2440
2441 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2442 (tdba & DMA_BIT_MASK(32)));
2443 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2444 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2445 ring->count * sizeof(union ixgbe_adv_tx_desc));
2446 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2447 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2448 ring->head = IXGBE_TDH(reg_idx);
2449 ring->tail = IXGBE_TDT(reg_idx);
2450
2451}
2452
120ff942
AD		 2453static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2454{
2455 struct ixgbe_hw *hw = &adapter->hw;
2456 u32 rttdcs;
2457 u32 mask;
2458
2459 if (hw->mac.type == ixgbe_mac_82598EB)
2460 return;
2461
2462 /* disable the arbiter while setting MTQC */
2463 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2464 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2465 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2466
2467 /* set transmit pool layout */
2468 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2469 switch (adapter->flags & mask) {
2470
2471 case (IXGBE_FLAG_SRIOV_ENABLED):
2472 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2473 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2474 break;
2475
2476 case (IXGBE_FLAG_DCB_ENABLED):
2477 /* We enable 8 traffic classes, DCB only */
2478 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2479 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2480 break;
2481
2482 default:
2483 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2484 break;
2485 }
2486
2487 /* re-enable the arbiter */
2488 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2489 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2490}
2491
9a799d71 2492/**
3a581073 2493 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2494 * @adapter: board private structure
2495 *
2496 * Configure the Tx unit of the MAC after a reset.
2497 **/
2498static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2499{
43e69bf0 2500 u32 i;
9a799d71
AK		 2501
2502 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2503 for (i = 0; i < adapter->num_tx_queues; i++)
2504 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
ee5f784a 2505
120ff942 2506 ixgbe_setup_mtqc(adapter);
9a799d71
AK		 2507}
2508
e8e26350 2509#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2510
a6616b42
YZ		 2511static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2512 struct ixgbe_ring *rx_ring)
cc41ac7c 2513{
cc41ac7c 2514 u32 srrctl;
a6616b42 2515 int index;
0cefafad 2516 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2517
a6616b42
YZ		 2518 index = rx_ring->reg_idx;
2519 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2520 unsigned long mask;
0cefafad 2521 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2522 index = index & mask;
cc41ac7c 2523 }
cc41ac7c
JB		 2524 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2525
2526 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2527 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2528
afafd5b0
AD		 2529 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2530 IXGBE_SRRCTL_BSIZEHDR_MASK;
2531
6e455b89 2532 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2533#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535#else
2536 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537#endif
cc41ac7c 2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2539 } else {
afafd5b0
AD		 2540 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2541 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2542 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2543 }
e8e26350 2544
cc41ac7c
JB		 2545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2546}
9a799d71 2547
05abb126 2548static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2549{
05abb126
AD		 2550 struct ixgbe_hw *hw = &adapter->hw;
2551 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554 u32 mrqc = 0, reta = 0;
2555 u32 rxcsum;
2556 int i, j;
0cefafad
JB		 2557 int mask;
2558
05abb126
AD		 2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
2565 if (j == adapter->ring_feature[RING_F_RSS].indices)
2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
0cefafad 2573
05abb126
AD		 2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2580 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2581 else
2582 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2583#ifdef CONFIG_IXGBE_DCB
05abb126 2584 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2585#endif
05abb126
AD		 2586 | IXGBE_FLAG_SRIOV_ENABLED
2587 );
0cefafad
JB		 2588
2589 switch (mask) {
2590 case (IXGBE_FLAG_RSS_ENABLED):
2591 mrqc = IXGBE_MRQC_RSSEN;
2592 break;
1cdd1ec8
GR		 2593 case (IXGBE_FLAG_SRIOV_ENABLED):
2594 mrqc = IXGBE_MRQC_VMDQEN;
2595 break;
0cefafad
JB		 2596#ifdef CONFIG_IXGBE_DCB
2597 case (IXGBE_FLAG_DCB_ENABLED):
2598 mrqc = IXGBE_MRQC_RT8TCEN;
2599 break;
2600#endif /* CONFIG_IXGBE_DCB */
2601 default:
2602 break;
2603 }
2604
05abb126
AD		 2605 /* Perform hash on these packet types */
2606 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608 | IXGBE_MRQC_RSS_FIELD_IPV6
2609 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2612}
2613
bb5a9ad2
NS		 2614/**
2615 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616 * @adapter: address of board private structure
2617 * @index: index of ring to set
bb5a9ad2 2618 **/
edd2ea55 2619static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2620{
2621 struct ixgbe_ring *rx_ring;
2622 struct ixgbe_hw *hw = &adapter->hw;
2623 int j;
2624 u32 rscctrl;
edd2ea55 2625 int rx_buf_len;
bb5a9ad2 2626
4a0b9ca0 2627 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2628 j = rx_ring->reg_idx;
edd2ea55 2629 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2630 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2631 rscctrl |= IXGBE_RSCCTL_RSCEN;
2632 /*
2633 * we must limit the number of descriptors so that the
2634 * total size of max desc * buf_len is not greater
2635 * than 65535
2636 */
2637 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2638#if (MAX_SKB_FRAGS > 16)
2639 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2640#elif (MAX_SKB_FRAGS > 8)
2641 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2642#elif (MAX_SKB_FRAGS > 4)
2643 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2644#else
2645 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2646#endif
2647 } else {
2648 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2649 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2650 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2651 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2652 else
2653 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2654 }
2655 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2656}
2657
9a799d71 2658/**
3a581073 2659 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2660 * @adapter: board private structure
2661 *
2662 * Configure the Rx unit of the MAC after a reset.
2663 **/
2664static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2665{
2666 u64 rdba;
2667 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2668 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2669 struct net_device *netdev = adapter->netdev;
2670 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2671 int i, j;
05abb126 2672 u32 rdlen, rxctrl;
9a799d71 2673 u32 fctrl, hlreg0;
cc41ac7c 2674 u32 rdrxctl;
7c6e0a43 2675 int rx_buf_len;
9a799d71
AK		 2676
2677 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2678 /* Do not use packet split if we're in SR-IOV Mode */
2679 if (!adapter->num_vfs)
2680 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2681
2682 /* Set the RX buffer length according to the mode */
2683 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2684 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2685 if (hw->mac.type == ixgbe_mac_82599EB) {
2686 /* PSRTYPE must be initialized in 82599 */
2687 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2688 IXGBE_PSRTYPE_UDPHDR |
2689 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2690 IXGBE_PSRTYPE_IPV6HDR |
2691 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2692 IXGBE_WRITE_REG(hw,
2693 IXGBE_PSRTYPE(adapter->num_vfs),
2694 psrtype);
e8e26350 2695 }
9a799d71 2696 } else {
0c19d6af 2697 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2698 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2699 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2700 else
7c6e0a43 2701 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2702 }
2703
2704 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2705 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2706 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2707 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2708 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2709
2710 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2711 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2712 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2713 else
2714 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2715#ifdef IXGBE_FCOE
f34c5c82 2716 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2717 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2718#endif
9a799d71
AK		 2719 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2720
4a0b9ca0 2721 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2722 /* disable receives while setting up the descriptors */
2723 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2724 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2725
0cefafad
JB		 2726 /*
2727 * Setup the HW Rx Head and Tail Descriptor Pointers and
2728 * the Base and Length of the Rx Descriptor Ring
2729 */
9a799d71 2730 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2731 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2732 rdba = rx_ring->dma;
2733 j = rx_ring->reg_idx;
284901a9 2734 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2735 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2736 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2737 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2738 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2739 rx_ring->head = IXGBE_RDH(j);
2740 rx_ring->tail = IXGBE_RDT(j);
2741 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2742
6e455b89
YZ		 2743 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2744 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2745 else
2746 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2747
63f39bd1 2748#ifdef IXGBE_FCOE
f34c5c82 2749 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2750 struct ixgbe_ring_feature *f;
2751 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2752 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2753 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2754 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2755 rx_ring->rx_buf_len =
2756 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2757 }
63f39bd1
YZ		 2758 }
2759
2760#endif /* IXGBE_FCOE */
a6616b42 2761 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2762 }
2763
e8e26350
PW		 2764 if (hw->mac.type == ixgbe_mac_82598EB) {
2765 /*
2766 * For VMDq support of different descriptor types or
2767 * buffer sizes through the use of multiple SRRCTL
2768 * registers, RDRXCTL.MVMEN must be set to 1
2769 *
2770 * also, the manual doesn't mention it clearly but DCA hints
2771 * will only use queue 0's tags unless this bit is set. Side
2772 * effects of setting this bit are only that SRRCTL must be
2773 * fully programmed [0..15]
2774 */
2a41ff81
JB		 2775 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2776 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2777 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2778 }
177db6ff 2779
1cdd1ec8
GR		 2780 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2781 u32 vt_reg_bits;
2782 u32 reg_offset, vf_shift;
2783 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2784 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2785 | IXGBE_VT_CTL_REPLEN;
2786 vt_reg_bits |= (adapter->num_vfs <<
2787 IXGBE_VT_CTL_POOL_SHIFT);
2788 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2789 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2790
2791 vf_shift = adapter->num_vfs % 32;
2792 reg_offset = adapter->num_vfs / 32;
2793 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2794 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2795 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2796 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2797 /* Enable only the PF's pool for Tx/Rx */
2798 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2799 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2800 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f0412776 2801 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
1cdd1ec8
GR		 2802 }
2803
e8e26350 2804 /* Program MRQC for the distribution of queues */
05abb126 2805 ixgbe_setup_mrqc(adapter);
9a799d71 2806
1cdd1ec8
GR		 2807 if (adapter->num_vfs) {
2808 u32 reg;
2809
2810 /* Map PF MAC address in RAR Entry 0 to first pool
2811 * following VFs */
2812 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2813
2814 /* Set up VF register offsets for selected VT Mode, i.e.
2815 * 64 VFs for SR-IOV */
2816 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2817 reg |= IXGBE_GCR_EXT_SRIOV;
2818 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2819 }
2820
e8e26350
PW		 2821 if (hw->mac.type == ixgbe_mac_82599EB) {
2822 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2823 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2824 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2825 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2826 }
f8212f97 2827
0c19d6af 2828 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2829 /* Enable 82599 HW-RSC */
bb5a9ad2 2830 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2831 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2832
f8212f97
AD		 2833 /* Disable RSC for ACK packets */
2834 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2835 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2836 }
9a799d71
AK		 2837}
2838
068c89b0
DS		 2839static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2840{
2841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2842 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2843 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2844
2845 /* add VID to filter table */
1ada1b1b 2846 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2847}
2848
2849static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2850{
2851 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2852 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2853 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2854
2855 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2856 ixgbe_irq_disable(adapter);
2857
2858 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2859
2860 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2861 ixgbe_irq_enable(adapter);
2862
2863 /* remove VID from filter table */
1ada1b1b 2864 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2865}
2866
5f6c0181
JB		 2867/**
2868 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2869 * @adapter: driver data
2870 */
2871static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2872{
2873 struct ixgbe_hw *hw = &adapter->hw;
2874 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2875 int i, j;
2876
2877 switch (hw->mac.type) {
2878 case ixgbe_mac_82598EB:
38e0bd98
YZ		 2879 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2880#ifdef CONFIG_IXGBE_DCB
2881 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2882 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2883#endif
5f6c0181
JB		 2884 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2885 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2886 break;
2887 case ixgbe_mac_82599EB:
2888 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2889 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2890 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 2891#ifdef CONFIG_IXGBE_DCB
2892 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2893 break;
2894#endif
5f6c0181
JB		 2895 for (i = 0; i < adapter->num_rx_queues; i++) {
2896 j = adapter->rx_ring[i]->reg_idx;
2897 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2898 vlnctrl &= ~IXGBE_RXDCTL_VME;
2899 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2900 }
2901 break;
2902 default:
2903 break;
2904 }
2905}
2906
2907/**
2908 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2909 * @adapter: driver data
2910 */
2911static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2912{
2913 struct ixgbe_hw *hw = &adapter->hw;
2914 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2915 int i, j;
2916
2917 switch (hw->mac.type) {
2918 case ixgbe_mac_82598EB:
2919 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2920 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2921 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2922 break;
2923 case ixgbe_mac_82599EB:
2924 vlnctrl |= IXGBE_VLNCTRL_VFE;
2925 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2926 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2927 for (i = 0; i < adapter->num_rx_queues; i++) {
2928 j = adapter->rx_ring[i]->reg_idx;
2929 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2930 vlnctrl |= IXGBE_RXDCTL_VME;
2931 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2932 }
2933 break;
2934 default:
2935 break;
2936 }
2937}
2938
9a799d71 2939static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2940 struct vlan_group *grp)
9a799d71
AK		 2941{
2942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2943
d4f80882
AV		 2944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2945 ixgbe_irq_disable(adapter);
9a799d71
AK		 2946 adapter->vlgrp = grp;
2947
2f90b865
AD		 2948 /*
2949 * For a DCB driver, always enable VLAN tag stripping so we can
2950 * still receive traffic from a DCB-enabled host even if we're
2951 * not in DCB mode.
2952 */
5f6c0181 2953 ixgbe_vlan_filter_enable(adapter);
dc63d377 2954
e8e26350 2955 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2956
d4f80882
AV		 2957 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2958 ixgbe_irq_enable(adapter);
9a799d71
AK		 2959}
2960
9a799d71
AK		 2961static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2962{
2963 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2964
2965 if (adapter->vlgrp) {
2966 u16 vid;
2967 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2968 if (!vlan_group_get_device(adapter->vlgrp, vid))
2969 continue;
2970 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2971 }
2972 }
2973}
2974
2850062a
AD		 2975/**
2976 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2977 * @netdev: network interface device structure
2978 *
2979 * Writes unicast address list to the RAR table.
2980 * Returns: -ENOMEM on failure/insufficient address space
2981 * 0 on no addresses written
2982 * X on writing X addresses to the RAR table
2983 **/
2984static int ixgbe_write_uc_addr_list(struct net_device *netdev)
2985{
2986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 unsigned int vfn = adapter->num_vfs;
2989 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
2990 int count = 0;
2991
2992 /* return ENOMEM indicating insufficient memory for addresses */
2993 if (netdev_uc_count(netdev) > rar_entries)
2994 return -ENOMEM;
2995
2996 if (!netdev_uc_empty(netdev) && rar_entries) {
2997 struct netdev_hw_addr *ha;
2998 /* return error if we do not support writing to RAR table */
2999 if (!hw->mac.ops.set_rar)
3000 return -ENOMEM;
3001
3002 netdev_for_each_uc_addr(ha, netdev) {
3003 if (!rar_entries)
3004 break;
3005 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3006 vfn, IXGBE_RAH_AV);
3007 count++;
3008 }
3009 }
3010 /* write the addresses in reverse order to avoid write combining */
3011 for (; rar_entries > 0 ; rar_entries--)
3012 hw->mac.ops.clear_rar(hw, rar_entries);
3013
3014 return count;
3015}
3016
9a799d71 3017/**
2c5645cf 3018 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3019 * @netdev: network interface device structure
3020 *
2c5645cf
CL		 3021 * The set_rx_method entry point is called whenever the unicast/multicast
3022 * address list or the network interface flags are updated. This routine is
3023 * responsible for configuring the hardware for proper unicast, multicast and
3024 * promiscuous mode.
9a799d71 3025 **/
7f870475 3026void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3027{
3028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3029 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3030 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3031 int count;
9a799d71
AK		 3032
3033 /* Check for Promiscuous and All Multicast modes */
3034
3035 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3036
2850062a
AD		 3037 /* clear the bits we are changing the status of */
3038 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3039
9a799d71 3040 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3041 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3042 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3043 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3044 /* don't hardware filter vlans in promisc mode */
3045 ixgbe_vlan_filter_disable(adapter);
9a799d71 3046 } else {
746b9f02
PM		 3047 if (netdev->flags & IFF_ALLMULTI) {
3048 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3049 vmolr |= IXGBE_VMOLR_MPE;
3050 } else {
3051 /*
3052 * Write addresses to the MTA, if the attempt fails
3053 * then we should just turn on promiscous mode so
3054 * that we can at least receive multicast traffic
3055 */
3056 hw->mac.ops.update_mc_addr_list(hw, netdev);
3057 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3058 }
5f6c0181 3059 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3060 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3061 /*
3062 * Write addresses to available RAR registers, if there is not
3063 * sufficient space to store all the addresses then enable
3064 * unicast promiscous mode
3065 */
3066 count = ixgbe_write_uc_addr_list(netdev);
3067 if (count < 0) {
3068 fctrl |= IXGBE_FCTRL_UPE;
3069 vmolr |= IXGBE_VMOLR_ROPE;
3070 }
9a799d71
AK		 3071 }
3072
2850062a 3073 if (adapter->num_vfs) {
1cdd1ec8 3074 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3075 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3076 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3077 IXGBE_VMOLR_ROPE);
3078 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3079 }
3080
3081 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
9a799d71
AK		 3082}
3083
021230d4
AV		 3084static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3085{
3086 int q_idx;
3087 struct ixgbe_q_vector *q_vector;
3088 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3089
3090 /* legacy and MSI only use one vector */
3091 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3092 q_vectors = 1;
3093
3094 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3095 struct napi_struct *napi;
7a921c93 3096 q_vector = adapter->q_vector[q_idx];
f0848276 3097 napi = &q_vector->napi;
91281fd3
AD		 3098 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3099 if (!q_vector->rxr_count || !q_vector->txr_count) {
3100 if (q_vector->txr_count == 1)
3101 napi->poll = &ixgbe_clean_txonly;
3102 else if (q_vector->rxr_count == 1)
3103 napi->poll = &ixgbe_clean_rxonly;
3104 }
3105 }
f0848276
JB		 3106
3107 napi_enable(napi);
021230d4
AV		 3108 }
3109}
3110
3111static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3112{
3113 int q_idx;
3114 struct ixgbe_q_vector *q_vector;
3115 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3116
3117 /* legacy and MSI only use one vector */
3118 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3119 q_vectors = 1;
3120
3121 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3122 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3123 napi_disable(&q_vector->napi);
3124 }
3125}
3126
7a6b6f51 3127#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3128/*
3129 * ixgbe_configure_dcb - Configure DCB hardware
3130 * @adapter: ixgbe adapter struct
3131 *
3132 * This is called by the driver on open to configure the DCB hardware.
3133 * This is also called by the gennetlink interface when reconfiguring
3134 * the DCB state.
3135 */
3136static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3137{
3138 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3139 u32 txdctl;
2f90b865
AD		 3140 int i, j;
3141
67ebd791
AD		 3142 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3143 if (hw->mac.type == ixgbe_mac_82598EB)
3144 netif_set_gso_max_size(adapter->netdev, 65536);
3145 return;
3146 }
3147
3148 if (hw->mac.type == ixgbe_mac_82598EB)
3149 netif_set_gso_max_size(adapter->netdev, 32768);
3150
2f90b865
AD		 3151 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3152 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3153 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3154
3155 /* reconfigure the hardware */
3156 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3157
3158 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3159 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3160 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3161 /* PThresh workaround for Tx hang with DFP enabled. */
3162 txdctl |= 32;
3163 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3164 }
3165 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3166 ixgbe_vlan_filter_enable(adapter);
3167
2f90b865
AD		 3168 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3169}
3170
3171#endif
9a799d71
AK		 3172static void ixgbe_configure(struct ixgbe_adapter *adapter)
3173{
3174 struct net_device *netdev = adapter->netdev;
c4cf55e5 3175 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3176 int i;
3177
2c5645cf 3178 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3179
3180 ixgbe_restore_vlan(adapter);
7a6b6f51 3181#ifdef CONFIG_IXGBE_DCB
67ebd791 3182 ixgbe_configure_dcb(adapter);
2f90b865 3183#endif
9a799d71 3184
eacd73f7
YZ		 3185#ifdef IXGBE_FCOE
3186 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3187 ixgbe_configure_fcoe(adapter);
3188
3189#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3190 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3191 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3192 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 3193 adapter->atr_sample_rate;
3194 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3195 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3196 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3197 }
3198
9a799d71
AK		 3199 ixgbe_configure_tx(adapter);
3200 ixgbe_configure_rx(adapter);
3201 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 3202 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3203 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 3204}
3205
e8e26350
PW		 3206static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3207{
3208 switch (hw->phy.type) {
3209 case ixgbe_phy_sfp_avago:
3210 case ixgbe_phy_sfp_ftl:
3211 case ixgbe_phy_sfp_intel:
3212 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3213 case ixgbe_phy_sfp_passive_tyco:
3214 case ixgbe_phy_sfp_passive_unknown:
3215 case ixgbe_phy_sfp_active_unknown:
3216 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3217 return true;
3218 default:
3219 return false;
3220 }
3221}
3222
0ecc061d 3223/**
e8e26350
PW		 3224 * ixgbe_sfp_link_config - set up SFP+ link
3225 * @adapter: pointer to private adapter struct
3226 **/
3227static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3228{
3229 struct ixgbe_hw *hw = &adapter->hw;
3230
3231 if (hw->phy.multispeed_fiber) {
3232 /*
3233 * In multispeed fiber setups, the device may not have
3234 * had a physical connection when the driver loaded.
3235 * If that's the case, the initial link configuration
3236 * couldn't get the MAC into 10G or 1G mode, so we'll
3237 * never have a link status change interrupt fire.
3238 * We need to try and force an autonegotiation
3239 * session, then bring up link.
3240 */
3241 hw->mac.ops.setup_sfp(hw);
3242 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3243 schedule_work(&adapter->multispeed_fiber_task);
3244 } else {
3245 /*
3246 * Direct Attach Cu and non-multispeed fiber modules
3247 * still need to be configured properly prior to
3248 * attempting link.
3249 */
3250 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3251 schedule_work(&adapter->sfp_config_module_task);
3252 }
3253}
3254
3255/**
3256 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3257 * @hw: pointer to private hardware struct
3258 *
3259 * Returns 0 on success, negative on failure
3260 **/
e8e26350 3261static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3262{
3263 u32 autoneg;
8620a103 3264 bool negotiation, link_up = false;
0ecc061d
PWJ		 3265 u32 ret = IXGBE_ERR_LINK_SETUP;
3266
3267 if (hw->mac.ops.check_link)
3268 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3269
3270 if (ret)
3271 goto link_cfg_out;
3272
3273 if (hw->mac.ops.get_link_capabilities)
8620a103 3274 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 3275 if (ret)
3276 goto link_cfg_out;
3277
8620a103
MC		 3278 if (hw->mac.ops.setup_link)
3279 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3280link_cfg_out:
3281 return ret;
3282}
3283
e8e26350
PW		 3284#define IXGBE_MAX_RX_DESC_POLL 10
3285static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3286 int rxr)
3287{
4a0b9ca0 3288 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 3289 int k;
3290
3291 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3292 if (IXGBE_READ_REG(&adapter->hw,
3293 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3294 break;
3295 else
3296 msleep(1);
3297 }
3298 if (k >= IXGBE_MAX_RX_DESC_POLL) {
396e799c 3299 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
849c4542 3300 "the polling period\n", rxr);
e8e26350 3301 }
4a0b9ca0
PW		 3302 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3303 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 3304}
3305
9a799d71
AK		 3306static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3307{
3308 struct net_device *netdev = adapter->netdev;
9a799d71 3309 struct ixgbe_hw *hw = &adapter->hw;
021230d4 3310 int i, j = 0;
e8e26350 3311 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 3312 int err;
9a799d71 3313 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 3314 u32 txdctl, rxdctl, mhadd;
e8e26350 3315 u32 dmatxctl;
021230d4 3316 u32 gpie;
c9205697 3317 u32 ctrl_ext;
9a799d71 3318
5eba3699
AV		 3319 ixgbe_get_hw_control(adapter);
3320
021230d4
AV		 3321 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3322 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 3323 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3324 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 3325 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 3326 } else {
3327 /* MSI only */
021230d4 3328 gpie = 0;
9a799d71 3329 }
1cdd1ec8
GR		 3330 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3331 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3332 gpie |= IXGBE_GPIE_VTMODE_64;
3333 }
021230d4
AV		 3334 /* XXX: to interrupt immediately for EICS writes, enable this */
3335 /* gpie |= IXGBE_GPIE_EIMEN; */
3336 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 3337 }
3338
9b471446
JB		 3339 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3340 /*
3341 * use EIAM to auto-mask when MSI-X interrupt is asserted
3342 * this saves a register write for every interrupt
3343 */
3344 switch (hw->mac.type) {
3345 case ixgbe_mac_82598EB:
3346 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3347 break;
3348 default:
3349 case ixgbe_mac_82599EB:
3350 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3351 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3352 break;
3353 }
3354 } else {
021230d4
AV		 3355 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3356 * specifically only auto mask tx and rx interrupts */
3357 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3358 }
9a799d71 3359
119fc60a
MC		 3360 /* Enable Thermal over heat sensor interrupt */
3361 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3362 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3363 gpie |= IXGBE_SDP0_GPIEN;
3364 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3365 }
3366
0befdb3e
JB		 3367 /* Enable fan failure interrupt if media type is copper */
3368 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3369 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3370 gpie |= IXGBE_SDP1_GPIEN;
3371 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3372 }
3373
e8e26350
PW		 3374 if (hw->mac.type == ixgbe_mac_82599EB) {
3375 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3376 gpie |= IXGBE_SDP1_GPIEN;
3377 gpie |= IXGBE_SDP2_GPIEN;
3378 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3379 }
3380
63f39bd1
YZ		 3381#ifdef IXGBE_FCOE
3382 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 3383 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 3384 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3385 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3386
3387#endif /* IXGBE_FCOE */
021230d4 3388 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 3389 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3390 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3391 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3392
3393 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3394 }
3395
179b4096
AD		 3396 if (hw->mac.type == ixgbe_mac_82599EB) {
3397 /* DMATXCTL.EN must be set after all Tx queue config is done */
3398 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3399 dmatxctl |= IXGBE_DMATXCTL_TE;
3400 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3401 }
9a799d71 3402 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3403 j = adapter->tx_ring[i]->reg_idx;
021230d4 3404 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 3405 if (adapter->rx_itr_setting == 0) {
3406 /* cannot set wthresh when itr==0 */
3407 txdctl &= ~0x007F0000;
3408 } else {
3409 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3410 txdctl |= (8 << 16);
3411 }
9a799d71 3412 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 3413 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 3414 if (hw->mac.type == ixgbe_mac_82599EB) {
3415 int wait_loop = 10;
3416 /* poll for Tx Enable ready */
3417 do {
3418 msleep(1);
3419 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3420 } while (--wait_loop &&
3421 !(txdctl & IXGBE_TXDCTL_ENABLE));
3422 if (!wait_loop)
396e799c 3423 e_err(drv, "Could not enable Tx Queue %d\n", j);
1cdd1ec8 3424 }
9a799d71
AK		 3425 }
3426
e8e26350 3427 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 3428 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 3429 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3430 /* enable PTHRESH=32 descriptors (half the internal cache)
3431 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3432 * this also removes a pesky rx_no_buffer_count increment */
3433 rxdctl |= 0x0020;
9a799d71 3434 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 3435 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 3436 if (hw->mac.type == ixgbe_mac_82599EB)
3437 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 3438 }
3439 /* enable all receives */
3440 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 3441 if (hw->mac.type == ixgbe_mac_82598EB)
3442 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3443 else
3444 rxdctl |= IXGBE_RXCTRL_RXEN;
3445 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3446
3447 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3448 ixgbe_configure_msix(adapter);
3449 else
3450 ixgbe_configure_msi_and_legacy(adapter);
3451
61fac744
PW		 3452 /* enable the optics */
3453 if (hw->phy.multispeed_fiber)
3454 hw->mac.ops.enable_tx_laser(hw);
3455
9a799d71 3456 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3457 ixgbe_napi_enable_all(adapter);
3458
3459 /* clear any pending interrupts, may auto mask */
3460 IXGBE_READ_REG(hw, IXGBE_EICR);
3461
9a799d71
AK		 3462 ixgbe_irq_enable(adapter);
3463
bf069c97
DS		 3464 /*
3465 * If this adapter has a fan, check to see if we had a failure
3466 * before we enabled the interrupt.
3467 */
3468 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3469 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3470 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3471 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3472 }
3473
e8e26350
PW		 3474 /*
3475 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3476 * arrived before interrupts were enabled but after probe. Such
3477 * devices wouldn't have their type identified yet. We need to
3478 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3479 * If we're not hot-pluggable SFP+, we just need to configure link
3480 * and bring it up.
3481 */
19343de2
DS		 3482 if (hw->phy.type == ixgbe_phy_unknown) {
3483 err = hw->phy.ops.identify(hw);
3484 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3485 /*
3486 * Take the device down and schedule the sfp tasklet
3487 * which will unregister_netdev and log it.
3488 */
19343de2 3489 ixgbe_down(adapter);
5da43c1a 3490 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3491 return err;
3492 }
e8e26350
PW		 3493 }
3494
3495 if (ixgbe_is_sfp(hw)) {
3496 ixgbe_sfp_link_config(adapter);
3497 } else {
3498 err = ixgbe_non_sfp_link_config(hw);
3499 if (err)
396e799c 3500 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3501 }
0ecc061d 3502
c4cf55e5
PWJ		 3503 for (i = 0; i < adapter->num_tx_queues; i++)
3504 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3505 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3506
1da100bb
PWJ		 3507 /* enable transmits */
3508 netif_tx_start_all_queues(netdev);
3509
9a799d71
AK		 3510 /* bring the link up in the watchdog, this could race with our first
3511 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3512 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3513 adapter->link_check_timeout = jiffies;
9a799d71 3514 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3515
3516 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3517 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3518 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3519 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3520
9a799d71
AK		 3521 return 0;
3522}
3523
d4f80882
AV		 3524void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3525{
3526 WARN_ON(in_interrupt());
3527 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3528 msleep(1);
3529 ixgbe_down(adapter);
5809a1ae
GR		 3530 /*
3531 * If SR-IOV enabled then wait a bit before bringing the adapter
3532 * back up to give the VFs time to respond to the reset. The
3533 * two second wait is based upon the watchdog timer cycle in
3534 * the VF driver.
3535 */
3536 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3537 msleep(2000);
d4f80882
AV		 3538 ixgbe_up(adapter);
3539 clear_bit(__IXGBE_RESETTING, &adapter->state);
3540}
3541
9a799d71
AK		 3542int ixgbe_up(struct ixgbe_adapter *adapter)
3543{
3544 /* hardware has been reset, we need to reload some things */
3545 ixgbe_configure(adapter);
3546
3547 return ixgbe_up_complete(adapter);
3548}
3549
3550void ixgbe_reset(struct ixgbe_adapter *adapter)
3551{
c44ade9e 3552 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3553 int err;
3554
3555 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3556 switch (err) {
3557 case 0:
3558 case IXGBE_ERR_SFP_NOT_PRESENT:
3559 break;
3560 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3561 e_dev_err("master disable timed out\n");
da4dd0f7 3562 break;
794caeb2
PWJ		 3563 case IXGBE_ERR_EEPROM_VERSION:
3564 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3565 e_dev_warn("This device is a pre-production adapter/LOM. "
3566 "Please be aware there may be issuesassociated with "
3567 "your hardware. If you are experiencing problems "
3568 "please contact your Intel or hardware "
3569 "representative who provided you with this "
3570 "hardware.\n");
794caeb2 3571 break;
da4dd0f7 3572 default:
849c4542 3573 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3574 }
9a799d71
AK		 3575
3576 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3577 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3578 IXGBE_RAH_AV);
9a799d71
AK		 3579}
3580
9a799d71
AK		 3581/**
3582 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3583 * @adapter: board private structure
3584 * @rx_ring: ring to free buffers from
3585 **/
3586static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3587 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3588{
3589 struct pci_dev *pdev = adapter->pdev;
3590 unsigned long size;
3591 unsigned int i;
3592
3593 /* Free all the Rx ring sk_buffs */
3594
3595 for (i = 0; i < rx_ring->count; i++) {
3596 struct ixgbe_rx_buffer *rx_buffer_info;
3597
3598 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3599 if (rx_buffer_info->dma) {
1b507730 3600 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3601 rx_ring->rx_buf_len,
1b507730 3602 DMA_FROM_DEVICE);
9a799d71
AK		 3603 rx_buffer_info->dma = 0;
3604 }
3605 if (rx_buffer_info->skb) {
f8212f97 3606 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3607 rx_buffer_info->skb = NULL;
f8212f97
AD		 3608 do {
3609 struct sk_buff *this = skb;
e8171aaa 3610 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3611 dma_unmap_single(&pdev->dev,
3612 IXGBE_RSC_CB(this)->dma,
43634e82 3613 rx_ring->rx_buf_len,
1b507730 3614 DMA_FROM_DEVICE);
fd3686a8 3615 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3616 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3617 }
f8212f97
AD		 3618 skb = skb->prev;
3619 dev_kfree_skb(this);
3620 } while (skb);
9a799d71
AK		 3621 }
3622 if (!rx_buffer_info->page)
3623 continue;
4f57ca6e 3624 if (rx_buffer_info->page_dma) {
1b507730
NN		 3625 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3626 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3627 rx_buffer_info->page_dma = 0;
3628 }
9a799d71
AK		 3629 put_page(rx_buffer_info->page);
3630 rx_buffer_info->page = NULL;
762f4c57 3631 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3632 }
3633
3634 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3635 memset(rx_ring->rx_buffer_info, 0, size);
3636
3637 /* Zero out the descriptor ring */
3638 memset(rx_ring->desc, 0, rx_ring->size);
3639
3640 rx_ring->next_to_clean = 0;
3641 rx_ring->next_to_use = 0;
3642
9891ca7c
JB		 3643 if (rx_ring->head)
3644 writel(0, adapter->hw.hw_addr + rx_ring->head);
3645 if (rx_ring->tail)
3646 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3647}
3648
3649/**
3650 * ixgbe_clean_tx_ring - Free Tx Buffers
3651 * @adapter: board private structure
3652 * @tx_ring: ring to be cleaned
3653 **/
3654static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3655 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3656{
3657 struct ixgbe_tx_buffer *tx_buffer_info;
3658 unsigned long size;
3659 unsigned int i;
3660
3661 /* Free all the Tx ring sk_buffs */
3662
3663 for (i = 0; i < tx_ring->count; i++) {
3664 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3665 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3666 }
3667
3668 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3669 memset(tx_ring->tx_buffer_info, 0, size);
3670
3671 /* Zero out the descriptor ring */
3672 memset(tx_ring->desc, 0, tx_ring->size);
3673
3674 tx_ring->next_to_use = 0;
3675 tx_ring->next_to_clean = 0;
3676
9891ca7c
JB		 3677 if (tx_ring->head)
3678 writel(0, adapter->hw.hw_addr + tx_ring->head);
3679 if (tx_ring->tail)
3680 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3681}
3682
3683/**
021230d4 3684 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3685 * @adapter: board private structure
3686 **/
021230d4 3687static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3688{
3689 int i;
3690
021230d4 3691 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3692 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3693}
3694
3695/**
021230d4 3696 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3697 * @adapter: board private structure
3698 **/
021230d4 3699static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3700{
3701 int i;
3702
021230d4 3703 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3704 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3705}
3706
3707void ixgbe_down(struct ixgbe_adapter *adapter)
3708{
3709 struct net_device *netdev = adapter->netdev;
7f821875 3710 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3711 u32 rxctrl;
7f821875
JB		 3712 u32 txdctl;
3713 int i, j;
9a799d71
AK		 3714
3715 /* signal that we are down to the interrupt handler */
3716 set_bit(__IXGBE_DOWN, &adapter->state);
3717
767081ad
GR		 3718 /* disable receive for all VFs and wait one second */
3719 if (adapter->num_vfs) {
767081ad
GR		 3720 /* ping all the active vfs to let them know we are going down */
3721 ixgbe_ping_all_vfs(adapter);
581d1aa7 3722
767081ad
GR		 3723 /* Disable all VFTE/VFRE TX/RX */
3724 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3725
3726 /* Mark all the VFs as inactive */
3727 for (i = 0 ; i < adapter->num_vfs; i++)
3728 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3729 }
3730
9a799d71 3731 /* disable receives */
7f821875
JB		 3732 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3733 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3734
7f821875 3735 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3736 msleep(10);
3737
7f821875
JB		 3738 netif_tx_stop_all_queues(netdev);
3739
0a1f87cb
DS		 3740 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3741 del_timer_sync(&adapter->sfp_timer);
9a799d71 3742 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3743 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3744
c0dfb90e
JF		 3745 netif_carrier_off(netdev);
3746 netif_tx_disable(netdev);
3747
3748 ixgbe_irq_disable(adapter);
3749
3750 ixgbe_napi_disable_all(adapter);
3751
c4cf55e5
PWJ		 3752 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3753 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3754 cancel_work_sync(&adapter->fdir_reinit_task);
3755
119fc60a
MC		 3756 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3757 cancel_work_sync(&adapter->check_overtemp_task);
3758
7f821875
JB		 3759 /* disable transmits in the hardware now that interrupts are off */
3760 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3761 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3762 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3763 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3764 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3765 }
88512539
PW		 3766 /* Disable the Tx DMA engine on 82599 */
3767 if (hw->mac.type == ixgbe_mac_82599EB)
3768 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3769 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3770 ~IXGBE_DMATXCTL_TE));
7f821875 3771
9f756f01
JF		 3772 /* power down the optics */
3773 if (hw->phy.multispeed_fiber)
3774 hw->mac.ops.disable_tx_laser(hw);
3775
9a713e7c
PW		 3776 /* clear n-tuple filters that are cached */
3777 ethtool_ntuple_flush(netdev);
3778
6f4a0e45
PL		 3779 if (!pci_channel_offline(adapter->pdev))
3780 ixgbe_reset(adapter);
9a799d71
AK		 3781 ixgbe_clean_all_tx_rings(adapter);
3782 ixgbe_clean_all_rx_rings(adapter);
3783
5dd2d332 3784#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3785 /* since we reset the hardware DCA settings were cleared */
e35ec126 3786 ixgbe_setup_dca(adapter);
96b0e0f6 3787#endif
9a799d71
AK		 3788}
3789
9a799d71 3790/**
021230d4
AV		 3791 * ixgbe_poll - NAPI Rx polling callback
3792 * @napi: structure for representing this polling device
3793 * @budget: how many packets driver is allowed to clean
3794 *
3795 * This function is used for legacy and MSI, NAPI mode
9a799d71 3796 **/
021230d4 3797static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3798{
9a1a69ad
JB		 3799 struct ixgbe_q_vector *q_vector =
3800 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3801 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3802 int tx_clean_complete, work_done = 0;
9a799d71 3803
5dd2d332 3804#ifdef CONFIG_IXGBE_DCA
bd0362dd 3805 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3806 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3807 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3808 }
3809#endif
3810
4a0b9ca0
PW		 3811 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3812 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3813
9a1a69ad 3814 if (!tx_clean_complete)
d2c7ddd6
DM		 3815 work_done = budget;
3816
53e52c72
DM		 3817 /* If budget not fully consumed, exit the polling mode */
3818 if (work_done < budget) {
288379f0 3819 napi_complete(napi);
f7554a2b 3820 if (adapter->rx_itr_setting & 1)
f494e8fa 3821 ixgbe_set_itr(adapter);
d4f80882 3822 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3823 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3824 }
9a799d71
AK		 3825 return work_done;
3826}
3827
3828/**
3829 * ixgbe_tx_timeout - Respond to a Tx Hang
3830 * @netdev: network interface device structure
3831 **/
3832static void ixgbe_tx_timeout(struct net_device *netdev)
3833{
3834 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3835
3836 /* Do the reset outside of interrupt context */
3837 schedule_work(&adapter->reset_task);
3838}
3839
3840static void ixgbe_reset_task(struct work_struct *work)
3841{
3842 struct ixgbe_adapter *adapter;
3843 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3844
2f90b865
AD		 3845 /* If we're already down or resetting, just bail */
3846 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3847 test_bit(__IXGBE_RESETTING, &adapter->state))
3848 return;
3849
9a799d71
AK		 3850 adapter->tx_timeout_count++;
3851
dcd79aeb
TI		 3852 ixgbe_dump(adapter);
3853 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3854 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3855}
3856
bc97114d
PWJ		 3857#ifdef CONFIG_IXGBE_DCB
3858static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3859{
bc97114d 3860 bool ret = false;
0cefafad 3861 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3862
0cefafad
JB		 3863 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3864 return ret;
3865
3866 f->mask = 0x7 << 3;
3867 adapter->num_rx_queues = f->indices;
3868 adapter->num_tx_queues = f->indices;
3869 ret = true;
2f90b865 3870
bc97114d
PWJ		 3871 return ret;
3872}
3873#endif
3874
4df10466
JB		 3875/**
3876 * ixgbe_set_rss_queues: Allocate queues for RSS
3877 * @adapter: board private structure to initialize
3878 *
3879 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3880 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3881 *
3882 **/
bc97114d
PWJ		 3883static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3884{
3885 bool ret = false;
0cefafad 3886 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3887
3888 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3889 f->mask = 0xF;
3890 adapter->num_rx_queues = f->indices;
3891 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3892 ret = true;
3893 } else {
bc97114d 3894 ret = false;
b9804972
JB		 3895 }
3896
bc97114d
PWJ		 3897 return ret;
3898}
3899
c4cf55e5
PWJ		 3900/**
3901 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3902 * @adapter: board private structure to initialize
3903 *
3904 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3905 * to the original CPU that initiated the Tx session. This runs in addition
3906 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3907 * Rx load across CPUs using RSS.
3908 *
3909 **/
3910static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3911{
3912 bool ret = false;
3913 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3914
3915 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3916 f_fdir->mask = 0;
3917
3918 /* Flow Director must have RSS enabled */
3919 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3920 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3921 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3922 adapter->num_tx_queues = f_fdir->indices;
3923 adapter->num_rx_queues = f_fdir->indices;
3924 ret = true;
3925 } else {
3926 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3927 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3928 }
3929 return ret;
3930}
3931
0331a832
YZ		 3932#ifdef IXGBE_FCOE
3933/**
3934 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3935 * @adapter: board private structure to initialize
3936 *
3937 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3938 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3939 * rx queues out of the max number of rx queues, instead, it is used as the
3940 * index of the first rx queue used by FCoE.
3941 *
3942 **/
3943static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3944{
3945 bool ret = false;
3946 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3947
3948 f->indices = min((int)num_online_cpus(), f->indices);
3949 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3950 adapter->num_rx_queues = 1;
3951 adapter->num_tx_queues = 1;
0331a832
YZ		 3952#ifdef CONFIG_IXGBE_DCB
3953 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 3954 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 3955 ixgbe_set_dcb_queues(adapter);
3956 }
3957#endif
3958 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 3959 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3960 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3961 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3962 ixgbe_set_fdir_queues(adapter);
3963 else
3964 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3965 }
3966 /* adding FCoE rx rings to the end */
3967 f->mask = adapter->num_rx_queues;
3968 adapter->num_rx_queues += f->indices;
8de8b2e6 3969 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3970
3971 ret = true;
3972 }
3973
3974 return ret;
3975}
3976
3977#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3978/**
3979 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3980 * @adapter: board private structure to initialize
3981 *
3982 * IOV doesn't actually use anything, so just NAK the
3983 * request for now and let the other queue routines
3984 * figure out what to do.
3985 */
3986static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3987{
3988 return false;
3989}
3990
4df10466
JB		 3991/*
3992 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3993 * @adapter: board private structure to initialize
3994 *
3995 * This is the top level queue allocation routine. The order here is very
3996 * important, starting with the "most" number of features turned on at once,
3997 * and ending with the smallest set of features. This way large combinations
3998 * can be allocated if they're turned on, and smaller combinations are the
3999 * fallthrough conditions.
4000 *
4001 **/
bc97114d
PWJ		 4002static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4003{
1cdd1ec8
GR		 4004 /* Start with base case */
4005 adapter->num_rx_queues = 1;
4006 adapter->num_tx_queues = 1;
4007 adapter->num_rx_pools = adapter->num_rx_queues;
4008 adapter->num_rx_queues_per_pool = 1;
4009
4010 if (ixgbe_set_sriov_queues(adapter))
4011 return;
4012
0331a832
YZ		 4013#ifdef IXGBE_FCOE
4014 if (ixgbe_set_fcoe_queues(adapter))
4015 goto done;
4016
4017#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4018#ifdef CONFIG_IXGBE_DCB
4019 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4020 goto done;
bc97114d
PWJ		 4021
4022#endif
c4cf55e5
PWJ		 4023 if (ixgbe_set_fdir_queues(adapter))
4024 goto done;
4025
bc97114d 4026 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4027 goto done;
4028
4029 /* fallback to base case */
4030 adapter->num_rx_queues = 1;
4031 adapter->num_tx_queues = 1;
4032
4033done:
4034 /* Notify the stack of the (possibly) reduced Tx Queue count. */
f0796d5c 4035 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
b9804972
JB		 4036}
4037
021230d4 4038static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 4039 int vectors)
021230d4
AV		 4040{
4041 int err, vector_threshold;
4042
4043 /* We'll want at least 3 (vector_threshold):
4044 * 1) TxQ[0] Cleanup
4045 * 2) RxQ[0] Cleanup
4046 * 3) Other (Link Status Change, etc.)
4047 * 4) TCP Timer (optional)
4048 */
4049 vector_threshold = MIN_MSIX_COUNT;
4050
4051 /* The more we get, the more we will assign to Tx/Rx Cleanup
4052 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4053 * Right now, we simply care about how many we'll get; we'll
4054 * set them up later while requesting irq's.
4055 */
4056 while (vectors >= vector_threshold) {
4057 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 4058 vectors);
021230d4
AV		 4059 if (!err) /* Success in acquiring all requested vectors. */
4060 break;
4061 else if (err < 0)
4062 vectors = 0; /* Nasty failure, quit now */
4063 else /* err == number of vectors we should try again with */
4064 vectors = err;
4065 }
4066
4067 if (vectors < vector_threshold) {
4068 /* Can't allocate enough MSI-X interrupts? Oh well.
4069 * This just means we'll go with either a single MSI
4070 * vector or fall back to legacy interrupts.
4071 */
849c4542
ET		 4072 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4073 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4074 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4075 kfree(adapter->msix_entries);
4076 adapter->msix_entries = NULL;
021230d4
AV		 4077 } else {
4078 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4079 /*
4080 * Adjust for only the vectors we'll use, which is minimum
4081 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4082 * vectors we were allocated.
4083 */
4084 adapter->num_msix_vectors = min(vectors,
4085 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4086 }
4087}
4088
021230d4 4089/**
bc97114d 4090 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4091 * @adapter: board private structure to initialize
4092 *
bc97114d
PWJ		 4093 * Cache the descriptor ring offsets for RSS to the assigned rings.
4094 *
021230d4 4095 **/
bc97114d 4096static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4097{
bc97114d
PWJ		 4098 int i;
4099 bool ret = false;
4100
4101 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4102 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4103 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4104 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4105 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4106 ret = true;
4107 } else {
4108 ret = false;
4109 }
4110
4111 return ret;
4112}
4113
4114#ifdef CONFIG_IXGBE_DCB
4115/**
4116 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4117 * @adapter: board private structure to initialize
4118 *
4119 * Cache the descriptor ring offsets for DCB to the assigned rings.
4120 *
4121 **/
4122static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4123{
4124 int i;
4125 bool ret = false;
4126 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4127
4128 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4129 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4130 /* the number of queues is assumed to be symmetric */
4131 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4132 adapter->rx_ring[i]->reg_idx = i << 3;
4133 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4134 }
bc97114d 4135 ret = true;
e8e26350 4136 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4137 if (dcb_i == 8) {
4138 /*
4139 * Tx TC0 starts at: descriptor queue 0
4140 * Tx TC1 starts at: descriptor queue 32
4141 * Tx TC2 starts at: descriptor queue 64
4142 * Tx TC3 starts at: descriptor queue 80
4143 * Tx TC4 starts at: descriptor queue 96
4144 * Tx TC5 starts at: descriptor queue 104
4145 * Tx TC6 starts at: descriptor queue 112
4146 * Tx TC7 starts at: descriptor queue 120
4147 *
4148 * Rx TC0-TC7 are offset by 16 queues each
4149 */
4150 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4151 adapter->tx_ring[i]->reg_idx = i << 5;
4152 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4153 }
4154 for ( ; i < 5; i++) {
4a0b9ca0 4155 adapter->tx_ring[i]->reg_idx =
f92ef202 4156 ((i + 2) << 4);
4a0b9ca0 4157 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4158 }
4159 for ( ; i < dcb_i; i++) {
4a0b9ca0 4160 adapter->tx_ring[i]->reg_idx =
f92ef202 4161 ((i + 8) << 3);
4a0b9ca0 4162 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4163 }
4164
4165 ret = true;
4166 } else if (dcb_i == 4) {
4167 /*
4168 * Tx TC0 starts at: descriptor queue 0
4169 * Tx TC1 starts at: descriptor queue 64
4170 * Tx TC2 starts at: descriptor queue 96
4171 * Tx TC3 starts at: descriptor queue 112
4172 *
4173 * Rx TC0-TC3 are offset by 32 queues each
4174 */
4a0b9ca0
PW		 4175 adapter->tx_ring[0]->reg_idx = 0;
4176 adapter->tx_ring[1]->reg_idx = 64;
4177 adapter->tx_ring[2]->reg_idx = 96;
4178 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4179 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4180 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4181
4182 ret = true;
4183 } else {
4184 ret = false;
e8e26350 4185 }
bc97114d
PWJ		 4186 } else {
4187 ret = false;
021230d4 4188 }
bc97114d
PWJ		 4189 } else {
4190 ret = false;
021230d4 4191 }
bc97114d
PWJ		 4192
4193 return ret;
4194}
4195#endif
4196
c4cf55e5
PWJ		 4197/**
4198 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4199 * @adapter: board private structure to initialize
4200 *
4201 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4202 *
4203 **/
4204static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4205{
4206 int i;
4207 bool ret = false;
4208
4209 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4210 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4211 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4212 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4213 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4214 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4215 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4216 ret = true;
4217 }
4218
4219 return ret;
4220}
4221
0331a832
YZ		 4222#ifdef IXGBE_FCOE
4223/**
4224 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4225 * @adapter: board private structure to initialize
4226 *
4227 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4228 *
4229 */
4230static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4231{
8de8b2e6 4232 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4233 bool ret = false;
4234 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4235
4236 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4237#ifdef CONFIG_IXGBE_DCB
4238 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4239 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4240
0331a832 4241 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4242 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4243 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4244 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4245 /*
4246 * In 82599, the number of Tx queues for each traffic
4247 * class for both 8-TC and 4-TC modes are:
4248 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4249 * 8 TCs: 32 32 16 16 8 8 8 8
4250 * 4 TCs: 64 64 32 32
4251 * We have max 8 queues for FCoE, where 8 the is
4252 * FCoE redirection table size. If TC for FCoE is
4253 * less than or equal to TC3, we have enough queues
4254 * to add max of 8 queues for FCoE, so we start FCoE
4255 * tx descriptor from the next one, i.e., reg_idx + 1.
4256 * If TC for FCoE is above TC3, implying 8 TC mode,
4257 * and we need 8 for FCoE, we have to take all queues
4258 * in that traffic class for FCoE.
4259 */
4260 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4261 fcoe_tx_i--;
0331a832
YZ		 4262 }
4263#endif /* CONFIG_IXGBE_DCB */
4264 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4265 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4266 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4267 ixgbe_cache_ring_fdir(adapter);
4268 else
4269 ixgbe_cache_ring_rss(adapter);
4270
8de8b2e6
YZ		 4271 fcoe_rx_i = f->mask;
4272 fcoe_tx_i = f->mask;
4273 }
4274 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4275 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4276 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4277 }
0331a832
YZ		 4278 ret = true;
4279 }
4280 return ret;
4281}
4282
4283#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4284/**
4285 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4286 * @adapter: board private structure to initialize
4287 *
4288 * SR-IOV doesn't use any descriptor rings but changes the default if
4289 * no other mapping is used.
4290 *
4291 */
4292static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4293{
4a0b9ca0
PW		 4294 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4295 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4296 if (adapter->num_vfs)
4297 return true;
4298 else
4299 return false;
4300}
4301
bc97114d
PWJ		 4302/**
4303 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4304 * @adapter: board private structure to initialize
4305 *
4306 * Once we know the feature-set enabled for the device, we'll cache
4307 * the register offset the descriptor ring is assigned to.
4308 *
4309 * Note, the order the various feature calls is important. It must start with
4310 * the "most" features enabled at the same time, then trickle down to the
4311 * least amount of features turned on at once.
4312 **/
4313static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4314{
4315 /* start with default case */
4a0b9ca0
PW		 4316 adapter->rx_ring[0]->reg_idx = 0;
4317 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4318
1cdd1ec8
GR		 4319 if (ixgbe_cache_ring_sriov(adapter))
4320 return;
4321
0331a832
YZ		 4322#ifdef IXGBE_FCOE
4323 if (ixgbe_cache_ring_fcoe(adapter))
4324 return;
4325
4326#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4327#ifdef CONFIG_IXGBE_DCB
4328 if (ixgbe_cache_ring_dcb(adapter))
4329 return;
4330
4331#endif
c4cf55e5
PWJ		 4332 if (ixgbe_cache_ring_fdir(adapter))
4333 return;
4334
bc97114d
PWJ		 4335 if (ixgbe_cache_ring_rss(adapter))
4336 return;
021230d4
AV		 4337}
4338
9a799d71
AK		 4339/**
4340 * ixgbe_alloc_queues - Allocate memory for all rings
4341 * @adapter: board private structure to initialize
4342 *
4343 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4344 * number of queues at compile-time. The polling_netdev array is
4345 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4346 **/
2f90b865 4347static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4348{
4349 int i;
4a0b9ca0 4350 int orig_node = adapter->node;
9a799d71 4351
021230d4 4352 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4353 struct ixgbe_ring *ring = adapter->tx_ring[i];
4354 if (orig_node == -1) {
4355 int cur_node = next_online_node(adapter->node);
4356 if (cur_node == MAX_NUMNODES)
4357 cur_node = first_online_node;
4358 adapter->node = cur_node;
4359 }
4360 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4361 adapter->node);
4362 if (!ring)
4363 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4364 if (!ring)
4365 goto err_tx_ring_allocation;
4366 ring->count = adapter->tx_ring_count;
4367 ring->queue_index = i;
4368 ring->numa_node = adapter->node;
4369
4370 adapter->tx_ring[i] = ring;
021230d4 4371 }
b9804972 4372
4a0b9ca0
PW		 4373 /* Restore the adapter's original node */
4374 adapter->node = orig_node;
4375
9a799d71 4376 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4377 struct ixgbe_ring *ring = adapter->rx_ring[i];
4378 if (orig_node == -1) {
4379 int cur_node = next_online_node(adapter->node);
4380 if (cur_node == MAX_NUMNODES)
4381 cur_node = first_online_node;
4382 adapter->node = cur_node;
4383 }
4384 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4385 adapter->node);
4386 if (!ring)
4387 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4388 if (!ring)
4389 goto err_rx_ring_allocation;
4390 ring->count = adapter->rx_ring_count;
4391 ring->queue_index = i;
4392 ring->numa_node = adapter->node;
4393
4394 adapter->rx_ring[i] = ring;
021230d4
AV		 4395 }
4396
4a0b9ca0
PW		 4397 /* Restore the adapter's original node */
4398 adapter->node = orig_node;
4399
021230d4
AV		 4400 ixgbe_cache_ring_register(adapter);
4401
4402 return 0;
4403
4404err_rx_ring_allocation:
4a0b9ca0
PW		 4405 for (i = 0; i < adapter->num_tx_queues; i++)
4406 kfree(adapter->tx_ring[i]);
021230d4
AV		 4407err_tx_ring_allocation:
4408 return -ENOMEM;
4409}
4410
4411/**
4412 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4413 * @adapter: board private structure to initialize
4414 *
4415 * Attempt to configure the interrupts using the best available
4416 * capabilities of the hardware and the kernel.
4417 **/
feea6a57 4418static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4419{
8be0e467 4420 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4421 int err = 0;
4422 int vector, v_budget;
4423
4424 /*
4425 * It's easy to be greedy for MSI-X vectors, but it really
4426 * doesn't do us much good if we have a lot more vectors
4427 * than CPU's. So let's be conservative and only ask for
342bde1b 4428 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4429 */
4430 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 4431 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4432
4433 /*
4434 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4435 * hw.mac->max_msix_vectors vectors. With features
4436 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4437 * descriptor queues supported by our device. Thus, we cap it off in
4438 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4439 */
8be0e467 4440 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4441
4442 /* A failure in MSI-X entry allocation isn't fatal, but it does
4443 * mean we disable MSI-X capabilities of the adapter. */
4444 adapter->msix_entries = kcalloc(v_budget,
b4617240 4445 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4446 if (adapter->msix_entries) {
4447 for (vector = 0; vector < v_budget; vector++)
4448 adapter->msix_entries[vector].entry = vector;
021230d4 4449
7a921c93 4450 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4451
7a921c93
AD		 4452 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4453 goto out;
4454 }
26d27844 4455
7a921c93
AD		 4456 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4457 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4458 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4459 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4460 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4461 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4462 ixgbe_disable_sriov(adapter);
4463
7a921c93 4464 ixgbe_set_num_queues(adapter);
021230d4 4465
021230d4
AV		 4466 err = pci_enable_msi(adapter->pdev);
4467 if (!err) {
4468 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4469 } else {
849c4542
ET		 4470 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4471 "Unable to allocate MSI interrupt, "
4472 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4473 /* reset err */
4474 err = 0;
4475 }
4476
4477out:
021230d4
AV		 4478 return err;
4479}
4480
7a921c93
AD		 4481/**
4482 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4483 * @adapter: board private structure to initialize
4484 *
4485 * We allocate one q_vector per queue interrupt. If allocation fails we
4486 * return -ENOMEM.
4487 **/
4488static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4489{
4490 int q_idx, num_q_vectors;
4491 struct ixgbe_q_vector *q_vector;
4492 int napi_vectors;
4493 int (*poll)(struct napi_struct *, int);
4494
4495 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4496 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4497 napi_vectors = adapter->num_rx_queues;
91281fd3 4498 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4499 } else {
4500 num_q_vectors = 1;
4501 napi_vectors = 1;
4502 poll = &ixgbe_poll;
4503 }
4504
4505 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4506 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4507 GFP_KERNEL, adapter->node);
4508 if (!q_vector)
4509 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4510 GFP_KERNEL);
7a921c93
AD		 4511 if (!q_vector)
4512 goto err_out;
4513 q_vector->adapter = adapter;
f7554a2b
NS		 4514 if (q_vector->txr_count && !q_vector->rxr_count)
4515 q_vector->eitr = adapter->tx_eitr_param;
4516 else
4517 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4518 q_vector->v_idx = q_idx;
91281fd3 4519 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4520 adapter->q_vector[q_idx] = q_vector;
4521 }
4522
4523 return 0;
4524
4525err_out:
4526 while (q_idx) {
4527 q_idx--;
4528 q_vector = adapter->q_vector[q_idx];
4529 netif_napi_del(&q_vector->napi);
4530 kfree(q_vector);
4531 adapter->q_vector[q_idx] = NULL;
4532 }
4533 return -ENOMEM;
4534}
4535
4536/**
4537 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4538 * @adapter: board private structure to initialize
4539 *
4540 * This function frees the memory allocated to the q_vectors. In addition if
4541 * NAPI is enabled it will delete any references to the NAPI struct prior
4542 * to freeing the q_vector.
4543 **/
4544static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4545{
4546 int q_idx, num_q_vectors;
7a921c93 4547
91281fd3 4548 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4549 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4550 else
7a921c93 4551 num_q_vectors = 1;
7a921c93
AD		 4552
4553 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4554 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4555 adapter->q_vector[q_idx] = NULL;
91281fd3 4556 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4557 kfree(q_vector);
4558 }
4559}
4560
7b25cdba 4561static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4562{
4563 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4564 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4565 pci_disable_msix(adapter->pdev);
4566 kfree(adapter->msix_entries);
4567 adapter->msix_entries = NULL;
4568 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4569 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4570 pci_disable_msi(adapter->pdev);
4571 }
021230d4
AV		 4572}
4573
4574/**
4575 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4576 * @adapter: board private structure to initialize
4577 *
4578 * We determine which interrupt scheme to use based on...
4579 * - Kernel support (MSI, MSI-X)
4580 * - which can be user-defined (via MODULE_PARAM)
4581 * - Hardware queue count (num_*_queues)
4582 * - defined by miscellaneous hardware support/features (RSS, etc.)
4583 **/
2f90b865 4584int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4585{
4586 int err;
4587
4588 /* Number of supported queues */
4589 ixgbe_set_num_queues(adapter);
4590
021230d4
AV		 4591 err = ixgbe_set_interrupt_capability(adapter);
4592 if (err) {
849c4542 4593 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4594 goto err_set_interrupt;
9a799d71
AK		 4595 }
4596
7a921c93
AD		 4597 err = ixgbe_alloc_q_vectors(adapter);
4598 if (err) {
849c4542 4599 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4600 goto err_alloc_q_vectors;
4601 }
4602
4603 err = ixgbe_alloc_queues(adapter);
4604 if (err) {
849c4542 4605 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4606 goto err_alloc_queues;
4607 }
4608
849c4542 4609 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4610 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4611 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4612
4613 set_bit(__IXGBE_DOWN, &adapter->state);
4614
9a799d71 4615 return 0;
021230d4 4616
7a921c93
AD		 4617err_alloc_queues:
4618 ixgbe_free_q_vectors(adapter);
4619err_alloc_q_vectors:
4620 ixgbe_reset_interrupt_capability(adapter);
021230d4 4621err_set_interrupt:
7a921c93
AD		 4622 return err;
4623}
4624
4625/**
4626 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4627 * @adapter: board private structure to clear interrupt scheme on
4628 *
4629 * We go through and clear interrupt specific resources and reset the structure
4630 * to pre-load conditions
4631 **/
4632void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4633{
4a0b9ca0
PW		 4634 int i;
4635
4636 for (i = 0; i < adapter->num_tx_queues; i++) {
4637 kfree(adapter->tx_ring[i]);
4638 adapter->tx_ring[i] = NULL;
4639 }
4640 for (i = 0; i < adapter->num_rx_queues; i++) {
4641 kfree(adapter->rx_ring[i]);
4642 adapter->rx_ring[i] = NULL;
4643 }
7a921c93
AD		 4644
4645 ixgbe_free_q_vectors(adapter);
4646 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4647}
4648
c4900be0
DS		 4649/**
4650 * ixgbe_sfp_timer - worker thread to find a missing module
4651 * @data: pointer to our adapter struct
4652 **/
4653static void ixgbe_sfp_timer(unsigned long data)
4654{
4655 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4656
4df10466
JB		 4657 /*
4658 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4659 * delays that sfp+ detection requires
4660 */
4661 schedule_work(&adapter->sfp_task);
4662}
4663
4664/**
4665 * ixgbe_sfp_task - worker thread to find a missing module
4666 * @work: pointer to work_struct containing our data
4667 **/
4668static void ixgbe_sfp_task(struct work_struct *work)
4669{
4670 struct ixgbe_adapter *adapter = container_of(work,
4671 struct ixgbe_adapter,
4672 sfp_task);
4673 struct ixgbe_hw *hw = &adapter->hw;
4674
4675 if ((hw->phy.type == ixgbe_phy_nl) &&
4676 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4677 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4678 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4679 goto reschedule;
4680 ret = hw->phy.ops.reset(hw);
4681 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4682 e_dev_err("failed to initialize because an unsupported "
4683 "SFP+ module type was detected.\n");
4684 e_dev_err("Reload the driver after installing a "
4685 "supported module.\n");
c4900be0
DS		 4686 unregister_netdev(adapter->netdev);
4687 } else {
396e799c 4688 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4689 }
4690 /* don't need this routine any more */
4691 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4692 }
4693 return;
4694reschedule:
4695 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4696 mod_timer(&adapter->sfp_timer,
4697 round_jiffies(jiffies + (2 * HZ)));
4698}
4699
9a799d71
AK		 4700/**
4701 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4702 * @adapter: board private structure to initialize
4703 *
4704 * ixgbe_sw_init initializes the Adapter private data structure.
4705 * Fields are initialized based on PCI device information and
4706 * OS network device settings (MTU size).
4707 **/
4708static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4709{
4710 struct ixgbe_hw *hw = &adapter->hw;
4711 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4712 struct net_device *dev = adapter->netdev;
021230d4 4713 unsigned int rss;
7a6b6f51 4714#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4715 int j;
4716 struct tc_configuration *tc;
4717#endif
021230d4 4718
c44ade9e
JB		 4719 /* PCI config space info */
4720
4721 hw->vendor_id = pdev->vendor;
4722 hw->device_id = pdev->device;
4723 hw->revision_id = pdev->revision;
4724 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4725 hw->subsystem_device_id = pdev->subsystem_device;
4726
021230d4
AV		 4727 /* Set capability flags */
4728 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4729 adapter->ring_feature[RING_F_RSS].indices = rss;
4730 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4731 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4732 if (hw->mac.type == ixgbe_mac_82598EB) {
4733 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4734 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4735 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4736 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4737 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4738 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4739 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4740 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4741 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4742 if (dev->features & NETIF_F_NTUPLE) {
4743 /* Flow Director perfect filter enabled */
4744 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4745 adapter->atr_sample_rate = 0;
4746 spin_lock_init(&adapter->fdir_perfect_lock);
4747 } else {
4748 /* Flow Director hash filters enabled */
4749 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4750 adapter->atr_sample_rate = 20;
4751 }
c4cf55e5
PWJ		 4752 adapter->ring_feature[RING_F_FDIR].indices =
4753 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4754 adapter->fdir_pballoc = 0;
eacd73f7 4755#ifdef IXGBE_FCOE
0d551589
YZ		 4756 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4757 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4758 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4759#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4760 /* Default traffic class to use for FCoE */
4761 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4762 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4763#endif
eacd73f7 4764#endif /* IXGBE_FCOE */
f8212f97 4765 }
2f90b865 4766
7a6b6f51 4767#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4768 /* Configure DCB traffic classes */
4769 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4770 tc = &adapter->dcb_cfg.tc_config[j];
4771 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4772 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4773 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4774 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4775 tc->dcb_pfc = pfc_disabled;
4776 }
4777 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4778 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4779 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4780 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4781 adapter->dcb_cfg.round_robin_enable = false;
4782 adapter->dcb_set_bitmap = 0x00;
4783 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4784 adapter->ring_feature[RING_F_DCB].indices);
4785
4786#endif
9a799d71
AK		 4787
4788 /* default flow control settings */
cd7664f6 4789 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4790 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4791#ifdef CONFIG_DCB
4792 adapter->last_lfc_mode = hw->fc.current_mode;
4793#endif
2b9ade93
JB		 4794 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4795 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4796 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4797 hw->fc.send_xon = true;
71fd570b 4798 hw->fc.disable_fc_autoneg = false;
9a799d71 4799
30efa5a3 4800 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4801 adapter->rx_itr_setting = 1;
4802 adapter->rx_eitr_param = 20000;
4803 adapter->tx_itr_setting = 1;
4804 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4805
4806 /* set defaults for eitr in MegaBytes */
4807 adapter->eitr_low = 10;
4808 adapter->eitr_high = 20;
4809
4810 /* set default ring sizes */
4811 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4812 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4813
9a799d71 4814 /* initialize eeprom parameters */
c44ade9e 4815 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4816 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4817 return -EIO;
4818 }
4819
021230d4 4820 /* enable rx csum by default */
9a799d71
AK		 4821 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4822
1a6c14a2
JB		 4823 /* get assigned NUMA node */
4824 adapter->node = dev_to_node(&pdev->dev);
4825
9a799d71
AK		 4826 set_bit(__IXGBE_DOWN, &adapter->state);
4827
4828 return 0;
4829}
4830
4831/**
4832 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4833 * @adapter: board private structure
3a581073 4834 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4835 *
4836 * Return 0 on success, negative on failure
4837 **/
4838int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4839 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4840{
4841 struct pci_dev *pdev = adapter->pdev;
4842 int size;
4843
3a581073 4844 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4845 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4846 if (!tx_ring->tx_buffer_info)
4847 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4848 if (!tx_ring->tx_buffer_info)
4849 goto err;
3a581073 4850 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4851
4852 /* round up to nearest 4K */
12207e49 4853 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4854 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4855
1b507730
NN		 4856 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4857 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4858 if (!tx_ring->desc)
4859 goto err;
9a799d71 4860
3a581073
JB		 4861 tx_ring->next_to_use = 0;
4862 tx_ring->next_to_clean = 0;
4863 tx_ring->work_limit = tx_ring->count;
9a799d71 4864 return 0;
e01c31a5
JB		 4865
4866err:
4867 vfree(tx_ring->tx_buffer_info);
4868 tx_ring->tx_buffer_info = NULL;
396e799c 4869 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4870 return -ENOMEM;
9a799d71
AK		 4871}
4872
69888674
AD		 4873/**
4874 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4875 * @adapter: board private structure
4876 *
4877 * If this function returns with an error, then it's possible one or
4878 * more of the rings is populated (while the rest are not). It is the
4879 * callers duty to clean those orphaned rings.
4880 *
4881 * Return 0 on success, negative on failure
4882 **/
4883static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4884{
4885 int i, err = 0;
4886
4887 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4888 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4889 if (!err)
4890 continue;
396e799c 4891 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4892 break;
4893 }
4894
4895 return err;
4896}
4897
9a799d71
AK		 4898/**
4899 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4900 * @adapter: board private structure
3a581073 4901 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4902 *
4903 * Returns 0 on success, negative on failure
4904 **/
4905int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4906 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4907{
4908 struct pci_dev *pdev = adapter->pdev;
021230d4 4909 int size;
9a799d71 4910
3a581073 4911 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4912 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4913 if (!rx_ring->rx_buffer_info)
4914 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4915 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 4916 e_err(probe, "vmalloc allocation failed for the Rx "
4917 "descriptor ring\n");
177db6ff 4918 goto alloc_failed;
9a799d71 4919 }
3a581073 4920 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4921
9a799d71 4922 /* Round up to nearest 4K */
3a581073
JB		 4923 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4924 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4925
1b507730
NN		 4926 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4927 &rx_ring->dma, GFP_KERNEL);
9a799d71 4928
3a581073 4929 if (!rx_ring->desc) {
396e799c
ET		 4930 e_err(probe, "Memory allocation failed for the Rx "
4931 "descriptor ring\n");
3a581073 4932 vfree(rx_ring->rx_buffer_info);
177db6ff 4933 goto alloc_failed;
9a799d71
AK		 4934 }
4935
3a581073
JB		 4936 rx_ring->next_to_clean = 0;
4937 rx_ring->next_to_use = 0;
9a799d71
AK		 4938
4939 return 0;
177db6ff
MC		 4940
4941alloc_failed:
177db6ff 4942 return -ENOMEM;
9a799d71
AK		 4943}
4944
69888674
AD		 4945/**
4946 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4947 * @adapter: board private structure
4948 *
4949 * If this function returns with an error, then it's possible one or
4950 * more of the rings is populated (while the rest are not). It is the
4951 * callers duty to clean those orphaned rings.
4952 *
4953 * Return 0 on success, negative on failure
4954 **/
4955
4956static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4957{
4958 int i, err = 0;
4959
4960 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4961 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4962 if (!err)
4963 continue;
396e799c 4964 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 4965 break;
4966 }
4967
4968 return err;
4969}
4970
9a799d71
AK		 4971/**
4972 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4973 * @adapter: board private structure
4974 * @tx_ring: Tx descriptor ring for a specific queue
4975 *
4976 * Free all transmit software resources
4977 **/
c431f97e
JB		 4978void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4979 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4980{
4981 struct pci_dev *pdev = adapter->pdev;
4982
4983 ixgbe_clean_tx_ring(adapter, tx_ring);
4984
4985 vfree(tx_ring->tx_buffer_info);
4986 tx_ring->tx_buffer_info = NULL;
4987
1b507730
NN		 4988 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
4989 tx_ring->dma);
9a799d71
AK		 4990
4991 tx_ring->desc = NULL;
4992}
4993
4994/**
4995 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4996 * @adapter: board private structure
4997 *
4998 * Free all transmit software resources
4999 **/
5000static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5001{
5002 int i;
5003
5004 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5005 if (adapter->tx_ring[i]->desc)
5006 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5007}
5008
5009/**
b4617240 5010 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5011 * @adapter: board private structure
5012 * @rx_ring: ring to clean the resources from
5013 *
5014 * Free all receive software resources
5015 **/
c431f97e
JB		 5016void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5017 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5018{
5019 struct pci_dev *pdev = adapter->pdev;
5020
5021 ixgbe_clean_rx_ring(adapter, rx_ring);
5022
5023 vfree(rx_ring->rx_buffer_info);
5024 rx_ring->rx_buffer_info = NULL;
5025
1b507730
NN		 5026 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5027 rx_ring->dma);
9a799d71
AK		 5028
5029 rx_ring->desc = NULL;
5030}
5031
5032/**
5033 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5034 * @adapter: board private structure
5035 *
5036 * Free all receive software resources
5037 **/
5038static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5039{
5040 int i;
5041
5042 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5043 if (adapter->rx_ring[i]->desc)
5044 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5045}
5046
9a799d71
AK		 5047/**
5048 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5049 * @netdev: network interface device structure
5050 * @new_mtu: new value for maximum frame size
5051 *
5052 * Returns 0 on success, negative on failure
5053 **/
5054static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5055{
5056 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5057 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5058
42c783c5
JB		 5059 /* MTU < 68 is an error and causes problems on some kernels */
5060 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5061 return -EINVAL;
5062
396e799c 5063 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5064 /* must set new MTU before calling down or up */
9a799d71
AK		 5065 netdev->mtu = new_mtu;
5066
d4f80882
AV		 5067 if (netif_running(netdev))
5068 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5069
5070 return 0;
5071}
5072
5073/**
5074 * ixgbe_open - Called when a network interface is made active
5075 * @netdev: network interface device structure
5076 *
5077 * Returns 0 on success, negative value on failure
5078 *
5079 * The open entry point is called when a network interface is made
5080 * active by the system (IFF_UP). At this point all resources needed
5081 * for transmit and receive operations are allocated, the interrupt
5082 * handler is registered with the OS, the watchdog timer is started,
5083 * and the stack is notified that the interface is ready.
5084 **/
5085static int ixgbe_open(struct net_device *netdev)
5086{
5087 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5088 int err;
4bebfaa5
AK		 5089
5090 /* disallow open during test */
5091 if (test_bit(__IXGBE_TESTING, &adapter->state))
5092 return -EBUSY;
9a799d71 5093
54386467
JB		 5094 netif_carrier_off(netdev);
5095
9a799d71
AK		 5096 /* allocate transmit descriptors */
5097 err = ixgbe_setup_all_tx_resources(adapter);
5098 if (err)
5099 goto err_setup_tx;
5100
9a799d71
AK		 5101 /* allocate receive descriptors */
5102 err = ixgbe_setup_all_rx_resources(adapter);
5103 if (err)
5104 goto err_setup_rx;
5105
5106 ixgbe_configure(adapter);
5107
021230d4 5108 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5109 if (err)
5110 goto err_req_irq;
5111
9a799d71
AK		 5112 err = ixgbe_up_complete(adapter);
5113 if (err)
5114 goto err_up;
5115
d55b53ff
JK		 5116 netif_tx_start_all_queues(netdev);
5117
9a799d71
AK		 5118 return 0;
5119
5120err_up:
5eba3699 5121 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5122 ixgbe_free_irq(adapter);
5123err_req_irq:
9a799d71 5124err_setup_rx:
a20a1199 5125 ixgbe_free_all_rx_resources(adapter);
9a799d71 5126err_setup_tx:
a20a1199 5127 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5128 ixgbe_reset(adapter);
5129
5130 return err;
5131}
5132
5133/**
5134 * ixgbe_close - Disables a network interface
5135 * @netdev: network interface device structure
5136 *
5137 * Returns 0, this is not allowed to fail
5138 *
5139 * The close entry point is called when an interface is de-activated
5140 * by the OS. The hardware is still under the drivers control, but
5141 * needs to be disabled. A global MAC reset is issued to stop the
5142 * hardware, and all transmit and receive resources are freed.
5143 **/
5144static int ixgbe_close(struct net_device *netdev)
5145{
5146 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5147
5148 ixgbe_down(adapter);
5149 ixgbe_free_irq(adapter);
5150
5151 ixgbe_free_all_tx_resources(adapter);
5152 ixgbe_free_all_rx_resources(adapter);
5153
5eba3699 5154 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5155
5156 return 0;
5157}
5158
b3c8b4ba
AD		 5159#ifdef CONFIG_PM
5160static int ixgbe_resume(struct pci_dev *pdev)
5161{
5162 struct net_device *netdev = pci_get_drvdata(pdev);
5163 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5164 u32 err;
5165
5166 pci_set_power_state(pdev, PCI_D0);
5167 pci_restore_state(pdev);
656ab817
DS		 5168 /*
5169 * pci_restore_state clears dev->state_saved so call
5170 * pci_save_state to restore it.
5171 */
5172 pci_save_state(pdev);
9ce77666 5173
5174 err = pci_enable_device_mem(pdev);
b3c8b4ba 5175 if (err) {
849c4542 5176 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5177 return err;
5178 }
5179 pci_set_master(pdev);
5180
dd4d8ca6 5181 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5182
5183 err = ixgbe_init_interrupt_scheme(adapter);
5184 if (err) {
849c4542 5185 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5186 return err;
5187 }
5188
b3c8b4ba
AD		 5189 ixgbe_reset(adapter);
5190
495dce12
WJP		 5191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5192
b3c8b4ba
AD		 5193 if (netif_running(netdev)) {
5194 err = ixgbe_open(adapter->netdev);
5195 if (err)
5196 return err;
5197 }
5198
5199 netif_device_attach(netdev);
5200
5201 return 0;
5202}
b3c8b4ba 5203#endif /* CONFIG_PM */
9d8d05ae
RW		 5204
5205static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5206{
5207 struct net_device *netdev = pci_get_drvdata(pdev);
5208 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5209 struct ixgbe_hw *hw = &adapter->hw;
5210 u32 ctrl, fctrl;
5211 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5212#ifdef CONFIG_PM
5213 int retval = 0;
5214#endif
5215
5216 netif_device_detach(netdev);
5217
5218 if (netif_running(netdev)) {
5219 ixgbe_down(adapter);
5220 ixgbe_free_irq(adapter);
5221 ixgbe_free_all_tx_resources(adapter);
5222 ixgbe_free_all_rx_resources(adapter);
5223 }
b3c8b4ba
AD		 5224
5225#ifdef CONFIG_PM
5226 retval = pci_save_state(pdev);
5227 if (retval)
5228 return retval;
4df10466 5229
b3c8b4ba 5230#endif
e8e26350
PW		 5231 if (wufc) {
5232 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5233
e8e26350
PW		 5234 /* turn on all-multi mode if wake on multicast is enabled */
5235 if (wufc & IXGBE_WUFC_MC) {
5236 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5237 fctrl |= IXGBE_FCTRL_MPE;
5238 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5239 }
5240
5241 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5242 ctrl |= IXGBE_CTRL_GIO_DIS;
5243 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5244
5245 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5246 } else {
5247 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5248 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5249 }
5250
dd4d8ca6
DS		 5251 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5252 pci_wake_from_d3(pdev, true);
5253 else
5254 pci_wake_from_d3(pdev, false);
b3c8b4ba 5255
9d8d05ae
RW		 5256 *enable_wake = !!wufc;
5257
fa378134
AG		 5258 ixgbe_clear_interrupt_scheme(adapter);
5259
b3c8b4ba
AD		 5260 ixgbe_release_hw_control(adapter);
5261
5262 pci_disable_device(pdev);
5263
9d8d05ae
RW		 5264 return 0;
5265}
5266
5267#ifdef CONFIG_PM
5268static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5269{
5270 int retval;
5271 bool wake;
5272
5273 retval = __ixgbe_shutdown(pdev, &wake);
5274 if (retval)
5275 return retval;
5276
5277 if (wake) {
5278 pci_prepare_to_sleep(pdev);
5279 } else {
5280 pci_wake_from_d3(pdev, false);
5281 pci_set_power_state(pdev, PCI_D3hot);
5282 }
b3c8b4ba
AD		 5283
5284 return 0;
5285}
9d8d05ae 5286#endif /* CONFIG_PM */
b3c8b4ba
AD		 5287
5288static void ixgbe_shutdown(struct pci_dev *pdev)
5289{
9d8d05ae
RW		 5290 bool wake;
5291
5292 __ixgbe_shutdown(pdev, &wake);
5293
5294 if (system_state == SYSTEM_POWER_OFF) {
5295 pci_wake_from_d3(pdev, wake);
5296 pci_set_power_state(pdev, PCI_D3hot);
5297 }
b3c8b4ba
AD		 5298}
5299
9a799d71
AK		 5300/**
5301 * ixgbe_update_stats - Update the board statistics counters.
5302 * @adapter: board private structure
5303 **/
5304void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5305{
2d86f139 5306 struct net_device *netdev = adapter->netdev;
9a799d71 5307 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5308 u64 total_mpc = 0;
5309 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5310 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5311
d08935c2
DS		 5312 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5313 test_bit(__IXGBE_RESETTING, &adapter->state))
5314 return;
5315
94b982b2 5316 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5317 u64 rsc_count = 0;
94b982b2 5318 u64 rsc_flush = 0;
d51019a4
PW		 5319 for (i = 0; i < 16; i++)
5320 adapter->hw_rx_no_dma_resources +=
5321 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5322 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5323 rsc_count += adapter->rx_ring[i]->rsc_count;
5324 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5325 }
5326 adapter->rsc_total_count = rsc_count;
5327 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5328 }
5329
7ca3bc58
JB		 5330 /* gather some stats to the adapter struct that are per queue */
5331 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5332 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5333 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5334
5335 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5336 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5337 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5338
9a799d71 5339 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5340 for (i = 0; i < 8; i++) {
5341 /* for packet buffers not used, the register should read 0 */
5342 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5343 missed_rx += mpc;
5344 adapter->stats.mpc[i] += mpc;
5345 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5346 if (hw->mac.type == ixgbe_mac_82598EB)
5347 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5348 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5349 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5350 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5351 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5352 if (hw->mac.type == ixgbe_mac_82599EB) {
5353 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5354 IXGBE_PXONRXCNT(i));
5355 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5356 IXGBE_PXOFFRXCNT(i));
5357 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5358 } else {
5359 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5360 IXGBE_PXONRXC(i));
5361 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5362 IXGBE_PXOFFRXC(i));
5363 }
2f90b865
AD		 5364 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5365 IXGBE_PXONTXC(i));
2f90b865 5366 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 5367 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5368 }
5369 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5370 /* work around hardware counting issue */
5371 adapter->stats.gprc -= missed_rx;
5372
5373 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5374 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5375 u64 tmp;
e8e26350 5376 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 5377 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5378 adapter->stats.gorc += (tmp << 32);
e8e26350 5379 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 5380 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5381 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 5382 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5383 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5384 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5385 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5386 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5387 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5388#ifdef IXGBE_FCOE
5389 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5390 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5391 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5392 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5393 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5394 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5395#endif /* IXGBE_FCOE */
e8e26350
PW		 5396 } else {
5397 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5398 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5399 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5400 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5401 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5402 }
9a799d71
AK		 5403 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5404 adapter->stats.bprc += bprc;
5405 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5406 if (hw->mac.type == ixgbe_mac_82598EB)
5407 adapter->stats.mprc -= bprc;
9a799d71
AK		 5408 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5409 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5410 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5411 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5412 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5413 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5414 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5415 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5416 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5417 adapter->stats.lxontxc += lxon;
5418 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5419 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5420 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5421 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5422 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5423 /*
5424 * 82598 errata - tx of flow control packets is included in tx counters
5425 */
5426 xon_off_tot = lxon + lxoff;
5427 adapter->stats.gptc -= xon_off_tot;
5428 adapter->stats.mptc -= xon_off_tot;
5429 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5430 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5431 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5432 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5433 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5434 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5435 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5436 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5437 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5438 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5439 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5440 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5441 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5442
5443 /* Fill out the OS statistics structure */
2d86f139 5444 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5445
5446 /* Rx Errors */
2d86f139 5447 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5448 adapter->stats.rlec;
2d86f139
AK		 5449 netdev->stats.rx_dropped = 0;
5450 netdev->stats.rx_length_errors = adapter->stats.rlec;
5451 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5452 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5453}
5454
5455/**
5456 * ixgbe_watchdog - Timer Call-back
5457 * @data: pointer to adapter cast into an unsigned long
5458 **/
5459static void ixgbe_watchdog(unsigned long data)
5460{
5461 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5462 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5463 u64 eics = 0;
5464 int i;
cf8280ee 5465
fe49f04a
AD		 5466 /*
5467 * Do the watchdog outside of interrupt context due to the lovely
5468 * delays that some of the newer hardware requires
5469 */
22d5a71b 5470
fe49f04a
AD		 5471 if (test_bit(__IXGBE_DOWN, &adapter->state))
5472 goto watchdog_short_circuit;
22d5a71b 5473
fe49f04a
AD		 5474 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5475 /*
5476 * for legacy and MSI interrupts don't set any bits
5477 * that are enabled for EIAM, because this operation
5478 * would set *both* EIMS and EICS for any bit in EIAM
5479 */
5480 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5481 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5482 goto watchdog_reschedule;
5483 }
5484
5485 /* get one bit for every active tx/rx interrupt vector */
5486 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5487 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5488 if (qv->rxr_count || qv->txr_count)
5489 eics |= ((u64)1 << i);
cf8280ee 5490 }
9a799d71 5491
fe49f04a
AD		 5492 /* Cause software interrupt to ensure rx rings are cleaned */
5493 ixgbe_irq_rearm_queues(adapter, eics);
5494
5495watchdog_reschedule:
5496 /* Reset the timer */
5497 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5498
5499watchdog_short_circuit:
cf8280ee
JB		 5500 schedule_work(&adapter->watchdog_task);
5501}
5502
e8e26350
PW		 5503/**
5504 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5505 * @work: pointer to work_struct containing our data
5506 **/
5507static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5508{
5509 struct ixgbe_adapter *adapter = container_of(work,
5510 struct ixgbe_adapter,
5511 multispeed_fiber_task);
5512 struct ixgbe_hw *hw = &adapter->hw;
5513 u32 autoneg;
8620a103 5514 bool negotiation;
e8e26350
PW		 5515
5516 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5517 autoneg = hw->phy.autoneg_advertised;
5518 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5519 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5520 hw->mac.autotry_restart = false;
8620a103
MC		 5521 if (hw->mac.ops.setup_link)
5522 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5523 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5524 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5525}
5526
5527/**
5528 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5529 * @work: pointer to work_struct containing our data
5530 **/
5531static void ixgbe_sfp_config_module_task(struct work_struct *work)
5532{
5533 struct ixgbe_adapter *adapter = container_of(work,
5534 struct ixgbe_adapter,
5535 sfp_config_module_task);
5536 struct ixgbe_hw *hw = &adapter->hw;
5537 u32 err;
5538
5539 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5540
5541 /* Time for electrical oscillations to settle down */
5542 msleep(100);
e8e26350 5543 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5544
e8e26350 5545 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5546 e_dev_err("failed to initialize because an unsupported SFP+ "
5547 "module type was detected.\n");
5548 e_dev_err("Reload the driver after installing a supported "
5549 "module.\n");
63d6e1d8 5550 unregister_netdev(adapter->netdev);
e8e26350
PW		 5551 return;
5552 }
5553 hw->mac.ops.setup_sfp(hw);
5554
8d1c3c07 5555 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5556 /* This will also work for DA Twinax connections */
5557 schedule_work(&adapter->multispeed_fiber_task);
5558 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5559}
5560
c4cf55e5
PWJ		 5561/**
5562 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5563 * @work: pointer to work_struct containing our data
5564 **/
5565static void ixgbe_fdir_reinit_task(struct work_struct *work)
5566{
5567 struct ixgbe_adapter *adapter = container_of(work,
5568 struct ixgbe_adapter,
5569 fdir_reinit_task);
5570 struct ixgbe_hw *hw = &adapter->hw;
5571 int i;
5572
5573 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5574 for (i = 0; i < adapter->num_tx_queues; i++)
5575 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5576 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5577 } else {
396e799c 5578 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5579 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5580 }
5581 /* Done FDIR Re-initialization, enable transmits */
5582 netif_tx_start_all_queues(adapter->netdev);
5583}
5584
10eec955
JF		 5585static DEFINE_MUTEX(ixgbe_watchdog_lock);
5586
cf8280ee 5587/**
69888674
AD		 5588 * ixgbe_watchdog_task - worker thread to bring link up
5589 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5590 **/
5591static void ixgbe_watchdog_task(struct work_struct *work)
5592{
5593 struct ixgbe_adapter *adapter = container_of(work,
5594 struct ixgbe_adapter,
5595 watchdog_task);
5596 struct net_device *netdev = adapter->netdev;
5597 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5598 u32 link_speed;
5599 bool link_up;
bc59fcda
NS		 5600 int i;
5601 struct ixgbe_ring *tx_ring;
5602 int some_tx_pending = 0;
cf8280ee 5603
10eec955
JF		 5604 mutex_lock(&ixgbe_watchdog_lock);
5605
5606 link_up = adapter->link_up;
5607 link_speed = adapter->link_speed;
cf8280ee
JB		 5608
5609 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5610 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5611 if (link_up) {
5612#ifdef CONFIG_DCB
5613 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5614 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5615 hw->mac.ops.fc_enable(hw, i);
264857b8 5616 } else {
620fa036 5617 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5618 }
5619#else
620fa036 5620 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5621#endif
5622 }
5623
cf8280ee
JB		 5624 if (link_up ||
5625 time_after(jiffies, (adapter->link_check_timeout +
5626 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5627 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5628 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5629 }
5630 adapter->link_up = link_up;
5631 adapter->link_speed = link_speed;
5632 }
9a799d71
AK		 5633
5634 if (link_up) {
5635 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5636 bool flow_rx, flow_tx;
5637
5638 if (hw->mac.type == ixgbe_mac_82599EB) {
5639 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5640 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5641 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5642 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5643 } else {
5644 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5645 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5646 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5647 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5648 }
5649
396e799c 5650 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5651 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5652 "10 Gbps" :
5653 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5654 "1 Gbps" : "unknown speed")),
e8e26350 5655 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5656 (flow_rx ? "RX" :
5657 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5658
5659 netif_carrier_on(netdev);
9a799d71
AK		 5660 } else {
5661 /* Force detection of hung controller */
5662 adapter->detect_tx_hung = true;
5663 }
5664 } else {
cf8280ee
JB		 5665 adapter->link_up = false;
5666 adapter->link_speed = 0;
9a799d71 5667 if (netif_carrier_ok(netdev)) {
396e799c 5668 e_info(drv, "NIC Link is Down\n");
9a799d71 5669 netif_carrier_off(netdev);
9a799d71
AK		 5670 }
5671 }
5672
bc59fcda
NS		 5673 if (!netif_carrier_ok(netdev)) {
5674 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5675 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5676 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5677 some_tx_pending = 1;
5678 break;
5679 }
5680 }
5681
5682 if (some_tx_pending) {
5683 /* We've lost link, so the controller stops DMA,
5684 * but we've got queued Tx work that's never going
5685 * to get done, so reset controller to flush Tx.
5686 * (Do the reset outside of interrupt context).
5687 */
5688 schedule_work(&adapter->reset_task);
5689 }
5690 }
5691
9a799d71 5692 ixgbe_update_stats(adapter);
10eec955 5693 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5694}
5695
9a799d71 5696static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5697 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5698 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5699{
5700 struct ixgbe_adv_tx_context_desc *context_desc;
5701 unsigned int i;
5702 int err;
5703 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5704 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5705 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5706
5707 if (skb_is_gso(skb)) {
5708 if (skb_header_cloned(skb)) {
5709 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5710 if (err)
5711 return err;
5712 }
5713 l4len = tcp_hdrlen(skb);
5714 *hdr_len += l4len;
5715
8327d000 5716 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5717 struct iphdr *iph = ip_hdr(skb);
5718 iph->tot_len = 0;
5719 iph->check = 0;
5720 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5721 iph->daddr, 0,
5722 IPPROTO_TCP,
5723 0);
8e1e8a47 5724 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5725 ipv6_hdr(skb)->payload_len = 0;
5726 tcp_hdr(skb)->check =
5727 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5728 &ipv6_hdr(skb)->daddr,
5729 0, IPPROTO_TCP, 0);
9a799d71
AK		 5730 }
5731
5732 i = tx_ring->next_to_use;
5733
5734 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5735 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5736
5737 /* VLAN MACLEN IPLEN */
5738 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5739 vlan_macip_lens |=
5740 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5741 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5742 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5743 *hdr_len += skb_network_offset(skb);
5744 vlan_macip_lens |=
5745 (skb_transport_header(skb) - skb_network_header(skb));
5746 *hdr_len +=
5747 (skb_transport_header(skb) - skb_network_header(skb));
5748 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5749 context_desc->seqnum_seed = 0;
5750
5751 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5752 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5753 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5754
8327d000 5755 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5756 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5757 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5758 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5759
5760 /* MSS L4LEN IDX */
9f8cdf4f 5761 mss_l4len_idx =
9a799d71
AK		 5762 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5763 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5764 /* use index 1 for TSO */
5765 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5766 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5767
5768 tx_buffer_info->time_stamp = jiffies;
5769 tx_buffer_info->next_to_watch = i;
5770
5771 i++;
5772 if (i == tx_ring->count)
5773 i = 0;
5774 tx_ring->next_to_use = i;
5775
5776 return true;
5777 }
5778 return false;
5779}
5780
5781static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5782 struct ixgbe_ring *tx_ring,
5783 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5784{
5785 struct ixgbe_adv_tx_context_desc *context_desc;
5786 unsigned int i;
5787 struct ixgbe_tx_buffer *tx_buffer_info;
5788 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5789
5790 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5791 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5792 i = tx_ring->next_to_use;
5793 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5794 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5795
5796 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5797 vlan_macip_lens |=
5798 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5799 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5800 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5801 if (skb->ip_summed == CHECKSUM_PARTIAL)
5802 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5803 skb_network_header(skb));
9a799d71
AK		 5804
5805 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5806 context_desc->seqnum_seed = 0;
5807
5808 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5809 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5810
5811 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5812 __be16 protocol;
5813
5814 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5815 const struct vlan_ethhdr *vhdr =
5816 (const struct vlan_ethhdr *)skb->data;
5817
5818 protocol = vhdr->h_vlan_encapsulated_proto;
5819 } else {
5820 protocol = skb->protocol;
5821 }
5822
5823 switch (protocol) {
09640e63 5824 case cpu_to_be16(ETH_P_IP):
9a799d71 5825 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5826 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5827 type_tucmd_mlhl |=
b4617240 5828 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5829 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5830 type_tucmd_mlhl |=
5831 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5832 break;
09640e63 5833 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5834 /* XXX what about other V6 headers?? */
5835 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5836 type_tucmd_mlhl |=
b4617240 5837 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5838 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5839 type_tucmd_mlhl |=
5840 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5841 break;
41825d71
AK		 5842 default:
5843 if (unlikely(net_ratelimit())) {
396e799c
ET		 5844 e_warn(probe, "partial checksum "
5845 "but proto=%x!\n",
5846 skb->protocol);
41825d71
AK		 5847 }
5848 break;
5849 }
9a799d71
AK		 5850 }
5851
5852 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5853 /* use index zero for tx checksum offload */
9a799d71
AK		 5854 context_desc->mss_l4len_idx = 0;
5855
5856 tx_buffer_info->time_stamp = jiffies;
5857 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5858
9a799d71
AK		 5859 i++;
5860 if (i == tx_ring->count)
5861 i = 0;
5862 tx_ring->next_to_use = i;
5863
5864 return true;
5865 }
9f8cdf4f 5866
9a799d71
AK		 5867 return false;
5868}
5869
5870static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5871 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5872 struct sk_buff *skb, u32 tx_flags,
5873 unsigned int first)
9a799d71 5874{
e5a43549 5875 struct pci_dev *pdev = adapter->pdev;
9a799d71 5876 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5877 unsigned int len;
5878 unsigned int total = skb->len;
9a799d71
AK		 5879 unsigned int offset = 0, size, count = 0, i;
5880 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5881 unsigned int f;
9a799d71
AK		 5882
5883 i = tx_ring->next_to_use;
5884
eacd73f7
YZ		 5885 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5886 /* excluding fcoe_crc_eof for FCoE */
5887 total -= sizeof(struct fcoe_crc_eof);
5888
5889 len = min(skb_headlen(skb), total);
9a799d71
AK		 5890 while (len) {
5891 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5892 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5893
5894 tx_buffer_info->length = size;
e5a43549 5895 tx_buffer_info->mapped_as_page = false;
1b507730 5896 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5897 skb->data + offset,
1b507730
NN		 5898 size, DMA_TO_DEVICE);
5899 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5900 goto dma_error;
9a799d71
AK		 5901 tx_buffer_info->time_stamp = jiffies;
5902 tx_buffer_info->next_to_watch = i;
5903
5904 len -= size;
eacd73f7 5905 total -= size;
9a799d71
AK		 5906 offset += size;
5907 count++;
44df32c5
AD		 5908
5909 if (len) {
5910 i++;
5911 if (i == tx_ring->count)
5912 i = 0;
5913 }
9a799d71
AK		 5914 }
5915
5916 for (f = 0; f < nr_frags; f++) {
5917 struct skb_frag_struct *frag;
5918
5919 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5920 len = min((unsigned int)frag->size, total);
e5a43549 5921 offset = frag->page_offset;
9a799d71
AK		 5922
5923 while (len) {
44df32c5
AD		 5924 i++;
5925 if (i == tx_ring->count)
5926 i = 0;
5927
9a799d71
AK		 5928 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5929 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5930
5931 tx_buffer_info->length = size;
1b507730 5932 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5933 frag->page,
5934 offset, size,
1b507730 5935 DMA_TO_DEVICE);
e5a43549 5936 tx_buffer_info->mapped_as_page = true;
1b507730 5937 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5938 goto dma_error;
9a799d71
AK		 5939 tx_buffer_info->time_stamp = jiffies;
5940 tx_buffer_info->next_to_watch = i;
5941
5942 len -= size;
eacd73f7 5943 total -= size;
9a799d71
AK		 5944 offset += size;
5945 count++;
9a799d71 5946 }
eacd73f7
YZ		 5947 if (total == 0)
5948 break;
9a799d71 5949 }
44df32c5 5950
9a799d71
AK		 5951 tx_ring->tx_buffer_info[i].skb = skb;
5952 tx_ring->tx_buffer_info[first].next_to_watch = i;
5953
e5a43549
AD		 5954 return count;
5955
5956dma_error:
849c4542 5957 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 5958
5959 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5960 tx_buffer_info->dma = 0;
5961 tx_buffer_info->time_stamp = 0;
5962 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5963 if (count)
5964 count--;
e5a43549
AD		 5965
5966 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5967 while (count--) {
5968 if (i==0)
e5a43549 5969 i += tx_ring->count;
c1fa347f 5970 i--;
e5a43549
AD		 5971 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5972 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5973 }
5974
e44d38e1 5975 return 0;
9a799d71
AK		 5976}
5977
5978static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5979 struct ixgbe_ring *tx_ring,
5980 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5981{
5982 union ixgbe_adv_tx_desc *tx_desc = NULL;
5983 struct ixgbe_tx_buffer *tx_buffer_info;
5984 u32 olinfo_status = 0, cmd_type_len = 0;
5985 unsigned int i;
5986 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5987
5988 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5989
5990 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5991
5992 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5993 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5994
5995 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5996 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5997
5998 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5999 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6000
4eeae6fd
PW		 6001 /* use index 1 context for tso */
6002 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6003 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6004 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 6005 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6006
6007 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6008 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6009 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6010
eacd73f7
YZ		 6011 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6012 olinfo_status |= IXGBE_ADVTXD_CC;
6013 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6014 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6015 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6016 }
6017
9a799d71
AK		 6018 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6019
6020 i = tx_ring->next_to_use;
6021 while (count--) {
6022 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6023 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6024 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6025 tx_desc->read.cmd_type_len =
b4617240 6026 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6027 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6028 i++;
6029 if (i == tx_ring->count)
6030 i = 0;
6031 }
6032
6033 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6034
6035 /*
6036 * Force memory writes to complete before letting h/w
6037 * know there are new descriptors to fetch. (Only
6038 * applicable for weak-ordered memory model archs,
6039 * such as IA-64).
6040 */
6041 wmb();
6042
6043 tx_ring->next_to_use = i;
6044 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6045}
6046
c4cf55e5
PWJ		 6047static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6048 int queue, u32 tx_flags)
6049{
c4cf55e5
PWJ		 6050 struct ixgbe_atr_input atr_input;
6051 struct tcphdr *th;
c4cf55e5
PWJ		 6052 struct iphdr *iph = ip_hdr(skb);
6053 struct ethhdr *eth = (struct ethhdr *)skb->data;
6054 u16 vlan_id, src_port, dst_port, flex_bytes;
6055 u32 src_ipv4_addr, dst_ipv4_addr;
6056 u8 l4type = 0;
6057
d3ead241
GG		 6058 /* Right now, we support IPv4 only */
6059 if (skb->protocol != htons(ETH_P_IP))
6060 return;
c4cf55e5
PWJ		 6061 /* check if we're UDP or TCP */
6062 if (iph->protocol == IPPROTO_TCP) {
6063 th = tcp_hdr(skb);
6064 src_port = th->source;
6065 dst_port = th->dest;
6066 l4type |= IXGBE_ATR_L4TYPE_TCP;
6067 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6068 } else {
6069 /* Unsupported L4 header, just bail here */
6070 return;
6071 }
6072
6073 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6074
6075 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6076 IXGBE_TX_FLAGS_VLAN_SHIFT;
6077 src_ipv4_addr = iph->saddr;
6078 dst_ipv4_addr = iph->daddr;
6079 flex_bytes = eth->h_proto;
6080
6081 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6082 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6083 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6084 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6085 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6086 /* src and dst are inverted, think how the receiver sees them */
6087 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6088 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6089
6090 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6091 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6092}
6093
e092be60 6094static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6095 struct ixgbe_ring *tx_ring, int size)
e092be60 6096{
30eba97a 6097 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6098 /* Herbert's original patch had:
6099 * smp_mb__after_netif_stop_queue();
6100 * but since that doesn't exist yet, just open code it. */
6101 smp_mb();
6102
6103 /* We need to check again in a case another CPU has just
6104 * made room available. */
6105 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6106 return -EBUSY;
6107
6108 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6109 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6110 ++tx_ring->restart_queue;
e092be60
AV		 6111 return 0;
6112}
6113
6114static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6115 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6116{
6117 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6118 return 0;
6119 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6120}
6121
09a3b1f8
SH		 6122static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6123{
6124 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6125 int txq = smp_processor_id();
09a3b1f8 6126
56075a98
JF		 6127#ifdef IXGBE_FCOE
6128 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6129 (skb->protocol == htons(ETH_P_FIP))) {
6130 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6131 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6132 txq += adapter->ring_feature[RING_F_FCOE].mask;
6133 return txq;
4bc091d8 6134#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6135 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6136 txq = adapter->fcoe.up;
6137 return txq;
4bc091d8 6138#endif
56075a98
JF		 6139 }
6140 }
6141#endif
6142
fdd3d631
KK		 6143 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6144 while (unlikely(txq >= dev->real_num_tx_queues))
6145 txq -= dev->real_num_tx_queues;
5f715823 6146 return txq;
fdd3d631 6147 }
c4cf55e5 6148
2ea186ae
JF		 6149 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6150 if (skb->priority == TC_PRIO_CONTROL)
6151 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6152 else
6153 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6154 >> 13;
6155 return txq;
6156 }
09a3b1f8
SH		 6157
6158 return skb_tx_hash(dev, skb);
6159}
6160
3b29a56d
SH		 6161static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6162 struct net_device *netdev)
9a799d71
AK		 6163{
6164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6165 struct ixgbe_ring *tx_ring;
60d51134 6166 struct netdev_queue *txq;
9a799d71
AK		 6167 unsigned int first;
6168 unsigned int tx_flags = 0;
30eba97a 6169 u8 hdr_len = 0;
5f715823 6170 int tso;
9a799d71
AK		 6171 int count = 0;
6172 unsigned int f;
9f8cdf4f 6173
9f8cdf4f
JB		 6174 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6175 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6176 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6177 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6178 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6179 }
6180 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6181 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6182 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6183 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6184 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6185 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6186 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6187 }
eacd73f7 6188
4a0b9ca0 6189 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 6190
09ad1cc0 6191#ifdef IXGBE_FCOE
56075a98
JF		 6192 /* for FCoE with DCB, we force the priority to what
6193 * was specified by the switch */
6194 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6195 (skb->protocol == htons(ETH_P_FCOE) ||
6196 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6197#ifdef CONFIG_IXGBE_DCB
6198 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6199 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6200 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6201 tx_flags |= ((adapter->fcoe.up << 13)
6202 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6203 }
6204#endif
ca77cd59
RL		 6205 /* flag for FCoE offloads */
6206 if (skb->protocol == htons(ETH_P_FCOE))
6207 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6208 }
ca77cd59
RL		 6209#endif
6210
eacd73f7 6211 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6212 if (skb_is_gso(skb) ||
6213 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6214 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6215 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6216 count++;
6217
9f8cdf4f
JB		 6218 count += TXD_USE_COUNT(skb_headlen(skb));
6219 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6220 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6221
e092be60 6222 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6223 adapter->tx_busy++;
9a799d71
AK		 6224 return NETDEV_TX_BUSY;
6225 }
9a799d71 6226
9a799d71 6227 first = tx_ring->next_to_use;
eacd73f7
YZ		 6228 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6229#ifdef IXGBE_FCOE
6230 /* setup tx offload for FCoE */
6231 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6232 if (tso < 0) {
6233 dev_kfree_skb_any(skb);
6234 return NETDEV_TX_OK;
6235 }
6236 if (tso)
6237 tx_flags |= IXGBE_TX_FLAGS_FSO;
6238#endif /* IXGBE_FCOE */
6239 } else {
6240 if (skb->protocol == htons(ETH_P_IP))
6241 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6242 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6243 if (tso < 0) {
6244 dev_kfree_skb_any(skb);
6245 return NETDEV_TX_OK;
6246 }
9a799d71 6247
eacd73f7
YZ		 6248 if (tso)
6249 tx_flags |= IXGBE_TX_FLAGS_TSO;
6250 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6251 (skb->ip_summed == CHECKSUM_PARTIAL))
6252 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6253 }
9a799d71 6254
eacd73f7 6255 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6256 if (count) {
c4cf55e5
PWJ		 6257 /* add the ATR filter if ATR is on */
6258 if (tx_ring->atr_sample_rate) {
6259 ++tx_ring->atr_count;
6260 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6261 test_bit(__IXGBE_FDIR_INIT_DONE,
6262 &tx_ring->reinit_state)) {
6263 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6264 tx_flags);
6265 tx_ring->atr_count = 0;
6266 }
6267 }
60d51134
ED		 6268 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6269 txq->tx_bytes += skb->len;
6270 txq->tx_packets++;
44df32c5
AD		 6271 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6272 hdr_len);
44df32c5 6273 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6274
44df32c5
AD		 6275 } else {
6276 dev_kfree_skb_any(skb);
6277 tx_ring->tx_buffer_info[first].time_stamp = 0;
6278 tx_ring->next_to_use = first;
6279 }
9a799d71
AK		 6280
6281 return NETDEV_TX_OK;
6282}
6283
9a799d71
AK		 6284/**
6285 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6286 * @netdev: network interface device structure
6287 * @p: pointer to an address structure
6288 *
6289 * Returns 0 on success, negative on failure
6290 **/
6291static int ixgbe_set_mac(struct net_device *netdev, void *p)
6292{
6293 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6294 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6295 struct sockaddr *addr = p;
6296
6297 if (!is_valid_ether_addr(addr->sa_data))
6298 return -EADDRNOTAVAIL;
6299
6300 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6301 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6302
1cdd1ec8
GR		 6303 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6304 IXGBE_RAH_AV);
9a799d71
AK		 6305
6306 return 0;
6307}
6308
6b73e10d
BH		 6309static int
6310ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6311{
6312 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6313 struct ixgbe_hw *hw = &adapter->hw;
6314 u16 value;
6315 int rc;
6316
6317 if (prtad != hw->phy.mdio.prtad)
6318 return -EINVAL;
6319 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6320 if (!rc)
6321 rc = value;
6322 return rc;
6323}
6324
6325static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6326 u16 addr, u16 value)
6327{
6328 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6329 struct ixgbe_hw *hw = &adapter->hw;
6330
6331 if (prtad != hw->phy.mdio.prtad)
6332 return -EINVAL;
6333 return hw->phy.ops.write_reg(hw, addr, devad, value);
6334}
6335
6336static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6337{
6338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6339
6340 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6341}
6342
0365e6e4
PW		 6343/**
6344 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6345 * netdev->dev_addrs
0365e6e4
PW		 6346 * @netdev: network interface device structure
6347 *
6348 * Returns non-zero on failure
6349 **/
6350static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6351{
6352 int err = 0;
6353 struct ixgbe_adapter *adapter = netdev_priv(dev);
6354 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6355
6356 if (is_valid_ether_addr(mac->san_addr)) {
6357 rtnl_lock();
6358 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6359 rtnl_unlock();
6360 }
6361 return err;
6362}
6363
6364/**
6365 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6366 * netdev->dev_addrs
0365e6e4
PW		 6367 * @netdev: network interface device structure
6368 *
6369 * Returns non-zero on failure
6370 **/
6371static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6372{
6373 int err = 0;
6374 struct ixgbe_adapter *adapter = netdev_priv(dev);
6375 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6376
6377 if (is_valid_ether_addr(mac->san_addr)) {
6378 rtnl_lock();
6379 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6380 rtnl_unlock();
6381 }
6382 return err;
6383}
6384
9a799d71
AK		 6385#ifdef CONFIG_NET_POLL_CONTROLLER
6386/*
6387 * Polling 'interrupt' - used by things like netconsole to send skbs
6388 * without having to re-enable interrupts. It's not called while
6389 * the interrupt routine is executing.
6390 */
6391static void ixgbe_netpoll(struct net_device *netdev)
6392{
6393 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6394 int i;
9a799d71 6395
1a647bd2
AD		 6396 /* if interface is down do nothing */
6397 if (test_bit(__IXGBE_DOWN, &adapter->state))
6398 return;
6399
9a799d71 6400 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6401 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6402 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6403 for (i = 0; i < num_q_vectors; i++) {
6404 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6405 ixgbe_msix_clean_many(0, q_vector);
6406 }
6407 } else {
6408 ixgbe_intr(adapter->pdev->irq, netdev);
6409 }
9a799d71 6410 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6411}
6412#endif
6413
0edc3527
SH		 6414static const struct net_device_ops ixgbe_netdev_ops = {
6415 .ndo_open = ixgbe_open,
6416 .ndo_stop = ixgbe_close,
00829823 6417 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6418 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6419 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6420 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6421 .ndo_validate_addr = eth_validate_addr,
6422 .ndo_set_mac_address = ixgbe_set_mac,
6423 .ndo_change_mtu = ixgbe_change_mtu,
6424 .ndo_tx_timeout = ixgbe_tx_timeout,
6425 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6426 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6427 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6428 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6429 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6430 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6431 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6432 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6433#ifdef CONFIG_NET_POLL_CONTROLLER
6434 .ndo_poll_controller = ixgbe_netpoll,
6435#endif
332d4a7d
YZ		 6436#ifdef IXGBE_FCOE
6437 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6438 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6439 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6440 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6441 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6442#endif /* IXGBE_FCOE */
0edc3527
SH		 6443};
6444
1cdd1ec8
GR		 6445static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6446 const struct ixgbe_info *ii)
6447{
6448#ifdef CONFIG_PCI_IOV
6449 struct ixgbe_hw *hw = &adapter->hw;
6450 int err;
6451
6452 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6453 return;
6454
6455 /* The 82599 supports up to 64 VFs per physical function
6456 * but this implementation limits allocation to 63 so that
6457 * basic networking resources are still available to the
6458 * physical function
6459 */
6460 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6461 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6462 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6463 if (err) {
396e799c 6464 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6465 goto err_novfs;
6466 }
6467 /* If call to enable VFs succeeded then allocate memory
6468 * for per VF control structures.
6469 */
6470 adapter->vfinfo =
6471 kcalloc(adapter->num_vfs,
6472 sizeof(struct vf_data_storage), GFP_KERNEL);
6473 if (adapter->vfinfo) {
6474 /* Now that we're sure SR-IOV is enabled
6475 * and memory allocated set up the mailbox parameters
6476 */
6477 ixgbe_init_mbx_params_pf(hw);
6478 memcpy(&hw->mbx.ops, ii->mbx_ops,
6479 sizeof(hw->mbx.ops));
6480
6481 /* Disable RSC when in SR-IOV mode */
6482 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6483 IXGBE_FLAG2_RSC_ENABLED);
6484 return;
6485 }
6486
6487 /* Oh oh */
396e799c
ET		 6488 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6489 "SRIOV disabled\n");
1cdd1ec8
GR		 6490 pci_disable_sriov(adapter->pdev);
6491
6492err_novfs:
6493 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6494 adapter->num_vfs = 0;
6495#endif /* CONFIG_PCI_IOV */
6496}
6497
9a799d71
AK		 6498/**
6499 * ixgbe_probe - Device Initialization Routine
6500 * @pdev: PCI device information struct
6501 * @ent: entry in ixgbe_pci_tbl
6502 *
6503 * Returns 0 on success, negative on failure
6504 *
6505 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6506 * The OS initialization, configuring of the adapter private structure,
6507 * and a hardware reset occur.
6508 **/
6509static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6510 const struct pci_device_id *ent)
9a799d71
AK		 6511{
6512 struct net_device *netdev;
6513 struct ixgbe_adapter *adapter = NULL;
6514 struct ixgbe_hw *hw;
6515 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6516 static int cards_found;
6517 int i, err, pci_using_dac;
c85a2618 6518 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6519#ifdef IXGBE_FCOE
6520 u16 device_caps;
6521#endif
c44ade9e 6522 u32 part_num, eec;
9a799d71 6523
bded64a7
AG		 6524 /* Catch broken hardware that put the wrong VF device ID in
6525 * the PCIe SR-IOV capability.
6526 */
6527 if (pdev->is_virtfn) {
6528 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6529 pci_name(pdev), pdev->vendor, pdev->device);
6530 return -EINVAL;
6531 }
6532
9ce77666 6533 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6534 if (err)
6535 return err;
6536
1b507730
NN		 6537 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6538 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6539 pci_using_dac = 1;
6540 } else {
1b507730 6541 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6542 if (err) {
1b507730
NN		 6543 err = dma_set_coherent_mask(&pdev->dev,
6544 DMA_BIT_MASK(32));
9a799d71 6545 if (err) {
b8bc0421
DC		 6546 dev_err(&pdev->dev,
6547 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6548 goto err_dma;
6549 }
6550 }
6551 pci_using_dac = 0;
6552 }
6553
9ce77666 6554 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6555 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6556 if (err) {
b8bc0421
DC		 6557 dev_err(&pdev->dev,
6558 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6559 goto err_pci_reg;
6560 }
6561
19d5afd4 6562 pci_enable_pcie_error_reporting(pdev);
6fabd715 6563
9a799d71 6564 pci_set_master(pdev);
fb3b27bc 6565 pci_save_state(pdev);
9a799d71 6566
c85a2618
JF		 6567 if (ii->mac == ixgbe_mac_82598EB)
6568 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6569 else
6570 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6571
6572 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6573#ifdef IXGBE_FCOE
6574 indices += min_t(unsigned int, num_possible_cpus(),
6575 IXGBE_MAX_FCOE_INDICES);
6576#endif
c85a2618 6577 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6578 if (!netdev) {
6579 err = -ENOMEM;
6580 goto err_alloc_etherdev;
6581 }
6582
9a799d71
AK		 6583 SET_NETDEV_DEV(netdev, &pdev->dev);
6584
6585 pci_set_drvdata(pdev, netdev);
6586 adapter = netdev_priv(netdev);
6587
6588 adapter->netdev = netdev;
6589 adapter->pdev = pdev;
6590 hw = &adapter->hw;
6591 hw->back = adapter;
6592 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6593
05857980
JK		 6594 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6595 pci_resource_len(pdev, 0));
9a799d71
AK		 6596 if (!hw->hw_addr) {
6597 err = -EIO;
6598 goto err_ioremap;
6599 }
6600
6601 for (i = 1; i <= 5; i++) {
6602 if (pci_resource_len(pdev, i) == 0)
6603 continue;
6604 }
6605
0edc3527 6606 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6607 ixgbe_set_ethtool_ops(netdev);
9a799d71 6608 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6609 strcpy(netdev->name, pci_name(pdev));
6610
9a799d71
AK		 6611 adapter->bd_number = cards_found;
6612
9a799d71
AK		 6613 /* Setup hw api */
6614 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6615 hw->mac.type = ii->mac;
9a799d71 6616
c44ade9e
JB		 6617 /* EEPROM */
6618 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6619 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6620 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6621 if (!(eec & (1 << 8)))
6622 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6623
6624 /* PHY */
6625 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6626 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6627 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6628 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6629 hw->phy.mdio.mmds = 0;
6630 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6631 hw->phy.mdio.dev = netdev;
6632 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6633 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6634
6635 /* set up this timer and work struct before calling get_invariants
6636 * which might start the timer
6637 */
6638 init_timer(&adapter->sfp_timer);
6639 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6640 adapter->sfp_timer.data = (unsigned long) adapter;
6641
6642 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6643
e8e26350
PW		 6644 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6645 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6646
6647 /* a new SFP+ module arrival, called from GPI SDP2 context */
6648 INIT_WORK(&adapter->sfp_config_module_task,
6649 ixgbe_sfp_config_module_task);
6650
8ca783ab 6651 ii->get_invariants(hw);
9a799d71
AK		 6652
6653 /* setup the private structure */
6654 err = ixgbe_sw_init(adapter);
6655 if (err)
6656 goto err_sw_init;
6657
e86bff0e
DS		 6658 /* Make it possible the adapter to be woken up via WOL */
6659 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6661
bf069c97
DS		 6662 /*
6663 * If there is a fan on this device and it has failed log the
6664 * failure.
6665 */
6666 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6667 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6668 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6669 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6670 }
6671
c44ade9e 6672 /* reset_hw fills in the perm_addr as well */
119fc60a 6673 hw->phy.reset_if_overtemp = true;
c44ade9e 6674 err = hw->mac.ops.reset_hw(hw);
119fc60a 6675 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6676 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6677 hw->mac.type == ixgbe_mac_82598EB) {
6678 /*
6679 * Start a kernel thread to watch for a module to arrive.
6680 * Only do this for 82598, since 82599 will generate
6681 * interrupts on module arrival.
6682 */
6683 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6684 mod_timer(&adapter->sfp_timer,
6685 round_jiffies(jiffies + (2 * HZ)));
6686 err = 0;
6687 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6688 e_dev_err("failed to initialize because an unsupported SFP+ "
6689 "module type was detected.\n");
6690 e_dev_err("Reload the driver after installing a supported "
6691 "module.\n");
04f165ef
PW		 6692 goto err_sw_init;
6693 } else if (err) {
849c4542 6694 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6695 goto err_sw_init;
6696 }
6697
1cdd1ec8
GR		 6698 ixgbe_probe_vf(adapter, ii);
6699
396e799c 6700 netdev->features = NETIF_F_SG |
b4617240
PW		 6701 NETIF_F_IP_CSUM |
6702 NETIF_F_HW_VLAN_TX |
6703 NETIF_F_HW_VLAN_RX |
6704 NETIF_F_HW_VLAN_FILTER;
9a799d71 6705
e9990a9c 6706 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6707 netdev->features |= NETIF_F_TSO;
9a799d71 6708 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6709 netdev->features |= NETIF_F_GRO;
ad31c402 6710
45a5ead0
JB		 6711 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6712 netdev->features |= NETIF_F_SCTP_CSUM;
6713
ad31c402
JK		 6714 netdev->vlan_features |= NETIF_F_TSO;
6715 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6716 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6717 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6718 netdev->vlan_features |= NETIF_F_SG;
6719
1cdd1ec8
GR		 6720 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6721 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6722 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6723 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6724 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6725
7a6b6f51 6726#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6727 netdev->dcbnl_ops = &dcbnl_ops;
6728#endif
6729
eacd73f7 6730#ifdef IXGBE_FCOE
0d551589 6731 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6732 if (hw->mac.ops.get_device_caps) {
6733 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6734 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6735 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6736 }
6737 }
5e09d7f6
YZ		 6738 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6739 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6740 netdev->vlan_features |= NETIF_F_FSO;
6741 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6742 }
eacd73f7 6743#endif /* IXGBE_FCOE */
9a799d71
AK		 6744 if (pci_using_dac)
6745 netdev->features |= NETIF_F_HIGHDMA;
6746
0c19d6af 6747 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6748 netdev->features |= NETIF_F_LRO;
6749
9a799d71 6750 /* make sure the EEPROM is good */
c44ade9e 6751 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6752 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6753 err = -EIO;
6754 goto err_eeprom;
6755 }
6756
6757 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6758 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6759
c44ade9e 6760 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6761 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6762 err = -EIO;
6763 goto err_eeprom;
6764 }
6765
61fac744
PW		 6766 /* power down the optics */
6767 if (hw->phy.multispeed_fiber)
6768 hw->mac.ops.disable_tx_laser(hw);
6769
9a799d71
AK		 6770 init_timer(&adapter->watchdog_timer);
6771 adapter->watchdog_timer.function = &ixgbe_watchdog;
6772 adapter->watchdog_timer.data = (unsigned long)adapter;
6773
6774 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6775 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6776
021230d4
AV		 6777 err = ixgbe_init_interrupt_scheme(adapter);
6778 if (err)
6779 goto err_sw_init;
9a799d71 6780
e8e26350
PW		 6781 switch (pdev->device) {
6782 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6783 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6784 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6785 break;
6786 default:
6787 adapter->wol = 0;
6788 break;
6789 }
e8e26350
PW		 6790 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6791
04f165ef
PW		 6792 /* pick up the PCI bus settings for reporting later */
6793 hw->mac.ops.get_bus_info(hw);
6794
9a799d71 6795 /* print bus type/speed/width info */
849c4542 6796 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6797 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6798 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6799 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6800 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6801 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6802 "Unknown"),
7c510e4b 6803 netdev->dev_addr);
c44ade9e 6804 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6805 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6806 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6807 "PBA No: %06x-%03x\n",
6808 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6809 (part_num >> 8), (part_num & 0xff));
e8e26350 6810 else
849c4542
ET		 6811 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6812 hw->mac.type, hw->phy.type,
6813 (part_num >> 8), (part_num & 0xff));
9a799d71 6814
e8e26350 6815 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6816 e_dev_warn("PCI-Express bandwidth available for this card is "
6817 "not sufficient for optimal performance.\n");
6818 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6819 "is required.\n");
0c254d86
AK		 6820 }
6821
34b0368c
PWJ		 6822 /* save off EEPROM version number */
6823 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6824
9a799d71 6825 /* reset the hardware with the new settings */
794caeb2 6826 err = hw->mac.ops.start_hw(hw);
c44ade9e 6827
794caeb2
PWJ		 6828 if (err == IXGBE_ERR_EEPROM_VERSION) {
6829 /* We are running on a pre-production device, log a warning */
849c4542
ET		 6830 e_dev_warn("This device is a pre-production adapter/LOM. "
6831 "Please be aware there may be issues associated "
6832 "with your hardware. If you are experiencing "
6833 "problems please contact your Intel or hardware "
6834 "representative who provided you with this "
6835 "hardware.\n");
794caeb2 6836 }
9a799d71
AK		 6837 strcpy(netdev->name, "eth%d");
6838 err = register_netdev(netdev);
6839 if (err)
6840 goto err_register;
6841
54386467
JB		 6842 /* carrier off reporting is important to ethtool even BEFORE open */
6843 netif_carrier_off(netdev);
6844
c4cf55e5
PWJ		 6845 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6846 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6847 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6848
119fc60a
MC		 6849 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6850 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
5dd2d332 6851#ifdef CONFIG_IXGBE_DCA
652f093f 6852 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6853 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6854 ixgbe_setup_dca(adapter);
6855 }
6856#endif
1cdd1ec8 6857 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 6858 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 6859 for (i = 0; i < adapter->num_vfs; i++)
6860 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6861 }
6862
0365e6e4
PW		 6863 /* add san mac addr to netdev */
6864 ixgbe_add_sanmac_netdev(netdev);
9a799d71 6865
849c4542 6866 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 6867 cards_found++;
6868 return 0;
6869
6870err_register:
5eba3699 6871 ixgbe_release_hw_control(adapter);
7a921c93 6872 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6873err_sw_init:
6874err_eeprom:
1cdd1ec8
GR		 6875 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6876 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6877 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6878 del_timer_sync(&adapter->sfp_timer);
6879 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6880 cancel_work_sync(&adapter->multispeed_fiber_task);
6881 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6882 iounmap(hw->hw_addr);
6883err_ioremap:
6884 free_netdev(netdev);
6885err_alloc_etherdev:
9ce77666 6886 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6887 IORESOURCE_MEM));
9a799d71
AK		 6888err_pci_reg:
6889err_dma:
6890 pci_disable_device(pdev);
6891 return err;
6892}
6893
6894/**
6895 * ixgbe_remove - Device Removal Routine
6896 * @pdev: PCI device information struct
6897 *
6898 * ixgbe_remove is called by the PCI subsystem to alert the driver
6899 * that it should release a PCI device. The could be caused by a
6900 * Hot-Plug event, or because the driver is going to be removed from
6901 * memory.
6902 **/
6903static void __devexit ixgbe_remove(struct pci_dev *pdev)
6904{
6905 struct net_device *netdev = pci_get_drvdata(pdev);
6906 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6907
6908 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6909 /* clear the module not found bit to make sure the worker won't
6910 * reschedule
6911 */
6912 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6913 del_timer_sync(&adapter->watchdog_timer);
6914
c4900be0
DS		 6915 del_timer_sync(&adapter->sfp_timer);
6916 cancel_work_sync(&adapter->watchdog_task);
6917 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6918 cancel_work_sync(&adapter->multispeed_fiber_task);
6919 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6920 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6921 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6922 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6923 flush_scheduled_work();
6924
5dd2d332 6925#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6926 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6927 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6928 dca_remove_requester(&pdev->dev);
6929 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6930 }
6931
6932#endif
332d4a7d
YZ		 6933#ifdef IXGBE_FCOE
6934 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6935 ixgbe_cleanup_fcoe(adapter);
6936
6937#endif /* IXGBE_FCOE */
0365e6e4
PW		 6938
6939 /* remove the added san mac */
6940 ixgbe_del_sanmac_netdev(netdev);
6941
c4900be0
DS		 6942 if (netdev->reg_state == NETREG_REGISTERED)
6943 unregister_netdev(netdev);
9a799d71 6944
1cdd1ec8
GR		 6945 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6946 ixgbe_disable_sriov(adapter);
6947
7a921c93 6948 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6949
021230d4 6950 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6951
6952 iounmap(adapter->hw.hw_addr);
9ce77666 6953 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6954 IORESOURCE_MEM));
9a799d71 6955
849c4542 6956 e_dev_info("complete\n");
021230d4 6957
9a799d71
AK		 6958 free_netdev(netdev);
6959
19d5afd4 6960 pci_disable_pcie_error_reporting(pdev);
6fabd715 6961
9a799d71
AK		 6962 pci_disable_device(pdev);
6963}
6964
6965/**
6966 * ixgbe_io_error_detected - called when PCI error is detected
6967 * @pdev: Pointer to PCI device
6968 * @state: The current pci connection state
6969 *
6970 * This function is called after a PCI bus error affecting
6971 * this device has been detected.
6972 */
6973static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6974 pci_channel_state_t state)
9a799d71
AK		 6975{
6976 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6977 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6978
6979 netif_device_detach(netdev);
6980
3044b8d1
BL		 6981 if (state == pci_channel_io_perm_failure)
6982 return PCI_ERS_RESULT_DISCONNECT;
6983
9a799d71
AK		 6984 if (netif_running(netdev))
6985 ixgbe_down(adapter);
6986 pci_disable_device(pdev);
6987
b4617240 6988 /* Request a slot reset. */
9a799d71
AK		 6989 return PCI_ERS_RESULT_NEED_RESET;
6990}
6991
6992/**
6993 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6994 * @pdev: Pointer to PCI device
6995 *
6996 * Restart the card from scratch, as if from a cold-boot.
6997 */
6998static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6999{
7000 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7001 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7002 pci_ers_result_t result;
7003 int err;
9a799d71 7004
9ce77666 7005 if (pci_enable_device_mem(pdev)) {
396e799c 7006 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7007 result = PCI_ERS_RESULT_DISCONNECT;
7008 } else {
7009 pci_set_master(pdev);
7010 pci_restore_state(pdev);
c0e1f68b 7011 pci_save_state(pdev);
9a799d71 7012
dd4d8ca6 7013 pci_wake_from_d3(pdev, false);
9a799d71 7014
6fabd715 7015 ixgbe_reset(adapter);
88512539 7016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7017 result = PCI_ERS_RESULT_RECOVERED;
7018 }
7019
7020 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7021 if (err) {
849c4542
ET		 7022 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7023 "failed 0x%0x\n", err);
6fabd715
PWJ		 7024 /* non-fatal, continue */
7025 }
9a799d71 7026
6fabd715 7027 return result;
9a799d71
AK		 7028}
7029
7030/**
7031 * ixgbe_io_resume - called when traffic can start flowing again.
7032 * @pdev: Pointer to PCI device
7033 *
7034 * This callback is called when the error recovery driver tells us that
7035 * its OK to resume normal operation.
7036 */
7037static void ixgbe_io_resume(struct pci_dev *pdev)
7038{
7039 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7040 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7041
7042 if (netif_running(netdev)) {
7043 if (ixgbe_up(adapter)) {
396e799c 7044 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7045 return;
7046 }
7047 }
7048
7049 netif_device_attach(netdev);
9a799d71
AK		 7050}
7051
7052static struct pci_error_handlers ixgbe_err_handler = {
7053 .error_detected = ixgbe_io_error_detected,
7054 .slot_reset = ixgbe_io_slot_reset,
7055 .resume = ixgbe_io_resume,
7056};
7057
7058static struct pci_driver ixgbe_driver = {
7059 .name = ixgbe_driver_name,
7060 .id_table = ixgbe_pci_tbl,
7061 .probe = ixgbe_probe,
7062 .remove = __devexit_p(ixgbe_remove),
7063#ifdef CONFIG_PM
7064 .suspend = ixgbe_suspend,
7065 .resume = ixgbe_resume,
7066#endif
7067 .shutdown = ixgbe_shutdown,
7068 .err_handler = &ixgbe_err_handler
7069};
7070
7071/**
7072 * ixgbe_init_module - Driver Registration Routine
7073 *
7074 * ixgbe_init_module is the first routine called when the driver is
7075 * loaded. All it does is register with the PCI subsystem.
7076 **/
7077static int __init ixgbe_init_module(void)
7078{
7079 int ret;
849c4542
ET		 7080 pr_info("%s - version %s\n", ixgbe_driver_string,
7081 ixgbe_driver_version);
7082 pr_info("%s\n", ixgbe_copyright);
9a799d71 7083
5dd2d332 7084#ifdef CONFIG_IXGBE_DCA
bd0362dd 7085 dca_register_notify(&dca_notifier);
bd0362dd 7086#endif
5dd2d332 7087
9a799d71
AK		 7088 ret = pci_register_driver(&ixgbe_driver);
7089 return ret;
7090}
b4617240 7091
9a799d71
AK		 7092module_init(ixgbe_init_module);
7093
7094/**
7095 * ixgbe_exit_module - Driver Exit Cleanup Routine
7096 *
7097 * ixgbe_exit_module is called just before the driver is removed
7098 * from memory.
7099 **/
7100static void __exit ixgbe_exit_module(void)
7101{
5dd2d332 7102#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7103 dca_unregister_notify(&dca_notifier);
7104#endif
9a799d71
AK		 7105 pci_unregister_driver(&ixgbe_driver);
7106}
bd0362dd 7107
5dd2d332 7108#ifdef CONFIG_IXGBE_DCA
bd0362dd 7109static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 7110 void *p)
bd0362dd
JC		 7111{
7112 int ret_val;
7113
7114 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 7115 __ixgbe_notify_dca);
bd0362dd
JC		 7116
7117 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7118}
b453368d 7119
5dd2d332 7120#endif /* CONFIG_IXGBE_DCA */
849c4542 7121
b453368d 7122/**
849c4542 7123 * ixgbe_get_hw_dev return device
b453368d
AD		 7124 * used by hardware layer to print debugging information
7125 **/
849c4542 7126struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7127{
7128 struct ixgbe_adapter *adapter = hw->back;
849c4542 7129 return adapter->netdev;
b453368d 7130}
bd0362dd 7131
9a799d71
AK		 7132module_exit(ixgbe_exit_module);
7133
7134/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)