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d3a2ae6d YZ |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
4 | Copyright(c) 1999 - 2009 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | ||
29 | #include "ixgbe.h" | |
6ee16520 YZ |
30 | #ifdef CONFIG_IXGBE_DCB |
31 | #include "ixgbe_dcb_82599.h" | |
32 | #endif /* CONFIG_IXGBE_DCB */ | |
d3a2ae6d YZ |
33 | #include <linux/if_ether.h> |
34 | #include <scsi/scsi_cmnd.h> | |
35 | #include <scsi/scsi_device.h> | |
36 | #include <scsi/fc/fc_fs.h> | |
37 | #include <scsi/fc/fc_fcoe.h> | |
38 | #include <scsi/libfc.h> | |
39 | #include <scsi/libfcoe.h> | |
40 | ||
d0ed8937 YZ |
41 | /** |
42 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
43 | * @rx_desc: advanced rx descriptor | |
44 | * | |
45 | * Returns : true if it is FCoE pkt | |
46 | */ | |
47 | static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc) | |
48 | { | |
49 | u16 p; | |
50 | ||
51 | p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info); | |
52 | if (p & IXGBE_RXDADV_PKTTYPE_ETQF) { | |
53 | p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK; | |
54 | p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT; | |
55 | return p == IXGBE_ETQF_FILTER_FCOE; | |
56 | } | |
57 | return false; | |
58 | } | |
59 | ||
60 | /** | |
61 | * ixgbe_fcoe_clear_ddp - clear the given ddp context | |
62 | * @ddp - ptr to the ixgbe_fcoe_ddp | |
63 | * | |
64 | * Returns : none | |
65 | * | |
66 | */ | |
67 | static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp) | |
68 | { | |
69 | ddp->len = 0; | |
70 | ddp->err = 0; | |
71 | ddp->udl = NULL; | |
72 | ddp->udp = 0UL; | |
73 | ddp->sgl = NULL; | |
74 | ddp->sgc = 0; | |
75 | } | |
76 | ||
77 | /** | |
78 | * ixgbe_fcoe_ddp_put - free the ddp context for a given xid | |
79 | * @netdev: the corresponding net_device | |
80 | * @xid: the xid that corresponding ddp will be freed | |
81 | * | |
82 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_done | |
83 | * and it is expected to be called by ULD, i.e., FCP layer of libfc | |
84 | * to release the corresponding ddp context when the I/O is done. | |
85 | * | |
86 | * Returns : data length already ddp-ed in bytes | |
87 | */ | |
88 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid) | |
89 | { | |
90 | int len = 0; | |
91 | struct ixgbe_fcoe *fcoe; | |
92 | struct ixgbe_adapter *adapter; | |
93 | struct ixgbe_fcoe_ddp *ddp; | |
94 | ||
95 | if (!netdev) | |
96 | goto out_ddp_put; | |
97 | ||
98 | if (xid >= IXGBE_FCOE_DDP_MAX) | |
99 | goto out_ddp_put; | |
100 | ||
101 | adapter = netdev_priv(netdev); | |
102 | fcoe = &adapter->fcoe; | |
103 | ddp = &fcoe->ddp[xid]; | |
104 | if (!ddp->udl) | |
105 | goto out_ddp_put; | |
106 | ||
107 | len = ddp->len; | |
108 | /* if there an error, force to invalidate ddp context */ | |
109 | if (ddp->err) { | |
110 | spin_lock_bh(&fcoe->lock); | |
111 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0); | |
112 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW, | |
113 | (xid | IXGBE_FCFLTRW_WE)); | |
114 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0); | |
115 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW, | |
116 | (xid | IXGBE_FCDMARW_WE)); | |
117 | spin_unlock_bh(&fcoe->lock); | |
118 | } | |
119 | if (ddp->sgl) | |
120 | pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc, | |
121 | DMA_FROM_DEVICE); | |
122 | pci_pool_free(fcoe->pool, ddp->udl, ddp->udp); | |
123 | ixgbe_fcoe_clear_ddp(ddp); | |
124 | ||
125 | out_ddp_put: | |
126 | return len; | |
127 | } | |
128 | ||
129 | /** | |
130 | * ixgbe_fcoe_ddp_get - called to set up ddp context | |
131 | * @netdev: the corresponding net_device | |
132 | * @xid: the exchange id requesting ddp | |
133 | * @sgl: the scatter-gather list for this request | |
134 | * @sgc: the number of scatter-gather items | |
135 | * | |
136 | * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup | |
137 | * and is expected to be called from ULD, e.g., FCP layer of libfc | |
138 | * to set up ddp for the corresponding xid of the given sglist for | |
139 | * the corresponding I/O. | |
140 | * | |
141 | * Returns : 1 for success and 0 for no ddp | |
142 | */ | |
143 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
144 | struct scatterlist *sgl, unsigned int sgc) | |
145 | { | |
146 | struct ixgbe_adapter *adapter; | |
147 | struct ixgbe_hw *hw; | |
148 | struct ixgbe_fcoe *fcoe; | |
149 | struct ixgbe_fcoe_ddp *ddp; | |
150 | struct scatterlist *sg; | |
151 | unsigned int i, j, dmacount; | |
152 | unsigned int len; | |
153 | static const unsigned int bufflen = 4096; | |
154 | unsigned int firstoff = 0; | |
155 | unsigned int lastsize; | |
156 | unsigned int thisoff = 0; | |
157 | unsigned int thislen = 0; | |
158 | u32 fcbuff, fcdmarw, fcfltrw; | |
159 | dma_addr_t addr; | |
160 | ||
161 | if (!netdev || !sgl) | |
162 | return 0; | |
163 | ||
164 | adapter = netdev_priv(netdev); | |
165 | if (xid >= IXGBE_FCOE_DDP_MAX) { | |
166 | DPRINTK(DRV, WARNING, "xid=0x%x out-of-range\n", xid); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | fcoe = &adapter->fcoe; | |
171 | if (!fcoe->pool) { | |
172 | DPRINTK(DRV, WARNING, "xid=0x%x no ddp pool for fcoe\n", xid); | |
173 | return 0; | |
174 | } | |
175 | ||
176 | ddp = &fcoe->ddp[xid]; | |
177 | if (ddp->sgl) { | |
178 | DPRINTK(DRV, ERR, "xid 0x%x w/ non-null sgl=%p nents=%d\n", | |
179 | xid, ddp->sgl, ddp->sgc); | |
180 | return 0; | |
181 | } | |
182 | ixgbe_fcoe_clear_ddp(ddp); | |
183 | ||
184 | /* setup dma from scsi command sgl */ | |
185 | dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE); | |
186 | if (dmacount == 0) { | |
187 | DPRINTK(DRV, ERR, "xid 0x%x DMA map error\n", xid); | |
188 | return 0; | |
189 | } | |
190 | ||
191 | /* alloc the udl from our ddp pool */ | |
192 | ddp->udl = pci_pool_alloc(fcoe->pool, GFP_KERNEL, &ddp->udp); | |
193 | if (!ddp->udl) { | |
194 | DPRINTK(DRV, ERR, "failed allocated ddp context\n"); | |
195 | goto out_noddp_unmap; | |
196 | } | |
197 | ddp->sgl = sgl; | |
198 | ddp->sgc = sgc; | |
199 | ||
200 | j = 0; | |
201 | for_each_sg(sgl, sg, dmacount, i) { | |
202 | addr = sg_dma_address(sg); | |
203 | len = sg_dma_len(sg); | |
204 | while (len) { | |
205 | /* get the offset of length of current buffer */ | |
206 | thisoff = addr & ((dma_addr_t)bufflen - 1); | |
207 | thislen = min((bufflen - thisoff), len); | |
208 | /* | |
209 | * all but the 1st buffer (j == 0) | |
210 | * must be aligned on bufflen | |
211 | */ | |
212 | if ((j != 0) && (thisoff)) | |
213 | goto out_noddp_free; | |
214 | /* | |
215 | * all but the last buffer | |
216 | * ((i == (dmacount - 1)) && (thislen == len)) | |
217 | * must end at bufflen | |
218 | */ | |
219 | if (((i != (dmacount - 1)) || (thislen != len)) | |
220 | && ((thislen + thisoff) != bufflen)) | |
221 | goto out_noddp_free; | |
222 | ||
223 | ddp->udl[j] = (u64)(addr - thisoff); | |
224 | /* only the first buffer may have none-zero offset */ | |
225 | if (j == 0) | |
226 | firstoff = thisoff; | |
227 | len -= thislen; | |
228 | addr += thislen; | |
229 | j++; | |
230 | /* max number of buffers allowed in one DDP context */ | |
231 | if (j > IXGBE_BUFFCNT_MAX) { | |
232 | DPRINTK(DRV, ERR, "xid=%x:%d,%d,%d:addr=%llx " | |
233 | "not enough descriptors\n", | |
234 | xid, i, j, dmacount, (u64)addr); | |
235 | goto out_noddp_free; | |
236 | } | |
237 | } | |
238 | } | |
239 | /* only the last buffer may have non-full bufflen */ | |
240 | lastsize = thisoff + thislen; | |
241 | ||
242 | fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT); | |
243 | fcbuff |= (j << IXGBE_FCBUFF_BUFFCNT_SHIFT); | |
244 | fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT); | |
245 | fcbuff |= (IXGBE_FCBUFF_VALID); | |
246 | ||
247 | fcdmarw = xid; | |
248 | fcdmarw |= IXGBE_FCDMARW_WE; | |
249 | fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT); | |
250 | ||
251 | fcfltrw = xid; | |
252 | fcfltrw |= IXGBE_FCFLTRW_WE; | |
253 | ||
254 | /* program DMA context */ | |
255 | hw = &adapter->hw; | |
256 | spin_lock_bh(&fcoe->lock); | |
8e20ce94 | 257 | IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32)); |
d0ed8937 YZ |
258 | IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32); |
259 | IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff); | |
260 | IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw); | |
261 | /* program filter context */ | |
262 | IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0); | |
263 | IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID); | |
264 | IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw); | |
265 | spin_unlock_bh(&fcoe->lock); | |
266 | ||
267 | return 1; | |
268 | ||
269 | out_noddp_free: | |
270 | pci_pool_free(fcoe->pool, ddp->udl, ddp->udp); | |
271 | ixgbe_fcoe_clear_ddp(ddp); | |
272 | ||
273 | out_noddp_unmap: | |
274 | pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE); | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /** | |
279 | * ixgbe_fcoe_ddp - check ddp status and mark it done | |
280 | * @adapter: ixgbe adapter | |
281 | * @rx_desc: advanced rx descriptor | |
282 | * @skb: the skb holding the received data | |
283 | * | |
284 | * This checks ddp status. | |
285 | * | |
3d8fd385 YZ |
286 | * Returns : < 0 indicates an error or not a FCiE ddp, 0 indicates |
287 | * not passing the skb to ULD, > 0 indicates is the length of data | |
288 | * being ddped. | |
d0ed8937 YZ |
289 | */ |
290 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
291 | union ixgbe_adv_rx_desc *rx_desc, | |
292 | struct sk_buff *skb) | |
293 | { | |
294 | u16 xid; | |
d4ab8819 | 295 | u32 fctl; |
d0ed8937 YZ |
296 | u32 sterr, fceofe, fcerr, fcstat; |
297 | int rc = -EINVAL; | |
298 | struct ixgbe_fcoe *fcoe; | |
299 | struct ixgbe_fcoe_ddp *ddp; | |
300 | struct fc_frame_header *fh; | |
301 | ||
302 | if (!ixgbe_rx_is_fcoe(rx_desc)) | |
303 | goto ddp_out; | |
304 | ||
305 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
306 | sterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
307 | fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR); | |
308 | fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE); | |
309 | if (fcerr == IXGBE_FCERR_BADCRC) | |
310 | skb->ip_summed = CHECKSUM_NONE; | |
311 | ||
312 | skb_reset_network_header(skb); | |
313 | skb_set_transport_header(skb, skb_network_offset(skb) + | |
314 | sizeof(struct fcoe_hdr)); | |
315 | fh = (struct fc_frame_header *)skb_transport_header(skb); | |
d4ab8819 YZ |
316 | fctl = ntoh24(fh->fh_f_ctl); |
317 | if (fctl & FC_FC_EX_CTX) | |
318 | xid = be16_to_cpu(fh->fh_ox_id); | |
319 | else | |
320 | xid = be16_to_cpu(fh->fh_rx_id); | |
321 | ||
d0ed8937 YZ |
322 | if (xid >= IXGBE_FCOE_DDP_MAX) |
323 | goto ddp_out; | |
324 | ||
325 | fcoe = &adapter->fcoe; | |
326 | ddp = &fcoe->ddp[xid]; | |
327 | if (!ddp->udl) | |
328 | goto ddp_out; | |
329 | ||
330 | ddp->err = (fcerr | fceofe); | |
331 | if (ddp->err) | |
332 | goto ddp_out; | |
333 | ||
334 | fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT); | |
335 | if (fcstat) { | |
336 | /* update length of DDPed data */ | |
337 | ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
338 | /* unmap the sg list when FCP_RSP is received */ | |
339 | if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) { | |
340 | pci_unmap_sg(adapter->pdev, ddp->sgl, | |
341 | ddp->sgc, DMA_FROM_DEVICE); | |
342 | ddp->sgl = NULL; | |
343 | ddp->sgc = 0; | |
344 | } | |
345 | /* return 0 to bypass going to ULD for DDPed data */ | |
346 | if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP) | |
347 | rc = 0; | |
17e78b06 | 348 | else if (ddp->len) |
3d8fd385 | 349 | rc = ddp->len; |
d0ed8937 YZ |
350 | } |
351 | ||
352 | ddp_out: | |
353 | return rc; | |
354 | } | |
355 | ||
bc079228 YZ |
356 | /** |
357 | * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO) | |
358 | * @adapter: ixgbe adapter | |
359 | * @tx_ring: tx desc ring | |
360 | * @skb: associated skb | |
361 | * @tx_flags: tx flags | |
362 | * @hdr_len: hdr_len to be returned | |
363 | * | |
364 | * This sets up large send offload for FCoE | |
365 | * | |
366 | * Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error | |
367 | */ | |
368 | int ixgbe_fso(struct ixgbe_adapter *adapter, | |
369 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, | |
370 | u32 tx_flags, u8 *hdr_len) | |
371 | { | |
372 | u8 sof, eof; | |
373 | u32 vlan_macip_lens; | |
374 | u32 fcoe_sof_eof; | |
375 | u32 type_tucmd; | |
376 | u32 mss_l4len_idx; | |
377 | int mss = 0; | |
378 | unsigned int i; | |
379 | struct ixgbe_tx_buffer *tx_buffer_info; | |
380 | struct ixgbe_adv_tx_context_desc *context_desc; | |
381 | struct fc_frame_header *fh; | |
382 | ||
383 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) { | |
384 | DPRINTK(DRV, ERR, "Wrong gso type %d:expecting SKB_GSO_FCOE\n", | |
385 | skb_shinfo(skb)->gso_type); | |
386 | return -EINVAL; | |
387 | } | |
388 | ||
389 | /* resets the header to point fcoe/fc */ | |
390 | skb_set_network_header(skb, skb->mac_len); | |
391 | skb_set_transport_header(skb, skb->mac_len + | |
392 | sizeof(struct fcoe_hdr)); | |
393 | ||
394 | /* sets up SOF and ORIS */ | |
395 | fcoe_sof_eof = 0; | |
396 | sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof; | |
397 | switch (sof) { | |
398 | case FC_SOF_I2: | |
399 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS; | |
400 | break; | |
401 | case FC_SOF_I3: | |
402 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF; | |
403 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS; | |
404 | break; | |
405 | case FC_SOF_N2: | |
406 | break; | |
407 | case FC_SOF_N3: | |
408 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF; | |
409 | break; | |
410 | default: | |
411 | DPRINTK(DRV, WARNING, "unknown sof = 0x%x\n", sof); | |
412 | return -EINVAL; | |
413 | } | |
414 | ||
415 | /* the first byte of the last dword is EOF */ | |
416 | skb_copy_bits(skb, skb->len - 4, &eof, 1); | |
417 | /* sets up EOF and ORIE */ | |
418 | switch (eof) { | |
419 | case FC_EOF_N: | |
420 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N; | |
421 | break; | |
422 | case FC_EOF_T: | |
423 | /* lso needs ORIE */ | |
424 | if (skb_is_gso(skb)) { | |
425 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N; | |
426 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIE; | |
427 | } else { | |
428 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T; | |
429 | } | |
430 | break; | |
431 | case FC_EOF_NI: | |
432 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI; | |
433 | break; | |
434 | case FC_EOF_A: | |
435 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A; | |
436 | break; | |
437 | default: | |
438 | DPRINTK(DRV, WARNING, "unknown eof = 0x%x\n", eof); | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | /* sets up PARINC indicating data offset */ | |
443 | fh = (struct fc_frame_header *)skb_transport_header(skb); | |
444 | if (fh->fh_f_ctl[2] & FC_FC_REL_OFF) | |
445 | fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC; | |
446 | ||
447 | /* hdr_len includes fc_hdr if FCoE lso is enabled */ | |
448 | *hdr_len = sizeof(struct fcoe_crc_eof); | |
449 | if (skb_is_gso(skb)) | |
450 | *hdr_len += (skb_transport_offset(skb) + | |
451 | sizeof(struct fc_frame_header)); | |
452 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
453 | vlan_macip_lens = (skb_transport_offset(skb) + | |
454 | sizeof(struct fc_frame_header)); | |
455 | vlan_macip_lens |= ((skb_transport_offset(skb) - 4) | |
456 | << IXGBE_ADVTXD_MACLEN_SHIFT); | |
457 | vlan_macip_lens |= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
458 | ||
459 | /* type_tycmd and mss: set TUCMD.FCoE to enable offload */ | |
460 | type_tucmd = IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT | | |
461 | IXGBE_ADVTXT_TUCMD_FCOE; | |
462 | if (skb_is_gso(skb)) | |
463 | mss = skb_shinfo(skb)->gso_size; | |
464 | /* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */ | |
465 | mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) | | |
466 | (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
467 | ||
468 | /* write context desc */ | |
469 | i = tx_ring->next_to_use; | |
470 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
471 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
472 | context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); | |
473 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
474 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
475 | ||
476 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
477 | tx_buffer_info->time_stamp = jiffies; | |
478 | tx_buffer_info->next_to_watch = i; | |
479 | ||
480 | i++; | |
481 | if (i == tx_ring->count) | |
482 | i = 0; | |
483 | tx_ring->next_to_use = i; | |
484 | ||
485 | return skb_is_gso(skb); | |
486 | } | |
487 | ||
d3a2ae6d YZ |
488 | /** |
489 | * ixgbe_configure_fcoe - configures registers for fcoe at start | |
490 | * @adapter: ptr to ixgbe adapter | |
491 | * | |
492 | * This sets up FCoE related registers | |
493 | * | |
494 | * Returns : none | |
495 | */ | |
496 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter) | |
497 | { | |
29ebf6f8 | 498 | int i, fcoe_q, fcoe_i; |
d3a2ae6d | 499 | struct ixgbe_hw *hw = &adapter->hw; |
d0ed8937 | 500 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; |
29ebf6f8 | 501 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
d0ed8937 YZ |
502 | |
503 | /* create the pool for ddp if not created yet */ | |
504 | if (!fcoe->pool) { | |
505 | /* allocate ddp pool */ | |
506 | fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp", | |
507 | adapter->pdev, IXGBE_FCPTR_MAX, | |
508 | IXGBE_FCPTR_ALIGN, PAGE_SIZE); | |
509 | if (!fcoe->pool) | |
510 | DPRINTK(DRV, ERR, | |
511 | "failed to allocated FCoE DDP pool\n"); | |
d3a2ae6d | 512 | |
d0ed8937 YZ |
513 | spin_lock_init(&fcoe->lock); |
514 | } | |
29ebf6f8 YZ |
515 | |
516 | /* Enable L2 eth type filter for FCoE */ | |
d3a2ae6d YZ |
517 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE), |
518 | (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN)); | |
29ebf6f8 YZ |
519 | if (adapter->ring_feature[RING_F_FCOE].indices) { |
520 | /* Use multiple rx queues for FCoE by redirection table */ | |
521 | for (i = 0; i < IXGBE_FCRETA_SIZE; i++) { | |
522 | fcoe_i = f->mask + i % f->indices; | |
523 | fcoe_i &= IXGBE_FCRETA_ENTRY_MASK; | |
524 | fcoe_q = adapter->rx_ring[fcoe_i].reg_idx; | |
525 | IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q); | |
526 | } | |
527 | IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA); | |
528 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0); | |
529 | } else { | |
530 | /* Use single rx queue for FCoE */ | |
531 | fcoe_i = f->mask; | |
532 | fcoe_q = adapter->rx_ring[fcoe_i].reg_idx; | |
533 | IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0); | |
534 | IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), | |
535 | IXGBE_ETQS_QUEUE_EN | | |
536 | (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); | |
537 | } | |
538 | ||
d3a2ae6d YZ |
539 | IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, |
540 | IXGBE_FCRXCTRL_FCOELLI | | |
541 | IXGBE_FCRXCTRL_FCCRCBO | | |
542 | (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT)); | |
543 | } | |
d0ed8937 YZ |
544 | |
545 | /** | |
546 | * ixgbe_cleanup_fcoe - release all fcoe ddp context resources | |
547 | * @adapter : ixgbe adapter | |
548 | * | |
549 | * Cleans up outstanding ddp context resources | |
550 | * | |
551 | * Returns : none | |
552 | */ | |
553 | void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter) | |
554 | { | |
555 | int i; | |
556 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
557 | ||
558 | /* release ddp resource */ | |
559 | if (fcoe->pool) { | |
560 | for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++) | |
561 | ixgbe_fcoe_ddp_put(adapter->netdev, i); | |
562 | pci_pool_destroy(fcoe->pool); | |
563 | fcoe->pool = NULL; | |
564 | } | |
565 | } | |
8450ff8c YZ |
566 | |
567 | /** | |
568 | * ixgbe_fcoe_enable - turn on FCoE offload feature | |
569 | * @netdev: the corresponding netdev | |
570 | * | |
571 | * Turns on FCoE offload feature in 82599. | |
572 | * | |
573 | * Returns : 0 indicates success or -EINVAL on failure | |
574 | */ | |
575 | int ixgbe_fcoe_enable(struct net_device *netdev) | |
576 | { | |
577 | int rc = -EINVAL; | |
578 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
579 | ||
580 | ||
581 | if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE)) | |
582 | goto out_enable; | |
583 | ||
584 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
585 | goto out_enable; | |
586 | ||
587 | DPRINTK(DRV, INFO, "Enabling FCoE offload features.\n"); | |
588 | if (netif_running(netdev)) | |
589 | netdev->netdev_ops->ndo_stop(netdev); | |
590 | ||
591 | ixgbe_clear_interrupt_scheme(adapter); | |
592 | ||
593 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
594 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; | |
595 | netdev->features |= NETIF_F_FCOE_CRC; | |
596 | netdev->features |= NETIF_F_FSO; | |
597 | netdev->features |= NETIF_F_FCOE_MTU; | |
598 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
599 | netdev->vlan_features |= NETIF_F_FSO; | |
600 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
601 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; | |
602 | netdev_features_change(netdev); | |
603 | ||
604 | ixgbe_init_interrupt_scheme(adapter); | |
605 | ||
606 | if (netif_running(netdev)) | |
607 | netdev->netdev_ops->ndo_open(netdev); | |
608 | rc = 0; | |
609 | ||
610 | out_enable: | |
611 | return rc; | |
612 | } | |
613 | ||
614 | /** | |
615 | * ixgbe_fcoe_disable - turn off FCoE offload feature | |
616 | * @netdev: the corresponding netdev | |
617 | * | |
618 | * Turns off FCoE offload feature in 82599. | |
619 | * | |
620 | * Returns : 0 indicates success or -EINVAL on failure | |
621 | */ | |
622 | int ixgbe_fcoe_disable(struct net_device *netdev) | |
623 | { | |
624 | int rc = -EINVAL; | |
625 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
626 | ||
627 | if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE)) | |
628 | goto out_disable; | |
629 | ||
630 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
631 | goto out_disable; | |
632 | ||
633 | DPRINTK(DRV, INFO, "Disabling FCoE offload features.\n"); | |
634 | if (netif_running(netdev)) | |
635 | netdev->netdev_ops->ndo_stop(netdev); | |
636 | ||
637 | ixgbe_clear_interrupt_scheme(adapter); | |
638 | ||
639 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
640 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
641 | netdev->features &= ~NETIF_F_FCOE_CRC; | |
642 | netdev->features &= ~NETIF_F_FSO; | |
643 | netdev->features &= ~NETIF_F_FCOE_MTU; | |
644 | netdev->vlan_features &= ~NETIF_F_FCOE_CRC; | |
645 | netdev->vlan_features &= ~NETIF_F_FSO; | |
646 | netdev->vlan_features &= ~NETIF_F_FCOE_MTU; | |
647 | netdev->fcoe_ddp_xid = 0; | |
648 | netdev_features_change(netdev); | |
649 | ||
650 | ixgbe_cleanup_fcoe(adapter); | |
651 | ||
652 | ixgbe_init_interrupt_scheme(adapter); | |
653 | if (netif_running(netdev)) | |
654 | netdev->netdev_ops->ndo_open(netdev); | |
655 | rc = 0; | |
656 | ||
657 | out_disable: | |
658 | return rc; | |
659 | } | |
6ee16520 YZ |
660 | |
661 | #ifdef CONFIG_IXGBE_DCB | |
662 | /** | |
663 | * ixgbe_fcoe_getapp - retrieves current user priority bitmap for FCoE | |
664 | * @adapter : ixgbe adapter | |
665 | * | |
666 | * Finds out the corresponding user priority bitmap from the current | |
667 | * traffic class that FCoE belongs to. Returns 0 as the invalid user | |
668 | * priority bitmap to indicate an error. | |
669 | * | |
670 | * Returns : 802.1p user priority bitmap for FCoE | |
671 | */ | |
672 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter) | |
673 | { | |
674 | int i; | |
675 | u8 tc; | |
676 | u32 up2tc; | |
677 | ||
678 | up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC); | |
679 | for (i = 0; i < MAX_USER_PRIORITY; i++) { | |
680 | tc = (u8)(up2tc >> (i * IXGBE_RTTUP2TC_UP_SHIFT)); | |
681 | tc &= (MAX_TRAFFIC_CLASS - 1); | |
682 | if (adapter->fcoe.tc == tc) | |
683 | return 1 << i; | |
684 | } | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
689 | /** | |
690 | * ixgbe_fcoe_setapp - sets the user priority bitmap for FCoE | |
691 | * @adapter : ixgbe adapter | |
692 | * @up : 802.1p user priority bitmap | |
693 | * | |
694 | * Finds out the traffic class from the input user priority | |
695 | * bitmap for FCoE. | |
696 | * | |
697 | * Returns : 0 on success otherwise returns 1 on error | |
698 | */ | |
699 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up) | |
700 | { | |
701 | int i; | |
702 | u32 up2tc; | |
703 | ||
704 | /* valid user priority bitmap must not be 0 */ | |
705 | if (up) { | |
706 | /* from user priority to the corresponding traffic class */ | |
707 | up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC); | |
708 | for (i = 0; i < MAX_USER_PRIORITY; i++) { | |
709 | if (up & (1 << i)) { | |
710 | up2tc >>= (i * IXGBE_RTTUP2TC_UP_SHIFT); | |
711 | up2tc &= (MAX_TRAFFIC_CLASS - 1); | |
712 | adapter->fcoe.tc = (u8)up2tc; | |
713 | return 0; | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | return 1; | |
719 | } | |
720 | #endif /* CONFIG_IXGBE_DCB */ |