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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* ethtool support for ixgbe */ | |
29 | ||
30 | #include <linux/types.h> | |
31 | #include <linux/module.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9a799d71 AK |
33 | #include <linux/pci.h> |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/vmalloc.h> | |
37 | #include <linux/uaccess.h> | |
38 | ||
39 | #include "ixgbe.h" | |
40 | ||
41 | ||
42 | #define IXGBE_ALL_RAR_ENTRIES 16 | |
43 | ||
29c3a050 AK |
44 | enum {NETDEV_STATS, IXGBE_STATS}; |
45 | ||
9a799d71 AK |
46 | struct ixgbe_stats { |
47 | char stat_string[ETH_GSTRING_LEN]; | |
29c3a050 | 48 | int type; |
9a799d71 AK |
49 | int sizeof_stat; |
50 | int stat_offset; | |
51 | }; | |
52 | ||
29c3a050 AK |
53 | #define IXGBE_STAT(m) IXGBE_STATS, \ |
54 | sizeof(((struct ixgbe_adapter *)0)->m), \ | |
55 | offsetof(struct ixgbe_adapter, m) | |
56 | #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ | |
55bad823 ED |
57 | sizeof(((struct rtnl_link_stats64 *)0)->m), \ |
58 | offsetof(struct rtnl_link_stats64, m) | |
29c3a050 | 59 | |
9a799d71 | 60 | static struct ixgbe_stats ixgbe_gstrings_stats[] = { |
55bad823 ED |
61 | {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, |
62 | {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, | |
63 | {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, | |
64 | {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, | |
aad71918 BG |
65 | {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, |
66 | {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, | |
67 | {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, | |
68 | {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, | |
9a799d71 AK |
69 | {"lsc_int", IXGBE_STAT(lsc_int)}, |
70 | {"tx_busy", IXGBE_STAT(tx_busy)}, | |
71 | {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, | |
55bad823 ED |
72 | {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, |
73 | {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, | |
74 | {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, | |
75 | {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, | |
76 | {"multicast", IXGBE_NETDEV_STAT(multicast)}, | |
9a799d71 AK |
77 | {"broadcast", IXGBE_STAT(stats.bprc)}, |
78 | {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, | |
55bad823 ED |
79 | {"collisions", IXGBE_NETDEV_STAT(collisions)}, |
80 | {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, | |
81 | {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, | |
82 | {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, | |
94b982b2 MC |
83 | {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, |
84 | {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, | |
c4cf55e5 PWJ |
85 | {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, |
86 | {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, | |
55bad823 ED |
87 | {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, |
88 | {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, | |
89 | {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, | |
90 | {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, | |
91 | {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, | |
92 | {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, | |
9a799d71 AK |
93 | {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, |
94 | {"tx_restart_queue", IXGBE_STAT(restart_queue)}, | |
95 | {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, | |
96 | {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, | |
9a799d71 AK |
97 | {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, |
98 | {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, | |
99 | {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, | |
100 | {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, | |
9a799d71 | 101 | {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, |
9a799d71 AK |
102 | {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, |
103 | {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, | |
e8e26350 | 104 | {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, |
6d45522c YZ |
105 | #ifdef IXGBE_FCOE |
106 | {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, | |
107 | {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, | |
108 | {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, | |
109 | {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, | |
110 | {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, | |
111 | {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, | |
112 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
113 | }; |
114 | ||
115 | #define IXGBE_QUEUE_STATS_LEN \ | |
454d7c9b WC |
116 | ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \ |
117 | ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \ | |
118 | (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) | |
b4617240 | 119 | #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) |
2f90b865 | 120 | #define IXGBE_PB_STATS_LEN ( \ |
9d2f4720 | 121 | (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \ |
2f90b865 AD |
122 | IXGBE_FLAG_DCB_ENABLED) ? \ |
123 | (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ | |
124 | sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ | |
125 | sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ | |
126 | sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ | |
127 | / sizeof(u64) : 0) | |
128 | #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ | |
129 | IXGBE_PB_STATS_LEN + \ | |
130 | IXGBE_QUEUE_STATS_LEN) | |
9a799d71 | 131 | |
da4dd0f7 PWJ |
132 | static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { |
133 | "Register test (offline)", "Eeprom test (offline)", | |
134 | "Interrupt test (offline)", "Loopback test (offline)", | |
135 | "Link test (on/offline)" | |
136 | }; | |
137 | #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN | |
138 | ||
9a799d71 | 139 | static int ixgbe_get_settings(struct net_device *netdev, |
b4617240 | 140 | struct ethtool_cmd *ecmd) |
9a799d71 AK |
141 | { |
142 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
735441fb AV |
143 | struct ixgbe_hw *hw = &adapter->hw; |
144 | u32 link_speed = 0; | |
145 | bool link_up; | |
9a799d71 | 146 | |
735441fb AV |
147 | ecmd->supported = SUPPORTED_10000baseT_Full; |
148 | ecmd->autoneg = AUTONEG_ENABLE; | |
9a799d71 | 149 | ecmd->transceiver = XCVR_EXTERNAL; |
74766013 | 150 | if ((hw->phy.media_type == ixgbe_media_type_copper) || |
a3801379 | 151 | (hw->phy.multispeed_fiber)) { |
735441fb | 152 | ecmd->supported |= (SUPPORTED_1000baseT_Full | |
74766013 | 153 | SUPPORTED_Autoneg); |
735441fb | 154 | |
74766013 | 155 | ecmd->advertising = ADVERTISED_Autoneg; |
735441fb AV |
156 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
157 | ecmd->advertising |= ADVERTISED_10000baseT_Full; | |
158 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | |
159 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
7c5b8323 DS |
160 | /* |
161 | * It's possible that phy.autoneg_advertised may not be | |
162 | * set yet. If so display what the default would be - | |
163 | * both 1G and 10G supported. | |
164 | */ | |
165 | if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full | | |
166 | ADVERTISED_10000baseT_Full))) | |
167 | ecmd->advertising |= (ADVERTISED_10000baseT_Full | | |
168 | ADVERTISED_1000baseT_Full); | |
735441fb | 169 | |
74766013 MC |
170 | if (hw->phy.media_type == ixgbe_media_type_copper) { |
171 | ecmd->supported |= SUPPORTED_TP; | |
172 | ecmd->advertising |= ADVERTISED_TP; | |
173 | ecmd->port = PORT_TP; | |
174 | } else { | |
175 | ecmd->supported |= SUPPORTED_FIBRE; | |
176 | ecmd->advertising |= ADVERTISED_FIBRE; | |
177 | ecmd->port = PORT_FIBRE; | |
178 | } | |
1e336d0f DS |
179 | } else if (hw->phy.media_type == ixgbe_media_type_backplane) { |
180 | /* Set as FIBRE until SERDES defined in kernel */ | |
46a72b35 | 181 | if (hw->device_id == IXGBE_DEV_ID_82598_BX) { |
2f21bdd3 DS |
182 | ecmd->supported = (SUPPORTED_1000baseT_Full | |
183 | SUPPORTED_FIBRE); | |
184 | ecmd->advertising = (ADVERTISED_1000baseT_Full | | |
185 | ADVERTISED_FIBRE); | |
186 | ecmd->port = PORT_FIBRE; | |
187 | ecmd->autoneg = AUTONEG_DISABLE; | |
50d6c681 AD |
188 | } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) || |
189 | (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) { | |
190 | ecmd->supported |= (SUPPORTED_1000baseT_Full | | |
191 | SUPPORTED_Autoneg | | |
192 | SUPPORTED_FIBRE); | |
193 | ecmd->advertising = (ADVERTISED_10000baseT_Full | | |
194 | ADVERTISED_1000baseT_Full | | |
195 | ADVERTISED_Autoneg | | |
196 | ADVERTISED_FIBRE); | |
197 | ecmd->port = PORT_FIBRE; | |
46a72b35 MC |
198 | } else { |
199 | ecmd->supported |= (SUPPORTED_1000baseT_Full | | |
200 | SUPPORTED_FIBRE); | |
201 | ecmd->advertising = (ADVERTISED_10000baseT_Full | | |
202 | ADVERTISED_1000baseT_Full | | |
203 | ADVERTISED_FIBRE); | |
204 | ecmd->port = PORT_FIBRE; | |
1e336d0f | 205 | } |
735441fb AV |
206 | } else { |
207 | ecmd->supported |= SUPPORTED_FIBRE; | |
208 | ecmd->advertising = (ADVERTISED_10000baseT_Full | | |
b4617240 | 209 | ADVERTISED_FIBRE); |
735441fb | 210 | ecmd->port = PORT_FIBRE; |
c44ade9e | 211 | ecmd->autoneg = AUTONEG_DISABLE; |
735441fb | 212 | } |
9a799d71 | 213 | |
3b8626ba PW |
214 | /* Get PHY type */ |
215 | switch (adapter->hw.phy.type) { | |
216 | case ixgbe_phy_tn: | |
fe15e8e1 | 217 | case ixgbe_phy_aq: |
3b8626ba PW |
218 | case ixgbe_phy_cu_unknown: |
219 | /* Copper 10G-BASET */ | |
220 | ecmd->port = PORT_TP; | |
221 | break; | |
222 | case ixgbe_phy_qt: | |
223 | ecmd->port = PORT_FIBRE; | |
224 | break; | |
225 | case ixgbe_phy_nl: | |
ea0a04df DS |
226 | case ixgbe_phy_sfp_passive_tyco: |
227 | case ixgbe_phy_sfp_passive_unknown: | |
3b8626ba PW |
228 | case ixgbe_phy_sfp_ftl: |
229 | case ixgbe_phy_sfp_avago: | |
230 | case ixgbe_phy_sfp_intel: | |
231 | case ixgbe_phy_sfp_unknown: | |
232 | switch (adapter->hw.phy.sfp_type) { | |
233 | /* SFP+ devices, further checking needed */ | |
234 | case ixgbe_sfp_type_da_cu: | |
235 | case ixgbe_sfp_type_da_cu_core0: | |
236 | case ixgbe_sfp_type_da_cu_core1: | |
237 | ecmd->port = PORT_DA; | |
238 | break; | |
239 | case ixgbe_sfp_type_sr: | |
240 | case ixgbe_sfp_type_lr: | |
241 | case ixgbe_sfp_type_srlr_core0: | |
242 | case ixgbe_sfp_type_srlr_core1: | |
243 | ecmd->port = PORT_FIBRE; | |
244 | break; | |
245 | case ixgbe_sfp_type_not_present: | |
246 | ecmd->port = PORT_NONE; | |
247 | break; | |
cb836a97 DS |
248 | case ixgbe_sfp_type_1g_cu_core0: |
249 | case ixgbe_sfp_type_1g_cu_core1: | |
250 | ecmd->port = PORT_TP; | |
251 | ecmd->supported = SUPPORTED_TP; | |
252 | ecmd->advertising = (ADVERTISED_1000baseT_Full | | |
253 | ADVERTISED_TP); | |
254 | break; | |
3b8626ba PW |
255 | case ixgbe_sfp_type_unknown: |
256 | default: | |
257 | ecmd->port = PORT_OTHER; | |
258 | break; | |
259 | } | |
260 | break; | |
261 | case ixgbe_phy_xaui: | |
262 | ecmd->port = PORT_NONE; | |
263 | break; | |
264 | case ixgbe_phy_unknown: | |
265 | case ixgbe_phy_generic: | |
266 | case ixgbe_phy_sfp_unsupported: | |
267 | default: | |
268 | ecmd->port = PORT_OTHER; | |
269 | break; | |
270 | } | |
271 | ||
c44ade9e | 272 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); |
735441fb AV |
273 | if (link_up) { |
274 | ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ? | |
b4617240 | 275 | SPEED_10000 : SPEED_1000; |
9a799d71 AK |
276 | ecmd->duplex = DUPLEX_FULL; |
277 | } else { | |
278 | ecmd->speed = -1; | |
279 | ecmd->duplex = -1; | |
280 | } | |
281 | ||
9a799d71 AK |
282 | return 0; |
283 | } | |
284 | ||
285 | static int ixgbe_set_settings(struct net_device *netdev, | |
b4617240 | 286 | struct ethtool_cmd *ecmd) |
9a799d71 AK |
287 | { |
288 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
735441fb | 289 | struct ixgbe_hw *hw = &adapter->hw; |
0befdb3e | 290 | u32 advertised, old; |
74766013 | 291 | s32 err = 0; |
9a799d71 | 292 | |
74766013 | 293 | if ((hw->phy.media_type == ixgbe_media_type_copper) || |
a3801379 | 294 | (hw->phy.multispeed_fiber)) { |
0befdb3e JB |
295 | /* 10000/copper and 1000/copper must autoneg |
296 | * this function does not support any duplex forcing, but can | |
297 | * limit the advertising of the adapter to only 10000 or 1000 */ | |
298 | if (ecmd->autoneg == AUTONEG_DISABLE) | |
299 | return -EINVAL; | |
300 | ||
301 | old = hw->phy.autoneg_advertised; | |
302 | advertised = 0; | |
303 | if (ecmd->advertising & ADVERTISED_10000baseT_Full) | |
304 | advertised |= IXGBE_LINK_SPEED_10GB_FULL; | |
305 | ||
306 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
307 | advertised |= IXGBE_LINK_SPEED_1GB_FULL; | |
308 | ||
309 | if (old == advertised) | |
74766013 | 310 | return err; |
0befdb3e | 311 | /* this sets the link speed and restarts auto-neg */ |
74766013 | 312 | hw->mac.autotry_restart = true; |
8620a103 | 313 | err = hw->mac.ops.setup_link(hw, advertised, true, true); |
0befdb3e | 314 | if (err) { |
396e799c | 315 | e_info(probe, "setup link failed with code %d\n", err); |
8620a103 | 316 | hw->mac.ops.setup_link(hw, old, true, true); |
0befdb3e | 317 | } |
74766013 MC |
318 | } else { |
319 | /* in this case we currently only support 10Gb/FULL */ | |
320 | if ((ecmd->autoneg == AUTONEG_ENABLE) || | |
a3801379 | 321 | (ecmd->advertising != ADVERTISED_10000baseT_Full) || |
74766013 MC |
322 | (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) |
323 | return -EINVAL; | |
9a799d71 AK |
324 | } |
325 | ||
74766013 | 326 | return err; |
9a799d71 AK |
327 | } |
328 | ||
329 | static void ixgbe_get_pauseparam(struct net_device *netdev, | |
b4617240 | 330 | struct ethtool_pauseparam *pause) |
9a799d71 AK |
331 | { |
332 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
333 | struct ixgbe_hw *hw = &adapter->hw; | |
334 | ||
71fd570b DS |
335 | /* |
336 | * Flow Control Autoneg isn't on if | |
337 | * - we didn't ask for it OR | |
338 | * - it failed, we know this by tx & rx being off | |
339 | */ | |
340 | if (hw->fc.disable_fc_autoneg || | |
341 | (hw->fc.current_mode == ixgbe_fc_none)) | |
342 | pause->autoneg = 0; | |
343 | else | |
344 | pause->autoneg = 1; | |
9a799d71 | 345 | |
0ecc061d | 346 | if (hw->fc.current_mode == ixgbe_fc_rx_pause) { |
9a799d71 | 347 | pause->rx_pause = 1; |
0ecc061d | 348 | } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { |
9a799d71 | 349 | pause->tx_pause = 1; |
0ecc061d | 350 | } else if (hw->fc.current_mode == ixgbe_fc_full) { |
9a799d71 AK |
351 | pause->rx_pause = 1; |
352 | pause->tx_pause = 1; | |
673ac604 AD |
353 | #ifdef CONFIG_DCB |
354 | } else if (hw->fc.current_mode == ixgbe_fc_pfc) { | |
355 | pause->rx_pause = 0; | |
356 | pause->tx_pause = 0; | |
357 | #endif | |
9a799d71 AK |
358 | } |
359 | } | |
360 | ||
361 | static int ixgbe_set_pauseparam(struct net_device *netdev, | |
b4617240 | 362 | struct ethtool_pauseparam *pause) |
9a799d71 AK |
363 | { |
364 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
365 | struct ixgbe_hw *hw = &adapter->hw; | |
620fa036 | 366 | struct ixgbe_fc_info fc; |
9a799d71 | 367 | |
264857b8 PWJ |
368 | #ifdef CONFIG_DCB |
369 | if (adapter->dcb_cfg.pfc_mode_enable || | |
370 | ((hw->mac.type == ixgbe_mac_82598EB) && | |
371 | (adapter->flags & IXGBE_FLAG_DCB_ENABLED))) | |
372 | return -EINVAL; | |
373 | ||
374 | #endif | |
620fa036 MC |
375 | fc = hw->fc; |
376 | ||
71fd570b | 377 | if (pause->autoneg != AUTONEG_ENABLE) |
620fa036 | 378 | fc.disable_fc_autoneg = true; |
71fd570b | 379 | else |
620fa036 | 380 | fc.disable_fc_autoneg = false; |
71fd570b | 381 | |
1c4f0ef8 | 382 | if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) |
620fa036 | 383 | fc.requested_mode = ixgbe_fc_full; |
9a799d71 | 384 | else if (pause->rx_pause && !pause->tx_pause) |
620fa036 | 385 | fc.requested_mode = ixgbe_fc_rx_pause; |
9a799d71 | 386 | else if (!pause->rx_pause && pause->tx_pause) |
620fa036 | 387 | fc.requested_mode = ixgbe_fc_tx_pause; |
9a799d71 | 388 | else if (!pause->rx_pause && !pause->tx_pause) |
620fa036 | 389 | fc.requested_mode = ixgbe_fc_none; |
9c83b070 AV |
390 | else |
391 | return -EINVAL; | |
9a799d71 | 392 | |
264857b8 | 393 | #ifdef CONFIG_DCB |
620fa036 | 394 | adapter->last_lfc_mode = fc.requested_mode; |
264857b8 | 395 | #endif |
620fa036 MC |
396 | |
397 | /* if the thing changed then we'll update and use new autoneg */ | |
398 | if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { | |
399 | hw->fc = fc; | |
400 | if (netif_running(netdev)) | |
401 | ixgbe_reinit_locked(adapter); | |
402 | else | |
403 | ixgbe_reset(adapter); | |
404 | } | |
9a799d71 AK |
405 | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static u32 ixgbe_get_rx_csum(struct net_device *netdev) | |
410 | { | |
411 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
807540ba | 412 | return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED; |
9a799d71 AK |
413 | } |
414 | ||
415 | static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data) | |
416 | { | |
417 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
418 | if (data) | |
419 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; | |
420 | else | |
421 | adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED; | |
422 | ||
9a799d71 AK |
423 | return 0; |
424 | } | |
425 | ||
426 | static u32 ixgbe_get_tx_csum(struct net_device *netdev) | |
427 | { | |
22f32b7a | 428 | return (netdev->features & NETIF_F_IP_CSUM) != 0; |
9a799d71 AK |
429 | } |
430 | ||
431 | static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data) | |
432 | { | |
45a5ead0 | 433 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
b93a2226 | 434 | u32 feature_list; |
45a5ead0 | 435 | |
b93a2226 DS |
436 | feature_list = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); |
437 | switch (adapter->hw.mac.type) { | |
438 | case ixgbe_mac_82599EB: | |
439 | case ixgbe_mac_X540: | |
440 | feature_list |= NETIF_F_SCTP_CSUM; | |
441 | break; | |
442 | default: | |
443 | break; | |
45a5ead0 | 444 | } |
b93a2226 DS |
445 | if (data) |
446 | netdev->features |= feature_list; | |
447 | else | |
448 | netdev->features &= ~feature_list; | |
9a799d71 AK |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
453 | static int ixgbe_set_tso(struct net_device *netdev, u32 data) | |
454 | { | |
9a799d71 AK |
455 | if (data) { |
456 | netdev->features |= NETIF_F_TSO; | |
457 | netdev->features |= NETIF_F_TSO6; | |
458 | } else { | |
459 | netdev->features &= ~NETIF_F_TSO; | |
460 | netdev->features &= ~NETIF_F_TSO6; | |
461 | } | |
462 | return 0; | |
463 | } | |
464 | ||
465 | static u32 ixgbe_get_msglevel(struct net_device *netdev) | |
466 | { | |
467 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
468 | return adapter->msg_enable; | |
469 | } | |
470 | ||
471 | static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) | |
472 | { | |
473 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
474 | adapter->msg_enable = data; | |
475 | } | |
476 | ||
477 | static int ixgbe_get_regs_len(struct net_device *netdev) | |
478 | { | |
479 | #define IXGBE_REGS_LEN 1128 | |
480 | return IXGBE_REGS_LEN * sizeof(u32); | |
481 | } | |
482 | ||
483 | #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ | |
484 | ||
485 | static void ixgbe_get_regs(struct net_device *netdev, | |
b4617240 | 486 | struct ethtool_regs *regs, void *p) |
9a799d71 AK |
487 | { |
488 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
489 | struct ixgbe_hw *hw = &adapter->hw; | |
490 | u32 *regs_buff = p; | |
491 | u8 i; | |
492 | ||
493 | memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); | |
494 | ||
495 | regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id; | |
496 | ||
497 | /* General Registers */ | |
498 | regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
499 | regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); | |
500 | regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
501 | regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
502 | regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); | |
503 | regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
504 | regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); | |
505 | regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); | |
506 | ||
507 | /* NVM Register */ | |
508 | regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC); | |
509 | regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); | |
510 | regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA); | |
511 | regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); | |
512 | regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); | |
513 | regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); | |
514 | regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); | |
515 | regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); | |
516 | regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); | |
517 | regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC); | |
518 | ||
519 | /* Interrupt */ | |
98c00a1c JB |
520 | /* don't read EICR because it can clear interrupt causes, instead |
521 | * read EICS which is a shadow but doesn't clear EICR */ | |
522 | regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); | |
9a799d71 AK |
523 | regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); |
524 | regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); | |
525 | regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); | |
526 | regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); | |
527 | regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); | |
528 | regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); | |
529 | regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); | |
530 | regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); | |
531 | regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); | |
c44ade9e | 532 | regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); |
9a799d71 AK |
533 | regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); |
534 | ||
535 | /* Flow Control */ | |
536 | regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); | |
537 | regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); | |
538 | regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); | |
539 | regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); | |
540 | regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); | |
bd508178 AD |
541 | for (i = 0; i < 8; i++) { |
542 | switch (hw->mac.type) { | |
543 | case ixgbe_mac_82598EB: | |
544 | regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); | |
545 | regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); | |
546 | break; | |
547 | case ixgbe_mac_82599EB: | |
548 | regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); | |
549 | regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); | |
550 | break; | |
551 | default: | |
552 | break; | |
553 | } | |
554 | } | |
9a799d71 AK |
555 | regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); |
556 | regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); | |
557 | ||
558 | /* Receive DMA */ | |
559 | for (i = 0; i < 64; i++) | |
560 | regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
561 | for (i = 0; i < 64; i++) | |
562 | regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
563 | for (i = 0; i < 64; i++) | |
564 | regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
565 | for (i = 0; i < 64; i++) | |
566 | regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
567 | for (i = 0; i < 64; i++) | |
568 | regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
569 | for (i = 0; i < 64; i++) | |
570 | regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
571 | for (i = 0; i < 16; i++) | |
572 | regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
573 | for (i = 0; i < 16; i++) | |
574 | regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
575 | regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
576 | for (i = 0; i < 8; i++) | |
577 | regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); | |
578 | regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
579 | regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); | |
580 | ||
581 | /* Receive */ | |
582 | regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
583 | regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); | |
584 | for (i = 0; i < 16; i++) | |
585 | regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); | |
586 | for (i = 0; i < 16; i++) | |
587 | regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); | |
c44ade9e | 588 | regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); |
9a799d71 AK |
589 | regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
590 | regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
591 | regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); | |
592 | regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); | |
593 | regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
594 | for (i = 0; i < 8; i++) | |
595 | regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); | |
596 | for (i = 0; i < 8; i++) | |
597 | regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); | |
598 | regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); | |
599 | ||
600 | /* Transmit */ | |
601 | for (i = 0; i < 32; i++) | |
602 | regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
603 | for (i = 0; i < 32; i++) | |
604 | regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
605 | for (i = 0; i < 32; i++) | |
606 | regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
607 | for (i = 0; i < 32; i++) | |
608 | regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
609 | for (i = 0; i < 32; i++) | |
610 | regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
611 | for (i = 0; i < 32; i++) | |
612 | regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
613 | for (i = 0; i < 32; i++) | |
614 | regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); | |
615 | for (i = 0; i < 32; i++) | |
616 | regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); | |
617 | regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); | |
618 | for (i = 0; i < 16; i++) | |
619 | regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); | |
620 | regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); | |
621 | for (i = 0; i < 8; i++) | |
622 | regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); | |
623 | regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); | |
624 | ||
625 | /* Wake Up */ | |
626 | regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); | |
627 | regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); | |
628 | regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); | |
629 | regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); | |
630 | regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); | |
631 | regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); | |
632 | regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); | |
633 | regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); | |
11afc1b1 | 634 | regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); |
9a799d71 | 635 | |
673ac604 | 636 | /* DCB */ |
9a799d71 AK |
637 | regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); |
638 | regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); | |
639 | regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); | |
640 | regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); | |
641 | for (i = 0; i < 8; i++) | |
642 | regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); | |
643 | for (i = 0; i < 8; i++) | |
644 | regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); | |
645 | for (i = 0; i < 8; i++) | |
646 | regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); | |
647 | for (i = 0; i < 8; i++) | |
648 | regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); | |
649 | for (i = 0; i < 8; i++) | |
650 | regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); | |
651 | for (i = 0; i < 8; i++) | |
652 | regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); | |
653 | ||
654 | /* Statistics */ | |
655 | regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); | |
656 | regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); | |
657 | regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); | |
658 | regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); | |
659 | for (i = 0; i < 8; i++) | |
660 | regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); | |
661 | regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); | |
662 | regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); | |
663 | regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); | |
664 | regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); | |
665 | regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); | |
666 | regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); | |
667 | regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); | |
668 | for (i = 0; i < 8; i++) | |
669 | regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); | |
670 | for (i = 0; i < 8; i++) | |
671 | regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); | |
672 | for (i = 0; i < 8; i++) | |
673 | regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); | |
674 | for (i = 0; i < 8; i++) | |
675 | regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); | |
676 | regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); | |
677 | regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); | |
678 | regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); | |
679 | regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); | |
680 | regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); | |
681 | regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); | |
682 | regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); | |
683 | regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); | |
684 | regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); | |
685 | regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); | |
686 | regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); | |
687 | regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); | |
688 | for (i = 0; i < 8; i++) | |
689 | regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); | |
690 | regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); | |
691 | regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); | |
692 | regs_buff[956] = IXGBE_GET_STAT(adapter, roc); | |
693 | regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); | |
694 | regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); | |
695 | regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); | |
696 | regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); | |
697 | regs_buff[961] = IXGBE_GET_STAT(adapter, tor); | |
698 | regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); | |
699 | regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); | |
700 | regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); | |
701 | regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); | |
702 | regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); | |
703 | regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); | |
704 | regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); | |
705 | regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); | |
706 | regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); | |
707 | regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); | |
708 | regs_buff[973] = IXGBE_GET_STAT(adapter, xec); | |
709 | for (i = 0; i < 16; i++) | |
710 | regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); | |
711 | for (i = 0; i < 16; i++) | |
712 | regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); | |
713 | for (i = 0; i < 16; i++) | |
714 | regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); | |
715 | for (i = 0; i < 16; i++) | |
716 | regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); | |
717 | ||
718 | /* MAC */ | |
719 | regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); | |
720 | regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | |
721 | regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | |
722 | regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); | |
723 | regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); | |
724 | regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | |
725 | regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | |
726 | regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); | |
727 | regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); | |
728 | regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
729 | regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); | |
730 | regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); | |
731 | regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); | |
732 | regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); | |
733 | regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); | |
734 | regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); | |
735 | regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
736 | regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); | |
737 | regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); | |
738 | regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
739 | regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); | |
740 | regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); | |
741 | regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); | |
742 | regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); | |
743 | regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); | |
744 | regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); | |
745 | regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
746 | regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
747 | regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
748 | regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); | |
749 | regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); | |
750 | regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); | |
751 | regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
752 | ||
753 | /* Diagnostic */ | |
754 | regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); | |
755 | for (i = 0; i < 8; i++) | |
98c00a1c | 756 | regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); |
9a799d71 | 757 | regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); |
98c00a1c JB |
758 | for (i = 0; i < 4; i++) |
759 | regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); | |
9a799d71 AK |
760 | regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); |
761 | regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); | |
762 | for (i = 0; i < 8; i++) | |
98c00a1c | 763 | regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); |
9a799d71 | 764 | regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); |
98c00a1c JB |
765 | for (i = 0; i < 4; i++) |
766 | regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); | |
9a799d71 AK |
767 | regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); |
768 | regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); | |
769 | regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); | |
770 | regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); | |
771 | regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); | |
772 | regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); | |
773 | regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); | |
774 | regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); | |
775 | regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); | |
776 | regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); | |
777 | regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); | |
778 | for (i = 0; i < 8; i++) | |
98c00a1c | 779 | regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); |
9a799d71 AK |
780 | regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); |
781 | regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); | |
782 | regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); | |
783 | regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); | |
784 | regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); | |
785 | regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); | |
786 | regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); | |
787 | regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); | |
788 | regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); | |
789 | } | |
790 | ||
791 | static int ixgbe_get_eeprom_len(struct net_device *netdev) | |
792 | { | |
793 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
794 | return adapter->hw.eeprom.word_size * 2; | |
795 | } | |
796 | ||
797 | static int ixgbe_get_eeprom(struct net_device *netdev, | |
b4617240 | 798 | struct ethtool_eeprom *eeprom, u8 *bytes) |
9a799d71 AK |
799 | { |
800 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
801 | struct ixgbe_hw *hw = &adapter->hw; | |
802 | u16 *eeprom_buff; | |
803 | int first_word, last_word, eeprom_len; | |
804 | int ret_val = 0; | |
805 | u16 i; | |
806 | ||
807 | if (eeprom->len == 0) | |
808 | return -EINVAL; | |
809 | ||
810 | eeprom->magic = hw->vendor_id | (hw->device_id << 16); | |
811 | ||
812 | first_word = eeprom->offset >> 1; | |
813 | last_word = (eeprom->offset + eeprom->len - 1) >> 1; | |
814 | eeprom_len = last_word - first_word + 1; | |
815 | ||
816 | eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); | |
817 | if (!eeprom_buff) | |
818 | return -ENOMEM; | |
819 | ||
820 | for (i = 0; i < eeprom_len; i++) { | |
c44ade9e | 821 | if ((ret_val = hw->eeprom.ops.read(hw, first_word + i, |
b4617240 | 822 | &eeprom_buff[i]))) |
9a799d71 AK |
823 | break; |
824 | } | |
825 | ||
826 | /* Device's eeprom is always little-endian, word addressable */ | |
827 | for (i = 0; i < eeprom_len; i++) | |
828 | le16_to_cpus(&eeprom_buff[i]); | |
829 | ||
830 | memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); | |
831 | kfree(eeprom_buff); | |
832 | ||
833 | return ret_val; | |
834 | } | |
835 | ||
836 | static void ixgbe_get_drvinfo(struct net_device *netdev, | |
b4617240 | 837 | struct ethtool_drvinfo *drvinfo) |
9a799d71 AK |
838 | { |
839 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
34b0368c | 840 | char firmware_version[32]; |
9a799d71 | 841 | |
083fc582 DS |
842 | strncpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); |
843 | strncpy(drvinfo->version, ixgbe_driver_version, | |
844 | sizeof(drvinfo->version)); | |
845 | ||
846 | snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d", | |
847 | (adapter->eeprom_version & 0xF000) >> 12, | |
848 | (adapter->eeprom_version & 0x0FF0) >> 4, | |
849 | adapter->eeprom_version & 0x000F); | |
850 | ||
851 | strncpy(drvinfo->fw_version, firmware_version, | |
852 | sizeof(drvinfo->fw_version)); | |
853 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), | |
854 | sizeof(drvinfo->bus_info)); | |
9a799d71 | 855 | drvinfo->n_stats = IXGBE_STATS_LEN; |
da4dd0f7 | 856 | drvinfo->testinfo_len = IXGBE_TEST_LEN; |
9a799d71 AK |
857 | drvinfo->regdump_len = ixgbe_get_regs_len(netdev); |
858 | } | |
859 | ||
860 | static void ixgbe_get_ringparam(struct net_device *netdev, | |
b4617240 | 861 | struct ethtool_ringparam *ring) |
9a799d71 AK |
862 | { |
863 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4a0b9ca0 PW |
864 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; |
865 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; | |
9a799d71 AK |
866 | |
867 | ring->rx_max_pending = IXGBE_MAX_RXD; | |
868 | ring->tx_max_pending = IXGBE_MAX_TXD; | |
869 | ring->rx_mini_max_pending = 0; | |
870 | ring->rx_jumbo_max_pending = 0; | |
871 | ring->rx_pending = rx_ring->count; | |
872 | ring->tx_pending = tx_ring->count; | |
873 | ring->rx_mini_pending = 0; | |
874 | ring->rx_jumbo_pending = 0; | |
875 | } | |
876 | ||
877 | static int ixgbe_set_ringparam(struct net_device *netdev, | |
b4617240 | 878 | struct ethtool_ringparam *ring) |
9a799d71 AK |
879 | { |
880 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
f9ed8854 | 881 | struct ixgbe_ring *temp_tx_ring, *temp_rx_ring; |
759884b4 | 882 | int i, err = 0; |
c431f97e | 883 | u32 new_rx_count, new_tx_count; |
f9ed8854 | 884 | bool need_update = false; |
9a799d71 AK |
885 | |
886 | if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) | |
887 | return -EINVAL; | |
888 | ||
889 | new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD); | |
890 | new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD); | |
891 | new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); | |
892 | ||
893 | new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD); | |
894 | new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD); | |
895 | new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); | |
896 | ||
4a0b9ca0 PW |
897 | if ((new_tx_count == adapter->tx_ring[0]->count) && |
898 | (new_rx_count == adapter->rx_ring[0]->count)) { | |
9a799d71 AK |
899 | /* nothing to do */ |
900 | return 0; | |
901 | } | |
902 | ||
d4f80882 AV |
903 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
904 | msleep(1); | |
905 | ||
759884b4 AD |
906 | if (!netif_running(adapter->netdev)) { |
907 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 908 | adapter->tx_ring[i]->count = new_tx_count; |
759884b4 | 909 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 910 | adapter->rx_ring[i]->count = new_rx_count; |
759884b4 AD |
911 | adapter->tx_ring_count = new_tx_count; |
912 | adapter->rx_ring_count = new_rx_count; | |
4a0b9ca0 | 913 | goto clear_reset; |
759884b4 AD |
914 | } |
915 | ||
4a0b9ca0 | 916 | temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring)); |
f9ed8854 MC |
917 | if (!temp_tx_ring) { |
918 | err = -ENOMEM; | |
4a0b9ca0 | 919 | goto clear_reset; |
f9ed8854 MC |
920 | } |
921 | ||
922 | if (new_tx_count != adapter->tx_ring_count) { | |
9a799d71 | 923 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
924 | memcpy(&temp_tx_ring[i], adapter->tx_ring[i], |
925 | sizeof(struct ixgbe_ring)); | |
f9ed8854 | 926 | temp_tx_ring[i].count = new_tx_count; |
b6ec895e | 927 | err = ixgbe_setup_tx_resources(&temp_tx_ring[i]); |
9a799d71 | 928 | if (err) { |
c431f97e JB |
929 | while (i) { |
930 | i--; | |
b6ec895e | 931 | ixgbe_free_tx_resources(&temp_tx_ring[i]); |
c431f97e | 932 | } |
4a0b9ca0 | 933 | goto clear_reset; |
9a799d71 | 934 | } |
9a799d71 | 935 | } |
f9ed8854 | 936 | need_update = true; |
9a799d71 AK |
937 | } |
938 | ||
4a0b9ca0 PW |
939 | temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring)); |
940 | if (!temp_rx_ring) { | |
f9ed8854 MC |
941 | err = -ENOMEM; |
942 | goto err_setup; | |
d3fa4721 | 943 | } |
9a799d71 | 944 | |
f9ed8854 | 945 | if (new_rx_count != adapter->rx_ring_count) { |
c431f97e | 946 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
947 | memcpy(&temp_rx_ring[i], adapter->rx_ring[i], |
948 | sizeof(struct ixgbe_ring)); | |
f9ed8854 | 949 | temp_rx_ring[i].count = new_rx_count; |
b6ec895e | 950 | err = ixgbe_setup_rx_resources(&temp_rx_ring[i]); |
9a799d71 | 951 | if (err) { |
c431f97e JB |
952 | while (i) { |
953 | i--; | |
b6ec895e | 954 | ixgbe_free_rx_resources(&temp_rx_ring[i]); |
c431f97e | 955 | } |
9a799d71 AK |
956 | goto err_setup; |
957 | } | |
9a799d71 | 958 | } |
f9ed8854 MC |
959 | need_update = true; |
960 | } | |
961 | ||
962 | /* if rings need to be updated, here's the place to do it in one shot */ | |
963 | if (need_update) { | |
759884b4 | 964 | ixgbe_down(adapter); |
f9ed8854 MC |
965 | |
966 | /* tx */ | |
967 | if (new_tx_count != adapter->tx_ring_count) { | |
4a0b9ca0 | 968 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b6ec895e | 969 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
4a0b9ca0 PW |
970 | memcpy(adapter->tx_ring[i], &temp_tx_ring[i], |
971 | sizeof(struct ixgbe_ring)); | |
972 | } | |
f9ed8854 MC |
973 | adapter->tx_ring_count = new_tx_count; |
974 | } | |
975 | ||
976 | /* rx */ | |
977 | if (new_rx_count != adapter->rx_ring_count) { | |
4a0b9ca0 | 978 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b6ec895e | 979 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
4a0b9ca0 PW |
980 | memcpy(adapter->rx_ring[i], &temp_rx_ring[i], |
981 | sizeof(struct ixgbe_ring)); | |
982 | } | |
f9ed8854 MC |
983 | adapter->rx_ring_count = new_rx_count; |
984 | } | |
f9ed8854 | 985 | ixgbe_up(adapter); |
759884b4 | 986 | } |
4a0b9ca0 PW |
987 | |
988 | vfree(temp_rx_ring); | |
f9ed8854 | 989 | err_setup: |
4a0b9ca0 PW |
990 | vfree(temp_tx_ring); |
991 | clear_reset: | |
d4f80882 | 992 | clear_bit(__IXGBE_RESETTING, &adapter->state); |
9a799d71 AK |
993 | return err; |
994 | } | |
995 | ||
b9f2c044 | 996 | static int ixgbe_get_sset_count(struct net_device *netdev, int sset) |
9a799d71 | 997 | { |
b9f2c044 | 998 | switch (sset) { |
da4dd0f7 PWJ |
999 | case ETH_SS_TEST: |
1000 | return IXGBE_TEST_LEN; | |
b9f2c044 JG |
1001 | case ETH_SS_STATS: |
1002 | return IXGBE_STATS_LEN; | |
9a713e7c | 1003 | case ETH_SS_NTUPLE_FILTERS: |
807540ba ED |
1004 | return ETHTOOL_MAX_NTUPLE_LIST_ENTRY * |
1005 | ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY; | |
b9f2c044 JG |
1006 | default: |
1007 | return -EOPNOTSUPP; | |
1008 | } | |
9a799d71 AK |
1009 | } |
1010 | ||
1011 | static void ixgbe_get_ethtool_stats(struct net_device *netdev, | |
b4617240 | 1012 | struct ethtool_stats *stats, u64 *data) |
9a799d71 AK |
1013 | { |
1014 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
28172739 ED |
1015 | struct rtnl_link_stats64 temp; |
1016 | const struct rtnl_link_stats64 *net_stats; | |
de1036b1 ED |
1017 | unsigned int start; |
1018 | struct ixgbe_ring *ring; | |
1019 | int i, j; | |
29c3a050 | 1020 | char *p = NULL; |
9a799d71 AK |
1021 | |
1022 | ixgbe_update_stats(adapter); | |
28172739 | 1023 | net_stats = dev_get_stats(netdev, &temp); |
9a799d71 | 1024 | for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { |
29c3a050 AK |
1025 | switch (ixgbe_gstrings_stats[i].type) { |
1026 | case NETDEV_STATS: | |
28172739 | 1027 | p = (char *) net_stats + |
29c3a050 AK |
1028 | ixgbe_gstrings_stats[i].stat_offset; |
1029 | break; | |
1030 | case IXGBE_STATS: | |
1031 | p = (char *) adapter + | |
1032 | ixgbe_gstrings_stats[i].stat_offset; | |
1033 | break; | |
1034 | } | |
1035 | ||
9a799d71 | 1036 | data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == |
b4617240 | 1037 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; |
9a799d71 AK |
1038 | } |
1039 | for (j = 0; j < adapter->num_tx_queues; j++) { | |
de1036b1 ED |
1040 | ring = adapter->tx_ring[j]; |
1041 | do { | |
1042 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
1043 | data[i] = ring->stats.packets; | |
1044 | data[i+1] = ring->stats.bytes; | |
1045 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
1046 | i += 2; | |
9a799d71 AK |
1047 | } |
1048 | for (j = 0; j < adapter->num_rx_queues; j++) { | |
de1036b1 ED |
1049 | ring = adapter->rx_ring[j]; |
1050 | do { | |
1051 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
1052 | data[i] = ring->stats.packets; | |
1053 | data[i+1] = ring->stats.bytes; | |
1054 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
1055 | i += 2; | |
9a799d71 | 1056 | } |
2f90b865 AD |
1057 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1058 | for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) { | |
1059 | data[i++] = adapter->stats.pxontxc[j]; | |
1060 | data[i++] = adapter->stats.pxofftxc[j]; | |
1061 | } | |
1062 | for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) { | |
1063 | data[i++] = adapter->stats.pxonrxc[j]; | |
1064 | data[i++] = adapter->stats.pxoffrxc[j]; | |
1065 | } | |
1066 | } | |
9a799d71 AK |
1067 | } |
1068 | ||
1069 | static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, | |
b4617240 | 1070 | u8 *data) |
9a799d71 AK |
1071 | { |
1072 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e | 1073 | char *p = (char *)data; |
9a799d71 AK |
1074 | int i; |
1075 | ||
1076 | switch (stringset) { | |
da4dd0f7 PWJ |
1077 | case ETH_SS_TEST: |
1078 | memcpy(data, *ixgbe_gstrings_test, | |
1079 | IXGBE_TEST_LEN * ETH_GSTRING_LEN); | |
1080 | break; | |
9a799d71 AK |
1081 | case ETH_SS_STATS: |
1082 | for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { | |
1083 | memcpy(p, ixgbe_gstrings_stats[i].stat_string, | |
1084 | ETH_GSTRING_LEN); | |
1085 | p += ETH_GSTRING_LEN; | |
1086 | } | |
1087 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1088 | sprintf(p, "tx_queue_%u_packets", i); | |
1089 | p += ETH_GSTRING_LEN; | |
1090 | sprintf(p, "tx_queue_%u_bytes", i); | |
1091 | p += ETH_GSTRING_LEN; | |
1092 | } | |
1093 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1094 | sprintf(p, "rx_queue_%u_packets", i); | |
1095 | p += ETH_GSTRING_LEN; | |
1096 | sprintf(p, "rx_queue_%u_bytes", i); | |
1097 | p += ETH_GSTRING_LEN; | |
1098 | } | |
2f90b865 AD |
1099 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1100 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
1101 | sprintf(p, "tx_pb_%u_pxon", i); | |
bfb8cc31 DS |
1102 | p += ETH_GSTRING_LEN; |
1103 | sprintf(p, "tx_pb_%u_pxoff", i); | |
1104 | p += ETH_GSTRING_LEN; | |
2f90b865 AD |
1105 | } |
1106 | for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) { | |
bfb8cc31 DS |
1107 | sprintf(p, "rx_pb_%u_pxon", i); |
1108 | p += ETH_GSTRING_LEN; | |
1109 | sprintf(p, "rx_pb_%u_pxoff", i); | |
1110 | p += ETH_GSTRING_LEN; | |
2f90b865 AD |
1111 | } |
1112 | } | |
b4617240 | 1113 | /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ |
9a799d71 AK |
1114 | break; |
1115 | } | |
1116 | } | |
1117 | ||
da4dd0f7 PWJ |
1118 | static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) |
1119 | { | |
1120 | struct ixgbe_hw *hw = &adapter->hw; | |
1121 | bool link_up; | |
1122 | u32 link_speed = 0; | |
1123 | *data = 0; | |
1124 | ||
1125 | hw->mac.ops.check_link(hw, &link_speed, &link_up, true); | |
1126 | if (link_up) | |
1127 | return *data; | |
1128 | else | |
1129 | *data = 1; | |
1130 | return *data; | |
1131 | } | |
1132 | ||
1133 | /* ethtool register test data */ | |
1134 | struct ixgbe_reg_test { | |
1135 | u16 reg; | |
1136 | u8 array_len; | |
1137 | u8 test_type; | |
1138 | u32 mask; | |
1139 | u32 write; | |
1140 | }; | |
1141 | ||
1142 | /* In the hardware, registers are laid out either singly, in arrays | |
1143 | * spaced 0x40 bytes apart, or in contiguous tables. We assume | |
1144 | * most tests take place on arrays or single registers (handled | |
1145 | * as a single-element array) and special-case the tables. | |
1146 | * Table tests are always pattern tests. | |
1147 | * | |
1148 | * We also make provision for some required setup steps by specifying | |
1149 | * registers to be written without any read-back testing. | |
1150 | */ | |
1151 | ||
1152 | #define PATTERN_TEST 1 | |
1153 | #define SET_READ_TEST 2 | |
1154 | #define WRITE_NO_TEST 3 | |
1155 | #define TABLE32_TEST 4 | |
1156 | #define TABLE64_TEST_LO 5 | |
1157 | #define TABLE64_TEST_HI 6 | |
1158 | ||
1159 | /* default 82599 register test */ | |
66744500 | 1160 | static const struct ixgbe_reg_test reg_test_82599[] = { |
da4dd0f7 PWJ |
1161 | { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, |
1162 | { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1163 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1164 | { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, | |
1165 | { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, | |
1166 | { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1167 | { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1168 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, | |
1169 | { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1170 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, | |
1171 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1172 | { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1173 | { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1174 | { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1175 | { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, | |
1176 | { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, | |
1177 | { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1178 | { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, | |
1179 | { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1180 | { 0, 0, 0, 0 } | |
1181 | }; | |
1182 | ||
1183 | /* default 82598 register test */ | |
66744500 | 1184 | static const struct ixgbe_reg_test reg_test_82598[] = { |
da4dd0f7 PWJ |
1185 | { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, |
1186 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1187 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1188 | { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, | |
1189 | { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1190 | { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1191 | { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1192 | /* Enable all four RX queues before testing. */ | |
1193 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, | |
1194 | /* RDH is read-only for 82598, only test RDT. */ | |
1195 | { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1196 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, | |
1197 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1198 | { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1199 | { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, | |
1200 | { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1201 | { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1202 | { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1203 | { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, | |
1204 | { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, | |
1205 | { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1206 | { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, | |
1207 | { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1208 | { 0, 0, 0, 0 } | |
1209 | }; | |
1210 | ||
66744500 JK |
1211 | static const u32 register_test_patterns[] = { |
1212 | 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF | |
1213 | }; | |
1214 | ||
da4dd0f7 PWJ |
1215 | #define REG_PATTERN_TEST(R, M, W) \ |
1216 | { \ | |
1217 | u32 pat, val, before; \ | |
66744500 | 1218 | for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) { \ |
da4dd0f7 | 1219 | before = readl(adapter->hw.hw_addr + R); \ |
66744500 JK |
1220 | writel((register_test_patterns[pat] & W), \ |
1221 | (adapter->hw.hw_addr + R)); \ | |
da4dd0f7 | 1222 | val = readl(adapter->hw.hw_addr + R); \ |
66744500 JK |
1223 | if (val != (register_test_patterns[pat] & W & M)) { \ |
1224 | e_err(drv, "pattern test reg %04X failed: got " \ | |
1225 | "0x%08X expected 0x%08X\n", \ | |
1226 | R, val, (register_test_patterns[pat] & W & M)); \ | |
da4dd0f7 PWJ |
1227 | *data = R; \ |
1228 | writel(before, adapter->hw.hw_addr + R); \ | |
1229 | return 1; \ | |
1230 | } \ | |
1231 | writel(before, adapter->hw.hw_addr + R); \ | |
1232 | } \ | |
1233 | } | |
1234 | ||
1235 | #define REG_SET_AND_CHECK(R, M, W) \ | |
1236 | { \ | |
1237 | u32 val, before; \ | |
1238 | before = readl(adapter->hw.hw_addr + R); \ | |
1239 | writel((W & M), (adapter->hw.hw_addr + R)); \ | |
1240 | val = readl(adapter->hw.hw_addr + R); \ | |
1241 | if ((W & M) != (val & M)) { \ | |
396e799c ET |
1242 | e_err(drv, "set/check reg %04X test failed: got 0x%08X " \ |
1243 | "expected 0x%08X\n", R, (val & M), (W & M)); \ | |
da4dd0f7 PWJ |
1244 | *data = R; \ |
1245 | writel(before, (adapter->hw.hw_addr + R)); \ | |
1246 | return 1; \ | |
1247 | } \ | |
1248 | writel(before, (adapter->hw.hw_addr + R)); \ | |
1249 | } | |
1250 | ||
1251 | static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) | |
1252 | { | |
66744500 | 1253 | const struct ixgbe_reg_test *test; |
da4dd0f7 PWJ |
1254 | u32 value, before, after; |
1255 | u32 i, toggle; | |
1256 | ||
bd508178 AD |
1257 | switch (adapter->hw.mac.type) { |
1258 | case ixgbe_mac_82598EB: | |
da4dd0f7 PWJ |
1259 | toggle = 0x7FFFF3FF; |
1260 | test = reg_test_82598; | |
bd508178 AD |
1261 | break; |
1262 | case ixgbe_mac_82599EB: | |
b93a2226 | 1263 | case ixgbe_mac_X540: |
bd508178 AD |
1264 | toggle = 0x7FFFF30F; |
1265 | test = reg_test_82599; | |
1266 | break; | |
1267 | default: | |
1268 | *data = 1; | |
1269 | return 1; | |
1270 | break; | |
da4dd0f7 PWJ |
1271 | } |
1272 | ||
1273 | /* | |
1274 | * Because the status register is such a special case, | |
1275 | * we handle it separately from the rest of the register | |
1276 | * tests. Some bits are read-only, some toggle, and some | |
1277 | * are writeable on newer MACs. | |
1278 | */ | |
1279 | before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS); | |
1280 | value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle); | |
1281 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle); | |
1282 | after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle; | |
1283 | if (value != after) { | |
396e799c ET |
1284 | e_err(drv, "failed STATUS register test got: 0x%08X " |
1285 | "expected: 0x%08X\n", after, value); | |
da4dd0f7 PWJ |
1286 | *data = 1; |
1287 | return 1; | |
1288 | } | |
1289 | /* restore previous status */ | |
1290 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before); | |
1291 | ||
1292 | /* | |
1293 | * Perform the remainder of the register test, looping through | |
1294 | * the test table until we either fail or reach the null entry. | |
1295 | */ | |
1296 | while (test->reg) { | |
1297 | for (i = 0; i < test->array_len; i++) { | |
1298 | switch (test->test_type) { | |
1299 | case PATTERN_TEST: | |
1300 | REG_PATTERN_TEST(test->reg + (i * 0x40), | |
1301 | test->mask, | |
1302 | test->write); | |
1303 | break; | |
1304 | case SET_READ_TEST: | |
1305 | REG_SET_AND_CHECK(test->reg + (i * 0x40), | |
1306 | test->mask, | |
1307 | test->write); | |
1308 | break; | |
1309 | case WRITE_NO_TEST: | |
1310 | writel(test->write, | |
1311 | (adapter->hw.hw_addr + test->reg) | |
1312 | + (i * 0x40)); | |
1313 | break; | |
1314 | case TABLE32_TEST: | |
1315 | REG_PATTERN_TEST(test->reg + (i * 4), | |
1316 | test->mask, | |
1317 | test->write); | |
1318 | break; | |
1319 | case TABLE64_TEST_LO: | |
1320 | REG_PATTERN_TEST(test->reg + (i * 8), | |
1321 | test->mask, | |
1322 | test->write); | |
1323 | break; | |
1324 | case TABLE64_TEST_HI: | |
1325 | REG_PATTERN_TEST((test->reg + 4) + (i * 8), | |
1326 | test->mask, | |
1327 | test->write); | |
1328 | break; | |
1329 | } | |
1330 | } | |
1331 | test++; | |
1332 | } | |
1333 | ||
1334 | *data = 0; | |
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) | |
1339 | { | |
1340 | struct ixgbe_hw *hw = &adapter->hw; | |
1341 | if (hw->eeprom.ops.validate_checksum(hw, NULL)) | |
1342 | *data = 1; | |
1343 | else | |
1344 | *data = 0; | |
1345 | return *data; | |
1346 | } | |
1347 | ||
1348 | static irqreturn_t ixgbe_test_intr(int irq, void *data) | |
1349 | { | |
1350 | struct net_device *netdev = (struct net_device *) data; | |
1351 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1352 | ||
1353 | adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); | |
1354 | ||
1355 | return IRQ_HANDLED; | |
1356 | } | |
1357 | ||
1358 | static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) | |
1359 | { | |
1360 | struct net_device *netdev = adapter->netdev; | |
1361 | u32 mask, i = 0, shared_int = true; | |
1362 | u32 irq = adapter->pdev->irq; | |
1363 | ||
1364 | *data = 0; | |
1365 | ||
1366 | /* Hook up test interrupt handler just for this test */ | |
1367 | if (adapter->msix_entries) { | |
1368 | /* NOTE: we don't test MSI-X interrupts here, yet */ | |
1369 | return 0; | |
1370 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1371 | shared_int = false; | |
a0607fd3 | 1372 | if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, |
da4dd0f7 PWJ |
1373 | netdev)) { |
1374 | *data = 1; | |
1375 | return -1; | |
1376 | } | |
a0607fd3 | 1377 | } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, |
da4dd0f7 PWJ |
1378 | netdev->name, netdev)) { |
1379 | shared_int = false; | |
a0607fd3 | 1380 | } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, |
da4dd0f7 PWJ |
1381 | netdev->name, netdev)) { |
1382 | *data = 1; | |
1383 | return -1; | |
1384 | } | |
396e799c ET |
1385 | e_info(hw, "testing %s interrupt\n", shared_int ? |
1386 | "shared" : "unshared"); | |
da4dd0f7 PWJ |
1387 | |
1388 | /* Disable all the interrupts */ | |
1389 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); | |
1390 | msleep(10); | |
1391 | ||
1392 | /* Test each interrupt */ | |
1393 | for (; i < 10; i++) { | |
1394 | /* Interrupt to test */ | |
1395 | mask = 1 << i; | |
1396 | ||
1397 | if (!shared_int) { | |
1398 | /* | |
1399 | * Disable the interrupts to be reported in | |
1400 | * the cause register and then force the same | |
1401 | * interrupt and see if one gets posted. If | |
1402 | * an interrupt was posted to the bus, the | |
1403 | * test failed. | |
1404 | */ | |
1405 | adapter->test_icr = 0; | |
1406 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, | |
1407 | ~mask & 0x00007FFF); | |
1408 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
1409 | ~mask & 0x00007FFF); | |
1410 | msleep(10); | |
1411 | ||
1412 | if (adapter->test_icr & mask) { | |
1413 | *data = 3; | |
1414 | break; | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | /* | |
1419 | * Enable the interrupt to be reported in the cause | |
1420 | * register and then force the same interrupt and see | |
1421 | * if one gets posted. If an interrupt was not posted | |
1422 | * to the bus, the test failed. | |
1423 | */ | |
1424 | adapter->test_icr = 0; | |
1425 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1426 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
1427 | msleep(10); | |
1428 | ||
1429 | if (!(adapter->test_icr &mask)) { | |
1430 | *data = 4; | |
1431 | break; | |
1432 | } | |
1433 | ||
1434 | if (!shared_int) { | |
1435 | /* | |
1436 | * Disable the other interrupts to be reported in | |
1437 | * the cause register and then force the other | |
1438 | * interrupts and see if any get posted. If | |
1439 | * an interrupt was posted to the bus, the | |
1440 | * test failed. | |
1441 | */ | |
1442 | adapter->test_icr = 0; | |
1443 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, | |
1444 | ~mask & 0x00007FFF); | |
1445 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
1446 | ~mask & 0x00007FFF); | |
1447 | msleep(10); | |
1448 | ||
1449 | if (adapter->test_icr) { | |
1450 | *data = 5; | |
1451 | break; | |
1452 | } | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | /* Disable all the interrupts */ | |
1457 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); | |
1458 | msleep(10); | |
1459 | ||
1460 | /* Unhook test interrupt handler */ | |
1461 | free_irq(irq, netdev); | |
1462 | ||
1463 | return *data; | |
1464 | } | |
1465 | ||
1466 | static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) | |
1467 | { | |
1468 | struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; | |
1469 | struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; | |
1470 | struct ixgbe_hw *hw = &adapter->hw; | |
da4dd0f7 | 1471 | u32 reg_ctl; |
da4dd0f7 PWJ |
1472 | |
1473 | /* shut down the DMA engines now so they can be reinitialized later */ | |
1474 | ||
1475 | /* first Rx */ | |
1476 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1477 | reg_ctl &= ~IXGBE_RXCTRL_RXEN; | |
1478 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); | |
84418e3b | 1479 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx)); |
da4dd0f7 | 1480 | reg_ctl &= ~IXGBE_RXDCTL_ENABLE; |
84418e3b | 1481 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl); |
da4dd0f7 PWJ |
1482 | |
1483 | /* now Tx */ | |
84418e3b | 1484 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); |
da4dd0f7 | 1485 | reg_ctl &= ~IXGBE_TXDCTL_ENABLE; |
84418e3b AD |
1486 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); |
1487 | ||
bd508178 AD |
1488 | switch (hw->mac.type) { |
1489 | case ixgbe_mac_82599EB: | |
b93a2226 | 1490 | case ixgbe_mac_X540: |
da4dd0f7 PWJ |
1491 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); |
1492 | reg_ctl &= ~IXGBE_DMATXCTL_TE; | |
1493 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); | |
bd508178 AD |
1494 | break; |
1495 | default: | |
1496 | break; | |
da4dd0f7 PWJ |
1497 | } |
1498 | ||
1499 | ixgbe_reset(adapter); | |
1500 | ||
b6ec895e AD |
1501 | ixgbe_free_tx_resources(&adapter->test_tx_ring); |
1502 | ixgbe_free_rx_resources(&adapter->test_rx_ring); | |
da4dd0f7 PWJ |
1503 | } |
1504 | ||
1505 | static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) | |
1506 | { | |
1507 | struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; | |
1508 | struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; | |
da4dd0f7 | 1509 | u32 rctl, reg_data; |
84418e3b AD |
1510 | int ret_val; |
1511 | int err; | |
da4dd0f7 PWJ |
1512 | |
1513 | /* Setup Tx descriptor ring and Tx buffers */ | |
84418e3b AD |
1514 | tx_ring->count = IXGBE_DEFAULT_TXD; |
1515 | tx_ring->queue_index = 0; | |
b6ec895e | 1516 | tx_ring->dev = &adapter->pdev->dev; |
fc77dc3c | 1517 | tx_ring->netdev = adapter->netdev; |
84418e3b AD |
1518 | tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; |
1519 | tx_ring->numa_node = adapter->node; | |
da4dd0f7 | 1520 | |
b6ec895e | 1521 | err = ixgbe_setup_tx_resources(tx_ring); |
84418e3b AD |
1522 | if (err) |
1523 | return 1; | |
da4dd0f7 | 1524 | |
bd508178 AD |
1525 | switch (adapter->hw.mac.type) { |
1526 | case ixgbe_mac_82599EB: | |
b93a2226 | 1527 | case ixgbe_mac_X540: |
da4dd0f7 PWJ |
1528 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); |
1529 | reg_data |= IXGBE_DMATXCTL_TE; | |
1530 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); | |
bd508178 AD |
1531 | break; |
1532 | default: | |
1533 | break; | |
da4dd0f7 | 1534 | } |
f4ec443b | 1535 | |
84418e3b | 1536 | ixgbe_configure_tx_ring(adapter, tx_ring); |
da4dd0f7 PWJ |
1537 | |
1538 | /* Setup Rx Descriptor ring and Rx buffers */ | |
84418e3b AD |
1539 | rx_ring->count = IXGBE_DEFAULT_RXD; |
1540 | rx_ring->queue_index = 0; | |
b6ec895e | 1541 | rx_ring->dev = &adapter->pdev->dev; |
fc77dc3c | 1542 | rx_ring->netdev = adapter->netdev; |
84418e3b AD |
1543 | rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; |
1544 | rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048; | |
1545 | rx_ring->numa_node = adapter->node; | |
1546 | ||
b6ec895e | 1547 | err = ixgbe_setup_rx_resources(rx_ring); |
84418e3b | 1548 | if (err) { |
da4dd0f7 PWJ |
1549 | ret_val = 4; |
1550 | goto err_nomem; | |
1551 | } | |
1552 | ||
da4dd0f7 PWJ |
1553 | rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); |
1554 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); | |
da4dd0f7 | 1555 | |
84418e3b | 1556 | ixgbe_configure_rx_ring(adapter, rx_ring); |
da4dd0f7 PWJ |
1557 | |
1558 | rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; | |
1559 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); | |
1560 | ||
da4dd0f7 PWJ |
1561 | return 0; |
1562 | ||
1563 | err_nomem: | |
1564 | ixgbe_free_desc_rings(adapter); | |
1565 | return ret_val; | |
1566 | } | |
1567 | ||
1568 | static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) | |
1569 | { | |
1570 | struct ixgbe_hw *hw = &adapter->hw; | |
1571 | u32 reg_data; | |
1572 | ||
1573 | /* right now we only support MAC loopback in the driver */ | |
da4dd0f7 | 1574 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); |
84418e3b | 1575 | /* Setup MAC loopback */ |
da4dd0f7 PWJ |
1576 | reg_data |= IXGBE_HLREG0_LPBK; |
1577 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); | |
1578 | ||
84418e3b AD |
1579 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); |
1580 | reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; | |
1581 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data); | |
1582 | ||
da4dd0f7 PWJ |
1583 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC); |
1584 | reg_data &= ~IXGBE_AUTOC_LMS_MASK; | |
1585 | reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU; | |
1586 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data); | |
84418e3b AD |
1587 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1588 | msleep(10); | |
da4dd0f7 PWJ |
1589 | |
1590 | /* Disable Atlas Tx lanes; re-enabled in reset path */ | |
1591 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
1592 | u8 atlas; | |
1593 | ||
1594 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); | |
1595 | atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; | |
1596 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); | |
1597 | ||
1598 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); | |
1599 | atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; | |
1600 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); | |
1601 | ||
1602 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); | |
1603 | atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; | |
1604 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); | |
1605 | ||
1606 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); | |
1607 | atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; | |
1608 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); | |
1609 | } | |
1610 | ||
1611 | return 0; | |
1612 | } | |
1613 | ||
1614 | static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) | |
1615 | { | |
1616 | u32 reg_data; | |
1617 | ||
1618 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); | |
1619 | reg_data &= ~IXGBE_HLREG0_LPBK; | |
1620 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); | |
1621 | } | |
1622 | ||
1623 | static void ixgbe_create_lbtest_frame(struct sk_buff *skb, | |
1624 | unsigned int frame_size) | |
1625 | { | |
1626 | memset(skb->data, 0xFF, frame_size); | |
1627 | frame_size &= ~1; | |
1628 | memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); | |
1629 | memset(&skb->data[frame_size / 2 + 10], 0xBE, 1); | |
1630 | memset(&skb->data[frame_size / 2 + 12], 0xAF, 1); | |
1631 | } | |
1632 | ||
1633 | static int ixgbe_check_lbtest_frame(struct sk_buff *skb, | |
1634 | unsigned int frame_size) | |
1635 | { | |
1636 | frame_size &= ~1; | |
1637 | if (*(skb->data + 3) == 0xFF) { | |
1638 | if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && | |
1639 | (*(skb->data + frame_size / 2 + 12) == 0xAF)) { | |
1640 | return 0; | |
1641 | } | |
1642 | } | |
1643 | return 13; | |
1644 | } | |
1645 | ||
fc77dc3c | 1646 | static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, |
84418e3b AD |
1647 | struct ixgbe_ring *tx_ring, |
1648 | unsigned int size) | |
1649 | { | |
1650 | union ixgbe_adv_rx_desc *rx_desc; | |
1651 | struct ixgbe_rx_buffer *rx_buffer_info; | |
1652 | struct ixgbe_tx_buffer *tx_buffer_info; | |
1653 | const int bufsz = rx_ring->rx_buf_len; | |
1654 | u32 staterr; | |
1655 | u16 rx_ntc, tx_ntc, count = 0; | |
1656 | ||
1657 | /* initialize next to clean and descriptor values */ | |
1658 | rx_ntc = rx_ring->next_to_clean; | |
1659 | tx_ntc = tx_ring->next_to_clean; | |
1660 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc); | |
1661 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1662 | ||
1663 | while (staterr & IXGBE_RXD_STAT_DD) { | |
1664 | /* check Rx buffer */ | |
1665 | rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; | |
1666 | ||
1667 | /* unmap Rx buffer, will be remapped by alloc_rx_buffers */ | |
b6ec895e | 1668 | dma_unmap_single(rx_ring->dev, |
84418e3b AD |
1669 | rx_buffer_info->dma, |
1670 | bufsz, | |
1671 | DMA_FROM_DEVICE); | |
1672 | rx_buffer_info->dma = 0; | |
1673 | ||
1674 | /* verify contents of skb */ | |
1675 | if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size)) | |
1676 | count++; | |
1677 | ||
1678 | /* unmap buffer on Tx side */ | |
1679 | tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; | |
b6ec895e | 1680 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
84418e3b AD |
1681 | |
1682 | /* increment Rx/Tx next to clean counters */ | |
1683 | rx_ntc++; | |
1684 | if (rx_ntc == rx_ring->count) | |
1685 | rx_ntc = 0; | |
1686 | tx_ntc++; | |
1687 | if (tx_ntc == tx_ring->count) | |
1688 | tx_ntc = 0; | |
1689 | ||
1690 | /* fetch next descriptor */ | |
1691 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc); | |
1692 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1693 | } | |
1694 | ||
1695 | /* re-map buffers to ring, store next to clean values */ | |
fc77dc3c | 1696 | ixgbe_alloc_rx_buffers(rx_ring, count); |
84418e3b AD |
1697 | rx_ring->next_to_clean = rx_ntc; |
1698 | tx_ring->next_to_clean = tx_ntc; | |
1699 | ||
1700 | return count; | |
1701 | } | |
1702 | ||
da4dd0f7 PWJ |
1703 | static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) |
1704 | { | |
1705 | struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; | |
1706 | struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; | |
84418e3b AD |
1707 | int i, j, lc, good_cnt, ret_val = 0; |
1708 | unsigned int size = 1024; | |
1709 | netdev_tx_t tx_ret_val; | |
1710 | struct sk_buff *skb; | |
1711 | ||
1712 | /* allocate test skb */ | |
1713 | skb = alloc_skb(size, GFP_KERNEL); | |
1714 | if (!skb) | |
1715 | return 11; | |
da4dd0f7 | 1716 | |
84418e3b AD |
1717 | /* place data into test skb */ |
1718 | ixgbe_create_lbtest_frame(skb, size); | |
1719 | skb_put(skb, size); | |
da4dd0f7 PWJ |
1720 | |
1721 | /* | |
1722 | * Calculate the loop count based on the largest descriptor ring | |
1723 | * The idea is to wrap the largest ring a number of times using 64 | |
1724 | * send/receive pairs during each loop | |
1725 | */ | |
1726 | ||
1727 | if (rx_ring->count <= tx_ring->count) | |
1728 | lc = ((tx_ring->count / 64) * 2) + 1; | |
1729 | else | |
1730 | lc = ((rx_ring->count / 64) * 2) + 1; | |
1731 | ||
da4dd0f7 | 1732 | for (j = 0; j <= lc; j++) { |
84418e3b | 1733 | /* reset count of good packets */ |
da4dd0f7 | 1734 | good_cnt = 0; |
84418e3b AD |
1735 | |
1736 | /* place 64 packets on the transmit queue*/ | |
1737 | for (i = 0; i < 64; i++) { | |
1738 | skb_get(skb); | |
1739 | tx_ret_val = ixgbe_xmit_frame_ring(skb, | |
84418e3b AD |
1740 | adapter, |
1741 | tx_ring); | |
1742 | if (tx_ret_val == NETDEV_TX_OK) | |
da4dd0f7 | 1743 | good_cnt++; |
84418e3b AD |
1744 | } |
1745 | ||
da4dd0f7 | 1746 | if (good_cnt != 64) { |
84418e3b | 1747 | ret_val = 12; |
da4dd0f7 PWJ |
1748 | break; |
1749 | } | |
84418e3b AD |
1750 | |
1751 | /* allow 200 milliseconds for packets to go from Tx to Rx */ | |
1752 | msleep(200); | |
1753 | ||
fc77dc3c | 1754 | good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); |
84418e3b AD |
1755 | if (good_cnt != 64) { |
1756 | ret_val = 13; | |
da4dd0f7 PWJ |
1757 | break; |
1758 | } | |
1759 | } | |
1760 | ||
84418e3b AD |
1761 | /* free the original skb */ |
1762 | kfree_skb(skb); | |
1763 | ||
da4dd0f7 PWJ |
1764 | return ret_val; |
1765 | } | |
1766 | ||
1767 | static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) | |
1768 | { | |
1769 | *data = ixgbe_setup_desc_rings(adapter); | |
1770 | if (*data) | |
1771 | goto out; | |
1772 | *data = ixgbe_setup_loopback_test(adapter); | |
1773 | if (*data) | |
1774 | goto err_loopback; | |
1775 | *data = ixgbe_run_loopback_test(adapter); | |
1776 | ixgbe_loopback_cleanup(adapter); | |
1777 | ||
1778 | err_loopback: | |
1779 | ixgbe_free_desc_rings(adapter); | |
1780 | out: | |
1781 | return *data; | |
1782 | } | |
1783 | ||
1784 | static void ixgbe_diag_test(struct net_device *netdev, | |
1785 | struct ethtool_test *eth_test, u64 *data) | |
1786 | { | |
1787 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1788 | bool if_running = netif_running(netdev); | |
1789 | ||
1790 | set_bit(__IXGBE_TESTING, &adapter->state); | |
1791 | if (eth_test->flags == ETH_TEST_FL_OFFLINE) { | |
1792 | /* Offline tests */ | |
1793 | ||
396e799c | 1794 | e_info(hw, "offline testing starting\n"); |
da4dd0f7 PWJ |
1795 | |
1796 | /* Link test performed before hardware reset so autoneg doesn't | |
1797 | * interfere with test result */ | |
1798 | if (ixgbe_link_test(adapter, &data[4])) | |
1799 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1800 | ||
e7d481a6 GR |
1801 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
1802 | int i; | |
1803 | for (i = 0; i < adapter->num_vfs; i++) { | |
1804 | if (adapter->vfinfo[i].clear_to_send) { | |
1805 | netdev_warn(netdev, "%s", | |
1806 | "offline diagnostic is not " | |
1807 | "supported when VFs are " | |
1808 | "present\n"); | |
1809 | data[0] = 1; | |
1810 | data[1] = 1; | |
1811 | data[2] = 1; | |
1812 | data[3] = 1; | |
1813 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1814 | clear_bit(__IXGBE_TESTING, | |
1815 | &adapter->state); | |
1816 | goto skip_ol_tests; | |
1817 | } | |
1818 | } | |
1819 | } | |
1820 | ||
da4dd0f7 PWJ |
1821 | if (if_running) |
1822 | /* indicate we're in test mode */ | |
1823 | dev_close(netdev); | |
1824 | else | |
1825 | ixgbe_reset(adapter); | |
1826 | ||
396e799c | 1827 | e_info(hw, "register testing starting\n"); |
da4dd0f7 PWJ |
1828 | if (ixgbe_reg_test(adapter, &data[0])) |
1829 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1830 | ||
1831 | ixgbe_reset(adapter); | |
396e799c | 1832 | e_info(hw, "eeprom testing starting\n"); |
da4dd0f7 PWJ |
1833 | if (ixgbe_eeprom_test(adapter, &data[1])) |
1834 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1835 | ||
1836 | ixgbe_reset(adapter); | |
396e799c | 1837 | e_info(hw, "interrupt testing starting\n"); |
da4dd0f7 PWJ |
1838 | if (ixgbe_intr_test(adapter, &data[2])) |
1839 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1840 | ||
bdbec4b8 GR |
1841 | /* If SRIOV or VMDq is enabled then skip MAC |
1842 | * loopback diagnostic. */ | |
1843 | if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | | |
1844 | IXGBE_FLAG_VMDQ_ENABLED)) { | |
396e799c ET |
1845 | e_info(hw, "Skip MAC loopback diagnostic in VT " |
1846 | "mode\n"); | |
bdbec4b8 GR |
1847 | data[3] = 0; |
1848 | goto skip_loopback; | |
1849 | } | |
1850 | ||
da4dd0f7 | 1851 | ixgbe_reset(adapter); |
396e799c | 1852 | e_info(hw, "loopback testing starting\n"); |
da4dd0f7 PWJ |
1853 | if (ixgbe_loopback_test(adapter, &data[3])) |
1854 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1855 | ||
bdbec4b8 | 1856 | skip_loopback: |
da4dd0f7 PWJ |
1857 | ixgbe_reset(adapter); |
1858 | ||
1859 | clear_bit(__IXGBE_TESTING, &adapter->state); | |
1860 | if (if_running) | |
1861 | dev_open(netdev); | |
1862 | } else { | |
396e799c | 1863 | e_info(hw, "online testing starting\n"); |
da4dd0f7 PWJ |
1864 | /* Online tests */ |
1865 | if (ixgbe_link_test(adapter, &data[4])) | |
1866 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1867 | ||
1868 | /* Online tests aren't run; pass by default */ | |
1869 | data[0] = 0; | |
1870 | data[1] = 0; | |
1871 | data[2] = 0; | |
1872 | data[3] = 0; | |
1873 | ||
1874 | clear_bit(__IXGBE_TESTING, &adapter->state); | |
1875 | } | |
e7d481a6 | 1876 | skip_ol_tests: |
da4dd0f7 PWJ |
1877 | msleep_interruptible(4 * 1000); |
1878 | } | |
9a799d71 | 1879 | |
d6c519e1 AD |
1880 | static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, |
1881 | struct ethtool_wolinfo *wol) | |
1882 | { | |
1883 | struct ixgbe_hw *hw = &adapter->hw; | |
1884 | int retval = 1; | |
1885 | ||
0b077fea | 1886 | /* WOL not supported except for the following */ |
d6c519e1 | 1887 | switch(hw->device_id) { |
0b077fea DS |
1888 | case IXGBE_DEV_ID_82599_SFP: |
1889 | /* Only this subdevice supports WOL */ | |
1890 | if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) { | |
1891 | wol->supported = 0; | |
1892 | break; | |
1893 | } | |
1894 | retval = 0; | |
1895 | break; | |
50d6c681 AD |
1896 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
1897 | /* All except this subdevice support WOL */ | |
1898 | if (hw->subsystem_device_id == | |
1899 | IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) { | |
1900 | wol->supported = 0; | |
1901 | break; | |
1902 | } | |
0b077fea DS |
1903 | retval = 0; |
1904 | break; | |
d6c519e1 AD |
1905 | case IXGBE_DEV_ID_82599_KX4: |
1906 | retval = 0; | |
1907 | break; | |
1908 | default: | |
1909 | wol->supported = 0; | |
d6c519e1 AD |
1910 | } |
1911 | ||
1912 | return retval; | |
1913 | } | |
1914 | ||
9a799d71 | 1915 | static void ixgbe_get_wol(struct net_device *netdev, |
b4617240 | 1916 | struct ethtool_wolinfo *wol) |
9a799d71 | 1917 | { |
e63d9762 PW |
1918 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
1919 | ||
1920 | wol->supported = WAKE_UCAST | WAKE_MCAST | | |
1921 | WAKE_BCAST | WAKE_MAGIC; | |
9a799d71 AK |
1922 | wol->wolopts = 0; |
1923 | ||
d6c519e1 AD |
1924 | if (ixgbe_wol_exclusion(adapter, wol) || |
1925 | !device_can_wakeup(&adapter->pdev->dev)) | |
e63d9762 PW |
1926 | return; |
1927 | ||
1928 | if (adapter->wol & IXGBE_WUFC_EX) | |
1929 | wol->wolopts |= WAKE_UCAST; | |
1930 | if (adapter->wol & IXGBE_WUFC_MC) | |
1931 | wol->wolopts |= WAKE_MCAST; | |
1932 | if (adapter->wol & IXGBE_WUFC_BC) | |
1933 | wol->wolopts |= WAKE_BCAST; | |
1934 | if (adapter->wol & IXGBE_WUFC_MAG) | |
1935 | wol->wolopts |= WAKE_MAGIC; | |
9a799d71 AK |
1936 | } |
1937 | ||
e63d9762 PW |
1938 | static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) |
1939 | { | |
1940 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1941 | ||
1942 | if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) | |
1943 | return -EOPNOTSUPP; | |
1944 | ||
d6c519e1 AD |
1945 | if (ixgbe_wol_exclusion(adapter, wol)) |
1946 | return wol->wolopts ? -EOPNOTSUPP : 0; | |
1947 | ||
e63d9762 PW |
1948 | adapter->wol = 0; |
1949 | ||
1950 | if (wol->wolopts & WAKE_UCAST) | |
1951 | adapter->wol |= IXGBE_WUFC_EX; | |
1952 | if (wol->wolopts & WAKE_MCAST) | |
1953 | adapter->wol |= IXGBE_WUFC_MC; | |
1954 | if (wol->wolopts & WAKE_BCAST) | |
1955 | adapter->wol |= IXGBE_WUFC_BC; | |
1956 | if (wol->wolopts & WAKE_MAGIC) | |
1957 | adapter->wol |= IXGBE_WUFC_MAG; | |
1958 | ||
1959 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
1960 | ||
1961 | return 0; | |
1962 | } | |
1963 | ||
9a799d71 AK |
1964 | static int ixgbe_nway_reset(struct net_device *netdev) |
1965 | { | |
1966 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1967 | ||
d4f80882 AV |
1968 | if (netif_running(netdev)) |
1969 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
1970 | |
1971 | return 0; | |
1972 | } | |
1973 | ||
1974 | static int ixgbe_phys_id(struct net_device *netdev, u32 data) | |
1975 | { | |
1976 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e JB |
1977 | struct ixgbe_hw *hw = &adapter->hw; |
1978 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
9a799d71 AK |
1979 | u32 i; |
1980 | ||
1981 | if (!data || data > 300) | |
1982 | data = 300; | |
1983 | ||
1984 | for (i = 0; i < (data * 1000); i += 400) { | |
c44ade9e | 1985 | hw->mac.ops.led_on(hw, IXGBE_LED_ON); |
9a799d71 | 1986 | msleep_interruptible(200); |
c44ade9e | 1987 | hw->mac.ops.led_off(hw, IXGBE_LED_ON); |
9a799d71 AK |
1988 | msleep_interruptible(200); |
1989 | } | |
1990 | ||
1991 | /* Restore LED settings */ | |
1992 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg); | |
1993 | ||
1994 | return 0; | |
1995 | } | |
1996 | ||
1997 | static int ixgbe_get_coalesce(struct net_device *netdev, | |
b4617240 | 1998 | struct ethtool_coalesce *ec) |
9a799d71 AK |
1999 | { |
2000 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2001 | ||
4a0b9ca0 | 2002 | ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit; |
30efa5a3 JB |
2003 | |
2004 | /* only valid if in constant ITR mode */ | |
f7554a2b | 2005 | switch (adapter->rx_itr_setting) { |
30efa5a3 JB |
2006 | case 0: |
2007 | /* throttling disabled */ | |
2008 | ec->rx_coalesce_usecs = 0; | |
2009 | break; | |
2010 | case 1: | |
2011 | /* dynamic ITR mode */ | |
2012 | ec->rx_coalesce_usecs = 1; | |
2013 | break; | |
2014 | default: | |
2015 | /* fixed interrupt rate mode */ | |
f7554a2b | 2016 | ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param; |
30efa5a3 JB |
2017 | break; |
2018 | } | |
f7554a2b | 2019 | |
cfb3f91a SN |
2020 | /* if in mixed tx/rx queues per vector mode, report only rx settings */ |
2021 | if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count) | |
2022 | return 0; | |
2023 | ||
f7554a2b NS |
2024 | /* only valid if in constant ITR mode */ |
2025 | switch (adapter->tx_itr_setting) { | |
2026 | case 0: | |
2027 | /* throttling disabled */ | |
2028 | ec->tx_coalesce_usecs = 0; | |
2029 | break; | |
2030 | case 1: | |
2031 | /* dynamic ITR mode */ | |
2032 | ec->tx_coalesce_usecs = 1; | |
2033 | break; | |
2034 | default: | |
2035 | ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param; | |
2036 | break; | |
2037 | } | |
2038 | ||
9a799d71 AK |
2039 | return 0; |
2040 | } | |
2041 | ||
80fba3f4 AD |
2042 | /* |
2043 | * this function must be called before setting the new value of | |
2044 | * rx_itr_setting | |
2045 | */ | |
2046 | static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter, | |
2047 | struct ethtool_coalesce *ec) | |
2048 | { | |
2049 | struct net_device *netdev = adapter->netdev; | |
2050 | ||
2051 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
2052 | return false; | |
2053 | ||
2054 | /* if interrupt rate is too high then disable RSC */ | |
2055 | if (ec->rx_coalesce_usecs != 1 && | |
2056 | ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) { | |
2057 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { | |
2058 | e_info(probe, "rx-usecs set too low, " | |
2059 | "disabling RSC\n"); | |
2060 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; | |
2061 | return true; | |
2062 | } | |
2063 | } else { | |
2064 | /* check the feature flag value and enable RSC if necessary */ | |
2065 | if ((netdev->features & NETIF_F_LRO) && | |
2066 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
2067 | e_info(probe, "rx-usecs set to %d, " | |
2068 | "re-enabling RSC\n", | |
2069 | ec->rx_coalesce_usecs); | |
2070 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
2071 | return true; | |
2072 | } | |
2073 | } | |
2074 | return false; | |
2075 | } | |
2076 | ||
9a799d71 | 2077 | static int ixgbe_set_coalesce(struct net_device *netdev, |
b4617240 | 2078 | struct ethtool_coalesce *ec) |
9a799d71 AK |
2079 | { |
2080 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
237057ad | 2081 | struct ixgbe_q_vector *q_vector; |
30efa5a3 | 2082 | int i; |
ef021194 | 2083 | bool need_reset = false; |
9a799d71 | 2084 | |
cfb3f91a SN |
2085 | /* don't accept tx specific changes if we've got mixed RxTx vectors */ |
2086 | if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count | |
2087 | && ec->tx_coalesce_usecs) | |
f7554a2b NS |
2088 | return -EINVAL; |
2089 | ||
9a799d71 | 2090 | if (ec->tx_max_coalesced_frames_irq) |
4a0b9ca0 | 2091 | adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq; |
30efa5a3 JB |
2092 | |
2093 | if (ec->rx_coalesce_usecs > 1) { | |
509ee935 | 2094 | /* check the limits */ |
80fba3f4 | 2095 | if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) || |
509ee935 JB |
2096 | (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE)) |
2097 | return -EINVAL; | |
2098 | ||
80fba3f4 AD |
2099 | /* check the old value and enable RSC if necessary */ |
2100 | need_reset = ixgbe_update_rsc(adapter, ec); | |
2101 | ||
30efa5a3 | 2102 | /* store the value in ints/second */ |
f7554a2b | 2103 | adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs; |
30efa5a3 JB |
2104 | |
2105 | /* static value of interrupt rate */ | |
f7554a2b | 2106 | adapter->rx_itr_setting = adapter->rx_eitr_param; |
509ee935 | 2107 | /* clear the lower bit as its used for dynamic state */ |
f7554a2b | 2108 | adapter->rx_itr_setting &= ~1; |
30efa5a3 | 2109 | } else if (ec->rx_coalesce_usecs == 1) { |
80fba3f4 AD |
2110 | /* check the old value and enable RSC if necessary */ |
2111 | need_reset = ixgbe_update_rsc(adapter, ec); | |
2112 | ||
30efa5a3 | 2113 | /* 1 means dynamic mode */ |
f7554a2b NS |
2114 | adapter->rx_eitr_param = 20000; |
2115 | adapter->rx_itr_setting = 1; | |
30efa5a3 | 2116 | } else { |
80fba3f4 AD |
2117 | /* check the old value and enable RSC if necessary */ |
2118 | need_reset = ixgbe_update_rsc(adapter, ec); | |
509ee935 JB |
2119 | /* |
2120 | * any other value means disable eitr, which is best | |
2121 | * served by setting the interrupt rate very high | |
2122 | */ | |
f8d1dcaf | 2123 | adapter->rx_eitr_param = IXGBE_MAX_INT_RATE; |
f7554a2b NS |
2124 | adapter->rx_itr_setting = 0; |
2125 | } | |
2126 | ||
2127 | if (ec->tx_coalesce_usecs > 1) { | |
f8d1dcaf JB |
2128 | /* |
2129 | * don't have to worry about max_int as above because | |
2130 | * tx vectors don't do hardware RSC (an rx function) | |
2131 | */ | |
f7554a2b NS |
2132 | /* check the limits */ |
2133 | if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) || | |
2134 | (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE)) | |
2135 | return -EINVAL; | |
2136 | ||
2137 | /* store the value in ints/second */ | |
2138 | adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs; | |
2139 | ||
2140 | /* static value of interrupt rate */ | |
2141 | adapter->tx_itr_setting = adapter->tx_eitr_param; | |
2142 | ||
2143 | /* clear the lower bit as its used for dynamic state */ | |
2144 | adapter->tx_itr_setting &= ~1; | |
2145 | } else if (ec->tx_coalesce_usecs == 1) { | |
2146 | /* 1 means dynamic mode */ | |
2147 | adapter->tx_eitr_param = 10000; | |
2148 | adapter->tx_itr_setting = 1; | |
2149 | } else { | |
2150 | adapter->tx_eitr_param = IXGBE_MAX_INT_RATE; | |
2151 | adapter->tx_itr_setting = 0; | |
30efa5a3 | 2152 | } |
9a799d71 | 2153 | |
237057ad DS |
2154 | /* MSI/MSIx Interrupt Mode */ |
2155 | if (adapter->flags & | |
2156 | (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) { | |
2157 | int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2158 | for (i = 0; i < num_vectors; i++) { | |
2159 | q_vector = adapter->q_vector[i]; | |
2160 | if (q_vector->txr_count && !q_vector->rxr_count) | |
f7554a2b NS |
2161 | /* tx only */ |
2162 | q_vector->eitr = adapter->tx_eitr_param; | |
237057ad DS |
2163 | else |
2164 | /* rx only or mixed */ | |
f7554a2b | 2165 | q_vector->eitr = adapter->rx_eitr_param; |
237057ad DS |
2166 | ixgbe_write_eitr(q_vector); |
2167 | } | |
2168 | /* Legacy Interrupt Mode */ | |
2169 | } else { | |
2170 | q_vector = adapter->q_vector[0]; | |
f7554a2b | 2171 | q_vector->eitr = adapter->rx_eitr_param; |
fe49f04a | 2172 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
2173 | } |
2174 | ||
ef021194 JB |
2175 | /* |
2176 | * do reset here at the end to make sure EITR==0 case is handled | |
2177 | * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings | |
2178 | * also locks in RSC enable/disable which requires reset | |
2179 | */ | |
2180 | if (need_reset) { | |
2181 | if (netif_running(netdev)) | |
2182 | ixgbe_reinit_locked(adapter); | |
2183 | else | |
2184 | ixgbe_reset(adapter); | |
2185 | } | |
2186 | ||
9a799d71 AK |
2187 | return 0; |
2188 | } | |
2189 | ||
f8212f97 AD |
2190 | static int ixgbe_set_flags(struct net_device *netdev, u32 data) |
2191 | { | |
2192 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a713e7c | 2193 | bool need_reset = false; |
1437ce39 | 2194 | int rc; |
f8212f97 | 2195 | |
f62bbb5e JG |
2196 | #ifdef CONFIG_IXGBE_DCB |
2197 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
2198 | !(data & ETH_FLAG_RXVLAN)) | |
2199 | return -EINVAL; | |
2200 | #endif | |
2201 | ||
2202 | need_reset = (data & ETH_FLAG_RXVLAN) != | |
2203 | (netdev->features & NETIF_F_HW_VLAN_RX); | |
2204 | ||
5136cad3 | 2205 | rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE | |
f62bbb5e | 2206 | ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN); |
1437ce39 BH |
2207 | if (rc) |
2208 | return rc; | |
f8212f97 | 2209 | |
f8212f97 | 2210 | /* if state changes we need to update adapter->flags and reset */ |
80fba3f4 AD |
2211 | if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && |
2212 | (!!(data & ETH_FLAG_LRO) != | |
2213 | !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) { | |
2214 | if ((data & ETH_FLAG_LRO) && | |
2215 | (!adapter->rx_itr_setting || | |
2216 | (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) { | |
2217 | e_info(probe, "rx-usecs set too low, " | |
2218 | "not enabling RSC.\n"); | |
2219 | } else { | |
f8d1dcaf JB |
2220 | adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; |
2221 | switch (adapter->hw.mac.type) { | |
2222 | case ixgbe_mac_82599EB: | |
2223 | need_reset = true; | |
2224 | break; | |
b93a2226 DS |
2225 | case ixgbe_mac_X540: { |
2226 | int i; | |
2227 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2228 | struct ixgbe_ring *ring = | |
2229 | adapter->rx_ring[i]; | |
2230 | if (adapter->flags2 & | |
2231 | IXGBE_FLAG2_RSC_ENABLED) { | |
2232 | ixgbe_configure_rscctl(adapter, | |
2233 | ring); | |
2234 | } else { | |
2235 | ixgbe_clear_rscctl(adapter, | |
2236 | ring); | |
2237 | } | |
2238 | } | |
2239 | } | |
2240 | break; | |
f8d1dcaf JB |
2241 | default: |
2242 | break; | |
2243 | } | |
f8d1dcaf | 2244 | } |
9a713e7c PW |
2245 | } |
2246 | ||
2247 | /* | |
2248 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
2249 | * the state changed, we need to reset. | |
2250 | */ | |
2251 | if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) && | |
2252 | (!(data & ETH_FLAG_NTUPLE))) { | |
2253 | /* turn off Flow Director perfect, set hash and reset */ | |
2254 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
2255 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
2256 | need_reset = true; | |
2257 | } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) && | |
2258 | (data & ETH_FLAG_NTUPLE)) { | |
2259 | /* turn off Flow Director hash, enable perfect and reset */ | |
2260 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
2261 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
2262 | need_reset = true; | |
2263 | } else { | |
2264 | /* no state change */ | |
2265 | } | |
2266 | ||
2267 | if (need_reset) { | |
f8212f97 AD |
2268 | if (netif_running(netdev)) |
2269 | ixgbe_reinit_locked(adapter); | |
2270 | else | |
2271 | ixgbe_reset(adapter); | |
2272 | } | |
9a713e7c | 2273 | |
f8212f97 | 2274 | return 0; |
9a713e7c PW |
2275 | } |
2276 | ||
2277 | static int ixgbe_set_rx_ntuple(struct net_device *dev, | |
2278 | struct ethtool_rx_ntuple *cmd) | |
2279 | { | |
2280 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
2281 | struct ethtool_rx_ntuple_flow_spec fs = cmd->fs; | |
2282 | struct ixgbe_atr_input input_struct; | |
2283 | struct ixgbe_atr_input_masks input_masks; | |
2284 | int target_queue; | |
2285 | ||
2286 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
2287 | return -EOPNOTSUPP; | |
2288 | ||
2289 | /* | |
2290 | * Don't allow programming if the action is a queue greater than | |
2291 | * the number of online Tx queues. | |
2292 | */ | |
2293 | if ((fs.action >= adapter->num_tx_queues) || | |
2294 | (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP)) | |
2295 | return -EINVAL; | |
2296 | ||
2297 | memset(&input_struct, 0, sizeof(struct ixgbe_atr_input)); | |
2298 | memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks)); | |
2299 | ||
2300 | input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src; | |
2301 | input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst; | |
2302 | input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc; | |
2303 | input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst; | |
2304 | input_masks.vlan_id_mask = fs.vlan_tag_mask; | |
2305 | /* only use the lowest 2 bytes for flex bytes */ | |
2306 | input_masks.data_mask = (fs.data_mask & 0xffff); | |
2307 | ||
2308 | switch (fs.flow_type) { | |
2309 | case TCP_V4_FLOW: | |
2310 | ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP); | |
2311 | break; | |
2312 | case UDP_V4_FLOW: | |
2313 | ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP); | |
2314 | break; | |
2315 | case SCTP_V4_FLOW: | |
2316 | ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP); | |
2317 | break; | |
2318 | default: | |
2319 | return -1; | |
2320 | } | |
f8212f97 | 2321 | |
9a713e7c PW |
2322 | /* Mask bits from the inputs based on user-supplied mask */ |
2323 | ixgbe_atr_set_src_ipv4_82599(&input_struct, | |
2324 | (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src)); | |
2325 | ixgbe_atr_set_dst_ipv4_82599(&input_struct, | |
2326 | (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst)); | |
2327 | /* 82599 expects these to be byte-swapped for perfect filtering */ | |
2328 | ixgbe_atr_set_src_port_82599(&input_struct, | |
2329 | ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc)); | |
2330 | ixgbe_atr_set_dst_port_82599(&input_struct, | |
2331 | ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst)); | |
2332 | ||
2333 | /* VLAN and Flex bytes are either completely masked or not */ | |
2334 | if (!fs.vlan_tag_mask) | |
2335 | ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag); | |
2336 | ||
2337 | if (!input_masks.data_mask) | |
2338 | /* make sure we only use the first 2 bytes of user data */ | |
2339 | ixgbe_atr_set_flex_byte_82599(&input_struct, | |
2340 | (fs.data & 0xffff)); | |
2341 | ||
2342 | /* determine if we need to drop or route the packet */ | |
2343 | if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP) | |
2344 | target_queue = MAX_RX_QUEUES - 1; | |
2345 | else | |
2346 | target_queue = fs.action; | |
2347 | ||
2348 | spin_lock(&adapter->fdir_perfect_lock); | |
2349 | ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct, | |
2350 | &input_masks, 0, target_queue); | |
2351 | spin_unlock(&adapter->fdir_perfect_lock); | |
2352 | ||
2353 | return 0; | |
f8212f97 | 2354 | } |
9a799d71 | 2355 | |
b9804972 | 2356 | static const struct ethtool_ops ixgbe_ethtool_ops = { |
9a799d71 AK |
2357 | .get_settings = ixgbe_get_settings, |
2358 | .set_settings = ixgbe_set_settings, | |
2359 | .get_drvinfo = ixgbe_get_drvinfo, | |
2360 | .get_regs_len = ixgbe_get_regs_len, | |
2361 | .get_regs = ixgbe_get_regs, | |
2362 | .get_wol = ixgbe_get_wol, | |
e63d9762 | 2363 | .set_wol = ixgbe_set_wol, |
9a799d71 AK |
2364 | .nway_reset = ixgbe_nway_reset, |
2365 | .get_link = ethtool_op_get_link, | |
2366 | .get_eeprom_len = ixgbe_get_eeprom_len, | |
2367 | .get_eeprom = ixgbe_get_eeprom, | |
2368 | .get_ringparam = ixgbe_get_ringparam, | |
2369 | .set_ringparam = ixgbe_set_ringparam, | |
2370 | .get_pauseparam = ixgbe_get_pauseparam, | |
2371 | .set_pauseparam = ixgbe_set_pauseparam, | |
2372 | .get_rx_csum = ixgbe_get_rx_csum, | |
2373 | .set_rx_csum = ixgbe_set_rx_csum, | |
2374 | .get_tx_csum = ixgbe_get_tx_csum, | |
2375 | .set_tx_csum = ixgbe_set_tx_csum, | |
2376 | .get_sg = ethtool_op_get_sg, | |
2377 | .set_sg = ethtool_op_set_sg, | |
2378 | .get_msglevel = ixgbe_get_msglevel, | |
2379 | .set_msglevel = ixgbe_set_msglevel, | |
2380 | .get_tso = ethtool_op_get_tso, | |
2381 | .set_tso = ixgbe_set_tso, | |
da4dd0f7 | 2382 | .self_test = ixgbe_diag_test, |
9a799d71 AK |
2383 | .get_strings = ixgbe_get_strings, |
2384 | .phys_id = ixgbe_phys_id, | |
b4617240 | 2385 | .get_sset_count = ixgbe_get_sset_count, |
9a799d71 AK |
2386 | .get_ethtool_stats = ixgbe_get_ethtool_stats, |
2387 | .get_coalesce = ixgbe_get_coalesce, | |
2388 | .set_coalesce = ixgbe_set_coalesce, | |
177db6ff | 2389 | .get_flags = ethtool_op_get_flags, |
f8212f97 | 2390 | .set_flags = ixgbe_set_flags, |
9a713e7c | 2391 | .set_rx_ntuple = ixgbe_set_rx_ntuple, |
9a799d71 AK |
2392 | }; |
2393 | ||
2394 | void ixgbe_set_ethtool_ops(struct net_device *netdev) | |
2395 | { | |
2396 | SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops); | |
2397 | } |