projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
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| 2f90b865 AD |
1 | /******************************************************************************* |
| 2 | ||
| 3 | Intel 10 Gigabit PCI Express Linux driver | |
| 4 | Copyright(c) 1999 - 2007 Intel Corporation. | |
| 5 | ||
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 13 | more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License along with | |
| 16 | this program; if not, write to the Free Software Foundation, Inc., | |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | ||
| 19 | The full GNU General Public License is included in this distribution in | |
| 20 | the file called "COPYING". | |
| 21 | ||
| 22 | Contact Information: | |
| 23 | Linux NICS <linux.nics@intel.com> | |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 26 | ||
| 27 | *******************************************************************************/ | |
| 28 | ||
| 29 | #ifndef _DCB_CONFIG_H_ | |
| 30 | #define _DCB_CONFIG_H_ | |
| 31 | ||
| 32 | #include "ixgbe_type.h" | |
| 33 | ||
| 34 | /* DCB data structures */ | |
| 35 | ||
| 36 | #define IXGBE_MAX_PACKET_BUFFERS 8 | |
| 37 | #define MAX_USER_PRIORITY 8 | |
| 38 | #define MAX_TRAFFIC_CLASS 8 | |
| 39 | #define MAX_BW_GROUP 8 | |
| 40 | #define BW_PERCENT 100 | |
| 41 | ||
| 42 | #define DCB_TX_CONFIG 0 | |
| 43 | #define DCB_RX_CONFIG 1 | |
| 44 | ||
| 45 | /* DCB error Codes */ | |
| 46 | #define DCB_SUCCESS 0 | |
| 47 | #define DCB_ERR_CONFIG -1 | |
| 48 | #define DCB_ERR_PARAM -2 | |
| 49 | ||
| 50 | /* Transmit and receive Errors */ | |
| 51 | /* Error in bandwidth group allocation */ | |
| 52 | #define DCB_ERR_BW_GROUP -3 | |
| 53 | /* Error in traffic class bandwidth allocation */ | |
| 54 | #define DCB_ERR_TC_BW -4 | |
| 55 | /* Traffic class has both link strict and group strict enabled */ | |
| 56 | #define DCB_ERR_LS_GS -5 | |
| 57 | /* Link strict traffic class has non zero bandwidth */ | |
| 58 | #define DCB_ERR_LS_BW_NONZERO -6 | |
| 59 | /* Link strict bandwidth group has non zero bandwidth */ | |
| 60 | #define DCB_ERR_LS_BWG_NONZERO -7 | |
| 61 | /* Traffic class has zero bandwidth */ | |
| 62 | #define DCB_ERR_TC_BW_ZERO -8 | |
| 63 | ||
| 64 | #define DCB_NOT_IMPLEMENTED 0x7FFFFFFF | |
| 65 | ||
| 66 | struct dcb_pfc_tc_debug { | |
| 67 | u8 tc; | |
| 68 | u8 pause_status; | |
| 69 | u64 pause_quanta; | |
| 70 | }; | |
| 71 | ||
| 72 | enum strict_prio_type { | |
| 73 | prio_none = 0, | |
| 74 | prio_group, | |
| 75 | prio_link | |
| 76 | }; | |
| 77 | ||
| 78 | /* Traffic class bandwidth allocation per direction */ | |
| 79 | struct tc_bw_alloc { | |
| 80 | u8 bwg_id; /* Bandwidth Group (BWG) ID */ | |
| 81 | u8 bwg_percent; /* % of BWG's bandwidth */ | |
| 82 | u8 link_percent; /* % of link bandwidth */ | |
| 83 | u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ | |
| 84 | u16 data_credits_refill; /* Credit refill amount in 64B granularity */ | |
| 85 | u16 data_credits_max; /* Max credits for a configured packet buffer | |
| 86 | * in 64B granularity.*/ | |
| 87 | enum strict_prio_type prio_type; /* Link or Group Strict Priority */ | |
| 88 | }; | |
| 89 | ||
| 90 | enum dcb_pfc_type { | |
| 91 | pfc_disabled = 0, | |
| 92 | pfc_enabled_full, | |
| 93 | pfc_enabled_tx, | |
| 94 | pfc_enabled_rx | |
| 95 | }; | |
| 96 | ||
| 97 | /* Traffic class configuration */ | |
| 98 | struct tc_configuration { | |
| 99 | struct tc_bw_alloc path[2]; /* One each for Tx/Rx */ | |
| 100 | enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */ | |
| 101 | ||
| 102 | u16 desc_credits_max; /* For Tx Descriptor arbitration */ | |
| 103 | u8 tc; /* Traffic class (TC) */ | |
| 104 | }; | |
| 105 | ||
| 106 | enum dcb_rx_pba_cfg { | |
| 107 | pba_equal, /* PBA[0-7] each use 64KB FIFO */ | |
| 108 | pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ | |
| 109 | }; | |
| 110 | ||
| 111 | struct ixgbe_dcb_config { | |
| 112 | struct tc_configuration tc_config[MAX_TRAFFIC_CLASS]; | |
| 113 | u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */ | |
| 114 | ||
| 115 | bool round_robin_enable; | |
| 116 | ||
| 117 | enum dcb_rx_pba_cfg rx_pba_cfg; | |
| 118 | ||
| 119 | u32 dcb_cfg_version; /* Not used...OS-specific? */ | |
| 120 | u32 link_speed; /* For bandwidth allocation validation purpose */ | |
| 121 | }; | |
| 122 | ||
| 123 | /* DCB driver APIs */ | |
| 124 | ||
| 125 | /* DCB rule checking function.*/ | |
| 126 | s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *config); | |
| 127 | ||
| 128 | /* DCB credits calculation */ | |
| 129 | s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, u8); | |
| 130 | ||
| 131 | /* DCB PFC functions */ | |
| 132 | s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, struct ixgbe_dcb_config *g); | |
| 133 | s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); | |
| 134 | ||
| 135 | /* DCB traffic class stats */ | |
| 136 | s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); | |
| 137 | s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); | |
| 138 | ||
| 139 | /* DCB config arbiters */ | |
| 140 | s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *, | |
| 141 | struct ixgbe_dcb_config *); | |
| 142 | s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *, | |
| 143 | struct ixgbe_dcb_config *); | |
| 144 | s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *, struct ixgbe_dcb_config *); | |
| 145 | ||
| 146 | /* DCB hw initialization */ | |
| 147 | s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *); | |
| 148 | ||
| 149 | /* DCB definitions for credit calculation */ | |
| 150 | #define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */ | |
| 151 | #define MINIMUM_CREDIT_REFILL 5 /* 5*64B = 320B */ | |
| 152 | #define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145= UpperBound((9*1024+54)/64B) for 9KB jumbo frame */ | |
| 153 | #define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */ | |
| 154 | #define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */ | |
| 155 | #define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */ | |
| 156 | ||
| 157 | #endif /* _DCB_CONFIG_H */ |