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11afc1b1 PW |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
11afc1b1 PW |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
32 | #include "ixgbe.h" | |
33 | #include "ixgbe_phy.h" | |
096a58fd | 34 | #include "ixgbe_mbx.h" |
11afc1b1 PW |
35 | |
36 | #define IXGBE_82599_MAX_TX_QUEUES 128 | |
37 | #define IXGBE_82599_MAX_RX_QUEUES 128 | |
38 | #define IXGBE_82599_RAR_ENTRIES 128 | |
39 | #define IXGBE_82599_MC_TBL_SIZE 128 | |
40 | #define IXGBE_82599_VFT_TBL_SIZE 128 | |
41 | ||
5d5b7c39 ET |
42 | static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
43 | static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); | |
44 | static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); | |
45 | static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, | |
46 | ixgbe_link_speed speed, | |
47 | bool autoneg, | |
48 | bool autoneg_wait_to_complete); | |
cd7e1f0b DS |
49 | static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, |
50 | ixgbe_link_speed speed, | |
51 | bool autoneg, | |
52 | bool autoneg_wait_to_complete); | |
5d5b7c39 ET |
53 | static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, |
54 | bool autoneg_wait_to_complete); | |
55 | static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, | |
8620a103 MC |
56 | ixgbe_link_speed speed, |
57 | bool autoneg, | |
58 | bool autoneg_wait_to_complete); | |
8620a103 MC |
59 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, |
60 | ixgbe_link_speed speed, | |
61 | bool autoneg, | |
62 | bool autoneg_wait_to_complete); | |
794caeb2 | 63 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); |
11afc1b1 | 64 | |
7b25cdba | 65 | static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
66 | { |
67 | struct ixgbe_mac_info *mac = &hw->mac; | |
c6ecf39a DS |
68 | |
69 | /* enable the laser control functions for SFP+ fiber */ | |
70 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { | |
61fac744 PW |
71 | mac->ops.disable_tx_laser = |
72 | &ixgbe_disable_tx_laser_multispeed_fiber; | |
73 | mac->ops.enable_tx_laser = | |
74 | &ixgbe_enable_tx_laser_multispeed_fiber; | |
1097cd17 | 75 | mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; |
11afc1b1 | 76 | } else { |
61fac744 PW |
77 | mac->ops.disable_tx_laser = NULL; |
78 | mac->ops.enable_tx_laser = NULL; | |
1097cd17 | 79 | mac->ops.flap_tx_laser = NULL; |
c6ecf39a DS |
80 | } |
81 | ||
82 | if (hw->phy.multispeed_fiber) { | |
83 | /* Set up dual speed SFP+ support */ | |
84 | mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; | |
85 | } else { | |
cd7e1f0b DS |
86 | if ((mac->ops.get_media_type(hw) == |
87 | ixgbe_media_type_backplane) && | |
88 | (hw->phy.smart_speed == ixgbe_smart_speed_auto || | |
89 | hw->phy.smart_speed == ixgbe_smart_speed_on)) | |
90 | mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; | |
91 | else | |
92 | mac->ops.setup_link = &ixgbe_setup_mac_link_82599; | |
11afc1b1 PW |
93 | } |
94 | } | |
95 | ||
7b25cdba | 96 | static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
97 | { |
98 | s32 ret_val = 0; | |
99 | u16 list_offset, data_offset, data_value; | |
100 | ||
101 | if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { | |
102 | ixgbe_init_mac_link_ops_82599(hw); | |
553b4497 PW |
103 | |
104 | hw->phy.ops.reset = NULL; | |
105 | ||
11afc1b1 PW |
106 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
107 | &data_offset); | |
108 | ||
109 | if (ret_val != 0) | |
110 | goto setup_sfp_out; | |
111 | ||
aa5aec88 PWJ |
112 | /* PHY config will finish before releasing the semaphore */ |
113 | ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); | |
114 | if (ret_val != 0) { | |
115 | ret_val = IXGBE_ERR_SWFW_SYNC; | |
116 | goto setup_sfp_out; | |
117 | } | |
118 | ||
11afc1b1 PW |
119 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
120 | while (data_value != 0xffff) { | |
121 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); | |
122 | IXGBE_WRITE_FLUSH(hw); | |
123 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); | |
124 | } | |
1479ad4f PWJ |
125 | /* Now restart DSP by setting Restart_AN */ |
126 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, | |
127 | (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART)); | |
aa5aec88 PWJ |
128 | |
129 | /* Release the semaphore */ | |
130 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); | |
131 | /* Delay obtaining semaphore again to allow FW access */ | |
132 | msleep(hw->eeprom.semaphore_delay); | |
11afc1b1 PW |
133 | } |
134 | ||
135 | setup_sfp_out: | |
136 | return ret_val; | |
137 | } | |
138 | ||
11afc1b1 PW |
139 | static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) |
140 | { | |
141 | struct ixgbe_mac_info *mac = &hw->mac; | |
11afc1b1 | 142 | |
04f165ef | 143 | ixgbe_init_mac_link_ops_82599(hw); |
11afc1b1 | 144 | |
04f165ef PW |
145 | mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; |
146 | mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; | |
147 | mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; | |
148 | mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; | |
149 | mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; | |
21ce849b | 150 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); |
11afc1b1 | 151 | |
04f165ef PW |
152 | return 0; |
153 | } | |
11afc1b1 | 154 | |
04f165ef PW |
155 | /** |
156 | * ixgbe_init_phy_ops_82599 - PHY/SFP specific init | |
157 | * @hw: pointer to hardware structure | |
158 | * | |
159 | * Initialize any function pointers that were not able to be | |
160 | * set during get_invariants because the PHY/SFP type was | |
161 | * not known. Perform the SFP init if necessary. | |
162 | * | |
163 | **/ | |
7b25cdba | 164 | static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) |
04f165ef PW |
165 | { |
166 | struct ixgbe_mac_info *mac = &hw->mac; | |
167 | struct ixgbe_phy_info *phy = &hw->phy; | |
168 | s32 ret_val = 0; | |
11afc1b1 | 169 | |
04f165ef PW |
170 | /* Identify the PHY or SFP module */ |
171 | ret_val = phy->ops.identify(hw); | |
172 | ||
173 | /* Setup function pointers based on detected SFP module and speeds */ | |
174 | ixgbe_init_mac_link_ops_82599(hw); | |
11afc1b1 PW |
175 | |
176 | /* If copper media, overwrite with copper function pointers */ | |
177 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
178 | mac->ops.setup_link = &ixgbe_setup_copper_link_82599; | |
11afc1b1 | 179 | mac->ops.get_link_capabilities = |
a391f1d5 | 180 | &ixgbe_get_copper_link_capabilities_generic; |
11afc1b1 PW |
181 | } |
182 | ||
04f165ef | 183 | /* Set necessary function pointers based on phy type */ |
11afc1b1 PW |
184 | switch (hw->phy.type) { |
185 | case ixgbe_phy_tn: | |
186 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; | |
187 | phy->ops.get_firmware_version = | |
04f165ef | 188 | &ixgbe_get_phy_firmware_version_tnx; |
11afc1b1 | 189 | break; |
fe15e8e1 DS |
190 | case ixgbe_phy_aq: |
191 | phy->ops.get_firmware_version = | |
192 | &ixgbe_get_phy_firmware_version_generic; | |
193 | break; | |
11afc1b1 PW |
194 | default: |
195 | break; | |
196 | } | |
197 | ||
11afc1b1 PW |
198 | return ret_val; |
199 | } | |
200 | ||
201 | /** | |
202 | * ixgbe_get_link_capabilities_82599 - Determines link capabilities | |
203 | * @hw: pointer to hardware structure | |
204 | * @speed: pointer to link speed | |
205 | * @negotiation: true when autoneg or autotry is enabled | |
206 | * | |
207 | * Determines the link capabilities by reading the AUTOC register. | |
208 | **/ | |
7b25cdba DS |
209 | static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
210 | ixgbe_link_speed *speed, | |
211 | bool *negotiation) | |
11afc1b1 PW |
212 | { |
213 | s32 status = 0; | |
1eb99d5a | 214 | u32 autoc = 0; |
11afc1b1 | 215 | |
cb836a97 DS |
216 | /* Determine 1G link capabilities off of SFP+ type */ |
217 | if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || | |
218 | hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { | |
219 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
220 | *negotiation = true; | |
221 | goto out; | |
222 | } | |
223 | ||
1eb99d5a PW |
224 | /* |
225 | * Determine link capabilities based on the stored value of AUTOC, | |
226 | * which represents EEPROM defaults. If AUTOC value has not been | |
227 | * stored, use the current register value. | |
228 | */ | |
229 | if (hw->mac.orig_link_settings_stored) | |
230 | autoc = hw->mac.orig_autoc; | |
231 | else | |
232 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
233 | ||
234 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
11afc1b1 PW |
235 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
236 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
237 | *negotiation = false; | |
238 | break; | |
239 | ||
240 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
241 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
242 | *negotiation = false; | |
243 | break; | |
244 | ||
245 | case IXGBE_AUTOC_LMS_1G_AN: | |
246 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
247 | *negotiation = true; | |
248 | break; | |
249 | ||
250 | case IXGBE_AUTOC_LMS_10G_SERIAL: | |
251 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
252 | *negotiation = false; | |
253 | break; | |
254 | ||
255 | case IXGBE_AUTOC_LMS_KX4_KX_KR: | |
256 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: | |
257 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 258 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
11afc1b1 | 259 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 260 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
11afc1b1 | 261 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 262 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
11afc1b1 PW |
263 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
264 | *negotiation = true; | |
265 | break; | |
266 | ||
267 | case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: | |
268 | *speed = IXGBE_LINK_SPEED_100_FULL; | |
1eb99d5a | 269 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
11afc1b1 | 270 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 271 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
11afc1b1 | 272 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 273 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
11afc1b1 PW |
274 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
275 | *negotiation = true; | |
276 | break; | |
277 | ||
278 | case IXGBE_AUTOC_LMS_SGMII_1G_100M: | |
279 | *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; | |
280 | *negotiation = false; | |
281 | break; | |
282 | ||
283 | default: | |
284 | status = IXGBE_ERR_LINK_SETUP; | |
285 | goto out; | |
286 | break; | |
287 | } | |
288 | ||
289 | if (hw->phy.multispeed_fiber) { | |
290 | *speed |= IXGBE_LINK_SPEED_10GB_FULL | | |
291 | IXGBE_LINK_SPEED_1GB_FULL; | |
292 | *negotiation = true; | |
293 | } | |
294 | ||
295 | out: | |
296 | return status; | |
297 | } | |
298 | ||
11afc1b1 PW |
299 | /** |
300 | * ixgbe_get_media_type_82599 - Get media type | |
301 | * @hw: pointer to hardware structure | |
302 | * | |
303 | * Returns the media type (fiber, copper, backplane) | |
304 | **/ | |
7b25cdba | 305 | static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
306 | { |
307 | enum ixgbe_media_type media_type; | |
308 | ||
309 | /* Detect if there is a copper PHY attached. */ | |
310 | if (hw->phy.type == ixgbe_phy_cu_unknown || | |
fe15e8e1 DS |
311 | hw->phy.type == ixgbe_phy_tn || |
312 | hw->phy.type == ixgbe_phy_aq) { | |
11afc1b1 PW |
313 | media_type = ixgbe_media_type_copper; |
314 | goto out; | |
315 | } | |
316 | ||
317 | switch (hw->device_id) { | |
11afc1b1 | 318 | case IXGBE_DEV_ID_82599_KX4: |
dbfec662 | 319 | case IXGBE_DEV_ID_82599_KX4_MEZZ: |
312eb931 | 320 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
74757d49 | 321 | case IXGBE_DEV_ID_82599_KR: |
dbffcb21 | 322 | case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: |
1fcf03e6 | 323 | case IXGBE_DEV_ID_82599_XAUI_LOM: |
11afc1b1 PW |
324 | /* Default device ID is mezzanine card KX/KX4 */ |
325 | media_type = ixgbe_media_type_backplane; | |
326 | break; | |
327 | case IXGBE_DEV_ID_82599_SFP: | |
dbffcb21 | 328 | case IXGBE_DEV_ID_82599_SFP_FCOE: |
38ad1c8e | 329 | case IXGBE_DEV_ID_82599_SFP_EM: |
11afc1b1 PW |
330 | media_type = ixgbe_media_type_fiber; |
331 | break; | |
8911184f | 332 | case IXGBE_DEV_ID_82599_CX4: |
6b1be199 | 333 | media_type = ixgbe_media_type_cx4; |
8911184f | 334 | break; |
11afc1b1 PW |
335 | default: |
336 | media_type = ixgbe_media_type_unknown; | |
337 | break; | |
338 | } | |
339 | out: | |
340 | return media_type; | |
341 | } | |
342 | ||
343 | /** | |
8620a103 | 344 | * ixgbe_start_mac_link_82599 - Setup MAC link settings |
11afc1b1 | 345 | * @hw: pointer to hardware structure |
8620a103 | 346 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
11afc1b1 PW |
347 | * |
348 | * Configures link settings based on values in the ixgbe_hw struct. | |
349 | * Restarts the link. Performs autonegotiation if needed. | |
350 | **/ | |
5d5b7c39 | 351 | static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, |
8620a103 | 352 | bool autoneg_wait_to_complete) |
11afc1b1 PW |
353 | { |
354 | u32 autoc_reg; | |
355 | u32 links_reg; | |
356 | u32 i; | |
357 | s32 status = 0; | |
358 | ||
359 | /* Restart link */ | |
360 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
361 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; | |
362 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
363 | ||
364 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 365 | if (autoneg_wait_to_complete) { |
11afc1b1 PW |
366 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
367 | IXGBE_AUTOC_LMS_KX4_KX_KR || | |
368 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
369 | IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || | |
370 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
371 | IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { | |
372 | links_reg = 0; /* Just in case Autoneg time = 0 */ | |
373 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
374 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
375 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
376 | break; | |
377 | msleep(100); | |
378 | } | |
379 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
380 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
381 | hw_dbg(hw, "Autoneg did not complete.\n"); | |
382 | } | |
383 | } | |
384 | } | |
385 | ||
11afc1b1 PW |
386 | /* Add delay to filter out noises during initial link setup */ |
387 | msleep(50); | |
388 | ||
389 | return status; | |
390 | } | |
391 | ||
61fac744 PW |
392 | /** |
393 | * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser | |
394 | * @hw: pointer to hardware structure | |
395 | * | |
396 | * The base drivers may require better control over SFP+ module | |
397 | * PHY states. This includes selectively shutting down the Tx | |
398 | * laser on the PHY, effectively halting physical link. | |
399 | **/ | |
5d5b7c39 | 400 | static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
61fac744 PW |
401 | { |
402 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
403 | ||
404 | /* Disable tx laser; allow 100us to go dark per spec */ | |
405 | esdp_reg |= IXGBE_ESDP_SDP3; | |
406 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); | |
407 | IXGBE_WRITE_FLUSH(hw); | |
408 | udelay(100); | |
409 | } | |
410 | ||
411 | /** | |
412 | * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser | |
413 | * @hw: pointer to hardware structure | |
414 | * | |
415 | * The base drivers may require better control over SFP+ module | |
416 | * PHY states. This includes selectively turning on the Tx | |
417 | * laser on the PHY, effectively starting physical link. | |
418 | **/ | |
5d5b7c39 | 419 | static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
61fac744 PW |
420 | { |
421 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
422 | ||
423 | /* Enable tx laser; allow 100ms to light up */ | |
424 | esdp_reg &= ~IXGBE_ESDP_SDP3; | |
425 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); | |
426 | IXGBE_WRITE_FLUSH(hw); | |
427 | msleep(100); | |
428 | } | |
429 | ||
1097cd17 MC |
430 | /** |
431 | * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser | |
432 | * @hw: pointer to hardware structure | |
433 | * | |
434 | * When the driver changes the link speeds that it can support, | |
435 | * it sets autotry_restart to true to indicate that we need to | |
436 | * initiate a new autotry session with the link partner. To do | |
437 | * so, we set the speed then disable and re-enable the tx laser, to | |
438 | * alert the link partner that it also needs to restart autotry on its | |
439 | * end. This is consistent with true clause 37 autoneg, which also | |
440 | * involves a loss of signal. | |
441 | **/ | |
5d5b7c39 | 442 | static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
1097cd17 | 443 | { |
1097cd17 MC |
444 | hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n"); |
445 | ||
446 | if (hw->mac.autotry_restart) { | |
61fac744 PW |
447 | ixgbe_disable_tx_laser_multispeed_fiber(hw); |
448 | ixgbe_enable_tx_laser_multispeed_fiber(hw); | |
1097cd17 MC |
449 | hw->mac.autotry_restart = false; |
450 | } | |
451 | } | |
452 | ||
11afc1b1 | 453 | /** |
8620a103 | 454 | * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed |
11afc1b1 PW |
455 | * @hw: pointer to hardware structure |
456 | * @speed: new link speed | |
457 | * @autoneg: true if autonegotiation enabled | |
458 | * @autoneg_wait_to_complete: true when waiting for completion is needed | |
459 | * | |
460 | * Set the link speed in the AUTOC register and restarts link. | |
461 | **/ | |
8620a103 MC |
462 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
463 | ixgbe_link_speed speed, | |
464 | bool autoneg, | |
465 | bool autoneg_wait_to_complete) | |
11afc1b1 PW |
466 | { |
467 | s32 status = 0; | |
468 | ixgbe_link_speed phy_link_speed; | |
469 | ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; | |
470 | u32 speedcnt = 0; | |
471 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
472 | bool link_up = false; | |
473 | bool negotiation; | |
50ac58ba | 474 | int i; |
11afc1b1 PW |
475 | |
476 | /* Mask off requested but non-supported speeds */ | |
477 | hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation); | |
478 | speed &= phy_link_speed; | |
479 | ||
480 | /* | |
481 | * Try each speed one by one, highest priority first. We do this in | |
482 | * software because 10gb fiber doesn't support speed autonegotiation. | |
483 | */ | |
484 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { | |
485 | speedcnt++; | |
486 | highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
487 | ||
50ac58ba PWJ |
488 | /* If we already have link at this speed, just jump out */ |
489 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); | |
490 | ||
491 | if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) | |
492 | goto out; | |
493 | ||
494 | /* Set the module link speed */ | |
11afc1b1 PW |
495 | esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); |
496 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); | |
1097cd17 | 497 | IXGBE_WRITE_FLUSH(hw); |
11afc1b1 | 498 | |
50ac58ba PWJ |
499 | /* Allow module to change analog characteristics (1G->10G) */ |
500 | msleep(40); | |
11afc1b1 | 501 | |
8620a103 MC |
502 | status = ixgbe_setup_mac_link_82599(hw, |
503 | IXGBE_LINK_SPEED_10GB_FULL, | |
504 | autoneg, | |
505 | autoneg_wait_to_complete); | |
50ac58ba | 506 | if (status != 0) |
c3c74327 | 507 | return status; |
50ac58ba PWJ |
508 | |
509 | /* Flap the tx laser if it has not already been done */ | |
1097cd17 | 510 | hw->mac.ops.flap_tx_laser(hw); |
50ac58ba | 511 | |
cd7e1f0b DS |
512 | /* |
513 | * Wait for the controller to acquire link. Per IEEE 802.3ap, | |
514 | * Section 73.10.2, we may have to wait up to 500ms if KR is | |
515 | * attempted. 82599 uses the same timing for 10g SFI. | |
516 | */ | |
517 | ||
50ac58ba PWJ |
518 | for (i = 0; i < 5; i++) { |
519 | /* Wait for the link partner to also set speed */ | |
520 | msleep(100); | |
521 | ||
522 | /* If we have link, just jump out */ | |
523 | hw->mac.ops.check_link(hw, &phy_link_speed, | |
524 | &link_up, false); | |
525 | if (link_up) | |
526 | goto out; | |
527 | } | |
11afc1b1 PW |
528 | } |
529 | ||
530 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { | |
531 | speedcnt++; | |
532 | if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) | |
533 | highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; | |
534 | ||
50ac58ba PWJ |
535 | /* If we already have link at this speed, just jump out */ |
536 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); | |
537 | ||
538 | if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) | |
539 | goto out; | |
540 | ||
541 | /* Set the module link speed */ | |
11afc1b1 PW |
542 | esdp_reg &= ~IXGBE_ESDP_SDP5; |
543 | esdp_reg |= IXGBE_ESDP_SDP5_DIR; | |
544 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); | |
1097cd17 | 545 | IXGBE_WRITE_FLUSH(hw); |
11afc1b1 | 546 | |
50ac58ba PWJ |
547 | /* Allow module to change analog characteristics (10G->1G) */ |
548 | msleep(40); | |
11afc1b1 | 549 | |
8620a103 | 550 | status = ixgbe_setup_mac_link_82599(hw, |
50ac58ba PWJ |
551 | IXGBE_LINK_SPEED_1GB_FULL, |
552 | autoneg, | |
553 | autoneg_wait_to_complete); | |
554 | if (status != 0) | |
c3c74327 | 555 | return status; |
50ac58ba PWJ |
556 | |
557 | /* Flap the tx laser if it has not already been done */ | |
1097cd17 | 558 | hw->mac.ops.flap_tx_laser(hw); |
50ac58ba PWJ |
559 | |
560 | /* Wait for the link partner to also set speed */ | |
561 | msleep(100); | |
11afc1b1 PW |
562 | |
563 | /* If we have link, just jump out */ | |
564 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); | |
565 | if (link_up) | |
566 | goto out; | |
567 | } | |
568 | ||
569 | /* | |
570 | * We didn't get link. Configure back to the highest speed we tried, | |
571 | * (if there was more than one). We call ourselves back with just the | |
572 | * single highest speed that the user requested. | |
573 | */ | |
574 | if (speedcnt > 1) | |
8620a103 MC |
575 | status = ixgbe_setup_mac_link_multispeed_fiber(hw, |
576 | highest_link_speed, | |
577 | autoneg, | |
578 | autoneg_wait_to_complete); | |
11afc1b1 PW |
579 | |
580 | out: | |
c3c74327 MC |
581 | /* Set autoneg_advertised value based on input link speed */ |
582 | hw->phy.autoneg_advertised = 0; | |
583 | ||
584 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
585 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; | |
586 | ||
587 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
588 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; | |
589 | ||
11afc1b1 PW |
590 | return status; |
591 | } | |
592 | ||
cd7e1f0b DS |
593 | /** |
594 | * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed | |
595 | * @hw: pointer to hardware structure | |
596 | * @speed: new link speed | |
597 | * @autoneg: true if autonegotiation enabled | |
598 | * @autoneg_wait_to_complete: true when waiting for completion is needed | |
599 | * | |
600 | * Implements the Intel SmartSpeed algorithm. | |
601 | **/ | |
602 | static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, | |
603 | ixgbe_link_speed speed, bool autoneg, | |
604 | bool autoneg_wait_to_complete) | |
605 | { | |
606 | s32 status = 0; | |
607 | ixgbe_link_speed link_speed; | |
608 | s32 i, j; | |
609 | bool link_up = false; | |
610 | u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
c4ee6a53 | 611 | struct ixgbe_adapter *adapter = hw->back; |
cd7e1f0b DS |
612 | |
613 | hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n"); | |
614 | ||
615 | /* Set autoneg_advertised value based on input link speed */ | |
616 | hw->phy.autoneg_advertised = 0; | |
617 | ||
618 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
619 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; | |
620 | ||
621 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
622 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; | |
623 | ||
624 | if (speed & IXGBE_LINK_SPEED_100_FULL) | |
625 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; | |
626 | ||
627 | /* | |
628 | * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the | |
629 | * autoneg advertisement if link is unable to be established at the | |
630 | * highest negotiated rate. This can sometimes happen due to integrity | |
631 | * issues with the physical media connection. | |
632 | */ | |
633 | ||
634 | /* First, try to get link with full advertisement */ | |
635 | hw->phy.smart_speed_active = false; | |
636 | for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { | |
637 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, | |
638 | autoneg_wait_to_complete); | |
639 | if (status) | |
640 | goto out; | |
641 | ||
642 | /* | |
643 | * Wait for the controller to acquire link. Per IEEE 802.3ap, | |
644 | * Section 73.10.2, we may have to wait up to 500ms if KR is | |
645 | * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per | |
646 | * Table 9 in the AN MAS. | |
647 | */ | |
648 | for (i = 0; i < 5; i++) { | |
649 | mdelay(100); | |
650 | ||
651 | /* If we have link, just jump out */ | |
652 | hw->mac.ops.check_link(hw, &link_speed, | |
653 | &link_up, false); | |
654 | if (link_up) | |
655 | goto out; | |
656 | } | |
657 | } | |
658 | ||
659 | /* | |
660 | * We didn't get link. If we advertised KR plus one of KX4/KX | |
661 | * (or BX4/BX), then disable KR and try again. | |
662 | */ | |
663 | if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || | |
664 | ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) | |
665 | goto out; | |
666 | ||
667 | /* Turn SmartSpeed on to disable KR support */ | |
668 | hw->phy.smart_speed_active = true; | |
669 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, | |
670 | autoneg_wait_to_complete); | |
671 | if (status) | |
672 | goto out; | |
673 | ||
674 | /* | |
675 | * Wait for the controller to acquire link. 600ms will allow for | |
676 | * the AN link_fail_inhibit_timer as well for multiple cycles of | |
677 | * parallel detect, both 10g and 1g. This allows for the maximum | |
678 | * connect attempts as defined in the AN MAS table 73-7. | |
679 | */ | |
680 | for (i = 0; i < 6; i++) { | |
681 | mdelay(100); | |
682 | ||
683 | /* If we have link, just jump out */ | |
684 | hw->mac.ops.check_link(hw, &link_speed, | |
685 | &link_up, false); | |
686 | if (link_up) | |
687 | goto out; | |
688 | } | |
689 | ||
690 | /* We didn't get link. Turn SmartSpeed back off. */ | |
691 | hw->phy.smart_speed_active = false; | |
692 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, | |
693 | autoneg_wait_to_complete); | |
694 | ||
695 | out: | |
c4ee6a53 | 696 | if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) |
396e799c | 697 | e_info(hw, "Smartspeed has downgraded the link speed from " |
849c4542 | 698 | "the maximum advertised\n"); |
cd7e1f0b DS |
699 | return status; |
700 | } | |
701 | ||
11afc1b1 | 702 | /** |
8620a103 | 703 | * ixgbe_setup_mac_link_82599 - Set MAC link speed |
11afc1b1 PW |
704 | * @hw: pointer to hardware structure |
705 | * @speed: new link speed | |
706 | * @autoneg: true if autonegotiation enabled | |
707 | * @autoneg_wait_to_complete: true when waiting for completion is needed | |
708 | * | |
709 | * Set the link speed in the AUTOC register and restarts link. | |
710 | **/ | |
5d5b7c39 | 711 | static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, |
8620a103 MC |
712 | ixgbe_link_speed speed, bool autoneg, |
713 | bool autoneg_wait_to_complete) | |
11afc1b1 PW |
714 | { |
715 | s32 status = 0; | |
716 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
717 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
50ac58ba | 718 | u32 start_autoc = autoc; |
1eb99d5a | 719 | u32 orig_autoc = 0; |
11afc1b1 PW |
720 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; |
721 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
722 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; | |
723 | u32 links_reg; | |
724 | u32 i; | |
725 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
726 | ||
727 | /* Check to see if speed passed in is supported. */ | |
728 | hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); | |
729 | speed &= link_capabilities; | |
730 | ||
50ac58ba PWJ |
731 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) { |
732 | status = IXGBE_ERR_LINK_SETUP; | |
733 | goto out; | |
734 | } | |
735 | ||
1eb99d5a PW |
736 | /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ |
737 | if (hw->mac.orig_link_settings_stored) | |
738 | orig_autoc = hw->mac.orig_autoc; | |
739 | else | |
740 | orig_autoc = autoc; | |
741 | ||
742 | ||
50ac58ba PWJ |
743 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
744 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || | |
745 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { | |
11afc1b1 PW |
746 | /* Set KX4/KX/KR support according to speed requested */ |
747 | autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); | |
748 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
1eb99d5a | 749 | if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) |
11afc1b1 | 750 | autoc |= IXGBE_AUTOC_KX4_SUPP; |
cd7e1f0b DS |
751 | if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && |
752 | (hw->phy.smart_speed_active == false)) | |
11afc1b1 PW |
753 | autoc |= IXGBE_AUTOC_KR_SUPP; |
754 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
755 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
756 | } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && | |
757 | (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || | |
758 | link_mode == IXGBE_AUTOC_LMS_1G_AN)) { | |
759 | /* Switch from 1G SFI to 10G SFI if requested */ | |
760 | if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && | |
761 | (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { | |
762 | autoc &= ~IXGBE_AUTOC_LMS_MASK; | |
763 | autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; | |
764 | } | |
765 | } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && | |
766 | (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { | |
767 | /* Switch from 10G SFI to 1G SFI if requested */ | |
768 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && | |
769 | (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { | |
770 | autoc &= ~IXGBE_AUTOC_LMS_MASK; | |
771 | if (autoneg) | |
772 | autoc |= IXGBE_AUTOC_LMS_1G_AN; | |
773 | else | |
774 | autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; | |
775 | } | |
776 | } | |
777 | ||
50ac58ba | 778 | if (autoc != start_autoc) { |
11afc1b1 PW |
779 | /* Restart link */ |
780 | autoc |= IXGBE_AUTOC_AN_RESTART; | |
781 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
782 | ||
783 | /* Only poll for autoneg to complete if specified to do so */ | |
784 | if (autoneg_wait_to_complete) { | |
785 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || | |
786 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || | |
787 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { | |
788 | links_reg = 0; /*Just in case Autoneg time=0*/ | |
789 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
790 | links_reg = | |
791 | IXGBE_READ_REG(hw, IXGBE_LINKS); | |
792 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
793 | break; | |
794 | msleep(100); | |
795 | } | |
796 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
797 | status = | |
798 | IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
799 | hw_dbg(hw, "Autoneg did not " | |
800 | "complete.\n"); | |
801 | } | |
802 | } | |
803 | } | |
804 | ||
11afc1b1 PW |
805 | /* Add delay to filter out noises during initial link setup */ |
806 | msleep(50); | |
807 | } | |
808 | ||
50ac58ba | 809 | out: |
11afc1b1 PW |
810 | return status; |
811 | } | |
812 | ||
813 | /** | |
8620a103 | 814 | * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field |
11afc1b1 PW |
815 | * @hw: pointer to hardware structure |
816 | * @speed: new link speed | |
817 | * @autoneg: true if autonegotiation enabled | |
818 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
819 | * | |
820 | * Restarts link on PHY and MAC based on settings passed in. | |
821 | **/ | |
8620a103 MC |
822 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, |
823 | ixgbe_link_speed speed, | |
824 | bool autoneg, | |
825 | bool autoneg_wait_to_complete) | |
11afc1b1 PW |
826 | { |
827 | s32 status; | |
828 | ||
829 | /* Setup the PHY according to input speed */ | |
830 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, | |
831 | autoneg_wait_to_complete); | |
832 | /* Set up MAC */ | |
8620a103 | 833 | ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); |
11afc1b1 PW |
834 | |
835 | return status; | |
836 | } | |
837 | ||
838 | /** | |
839 | * ixgbe_reset_hw_82599 - Perform hardware reset | |
840 | * @hw: pointer to hardware structure | |
841 | * | |
842 | * Resets the hardware by resetting the transmit and receive units, masks | |
843 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) | |
844 | * reset. | |
845 | **/ | |
7b25cdba | 846 | static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
847 | { |
848 | s32 status = 0; | |
c9205697 | 849 | u32 ctrl; |
11afc1b1 PW |
850 | u32 i; |
851 | u32 autoc; | |
852 | u32 autoc2; | |
853 | ||
854 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
855 | hw->mac.ops.stop_adapter(hw); | |
856 | ||
553b4497 | 857 | /* PHY ops must be identified and initialized prior to reset */ |
04f165ef | 858 | |
553b4497 PW |
859 | /* Init PHY and function pointers, perform SFP setup */ |
860 | status = hw->phy.ops.init(hw); | |
04f165ef | 861 | |
553b4497 PW |
862 | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) |
863 | goto reset_hw_out; | |
04f165ef | 864 | |
553b4497 PW |
865 | /* Setup SFP module if there is one present. */ |
866 | if (hw->phy.sfp_setup_needed) { | |
867 | status = hw->mac.ops.setup_sfp(hw); | |
868 | hw->phy.sfp_setup_needed = false; | |
04f165ef | 869 | } |
11afc1b1 | 870 | |
553b4497 PW |
871 | /* Reset PHY */ |
872 | if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) | |
873 | hw->phy.ops.reset(hw); | |
874 | ||
11afc1b1 PW |
875 | /* |
876 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
877 | * access and verify no pending requests before reset | |
878 | */ | |
04f165ef PW |
879 | status = ixgbe_disable_pcie_master(hw); |
880 | if (status != 0) { | |
11afc1b1 PW |
881 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
882 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
883 | } | |
884 | ||
885 | /* | |
886 | * Issue global reset to the MAC. This needs to be a SW reset. | |
887 | * If link reset is used, it might reset the MAC when mng is using it | |
888 | */ | |
889 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
890 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); | |
891 | IXGBE_WRITE_FLUSH(hw); | |
892 | ||
893 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
894 | for (i = 0; i < 10; i++) { | |
895 | udelay(1); | |
896 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
897 | if (!(ctrl & IXGBE_CTRL_RST)) | |
898 | break; | |
899 | } | |
900 | if (ctrl & IXGBE_CTRL_RST) { | |
901 | status = IXGBE_ERR_RESET_FAILED; | |
902 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
903 | } | |
11afc1b1 PW |
904 | |
905 | msleep(50); | |
906 | ||
11afc1b1 PW |
907 | /* |
908 | * Store the original AUTOC/AUTOC2 values if they have not been | |
909 | * stored off yet. Otherwise restore the stored original | |
910 | * values since the reset operation sets back to defaults. | |
911 | */ | |
912 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
913 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
914 | if (hw->mac.orig_link_settings_stored == false) { | |
915 | hw->mac.orig_autoc = autoc; | |
916 | hw->mac.orig_autoc2 = autoc2; | |
917 | hw->mac.orig_link_settings_stored = true; | |
4df10466 | 918 | } else { |
11afc1b1 PW |
919 | if (autoc != hw->mac.orig_autoc) |
920 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | | |
921 | IXGBE_AUTOC_AN_RESTART)); | |
922 | ||
923 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != | |
924 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { | |
925 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; | |
926 | autoc2 |= (hw->mac.orig_autoc2 & | |
927 | IXGBE_AUTOC2_UPPER_MASK); | |
928 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); | |
929 | } | |
930 | } | |
931 | ||
aca6bee7 WJP |
932 | /* |
933 | * Store MAC address from RAR0, clear receive address registers, and | |
934 | * clear the multicast table. Also reset num_rar_entries to 128, | |
935 | * since we modify this value when programming the SAN MAC address. | |
936 | */ | |
937 | hw->mac.num_rar_entries = 128; | |
938 | hw->mac.ops.init_rx_addrs(hw); | |
939 | ||
11afc1b1 PW |
940 | /* Store the permanent mac address */ |
941 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
942 | ||
0365e6e4 PW |
943 | /* Store the permanent SAN mac address */ |
944 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | |
945 | ||
aca6bee7 WJP |
946 | /* Add the SAN MAC address to the RAR only if it's a valid address */ |
947 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | |
948 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, | |
949 | hw->mac.san_addr, 0, IXGBE_RAH_AV); | |
950 | ||
951 | /* Reserve the last RAR for the SAN MAC address */ | |
952 | hw->mac.num_rar_entries--; | |
953 | } | |
954 | ||
383ff34b YZ |
955 | /* Store the alternative WWNN/WWPN prefix */ |
956 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | |
957 | &hw->mac.wwpn_prefix); | |
958 | ||
04f165ef | 959 | reset_hw_out: |
11afc1b1 PW |
960 | return status; |
961 | } | |
962 | ||
ffff4772 PWJ |
963 | /** |
964 | * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. | |
965 | * @hw: pointer to hardware structure | |
966 | **/ | |
967 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) | |
968 | { | |
969 | int i; | |
970 | u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); | |
971 | fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; | |
972 | ||
973 | /* | |
974 | * Before starting reinitialization process, | |
975 | * FDIRCMD.CMD must be zero. | |
976 | */ | |
977 | for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { | |
978 | if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & | |
979 | IXGBE_FDIRCMD_CMD_MASK)) | |
980 | break; | |
981 | udelay(10); | |
982 | } | |
983 | if (i >= IXGBE_FDIRCMD_CMD_POLL) { | |
984 | hw_dbg(hw ,"Flow Director previous command isn't complete, " | |
d6dbee86 | 985 | "aborting table re-initialization.\n"); |
ffff4772 PWJ |
986 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
987 | } | |
988 | ||
989 | IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); | |
990 | IXGBE_WRITE_FLUSH(hw); | |
991 | /* | |
992 | * 82599 adapters flow director init flow cannot be restarted, | |
993 | * Workaround 82599 silicon errata by performing the following steps | |
994 | * before re-writing the FDIRCTRL control register with the same value. | |
995 | * - write 1 to bit 8 of FDIRCMD register & | |
996 | * - write 0 to bit 8 of FDIRCMD register | |
997 | */ | |
998 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, | |
999 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | | |
1000 | IXGBE_FDIRCMD_CLEARHT)); | |
1001 | IXGBE_WRITE_FLUSH(hw); | |
1002 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, | |
1003 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & | |
1004 | ~IXGBE_FDIRCMD_CLEARHT)); | |
1005 | IXGBE_WRITE_FLUSH(hw); | |
1006 | /* | |
1007 | * Clear FDIR Hash register to clear any leftover hashes | |
1008 | * waiting to be programmed. | |
1009 | */ | |
1010 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); | |
1011 | IXGBE_WRITE_FLUSH(hw); | |
1012 | ||
1013 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); | |
1014 | IXGBE_WRITE_FLUSH(hw); | |
1015 | ||
1016 | /* Poll init-done after we write FDIRCTRL register */ | |
1017 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { | |
1018 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & | |
1019 | IXGBE_FDIRCTRL_INIT_DONE) | |
1020 | break; | |
1021 | udelay(10); | |
1022 | } | |
1023 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) { | |
1024 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); | |
1025 | return IXGBE_ERR_FDIR_REINIT_FAILED; | |
1026 | } | |
1027 | ||
1028 | /* Clear FDIR statistics registers (read to clear) */ | |
1029 | IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); | |
1030 | IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); | |
1031 | IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); | |
1032 | IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
1033 | IXGBE_READ_REG(hw, IXGBE_FDIRLEN); | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /** | |
1039 | * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters | |
1040 | * @hw: pointer to hardware structure | |
1041 | * @pballoc: which mode to allocate filters with | |
1042 | **/ | |
1043 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) | |
1044 | { | |
1045 | u32 fdirctrl = 0; | |
1046 | u32 pbsize; | |
1047 | int i; | |
1048 | ||
1049 | /* | |
1050 | * Before enabling Flow Director, the Rx Packet Buffer size | |
1051 | * must be reduced. The new value is the current size minus | |
1052 | * flow director memory usage size. | |
1053 | */ | |
1054 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); | |
1055 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), | |
1056 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); | |
1057 | ||
1058 | /* | |
1059 | * The defaults in the HW for RX PB 1-7 are not zero and so should be | |
1060 | * intialized to zero for non DCB mode otherwise actual total RX PB | |
1061 | * would be bigger than programmed and filter space would run into | |
1062 | * the PB 0 region. | |
1063 | */ | |
1064 | for (i = 1; i < 8; i++) | |
1065 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); | |
1066 | ||
1067 | /* Send interrupt when 64 filters are left */ | |
1068 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; | |
1069 | ||
1070 | /* Set the maximum length per hash bucket to 0xA filters */ | |
1071 | fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; | |
1072 | ||
1073 | switch (pballoc) { | |
1074 | case IXGBE_FDIR_PBALLOC_64K: | |
1075 | /* 8k - 1 signature filters */ | |
1076 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; | |
1077 | break; | |
1078 | case IXGBE_FDIR_PBALLOC_128K: | |
1079 | /* 16k - 1 signature filters */ | |
1080 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; | |
1081 | break; | |
1082 | case IXGBE_FDIR_PBALLOC_256K: | |
1083 | /* 32k - 1 signature filters */ | |
1084 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; | |
1085 | break; | |
1086 | default: | |
1087 | /* bad value */ | |
1088 | return IXGBE_ERR_CONFIG; | |
1089 | }; | |
1090 | ||
1091 | /* Move the flexible bytes to use the ethertype - shift 6 words */ | |
1092 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); | |
1093 | ||
1094 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; | |
1095 | ||
1096 | /* Prime the keys for hashing */ | |
1097 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, | |
1098 | htonl(IXGBE_ATR_BUCKET_HASH_KEY)); | |
1099 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, | |
1100 | htonl(IXGBE_ATR_SIGNATURE_HASH_KEY)); | |
1101 | ||
1102 | /* | |
1103 | * Poll init-done after we write the register. Estimated times: | |
1104 | * 10G: PBALLOC = 11b, timing is 60us | |
1105 | * 1G: PBALLOC = 11b, timing is 600us | |
1106 | * 100M: PBALLOC = 11b, timing is 6ms | |
1107 | * | |
1108 | * Multiple these timings by 4 if under full Rx load | |
1109 | * | |
1110 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for | |
1111 | * 1 msec per poll time. If we're at line rate and drop to 100M, then | |
1112 | * this might not finish in our poll time, but we can live with that | |
1113 | * for now. | |
1114 | */ | |
1115 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); | |
1116 | IXGBE_WRITE_FLUSH(hw); | |
1117 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { | |
1118 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & | |
1119 | IXGBE_FDIRCTRL_INIT_DONE) | |
1120 | break; | |
1121 | msleep(1); | |
1122 | } | |
1123 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) | |
1124 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters | |
1131 | * @hw: pointer to hardware structure | |
1132 | * @pballoc: which mode to allocate filters with | |
1133 | **/ | |
1134 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) | |
1135 | { | |
1136 | u32 fdirctrl = 0; | |
1137 | u32 pbsize; | |
1138 | int i; | |
1139 | ||
1140 | /* | |
1141 | * Before enabling Flow Director, the Rx Packet Buffer size | |
1142 | * must be reduced. The new value is the current size minus | |
1143 | * flow director memory usage size. | |
1144 | */ | |
1145 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); | |
1146 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), | |
1147 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); | |
1148 | ||
1149 | /* | |
1150 | * The defaults in the HW for RX PB 1-7 are not zero and so should be | |
1151 | * intialized to zero for non DCB mode otherwise actual total RX PB | |
1152 | * would be bigger than programmed and filter space would run into | |
1153 | * the PB 0 region. | |
1154 | */ | |
1155 | for (i = 1; i < 8; i++) | |
1156 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); | |
1157 | ||
1158 | /* Send interrupt when 64 filters are left */ | |
1159 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; | |
1160 | ||
9a713e7c PW |
1161 | /* Initialize the drop queue to Rx queue 127 */ |
1162 | fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT); | |
1163 | ||
ffff4772 PWJ |
1164 | switch (pballoc) { |
1165 | case IXGBE_FDIR_PBALLOC_64K: | |
1166 | /* 2k - 1 perfect filters */ | |
1167 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; | |
1168 | break; | |
1169 | case IXGBE_FDIR_PBALLOC_128K: | |
1170 | /* 4k - 1 perfect filters */ | |
1171 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; | |
1172 | break; | |
1173 | case IXGBE_FDIR_PBALLOC_256K: | |
1174 | /* 8k - 1 perfect filters */ | |
1175 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; | |
1176 | break; | |
1177 | default: | |
1178 | /* bad value */ | |
1179 | return IXGBE_ERR_CONFIG; | |
1180 | }; | |
1181 | ||
1182 | /* Turn perfect match filtering on */ | |
1183 | fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; | |
1184 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; | |
1185 | ||
1186 | /* Move the flexible bytes to use the ethertype - shift 6 words */ | |
1187 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); | |
1188 | ||
1189 | /* Prime the keys for hashing */ | |
1190 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, | |
1191 | htonl(IXGBE_ATR_BUCKET_HASH_KEY)); | |
1192 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, | |
1193 | htonl(IXGBE_ATR_SIGNATURE_HASH_KEY)); | |
1194 | ||
1195 | /* | |
1196 | * Poll init-done after we write the register. Estimated times: | |
1197 | * 10G: PBALLOC = 11b, timing is 60us | |
1198 | * 1G: PBALLOC = 11b, timing is 600us | |
1199 | * 100M: PBALLOC = 11b, timing is 6ms | |
1200 | * | |
1201 | * Multiple these timings by 4 if under full Rx load | |
1202 | * | |
1203 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for | |
1204 | * 1 msec per poll time. If we're at line rate and drop to 100M, then | |
1205 | * this might not finish in our poll time, but we can live with that | |
1206 | * for now. | |
1207 | */ | |
1208 | ||
1209 | /* Set the maximum length per hash bucket to 0xA filters */ | |
1210 | fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); | |
1211 | ||
1212 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); | |
1213 | IXGBE_WRITE_FLUSH(hw); | |
1214 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { | |
1215 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & | |
1216 | IXGBE_FDIRCTRL_INIT_DONE) | |
1217 | break; | |
1218 | msleep(1); | |
1219 | } | |
1220 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) | |
1221 | hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n"); | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | ||
1227 | /** | |
1228 | * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR | |
1229 | * @stream: input bitstream to compute the hash on | |
1230 | * @key: 32-bit hash key | |
1231 | **/ | |
7b25cdba DS |
1232 | static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, |
1233 | u32 key) | |
ffff4772 PWJ |
1234 | { |
1235 | /* | |
1236 | * The algorithm is as follows: | |
1237 | * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 | |
1238 | * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] | |
1239 | * and A[n] x B[n] is bitwise AND between same length strings | |
1240 | * | |
1241 | * K[n] is 16 bits, defined as: | |
1242 | * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] | |
1243 | * for n modulo 32 < 15, K[n] = | |
1244 | * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] | |
1245 | * | |
1246 | * S[n] is 16 bits, defined as: | |
1247 | * for n >= 15, S[n] = S[n:n - 15] | |
1248 | * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] | |
1249 | * | |
1250 | * To simplify for programming, the algorithm is implemented | |
1251 | * in software this way: | |
1252 | * | |
1253 | * Key[31:0], Stream[335:0] | |
1254 | * | |
1255 | * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times | |
1256 | * int_key[350:0] = tmp_key[351:1] | |
1257 | * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321] | |
1258 | * | |
1259 | * hash[15:0] = 0; | |
1260 | * for (i = 0; i < 351; i++) { | |
1261 | * if (int_key[i]) | |
1262 | * hash ^= int_stream[(i + 15):i]; | |
1263 | * } | |
1264 | */ | |
1265 | ||
1266 | union { | |
1267 | u64 fill[6]; | |
1268 | u32 key[11]; | |
1269 | u8 key_stream[44]; | |
1270 | } tmp_key; | |
1271 | ||
1272 | u8 *stream = (u8 *)atr_input; | |
1273 | u8 int_key[44]; /* upper-most bit unused */ | |
1274 | u8 hash_str[46]; /* upper-most 2 bits unused */ | |
1275 | u16 hash_result = 0; | |
1276 | int i, j, k, h; | |
1277 | ||
1278 | /* | |
1279 | * Initialize the fill member to prevent warnings | |
1280 | * on some compilers | |
1281 | */ | |
1282 | tmp_key.fill[0] = 0; | |
1283 | ||
1284 | /* First load the temporary key stream */ | |
1285 | for (i = 0; i < 6; i++) { | |
1286 | u64 fillkey = ((u64)key << 32) | key; | |
1287 | tmp_key.fill[i] = fillkey; | |
1288 | } | |
1289 | ||
1290 | /* | |
1291 | * Set the interim key for the hashing. Bit 352 is unused, so we must | |
1292 | * shift and compensate when building the key. | |
1293 | */ | |
1294 | ||
1295 | int_key[0] = tmp_key.key_stream[0] >> 1; | |
1296 | for (i = 1, j = 0; i < 44; i++) { | |
1297 | unsigned int this_key = tmp_key.key_stream[j] << 7; | |
1298 | j++; | |
1299 | int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1)); | |
1300 | } | |
1301 | ||
1302 | /* | |
1303 | * Set the interim bit string for the hashing. Bits 368 and 367 are | |
1304 | * unused, so shift and compensate when building the string. | |
1305 | */ | |
1306 | hash_str[0] = (stream[40] & 0x7f) >> 1; | |
1307 | for (i = 1, j = 40; i < 46; i++) { | |
1308 | unsigned int this_str = stream[j] << 7; | |
1309 | j++; | |
1310 | if (j > 41) | |
1311 | j = 0; | |
1312 | hash_str[i] = (u8)(this_str | (stream[j] >> 1)); | |
1313 | } | |
1314 | ||
1315 | /* | |
1316 | * Now compute the hash. i is the index into hash_str, j is into our | |
1317 | * key stream, k is counting the number of bits, and h interates within | |
1318 | * each byte. | |
1319 | */ | |
1320 | for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { | |
1321 | for (h = 0; h < 8 && k < 351; h++, k++) { | |
1322 | if (int_key[j] & (1 << h)) { | |
1323 | /* | |
1324 | * Key bit is set, XOR in the current 16-bit | |
1325 | * string. Example of processing: | |
1326 | * h = 0, | |
1327 | * tmp = (hash_str[i - 2] & 0 << 16) | | |
1328 | * (hash_str[i - 1] & 0xff << 8) | | |
1329 | * (hash_str[i] & 0xff >> 0) | |
1330 | * So tmp = hash_str[15 + k:k], since the | |
1331 | * i + 2 clause rolls off the 16-bit value | |
1332 | * h = 7, | |
1333 | * tmp = (hash_str[i - 2] & 0x7f << 9) | | |
1334 | * (hash_str[i - 1] & 0xff << 1) | | |
1335 | * (hash_str[i] & 0x80 >> 7) | |
1336 | */ | |
1337 | int tmp = (hash_str[i] >> h); | |
1338 | tmp |= (hash_str[i - 1] << (8 - h)); | |
1339 | tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1)) | |
1340 | << (16 - h); | |
1341 | hash_result ^= (u16)tmp; | |
1342 | } | |
1343 | } | |
1344 | } | |
1345 | ||
1346 | return hash_result; | |
1347 | } | |
1348 | ||
1349 | /** | |
1350 | * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream | |
1351 | * @input: input stream to modify | |
1352 | * @vlan: the VLAN id to load | |
1353 | **/ | |
1354 | s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan) | |
1355 | { | |
1356 | input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8; | |
1357 | input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff; | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /** | |
1363 | * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address | |
1364 | * @input: input stream to modify | |
1365 | * @src_addr: the IP address to load | |
1366 | **/ | |
1367 | s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr) | |
1368 | { | |
1369 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24; | |
1370 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] = | |
1371 | (src_addr >> 16) & 0xff; | |
1372 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] = | |
1373 | (src_addr >> 8) & 0xff; | |
1374 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff; | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | /** | |
1380 | * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address | |
1381 | * @input: input stream to modify | |
1382 | * @dst_addr: the IP address to load | |
1383 | **/ | |
1384 | s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr) | |
1385 | { | |
1386 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24; | |
1387 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] = | |
1388 | (dst_addr >> 16) & 0xff; | |
1389 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] = | |
1390 | (dst_addr >> 8) & 0xff; | |
1391 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff; | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
ffff4772 PWJ |
1396 | /** |
1397 | * ixgbe_atr_set_src_port_82599 - Sets the source port | |
1398 | * @input: input stream to modify | |
1399 | * @src_port: the source port to load | |
1400 | **/ | |
1401 | s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port) | |
1402 | { | |
1403 | input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8; | |
1404 | input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff; | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | /** | |
1410 | * ixgbe_atr_set_dst_port_82599 - Sets the destination port | |
1411 | * @input: input stream to modify | |
1412 | * @dst_port: the destination port to load | |
1413 | **/ | |
1414 | s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port) | |
1415 | { | |
1416 | input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8; | |
1417 | input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff; | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | /** | |
1423 | * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes | |
1424 | * @input: input stream to modify | |
1425 | * @flex_bytes: the flexible bytes to load | |
1426 | **/ | |
1427 | s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte) | |
1428 | { | |
1429 | input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8; | |
1430 | input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff; | |
1431 | ||
1432 | return 0; | |
1433 | } | |
1434 | ||
ffff4772 PWJ |
1435 | /** |
1436 | * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type | |
1437 | * @input: input stream to modify | |
1438 | * @l4type: the layer 4 type value to load | |
1439 | **/ | |
1440 | s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type) | |
1441 | { | |
1442 | input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type; | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | /** | |
1448 | * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream | |
1449 | * @input: input stream to search | |
1450 | * @vlan: the VLAN id to load | |
1451 | **/ | |
9a713e7c | 1452 | static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan) |
ffff4772 PWJ |
1453 | { |
1454 | *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET]; | |
1455 | *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8; | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | /** | |
1461 | * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address | |
1462 | * @input: input stream to search | |
1463 | * @src_addr: the IP address to load | |
1464 | **/ | |
7b25cdba DS |
1465 | static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, |
1466 | u32 *src_addr) | |
ffff4772 PWJ |
1467 | { |
1468 | *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET]; | |
1469 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8; | |
1470 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16; | |
1471 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24; | |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | /** | |
1477 | * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address | |
1478 | * @input: input stream to search | |
1479 | * @dst_addr: the IP address to load | |
1480 | **/ | |
7b25cdba DS |
1481 | static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, |
1482 | u32 *dst_addr) | |
ffff4772 PWJ |
1483 | { |
1484 | *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET]; | |
1485 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8; | |
1486 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16; | |
1487 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24; | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | /** | |
1493 | * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address | |
1494 | * @input: input stream to search | |
1495 | * @src_addr_1: the first 4 bytes of the IP address to load | |
1496 | * @src_addr_2: the second 4 bytes of the IP address to load | |
1497 | * @src_addr_3: the third 4 bytes of the IP address to load | |
1498 | * @src_addr_4: the fourth 4 bytes of the IP address to load | |
1499 | **/ | |
7b25cdba DS |
1500 | static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, |
1501 | u32 *src_addr_1, u32 *src_addr_2, | |
1502 | u32 *src_addr_3, u32 *src_addr_4) | |
ffff4772 PWJ |
1503 | { |
1504 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12]; | |
1505 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8; | |
1506 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16; | |
1507 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24; | |
1508 | ||
1509 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8]; | |
1510 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8; | |
1511 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16; | |
1512 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24; | |
1513 | ||
1514 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4]; | |
1515 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8; | |
1516 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16; | |
1517 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24; | |
1518 | ||
1519 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET]; | |
1520 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8; | |
1521 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16; | |
1522 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24; | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
ffff4772 PWJ |
1527 | /** |
1528 | * ixgbe_atr_get_src_port_82599 - Gets the source port | |
1529 | * @input: input stream to modify | |
1530 | * @src_port: the source port to load | |
1531 | * | |
1532 | * Even though the input is given in big-endian, the FDIRPORT registers | |
1533 | * expect the ports to be programmed in little-endian. Hence the need to swap | |
1534 | * endianness when retrieving the data. This can be confusing since the | |
1535 | * internal hash engine expects it to be big-endian. | |
1536 | **/ | |
7b25cdba DS |
1537 | static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, |
1538 | u16 *src_port) | |
ffff4772 PWJ |
1539 | { |
1540 | *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; | |
1541 | *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | /** | |
1547 | * ixgbe_atr_get_dst_port_82599 - Gets the destination port | |
1548 | * @input: input stream to modify | |
1549 | * @dst_port: the destination port to load | |
1550 | * | |
1551 | * Even though the input is given in big-endian, the FDIRPORT registers | |
1552 | * expect the ports to be programmed in little-endian. Hence the need to swap | |
1553 | * endianness when retrieving the data. This can be confusing since the | |
1554 | * internal hash engine expects it to be big-endian. | |
1555 | **/ | |
7b25cdba DS |
1556 | static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, |
1557 | u16 *dst_port) | |
ffff4772 PWJ |
1558 | { |
1559 | *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8; | |
1560 | *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1]; | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes | |
1567 | * @input: input stream to modify | |
1568 | * @flex_bytes: the flexible bytes to load | |
1569 | **/ | |
7b25cdba DS |
1570 | static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, |
1571 | u16 *flex_byte) | |
ffff4772 PWJ |
1572 | { |
1573 | *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET]; | |
1574 | *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8; | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
ffff4772 PWJ |
1579 | /** |
1580 | * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type | |
1581 | * @input: input stream to modify | |
1582 | * @l4type: the layer 4 type value to load | |
1583 | **/ | |
7b25cdba DS |
1584 | static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, |
1585 | u8 *l4type) | |
ffff4772 PWJ |
1586 | { |
1587 | *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET]; | |
1588 | ||
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | /** | |
1593 | * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter | |
1594 | * @hw: pointer to hardware structure | |
1595 | * @stream: input bitstream | |
1596 | * @queue: queue index to direct traffic to | |
1597 | **/ | |
1598 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
1599 | struct ixgbe_atr_input *input, | |
1600 | u8 queue) | |
1601 | { | |
1602 | u64 fdirhashcmd; | |
1603 | u64 fdircmd; | |
1604 | u32 fdirhash; | |
1605 | u16 bucket_hash, sig_hash; | |
1606 | u8 l4type; | |
1607 | ||
1608 | bucket_hash = ixgbe_atr_compute_hash_82599(input, | |
1609 | IXGBE_ATR_BUCKET_HASH_KEY); | |
1610 | ||
1611 | /* bucket_hash is only 15 bits */ | |
1612 | bucket_hash &= IXGBE_ATR_HASH_MASK; | |
1613 | ||
1614 | sig_hash = ixgbe_atr_compute_hash_82599(input, | |
1615 | IXGBE_ATR_SIGNATURE_HASH_KEY); | |
1616 | ||
1617 | /* Get the l4type in order to program FDIRCMD properly */ | |
1618 | /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */ | |
1619 | ixgbe_atr_get_l4type_82599(input, &l4type); | |
1620 | ||
1621 | /* | |
1622 | * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits | |
1623 | * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. | |
1624 | */ | |
1625 | fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; | |
1626 | ||
1627 | fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | | |
1628 | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); | |
1629 | ||
1630 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { | |
1631 | case IXGBE_ATR_L4TYPE_TCP: | |
1632 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; | |
1633 | break; | |
1634 | case IXGBE_ATR_L4TYPE_UDP: | |
1635 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; | |
1636 | break; | |
1637 | case IXGBE_ATR_L4TYPE_SCTP: | |
1638 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; | |
1639 | break; | |
1640 | default: | |
1641 | hw_dbg(hw, "Error on l4type input\n"); | |
1642 | return IXGBE_ERR_CONFIG; | |
1643 | } | |
1644 | ||
1645 | if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) | |
1646 | fdircmd |= IXGBE_FDIRCMD_IPV6; | |
1647 | ||
1648 | fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); | |
1649 | fdirhashcmd = ((fdircmd << 32) | fdirhash); | |
1650 | ||
1651 | IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
1656 | /** | |
1657 | * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter | |
1658 | * @hw: pointer to hardware structure | |
1659 | * @input: input bitstream | |
9a713e7c PW |
1660 | * @input_masks: bitwise masks for relevant fields |
1661 | * @soft_id: software index into the silicon hash tables for filter storage | |
ffff4772 PWJ |
1662 | * @queue: queue index to direct traffic to |
1663 | * | |
1664 | * Note that the caller to this function must lock before calling, since the | |
1665 | * hardware writes must be protected from one another. | |
1666 | **/ | |
1667 | s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, | |
9a713e7c PW |
1668 | struct ixgbe_atr_input *input, |
1669 | struct ixgbe_atr_input_masks *input_masks, | |
1670 | u16 soft_id, u8 queue) | |
ffff4772 PWJ |
1671 | { |
1672 | u32 fdircmd = 0; | |
1673 | u32 fdirhash; | |
9a713e7c | 1674 | u32 src_ipv4 = 0, dst_ipv4 = 0; |
ffff4772 PWJ |
1675 | u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; |
1676 | u16 src_port, dst_port, vlan_id, flex_bytes; | |
1677 | u16 bucket_hash; | |
1678 | u8 l4type; | |
9a713e7c | 1679 | u8 fdirm = 0; |
ffff4772 PWJ |
1680 | |
1681 | /* Get our input values */ | |
1682 | ixgbe_atr_get_l4type_82599(input, &l4type); | |
1683 | ||
1684 | /* | |
1685 | * Check l4type formatting, and bail out before we touch the hardware | |
1686 | * if there's a configuration issue | |
1687 | */ | |
1688 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { | |
1689 | case IXGBE_ATR_L4TYPE_TCP: | |
1690 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; | |
1691 | break; | |
1692 | case IXGBE_ATR_L4TYPE_UDP: | |
1693 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; | |
1694 | break; | |
1695 | case IXGBE_ATR_L4TYPE_SCTP: | |
1696 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; | |
1697 | break; | |
1698 | default: | |
1699 | hw_dbg(hw, "Error on l4type input\n"); | |
1700 | return IXGBE_ERR_CONFIG; | |
1701 | } | |
1702 | ||
1703 | bucket_hash = ixgbe_atr_compute_hash_82599(input, | |
1704 | IXGBE_ATR_BUCKET_HASH_KEY); | |
1705 | ||
1706 | /* bucket_hash is only 15 bits */ | |
1707 | bucket_hash &= IXGBE_ATR_HASH_MASK; | |
1708 | ||
1709 | ixgbe_atr_get_vlan_id_82599(input, &vlan_id); | |
1710 | ixgbe_atr_get_src_port_82599(input, &src_port); | |
1711 | ixgbe_atr_get_dst_port_82599(input, &dst_port); | |
1712 | ixgbe_atr_get_flex_byte_82599(input, &flex_bytes); | |
1713 | ||
1714 | fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; | |
1715 | ||
1716 | /* Now figure out if we're IPv4 or IPv6 */ | |
1717 | if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) { | |
1718 | /* IPv6 */ | |
1719 | ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2, | |
1720 | &src_ipv6_3, &src_ipv6_4); | |
1721 | ||
1722 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1); | |
1723 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2); | |
1724 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3); | |
1725 | /* The last 4 bytes is the same register as IPv4 */ | |
1726 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4); | |
1727 | ||
1728 | fdircmd |= IXGBE_FDIRCMD_IPV6; | |
1729 | fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH; | |
1730 | } else { | |
1731 | /* IPv4 */ | |
1732 | ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4); | |
1733 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4); | |
ffff4772 PWJ |
1734 | } |
1735 | ||
1736 | ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4); | |
1737 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4); | |
1738 | ||
1739 | IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id | | |
1740 | (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT))); | |
1741 | IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port | | |
9a713e7c PW |
1742 | (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT))); |
1743 | ||
1744 | /* | |
be2902da BH |
1745 | * Program the relevant mask registers. L4type cannot be |
1746 | * masked out in this implementation. | |
9a713e7c PW |
1747 | * |
1748 | * This also assumes IPv4 only. IPv6 masking isn't supported at this | |
1749 | * point in time. | |
1750 | */ | |
be2902da BH |
1751 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask); |
1752 | IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask); | |
9a713e7c PW |
1753 | |
1754 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { | |
1755 | case IXGBE_ATR_L4TYPE_TCP: | |
be2902da BH |
1756 | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask); |
1757 | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, | |
1758 | (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) | | |
1759 | (input_masks->dst_port_mask << 16))); | |
9a713e7c PW |
1760 | break; |
1761 | case IXGBE_ATR_L4TYPE_UDP: | |
be2902da BH |
1762 | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask); |
1763 | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, | |
1764 | (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) | | |
1765 | (input_masks->src_port_mask << 16))); | |
9a713e7c PW |
1766 | break; |
1767 | default: | |
1768 | /* this already would have failed above */ | |
1769 | break; | |
1770 | } | |
1771 | ||
1772 | /* Program the last mask register, FDIRM */ | |
be2902da | 1773 | if (input_masks->vlan_id_mask) |
9a713e7c PW |
1774 | /* Mask both VLAN and VLANP - bits 0 and 1 */ |
1775 | fdirm |= 0x3; | |
1776 | ||
be2902da | 1777 | if (input_masks->data_mask) |
9a713e7c PW |
1778 | /* Flex bytes need masking, so mask the whole thing - bit 4 */ |
1779 | fdirm |= 0x10; | |
1780 | ||
1781 | /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ | |
1782 | fdirm |= 0x24; | |
1783 | ||
1784 | IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); | |
ffff4772 PWJ |
1785 | |
1786 | fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; | |
1787 | fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; | |
1788 | fdircmd |= IXGBE_FDIRCMD_LAST; | |
1789 | fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; | |
1790 | fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; | |
1791 | ||
1792 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); | |
1793 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); | |
1794 | ||
1795 | return 0; | |
1796 | } | |
11afc1b1 PW |
1797 | /** |
1798 | * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register | |
1799 | * @hw: pointer to hardware structure | |
1800 | * @reg: analog register to read | |
1801 | * @val: read value | |
1802 | * | |
1803 | * Performs read operation to Omer analog register specified. | |
1804 | **/ | |
7b25cdba | 1805 | static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) |
11afc1b1 PW |
1806 | { |
1807 | u32 core_ctl; | |
1808 | ||
1809 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | | |
1810 | (reg << 8)); | |
1811 | IXGBE_WRITE_FLUSH(hw); | |
1812 | udelay(10); | |
1813 | core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); | |
1814 | *val = (u8)core_ctl; | |
1815 | ||
1816 | return 0; | |
1817 | } | |
1818 | ||
1819 | /** | |
1820 | * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register | |
1821 | * @hw: pointer to hardware structure | |
1822 | * @reg: atlas register to write | |
1823 | * @val: value to write | |
1824 | * | |
1825 | * Performs write operation to Omer analog register specified. | |
1826 | **/ | |
7b25cdba | 1827 | static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) |
11afc1b1 PW |
1828 | { |
1829 | u32 core_ctl; | |
1830 | ||
1831 | core_ctl = (reg << 8) | val; | |
1832 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); | |
1833 | IXGBE_WRITE_FLUSH(hw); | |
1834 | udelay(10); | |
1835 | ||
1836 | return 0; | |
1837 | } | |
1838 | ||
1839 | /** | |
1840 | * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx | |
1841 | * @hw: pointer to hardware structure | |
1842 | * | |
1843 | * Starts the hardware using the generic start_hw function. | |
1844 | * Then performs device-specific: | |
1845 | * Clears the rate limiter registers. | |
1846 | **/ | |
7b25cdba | 1847 | static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
1848 | { |
1849 | u32 q_num; | |
794caeb2 | 1850 | s32 ret_val; |
11afc1b1 | 1851 | |
794caeb2 | 1852 | ret_val = ixgbe_start_hw_generic(hw); |
11afc1b1 PW |
1853 | |
1854 | /* Clear the rate limiters */ | |
1855 | for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { | |
1856 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); | |
1857 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); | |
1858 | } | |
1859 | IXGBE_WRITE_FLUSH(hw); | |
1860 | ||
50ac58ba PWJ |
1861 | /* We need to run link autotry after the driver loads */ |
1862 | hw->mac.autotry_restart = true; | |
1863 | ||
794caeb2 PWJ |
1864 | if (ret_val == 0) |
1865 | ret_val = ixgbe_verify_fw_version_82599(hw); | |
1866 | ||
1867 | return ret_val; | |
11afc1b1 PW |
1868 | } |
1869 | ||
1870 | /** | |
1871 | * ixgbe_identify_phy_82599 - Get physical layer module | |
1872 | * @hw: pointer to hardware structure | |
1873 | * | |
1874 | * Determines the physical layer module found on the current adapter. | |
1875 | **/ | |
7b25cdba | 1876 | static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
1877 | { |
1878 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; | |
1879 | status = ixgbe_identify_phy_generic(hw); | |
1880 | if (status != 0) | |
1881 | status = ixgbe_identify_sfp_module_generic(hw); | |
1882 | return status; | |
1883 | } | |
1884 | ||
1885 | /** | |
1886 | * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type | |
1887 | * @hw: pointer to hardware structure | |
1888 | * | |
1889 | * Determines physical layer capabilities of the current configuration. | |
1890 | **/ | |
7b25cdba | 1891 | static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) |
11afc1b1 PW |
1892 | { |
1893 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
04193058 PWJ |
1894 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1895 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
1896 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; | |
1897 | u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1898 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1899 | u16 ext_ability = 0; | |
1339b9e9 | 1900 | u8 comp_codes_10g = 0; |
cb836a97 | 1901 | u8 comp_codes_1g = 0; |
11afc1b1 | 1902 | |
04193058 PWJ |
1903 | hw->phy.ops.identify(hw); |
1904 | ||
1905 | if (hw->phy.type == ixgbe_phy_tn || | |
fe15e8e1 | 1906 | hw->phy.type == ixgbe_phy_aq || |
04193058 | 1907 | hw->phy.type == ixgbe_phy_cu_unknown) { |
6b73e10d BH |
1908 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
1909 | &ext_ability); | |
1910 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
04193058 | 1911 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1912 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1913 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1914 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1915 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1916 | goto out; | |
1917 | } | |
1918 | ||
1919 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
1920 | case IXGBE_AUTOC_LMS_1G_AN: | |
1921 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1922 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { | |
1923 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | | |
1924 | IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
1925 | goto out; | |
1926 | } else | |
1927 | /* SFI mode so read SFP module */ | |
1928 | goto sfp_check; | |
11afc1b1 | 1929 | break; |
04193058 PWJ |
1930 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1931 | if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) | |
1932 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1933 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) | |
1934 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1fcf03e6 PWJ |
1935 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) |
1936 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; | |
04193058 PWJ |
1937 | goto out; |
1938 | break; | |
1939 | case IXGBE_AUTOC_LMS_10G_SERIAL: | |
1940 | if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { | |
1941 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; | |
1942 | goto out; | |
1943 | } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) | |
1944 | goto sfp_check; | |
1945 | break; | |
1946 | case IXGBE_AUTOC_LMS_KX4_KX_KR: | |
1947 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: | |
1948 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1949 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1950 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1951 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1952 | if (autoc & IXGBE_AUTOC_KR_SUPP) | |
1953 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; | |
1954 | goto out; | |
1955 | break; | |
1956 | default: | |
1957 | goto out; | |
1958 | break; | |
1959 | } | |
11afc1b1 | 1960 | |
04193058 PWJ |
1961 | sfp_check: |
1962 | /* SFP check must be done last since DA modules are sometimes used to | |
1963 | * test KR mode - we need to id KR mode correctly before SFP module. | |
1964 | * Call identify_sfp because the pluggable module may have changed */ | |
1965 | hw->phy.ops.identify_sfp(hw); | |
1966 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) | |
1967 | goto out; | |
1968 | ||
1969 | switch (hw->phy.type) { | |
ea0a04df DS |
1970 | case ixgbe_phy_sfp_passive_tyco: |
1971 | case ixgbe_phy_sfp_passive_unknown: | |
04193058 PWJ |
1972 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; |
1973 | break; | |
ea0a04df DS |
1974 | case ixgbe_phy_sfp_ftl_active: |
1975 | case ixgbe_phy_sfp_active_unknown: | |
1976 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; | |
1977 | break; | |
04193058 PWJ |
1978 | case ixgbe_phy_sfp_avago: |
1979 | case ixgbe_phy_sfp_ftl: | |
1980 | case ixgbe_phy_sfp_intel: | |
1981 | case ixgbe_phy_sfp_unknown: | |
cb836a97 DS |
1982 | hw->phy.ops.read_i2c_eeprom(hw, |
1983 | IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); | |
04193058 PWJ |
1984 | hw->phy.ops.read_i2c_eeprom(hw, |
1985 | IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); | |
1986 | if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) | |
11afc1b1 | 1987 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; |
04193058 | 1988 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
11afc1b1 | 1989 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; |
cb836a97 DS |
1990 | else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) |
1991 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; | |
11afc1b1 PW |
1992 | break; |
1993 | default: | |
11afc1b1 PW |
1994 | break; |
1995 | } | |
1996 | ||
04193058 | 1997 | out: |
11afc1b1 PW |
1998 | return physical_layer; |
1999 | } | |
2000 | ||
2001 | /** | |
2002 | * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 | |
2003 | * @hw: pointer to hardware structure | |
2004 | * @regval: register value to write to RXCTRL | |
2005 | * | |
2006 | * Enables the Rx DMA unit for 82599 | |
2007 | **/ | |
7b25cdba | 2008 | static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) |
11afc1b1 PW |
2009 | { |
2010 | #define IXGBE_MAX_SECRX_POLL 30 | |
2011 | int i; | |
2012 | int secrxreg; | |
2013 | ||
2014 | /* | |
2015 | * Workaround for 82599 silicon errata when enabling the Rx datapath. | |
2016 | * If traffic is incoming before we enable the Rx unit, it could hang | |
2017 | * the Rx DMA unit. Therefore, make sure the security engine is | |
2018 | * completely disabled prior to enabling the Rx unit. | |
2019 | */ | |
2020 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); | |
2021 | secrxreg |= IXGBE_SECRXCTRL_RX_DIS; | |
2022 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); | |
2023 | for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { | |
2024 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); | |
2025 | if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) | |
2026 | break; | |
2027 | else | |
2028 | udelay(10); | |
2029 | } | |
2030 | ||
2031 | /* For informational purposes only */ | |
2032 | if (i >= IXGBE_MAX_SECRX_POLL) | |
2033 | hw_dbg(hw, "Rx unit being enabled before security " | |
2034 | "path fully disabled. Continuing with init.\n"); | |
2035 | ||
2036 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); | |
2037 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); | |
2038 | secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; | |
2039 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); | |
2040 | IXGBE_WRITE_FLUSH(hw); | |
2041 | ||
2042 | return 0; | |
2043 | } | |
2044 | ||
04193058 PWJ |
2045 | /** |
2046 | * ixgbe_get_device_caps_82599 - Get additional device capabilities | |
2047 | * @hw: pointer to hardware structure | |
2048 | * @device_caps: the EEPROM word with the extra device capabilities | |
2049 | * | |
2050 | * This function will read the EEPROM location for the device capabilities, | |
2051 | * and return the word through device_caps. | |
2052 | **/ | |
7b25cdba | 2053 | static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) |
04193058 PWJ |
2054 | { |
2055 | hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); | |
2056 | ||
2057 | return 0; | |
2058 | } | |
2059 | ||
794caeb2 PWJ |
2060 | /** |
2061 | * ixgbe_verify_fw_version_82599 - verify fw version for 82599 | |
2062 | * @hw: pointer to hardware structure | |
2063 | * | |
2064 | * Verifies that installed the firmware version is 0.6 or higher | |
2065 | * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. | |
2066 | * | |
2067 | * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or | |
2068 | * if the FW version is not supported. | |
2069 | **/ | |
2070 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) | |
2071 | { | |
2072 | s32 status = IXGBE_ERR_EEPROM_VERSION; | |
2073 | u16 fw_offset, fw_ptp_cfg_offset; | |
2074 | u16 fw_version = 0; | |
2075 | ||
2076 | /* firmware check is only necessary for SFI devices */ | |
2077 | if (hw->phy.media_type != ixgbe_media_type_fiber) { | |
2078 | status = 0; | |
2079 | goto fw_version_out; | |
2080 | } | |
2081 | ||
2082 | /* get the offset to the Firmware Module block */ | |
2083 | hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); | |
2084 | ||
2085 | if ((fw_offset == 0) || (fw_offset == 0xFFFF)) | |
2086 | goto fw_version_out; | |
2087 | ||
2088 | /* get the offset to the Pass Through Patch Configuration block */ | |
2089 | hw->eeprom.ops.read(hw, (fw_offset + | |
2090 | IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), | |
2091 | &fw_ptp_cfg_offset); | |
2092 | ||
2093 | if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) | |
2094 | goto fw_version_out; | |
2095 | ||
2096 | /* get the firmware version */ | |
2097 | hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + | |
2098 | IXGBE_FW_PATCH_VERSION_4), | |
2099 | &fw_version); | |
2100 | ||
2101 | if (fw_version > 0x5) | |
2102 | status = 0; | |
2103 | ||
2104 | fw_version_out: | |
2105 | return status; | |
2106 | } | |
2107 | ||
11afc1b1 PW |
2108 | static struct ixgbe_mac_operations mac_ops_82599 = { |
2109 | .init_hw = &ixgbe_init_hw_generic, | |
2110 | .reset_hw = &ixgbe_reset_hw_82599, | |
2111 | .start_hw = &ixgbe_start_hw_82599, | |
2112 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, | |
2113 | .get_media_type = &ixgbe_get_media_type_82599, | |
2114 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, | |
2115 | .enable_rx_dma = &ixgbe_enable_rx_dma_82599, | |
2116 | .get_mac_addr = &ixgbe_get_mac_addr_generic, | |
21ce849b | 2117 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, |
04193058 | 2118 | .get_device_caps = &ixgbe_get_device_caps_82599, |
a391f1d5 | 2119 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, |
11afc1b1 PW |
2120 | .stop_adapter = &ixgbe_stop_adapter_generic, |
2121 | .get_bus_info = &ixgbe_get_bus_info_generic, | |
2122 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
2123 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, | |
2124 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, | |
2125 | .setup_link = &ixgbe_setup_mac_link_82599, | |
21ce849b | 2126 | .check_link = &ixgbe_check_mac_link_generic, |
11afc1b1 PW |
2127 | .get_link_capabilities = &ixgbe_get_link_capabilities_82599, |
2128 | .led_on = &ixgbe_led_on_generic, | |
2129 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
2130 | .blink_led_start = &ixgbe_blink_led_start_generic, |
2131 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
11afc1b1 PW |
2132 | .set_rar = &ixgbe_set_rar_generic, |
2133 | .clear_rar = &ixgbe_clear_rar_generic, | |
21ce849b MC |
2134 | .set_vmdq = &ixgbe_set_vmdq_generic, |
2135 | .clear_vmdq = &ixgbe_clear_vmdq_generic, | |
11afc1b1 PW |
2136 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, |
2137 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, | |
2138 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, | |
2139 | .enable_mc = &ixgbe_enable_mc_generic, | |
2140 | .disable_mc = &ixgbe_disable_mc_generic, | |
21ce849b MC |
2141 | .clear_vfta = &ixgbe_clear_vfta_generic, |
2142 | .set_vfta = &ixgbe_set_vfta_generic, | |
2143 | .fc_enable = &ixgbe_fc_enable_generic, | |
2144 | .init_uta_tables = &ixgbe_init_uta_tables_generic, | |
11afc1b1 PW |
2145 | .setup_sfp = &ixgbe_setup_sfp_modules_82599, |
2146 | }; | |
2147 | ||
2148 | static struct ixgbe_eeprom_operations eeprom_ops_82599 = { | |
2149 | .init_params = &ixgbe_init_eeprom_params_generic, | |
21ce849b | 2150 | .read = &ixgbe_read_eerd_generic, |
11afc1b1 | 2151 | .write = &ixgbe_write_eeprom_generic, |
a391f1d5 | 2152 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
11afc1b1 PW |
2153 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
2154 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
2155 | }; | |
2156 | ||
2157 | static struct ixgbe_phy_operations phy_ops_82599 = { | |
2158 | .identify = &ixgbe_identify_phy_82599, | |
2159 | .identify_sfp = &ixgbe_identify_sfp_module_generic, | |
21ce849b | 2160 | .init = &ixgbe_init_phy_ops_82599, |
11afc1b1 PW |
2161 | .reset = &ixgbe_reset_phy_generic, |
2162 | .read_reg = &ixgbe_read_phy_reg_generic, | |
2163 | .write_reg = &ixgbe_write_phy_reg_generic, | |
2164 | .setup_link = &ixgbe_setup_phy_link_generic, | |
2165 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
2166 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, | |
2167 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, | |
2168 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, | |
2169 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, | |
119fc60a | 2170 | .check_overtemp = &ixgbe_tn_check_overtemp, |
11afc1b1 PW |
2171 | }; |
2172 | ||
2173 | struct ixgbe_info ixgbe_82599_info = { | |
2174 | .mac = ixgbe_mac_82599EB, | |
2175 | .get_invariants = &ixgbe_get_invariants_82599, | |
2176 | .mac_ops = &mac_ops_82599, | |
2177 | .eeprom_ops = &eeprom_ops_82599, | |
2178 | .phy_ops = &phy_ops_82599, | |
a391f1d5 | 2179 | .mbx_ops = &mbx_ops_generic, |
11afc1b1 | 2180 | }; |