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ixgbe: fix 82598 SFP initialization after driver load.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ixgbe / ixgbe_82598.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
9c8eb720 32#include "ixgbe.h"
9a799d71
AK		 33#include "ixgbe_phy.h"
34
35#define IXGBE_82598_MAX_TX_QUEUES 32
36#define IXGBE_82598_MAX_RX_QUEUES 64
37#define IXGBE_82598_RAR_ENTRIES 16
2c5645cf
CL		 38#define IXGBE_82598_MC_TBL_SIZE 128
39#define IXGBE_82598_VFT_TBL_SIZE 128
9a799d71 40
c44ade9e
JB		 41static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
9a799d71 44static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
c44ade9e
JB		 45static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
c4900be0
DS		 49static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data);
9a799d71 51
eb7f139c
PWJ		 52/**
53 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
54 * @hw: pointer to hardware structure
55 *
56 * Read PCIe configuration space, and get the MSI-X vector count from
57 * the capabilities table.
58 **/
1aef47c4 59static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
eb7f139c
PWJ		 60{
61 struct ixgbe_adapter *adapter = hw->back;
62 u16 msix_count;
63 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
64 &msix_count);
65 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
66
67 /* MSI-X count is zero-based in HW, so increment to give proper value */
68 msix_count++;
69
70 return msix_count;
71}
72
c44ade9e
JB		 73/**
74 */
9a799d71 75static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
04f165ef
PW		 76{
77 struct ixgbe_mac_info *mac = &hw->mac;
78
79 /* Call PHY identify routine to get the phy type */
80 ixgbe_identify_phy_generic(hw);
81
82 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
83 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
84 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
85 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
86 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
87 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
88
89 return 0;
90}
91
92/**
93 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
94 * @hw: pointer to hardware structure
95 *
96 * Initialize any function pointers that were not able to be
97 * set during get_invariants because the PHY/SFP type was
98 * not known. Perform the SFP init if necessary.
99 *
100 **/
101s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
9a799d71 102{
c44ade9e
JB		 103 struct ixgbe_mac_info *mac = &hw->mac;
104 struct ixgbe_phy_info *phy = &hw->phy;
c4900be0
DS		 105 s32 ret_val = 0;
106 u16 list_offset, data_offset;
c44ade9e 107
04f165ef
PW		 108 /* Identify the PHY */
109 phy->ops.identify(hw);
03cfa205 110
04f165ef
PW		 111 /* Overwrite the link function pointers if copper PHY */
112 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
113 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
114 mac->ops.setup_link_speed =
115 &ixgbe_setup_copper_link_speed_82598;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_82598;
118 }
c44ade9e 119
04f165ef 120 switch (hw->phy.type) {
0befdb3e
JB		 121 case ixgbe_phy_tn:
122 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
123 phy->ops.get_firmware_version =
124 &ixgbe_get_phy_firmware_version_tnx;
125 break;
c4900be0
DS		 126 case ixgbe_phy_nl:
127 phy->ops.reset = &ixgbe_reset_phy_nl;
128
129 /* Call SFP+ identify routine to get the SFP+ module type */
130 ret_val = phy->ops.identify_sfp(hw);
131 if (ret_val != 0)
132 goto out;
133 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
134 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
135 goto out;
136 }
137
138 /* Check to see if SFP+ module is supported */
139 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
04f165ef
PW		 140 &list_offset,
141 &data_offset);
c4900be0
DS		 142 if (ret_val != 0) {
143 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
144 goto out;
145 }
146 break;
c44ade9e
JB		 147 default:
148 break;
149 }
150
c4900be0
DS		 151out:
152 return ret_val;
9a799d71
AK		 153}
154
155/**
c44ade9e 156 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
9a799d71
AK		 157 * @hw: pointer to hardware structure
158 * @speed: pointer to link speed
159 * @autoneg: boolean auto-negotiation value
160 *
c44ade9e 161 * Determines the link capabilities by reading the AUTOC register.
9a799d71 162 **/
c44ade9e 163static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
b4617240
PW		 164 ixgbe_link_speed *speed,
165 bool *autoneg)
9a799d71
AK		 166{
167 s32 status = 0;
1eb99d5a 168 u32 autoc = 0;
9a799d71 169
3201d313
PWJ		 170 /*
171 * Determine link capabilities based on the stored value of AUTOC,
1eb99d5a
PW		 172 * which represents EEPROM defaults. If AUTOC value has not been
173 * stored, use the current register value.
3201d313 174 */
1eb99d5a
PW		 175 if (hw->mac.orig_link_settings_stored)
176 autoc = hw->mac.orig_autoc;
177 else
178 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
179
180 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
9a799d71
AK		 181 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
182 *speed = IXGBE_LINK_SPEED_1GB_FULL;
183 *autoneg = false;
184 break;
185
186 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
187 *speed = IXGBE_LINK_SPEED_10GB_FULL;
188 *autoneg = false;
189 break;
190
191 case IXGBE_AUTOC_LMS_1G_AN:
192 *speed = IXGBE_LINK_SPEED_1GB_FULL;
193 *autoneg = true;
194 break;
195
196 case IXGBE_AUTOC_LMS_KX4_AN:
197 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
198 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 199 if (autoc & IXGBE_AUTOC_KX4_SUPP)
9a799d71 200 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 201 if (autoc & IXGBE_AUTOC_KX_SUPP)
9a799d71
AK		 202 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
203 *autoneg = true;
204 break;
205
206 default:
207 status = IXGBE_ERR_LINK_SETUP;
208 break;
209 }
210
211 return status;
212}
213
214/**
c44ade9e 215 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
9a799d71
AK		 216 * @hw: pointer to hardware structure
217 * @speed: pointer to link speed
218 * @autoneg: boolean auto-negotiation value
219 *
c44ade9e 220 * Determines the link capabilities by reading the AUTOC register.
9a799d71 221 **/
e855aac8
HE		 222static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
223 ixgbe_link_speed *speed,
224 bool *autoneg)
9a799d71
AK		 225{
226 s32 status = IXGBE_ERR_LINK_SETUP;
227 u16 speed_ability;
228
229 *speed = 0;
230 *autoneg = true;
231
6b73e10d 232 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
b4617240 233 &speed_ability);
9a799d71
AK		 234
235 if (status == 0) {
6b73e10d 236 if (speed_ability & MDIO_SPEED_10G)
9a799d71 237 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 238 if (speed_ability & MDIO_PMA_SPEED_1000)
9a799d71
AK		 239 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
240 }
241
242 return status;
243}
244
245/**
246 * ixgbe_get_media_type_82598 - Determines media type
247 * @hw: pointer to hardware structure
248 *
249 * Returns the media type (fiber, copper, backplane)
250 **/
251static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
252{
253 enum ixgbe_media_type media_type;
254
255 /* Media type for I82598 is based on device ID */
256 switch (hw->device_id) {
1e336d0f 257 case IXGBE_DEV_ID_82598:
2f21bdd3 258 case IXGBE_DEV_ID_82598_BX:
1e336d0f
DS		 259 media_type = ixgbe_media_type_backplane;
260 break;
9a799d71
AK		 261 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
262 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
263 case IXGBE_DEV_ID_82598EB_CX4:
8d792cd9 264 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
c4900be0
DS		 265 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
266 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
b95f5fcb 267 case IXGBE_DEV_ID_82598EB_XF_LR:
c4900be0 268 case IXGBE_DEV_ID_82598EB_SFP_LOM:
9a799d71
AK		 269 media_type = ixgbe_media_type_fiber;
270 break;
0befdb3e
JB		 271 case IXGBE_DEV_ID_82598AT:
272 media_type = ixgbe_media_type_copper;
273 break;
9a799d71
AK		 274 default:
275 media_type = ixgbe_media_type_unknown;
276 break;
277 }
278
279 return media_type;
280}
281
c44ade9e 282/**
0ecc061d 283 * ixgbe_fc_enable_82598 - Enable flow control
c44ade9e
JB		 284 * @hw: pointer to hardware structure
285 * @packetbuf_num: packet buffer number (0-7)
286 *
0ecc061d 287 * Enable flow control according to the current settings.
c44ade9e 288 **/
0ecc061d 289static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
c44ade9e 290{
0ecc061d
PWJ		 291 s32 ret_val = 0;
292 u32 fctrl_reg;
c44ade9e 293 u32 rmcs_reg;
0ecc061d 294 u32 reg;
c44ade9e 295
0ecc061d
PWJ		 296 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
297 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
c44ade9e
JB		 298
299 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
300 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
301
302 /*
0ecc061d 303 * The possible values of fc.current_mode are:
c44ade9e 304 * 0: Flow control is completely disabled
0ecc061d
PWJ		 305 * 1: Rx flow control is enabled (we can receive pause frames,
306 * but not send pause frames).
307 * 2: Tx flow control is enabled (we can send pause frames but
308 * we do not support receiving pause frames).
c44ade9e
JB		 309 * 3: Both Rx and Tx flow control (symmetric) are enabled.
310 * other: Invalid.
311 */
0ecc061d 312 switch (hw->fc.current_mode) {
c44ade9e 313 case ixgbe_fc_none:
0ecc061d 314 /* Flow control completely disabled by software override. */
c44ade9e
JB		 315 break;
316 case ixgbe_fc_rx_pause:
317 /*
0ecc061d
PWJ		 318 * Rx Flow control is enabled and Tx Flow control is
319 * disabled by software override. Since there really
320 * isn't a way to advertise that we are capable of RX
321 * Pause ONLY, we will advertise that we support both
322 * symmetric and asymmetric Rx PAUSE. Later, we will
323 * disable the adapter's ability to send PAUSE frames.
c44ade9e 324 */
0ecc061d 325 fctrl_reg |= IXGBE_FCTRL_RFCE;
c44ade9e
JB		 326 break;
327 case ixgbe_fc_tx_pause:
328 /*
0ecc061d
PWJ		 329 * Tx Flow control is enabled, and Rx Flow control is
330 * disabled by software override.
c44ade9e
JB		 331 */
332 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
333 break;
334 case ixgbe_fc_full:
0ecc061d
PWJ		 335 /* Flow control (both Rx and Tx) is enabled by SW override. */
336 fctrl_reg |= IXGBE_FCTRL_RFCE;
c44ade9e
JB		 337 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
338 break;
339 default:
c44ade9e 340 hw_dbg(hw, "Flow control param set incorrectly\n");
0ecc061d
PWJ		 341 ret_val = -IXGBE_ERR_CONFIG;
342 goto out;
c44ade9e
JB		 343 break;
344 }
345
346 /* Enable 802.3x based flow control settings. */
2132d381 347 fctrl_reg |= IXGBE_FCTRL_DPF;
0ecc061d 348 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
c44ade9e
JB		 349 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
350
0ecc061d
PWJ		 351 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
352 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
c44ade9e
JB		 353 if (hw->fc.send_xon) {
354 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
355 (hw->fc.low_water | IXGBE_FCRTL_XONE));
356 } else {
357 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
358 hw->fc.low_water);
359 }
0ecc061d 360
c44ade9e 361 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
0ecc061d 362 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
c44ade9e
JB		 363 }
364
0ecc061d 365 /* Configure pause time (2 TCs per register) */
264857b8 366 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
0ecc061d
PWJ		 367 if ((packetbuf_num & 1) == 0)
368 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
369 else
370 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
371 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
372
c44ade9e
JB		 373 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
374
0ecc061d
PWJ		 375out:
376 return ret_val;
377}
378
379/**
380 * ixgbe_setup_fc_82598 - Configure flow control settings
381 * @hw: pointer to hardware structure
382 * @packetbuf_num: packet buffer number (0-7)
383 *
384 * Configures the flow control settings based on SW configuration. This
385 * function is used for 802.3x flow control configuration only.
386 **/
387static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
388{
389 s32 ret_val = 0;
390 ixgbe_link_speed speed;
391 bool link_up;
392
393 /* Validate the packetbuf configuration */
394 if (packetbuf_num < 0 || packetbuf_num > 7) {
395 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
396 " 0-7\n", packetbuf_num);
397 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
398 goto out;
399 }
400
401 /*
402 * Validate the water mark configuration. Zero water marks are invalid
403 * because it causes the controller to just blast out fc packets.
404 */
405 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
d3e9c56c
PW		 406 if (hw->fc.requested_mode != ixgbe_fc_none) {
407 hw_dbg(hw, "Invalid water mark configuration\n");
408 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
409 goto out;
410 }
0ecc061d
PWJ		 411 }
412
413 /*
414 * Validate the requested mode. Strict IEEE mode does not allow
415 * ixgbe_fc_rx_pause because it will cause testing anomalies.
416 */
417 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
418 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
419 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
420 goto out;
421 }
422
423 /*
424 * 10gig parts do not have a word in the EEPROM to determine the
425 * default flow control setting, so we explicitly set it to full.
426 */
427 if (hw->fc.requested_mode == ixgbe_fc_default)
428 hw->fc.requested_mode = ixgbe_fc_full;
429
430 /*
431 * Save off the requested flow control mode for use later. Depending
432 * on the link partner's capabilities, we may or may not use this mode.
433 */
434
435 hw->fc.current_mode = hw->fc.requested_mode;
436
437 /* Decide whether to use autoneg or not. */
438 hw->mac.ops.check_link(hw, &speed, &link_up, false);
71fd570b
DS		 439 if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
440 (speed == IXGBE_LINK_SPEED_1GB_FULL))
0ecc061d
PWJ		 441 ret_val = ixgbe_fc_autoneg(hw);
442
443 if (ret_val)
444 goto out;
445
446 ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
447
448out:
449 return ret_val;
c44ade9e
JB		 450}
451
9a799d71
AK		 452/**
453 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
454 * @hw: pointer to hardware structure
455 *
456 * Configures link settings based on values in the ixgbe_hw struct.
457 * Restarts the link. Performs autonegotiation if needed.
458 **/
459static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
460{
461 u32 autoc_reg;
462 u32 links_reg;
463 u32 i;
464 s32 status = 0;
465
9a799d71 466 /* Restart link */
3201d313 467 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
9a799d71
AK		 468 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
469 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
470
471 /* Only poll for autoneg to complete if specified to do so */
472 if (hw->phy.autoneg_wait_to_complete) {
3201d313
PWJ		 473 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
474 IXGBE_AUTOC_LMS_KX4_AN ||
475 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
476 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
9a799d71
AK		 477 links_reg = 0; /* Just in case Autoneg time = 0 */
478 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
479 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
480 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
481 break;
482 msleep(100);
483 }
484 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
485 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
c44ade9e 486 hw_dbg(hw, "Autonegotiation did not complete.\n");
9a799d71
AK		 487 }
488 }
489 }
490
491 /*
492 * We want to save off the original Flow Control configuration just in
493 * case we get disconnected and then reconnected into a different hub
494 * or switch with different Flow Control capabilities.
495 */
c44ade9e 496 ixgbe_setup_fc_82598(hw, 0);
9a799d71
AK		 497
498 /* Add delay to filter out noises during initial link setup */
499 msleep(50);
500
501 return status;
502}
503
504/**
505 * ixgbe_check_mac_link_82598 - Get link/speed status
506 * @hw: pointer to hardware structure
507 * @speed: pointer to link speed
508 * @link_up: true is link is up, false otherwise
cf8280ee 509 * @link_up_wait_to_complete: bool used to wait for link up or not
9a799d71
AK		 510 *
511 * Reads the links register to determine if link is up and the current speed
512 **/
b4617240
PW		 513static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
514 ixgbe_link_speed *speed, bool *link_up,
515 bool link_up_wait_to_complete)
9a799d71
AK		 516{
517 u32 links_reg;
cf8280ee 518 u32 i;
c4900be0
DS		 519 u16 link_reg, adapt_comp_reg;
520
521 /*
522 * SERDES PHY requires us to read link status from register 0xC79F.
523 * Bit 0 set indicates link is up/ready; clear indicates link down.
524 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
525 * clear indicates active; set indicates inactive.
526 */
527 if (hw->phy.type == ixgbe_phy_nl) {
6b73e10d
BH		 528 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
529 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
530 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
c4900be0
DS		 531 &adapt_comp_reg);
532 if (link_up_wait_to_complete) {
533 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
534 if ((link_reg & 1) &&
535 ((adapt_comp_reg & 1) == 0)) {
536 *link_up = true;
537 break;
538 } else {
539 *link_up = false;
540 }
541 msleep(100);
542 hw->phy.ops.read_reg(hw, 0xC79F,
6b73e10d 543 MDIO_MMD_PMAPMD,
c4900be0
DS		 544 &link_reg);
545 hw->phy.ops.read_reg(hw, 0xC00C,
6b73e10d 546 MDIO_MMD_PMAPMD,
c4900be0
DS		 547 &adapt_comp_reg);
548 }
549 } else {
550 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
551 *link_up = true;
552 else
553 *link_up = false;
554 }
555
556 if (*link_up == false)
557 goto out;
558 }
9a799d71
AK		 559
560 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
cf8280ee
JB		 561 if (link_up_wait_to_complete) {
562 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
563 if (links_reg & IXGBE_LINKS_UP) {
564 *link_up = true;
565 break;
566 } else {
567 *link_up = false;
568 }
569 msleep(100);
570 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
571 }
572 } else {
573 if (links_reg & IXGBE_LINKS_UP)
574 *link_up = true;
575 else
576 *link_up = false;
577 }
9a799d71
AK		 578
579 if (links_reg & IXGBE_LINKS_SPEED)
580 *speed = IXGBE_LINK_SPEED_10GB_FULL;
581 else
582 *speed = IXGBE_LINK_SPEED_1GB_FULL;
583
c4900be0 584out:
9a799d71
AK		 585 return 0;
586}
587
c44ade9e 588
9a799d71
AK		 589/**
590 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
591 * @hw: pointer to hardware structure
592 * @speed: new link speed
593 * @autoneg: true if auto-negotiation enabled
594 * @autoneg_wait_to_complete: true if waiting is needed to complete
595 *
596 * Set the link speed in the AUTOC register and restarts link.
597 **/
598static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
3201d313
PWJ		 599 ixgbe_link_speed speed, bool autoneg,
600 bool autoneg_wait_to_complete)
9a799d71 601{
3201d313
PWJ		 602 s32 status = 0;
603 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
604 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
605 u32 autoc = curr_autoc;
606 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
9a799d71 607
3201d313
PWJ		 608 /* Check to see if speed passed in is supported. */
609 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
610 speed &= link_capabilities;
611
612 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
9a799d71 613 status = IXGBE_ERR_LINK_SETUP;
3201d313
PWJ		 614
615 /* Set KX4/KX support according to speed requested */
616 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
617 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
618 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
619 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
620 autoc |= IXGBE_AUTOC_KX4_SUPP;
621 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
622 autoc |= IXGBE_AUTOC_KX_SUPP;
623 if (autoc != curr_autoc)
624 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
9a799d71
AK		 625 }
626
627 if (status == 0) {
628 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
629
9a799d71
AK		 630 /*
631 * Setup and restart the link based on the new values in
632 * ixgbe_hw This will write the AUTOC register based on the new
633 * stored values
634 */
3201d313 635 status = ixgbe_setup_mac_link_82598(hw);
9a799d71
AK		 636 }
637
638 return status;
639}
640
641
642/**
643 * ixgbe_setup_copper_link_82598 - Setup copper link settings
644 * @hw: pointer to hardware structure
645 *
646 * Configures link settings based on values in the ixgbe_hw struct.
647 * Restarts the link. Performs autonegotiation if needed. Restart
648 * phy and wait for autonegotiate to finish. Then synchronize the
649 * MAC and PHY.
650 **/
651static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
652{
c44ade9e 653 s32 status;
9a799d71
AK		 654
655 /* Restart autonegotiation on PHY */
c44ade9e 656 status = hw->phy.ops.setup_link(hw);
9a799d71 657
3957d63d 658 /* Set up MAC */
c44ade9e 659 ixgbe_setup_mac_link_82598(hw);
9a799d71
AK		 660
661 return status;
662}
663
664/**
665 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
666 * @hw: pointer to hardware structure
667 * @speed: new link speed
668 * @autoneg: true if autonegotiation enabled
669 * @autoneg_wait_to_complete: true if waiting is needed to complete
670 *
671 * Sets the link speed in the AUTOC register in the MAC and restarts link.
672 **/
c44ade9e 673static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
b4617240
PW		 674 ixgbe_link_speed speed,
675 bool autoneg,
676 bool autoneg_wait_to_complete)
9a799d71 677{
c44ade9e 678 s32 status;
9a799d71
AK		 679
680 /* Setup the PHY according to input speed */
b4617240
PW		 681 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
682 autoneg_wait_to_complete);
3957d63d 683
3957d63d 684 /* Set up MAC */
c44ade9e 685 ixgbe_setup_mac_link_82598(hw);
9a799d71
AK		 686
687 return status;
688}
689
690/**
691 * ixgbe_reset_hw_82598 - Performs hardware reset
692 * @hw: pointer to hardware structure
693 *
c44ade9e 694 * Resets the hardware by resetting the transmit and receive units, masks and
9a799d71
AK		 695 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
696 * reset.
697 **/
698static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
699{
700 s32 status = 0;
8ca783ab 701 s32 phy_status = 0;
9a799d71
AK		 702 u32 ctrl;
703 u32 gheccr;
704 u32 i;
705 u32 autoc;
706 u8 analog_val;
707
708 /* Call adapter stop to disable tx/rx and clear interrupts */
c44ade9e 709 hw->mac.ops.stop_adapter(hw);
9a799d71
AK		 710
711 /*
c44ade9e
JB		 712 * Power up the Atlas Tx lanes if they are currently powered down.
713 * Atlas Tx lanes are powered down for MAC loopback tests, but
9a799d71
AK		 714 * they are not automatically restored on reset.
715 */
c44ade9e 716 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
9a799d71 717 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
c44ade9e
JB		 718 /* Enable Tx Atlas so packets can be transmitted again */
719 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
720 &analog_val);
9a799d71 721 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
c44ade9e
JB		 722 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
723 analog_val);
9a799d71 724
c44ade9e
JB		 725 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
726 &analog_val);
9a799d71 727 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
c44ade9e
JB		 728 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
729 analog_val);
9a799d71 730
c44ade9e
JB		 731 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
732 &analog_val);
9a799d71 733 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
c44ade9e
JB		 734 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
735 analog_val);
9a799d71 736
c44ade9e
JB		 737 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
738 &analog_val);
9a799d71 739 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
c44ade9e
JB		 740 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
741 analog_val);
9a799d71
AK		 742 }
743
744 /* Reset PHY */
04f165ef
PW		 745 if (hw->phy.reset_disable == false) {
746 /* PHY ops must be identified and initialized prior to reset */
747
748 /* Init PHY and function pointers, perform SFP setup */
8ca783ab
DS		 749 phy_status = hw->phy.ops.init(hw);
750 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
04f165ef 751 goto reset_hw_out;
8ca783ab
DS		 752 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
753 goto no_phy_reset;
754
04f165ef 755
c44ade9e 756 hw->phy.ops.reset(hw);
04f165ef 757 }
9a799d71 758
8ca783ab 759no_phy_reset:
9a799d71
AK		 760 /*
761 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
762 * access and verify no pending requests before reset
763 */
04f165ef
PW		 764 status = ixgbe_disable_pcie_master(hw);
765 if (status != 0) {
9a799d71
AK		 766 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
767 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
768 }
769
770 /*
771 * Issue global reset to the MAC. This needs to be a SW reset.
772 * If link reset is used, it might reset the MAC when mng is using it
773 */
774 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
775 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
776 IXGBE_WRITE_FLUSH(hw);
777
778 /* Poll for reset bit to self-clear indicating reset is complete */
779 for (i = 0; i < 10; i++) {
780 udelay(1);
781 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
782 if (!(ctrl & IXGBE_CTRL_RST))
783 break;
784 }
785 if (ctrl & IXGBE_CTRL_RST) {
786 status = IXGBE_ERR_RESET_FAILED;
787 hw_dbg(hw, "Reset polling failed to complete.\n");
788 }
789
790 msleep(50);
791
792 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
793 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
794 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
795
796 /*
3201d313
PWJ		 797 * Store the original AUTOC value if it has not been
798 * stored off yet. Otherwise restore the stored original
799 * AUTOC value since the reset operation sets back to deaults.
9a799d71
AK		 800 */
801 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3201d313
PWJ		 802 if (hw->mac.orig_link_settings_stored == false) {
803 hw->mac.orig_autoc = autoc;
804 hw->mac.orig_link_settings_stored = true;
805 } else if (autoc != hw->mac.orig_autoc) {
806 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
9a799d71
AK		 807 }
808
aca6bee7
WJP		 809 /*
810 * Store MAC address from RAR0, clear receive address registers, and
811 * clear the multicast table
812 */
813 hw->mac.ops.init_rx_addrs(hw);
814
9a799d71 815 /* Store the permanent mac address */
c44ade9e 816 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
9a799d71 817
04f165ef 818reset_hw_out:
8ca783ab
DS		 819 if (phy_status)
820 status = phy_status;
821
9a799d71
AK		 822 return status;
823}
824
c44ade9e
JB		 825/**
826 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
827 * @hw: pointer to hardware struct
828 * @rar: receive address register index to associate with a VMDq index
829 * @vmdq: VMDq set index
830 **/
e855aac8 831static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
c44ade9e
JB		 832{
833 u32 rar_high;
834
835 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
836 rar_high &= ~IXGBE_RAH_VIND_MASK;
837 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
838 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
839 return 0;
840}
841
842/**
843 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
844 * @hw: pointer to hardware struct
845 * @rar: receive address register index to associate with a VMDq index
846 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
847 **/
848static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
849{
850 u32 rar_high;
851 u32 rar_entries = hw->mac.num_rar_entries;
852
853 if (rar < rar_entries) {
854 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
855 if (rar_high & IXGBE_RAH_VIND_MASK) {
856 rar_high &= ~IXGBE_RAH_VIND_MASK;
857 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
858 }
859 } else {
860 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
861 }
862
863 return 0;
864}
865
866/**
867 * ixgbe_set_vfta_82598 - Set VLAN filter table
868 * @hw: pointer to hardware structure
869 * @vlan: VLAN id to write to VLAN filter
870 * @vind: VMDq output index that maps queue to VLAN id in VFTA
871 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
872 *
873 * Turn on/off specified VLAN in the VLAN filter table.
874 **/
e855aac8
HE		 875static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
876 bool vlan_on)
c44ade9e
JB		 877{
878 u32 regindex;
879 u32 bitindex;
880 u32 bits;
881 u32 vftabyte;
882
883 if (vlan > 4095)
884 return IXGBE_ERR_PARAM;
885
886 /* Determine 32-bit word position in array */
887 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
888
889 /* Determine the location of the (VMD) queue index */
890 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
891 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
892
893 /* Set the nibble for VMD queue index */
894 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
895 bits &= (~(0x0F << bitindex));
896 bits |= (vind << bitindex);
897 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
898
899 /* Determine the location of the bit for this VLAN id */
900 bitindex = vlan & 0x1F; /* lower five bits */
901
902 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
903 if (vlan_on)
904 /* Turn on this VLAN id */
905 bits |= (1 << bitindex);
906 else
907 /* Turn off this VLAN id */
908 bits &= ~(1 << bitindex);
909 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
910
911 return 0;
912}
913
914/**
915 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
916 * @hw: pointer to hardware structure
917 *
918 * Clears the VLAN filer table, and the VMDq index associated with the filter
919 **/
920static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
921{
922 u32 offset;
923 u32 vlanbyte;
924
925 for (offset = 0; offset < hw->mac.vft_size; offset++)
926 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
927
928 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
929 for (offset = 0; offset < hw->mac.vft_size; offset++)
930 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
b4617240 931 0);
c44ade9e
JB		 932
933 return 0;
934}
935
c44ade9e
JB		 936/**
937 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
938 * @hw: pointer to hardware structure
939 * @reg: analog register to read
940 * @val: read value
941 *
942 * Performs read operation to Atlas analog register specified.
943 **/
e855aac8 944static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
c44ade9e
JB		 945{
946 u32 atlas_ctl;
947
948 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
949 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
950 IXGBE_WRITE_FLUSH(hw);
951 udelay(10);
952 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
953 *val = (u8)atlas_ctl;
954
955 return 0;
956}
957
958/**
959 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
960 * @hw: pointer to hardware structure
961 * @reg: atlas register to write
962 * @val: value to write
963 *
964 * Performs write operation to Atlas analog register specified.
965 **/
e855aac8 966static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
c44ade9e
JB		 967{
968 u32 atlas_ctl;
969
970 atlas_ctl = (reg << 8) | val;
971 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
972 IXGBE_WRITE_FLUSH(hw);
973 udelay(10);
974
975 return 0;
976}
977
c4900be0
DS		 978/**
979 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
980 * over I2C interface through an intermediate phy.
981 * @hw: pointer to hardware structure
982 * @byte_offset: EEPROM byte offset to read
983 * @eeprom_data: value read
984 *
985 * Performs byte read operation to SFP module's EEPROM over I2C interface.
986 **/
e855aac8
HE		 987static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
988 u8 *eeprom_data)
c4900be0
DS		 989{
990 s32 status = 0;
991 u16 sfp_addr = 0;
992 u16 sfp_data = 0;
993 u16 sfp_stat = 0;
994 u32 i;
995
996 if (hw->phy.type == ixgbe_phy_nl) {
997 /*
998 * phy SDA/SCL registers are at addresses 0xC30A to
999 * 0xC30D. These registers are used to talk to the SFP+
1000 * module's EEPROM through the SDA/SCL (I2C) interface.
1001 */
1002 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1003 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1004 hw->phy.ops.write_reg(hw,
1005 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
6b73e10d 1006 MDIO_MMD_PMAPMD,
c4900be0
DS		 1007 sfp_addr);
1008
1009 /* Poll status */
1010 for (i = 0; i < 100; i++) {
1011 hw->phy.ops.read_reg(hw,
1012 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
6b73e10d 1013 MDIO_MMD_PMAPMD,
c4900be0
DS		 1014 &sfp_stat);
1015 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1016 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1017 break;
1018 msleep(10);
1019 }
1020
1021 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1022 hw_dbg(hw, "EEPROM read did not pass.\n");
1023 status = IXGBE_ERR_SFP_NOT_PRESENT;
1024 goto out;
1025 }
1026
1027 /* Read data */
1028 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
6b73e10d 1029 MDIO_MMD_PMAPMD, &sfp_data);
c4900be0
DS		 1030
1031 *eeprom_data = (u8)(sfp_data >> 8);
1032 } else {
1033 status = IXGBE_ERR_PHY;
1034 goto out;
1035 }
1036
1037out:
1038 return status;
1039}
1040
c44ade9e
JB		 1041/**
1042 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1043 * @hw: pointer to hardware structure
1044 *
1045 * Determines physical layer capabilities of the current configuration.
1046 **/
11afc1b1 1047static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
c44ade9e 1048{
11afc1b1 1049 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1050 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1051 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1052 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1053 u16 ext_ability = 0;
1054
1055 hw->phy.ops.identify(hw);
1056
1057 /* Copper PHY must be checked before AUTOC LMS to determine correct
1058 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1059 if (hw->phy.type == ixgbe_phy_tn ||
1060 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 1061 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1062 &ext_ability);
1063 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1064 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1065 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1066 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1067 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1068 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1069 goto out;
1070 }
c44ade9e 1071
04193058
PWJ		 1072 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1073 case IXGBE_AUTOC_LMS_1G_AN:
1074 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1075 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1076 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1077 else
1078 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
c4900be0 1079 break;
04193058
PWJ		 1080 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1081 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1082 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1083 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1084 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1085 else /* XAUI */
1086 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
c44ade9e 1087 break;
04193058
PWJ		 1088 case IXGBE_AUTOC_LMS_KX4_AN:
1089 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1090 if (autoc & IXGBE_AUTOC_KX_SUPP)
1091 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1092 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1093 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
c44ade9e 1094 break;
04193058 1095 default:
0befdb3e 1096 break;
04193058
PWJ		 1097 }
1098
1099 if (hw->phy.type == ixgbe_phy_nl) {
c4900be0
DS		 1100 hw->phy.ops.identify_sfp(hw);
1101
1102 switch (hw->phy.sfp_type) {
1103 case ixgbe_sfp_type_da_cu:
1104 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1105 break;
1106 case ixgbe_sfp_type_sr:
1107 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1108 break;
1109 case ixgbe_sfp_type_lr:
1110 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1111 break;
1112 default:
1113 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1114 break;
1115 }
04193058 1116 }
c44ade9e 1117
04193058
PWJ		 1118 switch (hw->device_id) {
1119 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1120 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1121 break;
1122 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1123 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1124 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1125 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1126 break;
1127 case IXGBE_DEV_ID_82598EB_XF_LR:
1128 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1129 break;
c44ade9e 1130 default:
c44ade9e
JB		 1131 break;
1132 }
1133
04193058 1134out:
c44ade9e
JB		 1135 return physical_layer;
1136}
1137
9a799d71 1138static struct ixgbe_mac_operations mac_ops_82598 = {
c44ade9e
JB		 1139 .init_hw = &ixgbe_init_hw_generic,
1140 .reset_hw = &ixgbe_reset_hw_82598,
1141 .start_hw = &ixgbe_start_hw_generic,
1142 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
9a799d71 1143 .get_media_type = &ixgbe_get_media_type_82598,
c44ade9e 1144 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
11afc1b1 1145 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
c44ade9e
JB		 1146 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1147 .stop_adapter = &ixgbe_stop_adapter_generic,
11afc1b1
PW		 1148 .get_bus_info = &ixgbe_get_bus_info_generic,
1149 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
c44ade9e
JB		 1150 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1151 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
3957d63d 1152 .setup_link = &ixgbe_setup_mac_link_82598,
3957d63d 1153 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
c44ade9e
JB		 1154 .check_link = &ixgbe_check_mac_link_82598,
1155 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1156 .led_on = &ixgbe_led_on_generic,
1157 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 1158 .blink_led_start = &ixgbe_blink_led_start_generic,
1159 .blink_led_stop = &ixgbe_blink_led_stop_generic,
c44ade9e
JB		 1160 .set_rar = &ixgbe_set_rar_generic,
1161 .clear_rar = &ixgbe_clear_rar_generic,
1162 .set_vmdq = &ixgbe_set_vmdq_82598,
1163 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1164 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1165 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1166 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1167 .enable_mc = &ixgbe_enable_mc_generic,
1168 .disable_mc = &ixgbe_disable_mc_generic,
1169 .clear_vfta = &ixgbe_clear_vfta_82598,
1170 .set_vfta = &ixgbe_set_vfta_82598,
1171 .setup_fc = &ixgbe_setup_fc_82598,
1172};
1173
1174static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1175 .init_params = &ixgbe_init_eeprom_params_generic,
1176 .read = &ixgbe_read_eeprom_generic,
1177 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1178 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1179};
1180
1181static struct ixgbe_phy_operations phy_ops_82598 = {
1182 .identify = &ixgbe_identify_phy_generic,
c4900be0 1183 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 1184 .init = &ixgbe_init_phy_ops_82598,
c44ade9e
JB		 1185 .reset = &ixgbe_reset_phy_generic,
1186 .read_reg = &ixgbe_read_phy_reg_generic,
1187 .write_reg = &ixgbe_write_phy_reg_generic,
1188 .setup_link = &ixgbe_setup_phy_link_generic,
1189 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
c4900be0 1190 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
9a799d71
AK		 1191};
1192
3957d63d 1193struct ixgbe_info ixgbe_82598_info = {
9a799d71
AK		 1194 .mac = ixgbe_mac_82598EB,
1195 .get_invariants = &ixgbe_get_invariants_82598,
1196 .mac_ops = &mac_ops_82598,
c44ade9e
JB		 1197 .eeprom_ops = &eeprom_ops_82598,
1198 .phy_ops = &phy_ops_82598,
9a799d71
AK		 1199};
1200
kernel source for telekom puls (alcatel/mediatek)