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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
9c8eb720 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_phy.h" |
34 | ||
35 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
36 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
37 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
38 | #define IXGBE_82598_MC_TBL_SIZE 128 |
39 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
9a799d71 | 40 | |
c44ade9e JB |
41 | static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, |
42 | ixgbe_link_speed *speed, | |
43 | bool *autoneg); | |
8620a103 | 44 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
c44ade9e JB |
45 | ixgbe_link_speed speed, |
46 | bool autoneg, | |
47 | bool autoneg_wait_to_complete); | |
c4900be0 DS |
48 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
49 | u8 *eeprom_data); | |
9a799d71 | 50 | |
202ff1ec MC |
51 | /** |
52 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
53 | * @hw: pointer to the HW structure | |
54 | * | |
55 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
56 | * however the hardware default for these parts is 500us to 1ms which is less | |
57 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
58 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
59 | * or 16ms to 55ms for version 2. | |
60 | **/ | |
7b25cdba | 61 | static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) |
202ff1ec MC |
62 | { |
63 | struct ixgbe_adapter *adapter = hw->back; | |
64 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | |
65 | u16 pcie_devctl2; | |
66 | ||
67 | /* only take action if timeout value is defaulted to 0 */ | |
68 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
69 | goto out; | |
70 | ||
71 | /* | |
72 | * if capababilities version is type 1 we can write the | |
73 | * timeout of 10ms to 250ms through the GCR register | |
74 | */ | |
75 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
76 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
77 | goto out; | |
78 | } | |
79 | ||
80 | /* | |
81 | * for version 2 capabilities we need to write the config space | |
82 | * directly in order to set the completion timeout value for | |
83 | * 16ms to 55ms | |
84 | */ | |
85 | pci_read_config_word(adapter->pdev, | |
86 | IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); | |
87 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; | |
88 | pci_write_config_word(adapter->pdev, | |
89 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | |
90 | out: | |
91 | /* disable completion timeout resend */ | |
92 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
93 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
94 | } | |
95 | ||
eb7f139c PWJ |
96 | /** |
97 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count | |
98 | * @hw: pointer to hardware structure | |
99 | * | |
100 | * Read PCIe configuration space, and get the MSI-X vector count from | |
101 | * the capabilities table. | |
102 | **/ | |
1aef47c4 | 103 | static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) |
eb7f139c PWJ |
104 | { |
105 | struct ixgbe_adapter *adapter = hw->back; | |
106 | u16 msix_count; | |
107 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, | |
108 | &msix_count); | |
109 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; | |
110 | ||
111 | /* MSI-X count is zero-based in HW, so increment to give proper value */ | |
112 | msix_count++; | |
113 | ||
114 | return msix_count; | |
115 | } | |
116 | ||
c44ade9e JB |
117 | /** |
118 | */ | |
9a799d71 | 119 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
120 | { |
121 | struct ixgbe_mac_info *mac = &hw->mac; | |
122 | ||
123 | /* Call PHY identify routine to get the phy type */ | |
124 | ixgbe_identify_phy_generic(hw); | |
125 | ||
126 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
127 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
128 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
129 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; | |
130 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
131 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | /** | |
137 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
138 | * @hw: pointer to hardware structure | |
139 | * | |
140 | * Initialize any function pointers that were not able to be | |
141 | * set during get_invariants because the PHY/SFP type was | |
142 | * not known. Perform the SFP init if necessary. | |
143 | * | |
144 | **/ | |
7b25cdba | 145 | static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) |
9a799d71 | 146 | { |
c44ade9e JB |
147 | struct ixgbe_mac_info *mac = &hw->mac; |
148 | struct ixgbe_phy_info *phy = &hw->phy; | |
c4900be0 DS |
149 | s32 ret_val = 0; |
150 | u16 list_offset, data_offset; | |
c44ade9e | 151 | |
04f165ef PW |
152 | /* Identify the PHY */ |
153 | phy->ops.identify(hw); | |
03cfa205 | 154 | |
04f165ef PW |
155 | /* Overwrite the link function pointers if copper PHY */ |
156 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
157 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
04f165ef PW |
158 | mac->ops.get_link_capabilities = |
159 | &ixgbe_get_copper_link_capabilities_82598; | |
160 | } | |
c44ade9e | 161 | |
04f165ef | 162 | switch (hw->phy.type) { |
0befdb3e JB |
163 | case ixgbe_phy_tn: |
164 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; | |
165 | phy->ops.get_firmware_version = | |
166 | &ixgbe_get_phy_firmware_version_tnx; | |
167 | break; | |
c4900be0 DS |
168 | case ixgbe_phy_nl: |
169 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
170 | ||
171 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
172 | ret_val = phy->ops.identify_sfp(hw); | |
173 | if (ret_val != 0) | |
174 | goto out; | |
175 | else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { | |
176 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
177 | goto out; | |
178 | } | |
179 | ||
180 | /* Check to see if SFP+ module is supported */ | |
181 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
04f165ef PW |
182 | &list_offset, |
183 | &data_offset); | |
c4900be0 DS |
184 | if (ret_val != 0) { |
185 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
186 | goto out; | |
187 | } | |
188 | break; | |
c44ade9e JB |
189 | default: |
190 | break; | |
191 | } | |
192 | ||
c4900be0 DS |
193 | out: |
194 | return ret_val; | |
9a799d71 AK |
195 | } |
196 | ||
202ff1ec MC |
197 | /** |
198 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
199 | * @hw: pointer to hardware structure | |
200 | * | |
201 | * Starts the hardware using the generic start_hw function. | |
202 | * Then set pcie completion timeout | |
203 | **/ | |
7b25cdba | 204 | static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) |
202ff1ec MC |
205 | { |
206 | s32 ret_val = 0; | |
207 | ||
208 | ret_val = ixgbe_start_hw_generic(hw); | |
209 | ||
210 | /* set the completion timeout for interface */ | |
211 | if (ret_val == 0) | |
212 | ixgbe_set_pcie_completion_timeout(hw); | |
213 | ||
214 | return ret_val; | |
215 | } | |
216 | ||
9a799d71 | 217 | /** |
c44ade9e | 218 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
219 | * @hw: pointer to hardware structure |
220 | * @speed: pointer to link speed | |
221 | * @autoneg: boolean auto-negotiation value | |
222 | * | |
c44ade9e | 223 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 224 | **/ |
c44ade9e | 225 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
b4617240 PW |
226 | ixgbe_link_speed *speed, |
227 | bool *autoneg) | |
9a799d71 AK |
228 | { |
229 | s32 status = 0; | |
1eb99d5a | 230 | u32 autoc = 0; |
9a799d71 | 231 | |
3201d313 PWJ |
232 | /* |
233 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
234 | * which represents EEPROM defaults. If AUTOC value has not been |
235 | * stored, use the current register value. | |
3201d313 | 236 | */ |
1eb99d5a PW |
237 | if (hw->mac.orig_link_settings_stored) |
238 | autoc = hw->mac.orig_autoc; | |
239 | else | |
240 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
241 | ||
242 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
243 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
244 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
245 | *autoneg = false; | |
246 | break; | |
247 | ||
248 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
249 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
250 | *autoneg = false; | |
251 | break; | |
252 | ||
253 | case IXGBE_AUTOC_LMS_1G_AN: | |
254 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
255 | *autoneg = true; | |
256 | break; | |
257 | ||
258 | case IXGBE_AUTOC_LMS_KX4_AN: | |
259 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
260 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 261 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 262 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 263 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
264 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
265 | *autoneg = true; | |
266 | break; | |
267 | ||
268 | default: | |
269 | status = IXGBE_ERR_LINK_SETUP; | |
270 | break; | |
271 | } | |
272 | ||
273 | return status; | |
274 | } | |
275 | ||
276 | /** | |
c44ade9e | 277 | * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
278 | * @hw: pointer to hardware structure |
279 | * @speed: pointer to link speed | |
280 | * @autoneg: boolean auto-negotiation value | |
281 | * | |
c44ade9e | 282 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 283 | **/ |
e855aac8 HE |
284 | static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, |
285 | ixgbe_link_speed *speed, | |
286 | bool *autoneg) | |
9a799d71 AK |
287 | { |
288 | s32 status = IXGBE_ERR_LINK_SETUP; | |
289 | u16 speed_ability; | |
290 | ||
291 | *speed = 0; | |
292 | *autoneg = true; | |
293 | ||
6b73e10d | 294 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, |
b4617240 | 295 | &speed_ability); |
9a799d71 AK |
296 | |
297 | if (status == 0) { | |
6b73e10d | 298 | if (speed_ability & MDIO_SPEED_10G) |
9a799d71 | 299 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
6b73e10d | 300 | if (speed_ability & MDIO_PMA_SPEED_1000) |
9a799d71 AK |
301 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
302 | } | |
303 | ||
304 | return status; | |
305 | } | |
306 | ||
307 | /** | |
308 | * ixgbe_get_media_type_82598 - Determines media type | |
309 | * @hw: pointer to hardware structure | |
310 | * | |
311 | * Returns the media type (fiber, copper, backplane) | |
312 | **/ | |
313 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
314 | { | |
315 | enum ixgbe_media_type media_type; | |
316 | ||
317 | /* Media type for I82598 is based on device ID */ | |
318 | switch (hw->device_id) { | |
1e336d0f | 319 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 320 | case IXGBE_DEV_ID_82598_BX: |
1e336d0f DS |
321 | media_type = ixgbe_media_type_backplane; |
322 | break; | |
9a799d71 AK |
323 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
324 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
325 | case IXGBE_DEV_ID_82598EB_CX4: | |
8d792cd9 | 326 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: |
c4900be0 DS |
327 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
328 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 329 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 330 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
9a799d71 AK |
331 | media_type = ixgbe_media_type_fiber; |
332 | break; | |
0befdb3e | 333 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 334 | case IXGBE_DEV_ID_82598AT2: |
0befdb3e JB |
335 | media_type = ixgbe_media_type_copper; |
336 | break; | |
9a799d71 AK |
337 | default: |
338 | media_type = ixgbe_media_type_unknown; | |
339 | break; | |
340 | } | |
341 | ||
342 | return media_type; | |
343 | } | |
344 | ||
c44ade9e | 345 | /** |
0ecc061d | 346 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e JB |
347 | * @hw: pointer to hardware structure |
348 | * @packetbuf_num: packet buffer number (0-7) | |
349 | * | |
0ecc061d | 350 | * Enable flow control according to the current settings. |
c44ade9e | 351 | **/ |
0ecc061d | 352 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) |
c44ade9e | 353 | { |
0ecc061d PWJ |
354 | s32 ret_val = 0; |
355 | u32 fctrl_reg; | |
c44ade9e | 356 | u32 rmcs_reg; |
0ecc061d | 357 | u32 reg; |
c44ade9e | 358 | |
620fa036 MC |
359 | #ifdef CONFIG_DCB |
360 | if (hw->fc.requested_mode == ixgbe_fc_pfc) | |
361 | goto out; | |
362 | ||
363 | #endif /* CONFIG_DCB */ | |
364 | /* Negotiate the fc mode to use */ | |
365 | ret_val = ixgbe_fc_autoneg(hw); | |
366 | if (ret_val) | |
367 | goto out; | |
368 | ||
369 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
370 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
371 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
372 | |
373 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
374 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
375 | ||
376 | /* | |
0ecc061d | 377 | * The possible values of fc.current_mode are: |
c44ade9e | 378 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
379 | * 1: Rx flow control is enabled (we can receive pause frames, |
380 | * but not send pause frames). | |
620fa036 | 381 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 382 | * we do not support receiving pause frames). |
c44ade9e JB |
383 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
384 | * other: Invalid. | |
620fa036 MC |
385 | #ifdef CONFIG_DCB |
386 | * 4: Priority Flow Control is enabled. | |
387 | #endif | |
c44ade9e | 388 | */ |
0ecc061d | 389 | switch (hw->fc.current_mode) { |
c44ade9e | 390 | case ixgbe_fc_none: |
620fa036 MC |
391 | /* |
392 | * Flow control is disabled by software override or autoneg. | |
393 | * The code below will actually disable it in the HW. | |
394 | */ | |
c44ade9e JB |
395 | break; |
396 | case ixgbe_fc_rx_pause: | |
397 | /* | |
0ecc061d PWJ |
398 | * Rx Flow control is enabled and Tx Flow control is |
399 | * disabled by software override. Since there really | |
400 | * isn't a way to advertise that we are capable of RX | |
401 | * Pause ONLY, we will advertise that we support both | |
402 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
403 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 404 | */ |
0ecc061d | 405 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
406 | break; |
407 | case ixgbe_fc_tx_pause: | |
408 | /* | |
0ecc061d PWJ |
409 | * Tx Flow control is enabled, and Rx Flow control is |
410 | * disabled by software override. | |
c44ade9e JB |
411 | */ |
412 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
413 | break; | |
414 | case ixgbe_fc_full: | |
0ecc061d PWJ |
415 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
416 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
417 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
418 | break; | |
620fa036 MC |
419 | #ifdef CONFIG_DCB |
420 | case ixgbe_fc_pfc: | |
421 | goto out; | |
422 | break; | |
423 | #endif /* CONFIG_DCB */ | |
c44ade9e | 424 | default: |
c44ade9e | 425 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
0ecc061d PWJ |
426 | ret_val = -IXGBE_ERR_CONFIG; |
427 | goto out; | |
c44ade9e JB |
428 | break; |
429 | } | |
430 | ||
620fa036 | 431 | /* Set 802.3x based flow control settings. */ |
2132d381 | 432 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 433 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
434 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
435 | ||
0ecc061d PWJ |
436 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
437 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
c44ade9e JB |
438 | if (hw->fc.send_xon) { |
439 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | |
440 | (hw->fc.low_water | IXGBE_FCRTL_XONE)); | |
441 | } else { | |
442 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | |
443 | hw->fc.low_water); | |
444 | } | |
0ecc061d | 445 | |
c44ade9e | 446 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), |
0ecc061d | 447 | (hw->fc.high_water | IXGBE_FCRTH_FCEN)); |
c44ade9e JB |
448 | } |
449 | ||
0ecc061d | 450 | /* Configure pause time (2 TCs per register) */ |
264857b8 | 451 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); |
0ecc061d PWJ |
452 | if ((packetbuf_num & 1) == 0) |
453 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
454 | else | |
455 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
456 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
457 | ||
c44ade9e JB |
458 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); |
459 | ||
0ecc061d PWJ |
460 | out: |
461 | return ret_val; | |
462 | } | |
463 | ||
9a799d71 | 464 | /** |
8620a103 | 465 | * ixgbe_start_mac_link_82598 - Configures MAC link settings |
9a799d71 AK |
466 | * @hw: pointer to hardware structure |
467 | * | |
468 | * Configures link settings based on values in the ixgbe_hw struct. | |
469 | * Restarts the link. Performs autonegotiation if needed. | |
470 | **/ | |
8620a103 MC |
471 | static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, |
472 | bool autoneg_wait_to_complete) | |
9a799d71 AK |
473 | { |
474 | u32 autoc_reg; | |
475 | u32 links_reg; | |
476 | u32 i; | |
477 | s32 status = 0; | |
478 | ||
9a799d71 | 479 | /* Restart link */ |
3201d313 | 480 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
481 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
482 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
483 | ||
484 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 485 | if (autoneg_wait_to_complete) { |
3201d313 PWJ |
486 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
487 | IXGBE_AUTOC_LMS_KX4_AN || | |
488 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
489 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
490 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
491 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
492 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
493 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
494 | break; | |
495 | msleep(100); | |
496 | } | |
497 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
498 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 499 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
500 | } |
501 | } | |
502 | } | |
503 | ||
9a799d71 AK |
504 | /* Add delay to filter out noises during initial link setup */ |
505 | msleep(50); | |
506 | ||
507 | return status; | |
508 | } | |
509 | ||
510 | /** | |
511 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
512 | * @hw: pointer to hardware structure | |
513 | * @speed: pointer to link speed | |
514 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 515 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
516 | * |
517 | * Reads the links register to determine if link is up and the current speed | |
518 | **/ | |
b4617240 PW |
519 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
520 | ixgbe_link_speed *speed, bool *link_up, | |
521 | bool link_up_wait_to_complete) | |
9a799d71 AK |
522 | { |
523 | u32 links_reg; | |
cf8280ee | 524 | u32 i; |
c4900be0 DS |
525 | u16 link_reg, adapt_comp_reg; |
526 | ||
527 | /* | |
528 | * SERDES PHY requires us to read link status from register 0xC79F. | |
529 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
530 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
531 | * clear indicates active; set indicates inactive. | |
532 | */ | |
533 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
534 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
535 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
536 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
c4900be0 DS |
537 | &adapt_comp_reg); |
538 | if (link_up_wait_to_complete) { | |
539 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
540 | if ((link_reg & 1) && | |
541 | ((adapt_comp_reg & 1) == 0)) { | |
542 | *link_up = true; | |
543 | break; | |
544 | } else { | |
545 | *link_up = false; | |
546 | } | |
547 | msleep(100); | |
548 | hw->phy.ops.read_reg(hw, 0xC79F, | |
6b73e10d | 549 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
550 | &link_reg); |
551 | hw->phy.ops.read_reg(hw, 0xC00C, | |
6b73e10d | 552 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
553 | &adapt_comp_reg); |
554 | } | |
555 | } else { | |
556 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
557 | *link_up = true; | |
558 | else | |
559 | *link_up = false; | |
560 | } | |
561 | ||
562 | if (*link_up == false) | |
563 | goto out; | |
564 | } | |
9a799d71 AK |
565 | |
566 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
567 | if (link_up_wait_to_complete) { |
568 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
569 | if (links_reg & IXGBE_LINKS_UP) { | |
570 | *link_up = true; | |
571 | break; | |
572 | } else { | |
573 | *link_up = false; | |
574 | } | |
575 | msleep(100); | |
576 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
577 | } | |
578 | } else { | |
579 | if (links_reg & IXGBE_LINKS_UP) | |
580 | *link_up = true; | |
581 | else | |
582 | *link_up = false; | |
583 | } | |
9a799d71 AK |
584 | |
585 | if (links_reg & IXGBE_LINKS_SPEED) | |
586 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
587 | else | |
588 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
589 | ||
620fa036 MC |
590 | /* if link is down, zero out the current_mode */ |
591 | if (*link_up == false) { | |
592 | hw->fc.current_mode = ixgbe_fc_none; | |
593 | hw->fc.fc_was_autonegged = false; | |
594 | } | |
c4900be0 | 595 | out: |
9a799d71 AK |
596 | return 0; |
597 | } | |
598 | ||
c44ade9e | 599 | |
9a799d71 | 600 | /** |
8620a103 | 601 | * ixgbe_setup_mac_link_82598 - Set MAC link speed |
9a799d71 AK |
602 | * @hw: pointer to hardware structure |
603 | * @speed: new link speed | |
604 | * @autoneg: true if auto-negotiation enabled | |
605 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
606 | * | |
607 | * Set the link speed in the AUTOC register and restarts link. | |
608 | **/ | |
8620a103 | 609 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, |
3201d313 PWJ |
610 | ixgbe_link_speed speed, bool autoneg, |
611 | bool autoneg_wait_to_complete) | |
9a799d71 | 612 | { |
3201d313 PWJ |
613 | s32 status = 0; |
614 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
615 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
616 | u32 autoc = curr_autoc; | |
617 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 618 | |
3201d313 PWJ |
619 | /* Check to see if speed passed in is supported. */ |
620 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
621 | speed &= link_capabilities; | |
622 | ||
623 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
9a799d71 | 624 | status = IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
625 | |
626 | /* Set KX4/KX support according to speed requested */ | |
627 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
628 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
629 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; | |
630 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
631 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
632 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
633 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
634 | if (autoc != curr_autoc) | |
635 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
636 | } |
637 | ||
638 | if (status == 0) { | |
9a799d71 AK |
639 | /* |
640 | * Setup and restart the link based on the new values in | |
641 | * ixgbe_hw This will write the AUTOC register based on the new | |
642 | * stored values | |
643 | */ | |
8620a103 | 644 | status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
645 | } |
646 | ||
647 | return status; | |
648 | } | |
649 | ||
650 | ||
651 | /** | |
8620a103 | 652 | * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field |
9a799d71 AK |
653 | * @hw: pointer to hardware structure |
654 | * @speed: new link speed | |
655 | * @autoneg: true if autonegotiation enabled | |
656 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
657 | * | |
658 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
659 | **/ | |
8620a103 | 660 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
b4617240 PW |
661 | ixgbe_link_speed speed, |
662 | bool autoneg, | |
663 | bool autoneg_wait_to_complete) | |
9a799d71 | 664 | { |
c44ade9e | 665 | s32 status; |
9a799d71 AK |
666 | |
667 | /* Setup the PHY according to input speed */ | |
b4617240 PW |
668 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
669 | autoneg_wait_to_complete); | |
3957d63d | 670 | |
3957d63d | 671 | /* Set up MAC */ |
8620a103 | 672 | ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
673 | |
674 | return status; | |
675 | } | |
676 | ||
677 | /** | |
678 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
679 | * @hw: pointer to hardware structure | |
680 | * | |
c44ade9e | 681 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
682 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
683 | * reset. | |
684 | **/ | |
685 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
686 | { | |
687 | s32 status = 0; | |
8ca783ab | 688 | s32 phy_status = 0; |
9a799d71 AK |
689 | u32 ctrl; |
690 | u32 gheccr; | |
691 | u32 i; | |
692 | u32 autoc; | |
693 | u8 analog_val; | |
694 | ||
695 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
c44ade9e | 696 | hw->mac.ops.stop_adapter(hw); |
9a799d71 AK |
697 | |
698 | /* | |
c44ade9e JB |
699 | * Power up the Atlas Tx lanes if they are currently powered down. |
700 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
701 | * they are not automatically restored on reset. |
702 | */ | |
c44ade9e | 703 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 704 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
705 | /* Enable Tx Atlas so packets can be transmitted again */ |
706 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
707 | &analog_val); | |
9a799d71 | 708 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e JB |
709 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
710 | analog_val); | |
9a799d71 | 711 | |
c44ade9e JB |
712 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
713 | &analog_val); | |
9a799d71 | 714 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e JB |
715 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
716 | analog_val); | |
9a799d71 | 717 | |
c44ade9e JB |
718 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
719 | &analog_val); | |
9a799d71 | 720 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e JB |
721 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
722 | analog_val); | |
9a799d71 | 723 | |
c44ade9e JB |
724 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
725 | &analog_val); | |
9a799d71 | 726 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e JB |
727 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
728 | analog_val); | |
9a799d71 AK |
729 | } |
730 | ||
731 | /* Reset PHY */ | |
04f165ef PW |
732 | if (hw->phy.reset_disable == false) { |
733 | /* PHY ops must be identified and initialized prior to reset */ | |
734 | ||
735 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
736 | phy_status = hw->phy.ops.init(hw); |
737 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
04f165ef | 738 | goto reset_hw_out; |
8ca783ab DS |
739 | else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
740 | goto no_phy_reset; | |
741 | ||
04f165ef | 742 | |
c44ade9e | 743 | hw->phy.ops.reset(hw); |
04f165ef | 744 | } |
9a799d71 | 745 | |
8ca783ab | 746 | no_phy_reset: |
9a799d71 AK |
747 | /* |
748 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
749 | * access and verify no pending requests before reset | |
750 | */ | |
04f165ef PW |
751 | status = ixgbe_disable_pcie_master(hw); |
752 | if (status != 0) { | |
9a799d71 AK |
753 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
754 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
755 | } | |
756 | ||
757 | /* | |
758 | * Issue global reset to the MAC. This needs to be a SW reset. | |
759 | * If link reset is used, it might reset the MAC when mng is using it | |
760 | */ | |
761 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
762 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); | |
763 | IXGBE_WRITE_FLUSH(hw); | |
764 | ||
765 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
766 | for (i = 0; i < 10; i++) { | |
767 | udelay(1); | |
768 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
769 | if (!(ctrl & IXGBE_CTRL_RST)) | |
770 | break; | |
771 | } | |
772 | if (ctrl & IXGBE_CTRL_RST) { | |
773 | status = IXGBE_ERR_RESET_FAILED; | |
774 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
775 | } | |
776 | ||
777 | msleep(50); | |
778 | ||
779 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); | |
780 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
781 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
782 | ||
783 | /* | |
3201d313 PWJ |
784 | * Store the original AUTOC value if it has not been |
785 | * stored off yet. Otherwise restore the stored original | |
786 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
787 | */ |
788 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
789 | if (hw->mac.orig_link_settings_stored == false) { |
790 | hw->mac.orig_autoc = autoc; | |
791 | hw->mac.orig_link_settings_stored = true; | |
792 | } else if (autoc != hw->mac.orig_autoc) { | |
793 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
794 | } |
795 | ||
aca6bee7 WJP |
796 | /* |
797 | * Store MAC address from RAR0, clear receive address registers, and | |
798 | * clear the multicast table | |
799 | */ | |
800 | hw->mac.ops.init_rx_addrs(hw); | |
801 | ||
9a799d71 | 802 | /* Store the permanent mac address */ |
c44ade9e | 803 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
9a799d71 | 804 | |
04f165ef | 805 | reset_hw_out: |
8ca783ab DS |
806 | if (phy_status) |
807 | status = phy_status; | |
808 | ||
9a799d71 AK |
809 | return status; |
810 | } | |
811 | ||
c44ade9e JB |
812 | /** |
813 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
814 | * @hw: pointer to hardware struct | |
815 | * @rar: receive address register index to associate with a VMDq index | |
816 | * @vmdq: VMDq set index | |
817 | **/ | |
e855aac8 | 818 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
819 | { |
820 | u32 rar_high; | |
821 | ||
822 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
823 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
824 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
825 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
826 | return 0; | |
827 | } | |
828 | ||
829 | /** | |
830 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
831 | * @hw: pointer to hardware struct | |
832 | * @rar: receive address register index to associate with a VMDq index | |
833 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
834 | **/ | |
835 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
836 | { | |
837 | u32 rar_high; | |
838 | u32 rar_entries = hw->mac.num_rar_entries; | |
839 | ||
840 | if (rar < rar_entries) { | |
841 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
842 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
843 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
844 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
845 | } | |
846 | } else { | |
847 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
848 | } | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | /** | |
854 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
855 | * @hw: pointer to hardware structure | |
856 | * @vlan: VLAN id to write to VLAN filter | |
857 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
858 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
859 | * | |
860 | * Turn on/off specified VLAN in the VLAN filter table. | |
861 | **/ | |
e855aac8 HE |
862 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
863 | bool vlan_on) | |
c44ade9e JB |
864 | { |
865 | u32 regindex; | |
866 | u32 bitindex; | |
867 | u32 bits; | |
868 | u32 vftabyte; | |
869 | ||
870 | if (vlan > 4095) | |
871 | return IXGBE_ERR_PARAM; | |
872 | ||
873 | /* Determine 32-bit word position in array */ | |
874 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
875 | ||
876 | /* Determine the location of the (VMD) queue index */ | |
877 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
878 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
879 | ||
880 | /* Set the nibble for VMD queue index */ | |
881 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
882 | bits &= (~(0x0F << bitindex)); | |
883 | bits |= (vind << bitindex); | |
884 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
885 | ||
886 | /* Determine the location of the bit for this VLAN id */ | |
887 | bitindex = vlan & 0x1F; /* lower five bits */ | |
888 | ||
889 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
890 | if (vlan_on) | |
891 | /* Turn on this VLAN id */ | |
892 | bits |= (1 << bitindex); | |
893 | else | |
894 | /* Turn off this VLAN id */ | |
895 | bits &= ~(1 << bitindex); | |
896 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | /** | |
902 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
903 | * @hw: pointer to hardware structure | |
904 | * | |
905 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
906 | **/ | |
907 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
908 | { | |
909 | u32 offset; | |
910 | u32 vlanbyte; | |
911 | ||
912 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
913 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
914 | ||
915 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
916 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
917 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
b4617240 | 918 | 0); |
c44ade9e JB |
919 | |
920 | return 0; | |
921 | } | |
922 | ||
c44ade9e JB |
923 | /** |
924 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
925 | * @hw: pointer to hardware structure | |
926 | * @reg: analog register to read | |
927 | * @val: read value | |
928 | * | |
929 | * Performs read operation to Atlas analog register specified. | |
930 | **/ | |
e855aac8 | 931 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
932 | { |
933 | u32 atlas_ctl; | |
934 | ||
935 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
936 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
937 | IXGBE_WRITE_FLUSH(hw); | |
938 | udelay(10); | |
939 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
940 | *val = (u8)atlas_ctl; | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | /** | |
946 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
947 | * @hw: pointer to hardware structure | |
948 | * @reg: atlas register to write | |
949 | * @val: value to write | |
950 | * | |
951 | * Performs write operation to Atlas analog register specified. | |
952 | **/ | |
e855aac8 | 953 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
954 | { |
955 | u32 atlas_ctl; | |
956 | ||
957 | atlas_ctl = (reg << 8) | val; | |
958 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
959 | IXGBE_WRITE_FLUSH(hw); | |
960 | udelay(10); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
c4900be0 DS |
965 | /** |
966 | * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module | |
967 | * over I2C interface through an intermediate phy. | |
968 | * @hw: pointer to hardware structure | |
969 | * @byte_offset: EEPROM byte offset to read | |
970 | * @eeprom_data: value read | |
971 | * | |
972 | * Performs byte read operation to SFP module's EEPROM over I2C interface. | |
973 | **/ | |
e855aac8 HE |
974 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
975 | u8 *eeprom_data) | |
c4900be0 DS |
976 | { |
977 | s32 status = 0; | |
978 | u16 sfp_addr = 0; | |
979 | u16 sfp_data = 0; | |
980 | u16 sfp_stat = 0; | |
981 | u32 i; | |
982 | ||
983 | if (hw->phy.type == ixgbe_phy_nl) { | |
984 | /* | |
985 | * phy SDA/SCL registers are at addresses 0xC30A to | |
986 | * 0xC30D. These registers are used to talk to the SFP+ | |
987 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
988 | */ | |
989 | sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; | |
990 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); | |
991 | hw->phy.ops.write_reg(hw, | |
992 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
6b73e10d | 993 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
994 | sfp_addr); |
995 | ||
996 | /* Poll status */ | |
997 | for (i = 0; i < 100; i++) { | |
998 | hw->phy.ops.read_reg(hw, | |
999 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
6b73e10d | 1000 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1001 | &sfp_stat); |
1002 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; | |
1003 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1004 | break; | |
1005 | msleep(10); | |
1006 | } | |
1007 | ||
1008 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1009 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1010 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1011 | goto out; | |
1012 | } | |
1013 | ||
1014 | /* Read data */ | |
1015 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, | |
6b73e10d | 1016 | MDIO_MMD_PMAPMD, &sfp_data); |
c4900be0 DS |
1017 | |
1018 | *eeprom_data = (u8)(sfp_data >> 8); | |
1019 | } else { | |
1020 | status = IXGBE_ERR_PHY; | |
1021 | goto out; | |
1022 | } | |
1023 | ||
1024 | out: | |
1025 | return status; | |
1026 | } | |
1027 | ||
c44ade9e JB |
1028 | /** |
1029 | * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type | |
1030 | * @hw: pointer to hardware structure | |
1031 | * | |
1032 | * Determines physical layer capabilities of the current configuration. | |
1033 | **/ | |
11afc1b1 | 1034 | static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) |
c44ade9e | 1035 | { |
11afc1b1 | 1036 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
04193058 PWJ |
1037 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1038 | u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1039 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1040 | u16 ext_ability = 0; | |
1041 | ||
1042 | hw->phy.ops.identify(hw); | |
1043 | ||
1044 | /* Copper PHY must be checked before AUTOC LMS to determine correct | |
1045 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ | |
1046 | if (hw->phy.type == ixgbe_phy_tn || | |
1047 | hw->phy.type == ixgbe_phy_cu_unknown) { | |
6b73e10d BH |
1048 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
1049 | &ext_ability); | |
1050 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
04193058 | 1051 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1052 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1053 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1054 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1055 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1056 | goto out; | |
1057 | } | |
c44ade9e | 1058 | |
04193058 PWJ |
1059 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
1060 | case IXGBE_AUTOC_LMS_1G_AN: | |
1061 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1062 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) | |
1063 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1064 | else | |
1065 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
c4900be0 | 1066 | break; |
04193058 PWJ |
1067 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1068 | if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) | |
1069 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1070 | else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) | |
1071 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1072 | else /* XAUI */ | |
1073 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
c44ade9e | 1074 | break; |
04193058 PWJ |
1075 | case IXGBE_AUTOC_LMS_KX4_AN: |
1076 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
1077 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1078 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1079 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1080 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
c44ade9e | 1081 | break; |
04193058 | 1082 | default: |
0befdb3e | 1083 | break; |
04193058 PWJ |
1084 | } |
1085 | ||
1086 | if (hw->phy.type == ixgbe_phy_nl) { | |
c4900be0 DS |
1087 | hw->phy.ops.identify_sfp(hw); |
1088 | ||
1089 | switch (hw->phy.sfp_type) { | |
1090 | case ixgbe_sfp_type_da_cu: | |
1091 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1092 | break; | |
1093 | case ixgbe_sfp_type_sr: | |
1094 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1095 | break; | |
1096 | case ixgbe_sfp_type_lr: | |
1097 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1098 | break; | |
1099 | default: | |
1100 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
1101 | break; | |
1102 | } | |
04193058 | 1103 | } |
c44ade9e | 1104 | |
04193058 PWJ |
1105 | switch (hw->device_id) { |
1106 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: | |
1107 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1108 | break; | |
1109 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: | |
1110 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
1111 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
1112 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1113 | break; | |
1114 | case IXGBE_DEV_ID_82598EB_XF_LR: | |
1115 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1116 | break; | |
c44ade9e | 1117 | default: |
c44ade9e JB |
1118 | break; |
1119 | } | |
1120 | ||
04193058 | 1121 | out: |
c44ade9e JB |
1122 | return physical_layer; |
1123 | } | |
1124 | ||
9a799d71 | 1125 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1126 | .init_hw = &ixgbe_init_hw_generic, |
1127 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1128 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1129 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1130 | .get_media_type = &ixgbe_get_media_type_82598, |
c44ade9e | 1131 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
11afc1b1 | 1132 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1133 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1134 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 PW |
1135 | .get_bus_info = &ixgbe_get_bus_info_generic, |
1136 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
c44ade9e JB |
1137 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1138 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1139 | .setup_link = &ixgbe_setup_mac_link_82598, |
c44ade9e JB |
1140 | .check_link = &ixgbe_check_mac_link_82598, |
1141 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1142 | .led_on = &ixgbe_led_on_generic, | |
1143 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1144 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1145 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1146 | .set_rar = &ixgbe_set_rar_generic, |
1147 | .clear_rar = &ixgbe_clear_rar_generic, | |
1148 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1149 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1150 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
1151 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, | |
1152 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, | |
1153 | .enable_mc = &ixgbe_enable_mc_generic, | |
1154 | .disable_mc = &ixgbe_disable_mc_generic, | |
1155 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1156 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1157 | .fc_enable = &ixgbe_fc_enable_82598, |
c44ade9e JB |
1158 | }; |
1159 | ||
1160 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1161 | .init_params = &ixgbe_init_eeprom_params_generic, | |
1162 | .read = &ixgbe_read_eeprom_generic, | |
1163 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, | |
1164 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1165 | }; | |
1166 | ||
1167 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1168 | .identify = &ixgbe_identify_phy_generic, | |
c4900be0 | 1169 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
04f165ef | 1170 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1171 | .reset = &ixgbe_reset_phy_generic, |
1172 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1173 | .write_reg = &ixgbe_write_phy_reg_generic, | |
1174 | .setup_link = &ixgbe_setup_phy_link_generic, | |
1175 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
c4900be0 | 1176 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
9a799d71 AK |
1177 | }; |
1178 | ||
3957d63d | 1179 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1180 | .mac = ixgbe_mac_82598EB, |
1181 | .get_invariants = &ixgbe_get_invariants_82598, | |
1182 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1183 | .eeprom_ops = &eeprom_ops_82598, |
1184 | .phy_ops = &phy_ops_82598, | |
9a799d71 AK |
1185 | }; |
1186 |