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1da177e4 LT |
1 | /********************************************************************* |
2 | * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $ | |
3 | * | |
4 | * Description: Driver for the SMC Infrared Communications Controller | |
5 | * Status: Experimental. | |
6 | * Author: Daniele Peri (peri@csai.unipa.it) | |
527b6af4 DT |
7 | * Created at: |
8 | * Modified at: | |
9 | * Modified by: | |
10 | * | |
1da177e4 LT |
11 | * Copyright (c) 2002 Daniele Peri |
12 | * All Rights Reserved. | |
13 | * Copyright (c) 2002 Jean Tourrilhes | |
c1e14a6e | 14 | * Copyright (c) 2006 Linus Walleij |
1da177e4 LT |
15 | * |
16 | * | |
17 | * Based on smc-ircc.c: | |
18 | * | |
19 | * Copyright (c) 2001 Stefani Seibold | |
20 | * Copyright (c) 1999-2001 Dag Brattli | |
527b6af4 | 21 | * Copyright (c) 1998-1999 Thomas Davis, |
1da177e4 LT |
22 | * |
23 | * and irport.c: | |
24 | * | |
25 | * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved. | |
26 | * | |
527b6af4 DT |
27 | * |
28 | * This program is free software; you can redistribute it and/or | |
29 | * modify it under the terms of the GNU General Public License as | |
30 | * published by the Free Software Foundation; either version 2 of | |
1da177e4 | 31 | * the License, or (at your option) any later version. |
527b6af4 | 32 | * |
1da177e4 LT |
33 | * This program is distributed in the hope that it will be useful, |
34 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
35 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
36 | * GNU General Public License for more details. | |
527b6af4 DT |
37 | * |
38 | * You should have received a copy of the GNU General Public License | |
39 | * along with this program; if not, write to the Free Software | |
40 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
1da177e4 LT |
41 | * MA 02111-1307 USA |
42 | * | |
43 | ********************************************************************/ | |
44 | ||
45 | #include <linux/module.h> | |
46 | #include <linux/kernel.h> | |
47 | #include <linux/types.h> | |
48 | #include <linux/skbuff.h> | |
49 | #include <linux/netdevice.h> | |
50 | #include <linux/ioport.h> | |
51 | #include <linux/delay.h> | |
52 | #include <linux/slab.h> | |
53 | #include <linux/init.h> | |
54 | #include <linux/rtnetlink.h> | |
55 | #include <linux/serial_reg.h> | |
56 | #include <linux/dma-mapping.h> | |
d94c77b9 | 57 | #include <linux/pnp.h> |
d052d1be | 58 | #include <linux/platform_device.h> |
1da177e4 LT |
59 | |
60 | #include <asm/io.h> | |
61 | #include <asm/dma.h> | |
62 | #include <asm/byteorder.h> | |
63 | ||
64 | #include <linux/spinlock.h> | |
65 | #include <linux/pm.h> | |
c1e14a6e LW |
66 | #ifdef CONFIG_PCI |
67 | #include <linux/pci.h> | |
68 | #endif | |
1da177e4 LT |
69 | |
70 | #include <net/irda/wrapper.h> | |
71 | #include <net/irda/irda.h> | |
72 | #include <net/irda/irda_device.h> | |
73 | ||
74 | #include "smsc-ircc2.h" | |
75 | #include "smsc-sio.h" | |
76 | ||
98b77773 DT |
77 | |
78 | MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); | |
79 | MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); | |
80 | MODULE_LICENSE("GPL"); | |
81 | ||
98b77773 DT |
82 | static int ircc_dma = 255; |
83 | module_param(ircc_dma, int, 0); | |
84 | MODULE_PARM_DESC(ircc_dma, "DMA channel"); | |
85 | ||
86 | static int ircc_irq = 255; | |
87 | module_param(ircc_irq, int, 0); | |
88 | MODULE_PARM_DESC(ircc_irq, "IRQ line"); | |
89 | ||
90 | static int ircc_fir; | |
91 | module_param(ircc_fir, int, 0); | |
92 | MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); | |
93 | ||
94 | static int ircc_sir; | |
95 | module_param(ircc_sir, int, 0); | |
96 | MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); | |
97 | ||
98 | static int ircc_cfg; | |
99 | module_param(ircc_cfg, int, 0); | |
100 | MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); | |
101 | ||
102 | static int ircc_transceiver; | |
103 | module_param(ircc_transceiver, int, 0); | |
104 | MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); | |
105 | ||
1da177e4 LT |
106 | /* Types */ |
107 | ||
c1e14a6e LW |
108 | #ifdef CONFIG_PCI |
109 | struct smsc_ircc_subsystem_configuration { | |
110 | unsigned short vendor; /* PCI vendor ID */ | |
111 | unsigned short device; /* PCI vendor ID */ | |
112 | unsigned short subvendor; /* PCI subsystem vendor ID */ | |
113 | unsigned short subdevice; /* PCI sybsystem device ID */ | |
114 | unsigned short sir_io; /* I/O port for SIR */ | |
115 | unsigned short fir_io; /* I/O port for FIR */ | |
116 | unsigned char fir_irq; /* FIR IRQ */ | |
117 | unsigned char fir_dma; /* FIR DMA */ | |
118 | unsigned short cfg_base; /* I/O port for chip configuration */ | |
119 | int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */ | |
120 | const char *name; /* name shown as info */ | |
121 | }; | |
122 | #endif | |
123 | ||
1da177e4 LT |
124 | struct smsc_transceiver { |
125 | char *name; | |
527b6af4 | 126 | void (*set_for_speed)(int fir_base, u32 speed); |
1da177e4 LT |
127 | int (*probe)(int fir_base); |
128 | }; | |
1da177e4 LT |
129 | |
130 | struct smsc_chip { | |
131 | char *name; | |
132 | #if 0 | |
133 | u8 type; | |
134 | #endif | |
135 | u16 flags; | |
136 | u8 devid; | |
137 | u8 rev; | |
138 | }; | |
1da177e4 LT |
139 | |
140 | struct smsc_chip_address { | |
141 | unsigned int cfg_base; | |
142 | unsigned int type; | |
143 | }; | |
1da177e4 LT |
144 | |
145 | /* Private data for each instance */ | |
146 | struct smsc_ircc_cb { | |
147 | struct net_device *netdev; /* Yes! we are some kind of netdevice */ | |
148 | struct net_device_stats stats; | |
149 | struct irlap_cb *irlap; /* The link layer we are binded to */ | |
527b6af4 | 150 | |
1da177e4 LT |
151 | chipio_t io; /* IrDA controller information */ |
152 | iobuff_t tx_buff; /* Transmit buffer */ | |
153 | iobuff_t rx_buff; /* Receive buffer */ | |
154 | dma_addr_t tx_buff_dma; | |
155 | dma_addr_t rx_buff_dma; | |
156 | ||
157 | struct qos_info qos; /* QoS capabilities for this device */ | |
158 | ||
159 | spinlock_t lock; /* For serializing operations */ | |
527b6af4 | 160 | |
1da177e4 LT |
161 | __u32 new_speed; |
162 | __u32 flags; /* Interface flags */ | |
163 | ||
164 | int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ | |
165 | int tx_len; /* Number of frames in tx_buff */ | |
166 | ||
167 | int transceiver; | |
6bb3b2cd | 168 | struct platform_device *pldev; |
1da177e4 LT |
169 | }; |
170 | ||
171 | /* Constants */ | |
172 | ||
6bb3b2cd DT |
173 | #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2" |
174 | ||
1da177e4 LT |
175 | #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 |
176 | #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 | |
98b77773 | 177 | #define SMSC_IRCC2_C_NET_TIMEOUT 0 |
1da177e4 LT |
178 | #define SMSC_IRCC2_C_SIR_STOP 0 |
179 | ||
6bb3b2cd DT |
180 | static const char *driver_name = SMSC_IRCC2_DRIVER_NAME; |
181 | ||
1da177e4 LT |
182 | /* Prototypes */ |
183 | ||
184 | static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq); | |
185 | static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base); | |
186 | static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq); | |
187 | static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self); | |
188 | static void smsc_ircc_init_chip(struct smsc_ircc_cb *self); | |
189 | static int __exit smsc_ircc_close(struct smsc_ircc_cb *self); | |
80a90589 DT |
190 | static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self); |
191 | static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self); | |
1da177e4 LT |
192 | static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self); |
193 | static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev); | |
194 | static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev); | |
80a90589 DT |
195 | static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs); |
196 | static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self); | |
0fa2f491 DT |
197 | static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed); |
198 | static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed); | |
7d12e780 | 199 | static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id); |
1da177e4 LT |
200 | static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev); |
201 | static void smsc_ircc_sir_start(struct smsc_ircc_cb *self); | |
202 | #if SMSC_IRCC2_C_SIR_STOP | |
203 | static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self); | |
204 | #endif | |
205 | static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self); | |
206 | static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len); | |
207 | static int smsc_ircc_net_open(struct net_device *dev); | |
208 | static int smsc_ircc_net_close(struct net_device *dev); | |
209 | static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
210 | #if SMSC_IRCC2_C_NET_TIMEOUT | |
211 | static void smsc_ircc_timeout(struct net_device *dev); | |
212 | #endif | |
213 | static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev); | |
1da177e4 LT |
214 | static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self); |
215 | static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self); | |
216 | static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed); | |
217 | static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); | |
218 | ||
219 | /* Probing */ | |
220 | static int __init smsc_ircc_look_for_chips(void); | |
b6158d23 DT |
221 | static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type); |
222 | static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type); | |
223 | static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type); | |
1da177e4 LT |
224 | static int __init smsc_superio_fdc(unsigned short cfg_base); |
225 | static int __init smsc_superio_lpc(unsigned short cfg_base); | |
c1e14a6e LW |
226 | #ifdef CONFIG_PCI |
227 | static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf); | |
228 | static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); | |
08d09997 LW |
229 | static void __init preconfigure_ali_port(struct pci_dev *dev, |
230 | unsigned short port); | |
c1e14a6e LW |
231 | static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); |
232 | static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, | |
233 | unsigned short ircc_fir, | |
234 | unsigned short ircc_sir, | |
235 | unsigned char ircc_dma, | |
236 | unsigned char ircc_irq); | |
237 | #endif | |
1da177e4 LT |
238 | |
239 | /* Transceivers specific functions */ | |
240 | ||
241 | static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed); | |
242 | static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base); | |
243 | static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed); | |
244 | static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base); | |
245 | static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed); | |
246 | static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base); | |
247 | ||
248 | /* Power Management */ | |
249 | ||
3ae5eaec RK |
250 | static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state); |
251 | static int smsc_ircc_resume(struct platform_device *dev); | |
1da177e4 | 252 | |
3ae5eaec | 253 | static struct platform_driver smsc_ircc_driver = { |
6bb3b2cd DT |
254 | .suspend = smsc_ircc_suspend, |
255 | .resume = smsc_ircc_resume, | |
3ae5eaec RK |
256 | .driver = { |
257 | .name = SMSC_IRCC2_DRIVER_NAME, | |
258 | }, | |
6bb3b2cd | 259 | }; |
1da177e4 LT |
260 | |
261 | /* Transceivers for SMSC-ircc */ | |
262 | ||
b6158d23 | 263 | static struct smsc_transceiver smsc_transceivers[] = |
1da177e4 | 264 | { |
98b77773 DT |
265 | { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, |
266 | { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, | |
267 | { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, | |
268 | { NULL, NULL } | |
1da177e4 | 269 | }; |
a956f4ca | 270 | #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1) |
1da177e4 LT |
271 | |
272 | /* SMC SuperIO chipsets definitions */ | |
273 | ||
274 | #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */ | |
275 | #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */ | |
276 | #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */ | |
277 | #define SIR 0 /* SuperIO Chip has only slow IRDA */ | |
278 | #define FIR 4 /* SuperIO Chip has fast IRDA */ | |
279 | #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ | |
280 | ||
b6158d23 | 281 | static struct smsc_chip __initdata fdc_chips_flat[] = |
1da177e4 LT |
282 | { |
283 | /* Base address 0x3f0 or 0x370 */ | |
284 | { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ | |
285 | { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 }, | |
286 | { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 }, | |
287 | { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 }, | |
288 | { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */ | |
289 | { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 }, | |
290 | { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 }, | |
291 | { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 }, | |
292 | { NULL } | |
293 | }; | |
294 | ||
b6158d23 | 295 | static struct smsc_chip __initdata fdc_chips_paged[] = |
1da177e4 LT |
296 | { |
297 | /* Base address 0x3f0 or 0x370 */ | |
298 | { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, | |
299 | { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 }, | |
300 | { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 }, | |
301 | { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 }, | |
302 | { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 }, | |
303 | { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 }, | |
304 | { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 }, | |
305 | { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 }, | |
306 | { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 }, | |
307 | { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 }, | |
308 | { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 }, | |
309 | { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 }, | |
310 | { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 }, | |
311 | { NULL } | |
312 | }; | |
313 | ||
b6158d23 | 314 | static struct smsc_chip __initdata lpc_chips_flat[] = |
1da177e4 LT |
315 | { |
316 | /* Base address 0x2E or 0x4E */ | |
317 | { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, | |
afdf27c9 | 318 | { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 }, |
1da177e4 LT |
319 | { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 }, |
320 | { NULL } | |
321 | }; | |
322 | ||
b6158d23 | 323 | static struct smsc_chip __initdata lpc_chips_paged[] = |
1da177e4 LT |
324 | { |
325 | /* Base address 0x2E or 0x4E */ | |
326 | { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, | |
327 | { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 }, | |
328 | { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, | |
329 | { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 }, | |
330 | { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, | |
331 | { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 }, | |
332 | { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 }, | |
333 | { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 }, | |
334 | { NULL } | |
335 | }; | |
336 | ||
337 | #define SMSCSIO_TYPE_FDC 1 | |
338 | #define SMSCSIO_TYPE_LPC 2 | |
339 | #define SMSCSIO_TYPE_FLAT 4 | |
340 | #define SMSCSIO_TYPE_PAGED 8 | |
341 | ||
b6158d23 | 342 | static struct smsc_chip_address __initdata possible_addresses[] = |
1da177e4 | 343 | { |
98b77773 DT |
344 | { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, |
345 | { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
346 | { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
347 | { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
348 | { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, | |
349 | { 0, 0 } | |
1da177e4 LT |
350 | }; |
351 | ||
352 | /* Globals */ | |
353 | ||
98b77773 DT |
354 | static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; |
355 | static unsigned short dev_count; | |
1da177e4 LT |
356 | |
357 | static inline void register_bank(int iobase, int bank) | |
358 | { | |
98b77773 DT |
359 | outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), |
360 | iobase + IRCC_MASTER); | |
1da177e4 LT |
361 | } |
362 | ||
d94c77b9 DB |
363 | #ifdef CONFIG_PNP |
364 | /* PNP hotplug support */ | |
365 | static const struct pnp_device_id smsc_ircc_pnp_table[] = { | |
366 | { .id = "SMCf010", .driver_data = 0 }, | |
367 | /* and presumably others */ | |
368 | { } | |
369 | }; | |
370 | MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table); | |
371 | #endif | |
372 | ||
1da177e4 LT |
373 | |
374 | /******************************************************************************* | |
375 | * | |
376 | * | |
377 | * SMSC-ircc stuff | |
378 | * | |
379 | * | |
380 | *******************************************************************************/ | |
381 | ||
382 | /* | |
383 | * Function smsc_ircc_init () | |
384 | * | |
385 | * Initialize chip. Just try to find out how many chips we are dealing with | |
386 | * and where they are | |
387 | */ | |
388 | static int __init smsc_ircc_init(void) | |
389 | { | |
6bb3b2cd | 390 | int ret; |
1da177e4 LT |
391 | |
392 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
393 | ||
3ae5eaec | 394 | ret = platform_driver_register(&smsc_ircc_driver); |
6bb3b2cd DT |
395 | if (ret) { |
396 | IRDA_ERROR("%s, Can't register driver!\n", driver_name); | |
397 | return ret; | |
398 | } | |
399 | ||
c1e14a6e LW |
400 | #ifdef CONFIG_PCI |
401 | if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) { | |
402 | /* Ignore errors from preconfiguration */ | |
403 | IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name); | |
404 | } | |
405 | #endif | |
406 | ||
98b77773 | 407 | dev_count = 0; |
527b6af4 | 408 | |
98b77773 | 409 | if (ircc_fir > 0 && ircc_sir > 0) { |
1da177e4 LT |
410 | IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); |
411 | IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); | |
412 | ||
6bb3b2cd DT |
413 | if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq)) |
414 | ret = -ENODEV; | |
415 | } else { | |
505db036 | 416 | ret = -ENODEV; |
1da177e4 | 417 | |
6bb3b2cd DT |
418 | /* try user provided configuration register base address */ |
419 | if (ircc_cfg > 0) { | |
420 | IRDA_MESSAGE(" Overriding configuration address " | |
421 | "0x%04x\n", ircc_cfg); | |
422 | if (!smsc_superio_fdc(ircc_cfg)) | |
423 | ret = 0; | |
424 | if (!smsc_superio_lpc(ircc_cfg)) | |
425 | ret = 0; | |
426 | } | |
1da177e4 | 427 | |
6bb3b2cd | 428 | if (smsc_ircc_look_for_chips() > 0) |
1da177e4 LT |
429 | ret = 0; |
430 | } | |
527b6af4 | 431 | |
6bb3b2cd | 432 | if (ret) |
3ae5eaec | 433 | platform_driver_unregister(&smsc_ircc_driver); |
527b6af4 | 434 | |
1da177e4 LT |
435 | return ret; |
436 | } | |
437 | ||
438 | /* | |
439 | * Function smsc_ircc_open (firbase, sirbase, dma, irq) | |
440 | * | |
441 | * Try to open driver instance | |
442 | * | |
443 | */ | |
444 | static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq) | |
445 | { | |
446 | struct smsc_ircc_cb *self; | |
447 | struct net_device *dev; | |
448 | int err; | |
527b6af4 | 449 | |
1da177e4 LT |
450 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
451 | ||
452 | err = smsc_ircc_present(fir_base, sir_base); | |
98b77773 | 453 | if (err) |
1da177e4 | 454 | goto err_out; |
527b6af4 | 455 | |
1da177e4 | 456 | err = -ENOMEM; |
a956f4ca | 457 | if (dev_count >= ARRAY_SIZE(dev_self)) { |
1da177e4 LT |
458 | IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__); |
459 | goto err_out1; | |
460 | } | |
461 | ||
462 | /* | |
463 | * Allocate new instance of the driver | |
464 | */ | |
465 | dev = alloc_irdadev(sizeof(struct smsc_ircc_cb)); | |
466 | if (!dev) { | |
467 | IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__); | |
468 | goto err_out1; | |
469 | } | |
470 | ||
471 | SET_MODULE_OWNER(dev); | |
472 | ||
473 | dev->hard_start_xmit = smsc_ircc_hard_xmit_sir; | |
474 | #if SMSC_IRCC2_C_NET_TIMEOUT | |
475 | dev->tx_timeout = smsc_ircc_timeout; | |
98b77773 | 476 | dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ |
1da177e4 LT |
477 | #endif |
478 | dev->open = smsc_ircc_net_open; | |
479 | dev->stop = smsc_ircc_net_close; | |
480 | dev->do_ioctl = smsc_ircc_net_ioctl; | |
481 | dev->get_stats = smsc_ircc_net_get_stats; | |
527b6af4 | 482 | |
da0841a0 | 483 | self = netdev_priv(dev); |
1da177e4 LT |
484 | self->netdev = dev; |
485 | ||
486 | /* Make ifconfig display some details */ | |
487 | dev->base_addr = self->io.fir_base = fir_base; | |
488 | dev->irq = self->io.irq = irq; | |
489 | ||
490 | /* Need to store self somewhere */ | |
6bb3b2cd | 491 | dev_self[dev_count] = self; |
1da177e4 LT |
492 | spin_lock_init(&self->lock); |
493 | ||
527b6af4 | 494 | self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE; |
1da177e4 LT |
495 | self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE; |
496 | ||
497 | self->rx_buff.head = | |
498 | dma_alloc_coherent(NULL, self->rx_buff.truesize, | |
499 | &self->rx_buff_dma, GFP_KERNEL); | |
500 | if (self->rx_buff.head == NULL) { | |
501 | IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n", | |
502 | driver_name); | |
503 | goto err_out2; | |
504 | } | |
505 | ||
506 | self->tx_buff.head = | |
507 | dma_alloc_coherent(NULL, self->tx_buff.truesize, | |
508 | &self->tx_buff_dma, GFP_KERNEL); | |
509 | if (self->tx_buff.head == NULL) { | |
510 | IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n", | |
511 | driver_name); | |
512 | goto err_out3; | |
513 | } | |
514 | ||
515 | memset(self->rx_buff.head, 0, self->rx_buff.truesize); | |
516 | memset(self->tx_buff.head, 0, self->tx_buff.truesize); | |
517 | ||
518 | self->rx_buff.in_frame = FALSE; | |
519 | self->rx_buff.state = OUTSIDE_FRAME; | |
520 | self->tx_buff.data = self->tx_buff.head; | |
521 | self->rx_buff.data = self->rx_buff.head; | |
527b6af4 | 522 | |
1da177e4 | 523 | smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); |
1da177e4 | 524 | smsc_ircc_setup_qos(self); |
1da177e4 | 525 | smsc_ircc_init_chip(self); |
527b6af4 | 526 | |
98b77773 DT |
527 | if (ircc_transceiver > 0 && |
528 | ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) | |
1da177e4 LT |
529 | self->transceiver = ircc_transceiver; |
530 | else | |
531 | smsc_ircc_probe_transceiver(self); | |
532 | ||
533 | err = register_netdev(self->netdev); | |
98b77773 | 534 | if (err) { |
1da177e4 LT |
535 | IRDA_ERROR("%s, Network device registration failed!\n", |
536 | driver_name); | |
537 | goto err_out4; | |
538 | } | |
539 | ||
6bb3b2cd DT |
540 | self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME, |
541 | dev_count, NULL, 0); | |
542 | if (IS_ERR(self->pldev)) { | |
543 | err = PTR_ERR(self->pldev); | |
544 | goto err_out5; | |
545 | } | |
3ae5eaec | 546 | platform_set_drvdata(self->pldev, self); |
1da177e4 LT |
547 | |
548 | IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); | |
6bb3b2cd | 549 | dev_count++; |
1da177e4 LT |
550 | |
551 | return 0; | |
98b77773 | 552 | |
6bb3b2cd DT |
553 | err_out5: |
554 | unregister_netdev(self->netdev); | |
555 | ||
1da177e4 LT |
556 | err_out4: |
557 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
558 | self->tx_buff.head, self->tx_buff_dma); | |
559 | err_out3: | |
560 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
561 | self->rx_buff.head, self->rx_buff_dma); | |
562 | err_out2: | |
563 | free_netdev(self->netdev); | |
6bb3b2cd | 564 | dev_self[dev_count] = NULL; |
1da177e4 LT |
565 | err_out1: |
566 | release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); | |
567 | release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); | |
568 | err_out: | |
569 | return err; | |
570 | } | |
571 | ||
572 | /* | |
573 | * Function smsc_ircc_present(fir_base, sir_base) | |
574 | * | |
575 | * Check the smsc-ircc chip presence | |
576 | * | |
577 | */ | |
578 | static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) | |
579 | { | |
580 | unsigned char low, high, chip, config, dma, irq, version; | |
581 | ||
582 | if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT, | |
583 | driver_name)) { | |
584 | IRDA_WARNING("%s: can't get fir_base of 0x%03x\n", | |
585 | __FUNCTION__, fir_base); | |
586 | goto out1; | |
587 | } | |
588 | ||
589 | if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT, | |
590 | driver_name)) { | |
591 | IRDA_WARNING("%s: can't get sir_base of 0x%03x\n", | |
592 | __FUNCTION__, sir_base); | |
593 | goto out2; | |
594 | } | |
595 | ||
596 | register_bank(fir_base, 3); | |
597 | ||
98b77773 DT |
598 | high = inb(fir_base + IRCC_ID_HIGH); |
599 | low = inb(fir_base + IRCC_ID_LOW); | |
600 | chip = inb(fir_base + IRCC_CHIP_ID); | |
601 | version = inb(fir_base + IRCC_VERSION); | |
602 | config = inb(fir_base + IRCC_INTERFACE); | |
1da177e4 LT |
603 | dma = config & IRCC_INTERFACE_DMA_MASK; |
604 | irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; | |
605 | ||
527b6af4 | 606 | if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { |
98b77773 | 607 | IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", |
1da177e4 LT |
608 | __FUNCTION__, fir_base); |
609 | goto out3; | |
610 | } | |
611 | IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, " | |
612 | "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n", | |
613 | chip & 0x0f, version, fir_base, sir_base, dma, irq); | |
614 | ||
615 | return 0; | |
98b77773 | 616 | |
1da177e4 LT |
617 | out3: |
618 | release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); | |
619 | out2: | |
620 | release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); | |
621 | out1: | |
622 | return -ENODEV; | |
623 | } | |
624 | ||
625 | /* | |
626 | * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq) | |
627 | * | |
628 | * Setup I/O | |
629 | * | |
630 | */ | |
527b6af4 DT |
631 | static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, |
632 | unsigned int fir_base, unsigned int sir_base, | |
1da177e4 LT |
633 | u8 dma, u8 irq) |
634 | { | |
635 | unsigned char config, chip_dma, chip_irq; | |
636 | ||
637 | register_bank(fir_base, 3); | |
98b77773 DT |
638 | config = inb(fir_base + IRCC_INTERFACE); |
639 | chip_dma = config & IRCC_INTERFACE_DMA_MASK; | |
640 | chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; | |
1da177e4 LT |
641 | |
642 | self->io.fir_base = fir_base; | |
643 | self->io.sir_base = sir_base; | |
644 | self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT; | |
645 | self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT; | |
646 | self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE; | |
647 | self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED; | |
648 | ||
649 | if (irq < 255) { | |
650 | if (irq != chip_irq) | |
651 | IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", | |
652 | driver_name, chip_irq, irq); | |
653 | self->io.irq = irq; | |
98b77773 | 654 | } else |
1da177e4 | 655 | self->io.irq = chip_irq; |
527b6af4 | 656 | |
1da177e4 LT |
657 | if (dma < 255) { |
658 | if (dma != chip_dma) | |
659 | IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", | |
660 | driver_name, chip_dma, dma); | |
661 | self->io.dma = dma; | |
98b77773 | 662 | } else |
1da177e4 LT |
663 | self->io.dma = chip_dma; |
664 | ||
665 | } | |
666 | ||
667 | /* | |
668 | * Function smsc_ircc_setup_qos(self) | |
669 | * | |
670 | * Setup qos | |
671 | * | |
672 | */ | |
673 | static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self) | |
674 | { | |
675 | /* Initialize QoS for this device */ | |
676 | irda_init_max_qos_capabilies(&self->qos); | |
527b6af4 | 677 | |
1da177e4 LT |
678 | self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| |
679 | IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); | |
680 | ||
681 | self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME; | |
682 | self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE; | |
683 | irda_qos_bits_to_value(&self->qos); | |
684 | } | |
685 | ||
686 | /* | |
687 | * Function smsc_ircc_init_chip(self) | |
688 | * | |
689 | * Init chip | |
690 | * | |
691 | */ | |
692 | static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) | |
693 | { | |
e812cb52 | 694 | int iobase = self->io.fir_base; |
1da177e4 LT |
695 | |
696 | register_bank(iobase, 0); | |
98b77773 DT |
697 | outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); |
698 | outb(0x00, iobase + IRCC_MASTER); | |
1da177e4 LT |
699 | |
700 | register_bank(iobase, 1); | |
e812cb52 | 701 | outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), |
98b77773 | 702 | iobase + IRCC_SCE_CFGA); |
1da177e4 LT |
703 | |
704 | #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ | |
98b77773 DT |
705 | outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), |
706 | iobase + IRCC_SCE_CFGB); | |
527b6af4 | 707 | #else |
98b77773 DT |
708 | outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), |
709 | iobase + IRCC_SCE_CFGB); | |
527b6af4 | 710 | #endif |
98b77773 DT |
711 | (void) inb(iobase + IRCC_FIFO_THRESHOLD); |
712 | outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); | |
527b6af4 | 713 | |
1da177e4 | 714 | register_bank(iobase, 4); |
e812cb52 | 715 | outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); |
527b6af4 | 716 | |
1da177e4 | 717 | register_bank(iobase, 0); |
e812cb52 | 718 | outb(0, iobase + IRCC_LCR_A); |
1da177e4 LT |
719 | |
720 | smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); | |
527b6af4 | 721 | |
1da177e4 | 722 | /* Power on device */ |
98b77773 | 723 | outb(0x00, iobase + IRCC_MASTER); |
1da177e4 LT |
724 | } |
725 | ||
726 | /* | |
727 | * Function smsc_ircc_net_ioctl (dev, rq, cmd) | |
728 | * | |
729 | * Process IOCTL commands for this device | |
730 | * | |
731 | */ | |
732 | static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
733 | { | |
734 | struct if_irda_req *irq = (struct if_irda_req *) rq; | |
735 | struct smsc_ircc_cb *self; | |
736 | unsigned long flags; | |
737 | int ret = 0; | |
738 | ||
739 | IRDA_ASSERT(dev != NULL, return -1;); | |
740 | ||
da0841a0 | 741 | self = netdev_priv(dev); |
1da177e4 LT |
742 | |
743 | IRDA_ASSERT(self != NULL, return -1;); | |
744 | ||
745 | IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd); | |
527b6af4 | 746 | |
1da177e4 LT |
747 | switch (cmd) { |
748 | case SIOCSBANDWIDTH: /* Set bandwidth */ | |
749 | if (!capable(CAP_NET_ADMIN)) | |
750 | ret = -EPERM; | |
751 | else { | |
752 | /* Make sure we are the only one touching | |
753 | * self->io.speed and the hardware - Jean II */ | |
754 | spin_lock_irqsave(&self->lock, flags); | |
755 | smsc_ircc_change_speed(self, irq->ifr_baudrate); | |
756 | spin_unlock_irqrestore(&self->lock, flags); | |
757 | } | |
758 | break; | |
759 | case SIOCSMEDIABUSY: /* Set media busy */ | |
760 | if (!capable(CAP_NET_ADMIN)) { | |
761 | ret = -EPERM; | |
762 | break; | |
763 | } | |
764 | ||
765 | irda_device_set_media_busy(self->netdev, TRUE); | |
766 | break; | |
767 | case SIOCGRECEIVING: /* Check if we are receiving right now */ | |
768 | irq->ifr_receiving = smsc_ircc_is_receiving(self); | |
769 | break; | |
770 | #if 0 | |
771 | case SIOCSDTRRTS: | |
772 | if (!capable(CAP_NET_ADMIN)) { | |
773 | ret = -EPERM; | |
774 | break; | |
775 | } | |
776 | smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts); | |
777 | break; | |
778 | #endif | |
779 | default: | |
780 | ret = -EOPNOTSUPP; | |
781 | } | |
527b6af4 | 782 | |
1da177e4 LT |
783 | return ret; |
784 | } | |
785 | ||
786 | static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev) | |
787 | { | |
da0841a0 | 788 | struct smsc_ircc_cb *self = netdev_priv(dev); |
527b6af4 | 789 | |
1da177e4 LT |
790 | return &self->stats; |
791 | } | |
792 | ||
793 | #if SMSC_IRCC2_C_NET_TIMEOUT | |
794 | /* | |
795 | * Function smsc_ircc_timeout (struct net_device *dev) | |
796 | * | |
797 | * The networking timeout management. | |
798 | * | |
799 | */ | |
800 | ||
801 | static void smsc_ircc_timeout(struct net_device *dev) | |
802 | { | |
da0841a0 | 803 | struct smsc_ircc_cb *self = netdev_priv(dev); |
1da177e4 LT |
804 | unsigned long flags; |
805 | ||
1da177e4 LT |
806 | IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n", |
807 | dev->name, self->io.speed); | |
808 | spin_lock_irqsave(&self->lock, flags); | |
809 | smsc_ircc_sir_start(self); | |
810 | smsc_ircc_change_speed(self, self->io.speed); | |
811 | dev->trans_start = jiffies; | |
812 | netif_wake_queue(dev); | |
813 | spin_unlock_irqrestore(&self->lock, flags); | |
814 | } | |
815 | #endif | |
816 | ||
817 | /* | |
818 | * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev) | |
819 | * | |
820 | * Transmits the current frame until FIFO is full, then | |
821 | * waits until the next transmit interrupt, and continues until the | |
822 | * frame is transmitted. | |
823 | */ | |
824 | int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) | |
825 | { | |
826 | struct smsc_ircc_cb *self; | |
827 | unsigned long flags; | |
1da177e4 LT |
828 | s32 speed; |
829 | ||
830 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
831 | ||
832 | IRDA_ASSERT(dev != NULL, return 0;); | |
527b6af4 | 833 | |
da0841a0 | 834 | self = netdev_priv(dev); |
1da177e4 LT |
835 | IRDA_ASSERT(self != NULL, return 0;); |
836 | ||
1da177e4 | 837 | netif_stop_queue(dev); |
527b6af4 | 838 | |
1da177e4 LT |
839 | /* Make sure test of self->io.speed & speed change are atomic */ |
840 | spin_lock_irqsave(&self->lock, flags); | |
841 | ||
842 | /* Check if we need to change the speed */ | |
843 | speed = irda_get_next_speed(skb); | |
98b77773 | 844 | if (speed != self->io.speed && speed != -1) { |
1da177e4 LT |
845 | /* Check for empty frame */ |
846 | if (!skb->len) { | |
847 | /* | |
848 | * We send frames one by one in SIR mode (no | |
849 | * pipelining), so at this point, if we were sending | |
850 | * a previous frame, we just received the interrupt | |
851 | * telling us it is finished (UART_IIR_THRI). | |
852 | * Therefore, waiting for the transmitter to really | |
853 | * finish draining the fifo won't take too long. | |
854 | * And the interrupt handler is not expected to run. | |
855 | * - Jean II */ | |
856 | smsc_ircc_sir_wait_hw_transmitter_finish(self); | |
857 | smsc_ircc_change_speed(self, speed); | |
858 | spin_unlock_irqrestore(&self->lock, flags); | |
859 | dev_kfree_skb(skb); | |
860 | return 0; | |
1da177e4 | 861 | } |
98b77773 | 862 | self->new_speed = speed; |
1da177e4 LT |
863 | } |
864 | ||
865 | /* Init tx buffer */ | |
866 | self->tx_buff.data = self->tx_buff.head; | |
867 | ||
868 | /* Copy skb to tx_buff while wrapping, stuffing and making CRC */ | |
527b6af4 | 869 | self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, |
1da177e4 | 870 | self->tx_buff.truesize); |
527b6af4 | 871 | |
1da177e4 LT |
872 | self->stats.tx_bytes += self->tx_buff.len; |
873 | ||
874 | /* Turn on transmit finished interrupt. Will fire immediately! */ | |
80a90589 | 875 | outb(UART_IER_THRI, self->io.sir_base + UART_IER); |
1da177e4 LT |
876 | |
877 | spin_unlock_irqrestore(&self->lock, flags); | |
878 | ||
879 | dev_kfree_skb(skb); | |
527b6af4 | 880 | |
1da177e4 LT |
881 | return 0; |
882 | } | |
883 | ||
884 | /* | |
885 | * Function smsc_ircc_set_fir_speed (self, baud) | |
886 | * | |
887 | * Change the speed of the device | |
888 | * | |
889 | */ | |
890 | static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) | |
891 | { | |
892 | int fir_base, ir_mode, ctrl, fast; | |
893 | ||
894 | IRDA_ASSERT(self != NULL, return;); | |
895 | fir_base = self->io.fir_base; | |
896 | ||
897 | self->io.speed = speed; | |
898 | ||
98b77773 | 899 | switch (speed) { |
1da177e4 | 900 | default: |
527b6af4 | 901 | case 576000: |
1da177e4 LT |
902 | ir_mode = IRCC_CFGA_IRDA_HDLC; |
903 | ctrl = IRCC_CRC; | |
904 | fast = 0; | |
905 | IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__); | |
906 | break; | |
907 | case 1152000: | |
908 | ir_mode = IRCC_CFGA_IRDA_HDLC; | |
909 | ctrl = IRCC_1152 | IRCC_CRC; | |
910 | fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA; | |
911 | IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", | |
912 | __FUNCTION__); | |
913 | break; | |
914 | case 4000000: | |
915 | ir_mode = IRCC_CFGA_IRDA_4PPM; | |
916 | ctrl = IRCC_CRC; | |
917 | fast = IRCC_LCR_A_FAST; | |
918 | IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", | |
919 | __FUNCTION__); | |
920 | break; | |
921 | } | |
922 | #if 0 | |
923 | Now in tranceiver! | |
924 | /* This causes an interrupt */ | |
925 | register_bank(fir_base, 0); | |
98b77773 | 926 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); |
1da177e4 | 927 | #endif |
527b6af4 | 928 | |
1da177e4 | 929 | register_bank(fir_base, 1); |
98b77773 | 930 | outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); |
527b6af4 | 931 | |
1da177e4 | 932 | register_bank(fir_base, 4); |
98b77773 | 933 | outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); |
1da177e4 LT |
934 | } |
935 | ||
936 | /* | |
937 | * Function smsc_ircc_fir_start(self) | |
938 | * | |
939 | * Change the speed of the device | |
940 | * | |
941 | */ | |
942 | static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) | |
943 | { | |
944 | struct net_device *dev; | |
945 | int fir_base; | |
946 | ||
947 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
948 | ||
949 | IRDA_ASSERT(self != NULL, return;); | |
950 | dev = self->netdev; | |
951 | IRDA_ASSERT(dev != NULL, return;); | |
952 | ||
953 | fir_base = self->io.fir_base; | |
954 | ||
955 | /* Reset everything */ | |
956 | ||
957 | /* Install FIR transmit handler */ | |
527b6af4 | 958 | dev->hard_start_xmit = smsc_ircc_hard_xmit_fir; |
1da177e4 LT |
959 | |
960 | /* Clear FIFO */ | |
98b77773 | 961 | outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); |
1da177e4 LT |
962 | |
963 | /* Enable interrupt */ | |
98b77773 | 964 | /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ |
1da177e4 LT |
965 | |
966 | register_bank(fir_base, 1); | |
967 | ||
527b6af4 | 968 | /* Select the TX/RX interface */ |
1da177e4 | 969 | #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ |
98b77773 DT |
970 | outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), |
971 | fir_base + IRCC_SCE_CFGB); | |
527b6af4 | 972 | #else |
98b77773 DT |
973 | outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), |
974 | fir_base + IRCC_SCE_CFGB); | |
527b6af4 | 975 | #endif |
98b77773 | 976 | (void) inb(fir_base + IRCC_FIFO_THRESHOLD); |
1da177e4 LT |
977 | |
978 | /* Enable SCE interrupts */ | |
98b77773 | 979 | outb(0, fir_base + IRCC_MASTER); |
1da177e4 | 980 | register_bank(fir_base, 0); |
98b77773 DT |
981 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); |
982 | outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); | |
1da177e4 LT |
983 | } |
984 | ||
985 | /* | |
986 | * Function smsc_ircc_fir_stop(self, baud) | |
987 | * | |
988 | * Change the speed of the device | |
989 | * | |
990 | */ | |
991 | static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) | |
992 | { | |
993 | int fir_base; | |
994 | ||
995 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
527b6af4 | 996 | |
1da177e4 LT |
997 | IRDA_ASSERT(self != NULL, return;); |
998 | ||
999 | fir_base = self->io.fir_base; | |
1000 | register_bank(fir_base, 0); | |
98b77773 DT |
1001 | /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ |
1002 | outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); | |
1da177e4 LT |
1003 | } |
1004 | ||
1005 | ||
1006 | /* | |
1007 | * Function smsc_ircc_change_speed(self, baud) | |
1008 | * | |
1009 | * Change the speed of the device | |
1010 | * | |
1011 | * This function *must* be called with spinlock held, because it may | |
1012 | * be called from the irq handler. - Jean II | |
1013 | */ | |
0fa2f491 | 1014 | static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed) |
1da177e4 | 1015 | { |
1da177e4 | 1016 | struct net_device *dev; |
1da177e4 | 1017 | int last_speed_was_sir; |
527b6af4 | 1018 | |
1da177e4 LT |
1019 | IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed); |
1020 | ||
1021 | IRDA_ASSERT(self != NULL, return;); | |
1022 | dev = self->netdev; | |
1da177e4 LT |
1023 | |
1024 | last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED; | |
1025 | ||
1026 | #if 0 | |
1027 | /* Temp Hack */ | |
1028 | speed= 1152000; | |
1029 | self->io.speed = speed; | |
1030 | last_speed_was_sir = 0; | |
527b6af4 | 1031 | smsc_ircc_fir_start(self); |
1da177e4 | 1032 | #endif |
527b6af4 | 1033 | |
98b77773 | 1034 | if (self->io.speed == 0) |
1da177e4 LT |
1035 | smsc_ircc_sir_start(self); |
1036 | ||
1037 | #if 0 | |
98b77773 | 1038 | if (!last_speed_was_sir) speed = self->io.speed; |
1da177e4 LT |
1039 | #endif |
1040 | ||
98b77773 DT |
1041 | if (self->io.speed != speed) |
1042 | smsc_ircc_set_transceiver_for_speed(self, speed); | |
1da177e4 LT |
1043 | |
1044 | self->io.speed = speed; | |
527b6af4 | 1045 | |
98b77773 DT |
1046 | if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { |
1047 | if (!last_speed_was_sir) { | |
1da177e4 LT |
1048 | smsc_ircc_fir_stop(self); |
1049 | smsc_ircc_sir_start(self); | |
1050 | } | |
527b6af4 | 1051 | smsc_ircc_set_sir_speed(self, speed); |
98b77773 DT |
1052 | } else { |
1053 | if (last_speed_was_sir) { | |
527b6af4 | 1054 | #if SMSC_IRCC2_C_SIR_STOP |
1da177e4 LT |
1055 | smsc_ircc_sir_stop(self); |
1056 | #endif | |
1057 | smsc_ircc_fir_start(self); | |
1058 | } | |
1059 | smsc_ircc_set_fir_speed(self, speed); | |
1060 | ||
1061 | #if 0 | |
1062 | self->tx_buff.len = 10; | |
1063 | self->tx_buff.data = self->tx_buff.head; | |
527b6af4 | 1064 | |
80a90589 | 1065 | smsc_ircc_dma_xmit(self, 4000); |
1da177e4 LT |
1066 | #endif |
1067 | /* Be ready for incoming frames */ | |
80a90589 | 1068 | smsc_ircc_dma_receive(self); |
1da177e4 | 1069 | } |
527b6af4 | 1070 | |
1da177e4 LT |
1071 | netif_wake_queue(dev); |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * Function smsc_ircc_set_sir_speed (self, speed) | |
1076 | * | |
1077 | * Set speed of IrDA port to specified baudrate | |
1078 | * | |
1079 | */ | |
0fa2f491 | 1080 | void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed) |
1da177e4 | 1081 | { |
527b6af4 | 1082 | int iobase; |
1da177e4 LT |
1083 | int fcr; /* FIFO control reg */ |
1084 | int lcr; /* Line control reg */ | |
1085 | int divisor; | |
1086 | ||
1087 | IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed); | |
1088 | ||
1089 | IRDA_ASSERT(self != NULL, return;); | |
1090 | iobase = self->io.sir_base; | |
527b6af4 | 1091 | |
1da177e4 LT |
1092 | /* Update accounting for new speed */ |
1093 | self->io.speed = speed; | |
1094 | ||
1095 | /* Turn off interrupts */ | |
98b77773 | 1096 | outb(0, iobase + UART_IER); |
1da177e4 | 1097 | |
98b77773 | 1098 | divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; |
527b6af4 | 1099 | |
1da177e4 LT |
1100 | fcr = UART_FCR_ENABLE_FIFO; |
1101 | ||
527b6af4 | 1102 | /* |
1da177e4 LT |
1103 | * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and |
1104 | * almost 1,7 ms at 19200 bps. At speeds above that we can just forget | |
527b6af4 | 1105 | * about this timeout since it will always be fast enough. |
1da177e4 | 1106 | */ |
98b77773 DT |
1107 | fcr |= self->io.speed < 38400 ? |
1108 | UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; | |
527b6af4 | 1109 | |
1da177e4 LT |
1110 | /* IrDA ports use 8N1 */ |
1111 | lcr = UART_LCR_WLEN8; | |
527b6af4 | 1112 | |
98b77773 DT |
1113 | outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ |
1114 | outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ | |
1115 | outb(divisor >> 8, iobase + UART_DLM); | |
1116 | outb(lcr, iobase + UART_LCR); /* Set 8N1 */ | |
1117 | outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ | |
1da177e4 LT |
1118 | |
1119 | /* Turn on interrups */ | |
98b77773 | 1120 | outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); |
1da177e4 LT |
1121 | |
1122 | IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed); | |
1123 | } | |
1124 | ||
1125 | ||
1126 | /* | |
1127 | * Function smsc_ircc_hard_xmit_fir (skb, dev) | |
1128 | * | |
1129 | * Transmit the frame! | |
1130 | * | |
1131 | */ | |
1132 | static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) | |
1133 | { | |
1134 | struct smsc_ircc_cb *self; | |
1135 | unsigned long flags; | |
1136 | s32 speed; | |
1da177e4 LT |
1137 | int mtt; |
1138 | ||
1139 | IRDA_ASSERT(dev != NULL, return 0;); | |
da0841a0 | 1140 | self = netdev_priv(dev); |
1da177e4 LT |
1141 | IRDA_ASSERT(self != NULL, return 0;); |
1142 | ||
1da177e4 LT |
1143 | netif_stop_queue(dev); |
1144 | ||
1145 | /* Make sure test of self->io.speed & speed change are atomic */ | |
1146 | spin_lock_irqsave(&self->lock, flags); | |
1147 | ||
1148 | /* Check if we need to change the speed after this frame */ | |
1149 | speed = irda_get_next_speed(skb); | |
98b77773 | 1150 | if (speed != self->io.speed && speed != -1) { |
1da177e4 LT |
1151 | /* Check for empty frame */ |
1152 | if (!skb->len) { | |
1153 | /* Note : you should make sure that speed changes | |
1154 | * are not going to corrupt any outgoing frame. | |
1155 | * Look at nsc-ircc for the gory details - Jean II */ | |
527b6af4 | 1156 | smsc_ircc_change_speed(self, speed); |
1da177e4 LT |
1157 | spin_unlock_irqrestore(&self->lock, flags); |
1158 | dev_kfree_skb(skb); | |
1159 | return 0; | |
98b77773 DT |
1160 | } |
1161 | ||
1162 | self->new_speed = speed; | |
1da177e4 | 1163 | } |
527b6af4 | 1164 | |
d626f62b | 1165 | skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len); |
1da177e4 LT |
1166 | |
1167 | self->tx_buff.len = skb->len; | |
1168 | self->tx_buff.data = self->tx_buff.head; | |
527b6af4 DT |
1169 | |
1170 | mtt = irda_get_mtt(skb); | |
1da177e4 LT |
1171 | if (mtt) { |
1172 | int bofs; | |
1173 | ||
527b6af4 | 1174 | /* |
1da177e4 LT |
1175 | * Compute how many BOFs (STA or PA's) we need to waste the |
1176 | * min turn time given the speed of the link. | |
1177 | */ | |
1178 | bofs = mtt * (self->io.speed / 1000) / 8000; | |
1179 | if (bofs > 4095) | |
1180 | bofs = 4095; | |
1181 | ||
80a90589 | 1182 | smsc_ircc_dma_xmit(self, bofs); |
1da177e4 LT |
1183 | } else { |
1184 | /* Transmit frame */ | |
80a90589 | 1185 | smsc_ircc_dma_xmit(self, 0); |
1da177e4 | 1186 | } |
98b77773 | 1187 | |
1da177e4 LT |
1188 | spin_unlock_irqrestore(&self->lock, flags); |
1189 | dev_kfree_skb(skb); | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | /* | |
80a90589 | 1195 | * Function smsc_ircc_dma_xmit (self, bofs) |
1da177e4 LT |
1196 | * |
1197 | * Transmit data using DMA | |
1198 | * | |
1199 | */ | |
80a90589 | 1200 | static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs) |
1da177e4 | 1201 | { |
80a90589 | 1202 | int iobase = self->io.fir_base; |
1da177e4 LT |
1203 | u8 ctrl; |
1204 | ||
1205 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); | |
1206 | #if 1 | |
1207 | /* Disable Rx */ | |
1208 | register_bank(iobase, 0); | |
98b77773 | 1209 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 LT |
1210 | #endif |
1211 | register_bank(iobase, 1); | |
98b77773 DT |
1212 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1213 | iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1214 | |
1215 | self->io.direction = IO_XMIT; | |
1216 | ||
1217 | /* Set BOF additional count for generating the min turn time */ | |
1218 | register_bank(iobase, 4); | |
98b77773 DT |
1219 | outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); |
1220 | ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; | |
1221 | outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); | |
1da177e4 LT |
1222 | |
1223 | /* Set max Tx frame size */ | |
98b77773 DT |
1224 | outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); |
1225 | outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); | |
1da177e4 LT |
1226 | |
1227 | /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ | |
527b6af4 | 1228 | |
1da177e4 LT |
1229 | /* Enable burst mode chip Tx DMA */ |
1230 | register_bank(iobase, 1); | |
98b77773 DT |
1231 | outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | |
1232 | IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1233 | |
1234 | /* Setup DMA controller (must be done after enabling chip DMA) */ | |
1235 | irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, | |
1236 | DMA_TX_MODE); | |
1237 | ||
1238 | /* Enable interrupt */ | |
1239 | ||
1240 | register_bank(iobase, 0); | |
98b77773 DT |
1241 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1242 | outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); | |
527b6af4 | 1243 | |
1da177e4 | 1244 | /* Enable transmit */ |
98b77773 | 1245 | outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); |
1da177e4 LT |
1246 | } |
1247 | ||
1248 | /* | |
1249 | * Function smsc_ircc_dma_xmit_complete (self) | |
1250 | * | |
527b6af4 | 1251 | * The transfer of a frame in finished. This function will only be called |
1da177e4 LT |
1252 | * by the interrupt handler |
1253 | * | |
1254 | */ | |
80a90589 | 1255 | static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self) |
1da177e4 | 1256 | { |
80a90589 DT |
1257 | int iobase = self->io.fir_base; |
1258 | ||
1da177e4 LT |
1259 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); |
1260 | #if 0 | |
1261 | /* Disable Tx */ | |
1262 | register_bank(iobase, 0); | |
98b77773 | 1263 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 | 1264 | #endif |
80a90589 DT |
1265 | register_bank(iobase, 1); |
1266 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, | |
1267 | iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1268 | |
1269 | /* Check for underrun! */ | |
1270 | register_bank(iobase, 0); | |
98b77773 | 1271 | if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { |
1da177e4 LT |
1272 | self->stats.tx_errors++; |
1273 | self->stats.tx_fifo_errors++; | |
1274 | ||
1275 | /* Reset error condition */ | |
1276 | register_bank(iobase, 0); | |
98b77773 DT |
1277 | outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); |
1278 | outb(0x00, iobase + IRCC_MASTER); | |
1da177e4 LT |
1279 | } else { |
1280 | self->stats.tx_packets++; | |
98b77773 | 1281 | self->stats.tx_bytes += self->tx_buff.len; |
1da177e4 LT |
1282 | } |
1283 | ||
1284 | /* Check if it's time to change the speed */ | |
1285 | if (self->new_speed) { | |
527b6af4 | 1286 | smsc_ircc_change_speed(self, self->new_speed); |
1da177e4 LT |
1287 | self->new_speed = 0; |
1288 | } | |
1289 | ||
1290 | netif_wake_queue(self->netdev); | |
1291 | } | |
1292 | ||
1293 | /* | |
1294 | * Function smsc_ircc_dma_receive(self) | |
1295 | * | |
1296 | * Get ready for receiving a frame. The device will initiate a DMA | |
1297 | * if it starts to receive a frame. | |
1298 | * | |
1299 | */ | |
80a90589 | 1300 | static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self) |
1da177e4 | 1301 | { |
80a90589 | 1302 | int iobase = self->io.fir_base; |
1da177e4 LT |
1303 | #if 0 |
1304 | /* Turn off chip DMA */ | |
1305 | register_bank(iobase, 1); | |
98b77773 DT |
1306 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1307 | iobase + IRCC_SCE_CFGB); | |
1da177e4 | 1308 | #endif |
527b6af4 | 1309 | |
1da177e4 LT |
1310 | /* Disable Tx */ |
1311 | register_bank(iobase, 0); | |
98b77773 | 1312 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 LT |
1313 | |
1314 | /* Turn off chip DMA */ | |
1315 | register_bank(iobase, 1); | |
98b77773 DT |
1316 | outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, |
1317 | iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1318 | |
1319 | self->io.direction = IO_RECV; | |
1320 | self->rx_buff.data = self->rx_buff.head; | |
1321 | ||
1322 | /* Set max Rx frame size */ | |
1323 | register_bank(iobase, 4); | |
98b77773 DT |
1324 | outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); |
1325 | outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); | |
1da177e4 LT |
1326 | |
1327 | /* Setup DMA controller */ | |
1328 | irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, | |
1329 | DMA_RX_MODE); | |
1330 | ||
1331 | /* Enable burst mode chip Rx DMA */ | |
1332 | register_bank(iobase, 1); | |
98b77773 DT |
1333 | outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | |
1334 | IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); | |
1da177e4 LT |
1335 | |
1336 | /* Enable interrupt */ | |
1337 | register_bank(iobase, 0); | |
98b77773 DT |
1338 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1339 | outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); | |
1da177e4 LT |
1340 | |
1341 | /* Enable receiver */ | |
1342 | register_bank(iobase, 0); | |
527b6af4 | 1343 | outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, |
98b77773 | 1344 | iobase + IRCC_LCR_B); |
527b6af4 | 1345 | |
1da177e4 LT |
1346 | return 0; |
1347 | } | |
1348 | ||
1349 | /* | |
80a90589 | 1350 | * Function smsc_ircc_dma_receive_complete(self) |
1da177e4 LT |
1351 | * |
1352 | * Finished with receiving frames | |
1353 | * | |
1354 | */ | |
80a90589 | 1355 | static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self) |
1da177e4 LT |
1356 | { |
1357 | struct sk_buff *skb; | |
1358 | int len, msgcnt, lsr; | |
80a90589 | 1359 | int iobase = self->io.fir_base; |
527b6af4 | 1360 | |
1da177e4 | 1361 | register_bank(iobase, 0); |
527b6af4 | 1362 | |
1da177e4 LT |
1363 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); |
1364 | #if 0 | |
1365 | /* Disable Rx */ | |
1366 | register_bank(iobase, 0); | |
98b77773 | 1367 | outb(0x00, iobase + IRCC_LCR_B); |
1da177e4 LT |
1368 | #endif |
1369 | register_bank(iobase, 0); | |
98b77773 DT |
1370 | outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); |
1371 | lsr= inb(iobase + IRCC_LSR); | |
1372 | msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; | |
1da177e4 LT |
1373 | |
1374 | IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__, | |
1375 | get_dma_residue(self->io.dma)); | |
1376 | ||
1377 | len = self->rx_buff.truesize - get_dma_residue(self->io.dma); | |
1378 | ||
98b77773 DT |
1379 | /* Look for errors */ |
1380 | if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { | |
1da177e4 | 1381 | self->stats.rx_errors++; |
98b77773 DT |
1382 | if (lsr & IRCC_LSR_FRAME_ERROR) |
1383 | self->stats.rx_frame_errors++; | |
1384 | if (lsr & IRCC_LSR_CRC_ERROR) | |
1385 | self->stats.rx_crc_errors++; | |
1386 | if (lsr & IRCC_LSR_SIZE_ERROR) | |
1387 | self->stats.rx_length_errors++; | |
1388 | if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) | |
1389 | self->stats.rx_length_errors++; | |
1da177e4 LT |
1390 | return; |
1391 | } | |
98b77773 | 1392 | |
1da177e4 | 1393 | /* Remove CRC */ |
98b77773 | 1394 | len -= self->io.speed < 4000000 ? 2 : 4; |
1da177e4 | 1395 | |
98b77773 | 1396 | if (len < 2 || len > 2050) { |
1da177e4 LT |
1397 | IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len); |
1398 | return; | |
1399 | } | |
1400 | IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len); | |
1401 | ||
98b77773 DT |
1402 | skb = dev_alloc_skb(len + 1); |
1403 | if (!skb) { | |
1da177e4 LT |
1404 | IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", |
1405 | __FUNCTION__); | |
1406 | return; | |
527b6af4 | 1407 | } |
1da177e4 | 1408 | /* Make sure IP header gets aligned */ |
527b6af4 | 1409 | skb_reserve(skb, 1); |
1da177e4 LT |
1410 | |
1411 | memcpy(skb_put(skb, len), self->rx_buff.data, len); | |
1412 | self->stats.rx_packets++; | |
1413 | self->stats.rx_bytes += len; | |
1414 | ||
1415 | skb->dev = self->netdev; | |
459a98ed | 1416 | skb_reset_mac_header(skb); |
1da177e4 LT |
1417 | skb->protocol = htons(ETH_P_IRDA); |
1418 | netif_rx(skb); | |
1419 | } | |
1420 | ||
1421 | /* | |
1422 | * Function smsc_ircc_sir_receive (self) | |
1423 | * | |
1424 | * Receive one frame from the infrared port | |
1425 | * | |
1426 | */ | |
527b6af4 | 1427 | static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) |
1da177e4 LT |
1428 | { |
1429 | int boguscount = 0; | |
1430 | int iobase; | |
1431 | ||
1432 | IRDA_ASSERT(self != NULL, return;); | |
1433 | ||
1434 | iobase = self->io.sir_base; | |
1435 | ||
527b6af4 DT |
1436 | /* |
1437 | * Receive all characters in Rx FIFO, unwrap and unstuff them. | |
1438 | * async_unwrap_char will deliver all found frames | |
1da177e4 LT |
1439 | */ |
1440 | do { | |
527b6af4 | 1441 | async_unwrap_char(self->netdev, &self->stats, &self->rx_buff, |
98b77773 | 1442 | inb(iobase + UART_RX)); |
1da177e4 LT |
1443 | |
1444 | /* Make sure we don't stay here to long */ | |
1445 | if (boguscount++ > 32) { | |
1446 | IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__); | |
1447 | break; | |
1448 | } | |
98b77773 | 1449 | } while (inb(iobase + UART_LSR) & UART_LSR_DR); |
1da177e4 LT |
1450 | } |
1451 | ||
1452 | ||
1453 | /* | |
1454 | * Function smsc_ircc_interrupt (irq, dev_id, regs) | |
1455 | * | |
1456 | * An interrupt from the chip has arrived. Time to do some work | |
1457 | * | |
1458 | */ | |
7d12e780 | 1459 | static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1460 | { |
1461 | struct net_device *dev = (struct net_device *) dev_id; | |
1462 | struct smsc_ircc_cb *self; | |
1463 | int iobase, iir, lcra, lsr; | |
1464 | irqreturn_t ret = IRQ_NONE; | |
1465 | ||
1466 | if (dev == NULL) { | |
527b6af4 | 1467 | printk(KERN_WARNING "%s: irq %d for unknown device.\n", |
1da177e4 LT |
1468 | driver_name, irq); |
1469 | goto irq_ret; | |
1470 | } | |
da0841a0 DT |
1471 | |
1472 | self = netdev_priv(dev); | |
1da177e4 LT |
1473 | IRDA_ASSERT(self != NULL, return IRQ_NONE;); |
1474 | ||
1475 | /* Serialise the interrupt handler in various CPUs, stop Tx path */ | |
527b6af4 | 1476 | spin_lock(&self->lock); |
1da177e4 LT |
1477 | |
1478 | /* Check if we should use the SIR interrupt handler */ | |
98b77773 | 1479 | if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { |
1da177e4 LT |
1480 | ret = smsc_ircc_interrupt_sir(dev); |
1481 | goto irq_ret_unlock; | |
1482 | } | |
1483 | ||
1484 | iobase = self->io.fir_base; | |
1485 | ||
1486 | register_bank(iobase, 0); | |
98b77773 | 1487 | iir = inb(iobase + IRCC_IIR); |
527b6af4 | 1488 | if (iir == 0) |
1da177e4 LT |
1489 | goto irq_ret_unlock; |
1490 | ret = IRQ_HANDLED; | |
1491 | ||
1492 | /* Disable interrupts */ | |
98b77773 DT |
1493 | outb(0, iobase + IRCC_IER); |
1494 | lcra = inb(iobase + IRCC_LCR_A); | |
1495 | lsr = inb(iobase + IRCC_LSR); | |
527b6af4 | 1496 | |
1da177e4 LT |
1497 | IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir); |
1498 | ||
1499 | if (iir & IRCC_IIR_EOM) { | |
1500 | if (self->io.direction == IO_RECV) | |
80a90589 | 1501 | smsc_ircc_dma_receive_complete(self); |
1da177e4 | 1502 | else |
80a90589 | 1503 | smsc_ircc_dma_xmit_complete(self); |
527b6af4 | 1504 | |
80a90589 | 1505 | smsc_ircc_dma_receive(self); |
1da177e4 LT |
1506 | } |
1507 | ||
1508 | if (iir & IRCC_IIR_ACTIVE_FRAME) { | |
1509 | /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/ | |
1510 | } | |
1511 | ||
1512 | /* Enable interrupts again */ | |
1513 | ||
1514 | register_bank(iobase, 0); | |
98b77773 | 1515 | outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); |
1da177e4 LT |
1516 | |
1517 | irq_ret_unlock: | |
1518 | spin_unlock(&self->lock); | |
1519 | irq_ret: | |
1520 | return ret; | |
1521 | } | |
1522 | ||
1523 | /* | |
7d12e780 | 1524 | * Function irport_interrupt_sir (irq, dev_id) |
1da177e4 LT |
1525 | * |
1526 | * Interrupt handler for SIR modes | |
1527 | */ | |
1528 | static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) | |
1529 | { | |
da0841a0 | 1530 | struct smsc_ircc_cb *self = netdev_priv(dev); |
1da177e4 LT |
1531 | int boguscount = 0; |
1532 | int iobase; | |
1533 | int iir, lsr; | |
1534 | ||
1535 | /* Already locked comming here in smsc_ircc_interrupt() */ | |
1536 | /*spin_lock(&self->lock);*/ | |
1537 | ||
1538 | iobase = self->io.sir_base; | |
1539 | ||
98b77773 | 1540 | iir = inb(iobase + UART_IIR) & UART_IIR_ID; |
1da177e4 LT |
1541 | if (iir == 0) |
1542 | return IRQ_NONE; | |
1543 | while (iir) { | |
1544 | /* Clear interrupt */ | |
98b77773 | 1545 | lsr = inb(iobase + UART_LSR); |
1da177e4 | 1546 | |
527b6af4 | 1547 | IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", |
1da177e4 LT |
1548 | __FUNCTION__, iir, lsr, iobase); |
1549 | ||
1550 | switch (iir) { | |
1551 | case UART_IIR_RLSI: | |
1552 | IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__); | |
1553 | break; | |
1554 | case UART_IIR_RDI: | |
1555 | /* Receive interrupt */ | |
1556 | smsc_ircc_sir_receive(self); | |
1557 | break; | |
1558 | case UART_IIR_THRI: | |
1559 | if (lsr & UART_LSR_THRE) | |
1560 | /* Transmitter ready for data */ | |
1561 | smsc_ircc_sir_write_wakeup(self); | |
1562 | break; | |
1563 | default: | |
1564 | IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n", | |
1565 | __FUNCTION__, iir); | |
1566 | break; | |
527b6af4 DT |
1567 | } |
1568 | ||
1da177e4 LT |
1569 | /* Make sure we don't stay here to long */ |
1570 | if (boguscount++ > 100) | |
1571 | break; | |
1572 | ||
527b6af4 | 1573 | iir = inb(iobase + UART_IIR) & UART_IIR_ID; |
1da177e4 LT |
1574 | } |
1575 | /*spin_unlock(&self->lock);*/ | |
1576 | return IRQ_HANDLED; | |
1577 | } | |
1578 | ||
1579 | ||
1580 | #if 0 /* unused */ | |
1581 | /* | |
1582 | * Function ircc_is_receiving (self) | |
1583 | * | |
1584 | * Return TRUE is we are currently receiving a frame | |
1585 | * | |
1586 | */ | |
1587 | static int ircc_is_receiving(struct smsc_ircc_cb *self) | |
1588 | { | |
1589 | int status = FALSE; | |
1590 | /* int iobase; */ | |
1591 | ||
1592 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
1593 | ||
1594 | IRDA_ASSERT(self != NULL, return FALSE;); | |
1595 | ||
1596 | IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__, | |
1597 | get_dma_residue(self->io.dma)); | |
1598 | ||
1599 | status = (self->rx_buff.state != OUTSIDE_FRAME); | |
527b6af4 | 1600 | |
1da177e4 LT |
1601 | return status; |
1602 | } | |
1603 | #endif /* unused */ | |
1604 | ||
e812cb52 DT |
1605 | static int smsc_ircc_request_irq(struct smsc_ircc_cb *self) |
1606 | { | |
1607 | int error; | |
1608 | ||
1609 | error = request_irq(self->io.irq, smsc_ircc_interrupt, 0, | |
1610 | self->netdev->name, self->netdev); | |
1611 | if (error) | |
1612 | IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n", | |
1613 | __FUNCTION__, self->io.irq, error); | |
1614 | ||
1615 | return error; | |
1616 | } | |
1617 | ||
1618 | static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self) | |
1619 | { | |
1620 | unsigned long flags; | |
1621 | ||
1622 | spin_lock_irqsave(&self->lock, flags); | |
1623 | ||
1624 | self->io.speed = 0; | |
1625 | smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); | |
1626 | ||
1627 | spin_unlock_irqrestore(&self->lock, flags); | |
1628 | } | |
1629 | ||
1630 | static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self) | |
1631 | { | |
1632 | int iobase = self->io.fir_base; | |
1633 | unsigned long flags; | |
1634 | ||
1635 | spin_lock_irqsave(&self->lock, flags); | |
1636 | ||
1637 | register_bank(iobase, 0); | |
1638 | outb(0, iobase + IRCC_IER); | |
1639 | outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); | |
1640 | outb(0x00, iobase + IRCC_MASTER); | |
1641 | ||
1642 | spin_unlock_irqrestore(&self->lock, flags); | |
1643 | } | |
1644 | ||
1da177e4 LT |
1645 | |
1646 | /* | |
1647 | * Function smsc_ircc_net_open (dev) | |
1648 | * | |
1649 | * Start the device | |
1650 | * | |
1651 | */ | |
1652 | static int smsc_ircc_net_open(struct net_device *dev) | |
1653 | { | |
1654 | struct smsc_ircc_cb *self; | |
1da177e4 | 1655 | char hwname[16]; |
1da177e4 LT |
1656 | |
1657 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
527b6af4 | 1658 | |
1da177e4 | 1659 | IRDA_ASSERT(dev != NULL, return -1;); |
da0841a0 | 1660 | self = netdev_priv(dev); |
1da177e4 | 1661 | IRDA_ASSERT(self != NULL, return 0;); |
527b6af4 | 1662 | |
e812cb52 DT |
1663 | if (self->io.suspended) { |
1664 | IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__); | |
1665 | return -EAGAIN; | |
1666 | } | |
1667 | ||
527b6af4 | 1668 | if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name, |
1da177e4 LT |
1669 | (void *) dev)) { |
1670 | IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n", | |
1671 | __FUNCTION__, self->io.irq); | |
1672 | return -EAGAIN; | |
1673 | } | |
1674 | ||
e812cb52 | 1675 | smsc_ircc_start_interrupts(self); |
527b6af4 | 1676 | |
1da177e4 LT |
1677 | /* Give self a hardware name */ |
1678 | /* It would be cool to offer the chip revision here - Jean II */ | |
1679 | sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base); | |
1680 | ||
527b6af4 | 1681 | /* |
1da177e4 | 1682 | * Open new IrLAP layer instance, now that everything should be |
527b6af4 | 1683 | * initialized properly |
1da177e4 LT |
1684 | */ |
1685 | self->irlap = irlap_open(dev, &self->qos, hwname); | |
1686 | ||
1687 | /* | |
1688 | * Always allocate the DMA channel after the IRQ, | |
1689 | * and clean up on failure. | |
1690 | */ | |
1691 | if (request_dma(self->io.dma, dev->name)) { | |
1692 | smsc_ircc_net_close(dev); | |
1693 | ||
1694 | IRDA_WARNING("%s(), unable to allocate DMA=%d\n", | |
1695 | __FUNCTION__, self->io.dma); | |
1696 | return -EAGAIN; | |
1697 | } | |
527b6af4 | 1698 | |
1da177e4 LT |
1699 | netif_start_queue(dev); |
1700 | ||
1701 | return 0; | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * Function smsc_ircc_net_close (dev) | |
1706 | * | |
1707 | * Stop the device | |
1708 | * | |
1709 | */ | |
1710 | static int smsc_ircc_net_close(struct net_device *dev) | |
1711 | { | |
1712 | struct smsc_ircc_cb *self; | |
1da177e4 LT |
1713 | |
1714 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
527b6af4 | 1715 | |
1da177e4 | 1716 | IRDA_ASSERT(dev != NULL, return -1;); |
da0841a0 | 1717 | self = netdev_priv(dev); |
1da177e4 | 1718 | IRDA_ASSERT(self != NULL, return 0;); |
527b6af4 | 1719 | |
1da177e4 LT |
1720 | /* Stop device */ |
1721 | netif_stop_queue(dev); | |
527b6af4 | 1722 | |
1da177e4 LT |
1723 | /* Stop and remove instance of IrLAP */ |
1724 | if (self->irlap) | |
1725 | irlap_close(self->irlap); | |
1726 | self->irlap = NULL; | |
1727 | ||
e812cb52 DT |
1728 | smsc_ircc_stop_interrupts(self); |
1729 | ||
1730 | /* if we are called from smsc_ircc_resume we don't have IRQ reserved */ | |
1731 | if (!self->io.suspended) | |
1732 | free_irq(self->io.irq, dev); | |
1733 | ||
1da177e4 | 1734 | disable_dma(self->io.dma); |
1da177e4 LT |
1735 | free_dma(self->io.dma); |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
3ae5eaec | 1740 | static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1741 | { |
3ae5eaec | 1742 | struct smsc_ircc_cb *self = platform_get_drvdata(dev); |
6bb3b2cd | 1743 | |
9480e307 | 1744 | if (!self->io.suspended) { |
e812cb52 DT |
1745 | IRDA_DEBUG(1, "%s, Suspending\n", driver_name); |
1746 | ||
1747 | rtnl_lock(); | |
1748 | if (netif_running(self->netdev)) { | |
1749 | netif_device_detach(self->netdev); | |
1750 | smsc_ircc_stop_interrupts(self); | |
1751 | free_irq(self->io.irq, self->netdev); | |
1752 | disable_dma(self->io.dma); | |
1753 | } | |
98b77773 | 1754 | self->io.suspended = 1; |
e812cb52 | 1755 | rtnl_unlock(); |
98b77773 | 1756 | } |
6bb3b2cd DT |
1757 | |
1758 | return 0; | |
1da177e4 LT |
1759 | } |
1760 | ||
3ae5eaec | 1761 | static int smsc_ircc_resume(struct platform_device *dev) |
1da177e4 | 1762 | { |
3ae5eaec | 1763 | struct smsc_ircc_cb *self = platform_get_drvdata(dev); |
1da177e4 | 1764 | |
9480e307 | 1765 | if (self->io.suspended) { |
e812cb52 DT |
1766 | IRDA_DEBUG(1, "%s, Waking up\n", driver_name); |
1767 | ||
1768 | rtnl_lock(); | |
1769 | smsc_ircc_init_chip(self); | |
1770 | if (netif_running(self->netdev)) { | |
1771 | if (smsc_ircc_request_irq(self)) { | |
1772 | /* | |
1773 | * Don't fail resume process, just kill this | |
1774 | * network interface | |
1775 | */ | |
1776 | unregister_netdevice(self->netdev); | |
1777 | } else { | |
1778 | enable_dma(self->io.dma); | |
1779 | smsc_ircc_start_interrupts(self); | |
1780 | netif_device_attach(self->netdev); | |
1781 | } | |
1782 | } | |
6bb3b2cd | 1783 | self->io.suspended = 0; |
e812cb52 | 1784 | rtnl_unlock(); |
6bb3b2cd | 1785 | } |
1da177e4 LT |
1786 | return 0; |
1787 | } | |
1788 | ||
1789 | /* | |
1790 | * Function smsc_ircc_close (self) | |
1791 | * | |
1792 | * Close driver instance | |
1793 | * | |
1794 | */ | |
1795 | static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) | |
1796 | { | |
1da177e4 LT |
1797 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
1798 | ||
1799 | IRDA_ASSERT(self != NULL, return -1;); | |
1800 | ||
6bb3b2cd | 1801 | platform_device_unregister(self->pldev); |
1da177e4 LT |
1802 | |
1803 | /* Remove netdevice */ | |
1804 | unregister_netdev(self->netdev); | |
1805 | ||
e812cb52 | 1806 | smsc_ircc_stop_interrupts(self); |
1da177e4 LT |
1807 | |
1808 | /* Release the PORTS that this driver is using */ | |
1809 | IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, | |
1810 | self->io.fir_base); | |
1811 | ||
1812 | release_region(self->io.fir_base, self->io.fir_ext); | |
1813 | ||
527b6af4 | 1814 | IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, |
1da177e4 LT |
1815 | self->io.sir_base); |
1816 | ||
1817 | release_region(self->io.sir_base, self->io.sir_ext); | |
1818 | ||
1819 | if (self->tx_buff.head) | |
1820 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
1821 | self->tx_buff.head, self->tx_buff_dma); | |
527b6af4 | 1822 | |
1da177e4 LT |
1823 | if (self->rx_buff.head) |
1824 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
1825 | self->rx_buff.head, self->rx_buff_dma); | |
1826 | ||
1827 | free_netdev(self->netdev); | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
1832 | static void __exit smsc_ircc_cleanup(void) | |
1833 | { | |
1834 | int i; | |
1835 | ||
1836 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
1837 | ||
98b77773 | 1838 | for (i = 0; i < 2; i++) { |
1da177e4 LT |
1839 | if (dev_self[i]) |
1840 | smsc_ircc_close(dev_self[i]); | |
1841 | } | |
6bb3b2cd | 1842 | |
3ae5eaec | 1843 | platform_driver_unregister(&smsc_ircc_driver); |
1da177e4 LT |
1844 | } |
1845 | ||
1846 | /* | |
1847 | * Start SIR operations | |
1848 | * | |
1849 | * This function *must* be called with spinlock held, because it may | |
1850 | * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II | |
1851 | */ | |
1852 | void smsc_ircc_sir_start(struct smsc_ircc_cb *self) | |
1853 | { | |
1854 | struct net_device *dev; | |
1855 | int fir_base, sir_base; | |
1856 | ||
1857 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); | |
1858 | ||
527b6af4 | 1859 | IRDA_ASSERT(self != NULL, return;); |
98b77773 | 1860 | dev = self->netdev; |
527b6af4 | 1861 | IRDA_ASSERT(dev != NULL, return;); |
1da177e4 LT |
1862 | dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir; |
1863 | ||
1864 | fir_base = self->io.fir_base; | |
1865 | sir_base = self->io.sir_base; | |
1866 | ||
1867 | /* Reset everything */ | |
98b77773 | 1868 | outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); |
1da177e4 LT |
1869 | |
1870 | #if SMSC_IRCC2_C_SIR_STOP | |
1871 | /*smsc_ircc_sir_stop(self);*/ | |
1872 | #endif | |
1873 | ||
1874 | register_bank(fir_base, 1); | |
98b77773 | 1875 | outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); |
1da177e4 LT |
1876 | |
1877 | /* Initialize UART */ | |
98b77773 DT |
1878 | outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ |
1879 | outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); | |
527b6af4 | 1880 | |
1da177e4 | 1881 | /* Turn on interrups */ |
98b77773 | 1882 | outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); |
1da177e4 LT |
1883 | |
1884 | IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__); | |
1885 | ||
98b77773 | 1886 | outb(0x00, fir_base + IRCC_MASTER); |
1da177e4 LT |
1887 | } |
1888 | ||
1889 | #if SMSC_IRCC2_C_SIR_STOP | |
1890 | void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) | |
1891 | { | |
1892 | int iobase; | |
1893 | ||
1894 | IRDA_DEBUG(3, "%s\n", __FUNCTION__); | |
1895 | iobase = self->io.sir_base; | |
1896 | ||
1897 | /* Reset UART */ | |
98b77773 | 1898 | outb(0, iobase + UART_MCR); |
527b6af4 | 1899 | |
1da177e4 | 1900 | /* Turn off interrupts */ |
98b77773 | 1901 | outb(0, iobase + UART_IER); |
1da177e4 LT |
1902 | } |
1903 | #endif | |
1904 | ||
1905 | /* | |
1906 | * Function smsc_sir_write_wakeup (self) | |
1907 | * | |
1908 | * Called by the SIR interrupt handler when there's room for more data. | |
1909 | * If we have more packets to send, we send them here. | |
1910 | * | |
1911 | */ | |
1912 | static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) | |
1913 | { | |
1914 | int actual = 0; | |
1915 | int iobase; | |
1916 | int fcr; | |
1917 | ||
1918 | IRDA_ASSERT(self != NULL, return;); | |
1919 | ||
1920 | IRDA_DEBUG(4, "%s\n", __FUNCTION__); | |
1921 | ||
1922 | iobase = self->io.sir_base; | |
1923 | ||
1924 | /* Finished with frame? */ | |
1925 | if (self->tx_buff.len > 0) { | |
1926 | /* Write data left in transmit buffer */ | |
527b6af4 | 1927 | actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, |
1da177e4 LT |
1928 | self->tx_buff.data, self->tx_buff.len); |
1929 | self->tx_buff.data += actual; | |
1930 | self->tx_buff.len -= actual; | |
1931 | } else { | |
527b6af4 | 1932 | |
1da177e4 | 1933 | /*if (self->tx_buff.len ==0) {*/ |
527b6af4 DT |
1934 | |
1935 | /* | |
1936 | * Now serial buffer is almost free & we can start | |
1da177e4 LT |
1937 | * transmission of another packet. But first we must check |
1938 | * if we need to change the speed of the hardware | |
1939 | */ | |
1940 | if (self->new_speed) { | |
1941 | IRDA_DEBUG(5, "%s(), Changing speed to %d.\n", | |
1942 | __FUNCTION__, self->new_speed); | |
1943 | smsc_ircc_sir_wait_hw_transmitter_finish(self); | |
1944 | smsc_ircc_change_speed(self, self->new_speed); | |
1945 | self->new_speed = 0; | |
1946 | } else { | |
1947 | /* Tell network layer that we want more frames */ | |
1948 | netif_wake_queue(self->netdev); | |
1949 | } | |
1950 | self->stats.tx_packets++; | |
1951 | ||
98b77773 DT |
1952 | if (self->io.speed <= 115200) { |
1953 | /* | |
1954 | * Reset Rx FIFO to make sure that all reflected transmit data | |
1955 | * is discarded. This is needed for half duplex operation | |
1956 | */ | |
1957 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; | |
1958 | fcr |= self->io.speed < 38400 ? | |
1959 | UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; | |
1da177e4 | 1960 | |
98b77773 | 1961 | outb(fcr, iobase + UART_FCR); |
1da177e4 | 1962 | |
98b77773 DT |
1963 | /* Turn on receive interrupts */ |
1964 | outb(UART_IER_RDI, iobase + UART_IER); | |
1da177e4 LT |
1965 | } |
1966 | } | |
1967 | } | |
1968 | ||
1969 | /* | |
1970 | * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len) | |
1971 | * | |
1972 | * Fill Tx FIFO with transmit data | |
1973 | * | |
1974 | */ | |
1975 | static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) | |
1976 | { | |
1977 | int actual = 0; | |
527b6af4 | 1978 | |
1da177e4 | 1979 | /* Tx FIFO should be empty! */ |
98b77773 | 1980 | if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { |
1da177e4 LT |
1981 | IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__); |
1982 | return 0; | |
1983 | } | |
527b6af4 | 1984 | |
1da177e4 | 1985 | /* Fill FIFO with current frame */ |
98b77773 | 1986 | while (fifo_size-- > 0 && actual < len) { |
1da177e4 | 1987 | /* Transmit next byte */ |
98b77773 | 1988 | outb(buf[actual], iobase + UART_TX); |
1da177e4 LT |
1989 | actual++; |
1990 | } | |
1991 | return actual; | |
1992 | } | |
1993 | ||
1994 | /* | |
1995 | * Function smsc_ircc_is_receiving (self) | |
1996 | * | |
1997 | * Returns true is we are currently receiving data | |
1998 | * | |
1999 | */ | |
2000 | static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self) | |
2001 | { | |
2002 | return (self->rx_buff.state != OUTSIDE_FRAME); | |
2003 | } | |
2004 | ||
2005 | ||
2006 | /* | |
2007 | * Function smsc_ircc_probe_transceiver(self) | |
2008 | * | |
2009 | * Tries to find the used Transceiver | |
2010 | * | |
2011 | */ | |
2012 | static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) | |
2013 | { | |
2014 | unsigned int i; | |
527b6af4 | 2015 | |
1da177e4 | 2016 | IRDA_ASSERT(self != NULL, return;); |
527b6af4 | 2017 | |
98b77773 DT |
2018 | for (i = 0; smsc_transceivers[i].name != NULL; i++) |
2019 | if (smsc_transceivers[i].probe(self->io.fir_base)) { | |
1da177e4 LT |
2020 | IRDA_MESSAGE(" %s transceiver found\n", |
2021 | smsc_transceivers[i].name); | |
98b77773 | 2022 | self->transceiver= i + 1; |
1da177e4 LT |
2023 | return; |
2024 | } | |
98b77773 | 2025 | |
1da177e4 LT |
2026 | IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", |
2027 | smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); | |
527b6af4 | 2028 | |
98b77773 | 2029 | self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; |
1da177e4 LT |
2030 | } |
2031 | ||
2032 | ||
2033 | /* | |
2034 | * Function smsc_ircc_set_transceiver_for_speed(self, speed) | |
2035 | * | |
2036 | * Set the transceiver according to the speed | |
2037 | * | |
2038 | */ | |
2039 | static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed) | |
2040 | { | |
2041 | unsigned int trx; | |
527b6af4 | 2042 | |
1da177e4 | 2043 | trx = self->transceiver; |
98b77773 DT |
2044 | if (trx > 0) |
2045 | smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); | |
1da177e4 LT |
2046 | } |
2047 | ||
2048 | /* | |
2049 | * Function smsc_ircc_wait_hw_transmitter_finish () | |
2050 | * | |
2051 | * Wait for the real end of HW transmission | |
2052 | * | |
2053 | * The UART is a strict FIFO, and we get called only when we have finished | |
2054 | * pushing data to the FIFO, so the maximum amount of time we must wait | |
2055 | * is only for the FIFO to drain out. | |
2056 | * | |
2057 | * We use a simple calibrated loop. We may need to adjust the loop | |
2058 | * delay (udelay) to balance I/O traffic and latency. And we also need to | |
2059 | * adjust the maximum timeout. | |
2060 | * It would probably be better to wait for the proper interrupt, | |
2061 | * but it doesn't seem to be available. | |
2062 | * | |
2063 | * We can't use jiffies or kernel timers because : | |
2064 | * 1) We are called from the interrupt handler, which disable softirqs, | |
2065 | * so jiffies won't be increased | |
2066 | * 2) Jiffies granularity is usually very coarse (10ms), and we don't | |
2067 | * want to wait that long to detect stuck hardware. | |
2068 | * Jean II | |
2069 | */ | |
2070 | ||
2071 | static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) | |
2072 | { | |
98b77773 | 2073 | int iobase = self->io.sir_base; |
1da177e4 | 2074 | int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; |
527b6af4 | 2075 | |
1da177e4 | 2076 | /* Calibrated busy loop */ |
98b77773 | 2077 | while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) |
1da177e4 LT |
2078 | udelay(1); |
2079 | ||
98b77773 | 2080 | if (count == 0) |
1da177e4 LT |
2081 | IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__); |
2082 | } | |
2083 | ||
2084 | ||
2085 | /* PROBING | |
2086 | * | |
d94c77b9 DB |
2087 | * REVISIT we can be told about the device by PNP, and should use that info |
2088 | * instead of probing hardware and creating a platform_device ... | |
1da177e4 LT |
2089 | */ |
2090 | ||
2091 | static int __init smsc_ircc_look_for_chips(void) | |
2092 | { | |
b6158d23 | 2093 | struct smsc_chip_address *address; |
98b77773 | 2094 | char *type; |
1da177e4 | 2095 | unsigned int cfg_base, found; |
527b6af4 | 2096 | |
1da177e4 LT |
2097 | found = 0; |
2098 | address = possible_addresses; | |
527b6af4 | 2099 | |
98b77773 | 2100 | while (address->cfg_base) { |
1da177e4 | 2101 | cfg_base = address->cfg_base; |
527b6af4 | 2102 | |
1da177e4 | 2103 | /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/ |
527b6af4 | 2104 | |
98b77773 | 2105 | if (address->type & SMSCSIO_TYPE_FDC) { |
1da177e4 | 2106 | type = "FDC"; |
98b77773 DT |
2107 | if (address->type & SMSCSIO_TYPE_FLAT) |
2108 | if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) | |
2109 | found++; | |
2110 | ||
2111 | if (address->type & SMSCSIO_TYPE_PAGED) | |
2112 | if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) | |
2113 | found++; | |
1da177e4 | 2114 | } |
98b77773 | 2115 | if (address->type & SMSCSIO_TYPE_LPC) { |
1da177e4 | 2116 | type = "LPC"; |
98b77773 DT |
2117 | if (address->type & SMSCSIO_TYPE_FLAT) |
2118 | if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) | |
2119 | found++; | |
2120 | ||
2121 | if (address->type & SMSCSIO_TYPE_PAGED) | |
2122 | if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) | |
2123 | found++; | |
1da177e4 LT |
2124 | } |
2125 | address++; | |
2126 | } | |
2127 | return found; | |
527b6af4 | 2128 | } |
1da177e4 LT |
2129 | |
2130 | /* | |
2131 | * Function smsc_superio_flat (chip, base, type) | |
2132 | * | |
2133 | * Try to get configuration of a smc SuperIO chip with flat register model | |
2134 | * | |
2135 | */ | |
b6158d23 | 2136 | static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type) |
1da177e4 LT |
2137 | { |
2138 | unsigned short firbase, sirbase; | |
2139 | u8 mode, dma, irq; | |
2140 | int ret = -ENODEV; | |
2141 | ||
2142 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
2143 | ||
98b77773 | 2144 | if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) |
1da177e4 LT |
2145 | return ret; |
2146 | ||
2147 | outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); | |
98b77773 | 2148 | mode = inb(cfgbase + 1); |
527b6af4 | 2149 | |
1da177e4 | 2150 | /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/ |
527b6af4 | 2151 | |
98b77773 | 2152 | if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) |
1da177e4 LT |
2153 | IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__); |
2154 | ||
2155 | outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); | |
98b77773 | 2156 | sirbase = inb(cfgbase + 1) << 2; |
1da177e4 | 2157 | |
527b6af4 | 2158 | /* FIR iobase */ |
1da177e4 | 2159 | outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); |
98b77773 | 2160 | firbase = inb(cfgbase + 1) << 3; |
1da177e4 LT |
2161 | |
2162 | /* DMA */ | |
2163 | outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); | |
98b77773 | 2164 | dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; |
527b6af4 | 2165 | |
1da177e4 LT |
2166 | /* IRQ */ |
2167 | outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); | |
98b77773 | 2168 | irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; |
1da177e4 LT |
2169 | |
2170 | IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode); | |
2171 | ||
98b77773 DT |
2172 | if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) |
2173 | ret = 0; | |
527b6af4 | 2174 | |
1da177e4 LT |
2175 | /* Exit configuration */ |
2176 | outb(SMSCSIO_CFGEXITKEY, cfgbase); | |
2177 | ||
2178 | return ret; | |
2179 | } | |
2180 | ||
2181 | /* | |
2182 | * Function smsc_superio_paged (chip, base, type) | |
2183 | * | |
2184 | * Try to get configuration of a smc SuperIO chip with paged register model | |
2185 | * | |
2186 | */ | |
b6158d23 | 2187 | static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type) |
1da177e4 LT |
2188 | { |
2189 | unsigned short fir_io, sir_io; | |
2190 | int ret = -ENODEV; | |
527b6af4 | 2191 | |
1da177e4 LT |
2192 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); |
2193 | ||
98b77773 | 2194 | if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) |
1da177e4 | 2195 | return ret; |
527b6af4 | 2196 | |
1da177e4 LT |
2197 | /* Select logical device (UART2) */ |
2198 | outb(0x07, cfg_base); | |
2199 | outb(0x05, cfg_base + 1); | |
527b6af4 | 2200 | |
1da177e4 LT |
2201 | /* SIR iobase */ |
2202 | outb(0x60, cfg_base); | |
98b77773 | 2203 | sir_io = inb(cfg_base + 1) << 8; |
1da177e4 LT |
2204 | outb(0x61, cfg_base); |
2205 | sir_io |= inb(cfg_base + 1); | |
527b6af4 | 2206 | |
1da177e4 LT |
2207 | /* Read FIR base */ |
2208 | outb(0x62, cfg_base); | |
2209 | fir_io = inb(cfg_base + 1) << 8; | |
2210 | outb(0x63, cfg_base); | |
2211 | fir_io |= inb(cfg_base + 1); | |
2212 | outb(0x2b, cfg_base); /* ??? */ | |
2213 | ||
98b77773 DT |
2214 | if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) |
2215 | ret = 0; | |
527b6af4 | 2216 | |
1da177e4 LT |
2217 | /* Exit configuration */ |
2218 | outb(SMSCSIO_CFGEXITKEY, cfg_base); | |
2219 | ||
2220 | return ret; | |
2221 | } | |
2222 | ||
2223 | ||
98b77773 | 2224 | static int __init smsc_access(unsigned short cfg_base, unsigned char reg) |
1da177e4 LT |
2225 | { |
2226 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
2227 | ||
2228 | outb(reg, cfg_base); | |
98b77773 | 2229 | return inb(cfg_base) != reg ? -1 : 0; |
1da177e4 LT |
2230 | } |
2231 | ||
b6158d23 | 2232 | static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type) |
1da177e4 | 2233 | { |
98b77773 | 2234 | u8 devid, xdevid, rev; |
1da177e4 LT |
2235 | |
2236 | IRDA_DEBUG(1, "%s\n", __FUNCTION__); | |
2237 | ||
2238 | /* Leave configuration */ | |
2239 | ||
2240 | outb(SMSCSIO_CFGEXITKEY, cfg_base); | |
2241 | ||
2242 | if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ | |
2243 | return NULL; | |
2244 | ||
2245 | outb(reg, cfg_base); | |
2246 | ||
98b77773 | 2247 | xdevid = inb(cfg_base + 1); |
1da177e4 LT |
2248 | |
2249 | /* Enter configuration */ | |
2250 | ||
2251 | outb(SMSCSIO_CFGACCESSKEY, cfg_base); | |
2252 | ||
2253 | #if 0 | |
2254 | if (smsc_access(cfg_base,0x55)) /* send second key and check */ | |
2255 | return NULL; | |
2256 | #endif | |
527b6af4 | 2257 | |
1da177e4 LT |
2258 | /* probe device ID */ |
2259 | ||
98b77773 | 2260 | if (smsc_access(cfg_base, reg)) |
1da177e4 LT |
2261 | return NULL; |
2262 | ||
98b77773 | 2263 | devid = inb(cfg_base + 1); |
527b6af4 | 2264 | |
98b77773 | 2265 | if (devid == 0 || devid == 0xff) /* typical values for unused port */ |
1da177e4 LT |
2266 | return NULL; |
2267 | ||
2268 | /* probe revision ID */ | |
2269 | ||
98b77773 | 2270 | if (smsc_access(cfg_base, reg + 1)) |
1da177e4 LT |
2271 | return NULL; |
2272 | ||
98b77773 | 2273 | rev = inb(cfg_base + 1); |
1da177e4 | 2274 | |
98b77773 | 2275 | if (rev >= 128) /* i think this will make no sense */ |
1da177e4 LT |
2276 | return NULL; |
2277 | ||
98b77773 | 2278 | if (devid == xdevid) /* protection against false positives */ |
1da177e4 LT |
2279 | return NULL; |
2280 | ||
2281 | /* Check for expected device ID; are there others? */ | |
2282 | ||
98b77773 | 2283 | while (chip->devid != devid) { |
1da177e4 LT |
2284 | |
2285 | chip++; | |
2286 | ||
98b77773 | 2287 | if (chip->name == NULL) |
1da177e4 LT |
2288 | return NULL; |
2289 | } | |
2290 | ||
98b77773 DT |
2291 | IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", |
2292 | devid, rev, cfg_base, type, chip->name); | |
1da177e4 | 2293 | |
98b77773 | 2294 | if (chip->rev > rev) { |
527b6af4 | 2295 | IRDA_MESSAGE("Revision higher than expected\n"); |
1da177e4 LT |
2296 | return NULL; |
2297 | } | |
527b6af4 | 2298 | |
98b77773 | 2299 | if (chip->flags & NoIRDA) |
1da177e4 LT |
2300 | IRDA_MESSAGE("chipset does not support IRDA\n"); |
2301 | ||
2302 | return chip; | |
2303 | } | |
2304 | ||
2305 | static int __init smsc_superio_fdc(unsigned short cfg_base) | |
2306 | { | |
2307 | int ret = -1; | |
2308 | ||
2309 | if (!request_region(cfg_base, 2, driver_name)) { | |
2310 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", | |
2311 | __FUNCTION__, cfg_base); | |
2312 | } else { | |
98b77773 DT |
2313 | if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || |
2314 | !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) | |
1da177e4 LT |
2315 | ret = 0; |
2316 | ||
2317 | release_region(cfg_base, 2); | |
2318 | } | |
2319 | ||
2320 | return ret; | |
2321 | } | |
2322 | ||
2323 | static int __init smsc_superio_lpc(unsigned short cfg_base) | |
2324 | { | |
2325 | int ret = -1; | |
2326 | ||
2327 | if (!request_region(cfg_base, 2, driver_name)) { | |
2328 | IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", | |
2329 | __FUNCTION__, cfg_base); | |
2330 | } else { | |
98b77773 DT |
2331 | if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || |
2332 | !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) | |
1da177e4 | 2333 | ret = 0; |
98b77773 | 2334 | |
1da177e4 LT |
2335 | release_region(cfg_base, 2); |
2336 | } | |
2337 | return ret; | |
2338 | } | |
2339 | ||
c1e14a6e LW |
2340 | /* |
2341 | * Look for some specific subsystem setups that need | |
2342 | * pre-configuration not properly done by the BIOS (especially laptops) | |
2343 | * This code is based in part on smcinit.c, tosh1800-smcinit.c | |
2344 | * and tosh2450-smcinit.c. The table lists the device entries | |
08d09997 LW |
2345 | * for ISA bridges with an LPC (Low Pin Count) controller which |
2346 | * handles the communication with the SMSC device. After the LPC | |
2347 | * controller is initialized through PCI, the SMSC device is initialized | |
2348 | * through a dedicated port in the ISA port-mapped I/O area, this latter | |
2349 | * area is used to configure the SMSC device with default | |
2350 | * SIR and FIR I/O ports, DMA and IRQ. Different vendors have | |
2351 | * used different sets of parameters and different control port | |
2352 | * addresses making a subsystem device table necessary. | |
c1e14a6e LW |
2353 | */ |
2354 | #ifdef CONFIG_PCI | |
2355 | #define PCIID_VENDOR_INTEL 0x8086 | |
2356 | #define PCIID_VENDOR_ALI 0x10b9 | |
c5d965ca | 2357 | static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { |
895de090 LWLE |
2358 | /* |
2359 | * Subsystems needing entries: | |
2360 | * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family | |
2361 | * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family | |
2362 | * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family | |
2363 | */ | |
2364 | { | |
2365 | /* Guessed entry */ | |
2366 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2367 | .device = 0x24cc, | |
2368 | .subvendor = 0x103c, | |
2369 | .subdevice = 0x08bc, | |
2370 | .sir_io = 0x02f8, | |
2371 | .fir_io = 0x0130, | |
2372 | .fir_irq = 0x05, | |
2373 | .fir_dma = 0x03, | |
2374 | .cfg_base = 0x004e, | |
2375 | .preconfigure = preconfigure_through_82801, | |
2376 | .name = "HP nx5000 family", | |
2377 | }, | |
c1e14a6e LW |
2378 | { |
2379 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2380 | .device = 0x24cc, | |
2381 | .subvendor = 0x103c, | |
2382 | .subdevice = 0x088c, | |
08d09997 LW |
2383 | /* Quite certain these are the same for nc8000 as for nc6000 */ |
2384 | .sir_io = 0x02f8, | |
c1e14a6e | 2385 | .fir_io = 0x0130, |
08d09997 | 2386 | .fir_irq = 0x05, |
c1e14a6e LW |
2387 | .fir_dma = 0x03, |
2388 | .cfg_base = 0x004e, | |
2389 | .preconfigure = preconfigure_through_82801, | |
895de090 | 2390 | .name = "HP nc8000 family", |
c1e14a6e LW |
2391 | }, |
2392 | { | |
2393 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2394 | .device = 0x24cc, | |
2395 | .subvendor = 0x103c, | |
2396 | .subdevice = 0x0890, | |
2397 | .sir_io = 0x02f8, | |
2398 | .fir_io = 0x0130, | |
08d09997 | 2399 | .fir_irq = 0x05, |
c1e14a6e LW |
2400 | .fir_dma = 0x03, |
2401 | .cfg_base = 0x004e, | |
2402 | .preconfigure = preconfigure_through_82801, | |
895de090 LWLE |
2403 | .name = "HP nc6000 family", |
2404 | }, | |
2405 | { | |
2406 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ | |
2407 | .device = 0x24cc, | |
2408 | .subvendor = 0x0e11, | |
2409 | .subdevice = 0x0860, | |
2410 | /* I assume these are the same for x1000 as for the others */ | |
2411 | .sir_io = 0x02e8, | |
2412 | .fir_io = 0x02f8, | |
2413 | .fir_irq = 0x07, | |
2414 | .fir_dma = 0x03, | |
2415 | .cfg_base = 0x002e, | |
2416 | .preconfigure = preconfigure_through_82801, | |
2417 | .name = "Compaq x1000 family", | |
c1e14a6e LW |
2418 | }, |
2419 | { | |
08d09997 LW |
2420 | /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ |
2421 | .vendor = PCIID_VENDOR_INTEL, | |
c1e14a6e LW |
2422 | .device = 0x24c0, |
2423 | .subvendor = 0x1179, | |
08d09997 | 2424 | .subdevice = 0xffff, /* 0xffff is "any" */ |
c1e14a6e LW |
2425 | .sir_io = 0x03f8, |
2426 | .fir_io = 0x0130, | |
2427 | .fir_irq = 0x07, | |
2428 | .fir_dma = 0x01, | |
2429 | .cfg_base = 0x002e, | |
2430 | .preconfigure = preconfigure_through_82801, | |
08d09997 | 2431 | .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", |
c1e14a6e LW |
2432 | }, |
2433 | { | |
2434 | .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */ | |
08d09997 | 2435 | .device = 0x248c, |
c1e14a6e | 2436 | .subvendor = 0x1179, |
08d09997 | 2437 | .subdevice = 0xffff, /* 0xffff is "any" */ |
c1e14a6e LW |
2438 | .sir_io = 0x03f8, |
2439 | .fir_io = 0x0130, | |
2440 | .fir_irq = 0x03, | |
2441 | .fir_dma = 0x03, | |
2442 | .cfg_base = 0x002e, | |
2443 | .preconfigure = preconfigure_through_82801, | |
08d09997 | 2444 | .name = "Toshiba laptop with Intel 82801CAM ISA bridge", |
c1e14a6e LW |
2445 | }, |
2446 | { | |
08d09997 LW |
2447 | /* 82801DBM (ICH4-M) LPC Interface Bridge */ |
2448 | .vendor = PCIID_VENDOR_INTEL, | |
2449 | .device = 0x24cc, | |
2450 | .subvendor = 0x1179, | |
2451 | .subdevice = 0xffff, /* 0xffff is "any" */ | |
2452 | .sir_io = 0x03f8, | |
2453 | .fir_io = 0x0130, | |
2454 | .fir_irq = 0x03, | |
2455 | .fir_dma = 0x03, | |
2456 | .cfg_base = 0x002e, | |
2457 | .preconfigure = preconfigure_through_82801, | |
2458 | .name = "Toshiba laptop with Intel 8281DBM LPC bridge", | |
2459 | }, | |
2460 | { | |
2461 | /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ | |
2462 | .vendor = PCIID_VENDOR_ALI, | |
c1e14a6e LW |
2463 | .device = 0x1533, |
2464 | .subvendor = 0x1179, | |
08d09997 | 2465 | .subdevice = 0xffff, /* 0xffff is "any" */ |
c1e14a6e LW |
2466 | .sir_io = 0x02e8, |
2467 | .fir_io = 0x02f8, | |
2468 | .fir_irq = 0x07, | |
2469 | .fir_dma = 0x03, | |
2470 | .cfg_base = 0x002e, | |
2471 | .preconfigure = preconfigure_through_ali, | |
08d09997 | 2472 | .name = "Toshiba laptop with ALi ISA bridge", |
c1e14a6e LW |
2473 | }, |
2474 | { } // Terminator | |
2475 | }; | |
2476 | ||
2477 | ||
2478 | /* | |
08d09997 LW |
2479 | * This sets up the basic SMSC parameters |
2480 | * (FIR port, SIR port, FIR DMA, FIR IRQ) | |
c1e14a6e LW |
2481 | * through the chip configuration port. |
2482 | */ | |
08d09997 LW |
2483 | static int __init preconfigure_smsc_chip(struct |
2484 | smsc_ircc_subsystem_configuration | |
2485 | *conf) | |
c1e14a6e LW |
2486 | { |
2487 | unsigned short iobase = conf->cfg_base; | |
2488 | unsigned char tmpbyte; | |
2489 | ||
2490 | outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state | |
2491 | outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID | |
2492 | tmpbyte = inb(iobase +1); // Read device ID | |
08d09997 LW |
2493 | IRDA_DEBUG(0, |
2494 | "Detected Chip id: 0x%02x, setting up registers...\n", | |
2495 | tmpbyte); | |
c1e14a6e LW |
2496 | |
2497 | /* Disable UART1 and set up SIR I/O port */ | |
2498 | outb(0x24, iobase); // select CR24 - UART1 base addr | |
2499 | outb(0x00, iobase + 1); // disable UART1 | |
2500 | outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr | |
2501 | outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 | |
2502 | tmpbyte = inb(iobase + 1); | |
2503 | if (tmpbyte != (conf->sir_io >> 2) ) { | |
2504 | IRDA_WARNING("ERROR: could not configure SIR ioport.\n"); | |
08d09997 | 2505 | IRDA_WARNING("Try to supply ircc_cfg argument.\n"); |
c1e14a6e LW |
2506 | return -ENXIO; |
2507 | } | |
2508 | ||
2509 | /* Set up FIR IRQ channel for UART2 */ | |
2510 | outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select | |
2511 | tmpbyte = inb(iobase + 1); | |
2512 | tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion | |
2513 | tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK); | |
2514 | outb(tmpbyte, iobase + 1); | |
2515 | tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; | |
2516 | if (tmpbyte != conf->fir_irq) { | |
2517 | IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n"); | |
2518 | return -ENXIO; | |
2519 | } | |
2520 | ||
2521 | /* Set up FIR I/O port */ | |
2522 | outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr | |
2523 | outb((conf->fir_io >> 3), iobase + 1); | |
2524 | tmpbyte = inb(iobase + 1); | |
2525 | if (tmpbyte != (conf->fir_io >> 3) ) { | |
2526 | IRDA_WARNING("ERROR: could not configure FIR I/O port.\n"); | |
2527 | return -ENXIO; | |
2528 | } | |
2529 | ||
2530 | /* Set up FIR DMA channel */ | |
2531 | outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select | |
2532 | outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA | |
2533 | tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; | |
2534 | if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) { | |
2535 | IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n"); | |
2536 | return -ENXIO; | |
2537 | } | |
2538 | ||
2539 | outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode | |
2540 | tmpbyte = inb(iobase + 1); | |
08d09997 LW |
2541 | tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | |
2542 | SMSCSIOFLAT_UART2MODE_VAL_IRDA; | |
c1e14a6e LW |
2543 | outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed |
2544 | ||
2545 | outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel | |
2546 | tmpbyte = inb(iobase + 1); | |
2547 | outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down | |
2548 | ||
2549 | /* This one was not part of tosh1800 */ | |
2550 | outb(0x0a, iobase); // CR0a - ecp fifo / ir mux | |
2551 | tmpbyte = inb(iobase + 1); | |
2552 | outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port | |
2553 | ||
2554 | outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power | |
2555 | tmpbyte = inb(iobase + 1); | |
2556 | outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down | |
2557 | ||
2558 | outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle | |
2559 | tmpbyte = inb(iobase + 1); | |
2560 | outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done | |
2561 | ||
2562 | outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration | |
2563 | ||
2564 | return 0; | |
2565 | } | |
2566 | ||
08d09997 | 2567 | /* 82801CAM generic registers */ |
c1e14a6e LW |
2568 | #define VID 0x00 |
2569 | #define DID 0x02 | |
08d09997 LW |
2570 | #define PIRQ_A_D_ROUT 0x60 |
2571 | #define SIRQ_CNTL 0x64 | |
2572 | #define PIRQ_E_H_ROUT 0x68 | |
c1e14a6e | 2573 | #define PCI_DMA_C 0x90 |
08d09997 | 2574 | /* LPC-specific registers */ |
c1e14a6e | 2575 | #define COM_DEC 0xe0 |
08d09997 | 2576 | #define GEN1_DEC 0xe4 |
c1e14a6e LW |
2577 | #define LPC_EN 0xe6 |
2578 | #define GEN2_DEC 0xec | |
2579 | /* | |
08d09997 LW |
2580 | * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge |
2581 | * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. | |
2582 | * They all work the same way! | |
c1e14a6e LW |
2583 | */ |
2584 | static int __init preconfigure_through_82801(struct pci_dev *dev, | |
08d09997 LW |
2585 | struct |
2586 | smsc_ircc_subsystem_configuration | |
2587 | *conf) | |
c1e14a6e LW |
2588 | { |
2589 | unsigned short tmpword; | |
08d09997 | 2590 | unsigned char tmpbyte; |
c1e14a6e | 2591 | |
08d09997 LW |
2592 | IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n"); |
2593 | /* | |
2594 | * Select the range for the COMA COM port (SIR) | |
2595 | * Register COM_DEC: | |
2596 | * Bit 7: reserved | |
2597 | * Bit 6-4, COMB decode range | |
2598 | * Bit 3: reserved | |
2599 | * Bit 2-0, COMA decode range | |
2600 | * | |
2601 | * Decode ranges: | |
2602 | * 000 = 0x3f8-0x3ff (COM1) | |
2603 | * 001 = 0x2f8-0x2ff (COM2) | |
2604 | * 010 = 0x220-0x227 | |
2605 | * 011 = 0x228-0x22f | |
2606 | * 100 = 0x238-0x23f | |
2607 | * 101 = 0x2e8-0x2ef (COM4) | |
2608 | * 110 = 0x338-0x33f | |
2609 | * 111 = 0x3e8-0x3ef (COM3) | |
2610 | */ | |
2611 | pci_read_config_byte(dev, COM_DEC, &tmpbyte); | |
2612 | tmpbyte &= 0xf8; /* mask COMA bits */ | |
2613 | switch(conf->sir_io) { | |
2614 | case 0x3f8: | |
2615 | tmpbyte |= 0x00; | |
2616 | break; | |
2617 | case 0x2f8: | |
2618 | tmpbyte |= 0x01; | |
2619 | break; | |
2620 | case 0x220: | |
2621 | tmpbyte |= 0x02; | |
2622 | break; | |
2623 | case 0x228: | |
2624 | tmpbyte |= 0x03; | |
2625 | break; | |
2626 | case 0x238: | |
2627 | tmpbyte |= 0x04; | |
2628 | break; | |
2629 | case 0x2e8: | |
2630 | tmpbyte |= 0x05; | |
2631 | break; | |
2632 | case 0x338: | |
2633 | tmpbyte |= 0x06; | |
2634 | break; | |
2635 | case 0x3e8: | |
2636 | tmpbyte |= 0x07; | |
2637 | break; | |
2638 | default: | |
2639 | tmpbyte |= 0x01; /* COM2 default */ | |
2640 | } | |
2641 | IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte); | |
2642 | pci_write_config_byte(dev, COM_DEC, tmpbyte); | |
c1e14a6e | 2643 | |
08d09997 LW |
2644 | /* Enable Low Pin Count interface */ |
2645 | pci_read_config_word(dev, LPC_EN, &tmpword); | |
2646 | /* These seem to be set up at all times, | |
2647 | * just make sure it is properly set. | |
2648 | */ | |
2649 | switch(conf->cfg_base) { | |
2650 | case 0x04e: | |
2651 | tmpword |= 0x2000; | |
2652 | break; | |
2653 | case 0x02e: | |
2654 | tmpword |= 0x1000; | |
2655 | break; | |
2656 | case 0x062: | |
2657 | tmpword |= 0x0800; | |
2658 | break; | |
2659 | case 0x060: | |
2660 | tmpword |= 0x0400; | |
2661 | break; | |
2662 | default: | |
2663 | IRDA_WARNING("Uncommon I/O base address: 0x%04x\n", | |
2664 | conf->cfg_base); | |
2665 | break; | |
2666 | } | |
2667 | tmpword &= 0xfffd; /* disable LPC COMB */ | |
2668 | tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ | |
2669 | IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword); | |
c1e14a6e LW |
2670 | pci_write_config_word(dev, LPC_EN, tmpword); |
2671 | ||
08d09997 LW |
2672 | /* |
2673 | * Configure LPC DMA channel | |
2674 | * PCI_DMA_C bits: | |
2675 | * Bit 15-14: DMA channel 7 select | |
2676 | * Bit 13-12: DMA channel 6 select | |
2677 | * Bit 11-10: DMA channel 5 select | |
2678 | * Bit 9-8: Reserved | |
2679 | * Bit 7-6: DMA channel 3 select | |
2680 | * Bit 5-4: DMA channel 2 select | |
2681 | * Bit 3-2: DMA channel 1 select | |
2682 | * Bit 1-0: DMA channel 0 select | |
2683 | * 00 = Reserved value | |
2684 | * 01 = PC/PCI DMA | |
2685 | * 10 = Reserved value | |
2686 | * 11 = LPC I/F DMA | |
2687 | */ | |
2688 | pci_read_config_word(dev, PCI_DMA_C, &tmpword); | |
2689 | switch(conf->fir_dma) { | |
2690 | case 0x07: | |
2691 | tmpword |= 0xc000; | |
2692 | break; | |
2693 | case 0x06: | |
2694 | tmpword |= 0x3000; | |
2695 | break; | |
2696 | case 0x05: | |
2697 | tmpword |= 0x0c00; | |
2698 | break; | |
2699 | case 0x03: | |
2700 | tmpword |= 0x00c0; | |
2701 | break; | |
2702 | case 0x02: | |
2703 | tmpword |= 0x0030; | |
2704 | break; | |
2705 | case 0x01: | |
2706 | tmpword |= 0x000c; | |
2707 | break; | |
2708 | case 0x00: | |
2709 | tmpword |= 0x0003; | |
2710 | break; | |
2711 | default: | |
2712 | break; /* do not change settings */ | |
2713 | } | |
2714 | IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword); | |
2715 | pci_write_config_word(dev, PCI_DMA_C, tmpword); | |
2716 | ||
2717 | /* | |
2718 | * GEN2_DEC bits: | |
2719 | * Bit 15-4: Generic I/O range | |
2720 | * Bit 3-1: reserved (read as 0) | |
2721 | * Bit 0: enable GEN2 range on LPC I/F | |
2722 | */ | |
2723 | tmpword = conf->fir_io & 0xfff8; | |
2724 | tmpword |= 0x0001; | |
2725 | IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword); | |
2726 | pci_write_config_word(dev, GEN2_DEC, tmpword); | |
c1e14a6e LW |
2727 | |
2728 | /* Pre-configure chip */ | |
08d09997 LW |
2729 | return preconfigure_smsc_chip(conf); |
2730 | } | |
c1e14a6e | 2731 | |
08d09997 LW |
2732 | /* |
2733 | * Pre-configure a certain port on the ALi 1533 bridge. | |
2734 | * This is based on reverse-engineering since ALi does not | |
2735 | * provide any data sheet for the 1533 chip. | |
2736 | */ | |
2737 | static void __init preconfigure_ali_port(struct pci_dev *dev, | |
2738 | unsigned short port) | |
2739 | { | |
2740 | unsigned char reg; | |
2741 | /* These bits obviously control the different ports */ | |
2742 | unsigned char mask; | |
2743 | unsigned char tmpbyte; | |
2744 | ||
2745 | switch(port) { | |
2746 | case 0x0130: | |
2747 | case 0x0178: | |
2748 | reg = 0xb0; | |
2749 | mask = 0x80; | |
2750 | break; | |
2751 | case 0x03f8: | |
2752 | reg = 0xb4; | |
2753 | mask = 0x80; | |
2754 | break; | |
2755 | case 0x02f8: | |
2756 | reg = 0xb4; | |
2757 | mask = 0x30; | |
2758 | break; | |
2759 | case 0x02e8: | |
2760 | reg = 0xb4; | |
2761 | mask = 0x08; | |
2762 | break; | |
2763 | default: | |
2764 | IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port); | |
2765 | return; | |
2766 | } | |
2767 | ||
2768 | pci_read_config_byte(dev, reg, &tmpbyte); | |
2769 | /* Turn on the right bits */ | |
2770 | tmpbyte |= mask; | |
2771 | pci_write_config_byte(dev, reg, tmpbyte); | |
2772 | IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port); | |
2773 | return; | |
c1e14a6e LW |
2774 | } |
2775 | ||
2776 | static int __init preconfigure_through_ali(struct pci_dev *dev, | |
08d09997 LW |
2777 | struct |
2778 | smsc_ircc_subsystem_configuration | |
2779 | *conf) | |
c1e14a6e | 2780 | { |
08d09997 LW |
2781 | /* Configure the two ports on the ALi 1533 */ |
2782 | preconfigure_ali_port(dev, conf->sir_io); | |
2783 | preconfigure_ali_port(dev, conf->fir_io); | |
2784 | ||
2785 | /* Pre-configure chip */ | |
2786 | return preconfigure_smsc_chip(conf); | |
c1e14a6e LW |
2787 | } |
2788 | ||
2789 | static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, | |
2790 | unsigned short ircc_fir, | |
2791 | unsigned short ircc_sir, | |
2792 | unsigned char ircc_dma, | |
2793 | unsigned char ircc_irq) | |
2794 | { | |
2795 | struct pci_dev *dev = NULL; | |
2796 | unsigned short ss_vendor = 0x0000; | |
2797 | unsigned short ss_device = 0x0000; | |
2798 | int ret = 0; | |
2799 | ||
2800 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
2801 | ||
2802 | while (dev != NULL) { | |
2803 | struct smsc_ircc_subsystem_configuration *conf; | |
2804 | ||
2805 | /* | |
08d09997 LW |
2806 | * Cache the subsystem vendor/device: |
2807 | * some manufacturers fail to set this for all components, | |
2808 | * so we save it in case there is just 0x0000 0x0000 on the | |
2809 | * device we want to check. | |
c1e14a6e LW |
2810 | */ |
2811 | if (dev->subsystem_vendor != 0x0000U) { | |
2812 | ss_vendor = dev->subsystem_vendor; | |
2813 | ss_device = dev->subsystem_device; | |
2814 | } | |
2815 | conf = subsystem_configurations; | |
2816 | for( ; conf->subvendor; conf++) { | |
2817 | if(conf->vendor == dev->vendor && | |
2818 | conf->device == dev->device && | |
08d09997 LW |
2819 | conf->subvendor == ss_vendor && |
2820 | /* Sometimes these are cached values */ | |
2821 | (conf->subdevice == ss_device || | |
2822 | conf->subdevice == 0xffff)) { | |
2823 | struct smsc_ircc_subsystem_configuration | |
2824 | tmpconf; | |
c1e14a6e | 2825 | |
08d09997 LW |
2826 | memcpy(&tmpconf, conf, |
2827 | sizeof(struct smsc_ircc_subsystem_configuration)); | |
c1e14a6e | 2828 | |
08d09997 LW |
2829 | /* |
2830 | * Override the default values with anything | |
2831 | * passed in as parameter | |
2832 | */ | |
c1e14a6e LW |
2833 | if (ircc_cfg != 0) |
2834 | tmpconf.cfg_base = ircc_cfg; | |
2835 | if (ircc_fir != 0) | |
2836 | tmpconf.fir_io = ircc_fir; | |
2837 | if (ircc_sir != 0) | |
2838 | tmpconf.sir_io = ircc_sir; | |
2839 | if (ircc_dma != 0xff) | |
2840 | tmpconf.fir_dma = ircc_dma; | |
2841 | if (ircc_irq != 0xff) | |
2842 | tmpconf.fir_irq = ircc_irq; | |
2843 | ||
2844 | IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name); | |
2845 | if (conf->preconfigure) | |
2846 | ret = conf->preconfigure(dev, &tmpconf); | |
2847 | else | |
2848 | ret = -ENODEV; | |
2849 | } | |
2850 | } | |
2851 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
2852 | } | |
2853 | ||
2854 | return ret; | |
2855 | } | |
2856 | #endif // CONFIG_PCI | |
2857 | ||
1da177e4 LT |
2858 | /************************************************ |
2859 | * | |
2860 | * Transceivers specific functions | |
2861 | * | |
2862 | ************************************************/ | |
2863 | ||
2864 | ||
2865 | /* | |
2866 | * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed) | |
2867 | * | |
2868 | * Program transceiver through smsc-ircc ATC circuitry | |
2869 | * | |
2870 | */ | |
2871 | ||
2872 | static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) | |
2873 | { | |
2874 | unsigned long jiffies_now, jiffies_timeout; | |
98b77773 | 2875 | u8 val; |
527b6af4 | 2876 | |
98b77773 DT |
2877 | jiffies_now = jiffies; |
2878 | jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; | |
527b6af4 | 2879 | |
1da177e4 LT |
2880 | /* ATC */ |
2881 | register_bank(fir_base, 4); | |
98b77773 DT |
2882 | outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, |
2883 | fir_base + IRCC_ATC); | |
2884 | ||
2885 | while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && | |
2886 | !time_after(jiffies, jiffies_timeout)) | |
2887 | /* empty */; | |
2888 | ||
2889 | if (val) | |
1da177e4 | 2890 | IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__, |
98b77773 | 2891 | inb(fir_base + IRCC_ATC)); |
1da177e4 LT |
2892 | } |
2893 | ||
2894 | /* | |
2895 | * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base) | |
2896 | * | |
2897 | * Probe transceiver smsc-ircc ATC circuitry | |
2898 | * | |
2899 | */ | |
2900 | ||
2901 | static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) | |
2902 | { | |
2903 | return 0; | |
2904 | } | |
2905 | ||
2906 | /* | |
2907 | * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed) | |
2908 | * | |
527b6af4 | 2909 | * Set transceiver |
1da177e4 LT |
2910 | * |
2911 | */ | |
2912 | ||
2913 | static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) | |
2914 | { | |
98b77773 | 2915 | u8 fast_mode; |
527b6af4 | 2916 | |
98b77773 DT |
2917 | switch (speed) { |
2918 | default: | |
2919 | case 576000 : | |
527b6af4 | 2920 | fast_mode = 0; |
1da177e4 | 2921 | break; |
98b77773 DT |
2922 | case 1152000 : |
2923 | case 4000000 : | |
1da177e4 LT |
2924 | fast_mode = IRCC_LCR_A_FAST; |
2925 | break; | |
1da177e4 LT |
2926 | } |
2927 | register_bank(fir_base, 0); | |
98b77773 | 2928 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); |
1da177e4 LT |
2929 | } |
2930 | ||
2931 | /* | |
2932 | * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base) | |
2933 | * | |
527b6af4 | 2934 | * Probe transceiver |
1da177e4 LT |
2935 | * |
2936 | */ | |
2937 | ||
2938 | static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) | |
2939 | { | |
2940 | return 0; | |
2941 | } | |
2942 | ||
2943 | /* | |
2944 | * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed) | |
2945 | * | |
527b6af4 | 2946 | * Set transceiver |
1da177e4 LT |
2947 | * |
2948 | */ | |
2949 | ||
2950 | static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) | |
2951 | { | |
98b77773 | 2952 | u8 fast_mode; |
527b6af4 | 2953 | |
98b77773 DT |
2954 | switch (speed) { |
2955 | default: | |
2956 | case 576000 : | |
527b6af4 | 2957 | fast_mode = 0; |
1da177e4 | 2958 | break; |
98b77773 DT |
2959 | case 1152000 : |
2960 | case 4000000 : | |
1da177e4 LT |
2961 | fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; |
2962 | break; | |
527b6af4 | 2963 | |
1da177e4 LT |
2964 | } |
2965 | /* This causes an interrupt */ | |
2966 | register_bank(fir_base, 0); | |
98b77773 | 2967 | outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); |
1da177e4 LT |
2968 | } |
2969 | ||
2970 | /* | |
2971 | * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base) | |
2972 | * | |
527b6af4 | 2973 | * Probe transceiver |
1da177e4 LT |
2974 | * |
2975 | */ | |
2976 | ||
2977 | static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) | |
2978 | { | |
2979 | return 0; | |
2980 | } | |
2981 | ||
2982 | ||
2983 | module_init(smsc_ircc_init); | |
2984 | module_exit(smsc_ircc_cleanup); |