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Merge remote-tracking branch 'regulator/fix/dbx500' into regulator-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4 1/*********************************************************************
1da177e4
LT		 2 *
3 * Description: Driver for the SMC Infrared Communications Controller
1da177e4 4 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 5 * Created at:
6 * Modified at:
7 * Modified by:
8 *
1da177e4
LT		 9 * Copyright (c) 2002 Daniele Peri
10 * All Rights Reserved.
11 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 12 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 13 *
14 *
15 * Based on smc-ircc.c:
16 *
17 * Copyright (c) 2001 Stefani Seibold
18 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 19 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 20 *
21 * and irport.c:
22 *
23 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
24 *
527b6af4
DT		 25 *
26 * This program is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU General Public License as
28 * published by the Free Software Foundation; either version 2 of
1da177e4 29 * the License, or (at your option) any later version.
527b6af4 30 *
1da177e4
LT		 31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
527b6af4
DT		 35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 39 * MA 02111-1307 USA
40 *
41 ********************************************************************/
42
43#include <linux/module.h>
44#include <linux/kernel.h>
45#include <linux/types.h>
46#include <linux/skbuff.h>
47#include <linux/netdevice.h>
48#include <linux/ioport.h>
49#include <linux/delay.h>
1da177e4 50#include <linux/init.h>
a6b7a407 51#include <linux/interrupt.h>
1da177e4
LT		 52#include <linux/rtnetlink.h>
53#include <linux/serial_reg.h>
54#include <linux/dma-mapping.h>
d94c77b9 55#include <linux/pnp.h>
d052d1be 56#include <linux/platform_device.h>
5a0e3ad6 57#include <linux/gfp.h>
1da177e4
LT		 58
59#include <asm/io.h>
60#include <asm/dma.h>
61#include <asm/byteorder.h>
62
63#include <linux/spinlock.h>
64#include <linux/pm.h>
c1e14a6e
LW		 65#ifdef CONFIG_PCI
66#include <linux/pci.h>
67#endif
1da177e4
LT		 68
69#include <net/irda/wrapper.h>
70#include <net/irda/irda.h>
71#include <net/irda/irda_device.h>
72
73#include "smsc-ircc2.h"
74#include "smsc-sio.h"
75
98b77773
DT		 76
77MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79MODULE_LICENSE("GPL");
80
eb939922 81static bool smsc_nopnp = true;
d0d4f69b 82module_param_named(nopnp, smsc_nopnp, bool, 0);
32db9276 83MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
d0d4f69b 84
916f11c7
BH		 85#define DMA_INVAL 255
86static int ircc_dma = DMA_INVAL;
98b77773
DT		 87module_param(ircc_dma, int, 0);
88MODULE_PARM_DESC(ircc_dma, "DMA channel");
89
916f11c7
BH		 90#define IRQ_INVAL 255
91static int ircc_irq = IRQ_INVAL;
98b77773
DT		 92module_param(ircc_irq, int, 0);
93MODULE_PARM_DESC(ircc_irq, "IRQ line");
94
95static int ircc_fir;
96module_param(ircc_fir, int, 0);
97MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
98
99static int ircc_sir;
100module_param(ircc_sir, int, 0);
101MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
102
103static int ircc_cfg;
104module_param(ircc_cfg, int, 0);
105MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
106
107static int ircc_transceiver;
108module_param(ircc_transceiver, int, 0);
109MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
110
1da177e4
LT		 111/* Types */
112
c1e14a6e
LW		 113#ifdef CONFIG_PCI
114struct smsc_ircc_subsystem_configuration {
115 unsigned short vendor; /* PCI vendor ID */
116 unsigned short device; /* PCI vendor ID */
117 unsigned short subvendor; /* PCI subsystem vendor ID */
83cf0a9b 118 unsigned short subdevice; /* PCI subsystem device ID */
c1e14a6e
LW		 119 unsigned short sir_io; /* I/O port for SIR */
120 unsigned short fir_io; /* I/O port for FIR */
121 unsigned char fir_irq; /* FIR IRQ */
122 unsigned char fir_dma; /* FIR DMA */
123 unsigned short cfg_base; /* I/O port for chip configuration */
124 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
125 const char *name; /* name shown as info */
126};
127#endif
128
1da177e4
LT		 129struct smsc_transceiver {
130 char *name;
527b6af4 131 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 132 int (*probe)(int fir_base);
133};
1da177e4
LT		 134
135struct smsc_chip {
136 char *name;
137 #if 0
138 u8 type;
139 #endif
140 u16 flags;
141 u8 devid;
142 u8 rev;
143};
1da177e4
LT		 144
145struct smsc_chip_address {
146 unsigned int cfg_base;
147 unsigned int type;
148};
1da177e4
LT		 149
150/* Private data for each instance */
151struct smsc_ircc_cb {
152 struct net_device *netdev; /* Yes! we are some kind of netdevice */
1da177e4 153 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 154
1da177e4
LT		 155 chipio_t io; /* IrDA controller information */
156 iobuff_t tx_buff; /* Transmit buffer */
157 iobuff_t rx_buff; /* Receive buffer */
158 dma_addr_t tx_buff_dma;
159 dma_addr_t rx_buff_dma;
160
161 struct qos_info qos; /* QoS capabilities for this device */
162
163 spinlock_t lock; /* For serializing operations */
527b6af4 164
1da177e4
LT		 165 __u32 new_speed;
166 __u32 flags; /* Interface flags */
167
168 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
169 int tx_len; /* Number of frames in tx_buff */
170
171 int transceiver;
6bb3b2cd 172 struct platform_device *pldev;
1da177e4
LT		 173};
174
175/* Constants */
176
6bb3b2cd
DT		 177#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
178
1da177e4
LT		 179#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
180#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 181#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 182#define SMSC_IRCC2_C_SIR_STOP 0
183
6bb3b2cd
DT		 184static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
185
1da177e4
LT		 186/* Prototypes */
187
188static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
189static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
190static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
191static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
192static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
193static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 194static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
195static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4 196static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
6518bbb8
SH		 197static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
198 struct net_device *dev);
199static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
200 struct net_device *dev);
80a90589
DT		 201static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 203static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
7d12e780 205static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
1da177e4
LT		 206static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208#if SMSC_IRCC2_C_SIR_STOP
209static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
210#endif
211static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213static int smsc_ircc_net_open(struct net_device *dev);
214static int smsc_ircc_net_close(struct net_device *dev);
215static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216#if SMSC_IRCC2_C_NET_TIMEOUT
217static void smsc_ircc_timeout(struct net_device *dev);
218#endif
1da177e4
LT		 219static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
220static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
221static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
222static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
223
224/* Probing */
948252cb
DM		 225static int __init smsc_ircc_look_for_chips(void);
226static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
227static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
228static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229static int __init smsc_superio_fdc(unsigned short cfg_base);
230static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e 231#ifdef CONFIG_PCI
948252cb
DM		 232static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
233static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
234static void __init preconfigure_ali_port(struct pci_dev *dev,
08d09997 235 unsigned short port);
948252cb
DM		 236static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
237static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
c1e14a6e
LW		 238 unsigned short ircc_fir,
239 unsigned short ircc_sir,
240 unsigned char ircc_dma,
241 unsigned char ircc_irq);
242#endif
1da177e4
LT		 243
244/* Transceivers specific functions */
245
246static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
247static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
248static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
249static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
250static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
251static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
252
253/* Power Management */
254
3ae5eaec
RK		 255static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
256static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 257
3ae5eaec 258static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 259 .suspend = smsc_ircc_suspend,
260 .resume = smsc_ircc_resume,
3ae5eaec
RK		 261 .driver = {
262 .name = SMSC_IRCC2_DRIVER_NAME,
263 },
6bb3b2cd 264};
1da177e4
LT		 265
266/* Transceivers for SMSC-ircc */
267
b6158d23 268static struct smsc_transceiver smsc_transceivers[] =
1da177e4 269{
98b77773
DT		 270 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
271 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
272 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
273 { NULL, NULL }
1da177e4 274};
a956f4ca 275#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 276
277/* SMC SuperIO chipsets definitions */
278
279#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
280#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
281#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
282#define SIR 0 /* SuperIO Chip has only slow IRDA */
283#define FIR 4 /* SuperIO Chip has fast IRDA */
284#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
285
b6158d23 286static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 287{
288 /* Base address 0x3f0 or 0x370 */
289 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
290 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
291 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
292 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
294 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
295 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
296 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
297 { NULL }
298};
299
b6158d23 300static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 301{
302 /* Base address 0x3f0 or 0x370 */
303 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
304 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
305 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
306 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
307 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
308 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
309 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
310 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
311 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
312 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
313 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
314 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
315 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
316 { NULL }
317};
318
b6158d23 319static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 320{
321 /* Base address 0x2E or 0x4E */
322 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
afdf27c9 323 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
1da177e4
LT		 324 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
325 { NULL }
326};
327
b6158d23 328static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 329{
330 /* Base address 0x2E or 0x4E */
331 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
332 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
333 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
335 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
336 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
337 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
338 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
339 { NULL }
340};
341
342#define SMSCSIO_TYPE_FDC 1
343#define SMSCSIO_TYPE_LPC 2
344#define SMSCSIO_TYPE_FLAT 4
345#define SMSCSIO_TYPE_PAGED 8
346
b6158d23 347static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 348{
98b77773
DT		 349 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0, 0 }
1da177e4
LT		 355};
356
357/* Globals */
358
98b77773
DT		 359static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
360static unsigned short dev_count;
1da177e4
LT		 361
362static inline void register_bank(int iobase, int bank)
363{
98b77773
DT		 364 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
365 iobase + IRCC_MASTER);
1da177e4
LT		 366}
367
d94c77b9 368/* PNP hotplug support */
948252cb 369static const struct pnp_device_id smsc_ircc_pnp_table[] = {
d94c77b9
DB		 370 { .id = "SMCf010", .driver_data = 0 },
371 /* and presumably others */
372 { }
373};
374MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
d0d4f69b
BH		 375
376static int pnp_driver_registered;
377
7a1aa309 378#ifdef CONFIG_PNP
45ac936c 379static int smsc_ircc_pnp_probe(struct pnp_dev *dev,
1dd06ae8 380 const struct pnp_device_id *dev_id)
d0d4f69b
BH		 381{
382 unsigned int firbase, sirbase;
383 u8 dma, irq;
384
385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
387 return -EINVAL;
388
389 sirbase = pnp_port_start(dev, 0);
390 firbase = pnp_port_start(dev, 1);
391 dma = pnp_dma(dev, 0);
392 irq = pnp_irq(dev, 0);
393
394 if (smsc_ircc_open(firbase, sirbase, dma, irq))
395 return -ENODEV;
396
397 return 0;
398}
399
400static struct pnp_driver smsc_ircc_pnp_driver = {
401 .name = "smsc-ircc2",
402 .id_table = smsc_ircc_pnp_table,
403 .probe = smsc_ircc_pnp_probe,
404};
7a1aa309
IM		 405#else /* CONFIG_PNP */
406static struct pnp_driver smsc_ircc_pnp_driver;
407#endif
1da177e4
LT		 408
409/*******************************************************************************
410 *
411 *
412 * SMSC-ircc stuff
413 *
414 *
415 *******************************************************************************/
416
d0d4f69b
BH		 417static int __init smsc_ircc_legacy_probe(void)
418{
419 int ret = 0;
420
7c31d2f5
BH		 421#ifdef CONFIG_PCI
422 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
423 /* Ignore errors from preconfiguration */
424 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
425 }
426#endif
427
d0d4f69b
BH		 428 if (ircc_fir > 0 && ircc_sir > 0) {
429 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
430 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
431
432 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
433 ret = -ENODEV;
434 } else {
435 ret = -ENODEV;
436
437 /* try user provided configuration register base address */
438 if (ircc_cfg > 0) {
439 IRDA_MESSAGE(" Overriding configuration address "
440 "0x%04x\n", ircc_cfg);
441 if (!smsc_superio_fdc(ircc_cfg))
442 ret = 0;
443 if (!smsc_superio_lpc(ircc_cfg))
444 ret = 0;
445 }
446
447 if (smsc_ircc_look_for_chips() > 0)
448 ret = 0;
449 }
450 return ret;
451}
452
1da177e4
LT		 453/*
454 * Function smsc_ircc_init ()
455 *
456 * Initialize chip. Just try to find out how many chips we are dealing with
457 * and where they are
458 */
459static int __init smsc_ircc_init(void)
460{
6bb3b2cd 461 int ret;
1da177e4 462
a97a6f10 463 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 464
3ae5eaec 465 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd
DT		 466 if (ret) {
467 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
468 return ret;
469 }
470
98b77773 471 dev_count = 0;
527b6af4 472
d0d4f69b
BH		 473 if (smsc_nopnp || !pnp_platform_devices ||
474 ircc_cfg || ircc_fir || ircc_sir ||
475 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
476 ret = smsc_ircc_legacy_probe();
6bb3b2cd 477 } else {
d0d4f69b
BH		 478 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
479 pnp_driver_registered = 1;
1da177e4 480 }
527b6af4 481
d0d4f69b
BH		 482 if (ret) {
483 if (pnp_driver_registered)
484 pnp_unregister_driver(&smsc_ircc_pnp_driver);
3ae5eaec 485 platform_driver_unregister(&smsc_ircc_driver);
d0d4f69b 486 }
527b6af4 487
1da177e4
LT		 488 return ret;
489}
490
6518bbb8
SH		 491static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
492 struct net_device *dev)
02087be6
SH		 493{
494 struct smsc_ircc_cb *self = netdev_priv(dev);
495
496 if (self->io.speed > 115200)
497 return smsc_ircc_hard_xmit_fir(skb, dev);
498 else
499 return smsc_ircc_hard_xmit_sir(skb, dev);
500}
501
502static const struct net_device_ops smsc_ircc_netdev_ops = {
503 .ndo_open = smsc_ircc_net_open,
504 .ndo_stop = smsc_ircc_net_close,
505 .ndo_do_ioctl = smsc_ircc_net_ioctl,
506 .ndo_start_xmit = smsc_ircc_net_xmit,
507#if SMSC_IRCC2_C_NET_TIMEOUT
508 .ndo_tx_timeout = smsc_ircc_timeout,
509#endif
510};
511
1da177e4
LT		 512/*
513 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
514 *
515 * Try to open driver instance
516 *
517 */
45ac936c 518static int smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
1da177e4
LT		 519{
520 struct smsc_ircc_cb *self;
521 struct net_device *dev;
522 int err;
527b6af4 523
a97a6f10 524 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 525
526 err = smsc_ircc_present(fir_base, sir_base);
98b77773 527 if (err)
1da177e4 528 goto err_out;
527b6af4 529
1da177e4 530 err = -ENOMEM;
a956f4ca 531 if (dev_count >= ARRAY_SIZE(dev_self)) {
a97a6f10 532 IRDA_WARNING("%s(), too many devices!\n", __func__);
1da177e4
LT		 533 goto err_out1;
534 }
535
536 /*
537 * Allocate new instance of the driver
538 */
539 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
540 if (!dev) {
a97a6f10 541 IRDA_WARNING("%s() can't allocate net device\n", __func__);
1da177e4
LT		 542 goto err_out1;
543 }
544
1da177e4 545#if SMSC_IRCC2_C_NET_TIMEOUT
98b77773 546 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4 547#endif
02087be6 548 dev->netdev_ops = &smsc_ircc_netdev_ops;
527b6af4 549
da0841a0 550 self = netdev_priv(dev);
1da177e4
LT		 551 self->netdev = dev;
552
553 /* Make ifconfig display some details */
554 dev->base_addr = self->io.fir_base = fir_base;
555 dev->irq = self->io.irq = irq;
556
557 /* Need to store self somewhere */
6bb3b2cd 558 dev_self[dev_count] = self;
1da177e4
LT		 559 spin_lock_init(&self->lock);
560
527b6af4 561 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 562 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
563
564 self->rx_buff.head =
565 dma_alloc_coherent(NULL, self->rx_buff.truesize,
1f9061d2 566 &self->rx_buff_dma, GFP_KERNEL | __GFP_ZERO);
d0320f75 567 if (self->rx_buff.head == NULL)
1da177e4 568 goto err_out2;
1da177e4
LT		 569
570 self->tx_buff.head =
571 dma_alloc_coherent(NULL, self->tx_buff.truesize,
1f9061d2 572 &self->tx_buff_dma, GFP_KERNEL | __GFP_ZERO);
d0320f75 573 if (self->tx_buff.head == NULL)
1da177e4 574 goto err_out3;
1da177e4 575
1da177e4
LT		 576 self->rx_buff.in_frame = FALSE;
577 self->rx_buff.state = OUTSIDE_FRAME;
578 self->tx_buff.data = self->tx_buff.head;
579 self->rx_buff.data = self->rx_buff.head;
527b6af4 580
1da177e4 581 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 582 smsc_ircc_setup_qos(self);
1da177e4 583 smsc_ircc_init_chip(self);
527b6af4 584
98b77773
DT		 585 if (ircc_transceiver > 0 &&
586 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 587 self->transceiver = ircc_transceiver;
588 else
589 smsc_ircc_probe_transceiver(self);
590
591 err = register_netdev(self->netdev);
98b77773 592 if (err) {
1da177e4
LT		 593 IRDA_ERROR("%s, Network device registration failed!\n",
594 driver_name);
595 goto err_out4;
596 }
597
6bb3b2cd
DT		 598 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
599 dev_count, NULL, 0);
600 if (IS_ERR(self->pldev)) {
601 err = PTR_ERR(self->pldev);
602 goto err_out5;
603 }
3ae5eaec 604 platform_set_drvdata(self->pldev, self);
1da177e4
LT		 605
606 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 607 dev_count++;
1da177e4
LT		 608
609 return 0;
98b77773 610
6bb3b2cd
DT		 611 err_out5:
612 unregister_netdev(self->netdev);
613
1da177e4
LT		 614 err_out4:
615 dma_free_coherent(NULL, self->tx_buff.truesize,
616 self->tx_buff.head, self->tx_buff_dma);
617 err_out3:
618 dma_free_coherent(NULL, self->rx_buff.truesize,
619 self->rx_buff.head, self->rx_buff_dma);
620 err_out2:
621 free_netdev(self->netdev);
6bb3b2cd 622 dev_self[dev_count] = NULL;
1da177e4
LT		 623 err_out1:
624 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
625 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
626 err_out:
627 return err;
628}
629
630/*
631 * Function smsc_ircc_present(fir_base, sir_base)
632 *
633 * Check the smsc-ircc chip presence
634 *
635 */
636static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
637{
638 unsigned char low, high, chip, config, dma, irq, version;
639
640 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
641 driver_name)) {
642 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
a97a6f10 643 __func__, fir_base);
1da177e4
LT		 644 goto out1;
645 }
646
647 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
648 driver_name)) {
649 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
a97a6f10 650 __func__, sir_base);
1da177e4
LT		 651 goto out2;
652 }
653
654 register_bank(fir_base, 3);
655
98b77773
DT		 656 high = inb(fir_base + IRCC_ID_HIGH);
657 low = inb(fir_base + IRCC_ID_LOW);
658 chip = inb(fir_base + IRCC_CHIP_ID);
659 version = inb(fir_base + IRCC_VERSION);
660 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 661 dma = config & IRCC_INTERFACE_DMA_MASK;
662 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
663
527b6af4 664 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 665 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
a97a6f10 666 __func__, fir_base);
1da177e4
LT		 667 goto out3;
668 }
669 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
670 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
671 chip & 0x0f, version, fir_base, sir_base, dma, irq);
672
673 return 0;
98b77773 674
1da177e4
LT		 675 out3:
676 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
677 out2:
678 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
679 out1:
680 return -ENODEV;
681}
682
683/*
684 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
685 *
686 * Setup I/O
687 *
688 */
527b6af4
DT		 689static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
690 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 691 u8 dma, u8 irq)
692{
693 unsigned char config, chip_dma, chip_irq;
694
695 register_bank(fir_base, 3);
98b77773
DT		 696 config = inb(fir_base + IRCC_INTERFACE);
697 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
698 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 699
700 self->io.fir_base = fir_base;
701 self->io.sir_base = sir_base;
702 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
703 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
704 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
705 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
706
916f11c7 707 if (irq != IRQ_INVAL) {
1da177e4
LT		 708 if (irq != chip_irq)
709 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
710 driver_name, chip_irq, irq);
711 self->io.irq = irq;
98b77773 712 } else
1da177e4 713 self->io.irq = chip_irq;
527b6af4 714
916f11c7 715 if (dma != DMA_INVAL) {
1da177e4
LT		 716 if (dma != chip_dma)
717 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
718 driver_name, chip_dma, dma);
719 self->io.dma = dma;
98b77773 720 } else
1da177e4
LT		 721 self->io.dma = chip_dma;
722
723}
724
725/*
726 * Function smsc_ircc_setup_qos(self)
727 *
728 * Setup qos
729 *
730 */
731static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
732{
733 /* Initialize QoS for this device */
734 irda_init_max_qos_capabilies(&self->qos);
527b6af4 735
1da177e4
LT		 736 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
737 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
738
739 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
740 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
741 irda_qos_bits_to_value(&self->qos);
742}
743
744/*
745 * Function smsc_ircc_init_chip(self)
746 *
747 * Init chip
748 *
749 */
750static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
751{
e812cb52 752 int iobase = self->io.fir_base;
1da177e4
LT		 753
754 register_bank(iobase, 0);
98b77773
DT		 755 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
756 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 757
758 register_bank(iobase, 1);
e812cb52 759 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 760 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 761
762#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 763 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
764 iobase + IRCC_SCE_CFGB);
527b6af4 765#else
98b77773
DT		 766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
767 iobase + IRCC_SCE_CFGB);
527b6af4 768#endif
98b77773
DT		 769 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
770 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 771
1da177e4 772 register_bank(iobase, 4);
e812cb52 773 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 774
1da177e4 775 register_bank(iobase, 0);
e812cb52 776 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 777
778 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 779
1da177e4 780 /* Power on device */
98b77773 781 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 782}
783
784/*
785 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
786 *
787 * Process IOCTL commands for this device
788 *
789 */
790static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
791{
792 struct if_irda_req *irq = (struct if_irda_req *) rq;
793 struct smsc_ircc_cb *self;
794 unsigned long flags;
795 int ret = 0;
796
797 IRDA_ASSERT(dev != NULL, return -1;);
798
da0841a0 799 self = netdev_priv(dev);
1da177e4
LT		 800
801 IRDA_ASSERT(self != NULL, return -1;);
802
a97a6f10 803 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
527b6af4 804
1da177e4
LT		 805 switch (cmd) {
806 case SIOCSBANDWIDTH: /* Set bandwidth */
807 if (!capable(CAP_NET_ADMIN))
808 ret = -EPERM;
809 else {
810 /* Make sure we are the only one touching
811 * self->io.speed and the hardware - Jean II */
812 spin_lock_irqsave(&self->lock, flags);
813 smsc_ircc_change_speed(self, irq->ifr_baudrate);
814 spin_unlock_irqrestore(&self->lock, flags);
815 }
816 break;
817 case SIOCSMEDIABUSY: /* Set media busy */
818 if (!capable(CAP_NET_ADMIN)) {
819 ret = -EPERM;
820 break;
821 }
822
823 irda_device_set_media_busy(self->netdev, TRUE);
824 break;
825 case SIOCGRECEIVING: /* Check if we are receiving right now */
826 irq->ifr_receiving = smsc_ircc_is_receiving(self);
827 break;
828 #if 0
829 case SIOCSDTRRTS:
830 if (!capable(CAP_NET_ADMIN)) {
831 ret = -EPERM;
832 break;
833 }
834 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
835 break;
836 #endif
837 default:
838 ret = -EOPNOTSUPP;
839 }
527b6af4 840
1da177e4
LT		 841 return ret;
842}
843
1da177e4
LT		 844#if SMSC_IRCC2_C_NET_TIMEOUT
845/*
846 * Function smsc_ircc_timeout (struct net_device *dev)
847 *
848 * The networking timeout management.
849 *
850 */
851
852static void smsc_ircc_timeout(struct net_device *dev)
853{
da0841a0 854 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 855 unsigned long flags;
856
1da177e4
LT		 857 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
858 dev->name, self->io.speed);
859 spin_lock_irqsave(&self->lock, flags);
860 smsc_ircc_sir_start(self);
861 smsc_ircc_change_speed(self, self->io.speed);
1ae5dc34 862 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 863 netif_wake_queue(dev);
864 spin_unlock_irqrestore(&self->lock, flags);
865}
866#endif
867
868/*
869 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
870 *
871 * Transmits the current frame until FIFO is full, then
872 * waits until the next transmit interrupt, and continues until the
873 * frame is transmitted.
874 */
6518bbb8
SH		 875static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
876 struct net_device *dev)
1da177e4
LT		 877{
878 struct smsc_ircc_cb *self;
879 unsigned long flags;
1da177e4
LT		 880 s32 speed;
881
a97a6f10 882 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 883
ec634fe3 884 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
527b6af4 885
da0841a0 886 self = netdev_priv(dev);
ec634fe3 887 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 888
1da177e4 889 netif_stop_queue(dev);
527b6af4 890
1da177e4
LT		 891 /* Make sure test of self->io.speed & speed change are atomic */
892 spin_lock_irqsave(&self->lock, flags);
893
894 /* Check if we need to change the speed */
895 speed = irda_get_next_speed(skb);
98b77773 896 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 897 /* Check for empty frame */
898 if (!skb->len) {
899 /*
900 * We send frames one by one in SIR mode (no
901 * pipelining), so at this point, if we were sending
902 * a previous frame, we just received the interrupt
903 * telling us it is finished (UART_IIR_THRI).
904 * Therefore, waiting for the transmitter to really
905 * finish draining the fifo won't take too long.
906 * And the interrupt handler is not expected to run.
907 * - Jean II */
908 smsc_ircc_sir_wait_hw_transmitter_finish(self);
909 smsc_ircc_change_speed(self, speed);
910 spin_unlock_irqrestore(&self->lock, flags);
911 dev_kfree_skb(skb);
ec634fe3 912 return NETDEV_TX_OK;
1da177e4 913 }
98b77773 914 self->new_speed = speed;
1da177e4
LT		 915 }
916
917 /* Init tx buffer */
918 self->tx_buff.data = self->tx_buff.head;
919
920 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 921 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 922 self->tx_buff.truesize);
527b6af4 923
af049081 924 dev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 925
926 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 927 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 928
929 spin_unlock_irqrestore(&self->lock, flags);
930
931 dev_kfree_skb(skb);
527b6af4 932
ec634fe3 933 return NETDEV_TX_OK;
1da177e4
LT		 934}
935
936/*
937 * Function smsc_ircc_set_fir_speed (self, baud)
938 *
939 * Change the speed of the device
940 *
941 */
942static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
943{
944 int fir_base, ir_mode, ctrl, fast;
945
946 IRDA_ASSERT(self != NULL, return;);
947 fir_base = self->io.fir_base;
948
949 self->io.speed = speed;
950
98b77773 951 switch (speed) {
1da177e4 952 default:
527b6af4 953 case 576000:
1da177e4
LT		 954 ir_mode = IRCC_CFGA_IRDA_HDLC;
955 ctrl = IRCC_CRC;
956 fast = 0;
a97a6f10 957 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
1da177e4
LT		 958 break;
959 case 1152000:
960 ir_mode = IRCC_CFGA_IRDA_HDLC;
961 ctrl = IRCC_1152 | IRCC_CRC;
962 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
963 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
a97a6f10 964 __func__);
1da177e4
LT		 965 break;
966 case 4000000:
967 ir_mode = IRCC_CFGA_IRDA_4PPM;
968 ctrl = IRCC_CRC;
969 fast = IRCC_LCR_A_FAST;
970 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
a97a6f10 971 __func__);
1da177e4
LT		 972 break;
973 }
974 #if 0
975 Now in tranceiver!
976 /* This causes an interrupt */
977 register_bank(fir_base, 0);
98b77773 978 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 979 #endif
527b6af4 980
1da177e4 981 register_bank(fir_base, 1);
98b77773 982 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 983
1da177e4 984 register_bank(fir_base, 4);
98b77773 985 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 986}
987
988/*
989 * Function smsc_ircc_fir_start(self)
990 *
991 * Change the speed of the device
992 *
993 */
994static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
995{
996 struct net_device *dev;
997 int fir_base;
998
a97a6f10 999 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1000
1001 IRDA_ASSERT(self != NULL, return;);
1002 dev = self->netdev;
1003 IRDA_ASSERT(dev != NULL, return;);
1004
1005 fir_base = self->io.fir_base;
1006
1007 /* Reset everything */
1008
1da177e4 1009 /* Clear FIFO */
98b77773 1010 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 1011
1012 /* Enable interrupt */
98b77773 1013 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 1014
1015 register_bank(fir_base, 1);
1016
527b6af4 1017 /* Select the TX/RX interface */
1da177e4 1018#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 1019 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1020 fir_base + IRCC_SCE_CFGB);
527b6af4 1021#else
98b77773
DT		 1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1023 fir_base + IRCC_SCE_CFGB);
527b6af4 1024#endif
98b77773 1025 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 1026
1027 /* Enable SCE interrupts */
98b77773 1028 outb(0, fir_base + IRCC_MASTER);
1da177e4 1029 register_bank(fir_base, 0);
98b77773
DT		 1030 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1031 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 1032}
1033
1034/*
1035 * Function smsc_ircc_fir_stop(self, baud)
1036 *
1037 * Change the speed of the device
1038 *
1039 */
1040static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1041{
1042 int fir_base;
1043
a97a6f10 1044 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1045
1da177e4
LT		 1046 IRDA_ASSERT(self != NULL, return;);
1047
1048 fir_base = self->io.fir_base;
1049 register_bank(fir_base, 0);
98b77773
DT		 1050 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1051 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 1052}
1053
1054
1055/*
1056 * Function smsc_ircc_change_speed(self, baud)
1057 *
1058 * Change the speed of the device
1059 *
1060 * This function *must* be called with spinlock held, because it may
1061 * be called from the irq handler. - Jean II
1062 */
0fa2f491 1063static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1064{
1da177e4 1065 struct net_device *dev;
1da177e4 1066 int last_speed_was_sir;
527b6af4 1067
a97a6f10 1068 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1da177e4
LT		 1069
1070 IRDA_ASSERT(self != NULL, return;);
1071 dev = self->netdev;
1da177e4
LT		 1072
1073 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1074
1075 #if 0
1076 /* Temp Hack */
1077 speed= 1152000;
1078 self->io.speed = speed;
1079 last_speed_was_sir = 0;
527b6af4 1080 smsc_ircc_fir_start(self);
1da177e4 1081 #endif
527b6af4 1082
98b77773 1083 if (self->io.speed == 0)
1da177e4
LT		 1084 smsc_ircc_sir_start(self);
1085
1086 #if 0
98b77773 1087 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1088 #endif
1089
98b77773
DT		 1090 if (self->io.speed != speed)
1091 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1092
1093 self->io.speed = speed;
527b6af4 1094
98b77773
DT		 1095 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1096 if (!last_speed_was_sir) {
1da177e4
LT		 1097 smsc_ircc_fir_stop(self);
1098 smsc_ircc_sir_start(self);
1099 }
527b6af4 1100 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1101 } else {
1102 if (last_speed_was_sir) {
527b6af4 1103 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1104 smsc_ircc_sir_stop(self);
1105 #endif
1106 smsc_ircc_fir_start(self);
1107 }
1108 smsc_ircc_set_fir_speed(self, speed);
1109
1110 #if 0
1111 self->tx_buff.len = 10;
1112 self->tx_buff.data = self->tx_buff.head;
527b6af4 1113
80a90589 1114 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1115 #endif
1116 /* Be ready for incoming frames */
80a90589 1117 smsc_ircc_dma_receive(self);
1da177e4 1118 }
527b6af4 1119
1da177e4
LT		 1120 netif_wake_queue(dev);
1121}
1122
1123/*
1124 * Function smsc_ircc_set_sir_speed (self, speed)
1125 *
1126 * Set speed of IrDA port to specified baudrate
1127 *
1128 */
0e49e645 1129static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1130{
527b6af4 1131 int iobase;
1da177e4
LT		 1132 int fcr; /* FIFO control reg */
1133 int lcr; /* Line control reg */
1134 int divisor;
1135
a97a6f10 1136 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1da177e4
LT		 1137
1138 IRDA_ASSERT(self != NULL, return;);
1139 iobase = self->io.sir_base;
527b6af4 1140
1da177e4
LT		 1141 /* Update accounting for new speed */
1142 self->io.speed = speed;
1143
1144 /* Turn off interrupts */
98b77773 1145 outb(0, iobase + UART_IER);
1da177e4 1146
98b77773 1147 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1148
1da177e4
LT		 1149 fcr = UART_FCR_ENABLE_FIFO;
1150
527b6af4 1151 /*
1da177e4
LT		 1152 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1153 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1154 * about this timeout since it will always be fast enough.
1da177e4 1155 */
98b77773
DT		 1156 fcr |= self->io.speed < 38400 ?
1157 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1158
1da177e4
LT		 1159 /* IrDA ports use 8N1 */
1160 lcr = UART_LCR_WLEN8;
527b6af4 1161
98b77773
DT		 1162 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1163 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1164 outb(divisor >> 8, iobase + UART_DLM);
1165 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1166 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1167
1168 /* Turn on interrups */
98b77773 1169 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4 1170
a97a6f10 1171 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1da177e4
LT		 1172}
1173
1174
1175/*
1176 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1177 *
1178 * Transmit the frame!
1179 *
1180 */
6518bbb8
SH		 1181static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1182 struct net_device *dev)
1da177e4
LT		 1183{
1184 struct smsc_ircc_cb *self;
1185 unsigned long flags;
1186 s32 speed;
1da177e4
LT		 1187 int mtt;
1188
ec634fe3 1189 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
da0841a0 1190 self = netdev_priv(dev);
ec634fe3 1191 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 1192
1da177e4
LT		 1193 netif_stop_queue(dev);
1194
1195 /* Make sure test of self->io.speed & speed change are atomic */
1196 spin_lock_irqsave(&self->lock, flags);
1197
1198 /* Check if we need to change the speed after this frame */
1199 speed = irda_get_next_speed(skb);
98b77773 1200 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1201 /* Check for empty frame */
1202 if (!skb->len) {
1203 /* Note : you should make sure that speed changes
1204 * are not going to corrupt any outgoing frame.
1205 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1206 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1207 spin_unlock_irqrestore(&self->lock, flags);
1208 dev_kfree_skb(skb);
ec634fe3 1209 return NETDEV_TX_OK;
98b77773
DT		 1210 }
1211
1212 self->new_speed = speed;
1da177e4 1213 }
527b6af4 1214
d626f62b 1215 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1da177e4
LT		 1216
1217 self->tx_buff.len = skb->len;
1218 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1219
1220 mtt = irda_get_mtt(skb);
1da177e4
LT		 1221 if (mtt) {
1222 int bofs;
1223
527b6af4 1224 /*
1da177e4
LT		 1225 * Compute how many BOFs (STA or PA's) we need to waste the
1226 * min turn time given the speed of the link.
1227 */
1228 bofs = mtt * (self->io.speed / 1000) / 8000;
1229 if (bofs > 4095)
1230 bofs = 4095;
1231
80a90589 1232 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1233 } else {
1234 /* Transmit frame */
80a90589 1235 smsc_ircc_dma_xmit(self, 0);
1da177e4 1236 }
98b77773 1237
1da177e4
LT		 1238 spin_unlock_irqrestore(&self->lock, flags);
1239 dev_kfree_skb(skb);
1240
ec634fe3 1241 return NETDEV_TX_OK;
1da177e4
LT		 1242}
1243
1244/*
80a90589 1245 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1246 *
1247 * Transmit data using DMA
1248 *
1249 */
80a90589 1250static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1251{
80a90589 1252 int iobase = self->io.fir_base;
1da177e4
LT		 1253 u8 ctrl;
1254
a97a6f10 1255 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1256#if 1
1257 /* Disable Rx */
1258 register_bank(iobase, 0);
98b77773 1259 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1260#endif
1261 register_bank(iobase, 1);
98b77773
DT		 1262 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1263 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1264
1265 self->io.direction = IO_XMIT;
1266
1267 /* Set BOF additional count for generating the min turn time */
1268 register_bank(iobase, 4);
98b77773
DT		 1269 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1270 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1271 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1272
1273 /* Set max Tx frame size */
98b77773
DT		 1274 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1275 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1276
1277 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1278
1da177e4
LT		 1279 /* Enable burst mode chip Tx DMA */
1280 register_bank(iobase, 1);
98b77773
DT		 1281 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1282 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1283
1284 /* Setup DMA controller (must be done after enabling chip DMA) */
1285 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1286 DMA_TX_MODE);
1287
1288 /* Enable interrupt */
1289
1290 register_bank(iobase, 0);
98b77773
DT		 1291 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1292 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1293
1da177e4 1294 /* Enable transmit */
98b77773 1295 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1296}
1297
1298/*
1299 * Function smsc_ircc_dma_xmit_complete (self)
1300 *
527b6af4 1301 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1302 * by the interrupt handler
1303 *
1304 */
80a90589 1305static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1306{
80a90589
DT		 1307 int iobase = self->io.fir_base;
1308
a97a6f10 1309 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1310#if 0
1311 /* Disable Tx */
1312 register_bank(iobase, 0);
98b77773 1313 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1314#endif
80a90589
DT		 1315 register_bank(iobase, 1);
1316 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1317 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1318
1319 /* Check for underrun! */
1320 register_bank(iobase, 0);
98b77773 1321 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
af049081
SH		 1322 self->netdev->stats.tx_errors++;
1323 self->netdev->stats.tx_fifo_errors++;
1da177e4
LT		 1324
1325 /* Reset error condition */
1326 register_bank(iobase, 0);
98b77773
DT		 1327 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1328 outb(0x00, iobase + IRCC_MASTER);
1da177e4 1329 } else {
af049081
SH		 1330 self->netdev->stats.tx_packets++;
1331 self->netdev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1332 }
1333
1334 /* Check if it's time to change the speed */
1335 if (self->new_speed) {
527b6af4 1336 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1337 self->new_speed = 0;
1338 }
1339
1340 netif_wake_queue(self->netdev);
1341}
1342
1343/*
1344 * Function smsc_ircc_dma_receive(self)
1345 *
1346 * Get ready for receiving a frame. The device will initiate a DMA
1347 * if it starts to receive a frame.
1348 *
1349 */
80a90589 1350static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1351{
80a90589 1352 int iobase = self->io.fir_base;
1da177e4
LT		 1353#if 0
1354 /* Turn off chip DMA */
1355 register_bank(iobase, 1);
98b77773
DT		 1356 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1357 iobase + IRCC_SCE_CFGB);
1da177e4 1358#endif
527b6af4 1359
1da177e4
LT		 1360 /* Disable Tx */
1361 register_bank(iobase, 0);
98b77773 1362 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1363
1364 /* Turn off chip DMA */
1365 register_bank(iobase, 1);
98b77773
DT		 1366 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1367 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1368
1369 self->io.direction = IO_RECV;
1370 self->rx_buff.data = self->rx_buff.head;
1371
1372 /* Set max Rx frame size */
1373 register_bank(iobase, 4);
98b77773
DT		 1374 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1375 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1376
1377 /* Setup DMA controller */
1378 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1379 DMA_RX_MODE);
1380
1381 /* Enable burst mode chip Rx DMA */
1382 register_bank(iobase, 1);
98b77773
DT		 1383 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1384 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1385
1386 /* Enable interrupt */
1387 register_bank(iobase, 0);
98b77773
DT		 1388 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1389 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1390
1391 /* Enable receiver */
1392 register_bank(iobase, 0);
527b6af4 1393 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1394 iobase + IRCC_LCR_B);
527b6af4 1395
1da177e4
LT		 1396 return 0;
1397}
1398
1399/*
80a90589 1400 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1401 *
1402 * Finished with receiving frames
1403 *
1404 */
80a90589 1405static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1406{
1407 struct sk_buff *skb;
1408 int len, msgcnt, lsr;
80a90589 1409 int iobase = self->io.fir_base;
527b6af4 1410
1da177e4 1411 register_bank(iobase, 0);
527b6af4 1412
a97a6f10 1413 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1414#if 0
1415 /* Disable Rx */
1416 register_bank(iobase, 0);
98b77773 1417 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1418#endif
1419 register_bank(iobase, 0);
98b77773
DT		 1420 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1421 lsr= inb(iobase + IRCC_LSR);
1422 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4 1423
a97a6f10 1424 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1da177e4
LT		 1425 get_dma_residue(self->io.dma));
1426
1427 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1428
98b77773
DT		 1429 /* Look for errors */
1430 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
af049081 1431 self->netdev->stats.rx_errors++;
98b77773 1432 if (lsr & IRCC_LSR_FRAME_ERROR)
af049081 1433 self->netdev->stats.rx_frame_errors++;
98b77773 1434 if (lsr & IRCC_LSR_CRC_ERROR)
af049081 1435 self->netdev->stats.rx_crc_errors++;
98b77773 1436 if (lsr & IRCC_LSR_SIZE_ERROR)
af049081 1437 self->netdev->stats.rx_length_errors++;
98b77773 1438 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
af049081 1439 self->netdev->stats.rx_length_errors++;
1da177e4
LT		 1440 return;
1441 }
98b77773 1442
1da177e4 1443 /* Remove CRC */
98b77773 1444 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1445
98b77773 1446 if (len < 2 || len > 2050) {
a97a6f10 1447 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1da177e4
LT		 1448 return;
1449 }
a97a6f10 1450 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1da177e4 1451
98b77773
DT		 1452 skb = dev_alloc_skb(len + 1);
1453 if (!skb) {
1da177e4 1454 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
a97a6f10 1455 __func__);
1da177e4 1456 return;
527b6af4 1457 }
1da177e4 1458 /* Make sure IP header gets aligned */
527b6af4 1459 skb_reserve(skb, 1);
1da177e4
LT		 1460
1461 memcpy(skb_put(skb, len), self->rx_buff.data, len);
af049081
SH		 1462 self->netdev->stats.rx_packets++;
1463 self->netdev->stats.rx_bytes += len;
1da177e4
LT		 1464
1465 skb->dev = self->netdev;
459a98ed 1466 skb_reset_mac_header(skb);
1da177e4
LT		 1467 skb->protocol = htons(ETH_P_IRDA);
1468 netif_rx(skb);
1469}
1470
1471/*
1472 * Function smsc_ircc_sir_receive (self)
1473 *
1474 * Receive one frame from the infrared port
1475 *
1476 */
527b6af4 1477static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1478{
1479 int boguscount = 0;
1480 int iobase;
1481
1482 IRDA_ASSERT(self != NULL, return;);
1483
1484 iobase = self->io.sir_base;
1485
527b6af4
DT		 1486 /*
1487 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1488 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1489 */
1490 do {
af049081 1491 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
98b77773 1492 inb(iobase + UART_RX));
1da177e4
LT		 1493
1494 /* Make sure we don't stay here to long */
1495 if (boguscount++ > 32) {
a97a6f10 1496 IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1da177e4
LT		 1497 break;
1498 }
98b77773 1499 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1500}
1501
1502
1503/*
1504 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1505 *
1506 * An interrupt from the chip has arrived. Time to do some work
1507 *
1508 */
28fc1f5a 1509static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1da177e4 1510{
28fc1f5a
JG		 1511 struct net_device *dev = dev_id;
1512 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1513 int iobase, iir, lcra, lsr;
1514 irqreturn_t ret = IRQ_NONE;
1515
1da177e4 1516 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1517 spin_lock(&self->lock);
1da177e4
LT		 1518
1519 /* Check if we should use the SIR interrupt handler */
98b77773 1520 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1521 ret = smsc_ircc_interrupt_sir(dev);
1522 goto irq_ret_unlock;
1523 }
1524
1525 iobase = self->io.fir_base;
1526
1527 register_bank(iobase, 0);
98b77773 1528 iir = inb(iobase + IRCC_IIR);
527b6af4 1529 if (iir == 0)
1da177e4
LT		 1530 goto irq_ret_unlock;
1531 ret = IRQ_HANDLED;
1532
1533 /* Disable interrupts */
98b77773
DT		 1534 outb(0, iobase + IRCC_IER);
1535 lcra = inb(iobase + IRCC_LCR_A);
1536 lsr = inb(iobase + IRCC_LSR);
527b6af4 1537
a97a6f10 1538 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1da177e4
LT		 1539
1540 if (iir & IRCC_IIR_EOM) {
1541 if (self->io.direction == IO_RECV)
80a90589 1542 smsc_ircc_dma_receive_complete(self);
1da177e4 1543 else
80a90589 1544 smsc_ircc_dma_xmit_complete(self);
527b6af4 1545
80a90589 1546 smsc_ircc_dma_receive(self);
1da177e4
LT		 1547 }
1548
1549 if (iir & IRCC_IIR_ACTIVE_FRAME) {
a97a6f10 1550 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1da177e4
LT		 1551 }
1552
1553 /* Enable interrupts again */
1554
1555 register_bank(iobase, 0);
98b77773 1556 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1557
1558 irq_ret_unlock:
1559 spin_unlock(&self->lock);
28fc1f5a 1560
1da177e4
LT		 1561 return ret;
1562}
1563
1564/*
7d12e780 1565 * Function irport_interrupt_sir (irq, dev_id)
1da177e4
LT		 1566 *
1567 * Interrupt handler for SIR modes
1568 */
1569static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1570{
da0841a0 1571 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1572 int boguscount = 0;
1573 int iobase;
1574 int iir, lsr;
1575
25985edc 1576 /* Already locked coming here in smsc_ircc_interrupt() */
1da177e4
LT		 1577 /*spin_lock(&self->lock);*/
1578
1579 iobase = self->io.sir_base;
1580
98b77773 1581 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1582 if (iir == 0)
1583 return IRQ_NONE;
1584 while (iir) {
1585 /* Clear interrupt */
98b77773 1586 lsr = inb(iobase + UART_LSR);
1da177e4 1587
527b6af4 1588 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
a97a6f10 1589 __func__, iir, lsr, iobase);
1da177e4
LT		 1590
1591 switch (iir) {
1592 case UART_IIR_RLSI:
a97a6f10 1593 IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1da177e4
LT		 1594 break;
1595 case UART_IIR_RDI:
1596 /* Receive interrupt */
1597 smsc_ircc_sir_receive(self);
1598 break;
1599 case UART_IIR_THRI:
1600 if (lsr & UART_LSR_THRE)
1601 /* Transmitter ready for data */
1602 smsc_ircc_sir_write_wakeup(self);
1603 break;
1604 default:
1605 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
a97a6f10 1606 __func__, iir);
1da177e4 1607 break;
527b6af4
DT		 1608 }
1609
1da177e4
LT		 1610 /* Make sure we don't stay here to long */
1611 if (boguscount++ > 100)
1612 break;
1613
527b6af4 1614 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1615 }
1616 /*spin_unlock(&self->lock);*/
1617 return IRQ_HANDLED;
1618}
1619
1620
1621#if 0 /* unused */
1622/*
1623 * Function ircc_is_receiving (self)
1624 *
1625 * Return TRUE is we are currently receiving a frame
1626 *
1627 */
1628static int ircc_is_receiving(struct smsc_ircc_cb *self)
1629{
1630 int status = FALSE;
1631 /* int iobase; */
1632
a97a6f10 1633 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1634
1635 IRDA_ASSERT(self != NULL, return FALSE;);
1636
a97a6f10 1637 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1da177e4
LT		 1638 get_dma_residue(self->io.dma));
1639
1640 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1641
1da177e4
LT		 1642 return status;
1643}
1644#endif /* unused */
1645
e812cb52
DT		 1646static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1647{
1648 int error;
1649
1650 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1651 self->netdev->name, self->netdev);
1652 if (error)
1653 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
a97a6f10 1654 __func__, self->io.irq, error);
e812cb52
DT		 1655
1656 return error;
1657}
1658
1659static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1660{
1661 unsigned long flags;
1662
1663 spin_lock_irqsave(&self->lock, flags);
1664
1665 self->io.speed = 0;
1666 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1667
1668 spin_unlock_irqrestore(&self->lock, flags);
1669}
1670
1671static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1672{
1673 int iobase = self->io.fir_base;
1674 unsigned long flags;
1675
1676 spin_lock_irqsave(&self->lock, flags);
1677
1678 register_bank(iobase, 0);
1679 outb(0, iobase + IRCC_IER);
1680 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1681 outb(0x00, iobase + IRCC_MASTER);
1682
1683 spin_unlock_irqrestore(&self->lock, flags);
1684}
1685
1da177e4
LT		 1686
1687/*
1688 * Function smsc_ircc_net_open (dev)
1689 *
1690 * Start the device
1691 *
1692 */
1693static int smsc_ircc_net_open(struct net_device *dev)
1694{
1695 struct smsc_ircc_cb *self;
1da177e4 1696 char hwname[16];
1da177e4 1697
a97a6f10 1698 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1699
1da177e4 1700 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1701 self = netdev_priv(dev);
1da177e4 1702 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1703
e812cb52 1704 if (self->io.suspended) {
a97a6f10 1705 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
e812cb52
DT		 1706 return -EAGAIN;
1707 }
1708
527b6af4 1709 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1710 (void *) dev)) {
1711 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
a97a6f10 1712 __func__, self->io.irq);
1da177e4
LT		 1713 return -EAGAIN;
1714 }
1715
e812cb52 1716 smsc_ircc_start_interrupts(self);
527b6af4 1717
1da177e4
LT		 1718 /* Give self a hardware name */
1719 /* It would be cool to offer the chip revision here - Jean II */
1720 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1721
527b6af4 1722 /*
1da177e4 1723 * Open new IrLAP layer instance, now that everything should be
527b6af4 1724 * initialized properly
1da177e4
LT		 1725 */
1726 self->irlap = irlap_open(dev, &self->qos, hwname);
1727
1728 /*
1729 * Always allocate the DMA channel after the IRQ,
1730 * and clean up on failure.
1731 */
1732 if (request_dma(self->io.dma, dev->name)) {
1733 smsc_ircc_net_close(dev);
1734
1735 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
a97a6f10 1736 __func__, self->io.dma);
1da177e4
LT		 1737 return -EAGAIN;
1738 }
527b6af4 1739
1da177e4
LT		 1740 netif_start_queue(dev);
1741
1742 return 0;
1743}
1744
1745/*
1746 * Function smsc_ircc_net_close (dev)
1747 *
1748 * Stop the device
1749 *
1750 */
1751static int smsc_ircc_net_close(struct net_device *dev)
1752{
1753 struct smsc_ircc_cb *self;
1da177e4 1754
a97a6f10 1755 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1756
1da177e4 1757 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1758 self = netdev_priv(dev);
1da177e4 1759 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1760
1da177e4
LT		 1761 /* Stop device */
1762 netif_stop_queue(dev);
527b6af4 1763
1da177e4
LT		 1764 /* Stop and remove instance of IrLAP */
1765 if (self->irlap)
1766 irlap_close(self->irlap);
1767 self->irlap = NULL;
1768
e812cb52
DT		 1769 smsc_ircc_stop_interrupts(self);
1770
1771 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1772 if (!self->io.suspended)
1773 free_irq(self->io.irq, dev);
1774
1da177e4 1775 disable_dma(self->io.dma);
1da177e4
LT		 1776 free_dma(self->io.dma);
1777
1778 return 0;
1779}
1780
3ae5eaec 1781static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1782{
3ae5eaec 1783 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1784
9480e307 1785 if (!self->io.suspended) {
e812cb52
DT		 1786 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1787
1788 rtnl_lock();
1789 if (netif_running(self->netdev)) {
1790 netif_device_detach(self->netdev);
1791 smsc_ircc_stop_interrupts(self);
1792 free_irq(self->io.irq, self->netdev);
1793 disable_dma(self->io.dma);
1794 }
98b77773 1795 self->io.suspended = 1;
e812cb52 1796 rtnl_unlock();
98b77773 1797 }
6bb3b2cd
DT		 1798
1799 return 0;
1da177e4
LT		 1800}
1801
3ae5eaec 1802static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1803{
3ae5eaec 1804 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1805
9480e307 1806 if (self->io.suspended) {
e812cb52
DT		 1807 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1808
1809 rtnl_lock();
1810 smsc_ircc_init_chip(self);
1811 if (netif_running(self->netdev)) {
1812 if (smsc_ircc_request_irq(self)) {
1813 /*
1814 * Don't fail resume process, just kill this
1815 * network interface
1816 */
1817 unregister_netdevice(self->netdev);
1818 } else {
1819 enable_dma(self->io.dma);
1820 smsc_ircc_start_interrupts(self);
1821 netif_device_attach(self->netdev);
1822 }
1823 }
6bb3b2cd 1824 self->io.suspended = 0;
e812cb52 1825 rtnl_unlock();
6bb3b2cd 1826 }
1da177e4
LT		 1827 return 0;
1828}
1829
1830/*
1831 * Function smsc_ircc_close (self)
1832 *
1833 * Close driver instance
1834 *
1835 */
1836static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1837{
a97a6f10 1838 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1839
1840 IRDA_ASSERT(self != NULL, return -1;);
1841
6bb3b2cd 1842 platform_device_unregister(self->pldev);
1da177e4
LT		 1843
1844 /* Remove netdevice */
1845 unregister_netdev(self->netdev);
1846
e812cb52 1847 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1848
1849 /* Release the PORTS that this driver is using */
a97a6f10 1850 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1da177e4
LT		 1851 self->io.fir_base);
1852
1853 release_region(self->io.fir_base, self->io.fir_ext);
1854
a97a6f10 1855 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1da177e4
LT		 1856 self->io.sir_base);
1857
1858 release_region(self->io.sir_base, self->io.sir_ext);
1859
1860 if (self->tx_buff.head)
1861 dma_free_coherent(NULL, self->tx_buff.truesize,
1862 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1863
1da177e4
LT		 1864 if (self->rx_buff.head)
1865 dma_free_coherent(NULL, self->rx_buff.truesize,
1866 self->rx_buff.head, self->rx_buff_dma);
1867
1868 free_netdev(self->netdev);
1869
1870 return 0;
1871}
1872
1873static void __exit smsc_ircc_cleanup(void)
1874{
1875 int i;
1876
a97a6f10 1877 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 1878
98b77773 1879 for (i = 0; i < 2; i++) {
1da177e4
LT		 1880 if (dev_self[i])
1881 smsc_ircc_close(dev_self[i]);
1882 }
6bb3b2cd 1883
d0d4f69b
BH		 1884 if (pnp_driver_registered)
1885 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1886
3ae5eaec 1887 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1888}
1889
1890/*
1891 * Start SIR operations
1892 *
1893 * This function *must* be called with spinlock held, because it may
1894 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1895 */
0e49e645 1896static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1da177e4
LT		 1897{
1898 struct net_device *dev;
1899 int fir_base, sir_base;
1900
a97a6f10 1901 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4 1902
527b6af4 1903 IRDA_ASSERT(self != NULL, return;);
98b77773 1904 dev = self->netdev;
527b6af4 1905 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1906
1907 fir_base = self->io.fir_base;
1908 sir_base = self->io.sir_base;
1909
1910 /* Reset everything */
98b77773 1911 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1912
1913 #if SMSC_IRCC2_C_SIR_STOP
1914 /*smsc_ircc_sir_stop(self);*/
1915 #endif
1916
1917 register_bank(fir_base, 1);
98b77773 1918 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1919
1920 /* Initialize UART */
98b77773
DT		 1921 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1922 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1923
1da177e4 1924 /* Turn on interrups */
98b77773 1925 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4 1926
a97a6f10 1927 IRDA_DEBUG(3, "%s() - exit\n", __func__);
1da177e4 1928
98b77773 1929 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1930}
1931
1932#if SMSC_IRCC2_C_SIR_STOP
1933void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1934{
1935 int iobase;
1936
a97a6f10 1937 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1938 iobase = self->io.sir_base;
1939
1940 /* Reset UART */
98b77773 1941 outb(0, iobase + UART_MCR);
527b6af4 1942
1da177e4 1943 /* Turn off interrupts */
98b77773 1944 outb(0, iobase + UART_IER);
1da177e4
LT		 1945}
1946#endif
1947
1948/*
1949 * Function smsc_sir_write_wakeup (self)
1950 *
1951 * Called by the SIR interrupt handler when there's room for more data.
1952 * If we have more packets to send, we send them here.
1953 *
1954 */
1955static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1956{
1957 int actual = 0;
1958 int iobase;
1959 int fcr;
1960
1961 IRDA_ASSERT(self != NULL, return;);
1962
a97a6f10 1963 IRDA_DEBUG(4, "%s\n", __func__);
1da177e4
LT		 1964
1965 iobase = self->io.sir_base;
1966
1967 /* Finished with frame? */
1968 if (self->tx_buff.len > 0) {
1969 /* Write data left in transmit buffer */
527b6af4 1970 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1971 self->tx_buff.data, self->tx_buff.len);
1972 self->tx_buff.data += actual;
1973 self->tx_buff.len -= actual;
1974 } else {
527b6af4 1975
1da177e4 1976 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1977
1978 /*
1979 * Now serial buffer is almost free & we can start
1da177e4
LT		 1980 * transmission of another packet. But first we must check
1981 * if we need to change the speed of the hardware
1982 */
1983 if (self->new_speed) {
1984 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
a97a6f10 1985 __func__, self->new_speed);
1da177e4
LT		 1986 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1987 smsc_ircc_change_speed(self, self->new_speed);
1988 self->new_speed = 0;
1989 } else {
1990 /* Tell network layer that we want more frames */
1991 netif_wake_queue(self->netdev);
1992 }
af049081 1993 self->netdev->stats.tx_packets++;
1da177e4 1994
98b77773
DT		 1995 if (self->io.speed <= 115200) {
1996 /*
1997 * Reset Rx FIFO to make sure that all reflected transmit data
1998 * is discarded. This is needed for half duplex operation
1999 */
2000 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2001 fcr |= self->io.speed < 38400 ?
2002 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 2003
98b77773 2004 outb(fcr, iobase + UART_FCR);
1da177e4 2005
98b77773
DT		 2006 /* Turn on receive interrupts */
2007 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 2008 }
2009 }
2010}
2011
2012/*
2013 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2014 *
2015 * Fill Tx FIFO with transmit data
2016 *
2017 */
2018static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2019{
2020 int actual = 0;
527b6af4 2021
1da177e4 2022 /* Tx FIFO should be empty! */
98b77773 2023 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
a97a6f10 2024 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
1da177e4
LT		 2025 return 0;
2026 }
527b6af4 2027
1da177e4 2028 /* Fill FIFO with current frame */
98b77773 2029 while (fifo_size-- > 0 && actual < len) {
1da177e4 2030 /* Transmit next byte */
98b77773 2031 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 2032 actual++;
2033 }
2034 return actual;
2035}
2036
2037/*
2038 * Function smsc_ircc_is_receiving (self)
2039 *
2040 * Returns true is we are currently receiving data
2041 *
2042 */
2043static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2044{
807540ba 2045 return self->rx_buff.state != OUTSIDE_FRAME;
1da177e4
LT		 2046}
2047
2048
2049/*
2050 * Function smsc_ircc_probe_transceiver(self)
2051 *
2052 * Tries to find the used Transceiver
2053 *
2054 */
2055static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2056{
2057 unsigned int i;
527b6af4 2058
1da177e4 2059 IRDA_ASSERT(self != NULL, return;);
527b6af4 2060
98b77773
DT		 2061 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2062 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 2063 IRDA_MESSAGE(" %s transceiver found\n",
2064 smsc_transceivers[i].name);
98b77773 2065 self->transceiver= i + 1;
1da177e4
LT		 2066 return;
2067 }
98b77773 2068
1da177e4
LT		 2069 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2070 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2071
98b77773 2072 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2073}
2074
2075
2076/*
2077 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2078 *
2079 * Set the transceiver according to the speed
2080 *
2081 */
2082static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2083{
2084 unsigned int trx;
527b6af4 2085
1da177e4 2086 trx = self->transceiver;
98b77773
DT		 2087 if (trx > 0)
2088 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2089}
2090
2091/*
2092 * Function smsc_ircc_wait_hw_transmitter_finish ()
2093 *
2094 * Wait for the real end of HW transmission
2095 *
2096 * The UART is a strict FIFO, and we get called only when we have finished
2097 * pushing data to the FIFO, so the maximum amount of time we must wait
2098 * is only for the FIFO to drain out.
2099 *
2100 * We use a simple calibrated loop. We may need to adjust the loop
2101 * delay (udelay) to balance I/O traffic and latency. And we also need to
2102 * adjust the maximum timeout.
2103 * It would probably be better to wait for the proper interrupt,
2104 * but it doesn't seem to be available.
2105 *
2106 * We can't use jiffies or kernel timers because :
2107 * 1) We are called from the interrupt handler, which disable softirqs,
2108 * so jiffies won't be increased
2109 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2110 * want to wait that long to detect stuck hardware.
2111 * Jean II
2112 */
2113
2114static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2115{
98b77773 2116 int iobase = self->io.sir_base;
1da177e4 2117 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2118
1da177e4 2119 /* Calibrated busy loop */
98b77773 2120 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2121 udelay(1);
2122
adbf7f01 2123 if (count < 0)
a97a6f10 2124 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
1da177e4
LT		 2125}
2126
2127
2128/* PROBING
2129 *
d94c77b9
DB		 2130 * REVISIT we can be told about the device by PNP, and should use that info
2131 * instead of probing hardware and creating a platform_device ...
1da177e4
LT		 2132 */
2133
2134static int __init smsc_ircc_look_for_chips(void)
2135{
b6158d23 2136 struct smsc_chip_address *address;
98b77773 2137 char *type;
1da177e4 2138 unsigned int cfg_base, found;
527b6af4 2139
1da177e4
LT		 2140 found = 0;
2141 address = possible_addresses;
527b6af4 2142
98b77773 2143 while (address->cfg_base) {
1da177e4 2144 cfg_base = address->cfg_base;
527b6af4 2145
a97a6f10 2146 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
527b6af4 2147
98b77773 2148 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2149 type = "FDC";
98b77773
DT		 2150 if (address->type & SMSCSIO_TYPE_FLAT)
2151 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2152 found++;
2153
2154 if (address->type & SMSCSIO_TYPE_PAGED)
2155 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2156 found++;
1da177e4 2157 }
98b77773 2158 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2159 type = "LPC";
98b77773
DT		 2160 if (address->type & SMSCSIO_TYPE_FLAT)
2161 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2162 found++;
2163
2164 if (address->type & SMSCSIO_TYPE_PAGED)
2165 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2166 found++;
1da177e4
LT		 2167 }
2168 address++;
2169 }
2170 return found;
527b6af4 2171}
1da177e4
LT		 2172
2173/*
2174 * Function smsc_superio_flat (chip, base, type)
2175 *
2176 * Try to get configuration of a smc SuperIO chip with flat register model
2177 *
2178 */
b6158d23 2179static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2180{
2181 unsigned short firbase, sirbase;
2182 u8 mode, dma, irq;
2183 int ret = -ENODEV;
2184
a97a6f10 2185 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 2186
98b77773 2187 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2188 return ret;
2189
2190 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2191 mode = inb(cfgbase + 1);
527b6af4 2192
a97a6f10 2193 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
527b6af4 2194
98b77773 2195 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
a97a6f10 2196 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
1da177e4
LT		 2197
2198 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2199 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2200
527b6af4 2201 /* FIR iobase */
1da177e4 2202 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2203 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2204
2205 /* DMA */
2206 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2207 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2208
1da177e4
LT		 2209 /* IRQ */
2210 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2211 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4 2212
a97a6f10 2213 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
1da177e4 2214
98b77773
DT		 2215 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2216 ret = 0;
527b6af4 2217
1da177e4
LT		 2218 /* Exit configuration */
2219 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2220
2221 return ret;
2222}
2223
2224/*
2225 * Function smsc_superio_paged (chip, base, type)
2226 *
2227 * Try to get configuration of a smc SuperIO chip with paged register model
2228 *
2229 */
b6158d23 2230static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2231{
2232 unsigned short fir_io, sir_io;
2233 int ret = -ENODEV;
527b6af4 2234
a97a6f10 2235 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 2236
98b77773 2237 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2238 return ret;
527b6af4 2239
1da177e4
LT		 2240 /* Select logical device (UART2) */
2241 outb(0x07, cfg_base);
2242 outb(0x05, cfg_base + 1);
527b6af4 2243
1da177e4
LT		 2244 /* SIR iobase */
2245 outb(0x60, cfg_base);
98b77773 2246 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2247 outb(0x61, cfg_base);
2248 sir_io |= inb(cfg_base + 1);
527b6af4 2249
1da177e4
LT		 2250 /* Read FIR base */
2251 outb(0x62, cfg_base);
2252 fir_io = inb(cfg_base + 1) << 8;
2253 outb(0x63, cfg_base);
2254 fir_io |= inb(cfg_base + 1);
2255 outb(0x2b, cfg_base); /* ??? */
2256
98b77773
DT		 2257 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2258 ret = 0;
527b6af4 2259
1da177e4
LT		 2260 /* Exit configuration */
2261 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2262
2263 return ret;
2264}
2265
2266
948252cb 2267static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4 2268{
a97a6f10 2269 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 2270
2271 outb(reg, cfg_base);
98b77773 2272 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2273}
2274
948252cb 2275static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2276{
98b77773 2277 u8 devid, xdevid, rev;
1da177e4 2278
a97a6f10 2279 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 2280
2281 /* Leave configuration */
2282
2283 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2284
2285 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2286 return NULL;
2287
2288 outb(reg, cfg_base);
2289
98b77773 2290 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2291
2292 /* Enter configuration */
2293
2294 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2295
2296 #if 0
2297 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2298 return NULL;
2299 #endif
527b6af4 2300
1da177e4
LT		 2301 /* probe device ID */
2302
98b77773 2303 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2304 return NULL;
2305
98b77773 2306 devid = inb(cfg_base + 1);
527b6af4 2307
98b77773 2308 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2309 return NULL;
2310
2311 /* probe revision ID */
2312
98b77773 2313 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2314 return NULL;
2315
98b77773 2316 rev = inb(cfg_base + 1);
1da177e4 2317
98b77773 2318 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2319 return NULL;
2320
98b77773 2321 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2322 return NULL;
2323
2324 /* Check for expected device ID; are there others? */
2325
98b77773 2326 while (chip->devid != devid) {
1da177e4
LT		 2327
2328 chip++;
2329
98b77773 2330 if (chip->name == NULL)
1da177e4
LT		 2331 return NULL;
2332 }
2333
98b77773
DT		 2334 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2335 devid, rev, cfg_base, type, chip->name);
1da177e4 2336
98b77773 2337 if (chip->rev > rev) {
527b6af4 2338 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2339 return NULL;
2340 }
527b6af4 2341
98b77773 2342 if (chip->flags & NoIRDA)
1da177e4
LT		 2343 IRDA_MESSAGE("chipset does not support IRDA\n");
2344
2345 return chip;
2346}
2347
2348static int __init smsc_superio_fdc(unsigned short cfg_base)
2349{
2350 int ret = -1;
2351
2352 if (!request_region(cfg_base, 2, driver_name)) {
2353 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
a97a6f10 2354 __func__, cfg_base);
1da177e4 2355 } else {
98b77773
DT		 2356 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2357 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2358 ret = 0;
2359
2360 release_region(cfg_base, 2);
2361 }
2362
2363 return ret;
2364}
2365
2366static int __init smsc_superio_lpc(unsigned short cfg_base)
2367{
2368 int ret = -1;
2369
2370 if (!request_region(cfg_base, 2, driver_name)) {
2371 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
a97a6f10 2372 __func__, cfg_base);
1da177e4 2373 } else {
98b77773
DT		 2374 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2375 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2376 ret = 0;
98b77773 2377
1da177e4
LT		 2378 release_region(cfg_base, 2);
2379 }
2380 return ret;
2381}
2382
c1e14a6e
LW		 2383/*
2384 * Look for some specific subsystem setups that need
2385 * pre-configuration not properly done by the BIOS (especially laptops)
2386 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2387 * and tosh2450-smcinit.c. The table lists the device entries
08d09997
LW		 2388 * for ISA bridges with an LPC (Low Pin Count) controller which
2389 * handles the communication with the SMSC device. After the LPC
2390 * controller is initialized through PCI, the SMSC device is initialized
2391 * through a dedicated port in the ISA port-mapped I/O area, this latter
2392 * area is used to configure the SMSC device with default
2393 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2394 * used different sets of parameters and different control port
2395 * addresses making a subsystem device table necessary.
c1e14a6e
LW		 2396 */
2397#ifdef CONFIG_PCI
948252cb 2398static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
895de090
LWLE		 2399 /*
2400 * Subsystems needing entries:
2401 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2402 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2403 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2404 */
2405 {
2406 /* Guessed entry */
5ee5a07c 2407 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
895de090
LWLE		 2408 .device = 0x24cc,
2409 .subvendor = 0x103c,
2410 .subdevice = 0x08bc,
2411 .sir_io = 0x02f8,
2412 .fir_io = 0x0130,
2413 .fir_irq = 0x05,
2414 .fir_dma = 0x03,
2415 .cfg_base = 0x004e,
2416 .preconfigure = preconfigure_through_82801,
2417 .name = "HP nx5000 family",
2418 },
c1e14a6e 2419 {
5ee5a07c 2420 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
c1e14a6e
LW		 2421 .device = 0x24cc,
2422 .subvendor = 0x103c,
2423 .subdevice = 0x088c,
08d09997
LW		 2424 /* Quite certain these are the same for nc8000 as for nc6000 */
2425 .sir_io = 0x02f8,
c1e14a6e 2426 .fir_io = 0x0130,
08d09997 2427 .fir_irq = 0x05,
c1e14a6e
LW		 2428 .fir_dma = 0x03,
2429 .cfg_base = 0x004e,
2430 .preconfigure = preconfigure_through_82801,
895de090 2431 .name = "HP nc8000 family",
c1e14a6e
LW		 2432 },
2433 {
5ee5a07c 2434 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
c1e14a6e
LW		 2435 .device = 0x24cc,
2436 .subvendor = 0x103c,
2437 .subdevice = 0x0890,
2438 .sir_io = 0x02f8,
2439 .fir_io = 0x0130,
08d09997 2440 .fir_irq = 0x05,
c1e14a6e
LW		 2441 .fir_dma = 0x03,
2442 .cfg_base = 0x004e,
2443 .preconfigure = preconfigure_through_82801,
895de090
LWLE		 2444 .name = "HP nc6000 family",
2445 },
2446 {
5ee5a07c 2447 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
895de090
LWLE		 2448 .device = 0x24cc,
2449 .subvendor = 0x0e11,
2450 .subdevice = 0x0860,
2451 /* I assume these are the same for x1000 as for the others */
2452 .sir_io = 0x02e8,
2453 .fir_io = 0x02f8,
2454 .fir_irq = 0x07,
2455 .fir_dma = 0x03,
2456 .cfg_base = 0x002e,
2457 .preconfigure = preconfigure_through_82801,
2458 .name = "Compaq x1000 family",
c1e14a6e
LW		 2459 },
2460 {
08d09997 2461 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
5ee5a07c 2462 .vendor = PCI_VENDOR_ID_INTEL,
c1e14a6e
LW		 2463 .device = 0x24c0,
2464 .subvendor = 0x1179,
08d09997 2465 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2466 .sir_io = 0x03f8,
2467 .fir_io = 0x0130,
2468 .fir_irq = 0x07,
2469 .fir_dma = 0x01,
2470 .cfg_base = 0x002e,
2471 .preconfigure = preconfigure_through_82801,
08d09997 2472 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
c1e14a6e
LW		 2473 },
2474 {
5ee5a07c 2475 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
08d09997 2476 .device = 0x248c,
c1e14a6e 2477 .subvendor = 0x1179,
08d09997 2478 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2479 .sir_io = 0x03f8,
2480 .fir_io = 0x0130,
2481 .fir_irq = 0x03,
2482 .fir_dma = 0x03,
2483 .cfg_base = 0x002e,
2484 .preconfigure = preconfigure_through_82801,
08d09997 2485 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
c1e14a6e
LW		 2486 },
2487 {
08d09997 2488 /* 82801DBM (ICH4-M) LPC Interface Bridge */
5ee5a07c 2489 .vendor = PCI_VENDOR_ID_INTEL,
08d09997
LW		 2490 .device = 0x24cc,
2491 .subvendor = 0x1179,
2492 .subdevice = 0xffff, /* 0xffff is "any" */
2493 .sir_io = 0x03f8,
2494 .fir_io = 0x0130,
2495 .fir_irq = 0x03,
2496 .fir_dma = 0x03,
2497 .cfg_base = 0x002e,
2498 .preconfigure = preconfigure_through_82801,
2499 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2500 },
2501 {
2502 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
5ee5a07c 2503 .vendor = PCI_VENDOR_ID_AL,
c1e14a6e
LW		 2504 .device = 0x1533,
2505 .subvendor = 0x1179,
08d09997 2506 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2507 .sir_io = 0x02e8,
2508 .fir_io = 0x02f8,
2509 .fir_irq = 0x07,
2510 .fir_dma = 0x03,
2511 .cfg_base = 0x002e,
2512 .preconfigure = preconfigure_through_ali,
08d09997 2513 .name = "Toshiba laptop with ALi ISA bridge",
c1e14a6e
LW		 2514 },
2515 { } // Terminator
2516};
2517
2518
2519/*
08d09997
LW		 2520 * This sets up the basic SMSC parameters
2521 * (FIR port, SIR port, FIR DMA, FIR IRQ)
c1e14a6e
LW		 2522 * through the chip configuration port.
2523 */
948252cb 2524static int __init preconfigure_smsc_chip(struct
08d09997
LW		 2525 smsc_ircc_subsystem_configuration
2526 *conf)
c1e14a6e
LW		 2527{
2528 unsigned short iobase = conf->cfg_base;
2529 unsigned char tmpbyte;
2530
2531 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2532 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2533 tmpbyte = inb(iobase +1); // Read device ID
08d09997
LW		 2534 IRDA_DEBUG(0,
2535 "Detected Chip id: 0x%02x, setting up registers...\n",
2536 tmpbyte);
c1e14a6e
LW		 2537
2538 /* Disable UART1 and set up SIR I/O port */
2539 outb(0x24, iobase); // select CR24 - UART1 base addr
2540 outb(0x00, iobase + 1); // disable UART1
2541 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2542 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2543 tmpbyte = inb(iobase + 1);
2544 if (tmpbyte != (conf->sir_io >> 2) ) {
2545 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
08d09997 2546 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
c1e14a6e
LW		 2547 return -ENXIO;
2548 }
2549
2550 /* Set up FIR IRQ channel for UART2 */
2551 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2552 tmpbyte = inb(iobase + 1);
2553 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2554 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2555 outb(tmpbyte, iobase + 1);
2556 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2557 if (tmpbyte != conf->fir_irq) {
2558 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2559 return -ENXIO;
2560 }
2561
2562 /* Set up FIR I/O port */
2563 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2564 outb((conf->fir_io >> 3), iobase + 1);
2565 tmpbyte = inb(iobase + 1);
2566 if (tmpbyte != (conf->fir_io >> 3) ) {
2567 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2568 return -ENXIO;
2569 }
2570
2571 /* Set up FIR DMA channel */
2572 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2573 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2574 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2575 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2576 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2577 return -ENXIO;
2578 }
2579
2580 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2581 tmpbyte = inb(iobase + 1);
08d09997
LW		 2582 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2583 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
c1e14a6e
LW		 2584 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2585
2586 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2587 tmpbyte = inb(iobase + 1);
2588 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2589
2590 /* This one was not part of tosh1800 */
2591 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2592 tmpbyte = inb(iobase + 1);
2593 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2594
2595 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2596 tmpbyte = inb(iobase + 1);
2597 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2598
2599 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2600 tmpbyte = inb(iobase + 1);
2601 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2602
2603 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2604
2605 return 0;
2606}
2607
08d09997 2608/* 82801CAM generic registers */
c1e14a6e
LW		 2609#define VID 0x00
2610#define DID 0x02
08d09997
LW		 2611#define PIRQ_A_D_ROUT 0x60
2612#define SIRQ_CNTL 0x64
2613#define PIRQ_E_H_ROUT 0x68
c1e14a6e 2614#define PCI_DMA_C 0x90
08d09997 2615/* LPC-specific registers */
c1e14a6e 2616#define COM_DEC 0xe0
08d09997 2617#define GEN1_DEC 0xe4
c1e14a6e
LW		 2618#define LPC_EN 0xe6
2619#define GEN2_DEC 0xec
2620/*
08d09997
LW		 2621 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2622 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2623 * They all work the same way!
c1e14a6e 2624 */
948252cb 2625static int __init preconfigure_through_82801(struct pci_dev *dev,
08d09997
LW		 2626 struct
2627 smsc_ircc_subsystem_configuration
2628 *conf)
c1e14a6e
LW		 2629{
2630 unsigned short tmpword;
08d09997 2631 unsigned char tmpbyte;
c1e14a6e 2632
08d09997
LW		 2633 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2634 /*
2635 * Select the range for the COMA COM port (SIR)
2636 * Register COM_DEC:
2637 * Bit 7: reserved
2638 * Bit 6-4, COMB decode range
2639 * Bit 3: reserved
2640 * Bit 2-0, COMA decode range
2641 *
2642 * Decode ranges:
2643 * 000 = 0x3f8-0x3ff (COM1)
2644 * 001 = 0x2f8-0x2ff (COM2)
2645 * 010 = 0x220-0x227
2646 * 011 = 0x228-0x22f
2647 * 100 = 0x238-0x23f
2648 * 101 = 0x2e8-0x2ef (COM4)
2649 * 110 = 0x338-0x33f
2650 * 111 = 0x3e8-0x3ef (COM3)
2651 */
2652 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2653 tmpbyte &= 0xf8; /* mask COMA bits */
2654 switch(conf->sir_io) {
2655 case 0x3f8:
2656 tmpbyte |= 0x00;
2657 break;
2658 case 0x2f8:
2659 tmpbyte |= 0x01;
2660 break;
2661 case 0x220:
2662 tmpbyte |= 0x02;
2663 break;
2664 case 0x228:
2665 tmpbyte |= 0x03;
2666 break;
2667 case 0x238:
2668 tmpbyte |= 0x04;
2669 break;
2670 case 0x2e8:
2671 tmpbyte |= 0x05;
2672 break;
2673 case 0x338:
2674 tmpbyte |= 0x06;
2675 break;
2676 case 0x3e8:
2677 tmpbyte |= 0x07;
2678 break;
2679 default:
2680 tmpbyte |= 0x01; /* COM2 default */
2681 }
2682 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2683 pci_write_config_byte(dev, COM_DEC, tmpbyte);
c1e14a6e 2684
08d09997
LW		 2685 /* Enable Low Pin Count interface */
2686 pci_read_config_word(dev, LPC_EN, &tmpword);
2687 /* These seem to be set up at all times,
2688 * just make sure it is properly set.
2689 */
2690 switch(conf->cfg_base) {
2691 case 0x04e:
2692 tmpword |= 0x2000;
2693 break;
2694 case 0x02e:
2695 tmpword |= 0x1000;
2696 break;
2697 case 0x062:
2698 tmpword |= 0x0800;
2699 break;
2700 case 0x060:
2701 tmpword |= 0x0400;
2702 break;
2703 default:
2704 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2705 conf->cfg_base);
2706 break;
2707 }
2708 tmpword &= 0xfffd; /* disable LPC COMB */
2709 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2710 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
c1e14a6e
LW		 2711 pci_write_config_word(dev, LPC_EN, tmpword);
2712
08d09997
LW		 2713 /*
2714 * Configure LPC DMA channel
2715 * PCI_DMA_C bits:
2716 * Bit 15-14: DMA channel 7 select
2717 * Bit 13-12: DMA channel 6 select
2718 * Bit 11-10: DMA channel 5 select
2719 * Bit 9-8: Reserved
2720 * Bit 7-6: DMA channel 3 select
2721 * Bit 5-4: DMA channel 2 select
2722 * Bit 3-2: DMA channel 1 select
2723 * Bit 1-0: DMA channel 0 select
2724 * 00 = Reserved value
2725 * 01 = PC/PCI DMA
2726 * 10 = Reserved value
2727 * 11 = LPC I/F DMA
2728 */
2729 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2730 switch(conf->fir_dma) {
2731 case 0x07:
2732 tmpword |= 0xc000;
2733 break;
2734 case 0x06:
2735 tmpword |= 0x3000;
2736 break;
2737 case 0x05:
2738 tmpword |= 0x0c00;
2739 break;
2740 case 0x03:
2741 tmpword |= 0x00c0;
2742 break;
2743 case 0x02:
2744 tmpword |= 0x0030;
2745 break;
2746 case 0x01:
2747 tmpword |= 0x000c;
2748 break;
2749 case 0x00:
2750 tmpword |= 0x0003;
2751 break;
2752 default:
2753 break; /* do not change settings */
2754 }
2755 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2756 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2757
2758 /*
2759 * GEN2_DEC bits:
2760 * Bit 15-4: Generic I/O range
2761 * Bit 3-1: reserved (read as 0)
2762 * Bit 0: enable GEN2 range on LPC I/F
2763 */
2764 tmpword = conf->fir_io & 0xfff8;
2765 tmpword |= 0x0001;
2766 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2767 pci_write_config_word(dev, GEN2_DEC, tmpword);
c1e14a6e
LW		 2768
2769 /* Pre-configure chip */
08d09997
LW		 2770 return preconfigure_smsc_chip(conf);
2771}
c1e14a6e 2772
08d09997
LW		 2773/*
2774 * Pre-configure a certain port on the ALi 1533 bridge.
2775 * This is based on reverse-engineering since ALi does not
2776 * provide any data sheet for the 1533 chip.
2777 */
948252cb 2778static void __init preconfigure_ali_port(struct pci_dev *dev,
08d09997
LW		 2779 unsigned short port)
2780{
2781 unsigned char reg;
2782 /* These bits obviously control the different ports */
2783 unsigned char mask;
2784 unsigned char tmpbyte;
2785
2786 switch(port) {
2787 case 0x0130:
2788 case 0x0178:
2789 reg = 0xb0;
2790 mask = 0x80;
2791 break;
2792 case 0x03f8:
2793 reg = 0xb4;
2794 mask = 0x80;
2795 break;
2796 case 0x02f8:
2797 reg = 0xb4;
2798 mask = 0x30;
2799 break;
2800 case 0x02e8:
2801 reg = 0xb4;
2802 mask = 0x08;
2803 break;
2804 default:
2805 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2806 return;
2807 }
2808
2809 pci_read_config_byte(dev, reg, &tmpbyte);
2810 /* Turn on the right bits */
2811 tmpbyte |= mask;
2812 pci_write_config_byte(dev, reg, tmpbyte);
2813 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
c1e14a6e
LW		 2814}
2815
948252cb 2816static int __init preconfigure_through_ali(struct pci_dev *dev,
08d09997
LW		 2817 struct
2818 smsc_ircc_subsystem_configuration
2819 *conf)
c1e14a6e 2820{
08d09997
LW		 2821 /* Configure the two ports on the ALi 1533 */
2822 preconfigure_ali_port(dev, conf->sir_io);
2823 preconfigure_ali_port(dev, conf->fir_io);
2824
2825 /* Pre-configure chip */
2826 return preconfigure_smsc_chip(conf);
c1e14a6e
LW		 2827}
2828
948252cb 2829static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
c1e14a6e
LW		 2830 unsigned short ircc_fir,
2831 unsigned short ircc_sir,
2832 unsigned char ircc_dma,
2833 unsigned char ircc_irq)
2834{
2835 struct pci_dev *dev = NULL;
2836 unsigned short ss_vendor = 0x0000;
2837 unsigned short ss_device = 0x0000;
2838 int ret = 0;
2839
2e4e7a97 2840 for_each_pci_dev(dev) {
948252cb 2841 struct smsc_ircc_subsystem_configuration *conf;
c1e14a6e
LW		 2842
2843 /*
08d09997
LW		 2844 * Cache the subsystem vendor/device:
2845 * some manufacturers fail to set this for all components,
2846 * so we save it in case there is just 0x0000 0x0000 on the
2847 * device we want to check.
c1e14a6e
LW		 2848 */
2849 if (dev->subsystem_vendor != 0x0000U) {
2850 ss_vendor = dev->subsystem_vendor;
2851 ss_device = dev->subsystem_device;
2852 }
2853 conf = subsystem_configurations;
2854 for( ; conf->subvendor; conf++) {
2855 if(conf->vendor == dev->vendor &&
2856 conf->device == dev->device &&
08d09997
LW		 2857 conf->subvendor == ss_vendor &&
2858 /* Sometimes these are cached values */
2859 (conf->subdevice == ss_device ||
2860 conf->subdevice == 0xffff)) {
2861 struct smsc_ircc_subsystem_configuration
2862 tmpconf;
c1e14a6e 2863
08d09997
LW		 2864 memcpy(&tmpconf, conf,
2865 sizeof(struct smsc_ircc_subsystem_configuration));
c1e14a6e 2866
08d09997
LW		 2867 /*
2868 * Override the default values with anything
2869 * passed in as parameter
2870 */
c1e14a6e
LW		 2871 if (ircc_cfg != 0)
2872 tmpconf.cfg_base = ircc_cfg;
2873 if (ircc_fir != 0)
2874 tmpconf.fir_io = ircc_fir;
2875 if (ircc_sir != 0)
2876 tmpconf.sir_io = ircc_sir;
916f11c7 2877 if (ircc_dma != DMA_INVAL)
c1e14a6e 2878 tmpconf.fir_dma = ircc_dma;
916f11c7 2879 if (ircc_irq != IRQ_INVAL)
c1e14a6e
LW		 2880 tmpconf.fir_irq = ircc_irq;
2881
2882 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2883 if (conf->preconfigure)
2884 ret = conf->preconfigure(dev, &tmpconf);
2885 else
2886 ret = -ENODEV;
2887 }
2888 }
c1e14a6e
LW		 2889 }
2890
2891 return ret;
2892}
2893#endif // CONFIG_PCI
2894
1da177e4
LT		 2895/************************************************
2896 *
2897 * Transceivers specific functions
2898 *
2899 ************************************************/
2900
2901
2902/*
2903 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2904 *
2905 * Program transceiver through smsc-ircc ATC circuitry
2906 *
2907 */
2908
2909static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2910{
2911 unsigned long jiffies_now, jiffies_timeout;
98b77773 2912 u8 val;
527b6af4 2913
98b77773
DT		 2914 jiffies_now = jiffies;
2915 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2916
1da177e4
LT		 2917 /* ATC */
2918 register_bank(fir_base, 4);
98b77773
DT		 2919 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2920 fir_base + IRCC_ATC);
2921
2922 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2923 !time_after(jiffies, jiffies_timeout))
2924 /* empty */;
2925
2926 if (val)
a97a6f10 2927 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
98b77773 2928 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2929}
2930
2931/*
2932 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2933 *
2934 * Probe transceiver smsc-ircc ATC circuitry
2935 *
2936 */
2937
2938static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2939{
2940 return 0;
2941}
2942
2943/*
2944 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2945 *
527b6af4 2946 * Set transceiver
1da177e4
LT		 2947 *
2948 */
2949
2950static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2951{
98b77773 2952 u8 fast_mode;
527b6af4 2953
98b77773
DT		 2954 switch (speed) {
2955 default:
2956 case 576000 :
527b6af4 2957 fast_mode = 0;
1da177e4 2958 break;
98b77773
DT		 2959 case 1152000 :
2960 case 4000000 :
1da177e4
LT		 2961 fast_mode = IRCC_LCR_A_FAST;
2962 break;
1da177e4
LT		 2963 }
2964 register_bank(fir_base, 0);
98b77773 2965 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2966}
2967
2968/*
2969 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2970 *
527b6af4 2971 * Probe transceiver
1da177e4
LT		 2972 *
2973 */
2974
2975static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2976{
2977 return 0;
2978}
2979
2980/*
2981 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2982 *
527b6af4 2983 * Set transceiver
1da177e4
LT		 2984 *
2985 */
2986
2987static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2988{
98b77773 2989 u8 fast_mode;
527b6af4 2990
98b77773
DT		 2991 switch (speed) {
2992 default:
2993 case 576000 :
527b6af4 2994 fast_mode = 0;
1da177e4 2995 break;
98b77773
DT		 2996 case 1152000 :
2997 case 4000000 :
1da177e4
LT		 2998 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2999 break;
527b6af4 3000
1da177e4
LT		 3001 }
3002 /* This causes an interrupt */
3003 register_bank(fir_base, 0);
98b77773 3004 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 3005}
3006
3007/*
3008 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3009 *
527b6af4 3010 * Probe transceiver
1da177e4
LT		 3011 *
3012 */
3013
3014static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3015{
3016 return 0;
3017}
3018
3019
3020module_init(smsc_ircc_init);
3021module_exit(smsc_ircc_cleanup);
kernel source for telekom puls (alcatel/mediatek)