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igb: place a pointer to the netdev struct in the ring itself
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
85b430b4 93static void igb_setup_tctl(struct igb_adapter *);
9d5c8243
AK		 94static void igb_setup_rctl(struct igb_adapter *);
95static void igb_clean_all_tx_rings(struct igb_adapter *);
96static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 97static void igb_clean_tx_ring(struct igb_ring *);
98static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 99static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 100static void igb_update_phy_info(unsigned long);
101static void igb_watchdog(unsigned long);
102static void igb_watchdog_task(struct work_struct *);
3b29a56d 103static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
3b29a56d
SH		 104 struct igb_ring *);
105static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
106 struct net_device *);
9d5c8243
AK		 107static struct net_device_stats *igb_get_stats(struct net_device *);
108static int igb_change_mtu(struct net_device *, int);
109static int igb_set_mac(struct net_device *, void *);
68d480c4 110static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 111static irqreturn_t igb_intr(int irq, void *);
112static irqreturn_t igb_intr_msi(int irq, void *);
113static irqreturn_t igb_msix_other(int irq, void *);
047e0030 114static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 115#ifdef CONFIG_IGB_DCA
047e0030 116static void igb_update_dca(struct igb_q_vector *);
fe4506b6 117static void igb_setup_dca(struct igb_adapter *);
421e02f0 118#endif /* CONFIG_IGB_DCA */
047e0030 119static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 120static int igb_poll(struct napi_struct *, int);
047e0030 121static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
3b644cf6 122static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 123static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
124static void igb_tx_timeout(struct net_device *);
125static void igb_reset_task(struct work_struct *);
126static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
127static void igb_vlan_rx_add_vid(struct net_device *, u16);
128static void igb_vlan_rx_kill_vid(struct net_device *, u16);
129static void igb_restore_vlan(struct igb_adapter *);
26ad9178 130static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 131static void igb_ping_all_vfs(struct igb_adapter *);
132static void igb_msg_task(struct igb_adapter *);
133static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 134static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 135static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
136static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 137
c8159b2d
ED		 138static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
139{
140 u32 reg_data;
141
142 reg_data = rd32(E1000_VMOLR(vfn));
143 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 144 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
145 E1000_VMOLR_AUPE | /* Accept untagged packets */
146 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
147 wr32(E1000_VMOLR(vfn), reg_data);
148}
149
150static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
151 int vfn)
152{
153 struct e1000_hw *hw = &adapter->hw;
154 u32 vmolr;
155
ae641bdc
AD		 156 /* if it isn't the PF check to see if VFs are enabled and
157 * increase the size to support vlan tags */
158 if (vfn < adapter->vfs_allocated_count &&
159 adapter->vf_data[vfn].vlans_enabled)
160 size += VLAN_TAG_SIZE;
161
c8159b2d
ED		 162 vmolr = rd32(E1000_VMOLR(vfn));
163 vmolr &= ~E1000_VMOLR_RLPML_MASK;
164 vmolr |= size | E1000_VMOLR_LPE;
165 wr32(E1000_VMOLR(vfn), vmolr);
166
167 return 0;
168}
169
9d5c8243 170#ifdef CONFIG_PM
3fe7c4c9 171static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 172static int igb_resume(struct pci_dev *);
173#endif
174static void igb_shutdown(struct pci_dev *);
421e02f0 175#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 176static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
177static struct notifier_block dca_notifier = {
178 .notifier_call = igb_notify_dca,
179 .next = NULL,
180 .priority = 0
181};
182#endif
9d5c8243
AK		 183#ifdef CONFIG_NET_POLL_CONTROLLER
184/* for netdump / net console */
185static void igb_netpoll(struct net_device *);
186#endif
37680117 187#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 188static unsigned int max_vfs = 0;
189module_param(max_vfs, uint, 0);
190MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
191 "per physical function");
192#endif /* CONFIG_PCI_IOV */
193
9d5c8243
AK		 194static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
195 pci_channel_state_t);
196static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
197static void igb_io_resume(struct pci_dev *);
198
199static struct pci_error_handlers igb_err_handler = {
200 .error_detected = igb_io_error_detected,
201 .slot_reset = igb_io_slot_reset,
202 .resume = igb_io_resume,
203};
204
205
206static struct pci_driver igb_driver = {
207 .name = igb_driver_name,
208 .id_table = igb_pci_tbl,
209 .probe = igb_probe,
210 .remove = __devexit_p(igb_remove),
211#ifdef CONFIG_PM
212 /* Power Managment Hooks */
213 .suspend = igb_suspend,
214 .resume = igb_resume,
215#endif
216 .shutdown = igb_shutdown,
217 .err_handler = &igb_err_handler
218};
219
7dfc16fa
AD		 220static int global_quad_port_a; /* global quad port a indication */
221
9d5c8243
AK		 222MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
223MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_VERSION);
226
38c845c7
PO		 227/**
228 * Scale the NIC clock cycle by a large factor so that
229 * relatively small clock corrections can be added or
230 * substracted at each clock tick. The drawbacks of a
231 * large factor are a) that the clock register overflows
232 * more quickly (not such a big deal) and b) that the
233 * increment per tick has to fit into 24 bits.
234 *
235 * Note that
236 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
237 * IGB_TSYNC_SCALE
238 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
239 *
240 * The base scale factor is intentionally a power of two
241 * so that the division in %struct timecounter can be done with
242 * a shift.
243 */
244#define IGB_TSYNC_SHIFT (19)
245#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
246
247/**
248 * The duration of one clock cycle of the NIC.
249 *
250 * @todo This hard-coded value is part of the specification and might change
251 * in future hardware revisions. Add revision check.
252 */
253#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
254
255#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
256# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
257#endif
258
259/**
260 * igb_read_clock - read raw cycle counter (to be used by time counter)
261 */
262static cycle_t igb_read_clock(const struct cyclecounter *tc)
263{
264 struct igb_adapter *adapter =
265 container_of(tc, struct igb_adapter, cycles);
266 struct e1000_hw *hw = &adapter->hw;
267 u64 stamp;
268
269 stamp = rd32(E1000_SYSTIML);
270 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
271
272 return stamp;
273}
274
9d5c8243
AK		 275#ifdef DEBUG
276/**
277 * igb_get_hw_dev_name - return device name string
278 * used by hardware layer to print debugging information
279 **/
280char *igb_get_hw_dev_name(struct e1000_hw *hw)
281{
282 struct igb_adapter *adapter = hw->back;
283 return adapter->netdev->name;
284}
38c845c7
PO		 285
286/**
287 * igb_get_time_str - format current NIC and system time as string
288 */
289static char *igb_get_time_str(struct igb_adapter *adapter,
290 char buffer[160])
291{
292 cycle_t hw = adapter->cycles.read(&adapter->cycles);
293 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
294 struct timespec sys;
295 struct timespec delta;
296 getnstimeofday(&sys);
297
298 delta = timespec_sub(nic, sys);
299
300 sprintf(buffer,
33af6bcc
PO		 301 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
302 hw,
38c845c7
PO		 303 (long)nic.tv_sec, nic.tv_nsec,
304 (long)sys.tv_sec, sys.tv_nsec,
305 (long)delta.tv_sec, delta.tv_nsec);
306
307 return buffer;
308}
9d5c8243
AK		 309#endif
310
c493ea45
AD		 311/**
312 * igb_desc_unused - calculate if we have unused descriptors
313 **/
314static int igb_desc_unused(struct igb_ring *ring)
315{
316 if (ring->next_to_clean > ring->next_to_use)
317 return ring->next_to_clean - ring->next_to_use - 1;
318
319 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
320}
321
9d5c8243
AK		 322/**
323 * igb_init_module - Driver Registration Routine
324 *
325 * igb_init_module is the first routine called when the driver is
326 * loaded. All it does is register with the PCI subsystem.
327 **/
328static int __init igb_init_module(void)
329{
330 int ret;
331 printk(KERN_INFO "%s - version %s\n",
332 igb_driver_string, igb_driver_version);
333
334 printk(KERN_INFO "%s\n", igb_copyright);
335
7dfc16fa
AD		 336 global_quad_port_a = 0;
337
421e02f0 338#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 339 dca_register_notify(&dca_notifier);
340#endif
bbd98fe4
AD		 341
342 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 343 return ret;
344}
345
346module_init(igb_init_module);
347
348/**
349 * igb_exit_module - Driver Exit Cleanup Routine
350 *
351 * igb_exit_module is called just before the driver is removed
352 * from memory.
353 **/
354static void __exit igb_exit_module(void)
355{
421e02f0 356#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 357 dca_unregister_notify(&dca_notifier);
358#endif
9d5c8243
AK		 359 pci_unregister_driver(&igb_driver);
360}
361
362module_exit(igb_exit_module);
363
26bc19ec
AD		 364#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
365/**
366 * igb_cache_ring_register - Descriptor ring to register mapping
367 * @adapter: board private structure to initialize
368 *
369 * Once we know the feature-set enabled for the device, we'll cache
370 * the register offset the descriptor ring is assigned to.
371 **/
372static void igb_cache_ring_register(struct igb_adapter *adapter)
373{
374 int i;
047e0030 375 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 376
377 switch (adapter->hw.mac.type) {
378 case e1000_82576:
379 /* The queues are allocated for virtualization such that VF 0
380 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
381 * In order to avoid collision we start at the first free queue
382 * and continue consuming queues in the same sequence
383 */
384 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 385 adapter->rx_ring[i].reg_idx = rbase_offset +
386 Q_IDX_82576(i);
26bc19ec 387 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 388 adapter->tx_ring[i].reg_idx = rbase_offset +
389 Q_IDX_82576(i);
26bc19ec
AD		 390 break;
391 case e1000_82575:
392 default:
393 for (i = 0; i < adapter->num_rx_queues; i++)
394 adapter->rx_ring[i].reg_idx = i;
395 for (i = 0; i < adapter->num_tx_queues; i++)
396 adapter->tx_ring[i].reg_idx = i;
397 break;
398 }
399}
400
047e0030
AD		 401static void igb_free_queues(struct igb_adapter *adapter)
402{
403 kfree(adapter->tx_ring);
404 kfree(adapter->rx_ring);
405
406 adapter->tx_ring = NULL;
407 adapter->rx_ring = NULL;
408
409 adapter->num_rx_queues = 0;
410 adapter->num_tx_queues = 0;
411}
412
9d5c8243
AK		 413/**
414 * igb_alloc_queues - Allocate memory for all rings
415 * @adapter: board private structure to initialize
416 *
417 * We allocate one ring per queue at run-time since we don't know the
418 * number of queues at compile-time.
419 **/
420static int igb_alloc_queues(struct igb_adapter *adapter)
421{
422 int i;
423
424 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
425 sizeof(struct igb_ring), GFP_KERNEL);
426 if (!adapter->tx_ring)
047e0030 427 goto err;
9d5c8243
AK		 428
429 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
430 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 431 if (!adapter->rx_ring)
432 goto err;
6eb5a7f1 433
661086df
PWJ		 434 for (i = 0; i < adapter->num_tx_queues; i++) {
435 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 436 ring->count = adapter->tx_ring_count;
661086df 437 ring->queue_index = i;
80785298 438 ring->pdev = adapter->pdev;
e694e964 439 ring->netdev = adapter->netdev;
85ad76b2
AD		 440 /* For 82575, context index must be unique per ring. */
441 if (adapter->hw.mac.type == e1000_82575)
442 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
661086df 443 }
85ad76b2 444
9d5c8243
AK		 445 for (i = 0; i < adapter->num_rx_queues; i++) {
446 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 447 ring->count = adapter->rx_ring_count;
844290e5 448 ring->queue_index = i;
80785298 449 ring->pdev = adapter->pdev;
e694e964 450 ring->netdev = adapter->netdev;
4c844851 451 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 452 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
453 /* set flag indicating ring supports SCTP checksum offload */
454 if (adapter->hw.mac.type >= e1000_82576)
455 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
9d5c8243 456 }
26bc19ec
AD		 457
458 igb_cache_ring_register(adapter);
9d5c8243 459
047e0030 460 return 0;
a88f10ec 461
047e0030
AD		 462err:
463 igb_free_queues(adapter);
d1a8c9e1 464
047e0030 465 return -ENOMEM;
a88f10ec
AD		 466}
467
9d5c8243 468#define IGB_N0_QUEUE -1
047e0030 469static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 470{
471 u32 msixbm = 0;
047e0030 472 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 473 struct e1000_hw *hw = &adapter->hw;
2d064c06 474 u32 ivar, index;
047e0030
AD		 475 int rx_queue = IGB_N0_QUEUE;
476 int tx_queue = IGB_N0_QUEUE;
477
478 if (q_vector->rx_ring)
479 rx_queue = q_vector->rx_ring->reg_idx;
480 if (q_vector->tx_ring)
481 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 482
483 switch (hw->mac.type) {
484 case e1000_82575:
9d5c8243
AK		 485 /* The 82575 assigns vectors using a bitmask, which matches the
486 bitmask for the EICR/EIMS/EIMC registers. To assign one
487 or more queues to a vector, we write the appropriate bits
488 into the MSIXBM register for that vector. */
047e0030 489 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 490 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 491 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 492 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 493 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 494 q_vector->eims_value = msixbm;
2d064c06
AD		 495 break;
496 case e1000_82576:
26bc19ec 497 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 498 Each queue has a single entry in the table to which we write
499 a vector number along with a "valid" bit. Sadly, the layout
500 of the table is somewhat counterintuitive. */
501 if (rx_queue > IGB_N0_QUEUE) {
047e0030 502 index = (rx_queue & 0x7);
2d064c06 503 ivar = array_rd32(E1000_IVAR0, index);
047e0030 504 if (rx_queue < 8) {
26bc19ec
AD		 505 /* vector goes into low byte of register */
506 ivar = ivar & 0xFFFFFF00;
507 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 508 } else {
509 /* vector goes into third byte of register */
510 ivar = ivar & 0xFF00FFFF;
511 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 512 }
2d064c06
AD		 513 array_wr32(E1000_IVAR0, index, ivar);
514 }
515 if (tx_queue > IGB_N0_QUEUE) {
047e0030 516 index = (tx_queue & 0x7);
2d064c06 517 ivar = array_rd32(E1000_IVAR0, index);
047e0030 518 if (tx_queue < 8) {
26bc19ec
AD		 519 /* vector goes into second byte of register */
520 ivar = ivar & 0xFFFF00FF;
521 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 522 } else {
523 /* vector goes into high byte of register */
524 ivar = ivar & 0x00FFFFFF;
525 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 526 }
2d064c06
AD		 527 array_wr32(E1000_IVAR0, index, ivar);
528 }
047e0030 529 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 530 break;
531 default:
532 BUG();
533 break;
534 }
9d5c8243
AK		 535}
536
537/**
538 * igb_configure_msix - Configure MSI-X hardware
539 *
540 * igb_configure_msix sets up the hardware to properly
541 * generate MSI-X interrupts.
542 **/
543static void igb_configure_msix(struct igb_adapter *adapter)
544{
545 u32 tmp;
546 int i, vector = 0;
547 struct e1000_hw *hw = &adapter->hw;
548
549 adapter->eims_enable_mask = 0;
9d5c8243
AK		 550
551 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 552 switch (hw->mac.type) {
553 case e1000_82575:
9d5c8243
AK		 554 tmp = rd32(E1000_CTRL_EXT);
555 /* enable MSI-X PBA support*/
556 tmp |= E1000_CTRL_EXT_PBA_CLR;
557
558 /* Auto-Mask interrupts upon ICR read. */
559 tmp |= E1000_CTRL_EXT_EIAME;
560 tmp |= E1000_CTRL_EXT_IRCA;
561
562 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 563
564 /* enable msix_other interrupt */
565 array_wr32(E1000_MSIXBM(0), vector++,
566 E1000_EIMS_OTHER);
844290e5 567 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 568
2d064c06
AD		 569 break;
570
571 case e1000_82576:
047e0030
AD		 572 /* Turn on MSI-X capability first, or our settings
573 * won't stick. And it will take days to debug. */
574 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
575 E1000_GPIE_PBA | E1000_GPIE_EIAME |
576 E1000_GPIE_NSICR);
577
578 /* enable msix_other interrupt */
579 adapter->eims_other = 1 << vector;
2d064c06 580 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 581
047e0030 582 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 583 break;
584 default:
585 /* do nothing, since nothing else supports MSI-X */
586 break;
587 } /* switch (hw->mac.type) */
047e0030
AD		 588
589 adapter->eims_enable_mask |= adapter->eims_other;
590
591 for (i = 0; i < adapter->num_q_vectors; i++) {
592 struct igb_q_vector *q_vector = adapter->q_vector[i];
593 igb_assign_vector(q_vector, vector++);
594 adapter->eims_enable_mask |= q_vector->eims_value;
595 }
596
9d5c8243
AK		 597 wrfl();
598}
599
600/**
601 * igb_request_msix - Initialize MSI-X interrupts
602 *
603 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
604 * kernel.
605 **/
606static int igb_request_msix(struct igb_adapter *adapter)
607{
608 struct net_device *netdev = adapter->netdev;
047e0030 609 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 610 int i, err = 0, vector = 0;
611
047e0030
AD		 612 err = request_irq(adapter->msix_entries[vector].vector,
613 &igb_msix_other, 0, netdev->name, adapter);
614 if (err)
615 goto out;
616 vector++;
617
618 for (i = 0; i < adapter->num_q_vectors; i++) {
619 struct igb_q_vector *q_vector = adapter->q_vector[i];
620
621 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
622
623 if (q_vector->rx_ring && q_vector->tx_ring)
624 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
625 q_vector->rx_ring->queue_index);
626 else if (q_vector->tx_ring)
627 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
628 q_vector->tx_ring->queue_index);
629 else if (q_vector->rx_ring)
630 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
631 q_vector->rx_ring->queue_index);
9d5c8243 632 else
047e0030
AD		 633 sprintf(q_vector->name, "%s-unused", netdev->name);
634
9d5c8243 635 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 636 &igb_msix_ring, 0, q_vector->name,
637 q_vector);
9d5c8243
AK		 638 if (err)
639 goto out;
9d5c8243
AK		 640 vector++;
641 }
642
9d5c8243
AK		 643 igb_configure_msix(adapter);
644 return 0;
645out:
646 return err;
647}
648
649static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
650{
651 if (adapter->msix_entries) {
652 pci_disable_msix(adapter->pdev);
653 kfree(adapter->msix_entries);
654 adapter->msix_entries = NULL;
047e0030 655 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 656 pci_disable_msi(adapter->pdev);
047e0030 657 }
9d5c8243
AK		 658}
659
047e0030
AD		 660/**
661 * igb_free_q_vectors - Free memory allocated for interrupt vectors
662 * @adapter: board private structure to initialize
663 *
664 * This function frees the memory allocated to the q_vectors. In addition if
665 * NAPI is enabled it will delete any references to the NAPI struct prior
666 * to freeing the q_vector.
667 **/
668static void igb_free_q_vectors(struct igb_adapter *adapter)
669{
670 int v_idx;
671
672 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
673 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
674 adapter->q_vector[v_idx] = NULL;
675 netif_napi_del(&q_vector->napi);
676 kfree(q_vector);
677 }
678 adapter->num_q_vectors = 0;
679}
680
681/**
682 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
683 *
684 * This function resets the device so that it has 0 rx queues, tx queues, and
685 * MSI-X interrupts allocated.
686 */
687static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
688{
689 igb_free_queues(adapter);
690 igb_free_q_vectors(adapter);
691 igb_reset_interrupt_capability(adapter);
692}
9d5c8243
AK		 693
694/**
695 * igb_set_interrupt_capability - set MSI or MSI-X if supported
696 *
697 * Attempt to configure interrupts using the best available
698 * capabilities of the hardware and kernel.
699 **/
700static void igb_set_interrupt_capability(struct igb_adapter *adapter)
701{
702 int err;
703 int numvecs, i;
704
83b7180d 705 /* Number of supported queues. */
83b7180d
AD		 706 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
707 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
708
047e0030
AD		 709 /* start with one vector for every rx queue */
710 numvecs = adapter->num_rx_queues;
711
712 /* if tx handler is seperate add 1 for every tx queue */
713 numvecs += adapter->num_tx_queues;
714
715 /* store the number of vectors reserved for queues */
716 adapter->num_q_vectors = numvecs;
717
718 /* add 1 vector for link status interrupts */
719 numvecs++;
9d5c8243
AK		 720 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
721 GFP_KERNEL);
722 if (!adapter->msix_entries)
723 goto msi_only;
724
725 for (i = 0; i < numvecs; i++)
726 adapter->msix_entries[i].entry = i;
727
728 err = pci_enable_msix(adapter->pdev,
729 adapter->msix_entries,
730 numvecs);
731 if (err == 0)
34a20e89 732 goto out;
9d5c8243
AK		 733
734 igb_reset_interrupt_capability(adapter);
735
736 /* If we can't do MSI-X, try MSI */
737msi_only:
2a3abf6d
AD		 738#ifdef CONFIG_PCI_IOV
739 /* disable SR-IOV for non MSI-X configurations */
740 if (adapter->vf_data) {
741 struct e1000_hw *hw = &adapter->hw;
742 /* disable iov and allow time for transactions to clear */
743 pci_disable_sriov(adapter->pdev);
744 msleep(500);
745
746 kfree(adapter->vf_data);
747 adapter->vf_data = NULL;
748 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
749 msleep(100);
750 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
751 }
752#endif
9d5c8243 753 adapter->num_rx_queues = 1;
661086df 754 adapter->num_tx_queues = 1;
047e0030 755 adapter->num_q_vectors = 1;
9d5c8243 756 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 757 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 758out:
661086df 759 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 760 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 761 return;
762}
763
047e0030
AD		 764/**
765 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
766 * @adapter: board private structure to initialize
767 *
768 * We allocate one q_vector per queue interrupt. If allocation fails we
769 * return -ENOMEM.
770 **/
771static int igb_alloc_q_vectors(struct igb_adapter *adapter)
772{
773 struct igb_q_vector *q_vector;
774 struct e1000_hw *hw = &adapter->hw;
775 int v_idx;
776
777 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
778 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
779 if (!q_vector)
780 goto err_out;
781 q_vector->adapter = adapter;
782 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
783 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
784 q_vector->itr_val = IGB_START_ITR;
785 q_vector->set_itr = 1;
786 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
787 adapter->q_vector[v_idx] = q_vector;
788 }
789 return 0;
790
791err_out:
792 while (v_idx) {
793 v_idx--;
794 q_vector = adapter->q_vector[v_idx];
795 netif_napi_del(&q_vector->napi);
796 kfree(q_vector);
797 adapter->q_vector[v_idx] = NULL;
798 }
799 return -ENOMEM;
800}
801
802static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
803 int ring_idx, int v_idx)
804{
805 struct igb_q_vector *q_vector;
806
807 q_vector = adapter->q_vector[v_idx];
808 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
809 q_vector->rx_ring->q_vector = q_vector;
810 q_vector->itr_val = adapter->itr;
811}
812
813static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
814 int ring_idx, int v_idx)
815{
816 struct igb_q_vector *q_vector;
817
818 q_vector = adapter->q_vector[v_idx];
819 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
820 q_vector->tx_ring->q_vector = q_vector;
821 q_vector->itr_val = adapter->itr;
822}
823
824/**
825 * igb_map_ring_to_vector - maps allocated queues to vectors
826 *
827 * This function maps the recently allocated queues to vectors.
828 **/
829static int igb_map_ring_to_vector(struct igb_adapter *adapter)
830{
831 int i;
832 int v_idx = 0;
833
834 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
835 (adapter->num_q_vectors < adapter->num_tx_queues))
836 return -ENOMEM;
837
838 if (adapter->num_q_vectors >=
839 (adapter->num_rx_queues + adapter->num_tx_queues)) {
840 for (i = 0; i < adapter->num_rx_queues; i++)
841 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
842 for (i = 0; i < adapter->num_tx_queues; i++)
843 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
844 } else {
845 for (i = 0; i < adapter->num_rx_queues; i++) {
846 if (i < adapter->num_tx_queues)
847 igb_map_tx_ring_to_vector(adapter, i, v_idx);
848 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
849 }
850 for (; i < adapter->num_tx_queues; i++)
851 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
852 }
853 return 0;
854}
855
856/**
857 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
858 *
859 * This function initializes the interrupts and allocates all of the queues.
860 **/
861static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
862{
863 struct pci_dev *pdev = adapter->pdev;
864 int err;
865
866 igb_set_interrupt_capability(adapter);
867
868 err = igb_alloc_q_vectors(adapter);
869 if (err) {
870 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
871 goto err_alloc_q_vectors;
872 }
873
874 err = igb_alloc_queues(adapter);
875 if (err) {
876 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
877 goto err_alloc_queues;
878 }
879
880 err = igb_map_ring_to_vector(adapter);
881 if (err) {
882 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
883 goto err_map_queues;
884 }
885
886
887 return 0;
888err_map_queues:
889 igb_free_queues(adapter);
890err_alloc_queues:
891 igb_free_q_vectors(adapter);
892err_alloc_q_vectors:
893 igb_reset_interrupt_capability(adapter);
894 return err;
895}
896
9d5c8243
AK		 897/**
898 * igb_request_irq - initialize interrupts
899 *
900 * Attempts to configure interrupts using the best available
901 * capabilities of the hardware and kernel.
902 **/
903static int igb_request_irq(struct igb_adapter *adapter)
904{
905 struct net_device *netdev = adapter->netdev;
047e0030 906 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 907 struct e1000_hw *hw = &adapter->hw;
908 int err = 0;
909
910 if (adapter->msix_entries) {
911 err = igb_request_msix(adapter);
844290e5 912 if (!err)
9d5c8243 913 goto request_done;
9d5c8243 914 /* fall back to MSI */
047e0030 915 igb_clear_interrupt_scheme(adapter);
9d5c8243 916 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 917 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 918 igb_free_all_tx_resources(adapter);
919 igb_free_all_rx_resources(adapter);
047e0030 920 adapter->num_tx_queues = 1;
9d5c8243 921 adapter->num_rx_queues = 1;
047e0030
AD		 922 adapter->num_q_vectors = 1;
923 err = igb_alloc_q_vectors(adapter);
924 if (err) {
925 dev_err(&pdev->dev,
926 "Unable to allocate memory for vectors\n");
927 goto request_done;
928 }
929 err = igb_alloc_queues(adapter);
930 if (err) {
931 dev_err(&pdev->dev,
932 "Unable to allocate memory for queues\n");
933 igb_free_q_vectors(adapter);
934 goto request_done;
935 }
936 igb_setup_all_tx_resources(adapter);
937 igb_setup_all_rx_resources(adapter);
844290e5 938 } else {
2d064c06
AD		 939 switch (hw->mac.type) {
940 case e1000_82575:
941 wr32(E1000_MSIXBM(0),
047e0030
AD		 942 (E1000_EICR_RX_QUEUE0 |
943 E1000_EICR_TX_QUEUE0 |
944 E1000_EIMS_OTHER));
2d064c06
AD		 945 break;
946 case e1000_82576:
947 wr32(E1000_IVAR0, E1000_IVAR_VALID);
948 break;
949 default:
950 break;
951 }
9d5c8243 952 }
844290e5 953
7dfc16fa 954 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 955 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 956 netdev->name, adapter);
9d5c8243
AK		 957 if (!err)
958 goto request_done;
047e0030 959
9d5c8243
AK		 960 /* fall back to legacy interrupts */
961 igb_reset_interrupt_capability(adapter);
7dfc16fa 962 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 963 }
964
965 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 966 netdev->name, adapter);
9d5c8243 967
6cb5e577 968 if (err)
9d5c8243
AK		 969 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
970 err);
9d5c8243
AK		 971
972request_done:
973 return err;
974}
975
976static void igb_free_irq(struct igb_adapter *adapter)
977{
9d5c8243
AK		 978 if (adapter->msix_entries) {
979 int vector = 0, i;
980
047e0030 981 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 982
047e0030
AD		 983 for (i = 0; i < adapter->num_q_vectors; i++) {
984 struct igb_q_vector *q_vector = adapter->q_vector[i];
985 free_irq(adapter->msix_entries[vector++].vector,
986 q_vector);
987 }
988 } else {
989 free_irq(adapter->pdev->irq, adapter);
9d5c8243 990 }
9d5c8243
AK		 991}
992
993/**
994 * igb_irq_disable - Mask off interrupt generation on the NIC
995 * @adapter: board private structure
996 **/
997static void igb_irq_disable(struct igb_adapter *adapter)
998{
999 struct e1000_hw *hw = &adapter->hw;
1000
1001 if (adapter->msix_entries) {
2dfd1212
AD		 1002 u32 regval = rd32(E1000_EIAM);
1003 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1004 wr32(E1000_EIMC, adapter->eims_enable_mask);
1005 regval = rd32(E1000_EIAC);
1006 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1007 }
844290e5
PW		 1008
1009 wr32(E1000_IAM, 0);
9d5c8243
AK		 1010 wr32(E1000_IMC, ~0);
1011 wrfl();
1012 synchronize_irq(adapter->pdev->irq);
1013}
1014
1015/**
1016 * igb_irq_enable - Enable default interrupt generation settings
1017 * @adapter: board private structure
1018 **/
1019static void igb_irq_enable(struct igb_adapter *adapter)
1020{
1021 struct e1000_hw *hw = &adapter->hw;
1022
1023 if (adapter->msix_entries) {
2dfd1212
AD		 1024 u32 regval = rd32(E1000_EIAC);
1025 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1026 regval = rd32(E1000_EIAM);
1027 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1028 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 1029 if (adapter->vfs_allocated_count)
1030 wr32(E1000_MBVFIMR, 0xFF);
1031 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
1032 E1000_IMS_DOUTSYNC));
844290e5
PW		 1033 } else {
1034 wr32(E1000_IMS, IMS_ENABLE_MASK);
1035 wr32(E1000_IAM, IMS_ENABLE_MASK);
1036 }
9d5c8243
AK		 1037}
1038
1039static void igb_update_mng_vlan(struct igb_adapter *adapter)
1040{
1041 struct net_device *netdev = adapter->netdev;
1042 u16 vid = adapter->hw.mng_cookie.vlan_id;
1043 u16 old_vid = adapter->mng_vlan_id;
1044 if (adapter->vlgrp) {
1045 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
1046 if (adapter->hw.mng_cookie.status &
1047 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1048 igb_vlan_rx_add_vid(netdev, vid);
1049 adapter->mng_vlan_id = vid;
1050 } else
1051 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1052
1053 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1054 (vid != old_vid) &&
1055 !vlan_group_get_device(adapter->vlgrp, old_vid))
1056 igb_vlan_rx_kill_vid(netdev, old_vid);
1057 } else
1058 adapter->mng_vlan_id = vid;
1059 }
1060}
1061
1062/**
1063 * igb_release_hw_control - release control of the h/w to f/w
1064 * @adapter: address of board private structure
1065 *
1066 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1067 * For ASF and Pass Through versions of f/w this means that the
1068 * driver is no longer loaded.
1069 *
1070 **/
1071static void igb_release_hw_control(struct igb_adapter *adapter)
1072{
1073 struct e1000_hw *hw = &adapter->hw;
1074 u32 ctrl_ext;
1075
1076 /* Let firmware take over control of h/w */
1077 ctrl_ext = rd32(E1000_CTRL_EXT);
1078 wr32(E1000_CTRL_EXT,
1079 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1080}
1081
1082
1083/**
1084 * igb_get_hw_control - get control of the h/w from f/w
1085 * @adapter: address of board private structure
1086 *
1087 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1088 * For ASF and Pass Through versions of f/w this means that
1089 * the driver is loaded.
1090 *
1091 **/
1092static void igb_get_hw_control(struct igb_adapter *adapter)
1093{
1094 struct e1000_hw *hw = &adapter->hw;
1095 u32 ctrl_ext;
1096
1097 /* Let firmware know the driver has taken over */
1098 ctrl_ext = rd32(E1000_CTRL_EXT);
1099 wr32(E1000_CTRL_EXT,
1100 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1101}
1102
9d5c8243
AK		 1103/**
1104 * igb_configure - configure the hardware for RX and TX
1105 * @adapter: private board structure
1106 **/
1107static void igb_configure(struct igb_adapter *adapter)
1108{
1109 struct net_device *netdev = adapter->netdev;
1110 int i;
1111
1112 igb_get_hw_control(adapter);
ff41f8dc 1113 igb_set_rx_mode(netdev);
9d5c8243
AK		 1114
1115 igb_restore_vlan(adapter);
9d5c8243 1116
85b430b4 1117 igb_setup_tctl(adapter);
9d5c8243 1118 igb_setup_rctl(adapter);
85b430b4
AD		 1119
1120 igb_configure_tx(adapter);
9d5c8243 1121 igb_configure_rx(adapter);
662d7205
AD		 1122
1123 igb_rx_fifo_flush_82575(&adapter->hw);
1124
c493ea45 1125 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1126 * at least 1 descriptor unused to make sure
1127 * next_to_use != next_to_clean */
1128 for (i = 0; i < adapter->num_rx_queues; i++) {
1129 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1130 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1131 }
1132
1133
1134 adapter->tx_queue_len = netdev->tx_queue_len;
1135}
1136
1137
1138/**
1139 * igb_up - Open the interface and prepare it to handle traffic
1140 * @adapter: board private structure
1141 **/
1142
1143int igb_up(struct igb_adapter *adapter)
1144{
1145 struct e1000_hw *hw = &adapter->hw;
1146 int i;
1147
1148 /* hardware has been reset, we need to reload some things */
1149 igb_configure(adapter);
1150
1151 clear_bit(__IGB_DOWN, &adapter->state);
1152
047e0030
AD		 1153 for (i = 0; i < adapter->num_q_vectors; i++) {
1154 struct igb_q_vector *q_vector = adapter->q_vector[i];
1155 napi_enable(&q_vector->napi);
1156 }
844290e5 1157 if (adapter->msix_entries)
9d5c8243 1158 igb_configure_msix(adapter);
9d5c8243 1159
4ae196df 1160 igb_vmm_control(adapter);
e1739522
AD		 1161 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1162
9d5c8243
AK		 1163 /* Clear any pending interrupts. */
1164 rd32(E1000_ICR);
1165 igb_irq_enable(adapter);
1166
4cb9be7a
JB		 1167 netif_tx_start_all_queues(adapter->netdev);
1168
9d5c8243
AK		 1169 /* Fire a link change interrupt to start the watchdog. */
1170 wr32(E1000_ICS, E1000_ICS_LSC);
1171 return 0;
1172}
1173
1174void igb_down(struct igb_adapter *adapter)
1175{
1176 struct e1000_hw *hw = &adapter->hw;
1177 struct net_device *netdev = adapter->netdev;
1178 u32 tctl, rctl;
1179 int i;
1180
1181 /* signal that we're down so the interrupt handler does not
1182 * reschedule our watchdog timer */
1183 set_bit(__IGB_DOWN, &adapter->state);
1184
1185 /* disable receives in the hardware */
1186 rctl = rd32(E1000_RCTL);
1187 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1188 /* flush and sleep below */
1189
fd2ea0a7 1190 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1191
1192 /* disable transmits in the hardware */
1193 tctl = rd32(E1000_TCTL);
1194 tctl &= ~E1000_TCTL_EN;
1195 wr32(E1000_TCTL, tctl);
1196 /* flush both disables and wait for them to finish */
1197 wrfl();
1198 msleep(10);
1199
047e0030
AD		 1200 for (i = 0; i < adapter->num_q_vectors; i++) {
1201 struct igb_q_vector *q_vector = adapter->q_vector[i];
1202 napi_disable(&q_vector->napi);
1203 }
9d5c8243 1204
9d5c8243
AK		 1205 igb_irq_disable(adapter);
1206
1207 del_timer_sync(&adapter->watchdog_timer);
1208 del_timer_sync(&adapter->phy_info_timer);
1209
1210 netdev->tx_queue_len = adapter->tx_queue_len;
1211 netif_carrier_off(netdev);
04fe6358
AD		 1212
1213 /* record the stats before reset*/
1214 igb_update_stats(adapter);
1215
9d5c8243
AK		 1216 adapter->link_speed = 0;
1217 adapter->link_duplex = 0;
1218
3023682e
JK		 1219 if (!pci_channel_offline(adapter->pdev))
1220 igb_reset(adapter);
9d5c8243
AK		 1221 igb_clean_all_tx_rings(adapter);
1222 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1223#ifdef CONFIG_IGB_DCA
1224
1225 /* since we reset the hardware DCA settings were cleared */
1226 igb_setup_dca(adapter);
1227#endif
9d5c8243
AK		 1228}
1229
1230void igb_reinit_locked(struct igb_adapter *adapter)
1231{
1232 WARN_ON(in_interrupt());
1233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1234 msleep(1);
1235 igb_down(adapter);
1236 igb_up(adapter);
1237 clear_bit(__IGB_RESETTING, &adapter->state);
1238}
1239
1240void igb_reset(struct igb_adapter *adapter)
1241{
1242 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1243 struct e1000_mac_info *mac = &hw->mac;
1244 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1245 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1246 u16 hwm;
1247
1248 /* Repartition Pba for greater than 9k mtu
1249 * To take effect CTRL.RST is required.
1250 */
fa4dfae0
AD		 1251 switch (mac->type) {
1252 case e1000_82576:
2d064c06 1253 pba = E1000_PBA_64K;
fa4dfae0
AD		 1254 break;
1255 case e1000_82575:
1256 default:
1257 pba = E1000_PBA_34K;
1258 break;
2d064c06 1259 }
9d5c8243 1260
2d064c06
AD		 1261 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1262 (mac->type < e1000_82576)) {
9d5c8243
AK		 1263 /* adjust PBA for jumbo frames */
1264 wr32(E1000_PBA, pba);
1265
1266 /* To maintain wire speed transmits, the Tx FIFO should be
1267 * large enough to accommodate two full transmit packets,
1268 * rounded up to the next 1KB and expressed in KB. Likewise,
1269 * the Rx FIFO should be large enough to accommodate at least
1270 * one full receive packet and is similarly rounded up and
1271 * expressed in KB. */
1272 pba = rd32(E1000_PBA);
1273 /* upper 16 bits has Tx packet buffer allocation size in KB */
1274 tx_space = pba >> 16;
1275 /* lower 16 bits has Rx packet buffer allocation size in KB */
1276 pba &= 0xffff;
1277 /* the tx fifo also stores 16 bytes of information about the tx
1278 * but don't include ethernet FCS because hardware appends it */
1279 min_tx_space = (adapter->max_frame_size +
85e8d004 1280 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1281 ETH_FCS_LEN) * 2;
1282 min_tx_space = ALIGN(min_tx_space, 1024);
1283 min_tx_space >>= 10;
1284 /* software strips receive CRC, so leave room for it */
1285 min_rx_space = adapter->max_frame_size;
1286 min_rx_space = ALIGN(min_rx_space, 1024);
1287 min_rx_space >>= 10;
1288
1289 /* If current Tx allocation is less than the min Tx FIFO size,
1290 * and the min Tx FIFO size is less than the current Rx FIFO
1291 * allocation, take space away from current Rx allocation */
1292 if (tx_space < min_tx_space &&
1293 ((min_tx_space - tx_space) < pba)) {
1294 pba = pba - (min_tx_space - tx_space);
1295
1296 /* if short on rx space, rx wins and must trump tx
1297 * adjustment */
1298 if (pba < min_rx_space)
1299 pba = min_rx_space;
1300 }
2d064c06 1301 wr32(E1000_PBA, pba);
9d5c8243 1302 }
9d5c8243
AK		 1303
1304 /* flow control settings */
1305 /* The high water mark must be low enough to fit one full frame
1306 * (or the size used for early receive) above it in the Rx FIFO.
1307 * Set it to the lower of:
1308 * - 90% of the Rx FIFO size, or
1309 * - the full Rx FIFO size minus one full frame */
1310 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1311 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1312
2d064c06
AD		 1313 if (mac->type < e1000_82576) {
1314 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1315 fc->low_water = fc->high_water - 8;
1316 } else {
1317 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1318 fc->low_water = fc->high_water - 16;
1319 }
9d5c8243
AK		 1320 fc->pause_time = 0xFFFF;
1321 fc->send_xon = 1;
0cce119a 1322 fc->current_mode = fc->requested_mode;
9d5c8243 1323
4ae196df
AD		 1324 /* disable receive for all VFs and wait one second */
1325 if (adapter->vfs_allocated_count) {
1326 int i;
1327 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1328 adapter->vf_data[i].clear_to_send = false;
1329
1330 /* ping all the active vfs to let them know we are going down */
1331 igb_ping_all_vfs(adapter);
1332
1333 /* disable transmits and receives */
1334 wr32(E1000_VFRE, 0);
1335 wr32(E1000_VFTE, 0);
1336 }
1337
9d5c8243
AK		 1338 /* Allow time for pending master requests to run */
1339 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1340 wr32(E1000_WUC, 0);
1341
1342 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1343 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1344
1345 igb_update_mng_vlan(adapter);
1346
1347 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1348 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1349
1350 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1351 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1352}
1353
2e5c6922
SH		 1354static const struct net_device_ops igb_netdev_ops = {
1355 .ndo_open = igb_open,
1356 .ndo_stop = igb_close,
00829823 1357 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1358 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1359 .ndo_set_rx_mode = igb_set_rx_mode,
1360 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1361 .ndo_set_mac_address = igb_set_mac,
1362 .ndo_change_mtu = igb_change_mtu,
1363 .ndo_do_ioctl = igb_ioctl,
1364 .ndo_tx_timeout = igb_tx_timeout,
1365 .ndo_validate_addr = eth_validate_addr,
1366 .ndo_vlan_rx_register = igb_vlan_rx_register,
1367 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1368 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1369#ifdef CONFIG_NET_POLL_CONTROLLER
1370 .ndo_poll_controller = igb_netpoll,
1371#endif
1372};
1373
9d5c8243
AK		 1374/**
1375 * igb_probe - Device Initialization Routine
1376 * @pdev: PCI device information struct
1377 * @ent: entry in igb_pci_tbl
1378 *
1379 * Returns 0 on success, negative on failure
1380 *
1381 * igb_probe initializes an adapter identified by a pci_dev structure.
1382 * The OS initialization, configuring of the adapter private structure,
1383 * and a hardware reset occur.
1384 **/
1385static int __devinit igb_probe(struct pci_dev *pdev,
1386 const struct pci_device_id *ent)
1387{
1388 struct net_device *netdev;
1389 struct igb_adapter *adapter;
1390 struct e1000_hw *hw;
1391 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1392 unsigned long mmio_start, mmio_len;
2d6a5e95 1393 int err, pci_using_dac;
682337fe 1394 u16 eeprom_data = 0;
9d5c8243
AK		 1395 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1396 u32 part_num;
1397
aed5dec3 1398 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1399 if (err)
1400 return err;
1401
1402 pci_using_dac = 0;
6a35528a 1403 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1404 if (!err) {
6a35528a 1405 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1406 if (!err)
1407 pci_using_dac = 1;
1408 } else {
284901a9 1409 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1410 if (err) {
284901a9 1411 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1412 if (err) {
1413 dev_err(&pdev->dev, "No usable DMA "
1414 "configuration, aborting\n");
1415 goto err_dma;
1416 }
1417 }
1418 }
1419
aed5dec3
AD		 1420 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1421 IORESOURCE_MEM),
1422 igb_driver_name);
9d5c8243
AK		 1423 if (err)
1424 goto err_pci_reg;
1425
19d5afd4 1426 pci_enable_pcie_error_reporting(pdev);
40a914fa 1427
9d5c8243 1428 pci_set_master(pdev);
c682fc23 1429 pci_save_state(pdev);
9d5c8243
AK		 1430
1431 err = -ENOMEM;
1bfaf07b
AD		 1432 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1433 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1434 if (!netdev)
1435 goto err_alloc_etherdev;
1436
1437 SET_NETDEV_DEV(netdev, &pdev->dev);
1438
1439 pci_set_drvdata(pdev, netdev);
1440 adapter = netdev_priv(netdev);
1441 adapter->netdev = netdev;
1442 adapter->pdev = pdev;
1443 hw = &adapter->hw;
1444 hw->back = adapter;
1445 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1446
1447 mmio_start = pci_resource_start(pdev, 0);
1448 mmio_len = pci_resource_len(pdev, 0);
1449
1450 err = -EIO;
28b0759c
AD		 1451 hw->hw_addr = ioremap(mmio_start, mmio_len);
1452 if (!hw->hw_addr)
9d5c8243
AK		 1453 goto err_ioremap;
1454
2e5c6922 1455 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1456 igb_set_ethtool_ops(netdev);
9d5c8243 1457 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1458
1459 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1460
1461 netdev->mem_start = mmio_start;
1462 netdev->mem_end = mmio_start + mmio_len;
1463
9d5c8243
AK		 1464 /* PCI config space info */
1465 hw->vendor_id = pdev->vendor;
1466 hw->device_id = pdev->device;
1467 hw->revision_id = pdev->revision;
1468 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1469 hw->subsystem_device_id = pdev->subsystem_device;
1470
1471 /* setup the private structure */
1472 hw->back = adapter;
1473 /* Copy the default MAC, PHY and NVM function pointers */
1474 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1475 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1476 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1477 /* Initialize skew-specific constants */
1478 err = ei->get_invariants(hw);
1479 if (err)
450c87c8 1480 goto err_sw_init;
9d5c8243 1481
2a3abf6d
AD		 1482#ifdef CONFIG_PCI_IOV
1483 /* since iov functionality isn't critical to base device function we
1484 * can accept failure. If it fails we don't allow iov to be enabled */
1485 if (hw->mac.type == e1000_82576) {
1486 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1487 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1488 int i;
1489 unsigned char mac_addr[ETH_ALEN];
1490
9ca046d5 1491 if (num_vfs) {
2a3abf6d
AD		 1492 adapter->vf_data = kcalloc(num_vfs,
1493 sizeof(struct vf_data_storage),
1494 GFP_KERNEL);
9ca046d5
AD		 1495 if (!adapter->vf_data) {
1496 dev_err(&pdev->dev,
1497 "Could not allocate VF private data - "
1498 "IOV enable failed\n");
2a3abf6d 1499 } else {
9ca046d5
AD		 1500 err = pci_enable_sriov(pdev, num_vfs);
1501 if (!err) {
1502 adapter->vfs_allocated_count = num_vfs;
1503 dev_info(&pdev->dev,
1504 "%d vfs allocated\n",
1505 num_vfs);
1506 for (i = 0;
1507 i < adapter->vfs_allocated_count;
1508 i++) {
1509 random_ether_addr(mac_addr);
1510 igb_set_vf_mac(adapter, i,
1511 mac_addr);
1512 }
1513 } else {
1514 kfree(adapter->vf_data);
1515 adapter->vf_data = NULL;
1516 }
2a3abf6d
AD		 1517 }
1518 }
1519 }
1520
1521#endif
450c87c8 1522 /* setup the private structure */
9d5c8243
AK		 1523 err = igb_sw_init(adapter);
1524 if (err)
1525 goto err_sw_init;
1526
1527 igb_get_bus_info_pcie(hw);
1528
1529 hw->phy.autoneg_wait_to_complete = false;
1530 hw->mac.adaptive_ifs = true;
1531
1532 /* Copper options */
1533 if (hw->phy.media_type == e1000_media_type_copper) {
1534 hw->phy.mdix = AUTO_ALL_MODES;
1535 hw->phy.disable_polarity_correction = false;
1536 hw->phy.ms_type = e1000_ms_hw_default;
1537 }
1538
1539 if (igb_check_reset_block(hw))
1540 dev_info(&pdev->dev,
1541 "PHY reset is blocked due to SOL/IDER session.\n");
1542
1543 netdev->features = NETIF_F_SG |
7d8eb29e 1544 NETIF_F_IP_CSUM |
9d5c8243
AK		 1545 NETIF_F_HW_VLAN_TX |
1546 NETIF_F_HW_VLAN_RX |
1547 NETIF_F_HW_VLAN_FILTER;
1548
7d8eb29e 1549 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1550 netdev->features |= NETIF_F_TSO;
9d5c8243 1551 netdev->features |= NETIF_F_TSO6;
48f29ffc 1552
5c0999b7 1553 netdev->features |= NETIF_F_GRO;
d3352520 1554
48f29ffc
JK		 1555 netdev->vlan_features |= NETIF_F_TSO;
1556 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1557 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1558 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1559 netdev->vlan_features |= NETIF_F_SG;
1560
9d5c8243
AK		 1561 if (pci_using_dac)
1562 netdev->features |= NETIF_F_HIGHDMA;
1563
b9473560
JB		 1564 if (adapter->hw.mac.type == e1000_82576)
1565 netdev->features |= NETIF_F_SCTP_CSUM;
1566
9d5c8243
AK		 1567 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1568
1569 /* before reading the NVM, reset the controller to put the device in a
1570 * known good starting state */
1571 hw->mac.ops.reset_hw(hw);
1572
1573 /* make sure the NVM is good */
1574 if (igb_validate_nvm_checksum(hw) < 0) {
1575 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1576 err = -EIO;
1577 goto err_eeprom;
1578 }
1579
1580 /* copy the MAC address out of the NVM */
1581 if (hw->mac.ops.read_mac_addr(hw))
1582 dev_err(&pdev->dev, "NVM Read Error\n");
1583
1584 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1585 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1586
1587 if (!is_valid_ether_addr(netdev->perm_addr)) {
1588 dev_err(&pdev->dev, "Invalid MAC Address\n");
1589 err = -EIO;
1590 goto err_eeprom;
1591 }
1592
0e340485
AD		 1593 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1594 (unsigned long) adapter);
1595 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1596 (unsigned long) adapter);
9d5c8243
AK		 1597
1598 INIT_WORK(&adapter->reset_task, igb_reset_task);
1599 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1600
450c87c8 1601 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1602 adapter->fc_autoneg = true;
1603 hw->mac.autoneg = true;
1604 hw->phy.autoneg_advertised = 0x2f;
1605
0cce119a
AD		 1606 hw->fc.requested_mode = e1000_fc_default;
1607 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1608
cbd347ad 1609 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1610 adapter->itr = IGB_START_ITR;
1611
1612 igb_validate_mdi_setting(hw);
1613
9d5c8243
AK		 1614 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1615 * enable the ACPI Magic Packet filter
1616 */
1617
a2cf8b6c 1618 if (hw->bus.func == 0)
312c75ae 1619 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1620 else if (hw->bus.func == 1)
1621 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1622
1623 if (eeprom_data & eeprom_apme_mask)
1624 adapter->eeprom_wol |= E1000_WUFC_MAG;
1625
1626 /* now that we have the eeprom settings, apply the special cases where
1627 * the eeprom may be wrong or the board simply won't support wake on
1628 * lan on a particular port */
1629 switch (pdev->device) {
1630 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1631 adapter->eeprom_wol = 0;
1632 break;
1633 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1634 case E1000_DEV_ID_82576_FIBER:
1635 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1636 /* Wake events only supported on port A for dual fiber
1637 * regardless of eeprom setting */
1638 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1639 adapter->eeprom_wol = 0;
1640 break;
c8ea5ea9
AD		 1641 case E1000_DEV_ID_82576_QUAD_COPPER:
1642 /* if quad port adapter, disable WoL on all but port A */
1643 if (global_quad_port_a != 0)
1644 adapter->eeprom_wol = 0;
1645 else
1646 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1647 /* Reset for multiple quad port adapters */
1648 if (++global_quad_port_a == 4)
1649 global_quad_port_a = 0;
1650 break;
9d5c8243
AK		 1651 }
1652
1653 /* initialize the wol settings based on the eeprom settings */
1654 adapter->wol = adapter->eeprom_wol;
e1b86d84 1655 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1656
1657 /* reset the hardware with the new settings */
1658 igb_reset(adapter);
1659
1660 /* let the f/w know that the h/w is now under the control of the
1661 * driver. */
1662 igb_get_hw_control(adapter);
1663
9d5c8243
AK		 1664 strcpy(netdev->name, "eth%d");
1665 err = register_netdev(netdev);
1666 if (err)
1667 goto err_register;
1668
b168dfc5
JB		 1669 /* carrier off reporting is important to ethtool even BEFORE open */
1670 netif_carrier_off(netdev);
1671
421e02f0 1672#ifdef CONFIG_IGB_DCA
bbd98fe4 1673 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1674 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1675 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1676 igb_setup_dca(adapter);
1677 }
1678#endif
1679
38c845c7
PO		 1680 /*
1681 * Initialize hardware timer: we keep it running just in case
1682 * that some program needs it later on.
1683 */
1684 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1685 adapter->cycles.read = igb_read_clock;
1686 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1687 adapter->cycles.mult = 1;
1688 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1689 wr32(E1000_TIMINCA,
1690 (1<<24) |
1691 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1692#if 0
1693 /*
1694 * Avoid rollover while we initialize by resetting the time counter.
1695 */
1696 wr32(E1000_SYSTIML, 0x00000000);
1697 wr32(E1000_SYSTIMH, 0x00000000);
1698#else
1699 /*
1700 * Set registers so that rollover occurs soon to test this.
1701 */
1702 wr32(E1000_SYSTIML, 0x00000000);
1703 wr32(E1000_SYSTIMH, 0xFF800000);
1704#endif
1705 wrfl();
1706 timecounter_init(&adapter->clock,
1707 &adapter->cycles,
1708 ktime_to_ns(ktime_get_real()));
1709
33af6bcc
PO		 1710 /*
1711 * Synchronize our NIC clock against system wall clock. NIC
1712 * time stamp reading requires ~3us per sample, each sample
1713 * was pretty stable even under load => only require 10
1714 * samples for each offset comparison.
1715 */
1716 memset(&adapter->compare, 0, sizeof(adapter->compare));
1717 adapter->compare.source = &adapter->clock;
1718 adapter->compare.target = ktime_get_real;
1719 adapter->compare.num_samples = 10;
1720 timecompare_update(&adapter->compare, 0);
1721
38c845c7
PO		 1722#ifdef DEBUG
1723 {
1724 char buffer[160];
1725 printk(KERN_DEBUG
1726 "igb: %s: hw %p initialized timer\n",
1727 igb_get_time_str(adapter, buffer),
1728 &adapter->hw);
1729 }
1730#endif
1731
9d5c8243
AK		 1732 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1733 /* print bus type/speed/width info */
7c510e4b 1734 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1735 netdev->name,
1736 ((hw->bus.speed == e1000_bus_speed_2500)
1737 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1738 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1739 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1740 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1741 "unknown"),
7c510e4b 1742 netdev->dev_addr);
9d5c8243
AK		 1743
1744 igb_read_part_num(hw, &part_num);
1745 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1746 (part_num >> 8), (part_num & 0xff));
1747
1748 dev_info(&pdev->dev,
1749 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1750 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1751 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1752 adapter->num_rx_queues, adapter->num_tx_queues);
1753
9d5c8243
AK		 1754 return 0;
1755
1756err_register:
1757 igb_release_hw_control(adapter);
1758err_eeprom:
1759 if (!igb_check_reset_block(hw))
f5f4cf08 1760 igb_reset_phy(hw);
9d5c8243
AK		 1761
1762 if (hw->flash_address)
1763 iounmap(hw->flash_address);
9d5c8243 1764err_sw_init:
047e0030 1765 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1766 iounmap(hw->hw_addr);
1767err_ioremap:
1768 free_netdev(netdev);
1769err_alloc_etherdev:
aed5dec3
AD		 1770 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1771 IORESOURCE_MEM));
9d5c8243
AK		 1772err_pci_reg:
1773err_dma:
1774 pci_disable_device(pdev);
1775 return err;
1776}
1777
1778/**
1779 * igb_remove - Device Removal Routine
1780 * @pdev: PCI device information struct
1781 *
1782 * igb_remove is called by the PCI subsystem to alert the driver
1783 * that it should release a PCI device. The could be caused by a
1784 * Hot-Plug event, or because the driver is going to be removed from
1785 * memory.
1786 **/
1787static void __devexit igb_remove(struct pci_dev *pdev)
1788{
1789 struct net_device *netdev = pci_get_drvdata(pdev);
1790 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1791 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1792
1793 /* flush_scheduled work may reschedule our watchdog task, so
1794 * explicitly disable watchdog tasks from being rescheduled */
1795 set_bit(__IGB_DOWN, &adapter->state);
1796 del_timer_sync(&adapter->watchdog_timer);
1797 del_timer_sync(&adapter->phy_info_timer);
1798
1799 flush_scheduled_work();
1800
421e02f0 1801#ifdef CONFIG_IGB_DCA
7dfc16fa 1802 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1803 dev_info(&pdev->dev, "DCA disabled\n");
1804 dca_remove_requester(&pdev->dev);
7dfc16fa 1805 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1806 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1807 }
1808#endif
1809
9d5c8243
AK		 1810 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1811 * would have already happened in close and is redundant. */
1812 igb_release_hw_control(adapter);
1813
1814 unregister_netdev(netdev);
1815
f5f4cf08
AD		 1816 if (!igb_check_reset_block(&adapter->hw))
1817 igb_reset_phy(&adapter->hw);
9d5c8243 1818
047e0030 1819 igb_clear_interrupt_scheme(adapter);
9d5c8243 1820
37680117
AD		 1821#ifdef CONFIG_PCI_IOV
1822 /* reclaim resources allocated to VFs */
1823 if (adapter->vf_data) {
1824 /* disable iov and allow time for transactions to clear */
1825 pci_disable_sriov(pdev);
1826 msleep(500);
1827
1828 kfree(adapter->vf_data);
1829 adapter->vf_data = NULL;
1830 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1831 msleep(100);
1832 dev_info(&pdev->dev, "IOV Disabled\n");
1833 }
1834#endif
28b0759c
AD		 1835 iounmap(hw->hw_addr);
1836 if (hw->flash_address)
1837 iounmap(hw->flash_address);
aed5dec3
AD		 1838 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1839 IORESOURCE_MEM));
9d5c8243
AK		 1840
1841 free_netdev(netdev);
1842
19d5afd4 1843 pci_disable_pcie_error_reporting(pdev);
40a914fa 1844
9d5c8243
AK		 1845 pci_disable_device(pdev);
1846}
1847
1848/**
1849 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1850 * @adapter: board private structure to initialize
1851 *
1852 * igb_sw_init initializes the Adapter private data structure.
1853 * Fields are initialized based on PCI device information and
1854 * OS network device settings (MTU size).
1855 **/
1856static int __devinit igb_sw_init(struct igb_adapter *adapter)
1857{
1858 struct e1000_hw *hw = &adapter->hw;
1859 struct net_device *netdev = adapter->netdev;
1860 struct pci_dev *pdev = adapter->pdev;
1861
1862 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1863
68fd9910
AD		 1864 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1865 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1866 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1867 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1868
661086df
PWJ		 1869 /* This call may decrease the number of queues depending on
1870 * interrupt mode. */
047e0030 1871 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1872 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1873 return -ENOMEM;
1874 }
1875
1876 /* Explicitly disable IRQ since the NIC can be in any state. */
1877 igb_irq_disable(adapter);
1878
1879 set_bit(__IGB_DOWN, &adapter->state);
1880 return 0;
1881}
1882
1883/**
1884 * igb_open - Called when a network interface is made active
1885 * @netdev: network interface device structure
1886 *
1887 * Returns 0 on success, negative value on failure
1888 *
1889 * The open entry point is called when a network interface is made
1890 * active by the system (IFF_UP). At this point all resources needed
1891 * for transmit and receive operations are allocated, the interrupt
1892 * handler is registered with the OS, the watchdog timer is started,
1893 * and the stack is notified that the interface is ready.
1894 **/
1895static int igb_open(struct net_device *netdev)
1896{
1897 struct igb_adapter *adapter = netdev_priv(netdev);
1898 struct e1000_hw *hw = &adapter->hw;
1899 int err;
1900 int i;
1901
1902 /* disallow open during test */
1903 if (test_bit(__IGB_TESTING, &adapter->state))
1904 return -EBUSY;
1905
b168dfc5
JB		 1906 netif_carrier_off(netdev);
1907
9d5c8243
AK		 1908 /* allocate transmit descriptors */
1909 err = igb_setup_all_tx_resources(adapter);
1910 if (err)
1911 goto err_setup_tx;
1912
1913 /* allocate receive descriptors */
1914 err = igb_setup_all_rx_resources(adapter);
1915 if (err)
1916 goto err_setup_rx;
1917
1918 /* e1000_power_up_phy(adapter); */
1919
1920 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1921 if ((adapter->hw.mng_cookie.status &
1922 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1923 igb_update_mng_vlan(adapter);
1924
1925 /* before we allocate an interrupt, we must be ready to handle it.
1926 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1927 * as soon as we call pci_request_irq, so we have to setup our
1928 * clean_rx handler before we do so. */
1929 igb_configure(adapter);
1930
4ae196df 1931 igb_vmm_control(adapter);
e1739522
AD		 1932 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1933
9d5c8243
AK		 1934 err = igb_request_irq(adapter);
1935 if (err)
1936 goto err_req_irq;
1937
1938 /* From here on the code is the same as igb_up() */
1939 clear_bit(__IGB_DOWN, &adapter->state);
1940
047e0030
AD		 1941 for (i = 0; i < adapter->num_q_vectors; i++) {
1942 struct igb_q_vector *q_vector = adapter->q_vector[i];
1943 napi_enable(&q_vector->napi);
1944 }
9d5c8243
AK		 1945
1946 /* Clear any pending interrupts. */
1947 rd32(E1000_ICR);
844290e5
PW		 1948
1949 igb_irq_enable(adapter);
1950
d55b53ff
JK		 1951 netif_tx_start_all_queues(netdev);
1952
9d5c8243
AK		 1953 /* Fire a link status change interrupt to start the watchdog. */
1954 wr32(E1000_ICS, E1000_ICS_LSC);
1955
1956 return 0;
1957
1958err_req_irq:
1959 igb_release_hw_control(adapter);
1960 /* e1000_power_down_phy(adapter); */
1961 igb_free_all_rx_resources(adapter);
1962err_setup_rx:
1963 igb_free_all_tx_resources(adapter);
1964err_setup_tx:
1965 igb_reset(adapter);
1966
1967 return err;
1968}
1969
1970/**
1971 * igb_close - Disables a network interface
1972 * @netdev: network interface device structure
1973 *
1974 * Returns 0, this is not allowed to fail
1975 *
1976 * The close entry point is called when an interface is de-activated
1977 * by the OS. The hardware is still under the driver's control, but
1978 * needs to be disabled. A global MAC reset is issued to stop the
1979 * hardware, and all transmit and receive resources are freed.
1980 **/
1981static int igb_close(struct net_device *netdev)
1982{
1983 struct igb_adapter *adapter = netdev_priv(netdev);
1984
1985 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1986 igb_down(adapter);
1987
1988 igb_free_irq(adapter);
1989
1990 igb_free_all_tx_resources(adapter);
1991 igb_free_all_rx_resources(adapter);
1992
1993 /* kill manageability vlan ID if supported, but not if a vlan with
1994 * the same ID is registered on the host OS (let 8021q kill it) */
1995 if ((adapter->hw.mng_cookie.status &
1996 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1997 !(adapter->vlgrp &&
1998 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1999 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2000
2001 return 0;
2002}
2003
2004/**
2005 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2006 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2007 *
2008 * Return 0 on success, negative on failure
2009 **/
80785298 2010int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2011{
80785298 2012 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 2013 int size;
2014
2015 size = sizeof(struct igb_buffer) * tx_ring->count;
2016 tx_ring->buffer_info = vmalloc(size);
2017 if (!tx_ring->buffer_info)
2018 goto err;
2019 memset(tx_ring->buffer_info, 0, size);
2020
2021 /* round up to nearest 4K */
85e8d004 2022 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2023 tx_ring->size = ALIGN(tx_ring->size, 4096);
2024
2025 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2026 &tx_ring->dma);
2027
2028 if (!tx_ring->desc)
2029 goto err;
2030
9d5c8243
AK		 2031 tx_ring->next_to_use = 0;
2032 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2033 return 0;
2034
2035err:
2036 vfree(tx_ring->buffer_info);
047e0030 2037 dev_err(&pdev->dev,
9d5c8243
AK		 2038 "Unable to allocate memory for the transmit descriptor ring\n");
2039 return -ENOMEM;
2040}
2041
2042/**
2043 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2044 * (Descriptors) for all queues
2045 * @adapter: board private structure
2046 *
2047 * Return 0 on success, negative on failure
2048 **/
2049static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2050{
2051 int i, err = 0;
661086df 2052 int r_idx;
9d5c8243
AK		 2053
2054 for (i = 0; i < adapter->num_tx_queues; i++) {
80785298 2055 err = igb_setup_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2056 if (err) {
2057 dev_err(&adapter->pdev->dev,
2058 "Allocation for Tx Queue %u failed\n", i);
2059 for (i--; i >= 0; i--)
3b644cf6 2060 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2061 break;
2062 }
2063 }
2064
661086df
PWJ		 2065 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2066 r_idx = i % adapter->num_tx_queues;
2067 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2068 }
9d5c8243
AK		 2069 return err;
2070}
2071
2072/**
85b430b4
AD		 2073 * igb_setup_tctl - configure the transmit control registers
2074 * @adapter: Board private structure
9d5c8243 2075 **/
85b430b4 2076static void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2077{
9d5c8243
AK		 2078 struct e1000_hw *hw = &adapter->hw;
2079 u32 tctl;
9d5c8243 2080
85b430b4
AD		 2081 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2082 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2083
2084 /* Program the Transmit Control Register */
9d5c8243
AK		 2085 tctl = rd32(E1000_TCTL);
2086 tctl &= ~E1000_TCTL_CT;
2087 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2088 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2089
2090 igb_config_collision_dist(hw);
2091
9d5c8243
AK		 2092 /* Enable transmits */
2093 tctl |= E1000_TCTL_EN;
2094
2095 wr32(E1000_TCTL, tctl);
2096}
2097
85b430b4
AD		 2098/**
2099 * igb_configure_tx_ring - Configure transmit ring after Reset
2100 * @adapter: board private structure
2101 * @ring: tx ring to configure
2102 *
2103 * Configure a transmit ring after a reset.
2104 **/
2105static void igb_configure_tx_ring(struct igb_adapter *adapter,
2106 struct igb_ring *ring)
2107{
2108 struct e1000_hw *hw = &adapter->hw;
2109 u32 txdctl;
2110 u64 tdba = ring->dma;
2111 int reg_idx = ring->reg_idx;
2112
2113 /* disable the queue */
2114 txdctl = rd32(E1000_TXDCTL(reg_idx));
2115 wr32(E1000_TXDCTL(reg_idx),
2116 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2117 wrfl();
2118 mdelay(10);
2119
2120 wr32(E1000_TDLEN(reg_idx),
2121 ring->count * sizeof(union e1000_adv_tx_desc));
2122 wr32(E1000_TDBAL(reg_idx),
2123 tdba & 0x00000000ffffffffULL);
2124 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2125
fce99e34
AD		 2126 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2127 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2128 writel(0, ring->head);
2129 writel(0, ring->tail);
85b430b4
AD		 2130
2131 txdctl |= IGB_TX_PTHRESH;
2132 txdctl |= IGB_TX_HTHRESH << 8;
2133 txdctl |= IGB_TX_WTHRESH << 16;
2134
2135 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2136 wr32(E1000_TXDCTL(reg_idx), txdctl);
2137}
2138
2139/**
2140 * igb_configure_tx - Configure transmit Unit after Reset
2141 * @adapter: board private structure
2142 *
2143 * Configure the Tx unit of the MAC after a reset.
2144 **/
2145static void igb_configure_tx(struct igb_adapter *adapter)
2146{
2147 int i;
2148
2149 for (i = 0; i < adapter->num_tx_queues; i++)
2150 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
85b430b4
AD		 2151}
2152
9d5c8243
AK		 2153/**
2154 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2155 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2156 *
2157 * Returns 0 on success, negative on failure
2158 **/
80785298 2159int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2160{
80785298 2161 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2162 int size, desc_len;
2163
2164 size = sizeof(struct igb_buffer) * rx_ring->count;
2165 rx_ring->buffer_info = vmalloc(size);
2166 if (!rx_ring->buffer_info)
2167 goto err;
2168 memset(rx_ring->buffer_info, 0, size);
2169
2170 desc_len = sizeof(union e1000_adv_rx_desc);
2171
2172 /* Round up to nearest 4K */
2173 rx_ring->size = rx_ring->count * desc_len;
2174 rx_ring->size = ALIGN(rx_ring->size, 4096);
2175
2176 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2177 &rx_ring->dma);
2178
2179 if (!rx_ring->desc)
2180 goto err;
2181
2182 rx_ring->next_to_clean = 0;
2183 rx_ring->next_to_use = 0;
9d5c8243 2184
9d5c8243
AK		 2185 return 0;
2186
2187err:
2188 vfree(rx_ring->buffer_info);
80785298 2189 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2190 "the receive descriptor ring\n");
2191 return -ENOMEM;
2192}
2193
2194/**
2195 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2196 * (Descriptors) for all queues
2197 * @adapter: board private structure
2198 *
2199 * Return 0 on success, negative on failure
2200 **/
2201static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2202{
2203 int i, err = 0;
2204
2205 for (i = 0; i < adapter->num_rx_queues; i++) {
80785298 2206 err = igb_setup_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2207 if (err) {
2208 dev_err(&adapter->pdev->dev,
2209 "Allocation for Rx Queue %u failed\n", i);
2210 for (i--; i >= 0; i--)
3b644cf6 2211 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2212 break;
2213 }
2214 }
2215
2216 return err;
2217}
2218
2219/**
2220 * igb_setup_rctl - configure the receive control registers
2221 * @adapter: Board private structure
2222 **/
2223static void igb_setup_rctl(struct igb_adapter *adapter)
2224{
2225 struct e1000_hw *hw = &adapter->hw;
2226 u32 rctl;
9d5c8243
AK		 2227
2228 rctl = rd32(E1000_RCTL);
2229
2230 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2231 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2232
69d728ba 2233 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2234 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2235
87cb7e8c
AK		 2236 /*
2237 * enable stripping of CRC. It's unlikely this will break BMC
2238 * redirection as it did with e1000. Newer features require
2239 * that the HW strips the CRC.
73cd78f1 2240 */
87cb7e8c 2241 rctl |= E1000_RCTL_SECRC;
9d5c8243 2242
9b07f3d3 2243 /*
ec54d7d6 2244 * disable store bad packets and clear size bits.
9b07f3d3 2245 */
ec54d7d6 2246 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2247
6ec43fe6
AD		 2248 /* enable LPE to prevent packets larger than max_frame_size */
2249 rctl |= E1000_RCTL_LPE;
9d5c8243 2250
952f72a8
AD		 2251 /* disable queue 0 to prevent tail write w/o re-config */
2252 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2253
e1739522
AD		 2254 /* Attention!!! For SR-IOV PF driver operations you must enable
2255 * queue drop for all VF and PF queues to prevent head of line blocking
2256 * if an un-trusted VF does not provide descriptors to hardware.
2257 */
2258 if (adapter->vfs_allocated_count) {
2259 u32 vmolr;
2260
e1739522
AD		 2261 /* set all queue drop enable bits */
2262 wr32(E1000_QDE, ALL_QUEUES);
e1739522 2263
77a22941 2264 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2265 if (rctl & E1000_RCTL_LPE)
2266 vmolr |= E1000_VMOLR_LPE;
77a22941 2267 if (adapter->num_rx_queues > 1)
e1739522 2268 vmolr |= E1000_VMOLR_RSSE;
77a22941 2269 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2270 }
2271
9d5c8243
AK		 2272 wr32(E1000_RCTL, rctl);
2273}
2274
e1739522
AD		 2275/**
2276 * igb_rlpml_set - set maximum receive packet size
2277 * @adapter: board private structure
2278 *
2279 * Configure maximum receivable packet size.
2280 **/
2281static void igb_rlpml_set(struct igb_adapter *adapter)
2282{
2283 u32 max_frame_size = adapter->max_frame_size;
2284 struct e1000_hw *hw = &adapter->hw;
2285 u16 pf_id = adapter->vfs_allocated_count;
2286
2287 if (adapter->vlgrp)
2288 max_frame_size += VLAN_TAG_SIZE;
2289
2290 /* if vfs are enabled we set RLPML to the largest possible request
2291 * size and set the VMOLR RLPML to the size we need */
2292 if (pf_id) {
2293 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2294 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2295 }
2296
2297 wr32(E1000_RLPML, max_frame_size);
2298}
2299
2300/**
2301 * igb_configure_vt_default_pool - Configure VT default pool
2302 * @adapter: board private structure
2303 *
2304 * Configure the default pool
2305 **/
2306static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2307{
2308 struct e1000_hw *hw = &adapter->hw;
2309 u16 pf_id = adapter->vfs_allocated_count;
2310 u32 vtctl;
2311
2312 /* not in sr-iov mode - do nothing */
2313 if (!pf_id)
2314 return;
2315
2316 vtctl = rd32(E1000_VT_CTL);
2317 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2318 E1000_VT_CTL_DISABLE_DEF_POOL);
2319 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2320 wr32(E1000_VT_CTL, vtctl);
2321}
2322
85b430b4
AD		 2323/**
2324 * igb_configure_rx_ring - Configure a receive ring after Reset
2325 * @adapter: board private structure
2326 * @ring: receive ring to be configured
2327 *
2328 * Configure the Rx unit of the MAC after a reset.
2329 **/
2330static void igb_configure_rx_ring(struct igb_adapter *adapter,
2331 struct igb_ring *ring)
2332{
2333 struct e1000_hw *hw = &adapter->hw;
2334 u64 rdba = ring->dma;
2335 int reg_idx = ring->reg_idx;
952f72a8 2336 u32 srrctl, rxdctl;
85b430b4
AD		 2337
2338 /* disable the queue */
2339 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2340 wr32(E1000_RXDCTL(reg_idx),
2341 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2342
2343 /* Set DMA base address registers */
2344 wr32(E1000_RDBAL(reg_idx),
2345 rdba & 0x00000000ffffffffULL);
2346 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2347 wr32(E1000_RDLEN(reg_idx),
2348 ring->count * sizeof(union e1000_adv_rx_desc));
2349
2350 /* initialize head and tail */
fce99e34
AD		 2351 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2352 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2353 writel(0, ring->head);
2354 writel(0, ring->tail);
85b430b4 2355
952f72a8 2356 /* set descriptor configuration */
4c844851
AD		 2357 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2358 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2359 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2360#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2361 srrctl |= IGB_RXBUFFER_16384 >>
2362 E1000_SRRCTL_BSIZEPKT_SHIFT;
2363#else
2364 srrctl |= (PAGE_SIZE / 2) >>
2365 E1000_SRRCTL_BSIZEPKT_SHIFT;
2366#endif
2367 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2368 } else {
4c844851 2369 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2370 E1000_SRRCTL_BSIZEPKT_SHIFT;
2371 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2372 }
2373
2374 wr32(E1000_SRRCTL(reg_idx), srrctl);
2375
85b430b4
AD		 2376 /* enable receive descriptor fetching */
2377 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2378 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2379 rxdctl &= 0xFFF00000;
2380 rxdctl |= IGB_RX_PTHRESH;
2381 rxdctl |= IGB_RX_HTHRESH << 8;
2382 rxdctl |= IGB_RX_WTHRESH << 16;
2383 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2384}
2385
9d5c8243
AK		 2386/**
2387 * igb_configure_rx - Configure receive Unit after Reset
2388 * @adapter: board private structure
2389 *
2390 * Configure the Rx unit of the MAC after a reset.
2391 **/
2392static void igb_configure_rx(struct igb_adapter *adapter)
2393{
9d5c8243
AK		 2394 struct e1000_hw *hw = &adapter->hw;
2395 u32 rctl, rxcsum;
9107584e 2396 int i;
9d5c8243
AK		 2397
2398 /* disable receives while setting up the descriptors */
2399 rctl = rd32(E1000_RCTL);
2400 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2401 wrfl();
2402 mdelay(10);
2403
2404 if (adapter->itr_setting > 3)
6eb5a7f1 2405 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2406
2407 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2408 * the Base and Length of the Rx Descriptor Ring */
85b430b4
AD		 2409 for (i = 0; i < adapter->num_rx_queues; i++)
2410 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2411
2412 if (adapter->num_rx_queues > 1) {
2413 u32 random[10];
2414 u32 mrqc;
2415 u32 j, shift;
2416 union e1000_reta {
2417 u32 dword;
2418 u8 bytes[4];
2419 } reta;
2420
2421 get_random_bytes(&random[0], 40);
2422
2d064c06
AD		 2423 if (hw->mac.type >= e1000_82576)
2424 shift = 0;
2425 else
2426 shift = 6;
9d5c8243
AK		 2427 for (j = 0; j < (32 * 4); j++) {
2428 reta.bytes[j & 3] =
26bc19ec 2429 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2430 if ((j & 3) == 3)
2431 writel(reta.dword,
2432 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2433 }
e1739522
AD		 2434 if (adapter->vfs_allocated_count)
2435 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2436 else
2437 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2438
2439 /* Fill out hash function seeds */
2440 for (j = 0; j < 10; j++)
2441 array_wr32(E1000_RSSRK(0), j, random[j]);
2442
2443 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2444 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2445 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2446 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2447 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2448 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2449 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2450 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2451
9d5c8243 2452 wr32(E1000_MRQC, mrqc);
2844f797 2453 } else if (adapter->vfs_allocated_count) {
e1739522 2454 /* Enable multi-queue for sr-iov */
2844f797 2455 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2456 }
2457
2844f797
AD		 2458 /* Enable Receive Checksum Offload for TCP and UDP */
2459 rxcsum = rd32(E1000_RXCSUM);
2460 /* Disable raw packet checksumming */
2461 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2462
2463 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2464 /* Enable Receive Checksum Offload for SCTP */
2465 rxcsum |= E1000_RXCSUM_CRCOFL;
2466
7beb0146 2467 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2468 wr32(E1000_RXCSUM, rxcsum);
2469
e1739522
AD		 2470 /* Set the default pool for the PF's first queue */
2471 igb_configure_vt_default_pool(adapter);
2472
68d480c4
AD		 2473 /* set UTA to appropriate mode */
2474 igb_set_uta(adapter);
2475
26ad9178
AD		 2476 /* set the correct pool for the PF default MAC address in entry 0 */
2477 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2478 adapter->vfs_allocated_count);
2479
e1739522 2480 igb_rlpml_set(adapter);
9d5c8243
AK		 2481
2482 /* Enable Receives */
2483 wr32(E1000_RCTL, rctl);
2484}
2485
2486/**
2487 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2488 * @tx_ring: Tx descriptor ring for a specific queue
2489 *
2490 * Free all transmit software resources
2491 **/
68fd9910 2492void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2493{
3b644cf6 2494 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2495
2496 vfree(tx_ring->buffer_info);
2497 tx_ring->buffer_info = NULL;
2498
80785298
AD		 2499 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2500 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2501
2502 tx_ring->desc = NULL;
2503}
2504
2505/**
2506 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2507 * @adapter: board private structure
2508 *
2509 * Free all transmit software resources
2510 **/
2511static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2512{
2513 int i;
2514
2515 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2516 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2517}
2518
80785298 2519static void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
9d5c8243
AK		 2520 struct igb_buffer *buffer_info)
2521{
65689fef 2522 buffer_info->dma = 0;
9d5c8243 2523 if (buffer_info->skb) {
80785298
AD		 2524 skb_dma_unmap(&tx_ring->pdev->dev,
2525 buffer_info->skb,
65689fef 2526 DMA_TO_DEVICE);
9d5c8243
AK		 2527 dev_kfree_skb_any(buffer_info->skb);
2528 buffer_info->skb = NULL;
2529 }
2530 buffer_info->time_stamp = 0;
2531 /* buffer_info must be completely set up in the transmit path */
2532}
2533
2534/**
2535 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2536 * @tx_ring: ring to be cleaned
2537 **/
3b644cf6 2538static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2539{
2540 struct igb_buffer *buffer_info;
2541 unsigned long size;
2542 unsigned int i;
2543
2544 if (!tx_ring->buffer_info)
2545 return;
2546 /* Free all the Tx ring sk_buffs */
2547
2548 for (i = 0; i < tx_ring->count; i++) {
2549 buffer_info = &tx_ring->buffer_info[i];
80785298 2550 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2551 }
2552
2553 size = sizeof(struct igb_buffer) * tx_ring->count;
2554 memset(tx_ring->buffer_info, 0, size);
2555
2556 /* Zero out the descriptor ring */
2557
2558 memset(tx_ring->desc, 0, tx_ring->size);
2559
2560 tx_ring->next_to_use = 0;
2561 tx_ring->next_to_clean = 0;
2562
fce99e34
AD		 2563 writel(0, tx_ring->head);
2564 writel(0, tx_ring->tail);
9d5c8243
AK		 2565}
2566
2567/**
2568 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2569 * @adapter: board private structure
2570 **/
2571static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2572{
2573 int i;
2574
2575 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2576 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2577}
2578
2579/**
2580 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2581 * @rx_ring: ring to clean the resources from
2582 *
2583 * Free all receive software resources
2584 **/
68fd9910 2585void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2586{
3b644cf6 2587 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2588
2589 vfree(rx_ring->buffer_info);
2590 rx_ring->buffer_info = NULL;
2591
80785298
AD		 2592 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2593 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2594
2595 rx_ring->desc = NULL;
2596}
2597
2598/**
2599 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2600 * @adapter: board private structure
2601 *
2602 * Free all receive software resources
2603 **/
2604static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2605{
2606 int i;
2607
2608 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2609 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2610}
2611
2612/**
2613 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2614 * @rx_ring: ring to free buffers from
2615 **/
3b644cf6 2616static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 2617{
2618 struct igb_buffer *buffer_info;
9d5c8243
AK		 2619 unsigned long size;
2620 unsigned int i;
2621
2622 if (!rx_ring->buffer_info)
2623 return;
2624 /* Free all the Rx ring sk_buffs */
2625 for (i = 0; i < rx_ring->count; i++) {
2626 buffer_info = &rx_ring->buffer_info[i];
2627 if (buffer_info->dma) {
80785298
AD		 2628 pci_unmap_single(rx_ring->pdev,
2629 buffer_info->dma,
4c844851 2630 rx_ring->rx_buffer_len,
6ec43fe6 2631 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2632 buffer_info->dma = 0;
2633 }
2634
2635 if (buffer_info->skb) {
2636 dev_kfree_skb(buffer_info->skb);
2637 buffer_info->skb = NULL;
2638 }
6ec43fe6 2639 if (buffer_info->page_dma) {
80785298
AD		 2640 pci_unmap_page(rx_ring->pdev,
2641 buffer_info->page_dma,
6ec43fe6
AD		 2642 PAGE_SIZE / 2,
2643 PCI_DMA_FROMDEVICE);
2644 buffer_info->page_dma = 0;
2645 }
9d5c8243 2646 if (buffer_info->page) {
9d5c8243
AK		 2647 put_page(buffer_info->page);
2648 buffer_info->page = NULL;
bf36c1a0 2649 buffer_info->page_offset = 0;
9d5c8243
AK		 2650 }
2651 }
2652
9d5c8243
AK		 2653 size = sizeof(struct igb_buffer) * rx_ring->count;
2654 memset(rx_ring->buffer_info, 0, size);
2655
2656 /* Zero out the descriptor ring */
2657 memset(rx_ring->desc, 0, rx_ring->size);
2658
2659 rx_ring->next_to_clean = 0;
2660 rx_ring->next_to_use = 0;
2661
fce99e34
AD		 2662 writel(0, rx_ring->head);
2663 writel(0, rx_ring->tail);
9d5c8243
AK		 2664}
2665
2666/**
2667 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2668 * @adapter: board private structure
2669 **/
2670static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2671{
2672 int i;
2673
2674 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2675 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2676}
2677
2678/**
2679 * igb_set_mac - Change the Ethernet Address of the NIC
2680 * @netdev: network interface device structure
2681 * @p: pointer to an address structure
2682 *
2683 * Returns 0 on success, negative on failure
2684 **/
2685static int igb_set_mac(struct net_device *netdev, void *p)
2686{
2687 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2688 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2689 struct sockaddr *addr = p;
2690
2691 if (!is_valid_ether_addr(addr->sa_data))
2692 return -EADDRNOTAVAIL;
2693
2694 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2695 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2696
26ad9178
AD		 2697 /* set the correct pool for the new PF MAC address in entry 0 */
2698 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2699 adapter->vfs_allocated_count);
e1739522 2700
9d5c8243
AK		 2701 return 0;
2702}
2703
2704/**
68d480c4 2705 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2706 * @netdev: network interface device structure
2707 *
68d480c4
AD		 2708 * Writes multicast address list to the MTA hash table.
2709 * Returns: -ENOMEM on failure
2710 * 0 on no addresses written
2711 * X on writing X addresses to MTA
9d5c8243 2712 **/
68d480c4 2713static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2714{
2715 struct igb_adapter *adapter = netdev_priv(netdev);
2716 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2717 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2718 u8 *mta_list;
2719 u32 vmolr = 0;
9d5c8243
AK		 2720 int i;
2721
68d480c4
AD		 2722 if (!netdev->mc_count) {
2723 /* nothing to program, so clear mc list */
2724 igb_update_mc_addr_list(hw, NULL, 0);
2725 igb_restore_vf_multicasts(adapter);
2726 return 0;
2727 }
9d5c8243 2728
68d480c4
AD		 2729 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2730 if (!mta_list)
2731 return -ENOMEM;
ff41f8dc 2732
68d480c4
AD		 2733 /* set vmolr receive overflow multicast bit */
2734 vmolr |= E1000_VMOLR_ROMPE;
2735
2736 /* The shared function expects a packed array of only addresses. */
2737 mc_ptr = netdev->mc_list;
2738
2739 for (i = 0; i < netdev->mc_count; i++) {
2740 if (!mc_ptr)
2741 break;
2742 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2743 mc_ptr = mc_ptr->next;
746b9f02 2744 }
68d480c4
AD		 2745 igb_update_mc_addr_list(hw, mta_list, i);
2746 kfree(mta_list);
2747
2748 return netdev->mc_count;
2749}
2750
2751/**
2752 * igb_write_uc_addr_list - write unicast addresses to RAR table
2753 * @netdev: network interface device structure
2754 *
2755 * Writes unicast address list to the RAR table.
2756 * Returns: -ENOMEM on failure/insufficient address space
2757 * 0 on no addresses written
2758 * X on writing X addresses to the RAR table
2759 **/
2760static int igb_write_uc_addr_list(struct net_device *netdev)
2761{
2762 struct igb_adapter *adapter = netdev_priv(netdev);
2763 struct e1000_hw *hw = &adapter->hw;
2764 unsigned int vfn = adapter->vfs_allocated_count;
2765 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2766 int count = 0;
2767
2768 /* return ENOMEM indicating insufficient memory for addresses */
2769 if (netdev->uc.count > rar_entries)
2770 return -ENOMEM;
9d5c8243 2771
ff41f8dc
AD		 2772 if (netdev->uc.count && rar_entries) {
2773 struct netdev_hw_addr *ha;
2774 list_for_each_entry(ha, &netdev->uc.list, list) {
2775 if (!rar_entries)
2776 break;
26ad9178
AD		 2777 igb_rar_set_qsel(adapter, ha->addr,
2778 rar_entries--,
68d480c4
AD		 2779 vfn);
2780 count++;
ff41f8dc
AD		 2781 }
2782 }
2783 /* write the addresses in reverse order to avoid write combining */
2784 for (; rar_entries > 0 ; rar_entries--) {
2785 wr32(E1000_RAH(rar_entries), 0);
2786 wr32(E1000_RAL(rar_entries), 0);
2787 }
2788 wrfl();
2789
68d480c4
AD		 2790 return count;
2791}
2792
2793/**
2794 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2795 * @netdev: network interface device structure
2796 *
2797 * The set_rx_mode entry point is called whenever the unicast or multicast
2798 * address lists or the network interface flags are updated. This routine is
2799 * responsible for configuring the hardware for proper unicast, multicast,
2800 * promiscuous mode, and all-multi behavior.
2801 **/
2802static void igb_set_rx_mode(struct net_device *netdev)
2803{
2804 struct igb_adapter *adapter = netdev_priv(netdev);
2805 struct e1000_hw *hw = &adapter->hw;
2806 unsigned int vfn = adapter->vfs_allocated_count;
2807 u32 rctl, vmolr = 0;
2808 int count;
2809
2810 /* Check for Promiscuous and All Multicast modes */
2811 rctl = rd32(E1000_RCTL);
2812
2813 /* clear the effected bits */
2814 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2815
2816 if (netdev->flags & IFF_PROMISC) {
2817 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2818 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2819 } else {
2820 if (netdev->flags & IFF_ALLMULTI) {
2821 rctl |= E1000_RCTL_MPE;
2822 vmolr |= E1000_VMOLR_MPME;
2823 } else {
2824 /*
2825 * Write addresses to the MTA, if the attempt fails
2826 * then we should just turn on promiscous mode so
2827 * that we can at least receive multicast traffic
2828 */
2829 count = igb_write_mc_addr_list(netdev);
2830 if (count < 0) {
2831 rctl |= E1000_RCTL_MPE;
2832 vmolr |= E1000_VMOLR_MPME;
2833 } else if (count) {
2834 vmolr |= E1000_VMOLR_ROMPE;
2835 }
2836 }
2837 /*
2838 * Write addresses to available RAR registers, if there is not
2839 * sufficient space to store all the addresses then enable
2840 * unicast promiscous mode
2841 */
2842 count = igb_write_uc_addr_list(netdev);
2843 if (count < 0) {
2844 rctl |= E1000_RCTL_UPE;
2845 vmolr |= E1000_VMOLR_ROPE;
2846 }
2847 rctl |= E1000_RCTL_VFE;
28fc06f5 2848 }
68d480c4 2849 wr32(E1000_RCTL, rctl);
28fc06f5 2850
68d480c4
AD		 2851 /*
2852 * In order to support SR-IOV and eventually VMDq it is necessary to set
2853 * the VMOLR to enable the appropriate modes. Without this workaround
2854 * we will have issues with VLAN tag stripping not being done for frames
2855 * that are only arriving because we are the default pool
2856 */
2857 if (hw->mac.type < e1000_82576)
28fc06f5 2858 return;
9d5c8243 2859
68d480c4
AD		 2860 vmolr |= rd32(E1000_VMOLR(vfn)) &
2861 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2862 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2863 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2864}
2865
2866/* Need to wait a few seconds after link up to get diagnostic information from
2867 * the phy */
2868static void igb_update_phy_info(unsigned long data)
2869{
2870 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2871 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2872}
2873
4d6b725e
AD		 2874/**
2875 * igb_has_link - check shared code for link and determine up/down
2876 * @adapter: pointer to driver private info
2877 **/
2878static bool igb_has_link(struct igb_adapter *adapter)
2879{
2880 struct e1000_hw *hw = &adapter->hw;
2881 bool link_active = false;
2882 s32 ret_val = 0;
2883
2884 /* get_link_status is set on LSC (link status) interrupt or
2885 * rx sequence error interrupt. get_link_status will stay
2886 * false until the e1000_check_for_link establishes link
2887 * for copper adapters ONLY
2888 */
2889 switch (hw->phy.media_type) {
2890 case e1000_media_type_copper:
2891 if (hw->mac.get_link_status) {
2892 ret_val = hw->mac.ops.check_for_link(hw);
2893 link_active = !hw->mac.get_link_status;
2894 } else {
2895 link_active = true;
2896 }
2897 break;
4d6b725e
AD		 2898 case e1000_media_type_internal_serdes:
2899 ret_val = hw->mac.ops.check_for_link(hw);
2900 link_active = hw->mac.serdes_has_link;
2901 break;
2902 default:
2903 case e1000_media_type_unknown:
2904 break;
2905 }
2906
2907 return link_active;
2908}
2909
9d5c8243
AK		 2910/**
2911 * igb_watchdog - Timer Call-back
2912 * @data: pointer to adapter cast into an unsigned long
2913 **/
2914static void igb_watchdog(unsigned long data)
2915{
2916 struct igb_adapter *adapter = (struct igb_adapter *)data;
2917 /* Do the rest outside of interrupt context */
2918 schedule_work(&adapter->watchdog_task);
2919}
2920
2921static void igb_watchdog_task(struct work_struct *work)
2922{
2923 struct igb_adapter *adapter = container_of(work,
2924 struct igb_adapter, watchdog_task);
2925 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2926 struct net_device *netdev = adapter->netdev;
2927 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2928 u32 link;
7a6ea550 2929 int i;
9d5c8243 2930
4d6b725e
AD		 2931 link = igb_has_link(adapter);
2932 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2933 goto link_up;
2934
9d5c8243
AK		 2935 if (link) {
2936 if (!netif_carrier_ok(netdev)) {
2937 u32 ctrl;
2938 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2939 &adapter->link_speed,
2940 &adapter->link_duplex);
2941
2942 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2943 /* Links status message must follow this format */
2944 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2945 "Flow Control: %s\n",
527d47c1 2946 netdev->name,
9d5c8243
AK		 2947 adapter->link_speed,
2948 adapter->link_duplex == FULL_DUPLEX ?
2949 "Full Duplex" : "Half Duplex",
2950 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2951 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2952 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2953 E1000_CTRL_TFCE) ? "TX" : "None")));
2954
2955 /* tweak tx_queue_len according to speed/duplex and
2956 * adjust the timeout factor */
2957 netdev->tx_queue_len = adapter->tx_queue_len;
2958 adapter->tx_timeout_factor = 1;
2959 switch (adapter->link_speed) {
2960 case SPEED_10:
2961 netdev->tx_queue_len = 10;
2962 adapter->tx_timeout_factor = 14;
2963 break;
2964 case SPEED_100:
2965 netdev->tx_queue_len = 100;
2966 /* maybe add some timeout factor ? */
2967 break;
2968 }
2969
2970 netif_carrier_on(netdev);
9d5c8243 2971
4ae196df
AD		 2972 igb_ping_all_vfs(adapter);
2973
4b1a9877 2974 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2975 if (!test_bit(__IGB_DOWN, &adapter->state))
2976 mod_timer(&adapter->phy_info_timer,
2977 round_jiffies(jiffies + 2 * HZ));
2978 }
2979 } else {
2980 if (netif_carrier_ok(netdev)) {
2981 adapter->link_speed = 0;
2982 adapter->link_duplex = 0;
527d47c1
AD		 2983 /* Links status message must follow this format */
2984 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2985 netdev->name);
9d5c8243 2986 netif_carrier_off(netdev);
4b1a9877 2987
4ae196df
AD		 2988 igb_ping_all_vfs(adapter);
2989
4b1a9877 2990 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2991 if (!test_bit(__IGB_DOWN, &adapter->state))
2992 mod_timer(&adapter->phy_info_timer,
2993 round_jiffies(jiffies + 2 * HZ));
2994 }
2995 }
2996
2997link_up:
2998 igb_update_stats(adapter);
2999
4b1a9877 3000 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 3001 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 3002 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 3003 adapter->colc_old = adapter->stats.colc;
3004
3005 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
3006 adapter->gorc_old = adapter->stats.gorc;
3007 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
3008 adapter->gotc_old = adapter->stats.gotc;
3009
3010 igb_update_adaptive(&adapter->hw);
3011
3012 if (!netif_carrier_ok(netdev)) {
c493ea45 3013 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 3014 /* We've lost link, so the controller stops DMA,
3015 * but we've got queued Tx work that's never going
3016 * to get done, so reset controller to flush Tx.
3017 * (Do the reset outside of interrupt context). */
3018 adapter->tx_timeout_count++;
3019 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 3020 /* return immediately since reset is imminent */
3021 return;
9d5c8243
AK		 3022 }
3023 }
3024
3025 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3026 if (adapter->msix_entries) {
047e0030
AD		 3027 u32 eics = 0;
3028 for (i = 0; i < adapter->num_q_vectors; i++) {
3029 struct igb_q_vector *q_vector = adapter->q_vector[i];
3030 eics |= q_vector->eims_value;
3031 }
7a6ea550
AD		 3032 wr32(E1000_EICS, eics);
3033 } else {
3034 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3035 }
9d5c8243
AK		 3036
3037 /* Force detection of hung controller every watchdog period */
3038 tx_ring->detect_tx_hung = true;
3039
3040 /* Reset the timer */
3041 if (!test_bit(__IGB_DOWN, &adapter->state))
3042 mod_timer(&adapter->watchdog_timer,
3043 round_jiffies(jiffies + 2 * HZ));
3044}
3045
3046enum latency_range {
3047 lowest_latency = 0,
3048 low_latency = 1,
3049 bulk_latency = 2,
3050 latency_invalid = 255
3051};
3052
3053
6eb5a7f1
AD		 3054/**
3055 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3056 *
3057 * Stores a new ITR value based on strictly on packet size. This
3058 * algorithm is less sophisticated than that used in igb_update_itr,
3059 * due to the difficulty of synchronizing statistics across multiple
3060 * receive rings. The divisors and thresholds used by this fuction
3061 * were determined based on theoretical maximum wire speed and testing
3062 * data, in order to minimize response time while increasing bulk
3063 * throughput.
3064 * This functionality is controlled by the InterruptThrottleRate module
3065 * parameter (see igb_param.c)
3066 * NOTE: This function is called only when operating in a multiqueue
3067 * receive environment.
047e0030 3068 * @q_vector: pointer to q_vector
6eb5a7f1 3069 **/
047e0030 3070static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3071{
047e0030 3072 int new_val = q_vector->itr_val;
6eb5a7f1 3073 int avg_wire_size = 0;
047e0030 3074 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3075
6eb5a7f1
AD		 3076 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3077 * ints/sec - ITR timer value of 120 ticks.
3078 */
3079 if (adapter->link_speed != SPEED_1000) {
047e0030 3080 new_val = 976;
6eb5a7f1 3081 goto set_itr_val;
9d5c8243 3082 }
047e0030
AD		 3083
3084 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3085 struct igb_ring *ring = q_vector->rx_ring;
3086 avg_wire_size = ring->total_bytes / ring->total_packets;
3087 }
3088
3089 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3090 struct igb_ring *ring = q_vector->tx_ring;
3091 avg_wire_size = max_t(u32, avg_wire_size,
3092 (ring->total_bytes /
3093 ring->total_packets));
3094 }
3095
3096 /* if avg_wire_size isn't set no work was done */
3097 if (!avg_wire_size)
3098 goto clear_counts;
9d5c8243 3099
6eb5a7f1
AD		 3100 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3101 avg_wire_size += 24;
3102
3103 /* Don't starve jumbo frames */
3104 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3105
6eb5a7f1
AD		 3106 /* Give a little boost to mid-size frames */
3107 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3108 new_val = avg_wire_size / 3;
3109 else
3110 new_val = avg_wire_size / 2;
9d5c8243 3111
6eb5a7f1 3112set_itr_val:
047e0030
AD		 3113 if (new_val != q_vector->itr_val) {
3114 q_vector->itr_val = new_val;
3115 q_vector->set_itr = 1;
9d5c8243 3116 }
6eb5a7f1 3117clear_counts:
047e0030
AD		 3118 if (q_vector->rx_ring) {
3119 q_vector->rx_ring->total_bytes = 0;
3120 q_vector->rx_ring->total_packets = 0;
3121 }
3122 if (q_vector->tx_ring) {
3123 q_vector->tx_ring->total_bytes = 0;
3124 q_vector->tx_ring->total_packets = 0;
3125 }
9d5c8243
AK		 3126}
3127
3128/**
3129 * igb_update_itr - update the dynamic ITR value based on statistics
3130 * Stores a new ITR value based on packets and byte
3131 * counts during the last interrupt. The advantage of per interrupt
3132 * computation is faster updates and more accurate ITR for the current
3133 * traffic pattern. Constants in this function were computed
3134 * based on theoretical maximum wire speed and thresholds were set based
3135 * on testing data as well as attempting to minimize response time
3136 * while increasing bulk throughput.
3137 * this functionality is controlled by the InterruptThrottleRate module
3138 * parameter (see igb_param.c)
3139 * NOTE: These calculations are only valid when operating in a single-
3140 * queue environment.
3141 * @adapter: pointer to adapter
047e0030 3142 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3143 * @packets: the number of packets during this measurement interval
3144 * @bytes: the number of bytes during this measurement interval
3145 **/
3146static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3147 int packets, int bytes)
3148{
3149 unsigned int retval = itr_setting;
3150
3151 if (packets == 0)
3152 goto update_itr_done;
3153
3154 switch (itr_setting) {
3155 case lowest_latency:
3156 /* handle TSO and jumbo frames */
3157 if (bytes/packets > 8000)
3158 retval = bulk_latency;
3159 else if ((packets < 5) && (bytes > 512))
3160 retval = low_latency;
3161 break;
3162 case low_latency: /* 50 usec aka 20000 ints/s */
3163 if (bytes > 10000) {
3164 /* this if handles the TSO accounting */
3165 if (bytes/packets > 8000) {
3166 retval = bulk_latency;
3167 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3168 retval = bulk_latency;
3169 } else if ((packets > 35)) {
3170 retval = lowest_latency;
3171 }
3172 } else if (bytes/packets > 2000) {
3173 retval = bulk_latency;
3174 } else if (packets <= 2 && bytes < 512) {
3175 retval = lowest_latency;
3176 }
3177 break;
3178 case bulk_latency: /* 250 usec aka 4000 ints/s */
3179 if (bytes > 25000) {
3180 if (packets > 35)
3181 retval = low_latency;
1e5c3d21 3182 } else if (bytes < 1500) {
9d5c8243
AK		 3183 retval = low_latency;
3184 }
3185 break;
3186 }
3187
3188update_itr_done:
3189 return retval;
3190}
3191
6eb5a7f1 3192static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3193{
047e0030 3194 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3195 u16 current_itr;
047e0030 3196 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3197
3198 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3199 if (adapter->link_speed != SPEED_1000) {
3200 current_itr = 0;
3201 new_itr = 4000;
3202 goto set_itr_now;
3203 }
3204
3205 adapter->rx_itr = igb_update_itr(adapter,
3206 adapter->rx_itr,
3207 adapter->rx_ring->total_packets,
3208 adapter->rx_ring->total_bytes);
9d5c8243 3209
047e0030
AD		 3210 adapter->tx_itr = igb_update_itr(adapter,
3211 adapter->tx_itr,
3212 adapter->tx_ring->total_packets,
3213 adapter->tx_ring->total_bytes);
3214 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3215
6eb5a7f1 3216 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3217 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3218 current_itr = low_latency;
3219
9d5c8243
AK		 3220 switch (current_itr) {
3221 /* counts and packets in update_itr are dependent on these numbers */
3222 case lowest_latency:
78b1f607 3223 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3224 break;
3225 case low_latency:
78b1f607 3226 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3227 break;
3228 case bulk_latency:
78b1f607 3229 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3230 break;
3231 default:
3232 break;
3233 }
3234
3235set_itr_now:
6eb5a7f1
AD		 3236 adapter->rx_ring->total_bytes = 0;
3237 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3238 adapter->tx_ring->total_bytes = 0;
3239 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3240
047e0030 3241 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3242 /* this attempts to bias the interrupt rate towards Bulk
3243 * by adding intermediate steps when interrupt rate is
3244 * increasing */
047e0030
AD		 3245 new_itr = new_itr > q_vector->itr_val ?
3246 max((new_itr * q_vector->itr_val) /
3247 (new_itr + (q_vector->itr_val >> 2)),
3248 new_itr) :
9d5c8243
AK		 3249 new_itr;
3250 /* Don't write the value here; it resets the adapter's
3251 * internal timer, and causes us to delay far longer than
3252 * we should between interrupts. Instead, we write the ITR
3253 * value at the beginning of the next interrupt so the timing
3254 * ends up being correct.
3255 */
047e0030
AD		 3256 q_vector->itr_val = new_itr;
3257 q_vector->set_itr = 1;
9d5c8243
AK		 3258 }
3259
3260 return;
3261}
3262
9d5c8243
AK		 3263#define IGB_TX_FLAGS_CSUM 0x00000001
3264#define IGB_TX_FLAGS_VLAN 0x00000002
3265#define IGB_TX_FLAGS_TSO 0x00000004
3266#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3267#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3268#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3269#define IGB_TX_FLAGS_VLAN_SHIFT 16
3270
85ad76b2 3271static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3272 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3273{
3274 struct e1000_adv_tx_context_desc *context_desc;
3275 unsigned int i;
3276 int err;
3277 struct igb_buffer *buffer_info;
3278 u32 info = 0, tu_cmd = 0;
3279 u32 mss_l4len_idx, l4len;
3280 *hdr_len = 0;
3281
3282 if (skb_header_cloned(skb)) {
3283 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3284 if (err)
3285 return err;
3286 }
3287
3288 l4len = tcp_hdrlen(skb);
3289 *hdr_len += l4len;
3290
3291 if (skb->protocol == htons(ETH_P_IP)) {
3292 struct iphdr *iph = ip_hdr(skb);
3293 iph->tot_len = 0;
3294 iph->check = 0;
3295 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3296 iph->daddr, 0,
3297 IPPROTO_TCP,
3298 0);
3299 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3300 ipv6_hdr(skb)->payload_len = 0;
3301 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3302 &ipv6_hdr(skb)->daddr,
3303 0, IPPROTO_TCP, 0);
3304 }
3305
3306 i = tx_ring->next_to_use;
3307
3308 buffer_info = &tx_ring->buffer_info[i];
3309 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3310 /* VLAN MACLEN IPLEN */
3311 if (tx_flags & IGB_TX_FLAGS_VLAN)
3312 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3313 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3314 *hdr_len += skb_network_offset(skb);
3315 info |= skb_network_header_len(skb);
3316 *hdr_len += skb_network_header_len(skb);
3317 context_desc->vlan_macip_lens = cpu_to_le32(info);
3318
3319 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3320 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3321
3322 if (skb->protocol == htons(ETH_P_IP))
3323 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3324 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3325
3326 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3327
3328 /* MSS L4LEN IDX */
3329 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3330 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3331
73cd78f1 3332 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3333 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3334 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3335
3336 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3337 context_desc->seqnum_seed = 0;
3338
3339 buffer_info->time_stamp = jiffies;
0e014cb1 3340 buffer_info->next_to_watch = i;
9d5c8243
AK		 3341 buffer_info->dma = 0;
3342 i++;
3343 if (i == tx_ring->count)
3344 i = 0;
3345
3346 tx_ring->next_to_use = i;
3347
3348 return true;
3349}
3350
85ad76b2
AD		 3351static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3352 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3353{
3354 struct e1000_adv_tx_context_desc *context_desc;
80785298 3355 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3356 struct igb_buffer *buffer_info;
3357 u32 info = 0, tu_cmd = 0;
80785298 3358 unsigned int i;
9d5c8243
AK		 3359
3360 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3361 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3362 i = tx_ring->next_to_use;
3363 buffer_info = &tx_ring->buffer_info[i];
3364 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3365
3366 if (tx_flags & IGB_TX_FLAGS_VLAN)
3367 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3368 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3369 if (skb->ip_summed == CHECKSUM_PARTIAL)
3370 info |= skb_network_header_len(skb);
3371
3372 context_desc->vlan_macip_lens = cpu_to_le32(info);
3373
3374 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3375
3376 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3377 __be16 protocol;
3378
3379 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3380 const struct vlan_ethhdr *vhdr =
3381 (const struct vlan_ethhdr*)skb->data;
3382
3383 protocol = vhdr->h_vlan_encapsulated_proto;
3384 } else {
3385 protocol = skb->protocol;
3386 }
3387
3388 switch (protocol) {
09640e63 3389 case cpu_to_be16(ETH_P_IP):
9d5c8243 3390 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3391 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3392 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3393 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3394 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3395 break;
09640e63 3396 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3397 /* XXX what about other V6 headers?? */
3398 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3399 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3400 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3401 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3402 break;
3403 default:
3404 if (unlikely(net_ratelimit()))
80785298 3405 dev_warn(&pdev->dev,
44b0cda3
MW		 3406 "partial checksum but proto=%x!\n",
3407 skb->protocol);
3408 break;
3409 }
9d5c8243
AK		 3410 }
3411
3412 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3413 context_desc->seqnum_seed = 0;
85ad76b2 3414 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3415 context_desc->mss_l4len_idx =
85ad76b2 3416 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3417
3418 buffer_info->time_stamp = jiffies;
0e014cb1 3419 buffer_info->next_to_watch = i;
9d5c8243
AK		 3420 buffer_info->dma = 0;
3421
3422 i++;
3423 if (i == tx_ring->count)
3424 i = 0;
3425 tx_ring->next_to_use = i;
3426
3427 return true;
3428 }
9d5c8243
AK		 3429 return false;
3430}
3431
3432#define IGB_MAX_TXD_PWR 16
3433#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3434
80785298 3435static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3436 unsigned int first)
9d5c8243
AK		 3437{
3438 struct igb_buffer *buffer_info;
80785298 3439 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3440 unsigned int len = skb_headlen(skb);
3441 unsigned int count = 0, i;
3442 unsigned int f;
65689fef 3443 dma_addr_t *map;
9d5c8243
AK		 3444
3445 i = tx_ring->next_to_use;
3446
80785298
AD		 3447 if (skb_dma_map(&pdev->dev, skb, DMA_TO_DEVICE)) {
3448 dev_err(&pdev->dev, "TX DMA map failed\n");
65689fef
AD		 3449 return 0;
3450 }
3451
3452 map = skb_shinfo(skb)->dma_maps;
3453
9d5c8243
AK		 3454 buffer_info = &tx_ring->buffer_info[i];
3455 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3456 buffer_info->length = len;
3457 /* set time_stamp *before* dma to help avoid a possible race */
3458 buffer_info->time_stamp = jiffies;
0e014cb1 3459 buffer_info->next_to_watch = i;
042a53a9 3460 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3461
3462 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3463 struct skb_frag_struct *frag;
3464
65689fef
AD		 3465 i++;
3466 if (i == tx_ring->count)
3467 i = 0;
3468
9d5c8243
AK		 3469 frag = &skb_shinfo(skb)->frags[f];
3470 len = frag->size;
3471
3472 buffer_info = &tx_ring->buffer_info[i];
3473 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3474 buffer_info->length = len;
3475 buffer_info->time_stamp = jiffies;
0e014cb1 3476 buffer_info->next_to_watch = i;
65689fef 3477 buffer_info->dma = map[count];
9d5c8243 3478 count++;
9d5c8243
AK		 3479 }
3480
9d5c8243 3481 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3482 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3483
042a53a9 3484 return count + 1;
9d5c8243
AK		 3485}
3486
85ad76b2 3487static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3488 int tx_flags, int count, u32 paylen,
3489 u8 hdr_len)
3490{
3491 union e1000_adv_tx_desc *tx_desc = NULL;
3492 struct igb_buffer *buffer_info;
3493 u32 olinfo_status = 0, cmd_type_len;
3494 unsigned int i;
3495
3496 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3497 E1000_ADVTXD_DCMD_DEXT);
3498
3499 if (tx_flags & IGB_TX_FLAGS_VLAN)
3500 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3501
33af6bcc
PO		 3502 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3503 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3504
9d5c8243
AK		 3505 if (tx_flags & IGB_TX_FLAGS_TSO) {
3506 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3507
3508 /* insert tcp checksum */
3509 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3510
3511 /* insert ip checksum */
3512 if (tx_flags & IGB_TX_FLAGS_IPV4)
3513 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3514
3515 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3516 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3517 }
3518
85ad76b2
AD		 3519 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3520 (tx_flags & (IGB_TX_FLAGS_CSUM |
3521 IGB_TX_FLAGS_TSO |
7dfc16fa 3522 IGB_TX_FLAGS_VLAN)))
85ad76b2 3523 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3524
3525 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3526
3527 i = tx_ring->next_to_use;
3528 while (count--) {
3529 buffer_info = &tx_ring->buffer_info[i];
3530 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3531 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3532 tx_desc->read.cmd_type_len =
3533 cpu_to_le32(cmd_type_len | buffer_info->length);
3534 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3535 i++;
3536 if (i == tx_ring->count)
3537 i = 0;
3538 }
3539
85ad76b2 3540 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 3541 /* Force memory writes to complete before letting h/w
3542 * know there are new descriptors to fetch. (Only
3543 * applicable for weak-ordered memory model archs,
3544 * such as IA-64). */
3545 wmb();
3546
3547 tx_ring->next_to_use = i;
fce99e34 3548 writel(i, tx_ring->tail);
9d5c8243
AK		 3549 /* we need this if more than one processor can write to our tail
3550 * at a time, it syncronizes IO on IA64/Altix systems */
3551 mmiowb();
3552}
3553
e694e964 3554static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3555{
e694e964
AD		 3556 struct net_device *netdev = tx_ring->netdev;
3557
661086df 3558 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3559
9d5c8243
AK		 3560 /* Herbert's original patch had:
3561 * smp_mb__after_netif_stop_queue();
3562 * but since that doesn't exist yet, just open code it. */
3563 smp_mb();
3564
3565 /* We need to check again in a case another CPU has just
3566 * made room available. */
c493ea45 3567 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3568 return -EBUSY;
3569
3570 /* A reprieve! */
661086df 3571 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 3572 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 3573 return 0;
3574}
3575
e694e964 3576static int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3577{
c493ea45 3578 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 3579 return 0;
e694e964 3580 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 3581}
3582
3b29a56d 3583static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3b29a56d 3584 struct igb_ring *tx_ring)
9d5c8243 3585{
e694e964 3586 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
0e014cb1 3587 unsigned int first;
9d5c8243 3588 unsigned int tx_flags = 0;
9d5c8243 3589 u8 hdr_len = 0;
65689fef 3590 int count = 0;
9d5c8243 3591 int tso = 0;
33af6bcc 3592 union skb_shared_tx *shtx;
9d5c8243 3593
9d5c8243
AK		 3594 if (test_bit(__IGB_DOWN, &adapter->state)) {
3595 dev_kfree_skb_any(skb);
3596 return NETDEV_TX_OK;
3597 }
3598
3599 if (skb->len <= 0) {
3600 dev_kfree_skb_any(skb);
3601 return NETDEV_TX_OK;
3602 }
3603
9d5c8243
AK		 3604 /* need: 1 descriptor per page,
3605 * + 2 desc gap to keep tail from touching head,
3606 * + 1 desc for skb->data,
3607 * + 1 desc for context descriptor,
3608 * otherwise try next time */
e694e964 3609 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 3610 /* this is a hard error */
9d5c8243
AK		 3611 return NETDEV_TX_BUSY;
3612 }
33af6bcc
PO		 3613
3614 /*
3615 * TODO: check that there currently is no other packet with
3616 * time stamping in the queue
3617 *
3618 * When doing time stamping, keep the connection to the socket
3619 * a while longer: it is still needed by skb_hwtstamp_tx(),
3620 * called either in igb_tx_hwtstamp() or by our caller when
3621 * doing software time stamping.
3622 */
3623 shtx = skb_tx(skb);
3624 if (unlikely(shtx->hardware)) {
3625 shtx->in_progress = 1;
3626 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3627 }
9d5c8243
AK		 3628
3629 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3630 tx_flags |= IGB_TX_FLAGS_VLAN;
3631 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3632 }
3633
661086df
PWJ		 3634 if (skb->protocol == htons(ETH_P_IP))
3635 tx_flags |= IGB_TX_FLAGS_IPV4;
3636
0e014cb1 3637 first = tx_ring->next_to_use;
85ad76b2
AD		 3638 if (skb_is_gso(skb)) {
3639 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
3640 if (tso < 0) {
3641 dev_kfree_skb_any(skb);
3642 return NETDEV_TX_OK;
3643 }
9d5c8243
AK		 3644 }
3645
3646 if (tso)
3647 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 3648 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 3649 (skb->ip_summed == CHECKSUM_PARTIAL))
3650 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3651
65689fef
AD		 3652 /*
3653 * count reflects descriptors mapped, if 0 then mapping error
3654 * has occured and we need to rewind the descriptor queue
3655 */
80785298 3656 count = igb_tx_map_adv(tx_ring, skb, first);
65689fef 3657
85ad76b2 3658 if (!count) {
65689fef
AD		 3659 dev_kfree_skb_any(skb);
3660 tx_ring->buffer_info[first].time_stamp = 0;
3661 tx_ring->next_to_use = first;
85ad76b2 3662 return NETDEV_TX_OK;
65689fef 3663 }
9d5c8243 3664
85ad76b2
AD		 3665 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3666
3667 /* Make sure there is space in the ring for the next send. */
e694e964 3668 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 3669
9d5c8243
AK		 3670 return NETDEV_TX_OK;
3671}
3672
3b29a56d
SH		 3673static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3674 struct net_device *netdev)
9d5c8243
AK		 3675{
3676 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3677 struct igb_ring *tx_ring;
3678
661086df 3679 int r_idx = 0;
1bfaf07b 3680 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3681 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3682
3683 /* This goes back to the question of how to logically map a tx queue
3684 * to a flow. Right now, performance is impacted slightly negatively
3685 * if using multiple tx queues. If the stack breaks away from a
3686 * single qdisc implementation, we can look at this again. */
e694e964 3687 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 3688}
3689
3690/**
3691 * igb_tx_timeout - Respond to a Tx Hang
3692 * @netdev: network interface device structure
3693 **/
3694static void igb_tx_timeout(struct net_device *netdev)
3695{
3696 struct igb_adapter *adapter = netdev_priv(netdev);
3697 struct e1000_hw *hw = &adapter->hw;
3698
3699 /* Do the reset outside of interrupt context */
3700 adapter->tx_timeout_count++;
3701 schedule_work(&adapter->reset_task);
265de409
AD		 3702 wr32(E1000_EICS,
3703 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3704}
3705
3706static void igb_reset_task(struct work_struct *work)
3707{
3708 struct igb_adapter *adapter;
3709 adapter = container_of(work, struct igb_adapter, reset_task);
3710
3711 igb_reinit_locked(adapter);
3712}
3713
3714/**
3715 * igb_get_stats - Get System Network Statistics
3716 * @netdev: network interface device structure
3717 *
3718 * Returns the address of the device statistics structure.
3719 * The statistics are actually updated from the timer callback.
3720 **/
73cd78f1 3721static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3722{
9d5c8243 3723 /* only return the current stats */
8d24e933 3724 return &netdev->stats;
9d5c8243
AK		 3725}
3726
3727/**
3728 * igb_change_mtu - Change the Maximum Transfer Unit
3729 * @netdev: network interface device structure
3730 * @new_mtu: new value for maximum frame size
3731 *
3732 * Returns 0 on success, negative on failure
3733 **/
3734static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3735{
3736 struct igb_adapter *adapter = netdev_priv(netdev);
3737 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 3738 u32 rx_buffer_len, i;
9d5c8243
AK		 3739
3740 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3741 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3742 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3743 return -EINVAL;
3744 }
3745
9d5c8243
AK		 3746 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3747 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3748 return -EINVAL;
3749 }
3750
3751 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3752 msleep(1);
73cd78f1 3753
9d5c8243
AK		 3754 /* igb_down has a dependency on max_frame_size */
3755 adapter->max_frame_size = max_frame;
9d5c8243
AK		 3756 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3757 * means we reserve 2 more, this pushes us to allocate from the next
3758 * larger slab size.
3759 * i.e. RXBUFFER_2048 --> size-4096 slab
3760 */
3761
7d95b717 3762 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 3763 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3764 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 3765 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 3766 else
4c844851
AD		 3767 rx_buffer_len = IGB_RXBUFFER_128;
3768
3769 if (netif_running(netdev))
3770 igb_down(adapter);
9d5c8243
AK		 3771
3772 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3773 netdev->mtu, new_mtu);
3774 netdev->mtu = new_mtu;
3775
4c844851
AD		 3776 for (i = 0; i < adapter->num_rx_queues; i++)
3777 adapter->rx_ring[i].rx_buffer_len = rx_buffer_len;
3778
9d5c8243
AK		 3779 if (netif_running(netdev))
3780 igb_up(adapter);
3781 else
3782 igb_reset(adapter);
3783
3784 clear_bit(__IGB_RESETTING, &adapter->state);
3785
3786 return 0;
3787}
3788
3789/**
3790 * igb_update_stats - Update the board statistics counters
3791 * @adapter: board private structure
3792 **/
3793
3794void igb_update_stats(struct igb_adapter *adapter)
3795{
8d24e933 3796 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3797 struct e1000_hw *hw = &adapter->hw;
3798 struct pci_dev *pdev = adapter->pdev;
3799 u16 phy_tmp;
3800
3801#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3802
3803 /*
3804 * Prevent stats update while adapter is being reset, or if the pci
3805 * connection is down.
3806 */
3807 if (adapter->link_speed == 0)
3808 return;
3809 if (pci_channel_offline(pdev))
3810 return;
3811
3812 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3813 adapter->stats.gprc += rd32(E1000_GPRC);
3814 adapter->stats.gorc += rd32(E1000_GORCL);
3815 rd32(E1000_GORCH); /* clear GORCL */
3816 adapter->stats.bprc += rd32(E1000_BPRC);
3817 adapter->stats.mprc += rd32(E1000_MPRC);
3818 adapter->stats.roc += rd32(E1000_ROC);
3819
3820 adapter->stats.prc64 += rd32(E1000_PRC64);
3821 adapter->stats.prc127 += rd32(E1000_PRC127);
3822 adapter->stats.prc255 += rd32(E1000_PRC255);
3823 adapter->stats.prc511 += rd32(E1000_PRC511);
3824 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3825 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3826 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3827 adapter->stats.sec += rd32(E1000_SEC);
3828
3829 adapter->stats.mpc += rd32(E1000_MPC);
3830 adapter->stats.scc += rd32(E1000_SCC);
3831 adapter->stats.ecol += rd32(E1000_ECOL);
3832 adapter->stats.mcc += rd32(E1000_MCC);
3833 adapter->stats.latecol += rd32(E1000_LATECOL);
3834 adapter->stats.dc += rd32(E1000_DC);
3835 adapter->stats.rlec += rd32(E1000_RLEC);
3836 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3837 adapter->stats.xontxc += rd32(E1000_XONTXC);
3838 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3839 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3840 adapter->stats.fcruc += rd32(E1000_FCRUC);
3841 adapter->stats.gptc += rd32(E1000_GPTC);
3842 adapter->stats.gotc += rd32(E1000_GOTCL);
3843 rd32(E1000_GOTCH); /* clear GOTCL */
3844 adapter->stats.rnbc += rd32(E1000_RNBC);
3845 adapter->stats.ruc += rd32(E1000_RUC);
3846 adapter->stats.rfc += rd32(E1000_RFC);
3847 adapter->stats.rjc += rd32(E1000_RJC);
3848 adapter->stats.tor += rd32(E1000_TORH);
3849 adapter->stats.tot += rd32(E1000_TOTH);
3850 adapter->stats.tpr += rd32(E1000_TPR);
3851
3852 adapter->stats.ptc64 += rd32(E1000_PTC64);
3853 adapter->stats.ptc127 += rd32(E1000_PTC127);
3854 adapter->stats.ptc255 += rd32(E1000_PTC255);
3855 adapter->stats.ptc511 += rd32(E1000_PTC511);
3856 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3857 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3858
3859 adapter->stats.mptc += rd32(E1000_MPTC);
3860 adapter->stats.bptc += rd32(E1000_BPTC);
3861
3862 /* used for adaptive IFS */
3863
3864 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3865 adapter->stats.tpt += hw->mac.tx_packet_delta;
3866 hw->mac.collision_delta = rd32(E1000_COLC);
3867 adapter->stats.colc += hw->mac.collision_delta;
3868
3869 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3870 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3871 adapter->stats.tncrs += rd32(E1000_TNCRS);
3872 adapter->stats.tsctc += rd32(E1000_TSCTC);
3873 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3874
3875 adapter->stats.iac += rd32(E1000_IAC);
3876 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3877 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3878 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3879 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3880 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3881 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3882 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3883 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3884
3885 /* Fill out the OS statistics structure */
8d24e933
AK		 3886 netdev->stats.multicast = adapter->stats.mprc;
3887 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3888
3889 /* Rx Errors */
3890
8c0ab70a
JDB		 3891 if (hw->mac.type != e1000_82575) {
3892 u32 rqdpc_tmp;
3ea73afa 3893 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3894 int i;
3895 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3896 * Queue Drop Packet Count) stats only gets incremented, if
3897 * the DROP_EN but it set (in the SRRCTL register for that
3898 * queue). If DROP_EN bit is NOT set, then the some what
3899 * equivalent count is stored in RNBC (not per queue basis).
3900 * Also note the drop count is due to lack of available
3901 * descriptors.
3902 */
3903 for (i = 0; i < adapter->num_rx_queues; i++) {
3904 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3905 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3906 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3907 }
8d24e933 3908 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3909 }
3910
3ea73afa
JDB		 3911 /* Note RNBC (Receive No Buffers Count) is an not an exact
3912 * drop count as the hardware FIFO might save the day. Thats
3913 * one of the reason for saving it in rx_fifo_errors, as its
3914 * potentially not a true drop.
3915 */
8d24e933 3916 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3917
9d5c8243 3918 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3919 * our own version based on RUC and ROC */
8d24e933 3920 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3921 adapter->stats.crcerrs + adapter->stats.algnerrc +
3922 adapter->stats.ruc + adapter->stats.roc +
3923 adapter->stats.cexterr;
8d24e933 3924 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3925 adapter->stats.roc;
8d24e933
AK		 3926 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3927 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3928 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3929
3930 /* Tx Errors */
8d24e933 3931 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3932 adapter->stats.latecol;
8d24e933
AK		 3933 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3934 netdev->stats.tx_window_errors = adapter->stats.latecol;
3935 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3936
3937 /* Tx Dropped needs to be maintained elsewhere */
3938
3939 /* Phy Stats */
3940 if (hw->phy.media_type == e1000_media_type_copper) {
3941 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3942 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3943 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3944 adapter->phy_stats.idle_errors += phy_tmp;
3945 }
3946 }
3947
3948 /* Management Stats */
3949 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3950 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3951 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3952}
3953
9d5c8243
AK		 3954static irqreturn_t igb_msix_other(int irq, void *data)
3955{
047e0030 3956 struct igb_adapter *adapter = data;
9d5c8243 3957 struct e1000_hw *hw = &adapter->hw;
844290e5 3958 u32 icr = rd32(E1000_ICR);
844290e5 3959 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3960
047e0030 3961 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3962 /* HW is reporting DMA is out of sync */
3963 adapter->stats.doosync++;
3964 }
eebbbdba 3965
4ae196df
AD		 3966 /* Check for a mailbox event */
3967 if (icr & E1000_ICR_VMMB)
3968 igb_msg_task(adapter);
3969
3970 if (icr & E1000_ICR_LSC) {
3971 hw->mac.get_link_status = 1;
3972 /* guard against interrupt when we're going down */
3973 if (!test_bit(__IGB_DOWN, &adapter->state))
3974 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3975 }
3976
3977 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3978 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3979
3980 return IRQ_HANDLED;
3981}
3982
047e0030 3983static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 3984{
047e0030 3985 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 3986
047e0030
AD		 3987 if (!q_vector->set_itr)
3988 return;
73cd78f1 3989
047e0030
AD		 3990 if (!itr_val)
3991 itr_val = 0x4;
661086df 3992
047e0030
AD		 3993 if (q_vector->itr_shift)
3994 itr_val |= itr_val << q_vector->itr_shift;
661086df 3995 else
047e0030 3996 itr_val |= 0x8000000;
661086df 3997
047e0030
AD		 3998 writel(itr_val, q_vector->itr_register);
3999 q_vector->set_itr = 0;
6eb5a7f1
AD		 4000}
4001
047e0030 4002static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4003{
047e0030 4004 struct igb_q_vector *q_vector = data;
9d5c8243 4005
047e0030
AD		 4006 /* Write the ITR value calculated from the previous interrupt. */
4007 igb_write_itr(q_vector);
9d5c8243 4008
047e0030 4009 napi_schedule(&q_vector->napi);
844290e5 4010
047e0030 4011 return IRQ_HANDLED;
fe4506b6
JC		 4012}
4013
421e02f0 4014#ifdef CONFIG_IGB_DCA
047e0030 4015static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4016{
047e0030 4017 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4018 struct e1000_hw *hw = &adapter->hw;
4019 int cpu = get_cpu();
fe4506b6 4020
047e0030
AD		 4021 if (q_vector->cpu == cpu)
4022 goto out_no_update;
4023
4024 if (q_vector->tx_ring) {
4025 int q = q_vector->tx_ring->reg_idx;
4026 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4027 if (hw->mac.type == e1000_82575) {
4028 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4029 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4030 } else {
047e0030
AD		 4031 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4032 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4033 E1000_DCA_TXCTRL_CPUID_SHIFT;
4034 }
4035 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4036 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4037 }
4038 if (q_vector->rx_ring) {
4039 int q = q_vector->rx_ring->reg_idx;
4040 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4041 if (hw->mac.type == e1000_82575) {
2d064c06 4042 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4043 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4044 } else {
4045 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4046 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4047 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4048 }
fe4506b6
JC		 4049 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4050 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4051 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4052 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4053 }
047e0030
AD		 4054 q_vector->cpu = cpu;
4055out_no_update:
fe4506b6
JC		 4056 put_cpu();
4057}
4058
4059static void igb_setup_dca(struct igb_adapter *adapter)
4060{
7e0e99ef 4061 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4062 int i;
4063
7dfc16fa 4064 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4065 return;
4066
7e0e99ef
AD		 4067 /* Always use CB2 mode, difference is masked in the CB driver. */
4068 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4069
047e0030
AD		 4070 for (i = 0; i < adapter->num_q_vectors; i++) {
4071 struct igb_q_vector *q_vector = adapter->q_vector[i];
4072 q_vector->cpu = -1;
4073 igb_update_dca(q_vector);
fe4506b6
JC		 4074 }
4075}
4076
4077static int __igb_notify_dca(struct device *dev, void *data)
4078{
4079 struct net_device *netdev = dev_get_drvdata(dev);
4080 struct igb_adapter *adapter = netdev_priv(netdev);
4081 struct e1000_hw *hw = &adapter->hw;
4082 unsigned long event = *(unsigned long *)data;
4083
4084 switch (event) {
4085 case DCA_PROVIDER_ADD:
4086 /* if already enabled, don't do it again */
7dfc16fa 4087 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4088 break;
fe4506b6
JC		 4089 /* Always use CB2 mode, difference is masked
4090 * in the CB driver. */
cbd347ad 4091 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4092 if (dca_add_requester(dev) == 0) {
bbd98fe4 4093 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4094 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4095 igb_setup_dca(adapter);
4096 break;
4097 }
4098 /* Fall Through since DCA is disabled. */
4099 case DCA_PROVIDER_REMOVE:
7dfc16fa 4100 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4101 /* without this a class_device is left
047e0030 4102 * hanging around in the sysfs model */
fe4506b6
JC		 4103 dca_remove_requester(dev);
4104 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4105 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4106 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4107 }
4108 break;
4109 }
bbd98fe4 4110
fe4506b6 4111 return 0;
9d5c8243
AK		 4112}
4113
fe4506b6
JC		 4114static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4115 void *p)
4116{
4117 int ret_val;
4118
4119 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4120 __igb_notify_dca);
4121
4122 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4123}
421e02f0 4124#endif /* CONFIG_IGB_DCA */
9d5c8243 4125
4ae196df
AD		 4126static void igb_ping_all_vfs(struct igb_adapter *adapter)
4127{
4128 struct e1000_hw *hw = &adapter->hw;
4129 u32 ping;
4130 int i;
4131
4132 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4133 ping = E1000_PF_CONTROL_MSG;
4134 if (adapter->vf_data[i].clear_to_send)
4135 ping |= E1000_VT_MSGTYPE_CTS;
4136 igb_write_mbx(hw, &ping, 1, i);
4137 }
4138}
4139
4140static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4141 u32 *msgbuf, u32 vf)
4142{
4143 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4144 u16 *hash_list = (u16 *)&msgbuf[1];
4145 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4146 int i;
4147
4148 /* only up to 30 hash values supported */
4149 if (n > 30)
4150 n = 30;
4151
4152 /* salt away the number of multi cast addresses assigned
4153 * to this VF for later use to restore when the PF multi cast
4154 * list changes
4155 */
4156 vf_data->num_vf_mc_hashes = n;
4157
4158 /* VFs are limited to using the MTA hash table for their multicast
4159 * addresses */
4160 for (i = 0; i < n; i++)
a419aef8 4161 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4162
4163 /* Flush and reset the mta with the new values */
ff41f8dc 4164 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4165
4166 return 0;
4167}
4168
4169static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4170{
4171 struct e1000_hw *hw = &adapter->hw;
4172 struct vf_data_storage *vf_data;
4173 int i, j;
4174
4175 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4176 vf_data = &adapter->vf_data[i];
75f4f382 4177 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4178 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4179 }
4180}
4181
4182static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4183{
4184 struct e1000_hw *hw = &adapter->hw;
4185 u32 pool_mask, reg, vid;
4186 int i;
4187
4188 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4189
4190 /* Find the vlan filter for this id */
4191 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4192 reg = rd32(E1000_VLVF(i));
4193
4194 /* remove the vf from the pool */
4195 reg &= ~pool_mask;
4196
4197 /* if pool is empty then remove entry from vfta */
4198 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4199 (reg & E1000_VLVF_VLANID_ENABLE)) {
4200 reg = 0;
4201 vid = reg & E1000_VLVF_VLANID_MASK;
4202 igb_vfta_set(hw, vid, false);
4203 }
4204
4205 wr32(E1000_VLVF(i), reg);
4206 }
ae641bdc
AD		 4207
4208 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4209}
4210
4211static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4212{
4213 struct e1000_hw *hw = &adapter->hw;
4214 u32 reg, i;
4215
4216 /* It is an error to call this function when VFs are not enabled */
4217 if (!adapter->vfs_allocated_count)
4218 return -1;
4219
4220 /* Find the vlan filter for this id */
4221 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4222 reg = rd32(E1000_VLVF(i));
4223 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4224 vid == (reg & E1000_VLVF_VLANID_MASK))
4225 break;
4226 }
4227
4228 if (add) {
4229 if (i == E1000_VLVF_ARRAY_SIZE) {
4230 /* Did not find a matching VLAN ID entry that was
4231 * enabled. Search for a free filter entry, i.e.
4232 * one without the enable bit set
4233 */
4234 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4235 reg = rd32(E1000_VLVF(i));
4236 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4237 break;
4238 }
4239 }
4240 if (i < E1000_VLVF_ARRAY_SIZE) {
4241 /* Found an enabled/available entry */
4242 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4243
4244 /* if !enabled we need to set this up in vfta */
4245 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4246 /* add VID to filter table, if bit already set
4247 * PF must have added it outside of table */
4248 if (igb_vfta_set(hw, vid, true))
4249 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4250 adapter->vfs_allocated_count);
4ae196df
AD		 4251 reg |= E1000_VLVF_VLANID_ENABLE;
4252 }
cad6d05f
AD		 4253 reg &= ~E1000_VLVF_VLANID_MASK;
4254 reg |= vid;
4ae196df
AD		 4255
4256 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4257
4258 /* do not modify RLPML for PF devices */
4259 if (vf >= adapter->vfs_allocated_count)
4260 return 0;
4261
4262 if (!adapter->vf_data[vf].vlans_enabled) {
4263 u32 size;
4264 reg = rd32(E1000_VMOLR(vf));
4265 size = reg & E1000_VMOLR_RLPML_MASK;
4266 size += 4;
4267 reg &= ~E1000_VMOLR_RLPML_MASK;
4268 reg |= size;
4269 wr32(E1000_VMOLR(vf), reg);
4270 }
4271 adapter->vf_data[vf].vlans_enabled++;
4272
4ae196df
AD		 4273 return 0;
4274 }
4275 } else {
4276 if (i < E1000_VLVF_ARRAY_SIZE) {
4277 /* remove vf from the pool */
4278 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4279 /* if pool is empty then remove entry from vfta */
4280 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4281 reg = 0;
4282 igb_vfta_set(hw, vid, false);
4283 }
4284 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4285
4286 /* do not modify RLPML for PF devices */
4287 if (vf >= adapter->vfs_allocated_count)
4288 return 0;
4289
4290 adapter->vf_data[vf].vlans_enabled--;
4291 if (!adapter->vf_data[vf].vlans_enabled) {
4292 u32 size;
4293 reg = rd32(E1000_VMOLR(vf));
4294 size = reg & E1000_VMOLR_RLPML_MASK;
4295 size -= 4;
4296 reg &= ~E1000_VMOLR_RLPML_MASK;
4297 reg |= size;
4298 wr32(E1000_VMOLR(vf), reg);
4299 }
4ae196df
AD		 4300 return 0;
4301 }
4302 }
4303 return -1;
4304}
4305
4306static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4307{
4308 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4309 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4310
4311 return igb_vlvf_set(adapter, vid, add, vf);
4312}
4313
4314static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4315{
4316 struct e1000_hw *hw = &adapter->hw;
4317
4318 /* disable mailbox functionality for vf */
4319 adapter->vf_data[vf].clear_to_send = false;
4320
4321 /* reset offloads to defaults */
4322 igb_set_vmolr(hw, vf);
4323
4324 /* reset vlans for device */
4325 igb_clear_vf_vfta(adapter, vf);
4326
4327 /* reset multicast table array for vf */
4328 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4329
4330 /* Flush and reset the mta with the new values */
ff41f8dc 4331 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4332}
4333
4334static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4335{
4336 struct e1000_hw *hw = &adapter->hw;
4337 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4338 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4339 u32 reg, msgbuf[3];
4340 u8 *addr = (u8 *)(&msgbuf[1]);
4341
4342 /* process all the same items cleared in a function level reset */
4343 igb_vf_reset_event(adapter, vf);
4344
4345 /* set vf mac address */
26ad9178 4346 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4347
4348 /* enable transmit and receive for vf */
4349 reg = rd32(E1000_VFTE);
4350 wr32(E1000_VFTE, reg | (1 << vf));
4351 reg = rd32(E1000_VFRE);
4352 wr32(E1000_VFRE, reg | (1 << vf));
4353
4354 /* enable mailbox functionality for vf */
4355 adapter->vf_data[vf].clear_to_send = true;
4356
4357 /* reply to reset with ack and vf mac address */
4358 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4359 memcpy(addr, vf_mac, 6);
4360 igb_write_mbx(hw, msgbuf, 3, vf);
4361}
4362
4363static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4364{
4365 unsigned char *addr = (char *)&msg[1];
4366 int err = -1;
4367
4368 if (is_valid_ether_addr(addr))
4369 err = igb_set_vf_mac(adapter, vf, addr);
4370
4371 return err;
4372
4373}
4374
4375static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4376{
4377 struct e1000_hw *hw = &adapter->hw;
4378 u32 msg = E1000_VT_MSGTYPE_NACK;
4379
4380 /* if device isn't clear to send it shouldn't be reading either */
4381 if (!adapter->vf_data[vf].clear_to_send)
4382 igb_write_mbx(hw, &msg, 1, vf);
4383}
4384
4385
4386static void igb_msg_task(struct igb_adapter *adapter)
4387{
4388 struct e1000_hw *hw = &adapter->hw;
4389 u32 vf;
4390
4391 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4392 /* process any reset requests */
4393 if (!igb_check_for_rst(hw, vf)) {
4394 adapter->vf_data[vf].clear_to_send = false;
4395 igb_vf_reset_event(adapter, vf);
4396 }
4397
4398 /* process any messages pending */
4399 if (!igb_check_for_msg(hw, vf))
4400 igb_rcv_msg_from_vf(adapter, vf);
4401
4402 /* process any acks */
4403 if (!igb_check_for_ack(hw, vf))
4404 igb_rcv_ack_from_vf(adapter, vf);
4405
4406 }
4407}
4408
4409static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4410{
4411 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4412 u32 msgbuf[mbx_size];
4413 struct e1000_hw *hw = &adapter->hw;
4414 s32 retval;
4415
4416 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4417
4418 if (retval)
4419 dev_err(&adapter->pdev->dev,
4420 "Error receiving message from VF\n");
4421
4422 /* this is a message we already processed, do nothing */
4423 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4424 return retval;
4425
4426 /*
4427 * until the vf completes a reset it should not be
4428 * allowed to start any configuration.
4429 */
4430
4431 if (msgbuf[0] == E1000_VF_RESET) {
4432 igb_vf_reset_msg(adapter, vf);
4433
4434 return retval;
4435 }
4436
4437 if (!adapter->vf_data[vf].clear_to_send) {
4438 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4439 igb_write_mbx(hw, msgbuf, 1, vf);
4440 return retval;
4441 }
4442
4443 switch ((msgbuf[0] & 0xFFFF)) {
4444 case E1000_VF_SET_MAC_ADDR:
4445 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4446 break;
4447 case E1000_VF_SET_MULTICAST:
4448 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4449 break;
4450 case E1000_VF_SET_LPE:
4451 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4452 break;
4453 case E1000_VF_SET_VLAN:
4454 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4455 break;
4456 default:
4457 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4458 retval = -1;
4459 break;
4460 }
4461
4462 /* notify the VF of the results of what it sent us */
4463 if (retval)
4464 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4465 else
4466 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4467
4468 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4469
4470 igb_write_mbx(hw, msgbuf, 1, vf);
4471
4472 return retval;
4473}
4474
68d480c4
AD		 4475/**
4476 * igb_set_uta - Set unicast filter table address
4477 * @adapter: board private structure
4478 *
4479 * The unicast table address is a register array of 32-bit registers.
4480 * The table is meant to be used in a way similar to how the MTA is used
4481 * however due to certain limitations in the hardware it is necessary to
4482 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4483 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4484 **/
4485static void igb_set_uta(struct igb_adapter *adapter)
4486{
4487 struct e1000_hw *hw = &adapter->hw;
4488 int i;
4489
4490 /* The UTA table only exists on 82576 hardware and newer */
4491 if (hw->mac.type < e1000_82576)
4492 return;
4493
4494 /* we only need to do this if VMDq is enabled */
4495 if (!adapter->vfs_allocated_count)
4496 return;
4497
4498 for (i = 0; i < hw->mac.uta_reg_count; i++)
4499 array_wr32(E1000_UTA, i, ~0);
4500}
4501
9d5c8243
AK		 4502/**
4503 * igb_intr_msi - Interrupt Handler
4504 * @irq: interrupt number
4505 * @data: pointer to a network interface device structure
4506 **/
4507static irqreturn_t igb_intr_msi(int irq, void *data)
4508{
047e0030
AD		 4509 struct igb_adapter *adapter = data;
4510 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4511 struct e1000_hw *hw = &adapter->hw;
4512 /* read ICR disables interrupts using IAM */
4513 u32 icr = rd32(E1000_ICR);
4514
047e0030 4515 igb_write_itr(q_vector);
9d5c8243 4516
047e0030 4517 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4518 /* HW is reporting DMA is out of sync */
4519 adapter->stats.doosync++;
4520 }
4521
9d5c8243
AK		 4522 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4523 hw->mac.get_link_status = 1;
4524 if (!test_bit(__IGB_DOWN, &adapter->state))
4525 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4526 }
4527
047e0030 4528 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4529
4530 return IRQ_HANDLED;
4531}
4532
4533/**
4a3c6433 4534 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4535 * @irq: interrupt number
4536 * @data: pointer to a network interface device structure
4537 **/
4538static irqreturn_t igb_intr(int irq, void *data)
4539{
047e0030
AD		 4540 struct igb_adapter *adapter = data;
4541 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4542 struct e1000_hw *hw = &adapter->hw;
4543 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4544 * need for the IMC write */
4545 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4546 if (!icr)
4547 return IRQ_NONE; /* Not our interrupt */
4548
047e0030 4549 igb_write_itr(q_vector);
9d5c8243
AK		 4550
4551 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4552 * not set, then the adapter didn't send an interrupt */
4553 if (!(icr & E1000_ICR_INT_ASSERTED))
4554 return IRQ_NONE;
4555
047e0030 4556 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4557 /* HW is reporting DMA is out of sync */
4558 adapter->stats.doosync++;
4559 }
4560
9d5c8243
AK		 4561 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4562 hw->mac.get_link_status = 1;
4563 /* guard against interrupt when we're going down */
4564 if (!test_bit(__IGB_DOWN, &adapter->state))
4565 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4566 }
4567
047e0030 4568 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4569
4570 return IRQ_HANDLED;
4571}
4572
047e0030 4573static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4574{
047e0030 4575 struct igb_adapter *adapter = q_vector->adapter;
46544258 4576 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4577
46544258 4578 if (adapter->itr_setting & 3) {
047e0030 4579 if (!adapter->msix_entries)
6eb5a7f1 4580 igb_set_itr(adapter);
46544258 4581 else
047e0030 4582 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4583 }
4584
46544258
AD		 4585 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4586 if (adapter->msix_entries)
047e0030 4587 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4588 else
4589 igb_irq_enable(adapter);
4590 }
9d5c8243
AK		 4591}
4592
46544258
AD		 4593/**
4594 * igb_poll - NAPI Rx polling callback
4595 * @napi: napi polling structure
4596 * @budget: count of how many packets we should handle
4597 **/
4598static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4599{
047e0030
AD		 4600 struct igb_q_vector *q_vector = container_of(napi,
4601 struct igb_q_vector,
4602 napi);
4603 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4604
421e02f0 4605#ifdef CONFIG_IGB_DCA
047e0030
AD		 4606 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4607 igb_update_dca(q_vector);
fe4506b6 4608#endif
047e0030
AD		 4609 if (q_vector->tx_ring)
4610 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4611
047e0030
AD		 4612 if (q_vector->rx_ring)
4613 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4614
4615 if (!tx_clean_complete)
4616 work_done = budget;
46544258 4617
9d5c8243 4618 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4619 if (work_done < budget) {
288379f0 4620 napi_complete(napi);
047e0030 4621 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4622 }
4623
46544258 4624 return work_done;
9d5c8243 4625}
6d8126f9 4626
33af6bcc
PO		 4627/**
4628 * igb_hwtstamp - utility function which checks for TX time stamp
4629 * @adapter: board private structure
4630 * @skb: packet that was just sent
4631 *
4632 * If we were asked to do hardware stamping and such a time stamp is
4633 * available, then it must have been for this skb here because we only
4634 * allow only one such packet into the queue.
4635 */
4636static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4637{
4638 union skb_shared_tx *shtx = skb_tx(skb);
4639 struct e1000_hw *hw = &adapter->hw;
4640
4641 if (unlikely(shtx->hardware)) {
4642 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4643 if (valid) {
4644 u64 regval = rd32(E1000_TXSTMPL);
4645 u64 ns;
4646 struct skb_shared_hwtstamps shhwtstamps;
4647
4648 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4649 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4650 ns = timecounter_cyc2time(&adapter->clock,
4651 regval);
4652 timecompare_update(&adapter->compare, ns);
4653 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4654 shhwtstamps.syststamp =
4655 timecompare_transform(&adapter->compare, ns);
4656 skb_tstamp_tx(skb, &shhwtstamps);
4657 }
33af6bcc
PO		 4658 }
4659}
4660
9d5c8243
AK		 4661/**
4662 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4663 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4664 * returns true if ring is completely cleaned
4665 **/
047e0030 4666static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4667{
047e0030
AD		 4668 struct igb_adapter *adapter = q_vector->adapter;
4669 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 4670 struct net_device *netdev = tx_ring->netdev;
0e014cb1 4671 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4672 struct igb_buffer *buffer_info;
4673 struct sk_buff *skb;
0e014cb1 4674 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4675 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4676 unsigned int i, eop, count = 0;
4677 bool cleaned = false;
9d5c8243 4678
9d5c8243 4679 i = tx_ring->next_to_clean;
0e014cb1
AD		 4680 eop = tx_ring->buffer_info[i].next_to_watch;
4681 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4682
4683 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4684 (count < tx_ring->count)) {
4685 for (cleaned = false; !cleaned; count++) {
4686 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4687 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4688 cleaned = (i == eop);
9d5c8243
AK		 4689 skb = buffer_info->skb;
4690
4691 if (skb) {
4692 unsigned int segs, bytecount;
4693 /* gso_segs is currently only valid for tcp */
4694 segs = skb_shinfo(skb)->gso_segs ?: 1;
4695 /* multiply data chunks by size of headers */
4696 bytecount = ((segs - 1) * skb_headlen(skb)) +
4697 skb->len;
4698 total_packets += segs;
4699 total_bytes += bytecount;
33af6bcc
PO		 4700
4701 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4702 }
4703
80785298 4704 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 4705 tx_desc->wb.status = 0;
9d5c8243
AK		 4706
4707 i++;
4708 if (i == tx_ring->count)
4709 i = 0;
9d5c8243 4710 }
0e014cb1
AD		 4711 eop = tx_ring->buffer_info[i].next_to_watch;
4712 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4713 }
4714
9d5c8243
AK		 4715 tx_ring->next_to_clean = i;
4716
fc7d345d 4717 if (unlikely(count &&
9d5c8243 4718 netif_carrier_ok(netdev) &&
c493ea45 4719 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4720 /* Make sure that anybody stopping the queue after this
4721 * sees the new next_to_clean.
4722 */
4723 smp_mb();
661086df
PWJ		 4724 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4725 !(test_bit(__IGB_DOWN, &adapter->state))) {
4726 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 4727 tx_ring->tx_stats.restart_queue++;
661086df 4728 }
9d5c8243
AK		 4729 }
4730
4731 if (tx_ring->detect_tx_hung) {
4732 /* Detect a transmit hang in hardware, this serializes the
4733 * check with the clearing of time_stamp and movement of i */
4734 tx_ring->detect_tx_hung = false;
4735 if (tx_ring->buffer_info[i].time_stamp &&
4736 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4737 (adapter->tx_timeout_factor * HZ))
4738 && !(rd32(E1000_STATUS) &
4739 E1000_STATUS_TXOFF)) {
4740
9d5c8243 4741 /* detected Tx unit hang */
80785298 4742 dev_err(&tx_ring->pdev->dev,
9d5c8243 4743 "Detected Tx Unit Hang\n"
2d064c06 4744 " Tx Queue <%d>\n"
9d5c8243
AK		 4745 " TDH <%x>\n"
4746 " TDT <%x>\n"
4747 " next_to_use <%x>\n"
4748 " next_to_clean <%x>\n"
9d5c8243
AK		 4749 "buffer_info[next_to_clean]\n"
4750 " time_stamp <%lx>\n"
0e014cb1 4751 " next_to_watch <%x>\n"
9d5c8243
AK		 4752 " jiffies <%lx>\n"
4753 " desc.status <%x>\n",
2d064c06 4754 tx_ring->queue_index,
fce99e34
AD		 4755 readl(tx_ring->head),
4756 readl(tx_ring->tail),
9d5c8243
AK		 4757 tx_ring->next_to_use,
4758 tx_ring->next_to_clean,
9d5c8243 4759 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4760 eop,
9d5c8243 4761 jiffies,
0e014cb1 4762 eop_desc->wb.status);
661086df 4763 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4764 }
4765 }
4766 tx_ring->total_bytes += total_bytes;
4767 tx_ring->total_packets += total_packets;
e21ed353
AD		 4768 tx_ring->tx_stats.bytes += total_bytes;
4769 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4770 netdev->stats.tx_bytes += total_bytes;
4771 netdev->stats.tx_packets += total_packets;
0e014cb1 4772 return (count < tx_ring->count);
9d5c8243
AK		 4773}
4774
9d5c8243
AK		 4775/**
4776 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4777 * @q_vector: structure containing interrupt and ring information
4778 * @skb: packet to send up
4779 * @vlan_tag: vlan tag for packet
9d5c8243 4780 **/
047e0030
AD		 4781static void igb_receive_skb(struct igb_q_vector *q_vector,
4782 struct sk_buff *skb,
4783 u16 vlan_tag)
4784{
4785 struct igb_adapter *adapter = q_vector->adapter;
4786
4787 if (vlan_tag)
4788 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4789 vlan_tag, skb);
182ff8df 4790 else
047e0030 4791 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4792}
4793
04a5fcaa 4794static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 4795 u32 status_err, struct sk_buff *skb)
4796{
4797 skb->ip_summed = CHECKSUM_NONE;
4798
4799 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 4800 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
4801 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 4802 return;
85ad76b2 4803
9d5c8243
AK		 4804 /* TCP/UDP checksum error bit is set */
4805 if (status_err &
4806 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4807 /*
4808 * work around errata with sctp packets where the TCPE aka
4809 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4810 * packets, (aka let the stack check the crc32c)
4811 */
85ad76b2
AD		 4812 if ((skb->len == 60) &&
4813 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 4814 ring->rx_stats.csum_err++;
85ad76b2 4815
9d5c8243 4816 /* let the stack verify checksum errors */
9d5c8243
AK		 4817 return;
4818 }
4819 /* It must be a TCP or UDP packet with a valid checksum */
4820 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4821 skb->ip_summed = CHECKSUM_UNNECESSARY;
4822
85ad76b2 4823 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4824}
4825
4c844851 4826static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 4827 union e1000_adv_rx_desc *rx_desc)
4828{
4829 /* HW will not DMA in data larger than the given buffer, even if it
4830 * parses the (NFS, of course) header to be larger. In that case, it
4831 * fills the header buffer and spills the rest into the page.
4832 */
4833 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4834 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 4835 if (hlen > rx_ring->rx_buffer_len)
4836 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 4837 return hlen;
4838}
4839
047e0030
AD		 4840static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4841 int *work_done, int budget)
9d5c8243 4842{
047e0030 4843 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4844 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 4845 struct net_device *netdev = rx_ring->netdev;
33af6bcc 4846 struct e1000_hw *hw = &adapter->hw;
80785298 4847 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 4848 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4849 struct igb_buffer *buffer_info , *next_buffer;
4850 struct sk_buff *skb;
9d5c8243
AK		 4851 bool cleaned = false;
4852 int cleaned_count = 0;
4853 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4854 unsigned int i;
2d94d8ab
AD		 4855 u32 staterr;
4856 u16 length;
047e0030 4857 u16 vlan_tag;
9d5c8243
AK		 4858
4859 i = rx_ring->next_to_clean;
69d3ca53 4860 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4861 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4862 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4863
4864 while (staterr & E1000_RXD_STAT_DD) {
4865 if (*work_done >= budget)
4866 break;
4867 (*work_done)++;
9d5c8243 4868
69d3ca53
AD		 4869 skb = buffer_info->skb;
4870 prefetch(skb->data - NET_IP_ALIGN);
4871 buffer_info->skb = NULL;
4872
4873 i++;
4874 if (i == rx_ring->count)
4875 i = 0;
4876 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4877 prefetch(next_rxd);
4878 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4879
4880 length = le16_to_cpu(rx_desc->wb.upper.length);
4881 cleaned = true;
4882 cleaned_count++;
4883
2d94d8ab 4884 if (buffer_info->dma) {
bf36c1a0 4885 pci_unmap_single(pdev, buffer_info->dma,
4c844851 4886 rx_ring->rx_buffer_len,
bf36c1a0 4887 PCI_DMA_FROMDEVICE);
91615f76 4888 buffer_info->dma = 0;
4c844851 4889 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 4890 skb_put(skb, length);
4891 goto send_up;
4892 }
4c844851 4893 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 4894 }
4895
4896 if (length) {
9d5c8243 4897 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4898 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4899 buffer_info->page_dma = 0;
bf36c1a0
AD		 4900
4901 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4902 buffer_info->page,
4903 buffer_info->page_offset,
4904 length);
4905
6ec43fe6 4906 if (page_count(buffer_info->page) != 1)
bf36c1a0
AD		 4907 buffer_info->page = NULL;
4908 else
4909 get_page(buffer_info->page);
9d5c8243
AK		 4910
4911 skb->len += length;
4912 skb->data_len += length;
9d5c8243 4913
bf36c1a0 4914 skb->truesize += length;
9d5c8243 4915 }
9d5c8243 4916
bf36c1a0 4917 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4918 buffer_info->skb = next_buffer->skb;
4919 buffer_info->dma = next_buffer->dma;
4920 next_buffer->skb = skb;
4921 next_buffer->dma = 0;
bf36c1a0
AD		 4922 goto next_desc;
4923 }
69d3ca53 4924send_up:
33af6bcc
PO		 4925 /*
4926 * If this bit is set, then the RX registers contain
4927 * the time stamp. No other packet will be time
4928 * stamped until we read these registers, so read the
4929 * registers to make them available again. Because
4930 * only one packet can be time stamped at a time, we
4931 * know that the register values must belong to this
4932 * one here and therefore we don't need to compare
4933 * any of the additional attributes stored for it.
4934 *
4935 * If nothing went wrong, then it should have a
4936 * skb_shared_tx that we can turn into a
4937 * skb_shared_hwtstamps.
4938 *
4939 * TODO: can time stamping be triggered (thus locking
4940 * the registers) without the packet reaching this point
4941 * here? In that case RX time stamping would get stuck.
4942 *
4943 * TODO: in "time stamp all packets" mode this bit is
4944 * not set. Need a global flag for this mode and then
4945 * always read the registers. Cannot be done without
4946 * a race condition.
4947 */
4948 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4949 u64 regval;
4950 u64 ns;
4951 struct skb_shared_hwtstamps *shhwtstamps =
4952 skb_hwtstamps(skb);
4953
4954 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4955 "igb: no RX time stamp available for time stamped packet");
4956 regval = rd32(E1000_RXSTMPL);
4957 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4958 ns = timecounter_cyc2time(&adapter->clock, regval);
4959 timecompare_update(&adapter->compare, ns);
4960 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4961 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4962 shhwtstamps->syststamp =
4963 timecompare_transform(&adapter->compare, ns);
4964 }
4965
9d5c8243
AK		 4966 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4967 dev_kfree_skb_irq(skb);
4968 goto next_desc;
4969 }
9d5c8243
AK		 4970
4971 total_bytes += skb->len;
4972 total_packets++;
4973
85ad76b2 4974 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 4975
4976 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 4977 skb_record_rx_queue(skb, rx_ring->queue_index);
4978
4979 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
4980 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 4981
047e0030 4982 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 4983
9d5c8243
AK		 4984next_desc:
4985 rx_desc->wb.upper.status_error = 0;
4986
4987 /* return some buffers to hardware, one at a time is too slow */
4988 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4989 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4990 cleaned_count = 0;
4991 }
4992
4993 /* use prefetched values */
4994 rx_desc = next_rxd;
4995 buffer_info = next_buffer;
9d5c8243
AK		 4996 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4997 }
bf36c1a0 4998
9d5c8243 4999 rx_ring->next_to_clean = i;
c493ea45 5000 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5001
5002 if (cleaned_count)
3b644cf6 5003 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5004
5005 rx_ring->total_packets += total_packets;
5006 rx_ring->total_bytes += total_bytes;
5007 rx_ring->rx_stats.packets += total_packets;
5008 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5009 netdev->stats.rx_bytes += total_bytes;
5010 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5011 return cleaned;
5012}
5013
9d5c8243
AK		 5014/**
5015 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5016 * @adapter: address of board private structure
5017 **/
3b644cf6 5018static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 5019 int cleaned_count)
5020{
e694e964 5021 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5022 union e1000_adv_rx_desc *rx_desc;
5023 struct igb_buffer *buffer_info;
5024 struct sk_buff *skb;
5025 unsigned int i;
db761762 5026 int bufsz;
9d5c8243
AK		 5027
5028 i = rx_ring->next_to_use;
5029 buffer_info = &rx_ring->buffer_info[i];
5030
4c844851 5031 bufsz = rx_ring->rx_buffer_len;
db761762 5032
9d5c8243
AK		 5033 while (cleaned_count--) {
5034 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5035
6ec43fe6 5036 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5037 if (!buffer_info->page) {
bf36c1a0
AD		 5038 buffer_info->page = alloc_page(GFP_ATOMIC);
5039 if (!buffer_info->page) {
04a5fcaa 5040 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5041 goto no_buffers;
5042 }
5043 buffer_info->page_offset = 0;
5044 } else {
5045 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5046 }
5047 buffer_info->page_dma =
80785298 5048 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5049 buffer_info->page_offset,
5050 PAGE_SIZE / 2,
9d5c8243
AK		 5051 PCI_DMA_FROMDEVICE);
5052 }
5053
5054 if (!buffer_info->skb) {
89d71a66 5055 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5056 if (!skb) {
04a5fcaa 5057 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5058 goto no_buffers;
5059 }
5060
9d5c8243 5061 buffer_info->skb = skb;
80785298
AD		 5062 buffer_info->dma = pci_map_single(rx_ring->pdev,
5063 skb->data,
9d5c8243
AK		 5064 bufsz,
5065 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5066 }
5067 /* Refresh the desc even if buffer_addrs didn't change because
5068 * each write-back erases this info. */
6ec43fe6 5069 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5070 rx_desc->read.pkt_addr =
5071 cpu_to_le64(buffer_info->page_dma);
5072 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5073 } else {
5074 rx_desc->read.pkt_addr =
5075 cpu_to_le64(buffer_info->dma);
5076 rx_desc->read.hdr_addr = 0;
5077 }
5078
5079 i++;
5080 if (i == rx_ring->count)
5081 i = 0;
5082 buffer_info = &rx_ring->buffer_info[i];
5083 }
5084
5085no_buffers:
5086 if (rx_ring->next_to_use != i) {
5087 rx_ring->next_to_use = i;
5088 if (i == 0)
5089 i = (rx_ring->count - 1);
5090 else
5091 i--;
5092
5093 /* Force memory writes to complete before letting h/w
5094 * know there are new descriptors to fetch. (Only
5095 * applicable for weak-ordered memory model archs,
5096 * such as IA-64). */
5097 wmb();
fce99e34 5098 writel(i, rx_ring->tail);
9d5c8243
AK		 5099 }
5100}
5101
5102/**
5103 * igb_mii_ioctl -
5104 * @netdev:
5105 * @ifreq:
5106 * @cmd:
5107 **/
5108static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5109{
5110 struct igb_adapter *adapter = netdev_priv(netdev);
5111 struct mii_ioctl_data *data = if_mii(ifr);
5112
5113 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5114 return -EOPNOTSUPP;
5115
5116 switch (cmd) {
5117 case SIOCGMIIPHY:
5118 data->phy_id = adapter->hw.phy.addr;
5119 break;
5120 case SIOCGMIIREG:
f5f4cf08
AD		 5121 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5122 &data->val_out))
9d5c8243
AK		 5123 return -EIO;
5124 break;
5125 case SIOCSMIIREG:
5126 default:
5127 return -EOPNOTSUPP;
5128 }
5129 return 0;
5130}
5131
c6cb090b
PO		 5132/**
5133 * igb_hwtstamp_ioctl - control hardware time stamping
5134 * @netdev:
5135 * @ifreq:
5136 * @cmd:
5137 *
33af6bcc
PO		 5138 * Outgoing time stamping can be enabled and disabled. Play nice and
5139 * disable it when requested, although it shouldn't case any overhead
5140 * when no packet needs it. At most one packet in the queue may be
5141 * marked for time stamping, otherwise it would be impossible to tell
5142 * for sure to which packet the hardware time stamp belongs.
5143 *
5144 * Incoming time stamping has to be configured via the hardware
5145 * filters. Not all combinations are supported, in particular event
5146 * type has to be specified. Matching the kind of event packet is
5147 * not supported, with the exception of "all V2 events regardless of
5148 * level 2 or 4".
5149 *
c6cb090b
PO		 5150 **/
5151static int igb_hwtstamp_ioctl(struct net_device *netdev,
5152 struct ifreq *ifr, int cmd)
5153{
33af6bcc
PO		 5154 struct igb_adapter *adapter = netdev_priv(netdev);
5155 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5156 struct hwtstamp_config config;
33af6bcc
PO		 5157 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5158 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5159 u32 tsync_rx_ctl_type = 0;
5160 u32 tsync_rx_cfg = 0;
5161 int is_l4 = 0;
5162 int is_l2 = 0;
5163 short port = 319; /* PTP */
5164 u32 regval;
c6cb090b
PO		 5165
5166 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5167 return -EFAULT;
5168
5169 /* reserved for future extensions */
5170 if (config.flags)
5171 return -EINVAL;
5172
33af6bcc
PO		 5173 switch (config.tx_type) {
5174 case HWTSTAMP_TX_OFF:
5175 tsync_tx_ctl_bit = 0;
5176 break;
5177 case HWTSTAMP_TX_ON:
5178 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5179 break;
5180 default:
5181 return -ERANGE;
5182 }
5183
5184 switch (config.rx_filter) {
5185 case HWTSTAMP_FILTER_NONE:
5186 tsync_rx_ctl_bit = 0;
5187 break;
5188 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5189 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5190 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5191 case HWTSTAMP_FILTER_ALL:
5192 /*
5193 * register TSYNCRXCFG must be set, therefore it is not
5194 * possible to time stamp both Sync and Delay_Req messages
5195 * => fall back to time stamping all packets
5196 */
5197 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5198 config.rx_filter = HWTSTAMP_FILTER_ALL;
5199 break;
5200 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5201 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5202 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5203 is_l4 = 1;
5204 break;
5205 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5206 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5207 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5208 is_l4 = 1;
5209 break;
5210 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5211 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5212 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5213 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5214 is_l2 = 1;
5215 is_l4 = 1;
5216 config.rx_filter = HWTSTAMP_FILTER_SOME;
5217 break;
5218 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5219 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5220 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5221 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5222 is_l2 = 1;
5223 is_l4 = 1;
5224 config.rx_filter = HWTSTAMP_FILTER_SOME;
5225 break;
5226 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5227 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5228 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5229 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5230 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5231 is_l2 = 1;
5232 break;
5233 default:
5234 return -ERANGE;
5235 }
5236
5237 /* enable/disable TX */
5238 regval = rd32(E1000_TSYNCTXCTL);
5239 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5240 wr32(E1000_TSYNCTXCTL, regval);
5241
5242 /* enable/disable RX, define which PTP packets are time stamped */
5243 regval = rd32(E1000_TSYNCRXCTL);
5244 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5245 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5246 wr32(E1000_TSYNCRXCTL, regval);
5247 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5248
5249 /*
5250 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5251 * (Ethertype to filter on)
5252 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5253 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5254 */
5255 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5256
5257 /* L4 Queue Filter[0]: only filter by source and destination port */
5258 wr32(E1000_SPQF0, htons(port));
5259 wr32(E1000_IMIREXT(0), is_l4 ?
5260 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5261 wr32(E1000_IMIR(0), is_l4 ?
5262 (htons(port)
5263 | (0<<16) /* immediate interrupt disabled */
5264 | 0 /* (1<<17) bit cleared: do not bypass
5265 destination port check */)
5266 : 0);
5267 wr32(E1000_FTQF0, is_l4 ?
5268 (0x11 /* UDP */
5269 | (1<<15) /* VF not compared */
5270 | (1<<27) /* Enable Timestamping */
5271 | (7<<28) /* only source port filter enabled,
5272 source/target address and protocol
5273 masked */)
5274 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5275 enabled */));
5276
5277 wrfl();
5278
5279 adapter->hwtstamp_config = config;
5280
5281 /* clear TX/RX time stamp registers, just to be sure */
5282 regval = rd32(E1000_TXSTMPH);
5283 regval = rd32(E1000_RXSTMPH);
c6cb090b 5284
33af6bcc
PO		 5285 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5286 -EFAULT : 0;
c6cb090b
PO		 5287}
5288
9d5c8243
AK		 5289/**
5290 * igb_ioctl -
5291 * @netdev:
5292 * @ifreq:
5293 * @cmd:
5294 **/
5295static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5296{
5297 switch (cmd) {
5298 case SIOCGMIIPHY:
5299 case SIOCGMIIREG:
5300 case SIOCSMIIREG:
5301 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5302 case SIOCSHWTSTAMP:
5303 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5304 default:
5305 return -EOPNOTSUPP;
5306 }
5307}
5308
009bc06e
AD		 5309s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5310{
5311 struct igb_adapter *adapter = hw->back;
5312 u16 cap_offset;
5313
5314 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5315 if (!cap_offset)
5316 return -E1000_ERR_CONFIG;
5317
5318 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5319
5320 return 0;
5321}
5322
5323s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5324{
5325 struct igb_adapter *adapter = hw->back;
5326 u16 cap_offset;
5327
5328 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5329 if (!cap_offset)
5330 return -E1000_ERR_CONFIG;
5331
5332 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5333
5334 return 0;
5335}
5336
9d5c8243
AK		 5337static void igb_vlan_rx_register(struct net_device *netdev,
5338 struct vlan_group *grp)
5339{
5340 struct igb_adapter *adapter = netdev_priv(netdev);
5341 struct e1000_hw *hw = &adapter->hw;
5342 u32 ctrl, rctl;
5343
5344 igb_irq_disable(adapter);
5345 adapter->vlgrp = grp;
5346
5347 if (grp) {
5348 /* enable VLAN tag insert/strip */
5349 ctrl = rd32(E1000_CTRL);
5350 ctrl |= E1000_CTRL_VME;
5351 wr32(E1000_CTRL, ctrl);
5352
5353 /* enable VLAN receive filtering */
5354 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5355 rctl &= ~E1000_RCTL_CFIEN;
5356 wr32(E1000_RCTL, rctl);
5357 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5358 } else {
5359 /* disable VLAN tag insert/strip */
5360 ctrl = rd32(E1000_CTRL);
5361 ctrl &= ~E1000_CTRL_VME;
5362 wr32(E1000_CTRL, ctrl);
5363
9d5c8243
AK		 5364 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5365 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5366 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5367 }
9d5c8243
AK		 5368 }
5369
e1739522
AD		 5370 igb_rlpml_set(adapter);
5371
9d5c8243
AK		 5372 if (!test_bit(__IGB_DOWN, &adapter->state))
5373 igb_irq_enable(adapter);
5374}
5375
5376static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5377{
5378 struct igb_adapter *adapter = netdev_priv(netdev);
5379 struct e1000_hw *hw = &adapter->hw;
4ae196df 5380 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5381
28b0759c 5382 if ((hw->mng_cookie.status &
9d5c8243
AK		 5383 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5384 (vid == adapter->mng_vlan_id))
5385 return;
4ae196df
AD		 5386
5387 /* add vid to vlvf if sr-iov is enabled,
5388 * if that fails add directly to filter table */
5389 if (igb_vlvf_set(adapter, vid, true, pf_id))
5390 igb_vfta_set(hw, vid, true);
5391
9d5c8243
AK		 5392}
5393
5394static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5395{
5396 struct igb_adapter *adapter = netdev_priv(netdev);
5397 struct e1000_hw *hw = &adapter->hw;
4ae196df 5398 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5399
5400 igb_irq_disable(adapter);
5401 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5402
5403 if (!test_bit(__IGB_DOWN, &adapter->state))
5404 igb_irq_enable(adapter);
5405
5406 if ((adapter->hw.mng_cookie.status &
5407 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5408 (vid == adapter->mng_vlan_id)) {
5409 /* release control to f/w */
5410 igb_release_hw_control(adapter);
5411 return;
5412 }
5413
4ae196df
AD		 5414 /* remove vid from vlvf if sr-iov is enabled,
5415 * if not in vlvf remove from vfta */
5416 if (igb_vlvf_set(adapter, vid, false, pf_id))
5417 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5418}
5419
5420static void igb_restore_vlan(struct igb_adapter *adapter)
5421{
5422 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5423
5424 if (adapter->vlgrp) {
5425 u16 vid;
5426 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5427 if (!vlan_group_get_device(adapter->vlgrp, vid))
5428 continue;
5429 igb_vlan_rx_add_vid(adapter->netdev, vid);
5430 }
5431 }
5432}
5433
5434int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5435{
5436 struct e1000_mac_info *mac = &adapter->hw.mac;
5437
5438 mac->autoneg = 0;
5439
9d5c8243
AK		 5440 switch (spddplx) {
5441 case SPEED_10 + DUPLEX_HALF:
5442 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5443 break;
5444 case SPEED_10 + DUPLEX_FULL:
5445 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5446 break;
5447 case SPEED_100 + DUPLEX_HALF:
5448 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5449 break;
5450 case SPEED_100 + DUPLEX_FULL:
5451 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5452 break;
5453 case SPEED_1000 + DUPLEX_FULL:
5454 mac->autoneg = 1;
5455 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5456 break;
5457 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5458 default:
5459 dev_err(&adapter->pdev->dev,
5460 "Unsupported Speed/Duplex configuration\n");
5461 return -EINVAL;
5462 }
5463 return 0;
5464}
5465
3fe7c4c9 5466static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5467{
5468 struct net_device *netdev = pci_get_drvdata(pdev);
5469 struct igb_adapter *adapter = netdev_priv(netdev);
5470 struct e1000_hw *hw = &adapter->hw;
2d064c06 5471 u32 ctrl, rctl, status;
9d5c8243
AK		 5472 u32 wufc = adapter->wol;
5473#ifdef CONFIG_PM
5474 int retval = 0;
5475#endif
5476
5477 netif_device_detach(netdev);
5478
a88f10ec
AD		 5479 if (netif_running(netdev))
5480 igb_close(netdev);
5481
047e0030 5482 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5483
5484#ifdef CONFIG_PM
5485 retval = pci_save_state(pdev);
5486 if (retval)
5487 return retval;
5488#endif
5489
5490 status = rd32(E1000_STATUS);
5491 if (status & E1000_STATUS_LU)
5492 wufc &= ~E1000_WUFC_LNKC;
5493
5494 if (wufc) {
5495 igb_setup_rctl(adapter);
ff41f8dc 5496 igb_set_rx_mode(netdev);
9d5c8243
AK		 5497
5498 /* turn on all-multi mode if wake on multicast is enabled */
5499 if (wufc & E1000_WUFC_MC) {
5500 rctl = rd32(E1000_RCTL);
5501 rctl |= E1000_RCTL_MPE;
5502 wr32(E1000_RCTL, rctl);
5503 }
5504
5505 ctrl = rd32(E1000_CTRL);
5506 /* advertise wake from D3Cold */
5507 #define E1000_CTRL_ADVD3WUC 0x00100000
5508 /* phy power management enable */
5509 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5510 ctrl |= E1000_CTRL_ADVD3WUC;
5511 wr32(E1000_CTRL, ctrl);
5512
9d5c8243
AK		 5513 /* Allow time for pending master requests to run */
5514 igb_disable_pcie_master(&adapter->hw);
5515
5516 wr32(E1000_WUC, E1000_WUC_PME_EN);
5517 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5518 } else {
5519 wr32(E1000_WUC, 0);
5520 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5521 }
5522
3fe7c4c9
RW		 5523 *enable_wake = wufc || adapter->en_mng_pt;
5524 if (!*enable_wake)
2fb02a26 5525 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5526
5527 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5528 * would have already happened in close and is redundant. */
5529 igb_release_hw_control(adapter);
5530
5531 pci_disable_device(pdev);
5532
9d5c8243
AK		 5533 return 0;
5534}
5535
5536#ifdef CONFIG_PM
3fe7c4c9
RW		 5537static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5538{
5539 int retval;
5540 bool wake;
5541
5542 retval = __igb_shutdown(pdev, &wake);
5543 if (retval)
5544 return retval;
5545
5546 if (wake) {
5547 pci_prepare_to_sleep(pdev);
5548 } else {
5549 pci_wake_from_d3(pdev, false);
5550 pci_set_power_state(pdev, PCI_D3hot);
5551 }
5552
5553 return 0;
5554}
5555
9d5c8243
AK		 5556static int igb_resume(struct pci_dev *pdev)
5557{
5558 struct net_device *netdev = pci_get_drvdata(pdev);
5559 struct igb_adapter *adapter = netdev_priv(netdev);
5560 struct e1000_hw *hw = &adapter->hw;
5561 u32 err;
5562
5563 pci_set_power_state(pdev, PCI_D0);
5564 pci_restore_state(pdev);
42bfd33a 5565
aed5dec3 5566 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5567 if (err) {
5568 dev_err(&pdev->dev,
5569 "igb: Cannot enable PCI device from suspend\n");
5570 return err;
5571 }
5572 pci_set_master(pdev);
5573
5574 pci_enable_wake(pdev, PCI_D3hot, 0);
5575 pci_enable_wake(pdev, PCI_D3cold, 0);
5576
047e0030 5577 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5578 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5579 return -ENOMEM;
9d5c8243
AK		 5580 }
5581
5582 /* e1000_power_up_phy(adapter); */
5583
5584 igb_reset(adapter);
a8564f03
AD		 5585
5586 /* let the f/w know that the h/w is now under the control of the
5587 * driver. */
5588 igb_get_hw_control(adapter);
5589
9d5c8243
AK		 5590 wr32(E1000_WUS, ~0);
5591
a88f10ec
AD		 5592 if (netif_running(netdev)) {
5593 err = igb_open(netdev);
5594 if (err)
5595 return err;
5596 }
9d5c8243
AK		 5597
5598 netif_device_attach(netdev);
5599
9d5c8243
AK		 5600 return 0;
5601}
5602#endif
5603
5604static void igb_shutdown(struct pci_dev *pdev)
5605{
3fe7c4c9
RW		 5606 bool wake;
5607
5608 __igb_shutdown(pdev, &wake);
5609
5610 if (system_state == SYSTEM_POWER_OFF) {
5611 pci_wake_from_d3(pdev, wake);
5612 pci_set_power_state(pdev, PCI_D3hot);
5613 }
9d5c8243
AK		 5614}
5615
5616#ifdef CONFIG_NET_POLL_CONTROLLER
5617/*
5618 * Polling 'interrupt' - used by things like netconsole to send skbs
5619 * without having to re-enable interrupts. It's not called while
5620 * the interrupt routine is executing.
5621 */
5622static void igb_netpoll(struct net_device *netdev)
5623{
5624 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5625 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5626 int i;
9d5c8243 5627
eebbbdba 5628 if (!adapter->msix_entries) {
047e0030 5629 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5630 igb_irq_disable(adapter);
047e0030 5631 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5632 return;
5633 }
9d5c8243 5634
047e0030
AD		 5635 for (i = 0; i < adapter->num_q_vectors; i++) {
5636 struct igb_q_vector *q_vector = adapter->q_vector[i];
5637 wr32(E1000_EIMC, q_vector->eims_value);
5638 napi_schedule(&q_vector->napi);
eebbbdba 5639 }
9d5c8243
AK		 5640}
5641#endif /* CONFIG_NET_POLL_CONTROLLER */
5642
5643/**
5644 * igb_io_error_detected - called when PCI error is detected
5645 * @pdev: Pointer to PCI device
5646 * @state: The current pci connection state
5647 *
5648 * This function is called after a PCI bus error affecting
5649 * this device has been detected.
5650 */
5651static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5652 pci_channel_state_t state)
5653{
5654 struct net_device *netdev = pci_get_drvdata(pdev);
5655 struct igb_adapter *adapter = netdev_priv(netdev);
5656
5657 netif_device_detach(netdev);
5658
59ed6eec
AD		 5659 if (state == pci_channel_io_perm_failure)
5660 return PCI_ERS_RESULT_DISCONNECT;
5661
9d5c8243
AK		 5662 if (netif_running(netdev))
5663 igb_down(adapter);
5664 pci_disable_device(pdev);
5665
5666 /* Request a slot slot reset. */
5667 return PCI_ERS_RESULT_NEED_RESET;
5668}
5669
5670/**
5671 * igb_io_slot_reset - called after the pci bus has been reset.
5672 * @pdev: Pointer to PCI device
5673 *
5674 * Restart the card from scratch, as if from a cold-boot. Implementation
5675 * resembles the first-half of the igb_resume routine.
5676 */
5677static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5678{
5679 struct net_device *netdev = pci_get_drvdata(pdev);
5680 struct igb_adapter *adapter = netdev_priv(netdev);
5681 struct e1000_hw *hw = &adapter->hw;
40a914fa 5682 pci_ers_result_t result;
42bfd33a 5683 int err;
9d5c8243 5684
aed5dec3 5685 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5686 dev_err(&pdev->dev,
5687 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5688 result = PCI_ERS_RESULT_DISCONNECT;
5689 } else {
5690 pci_set_master(pdev);
5691 pci_restore_state(pdev);
9d5c8243 5692
40a914fa
AD		 5693 pci_enable_wake(pdev, PCI_D3hot, 0);
5694 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5695
40a914fa
AD		 5696 igb_reset(adapter);
5697 wr32(E1000_WUS, ~0);
5698 result = PCI_ERS_RESULT_RECOVERED;
5699 }
9d5c8243 5700
ea943d41
JK		 5701 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5702 if (err) {
5703 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5704 "failed 0x%0x\n", err);
5705 /* non-fatal, continue */
5706 }
40a914fa
AD		 5707
5708 return result;
9d5c8243
AK		 5709}
5710
5711/**
5712 * igb_io_resume - called when traffic can start flowing again.
5713 * @pdev: Pointer to PCI device
5714 *
5715 * This callback is called when the error recovery driver tells us that
5716 * its OK to resume normal operation. Implementation resembles the
5717 * second-half of the igb_resume routine.
5718 */
5719static void igb_io_resume(struct pci_dev *pdev)
5720{
5721 struct net_device *netdev = pci_get_drvdata(pdev);
5722 struct igb_adapter *adapter = netdev_priv(netdev);
5723
9d5c8243
AK		 5724 if (netif_running(netdev)) {
5725 if (igb_up(adapter)) {
5726 dev_err(&pdev->dev, "igb_up failed after reset\n");
5727 return;
5728 }
5729 }
5730
5731 netif_device_attach(netdev);
5732
5733 /* let the f/w know that the h/w is now under the control of the
5734 * driver. */
5735 igb_get_hw_control(adapter);
9d5c8243
AK		 5736}
5737
26ad9178
AD		 5738static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5739 u8 qsel)
5740{
5741 u32 rar_low, rar_high;
5742 struct e1000_hw *hw = &adapter->hw;
5743
5744 /* HW expects these in little endian so we reverse the byte order
5745 * from network order (big endian) to little endian
5746 */
5747 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5748 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5749 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5750
5751 /* Indicate to hardware the Address is Valid. */
5752 rar_high |= E1000_RAH_AV;
5753
5754 if (hw->mac.type == e1000_82575)
5755 rar_high |= E1000_RAH_POOL_1 * qsel;
5756 else
5757 rar_high |= E1000_RAH_POOL_1 << qsel;
5758
5759 wr32(E1000_RAL(index), rar_low);
5760 wrfl();
5761 wr32(E1000_RAH(index), rar_high);
5762 wrfl();
5763}
5764
4ae196df
AD		 5765static int igb_set_vf_mac(struct igb_adapter *adapter,
5766 int vf, unsigned char *mac_addr)
5767{
5768 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5769 /* VF MAC addresses start at end of receive addresses and moves
5770 * torwards the first, as a result a collision should not be possible */
5771 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5772
37680117 5773 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5774
26ad9178 5775 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5776
5777 return 0;
5778}
5779
5780static void igb_vmm_control(struct igb_adapter *adapter)
5781{
5782 struct e1000_hw *hw = &adapter->hw;
5783 u32 reg_data;
5784
5785 if (!adapter->vfs_allocated_count)
5786 return;
5787
5788 /* VF's need PF reset indication before they
5789 * can send/receive mail */
5790 reg_data = rd32(E1000_CTRL_EXT);
5791 reg_data |= E1000_CTRL_EXT_PFRSTD;
5792 wr32(E1000_CTRL_EXT, reg_data);
5793
5794 igb_vmdq_set_loopback_pf(hw, true);
5795 igb_vmdq_set_replication_pf(hw, true);
5796}
5797
9d5c8243 5798/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)