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igb: add pf side of VMDq support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
71 {0, }
72};
73
74MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
75
76void igb_reset(struct igb_adapter *);
77static int igb_setup_all_tx_resources(struct igb_adapter *);
78static int igb_setup_all_rx_resources(struct igb_adapter *);
79static void igb_free_all_tx_resources(struct igb_adapter *);
80static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
e1739522
AD		 125static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
126static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
127static inline void igb_set_vmolr(struct e1000_hw *, int);
128static inline void igb_set_vf_rlpml(struct igb_adapter *, int, int);
9d5c8243
AK		 129
130static int igb_suspend(struct pci_dev *, pm_message_t);
131#ifdef CONFIG_PM
132static int igb_resume(struct pci_dev *);
133#endif
134static void igb_shutdown(struct pci_dev *);
421e02f0 135#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 136static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
137static struct notifier_block dca_notifier = {
138 .notifier_call = igb_notify_dca,
139 .next = NULL,
140 .priority = 0
141};
142#endif
9d5c8243
AK		 143
144#ifdef CONFIG_NET_POLL_CONTROLLER
145/* for netdump / net console */
146static void igb_netpoll(struct net_device *);
147#endif
148
149static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
150 pci_channel_state_t);
151static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
152static void igb_io_resume(struct pci_dev *);
153
154static struct pci_error_handlers igb_err_handler = {
155 .error_detected = igb_io_error_detected,
156 .slot_reset = igb_io_slot_reset,
157 .resume = igb_io_resume,
158};
159
160
161static struct pci_driver igb_driver = {
162 .name = igb_driver_name,
163 .id_table = igb_pci_tbl,
164 .probe = igb_probe,
165 .remove = __devexit_p(igb_remove),
166#ifdef CONFIG_PM
167 /* Power Managment Hooks */
168 .suspend = igb_suspend,
169 .resume = igb_resume,
170#endif
171 .shutdown = igb_shutdown,
172 .err_handler = &igb_err_handler
173};
174
7dfc16fa
AD		 175static int global_quad_port_a; /* global quad port a indication */
176
9d5c8243
AK		 177MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
178MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
179MODULE_LICENSE("GPL");
180MODULE_VERSION(DRV_VERSION);
181
38c845c7
PO		 182/**
183 * Scale the NIC clock cycle by a large factor so that
184 * relatively small clock corrections can be added or
185 * substracted at each clock tick. The drawbacks of a
186 * large factor are a) that the clock register overflows
187 * more quickly (not such a big deal) and b) that the
188 * increment per tick has to fit into 24 bits.
189 *
190 * Note that
191 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
192 * IGB_TSYNC_SCALE
193 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
194 *
195 * The base scale factor is intentionally a power of two
196 * so that the division in %struct timecounter can be done with
197 * a shift.
198 */
199#define IGB_TSYNC_SHIFT (19)
200#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
201
202/**
203 * The duration of one clock cycle of the NIC.
204 *
205 * @todo This hard-coded value is part of the specification and might change
206 * in future hardware revisions. Add revision check.
207 */
208#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
209
210#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
211# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
212#endif
213
214/**
215 * igb_read_clock - read raw cycle counter (to be used by time counter)
216 */
217static cycle_t igb_read_clock(const struct cyclecounter *tc)
218{
219 struct igb_adapter *adapter =
220 container_of(tc, struct igb_adapter, cycles);
221 struct e1000_hw *hw = &adapter->hw;
222 u64 stamp;
223
224 stamp = rd32(E1000_SYSTIML);
225 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
226
227 return stamp;
228}
229
9d5c8243
AK		 230#ifdef DEBUG
231/**
232 * igb_get_hw_dev_name - return device name string
233 * used by hardware layer to print debugging information
234 **/
235char *igb_get_hw_dev_name(struct e1000_hw *hw)
236{
237 struct igb_adapter *adapter = hw->back;
238 return adapter->netdev->name;
239}
38c845c7
PO		 240
241/**
242 * igb_get_time_str - format current NIC and system time as string
243 */
244static char *igb_get_time_str(struct igb_adapter *adapter,
245 char buffer[160])
246{
247 cycle_t hw = adapter->cycles.read(&adapter->cycles);
248 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
249 struct timespec sys;
250 struct timespec delta;
251 getnstimeofday(&sys);
252
253 delta = timespec_sub(nic, sys);
254
255 sprintf(buffer,
33af6bcc
PO		 256 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
257 hw,
38c845c7
PO		 258 (long)nic.tv_sec, nic.tv_nsec,
259 (long)sys.tv_sec, sys.tv_nsec,
260 (long)delta.tv_sec, delta.tv_nsec);
261
262 return buffer;
263}
9d5c8243
AK		 264#endif
265
266/**
267 * igb_init_module - Driver Registration Routine
268 *
269 * igb_init_module is the first routine called when the driver is
270 * loaded. All it does is register with the PCI subsystem.
271 **/
272static int __init igb_init_module(void)
273{
274 int ret;
275 printk(KERN_INFO "%s - version %s\n",
276 igb_driver_string, igb_driver_version);
277
278 printk(KERN_INFO "%s\n", igb_copyright);
279
7dfc16fa
AD		 280 global_quad_port_a = 0;
281
421e02f0 282#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 283 dca_register_notify(&dca_notifier);
284#endif
bbd98fe4
AD		 285
286 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 287 return ret;
288}
289
290module_init(igb_init_module);
291
292/**
293 * igb_exit_module - Driver Exit Cleanup Routine
294 *
295 * igb_exit_module is called just before the driver is removed
296 * from memory.
297 **/
298static void __exit igb_exit_module(void)
299{
421e02f0 300#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 301 dca_unregister_notify(&dca_notifier);
302#endif
9d5c8243
AK		 303 pci_unregister_driver(&igb_driver);
304}
305
306module_exit(igb_exit_module);
307
26bc19ec
AD		 308#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
309/**
310 * igb_cache_ring_register - Descriptor ring to register mapping
311 * @adapter: board private structure to initialize
312 *
313 * Once we know the feature-set enabled for the device, we'll cache
314 * the register offset the descriptor ring is assigned to.
315 **/
316static void igb_cache_ring_register(struct igb_adapter *adapter)
317{
318 int i;
1bfaf07b 319 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 320
321 switch (adapter->hw.mac.type) {
322 case e1000_82576:
323 /* The queues are allocated for virtualization such that VF 0
324 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
325 * In order to avoid collision we start at the first free queue
326 * and continue consuming queues in the same sequence
327 */
328 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 329 adapter->rx_ring[i].reg_idx = rbase_offset +
330 Q_IDX_82576(i);
26bc19ec 331 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 332 adapter->tx_ring[i].reg_idx = rbase_offset +
333 Q_IDX_82576(i);
26bc19ec
AD		 334 break;
335 case e1000_82575:
336 default:
337 for (i = 0; i < adapter->num_rx_queues; i++)
338 adapter->rx_ring[i].reg_idx = i;
339 for (i = 0; i < adapter->num_tx_queues; i++)
340 adapter->tx_ring[i].reg_idx = i;
341 break;
342 }
343}
344
9d5c8243
AK		 345/**
346 * igb_alloc_queues - Allocate memory for all rings
347 * @adapter: board private structure to initialize
348 *
349 * We allocate one ring per queue at run-time since we don't know the
350 * number of queues at compile-time.
351 **/
352static int igb_alloc_queues(struct igb_adapter *adapter)
353{
354 int i;
355
356 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
357 sizeof(struct igb_ring), GFP_KERNEL);
358 if (!adapter->tx_ring)
359 return -ENOMEM;
360
361 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
362 sizeof(struct igb_ring), GFP_KERNEL);
363 if (!adapter->rx_ring) {
364 kfree(adapter->tx_ring);
365 return -ENOMEM;
366 }
367
6eb5a7f1
AD		 368 adapter->rx_ring->buddy = adapter->tx_ring;
369
661086df
PWJ		 370 for (i = 0; i < adapter->num_tx_queues; i++) {
371 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 372 ring->count = adapter->tx_ring_count;
661086df
PWJ		 373 ring->adapter = adapter;
374 ring->queue_index = i;
375 }
9d5c8243
AK		 376 for (i = 0; i < adapter->num_rx_queues; i++) {
377 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 378 ring->count = adapter->rx_ring_count;
9d5c8243 379 ring->adapter = adapter;
844290e5 380 ring->queue_index = i;
9d5c8243
AK		 381 ring->itr_register = E1000_ITR;
382
844290e5 383 /* set a default napi handler for each rx_ring */
661086df 384 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 385 }
26bc19ec
AD		 386
387 igb_cache_ring_register(adapter);
9d5c8243
AK		 388 return 0;
389}
390
a88f10ec
AD		 391static void igb_free_queues(struct igb_adapter *adapter)
392{
393 int i;
394
395 for (i = 0; i < adapter->num_rx_queues; i++)
396 netif_napi_del(&adapter->rx_ring[i].napi);
397
398 kfree(adapter->tx_ring);
399 kfree(adapter->rx_ring);
400}
401
9d5c8243
AK		 402#define IGB_N0_QUEUE -1
403static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
404 int tx_queue, int msix_vector)
405{
406 u32 msixbm = 0;
407 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 408 u32 ivar, index;
409
410 switch (hw->mac.type) {
411 case e1000_82575:
9d5c8243
AK		 412 /* The 82575 assigns vectors using a bitmask, which matches the
413 bitmask for the EICR/EIMS/EIMC registers. To assign one
414 or more queues to a vector, we write the appropriate bits
415 into the MSIXBM register for that vector. */
416 if (rx_queue > IGB_N0_QUEUE) {
417 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
418 adapter->rx_ring[rx_queue].eims_value = msixbm;
419 }
420 if (tx_queue > IGB_N0_QUEUE) {
421 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
422 adapter->tx_ring[tx_queue].eims_value =
423 E1000_EICR_TX_QUEUE0 << tx_queue;
424 }
425 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 426 break;
427 case e1000_82576:
26bc19ec 428 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 429 Each queue has a single entry in the table to which we write
430 a vector number along with a "valid" bit. Sadly, the layout
431 of the table is somewhat counterintuitive. */
432 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 433 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 434 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 435 if (rx_queue & 0x1) {
2d064c06
AD		 436 /* vector goes into third byte of register */
437 ivar = ivar & 0xFF00FFFF;
438 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 439 } else {
440 /* vector goes into low byte of register */
441 ivar = ivar & 0xFFFFFF00;
442 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 443 }
444 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
445 array_wr32(E1000_IVAR0, index, ivar);
446 }
447 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 448 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 449 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 450 if (tx_queue & 0x1) {
2d064c06
AD		 451 /* vector goes into high byte of register */
452 ivar = ivar & 0x00FFFFFF;
453 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 454 } else {
455 /* vector goes into second byte of register */
456 ivar = ivar & 0xFFFF00FF;
457 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 458 }
459 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
460 array_wr32(E1000_IVAR0, index, ivar);
461 }
462 break;
463 default:
464 BUG();
465 break;
466 }
9d5c8243
AK		 467}
468
469/**
470 * igb_configure_msix - Configure MSI-X hardware
471 *
472 * igb_configure_msix sets up the hardware to properly
473 * generate MSI-X interrupts.
474 **/
475static void igb_configure_msix(struct igb_adapter *adapter)
476{
477 u32 tmp;
478 int i, vector = 0;
479 struct e1000_hw *hw = &adapter->hw;
480
481 adapter->eims_enable_mask = 0;
2d064c06
AD		 482 if (hw->mac.type == e1000_82576)
483 /* Turn on MSI-X capability first, or our settings
484 * won't stick. And it will take days to debug. */
485 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 486 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 487 E1000_GPIE_NSICR);
9d5c8243
AK		 488
489 for (i = 0; i < adapter->num_tx_queues; i++) {
490 struct igb_ring *tx_ring = &adapter->tx_ring[i];
491 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
492 adapter->eims_enable_mask |= tx_ring->eims_value;
493 if (tx_ring->itr_val)
6eb5a7f1 494 writel(tx_ring->itr_val,
9d5c8243
AK		 495 hw->hw_addr + tx_ring->itr_register);
496 else
497 writel(1, hw->hw_addr + tx_ring->itr_register);
498 }
499
500 for (i = 0; i < adapter->num_rx_queues; i++) {
501 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 502 rx_ring->buddy = NULL;
9d5c8243
AK		 503 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
504 adapter->eims_enable_mask |= rx_ring->eims_value;
505 if (rx_ring->itr_val)
6eb5a7f1 506 writel(rx_ring->itr_val,
9d5c8243
AK		 507 hw->hw_addr + rx_ring->itr_register);
508 else
509 writel(1, hw->hw_addr + rx_ring->itr_register);
510 }
511
512
513 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 514 switch (hw->mac.type) {
515 case e1000_82575:
9d5c8243
AK		 516 array_wr32(E1000_MSIXBM(0), vector++,
517 E1000_EIMS_OTHER);
518
9d5c8243
AK		 519 tmp = rd32(E1000_CTRL_EXT);
520 /* enable MSI-X PBA support*/
521 tmp |= E1000_CTRL_EXT_PBA_CLR;
522
523 /* Auto-Mask interrupts upon ICR read. */
524 tmp |= E1000_CTRL_EXT_EIAME;
525 tmp |= E1000_CTRL_EXT_IRCA;
526
527 wr32(E1000_CTRL_EXT, tmp);
528 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 529 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 530
2d064c06
AD		 531 break;
532
533 case e1000_82576:
534 tmp = (vector++ | E1000_IVAR_VALID) << 8;
535 wr32(E1000_IVAR_MISC, tmp);
536
537 adapter->eims_enable_mask = (1 << (vector)) - 1;
538 adapter->eims_other = 1 << (vector - 1);
539 break;
540 default:
541 /* do nothing, since nothing else supports MSI-X */
542 break;
543 } /* switch (hw->mac.type) */
9d5c8243
AK		 544 wrfl();
545}
546
547/**
548 * igb_request_msix - Initialize MSI-X interrupts
549 *
550 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
551 * kernel.
552 **/
553static int igb_request_msix(struct igb_adapter *adapter)
554{
555 struct net_device *netdev = adapter->netdev;
556 int i, err = 0, vector = 0;
557
558 vector = 0;
559
560 for (i = 0; i < adapter->num_tx_queues; i++) {
561 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 562 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 563 err = request_irq(adapter->msix_entries[vector].vector,
564 &igb_msix_tx, 0, ring->name,
565 &(adapter->tx_ring[i]));
566 if (err)
567 goto out;
568 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 569 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 570 vector++;
571 }
572 for (i = 0; i < adapter->num_rx_queues; i++) {
573 struct igb_ring *ring = &(adapter->rx_ring[i]);
574 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 575 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 576 else
577 memcpy(ring->name, netdev->name, IFNAMSIZ);
578 err = request_irq(adapter->msix_entries[vector].vector,
579 &igb_msix_rx, 0, ring->name,
580 &(adapter->rx_ring[i]));
581 if (err)
582 goto out;
583 ring->itr_register = E1000_EITR(0) + (vector << 2);
584 ring->itr_val = adapter->itr;
844290e5
PW		 585 /* overwrite the poll routine for MSIX, we've already done
586 * netif_napi_add */
587 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 588 vector++;
589 }
590
591 err = request_irq(adapter->msix_entries[vector].vector,
592 &igb_msix_other, 0, netdev->name, netdev);
593 if (err)
594 goto out;
595
9d5c8243
AK		 596 igb_configure_msix(adapter);
597 return 0;
598out:
599 return err;
600}
601
602static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
603{
604 if (adapter->msix_entries) {
605 pci_disable_msix(adapter->pdev);
606 kfree(adapter->msix_entries);
607 adapter->msix_entries = NULL;
7dfc16fa 608 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 609 pci_disable_msi(adapter->pdev);
610 return;
611}
612
613
614/**
615 * igb_set_interrupt_capability - set MSI or MSI-X if supported
616 *
617 * Attempt to configure interrupts using the best available
618 * capabilities of the hardware and kernel.
619 **/
620static void igb_set_interrupt_capability(struct igb_adapter *adapter)
621{
622 int err;
623 int numvecs, i;
624
83b7180d
AD		 625 /* Number of supported queues. */
626 /* Having more queues than CPUs doesn't make sense. */
627 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
628 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
629
9d5c8243
AK		 630 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
631 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
632 GFP_KERNEL);
633 if (!adapter->msix_entries)
634 goto msi_only;
635
636 for (i = 0; i < numvecs; i++)
637 adapter->msix_entries[i].entry = i;
638
639 err = pci_enable_msix(adapter->pdev,
640 adapter->msix_entries,
641 numvecs);
642 if (err == 0)
34a20e89 643 goto out;
9d5c8243
AK		 644
645 igb_reset_interrupt_capability(adapter);
646
647 /* If we can't do MSI-X, try MSI */
648msi_only:
649 adapter->num_rx_queues = 1;
661086df 650 adapter->num_tx_queues = 1;
9d5c8243 651 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 652 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 653out:
661086df 654 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 655 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 656 return;
657}
658
659/**
660 * igb_request_irq - initialize interrupts
661 *
662 * Attempts to configure interrupts using the best available
663 * capabilities of the hardware and kernel.
664 **/
665static int igb_request_irq(struct igb_adapter *adapter)
666{
667 struct net_device *netdev = adapter->netdev;
668 struct e1000_hw *hw = &adapter->hw;
669 int err = 0;
670
671 if (adapter->msix_entries) {
672 err = igb_request_msix(adapter);
844290e5 673 if (!err)
9d5c8243 674 goto request_done;
9d5c8243
AK		 675 /* fall back to MSI */
676 igb_reset_interrupt_capability(adapter);
677 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 678 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 679 igb_free_all_tx_resources(adapter);
680 igb_free_all_rx_resources(adapter);
681 adapter->num_rx_queues = 1;
682 igb_alloc_queues(adapter);
844290e5 683 } else {
2d064c06
AD		 684 switch (hw->mac.type) {
685 case e1000_82575:
686 wr32(E1000_MSIXBM(0),
687 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
688 break;
689 case e1000_82576:
690 wr32(E1000_IVAR0, E1000_IVAR_VALID);
691 break;
692 default:
693 break;
694 }
9d5c8243 695 }
844290e5 696
7dfc16fa 697 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 698 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
699 netdev->name, netdev);
700 if (!err)
701 goto request_done;
702 /* fall back to legacy interrupts */
703 igb_reset_interrupt_capability(adapter);
7dfc16fa 704 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 705 }
706
707 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
708 netdev->name, netdev);
709
6cb5e577 710 if (err)
9d5c8243
AK		 711 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
712 err);
9d5c8243
AK		 713
714request_done:
715 return err;
716}
717
718static void igb_free_irq(struct igb_adapter *adapter)
719{
720 struct net_device *netdev = adapter->netdev;
721
722 if (adapter->msix_entries) {
723 int vector = 0, i;
724
725 for (i = 0; i < adapter->num_tx_queues; i++)
726 free_irq(adapter->msix_entries[vector++].vector,
727 &(adapter->tx_ring[i]));
728 for (i = 0; i < adapter->num_rx_queues; i++)
729 free_irq(adapter->msix_entries[vector++].vector,
730 &(adapter->rx_ring[i]));
731
732 free_irq(adapter->msix_entries[vector++].vector, netdev);
733 return;
734 }
735
736 free_irq(adapter->pdev->irq, netdev);
737}
738
739/**
740 * igb_irq_disable - Mask off interrupt generation on the NIC
741 * @adapter: board private structure
742 **/
743static void igb_irq_disable(struct igb_adapter *adapter)
744{
745 struct e1000_hw *hw = &adapter->hw;
746
747 if (adapter->msix_entries) {
844290e5 748 wr32(E1000_EIAM, 0);
9d5c8243
AK		 749 wr32(E1000_EIMC, ~0);
750 wr32(E1000_EIAC, 0);
751 }
844290e5
PW		 752
753 wr32(E1000_IAM, 0);
9d5c8243
AK		 754 wr32(E1000_IMC, ~0);
755 wrfl();
756 synchronize_irq(adapter->pdev->irq);
757}
758
759/**
760 * igb_irq_enable - Enable default interrupt generation settings
761 * @adapter: board private structure
762 **/
763static void igb_irq_enable(struct igb_adapter *adapter)
764{
765 struct e1000_hw *hw = &adapter->hw;
766
767 if (adapter->msix_entries) {
844290e5
PW		 768 wr32(E1000_EIAC, adapter->eims_enable_mask);
769 wr32(E1000_EIAM, adapter->eims_enable_mask);
770 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 771 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 772 } else {
773 wr32(E1000_IMS, IMS_ENABLE_MASK);
774 wr32(E1000_IAM, IMS_ENABLE_MASK);
775 }
9d5c8243
AK		 776}
777
778static void igb_update_mng_vlan(struct igb_adapter *adapter)
779{
780 struct net_device *netdev = adapter->netdev;
781 u16 vid = adapter->hw.mng_cookie.vlan_id;
782 u16 old_vid = adapter->mng_vlan_id;
783 if (adapter->vlgrp) {
784 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
785 if (adapter->hw.mng_cookie.status &
786 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
787 igb_vlan_rx_add_vid(netdev, vid);
788 adapter->mng_vlan_id = vid;
789 } else
790 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
791
792 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
793 (vid != old_vid) &&
794 !vlan_group_get_device(adapter->vlgrp, old_vid))
795 igb_vlan_rx_kill_vid(netdev, old_vid);
796 } else
797 adapter->mng_vlan_id = vid;
798 }
799}
800
801/**
802 * igb_release_hw_control - release control of the h/w to f/w
803 * @adapter: address of board private structure
804 *
805 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
806 * For ASF and Pass Through versions of f/w this means that the
807 * driver is no longer loaded.
808 *
809 **/
810static void igb_release_hw_control(struct igb_adapter *adapter)
811{
812 struct e1000_hw *hw = &adapter->hw;
813 u32 ctrl_ext;
814
815 /* Let firmware take over control of h/w */
816 ctrl_ext = rd32(E1000_CTRL_EXT);
817 wr32(E1000_CTRL_EXT,
818 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
819}
820
821
822/**
823 * igb_get_hw_control - get control of the h/w from f/w
824 * @adapter: address of board private structure
825 *
826 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
827 * For ASF and Pass Through versions of f/w this means that
828 * the driver is loaded.
829 *
830 **/
831static void igb_get_hw_control(struct igb_adapter *adapter)
832{
833 struct e1000_hw *hw = &adapter->hw;
834 u32 ctrl_ext;
835
836 /* Let firmware know the driver has taken over */
837 ctrl_ext = rd32(E1000_CTRL_EXT);
838 wr32(E1000_CTRL_EXT,
839 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
840}
841
9d5c8243
AK		 842/**
843 * igb_configure - configure the hardware for RX and TX
844 * @adapter: private board structure
845 **/
846static void igb_configure(struct igb_adapter *adapter)
847{
848 struct net_device *netdev = adapter->netdev;
849 int i;
850
851 igb_get_hw_control(adapter);
852 igb_set_multi(netdev);
853
854 igb_restore_vlan(adapter);
9d5c8243
AK		 855
856 igb_configure_tx(adapter);
857 igb_setup_rctl(adapter);
858 igb_configure_rx(adapter);
662d7205
AD		 859
860 igb_rx_fifo_flush_82575(&adapter->hw);
861
9d5c8243
AK		 862 /* call IGB_DESC_UNUSED which always leaves
863 * at least 1 descriptor unused to make sure
864 * next_to_use != next_to_clean */
865 for (i = 0; i < adapter->num_rx_queues; i++) {
866 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 867 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 868 }
869
870
871 adapter->tx_queue_len = netdev->tx_queue_len;
872}
873
874
875/**
876 * igb_up - Open the interface and prepare it to handle traffic
877 * @adapter: board private structure
878 **/
879
880int igb_up(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
883 int i;
884
885 /* hardware has been reset, we need to reload some things */
886 igb_configure(adapter);
887
888 clear_bit(__IGB_DOWN, &adapter->state);
889
844290e5
PW		 890 for (i = 0; i < adapter->num_rx_queues; i++)
891 napi_enable(&adapter->rx_ring[i].napi);
892 if (adapter->msix_entries)
9d5c8243 893 igb_configure_msix(adapter);
9d5c8243 894
e1739522
AD		 895 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
896 igb_set_vmolr(hw, adapter->vfs_allocated_count);
897
9d5c8243
AK		 898 /* Clear any pending interrupts. */
899 rd32(E1000_ICR);
900 igb_irq_enable(adapter);
901
902 /* Fire a link change interrupt to start the watchdog. */
903 wr32(E1000_ICS, E1000_ICS_LSC);
904 return 0;
905}
906
907void igb_down(struct igb_adapter *adapter)
908{
909 struct e1000_hw *hw = &adapter->hw;
910 struct net_device *netdev = adapter->netdev;
911 u32 tctl, rctl;
912 int i;
913
914 /* signal that we're down so the interrupt handler does not
915 * reschedule our watchdog timer */
916 set_bit(__IGB_DOWN, &adapter->state);
917
918 /* disable receives in the hardware */
919 rctl = rd32(E1000_RCTL);
920 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
921 /* flush and sleep below */
922
fd2ea0a7 923 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 924
925 /* disable transmits in the hardware */
926 tctl = rd32(E1000_TCTL);
927 tctl &= ~E1000_TCTL_EN;
928 wr32(E1000_TCTL, tctl);
929 /* flush both disables and wait for them to finish */
930 wrfl();
931 msleep(10);
932
844290e5
PW		 933 for (i = 0; i < adapter->num_rx_queues; i++)
934 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 935
9d5c8243
AK		 936 igb_irq_disable(adapter);
937
938 del_timer_sync(&adapter->watchdog_timer);
939 del_timer_sync(&adapter->phy_info_timer);
940
941 netdev->tx_queue_len = adapter->tx_queue_len;
942 netif_carrier_off(netdev);
04fe6358
AD		 943
944 /* record the stats before reset*/
945 igb_update_stats(adapter);
946
9d5c8243
AK		 947 adapter->link_speed = 0;
948 adapter->link_duplex = 0;
949
3023682e
JK		 950 if (!pci_channel_offline(adapter->pdev))
951 igb_reset(adapter);
9d5c8243
AK		 952 igb_clean_all_tx_rings(adapter);
953 igb_clean_all_rx_rings(adapter);
954}
955
956void igb_reinit_locked(struct igb_adapter *adapter)
957{
958 WARN_ON(in_interrupt());
959 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
960 msleep(1);
961 igb_down(adapter);
962 igb_up(adapter);
963 clear_bit(__IGB_RESETTING, &adapter->state);
964}
965
966void igb_reset(struct igb_adapter *adapter)
967{
968 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 969 struct e1000_mac_info *mac = &hw->mac;
970 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 971 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
972 u16 hwm;
973
974 /* Repartition Pba for greater than 9k mtu
975 * To take effect CTRL.RST is required.
976 */
fa4dfae0
AD		 977 switch (mac->type) {
978 case e1000_82576:
2d064c06 979 pba = E1000_PBA_64K;
fa4dfae0
AD		 980 break;
981 case e1000_82575:
982 default:
983 pba = E1000_PBA_34K;
984 break;
2d064c06 985 }
9d5c8243 986
2d064c06
AD		 987 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
988 (mac->type < e1000_82576)) {
9d5c8243
AK		 989 /* adjust PBA for jumbo frames */
990 wr32(E1000_PBA, pba);
991
992 /* To maintain wire speed transmits, the Tx FIFO should be
993 * large enough to accommodate two full transmit packets,
994 * rounded up to the next 1KB and expressed in KB. Likewise,
995 * the Rx FIFO should be large enough to accommodate at least
996 * one full receive packet and is similarly rounded up and
997 * expressed in KB. */
998 pba = rd32(E1000_PBA);
999 /* upper 16 bits has Tx packet buffer allocation size in KB */
1000 tx_space = pba >> 16;
1001 /* lower 16 bits has Rx packet buffer allocation size in KB */
1002 pba &= 0xffff;
1003 /* the tx fifo also stores 16 bytes of information about the tx
1004 * but don't include ethernet FCS because hardware appends it */
1005 min_tx_space = (adapter->max_frame_size +
85e8d004 1006 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1007 ETH_FCS_LEN) * 2;
1008 min_tx_space = ALIGN(min_tx_space, 1024);
1009 min_tx_space >>= 10;
1010 /* software strips receive CRC, so leave room for it */
1011 min_rx_space = adapter->max_frame_size;
1012 min_rx_space = ALIGN(min_rx_space, 1024);
1013 min_rx_space >>= 10;
1014
1015 /* If current Tx allocation is less than the min Tx FIFO size,
1016 * and the min Tx FIFO size is less than the current Rx FIFO
1017 * allocation, take space away from current Rx allocation */
1018 if (tx_space < min_tx_space &&
1019 ((min_tx_space - tx_space) < pba)) {
1020 pba = pba - (min_tx_space - tx_space);
1021
1022 /* if short on rx space, rx wins and must trump tx
1023 * adjustment */
1024 if (pba < min_rx_space)
1025 pba = min_rx_space;
1026 }
2d064c06 1027 wr32(E1000_PBA, pba);
9d5c8243 1028 }
9d5c8243
AK		 1029
1030 /* flow control settings */
1031 /* The high water mark must be low enough to fit one full frame
1032 * (or the size used for early receive) above it in the Rx FIFO.
1033 * Set it to the lower of:
1034 * - 90% of the Rx FIFO size, or
1035 * - the full Rx FIFO size minus one full frame */
1036 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1037 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1038
2d064c06
AD		 1039 if (mac->type < e1000_82576) {
1040 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1041 fc->low_water = fc->high_water - 8;
1042 } else {
1043 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1044 fc->low_water = fc->high_water - 16;
1045 }
9d5c8243
AK		 1046 fc->pause_time = 0xFFFF;
1047 fc->send_xon = 1;
1048 fc->type = fc->original_type;
1049
1050 /* Allow time for pending master requests to run */
1051 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1052 wr32(E1000_WUC, 0);
1053
1054 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1055 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1056
1057 igb_update_mng_vlan(adapter);
1058
1059 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1060 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1061
1062 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1063 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1064}
1065
2e5c6922
SH		 1066static const struct net_device_ops igb_netdev_ops = {
1067 .ndo_open = igb_open,
1068 .ndo_stop = igb_close,
00829823 1069 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1070 .ndo_get_stats = igb_get_stats,
1071 .ndo_set_multicast_list = igb_set_multi,
1072 .ndo_set_mac_address = igb_set_mac,
1073 .ndo_change_mtu = igb_change_mtu,
1074 .ndo_do_ioctl = igb_ioctl,
1075 .ndo_tx_timeout = igb_tx_timeout,
1076 .ndo_validate_addr = eth_validate_addr,
1077 .ndo_vlan_rx_register = igb_vlan_rx_register,
1078 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1079 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1080#ifdef CONFIG_NET_POLL_CONTROLLER
1081 .ndo_poll_controller = igb_netpoll,
1082#endif
1083};
1084
9d5c8243
AK		 1085/**
1086 * igb_probe - Device Initialization Routine
1087 * @pdev: PCI device information struct
1088 * @ent: entry in igb_pci_tbl
1089 *
1090 * Returns 0 on success, negative on failure
1091 *
1092 * igb_probe initializes an adapter identified by a pci_dev structure.
1093 * The OS initialization, configuring of the adapter private structure,
1094 * and a hardware reset occur.
1095 **/
1096static int __devinit igb_probe(struct pci_dev *pdev,
1097 const struct pci_device_id *ent)
1098{
1099 struct net_device *netdev;
1100 struct igb_adapter *adapter;
1101 struct e1000_hw *hw;
c54106bb 1102 struct pci_dev *us_dev;
9d5c8243
AK		 1103 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1104 unsigned long mmio_start, mmio_len;
450c87c8 1105 int err, pci_using_dac, pos;
c54106bb 1106 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1107 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1108 u32 part_num;
1109
aed5dec3 1110 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1111 if (err)
1112 return err;
1113
1114 pci_using_dac = 0;
1115 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1116 if (!err) {
1117 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1118 if (!err)
1119 pci_using_dac = 1;
1120 } else {
1121 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1122 if (err) {
1123 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1124 if (err) {
1125 dev_err(&pdev->dev, "No usable DMA "
1126 "configuration, aborting\n");
1127 goto err_dma;
1128 }
1129 }
1130 }
1131
c54106bb
AD		 1132 /* 82575 requires that the pci-e link partner disable the L0s state */
1133 switch (pdev->device) {
1134 case E1000_DEV_ID_82575EB_COPPER:
1135 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1136 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1137 us_dev = pdev->bus->self;
1138 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1139 if (pos) {
1140 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1141 &state);
1142 state &= ~PCIE_LINK_STATE_L0S;
1143 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1144 state);
ac450208
BH		 1145 dev_info(&pdev->dev,
1146 "Disabling ASPM L0s upstream switch port %s\n",
1147 pci_name(us_dev));
c54106bb
AD		 1148 }
1149 default:
1150 break;
1151 }
1152
aed5dec3
AD		 1153 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1154 IORESOURCE_MEM),
1155 igb_driver_name);
9d5c8243
AK		 1156 if (err)
1157 goto err_pci_reg;
1158
ea943d41
JK		 1159 err = pci_enable_pcie_error_reporting(pdev);
1160 if (err) {
1161 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1162 "0x%x\n", err);
1163 /* non-fatal, continue */
1164 }
40a914fa 1165
9d5c8243 1166 pci_set_master(pdev);
c682fc23 1167 pci_save_state(pdev);
9d5c8243
AK		 1168
1169 err = -ENOMEM;
1bfaf07b
AD		 1170 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1171 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1172 if (!netdev)
1173 goto err_alloc_etherdev;
1174
1175 SET_NETDEV_DEV(netdev, &pdev->dev);
1176
1177 pci_set_drvdata(pdev, netdev);
1178 adapter = netdev_priv(netdev);
1179 adapter->netdev = netdev;
1180 adapter->pdev = pdev;
1181 hw = &adapter->hw;
1182 hw->back = adapter;
1183 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1184
1185 mmio_start = pci_resource_start(pdev, 0);
1186 mmio_len = pci_resource_len(pdev, 0);
1187
1188 err = -EIO;
28b0759c
AD		 1189 hw->hw_addr = ioremap(mmio_start, mmio_len);
1190 if (!hw->hw_addr)
9d5c8243
AK		 1191 goto err_ioremap;
1192
2e5c6922 1193 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1194 igb_set_ethtool_ops(netdev);
9d5c8243 1195 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1196
1197 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1198
1199 netdev->mem_start = mmio_start;
1200 netdev->mem_end = mmio_start + mmio_len;
1201
9d5c8243
AK		 1202 /* PCI config space info */
1203 hw->vendor_id = pdev->vendor;
1204 hw->device_id = pdev->device;
1205 hw->revision_id = pdev->revision;
1206 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1207 hw->subsystem_device_id = pdev->subsystem_device;
1208
1209 /* setup the private structure */
1210 hw->back = adapter;
1211 /* Copy the default MAC, PHY and NVM function pointers */
1212 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1213 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1214 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1215 /* Initialize skew-specific constants */
1216 err = ei->get_invariants(hw);
1217 if (err)
450c87c8 1218 goto err_sw_init;
9d5c8243 1219
450c87c8 1220 /* setup the private structure */
9d5c8243
AK		 1221 err = igb_sw_init(adapter);
1222 if (err)
1223 goto err_sw_init;
1224
1225 igb_get_bus_info_pcie(hw);
1226
7dfc16fa
AD		 1227 /* set flags */
1228 switch (hw->mac.type) {
7dfc16fa 1229 case e1000_82575:
7dfc16fa
AD		 1230 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1231 break;
bbd98fe4 1232 case e1000_82576:
7dfc16fa
AD		 1233 default:
1234 break;
1235 }
1236
9d5c8243
AK		 1237 hw->phy.autoneg_wait_to_complete = false;
1238 hw->mac.adaptive_ifs = true;
1239
1240 /* Copper options */
1241 if (hw->phy.media_type == e1000_media_type_copper) {
1242 hw->phy.mdix = AUTO_ALL_MODES;
1243 hw->phy.disable_polarity_correction = false;
1244 hw->phy.ms_type = e1000_ms_hw_default;
1245 }
1246
1247 if (igb_check_reset_block(hw))
1248 dev_info(&pdev->dev,
1249 "PHY reset is blocked due to SOL/IDER session.\n");
1250
1251 netdev->features = NETIF_F_SG |
7d8eb29e 1252 NETIF_F_IP_CSUM |
9d5c8243
AK		 1253 NETIF_F_HW_VLAN_TX |
1254 NETIF_F_HW_VLAN_RX |
1255 NETIF_F_HW_VLAN_FILTER;
1256
7d8eb29e 1257 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1258 netdev->features |= NETIF_F_TSO;
9d5c8243 1259 netdev->features |= NETIF_F_TSO6;
48f29ffc 1260
5c0999b7 1261 netdev->features |= NETIF_F_GRO;
d3352520 1262
48f29ffc
JK		 1263 netdev->vlan_features |= NETIF_F_TSO;
1264 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1265 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1266 netdev->vlan_features |= NETIF_F_SG;
1267
9d5c8243
AK		 1268 if (pci_using_dac)
1269 netdev->features |= NETIF_F_HIGHDMA;
1270
9d5c8243
AK		 1271 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1272
1273 /* before reading the NVM, reset the controller to put the device in a
1274 * known good starting state */
1275 hw->mac.ops.reset_hw(hw);
1276
1277 /* make sure the NVM is good */
1278 if (igb_validate_nvm_checksum(hw) < 0) {
1279 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1280 err = -EIO;
1281 goto err_eeprom;
1282 }
1283
1284 /* copy the MAC address out of the NVM */
1285 if (hw->mac.ops.read_mac_addr(hw))
1286 dev_err(&pdev->dev, "NVM Read Error\n");
1287
1288 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1289 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1290
1291 if (!is_valid_ether_addr(netdev->perm_addr)) {
1292 dev_err(&pdev->dev, "Invalid MAC Address\n");
1293 err = -EIO;
1294 goto err_eeprom;
1295 }
1296
1297 init_timer(&adapter->watchdog_timer);
1298 adapter->watchdog_timer.function = &igb_watchdog;
1299 adapter->watchdog_timer.data = (unsigned long) adapter;
1300
1301 init_timer(&adapter->phy_info_timer);
1302 adapter->phy_info_timer.function = &igb_update_phy_info;
1303 adapter->phy_info_timer.data = (unsigned long) adapter;
1304
1305 INIT_WORK(&adapter->reset_task, igb_reset_task);
1306 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1307
450c87c8 1308 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1309 adapter->fc_autoneg = true;
1310 hw->mac.autoneg = true;
1311 hw->phy.autoneg_advertised = 0x2f;
1312
1313 hw->fc.original_type = e1000_fc_default;
1314 hw->fc.type = e1000_fc_default;
1315
cbd347ad 1316 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1317 adapter->itr = IGB_START_ITR;
1318
1319 igb_validate_mdi_setting(hw);
1320
1321 adapter->rx_csum = 1;
1322
1323 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1324 * enable the ACPI Magic Packet filter
1325 */
1326
1327 if (hw->bus.func == 0 ||
1328 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1329 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1330
1331 if (eeprom_data & eeprom_apme_mask)
1332 adapter->eeprom_wol |= E1000_WUFC_MAG;
1333
1334 /* now that we have the eeprom settings, apply the special cases where
1335 * the eeprom may be wrong or the board simply won't support wake on
1336 * lan on a particular port */
1337 switch (pdev->device) {
1338 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1339 adapter->eeprom_wol = 0;
1340 break;
1341 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1342 case E1000_DEV_ID_82576_FIBER:
1343 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1344 /* Wake events only supported on port A for dual fiber
1345 * regardless of eeprom setting */
1346 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1347 adapter->eeprom_wol = 0;
1348 break;
1349 }
1350
1351 /* initialize the wol settings based on the eeprom settings */
1352 adapter->wol = adapter->eeprom_wol;
e1b86d84 1353 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1354
1355 /* reset the hardware with the new settings */
1356 igb_reset(adapter);
1357
1358 /* let the f/w know that the h/w is now under the control of the
1359 * driver. */
1360 igb_get_hw_control(adapter);
1361
1362 /* tell the stack to leave us alone until igb_open() is called */
1363 netif_carrier_off(netdev);
fd2ea0a7 1364 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1365
1366 strcpy(netdev->name, "eth%d");
1367 err = register_netdev(netdev);
1368 if (err)
1369 goto err_register;
1370
421e02f0 1371#ifdef CONFIG_IGB_DCA
bbd98fe4 1372 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1373 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1374 dev_info(&pdev->dev, "DCA enabled\n");
1375 /* Always use CB2 mode, difference is masked
1376 * in the CB driver. */
cbd347ad 1377 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6
JC		 1378 igb_setup_dca(adapter);
1379 }
1380#endif
1381
38c845c7
PO		 1382 /*
1383 * Initialize hardware timer: we keep it running just in case
1384 * that some program needs it later on.
1385 */
1386 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1387 adapter->cycles.read = igb_read_clock;
1388 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1389 adapter->cycles.mult = 1;
1390 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1391 wr32(E1000_TIMINCA,
1392 (1<<24) |
1393 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1394#if 0
1395 /*
1396 * Avoid rollover while we initialize by resetting the time counter.
1397 */
1398 wr32(E1000_SYSTIML, 0x00000000);
1399 wr32(E1000_SYSTIMH, 0x00000000);
1400#else
1401 /*
1402 * Set registers so that rollover occurs soon to test this.
1403 */
1404 wr32(E1000_SYSTIML, 0x00000000);
1405 wr32(E1000_SYSTIMH, 0xFF800000);
1406#endif
1407 wrfl();
1408 timecounter_init(&adapter->clock,
1409 &adapter->cycles,
1410 ktime_to_ns(ktime_get_real()));
1411
33af6bcc
PO		 1412 /*
1413 * Synchronize our NIC clock against system wall clock. NIC
1414 * time stamp reading requires ~3us per sample, each sample
1415 * was pretty stable even under load => only require 10
1416 * samples for each offset comparison.
1417 */
1418 memset(&adapter->compare, 0, sizeof(adapter->compare));
1419 adapter->compare.source = &adapter->clock;
1420 adapter->compare.target = ktime_get_real;
1421 adapter->compare.num_samples = 10;
1422 timecompare_update(&adapter->compare, 0);
1423
38c845c7
PO		 1424#ifdef DEBUG
1425 {
1426 char buffer[160];
1427 printk(KERN_DEBUG
1428 "igb: %s: hw %p initialized timer\n",
1429 igb_get_time_str(adapter, buffer),
1430 &adapter->hw);
1431 }
1432#endif
1433
9d5c8243
AK		 1434 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1435 /* print bus type/speed/width info */
7c510e4b 1436 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1437 netdev->name,
1438 ((hw->bus.speed == e1000_bus_speed_2500)
1439 ? "2.5Gb/s" : "unknown"),
1440 ((hw->bus.width == e1000_bus_width_pcie_x4)
1441 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1442 ? "Width x1" : "unknown"),
7c510e4b 1443 netdev->dev_addr);
9d5c8243
AK		 1444
1445 igb_read_part_num(hw, &part_num);
1446 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1447 (part_num >> 8), (part_num & 0xff));
1448
1449 dev_info(&pdev->dev,
1450 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1451 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1452 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1453 adapter->num_rx_queues, adapter->num_tx_queues);
1454
9d5c8243
AK		 1455 return 0;
1456
1457err_register:
1458 igb_release_hw_control(adapter);
1459err_eeprom:
1460 if (!igb_check_reset_block(hw))
f5f4cf08 1461 igb_reset_phy(hw);
9d5c8243
AK		 1462
1463 if (hw->flash_address)
1464 iounmap(hw->flash_address);
1465
a88f10ec 1466 igb_free_queues(adapter);
9d5c8243 1467err_sw_init:
9d5c8243
AK		 1468 iounmap(hw->hw_addr);
1469err_ioremap:
1470 free_netdev(netdev);
1471err_alloc_etherdev:
aed5dec3
AD		 1472 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1473 IORESOURCE_MEM));
9d5c8243
AK		 1474err_pci_reg:
1475err_dma:
1476 pci_disable_device(pdev);
1477 return err;
1478}
1479
1480/**
1481 * igb_remove - Device Removal Routine
1482 * @pdev: PCI device information struct
1483 *
1484 * igb_remove is called by the PCI subsystem to alert the driver
1485 * that it should release a PCI device. The could be caused by a
1486 * Hot-Plug event, or because the driver is going to be removed from
1487 * memory.
1488 **/
1489static void __devexit igb_remove(struct pci_dev *pdev)
1490{
1491 struct net_device *netdev = pci_get_drvdata(pdev);
1492 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1493 struct e1000_hw *hw = &adapter->hw;
ea943d41 1494 int err;
9d5c8243
AK		 1495
1496 /* flush_scheduled work may reschedule our watchdog task, so
1497 * explicitly disable watchdog tasks from being rescheduled */
1498 set_bit(__IGB_DOWN, &adapter->state);
1499 del_timer_sync(&adapter->watchdog_timer);
1500 del_timer_sync(&adapter->phy_info_timer);
1501
1502 flush_scheduled_work();
1503
421e02f0 1504#ifdef CONFIG_IGB_DCA
7dfc16fa 1505 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1506 dev_info(&pdev->dev, "DCA disabled\n");
1507 dca_remove_requester(&pdev->dev);
7dfc16fa 1508 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1509 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1510 }
1511#endif
1512
9d5c8243
AK		 1513 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1514 * would have already happened in close and is redundant. */
1515 igb_release_hw_control(adapter);
1516
1517 unregister_netdev(netdev);
1518
f5f4cf08
AD		 1519 if (!igb_check_reset_block(&adapter->hw))
1520 igb_reset_phy(&adapter->hw);
9d5c8243 1521
9d5c8243
AK		 1522 igb_reset_interrupt_capability(adapter);
1523
a88f10ec 1524 igb_free_queues(adapter);
9d5c8243 1525
28b0759c
AD		 1526 iounmap(hw->hw_addr);
1527 if (hw->flash_address)
1528 iounmap(hw->flash_address);
aed5dec3
AD		 1529 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1530 IORESOURCE_MEM));
9d5c8243
AK		 1531
1532 free_netdev(netdev);
1533
ea943d41
JK		 1534 err = pci_disable_pcie_error_reporting(pdev);
1535 if (err)
1536 dev_err(&pdev->dev,
1537 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1538
9d5c8243
AK		 1539 pci_disable_device(pdev);
1540}
1541
1542/**
1543 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1544 * @adapter: board private structure to initialize
1545 *
1546 * igb_sw_init initializes the Adapter private data structure.
1547 * Fields are initialized based on PCI device information and
1548 * OS network device settings (MTU size).
1549 **/
1550static int __devinit igb_sw_init(struct igb_adapter *adapter)
1551{
1552 struct e1000_hw *hw = &adapter->hw;
1553 struct net_device *netdev = adapter->netdev;
1554 struct pci_dev *pdev = adapter->pdev;
1555
1556 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1557
68fd9910
AD		 1558 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1559 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1560 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1561 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1562 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1563 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1564
661086df
PWJ		 1565 /* This call may decrease the number of queues depending on
1566 * interrupt mode. */
9d5c8243
AK		 1567 igb_set_interrupt_capability(adapter);
1568
1569 if (igb_alloc_queues(adapter)) {
1570 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1571 return -ENOMEM;
1572 }
1573
1574 /* Explicitly disable IRQ since the NIC can be in any state. */
1575 igb_irq_disable(adapter);
1576
1577 set_bit(__IGB_DOWN, &adapter->state);
1578 return 0;
1579}
1580
1581/**
1582 * igb_open - Called when a network interface is made active
1583 * @netdev: network interface device structure
1584 *
1585 * Returns 0 on success, negative value on failure
1586 *
1587 * The open entry point is called when a network interface is made
1588 * active by the system (IFF_UP). At this point all resources needed
1589 * for transmit and receive operations are allocated, the interrupt
1590 * handler is registered with the OS, the watchdog timer is started,
1591 * and the stack is notified that the interface is ready.
1592 **/
1593static int igb_open(struct net_device *netdev)
1594{
1595 struct igb_adapter *adapter = netdev_priv(netdev);
1596 struct e1000_hw *hw = &adapter->hw;
1597 int err;
1598 int i;
1599
1600 /* disallow open during test */
1601 if (test_bit(__IGB_TESTING, &adapter->state))
1602 return -EBUSY;
1603
1604 /* allocate transmit descriptors */
1605 err = igb_setup_all_tx_resources(adapter);
1606 if (err)
1607 goto err_setup_tx;
1608
1609 /* allocate receive descriptors */
1610 err = igb_setup_all_rx_resources(adapter);
1611 if (err)
1612 goto err_setup_rx;
1613
1614 /* e1000_power_up_phy(adapter); */
1615
1616 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1617 if ((adapter->hw.mng_cookie.status &
1618 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1619 igb_update_mng_vlan(adapter);
1620
1621 /* before we allocate an interrupt, we must be ready to handle it.
1622 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1623 * as soon as we call pci_request_irq, so we have to setup our
1624 * clean_rx handler before we do so. */
1625 igb_configure(adapter);
1626
e1739522
AD		 1627 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1628 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1629
9d5c8243
AK		 1630 err = igb_request_irq(adapter);
1631 if (err)
1632 goto err_req_irq;
1633
1634 /* From here on the code is the same as igb_up() */
1635 clear_bit(__IGB_DOWN, &adapter->state);
1636
844290e5
PW		 1637 for (i = 0; i < adapter->num_rx_queues; i++)
1638 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1639
1640 /* Clear any pending interrupts. */
1641 rd32(E1000_ICR);
844290e5
PW		 1642
1643 igb_irq_enable(adapter);
1644
d55b53ff
JK		 1645 netif_tx_start_all_queues(netdev);
1646
9d5c8243
AK		 1647 /* Fire a link status change interrupt to start the watchdog. */
1648 wr32(E1000_ICS, E1000_ICS_LSC);
1649
1650 return 0;
1651
1652err_req_irq:
1653 igb_release_hw_control(adapter);
1654 /* e1000_power_down_phy(adapter); */
1655 igb_free_all_rx_resources(adapter);
1656err_setup_rx:
1657 igb_free_all_tx_resources(adapter);
1658err_setup_tx:
1659 igb_reset(adapter);
1660
1661 return err;
1662}
1663
1664/**
1665 * igb_close - Disables a network interface
1666 * @netdev: network interface device structure
1667 *
1668 * Returns 0, this is not allowed to fail
1669 *
1670 * The close entry point is called when an interface is de-activated
1671 * by the OS. The hardware is still under the driver's control, but
1672 * needs to be disabled. A global MAC reset is issued to stop the
1673 * hardware, and all transmit and receive resources are freed.
1674 **/
1675static int igb_close(struct net_device *netdev)
1676{
1677 struct igb_adapter *adapter = netdev_priv(netdev);
1678
1679 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1680 igb_down(adapter);
1681
1682 igb_free_irq(adapter);
1683
1684 igb_free_all_tx_resources(adapter);
1685 igb_free_all_rx_resources(adapter);
1686
1687 /* kill manageability vlan ID if supported, but not if a vlan with
1688 * the same ID is registered on the host OS (let 8021q kill it) */
1689 if ((adapter->hw.mng_cookie.status &
1690 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1691 !(adapter->vlgrp &&
1692 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1693 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1694
1695 return 0;
1696}
1697
1698/**
1699 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1700 * @adapter: board private structure
1701 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1702 *
1703 * Return 0 on success, negative on failure
1704 **/
9d5c8243
AK		 1705int igb_setup_tx_resources(struct igb_adapter *adapter,
1706 struct igb_ring *tx_ring)
1707{
1708 struct pci_dev *pdev = adapter->pdev;
1709 int size;
1710
1711 size = sizeof(struct igb_buffer) * tx_ring->count;
1712 tx_ring->buffer_info = vmalloc(size);
1713 if (!tx_ring->buffer_info)
1714 goto err;
1715 memset(tx_ring->buffer_info, 0, size);
1716
1717 /* round up to nearest 4K */
85e8d004 1718 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1719 tx_ring->size = ALIGN(tx_ring->size, 4096);
1720
1721 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1722 &tx_ring->dma);
1723
1724 if (!tx_ring->desc)
1725 goto err;
1726
1727 tx_ring->adapter = adapter;
1728 tx_ring->next_to_use = 0;
1729 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1730 return 0;
1731
1732err:
1733 vfree(tx_ring->buffer_info);
1734 dev_err(&adapter->pdev->dev,
1735 "Unable to allocate memory for the transmit descriptor ring\n");
1736 return -ENOMEM;
1737}
1738
1739/**
1740 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1741 * (Descriptors) for all queues
1742 * @adapter: board private structure
1743 *
1744 * Return 0 on success, negative on failure
1745 **/
1746static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1747{
1748 int i, err = 0;
661086df 1749 int r_idx;
9d5c8243
AK		 1750
1751 for (i = 0; i < adapter->num_tx_queues; i++) {
1752 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1753 if (err) {
1754 dev_err(&adapter->pdev->dev,
1755 "Allocation for Tx Queue %u failed\n", i);
1756 for (i--; i >= 0; i--)
3b644cf6 1757 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1758 break;
1759 }
1760 }
1761
661086df
PWJ		 1762 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1763 r_idx = i % adapter->num_tx_queues;
1764 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1765 }
9d5c8243
AK		 1766 return err;
1767}
1768
1769/**
1770 * igb_configure_tx - Configure transmit Unit after Reset
1771 * @adapter: board private structure
1772 *
1773 * Configure the Tx unit of the MAC after a reset.
1774 **/
1775static void igb_configure_tx(struct igb_adapter *adapter)
1776{
0e014cb1 1777 u64 tdba;
9d5c8243
AK		 1778 struct e1000_hw *hw = &adapter->hw;
1779 u32 tctl;
1780 u32 txdctl, txctrl;
26bc19ec 1781 int i, j;
9d5c8243
AK		 1782
1783 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1784 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1785 j = ring->reg_idx;
1786 wr32(E1000_TDLEN(j),
85e8d004 1787 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1788 tdba = ring->dma;
26bc19ec 1789 wr32(E1000_TDBAL(j),
73cd78f1 1790 tdba & 0x00000000ffffffffULL);
26bc19ec 1791 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1792
26bc19ec
AD		 1793 ring->head = E1000_TDH(j);
1794 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1795 writel(0, hw->hw_addr + ring->tail);
1796 writel(0, hw->hw_addr + ring->head);
26bc19ec 1797 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1798 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1799 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1800
1801 /* Turn off Relaxed Ordering on head write-backs. The
1802 * writebacks MUST be delivered in order or it will
1803 * completely screw up our bookeeping.
1804 */
26bc19ec 1805 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1806 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1807 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1808 }
1809
e1739522
AD		 1810 /* disable queue 0 to prevent tail bump w/o re-configuration */
1811 if (adapter->vfs_allocated_count)
1812 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1813
1814 /* Program the Transmit Control Register */
9d5c8243
AK		 1815 tctl = rd32(E1000_TCTL);
1816 tctl &= ~E1000_TCTL_CT;
1817 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1818 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1819
1820 igb_config_collision_dist(hw);
1821
1822 /* Setup Transmit Descriptor Settings for eop descriptor */
1823 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1824
1825 /* Enable transmits */
1826 tctl |= E1000_TCTL_EN;
1827
1828 wr32(E1000_TCTL, tctl);
1829}
1830
1831/**
1832 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1833 * @adapter: board private structure
1834 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1835 *
1836 * Returns 0 on success, negative on failure
1837 **/
9d5c8243
AK		 1838int igb_setup_rx_resources(struct igb_adapter *adapter,
1839 struct igb_ring *rx_ring)
1840{
1841 struct pci_dev *pdev = adapter->pdev;
1842 int size, desc_len;
1843
1844 size = sizeof(struct igb_buffer) * rx_ring->count;
1845 rx_ring->buffer_info = vmalloc(size);
1846 if (!rx_ring->buffer_info)
1847 goto err;
1848 memset(rx_ring->buffer_info, 0, size);
1849
1850 desc_len = sizeof(union e1000_adv_rx_desc);
1851
1852 /* Round up to nearest 4K */
1853 rx_ring->size = rx_ring->count * desc_len;
1854 rx_ring->size = ALIGN(rx_ring->size, 4096);
1855
1856 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1857 &rx_ring->dma);
1858
1859 if (!rx_ring->desc)
1860 goto err;
1861
1862 rx_ring->next_to_clean = 0;
1863 rx_ring->next_to_use = 0;
9d5c8243
AK		 1864
1865 rx_ring->adapter = adapter;
9d5c8243
AK		 1866
1867 return 0;
1868
1869err:
1870 vfree(rx_ring->buffer_info);
1871 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1872 "the receive descriptor ring\n");
1873 return -ENOMEM;
1874}
1875
1876/**
1877 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1878 * (Descriptors) for all queues
1879 * @adapter: board private structure
1880 *
1881 * Return 0 on success, negative on failure
1882 **/
1883static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1884{
1885 int i, err = 0;
1886
1887 for (i = 0; i < adapter->num_rx_queues; i++) {
1888 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1889 if (err) {
1890 dev_err(&adapter->pdev->dev,
1891 "Allocation for Rx Queue %u failed\n", i);
1892 for (i--; i >= 0; i--)
3b644cf6 1893 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1894 break;
1895 }
1896 }
1897
1898 return err;
1899}
1900
1901/**
1902 * igb_setup_rctl - configure the receive control registers
1903 * @adapter: Board private structure
1904 **/
1905static void igb_setup_rctl(struct igb_adapter *adapter)
1906{
1907 struct e1000_hw *hw = &adapter->hw;
1908 u32 rctl;
1909 u32 srrctl = 0;
26bc19ec 1910 int i, j;
9d5c8243
AK		 1911
1912 rctl = rd32(E1000_RCTL);
1913
1914 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1915 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1916
69d728ba 1917 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1918 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1919
87cb7e8c
AK		 1920 /*
1921 * enable stripping of CRC. It's unlikely this will break BMC
1922 * redirection as it did with e1000. Newer features require
1923 * that the HW strips the CRC.
73cd78f1 1924 */
87cb7e8c 1925 rctl |= E1000_RCTL_SECRC;
9d5c8243 1926
9b07f3d3 1927 /*
ec54d7d6 1928 * disable store bad packets and clear size bits.
9b07f3d3 1929 */
ec54d7d6 1930 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1931
ec54d7d6 1932 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1933 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1934
1935 /* Setup buffer sizes */
1936 switch (adapter->rx_buffer_len) {
1937 case IGB_RXBUFFER_256:
1938 rctl |= E1000_RCTL_SZ_256;
1939 break;
1940 case IGB_RXBUFFER_512:
1941 rctl |= E1000_RCTL_SZ_512;
1942 break;
1943 default:
1944 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1945 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1946 break;
9d5c8243
AK		 1947 }
1948
1949 /* 82575 and greater support packet-split where the protocol
1950 * header is placed in skb->data and the packet data is
1951 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1952 * In the case of a non-split, skb->data is linearly filled,
1953 * followed by the page buffers. Therefore, skb->data is
1954 * sized to hold the largest protocol header.
1955 */
1956 /* allocations using alloc_page take too long for regular MTU
1957 * so only enable packet split for jumbo frames */
ec54d7d6 1958 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1959 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1960 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1961 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1962 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1963 } else {
1964 adapter->rx_ps_hdr_size = 0;
1965 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1966 }
1967
e1739522
AD		 1968 /* Attention!!! For SR-IOV PF driver operations you must enable
1969 * queue drop for all VF and PF queues to prevent head of line blocking
1970 * if an un-trusted VF does not provide descriptors to hardware.
1971 */
1972 if (adapter->vfs_allocated_count) {
1973 u32 vmolr;
1974
1975 j = adapter->rx_ring[0].reg_idx;
1976
1977 /* set all queue drop enable bits */
1978 wr32(E1000_QDE, ALL_QUEUES);
1979 srrctl |= E1000_SRRCTL_DROP_EN;
1980
1981 /* disable queue 0 to prevent tail write w/o re-config */
1982 wr32(E1000_RXDCTL(0), 0);
1983
1984 vmolr = rd32(E1000_VMOLR(j));
1985 if (rctl & E1000_RCTL_LPE)
1986 vmolr |= E1000_VMOLR_LPE;
1987 if (adapter->num_rx_queues > 0)
1988 vmolr |= E1000_VMOLR_RSSE;
1989 wr32(E1000_VMOLR(j), vmolr);
1990 }
1991
26bc19ec
AD		 1992 for (i = 0; i < adapter->num_rx_queues; i++) {
1993 j = adapter->rx_ring[i].reg_idx;
1994 wr32(E1000_SRRCTL(j), srrctl);
1995 }
9d5c8243
AK		 1996
1997 wr32(E1000_RCTL, rctl);
1998}
1999
e1739522
AD		 2000/**
2001 * igb_rlpml_set - set maximum receive packet size
2002 * @adapter: board private structure
2003 *
2004 * Configure maximum receivable packet size.
2005 **/
2006static void igb_rlpml_set(struct igb_adapter *adapter)
2007{
2008 u32 max_frame_size = adapter->max_frame_size;
2009 struct e1000_hw *hw = &adapter->hw;
2010 u16 pf_id = adapter->vfs_allocated_count;
2011
2012 if (adapter->vlgrp)
2013 max_frame_size += VLAN_TAG_SIZE;
2014
2015 /* if vfs are enabled we set RLPML to the largest possible request
2016 * size and set the VMOLR RLPML to the size we need */
2017 if (pf_id) {
2018 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2019 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2020 }
2021
2022 wr32(E1000_RLPML, max_frame_size);
2023}
2024
2025/**
2026 * igb_configure_vt_default_pool - Configure VT default pool
2027 * @adapter: board private structure
2028 *
2029 * Configure the default pool
2030 **/
2031static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2032{
2033 struct e1000_hw *hw = &adapter->hw;
2034 u16 pf_id = adapter->vfs_allocated_count;
2035 u32 vtctl;
2036
2037 /* not in sr-iov mode - do nothing */
2038 if (!pf_id)
2039 return;
2040
2041 vtctl = rd32(E1000_VT_CTL);
2042 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2043 E1000_VT_CTL_DISABLE_DEF_POOL);
2044 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2045 wr32(E1000_VT_CTL, vtctl);
2046}
2047
9d5c8243
AK		 2048/**
2049 * igb_configure_rx - Configure receive Unit after Reset
2050 * @adapter: board private structure
2051 *
2052 * Configure the Rx unit of the MAC after a reset.
2053 **/
2054static void igb_configure_rx(struct igb_adapter *adapter)
2055{
2056 u64 rdba;
2057 struct e1000_hw *hw = &adapter->hw;
2058 u32 rctl, rxcsum;
2059 u32 rxdctl;
9107584e 2060 int i;
9d5c8243
AK		 2061
2062 /* disable receives while setting up the descriptors */
2063 rctl = rd32(E1000_RCTL);
2064 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2065 wrfl();
2066 mdelay(10);
2067
2068 if (adapter->itr_setting > 3)
6eb5a7f1 2069 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2070
2071 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2072 * the Base and Length of the Rx Descriptor Ring */
2073 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2074 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2075 int j = ring->reg_idx;
9d5c8243 2076 rdba = ring->dma;
26bc19ec 2077 wr32(E1000_RDBAL(j),
73cd78f1 2078 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2079 wr32(E1000_RDBAH(j), rdba >> 32);
2080 wr32(E1000_RDLEN(j),
73cd78f1 2081 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2082
26bc19ec
AD		 2083 ring->head = E1000_RDH(j);
2084 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2085 writel(0, hw->hw_addr + ring->tail);
2086 writel(0, hw->hw_addr + ring->head);
2087
26bc19ec 2088 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2089 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2090 rxdctl &= 0xFFF00000;
2091 rxdctl |= IGB_RX_PTHRESH;
2092 rxdctl |= IGB_RX_HTHRESH << 8;
2093 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2094 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2095 }
2096
2097 if (adapter->num_rx_queues > 1) {
2098 u32 random[10];
2099 u32 mrqc;
2100 u32 j, shift;
2101 union e1000_reta {
2102 u32 dword;
2103 u8 bytes[4];
2104 } reta;
2105
2106 get_random_bytes(&random[0], 40);
2107
2d064c06
AD		 2108 if (hw->mac.type >= e1000_82576)
2109 shift = 0;
2110 else
2111 shift = 6;
9d5c8243
AK		 2112 for (j = 0; j < (32 * 4); j++) {
2113 reta.bytes[j & 3] =
26bc19ec 2114 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2115 if ((j & 3) == 3)
2116 writel(reta.dword,
2117 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2118 }
e1739522
AD		 2119 if (adapter->vfs_allocated_count)
2120 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2121 else
2122 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2123
2124 /* Fill out hash function seeds */
2125 for (j = 0; j < 10; j++)
2126 array_wr32(E1000_RSSRK(0), j, random[j]);
2127
2128 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2129 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2130 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2131 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2132 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2133 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2134 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2135 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2136
2137
2138 wr32(E1000_MRQC, mrqc);
2139
2140 /* Multiqueue and raw packet checksumming are mutually
2141 * exclusive. Note that this not the same as TCP/IP
2142 * checksumming, which works fine. */
2143 rxcsum = rd32(E1000_RXCSUM);
2144 rxcsum |= E1000_RXCSUM_PCSD;
2145 wr32(E1000_RXCSUM, rxcsum);
2146 } else {
e1739522
AD		 2147 /* Enable multi-queue for sr-iov */
2148 if (adapter->vfs_allocated_count)
2149 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2150 /* Enable Receive Checksum Offload for TCP and UDP */
2151 rxcsum = rd32(E1000_RXCSUM);
56fbbb4e
AD		 2152 if (adapter->rx_csum)
2153 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2154 else
2155 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2156
9d5c8243
AK		 2157 wr32(E1000_RXCSUM, rxcsum);
2158 }
2159
e1739522
AD		 2160 /* Set the default pool for the PF's first queue */
2161 igb_configure_vt_default_pool(adapter);
2162
2163 igb_rlpml_set(adapter);
9d5c8243
AK		 2164
2165 /* Enable Receives */
2166 wr32(E1000_RCTL, rctl);
2167}
2168
2169/**
2170 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2171 * @tx_ring: Tx descriptor ring for a specific queue
2172 *
2173 * Free all transmit software resources
2174 **/
68fd9910 2175void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2176{
3b644cf6 2177 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2178
3b644cf6 2179 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2180
2181 vfree(tx_ring->buffer_info);
2182 tx_ring->buffer_info = NULL;
2183
2184 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2185
2186 tx_ring->desc = NULL;
2187}
2188
2189/**
2190 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2191 * @adapter: board private structure
2192 *
2193 * Free all transmit software resources
2194 **/
2195static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2196{
2197 int i;
2198
2199 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2200 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2201}
2202
2203static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2204 struct igb_buffer *buffer_info)
2205{
2206 if (buffer_info->dma) {
2207 pci_unmap_page(adapter->pdev,
2208 buffer_info->dma,
2209 buffer_info->length,
2210 PCI_DMA_TODEVICE);
2211 buffer_info->dma = 0;
2212 }
2213 if (buffer_info->skb) {
2214 dev_kfree_skb_any(buffer_info->skb);
2215 buffer_info->skb = NULL;
2216 }
2217 buffer_info->time_stamp = 0;
73cd78f1 2218 buffer_info->next_to_watch = 0;
9d5c8243
AK		 2219 /* buffer_info must be completely set up in the transmit path */
2220}
2221
2222/**
2223 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2224 * @tx_ring: ring to be cleaned
2225 **/
3b644cf6 2226static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2227{
3b644cf6 2228 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2229 struct igb_buffer *buffer_info;
2230 unsigned long size;
2231 unsigned int i;
2232
2233 if (!tx_ring->buffer_info)
2234 return;
2235 /* Free all the Tx ring sk_buffs */
2236
2237 for (i = 0; i < tx_ring->count; i++) {
2238 buffer_info = &tx_ring->buffer_info[i];
2239 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2240 }
2241
2242 size = sizeof(struct igb_buffer) * tx_ring->count;
2243 memset(tx_ring->buffer_info, 0, size);
2244
2245 /* Zero out the descriptor ring */
2246
2247 memset(tx_ring->desc, 0, tx_ring->size);
2248
2249 tx_ring->next_to_use = 0;
2250 tx_ring->next_to_clean = 0;
2251
2252 writel(0, adapter->hw.hw_addr + tx_ring->head);
2253 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2254}
2255
2256/**
2257 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2258 * @adapter: board private structure
2259 **/
2260static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2261{
2262 int i;
2263
2264 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2265 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2266}
2267
2268/**
2269 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2270 * @rx_ring: ring to clean the resources from
2271 *
2272 * Free all receive software resources
2273 **/
68fd9910 2274void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2275{
3b644cf6 2276 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2277
3b644cf6 2278 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2279
2280 vfree(rx_ring->buffer_info);
2281 rx_ring->buffer_info = NULL;
2282
2283 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2284
2285 rx_ring->desc = NULL;
2286}
2287
2288/**
2289 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2290 * @adapter: board private structure
2291 *
2292 * Free all receive software resources
2293 **/
2294static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2295{
2296 int i;
2297
2298 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2299 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2300}
2301
2302/**
2303 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2304 * @rx_ring: ring to free buffers from
2305 **/
3b644cf6 2306static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2307{
3b644cf6 2308 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2309 struct igb_buffer *buffer_info;
2310 struct pci_dev *pdev = adapter->pdev;
2311 unsigned long size;
2312 unsigned int i;
2313
2314 if (!rx_ring->buffer_info)
2315 return;
2316 /* Free all the Rx ring sk_buffs */
2317 for (i = 0; i < rx_ring->count; i++) {
2318 buffer_info = &rx_ring->buffer_info[i];
2319 if (buffer_info->dma) {
2320 if (adapter->rx_ps_hdr_size)
2321 pci_unmap_single(pdev, buffer_info->dma,
2322 adapter->rx_ps_hdr_size,
2323 PCI_DMA_FROMDEVICE);
2324 else
2325 pci_unmap_single(pdev, buffer_info->dma,
2326 adapter->rx_buffer_len,
2327 PCI_DMA_FROMDEVICE);
2328 buffer_info->dma = 0;
2329 }
2330
2331 if (buffer_info->skb) {
2332 dev_kfree_skb(buffer_info->skb);
2333 buffer_info->skb = NULL;
2334 }
2335 if (buffer_info->page) {
bf36c1a0
AD		 2336 if (buffer_info->page_dma)
2337 pci_unmap_page(pdev, buffer_info->page_dma,
2338 PAGE_SIZE / 2,
2339 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2340 put_page(buffer_info->page);
2341 buffer_info->page = NULL;
2342 buffer_info->page_dma = 0;
bf36c1a0 2343 buffer_info->page_offset = 0;
9d5c8243
AK		 2344 }
2345 }
2346
9d5c8243
AK		 2347 size = sizeof(struct igb_buffer) * rx_ring->count;
2348 memset(rx_ring->buffer_info, 0, size);
2349
2350 /* Zero out the descriptor ring */
2351 memset(rx_ring->desc, 0, rx_ring->size);
2352
2353 rx_ring->next_to_clean = 0;
2354 rx_ring->next_to_use = 0;
2355
2356 writel(0, adapter->hw.hw_addr + rx_ring->head);
2357 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2358}
2359
2360/**
2361 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2362 * @adapter: board private structure
2363 **/
2364static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2365{
2366 int i;
2367
2368 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2369 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2370}
2371
2372/**
2373 * igb_set_mac - Change the Ethernet Address of the NIC
2374 * @netdev: network interface device structure
2375 * @p: pointer to an address structure
2376 *
2377 * Returns 0 on success, negative on failure
2378 **/
2379static int igb_set_mac(struct net_device *netdev, void *p)
2380{
2381 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2382 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2383 struct sockaddr *addr = p;
2384
2385 if (!is_valid_ether_addr(addr->sa_data))
2386 return -EADDRNOTAVAIL;
2387
2388 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2389 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2390
28b0759c 2391 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243 2392
e1739522
AD		 2393 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2394
9d5c8243
AK		 2395 return 0;
2396}
2397
2398/**
2399 * igb_set_multi - Multicast and Promiscuous mode set
2400 * @netdev: network interface device structure
2401 *
2402 * The set_multi entry point is called whenever the multicast address
2403 * list or the network interface flags are updated. This routine is
2404 * responsible for configuring the hardware for proper multicast,
2405 * promiscuous mode, and all-multi behavior.
2406 **/
2407static void igb_set_multi(struct net_device *netdev)
2408{
2409 struct igb_adapter *adapter = netdev_priv(netdev);
2410 struct e1000_hw *hw = &adapter->hw;
2411 struct e1000_mac_info *mac = &hw->mac;
2412 struct dev_mc_list *mc_ptr;
2413 u8 *mta_list;
2414 u32 rctl;
2415 int i;
2416
2417 /* Check for Promiscuous and All Multicast modes */
2418
2419 rctl = rd32(E1000_RCTL);
2420
746b9f02 2421 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2422 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2423 rctl &= ~E1000_RCTL_VFE;
2424 } else {
2425 if (netdev->flags & IFF_ALLMULTI) {
2426 rctl |= E1000_RCTL_MPE;
2427 rctl &= ~E1000_RCTL_UPE;
2428 } else
2429 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2430 rctl |= E1000_RCTL_VFE;
746b9f02 2431 }
9d5c8243
AK		 2432 wr32(E1000_RCTL, rctl);
2433
2434 if (!netdev->mc_count) {
2435 /* nothing to program, so clear mc list */
8a900862
AD		 2436 igb_update_mc_addr_list(hw, NULL, 0, 1,
2437 mac->rar_entry_count);
9d5c8243
AK		 2438 return;
2439 }
2440
2441 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2442 if (!mta_list)
2443 return;
2444
2445 /* The shared function expects a packed array of only addresses. */
2446 mc_ptr = netdev->mc_list;
2447
2448 for (i = 0; i < netdev->mc_count; i++) {
2449 if (!mc_ptr)
2450 break;
2451 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2452 mc_ptr = mc_ptr->next;
2453 }
e1739522
AD		 2454 igb_update_mc_addr_list(hw, mta_list, i,
2455 adapter->vfs_allocated_count + 1,
2456 mac->rar_entry_count);
2457
2458 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
9d5c8243
AK		 2459 kfree(mta_list);
2460}
2461
2462/* Need to wait a few seconds after link up to get diagnostic information from
2463 * the phy */
2464static void igb_update_phy_info(unsigned long data)
2465{
2466 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2467 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2468}
2469
4d6b725e
AD		 2470/**
2471 * igb_has_link - check shared code for link and determine up/down
2472 * @adapter: pointer to driver private info
2473 **/
2474static bool igb_has_link(struct igb_adapter *adapter)
2475{
2476 struct e1000_hw *hw = &adapter->hw;
2477 bool link_active = false;
2478 s32 ret_val = 0;
2479
2480 /* get_link_status is set on LSC (link status) interrupt or
2481 * rx sequence error interrupt. get_link_status will stay
2482 * false until the e1000_check_for_link establishes link
2483 * for copper adapters ONLY
2484 */
2485 switch (hw->phy.media_type) {
2486 case e1000_media_type_copper:
2487 if (hw->mac.get_link_status) {
2488 ret_val = hw->mac.ops.check_for_link(hw);
2489 link_active = !hw->mac.get_link_status;
2490 } else {
2491 link_active = true;
2492 }
2493 break;
2494 case e1000_media_type_fiber:
2495 ret_val = hw->mac.ops.check_for_link(hw);
2496 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2497 break;
2498 case e1000_media_type_internal_serdes:
2499 ret_val = hw->mac.ops.check_for_link(hw);
2500 link_active = hw->mac.serdes_has_link;
2501 break;
2502 default:
2503 case e1000_media_type_unknown:
2504 break;
2505 }
2506
2507 return link_active;
2508}
2509
9d5c8243
AK		 2510/**
2511 * igb_watchdog - Timer Call-back
2512 * @data: pointer to adapter cast into an unsigned long
2513 **/
2514static void igb_watchdog(unsigned long data)
2515{
2516 struct igb_adapter *adapter = (struct igb_adapter *)data;
2517 /* Do the rest outside of interrupt context */
2518 schedule_work(&adapter->watchdog_task);
2519}
2520
2521static void igb_watchdog_task(struct work_struct *work)
2522{
2523 struct igb_adapter *adapter = container_of(work,
2524 struct igb_adapter, watchdog_task);
2525 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2526 struct net_device *netdev = adapter->netdev;
2527 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2528 u32 link;
7a6ea550 2529 u32 eics = 0;
7a6ea550 2530 int i;
9d5c8243 2531
4d6b725e
AD		 2532 link = igb_has_link(adapter);
2533 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2534 goto link_up;
2535
9d5c8243
AK		 2536 if (link) {
2537 if (!netif_carrier_ok(netdev)) {
2538 u32 ctrl;
2539 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2540 &adapter->link_speed,
2541 &adapter->link_duplex);
2542
2543 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2544 /* Links status message must follow this format */
2545 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2546 "Flow Control: %s\n",
527d47c1 2547 netdev->name,
9d5c8243
AK		 2548 adapter->link_speed,
2549 adapter->link_duplex == FULL_DUPLEX ?
2550 "Full Duplex" : "Half Duplex",
2551 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2552 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2553 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2554 E1000_CTRL_TFCE) ? "TX" : "None")));
2555
2556 /* tweak tx_queue_len according to speed/duplex and
2557 * adjust the timeout factor */
2558 netdev->tx_queue_len = adapter->tx_queue_len;
2559 adapter->tx_timeout_factor = 1;
2560 switch (adapter->link_speed) {
2561 case SPEED_10:
2562 netdev->tx_queue_len = 10;
2563 adapter->tx_timeout_factor = 14;
2564 break;
2565 case SPEED_100:
2566 netdev->tx_queue_len = 100;
2567 /* maybe add some timeout factor ? */
2568 break;
2569 }
2570
2571 netif_carrier_on(netdev);
fd2ea0a7 2572 netif_tx_wake_all_queues(netdev);
9d5c8243 2573
4b1a9877 2574 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2575 if (!test_bit(__IGB_DOWN, &adapter->state))
2576 mod_timer(&adapter->phy_info_timer,
2577 round_jiffies(jiffies + 2 * HZ));
2578 }
2579 } else {
2580 if (netif_carrier_ok(netdev)) {
2581 adapter->link_speed = 0;
2582 adapter->link_duplex = 0;
527d47c1
AD		 2583 /* Links status message must follow this format */
2584 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2585 netdev->name);
9d5c8243 2586 netif_carrier_off(netdev);
fd2ea0a7 2587 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2588
2589 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2590 if (!test_bit(__IGB_DOWN, &adapter->state))
2591 mod_timer(&adapter->phy_info_timer,
2592 round_jiffies(jiffies + 2 * HZ));
2593 }
2594 }
2595
2596link_up:
2597 igb_update_stats(adapter);
2598
4b1a9877 2599 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2600 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2601 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2602 adapter->colc_old = adapter->stats.colc;
2603
2604 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2605 adapter->gorc_old = adapter->stats.gorc;
2606 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2607 adapter->gotc_old = adapter->stats.gotc;
2608
2609 igb_update_adaptive(&adapter->hw);
2610
2611 if (!netif_carrier_ok(netdev)) {
2612 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2613 /* We've lost link, so the controller stops DMA,
2614 * but we've got queued Tx work that's never going
2615 * to get done, so reset controller to flush Tx.
2616 * (Do the reset outside of interrupt context). */
2617 adapter->tx_timeout_count++;
2618 schedule_work(&adapter->reset_task);
2619 }
2620 }
2621
2622 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2623 if (adapter->msix_entries) {
2624 for (i = 0; i < adapter->num_rx_queues; i++)
2625 eics |= adapter->rx_ring[i].eims_value;
2626 wr32(E1000_EICS, eics);
2627 } else {
2628 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2629 }
9d5c8243
AK		 2630
2631 /* Force detection of hung controller every watchdog period */
2632 tx_ring->detect_tx_hung = true;
2633
2634 /* Reset the timer */
2635 if (!test_bit(__IGB_DOWN, &adapter->state))
2636 mod_timer(&adapter->watchdog_timer,
2637 round_jiffies(jiffies + 2 * HZ));
2638}
2639
2640enum latency_range {
2641 lowest_latency = 0,
2642 low_latency = 1,
2643 bulk_latency = 2,
2644 latency_invalid = 255
2645};
2646
2647
6eb5a7f1
AD		 2648/**
2649 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2650 *
2651 * Stores a new ITR value based on strictly on packet size. This
2652 * algorithm is less sophisticated than that used in igb_update_itr,
2653 * due to the difficulty of synchronizing statistics across multiple
2654 * receive rings. The divisors and thresholds used by this fuction
2655 * were determined based on theoretical maximum wire speed and testing
2656 * data, in order to minimize response time while increasing bulk
2657 * throughput.
2658 * This functionality is controlled by the InterruptThrottleRate module
2659 * parameter (see igb_param.c)
2660 * NOTE: This function is called only when operating in a multiqueue
2661 * receive environment.
2662 * @rx_ring: pointer to ring
2663 **/
2664static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2665{
6eb5a7f1
AD		 2666 int new_val = rx_ring->itr_val;
2667 int avg_wire_size = 0;
2668 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2669
6eb5a7f1
AD		 2670 if (!rx_ring->total_packets)
2671 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2672
6eb5a7f1
AD		 2673 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2674 * ints/sec - ITR timer value of 120 ticks.
2675 */
2676 if (adapter->link_speed != SPEED_1000) {
2677 new_val = 120;
2678 goto set_itr_val;
9d5c8243 2679 }
6eb5a7f1 2680 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2681
6eb5a7f1
AD		 2682 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2683 avg_wire_size += 24;
2684
2685 /* Don't starve jumbo frames */
2686 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2687
6eb5a7f1
AD		 2688 /* Give a little boost to mid-size frames */
2689 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2690 new_val = avg_wire_size / 3;
2691 else
2692 new_val = avg_wire_size / 2;
9d5c8243 2693
6eb5a7f1 2694set_itr_val:
9d5c8243
AK		 2695 if (new_val != rx_ring->itr_val) {
2696 rx_ring->itr_val = new_val;
6eb5a7f1 2697 rx_ring->set_itr = 1;
9d5c8243 2698 }
6eb5a7f1
AD		 2699clear_counts:
2700 rx_ring->total_bytes = 0;
2701 rx_ring->total_packets = 0;
9d5c8243
AK		 2702}
2703
2704/**
2705 * igb_update_itr - update the dynamic ITR value based on statistics
2706 * Stores a new ITR value based on packets and byte
2707 * counts during the last interrupt. The advantage of per interrupt
2708 * computation is faster updates and more accurate ITR for the current
2709 * traffic pattern. Constants in this function were computed
2710 * based on theoretical maximum wire speed and thresholds were set based
2711 * on testing data as well as attempting to minimize response time
2712 * while increasing bulk throughput.
2713 * this functionality is controlled by the InterruptThrottleRate module
2714 * parameter (see igb_param.c)
2715 * NOTE: These calculations are only valid when operating in a single-
2716 * queue environment.
2717 * @adapter: pointer to adapter
2718 * @itr_setting: current adapter->itr
2719 * @packets: the number of packets during this measurement interval
2720 * @bytes: the number of bytes during this measurement interval
2721 **/
2722static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2723 int packets, int bytes)
2724{
2725 unsigned int retval = itr_setting;
2726
2727 if (packets == 0)
2728 goto update_itr_done;
2729
2730 switch (itr_setting) {
2731 case lowest_latency:
2732 /* handle TSO and jumbo frames */
2733 if (bytes/packets > 8000)
2734 retval = bulk_latency;
2735 else if ((packets < 5) && (bytes > 512))
2736 retval = low_latency;
2737 break;
2738 case low_latency: /* 50 usec aka 20000 ints/s */
2739 if (bytes > 10000) {
2740 /* this if handles the TSO accounting */
2741 if (bytes/packets > 8000) {
2742 retval = bulk_latency;
2743 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2744 retval = bulk_latency;
2745 } else if ((packets > 35)) {
2746 retval = lowest_latency;
2747 }
2748 } else if (bytes/packets > 2000) {
2749 retval = bulk_latency;
2750 } else if (packets <= 2 && bytes < 512) {
2751 retval = lowest_latency;
2752 }
2753 break;
2754 case bulk_latency: /* 250 usec aka 4000 ints/s */
2755 if (bytes > 25000) {
2756 if (packets > 35)
2757 retval = low_latency;
1e5c3d21 2758 } else if (bytes < 1500) {
9d5c8243
AK		 2759 retval = low_latency;
2760 }
2761 break;
2762 }
2763
2764update_itr_done:
2765 return retval;
2766}
2767
6eb5a7f1 2768static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2769{
2770 u16 current_itr;
2771 u32 new_itr = adapter->itr;
2772
2773 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2774 if (adapter->link_speed != SPEED_1000) {
2775 current_itr = 0;
2776 new_itr = 4000;
2777 goto set_itr_now;
2778 }
2779
2780 adapter->rx_itr = igb_update_itr(adapter,
2781 adapter->rx_itr,
2782 adapter->rx_ring->total_packets,
2783 adapter->rx_ring->total_bytes);
9d5c8243 2784
6eb5a7f1 2785 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2786 adapter->tx_itr = igb_update_itr(adapter,
2787 adapter->tx_itr,
2788 adapter->tx_ring->total_packets,
2789 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2790 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2791 } else {
2792 current_itr = adapter->rx_itr;
2793 }
2794
6eb5a7f1 2795 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2796 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2797 current_itr = low_latency;
2798
9d5c8243
AK		 2799 switch (current_itr) {
2800 /* counts and packets in update_itr are dependent on these numbers */
2801 case lowest_latency:
2802 new_itr = 70000;
2803 break;
2804 case low_latency:
2805 new_itr = 20000; /* aka hwitr = ~200 */
2806 break;
2807 case bulk_latency:
2808 new_itr = 4000;
2809 break;
2810 default:
2811 break;
2812 }
2813
2814set_itr_now:
6eb5a7f1
AD		 2815 adapter->rx_ring->total_bytes = 0;
2816 adapter->rx_ring->total_packets = 0;
2817 if (adapter->rx_ring->buddy) {
2818 adapter->rx_ring->buddy->total_bytes = 0;
2819 adapter->rx_ring->buddy->total_packets = 0;
2820 }
2821
9d5c8243
AK		 2822 if (new_itr != adapter->itr) {
2823 /* this attempts to bias the interrupt rate towards Bulk
2824 * by adding intermediate steps when interrupt rate is
2825 * increasing */
2826 new_itr = new_itr > adapter->itr ?
2827 min(adapter->itr + (new_itr >> 2), new_itr) :
2828 new_itr;
2829 /* Don't write the value here; it resets the adapter's
2830 * internal timer, and causes us to delay far longer than
2831 * we should between interrupts. Instead, we write the ITR
2832 * value at the beginning of the next interrupt so the timing
2833 * ends up being correct.
2834 */
2835 adapter->itr = new_itr;
6eb5a7f1
AD		 2836 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2837 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2838 }
2839
2840 return;
2841}
2842
2843
2844#define IGB_TX_FLAGS_CSUM 0x00000001
2845#define IGB_TX_FLAGS_VLAN 0x00000002
2846#define IGB_TX_FLAGS_TSO 0x00000004
2847#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2848#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2849#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2850#define IGB_TX_FLAGS_VLAN_SHIFT 16
2851
2852static inline int igb_tso_adv(struct igb_adapter *adapter,
2853 struct igb_ring *tx_ring,
2854 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2855{
2856 struct e1000_adv_tx_context_desc *context_desc;
2857 unsigned int i;
2858 int err;
2859 struct igb_buffer *buffer_info;
2860 u32 info = 0, tu_cmd = 0;
2861 u32 mss_l4len_idx, l4len;
2862 *hdr_len = 0;
2863
2864 if (skb_header_cloned(skb)) {
2865 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2866 if (err)
2867 return err;
2868 }
2869
2870 l4len = tcp_hdrlen(skb);
2871 *hdr_len += l4len;
2872
2873 if (skb->protocol == htons(ETH_P_IP)) {
2874 struct iphdr *iph = ip_hdr(skb);
2875 iph->tot_len = 0;
2876 iph->check = 0;
2877 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2878 iph->daddr, 0,
2879 IPPROTO_TCP,
2880 0);
2881 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2882 ipv6_hdr(skb)->payload_len = 0;
2883 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2884 &ipv6_hdr(skb)->daddr,
2885 0, IPPROTO_TCP, 0);
2886 }
2887
2888 i = tx_ring->next_to_use;
2889
2890 buffer_info = &tx_ring->buffer_info[i];
2891 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2892 /* VLAN MACLEN IPLEN */
2893 if (tx_flags & IGB_TX_FLAGS_VLAN)
2894 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2895 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2896 *hdr_len += skb_network_offset(skb);
2897 info |= skb_network_header_len(skb);
2898 *hdr_len += skb_network_header_len(skb);
2899 context_desc->vlan_macip_lens = cpu_to_le32(info);
2900
2901 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2902 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2903
2904 if (skb->protocol == htons(ETH_P_IP))
2905 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2906 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2907
2908 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2909
2910 /* MSS L4LEN IDX */
2911 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2912 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2913
73cd78f1 2914 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 2915 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2916 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2917
2918 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2919 context_desc->seqnum_seed = 0;
2920
2921 buffer_info->time_stamp = jiffies;
0e014cb1 2922 buffer_info->next_to_watch = i;
9d5c8243
AK		 2923 buffer_info->dma = 0;
2924 i++;
2925 if (i == tx_ring->count)
2926 i = 0;
2927
2928 tx_ring->next_to_use = i;
2929
2930 return true;
2931}
2932
2933static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2934 struct igb_ring *tx_ring,
2935 struct sk_buff *skb, u32 tx_flags)
2936{
2937 struct e1000_adv_tx_context_desc *context_desc;
2938 unsigned int i;
2939 struct igb_buffer *buffer_info;
2940 u32 info = 0, tu_cmd = 0;
2941
2942 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2943 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2944 i = tx_ring->next_to_use;
2945 buffer_info = &tx_ring->buffer_info[i];
2946 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2947
2948 if (tx_flags & IGB_TX_FLAGS_VLAN)
2949 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2950 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2951 if (skb->ip_summed == CHECKSUM_PARTIAL)
2952 info |= skb_network_header_len(skb);
2953
2954 context_desc->vlan_macip_lens = cpu_to_le32(info);
2955
2956 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2957
2958 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2959 switch (skb->protocol) {
09640e63 2960 case cpu_to_be16(ETH_P_IP):
9d5c8243 2961 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2962 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2963 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2964 break;
09640e63 2965 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2966 /* XXX what about other V6 headers?? */
2967 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2968 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2969 break;
2970 default:
2971 if (unlikely(net_ratelimit()))
2972 dev_warn(&adapter->pdev->dev,
2973 "partial checksum but proto=%x!\n",
2974 skb->protocol);
2975 break;
2976 }
9d5c8243
AK		 2977 }
2978
2979 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2980 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2981 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2982 context_desc->mss_l4len_idx =
2983 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 2984 else
2985 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 2986
2987 buffer_info->time_stamp = jiffies;
0e014cb1 2988 buffer_info->next_to_watch = i;
9d5c8243
AK		 2989 buffer_info->dma = 0;
2990
2991 i++;
2992 if (i == tx_ring->count)
2993 i = 0;
2994 tx_ring->next_to_use = i;
2995
2996 return true;
2997 }
9d5c8243
AK		 2998 return false;
2999}
3000
3001#define IGB_MAX_TXD_PWR 16
3002#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3003
3004static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3005 struct igb_ring *tx_ring, struct sk_buff *skb,
3006 unsigned int first)
9d5c8243
AK		 3007{
3008 struct igb_buffer *buffer_info;
3009 unsigned int len = skb_headlen(skb);
3010 unsigned int count = 0, i;
3011 unsigned int f;
3012
3013 i = tx_ring->next_to_use;
3014
3015 buffer_info = &tx_ring->buffer_info[i];
3016 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3017 buffer_info->length = len;
3018 /* set time_stamp *before* dma to help avoid a possible race */
3019 buffer_info->time_stamp = jiffies;
0e014cb1 3020 buffer_info->next_to_watch = i;
9d5c8243
AK		 3021 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3022 PCI_DMA_TODEVICE);
3023 count++;
3024 i++;
3025 if (i == tx_ring->count)
3026 i = 0;
3027
3028 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3029 struct skb_frag_struct *frag;
3030
3031 frag = &skb_shinfo(skb)->frags[f];
3032 len = frag->size;
3033
3034 buffer_info = &tx_ring->buffer_info[i];
3035 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3036 buffer_info->length = len;
3037 buffer_info->time_stamp = jiffies;
0e014cb1 3038 buffer_info->next_to_watch = i;
9d5c8243
AK		 3039 buffer_info->dma = pci_map_page(adapter->pdev,
3040 frag->page,
3041 frag->page_offset,
3042 len,
3043 PCI_DMA_TODEVICE);
3044
3045 count++;
3046 i++;
3047 if (i == tx_ring->count)
3048 i = 0;
3049 }
3050
0e014cb1 3051 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 3052 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3053 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 3054
3055 return count;
3056}
3057
3058static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3059 struct igb_ring *tx_ring,
3060 int tx_flags, int count, u32 paylen,
3061 u8 hdr_len)
3062{
3063 union e1000_adv_tx_desc *tx_desc = NULL;
3064 struct igb_buffer *buffer_info;
3065 u32 olinfo_status = 0, cmd_type_len;
3066 unsigned int i;
3067
3068 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3069 E1000_ADVTXD_DCMD_DEXT);
3070
3071 if (tx_flags & IGB_TX_FLAGS_VLAN)
3072 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3073
33af6bcc
PO		 3074 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3075 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3076
9d5c8243
AK		 3077 if (tx_flags & IGB_TX_FLAGS_TSO) {
3078 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3079
3080 /* insert tcp checksum */
3081 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3082
3083 /* insert ip checksum */
3084 if (tx_flags & IGB_TX_FLAGS_IPV4)
3085 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3086
3087 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3088 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3089 }
3090
7dfc16fa
AD		 3091 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3092 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3093 IGB_TX_FLAGS_VLAN)))
661086df 3094 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3095
3096 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3097
3098 i = tx_ring->next_to_use;
3099 while (count--) {
3100 buffer_info = &tx_ring->buffer_info[i];
3101 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3102 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3103 tx_desc->read.cmd_type_len =
3104 cpu_to_le32(cmd_type_len | buffer_info->length);
3105 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3106 i++;
3107 if (i == tx_ring->count)
3108 i = 0;
3109 }
3110
3111 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3112 /* Force memory writes to complete before letting h/w
3113 * know there are new descriptors to fetch. (Only
3114 * applicable for weak-ordered memory model archs,
3115 * such as IA-64). */
3116 wmb();
3117
3118 tx_ring->next_to_use = i;
3119 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3120 /* we need this if more than one processor can write to our tail
3121 * at a time, it syncronizes IO on IA64/Altix systems */
3122 mmiowb();
3123}
3124
3125static int __igb_maybe_stop_tx(struct net_device *netdev,
3126 struct igb_ring *tx_ring, int size)
3127{
3128 struct igb_adapter *adapter = netdev_priv(netdev);
3129
661086df 3130 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3131
9d5c8243
AK		 3132 /* Herbert's original patch had:
3133 * smp_mb__after_netif_stop_queue();
3134 * but since that doesn't exist yet, just open code it. */
3135 smp_mb();
3136
3137 /* We need to check again in a case another CPU has just
3138 * made room available. */
3139 if (IGB_DESC_UNUSED(tx_ring) < size)
3140 return -EBUSY;
3141
3142 /* A reprieve! */
661086df 3143 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3144 ++adapter->restart_queue;
3145 return 0;
3146}
3147
3148static int igb_maybe_stop_tx(struct net_device *netdev,
3149 struct igb_ring *tx_ring, int size)
3150{
3151 if (IGB_DESC_UNUSED(tx_ring) >= size)
3152 return 0;
3153 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3154}
3155
9d5c8243
AK		 3156static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3157 struct net_device *netdev,
3158 struct igb_ring *tx_ring)
3159{
3160 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3161 unsigned int first;
9d5c8243 3162 unsigned int tx_flags = 0;
9d5c8243
AK		 3163 u8 hdr_len = 0;
3164 int tso = 0;
33af6bcc 3165 union skb_shared_tx *shtx;
9d5c8243 3166
9d5c8243
AK		 3167 if (test_bit(__IGB_DOWN, &adapter->state)) {
3168 dev_kfree_skb_any(skb);
3169 return NETDEV_TX_OK;
3170 }
3171
3172 if (skb->len <= 0) {
3173 dev_kfree_skb_any(skb);
3174 return NETDEV_TX_OK;
3175 }
3176
9d5c8243
AK		 3177 /* need: 1 descriptor per page,
3178 * + 2 desc gap to keep tail from touching head,
3179 * + 1 desc for skb->data,
3180 * + 1 desc for context descriptor,
3181 * otherwise try next time */
3182 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3183 /* this is a hard error */
9d5c8243
AK		 3184 return NETDEV_TX_BUSY;
3185 }
33af6bcc
PO		 3186
3187 /*
3188 * TODO: check that there currently is no other packet with
3189 * time stamping in the queue
3190 *
3191 * When doing time stamping, keep the connection to the socket
3192 * a while longer: it is still needed by skb_hwtstamp_tx(),
3193 * called either in igb_tx_hwtstamp() or by our caller when
3194 * doing software time stamping.
3195 */
3196 shtx = skb_tx(skb);
3197 if (unlikely(shtx->hardware)) {
3198 shtx->in_progress = 1;
3199 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3200 } else if (likely(!shtx->software)) {
3201 /*
3202 * TODO: can this be solved in dev.c:dev_hard_start_xmit()?
3203 * There are probably unmodified driver which do something
3204 * like this and thus don't work in combination with
3205 * SOF_TIMESTAMPING_TX_SOFTWARE.
3206 */
3207 skb_orphan(skb);
3208 }
9d5c8243
AK		 3209
3210 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3211 tx_flags |= IGB_TX_FLAGS_VLAN;
3212 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3213 }
3214
661086df
PWJ		 3215 if (skb->protocol == htons(ETH_P_IP))
3216 tx_flags |= IGB_TX_FLAGS_IPV4;
3217
0e014cb1 3218 first = tx_ring->next_to_use;
9d5c8243
AK		 3219 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3220 &hdr_len) : 0;
3221
3222 if (tso < 0) {
3223 dev_kfree_skb_any(skb);
9d5c8243
AK		 3224 return NETDEV_TX_OK;
3225 }
3226
3227 if (tso)
3228 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3229 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3230 (skb->ip_summed == CHECKSUM_PARTIAL))
3231 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3232
9d5c8243 3233 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3234 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3235 skb->len, hdr_len);
3236
3237 netdev->trans_start = jiffies;
3238
3239 /* Make sure there is space in the ring for the next send. */
3240 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3241
9d5c8243
AK		 3242 return NETDEV_TX_OK;
3243}
3244
3245static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3246{
3247 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3248 struct igb_ring *tx_ring;
3249
661086df 3250 int r_idx = 0;
1bfaf07b 3251 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3252 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3253
3254 /* This goes back to the question of how to logically map a tx queue
3255 * to a flow. Right now, performance is impacted slightly negatively
3256 * if using multiple tx queues. If the stack breaks away from a
3257 * single qdisc implementation, we can look at this again. */
3258 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3259}
3260
3261/**
3262 * igb_tx_timeout - Respond to a Tx Hang
3263 * @netdev: network interface device structure
3264 **/
3265static void igb_tx_timeout(struct net_device *netdev)
3266{
3267 struct igb_adapter *adapter = netdev_priv(netdev);
3268 struct e1000_hw *hw = &adapter->hw;
3269
3270 /* Do the reset outside of interrupt context */
3271 adapter->tx_timeout_count++;
3272 schedule_work(&adapter->reset_task);
265de409
AD		 3273 wr32(E1000_EICS,
3274 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3275}
3276
3277static void igb_reset_task(struct work_struct *work)
3278{
3279 struct igb_adapter *adapter;
3280 adapter = container_of(work, struct igb_adapter, reset_task);
3281
3282 igb_reinit_locked(adapter);
3283}
3284
3285/**
3286 * igb_get_stats - Get System Network Statistics
3287 * @netdev: network interface device structure
3288 *
3289 * Returns the address of the device statistics structure.
3290 * The statistics are actually updated from the timer callback.
3291 **/
73cd78f1 3292static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3293{
3294 struct igb_adapter *adapter = netdev_priv(netdev);
3295
3296 /* only return the current stats */
3297 return &adapter->net_stats;
3298}
3299
3300/**
3301 * igb_change_mtu - Change the Maximum Transfer Unit
3302 * @netdev: network interface device structure
3303 * @new_mtu: new value for maximum frame size
3304 *
3305 * Returns 0 on success, negative on failure
3306 **/
3307static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3308{
3309 struct igb_adapter *adapter = netdev_priv(netdev);
3310 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3311
3312 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3313 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3314 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3315 return -EINVAL;
3316 }
3317
9d5c8243
AK		 3318 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3319 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3320 return -EINVAL;
3321 }
3322
3323 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3324 msleep(1);
73cd78f1 3325
9d5c8243
AK		 3326 /* igb_down has a dependency on max_frame_size */
3327 adapter->max_frame_size = max_frame;
3328 if (netif_running(netdev))
3329 igb_down(adapter);
3330
3331 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3332 * means we reserve 2 more, this pushes us to allocate from the next
3333 * larger slab size.
3334 * i.e. RXBUFFER_2048 --> size-4096 slab
3335 */
3336
3337 if (max_frame <= IGB_RXBUFFER_256)
3338 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3339 else if (max_frame <= IGB_RXBUFFER_512)
3340 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3341 else if (max_frame <= IGB_RXBUFFER_1024)
3342 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3343 else if (max_frame <= IGB_RXBUFFER_2048)
3344 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3345 else
bf36c1a0
AD		 3346#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3347 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3348#else
3349 adapter->rx_buffer_len = PAGE_SIZE / 2;
3350#endif
e1739522
AD		 3351
3352 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3353 if (adapter->vfs_allocated_count &&
3354 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3355 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3356
9d5c8243
AK		 3357 /* adjust allocation if LPE protects us, and we aren't using SBP */
3358 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3359 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3360 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3361
3362 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3363 netdev->mtu, new_mtu);
3364 netdev->mtu = new_mtu;
3365
3366 if (netif_running(netdev))
3367 igb_up(adapter);
3368 else
3369 igb_reset(adapter);
3370
3371 clear_bit(__IGB_RESETTING, &adapter->state);
3372
3373 return 0;
3374}
3375
3376/**
3377 * igb_update_stats - Update the board statistics counters
3378 * @adapter: board private structure
3379 **/
3380
3381void igb_update_stats(struct igb_adapter *adapter)
3382{
3383 struct e1000_hw *hw = &adapter->hw;
3384 struct pci_dev *pdev = adapter->pdev;
3385 u16 phy_tmp;
3386
3387#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3388
3389 /*
3390 * Prevent stats update while adapter is being reset, or if the pci
3391 * connection is down.
3392 */
3393 if (adapter->link_speed == 0)
3394 return;
3395 if (pci_channel_offline(pdev))
3396 return;
3397
3398 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3399 adapter->stats.gprc += rd32(E1000_GPRC);
3400 adapter->stats.gorc += rd32(E1000_GORCL);
3401 rd32(E1000_GORCH); /* clear GORCL */
3402 adapter->stats.bprc += rd32(E1000_BPRC);
3403 adapter->stats.mprc += rd32(E1000_MPRC);
3404 adapter->stats.roc += rd32(E1000_ROC);
3405
3406 adapter->stats.prc64 += rd32(E1000_PRC64);
3407 adapter->stats.prc127 += rd32(E1000_PRC127);
3408 adapter->stats.prc255 += rd32(E1000_PRC255);
3409 adapter->stats.prc511 += rd32(E1000_PRC511);
3410 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3411 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3412 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3413 adapter->stats.sec += rd32(E1000_SEC);
3414
3415 adapter->stats.mpc += rd32(E1000_MPC);
3416 adapter->stats.scc += rd32(E1000_SCC);
3417 adapter->stats.ecol += rd32(E1000_ECOL);
3418 adapter->stats.mcc += rd32(E1000_MCC);
3419 adapter->stats.latecol += rd32(E1000_LATECOL);
3420 adapter->stats.dc += rd32(E1000_DC);
3421 adapter->stats.rlec += rd32(E1000_RLEC);
3422 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3423 adapter->stats.xontxc += rd32(E1000_XONTXC);
3424 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3425 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3426 adapter->stats.fcruc += rd32(E1000_FCRUC);
3427 adapter->stats.gptc += rd32(E1000_GPTC);
3428 adapter->stats.gotc += rd32(E1000_GOTCL);
3429 rd32(E1000_GOTCH); /* clear GOTCL */
3430 adapter->stats.rnbc += rd32(E1000_RNBC);
3431 adapter->stats.ruc += rd32(E1000_RUC);
3432 adapter->stats.rfc += rd32(E1000_RFC);
3433 adapter->stats.rjc += rd32(E1000_RJC);
3434 adapter->stats.tor += rd32(E1000_TORH);
3435 adapter->stats.tot += rd32(E1000_TOTH);
3436 adapter->stats.tpr += rd32(E1000_TPR);
3437
3438 adapter->stats.ptc64 += rd32(E1000_PTC64);
3439 adapter->stats.ptc127 += rd32(E1000_PTC127);
3440 adapter->stats.ptc255 += rd32(E1000_PTC255);
3441 adapter->stats.ptc511 += rd32(E1000_PTC511);
3442 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3443 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3444
3445 adapter->stats.mptc += rd32(E1000_MPTC);
3446 adapter->stats.bptc += rd32(E1000_BPTC);
3447
3448 /* used for adaptive IFS */
3449
3450 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3451 adapter->stats.tpt += hw->mac.tx_packet_delta;
3452 hw->mac.collision_delta = rd32(E1000_COLC);
3453 adapter->stats.colc += hw->mac.collision_delta;
3454
3455 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3456 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3457 adapter->stats.tncrs += rd32(E1000_TNCRS);
3458 adapter->stats.tsctc += rd32(E1000_TSCTC);
3459 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3460
3461 adapter->stats.iac += rd32(E1000_IAC);
3462 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3463 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3464 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3465 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3466 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3467 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3468 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3469 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3470
3471 /* Fill out the OS statistics structure */
3472 adapter->net_stats.multicast = adapter->stats.mprc;
3473 adapter->net_stats.collisions = adapter->stats.colc;
3474
3475 /* Rx Errors */
3476
3477 /* RLEC on some newer hardware can be incorrect so build
3478 * our own version based on RUC and ROC */
3479 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3480 adapter->stats.crcerrs + adapter->stats.algnerrc +
3481 adapter->stats.ruc + adapter->stats.roc +
3482 adapter->stats.cexterr;
3483 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3484 adapter->stats.roc;
3485 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3486 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3487 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3488
3489 /* Tx Errors */
3490 adapter->net_stats.tx_errors = adapter->stats.ecol +
3491 adapter->stats.latecol;
3492 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3493 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3494 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3495
3496 /* Tx Dropped needs to be maintained elsewhere */
3497
3498 /* Phy Stats */
3499 if (hw->phy.media_type == e1000_media_type_copper) {
3500 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3501 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3502 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3503 adapter->phy_stats.idle_errors += phy_tmp;
3504 }
3505 }
3506
3507 /* Management Stats */
3508 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3509 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3510 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3511}
3512
9d5c8243
AK		 3513static irqreturn_t igb_msix_other(int irq, void *data)
3514{
3515 struct net_device *netdev = data;
3516 struct igb_adapter *adapter = netdev_priv(netdev);
3517 struct e1000_hw *hw = &adapter->hw;
844290e5 3518 u32 icr = rd32(E1000_ICR);
9d5c8243 3519
844290e5 3520 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3521
3522 if(icr & E1000_ICR_DOUTSYNC) {
3523 /* HW is reporting DMA is out of sync */
3524 adapter->stats.doosync++;
3525 }
844290e5
PW		 3526 if (!(icr & E1000_ICR_LSC))
3527 goto no_link_interrupt;
3528 hw->mac.get_link_status = 1;
3529 /* guard against interrupt when we're going down */
3530 if (!test_bit(__IGB_DOWN, &adapter->state))
3531 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3532
9d5c8243 3533no_link_interrupt:
dda0e083 3534 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3535 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3536
3537 return IRQ_HANDLED;
3538}
3539
3540static irqreturn_t igb_msix_tx(int irq, void *data)
3541{
3542 struct igb_ring *tx_ring = data;
3543 struct igb_adapter *adapter = tx_ring->adapter;
3544 struct e1000_hw *hw = &adapter->hw;
3545
421e02f0 3546#ifdef CONFIG_IGB_DCA
7dfc16fa 3547 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3548 igb_update_tx_dca(tx_ring);
3549#endif
73cd78f1 3550
9d5c8243
AK		 3551 tx_ring->total_bytes = 0;
3552 tx_ring->total_packets = 0;
661086df
PWJ		 3553
3554 /* auto mask will automatically reenable the interrupt when we write
3555 * EICS */
3b644cf6 3556 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3557 /* Ring was not completely cleaned, so fire another interrupt */
3558 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3559 else
9d5c8243 3560 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3561
9d5c8243
AK		 3562 return IRQ_HANDLED;
3563}
3564
6eb5a7f1
AD		 3565static void igb_write_itr(struct igb_ring *ring)
3566{
3567 struct e1000_hw *hw = &ring->adapter->hw;
3568 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3569 switch (hw->mac.type) {
3570 case e1000_82576:
73cd78f1 3571 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3572 0x80000000);
3573 break;
3574 default:
73cd78f1 3575 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3576 (ring->itr_val << 16));
3577 break;
3578 }
3579 ring->set_itr = 0;
3580 }
3581}
3582
9d5c8243
AK		 3583static irqreturn_t igb_msix_rx(int irq, void *data)
3584{
3585 struct igb_ring *rx_ring = data;
9d5c8243 3586
844290e5
PW		 3587 /* Write the ITR value calculated at the end of the
3588 * previous interrupt.
3589 */
9d5c8243 3590
6eb5a7f1 3591 igb_write_itr(rx_ring);
9d5c8243 3592
288379f0
BH		 3593 if (napi_schedule_prep(&rx_ring->napi))
3594 __napi_schedule(&rx_ring->napi);
844290e5 3595
421e02f0 3596#ifdef CONFIG_IGB_DCA
8d253320 3597 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3598 igb_update_rx_dca(rx_ring);
3599#endif
3600 return IRQ_HANDLED;
3601}
3602
421e02f0 3603#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3604static void igb_update_rx_dca(struct igb_ring *rx_ring)
3605{
3606 u32 dca_rxctrl;
3607 struct igb_adapter *adapter = rx_ring->adapter;
3608 struct e1000_hw *hw = &adapter->hw;
3609 int cpu = get_cpu();
26bc19ec 3610 int q = rx_ring->reg_idx;
fe4506b6
JC		 3611
3612 if (rx_ring->cpu != cpu) {
3613 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3614 if (hw->mac.type == e1000_82576) {
3615 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3616 dca_rxctrl |= dca_get_tag(cpu) <<
3617 E1000_DCA_RXCTRL_CPUID_SHIFT;
3618 } else {
3619 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3620 dca_rxctrl |= dca_get_tag(cpu);
3621 }
fe4506b6
JC		 3622 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3623 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3624 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3625 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3626 rx_ring->cpu = cpu;
3627 }
3628 put_cpu();
3629}
3630
3631static void igb_update_tx_dca(struct igb_ring *tx_ring)
3632{
3633 u32 dca_txctrl;
3634 struct igb_adapter *adapter = tx_ring->adapter;
3635 struct e1000_hw *hw = &adapter->hw;
3636 int cpu = get_cpu();
26bc19ec 3637 int q = tx_ring->reg_idx;
fe4506b6
JC		 3638
3639 if (tx_ring->cpu != cpu) {
3640 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3641 if (hw->mac.type == e1000_82576) {
3642 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3643 dca_txctrl |= dca_get_tag(cpu) <<
3644 E1000_DCA_TXCTRL_CPUID_SHIFT;
3645 } else {
3646 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3647 dca_txctrl |= dca_get_tag(cpu);
3648 }
fe4506b6
JC		 3649 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3650 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3651 tx_ring->cpu = cpu;
3652 }
3653 put_cpu();
3654}
3655
3656static void igb_setup_dca(struct igb_adapter *adapter)
3657{
3658 int i;
3659
7dfc16fa 3660 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3661 return;
3662
3663 for (i = 0; i < adapter->num_tx_queues; i++) {
3664 adapter->tx_ring[i].cpu = -1;
3665 igb_update_tx_dca(&adapter->tx_ring[i]);
3666 }
3667 for (i = 0; i < adapter->num_rx_queues; i++) {
3668 adapter->rx_ring[i].cpu = -1;
3669 igb_update_rx_dca(&adapter->rx_ring[i]);
3670 }
3671}
3672
3673static int __igb_notify_dca(struct device *dev, void *data)
3674{
3675 struct net_device *netdev = dev_get_drvdata(dev);
3676 struct igb_adapter *adapter = netdev_priv(netdev);
3677 struct e1000_hw *hw = &adapter->hw;
3678 unsigned long event = *(unsigned long *)data;
3679
3680 switch (event) {
3681 case DCA_PROVIDER_ADD:
3682 /* if already enabled, don't do it again */
7dfc16fa 3683 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3684 break;
fe4506b6
JC		 3685 /* Always use CB2 mode, difference is masked
3686 * in the CB driver. */
cbd347ad 3687 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3688 if (dca_add_requester(dev) == 0) {
bbd98fe4 3689 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3690 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3691 igb_setup_dca(adapter);
3692 break;
3693 }
3694 /* Fall Through since DCA is disabled. */
3695 case DCA_PROVIDER_REMOVE:
7dfc16fa 3696 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3697 /* without this a class_device is left
3698 * hanging around in the sysfs model */
3699 dca_remove_requester(dev);
3700 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3701 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3702 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3703 }
3704 break;
3705 }
bbd98fe4 3706
fe4506b6 3707 return 0;
9d5c8243
AK		 3708}
3709
fe4506b6
JC		 3710static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3711 void *p)
3712{
3713 int ret_val;
3714
3715 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3716 __igb_notify_dca);
3717
3718 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3719}
421e02f0 3720#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3721
3722/**
3723 * igb_intr_msi - Interrupt Handler
3724 * @irq: interrupt number
3725 * @data: pointer to a network interface device structure
3726 **/
3727static irqreturn_t igb_intr_msi(int irq, void *data)
3728{
3729 struct net_device *netdev = data;
3730 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3731 struct e1000_hw *hw = &adapter->hw;
3732 /* read ICR disables interrupts using IAM */
3733 u32 icr = rd32(E1000_ICR);
3734
6eb5a7f1 3735 igb_write_itr(adapter->rx_ring);
9d5c8243 3736
dda0e083
AD		 3737 if(icr & E1000_ICR_DOUTSYNC) {
3738 /* HW is reporting DMA is out of sync */
3739 adapter->stats.doosync++;
3740 }
3741
9d5c8243
AK		 3742 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3743 hw->mac.get_link_status = 1;
3744 if (!test_bit(__IGB_DOWN, &adapter->state))
3745 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3746 }
3747
288379f0 3748 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3749
3750 return IRQ_HANDLED;
3751}
3752
3753/**
4a3c6433 3754 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3755 * @irq: interrupt number
3756 * @data: pointer to a network interface device structure
3757 **/
3758static irqreturn_t igb_intr(int irq, void *data)
3759{
3760 struct net_device *netdev = data;
3761 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3762 struct e1000_hw *hw = &adapter->hw;
3763 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3764 * need for the IMC write */
3765 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3766 if (!icr)
3767 return IRQ_NONE; /* Not our interrupt */
3768
6eb5a7f1 3769 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3770
3771 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3772 * not set, then the adapter didn't send an interrupt */
3773 if (!(icr & E1000_ICR_INT_ASSERTED))
3774 return IRQ_NONE;
3775
dda0e083
AD		 3776 if(icr & E1000_ICR_DOUTSYNC) {
3777 /* HW is reporting DMA is out of sync */
3778 adapter->stats.doosync++;
3779 }
3780
9d5c8243
AK		 3781 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3782 hw->mac.get_link_status = 1;
3783 /* guard against interrupt when we're going down */
3784 if (!test_bit(__IGB_DOWN, &adapter->state))
3785 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3786 }
3787
288379f0 3788 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3789
3790 return IRQ_HANDLED;
3791}
3792
46544258 3793static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 3794{
661086df 3795 struct igb_adapter *adapter = rx_ring->adapter;
46544258 3796 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3797
46544258
AD		 3798 if (adapter->itr_setting & 3) {
3799 if (adapter->num_rx_queues == 1)
6eb5a7f1 3800 igb_set_itr(adapter);
46544258
AD		 3801 else
3802 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 3803 }
3804
46544258
AD		 3805 if (!test_bit(__IGB_DOWN, &adapter->state)) {
3806 if (adapter->msix_entries)
3807 wr32(E1000_EIMS, rx_ring->eims_value);
3808 else
3809 igb_irq_enable(adapter);
3810 }
9d5c8243
AK		 3811}
3812
46544258
AD		 3813/**
3814 * igb_poll - NAPI Rx polling callback
3815 * @napi: napi polling structure
3816 * @budget: count of how many packets we should handle
3817 **/
3818static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 3819{
3820 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3821 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3822 struct net_device *netdev = adapter->netdev;
3823 int work_done = 0;
3824
421e02f0 3825#ifdef CONFIG_IGB_DCA
7dfc16fa 3826 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3827 igb_update_rx_dca(rx_ring);
3828#endif
3b644cf6 3829 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 3830
46544258
AD		 3831 if (rx_ring->buddy) {
3832#ifdef CONFIG_IGB_DCA
3833 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3834 igb_update_tx_dca(rx_ring->buddy);
3835#endif
3836 if (!igb_clean_tx_irq(rx_ring->buddy))
3837 work_done = budget;
3838 }
3839
9d5c8243 3840 /* If not enough Rx work done, exit the polling mode */
46544258 3841 if ((work_done < budget) || !netif_running(netdev)) {
288379f0 3842 napi_complete(napi);
46544258 3843 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 3844 }
3845
46544258 3846 return work_done;
9d5c8243 3847}
6d8126f9 3848
33af6bcc
PO		 3849/**
3850 * igb_hwtstamp - utility function which checks for TX time stamp
3851 * @adapter: board private structure
3852 * @skb: packet that was just sent
3853 *
3854 * If we were asked to do hardware stamping and such a time stamp is
3855 * available, then it must have been for this skb here because we only
3856 * allow only one such packet into the queue.
3857 */
3858static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
3859{
3860 union skb_shared_tx *shtx = skb_tx(skb);
3861 struct e1000_hw *hw = &adapter->hw;
3862
3863 if (unlikely(shtx->hardware)) {
3864 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
3865 if (valid) {
3866 u64 regval = rd32(E1000_TXSTMPL);
3867 u64 ns;
3868 struct skb_shared_hwtstamps shhwtstamps;
3869
3870 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3871 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
3872 ns = timecounter_cyc2time(&adapter->clock,
3873 regval);
3874 timecompare_update(&adapter->compare, ns);
3875 shhwtstamps.hwtstamp = ns_to_ktime(ns);
3876 shhwtstamps.syststamp =
3877 timecompare_transform(&adapter->compare, ns);
3878 skb_tstamp_tx(skb, &shhwtstamps);
3879 }
3880
3881 /* delayed orphaning: skb_tstamp_tx() needs the socket */
3882 skb_orphan(skb);
3883 }
3884}
3885
9d5c8243
AK		 3886/**
3887 * igb_clean_tx_irq - Reclaim resources after transmit completes
3888 * @adapter: board private structure
3889 * returns true if ring is completely cleaned
3890 **/
3b644cf6 3891static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3892{
3b644cf6 3893 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3894 struct net_device *netdev = adapter->netdev;
0e014cb1 3895 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3896 struct igb_buffer *buffer_info;
3897 struct sk_buff *skb;
0e014cb1 3898 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3899 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3900 unsigned int i, eop, count = 0;
3901 bool cleaned = false;
9d5c8243 3902
9d5c8243 3903 i = tx_ring->next_to_clean;
0e014cb1
AD		 3904 eop = tx_ring->buffer_info[i].next_to_watch;
3905 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3906
3907 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3908 (count < tx_ring->count)) {
3909 for (cleaned = false; !cleaned; count++) {
3910 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3911 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3912 cleaned = (i == eop);
9d5c8243
AK		 3913 skb = buffer_info->skb;
3914
3915 if (skb) {
3916 unsigned int segs, bytecount;
3917 /* gso_segs is currently only valid for tcp */
3918 segs = skb_shinfo(skb)->gso_segs ?: 1;
3919 /* multiply data chunks by size of headers */
3920 bytecount = ((segs - 1) * skb_headlen(skb)) +
3921 skb->len;
3922 total_packets += segs;
3923 total_bytes += bytecount;
33af6bcc
PO		 3924
3925 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 3926 }
3927
3928 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3929 tx_desc->wb.status = 0;
9d5c8243
AK		 3930
3931 i++;
3932 if (i == tx_ring->count)
3933 i = 0;
9d5c8243 3934 }
0e014cb1
AD		 3935 eop = tx_ring->buffer_info[i].next_to_watch;
3936 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3937 }
3938
9d5c8243
AK		 3939 tx_ring->next_to_clean = i;
3940
fc7d345d 3941 if (unlikely(count &&
9d5c8243
AK		 3942 netif_carrier_ok(netdev) &&
3943 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3944 /* Make sure that anybody stopping the queue after this
3945 * sees the new next_to_clean.
3946 */
3947 smp_mb();
661086df
PWJ		 3948 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3949 !(test_bit(__IGB_DOWN, &adapter->state))) {
3950 netif_wake_subqueue(netdev, tx_ring->queue_index);
3951 ++adapter->restart_queue;
3952 }
9d5c8243
AK		 3953 }
3954
3955 if (tx_ring->detect_tx_hung) {
3956 /* Detect a transmit hang in hardware, this serializes the
3957 * check with the clearing of time_stamp and movement of i */
3958 tx_ring->detect_tx_hung = false;
3959 if (tx_ring->buffer_info[i].time_stamp &&
3960 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3961 (adapter->tx_timeout_factor * HZ))
3962 && !(rd32(E1000_STATUS) &
3963 E1000_STATUS_TXOFF)) {
3964
9d5c8243
AK		 3965 /* detected Tx unit hang */
3966 dev_err(&adapter->pdev->dev,
3967 "Detected Tx Unit Hang\n"
2d064c06 3968 " Tx Queue <%d>\n"
9d5c8243
AK		 3969 " TDH <%x>\n"
3970 " TDT <%x>\n"
3971 " next_to_use <%x>\n"
3972 " next_to_clean <%x>\n"
9d5c8243
AK		 3973 "buffer_info[next_to_clean]\n"
3974 " time_stamp <%lx>\n"
0e014cb1 3975 " next_to_watch <%x>\n"
9d5c8243
AK		 3976 " jiffies <%lx>\n"
3977 " desc.status <%x>\n",
2d064c06 3978 tx_ring->queue_index,
9d5c8243
AK		 3979 readl(adapter->hw.hw_addr + tx_ring->head),
3980 readl(adapter->hw.hw_addr + tx_ring->tail),
3981 tx_ring->next_to_use,
3982 tx_ring->next_to_clean,
9d5c8243 3983 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3984 eop,
9d5c8243 3985 jiffies,
0e014cb1 3986 eop_desc->wb.status);
661086df 3987 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3988 }
3989 }
3990 tx_ring->total_bytes += total_bytes;
3991 tx_ring->total_packets += total_packets;
e21ed353
AD		 3992 tx_ring->tx_stats.bytes += total_bytes;
3993 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3994 adapter->net_stats.tx_bytes += total_bytes;
3995 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3996 return (count < tx_ring->count);
9d5c8243
AK		 3997}
3998
9d5c8243
AK		 3999/**
4000 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4001 * @ring: pointer to receive ring receving this packet
9d5c8243 4002 * @status: descriptor status field as written by hardware
73cd78f1 4003 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4004 * @skb: pointer to sk_buff to be indicated to stack
4005 **/
d3352520
AD		 4006static void igb_receive_skb(struct igb_ring *ring, u8 status,
4007 union e1000_adv_rx_desc * rx_desc,
4008 struct sk_buff *skb)
4009{
4010 struct igb_adapter * adapter = ring->adapter;
4011 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4012
0c8dfc83 4013 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 4014 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 4015 if (vlan_extracted)
5c0999b7
HX		 4016 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4017 le16_to_cpu(rx_desc->wb.upper.vlan),
4018 skb);
d3352520 4019 else
5c0999b7 4020 napi_gro_receive(&ring->napi, skb);
d3352520 4021 } else {
d3352520
AD		 4022 if (vlan_extracted)
4023 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4024 le16_to_cpu(rx_desc->wb.upper.vlan));
4025 else
d3352520 4026 netif_receive_skb(skb);
d3352520 4027 }
9d5c8243
AK		 4028}
4029
9d5c8243
AK		 4030static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4031 u32 status_err, struct sk_buff *skb)
4032{
4033 skb->ip_summed = CHECKSUM_NONE;
4034
4035 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4036 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4037 return;
4038 /* TCP/UDP checksum error bit is set */
4039 if (status_err &
4040 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4041 /* let the stack verify checksum errors */
4042 adapter->hw_csum_err++;
4043 return;
4044 }
4045 /* It must be a TCP or UDP packet with a valid checksum */
4046 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4047 skb->ip_summed = CHECKSUM_UNNECESSARY;
4048
4049 adapter->hw_csum_good++;
4050}
4051
3b644cf6
MW		 4052static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4053 int *work_done, int budget)
9d5c8243 4054{
3b644cf6 4055 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4056 struct net_device *netdev = adapter->netdev;
33af6bcc 4057 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4058 struct pci_dev *pdev = adapter->pdev;
4059 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4060 struct igb_buffer *buffer_info , *next_buffer;
4061 struct sk_buff *skb;
9d5c8243
AK		 4062 bool cleaned = false;
4063 int cleaned_count = 0;
4064 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 4065 unsigned int i;
4066 u32 length, hlen, staterr;
9d5c8243
AK		 4067
4068 i = rx_ring->next_to_clean;
69d3ca53 4069 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4070 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4071 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4072
4073 while (staterr & E1000_RXD_STAT_DD) {
4074 if (*work_done >= budget)
4075 break;
4076 (*work_done)++;
9d5c8243 4077
69d3ca53
AD		 4078 skb = buffer_info->skb;
4079 prefetch(skb->data - NET_IP_ALIGN);
4080 buffer_info->skb = NULL;
4081
4082 i++;
4083 if (i == rx_ring->count)
4084 i = 0;
4085 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4086 prefetch(next_rxd);
4087 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4088
4089 length = le16_to_cpu(rx_desc->wb.upper.length);
4090 cleaned = true;
4091 cleaned_count++;
4092
bf36c1a0
AD		 4093 if (!adapter->rx_ps_hdr_size) {
4094 pci_unmap_single(pdev, buffer_info->dma,
4095 adapter->rx_buffer_len +
4096 NET_IP_ALIGN,
4097 PCI_DMA_FROMDEVICE);
4098 skb_put(skb, length);
4099 goto send_up;
9d5c8243
AK		 4100 }
4101
69d3ca53
AD		 4102 /* HW will not DMA in data larger than the given buffer, even
4103 * if it parses the (NFS, of course) header to be larger. In
4104 * that case, it fills the header buffer and spills the rest
4105 * into the page.
4106 */
4107 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4108 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4109 if (hlen > adapter->rx_ps_hdr_size)
4110 hlen = adapter->rx_ps_hdr_size;
4111
bf36c1a0
AD		 4112 if (!skb_shinfo(skb)->nr_frags) {
4113 pci_unmap_single(pdev, buffer_info->dma,
73cd78f1 4114 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
bf36c1a0
AD		 4115 PCI_DMA_FROMDEVICE);
4116 skb_put(skb, hlen);
4117 }
4118
4119 if (length) {
9d5c8243 4120 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4121 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4122 buffer_info->page_dma = 0;
bf36c1a0
AD		 4123
4124 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4125 buffer_info->page,
4126 buffer_info->page_offset,
4127 length);
4128
4129 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4130 (page_count(buffer_info->page) != 1))
4131 buffer_info->page = NULL;
4132 else
4133 get_page(buffer_info->page);
9d5c8243
AK		 4134
4135 skb->len += length;
4136 skb->data_len += length;
9d5c8243 4137
bf36c1a0 4138 skb->truesize += length;
9d5c8243 4139 }
9d5c8243 4140
bf36c1a0 4141 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4142 buffer_info->skb = next_buffer->skb;
4143 buffer_info->dma = next_buffer->dma;
4144 next_buffer->skb = skb;
4145 next_buffer->dma = 0;
bf36c1a0
AD		 4146 goto next_desc;
4147 }
69d3ca53 4148send_up:
33af6bcc
PO		 4149 /*
4150 * If this bit is set, then the RX registers contain
4151 * the time stamp. No other packet will be time
4152 * stamped until we read these registers, so read the
4153 * registers to make them available again. Because
4154 * only one packet can be time stamped at a time, we
4155 * know that the register values must belong to this
4156 * one here and therefore we don't need to compare
4157 * any of the additional attributes stored for it.
4158 *
4159 * If nothing went wrong, then it should have a
4160 * skb_shared_tx that we can turn into a
4161 * skb_shared_hwtstamps.
4162 *
4163 * TODO: can time stamping be triggered (thus locking
4164 * the registers) without the packet reaching this point
4165 * here? In that case RX time stamping would get stuck.
4166 *
4167 * TODO: in "time stamp all packets" mode this bit is
4168 * not set. Need a global flag for this mode and then
4169 * always read the registers. Cannot be done without
4170 * a race condition.
4171 */
4172 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4173 u64 regval;
4174 u64 ns;
4175 struct skb_shared_hwtstamps *shhwtstamps =
4176 skb_hwtstamps(skb);
4177
4178 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4179 "igb: no RX time stamp available for time stamped packet");
4180 regval = rd32(E1000_RXSTMPL);
4181 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4182 ns = timecounter_cyc2time(&adapter->clock, regval);
4183 timecompare_update(&adapter->compare, ns);
4184 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4185 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4186 shhwtstamps->syststamp =
4187 timecompare_transform(&adapter->compare, ns);
4188 }
4189
9d5c8243
AK		 4190 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4191 dev_kfree_skb_irq(skb);
4192 goto next_desc;
4193 }
9d5c8243
AK		 4194
4195 total_bytes += skb->len;
4196 total_packets++;
4197
4198 igb_rx_checksum_adv(adapter, staterr, skb);
4199
4200 skb->protocol = eth_type_trans(skb, netdev);
4201
d3352520 4202 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4203
9d5c8243
AK		 4204next_desc:
4205 rx_desc->wb.upper.status_error = 0;
4206
4207 /* return some buffers to hardware, one at a time is too slow */
4208 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4209 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4210 cleaned_count = 0;
4211 }
4212
4213 /* use prefetched values */
4214 rx_desc = next_rxd;
4215 buffer_info = next_buffer;
9d5c8243
AK		 4216 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4217 }
bf36c1a0 4218
9d5c8243
AK		 4219 rx_ring->next_to_clean = i;
4220 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4221
4222 if (cleaned_count)
3b644cf6 4223 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4224
4225 rx_ring->total_packets += total_packets;
4226 rx_ring->total_bytes += total_bytes;
4227 rx_ring->rx_stats.packets += total_packets;
4228 rx_ring->rx_stats.bytes += total_bytes;
4229 adapter->net_stats.rx_bytes += total_bytes;
4230 adapter->net_stats.rx_packets += total_packets;
4231 return cleaned;
4232}
4233
9d5c8243
AK		 4234/**
4235 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4236 * @adapter: address of board private structure
4237 **/
3b644cf6 4238static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4239 int cleaned_count)
4240{
3b644cf6 4241 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4242 struct net_device *netdev = adapter->netdev;
4243 struct pci_dev *pdev = adapter->pdev;
4244 union e1000_adv_rx_desc *rx_desc;
4245 struct igb_buffer *buffer_info;
4246 struct sk_buff *skb;
4247 unsigned int i;
db761762 4248 int bufsz;
9d5c8243
AK		 4249
4250 i = rx_ring->next_to_use;
4251 buffer_info = &rx_ring->buffer_info[i];
4252
db761762
AD		 4253 if (adapter->rx_ps_hdr_size)
4254 bufsz = adapter->rx_ps_hdr_size;
4255 else
4256 bufsz = adapter->rx_buffer_len;
4257 bufsz += NET_IP_ALIGN;
4258
9d5c8243
AK		 4259 while (cleaned_count--) {
4260 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4261
bf36c1a0 4262 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4263 if (!buffer_info->page) {
bf36c1a0
AD		 4264 buffer_info->page = alloc_page(GFP_ATOMIC);
4265 if (!buffer_info->page) {
4266 adapter->alloc_rx_buff_failed++;
4267 goto no_buffers;
4268 }
4269 buffer_info->page_offset = 0;
4270 } else {
4271 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4272 }
4273 buffer_info->page_dma =
db761762 4274 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4275 buffer_info->page_offset,
4276 PAGE_SIZE / 2,
9d5c8243
AK		 4277 PCI_DMA_FROMDEVICE);
4278 }
4279
4280 if (!buffer_info->skb) {
9d5c8243 4281 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4282 if (!skb) {
4283 adapter->alloc_rx_buff_failed++;
4284 goto no_buffers;
4285 }
4286
4287 /* Make buffer alignment 2 beyond a 16 byte boundary
4288 * this will result in a 16 byte aligned IP header after
4289 * the 14 byte MAC header is removed
4290 */
4291 skb_reserve(skb, NET_IP_ALIGN);
4292
4293 buffer_info->skb = skb;
4294 buffer_info->dma = pci_map_single(pdev, skb->data,
4295 bufsz,
4296 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4297 }
4298 /* Refresh the desc even if buffer_addrs didn't change because
4299 * each write-back erases this info. */
4300 if (adapter->rx_ps_hdr_size) {
4301 rx_desc->read.pkt_addr =
4302 cpu_to_le64(buffer_info->page_dma);
4303 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4304 } else {
4305 rx_desc->read.pkt_addr =
4306 cpu_to_le64(buffer_info->dma);
4307 rx_desc->read.hdr_addr = 0;
4308 }
4309
4310 i++;
4311 if (i == rx_ring->count)
4312 i = 0;
4313 buffer_info = &rx_ring->buffer_info[i];
4314 }
4315
4316no_buffers:
4317 if (rx_ring->next_to_use != i) {
4318 rx_ring->next_to_use = i;
4319 if (i == 0)
4320 i = (rx_ring->count - 1);
4321 else
4322 i--;
4323
4324 /* Force memory writes to complete before letting h/w
4325 * know there are new descriptors to fetch. (Only
4326 * applicable for weak-ordered memory model archs,
4327 * such as IA-64). */
4328 wmb();
4329 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4330 }
4331}
4332
4333/**
4334 * igb_mii_ioctl -
4335 * @netdev:
4336 * @ifreq:
4337 * @cmd:
4338 **/
4339static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4340{
4341 struct igb_adapter *adapter = netdev_priv(netdev);
4342 struct mii_ioctl_data *data = if_mii(ifr);
4343
4344 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4345 return -EOPNOTSUPP;
4346
4347 switch (cmd) {
4348 case SIOCGMIIPHY:
4349 data->phy_id = adapter->hw.phy.addr;
4350 break;
4351 case SIOCGMIIREG:
4352 if (!capable(CAP_NET_ADMIN))
4353 return -EPERM;
f5f4cf08
AD		 4354 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4355 &data->val_out))
9d5c8243
AK		 4356 return -EIO;
4357 break;
4358 case SIOCSMIIREG:
4359 default:
4360 return -EOPNOTSUPP;
4361 }
4362 return 0;
4363}
4364
c6cb090b
PO		 4365/**
4366 * igb_hwtstamp_ioctl - control hardware time stamping
4367 * @netdev:
4368 * @ifreq:
4369 * @cmd:
4370 *
33af6bcc
PO		 4371 * Outgoing time stamping can be enabled and disabled. Play nice and
4372 * disable it when requested, although it shouldn't case any overhead
4373 * when no packet needs it. At most one packet in the queue may be
4374 * marked for time stamping, otherwise it would be impossible to tell
4375 * for sure to which packet the hardware time stamp belongs.
4376 *
4377 * Incoming time stamping has to be configured via the hardware
4378 * filters. Not all combinations are supported, in particular event
4379 * type has to be specified. Matching the kind of event packet is
4380 * not supported, with the exception of "all V2 events regardless of
4381 * level 2 or 4".
4382 *
c6cb090b
PO		 4383 **/
4384static int igb_hwtstamp_ioctl(struct net_device *netdev,
4385 struct ifreq *ifr, int cmd)
4386{
33af6bcc
PO		 4387 struct igb_adapter *adapter = netdev_priv(netdev);
4388 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4389 struct hwtstamp_config config;
33af6bcc
PO		 4390 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4391 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4392 u32 tsync_rx_ctl_type = 0;
4393 u32 tsync_rx_cfg = 0;
4394 int is_l4 = 0;
4395 int is_l2 = 0;
4396 short port = 319; /* PTP */
4397 u32 regval;
c6cb090b
PO		 4398
4399 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4400 return -EFAULT;
4401
4402 /* reserved for future extensions */
4403 if (config.flags)
4404 return -EINVAL;
4405
33af6bcc
PO		 4406 switch (config.tx_type) {
4407 case HWTSTAMP_TX_OFF:
4408 tsync_tx_ctl_bit = 0;
4409 break;
4410 case HWTSTAMP_TX_ON:
4411 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4412 break;
4413 default:
4414 return -ERANGE;
4415 }
4416
4417 switch (config.rx_filter) {
4418 case HWTSTAMP_FILTER_NONE:
4419 tsync_rx_ctl_bit = 0;
4420 break;
4421 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4422 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4423 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4424 case HWTSTAMP_FILTER_ALL:
4425 /*
4426 * register TSYNCRXCFG must be set, therefore it is not
4427 * possible to time stamp both Sync and Delay_Req messages
4428 * => fall back to time stamping all packets
4429 */
4430 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4431 config.rx_filter = HWTSTAMP_FILTER_ALL;
4432 break;
4433 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4434 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4435 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4436 is_l4 = 1;
4437 break;
4438 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4439 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4440 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4441 is_l4 = 1;
4442 break;
4443 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4444 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4445 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4446 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4447 is_l2 = 1;
4448 is_l4 = 1;
4449 config.rx_filter = HWTSTAMP_FILTER_SOME;
4450 break;
4451 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4452 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4453 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4454 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4455 is_l2 = 1;
4456 is_l4 = 1;
4457 config.rx_filter = HWTSTAMP_FILTER_SOME;
4458 break;
4459 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4460 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4461 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4462 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4463 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4464 is_l2 = 1;
4465 break;
4466 default:
4467 return -ERANGE;
4468 }
4469
4470 /* enable/disable TX */
4471 regval = rd32(E1000_TSYNCTXCTL);
4472 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4473 wr32(E1000_TSYNCTXCTL, regval);
4474
4475 /* enable/disable RX, define which PTP packets are time stamped */
4476 regval = rd32(E1000_TSYNCRXCTL);
4477 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4478 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4479 wr32(E1000_TSYNCRXCTL, regval);
4480 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4481
4482 /*
4483 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4484 * (Ethertype to filter on)
4485 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4486 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4487 */
4488 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4489
4490 /* L4 Queue Filter[0]: only filter by source and destination port */
4491 wr32(E1000_SPQF0, htons(port));
4492 wr32(E1000_IMIREXT(0), is_l4 ?
4493 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4494 wr32(E1000_IMIR(0), is_l4 ?
4495 (htons(port)
4496 | (0<<16) /* immediate interrupt disabled */
4497 | 0 /* (1<<17) bit cleared: do not bypass
4498 destination port check */)
4499 : 0);
4500 wr32(E1000_FTQF0, is_l4 ?
4501 (0x11 /* UDP */
4502 | (1<<15) /* VF not compared */
4503 | (1<<27) /* Enable Timestamping */
4504 | (7<<28) /* only source port filter enabled,
4505 source/target address and protocol
4506 masked */)
4507 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4508 enabled */));
4509
4510 wrfl();
4511
4512 adapter->hwtstamp_config = config;
4513
4514 /* clear TX/RX time stamp registers, just to be sure */
4515 regval = rd32(E1000_TXSTMPH);
4516 regval = rd32(E1000_RXSTMPH);
c6cb090b 4517
33af6bcc
PO		 4518 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4519 -EFAULT : 0;
c6cb090b
PO		 4520}
4521
9d5c8243
AK		 4522/**
4523 * igb_ioctl -
4524 * @netdev:
4525 * @ifreq:
4526 * @cmd:
4527 **/
4528static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4529{
4530 switch (cmd) {
4531 case SIOCGMIIPHY:
4532 case SIOCGMIIREG:
4533 case SIOCSMIIREG:
4534 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 4535 case SIOCSHWTSTAMP:
4536 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 4537 default:
4538 return -EOPNOTSUPP;
4539 }
4540}
4541
4542static void igb_vlan_rx_register(struct net_device *netdev,
4543 struct vlan_group *grp)
4544{
4545 struct igb_adapter *adapter = netdev_priv(netdev);
4546 struct e1000_hw *hw = &adapter->hw;
4547 u32 ctrl, rctl;
4548
4549 igb_irq_disable(adapter);
4550 adapter->vlgrp = grp;
4551
4552 if (grp) {
4553 /* enable VLAN tag insert/strip */
4554 ctrl = rd32(E1000_CTRL);
4555 ctrl |= E1000_CTRL_VME;
4556 wr32(E1000_CTRL, ctrl);
4557
4558 /* enable VLAN receive filtering */
4559 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4560 rctl &= ~E1000_RCTL_CFIEN;
4561 wr32(E1000_RCTL, rctl);
4562 igb_update_mng_vlan(adapter);
9d5c8243
AK		 4563 } else {
4564 /* disable VLAN tag insert/strip */
4565 ctrl = rd32(E1000_CTRL);
4566 ctrl &= ~E1000_CTRL_VME;
4567 wr32(E1000_CTRL, ctrl);
4568
9d5c8243
AK		 4569 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4570 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4571 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4572 }
9d5c8243
AK		 4573 }
4574
e1739522
AD		 4575 igb_rlpml_set(adapter);
4576
9d5c8243
AK		 4577 if (!test_bit(__IGB_DOWN, &adapter->state))
4578 igb_irq_enable(adapter);
4579}
4580
4581static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4582{
4583 struct igb_adapter *adapter = netdev_priv(netdev);
4584 struct e1000_hw *hw = &adapter->hw;
4585 u32 vfta, index;
4586
28b0759c 4587 if ((hw->mng_cookie.status &
9d5c8243
AK		 4588 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4589 (vid == adapter->mng_vlan_id))
4590 return;
4591 /* add VID to filter table */
4592 index = (vid >> 5) & 0x7F;
4593 vfta = array_rd32(E1000_VFTA, index);
4594 vfta |= (1 << (vid & 0x1F));
4595 igb_write_vfta(&adapter->hw, index, vfta);
4596}
4597
4598static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4599{
4600 struct igb_adapter *adapter = netdev_priv(netdev);
4601 struct e1000_hw *hw = &adapter->hw;
4602 u32 vfta, index;
4603
4604 igb_irq_disable(adapter);
4605 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4606
4607 if (!test_bit(__IGB_DOWN, &adapter->state))
4608 igb_irq_enable(adapter);
4609
4610 if ((adapter->hw.mng_cookie.status &
4611 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4612 (vid == adapter->mng_vlan_id)) {
4613 /* release control to f/w */
4614 igb_release_hw_control(adapter);
4615 return;
4616 }
4617
4618 /* remove VID from filter table */
4619 index = (vid >> 5) & 0x7F;
4620 vfta = array_rd32(E1000_VFTA, index);
4621 vfta &= ~(1 << (vid & 0x1F));
4622 igb_write_vfta(&adapter->hw, index, vfta);
4623}
4624
4625static void igb_restore_vlan(struct igb_adapter *adapter)
4626{
4627 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4628
4629 if (adapter->vlgrp) {
4630 u16 vid;
4631 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4632 if (!vlan_group_get_device(adapter->vlgrp, vid))
4633 continue;
4634 igb_vlan_rx_add_vid(adapter->netdev, vid);
4635 }
4636 }
4637}
4638
4639int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4640{
4641 struct e1000_mac_info *mac = &adapter->hw.mac;
4642
4643 mac->autoneg = 0;
4644
4645 /* Fiber NICs only allow 1000 gbps Full duplex */
4646 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4647 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4648 dev_err(&adapter->pdev->dev,
4649 "Unsupported Speed/Duplex configuration\n");
4650 return -EINVAL;
4651 }
4652
4653 switch (spddplx) {
4654 case SPEED_10 + DUPLEX_HALF:
4655 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4656 break;
4657 case SPEED_10 + DUPLEX_FULL:
4658 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4659 break;
4660 case SPEED_100 + DUPLEX_HALF:
4661 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4662 break;
4663 case SPEED_100 + DUPLEX_FULL:
4664 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4665 break;
4666 case SPEED_1000 + DUPLEX_FULL:
4667 mac->autoneg = 1;
4668 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4669 break;
4670 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4671 default:
4672 dev_err(&adapter->pdev->dev,
4673 "Unsupported Speed/Duplex configuration\n");
4674 return -EINVAL;
4675 }
4676 return 0;
4677}
4678
9d5c8243
AK		 4679static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4680{
4681 struct net_device *netdev = pci_get_drvdata(pdev);
4682 struct igb_adapter *adapter = netdev_priv(netdev);
4683 struct e1000_hw *hw = &adapter->hw;
2d064c06 4684 u32 ctrl, rctl, status;
9d5c8243
AK		 4685 u32 wufc = adapter->wol;
4686#ifdef CONFIG_PM
4687 int retval = 0;
4688#endif
4689
4690 netif_device_detach(netdev);
4691
a88f10ec
AD		 4692 if (netif_running(netdev))
4693 igb_close(netdev);
4694
4695 igb_reset_interrupt_capability(adapter);
4696
4697 igb_free_queues(adapter);
9d5c8243
AK		 4698
4699#ifdef CONFIG_PM
4700 retval = pci_save_state(pdev);
4701 if (retval)
4702 return retval;
4703#endif
4704
4705 status = rd32(E1000_STATUS);
4706 if (status & E1000_STATUS_LU)
4707 wufc &= ~E1000_WUFC_LNKC;
4708
4709 if (wufc) {
4710 igb_setup_rctl(adapter);
4711 igb_set_multi(netdev);
4712
4713 /* turn on all-multi mode if wake on multicast is enabled */
4714 if (wufc & E1000_WUFC_MC) {
4715 rctl = rd32(E1000_RCTL);
4716 rctl |= E1000_RCTL_MPE;
4717 wr32(E1000_RCTL, rctl);
4718 }
4719
4720 ctrl = rd32(E1000_CTRL);
4721 /* advertise wake from D3Cold */
4722 #define E1000_CTRL_ADVD3WUC 0x00100000
4723 /* phy power management enable */
4724 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4725 ctrl |= E1000_CTRL_ADVD3WUC;
4726 wr32(E1000_CTRL, ctrl);
4727
9d5c8243
AK		 4728 /* Allow time for pending master requests to run */
4729 igb_disable_pcie_master(&adapter->hw);
4730
4731 wr32(E1000_WUC, E1000_WUC_PME_EN);
4732 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4733 } else {
4734 wr32(E1000_WUC, 0);
4735 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4736 }
4737
2d064c06
AD		 4738 /* make sure adapter isn't asleep if manageability/wol is enabled */
4739 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4740 pci_enable_wake(pdev, PCI_D3hot, 1);
4741 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4742 } else {
4743 igb_shutdown_fiber_serdes_link_82575(hw);
4744 pci_enable_wake(pdev, PCI_D3hot, 0);
4745 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4746 }
4747
4748 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4749 * would have already happened in close and is redundant. */
4750 igb_release_hw_control(adapter);
4751
4752 pci_disable_device(pdev);
4753
4754 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4755
4756 return 0;
4757}
4758
4759#ifdef CONFIG_PM
4760static int igb_resume(struct pci_dev *pdev)
4761{
4762 struct net_device *netdev = pci_get_drvdata(pdev);
4763 struct igb_adapter *adapter = netdev_priv(netdev);
4764 struct e1000_hw *hw = &adapter->hw;
4765 u32 err;
4766
4767 pci_set_power_state(pdev, PCI_D0);
4768 pci_restore_state(pdev);
42bfd33a 4769
aed5dec3 4770 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4771 if (err) {
4772 dev_err(&pdev->dev,
4773 "igb: Cannot enable PCI device from suspend\n");
4774 return err;
4775 }
4776 pci_set_master(pdev);
4777
4778 pci_enable_wake(pdev, PCI_D3hot, 0);
4779 pci_enable_wake(pdev, PCI_D3cold, 0);
4780
a88f10ec
AD		 4781 igb_set_interrupt_capability(adapter);
4782
4783 if (igb_alloc_queues(adapter)) {
4784 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4785 return -ENOMEM;
9d5c8243
AK		 4786 }
4787
4788 /* e1000_power_up_phy(adapter); */
4789
4790 igb_reset(adapter);
a8564f03
AD		 4791
4792 /* let the f/w know that the h/w is now under the control of the
4793 * driver. */
4794 igb_get_hw_control(adapter);
4795
9d5c8243
AK		 4796 wr32(E1000_WUS, ~0);
4797
a88f10ec
AD		 4798 if (netif_running(netdev)) {
4799 err = igb_open(netdev);
4800 if (err)
4801 return err;
4802 }
9d5c8243
AK		 4803
4804 netif_device_attach(netdev);
4805
9d5c8243
AK		 4806 return 0;
4807}
4808#endif
4809
4810static void igb_shutdown(struct pci_dev *pdev)
4811{
4812 igb_suspend(pdev, PMSG_SUSPEND);
4813}
4814
4815#ifdef CONFIG_NET_POLL_CONTROLLER
4816/*
4817 * Polling 'interrupt' - used by things like netconsole to send skbs
4818 * without having to re-enable interrupts. It's not called while
4819 * the interrupt routine is executing.
4820 */
4821static void igb_netpoll(struct net_device *netdev)
4822{
4823 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4824 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4825 int i;
9d5c8243 4826
eebbbdba
AD		 4827 if (!adapter->msix_entries) {
4828 igb_irq_disable(adapter);
4829 napi_schedule(&adapter->rx_ring[0].napi);
4830 return;
4831 }
9d5c8243 4832
eebbbdba
AD		 4833 for (i = 0; i < adapter->num_tx_queues; i++) {
4834 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4835 wr32(E1000_EIMC, tx_ring->eims_value);
4836 igb_clean_tx_irq(tx_ring);
4837 wr32(E1000_EIMS, tx_ring->eims_value);
4838 }
9d5c8243 4839
eebbbdba
AD		 4840 for (i = 0; i < adapter->num_rx_queues; i++) {
4841 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4842 wr32(E1000_EIMC, rx_ring->eims_value);
4843 napi_schedule(&rx_ring->napi);
4844 }
9d5c8243
AK		 4845}
4846#endif /* CONFIG_NET_POLL_CONTROLLER */
4847
4848/**
4849 * igb_io_error_detected - called when PCI error is detected
4850 * @pdev: Pointer to PCI device
4851 * @state: The current pci connection state
4852 *
4853 * This function is called after a PCI bus error affecting
4854 * this device has been detected.
4855 */
4856static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4857 pci_channel_state_t state)
4858{
4859 struct net_device *netdev = pci_get_drvdata(pdev);
4860 struct igb_adapter *adapter = netdev_priv(netdev);
4861
4862 netif_device_detach(netdev);
4863
4864 if (netif_running(netdev))
4865 igb_down(adapter);
4866 pci_disable_device(pdev);
4867
4868 /* Request a slot slot reset. */
4869 return PCI_ERS_RESULT_NEED_RESET;
4870}
4871
4872/**
4873 * igb_io_slot_reset - called after the pci bus has been reset.
4874 * @pdev: Pointer to PCI device
4875 *
4876 * Restart the card from scratch, as if from a cold-boot. Implementation
4877 * resembles the first-half of the igb_resume routine.
4878 */
4879static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4880{
4881 struct net_device *netdev = pci_get_drvdata(pdev);
4882 struct igb_adapter *adapter = netdev_priv(netdev);
4883 struct e1000_hw *hw = &adapter->hw;
40a914fa 4884 pci_ers_result_t result;
42bfd33a 4885 int err;
9d5c8243 4886
aed5dec3 4887 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4888 dev_err(&pdev->dev,
4889 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4890 result = PCI_ERS_RESULT_DISCONNECT;
4891 } else {
4892 pci_set_master(pdev);
4893 pci_restore_state(pdev);
9d5c8243 4894
40a914fa
AD		 4895 pci_enable_wake(pdev, PCI_D3hot, 0);
4896 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4897
40a914fa
AD		 4898 igb_reset(adapter);
4899 wr32(E1000_WUS, ~0);
4900 result = PCI_ERS_RESULT_RECOVERED;
4901 }
9d5c8243 4902
ea943d41
JK		 4903 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4904 if (err) {
4905 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4906 "failed 0x%0x\n", err);
4907 /* non-fatal, continue */
4908 }
40a914fa
AD		 4909
4910 return result;
9d5c8243
AK		 4911}
4912
4913/**
4914 * igb_io_resume - called when traffic can start flowing again.
4915 * @pdev: Pointer to PCI device
4916 *
4917 * This callback is called when the error recovery driver tells us that
4918 * its OK to resume normal operation. Implementation resembles the
4919 * second-half of the igb_resume routine.
4920 */
4921static void igb_io_resume(struct pci_dev *pdev)
4922{
4923 struct net_device *netdev = pci_get_drvdata(pdev);
4924 struct igb_adapter *adapter = netdev_priv(netdev);
4925
9d5c8243
AK		 4926 if (netif_running(netdev)) {
4927 if (igb_up(adapter)) {
4928 dev_err(&pdev->dev, "igb_up failed after reset\n");
4929 return;
4930 }
4931 }
4932
4933 netif_device_attach(netdev);
4934
4935 /* let the f/w know that the h/w is now under the control of the
4936 * driver. */
4937 igb_get_hw_control(adapter);
9d5c8243
AK		 4938}
4939
e1739522
AD		 4940static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
4941{
4942 u32 reg_data;
4943
4944 reg_data = rd32(E1000_VMOLR(vfn));
4945 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
4946 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
4947 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
4948 E1000_VMOLR_AUPE | /* Accept untagged packets */
4949 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
4950 wr32(E1000_VMOLR(vfn), reg_data);
4951}
4952
4953static inline void igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4954 int vfn)
4955{
4956 struct e1000_hw *hw = &adapter->hw;
4957 u32 vmolr;
4958
4959 vmolr = rd32(E1000_VMOLR(vfn));
4960 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4961 vmolr |= size | E1000_VMOLR_LPE;
4962 wr32(E1000_VMOLR(vfn), vmolr);
4963}
4964
4965static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
4966{
4967 u32 reg_data;
4968
4969 reg_data = rd32(E1000_RAH(entry));
4970 reg_data &= ~E1000_RAH_POOL_MASK;
4971 reg_data |= E1000_RAH_POOL_1 << pool;;
4972 wr32(E1000_RAH(entry), reg_data);
4973}
4974
4975static void igb_set_mc_list_pools(struct igb_adapter *adapter,
4976 int entry_count, u16 total_rar_filters)
4977{
4978 struct e1000_hw *hw = &adapter->hw;
4979 int i = adapter->vfs_allocated_count + 1;
4980
4981 if ((i + entry_count) < total_rar_filters)
4982 total_rar_filters = i + entry_count;
4983
4984 for (; i < total_rar_filters; i++)
4985 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
4986}
4987
9d5c8243 4988/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)