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decnet: remove private wrappers of endian helpers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
421e02f0 45#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 46#include <linux/dca.h>
47#endif
9d5c8243
AK		 48#include "igb.h"
49
0024fd00 50#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 51char igb_driver_name[] = "igb";
52char igb_driver_version[] = DRV_VERSION;
53static const char igb_driver_string[] =
54 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 55static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 56
9d5c8243
AK		 57static const struct e1000_info *igb_info_tbl[] = {
58 [board_82575] = &e1000_82575_info,
59};
60
61static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
68 /* required last entry */
69 {0, }
70};
71
72MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
73
74void igb_reset(struct igb_adapter *);
75static int igb_setup_all_tx_resources(struct igb_adapter *);
76static int igb_setup_all_rx_resources(struct igb_adapter *);
77static void igb_free_all_tx_resources(struct igb_adapter *);
78static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 79void igb_update_stats(struct igb_adapter *);
80static int igb_probe(struct pci_dev *, const struct pci_device_id *);
81static void __devexit igb_remove(struct pci_dev *pdev);
82static int igb_sw_init(struct igb_adapter *);
83static int igb_open(struct net_device *);
84static int igb_close(struct net_device *);
85static void igb_configure_tx(struct igb_adapter *);
86static void igb_configure_rx(struct igb_adapter *);
87static void igb_setup_rctl(struct igb_adapter *);
88static void igb_clean_all_tx_rings(struct igb_adapter *);
89static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 90static void igb_clean_tx_ring(struct igb_ring *);
91static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 92static void igb_set_multi(struct net_device *);
93static void igb_update_phy_info(unsigned long);
94static void igb_watchdog(unsigned long);
95static void igb_watchdog_task(struct work_struct *);
96static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
97 struct igb_ring *);
98static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
99static struct net_device_stats *igb_get_stats(struct net_device *);
100static int igb_change_mtu(struct net_device *, int);
101static int igb_set_mac(struct net_device *, void *);
102static irqreturn_t igb_intr(int irq, void *);
103static irqreturn_t igb_intr_msi(int irq, void *);
104static irqreturn_t igb_msix_other(int irq, void *);
105static irqreturn_t igb_msix_rx(int irq, void *);
106static irqreturn_t igb_msix_tx(int irq, void *);
107static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 108#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 109static void igb_update_rx_dca(struct igb_ring *);
110static void igb_update_tx_dca(struct igb_ring *);
111static void igb_setup_dca(struct igb_adapter *);
421e02f0 112#endif /* CONFIG_IGB_DCA */
3b644cf6 113static bool igb_clean_tx_irq(struct igb_ring *);
661086df 114static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 115static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
116static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 117#ifdef CONFIG_IGB_LRO
118static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
119#endif
9d5c8243
AK		 120static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121static void igb_tx_timeout(struct net_device *);
122static void igb_reset_task(struct work_struct *);
123static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124static void igb_vlan_rx_add_vid(struct net_device *, u16);
125static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126static void igb_restore_vlan(struct igb_adapter *);
127
128static int igb_suspend(struct pci_dev *, pm_message_t);
129#ifdef CONFIG_PM
130static int igb_resume(struct pci_dev *);
131#endif
132static void igb_shutdown(struct pci_dev *);
421e02f0 133#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 134static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
135static struct notifier_block dca_notifier = {
136 .notifier_call = igb_notify_dca,
137 .next = NULL,
138 .priority = 0
139};
140#endif
9d5c8243
AK		 141
142#ifdef CONFIG_NET_POLL_CONTROLLER
143/* for netdump / net console */
144static void igb_netpoll(struct net_device *);
145#endif
146
147static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
148 pci_channel_state_t);
149static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
150static void igb_io_resume(struct pci_dev *);
151
152static struct pci_error_handlers igb_err_handler = {
153 .error_detected = igb_io_error_detected,
154 .slot_reset = igb_io_slot_reset,
155 .resume = igb_io_resume,
156};
157
158
159static struct pci_driver igb_driver = {
160 .name = igb_driver_name,
161 .id_table = igb_pci_tbl,
162 .probe = igb_probe,
163 .remove = __devexit_p(igb_remove),
164#ifdef CONFIG_PM
165 /* Power Managment Hooks */
166 .suspend = igb_suspend,
167 .resume = igb_resume,
168#endif
169 .shutdown = igb_shutdown,
170 .err_handler = &igb_err_handler
171};
172
7dfc16fa
AD		 173static int global_quad_port_a; /* global quad port a indication */
174
9d5c8243
AK		 175MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
176MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
177MODULE_LICENSE("GPL");
178MODULE_VERSION(DRV_VERSION);
179
180#ifdef DEBUG
181/**
182 * igb_get_hw_dev_name - return device name string
183 * used by hardware layer to print debugging information
184 **/
185char *igb_get_hw_dev_name(struct e1000_hw *hw)
186{
187 struct igb_adapter *adapter = hw->back;
188 return adapter->netdev->name;
189}
190#endif
191
192/**
193 * igb_init_module - Driver Registration Routine
194 *
195 * igb_init_module is the first routine called when the driver is
196 * loaded. All it does is register with the PCI subsystem.
197 **/
198static int __init igb_init_module(void)
199{
200 int ret;
201 printk(KERN_INFO "%s - version %s\n",
202 igb_driver_string, igb_driver_version);
203
204 printk(KERN_INFO "%s\n", igb_copyright);
205
7dfc16fa
AD		 206 global_quad_port_a = 0;
207
9d5c8243 208 ret = pci_register_driver(&igb_driver);
421e02f0 209#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 210 dca_register_notify(&dca_notifier);
211#endif
9d5c8243
AK		 212 return ret;
213}
214
215module_init(igb_init_module);
216
217/**
218 * igb_exit_module - Driver Exit Cleanup Routine
219 *
220 * igb_exit_module is called just before the driver is removed
221 * from memory.
222 **/
223static void __exit igb_exit_module(void)
224{
421e02f0 225#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 226 dca_unregister_notify(&dca_notifier);
227#endif
9d5c8243
AK		 228 pci_unregister_driver(&igb_driver);
229}
230
231module_exit(igb_exit_module);
232
233/**
234 * igb_alloc_queues - Allocate memory for all rings
235 * @adapter: board private structure to initialize
236 *
237 * We allocate one ring per queue at run-time since we don't know the
238 * number of queues at compile-time.
239 **/
240static int igb_alloc_queues(struct igb_adapter *adapter)
241{
242 int i;
243
244 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
245 sizeof(struct igb_ring), GFP_KERNEL);
246 if (!adapter->tx_ring)
247 return -ENOMEM;
248
249 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
250 sizeof(struct igb_ring), GFP_KERNEL);
251 if (!adapter->rx_ring) {
252 kfree(adapter->tx_ring);
253 return -ENOMEM;
254 }
255
6eb5a7f1
AD		 256 adapter->rx_ring->buddy = adapter->tx_ring;
257
661086df
PWJ		 258 for (i = 0; i < adapter->num_tx_queues; i++) {
259 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 260 ring->count = adapter->tx_ring_count;
661086df
PWJ		 261 ring->adapter = adapter;
262 ring->queue_index = i;
263 }
9d5c8243
AK		 264 for (i = 0; i < adapter->num_rx_queues; i++) {
265 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 266 ring->count = adapter->rx_ring_count;
9d5c8243 267 ring->adapter = adapter;
844290e5 268 ring->queue_index = i;
9d5c8243
AK		 269 ring->itr_register = E1000_ITR;
270
844290e5 271 /* set a default napi handler for each rx_ring */
661086df 272 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 273 }
274 return 0;
275}
276
a88f10ec
AD		 277static void igb_free_queues(struct igb_adapter *adapter)
278{
279 int i;
280
281 for (i = 0; i < adapter->num_rx_queues; i++)
282 netif_napi_del(&adapter->rx_ring[i].napi);
283
284 kfree(adapter->tx_ring);
285 kfree(adapter->rx_ring);
286}
287
9d5c8243
AK		 288#define IGB_N0_QUEUE -1
289static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
290 int tx_queue, int msix_vector)
291{
292 u32 msixbm = 0;
293 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 294 u32 ivar, index;
295
296 switch (hw->mac.type) {
297 case e1000_82575:
9d5c8243
AK		 298 /* The 82575 assigns vectors using a bitmask, which matches the
299 bitmask for the EICR/EIMS/EIMC registers. To assign one
300 or more queues to a vector, we write the appropriate bits
301 into the MSIXBM register for that vector. */
302 if (rx_queue > IGB_N0_QUEUE) {
303 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
304 adapter->rx_ring[rx_queue].eims_value = msixbm;
305 }
306 if (tx_queue > IGB_N0_QUEUE) {
307 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
308 adapter->tx_ring[tx_queue].eims_value =
309 E1000_EICR_TX_QUEUE0 << tx_queue;
310 }
311 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 312 break;
313 case e1000_82576:
106ef2fe 314 /* The 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 315 Each queue has a single entry in the table to which we write
316 a vector number along with a "valid" bit. Sadly, the layout
317 of the table is somewhat counterintuitive. */
318 if (rx_queue > IGB_N0_QUEUE) {
319 index = (rx_queue & 0x7);
320 ivar = array_rd32(E1000_IVAR0, index);
321 if (rx_queue < 8) {
322 /* vector goes into low byte of register */
323 ivar = ivar & 0xFFFFFF00;
324 ivar |= msix_vector | E1000_IVAR_VALID;
325 } else {
326 /* vector goes into third byte of register */
327 ivar = ivar & 0xFF00FFFF;
328 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
329 }
330 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
331 array_wr32(E1000_IVAR0, index, ivar);
332 }
333 if (tx_queue > IGB_N0_QUEUE) {
334 index = (tx_queue & 0x7);
335 ivar = array_rd32(E1000_IVAR0, index);
336 if (tx_queue < 8) {
337 /* vector goes into second byte of register */
338 ivar = ivar & 0xFFFF00FF;
339 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
340 } else {
341 /* vector goes into high byte of register */
342 ivar = ivar & 0x00FFFFFF;
343 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
344 }
345 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
346 array_wr32(E1000_IVAR0, index, ivar);
347 }
348 break;
349 default:
350 BUG();
351 break;
352 }
9d5c8243
AK		 353}
354
355/**
356 * igb_configure_msix - Configure MSI-X hardware
357 *
358 * igb_configure_msix sets up the hardware to properly
359 * generate MSI-X interrupts.
360 **/
361static void igb_configure_msix(struct igb_adapter *adapter)
362{
363 u32 tmp;
364 int i, vector = 0;
365 struct e1000_hw *hw = &adapter->hw;
366
367 adapter->eims_enable_mask = 0;
2d064c06
AD		 368 if (hw->mac.type == e1000_82576)
369 /* Turn on MSI-X capability first, or our settings
370 * won't stick. And it will take days to debug. */
371 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
372 E1000_GPIE_PBA | E1000_GPIE_EIAME |
373 E1000_GPIE_NSICR);
9d5c8243
AK		 374
375 for (i = 0; i < adapter->num_tx_queues; i++) {
376 struct igb_ring *tx_ring = &adapter->tx_ring[i];
377 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
378 adapter->eims_enable_mask |= tx_ring->eims_value;
379 if (tx_ring->itr_val)
6eb5a7f1 380 writel(tx_ring->itr_val,
9d5c8243
AK		 381 hw->hw_addr + tx_ring->itr_register);
382 else
383 writel(1, hw->hw_addr + tx_ring->itr_register);
384 }
385
386 for (i = 0; i < adapter->num_rx_queues; i++) {
387 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 388 rx_ring->buddy = NULL;
9d5c8243
AK		 389 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
390 adapter->eims_enable_mask |= rx_ring->eims_value;
391 if (rx_ring->itr_val)
6eb5a7f1 392 writel(rx_ring->itr_val,
9d5c8243
AK		 393 hw->hw_addr + rx_ring->itr_register);
394 else
395 writel(1, hw->hw_addr + rx_ring->itr_register);
396 }
397
398
399 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 400 switch (hw->mac.type) {
401 case e1000_82575:
9d5c8243
AK		 402 array_wr32(E1000_MSIXBM(0), vector++,
403 E1000_EIMS_OTHER);
404
9d5c8243
AK		 405 tmp = rd32(E1000_CTRL_EXT);
406 /* enable MSI-X PBA support*/
407 tmp |= E1000_CTRL_EXT_PBA_CLR;
408
409 /* Auto-Mask interrupts upon ICR read. */
410 tmp |= E1000_CTRL_EXT_EIAME;
411 tmp |= E1000_CTRL_EXT_IRCA;
412
413 wr32(E1000_CTRL_EXT, tmp);
414 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 415 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 416
2d064c06
AD		 417 break;
418
419 case e1000_82576:
420 tmp = (vector++ | E1000_IVAR_VALID) << 8;
421 wr32(E1000_IVAR_MISC, tmp);
422
423 adapter->eims_enable_mask = (1 << (vector)) - 1;
424 adapter->eims_other = 1 << (vector - 1);
425 break;
426 default:
427 /* do nothing, since nothing else supports MSI-X */
428 break;
429 } /* switch (hw->mac.type) */
9d5c8243
AK		 430 wrfl();
431}
432
433/**
434 * igb_request_msix - Initialize MSI-X interrupts
435 *
436 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
437 * kernel.
438 **/
439static int igb_request_msix(struct igb_adapter *adapter)
440{
441 struct net_device *netdev = adapter->netdev;
442 int i, err = 0, vector = 0;
443
444 vector = 0;
445
446 for (i = 0; i < adapter->num_tx_queues; i++) {
447 struct igb_ring *ring = &(adapter->tx_ring[i]);
448 sprintf(ring->name, "%s-tx%d", netdev->name, i);
449 err = request_irq(adapter->msix_entries[vector].vector,
450 &igb_msix_tx, 0, ring->name,
451 &(adapter->tx_ring[i]));
452 if (err)
453 goto out;
454 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 455 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 456 vector++;
457 }
458 for (i = 0; i < adapter->num_rx_queues; i++) {
459 struct igb_ring *ring = &(adapter->rx_ring[i]);
460 if (strlen(netdev->name) < (IFNAMSIZ - 5))
461 sprintf(ring->name, "%s-rx%d", netdev->name, i);
462 else
463 memcpy(ring->name, netdev->name, IFNAMSIZ);
464 err = request_irq(adapter->msix_entries[vector].vector,
465 &igb_msix_rx, 0, ring->name,
466 &(adapter->rx_ring[i]));
467 if (err)
468 goto out;
469 ring->itr_register = E1000_EITR(0) + (vector << 2);
470 ring->itr_val = adapter->itr;
844290e5
PW		 471 /* overwrite the poll routine for MSIX, we've already done
472 * netif_napi_add */
473 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 474 vector++;
475 }
476
477 err = request_irq(adapter->msix_entries[vector].vector,
478 &igb_msix_other, 0, netdev->name, netdev);
479 if (err)
480 goto out;
481
9d5c8243
AK		 482 igb_configure_msix(adapter);
483 return 0;
484out:
485 return err;
486}
487
488static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
489{
490 if (adapter->msix_entries) {
491 pci_disable_msix(adapter->pdev);
492 kfree(adapter->msix_entries);
493 adapter->msix_entries = NULL;
7dfc16fa 494 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 495 pci_disable_msi(adapter->pdev);
496 return;
497}
498
499
500/**
501 * igb_set_interrupt_capability - set MSI or MSI-X if supported
502 *
503 * Attempt to configure interrupts using the best available
504 * capabilities of the hardware and kernel.
505 **/
506static void igb_set_interrupt_capability(struct igb_adapter *adapter)
507{
508 int err;
509 int numvecs, i;
510
511 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
512 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
513 GFP_KERNEL);
514 if (!adapter->msix_entries)
515 goto msi_only;
516
517 for (i = 0; i < numvecs; i++)
518 adapter->msix_entries[i].entry = i;
519
520 err = pci_enable_msix(adapter->pdev,
521 adapter->msix_entries,
522 numvecs);
523 if (err == 0)
34a20e89 524 goto out;
9d5c8243
AK		 525
526 igb_reset_interrupt_capability(adapter);
527
528 /* If we can't do MSI-X, try MSI */
529msi_only:
530 adapter->num_rx_queues = 1;
661086df 531 adapter->num_tx_queues = 1;
9d5c8243 532 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 533 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 534out:
661086df 535 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 536 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 537 return;
538}
539
540/**
541 * igb_request_irq - initialize interrupts
542 *
543 * Attempts to configure interrupts using the best available
544 * capabilities of the hardware and kernel.
545 **/
546static int igb_request_irq(struct igb_adapter *adapter)
547{
548 struct net_device *netdev = adapter->netdev;
549 struct e1000_hw *hw = &adapter->hw;
550 int err = 0;
551
552 if (adapter->msix_entries) {
553 err = igb_request_msix(adapter);
844290e5 554 if (!err)
9d5c8243 555 goto request_done;
9d5c8243
AK		 556 /* fall back to MSI */
557 igb_reset_interrupt_capability(adapter);
558 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 559 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 560 igb_free_all_tx_resources(adapter);
561 igb_free_all_rx_resources(adapter);
562 adapter->num_rx_queues = 1;
563 igb_alloc_queues(adapter);
844290e5 564 } else {
2d064c06
AD		 565 switch (hw->mac.type) {
566 case e1000_82575:
567 wr32(E1000_MSIXBM(0),
568 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
569 break;
570 case e1000_82576:
571 wr32(E1000_IVAR0, E1000_IVAR_VALID);
572 break;
573 default:
574 break;
575 }
9d5c8243 576 }
844290e5 577
7dfc16fa 578 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 579 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
580 netdev->name, netdev);
581 if (!err)
582 goto request_done;
583 /* fall back to legacy interrupts */
584 igb_reset_interrupt_capability(adapter);
7dfc16fa 585 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 586 }
587
588 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
589 netdev->name, netdev);
590
6cb5e577 591 if (err)
9d5c8243
AK		 592 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
593 err);
9d5c8243
AK		 594
595request_done:
596 return err;
597}
598
599static void igb_free_irq(struct igb_adapter *adapter)
600{
601 struct net_device *netdev = adapter->netdev;
602
603 if (adapter->msix_entries) {
604 int vector = 0, i;
605
606 for (i = 0; i < adapter->num_tx_queues; i++)
607 free_irq(adapter->msix_entries[vector++].vector,
608 &(adapter->tx_ring[i]));
609 for (i = 0; i < adapter->num_rx_queues; i++)
610 free_irq(adapter->msix_entries[vector++].vector,
611 &(adapter->rx_ring[i]));
612
613 free_irq(adapter->msix_entries[vector++].vector, netdev);
614 return;
615 }
616
617 free_irq(adapter->pdev->irq, netdev);
618}
619
620/**
621 * igb_irq_disable - Mask off interrupt generation on the NIC
622 * @adapter: board private structure
623 **/
624static void igb_irq_disable(struct igb_adapter *adapter)
625{
626 struct e1000_hw *hw = &adapter->hw;
627
628 if (adapter->msix_entries) {
844290e5 629 wr32(E1000_EIAM, 0);
9d5c8243
AK		 630 wr32(E1000_EIMC, ~0);
631 wr32(E1000_EIAC, 0);
632 }
844290e5
PW		 633
634 wr32(E1000_IAM, 0);
9d5c8243
AK		 635 wr32(E1000_IMC, ~0);
636 wrfl();
637 synchronize_irq(adapter->pdev->irq);
638}
639
640/**
641 * igb_irq_enable - Enable default interrupt generation settings
642 * @adapter: board private structure
643 **/
644static void igb_irq_enable(struct igb_adapter *adapter)
645{
646 struct e1000_hw *hw = &adapter->hw;
647
648 if (adapter->msix_entries) {
844290e5
PW		 649 wr32(E1000_EIAC, adapter->eims_enable_mask);
650 wr32(E1000_EIAM, adapter->eims_enable_mask);
651 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 652 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 653 } else {
654 wr32(E1000_IMS, IMS_ENABLE_MASK);
655 wr32(E1000_IAM, IMS_ENABLE_MASK);
656 }
9d5c8243
AK		 657}
658
659static void igb_update_mng_vlan(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 u16 vid = adapter->hw.mng_cookie.vlan_id;
663 u16 old_vid = adapter->mng_vlan_id;
664 if (adapter->vlgrp) {
665 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
666 if (adapter->hw.mng_cookie.status &
667 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
668 igb_vlan_rx_add_vid(netdev, vid);
669 adapter->mng_vlan_id = vid;
670 } else
671 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
672
673 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
674 (vid != old_vid) &&
675 !vlan_group_get_device(adapter->vlgrp, old_vid))
676 igb_vlan_rx_kill_vid(netdev, old_vid);
677 } else
678 adapter->mng_vlan_id = vid;
679 }
680}
681
682/**
683 * igb_release_hw_control - release control of the h/w to f/w
684 * @adapter: address of board private structure
685 *
686 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
687 * For ASF and Pass Through versions of f/w this means that the
688 * driver is no longer loaded.
689 *
690 **/
691static void igb_release_hw_control(struct igb_adapter *adapter)
692{
693 struct e1000_hw *hw = &adapter->hw;
694 u32 ctrl_ext;
695
696 /* Let firmware take over control of h/w */
697 ctrl_ext = rd32(E1000_CTRL_EXT);
698 wr32(E1000_CTRL_EXT,
699 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
700}
701
702
703/**
704 * igb_get_hw_control - get control of the h/w from f/w
705 * @adapter: address of board private structure
706 *
707 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
708 * For ASF and Pass Through versions of f/w this means that
709 * the driver is loaded.
710 *
711 **/
712static void igb_get_hw_control(struct igb_adapter *adapter)
713{
714 struct e1000_hw *hw = &adapter->hw;
715 u32 ctrl_ext;
716
717 /* Let firmware know the driver has taken over */
718 ctrl_ext = rd32(E1000_CTRL_EXT);
719 wr32(E1000_CTRL_EXT,
720 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
721}
722
9d5c8243
AK		 723/**
724 * igb_configure - configure the hardware for RX and TX
725 * @adapter: private board structure
726 **/
727static void igb_configure(struct igb_adapter *adapter)
728{
729 struct net_device *netdev = adapter->netdev;
730 int i;
731
732 igb_get_hw_control(adapter);
733 igb_set_multi(netdev);
734
735 igb_restore_vlan(adapter);
9d5c8243
AK		 736
737 igb_configure_tx(adapter);
738 igb_setup_rctl(adapter);
739 igb_configure_rx(adapter);
662d7205
AD		 740
741 igb_rx_fifo_flush_82575(&adapter->hw);
742
9d5c8243
AK		 743 /* call IGB_DESC_UNUSED which always leaves
744 * at least 1 descriptor unused to make sure
745 * next_to_use != next_to_clean */
746 for (i = 0; i < adapter->num_rx_queues; i++) {
747 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 748 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 749 }
750
751
752 adapter->tx_queue_len = netdev->tx_queue_len;
753}
754
755
756/**
757 * igb_up - Open the interface and prepare it to handle traffic
758 * @adapter: board private structure
759 **/
760
761int igb_up(struct igb_adapter *adapter)
762{
763 struct e1000_hw *hw = &adapter->hw;
764 int i;
765
766 /* hardware has been reset, we need to reload some things */
767 igb_configure(adapter);
768
769 clear_bit(__IGB_DOWN, &adapter->state);
770
844290e5
PW		 771 for (i = 0; i < adapter->num_rx_queues; i++)
772 napi_enable(&adapter->rx_ring[i].napi);
773 if (adapter->msix_entries)
9d5c8243 774 igb_configure_msix(adapter);
9d5c8243
AK		 775
776 /* Clear any pending interrupts. */
777 rd32(E1000_ICR);
778 igb_irq_enable(adapter);
779
780 /* Fire a link change interrupt to start the watchdog. */
781 wr32(E1000_ICS, E1000_ICS_LSC);
782 return 0;
783}
784
785void igb_down(struct igb_adapter *adapter)
786{
787 struct e1000_hw *hw = &adapter->hw;
788 struct net_device *netdev = adapter->netdev;
789 u32 tctl, rctl;
790 int i;
791
792 /* signal that we're down so the interrupt handler does not
793 * reschedule our watchdog timer */
794 set_bit(__IGB_DOWN, &adapter->state);
795
796 /* disable receives in the hardware */
797 rctl = rd32(E1000_RCTL);
798 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
799 /* flush and sleep below */
800
fd2ea0a7 801 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 802
803 /* disable transmits in the hardware */
804 tctl = rd32(E1000_TCTL);
805 tctl &= ~E1000_TCTL_EN;
806 wr32(E1000_TCTL, tctl);
807 /* flush both disables and wait for them to finish */
808 wrfl();
809 msleep(10);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 813
9d5c8243
AK		 814 igb_irq_disable(adapter);
815
816 del_timer_sync(&adapter->watchdog_timer);
817 del_timer_sync(&adapter->phy_info_timer);
818
819 netdev->tx_queue_len = adapter->tx_queue_len;
820 netif_carrier_off(netdev);
821 adapter->link_speed = 0;
822 adapter->link_duplex = 0;
823
3023682e
JK		 824 if (!pci_channel_offline(adapter->pdev))
825 igb_reset(adapter);
9d5c8243
AK		 826 igb_clean_all_tx_rings(adapter);
827 igb_clean_all_rx_rings(adapter);
828}
829
830void igb_reinit_locked(struct igb_adapter *adapter)
831{
832 WARN_ON(in_interrupt());
833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
834 msleep(1);
835 igb_down(adapter);
836 igb_up(adapter);
837 clear_bit(__IGB_RESETTING, &adapter->state);
838}
839
840void igb_reset(struct igb_adapter *adapter)
841{
842 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 843 struct e1000_mac_info *mac = &hw->mac;
844 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 845 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
846 u16 hwm;
847
848 /* Repartition Pba for greater than 9k mtu
849 * To take effect CTRL.RST is required.
850 */
2d064c06 851 if (mac->type != e1000_82576) {
9d5c8243 852 pba = E1000_PBA_34K;
2d064c06
AD		 853 }
854 else {
855 pba = E1000_PBA_64K;
856 }
9d5c8243 857
2d064c06
AD		 858 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
859 (mac->type < e1000_82576)) {
9d5c8243
AK		 860 /* adjust PBA for jumbo frames */
861 wr32(E1000_PBA, pba);
862
863 /* To maintain wire speed transmits, the Tx FIFO should be
864 * large enough to accommodate two full transmit packets,
865 * rounded up to the next 1KB and expressed in KB. Likewise,
866 * the Rx FIFO should be large enough to accommodate at least
867 * one full receive packet and is similarly rounded up and
868 * expressed in KB. */
869 pba = rd32(E1000_PBA);
870 /* upper 16 bits has Tx packet buffer allocation size in KB */
871 tx_space = pba >> 16;
872 /* lower 16 bits has Rx packet buffer allocation size in KB */
873 pba &= 0xffff;
874 /* the tx fifo also stores 16 bytes of information about the tx
875 * but don't include ethernet FCS because hardware appends it */
876 min_tx_space = (adapter->max_frame_size +
877 sizeof(struct e1000_tx_desc) -
878 ETH_FCS_LEN) * 2;
879 min_tx_space = ALIGN(min_tx_space, 1024);
880 min_tx_space >>= 10;
881 /* software strips receive CRC, so leave room for it */
882 min_rx_space = adapter->max_frame_size;
883 min_rx_space = ALIGN(min_rx_space, 1024);
884 min_rx_space >>= 10;
885
886 /* If current Tx allocation is less than the min Tx FIFO size,
887 * and the min Tx FIFO size is less than the current Rx FIFO
888 * allocation, take space away from current Rx allocation */
889 if (tx_space < min_tx_space &&
890 ((min_tx_space - tx_space) < pba)) {
891 pba = pba - (min_tx_space - tx_space);
892
893 /* if short on rx space, rx wins and must trump tx
894 * adjustment */
895 if (pba < min_rx_space)
896 pba = min_rx_space;
897 }
2d064c06 898 wr32(E1000_PBA, pba);
9d5c8243 899 }
9d5c8243
AK		 900
901 /* flow control settings */
902 /* The high water mark must be low enough to fit one full frame
903 * (or the size used for early receive) above it in the Rx FIFO.
904 * Set it to the lower of:
905 * - 90% of the Rx FIFO size, or
906 * - the full Rx FIFO size minus one full frame */
907 hwm = min(((pba << 10) * 9 / 10),
2d064c06 908 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 909
2d064c06
AD		 910 if (mac->type < e1000_82576) {
911 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
912 fc->low_water = fc->high_water - 8;
913 } else {
914 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
915 fc->low_water = fc->high_water - 16;
916 }
9d5c8243
AK		 917 fc->pause_time = 0xFFFF;
918 fc->send_xon = 1;
919 fc->type = fc->original_type;
920
921 /* Allow time for pending master requests to run */
922 adapter->hw.mac.ops.reset_hw(&adapter->hw);
923 wr32(E1000_WUC, 0);
924
925 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
926 dev_err(&adapter->pdev->dev, "Hardware Error\n");
927
928 igb_update_mng_vlan(adapter);
929
930 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
931 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
932
933 igb_reset_adaptive(&adapter->hw);
f5f4cf08 934 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 935}
936
42bfd33a
TI		 937/**
938 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
939 * @pdev: PCI device information struct
940 *
941 * Returns true if an adapter needs ioport resources
942 **/
943static int igb_is_need_ioport(struct pci_dev *pdev)
944{
945 switch (pdev->device) {
946 /* Currently there are no adapters that need ioport resources */
947 default:
948 return false;
949 }
950}
951
2e5c6922
SH		 952static const struct net_device_ops igb_netdev_ops = {
953 .ndo_open = igb_open,
954 .ndo_stop = igb_close,
00829823 955 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 956 .ndo_get_stats = igb_get_stats,
957 .ndo_set_multicast_list = igb_set_multi,
958 .ndo_set_mac_address = igb_set_mac,
959 .ndo_change_mtu = igb_change_mtu,
960 .ndo_do_ioctl = igb_ioctl,
961 .ndo_tx_timeout = igb_tx_timeout,
962 .ndo_validate_addr = eth_validate_addr,
963 .ndo_vlan_rx_register = igb_vlan_rx_register,
964 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
965 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
966#ifdef CONFIG_NET_POLL_CONTROLLER
967 .ndo_poll_controller = igb_netpoll,
968#endif
969};
970
9d5c8243
AK		 971/**
972 * igb_probe - Device Initialization Routine
973 * @pdev: PCI device information struct
974 * @ent: entry in igb_pci_tbl
975 *
976 * Returns 0 on success, negative on failure
977 *
978 * igb_probe initializes an adapter identified by a pci_dev structure.
979 * The OS initialization, configuring of the adapter private structure,
980 * and a hardware reset occur.
981 **/
982static int __devinit igb_probe(struct pci_dev *pdev,
983 const struct pci_device_id *ent)
984{
985 struct net_device *netdev;
986 struct igb_adapter *adapter;
987 struct e1000_hw *hw;
c54106bb 988 struct pci_dev *us_dev;
9d5c8243
AK		 989 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
990 unsigned long mmio_start, mmio_len;
c54106bb
AD		 991 int i, err, pci_using_dac, pos;
992 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 993 u16 eeprom_apme_mask = IGB_EEPROM_APME;
994 u32 part_num;
42bfd33a 995 int bars, need_ioport;
9d5c8243 996
42bfd33a
TI		 997 /* do not allocate ioport bars when not needed */
998 need_ioport = igb_is_need_ioport(pdev);
999 if (need_ioport) {
1000 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1001 err = pci_enable_device(pdev);
1002 } else {
1003 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1004 err = pci_enable_device_mem(pdev);
1005 }
9d5c8243
AK		 1006 if (err)
1007 return err;
1008
1009 pci_using_dac = 0;
1010 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1011 if (!err) {
1012 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1013 if (!err)
1014 pci_using_dac = 1;
1015 } else {
1016 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1017 if (err) {
1018 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1019 if (err) {
1020 dev_err(&pdev->dev, "No usable DMA "
1021 "configuration, aborting\n");
1022 goto err_dma;
1023 }
1024 }
1025 }
1026
c54106bb
AD		 1027 /* 82575 requires that the pci-e link partner disable the L0s state */
1028 switch (pdev->device) {
1029 case E1000_DEV_ID_82575EB_COPPER:
1030 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1031 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1032 us_dev = pdev->bus->self;
1033 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1034 if (pos) {
1035 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1036 &state);
1037 state &= ~PCIE_LINK_STATE_L0S;
1038 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1039 state);
ac450208
BH		 1040 dev_info(&pdev->dev,
1041 "Disabling ASPM L0s upstream switch port %s\n",
1042 pci_name(us_dev));
c54106bb
AD		 1043 }
1044 default:
1045 break;
1046 }
1047
42bfd33a 1048 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1049 if (err)
1050 goto err_pci_reg;
1051
1052 pci_set_master(pdev);
c682fc23 1053 pci_save_state(pdev);
9d5c8243
AK		 1054
1055 err = -ENOMEM;
661086df 1056 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1057 if (!netdev)
1058 goto err_alloc_etherdev;
1059
1060 SET_NETDEV_DEV(netdev, &pdev->dev);
1061
1062 pci_set_drvdata(pdev, netdev);
1063 adapter = netdev_priv(netdev);
1064 adapter->netdev = netdev;
1065 adapter->pdev = pdev;
1066 hw = &adapter->hw;
1067 hw->back = adapter;
1068 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1069 adapter->bars = bars;
1070 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1071
1072 mmio_start = pci_resource_start(pdev, 0);
1073 mmio_len = pci_resource_len(pdev, 0);
1074
1075 err = -EIO;
1076 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1077 if (!adapter->hw.hw_addr)
1078 goto err_ioremap;
1079
2e5c6922 1080 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1081 igb_set_ethtool_ops(netdev);
9d5c8243 1082 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1083
1084 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1085
1086 netdev->mem_start = mmio_start;
1087 netdev->mem_end = mmio_start + mmio_len;
1088
9d5c8243
AK		 1089 /* PCI config space info */
1090 hw->vendor_id = pdev->vendor;
1091 hw->device_id = pdev->device;
1092 hw->revision_id = pdev->revision;
1093 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1094 hw->subsystem_device_id = pdev->subsystem_device;
1095
1096 /* setup the private structure */
1097 hw->back = adapter;
1098 /* Copy the default MAC, PHY and NVM function pointers */
1099 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1100 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1101 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1102 /* Initialize skew-specific constants */
1103 err = ei->get_invariants(hw);
1104 if (err)
1105 goto err_hw_init;
1106
1107 err = igb_sw_init(adapter);
1108 if (err)
1109 goto err_sw_init;
1110
1111 igb_get_bus_info_pcie(hw);
1112
7dfc16fa
AD		 1113 /* set flags */
1114 switch (hw->mac.type) {
1115 case e1000_82576:
1116 case e1000_82575:
1117 adapter->flags |= IGB_FLAG_HAS_DCA;
1118 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1119 break;
1120 default:
1121 break;
1122 }
1123
9d5c8243
AK		 1124 hw->phy.autoneg_wait_to_complete = false;
1125 hw->mac.adaptive_ifs = true;
1126
1127 /* Copper options */
1128 if (hw->phy.media_type == e1000_media_type_copper) {
1129 hw->phy.mdix = AUTO_ALL_MODES;
1130 hw->phy.disable_polarity_correction = false;
1131 hw->phy.ms_type = e1000_ms_hw_default;
1132 }
1133
1134 if (igb_check_reset_block(hw))
1135 dev_info(&pdev->dev,
1136 "PHY reset is blocked due to SOL/IDER session.\n");
1137
1138 netdev->features = NETIF_F_SG |
1139 NETIF_F_HW_CSUM |
1140 NETIF_F_HW_VLAN_TX |
1141 NETIF_F_HW_VLAN_RX |
1142 NETIF_F_HW_VLAN_FILTER;
1143
1144 netdev->features |= NETIF_F_TSO;
9d5c8243 1145 netdev->features |= NETIF_F_TSO6;
48f29ffc 1146
d3352520
AD		 1147#ifdef CONFIG_IGB_LRO
1148 netdev->features |= NETIF_F_LRO;
1149#endif
1150
48f29ffc
JK		 1151 netdev->vlan_features |= NETIF_F_TSO;
1152 netdev->vlan_features |= NETIF_F_TSO6;
1153 netdev->vlan_features |= NETIF_F_HW_CSUM;
1154 netdev->vlan_features |= NETIF_F_SG;
1155
9d5c8243
AK		 1156 if (pci_using_dac)
1157 netdev->features |= NETIF_F_HIGHDMA;
1158
1159 netdev->features |= NETIF_F_LLTX;
1160 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1161
1162 /* before reading the NVM, reset the controller to put the device in a
1163 * known good starting state */
1164 hw->mac.ops.reset_hw(hw);
1165
1166 /* make sure the NVM is good */
1167 if (igb_validate_nvm_checksum(hw) < 0) {
1168 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1169 err = -EIO;
1170 goto err_eeprom;
1171 }
1172
1173 /* copy the MAC address out of the NVM */
1174 if (hw->mac.ops.read_mac_addr(hw))
1175 dev_err(&pdev->dev, "NVM Read Error\n");
1176
1177 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1178 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1179
1180 if (!is_valid_ether_addr(netdev->perm_addr)) {
1181 dev_err(&pdev->dev, "Invalid MAC Address\n");
1182 err = -EIO;
1183 goto err_eeprom;
1184 }
1185
1186 init_timer(&adapter->watchdog_timer);
1187 adapter->watchdog_timer.function = &igb_watchdog;
1188 adapter->watchdog_timer.data = (unsigned long) adapter;
1189
1190 init_timer(&adapter->phy_info_timer);
1191 adapter->phy_info_timer.function = &igb_update_phy_info;
1192 adapter->phy_info_timer.data = (unsigned long) adapter;
1193
1194 INIT_WORK(&adapter->reset_task, igb_reset_task);
1195 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1196
1197 /* Initialize link & ring properties that are user-changeable */
1198 adapter->tx_ring->count = 256;
1199 for (i = 0; i < adapter->num_tx_queues; i++)
1200 adapter->tx_ring[i].count = adapter->tx_ring->count;
1201 adapter->rx_ring->count = 256;
1202 for (i = 0; i < adapter->num_rx_queues; i++)
1203 adapter->rx_ring[i].count = adapter->rx_ring->count;
1204
1205 adapter->fc_autoneg = true;
1206 hw->mac.autoneg = true;
1207 hw->phy.autoneg_advertised = 0x2f;
1208
1209 hw->fc.original_type = e1000_fc_default;
1210 hw->fc.type = e1000_fc_default;
1211
1212 adapter->itr_setting = 3;
1213 adapter->itr = IGB_START_ITR;
1214
1215 igb_validate_mdi_setting(hw);
1216
1217 adapter->rx_csum = 1;
1218
1219 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1220 * enable the ACPI Magic Packet filter
1221 */
1222
1223 if (hw->bus.func == 0 ||
1224 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1225 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1226 &eeprom_data);
1227
1228 if (eeprom_data & eeprom_apme_mask)
1229 adapter->eeprom_wol |= E1000_WUFC_MAG;
1230
1231 /* now that we have the eeprom settings, apply the special cases where
1232 * the eeprom may be wrong or the board simply won't support wake on
1233 * lan on a particular port */
1234 switch (pdev->device) {
1235 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1236 adapter->eeprom_wol = 0;
1237 break;
1238 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1239 case E1000_DEV_ID_82576_FIBER:
1240 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1241 /* Wake events only supported on port A for dual fiber
1242 * regardless of eeprom setting */
1243 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1244 adapter->eeprom_wol = 0;
1245 break;
1246 }
1247
1248 /* initialize the wol settings based on the eeprom settings */
1249 adapter->wol = adapter->eeprom_wol;
e1b86d84 1250 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1251
1252 /* reset the hardware with the new settings */
1253 igb_reset(adapter);
1254
1255 /* let the f/w know that the h/w is now under the control of the
1256 * driver. */
1257 igb_get_hw_control(adapter);
1258
1259 /* tell the stack to leave us alone until igb_open() is called */
1260 netif_carrier_off(netdev);
fd2ea0a7 1261 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1262
1263 strcpy(netdev->name, "eth%d");
1264 err = register_netdev(netdev);
1265 if (err)
1266 goto err_register;
1267
421e02f0 1268#ifdef CONFIG_IGB_DCA
7dfc16fa
AD		 1269 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1270 (dca_add_requester(&pdev->dev) == 0)) {
1271 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1272 dev_info(&pdev->dev, "DCA enabled\n");
1273 /* Always use CB2 mode, difference is masked
1274 * in the CB driver. */
1275 wr32(E1000_DCA_CTRL, 2);
1276 igb_setup_dca(adapter);
1277 }
1278#endif
1279
9d5c8243
AK		 1280 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1281 /* print bus type/speed/width info */
7c510e4b 1282 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1283 netdev->name,
1284 ((hw->bus.speed == e1000_bus_speed_2500)
1285 ? "2.5Gb/s" : "unknown"),
1286 ((hw->bus.width == e1000_bus_width_pcie_x4)
1287 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1288 ? "Width x1" : "unknown"),
7c510e4b 1289 netdev->dev_addr);
9d5c8243
AK		 1290
1291 igb_read_part_num(hw, &part_num);
1292 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1293 (part_num >> 8), (part_num & 0xff));
1294
1295 dev_info(&pdev->dev,
1296 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1297 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1298 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1299 adapter->num_rx_queues, adapter->num_tx_queues);
1300
9d5c8243
AK		 1301 return 0;
1302
1303err_register:
1304 igb_release_hw_control(adapter);
1305err_eeprom:
1306 if (!igb_check_reset_block(hw))
f5f4cf08 1307 igb_reset_phy(hw);
9d5c8243
AK		 1308
1309 if (hw->flash_address)
1310 iounmap(hw->flash_address);
1311
1312 igb_remove_device(hw);
a88f10ec 1313 igb_free_queues(adapter);
9d5c8243
AK		 1314err_sw_init:
1315err_hw_init:
1316 iounmap(hw->hw_addr);
1317err_ioremap:
1318 free_netdev(netdev);
1319err_alloc_etherdev:
42bfd33a 1320 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1321err_pci_reg:
1322err_dma:
1323 pci_disable_device(pdev);
1324 return err;
1325}
1326
1327/**
1328 * igb_remove - Device Removal Routine
1329 * @pdev: PCI device information struct
1330 *
1331 * igb_remove is called by the PCI subsystem to alert the driver
1332 * that it should release a PCI device. The could be caused by a
1333 * Hot-Plug event, or because the driver is going to be removed from
1334 * memory.
1335 **/
1336static void __devexit igb_remove(struct pci_dev *pdev)
1337{
1338 struct net_device *netdev = pci_get_drvdata(pdev);
1339 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1340#ifdef CONFIG_IGB_DCA
fe4506b6 1341 struct e1000_hw *hw = &adapter->hw;
9280fa52 1342#endif
9d5c8243
AK		 1343
1344 /* flush_scheduled work may reschedule our watchdog task, so
1345 * explicitly disable watchdog tasks from being rescheduled */
1346 set_bit(__IGB_DOWN, &adapter->state);
1347 del_timer_sync(&adapter->watchdog_timer);
1348 del_timer_sync(&adapter->phy_info_timer);
1349
1350 flush_scheduled_work();
1351
421e02f0 1352#ifdef CONFIG_IGB_DCA
7dfc16fa 1353 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1354 dev_info(&pdev->dev, "DCA disabled\n");
1355 dca_remove_requester(&pdev->dev);
7dfc16fa 1356 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1357 wr32(E1000_DCA_CTRL, 1);
1358 }
1359#endif
1360
9d5c8243
AK		 1361 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1362 * would have already happened in close and is redundant. */
1363 igb_release_hw_control(adapter);
1364
1365 unregister_netdev(netdev);
1366
f5f4cf08
AD		 1367 if (!igb_check_reset_block(&adapter->hw))
1368 igb_reset_phy(&adapter->hw);
9d5c8243
AK		 1369
1370 igb_remove_device(&adapter->hw);
1371 igb_reset_interrupt_capability(adapter);
1372
a88f10ec 1373 igb_free_queues(adapter);
9d5c8243
AK		 1374
1375 iounmap(adapter->hw.hw_addr);
1376 if (adapter->hw.flash_address)
1377 iounmap(adapter->hw.flash_address);
42bfd33a 1378 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1379
1380 free_netdev(netdev);
1381
1382 pci_disable_device(pdev);
1383}
1384
1385/**
1386 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1387 * @adapter: board private structure to initialize
1388 *
1389 * igb_sw_init initializes the Adapter private data structure.
1390 * Fields are initialized based on PCI device information and
1391 * OS network device settings (MTU size).
1392 **/
1393static int __devinit igb_sw_init(struct igb_adapter *adapter)
1394{
1395 struct e1000_hw *hw = &adapter->hw;
1396 struct net_device *netdev = adapter->netdev;
1397 struct pci_dev *pdev = adapter->pdev;
1398
1399 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1400
68fd9910
AD		 1401 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1402 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1403 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1404 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1405 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1406 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1407
1408 /* Number of supported queues. */
1409 /* Having more queues than CPUs doesn't make sense. */
661086df 1410 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1411 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1412
661086df
PWJ		 1413 /* This call may decrease the number of queues depending on
1414 * interrupt mode. */
9d5c8243
AK		 1415 igb_set_interrupt_capability(adapter);
1416
1417 if (igb_alloc_queues(adapter)) {
1418 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1419 return -ENOMEM;
1420 }
1421
1422 /* Explicitly disable IRQ since the NIC can be in any state. */
1423 igb_irq_disable(adapter);
1424
1425 set_bit(__IGB_DOWN, &adapter->state);
1426 return 0;
1427}
1428
1429/**
1430 * igb_open - Called when a network interface is made active
1431 * @netdev: network interface device structure
1432 *
1433 * Returns 0 on success, negative value on failure
1434 *
1435 * The open entry point is called when a network interface is made
1436 * active by the system (IFF_UP). At this point all resources needed
1437 * for transmit and receive operations are allocated, the interrupt
1438 * handler is registered with the OS, the watchdog timer is started,
1439 * and the stack is notified that the interface is ready.
1440 **/
1441static int igb_open(struct net_device *netdev)
1442{
1443 struct igb_adapter *adapter = netdev_priv(netdev);
1444 struct e1000_hw *hw = &adapter->hw;
1445 int err;
1446 int i;
1447
1448 /* disallow open during test */
1449 if (test_bit(__IGB_TESTING, &adapter->state))
1450 return -EBUSY;
1451
1452 /* allocate transmit descriptors */
1453 err = igb_setup_all_tx_resources(adapter);
1454 if (err)
1455 goto err_setup_tx;
1456
1457 /* allocate receive descriptors */
1458 err = igb_setup_all_rx_resources(adapter);
1459 if (err)
1460 goto err_setup_rx;
1461
1462 /* e1000_power_up_phy(adapter); */
1463
1464 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1465 if ((adapter->hw.mng_cookie.status &
1466 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1467 igb_update_mng_vlan(adapter);
1468
1469 /* before we allocate an interrupt, we must be ready to handle it.
1470 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1471 * as soon as we call pci_request_irq, so we have to setup our
1472 * clean_rx handler before we do so. */
1473 igb_configure(adapter);
1474
1475 err = igb_request_irq(adapter);
1476 if (err)
1477 goto err_req_irq;
1478
1479 /* From here on the code is the same as igb_up() */
1480 clear_bit(__IGB_DOWN, &adapter->state);
1481
844290e5
PW		 1482 for (i = 0; i < adapter->num_rx_queues; i++)
1483 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1484
1485 /* Clear any pending interrupts. */
1486 rd32(E1000_ICR);
844290e5
PW		 1487
1488 igb_irq_enable(adapter);
1489
d55b53ff
JK		 1490 netif_tx_start_all_queues(netdev);
1491
9d5c8243
AK		 1492 /* Fire a link status change interrupt to start the watchdog. */
1493 wr32(E1000_ICS, E1000_ICS_LSC);
1494
1495 return 0;
1496
1497err_req_irq:
1498 igb_release_hw_control(adapter);
1499 /* e1000_power_down_phy(adapter); */
1500 igb_free_all_rx_resources(adapter);
1501err_setup_rx:
1502 igb_free_all_tx_resources(adapter);
1503err_setup_tx:
1504 igb_reset(adapter);
1505
1506 return err;
1507}
1508
1509/**
1510 * igb_close - Disables a network interface
1511 * @netdev: network interface device structure
1512 *
1513 * Returns 0, this is not allowed to fail
1514 *
1515 * The close entry point is called when an interface is de-activated
1516 * by the OS. The hardware is still under the driver's control, but
1517 * needs to be disabled. A global MAC reset is issued to stop the
1518 * hardware, and all transmit and receive resources are freed.
1519 **/
1520static int igb_close(struct net_device *netdev)
1521{
1522 struct igb_adapter *adapter = netdev_priv(netdev);
1523
1524 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1525 igb_down(adapter);
1526
1527 igb_free_irq(adapter);
1528
1529 igb_free_all_tx_resources(adapter);
1530 igb_free_all_rx_resources(adapter);
1531
1532 /* kill manageability vlan ID if supported, but not if a vlan with
1533 * the same ID is registered on the host OS (let 8021q kill it) */
1534 if ((adapter->hw.mng_cookie.status &
1535 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1536 !(adapter->vlgrp &&
1537 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1538 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1539
1540 return 0;
1541}
1542
1543/**
1544 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1545 * @adapter: board private structure
1546 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1547 *
1548 * Return 0 on success, negative on failure
1549 **/
1550
1551int igb_setup_tx_resources(struct igb_adapter *adapter,
1552 struct igb_ring *tx_ring)
1553{
1554 struct pci_dev *pdev = adapter->pdev;
1555 int size;
1556
1557 size = sizeof(struct igb_buffer) * tx_ring->count;
1558 tx_ring->buffer_info = vmalloc(size);
1559 if (!tx_ring->buffer_info)
1560 goto err;
1561 memset(tx_ring->buffer_info, 0, size);
1562
1563 /* round up to nearest 4K */
1564 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1565 + sizeof(u32);
1566 tx_ring->size = ALIGN(tx_ring->size, 4096);
1567
1568 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1569 &tx_ring->dma);
1570
1571 if (!tx_ring->desc)
1572 goto err;
1573
1574 tx_ring->adapter = adapter;
1575 tx_ring->next_to_use = 0;
1576 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1577 return 0;
1578
1579err:
1580 vfree(tx_ring->buffer_info);
1581 dev_err(&adapter->pdev->dev,
1582 "Unable to allocate memory for the transmit descriptor ring\n");
1583 return -ENOMEM;
1584}
1585
1586/**
1587 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1588 * (Descriptors) for all queues
1589 * @adapter: board private structure
1590 *
1591 * Return 0 on success, negative on failure
1592 **/
1593static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1594{
1595 int i, err = 0;
661086df 1596 int r_idx;
9d5c8243
AK		 1597
1598 for (i = 0; i < adapter->num_tx_queues; i++) {
1599 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1600 if (err) {
1601 dev_err(&adapter->pdev->dev,
1602 "Allocation for Tx Queue %u failed\n", i);
1603 for (i--; i >= 0; i--)
3b644cf6 1604 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1605 break;
1606 }
1607 }
1608
661086df
PWJ		 1609 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1610 r_idx = i % adapter->num_tx_queues;
1611 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1612 }
9d5c8243
AK		 1613 return err;
1614}
1615
1616/**
1617 * igb_configure_tx - Configure transmit Unit after Reset
1618 * @adapter: board private structure
1619 *
1620 * Configure the Tx unit of the MAC after a reset.
1621 **/
1622static void igb_configure_tx(struct igb_adapter *adapter)
1623{
1624 u64 tdba, tdwba;
1625 struct e1000_hw *hw = &adapter->hw;
1626 u32 tctl;
1627 u32 txdctl, txctrl;
1628 int i;
1629
1630 for (i = 0; i < adapter->num_tx_queues; i++) {
1631 struct igb_ring *ring = &(adapter->tx_ring[i]);
1632
1633 wr32(E1000_TDLEN(i),
1634 ring->count * sizeof(struct e1000_tx_desc));
1635 tdba = ring->dma;
1636 wr32(E1000_TDBAL(i),
1637 tdba & 0x00000000ffffffffULL);
1638 wr32(E1000_TDBAH(i), tdba >> 32);
1639
1640 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1641 tdwba |= 1; /* enable head wb */
1642 wr32(E1000_TDWBAL(i),
1643 tdwba & 0x00000000ffffffffULL);
1644 wr32(E1000_TDWBAH(i), tdwba >> 32);
1645
1646 ring->head = E1000_TDH(i);
1647 ring->tail = E1000_TDT(i);
1648 writel(0, hw->hw_addr + ring->tail);
1649 writel(0, hw->hw_addr + ring->head);
1650 txdctl = rd32(E1000_TXDCTL(i));
1651 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1652 wr32(E1000_TXDCTL(i), txdctl);
1653
1654 /* Turn off Relaxed Ordering on head write-backs. The
1655 * writebacks MUST be delivered in order or it will
1656 * completely screw up our bookeeping.
1657 */
1658 txctrl = rd32(E1000_DCA_TXCTRL(i));
1659 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1660 wr32(E1000_DCA_TXCTRL(i), txctrl);
1661 }
1662
1663
1664
1665 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1666
1667 /* Program the Transmit Control Register */
1668
1669 tctl = rd32(E1000_TCTL);
1670 tctl &= ~E1000_TCTL_CT;
1671 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1672 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1673
1674 igb_config_collision_dist(hw);
1675
1676 /* Setup Transmit Descriptor Settings for eop descriptor */
1677 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1678
1679 /* Enable transmits */
1680 tctl |= E1000_TCTL_EN;
1681
1682 wr32(E1000_TCTL, tctl);
1683}
1684
1685/**
1686 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1687 * @adapter: board private structure
1688 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1689 *
1690 * Returns 0 on success, negative on failure
1691 **/
1692
1693int igb_setup_rx_resources(struct igb_adapter *adapter,
1694 struct igb_ring *rx_ring)
1695{
1696 struct pci_dev *pdev = adapter->pdev;
1697 int size, desc_len;
1698
d3352520
AD		 1699#ifdef CONFIG_IGB_LRO
1700 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1701 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1702 if (!rx_ring->lro_mgr.lro_arr)
1703 goto err;
1704 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1705#endif
1706
9d5c8243
AK		 1707 size = sizeof(struct igb_buffer) * rx_ring->count;
1708 rx_ring->buffer_info = vmalloc(size);
1709 if (!rx_ring->buffer_info)
1710 goto err;
1711 memset(rx_ring->buffer_info, 0, size);
1712
1713 desc_len = sizeof(union e1000_adv_rx_desc);
1714
1715 /* Round up to nearest 4K */
1716 rx_ring->size = rx_ring->count * desc_len;
1717 rx_ring->size = ALIGN(rx_ring->size, 4096);
1718
1719 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1720 &rx_ring->dma);
1721
1722 if (!rx_ring->desc)
1723 goto err;
1724
1725 rx_ring->next_to_clean = 0;
1726 rx_ring->next_to_use = 0;
9d5c8243
AK		 1727
1728 rx_ring->adapter = adapter;
9d5c8243
AK		 1729
1730 return 0;
1731
1732err:
d3352520
AD		 1733#ifdef CONFIG_IGB_LRO
1734 vfree(rx_ring->lro_mgr.lro_arr);
1735 rx_ring->lro_mgr.lro_arr = NULL;
1736#endif
9d5c8243
AK		 1737 vfree(rx_ring->buffer_info);
1738 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1739 "the receive descriptor ring\n");
1740 return -ENOMEM;
1741}
1742
1743/**
1744 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1745 * (Descriptors) for all queues
1746 * @adapter: board private structure
1747 *
1748 * Return 0 on success, negative on failure
1749 **/
1750static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1751{
1752 int i, err = 0;
1753
1754 for (i = 0; i < adapter->num_rx_queues; i++) {
1755 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1756 if (err) {
1757 dev_err(&adapter->pdev->dev,
1758 "Allocation for Rx Queue %u failed\n", i);
1759 for (i--; i >= 0; i--)
3b644cf6 1760 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1761 break;
1762 }
1763 }
1764
1765 return err;
1766}
1767
1768/**
1769 * igb_setup_rctl - configure the receive control registers
1770 * @adapter: Board private structure
1771 **/
1772static void igb_setup_rctl(struct igb_adapter *adapter)
1773{
1774 struct e1000_hw *hw = &adapter->hw;
1775 u32 rctl;
1776 u32 srrctl = 0;
1777 int i;
1778
1779 rctl = rd32(E1000_RCTL);
1780
1781 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1782 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1783
69d728ba 1784 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1785 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1786
87cb7e8c
AK		 1787 /*
1788 * enable stripping of CRC. It's unlikely this will break BMC
1789 * redirection as it did with e1000. Newer features require
1790 * that the HW strips the CRC.
9d5c8243 1791 */
87cb7e8c 1792 rctl |= E1000_RCTL_SECRC;
9d5c8243 1793
9b07f3d3
AD		 1794 /*
1795 * disable store bad packets, long packet enable, and clear size bits.
1796 */
1797 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_LPE | E1000_RCTL_SZ_256);
9d5c8243 1798
9b07f3d3 1799 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
9d5c8243 1800 /* Setup buffer sizes */
9d5c8243
AK		 1801 switch (adapter->rx_buffer_len) {
1802 case IGB_RXBUFFER_256:
1803 rctl |= E1000_RCTL_SZ_256;
9d5c8243
AK		 1804 break;
1805 case IGB_RXBUFFER_512:
1806 rctl |= E1000_RCTL_SZ_512;
9d5c8243
AK		 1807 break;
1808 case IGB_RXBUFFER_1024:
1809 rctl |= E1000_RCTL_SZ_1024;
9d5c8243 1810 break;
9d5c8243
AK		 1811 default:
1812 rctl |= E1000_RCTL_SZ_2048;
9d5c8243 1813 break;
9d5c8243
AK		 1814 }
1815 } else {
9b07f3d3 1816 rctl |= E1000_RCTL_LPE;
9d5c8243
AK		 1817 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1818 }
1819
1820 /* 82575 and greater support packet-split where the protocol
1821 * header is placed in skb->data and the packet data is
1822 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1823 * In the case of a non-split, skb->data is linearly filled,
1824 * followed by the page buffers. Therefore, skb->data is
1825 * sized to hold the largest protocol header.
1826 */
1827 /* allocations using alloc_page take too long for regular MTU
1828 * so only enable packet split for jumbo frames */
1829 if (rctl & E1000_RCTL_LPE) {
1830 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1831 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1832 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1833 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1834 } else {
1835 adapter->rx_ps_hdr_size = 0;
1836 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1837 }
1838
1839 for (i = 0; i < adapter->num_rx_queues; i++)
1840 wr32(E1000_SRRCTL(i), srrctl);
1841
1842 wr32(E1000_RCTL, rctl);
1843}
1844
1845/**
1846 * igb_configure_rx - Configure receive Unit after Reset
1847 * @adapter: board private structure
1848 *
1849 * Configure the Rx unit of the MAC after a reset.
1850 **/
1851static void igb_configure_rx(struct igb_adapter *adapter)
1852{
1853 u64 rdba;
1854 struct e1000_hw *hw = &adapter->hw;
1855 u32 rctl, rxcsum;
1856 u32 rxdctl;
1857 int i;
1858
1859 /* disable receives while setting up the descriptors */
1860 rctl = rd32(E1000_RCTL);
1861 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1862 wrfl();
1863 mdelay(10);
1864
1865 if (adapter->itr_setting > 3)
6eb5a7f1 1866 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1867
1868 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1869 * the Base and Length of the Rx Descriptor Ring */
1870 for (i = 0; i < adapter->num_rx_queues; i++) {
1871 struct igb_ring *ring = &(adapter->rx_ring[i]);
1872 rdba = ring->dma;
1873 wr32(E1000_RDBAL(i),
1874 rdba & 0x00000000ffffffffULL);
1875 wr32(E1000_RDBAH(i), rdba >> 32);
1876 wr32(E1000_RDLEN(i),
1877 ring->count * sizeof(union e1000_adv_rx_desc));
1878
1879 ring->head = E1000_RDH(i);
1880 ring->tail = E1000_RDT(i);
1881 writel(0, hw->hw_addr + ring->tail);
1882 writel(0, hw->hw_addr + ring->head);
1883
1884 rxdctl = rd32(E1000_RXDCTL(i));
1885 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1886 rxdctl &= 0xFFF00000;
1887 rxdctl |= IGB_RX_PTHRESH;
1888 rxdctl |= IGB_RX_HTHRESH << 8;
1889 rxdctl |= IGB_RX_WTHRESH << 16;
1890 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1891#ifdef CONFIG_IGB_LRO
1892 /* Intitial LRO Settings */
1893 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1894 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1895 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1896 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1897 ring->lro_mgr.dev = adapter->netdev;
1898 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1899 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1900#endif
9d5c8243
AK		 1901 }
1902
1903 if (adapter->num_rx_queues > 1) {
1904 u32 random[10];
1905 u32 mrqc;
1906 u32 j, shift;
1907 union e1000_reta {
1908 u32 dword;
1909 u8 bytes[4];
1910 } reta;
1911
1912 get_random_bytes(&random[0], 40);
1913
2d064c06
AD		 1914 if (hw->mac.type >= e1000_82576)
1915 shift = 0;
1916 else
1917 shift = 6;
9d5c8243
AK		 1918 for (j = 0; j < (32 * 4); j++) {
1919 reta.bytes[j & 3] =
1920 (j % adapter->num_rx_queues) << shift;
1921 if ((j & 3) == 3)
1922 writel(reta.dword,
1923 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1924 }
1925 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1926
1927 /* Fill out hash function seeds */
1928 for (j = 0; j < 10; j++)
1929 array_wr32(E1000_RSSRK(0), j, random[j]);
1930
1931 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1932 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1933 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1934 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1935 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1936 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1937 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1938 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1939
1940
1941 wr32(E1000_MRQC, mrqc);
1942
1943 /* Multiqueue and raw packet checksumming are mutually
1944 * exclusive. Note that this not the same as TCP/IP
1945 * checksumming, which works fine. */
1946 rxcsum = rd32(E1000_RXCSUM);
1947 rxcsum |= E1000_RXCSUM_PCSD;
1948 wr32(E1000_RXCSUM, rxcsum);
1949 } else {
1950 /* Enable Receive Checksum Offload for TCP and UDP */
1951 rxcsum = rd32(E1000_RXCSUM);
1952 if (adapter->rx_csum) {
1953 rxcsum |= E1000_RXCSUM_TUOFL;
1954
1955 /* Enable IPv4 payload checksum for UDP fragments
1956 * Must be used in conjunction with packet-split. */
1957 if (adapter->rx_ps_hdr_size)
1958 rxcsum |= E1000_RXCSUM_IPPCSE;
1959 } else {
1960 rxcsum &= ~E1000_RXCSUM_TUOFL;
1961 /* don't need to clear IPPCSE as it defaults to 0 */
1962 }
1963 wr32(E1000_RXCSUM, rxcsum);
1964 }
1965
1966 if (adapter->vlgrp)
1967 wr32(E1000_RLPML,
1968 adapter->max_frame_size + VLAN_TAG_SIZE);
1969 else
1970 wr32(E1000_RLPML, adapter->max_frame_size);
1971
1972 /* Enable Receives */
1973 wr32(E1000_RCTL, rctl);
1974}
1975
1976/**
1977 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1978 * @tx_ring: Tx descriptor ring for a specific queue
1979 *
1980 * Free all transmit software resources
1981 **/
68fd9910 1982void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1983{
3b644cf6 1984 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1985
3b644cf6 1986 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1987
1988 vfree(tx_ring->buffer_info);
1989 tx_ring->buffer_info = NULL;
1990
1991 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1992
1993 tx_ring->desc = NULL;
1994}
1995
1996/**
1997 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1998 * @adapter: board private structure
1999 *
2000 * Free all transmit software resources
2001 **/
2002static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2003{
2004 int i;
2005
2006 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2007 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2008}
2009
2010static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2011 struct igb_buffer *buffer_info)
2012{
2013 if (buffer_info->dma) {
2014 pci_unmap_page(adapter->pdev,
2015 buffer_info->dma,
2016 buffer_info->length,
2017 PCI_DMA_TODEVICE);
2018 buffer_info->dma = 0;
2019 }
2020 if (buffer_info->skb) {
2021 dev_kfree_skb_any(buffer_info->skb);
2022 buffer_info->skb = NULL;
2023 }
2024 buffer_info->time_stamp = 0;
2025 /* buffer_info must be completely set up in the transmit path */
2026}
2027
2028/**
2029 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2030 * @tx_ring: ring to be cleaned
2031 **/
3b644cf6 2032static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2033{
3b644cf6 2034 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2035 struct igb_buffer *buffer_info;
2036 unsigned long size;
2037 unsigned int i;
2038
2039 if (!tx_ring->buffer_info)
2040 return;
2041 /* Free all the Tx ring sk_buffs */
2042
2043 for (i = 0; i < tx_ring->count; i++) {
2044 buffer_info = &tx_ring->buffer_info[i];
2045 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2046 }
2047
2048 size = sizeof(struct igb_buffer) * tx_ring->count;
2049 memset(tx_ring->buffer_info, 0, size);
2050
2051 /* Zero out the descriptor ring */
2052
2053 memset(tx_ring->desc, 0, tx_ring->size);
2054
2055 tx_ring->next_to_use = 0;
2056 tx_ring->next_to_clean = 0;
2057
2058 writel(0, adapter->hw.hw_addr + tx_ring->head);
2059 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2060}
2061
2062/**
2063 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2064 * @adapter: board private structure
2065 **/
2066static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2067{
2068 int i;
2069
2070 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2071 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2072}
2073
2074/**
2075 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2076 * @rx_ring: ring to clean the resources from
2077 *
2078 * Free all receive software resources
2079 **/
68fd9910 2080void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2081{
3b644cf6 2082 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2083
3b644cf6 2084 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2085
2086 vfree(rx_ring->buffer_info);
2087 rx_ring->buffer_info = NULL;
2088
d3352520
AD		 2089#ifdef CONFIG_IGB_LRO
2090 vfree(rx_ring->lro_mgr.lro_arr);
2091 rx_ring->lro_mgr.lro_arr = NULL;
2092#endif
2093
9d5c8243
AK		 2094 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2095
2096 rx_ring->desc = NULL;
2097}
2098
2099/**
2100 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2101 * @adapter: board private structure
2102 *
2103 * Free all receive software resources
2104 **/
2105static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2106{
2107 int i;
2108
2109 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2110 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2111}
2112
2113/**
2114 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2115 * @rx_ring: ring to free buffers from
2116 **/
3b644cf6 2117static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2118{
3b644cf6 2119 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2120 struct igb_buffer *buffer_info;
2121 struct pci_dev *pdev = adapter->pdev;
2122 unsigned long size;
2123 unsigned int i;
2124
2125 if (!rx_ring->buffer_info)
2126 return;
2127 /* Free all the Rx ring sk_buffs */
2128 for (i = 0; i < rx_ring->count; i++) {
2129 buffer_info = &rx_ring->buffer_info[i];
2130 if (buffer_info->dma) {
2131 if (adapter->rx_ps_hdr_size)
2132 pci_unmap_single(pdev, buffer_info->dma,
2133 adapter->rx_ps_hdr_size,
2134 PCI_DMA_FROMDEVICE);
2135 else
2136 pci_unmap_single(pdev, buffer_info->dma,
2137 adapter->rx_buffer_len,
2138 PCI_DMA_FROMDEVICE);
2139 buffer_info->dma = 0;
2140 }
2141
2142 if (buffer_info->skb) {
2143 dev_kfree_skb(buffer_info->skb);
2144 buffer_info->skb = NULL;
2145 }
2146 if (buffer_info->page) {
bf36c1a0
AD		 2147 if (buffer_info->page_dma)
2148 pci_unmap_page(pdev, buffer_info->page_dma,
2149 PAGE_SIZE / 2,
2150 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2151 put_page(buffer_info->page);
2152 buffer_info->page = NULL;
2153 buffer_info->page_dma = 0;
bf36c1a0 2154 buffer_info->page_offset = 0;
9d5c8243
AK		 2155 }
2156 }
2157
9d5c8243
AK		 2158 size = sizeof(struct igb_buffer) * rx_ring->count;
2159 memset(rx_ring->buffer_info, 0, size);
2160
2161 /* Zero out the descriptor ring */
2162 memset(rx_ring->desc, 0, rx_ring->size);
2163
2164 rx_ring->next_to_clean = 0;
2165 rx_ring->next_to_use = 0;
2166
2167 writel(0, adapter->hw.hw_addr + rx_ring->head);
2168 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2169}
2170
2171/**
2172 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2173 * @adapter: board private structure
2174 **/
2175static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2176{
2177 int i;
2178
2179 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2180 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2181}
2182
2183/**
2184 * igb_set_mac - Change the Ethernet Address of the NIC
2185 * @netdev: network interface device structure
2186 * @p: pointer to an address structure
2187 *
2188 * Returns 0 on success, negative on failure
2189 **/
2190static int igb_set_mac(struct net_device *netdev, void *p)
2191{
2192 struct igb_adapter *adapter = netdev_priv(netdev);
2193 struct sockaddr *addr = p;
2194
2195 if (!is_valid_ether_addr(addr->sa_data))
2196 return -EADDRNOTAVAIL;
2197
2198 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2199 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2200
2201 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2202
2203 return 0;
2204}
2205
2206/**
2207 * igb_set_multi - Multicast and Promiscuous mode set
2208 * @netdev: network interface device structure
2209 *
2210 * The set_multi entry point is called whenever the multicast address
2211 * list or the network interface flags are updated. This routine is
2212 * responsible for configuring the hardware for proper multicast,
2213 * promiscuous mode, and all-multi behavior.
2214 **/
2215static void igb_set_multi(struct net_device *netdev)
2216{
2217 struct igb_adapter *adapter = netdev_priv(netdev);
2218 struct e1000_hw *hw = &adapter->hw;
2219 struct e1000_mac_info *mac = &hw->mac;
2220 struct dev_mc_list *mc_ptr;
2221 u8 *mta_list;
2222 u32 rctl;
2223 int i;
2224
2225 /* Check for Promiscuous and All Multicast modes */
2226
2227 rctl = rd32(E1000_RCTL);
2228
746b9f02 2229 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2230 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2231 rctl &= ~E1000_RCTL_VFE;
2232 } else {
2233 if (netdev->flags & IFF_ALLMULTI) {
2234 rctl |= E1000_RCTL_MPE;
2235 rctl &= ~E1000_RCTL_UPE;
2236 } else
2237 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2238 rctl |= E1000_RCTL_VFE;
746b9f02 2239 }
9d5c8243
AK		 2240 wr32(E1000_RCTL, rctl);
2241
2242 if (!netdev->mc_count) {
2243 /* nothing to program, so clear mc list */
2d064c06 2244 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2245 mac->rar_entry_count);
2246 return;
2247 }
2248
2249 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2250 if (!mta_list)
2251 return;
2252
2253 /* The shared function expects a packed array of only addresses. */
2254 mc_ptr = netdev->mc_list;
2255
2256 for (i = 0; i < netdev->mc_count; i++) {
2257 if (!mc_ptr)
2258 break;
2259 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2260 mc_ptr = mc_ptr->next;
2261 }
2d064c06
AD		 2262 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2263 mac->rar_entry_count);
9d5c8243
AK		 2264 kfree(mta_list);
2265}
2266
2267/* Need to wait a few seconds after link up to get diagnostic information from
2268 * the phy */
2269static void igb_update_phy_info(unsigned long data)
2270{
2271 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2272 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2273}
2274
2275/**
2276 * igb_watchdog - Timer Call-back
2277 * @data: pointer to adapter cast into an unsigned long
2278 **/
2279static void igb_watchdog(unsigned long data)
2280{
2281 struct igb_adapter *adapter = (struct igb_adapter *)data;
2282 /* Do the rest outside of interrupt context */
2283 schedule_work(&adapter->watchdog_task);
2284}
2285
2286static void igb_watchdog_task(struct work_struct *work)
2287{
2288 struct igb_adapter *adapter = container_of(work,
2289 struct igb_adapter, watchdog_task);
2290 struct e1000_hw *hw = &adapter->hw;
2291
2292 struct net_device *netdev = adapter->netdev;
2293 struct igb_ring *tx_ring = adapter->tx_ring;
2294 struct e1000_mac_info *mac = &adapter->hw.mac;
2295 u32 link;
7a6ea550 2296 u32 eics = 0;
9d5c8243 2297 s32 ret_val;
7a6ea550 2298 int i;
9d5c8243
AK		 2299
2300 if ((netif_carrier_ok(netdev)) &&
2301 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2302 goto link_up;
2303
2304 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2305 if ((ret_val == E1000_ERR_PHY) &&
2306 (hw->phy.type == e1000_phy_igp_3) &&
2307 (rd32(E1000_CTRL) &
2308 E1000_PHY_CTRL_GBE_DISABLE))
2309 dev_info(&adapter->pdev->dev,
2310 "Gigabit has been disabled, downgrading speed\n");
2311
2312 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2313 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2314 link = mac->serdes_has_link;
2315 else
2316 link = rd32(E1000_STATUS) &
2317 E1000_STATUS_LU;
2318
2319 if (link) {
2320 if (!netif_carrier_ok(netdev)) {
2321 u32 ctrl;
2322 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2323 &adapter->link_speed,
2324 &adapter->link_duplex);
2325
2326 ctrl = rd32(E1000_CTRL);
2327 dev_info(&adapter->pdev->dev,
2328 "NIC Link is Up %d Mbps %s, "
2329 "Flow Control: %s\n",
2330 adapter->link_speed,
2331 adapter->link_duplex == FULL_DUPLEX ?
2332 "Full Duplex" : "Half Duplex",
2333 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2334 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2335 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2336 E1000_CTRL_TFCE) ? "TX" : "None")));
2337
2338 /* tweak tx_queue_len according to speed/duplex and
2339 * adjust the timeout factor */
2340 netdev->tx_queue_len = adapter->tx_queue_len;
2341 adapter->tx_timeout_factor = 1;
2342 switch (adapter->link_speed) {
2343 case SPEED_10:
2344 netdev->tx_queue_len = 10;
2345 adapter->tx_timeout_factor = 14;
2346 break;
2347 case SPEED_100:
2348 netdev->tx_queue_len = 100;
2349 /* maybe add some timeout factor ? */
2350 break;
2351 }
2352
2353 netif_carrier_on(netdev);
fd2ea0a7 2354 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2355
2356 if (!test_bit(__IGB_DOWN, &adapter->state))
2357 mod_timer(&adapter->phy_info_timer,
2358 round_jiffies(jiffies + 2 * HZ));
2359 }
2360 } else {
2361 if (netif_carrier_ok(netdev)) {
2362 adapter->link_speed = 0;
2363 adapter->link_duplex = 0;
2364 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2365 netif_carrier_off(netdev);
fd2ea0a7 2366 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2367 if (!test_bit(__IGB_DOWN, &adapter->state))
2368 mod_timer(&adapter->phy_info_timer,
2369 round_jiffies(jiffies + 2 * HZ));
2370 }
2371 }
2372
2373link_up:
2374 igb_update_stats(adapter);
2375
2376 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2377 adapter->tpt_old = adapter->stats.tpt;
2378 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2379 adapter->colc_old = adapter->stats.colc;
2380
2381 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2382 adapter->gorc_old = adapter->stats.gorc;
2383 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2384 adapter->gotc_old = adapter->stats.gotc;
2385
2386 igb_update_adaptive(&adapter->hw);
2387
2388 if (!netif_carrier_ok(netdev)) {
2389 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2390 /* We've lost link, so the controller stops DMA,
2391 * but we've got queued Tx work that's never going
2392 * to get done, so reset controller to flush Tx.
2393 * (Do the reset outside of interrupt context). */
2394 adapter->tx_timeout_count++;
2395 schedule_work(&adapter->reset_task);
2396 }
2397 }
2398
2399 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2400 if (adapter->msix_entries) {
2401 for (i = 0; i < adapter->num_rx_queues; i++)
2402 eics |= adapter->rx_ring[i].eims_value;
2403 wr32(E1000_EICS, eics);
2404 } else {
2405 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2406 }
9d5c8243
AK		 2407
2408 /* Force detection of hung controller every watchdog period */
2409 tx_ring->detect_tx_hung = true;
2410
2411 /* Reset the timer */
2412 if (!test_bit(__IGB_DOWN, &adapter->state))
2413 mod_timer(&adapter->watchdog_timer,
2414 round_jiffies(jiffies + 2 * HZ));
2415}
2416
2417enum latency_range {
2418 lowest_latency = 0,
2419 low_latency = 1,
2420 bulk_latency = 2,
2421 latency_invalid = 255
2422};
2423
2424
6eb5a7f1
AD		 2425/**
2426 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2427 *
2428 * Stores a new ITR value based on strictly on packet size. This
2429 * algorithm is less sophisticated than that used in igb_update_itr,
2430 * due to the difficulty of synchronizing statistics across multiple
2431 * receive rings. The divisors and thresholds used by this fuction
2432 * were determined based on theoretical maximum wire speed and testing
2433 * data, in order to minimize response time while increasing bulk
2434 * throughput.
2435 * This functionality is controlled by the InterruptThrottleRate module
2436 * parameter (see igb_param.c)
2437 * NOTE: This function is called only when operating in a multiqueue
2438 * receive environment.
2439 * @rx_ring: pointer to ring
2440 **/
2441static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2442{
6eb5a7f1
AD		 2443 int new_val = rx_ring->itr_val;
2444 int avg_wire_size = 0;
2445 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2446
6eb5a7f1
AD		 2447 if (!rx_ring->total_packets)
2448 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2449
6eb5a7f1
AD		 2450 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2451 * ints/sec - ITR timer value of 120 ticks.
2452 */
2453 if (adapter->link_speed != SPEED_1000) {
2454 new_val = 120;
2455 goto set_itr_val;
9d5c8243 2456 }
6eb5a7f1 2457 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2458
6eb5a7f1
AD		 2459 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2460 avg_wire_size += 24;
2461
2462 /* Don't starve jumbo frames */
2463 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2464
6eb5a7f1
AD		 2465 /* Give a little boost to mid-size frames */
2466 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2467 new_val = avg_wire_size / 3;
2468 else
2469 new_val = avg_wire_size / 2;
9d5c8243 2470
6eb5a7f1 2471set_itr_val:
9d5c8243
AK		 2472 if (new_val != rx_ring->itr_val) {
2473 rx_ring->itr_val = new_val;
6eb5a7f1 2474 rx_ring->set_itr = 1;
9d5c8243 2475 }
6eb5a7f1
AD		 2476clear_counts:
2477 rx_ring->total_bytes = 0;
2478 rx_ring->total_packets = 0;
9d5c8243
AK		 2479}
2480
2481/**
2482 * igb_update_itr - update the dynamic ITR value based on statistics
2483 * Stores a new ITR value based on packets and byte
2484 * counts during the last interrupt. The advantage of per interrupt
2485 * computation is faster updates and more accurate ITR for the current
2486 * traffic pattern. Constants in this function were computed
2487 * based on theoretical maximum wire speed and thresholds were set based
2488 * on testing data as well as attempting to minimize response time
2489 * while increasing bulk throughput.
2490 * this functionality is controlled by the InterruptThrottleRate module
2491 * parameter (see igb_param.c)
2492 * NOTE: These calculations are only valid when operating in a single-
2493 * queue environment.
2494 * @adapter: pointer to adapter
2495 * @itr_setting: current adapter->itr
2496 * @packets: the number of packets during this measurement interval
2497 * @bytes: the number of bytes during this measurement interval
2498 **/
2499static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2500 int packets, int bytes)
2501{
2502 unsigned int retval = itr_setting;
2503
2504 if (packets == 0)
2505 goto update_itr_done;
2506
2507 switch (itr_setting) {
2508 case lowest_latency:
2509 /* handle TSO and jumbo frames */
2510 if (bytes/packets > 8000)
2511 retval = bulk_latency;
2512 else if ((packets < 5) && (bytes > 512))
2513 retval = low_latency;
2514 break;
2515 case low_latency: /* 50 usec aka 20000 ints/s */
2516 if (bytes > 10000) {
2517 /* this if handles the TSO accounting */
2518 if (bytes/packets > 8000) {
2519 retval = bulk_latency;
2520 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2521 retval = bulk_latency;
2522 } else if ((packets > 35)) {
2523 retval = lowest_latency;
2524 }
2525 } else if (bytes/packets > 2000) {
2526 retval = bulk_latency;
2527 } else if (packets <= 2 && bytes < 512) {
2528 retval = lowest_latency;
2529 }
2530 break;
2531 case bulk_latency: /* 250 usec aka 4000 ints/s */
2532 if (bytes > 25000) {
2533 if (packets > 35)
2534 retval = low_latency;
2535 } else if (bytes < 6000) {
2536 retval = low_latency;
2537 }
2538 break;
2539 }
2540
2541update_itr_done:
2542 return retval;
2543}
2544
6eb5a7f1 2545static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2546{
2547 u16 current_itr;
2548 u32 new_itr = adapter->itr;
2549
2550 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2551 if (adapter->link_speed != SPEED_1000) {
2552 current_itr = 0;
2553 new_itr = 4000;
2554 goto set_itr_now;
2555 }
2556
2557 adapter->rx_itr = igb_update_itr(adapter,
2558 adapter->rx_itr,
2559 adapter->rx_ring->total_packets,
2560 adapter->rx_ring->total_bytes);
9d5c8243 2561
6eb5a7f1 2562 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2563 adapter->tx_itr = igb_update_itr(adapter,
2564 adapter->tx_itr,
2565 adapter->tx_ring->total_packets,
2566 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2567
2568 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2569 } else {
2570 current_itr = adapter->rx_itr;
2571 }
2572
6eb5a7f1
AD		 2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2574 if (adapter->itr_setting == 3 &&
2575 current_itr == lowest_latency)
2576 current_itr = low_latency;
2577
9d5c8243
AK		 2578 switch (current_itr) {
2579 /* counts and packets in update_itr are dependent on these numbers */
2580 case lowest_latency:
2581 new_itr = 70000;
2582 break;
2583 case low_latency:
2584 new_itr = 20000; /* aka hwitr = ~200 */
2585 break;
2586 case bulk_latency:
2587 new_itr = 4000;
2588 break;
2589 default:
2590 break;
2591 }
2592
2593set_itr_now:
6eb5a7f1
AD		 2594 adapter->rx_ring->total_bytes = 0;
2595 adapter->rx_ring->total_packets = 0;
2596 if (adapter->rx_ring->buddy) {
2597 adapter->rx_ring->buddy->total_bytes = 0;
2598 adapter->rx_ring->buddy->total_packets = 0;
2599 }
2600
9d5c8243
AK		 2601 if (new_itr != adapter->itr) {
2602 /* this attempts to bias the interrupt rate towards Bulk
2603 * by adding intermediate steps when interrupt rate is
2604 * increasing */
2605 new_itr = new_itr > adapter->itr ?
2606 min(adapter->itr + (new_itr >> 2), new_itr) :
2607 new_itr;
2608 /* Don't write the value here; it resets the adapter's
2609 * internal timer, and causes us to delay far longer than
2610 * we should between interrupts. Instead, we write the ITR
2611 * value at the beginning of the next interrupt so the timing
2612 * ends up being correct.
2613 */
2614 adapter->itr = new_itr;
6eb5a7f1
AD		 2615 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2616 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2617 }
2618
2619 return;
2620}
2621
2622
2623#define IGB_TX_FLAGS_CSUM 0x00000001
2624#define IGB_TX_FLAGS_VLAN 0x00000002
2625#define IGB_TX_FLAGS_TSO 0x00000004
2626#define IGB_TX_FLAGS_IPV4 0x00000008
2627#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2628#define IGB_TX_FLAGS_VLAN_SHIFT 16
2629
2630static inline int igb_tso_adv(struct igb_adapter *adapter,
2631 struct igb_ring *tx_ring,
2632 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2633{
2634 struct e1000_adv_tx_context_desc *context_desc;
2635 unsigned int i;
2636 int err;
2637 struct igb_buffer *buffer_info;
2638 u32 info = 0, tu_cmd = 0;
2639 u32 mss_l4len_idx, l4len;
2640 *hdr_len = 0;
2641
2642 if (skb_header_cloned(skb)) {
2643 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2644 if (err)
2645 return err;
2646 }
2647
2648 l4len = tcp_hdrlen(skb);
2649 *hdr_len += l4len;
2650
2651 if (skb->protocol == htons(ETH_P_IP)) {
2652 struct iphdr *iph = ip_hdr(skb);
2653 iph->tot_len = 0;
2654 iph->check = 0;
2655 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2656 iph->daddr, 0,
2657 IPPROTO_TCP,
2658 0);
2659 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2660 ipv6_hdr(skb)->payload_len = 0;
2661 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2662 &ipv6_hdr(skb)->daddr,
2663 0, IPPROTO_TCP, 0);
2664 }
2665
2666 i = tx_ring->next_to_use;
2667
2668 buffer_info = &tx_ring->buffer_info[i];
2669 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2670 /* VLAN MACLEN IPLEN */
2671 if (tx_flags & IGB_TX_FLAGS_VLAN)
2672 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2673 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2674 *hdr_len += skb_network_offset(skb);
2675 info |= skb_network_header_len(skb);
2676 *hdr_len += skb_network_header_len(skb);
2677 context_desc->vlan_macip_lens = cpu_to_le32(info);
2678
2679 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2680 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2681
2682 if (skb->protocol == htons(ETH_P_IP))
2683 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2684 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2685
2686 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2687
2688 /* MSS L4LEN IDX */
2689 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2690 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2691
7dfc16fa
AD		 2692 /* Context index must be unique per ring. */
2693 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2694 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2695
2696 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2697 context_desc->seqnum_seed = 0;
2698
2699 buffer_info->time_stamp = jiffies;
2700 buffer_info->dma = 0;
2701 i++;
2702 if (i == tx_ring->count)
2703 i = 0;
2704
2705 tx_ring->next_to_use = i;
2706
2707 return true;
2708}
2709
2710static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2711 struct igb_ring *tx_ring,
2712 struct sk_buff *skb, u32 tx_flags)
2713{
2714 struct e1000_adv_tx_context_desc *context_desc;
2715 unsigned int i;
2716 struct igb_buffer *buffer_info;
2717 u32 info = 0, tu_cmd = 0;
2718
2719 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2720 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2721 i = tx_ring->next_to_use;
2722 buffer_info = &tx_ring->buffer_info[i];
2723 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2724
2725 if (tx_flags & IGB_TX_FLAGS_VLAN)
2726 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2727 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2728 if (skb->ip_summed == CHECKSUM_PARTIAL)
2729 info |= skb_network_header_len(skb);
2730
2731 context_desc->vlan_macip_lens = cpu_to_le32(info);
2732
2733 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2734
2735 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2736 switch (skb->protocol) {
2737 case __constant_htons(ETH_P_IP):
9d5c8243 2738 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2739 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2740 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2741 break;
2742 case __constant_htons(ETH_P_IPV6):
2743 /* XXX what about other V6 headers?? */
2744 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2745 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2746 break;
2747 default:
2748 if (unlikely(net_ratelimit()))
2749 dev_warn(&adapter->pdev->dev,
2750 "partial checksum but proto=%x!\n",
2751 skb->protocol);
2752 break;
2753 }
9d5c8243
AK		 2754 }
2755
2756 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2757 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2758 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2759 context_desc->mss_l4len_idx =
2760 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2761
2762 buffer_info->time_stamp = jiffies;
2763 buffer_info->dma = 0;
2764
2765 i++;
2766 if (i == tx_ring->count)
2767 i = 0;
2768 tx_ring->next_to_use = i;
2769
2770 return true;
2771 }
2772
2773
2774 return false;
2775}
2776
2777#define IGB_MAX_TXD_PWR 16
2778#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2779
2780static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2781 struct igb_ring *tx_ring,
2782 struct sk_buff *skb)
2783{
2784 struct igb_buffer *buffer_info;
2785 unsigned int len = skb_headlen(skb);
2786 unsigned int count = 0, i;
2787 unsigned int f;
2788
2789 i = tx_ring->next_to_use;
2790
2791 buffer_info = &tx_ring->buffer_info[i];
2792 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2793 buffer_info->length = len;
2794 /* set time_stamp *before* dma to help avoid a possible race */
2795 buffer_info->time_stamp = jiffies;
2796 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2797 PCI_DMA_TODEVICE);
2798 count++;
2799 i++;
2800 if (i == tx_ring->count)
2801 i = 0;
2802
2803 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2804 struct skb_frag_struct *frag;
2805
2806 frag = &skb_shinfo(skb)->frags[f];
2807 len = frag->size;
2808
2809 buffer_info = &tx_ring->buffer_info[i];
2810 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2811 buffer_info->length = len;
2812 buffer_info->time_stamp = jiffies;
2813 buffer_info->dma = pci_map_page(adapter->pdev,
2814 frag->page,
2815 frag->page_offset,
2816 len,
2817 PCI_DMA_TODEVICE);
2818
2819 count++;
2820 i++;
2821 if (i == tx_ring->count)
2822 i = 0;
2823 }
2824
2825 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2826 tx_ring->buffer_info[i].skb = skb;
2827
2828 return count;
2829}
2830
2831static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2832 struct igb_ring *tx_ring,
2833 int tx_flags, int count, u32 paylen,
2834 u8 hdr_len)
2835{
2836 union e1000_adv_tx_desc *tx_desc = NULL;
2837 struct igb_buffer *buffer_info;
2838 u32 olinfo_status = 0, cmd_type_len;
2839 unsigned int i;
2840
2841 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2842 E1000_ADVTXD_DCMD_DEXT);
2843
2844 if (tx_flags & IGB_TX_FLAGS_VLAN)
2845 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2846
2847 if (tx_flags & IGB_TX_FLAGS_TSO) {
2848 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2849
2850 /* insert tcp checksum */
2851 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2852
2853 /* insert ip checksum */
2854 if (tx_flags & IGB_TX_FLAGS_IPV4)
2855 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2856
2857 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2858 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2859 }
2860
7dfc16fa
AD		 2861 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2862 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2863 IGB_TX_FLAGS_VLAN)))
661086df 2864 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2865
2866 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2867
2868 i = tx_ring->next_to_use;
2869 while (count--) {
2870 buffer_info = &tx_ring->buffer_info[i];
2871 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2872 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2873 tx_desc->read.cmd_type_len =
2874 cpu_to_le32(cmd_type_len | buffer_info->length);
2875 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2876 i++;
2877 if (i == tx_ring->count)
2878 i = 0;
2879 }
2880
2881 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2882 /* Force memory writes to complete before letting h/w
2883 * know there are new descriptors to fetch. (Only
2884 * applicable for weak-ordered memory model archs,
2885 * such as IA-64). */
2886 wmb();
2887
2888 tx_ring->next_to_use = i;
2889 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2890 /* we need this if more than one processor can write to our tail
2891 * at a time, it syncronizes IO on IA64/Altix systems */
2892 mmiowb();
2893}
2894
2895static int __igb_maybe_stop_tx(struct net_device *netdev,
2896 struct igb_ring *tx_ring, int size)
2897{
2898 struct igb_adapter *adapter = netdev_priv(netdev);
2899
661086df 2900 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2901
9d5c8243
AK		 2902 /* Herbert's original patch had:
2903 * smp_mb__after_netif_stop_queue();
2904 * but since that doesn't exist yet, just open code it. */
2905 smp_mb();
2906
2907 /* We need to check again in a case another CPU has just
2908 * made room available. */
2909 if (IGB_DESC_UNUSED(tx_ring) < size)
2910 return -EBUSY;
2911
2912 /* A reprieve! */
661086df 2913 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2914 ++adapter->restart_queue;
2915 return 0;
2916}
2917
2918static int igb_maybe_stop_tx(struct net_device *netdev,
2919 struct igb_ring *tx_ring, int size)
2920{
2921 if (IGB_DESC_UNUSED(tx_ring) >= size)
2922 return 0;
2923 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2924}
2925
2926#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2927
2928static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2929 struct net_device *netdev,
2930 struct igb_ring *tx_ring)
2931{
2932 struct igb_adapter *adapter = netdev_priv(netdev);
2933 unsigned int tx_flags = 0;
2934 unsigned int len;
9d5c8243
AK		 2935 u8 hdr_len = 0;
2936 int tso = 0;
2937
2938 len = skb_headlen(skb);
2939
2940 if (test_bit(__IGB_DOWN, &adapter->state)) {
2941 dev_kfree_skb_any(skb);
2942 return NETDEV_TX_OK;
2943 }
2944
2945 if (skb->len <= 0) {
2946 dev_kfree_skb_any(skb);
2947 return NETDEV_TX_OK;
2948 }
2949
9d5c8243
AK		 2950 /* need: 1 descriptor per page,
2951 * + 2 desc gap to keep tail from touching head,
2952 * + 1 desc for skb->data,
2953 * + 1 desc for context descriptor,
2954 * otherwise try next time */
2955 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2956 /* this is a hard error */
9d5c8243
AK		 2957 return NETDEV_TX_BUSY;
2958 }
6eb5a7f1 2959 skb_orphan(skb);
9d5c8243
AK		 2960
2961 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2962 tx_flags |= IGB_TX_FLAGS_VLAN;
2963 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2964 }
2965
661086df
PWJ		 2966 if (skb->protocol == htons(ETH_P_IP))
2967 tx_flags |= IGB_TX_FLAGS_IPV4;
2968
9d5c8243
AK		 2969 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2970 &hdr_len) : 0;
2971
2972 if (tso < 0) {
2973 dev_kfree_skb_any(skb);
9d5c8243
AK		 2974 return NETDEV_TX_OK;
2975 }
2976
2977 if (tso)
2978 tx_flags |= IGB_TX_FLAGS_TSO;
2979 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2980 if (skb->ip_summed == CHECKSUM_PARTIAL)
2981 tx_flags |= IGB_TX_FLAGS_CSUM;
2982
9d5c8243
AK		 2983 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2984 igb_tx_map_adv(adapter, tx_ring, skb),
2985 skb->len, hdr_len);
2986
2987 netdev->trans_start = jiffies;
2988
2989 /* Make sure there is space in the ring for the next send. */
2990 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2991
9d5c8243
AK		 2992 return NETDEV_TX_OK;
2993}
2994
2995static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2996{
2997 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 2998 struct igb_ring *tx_ring;
2999
661086df
PWJ		 3000 int r_idx = 0;
3001 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3002 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3003
3004 /* This goes back to the question of how to logically map a tx queue
3005 * to a flow. Right now, performance is impacted slightly negatively
3006 * if using multiple tx queues. If the stack breaks away from a
3007 * single qdisc implementation, we can look at this again. */
3008 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3009}
3010
3011/**
3012 * igb_tx_timeout - Respond to a Tx Hang
3013 * @netdev: network interface device structure
3014 **/
3015static void igb_tx_timeout(struct net_device *netdev)
3016{
3017 struct igb_adapter *adapter = netdev_priv(netdev);
3018 struct e1000_hw *hw = &adapter->hw;
3019
3020 /* Do the reset outside of interrupt context */
3021 adapter->tx_timeout_count++;
3022 schedule_work(&adapter->reset_task);
3023 wr32(E1000_EICS, adapter->eims_enable_mask &
3024 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3025}
3026
3027static void igb_reset_task(struct work_struct *work)
3028{
3029 struct igb_adapter *adapter;
3030 adapter = container_of(work, struct igb_adapter, reset_task);
3031
3032 igb_reinit_locked(adapter);
3033}
3034
3035/**
3036 * igb_get_stats - Get System Network Statistics
3037 * @netdev: network interface device structure
3038 *
3039 * Returns the address of the device statistics structure.
3040 * The statistics are actually updated from the timer callback.
3041 **/
3042static struct net_device_stats *
3043igb_get_stats(struct net_device *netdev)
3044{
3045 struct igb_adapter *adapter = netdev_priv(netdev);
3046
3047 /* only return the current stats */
3048 return &adapter->net_stats;
3049}
3050
3051/**
3052 * igb_change_mtu - Change the Maximum Transfer Unit
3053 * @netdev: network interface device structure
3054 * @new_mtu: new value for maximum frame size
3055 *
3056 * Returns 0 on success, negative on failure
3057 **/
3058static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3059{
3060 struct igb_adapter *adapter = netdev_priv(netdev);
3061 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3062
3063 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3064 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3065 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3066 return -EINVAL;
3067 }
3068
3069#define MAX_STD_JUMBO_FRAME_SIZE 9234
3070 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3071 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3072 return -EINVAL;
3073 }
3074
3075 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3076 msleep(1);
3077 /* igb_down has a dependency on max_frame_size */
3078 adapter->max_frame_size = max_frame;
3079 if (netif_running(netdev))
3080 igb_down(adapter);
3081
3082 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3083 * means we reserve 2 more, this pushes us to allocate from the next
3084 * larger slab size.
3085 * i.e. RXBUFFER_2048 --> size-4096 slab
3086 */
3087
3088 if (max_frame <= IGB_RXBUFFER_256)
3089 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3090 else if (max_frame <= IGB_RXBUFFER_512)
3091 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3092 else if (max_frame <= IGB_RXBUFFER_1024)
3093 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3094 else if (max_frame <= IGB_RXBUFFER_2048)
3095 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3096 else
bf36c1a0
AD		 3097#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3098 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3099#else
3100 adapter->rx_buffer_len = PAGE_SIZE / 2;
3101#endif
9d5c8243
AK		 3102 /* adjust allocation if LPE protects us, and we aren't using SBP */
3103 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3104 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3105 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3106
3107 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3108 netdev->mtu, new_mtu);
3109 netdev->mtu = new_mtu;
3110
3111 if (netif_running(netdev))
3112 igb_up(adapter);
3113 else
3114 igb_reset(adapter);
3115
3116 clear_bit(__IGB_RESETTING, &adapter->state);
3117
3118 return 0;
3119}
3120
3121/**
3122 * igb_update_stats - Update the board statistics counters
3123 * @adapter: board private structure
3124 **/
3125
3126void igb_update_stats(struct igb_adapter *adapter)
3127{
3128 struct e1000_hw *hw = &adapter->hw;
3129 struct pci_dev *pdev = adapter->pdev;
3130 u16 phy_tmp;
3131
3132#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3133
3134 /*
3135 * Prevent stats update while adapter is being reset, or if the pci
3136 * connection is down.
3137 */
3138 if (adapter->link_speed == 0)
3139 return;
3140 if (pci_channel_offline(pdev))
3141 return;
3142
3143 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3144 adapter->stats.gprc += rd32(E1000_GPRC);
3145 adapter->stats.gorc += rd32(E1000_GORCL);
3146 rd32(E1000_GORCH); /* clear GORCL */
3147 adapter->stats.bprc += rd32(E1000_BPRC);
3148 adapter->stats.mprc += rd32(E1000_MPRC);
3149 adapter->stats.roc += rd32(E1000_ROC);
3150
3151 adapter->stats.prc64 += rd32(E1000_PRC64);
3152 adapter->stats.prc127 += rd32(E1000_PRC127);
3153 adapter->stats.prc255 += rd32(E1000_PRC255);
3154 adapter->stats.prc511 += rd32(E1000_PRC511);
3155 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3156 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3157 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3158 adapter->stats.sec += rd32(E1000_SEC);
3159
3160 adapter->stats.mpc += rd32(E1000_MPC);
3161 adapter->stats.scc += rd32(E1000_SCC);
3162 adapter->stats.ecol += rd32(E1000_ECOL);
3163 adapter->stats.mcc += rd32(E1000_MCC);
3164 adapter->stats.latecol += rd32(E1000_LATECOL);
3165 adapter->stats.dc += rd32(E1000_DC);
3166 adapter->stats.rlec += rd32(E1000_RLEC);
3167 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3168 adapter->stats.xontxc += rd32(E1000_XONTXC);
3169 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3170 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3171 adapter->stats.fcruc += rd32(E1000_FCRUC);
3172 adapter->stats.gptc += rd32(E1000_GPTC);
3173 adapter->stats.gotc += rd32(E1000_GOTCL);
3174 rd32(E1000_GOTCH); /* clear GOTCL */
3175 adapter->stats.rnbc += rd32(E1000_RNBC);
3176 adapter->stats.ruc += rd32(E1000_RUC);
3177 adapter->stats.rfc += rd32(E1000_RFC);
3178 adapter->stats.rjc += rd32(E1000_RJC);
3179 adapter->stats.tor += rd32(E1000_TORH);
3180 adapter->stats.tot += rd32(E1000_TOTH);
3181 adapter->stats.tpr += rd32(E1000_TPR);
3182
3183 adapter->stats.ptc64 += rd32(E1000_PTC64);
3184 adapter->stats.ptc127 += rd32(E1000_PTC127);
3185 adapter->stats.ptc255 += rd32(E1000_PTC255);
3186 adapter->stats.ptc511 += rd32(E1000_PTC511);
3187 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3188 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3189
3190 adapter->stats.mptc += rd32(E1000_MPTC);
3191 adapter->stats.bptc += rd32(E1000_BPTC);
3192
3193 /* used for adaptive IFS */
3194
3195 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3196 adapter->stats.tpt += hw->mac.tx_packet_delta;
3197 hw->mac.collision_delta = rd32(E1000_COLC);
3198 adapter->stats.colc += hw->mac.collision_delta;
3199
3200 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3201 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3202 adapter->stats.tncrs += rd32(E1000_TNCRS);
3203 adapter->stats.tsctc += rd32(E1000_TSCTC);
3204 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3205
3206 adapter->stats.iac += rd32(E1000_IAC);
3207 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3208 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3209 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3210 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3211 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3212 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3213 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3214 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3215
3216 /* Fill out the OS statistics structure */
3217 adapter->net_stats.multicast = adapter->stats.mprc;
3218 adapter->net_stats.collisions = adapter->stats.colc;
3219
3220 /* Rx Errors */
3221
3222 /* RLEC on some newer hardware can be incorrect so build
3223 * our own version based on RUC and ROC */
3224 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3225 adapter->stats.crcerrs + adapter->stats.algnerrc +
3226 adapter->stats.ruc + adapter->stats.roc +
3227 adapter->stats.cexterr;
3228 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3229 adapter->stats.roc;
3230 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3231 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3232 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3233
3234 /* Tx Errors */
3235 adapter->net_stats.tx_errors = adapter->stats.ecol +
3236 adapter->stats.latecol;
3237 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3238 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3239 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3240
3241 /* Tx Dropped needs to be maintained elsewhere */
3242
3243 /* Phy Stats */
3244 if (hw->phy.media_type == e1000_media_type_copper) {
3245 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3246 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3247 &phy_tmp))) {
3248 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3249 adapter->phy_stats.idle_errors += phy_tmp;
3250 }
3251 }
3252
3253 /* Management Stats */
3254 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3255 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3256 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3257}
3258
3259
3260static irqreturn_t igb_msix_other(int irq, void *data)
3261{
3262 struct net_device *netdev = data;
3263 struct igb_adapter *adapter = netdev_priv(netdev);
3264 struct e1000_hw *hw = &adapter->hw;
844290e5 3265 u32 icr = rd32(E1000_ICR);
9d5c8243 3266
844290e5
PW		 3267 /* reading ICR causes bit 31 of EICR to be cleared */
3268 if (!(icr & E1000_ICR_LSC))
3269 goto no_link_interrupt;
3270 hw->mac.get_link_status = 1;
3271 /* guard against interrupt when we're going down */
3272 if (!test_bit(__IGB_DOWN, &adapter->state))
3273 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3274
9d5c8243
AK		 3275no_link_interrupt:
3276 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3277 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3278
3279 return IRQ_HANDLED;
3280}
3281
3282static irqreturn_t igb_msix_tx(int irq, void *data)
3283{
3284 struct igb_ring *tx_ring = data;
3285 struct igb_adapter *adapter = tx_ring->adapter;
3286 struct e1000_hw *hw = &adapter->hw;
3287
421e02f0 3288#ifdef CONFIG_IGB_DCA
7dfc16fa 3289 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3290 igb_update_tx_dca(tx_ring);
3291#endif
9d5c8243
AK		 3292 tx_ring->total_bytes = 0;
3293 tx_ring->total_packets = 0;
661086df
PWJ		 3294
3295 /* auto mask will automatically reenable the interrupt when we write
3296 * EICS */
3b644cf6 3297 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3298 /* Ring was not completely cleaned, so fire another interrupt */
3299 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3300 else
9d5c8243 3301 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3302
9d5c8243
AK		 3303 return IRQ_HANDLED;
3304}
3305
6eb5a7f1
AD		 3306static void igb_write_itr(struct igb_ring *ring)
3307{
3308 struct e1000_hw *hw = &ring->adapter->hw;
3309 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3310 switch (hw->mac.type) {
3311 case e1000_82576:
3312 wr32(ring->itr_register,
3313 ring->itr_val |
3314 0x80000000);
3315 break;
3316 default:
3317 wr32(ring->itr_register,
3318 ring->itr_val |
3319 (ring->itr_val << 16));
3320 break;
3321 }
3322 ring->set_itr = 0;
3323 }
3324}
3325
9d5c8243
AK		 3326static irqreturn_t igb_msix_rx(int irq, void *data)
3327{
3328 struct igb_ring *rx_ring = data;
3329 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3330
844290e5
PW		 3331 /* Write the ITR value calculated at the end of the
3332 * previous interrupt.
3333 */
9d5c8243 3334
6eb5a7f1 3335 igb_write_itr(rx_ring);
9d5c8243 3336
844290e5
PW		 3337 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3338 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3339
421e02f0 3340#ifdef CONFIG_IGB_DCA
7dfc16fa 3341 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3342 igb_update_rx_dca(rx_ring);
3343#endif
3344 return IRQ_HANDLED;
3345}
3346
421e02f0 3347#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3348static void igb_update_rx_dca(struct igb_ring *rx_ring)
3349{
3350 u32 dca_rxctrl;
3351 struct igb_adapter *adapter = rx_ring->adapter;
3352 struct e1000_hw *hw = &adapter->hw;
3353 int cpu = get_cpu();
3354 int q = rx_ring - adapter->rx_ring;
3355
3356 if (rx_ring->cpu != cpu) {
3357 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3358 if (hw->mac.type == e1000_82576) {
3359 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3360 dca_rxctrl |= dca_get_tag(cpu) <<
3361 E1000_DCA_RXCTRL_CPUID_SHIFT;
3362 } else {
3363 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3364 dca_rxctrl |= dca_get_tag(cpu);
3365 }
fe4506b6
JC		 3366 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3367 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3368 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3369 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3370 rx_ring->cpu = cpu;
3371 }
3372 put_cpu();
3373}
3374
3375static void igb_update_tx_dca(struct igb_ring *tx_ring)
3376{
3377 u32 dca_txctrl;
3378 struct igb_adapter *adapter = tx_ring->adapter;
3379 struct e1000_hw *hw = &adapter->hw;
3380 int cpu = get_cpu();
3381 int q = tx_ring - adapter->tx_ring;
3382
3383 if (tx_ring->cpu != cpu) {
3384 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3385 if (hw->mac.type == e1000_82576) {
3386 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3387 dca_txctrl |= dca_get_tag(cpu) <<
3388 E1000_DCA_TXCTRL_CPUID_SHIFT;
3389 } else {
3390 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3391 dca_txctrl |= dca_get_tag(cpu);
3392 }
fe4506b6
JC		 3393 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3394 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3395 tx_ring->cpu = cpu;
3396 }
3397 put_cpu();
3398}
3399
3400static void igb_setup_dca(struct igb_adapter *adapter)
3401{
3402 int i;
3403
7dfc16fa 3404 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3405 return;
3406
3407 for (i = 0; i < adapter->num_tx_queues; i++) {
3408 adapter->tx_ring[i].cpu = -1;
3409 igb_update_tx_dca(&adapter->tx_ring[i]);
3410 }
3411 for (i = 0; i < adapter->num_rx_queues; i++) {
3412 adapter->rx_ring[i].cpu = -1;
3413 igb_update_rx_dca(&adapter->rx_ring[i]);
3414 }
3415}
3416
3417static int __igb_notify_dca(struct device *dev, void *data)
3418{
3419 struct net_device *netdev = dev_get_drvdata(dev);
3420 struct igb_adapter *adapter = netdev_priv(netdev);
3421 struct e1000_hw *hw = &adapter->hw;
3422 unsigned long event = *(unsigned long *)data;
3423
7dfc16fa
AD		 3424 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3425 goto out;
3426
fe4506b6
JC		 3427 switch (event) {
3428 case DCA_PROVIDER_ADD:
3429 /* if already enabled, don't do it again */
7dfc16fa 3430 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3431 break;
7dfc16fa 3432 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3433 /* Always use CB2 mode, difference is masked
3434 * in the CB driver. */
3435 wr32(E1000_DCA_CTRL, 2);
3436 if (dca_add_requester(dev) == 0) {
3437 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3438 igb_setup_dca(adapter);
3439 break;
3440 }
3441 /* Fall Through since DCA is disabled. */
3442 case DCA_PROVIDER_REMOVE:
7dfc16fa 3443 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3444 /* without this a class_device is left
3445 * hanging around in the sysfs model */
3446 dca_remove_requester(dev);
3447 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3448 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3449 wr32(E1000_DCA_CTRL, 1);
3450 }
3451 break;
3452 }
7dfc16fa 3453out:
fe4506b6 3454 return 0;
9d5c8243
AK		 3455}
3456
fe4506b6
JC		 3457static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3458 void *p)
3459{
3460 int ret_val;
3461
3462 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3463 __igb_notify_dca);
3464
3465 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3466}
421e02f0 3467#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3468
3469/**
3470 * igb_intr_msi - Interrupt Handler
3471 * @irq: interrupt number
3472 * @data: pointer to a network interface device structure
3473 **/
3474static irqreturn_t igb_intr_msi(int irq, void *data)
3475{
3476 struct net_device *netdev = data;
3477 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3478 struct e1000_hw *hw = &adapter->hw;
3479 /* read ICR disables interrupts using IAM */
3480 u32 icr = rd32(E1000_ICR);
3481
6eb5a7f1 3482 igb_write_itr(adapter->rx_ring);
9d5c8243 3483
9d5c8243
AK		 3484 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3485 hw->mac.get_link_status = 1;
3486 if (!test_bit(__IGB_DOWN, &adapter->state))
3487 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3488 }
3489
844290e5 3490 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3491
3492 return IRQ_HANDLED;
3493}
3494
3495/**
3496 * igb_intr - Interrupt Handler
3497 * @irq: interrupt number
3498 * @data: pointer to a network interface device structure
3499 **/
3500static irqreturn_t igb_intr(int irq, void *data)
3501{
3502 struct net_device *netdev = data;
3503 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3504 struct e1000_hw *hw = &adapter->hw;
3505 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3506 * need for the IMC write */
3507 u32 icr = rd32(E1000_ICR);
3508 u32 eicr = 0;
3509 if (!icr)
3510 return IRQ_NONE; /* Not our interrupt */
3511
6eb5a7f1 3512 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3513
3514 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3515 * not set, then the adapter didn't send an interrupt */
3516 if (!(icr & E1000_ICR_INT_ASSERTED))
3517 return IRQ_NONE;
3518
3519 eicr = rd32(E1000_EICR);
3520
3521 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3522 hw->mac.get_link_status = 1;
3523 /* guard against interrupt when we're going down */
3524 if (!test_bit(__IGB_DOWN, &adapter->state))
3525 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3526 }
3527
844290e5 3528 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3529
3530 return IRQ_HANDLED;
3531}
3532
3533/**
661086df
PWJ		 3534 * igb_poll - NAPI Rx polling callback
3535 * @napi: napi polling structure
3536 * @budget: count of how many packets we should handle
9d5c8243 3537 **/
661086df 3538static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3539{
661086df
PWJ		 3540 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3541 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3542 struct net_device *netdev = adapter->netdev;
661086df 3543 int tx_clean_complete, work_done = 0;
9d5c8243 3544
661086df 3545 /* this poll routine only supports one tx and one rx queue */
421e02f0 3546#ifdef CONFIG_IGB_DCA
7dfc16fa 3547 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3548 igb_update_tx_dca(&adapter->tx_ring[0]);
3549#endif
661086df 3550 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3551
421e02f0 3552#ifdef CONFIG_IGB_DCA
7dfc16fa 3553 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3554 igb_update_rx_dca(&adapter->rx_ring[0]);
3555#endif
661086df 3556 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3557
3558 /* If no Tx and not enough Rx work done, exit the polling mode */
3559 if ((tx_clean_complete && (work_done < budget)) ||
3560 !netif_running(netdev)) {
9d5c8243 3561 if (adapter->itr_setting & 3)
6eb5a7f1 3562 igb_set_itr(adapter);
9d5c8243
AK		 3563 netif_rx_complete(netdev, napi);
3564 if (!test_bit(__IGB_DOWN, &adapter->state))
3565 igb_irq_enable(adapter);
3566 return 0;
3567 }
3568
3569 return 1;
3570}
3571
3572static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3573{
3574 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3575 struct igb_adapter *adapter = rx_ring->adapter;
3576 struct e1000_hw *hw = &adapter->hw;
3577 struct net_device *netdev = adapter->netdev;
3578 int work_done = 0;
3579
421e02f0 3580#ifdef CONFIG_IGB_DCA
7dfc16fa 3581 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3582 igb_update_rx_dca(rx_ring);
3583#endif
3b644cf6 3584 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3585
3586
3587 /* If not enough Rx work done, exit the polling mode */
3588 if ((work_done == 0) || !netif_running(netdev)) {
9d5c8243
AK		 3589 netif_rx_complete(netdev, napi);
3590
6eb5a7f1
AD		 3591 if (adapter->itr_setting & 3) {
3592 if (adapter->num_rx_queues == 1)
3593 igb_set_itr(adapter);
3594 else
3595 igb_update_ring_itr(rx_ring);
9d5c8243 3596 }
844290e5
PW		 3597
3598 if (!test_bit(__IGB_DOWN, &adapter->state))
3599 wr32(E1000_EIMS, rx_ring->eims_value);
3600
9d5c8243
AK		 3601 return 0;
3602 }
3603
3604 return 1;
3605}
6d8126f9
AV		 3606
3607static inline u32 get_head(struct igb_ring *tx_ring)
3608{
3609 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3610 return le32_to_cpu(*(volatile __le32 *)end);
3611}
3612
9d5c8243
AK		 3613/**
3614 * igb_clean_tx_irq - Reclaim resources after transmit completes
3615 * @adapter: board private structure
3616 * returns true if ring is completely cleaned
3617 **/
3b644cf6 3618static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3619{
3b644cf6 3620 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3621 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3622 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3623 struct e1000_tx_desc *tx_desc;
3624 struct igb_buffer *buffer_info;
3625 struct sk_buff *skb;
3626 unsigned int i;
3627 u32 head, oldhead;
3628 unsigned int count = 0;
9d5c8243 3629 unsigned int total_bytes = 0, total_packets = 0;
fc7d345d 3630 bool retval = true;
9d5c8243
AK		 3631
3632 rmb();
6d8126f9 3633 head = get_head(tx_ring);
9d5c8243
AK		 3634 i = tx_ring->next_to_clean;
3635 while (1) {
3636 while (i != head) {
9d5c8243
AK		 3637 tx_desc = E1000_TX_DESC(*tx_ring, i);
3638 buffer_info = &tx_ring->buffer_info[i];
3639 skb = buffer_info->skb;
3640
3641 if (skb) {
3642 unsigned int segs, bytecount;
3643 /* gso_segs is currently only valid for tcp */
3644 segs = skb_shinfo(skb)->gso_segs ?: 1;
3645 /* multiply data chunks by size of headers */
3646 bytecount = ((segs - 1) * skb_headlen(skb)) +
3647 skb->len;
3648 total_packets += segs;
3649 total_bytes += bytecount;
3650 }
3651
3652 igb_unmap_and_free_tx_resource(adapter, buffer_info);
9d5c8243
AK		 3653
3654 i++;
3655 if (i == tx_ring->count)
3656 i = 0;
3657
3658 count++;
3659 if (count == IGB_MAX_TX_CLEAN) {
3660 retval = false;
3661 goto done_cleaning;
3662 }
3663 }
3664 oldhead = head;
3665 rmb();
6d8126f9 3666 head = get_head(tx_ring);
9d5c8243
AK		 3667 if (head == oldhead)
3668 goto done_cleaning;
3669 } /* while (1) */
3670
3671done_cleaning:
3672 tx_ring->next_to_clean = i;
3673
fc7d345d 3674 if (unlikely(count &&
9d5c8243
AK		 3675 netif_carrier_ok(netdev) &&
3676 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3677 /* Make sure that anybody stopping the queue after this
3678 * sees the new next_to_clean.
3679 */
3680 smp_mb();
661086df
PWJ		 3681 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3682 !(test_bit(__IGB_DOWN, &adapter->state))) {
3683 netif_wake_subqueue(netdev, tx_ring->queue_index);
3684 ++adapter->restart_queue;
3685 }
9d5c8243
AK		 3686 }
3687
3688 if (tx_ring->detect_tx_hung) {
3689 /* Detect a transmit hang in hardware, this serializes the
3690 * check with the clearing of time_stamp and movement of i */
3691 tx_ring->detect_tx_hung = false;
3692 if (tx_ring->buffer_info[i].time_stamp &&
3693 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3694 (adapter->tx_timeout_factor * HZ))
3695 && !(rd32(E1000_STATUS) &
3696 E1000_STATUS_TXOFF)) {
3697
3698 tx_desc = E1000_TX_DESC(*tx_ring, i);
3699 /* detected Tx unit hang */
3700 dev_err(&adapter->pdev->dev,
3701 "Detected Tx Unit Hang\n"
2d064c06 3702 " Tx Queue <%d>\n"
9d5c8243
AK		 3703 " TDH <%x>\n"
3704 " TDT <%x>\n"
3705 " next_to_use <%x>\n"
3706 " next_to_clean <%x>\n"
3707 " head (WB) <%x>\n"
3708 "buffer_info[next_to_clean]\n"
3709 " time_stamp <%lx>\n"
3710 " jiffies <%lx>\n"
3711 " desc.status <%x>\n",
2d064c06 3712 tx_ring->queue_index,
9d5c8243
AK		 3713 readl(adapter->hw.hw_addr + tx_ring->head),
3714 readl(adapter->hw.hw_addr + tx_ring->tail),
3715 tx_ring->next_to_use,
3716 tx_ring->next_to_clean,
3717 head,
3718 tx_ring->buffer_info[i].time_stamp,
3719 jiffies,
3720 tx_desc->upper.fields.status);
661086df 3721 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3722 }
3723 }
3724 tx_ring->total_bytes += total_bytes;
3725 tx_ring->total_packets += total_packets;
e21ed353
AD		 3726 tx_ring->tx_stats.bytes += total_bytes;
3727 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3728 adapter->net_stats.tx_bytes += total_bytes;
3729 adapter->net_stats.tx_packets += total_packets;
3730 return retval;
3731}
3732
d3352520
AD		 3733#ifdef CONFIG_IGB_LRO
3734 /**
3735 * igb_get_skb_hdr - helper function for LRO header processing
3736 * @skb: pointer to sk_buff to be added to LRO packet
3737 * @iphdr: pointer to ip header structure
3738 * @tcph: pointer to tcp header structure
3739 * @hdr_flags: pointer to header flags
3740 * @priv: pointer to the receive descriptor for the current sk_buff
3741 **/
3742static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3743 u64 *hdr_flags, void *priv)
3744{
3745 union e1000_adv_rx_desc *rx_desc = priv;
3746 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3747 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3748
3749 /* Verify that this is a valid IPv4 TCP packet */
3750 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3751 E1000_RXDADV_PKTTYPE_TCP))
3752 return -1;
3753
3754 /* Set network headers */
3755 skb_reset_network_header(skb);
3756 skb_set_transport_header(skb, ip_hdrlen(skb));
3757 *iphdr = ip_hdr(skb);
3758 *tcph = tcp_hdr(skb);
3759 *hdr_flags = LRO_IPV4 | LRO_TCP;
3760
3761 return 0;
3762
3763}
3764#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3765
3766/**
3767 * igb_receive_skb - helper function to handle rx indications
d3352520 3768 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3769 * @status: descriptor status field as written by hardware
3770 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3771 * @skb: pointer to sk_buff to be indicated to stack
3772 **/
d3352520
AD		 3773static void igb_receive_skb(struct igb_ring *ring, u8 status,
3774 union e1000_adv_rx_desc * rx_desc,
3775 struct sk_buff *skb)
3776{
3777 struct igb_adapter * adapter = ring->adapter;
3778 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3779
3780#ifdef CONFIG_IGB_LRO
3781 if (adapter->netdev->features & NETIF_F_LRO &&
3782 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3783 if (vlan_extracted)
3784 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3785 adapter->vlgrp,
3786 le16_to_cpu(rx_desc->wb.upper.vlan),
3787 rx_desc);
3788 else
3789 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3790 ring->lro_used = 1;
3791 } else {
3792#endif
3793 if (vlan_extracted)
3794 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3795 le16_to_cpu(rx_desc->wb.upper.vlan));
3796 else
3797
3798 netif_receive_skb(skb);
3799#ifdef CONFIG_IGB_LRO
3800 }
3801#endif
9d5c8243
AK		 3802}
3803
3804
3805static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3806 u32 status_err, struct sk_buff *skb)
3807{
3808 skb->ip_summed = CHECKSUM_NONE;
3809
3810 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3811 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3812 return;
3813 /* TCP/UDP checksum error bit is set */
3814 if (status_err &
3815 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3816 /* let the stack verify checksum errors */
3817 adapter->hw_csum_err++;
3818 return;
3819 }
3820 /* It must be a TCP or UDP packet with a valid checksum */
3821 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3822 skb->ip_summed = CHECKSUM_UNNECESSARY;
3823
3824 adapter->hw_csum_good++;
3825}
3826
3b644cf6
MW		 3827static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3828 int *work_done, int budget)
9d5c8243 3829{
3b644cf6 3830 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3831 struct net_device *netdev = adapter->netdev;
3832 struct pci_dev *pdev = adapter->pdev;
3833 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3834 struct igb_buffer *buffer_info , *next_buffer;
3835 struct sk_buff *skb;
bf36c1a0 3836 unsigned int i;
9d5c8243
AK		 3837 u32 length, hlen, staterr;
3838 bool cleaned = false;
3839 int cleaned_count = 0;
3840 unsigned int total_bytes = 0, total_packets = 0;
3841
3842 i = rx_ring->next_to_clean;
3843 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3844 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3845
3846 while (staterr & E1000_RXD_STAT_DD) {
3847 if (*work_done >= budget)
3848 break;
3849 (*work_done)++;
3850 buffer_info = &rx_ring->buffer_info[i];
3851
3852 /* HW will not DMA in data larger than the given buffer, even
3853 * if it parses the (NFS, of course) header to be larger. In
3854 * that case, it fills the header buffer and spills the rest
3855 * into the page.
3856 */
7deb07b1
AV		 3857 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3858 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3859 if (hlen > adapter->rx_ps_hdr_size)
3860 hlen = adapter->rx_ps_hdr_size;
3861
3862 length = le16_to_cpu(rx_desc->wb.upper.length);
3863 cleaned = true;
3864 cleaned_count++;
3865
bf36c1a0
AD		 3866 skb = buffer_info->skb;
3867 prefetch(skb->data - NET_IP_ALIGN);
3868 buffer_info->skb = NULL;
3869 if (!adapter->rx_ps_hdr_size) {
3870 pci_unmap_single(pdev, buffer_info->dma,
3871 adapter->rx_buffer_len +
3872 NET_IP_ALIGN,
3873 PCI_DMA_FROMDEVICE);
3874 skb_put(skb, length);
3875 goto send_up;
9d5c8243
AK		 3876 }
3877
bf36c1a0
AD		 3878 if (!skb_shinfo(skb)->nr_frags) {
3879 pci_unmap_single(pdev, buffer_info->dma,
3880 adapter->rx_ps_hdr_size +
3881 NET_IP_ALIGN,
3882 PCI_DMA_FROMDEVICE);
3883 skb_put(skb, hlen);
3884 }
3885
3886 if (length) {
9d5c8243 3887 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3888 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3889 buffer_info->page_dma = 0;
bf36c1a0
AD		 3890
3891 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3892 buffer_info->page,
3893 buffer_info->page_offset,
3894 length);
3895
3896 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3897 (page_count(buffer_info->page) != 1))
3898 buffer_info->page = NULL;
3899 else
3900 get_page(buffer_info->page);
9d5c8243
AK		 3901
3902 skb->len += length;
3903 skb->data_len += length;
9d5c8243 3904
bf36c1a0 3905 skb->truesize += length;
9d5c8243
AK		 3906 }
3907send_up:
9d5c8243
AK		 3908 i++;
3909 if (i == rx_ring->count)
3910 i = 0;
3911 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3912 prefetch(next_rxd);
3913 next_buffer = &rx_ring->buffer_info[i];
3914
bf36c1a0 3915 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3916 buffer_info->skb = next_buffer->skb;
3917 buffer_info->dma = next_buffer->dma;
3918 next_buffer->skb = skb;
3919 next_buffer->dma = 0;
bf36c1a0
AD		 3920 goto next_desc;
3921 }
3922
9d5c8243
AK		 3923 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3924 dev_kfree_skb_irq(skb);
3925 goto next_desc;
3926 }
9d5c8243
AK		 3927
3928 total_bytes += skb->len;
3929 total_packets++;
3930
3931 igb_rx_checksum_adv(adapter, staterr, skb);
3932
3933 skb->protocol = eth_type_trans(skb, netdev);
3934
d3352520 3935 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3936
9d5c8243
AK		 3937next_desc:
3938 rx_desc->wb.upper.status_error = 0;
3939
3940 /* return some buffers to hardware, one at a time is too slow */
3941 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3942 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3943 cleaned_count = 0;
3944 }
3945
3946 /* use prefetched values */
3947 rx_desc = next_rxd;
3948 buffer_info = next_buffer;
3949
3950 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3951 }
bf36c1a0 3952
9d5c8243
AK		 3953 rx_ring->next_to_clean = i;
3954 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3955
d3352520
AD		 3956#ifdef CONFIG_IGB_LRO
3957 if (rx_ring->lro_used) {
3958 lro_flush_all(&rx_ring->lro_mgr);
3959 rx_ring->lro_used = 0;
3960 }
3961#endif
3962
9d5c8243 3963 if (cleaned_count)
3b644cf6 3964 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3965
3966 rx_ring->total_packets += total_packets;
3967 rx_ring->total_bytes += total_bytes;
3968 rx_ring->rx_stats.packets += total_packets;
3969 rx_ring->rx_stats.bytes += total_bytes;
3970 adapter->net_stats.rx_bytes += total_bytes;
3971 adapter->net_stats.rx_packets += total_packets;
3972 return cleaned;
3973}
3974
3975
3976/**
3977 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3978 * @adapter: address of board private structure
3979 **/
3b644cf6 3980static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3981 int cleaned_count)
3982{
3b644cf6 3983 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3984 struct net_device *netdev = adapter->netdev;
3985 struct pci_dev *pdev = adapter->pdev;
3986 union e1000_adv_rx_desc *rx_desc;
3987 struct igb_buffer *buffer_info;
3988 struct sk_buff *skb;
3989 unsigned int i;
3990
3991 i = rx_ring->next_to_use;
3992 buffer_info = &rx_ring->buffer_info[i];
3993
3994 while (cleaned_count--) {
3995 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3996
bf36c1a0 3997 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3998 if (!buffer_info->page) {
bf36c1a0
AD		 3999 buffer_info->page = alloc_page(GFP_ATOMIC);
4000 if (!buffer_info->page) {
4001 adapter->alloc_rx_buff_failed++;
4002 goto no_buffers;
4003 }
4004 buffer_info->page_offset = 0;
4005 } else {
4006 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4007 }
4008 buffer_info->page_dma =
4009 pci_map_page(pdev,
4010 buffer_info->page,
bf36c1a0
AD		 4011 buffer_info->page_offset,
4012 PAGE_SIZE / 2,
9d5c8243
AK		 4013 PCI_DMA_FROMDEVICE);
4014 }
4015
4016 if (!buffer_info->skb) {
4017 int bufsz;
4018
4019 if (adapter->rx_ps_hdr_size)
4020 bufsz = adapter->rx_ps_hdr_size;
4021 else
4022 bufsz = adapter->rx_buffer_len;
4023 bufsz += NET_IP_ALIGN;
4024 skb = netdev_alloc_skb(netdev, bufsz);
4025
4026 if (!skb) {
4027 adapter->alloc_rx_buff_failed++;
4028 goto no_buffers;
4029 }
4030
4031 /* Make buffer alignment 2 beyond a 16 byte boundary
4032 * this will result in a 16 byte aligned IP header after
4033 * the 14 byte MAC header is removed
4034 */
4035 skb_reserve(skb, NET_IP_ALIGN);
4036
4037 buffer_info->skb = skb;
4038 buffer_info->dma = pci_map_single(pdev, skb->data,
4039 bufsz,
4040 PCI_DMA_FROMDEVICE);
4041
4042 }
4043 /* Refresh the desc even if buffer_addrs didn't change because
4044 * each write-back erases this info. */
4045 if (adapter->rx_ps_hdr_size) {
4046 rx_desc->read.pkt_addr =
4047 cpu_to_le64(buffer_info->page_dma);
4048 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4049 } else {
4050 rx_desc->read.pkt_addr =
4051 cpu_to_le64(buffer_info->dma);
4052 rx_desc->read.hdr_addr = 0;
4053 }
4054
4055 i++;
4056 if (i == rx_ring->count)
4057 i = 0;
4058 buffer_info = &rx_ring->buffer_info[i];
4059 }
4060
4061no_buffers:
4062 if (rx_ring->next_to_use != i) {
4063 rx_ring->next_to_use = i;
4064 if (i == 0)
4065 i = (rx_ring->count - 1);
4066 else
4067 i--;
4068
4069 /* Force memory writes to complete before letting h/w
4070 * know there are new descriptors to fetch. (Only
4071 * applicable for weak-ordered memory model archs,
4072 * such as IA-64). */
4073 wmb();
4074 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4075 }
4076}
4077
4078/**
4079 * igb_mii_ioctl -
4080 * @netdev:
4081 * @ifreq:
4082 * @cmd:
4083 **/
4084static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4085{
4086 struct igb_adapter *adapter = netdev_priv(netdev);
4087 struct mii_ioctl_data *data = if_mii(ifr);
4088
4089 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4090 return -EOPNOTSUPP;
4091
4092 switch (cmd) {
4093 case SIOCGMIIPHY:
4094 data->phy_id = adapter->hw.phy.addr;
4095 break;
4096 case SIOCGMIIREG:
4097 if (!capable(CAP_NET_ADMIN))
4098 return -EPERM;
f5f4cf08
AD		 4099 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4100 &data->val_out))
9d5c8243
AK		 4101 return -EIO;
4102 break;
4103 case SIOCSMIIREG:
4104 default:
4105 return -EOPNOTSUPP;
4106 }
4107 return 0;
4108}
4109
4110/**
4111 * igb_ioctl -
4112 * @netdev:
4113 * @ifreq:
4114 * @cmd:
4115 **/
4116static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4117{
4118 switch (cmd) {
4119 case SIOCGMIIPHY:
4120 case SIOCGMIIREG:
4121 case SIOCSMIIREG:
4122 return igb_mii_ioctl(netdev, ifr, cmd);
4123 default:
4124 return -EOPNOTSUPP;
4125 }
4126}
4127
4128static void igb_vlan_rx_register(struct net_device *netdev,
4129 struct vlan_group *grp)
4130{
4131 struct igb_adapter *adapter = netdev_priv(netdev);
4132 struct e1000_hw *hw = &adapter->hw;
4133 u32 ctrl, rctl;
4134
4135 igb_irq_disable(adapter);
4136 adapter->vlgrp = grp;
4137
4138 if (grp) {
4139 /* enable VLAN tag insert/strip */
4140 ctrl = rd32(E1000_CTRL);
4141 ctrl |= E1000_CTRL_VME;
4142 wr32(E1000_CTRL, ctrl);
4143
4144 /* enable VLAN receive filtering */
4145 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4146 rctl &= ~E1000_RCTL_CFIEN;
4147 wr32(E1000_RCTL, rctl);
4148 igb_update_mng_vlan(adapter);
4149 wr32(E1000_RLPML,
4150 adapter->max_frame_size + VLAN_TAG_SIZE);
4151 } else {
4152 /* disable VLAN tag insert/strip */
4153 ctrl = rd32(E1000_CTRL);
4154 ctrl &= ~E1000_CTRL_VME;
4155 wr32(E1000_CTRL, ctrl);
4156
9d5c8243
AK		 4157 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4158 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4159 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4160 }
4161 wr32(E1000_RLPML,
4162 adapter->max_frame_size);
4163 }
4164
4165 if (!test_bit(__IGB_DOWN, &adapter->state))
4166 igb_irq_enable(adapter);
4167}
4168
4169static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4170{
4171 struct igb_adapter *adapter = netdev_priv(netdev);
4172 struct e1000_hw *hw = &adapter->hw;
4173 u32 vfta, index;
4174
4175 if ((adapter->hw.mng_cookie.status &
4176 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4177 (vid == adapter->mng_vlan_id))
4178 return;
4179 /* add VID to filter table */
4180 index = (vid >> 5) & 0x7F;
4181 vfta = array_rd32(E1000_VFTA, index);
4182 vfta |= (1 << (vid & 0x1F));
4183 igb_write_vfta(&adapter->hw, index, vfta);
4184}
4185
4186static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4187{
4188 struct igb_adapter *adapter = netdev_priv(netdev);
4189 struct e1000_hw *hw = &adapter->hw;
4190 u32 vfta, index;
4191
4192 igb_irq_disable(adapter);
4193 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4194
4195 if (!test_bit(__IGB_DOWN, &adapter->state))
4196 igb_irq_enable(adapter);
4197
4198 if ((adapter->hw.mng_cookie.status &
4199 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4200 (vid == adapter->mng_vlan_id)) {
4201 /* release control to f/w */
4202 igb_release_hw_control(adapter);
4203 return;
4204 }
4205
4206 /* remove VID from filter table */
4207 index = (vid >> 5) & 0x7F;
4208 vfta = array_rd32(E1000_VFTA, index);
4209 vfta &= ~(1 << (vid & 0x1F));
4210 igb_write_vfta(&adapter->hw, index, vfta);
4211}
4212
4213static void igb_restore_vlan(struct igb_adapter *adapter)
4214{
4215 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4216
4217 if (adapter->vlgrp) {
4218 u16 vid;
4219 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4220 if (!vlan_group_get_device(adapter->vlgrp, vid))
4221 continue;
4222 igb_vlan_rx_add_vid(adapter->netdev, vid);
4223 }
4224 }
4225}
4226
4227int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4228{
4229 struct e1000_mac_info *mac = &adapter->hw.mac;
4230
4231 mac->autoneg = 0;
4232
4233 /* Fiber NICs only allow 1000 gbps Full duplex */
4234 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4235 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4236 dev_err(&adapter->pdev->dev,
4237 "Unsupported Speed/Duplex configuration\n");
4238 return -EINVAL;
4239 }
4240
4241 switch (spddplx) {
4242 case SPEED_10 + DUPLEX_HALF:
4243 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4244 break;
4245 case SPEED_10 + DUPLEX_FULL:
4246 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4247 break;
4248 case SPEED_100 + DUPLEX_HALF:
4249 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4250 break;
4251 case SPEED_100 + DUPLEX_FULL:
4252 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4253 break;
4254 case SPEED_1000 + DUPLEX_FULL:
4255 mac->autoneg = 1;
4256 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4257 break;
4258 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4259 default:
4260 dev_err(&adapter->pdev->dev,
4261 "Unsupported Speed/Duplex configuration\n");
4262 return -EINVAL;
4263 }
4264 return 0;
4265}
4266
4267
4268static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4269{
4270 struct net_device *netdev = pci_get_drvdata(pdev);
4271 struct igb_adapter *adapter = netdev_priv(netdev);
4272 struct e1000_hw *hw = &adapter->hw;
2d064c06 4273 u32 ctrl, rctl, status;
9d5c8243
AK		 4274 u32 wufc = adapter->wol;
4275#ifdef CONFIG_PM
4276 int retval = 0;
4277#endif
4278
4279 netif_device_detach(netdev);
4280
a88f10ec
AD		 4281 if (netif_running(netdev))
4282 igb_close(netdev);
4283
4284 igb_reset_interrupt_capability(adapter);
4285
4286 igb_free_queues(adapter);
9d5c8243
AK		 4287
4288#ifdef CONFIG_PM
4289 retval = pci_save_state(pdev);
4290 if (retval)
4291 return retval;
4292#endif
4293
4294 status = rd32(E1000_STATUS);
4295 if (status & E1000_STATUS_LU)
4296 wufc &= ~E1000_WUFC_LNKC;
4297
4298 if (wufc) {
4299 igb_setup_rctl(adapter);
4300 igb_set_multi(netdev);
4301
4302 /* turn on all-multi mode if wake on multicast is enabled */
4303 if (wufc & E1000_WUFC_MC) {
4304 rctl = rd32(E1000_RCTL);
4305 rctl |= E1000_RCTL_MPE;
4306 wr32(E1000_RCTL, rctl);
4307 }
4308
4309 ctrl = rd32(E1000_CTRL);
4310 /* advertise wake from D3Cold */
4311 #define E1000_CTRL_ADVD3WUC 0x00100000
4312 /* phy power management enable */
4313 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4314 ctrl |= E1000_CTRL_ADVD3WUC;
4315 wr32(E1000_CTRL, ctrl);
4316
9d5c8243
AK		 4317 /* Allow time for pending master requests to run */
4318 igb_disable_pcie_master(&adapter->hw);
4319
4320 wr32(E1000_WUC, E1000_WUC_PME_EN);
4321 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4322 } else {
4323 wr32(E1000_WUC, 0);
4324 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4325 }
4326
2d064c06
AD		 4327 /* make sure adapter isn't asleep if manageability/wol is enabled */
4328 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4329 pci_enable_wake(pdev, PCI_D3hot, 1);
4330 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4331 } else {
4332 igb_shutdown_fiber_serdes_link_82575(hw);
4333 pci_enable_wake(pdev, PCI_D3hot, 0);
4334 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4335 }
4336
4337 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4338 * would have already happened in close and is redundant. */
4339 igb_release_hw_control(adapter);
4340
4341 pci_disable_device(pdev);
4342
4343 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4344
4345 return 0;
4346}
4347
4348#ifdef CONFIG_PM
4349static int igb_resume(struct pci_dev *pdev)
4350{
4351 struct net_device *netdev = pci_get_drvdata(pdev);
4352 struct igb_adapter *adapter = netdev_priv(netdev);
4353 struct e1000_hw *hw = &adapter->hw;
4354 u32 err;
4355
4356 pci_set_power_state(pdev, PCI_D0);
4357 pci_restore_state(pdev);
42bfd33a
TI		 4358
4359 if (adapter->need_ioport)
4360 err = pci_enable_device(pdev);
4361 else
4362 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4363 if (err) {
4364 dev_err(&pdev->dev,
4365 "igb: Cannot enable PCI device from suspend\n");
4366 return err;
4367 }
4368 pci_set_master(pdev);
4369
4370 pci_enable_wake(pdev, PCI_D3hot, 0);
4371 pci_enable_wake(pdev, PCI_D3cold, 0);
4372
a88f10ec
AD		 4373 igb_set_interrupt_capability(adapter);
4374
4375 if (igb_alloc_queues(adapter)) {
4376 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4377 return -ENOMEM;
9d5c8243
AK		 4378 }
4379
4380 /* e1000_power_up_phy(adapter); */
4381
4382 igb_reset(adapter);
4383 wr32(E1000_WUS, ~0);
4384
a88f10ec
AD		 4385 if (netif_running(netdev)) {
4386 err = igb_open(netdev);
4387 if (err)
4388 return err;
4389 }
9d5c8243
AK		 4390
4391 netif_device_attach(netdev);
4392
4393 /* let the f/w know that the h/w is now under the control of the
4394 * driver. */
4395 igb_get_hw_control(adapter);
4396
4397 return 0;
4398}
4399#endif
4400
4401static void igb_shutdown(struct pci_dev *pdev)
4402{
4403 igb_suspend(pdev, PMSG_SUSPEND);
4404}
4405
4406#ifdef CONFIG_NET_POLL_CONTROLLER
4407/*
4408 * Polling 'interrupt' - used by things like netconsole to send skbs
4409 * without having to re-enable interrupts. It's not called while
4410 * the interrupt routine is executing.
4411 */
4412static void igb_netpoll(struct net_device *netdev)
4413{
4414 struct igb_adapter *adapter = netdev_priv(netdev);
4415 int i;
4416 int work_done = 0;
4417
4418 igb_irq_disable(adapter);
7dfc16fa
AD		 4419 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4420
9d5c8243 4421 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4422 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4423
4424 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4425 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4426 &work_done,
4427 adapter->rx_ring[i].napi.weight);
4428
7dfc16fa 4429 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4430 igb_irq_enable(adapter);
4431}
4432#endif /* CONFIG_NET_POLL_CONTROLLER */
4433
4434/**
4435 * igb_io_error_detected - called when PCI error is detected
4436 * @pdev: Pointer to PCI device
4437 * @state: The current pci connection state
4438 *
4439 * This function is called after a PCI bus error affecting
4440 * this device has been detected.
4441 */
4442static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4443 pci_channel_state_t state)
4444{
4445 struct net_device *netdev = pci_get_drvdata(pdev);
4446 struct igb_adapter *adapter = netdev_priv(netdev);
4447
4448 netif_device_detach(netdev);
4449
4450 if (netif_running(netdev))
4451 igb_down(adapter);
4452 pci_disable_device(pdev);
4453
4454 /* Request a slot slot reset. */
4455 return PCI_ERS_RESULT_NEED_RESET;
4456}
4457
4458/**
4459 * igb_io_slot_reset - called after the pci bus has been reset.
4460 * @pdev: Pointer to PCI device
4461 *
4462 * Restart the card from scratch, as if from a cold-boot. Implementation
4463 * resembles the first-half of the igb_resume routine.
4464 */
4465static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4466{
4467 struct net_device *netdev = pci_get_drvdata(pdev);
4468 struct igb_adapter *adapter = netdev_priv(netdev);
4469 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4470 int err;
9d5c8243 4471
42bfd33a
TI		 4472 if (adapter->need_ioport)
4473 err = pci_enable_device(pdev);
4474 else
4475 err = pci_enable_device_mem(pdev);
4476 if (err) {
9d5c8243
AK		 4477 dev_err(&pdev->dev,
4478 "Cannot re-enable PCI device after reset.\n");
4479 return PCI_ERS_RESULT_DISCONNECT;
4480 }
4481 pci_set_master(pdev);
c682fc23 4482 pci_restore_state(pdev);
9d5c8243
AK		 4483
4484 pci_enable_wake(pdev, PCI_D3hot, 0);
4485 pci_enable_wake(pdev, PCI_D3cold, 0);
4486
4487 igb_reset(adapter);
4488 wr32(E1000_WUS, ~0);
4489
4490 return PCI_ERS_RESULT_RECOVERED;
4491}
4492
4493/**
4494 * igb_io_resume - called when traffic can start flowing again.
4495 * @pdev: Pointer to PCI device
4496 *
4497 * This callback is called when the error recovery driver tells us that
4498 * its OK to resume normal operation. Implementation resembles the
4499 * second-half of the igb_resume routine.
4500 */
4501static void igb_io_resume(struct pci_dev *pdev)
4502{
4503 struct net_device *netdev = pci_get_drvdata(pdev);
4504 struct igb_adapter *adapter = netdev_priv(netdev);
4505
9d5c8243
AK		 4506 if (netif_running(netdev)) {
4507 if (igb_up(adapter)) {
4508 dev_err(&pdev->dev, "igb_up failed after reset\n");
4509 return;
4510 }
4511 }
4512
4513 netif_device_attach(netdev);
4514
4515 /* let the f/w know that the h/w is now under the control of the
4516 * driver. */
4517 igb_get_hw_control(adapter);
4518
4519}
4520
4521/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)