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igb: move get_hw_control within igb_resume.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207 dca_register_notify(&dca_notifier);
208#endif
bbd98fe4
AD		 209
210 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
421e02f0 224#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
26bc19ec
AD		 232#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
233/**
234 * igb_cache_ring_register - Descriptor ring to register mapping
235 * @adapter: board private structure to initialize
236 *
237 * Once we know the feature-set enabled for the device, we'll cache
238 * the register offset the descriptor ring is assigned to.
239 **/
240static void igb_cache_ring_register(struct igb_adapter *adapter)
241{
242 int i;
243
244 switch (adapter->hw.mac.type) {
245 case e1000_82576:
246 /* The queues are allocated for virtualization such that VF 0
247 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
248 * In order to avoid collision we start at the first free queue
249 * and continue consuming queues in the same sequence
250 */
251 for (i = 0; i < adapter->num_rx_queues; i++)
252 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
255 break;
256 case e1000_82575:
257 default:
258 for (i = 0; i < adapter->num_rx_queues; i++)
259 adapter->rx_ring[i].reg_idx = i;
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 adapter->tx_ring[i].reg_idx = i;
262 break;
263 }
264}
265
9d5c8243
AK		 266/**
267 * igb_alloc_queues - Allocate memory for all rings
268 * @adapter: board private structure to initialize
269 *
270 * We allocate one ring per queue at run-time since we don't know the
271 * number of queues at compile-time.
272 **/
273static int igb_alloc_queues(struct igb_adapter *adapter)
274{
275 int i;
276
277 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
278 sizeof(struct igb_ring), GFP_KERNEL);
279 if (!adapter->tx_ring)
280 return -ENOMEM;
281
282 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
283 sizeof(struct igb_ring), GFP_KERNEL);
284 if (!adapter->rx_ring) {
285 kfree(adapter->tx_ring);
286 return -ENOMEM;
287 }
288
6eb5a7f1
AD		 289 adapter->rx_ring->buddy = adapter->tx_ring;
290
661086df
PWJ		 291 for (i = 0; i < adapter->num_tx_queues; i++) {
292 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 293 ring->count = adapter->tx_ring_count;
661086df
PWJ		 294 ring->adapter = adapter;
295 ring->queue_index = i;
296 }
9d5c8243
AK		 297 for (i = 0; i < adapter->num_rx_queues; i++) {
298 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 299 ring->count = adapter->rx_ring_count;
9d5c8243 300 ring->adapter = adapter;
844290e5 301 ring->queue_index = i;
9d5c8243
AK		 302 ring->itr_register = E1000_ITR;
303
844290e5 304 /* set a default napi handler for each rx_ring */
661086df 305 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 306 }
26bc19ec
AD		 307
308 igb_cache_ring_register(adapter);
9d5c8243
AK		 309 return 0;
310}
311
a88f10ec
AD		 312static void igb_free_queues(struct igb_adapter *adapter)
313{
314 int i;
315
316 for (i = 0; i < adapter->num_rx_queues; i++)
317 netif_napi_del(&adapter->rx_ring[i].napi);
318
319 kfree(adapter->tx_ring);
320 kfree(adapter->rx_ring);
321}
322
9d5c8243
AK		 323#define IGB_N0_QUEUE -1
324static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
325 int tx_queue, int msix_vector)
326{
327 u32 msixbm = 0;
328 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 329 u32 ivar, index;
330
331 switch (hw->mac.type) {
332 case e1000_82575:
9d5c8243
AK		 333 /* The 82575 assigns vectors using a bitmask, which matches the
334 bitmask for the EICR/EIMS/EIMC registers. To assign one
335 or more queues to a vector, we write the appropriate bits
336 into the MSIXBM register for that vector. */
337 if (rx_queue > IGB_N0_QUEUE) {
338 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
339 adapter->rx_ring[rx_queue].eims_value = msixbm;
340 }
341 if (tx_queue > IGB_N0_QUEUE) {
342 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
343 adapter->tx_ring[tx_queue].eims_value =
344 E1000_EICR_TX_QUEUE0 << tx_queue;
345 }
346 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 347 break;
348 case e1000_82576:
26bc19ec 349 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 350 Each queue has a single entry in the table to which we write
351 a vector number along with a "valid" bit. Sadly, the layout
352 of the table is somewhat counterintuitive. */
353 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 354 index = (rx_queue >> 1);
2d064c06 355 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 356 if (rx_queue & 0x1) {
2d064c06
AD		 357 /* vector goes into third byte of register */
358 ivar = ivar & 0xFF00FFFF;
359 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 360 } else {
361 /* vector goes into low byte of register */
362 ivar = ivar & 0xFFFFFF00;
363 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 364 }
365 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
366 array_wr32(E1000_IVAR0, index, ivar);
367 }
368 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 369 index = (tx_queue >> 1);
2d064c06 370 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 371 if (tx_queue & 0x1) {
2d064c06
AD		 372 /* vector goes into high byte of register */
373 ivar = ivar & 0x00FFFFFF;
374 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 375 } else {
376 /* vector goes into second byte of register */
377 ivar = ivar & 0xFFFF00FF;
378 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 379 }
380 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
381 array_wr32(E1000_IVAR0, index, ivar);
382 }
383 break;
384 default:
385 BUG();
386 break;
387 }
9d5c8243
AK		 388}
389
390/**
391 * igb_configure_msix - Configure MSI-X hardware
392 *
393 * igb_configure_msix sets up the hardware to properly
394 * generate MSI-X interrupts.
395 **/
396static void igb_configure_msix(struct igb_adapter *adapter)
397{
398 u32 tmp;
399 int i, vector = 0;
400 struct e1000_hw *hw = &adapter->hw;
401
402 adapter->eims_enable_mask = 0;
2d064c06
AD		 403 if (hw->mac.type == e1000_82576)
404 /* Turn on MSI-X capability first, or our settings
405 * won't stick. And it will take days to debug. */
406 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 407 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 408 E1000_GPIE_NSICR);
9d5c8243
AK		 409
410 for (i = 0; i < adapter->num_tx_queues; i++) {
411 struct igb_ring *tx_ring = &adapter->tx_ring[i];
412 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
413 adapter->eims_enable_mask |= tx_ring->eims_value;
414 if (tx_ring->itr_val)
6eb5a7f1 415 writel(tx_ring->itr_val,
9d5c8243
AK		 416 hw->hw_addr + tx_ring->itr_register);
417 else
418 writel(1, hw->hw_addr + tx_ring->itr_register);
419 }
420
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 423 rx_ring->buddy = NULL;
9d5c8243
AK		 424 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
425 adapter->eims_enable_mask |= rx_ring->eims_value;
426 if (rx_ring->itr_val)
6eb5a7f1 427 writel(rx_ring->itr_val,
9d5c8243
AK		 428 hw->hw_addr + rx_ring->itr_register);
429 else
430 writel(1, hw->hw_addr + rx_ring->itr_register);
431 }
432
433
434 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 435 switch (hw->mac.type) {
436 case e1000_82575:
9d5c8243
AK		 437 array_wr32(E1000_MSIXBM(0), vector++,
438 E1000_EIMS_OTHER);
439
9d5c8243
AK		 440 tmp = rd32(E1000_CTRL_EXT);
441 /* enable MSI-X PBA support*/
442 tmp |= E1000_CTRL_EXT_PBA_CLR;
443
444 /* Auto-Mask interrupts upon ICR read. */
445 tmp |= E1000_CTRL_EXT_EIAME;
446 tmp |= E1000_CTRL_EXT_IRCA;
447
448 wr32(E1000_CTRL_EXT, tmp);
449 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 450 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 451
2d064c06
AD		 452 break;
453
454 case e1000_82576:
455 tmp = (vector++ | E1000_IVAR_VALID) << 8;
456 wr32(E1000_IVAR_MISC, tmp);
457
458 adapter->eims_enable_mask = (1 << (vector)) - 1;
459 adapter->eims_other = 1 << (vector - 1);
460 break;
461 default:
462 /* do nothing, since nothing else supports MSI-X */
463 break;
464 } /* switch (hw->mac.type) */
9d5c8243
AK		 465 wrfl();
466}
467
468/**
469 * igb_request_msix - Initialize MSI-X interrupts
470 *
471 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
472 * kernel.
473 **/
474static int igb_request_msix(struct igb_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
477 int i, err = 0, vector = 0;
478
479 vector = 0;
480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 483 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 484 err = request_irq(adapter->msix_entries[vector].vector,
485 &igb_msix_tx, 0, ring->name,
486 &(adapter->tx_ring[i]));
487 if (err)
488 goto out;
489 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 490 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 491 vector++;
492 }
493 for (i = 0; i < adapter->num_rx_queues; i++) {
494 struct igb_ring *ring = &(adapter->rx_ring[i]);
495 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 496 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 497 else
498 memcpy(ring->name, netdev->name, IFNAMSIZ);
499 err = request_irq(adapter->msix_entries[vector].vector,
500 &igb_msix_rx, 0, ring->name,
501 &(adapter->rx_ring[i]));
502 if (err)
503 goto out;
504 ring->itr_register = E1000_EITR(0) + (vector << 2);
505 ring->itr_val = adapter->itr;
844290e5
PW		 506 /* overwrite the poll routine for MSIX, we've already done
507 * netif_napi_add */
508 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 509 vector++;
510 }
511
512 err = request_irq(adapter->msix_entries[vector].vector,
513 &igb_msix_other, 0, netdev->name, netdev);
514 if (err)
515 goto out;
516
9d5c8243
AK		 517 igb_configure_msix(adapter);
518 return 0;
519out:
520 return err;
521}
522
523static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
524{
525 if (adapter->msix_entries) {
526 pci_disable_msix(adapter->pdev);
527 kfree(adapter->msix_entries);
528 adapter->msix_entries = NULL;
7dfc16fa 529 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 530 pci_disable_msi(adapter->pdev);
531 return;
532}
533
534
535/**
536 * igb_set_interrupt_capability - set MSI or MSI-X if supported
537 *
538 * Attempt to configure interrupts using the best available
539 * capabilities of the hardware and kernel.
540 **/
541static void igb_set_interrupt_capability(struct igb_adapter *adapter)
542{
543 int err;
544 int numvecs, i;
545
83b7180d
AD		 546 /* Number of supported queues. */
547 /* Having more queues than CPUs doesn't make sense. */
548 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
549 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
550
9d5c8243
AK		 551 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
552 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
553 GFP_KERNEL);
554 if (!adapter->msix_entries)
555 goto msi_only;
556
557 for (i = 0; i < numvecs; i++)
558 adapter->msix_entries[i].entry = i;
559
560 err = pci_enable_msix(adapter->pdev,
561 adapter->msix_entries,
562 numvecs);
563 if (err == 0)
34a20e89 564 goto out;
9d5c8243
AK		 565
566 igb_reset_interrupt_capability(adapter);
567
568 /* If we can't do MSI-X, try MSI */
569msi_only:
570 adapter->num_rx_queues = 1;
661086df 571 adapter->num_tx_queues = 1;
9d5c8243 572 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 573 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 574out:
661086df 575 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 576 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 577 return;
578}
579
580/**
581 * igb_request_irq - initialize interrupts
582 *
583 * Attempts to configure interrupts using the best available
584 * capabilities of the hardware and kernel.
585 **/
586static int igb_request_irq(struct igb_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct e1000_hw *hw = &adapter->hw;
590 int err = 0;
591
592 if (adapter->msix_entries) {
593 err = igb_request_msix(adapter);
844290e5 594 if (!err)
9d5c8243 595 goto request_done;
9d5c8243
AK		 596 /* fall back to MSI */
597 igb_reset_interrupt_capability(adapter);
598 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 599 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 600 igb_free_all_tx_resources(adapter);
601 igb_free_all_rx_resources(adapter);
602 adapter->num_rx_queues = 1;
603 igb_alloc_queues(adapter);
844290e5 604 } else {
2d064c06
AD		 605 switch (hw->mac.type) {
606 case e1000_82575:
607 wr32(E1000_MSIXBM(0),
608 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
609 break;
610 case e1000_82576:
611 wr32(E1000_IVAR0, E1000_IVAR_VALID);
612 break;
613 default:
614 break;
615 }
9d5c8243 616 }
844290e5 617
7dfc16fa 618 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 619 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
620 netdev->name, netdev);
621 if (!err)
622 goto request_done;
623 /* fall back to legacy interrupts */
624 igb_reset_interrupt_capability(adapter);
7dfc16fa 625 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 626 }
627
628 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
629 netdev->name, netdev);
630
6cb5e577 631 if (err)
9d5c8243
AK		 632 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
633 err);
9d5c8243
AK		 634
635request_done:
636 return err;
637}
638
639static void igb_free_irq(struct igb_adapter *adapter)
640{
641 struct net_device *netdev = adapter->netdev;
642
643 if (adapter->msix_entries) {
644 int vector = 0, i;
645
646 for (i = 0; i < adapter->num_tx_queues; i++)
647 free_irq(adapter->msix_entries[vector++].vector,
648 &(adapter->tx_ring[i]));
649 for (i = 0; i < adapter->num_rx_queues; i++)
650 free_irq(adapter->msix_entries[vector++].vector,
651 &(adapter->rx_ring[i]));
652
653 free_irq(adapter->msix_entries[vector++].vector, netdev);
654 return;
655 }
656
657 free_irq(adapter->pdev->irq, netdev);
658}
659
660/**
661 * igb_irq_disable - Mask off interrupt generation on the NIC
662 * @adapter: board private structure
663 **/
664static void igb_irq_disable(struct igb_adapter *adapter)
665{
666 struct e1000_hw *hw = &adapter->hw;
667
668 if (adapter->msix_entries) {
844290e5 669 wr32(E1000_EIAM, 0);
9d5c8243
AK		 670 wr32(E1000_EIMC, ~0);
671 wr32(E1000_EIAC, 0);
672 }
844290e5
PW		 673
674 wr32(E1000_IAM, 0);
9d5c8243
AK		 675 wr32(E1000_IMC, ~0);
676 wrfl();
677 synchronize_irq(adapter->pdev->irq);
678}
679
680/**
681 * igb_irq_enable - Enable default interrupt generation settings
682 * @adapter: board private structure
683 **/
684static void igb_irq_enable(struct igb_adapter *adapter)
685{
686 struct e1000_hw *hw = &adapter->hw;
687
688 if (adapter->msix_entries) {
844290e5
PW		 689 wr32(E1000_EIAC, adapter->eims_enable_mask);
690 wr32(E1000_EIAM, adapter->eims_enable_mask);
691 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 692 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 693 } else {
694 wr32(E1000_IMS, IMS_ENABLE_MASK);
695 wr32(E1000_IAM, IMS_ENABLE_MASK);
696 }
9d5c8243
AK		 697}
698
699static void igb_update_mng_vlan(struct igb_adapter *adapter)
700{
701 struct net_device *netdev = adapter->netdev;
702 u16 vid = adapter->hw.mng_cookie.vlan_id;
703 u16 old_vid = adapter->mng_vlan_id;
704 if (adapter->vlgrp) {
705 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
706 if (adapter->hw.mng_cookie.status &
707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
708 igb_vlan_rx_add_vid(netdev, vid);
709 adapter->mng_vlan_id = vid;
710 } else
711 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
712
713 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
714 (vid != old_vid) &&
715 !vlan_group_get_device(adapter->vlgrp, old_vid))
716 igb_vlan_rx_kill_vid(netdev, old_vid);
717 } else
718 adapter->mng_vlan_id = vid;
719 }
720}
721
722/**
723 * igb_release_hw_control - release control of the h/w to f/w
724 * @adapter: address of board private structure
725 *
726 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
727 * For ASF and Pass Through versions of f/w this means that the
728 * driver is no longer loaded.
729 *
730 **/
731static void igb_release_hw_control(struct igb_adapter *adapter)
732{
733 struct e1000_hw *hw = &adapter->hw;
734 u32 ctrl_ext;
735
736 /* Let firmware take over control of h/w */
737 ctrl_ext = rd32(E1000_CTRL_EXT);
738 wr32(E1000_CTRL_EXT,
739 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
740}
741
742
743/**
744 * igb_get_hw_control - get control of the h/w from f/w
745 * @adapter: address of board private structure
746 *
747 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
748 * For ASF and Pass Through versions of f/w this means that
749 * the driver is loaded.
750 *
751 **/
752static void igb_get_hw_control(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755 u32 ctrl_ext;
756
757 /* Let firmware know the driver has taken over */
758 ctrl_ext = rd32(E1000_CTRL_EXT);
759 wr32(E1000_CTRL_EXT,
760 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
761}
762
9d5c8243
AK		 763/**
764 * igb_configure - configure the hardware for RX and TX
765 * @adapter: private board structure
766 **/
767static void igb_configure(struct igb_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770 int i;
771
772 igb_get_hw_control(adapter);
773 igb_set_multi(netdev);
774
775 igb_restore_vlan(adapter);
9d5c8243
AK		 776
777 igb_configure_tx(adapter);
778 igb_setup_rctl(adapter);
779 igb_configure_rx(adapter);
662d7205
AD		 780
781 igb_rx_fifo_flush_82575(&adapter->hw);
782
9d5c8243
AK		 783 /* call IGB_DESC_UNUSED which always leaves
784 * at least 1 descriptor unused to make sure
785 * next_to_use != next_to_clean */
786 for (i = 0; i < adapter->num_rx_queues; i++) {
787 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 788 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 789 }
790
791
792 adapter->tx_queue_len = netdev->tx_queue_len;
793}
794
795
796/**
797 * igb_up - Open the interface and prepare it to handle traffic
798 * @adapter: board private structure
799 **/
800
801int igb_up(struct igb_adapter *adapter)
802{
803 struct e1000_hw *hw = &adapter->hw;
804 int i;
805
806 /* hardware has been reset, we need to reload some things */
807 igb_configure(adapter);
808
809 clear_bit(__IGB_DOWN, &adapter->state);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_enable(&adapter->rx_ring[i].napi);
813 if (adapter->msix_entries)
9d5c8243 814 igb_configure_msix(adapter);
9d5c8243
AK		 815
816 /* Clear any pending interrupts. */
817 rd32(E1000_ICR);
818 igb_irq_enable(adapter);
819
820 /* Fire a link change interrupt to start the watchdog. */
821 wr32(E1000_ICS, E1000_ICS_LSC);
822 return 0;
823}
824
825void igb_down(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 struct net_device *netdev = adapter->netdev;
829 u32 tctl, rctl;
830 int i;
831
832 /* signal that we're down so the interrupt handler does not
833 * reschedule our watchdog timer */
834 set_bit(__IGB_DOWN, &adapter->state);
835
836 /* disable receives in the hardware */
837 rctl = rd32(E1000_RCTL);
838 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
839 /* flush and sleep below */
840
fd2ea0a7 841 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 842
843 /* disable transmits in the hardware */
844 tctl = rd32(E1000_TCTL);
845 tctl &= ~E1000_TCTL_EN;
846 wr32(E1000_TCTL, tctl);
847 /* flush both disables and wait for them to finish */
848 wrfl();
849 msleep(10);
850
844290e5
PW		 851 for (i = 0; i < adapter->num_rx_queues; i++)
852 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 853
9d5c8243
AK		 854 igb_irq_disable(adapter);
855
856 del_timer_sync(&adapter->watchdog_timer);
857 del_timer_sync(&adapter->phy_info_timer);
858
859 netdev->tx_queue_len = adapter->tx_queue_len;
860 netif_carrier_off(netdev);
861 adapter->link_speed = 0;
862 adapter->link_duplex = 0;
863
3023682e
JK		 864 if (!pci_channel_offline(adapter->pdev))
865 igb_reset(adapter);
9d5c8243
AK		 866 igb_clean_all_tx_rings(adapter);
867 igb_clean_all_rx_rings(adapter);
868}
869
870void igb_reinit_locked(struct igb_adapter *adapter)
871{
872 WARN_ON(in_interrupt());
873 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
874 msleep(1);
875 igb_down(adapter);
876 igb_up(adapter);
877 clear_bit(__IGB_RESETTING, &adapter->state);
878}
879
880void igb_reset(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 883 struct e1000_mac_info *mac = &hw->mac;
884 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 885 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
886 u16 hwm;
887
888 /* Repartition Pba for greater than 9k mtu
889 * To take effect CTRL.RST is required.
890 */
2d064c06 891 if (mac->type != e1000_82576) {
9d5c8243 892 pba = E1000_PBA_34K;
2d064c06
AD		 893 }
894 else {
895 pba = E1000_PBA_64K;
896 }
9d5c8243 897
2d064c06
AD		 898 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
899 (mac->type < e1000_82576)) {
9d5c8243
AK		 900 /* adjust PBA for jumbo frames */
901 wr32(E1000_PBA, pba);
902
903 /* To maintain wire speed transmits, the Tx FIFO should be
904 * large enough to accommodate two full transmit packets,
905 * rounded up to the next 1KB and expressed in KB. Likewise,
906 * the Rx FIFO should be large enough to accommodate at least
907 * one full receive packet and is similarly rounded up and
908 * expressed in KB. */
909 pba = rd32(E1000_PBA);
910 /* upper 16 bits has Tx packet buffer allocation size in KB */
911 tx_space = pba >> 16;
912 /* lower 16 bits has Rx packet buffer allocation size in KB */
913 pba &= 0xffff;
914 /* the tx fifo also stores 16 bytes of information about the tx
915 * but don't include ethernet FCS because hardware appends it */
916 min_tx_space = (adapter->max_frame_size +
917 sizeof(struct e1000_tx_desc) -
918 ETH_FCS_LEN) * 2;
919 min_tx_space = ALIGN(min_tx_space, 1024);
920 min_tx_space >>= 10;
921 /* software strips receive CRC, so leave room for it */
922 min_rx_space = adapter->max_frame_size;
923 min_rx_space = ALIGN(min_rx_space, 1024);
924 min_rx_space >>= 10;
925
926 /* If current Tx allocation is less than the min Tx FIFO size,
927 * and the min Tx FIFO size is less than the current Rx FIFO
928 * allocation, take space away from current Rx allocation */
929 if (tx_space < min_tx_space &&
930 ((min_tx_space - tx_space) < pba)) {
931 pba = pba - (min_tx_space - tx_space);
932
933 /* if short on rx space, rx wins and must trump tx
934 * adjustment */
935 if (pba < min_rx_space)
936 pba = min_rx_space;
937 }
2d064c06 938 wr32(E1000_PBA, pba);
9d5c8243 939 }
9d5c8243
AK		 940
941 /* flow control settings */
942 /* The high water mark must be low enough to fit one full frame
943 * (or the size used for early receive) above it in the Rx FIFO.
944 * Set it to the lower of:
945 * - 90% of the Rx FIFO size, or
946 * - the full Rx FIFO size minus one full frame */
947 hwm = min(((pba << 10) * 9 / 10),
2d064c06 948 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 949
2d064c06
AD		 950 if (mac->type < e1000_82576) {
951 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
952 fc->low_water = fc->high_water - 8;
953 } else {
954 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
955 fc->low_water = fc->high_water - 16;
956 }
9d5c8243
AK		 957 fc->pause_time = 0xFFFF;
958 fc->send_xon = 1;
959 fc->type = fc->original_type;
960
961 /* Allow time for pending master requests to run */
962 adapter->hw.mac.ops.reset_hw(&adapter->hw);
963 wr32(E1000_WUC, 0);
964
965 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
966 dev_err(&adapter->pdev->dev, "Hardware Error\n");
967
968 igb_update_mng_vlan(adapter);
969
970 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
971 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
972
973 igb_reset_adaptive(&adapter->hw);
f5f4cf08 974 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 975}
976
2e5c6922
SH		 977static const struct net_device_ops igb_netdev_ops = {
978 .ndo_open = igb_open,
979 .ndo_stop = igb_close,
00829823 980 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 981 .ndo_get_stats = igb_get_stats,
982 .ndo_set_multicast_list = igb_set_multi,
983 .ndo_set_mac_address = igb_set_mac,
984 .ndo_change_mtu = igb_change_mtu,
985 .ndo_do_ioctl = igb_ioctl,
986 .ndo_tx_timeout = igb_tx_timeout,
987 .ndo_validate_addr = eth_validate_addr,
988 .ndo_vlan_rx_register = igb_vlan_rx_register,
989 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
990 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
991#ifdef CONFIG_NET_POLL_CONTROLLER
992 .ndo_poll_controller = igb_netpoll,
993#endif
994};
995
9d5c8243
AK		 996/**
997 * igb_probe - Device Initialization Routine
998 * @pdev: PCI device information struct
999 * @ent: entry in igb_pci_tbl
1000 *
1001 * Returns 0 on success, negative on failure
1002 *
1003 * igb_probe initializes an adapter identified by a pci_dev structure.
1004 * The OS initialization, configuring of the adapter private structure,
1005 * and a hardware reset occur.
1006 **/
1007static int __devinit igb_probe(struct pci_dev *pdev,
1008 const struct pci_device_id *ent)
1009{
1010 struct net_device *netdev;
1011 struct igb_adapter *adapter;
1012 struct e1000_hw *hw;
c54106bb 1013 struct pci_dev *us_dev;
9d5c8243
AK		 1014 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1015 unsigned long mmio_start, mmio_len;
c54106bb
AD		 1016 int i, err, pci_using_dac, pos;
1017 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1018 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1019 u32 part_num;
1020
aed5dec3 1021 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1022 if (err)
1023 return err;
1024
1025 pci_using_dac = 0;
1026 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1027 if (!err) {
1028 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1029 if (!err)
1030 pci_using_dac = 1;
1031 } else {
1032 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1033 if (err) {
1034 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1035 if (err) {
1036 dev_err(&pdev->dev, "No usable DMA "
1037 "configuration, aborting\n");
1038 goto err_dma;
1039 }
1040 }
1041 }
1042
c54106bb
AD		 1043 /* 82575 requires that the pci-e link partner disable the L0s state */
1044 switch (pdev->device) {
1045 case E1000_DEV_ID_82575EB_COPPER:
1046 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1047 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1048 us_dev = pdev->bus->self;
1049 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1050 if (pos) {
1051 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1052 &state);
1053 state &= ~PCIE_LINK_STATE_L0S;
1054 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1055 state);
ac450208
BH		 1056 dev_info(&pdev->dev,
1057 "Disabling ASPM L0s upstream switch port %s\n",
1058 pci_name(us_dev));
c54106bb
AD		 1059 }
1060 default:
1061 break;
1062 }
1063
aed5dec3
AD		 1064 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1065 IORESOURCE_MEM),
1066 igb_driver_name);
9d5c8243
AK		 1067 if (err)
1068 goto err_pci_reg;
1069
ea943d41
JK		 1070 err = pci_enable_pcie_error_reporting(pdev);
1071 if (err) {
1072 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1073 "0x%x\n", err);
1074 /* non-fatal, continue */
1075 }
40a914fa 1076
9d5c8243 1077 pci_set_master(pdev);
c682fc23 1078 pci_save_state(pdev);
9d5c8243
AK		 1079
1080 err = -ENOMEM;
661086df 1081 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1082 if (!netdev)
1083 goto err_alloc_etherdev;
1084
1085 SET_NETDEV_DEV(netdev, &pdev->dev);
1086
1087 pci_set_drvdata(pdev, netdev);
1088 adapter = netdev_priv(netdev);
1089 adapter->netdev = netdev;
1090 adapter->pdev = pdev;
1091 hw = &adapter->hw;
1092 hw->back = adapter;
1093 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1094
1095 mmio_start = pci_resource_start(pdev, 0);
1096 mmio_len = pci_resource_len(pdev, 0);
1097
1098 err = -EIO;
28b0759c
AD		 1099 hw->hw_addr = ioremap(mmio_start, mmio_len);
1100 if (!hw->hw_addr)
9d5c8243
AK		 1101 goto err_ioremap;
1102
2e5c6922 1103 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1104 igb_set_ethtool_ops(netdev);
9d5c8243 1105 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1106
1107 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1108
1109 netdev->mem_start = mmio_start;
1110 netdev->mem_end = mmio_start + mmio_len;
1111
9d5c8243
AK		 1112 /* PCI config space info */
1113 hw->vendor_id = pdev->vendor;
1114 hw->device_id = pdev->device;
1115 hw->revision_id = pdev->revision;
1116 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1117 hw->subsystem_device_id = pdev->subsystem_device;
1118
1119 /* setup the private structure */
1120 hw->back = adapter;
1121 /* Copy the default MAC, PHY and NVM function pointers */
1122 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1123 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1124 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1125 /* Initialize skew-specific constants */
1126 err = ei->get_invariants(hw);
1127 if (err)
1128 goto err_hw_init;
1129
1130 err = igb_sw_init(adapter);
1131 if (err)
1132 goto err_sw_init;
1133
1134 igb_get_bus_info_pcie(hw);
1135
7dfc16fa
AD		 1136 /* set flags */
1137 switch (hw->mac.type) {
7dfc16fa 1138 case e1000_82575:
7dfc16fa
AD		 1139 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1140 break;
bbd98fe4 1141 case e1000_82576:
7dfc16fa
AD		 1142 default:
1143 break;
1144 }
1145
9d5c8243
AK		 1146 hw->phy.autoneg_wait_to_complete = false;
1147 hw->mac.adaptive_ifs = true;
1148
1149 /* Copper options */
1150 if (hw->phy.media_type == e1000_media_type_copper) {
1151 hw->phy.mdix = AUTO_ALL_MODES;
1152 hw->phy.disable_polarity_correction = false;
1153 hw->phy.ms_type = e1000_ms_hw_default;
1154 }
1155
1156 if (igb_check_reset_block(hw))
1157 dev_info(&pdev->dev,
1158 "PHY reset is blocked due to SOL/IDER session.\n");
1159
1160 netdev->features = NETIF_F_SG |
7d8eb29e 1161 NETIF_F_IP_CSUM |
9d5c8243
AK		 1162 NETIF_F_HW_VLAN_TX |
1163 NETIF_F_HW_VLAN_RX |
1164 NETIF_F_HW_VLAN_FILTER;
1165
7d8eb29e 1166 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1167 netdev->features |= NETIF_F_TSO;
9d5c8243 1168 netdev->features |= NETIF_F_TSO6;
48f29ffc 1169
d3352520 1170#ifdef CONFIG_IGB_LRO
5c0999b7 1171 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1172#endif
1173
48f29ffc
JK		 1174 netdev->vlan_features |= NETIF_F_TSO;
1175 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1176 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1177 netdev->vlan_features |= NETIF_F_SG;
1178
9d5c8243
AK		 1179 if (pci_using_dac)
1180 netdev->features |= NETIF_F_HIGHDMA;
1181
9d5c8243
AK		 1182 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1183
1184 /* before reading the NVM, reset the controller to put the device in a
1185 * known good starting state */
1186 hw->mac.ops.reset_hw(hw);
1187
1188 /* make sure the NVM is good */
1189 if (igb_validate_nvm_checksum(hw) < 0) {
1190 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1191 err = -EIO;
1192 goto err_eeprom;
1193 }
1194
1195 /* copy the MAC address out of the NVM */
1196 if (hw->mac.ops.read_mac_addr(hw))
1197 dev_err(&pdev->dev, "NVM Read Error\n");
1198
1199 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1200 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1201
1202 if (!is_valid_ether_addr(netdev->perm_addr)) {
1203 dev_err(&pdev->dev, "Invalid MAC Address\n");
1204 err = -EIO;
1205 goto err_eeprom;
1206 }
1207
1208 init_timer(&adapter->watchdog_timer);
1209 adapter->watchdog_timer.function = &igb_watchdog;
1210 adapter->watchdog_timer.data = (unsigned long) adapter;
1211
1212 init_timer(&adapter->phy_info_timer);
1213 adapter->phy_info_timer.function = &igb_update_phy_info;
1214 adapter->phy_info_timer.data = (unsigned long) adapter;
1215
1216 INIT_WORK(&adapter->reset_task, igb_reset_task);
1217 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1218
1219 /* Initialize link & ring properties that are user-changeable */
1220 adapter->tx_ring->count = 256;
1221 for (i = 0; i < adapter->num_tx_queues; i++)
1222 adapter->tx_ring[i].count = adapter->tx_ring->count;
1223 adapter->rx_ring->count = 256;
1224 for (i = 0; i < adapter->num_rx_queues; i++)
1225 adapter->rx_ring[i].count = adapter->rx_ring->count;
1226
1227 adapter->fc_autoneg = true;
1228 hw->mac.autoneg = true;
1229 hw->phy.autoneg_advertised = 0x2f;
1230
1231 hw->fc.original_type = e1000_fc_default;
1232 hw->fc.type = e1000_fc_default;
1233
1234 adapter->itr_setting = 3;
1235 adapter->itr = IGB_START_ITR;
1236
1237 igb_validate_mdi_setting(hw);
1238
1239 adapter->rx_csum = 1;
1240
1241 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1242 * enable the ACPI Magic Packet filter
1243 */
1244
1245 if (hw->bus.func == 0 ||
1246 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1247 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1248
1249 if (eeprom_data & eeprom_apme_mask)
1250 adapter->eeprom_wol |= E1000_WUFC_MAG;
1251
1252 /* now that we have the eeprom settings, apply the special cases where
1253 * the eeprom may be wrong or the board simply won't support wake on
1254 * lan on a particular port */
1255 switch (pdev->device) {
1256 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1257 adapter->eeprom_wol = 0;
1258 break;
1259 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1260 case E1000_DEV_ID_82576_FIBER:
1261 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1262 /* Wake events only supported on port A for dual fiber
1263 * regardless of eeprom setting */
1264 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1265 adapter->eeprom_wol = 0;
1266 break;
1267 }
1268
1269 /* initialize the wol settings based on the eeprom settings */
1270 adapter->wol = adapter->eeprom_wol;
e1b86d84 1271 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1272
1273 /* reset the hardware with the new settings */
1274 igb_reset(adapter);
1275
1276 /* let the f/w know that the h/w is now under the control of the
1277 * driver. */
1278 igb_get_hw_control(adapter);
1279
1280 /* tell the stack to leave us alone until igb_open() is called */
1281 netif_carrier_off(netdev);
fd2ea0a7 1282 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1283
1284 strcpy(netdev->name, "eth%d");
1285 err = register_netdev(netdev);
1286 if (err)
1287 goto err_register;
1288
421e02f0 1289#ifdef CONFIG_IGB_DCA
bbd98fe4 1290 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1291 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1292 dev_info(&pdev->dev, "DCA enabled\n");
1293 /* Always use CB2 mode, difference is masked
1294 * in the CB driver. */
1295 wr32(E1000_DCA_CTRL, 2);
1296 igb_setup_dca(adapter);
1297 }
1298#endif
1299
9d5c8243
AK		 1300 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1301 /* print bus type/speed/width info */
7c510e4b 1302 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1303 netdev->name,
1304 ((hw->bus.speed == e1000_bus_speed_2500)
1305 ? "2.5Gb/s" : "unknown"),
1306 ((hw->bus.width == e1000_bus_width_pcie_x4)
1307 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1308 ? "Width x1" : "unknown"),
7c510e4b 1309 netdev->dev_addr);
9d5c8243
AK		 1310
1311 igb_read_part_num(hw, &part_num);
1312 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1313 (part_num >> 8), (part_num & 0xff));
1314
1315 dev_info(&pdev->dev,
1316 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1317 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1318 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1319 adapter->num_rx_queues, adapter->num_tx_queues);
1320
9d5c8243
AK		 1321 return 0;
1322
1323err_register:
1324 igb_release_hw_control(adapter);
1325err_eeprom:
1326 if (!igb_check_reset_block(hw))
f5f4cf08 1327 igb_reset_phy(hw);
9d5c8243
AK		 1328
1329 if (hw->flash_address)
1330 iounmap(hw->flash_address);
1331
a88f10ec 1332 igb_free_queues(adapter);
9d5c8243
AK		 1333err_sw_init:
1334err_hw_init:
1335 iounmap(hw->hw_addr);
1336err_ioremap:
1337 free_netdev(netdev);
1338err_alloc_etherdev:
aed5dec3
AD		 1339 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1340 IORESOURCE_MEM));
9d5c8243
AK		 1341err_pci_reg:
1342err_dma:
1343 pci_disable_device(pdev);
1344 return err;
1345}
1346
1347/**
1348 * igb_remove - Device Removal Routine
1349 * @pdev: PCI device information struct
1350 *
1351 * igb_remove is called by the PCI subsystem to alert the driver
1352 * that it should release a PCI device. The could be caused by a
1353 * Hot-Plug event, or because the driver is going to be removed from
1354 * memory.
1355 **/
1356static void __devexit igb_remove(struct pci_dev *pdev)
1357{
1358 struct net_device *netdev = pci_get_drvdata(pdev);
1359 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1360 struct e1000_hw *hw = &adapter->hw;
ea943d41 1361 int err;
9d5c8243
AK		 1362
1363 /* flush_scheduled work may reschedule our watchdog task, so
1364 * explicitly disable watchdog tasks from being rescheduled */
1365 set_bit(__IGB_DOWN, &adapter->state);
1366 del_timer_sync(&adapter->watchdog_timer);
1367 del_timer_sync(&adapter->phy_info_timer);
1368
1369 flush_scheduled_work();
1370
421e02f0 1371#ifdef CONFIG_IGB_DCA
7dfc16fa 1372 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1373 dev_info(&pdev->dev, "DCA disabled\n");
1374 dca_remove_requester(&pdev->dev);
7dfc16fa 1375 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1376 wr32(E1000_DCA_CTRL, 1);
1377 }
1378#endif
1379
9d5c8243
AK		 1380 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1381 * would have already happened in close and is redundant. */
1382 igb_release_hw_control(adapter);
1383
1384 unregister_netdev(netdev);
1385
f5f4cf08
AD		 1386 if (!igb_check_reset_block(&adapter->hw))
1387 igb_reset_phy(&adapter->hw);
9d5c8243 1388
9d5c8243
AK		 1389 igb_reset_interrupt_capability(adapter);
1390
a88f10ec 1391 igb_free_queues(adapter);
9d5c8243 1392
28b0759c
AD		 1393 iounmap(hw->hw_addr);
1394 if (hw->flash_address)
1395 iounmap(hw->flash_address);
aed5dec3
AD		 1396 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1397 IORESOURCE_MEM));
9d5c8243
AK		 1398
1399 free_netdev(netdev);
1400
ea943d41
JK		 1401 err = pci_disable_pcie_error_reporting(pdev);
1402 if (err)
1403 dev_err(&pdev->dev,
1404 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1405
9d5c8243
AK		 1406 pci_disable_device(pdev);
1407}
1408
1409/**
1410 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1411 * @adapter: board private structure to initialize
1412 *
1413 * igb_sw_init initializes the Adapter private data structure.
1414 * Fields are initialized based on PCI device information and
1415 * OS network device settings (MTU size).
1416 **/
1417static int __devinit igb_sw_init(struct igb_adapter *adapter)
1418{
1419 struct e1000_hw *hw = &adapter->hw;
1420 struct net_device *netdev = adapter->netdev;
1421 struct pci_dev *pdev = adapter->pdev;
1422
1423 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1424
68fd9910
AD		 1425 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1426 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1427 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1428 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1429 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1430 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1431
661086df
PWJ		 1432 /* This call may decrease the number of queues depending on
1433 * interrupt mode. */
9d5c8243
AK		 1434 igb_set_interrupt_capability(adapter);
1435
1436 if (igb_alloc_queues(adapter)) {
1437 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1438 return -ENOMEM;
1439 }
1440
1441 /* Explicitly disable IRQ since the NIC can be in any state. */
1442 igb_irq_disable(adapter);
1443
1444 set_bit(__IGB_DOWN, &adapter->state);
1445 return 0;
1446}
1447
1448/**
1449 * igb_open - Called when a network interface is made active
1450 * @netdev: network interface device structure
1451 *
1452 * Returns 0 on success, negative value on failure
1453 *
1454 * The open entry point is called when a network interface is made
1455 * active by the system (IFF_UP). At this point all resources needed
1456 * for transmit and receive operations are allocated, the interrupt
1457 * handler is registered with the OS, the watchdog timer is started,
1458 * and the stack is notified that the interface is ready.
1459 **/
1460static int igb_open(struct net_device *netdev)
1461{
1462 struct igb_adapter *adapter = netdev_priv(netdev);
1463 struct e1000_hw *hw = &adapter->hw;
1464 int err;
1465 int i;
1466
1467 /* disallow open during test */
1468 if (test_bit(__IGB_TESTING, &adapter->state))
1469 return -EBUSY;
1470
1471 /* allocate transmit descriptors */
1472 err = igb_setup_all_tx_resources(adapter);
1473 if (err)
1474 goto err_setup_tx;
1475
1476 /* allocate receive descriptors */
1477 err = igb_setup_all_rx_resources(adapter);
1478 if (err)
1479 goto err_setup_rx;
1480
1481 /* e1000_power_up_phy(adapter); */
1482
1483 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1484 if ((adapter->hw.mng_cookie.status &
1485 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1486 igb_update_mng_vlan(adapter);
1487
1488 /* before we allocate an interrupt, we must be ready to handle it.
1489 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1490 * as soon as we call pci_request_irq, so we have to setup our
1491 * clean_rx handler before we do so. */
1492 igb_configure(adapter);
1493
1494 err = igb_request_irq(adapter);
1495 if (err)
1496 goto err_req_irq;
1497
1498 /* From here on the code is the same as igb_up() */
1499 clear_bit(__IGB_DOWN, &adapter->state);
1500
844290e5
PW		 1501 for (i = 0; i < adapter->num_rx_queues; i++)
1502 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1503
1504 /* Clear any pending interrupts. */
1505 rd32(E1000_ICR);
844290e5
PW		 1506
1507 igb_irq_enable(adapter);
1508
d55b53ff
JK		 1509 netif_tx_start_all_queues(netdev);
1510
9d5c8243
AK		 1511 /* Fire a link status change interrupt to start the watchdog. */
1512 wr32(E1000_ICS, E1000_ICS_LSC);
1513
1514 return 0;
1515
1516err_req_irq:
1517 igb_release_hw_control(adapter);
1518 /* e1000_power_down_phy(adapter); */
1519 igb_free_all_rx_resources(adapter);
1520err_setup_rx:
1521 igb_free_all_tx_resources(adapter);
1522err_setup_tx:
1523 igb_reset(adapter);
1524
1525 return err;
1526}
1527
1528/**
1529 * igb_close - Disables a network interface
1530 * @netdev: network interface device structure
1531 *
1532 * Returns 0, this is not allowed to fail
1533 *
1534 * The close entry point is called when an interface is de-activated
1535 * by the OS. The hardware is still under the driver's control, but
1536 * needs to be disabled. A global MAC reset is issued to stop the
1537 * hardware, and all transmit and receive resources are freed.
1538 **/
1539static int igb_close(struct net_device *netdev)
1540{
1541 struct igb_adapter *adapter = netdev_priv(netdev);
1542
1543 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1544 igb_down(adapter);
1545
1546 igb_free_irq(adapter);
1547
1548 igb_free_all_tx_resources(adapter);
1549 igb_free_all_rx_resources(adapter);
1550
1551 /* kill manageability vlan ID if supported, but not if a vlan with
1552 * the same ID is registered on the host OS (let 8021q kill it) */
1553 if ((adapter->hw.mng_cookie.status &
1554 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1555 !(adapter->vlgrp &&
1556 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1557 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1558
1559 return 0;
1560}
1561
1562/**
1563 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1564 * @adapter: board private structure
1565 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1566 *
1567 * Return 0 on success, negative on failure
1568 **/
1569
1570int igb_setup_tx_resources(struct igb_adapter *adapter,
1571 struct igb_ring *tx_ring)
1572{
1573 struct pci_dev *pdev = adapter->pdev;
1574 int size;
1575
1576 size = sizeof(struct igb_buffer) * tx_ring->count;
1577 tx_ring->buffer_info = vmalloc(size);
1578 if (!tx_ring->buffer_info)
1579 goto err;
1580 memset(tx_ring->buffer_info, 0, size);
1581
1582 /* round up to nearest 4K */
0e014cb1 1583 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1584 tx_ring->size = ALIGN(tx_ring->size, 4096);
1585
1586 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1587 &tx_ring->dma);
1588
1589 if (!tx_ring->desc)
1590 goto err;
1591
1592 tx_ring->adapter = adapter;
1593 tx_ring->next_to_use = 0;
1594 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1595 return 0;
1596
1597err:
1598 vfree(tx_ring->buffer_info);
1599 dev_err(&adapter->pdev->dev,
1600 "Unable to allocate memory for the transmit descriptor ring\n");
1601 return -ENOMEM;
1602}
1603
1604/**
1605 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1606 * (Descriptors) for all queues
1607 * @adapter: board private structure
1608 *
1609 * Return 0 on success, negative on failure
1610 **/
1611static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1612{
1613 int i, err = 0;
661086df 1614 int r_idx;
9d5c8243
AK		 1615
1616 for (i = 0; i < adapter->num_tx_queues; i++) {
1617 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1618 if (err) {
1619 dev_err(&adapter->pdev->dev,
1620 "Allocation for Tx Queue %u failed\n", i);
1621 for (i--; i >= 0; i--)
3b644cf6 1622 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1623 break;
1624 }
1625 }
1626
661086df
PWJ		 1627 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1628 r_idx = i % adapter->num_tx_queues;
1629 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1630 }
9d5c8243
AK		 1631 return err;
1632}
1633
1634/**
1635 * igb_configure_tx - Configure transmit Unit after Reset
1636 * @adapter: board private structure
1637 *
1638 * Configure the Tx unit of the MAC after a reset.
1639 **/
1640static void igb_configure_tx(struct igb_adapter *adapter)
1641{
0e014cb1 1642 u64 tdba;
9d5c8243
AK		 1643 struct e1000_hw *hw = &adapter->hw;
1644 u32 tctl;
1645 u32 txdctl, txctrl;
26bc19ec 1646 int i, j;
9d5c8243
AK		 1647
1648 for (i = 0; i < adapter->num_tx_queues; i++) {
1649 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1650 j = ring->reg_idx;
1651 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1652 ring->count * sizeof(struct e1000_tx_desc));
1653 tdba = ring->dma;
26bc19ec 1654 wr32(E1000_TDBAL(j),
9d5c8243 1655 tdba & 0x00000000ffffffffULL);
26bc19ec 1656 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1657
26bc19ec
AD		 1658 ring->head = E1000_TDH(j);
1659 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1660 writel(0, hw->hw_addr + ring->tail);
1661 writel(0, hw->hw_addr + ring->head);
26bc19ec 1662 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1663 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1664 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1665
1666 /* Turn off Relaxed Ordering on head write-backs. The
1667 * writebacks MUST be delivered in order or it will
1668 * completely screw up our bookeeping.
1669 */
26bc19ec 1670 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1671 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1672 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1673 }
1674
1675
1676
1677 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1678
1679 /* Program the Transmit Control Register */
1680
1681 tctl = rd32(E1000_TCTL);
1682 tctl &= ~E1000_TCTL_CT;
1683 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1684 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1685
1686 igb_config_collision_dist(hw);
1687
1688 /* Setup Transmit Descriptor Settings for eop descriptor */
1689 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1690
1691 /* Enable transmits */
1692 tctl |= E1000_TCTL_EN;
1693
1694 wr32(E1000_TCTL, tctl);
1695}
1696
1697/**
1698 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1699 * @adapter: board private structure
1700 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1701 *
1702 * Returns 0 on success, negative on failure
1703 **/
1704
1705int igb_setup_rx_resources(struct igb_adapter *adapter,
1706 struct igb_ring *rx_ring)
1707{
1708 struct pci_dev *pdev = adapter->pdev;
1709 int size, desc_len;
1710
1711 size = sizeof(struct igb_buffer) * rx_ring->count;
1712 rx_ring->buffer_info = vmalloc(size);
1713 if (!rx_ring->buffer_info)
1714 goto err;
1715 memset(rx_ring->buffer_info, 0, size);
1716
1717 desc_len = sizeof(union e1000_adv_rx_desc);
1718
1719 /* Round up to nearest 4K */
1720 rx_ring->size = rx_ring->count * desc_len;
1721 rx_ring->size = ALIGN(rx_ring->size, 4096);
1722
1723 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1724 &rx_ring->dma);
1725
1726 if (!rx_ring->desc)
1727 goto err;
1728
1729 rx_ring->next_to_clean = 0;
1730 rx_ring->next_to_use = 0;
9d5c8243
AK		 1731
1732 rx_ring->adapter = adapter;
9d5c8243
AK		 1733
1734 return 0;
1735
1736err:
1737 vfree(rx_ring->buffer_info);
1738 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1739 "the receive descriptor ring\n");
1740 return -ENOMEM;
1741}
1742
1743/**
1744 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1745 * (Descriptors) for all queues
1746 * @adapter: board private structure
1747 *
1748 * Return 0 on success, negative on failure
1749 **/
1750static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1751{
1752 int i, err = 0;
1753
1754 for (i = 0; i < adapter->num_rx_queues; i++) {
1755 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1756 if (err) {
1757 dev_err(&adapter->pdev->dev,
1758 "Allocation for Rx Queue %u failed\n", i);
1759 for (i--; i >= 0; i--)
3b644cf6 1760 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1761 break;
1762 }
1763 }
1764
1765 return err;
1766}
1767
1768/**
1769 * igb_setup_rctl - configure the receive control registers
1770 * @adapter: Board private structure
1771 **/
1772static void igb_setup_rctl(struct igb_adapter *adapter)
1773{
1774 struct e1000_hw *hw = &adapter->hw;
1775 u32 rctl;
1776 u32 srrctl = 0;
26bc19ec 1777 int i, j;
9d5c8243
AK		 1778
1779 rctl = rd32(E1000_RCTL);
1780
1781 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1782 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1783
69d728ba 1784 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1785 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1786
87cb7e8c
AK		 1787 /*
1788 * enable stripping of CRC. It's unlikely this will break BMC
1789 * redirection as it did with e1000. Newer features require
1790 * that the HW strips the CRC.
9d5c8243 1791 */
87cb7e8c 1792 rctl |= E1000_RCTL_SECRC;
9d5c8243 1793
9b07f3d3 1794 /*
ec54d7d6 1795 * disable store bad packets and clear size bits.
9b07f3d3 1796 */
ec54d7d6 1797 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1798
ec54d7d6 1799 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1800 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1801
1802 /* Setup buffer sizes */
1803 switch (adapter->rx_buffer_len) {
1804 case IGB_RXBUFFER_256:
1805 rctl |= E1000_RCTL_SZ_256;
1806 break;
1807 case IGB_RXBUFFER_512:
1808 rctl |= E1000_RCTL_SZ_512;
1809 break;
1810 default:
1811 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1812 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1813 break;
9d5c8243
AK		 1814 }
1815
1816 /* 82575 and greater support packet-split where the protocol
1817 * header is placed in skb->data and the packet data is
1818 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1819 * In the case of a non-split, skb->data is linearly filled,
1820 * followed by the page buffers. Therefore, skb->data is
1821 * sized to hold the largest protocol header.
1822 */
1823 /* allocations using alloc_page take too long for regular MTU
1824 * so only enable packet split for jumbo frames */
ec54d7d6 1825 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1826 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1827 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1828 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1829 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1830 } else {
1831 adapter->rx_ps_hdr_size = 0;
1832 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1833 }
1834
26bc19ec
AD		 1835 for (i = 0; i < adapter->num_rx_queues; i++) {
1836 j = adapter->rx_ring[i].reg_idx;
1837 wr32(E1000_SRRCTL(j), srrctl);
1838 }
9d5c8243
AK		 1839
1840 wr32(E1000_RCTL, rctl);
1841}
1842
1843/**
1844 * igb_configure_rx - Configure receive Unit after Reset
1845 * @adapter: board private structure
1846 *
1847 * Configure the Rx unit of the MAC after a reset.
1848 **/
1849static void igb_configure_rx(struct igb_adapter *adapter)
1850{
1851 u64 rdba;
1852 struct e1000_hw *hw = &adapter->hw;
1853 u32 rctl, rxcsum;
1854 u32 rxdctl;
26bc19ec 1855 int i, j;
9d5c8243
AK		 1856
1857 /* disable receives while setting up the descriptors */
1858 rctl = rd32(E1000_RCTL);
1859 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1860 wrfl();
1861 mdelay(10);
1862
1863 if (adapter->itr_setting > 3)
6eb5a7f1 1864 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1865
1866 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1867 * the Base and Length of the Rx Descriptor Ring */
1868 for (i = 0; i < adapter->num_rx_queues; i++) {
1869 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1870 j = ring->reg_idx;
9d5c8243 1871 rdba = ring->dma;
26bc19ec 1872 wr32(E1000_RDBAL(j),
9d5c8243 1873 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1874 wr32(E1000_RDBAH(j), rdba >> 32);
1875 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1876 ring->count * sizeof(union e1000_adv_rx_desc));
1877
26bc19ec
AD		 1878 ring->head = E1000_RDH(j);
1879 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1880 writel(0, hw->hw_addr + ring->tail);
1881 writel(0, hw->hw_addr + ring->head);
1882
26bc19ec 1883 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1884 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1885 rxdctl &= 0xFFF00000;
1886 rxdctl |= IGB_RX_PTHRESH;
1887 rxdctl |= IGB_RX_HTHRESH << 8;
1888 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1889 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1890 }
1891
1892 if (adapter->num_rx_queues > 1) {
1893 u32 random[10];
1894 u32 mrqc;
1895 u32 j, shift;
1896 union e1000_reta {
1897 u32 dword;
1898 u8 bytes[4];
1899 } reta;
1900
1901 get_random_bytes(&random[0], 40);
1902
2d064c06
AD		 1903 if (hw->mac.type >= e1000_82576)
1904 shift = 0;
1905 else
1906 shift = 6;
9d5c8243
AK		 1907 for (j = 0; j < (32 * 4); j++) {
1908 reta.bytes[j & 3] =
26bc19ec 1909 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1910 if ((j & 3) == 3)
1911 writel(reta.dword,
1912 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1913 }
1914 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1915
1916 /* Fill out hash function seeds */
1917 for (j = 0; j < 10; j++)
1918 array_wr32(E1000_RSSRK(0), j, random[j]);
1919
1920 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1921 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1922 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1923 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1924 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1925 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1926 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1927 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1928
1929
1930 wr32(E1000_MRQC, mrqc);
1931
1932 /* Multiqueue and raw packet checksumming are mutually
1933 * exclusive. Note that this not the same as TCP/IP
1934 * checksumming, which works fine. */
1935 rxcsum = rd32(E1000_RXCSUM);
1936 rxcsum |= E1000_RXCSUM_PCSD;
1937 wr32(E1000_RXCSUM, rxcsum);
1938 } else {
1939 /* Enable Receive Checksum Offload for TCP and UDP */
1940 rxcsum = rd32(E1000_RXCSUM);
1941 if (adapter->rx_csum) {
1942 rxcsum |= E1000_RXCSUM_TUOFL;
1943
1944 /* Enable IPv4 payload checksum for UDP fragments
1945 * Must be used in conjunction with packet-split. */
1946 if (adapter->rx_ps_hdr_size)
1947 rxcsum |= E1000_RXCSUM_IPPCSE;
1948 } else {
1949 rxcsum &= ~E1000_RXCSUM_TUOFL;
1950 /* don't need to clear IPPCSE as it defaults to 0 */
1951 }
1952 wr32(E1000_RXCSUM, rxcsum);
1953 }
1954
1955 if (adapter->vlgrp)
1956 wr32(E1000_RLPML,
1957 adapter->max_frame_size + VLAN_TAG_SIZE);
1958 else
1959 wr32(E1000_RLPML, adapter->max_frame_size);
1960
1961 /* Enable Receives */
1962 wr32(E1000_RCTL, rctl);
1963}
1964
1965/**
1966 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1967 * @tx_ring: Tx descriptor ring for a specific queue
1968 *
1969 * Free all transmit software resources
1970 **/
68fd9910 1971void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1972{
3b644cf6 1973 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1974
3b644cf6 1975 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1976
1977 vfree(tx_ring->buffer_info);
1978 tx_ring->buffer_info = NULL;
1979
1980 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1981
1982 tx_ring->desc = NULL;
1983}
1984
1985/**
1986 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1987 * @adapter: board private structure
1988 *
1989 * Free all transmit software resources
1990 **/
1991static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1992{
1993 int i;
1994
1995 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1996 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1997}
1998
1999static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2000 struct igb_buffer *buffer_info)
2001{
2002 if (buffer_info->dma) {
2003 pci_unmap_page(adapter->pdev,
2004 buffer_info->dma,
2005 buffer_info->length,
2006 PCI_DMA_TODEVICE);
2007 buffer_info->dma = 0;
2008 }
2009 if (buffer_info->skb) {
2010 dev_kfree_skb_any(buffer_info->skb);
2011 buffer_info->skb = NULL;
2012 }
2013 buffer_info->time_stamp = 0;
2014 /* buffer_info must be completely set up in the transmit path */
2015}
2016
2017/**
2018 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2019 * @tx_ring: ring to be cleaned
2020 **/
3b644cf6 2021static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2022{
3b644cf6 2023 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2024 struct igb_buffer *buffer_info;
2025 unsigned long size;
2026 unsigned int i;
2027
2028 if (!tx_ring->buffer_info)
2029 return;
2030 /* Free all the Tx ring sk_buffs */
2031
2032 for (i = 0; i < tx_ring->count; i++) {
2033 buffer_info = &tx_ring->buffer_info[i];
2034 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2035 }
2036
2037 size = sizeof(struct igb_buffer) * tx_ring->count;
2038 memset(tx_ring->buffer_info, 0, size);
2039
2040 /* Zero out the descriptor ring */
2041
2042 memset(tx_ring->desc, 0, tx_ring->size);
2043
2044 tx_ring->next_to_use = 0;
2045 tx_ring->next_to_clean = 0;
2046
2047 writel(0, adapter->hw.hw_addr + tx_ring->head);
2048 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2049}
2050
2051/**
2052 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2053 * @adapter: board private structure
2054 **/
2055static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2056{
2057 int i;
2058
2059 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2060 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2061}
2062
2063/**
2064 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2065 * @rx_ring: ring to clean the resources from
2066 *
2067 * Free all receive software resources
2068 **/
68fd9910 2069void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2070{
3b644cf6 2071 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2072
3b644cf6 2073 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2074
2075 vfree(rx_ring->buffer_info);
2076 rx_ring->buffer_info = NULL;
2077
2078 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2079
2080 rx_ring->desc = NULL;
2081}
2082
2083/**
2084 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2085 * @adapter: board private structure
2086 *
2087 * Free all receive software resources
2088 **/
2089static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2090{
2091 int i;
2092
2093 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2094 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2095}
2096
2097/**
2098 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2099 * @rx_ring: ring to free buffers from
2100 **/
3b644cf6 2101static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2102{
3b644cf6 2103 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2104 struct igb_buffer *buffer_info;
2105 struct pci_dev *pdev = adapter->pdev;
2106 unsigned long size;
2107 unsigned int i;
2108
2109 if (!rx_ring->buffer_info)
2110 return;
2111 /* Free all the Rx ring sk_buffs */
2112 for (i = 0; i < rx_ring->count; i++) {
2113 buffer_info = &rx_ring->buffer_info[i];
2114 if (buffer_info->dma) {
2115 if (adapter->rx_ps_hdr_size)
2116 pci_unmap_single(pdev, buffer_info->dma,
2117 adapter->rx_ps_hdr_size,
2118 PCI_DMA_FROMDEVICE);
2119 else
2120 pci_unmap_single(pdev, buffer_info->dma,
2121 adapter->rx_buffer_len,
2122 PCI_DMA_FROMDEVICE);
2123 buffer_info->dma = 0;
2124 }
2125
2126 if (buffer_info->skb) {
2127 dev_kfree_skb(buffer_info->skb);
2128 buffer_info->skb = NULL;
2129 }
2130 if (buffer_info->page) {
bf36c1a0
AD		 2131 if (buffer_info->page_dma)
2132 pci_unmap_page(pdev, buffer_info->page_dma,
2133 PAGE_SIZE / 2,
2134 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2135 put_page(buffer_info->page);
2136 buffer_info->page = NULL;
2137 buffer_info->page_dma = 0;
bf36c1a0 2138 buffer_info->page_offset = 0;
9d5c8243
AK		 2139 }
2140 }
2141
9d5c8243
AK		 2142 size = sizeof(struct igb_buffer) * rx_ring->count;
2143 memset(rx_ring->buffer_info, 0, size);
2144
2145 /* Zero out the descriptor ring */
2146 memset(rx_ring->desc, 0, rx_ring->size);
2147
2148 rx_ring->next_to_clean = 0;
2149 rx_ring->next_to_use = 0;
2150
2151 writel(0, adapter->hw.hw_addr + rx_ring->head);
2152 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2153}
2154
2155/**
2156 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2157 * @adapter: board private structure
2158 **/
2159static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2160{
2161 int i;
2162
2163 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2164 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2165}
2166
2167/**
2168 * igb_set_mac - Change the Ethernet Address of the NIC
2169 * @netdev: network interface device structure
2170 * @p: pointer to an address structure
2171 *
2172 * Returns 0 on success, negative on failure
2173 **/
2174static int igb_set_mac(struct net_device *netdev, void *p)
2175{
2176 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2177 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2178 struct sockaddr *addr = p;
2179
2180 if (!is_valid_ether_addr(addr->sa_data))
2181 return -EADDRNOTAVAIL;
2182
2183 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2184 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2185
28b0759c 2186 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243
AK		 2187
2188 return 0;
2189}
2190
2191/**
2192 * igb_set_multi - Multicast and Promiscuous mode set
2193 * @netdev: network interface device structure
2194 *
2195 * The set_multi entry point is called whenever the multicast address
2196 * list or the network interface flags are updated. This routine is
2197 * responsible for configuring the hardware for proper multicast,
2198 * promiscuous mode, and all-multi behavior.
2199 **/
2200static void igb_set_multi(struct net_device *netdev)
2201{
2202 struct igb_adapter *adapter = netdev_priv(netdev);
2203 struct e1000_hw *hw = &adapter->hw;
2204 struct e1000_mac_info *mac = &hw->mac;
2205 struct dev_mc_list *mc_ptr;
2206 u8 *mta_list;
2207 u32 rctl;
2208 int i;
2209
2210 /* Check for Promiscuous and All Multicast modes */
2211
2212 rctl = rd32(E1000_RCTL);
2213
746b9f02 2214 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2215 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2216 rctl &= ~E1000_RCTL_VFE;
2217 } else {
2218 if (netdev->flags & IFF_ALLMULTI) {
2219 rctl |= E1000_RCTL_MPE;
2220 rctl &= ~E1000_RCTL_UPE;
2221 } else
2222 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2223 rctl |= E1000_RCTL_VFE;
746b9f02 2224 }
9d5c8243
AK		 2225 wr32(E1000_RCTL, rctl);
2226
2227 if (!netdev->mc_count) {
2228 /* nothing to program, so clear mc list */
8a900862
AD		 2229 igb_update_mc_addr_list(hw, NULL, 0, 1,
2230 mac->rar_entry_count);
9d5c8243
AK		 2231 return;
2232 }
2233
2234 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2235 if (!mta_list)
2236 return;
2237
2238 /* The shared function expects a packed array of only addresses. */
2239 mc_ptr = netdev->mc_list;
2240
2241 for (i = 0; i < netdev->mc_count; i++) {
2242 if (!mc_ptr)
2243 break;
2244 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2245 mc_ptr = mc_ptr->next;
2246 }
8a900862 2247 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2248 kfree(mta_list);
2249}
2250
2251/* Need to wait a few seconds after link up to get diagnostic information from
2252 * the phy */
2253static void igb_update_phy_info(unsigned long data)
2254{
2255 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2256 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2257}
2258
4d6b725e
AD		 2259/**
2260 * igb_has_link - check shared code for link and determine up/down
2261 * @adapter: pointer to driver private info
2262 **/
2263static bool igb_has_link(struct igb_adapter *adapter)
2264{
2265 struct e1000_hw *hw = &adapter->hw;
2266 bool link_active = false;
2267 s32 ret_val = 0;
2268
2269 /* get_link_status is set on LSC (link status) interrupt or
2270 * rx sequence error interrupt. get_link_status will stay
2271 * false until the e1000_check_for_link establishes link
2272 * for copper adapters ONLY
2273 */
2274 switch (hw->phy.media_type) {
2275 case e1000_media_type_copper:
2276 if (hw->mac.get_link_status) {
2277 ret_val = hw->mac.ops.check_for_link(hw);
2278 link_active = !hw->mac.get_link_status;
2279 } else {
2280 link_active = true;
2281 }
2282 break;
2283 case e1000_media_type_fiber:
2284 ret_val = hw->mac.ops.check_for_link(hw);
2285 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2286 break;
2287 case e1000_media_type_internal_serdes:
2288 ret_val = hw->mac.ops.check_for_link(hw);
2289 link_active = hw->mac.serdes_has_link;
2290 break;
2291 default:
2292 case e1000_media_type_unknown:
2293 break;
2294 }
2295
2296 return link_active;
2297}
2298
9d5c8243
AK		 2299/**
2300 * igb_watchdog - Timer Call-back
2301 * @data: pointer to adapter cast into an unsigned long
2302 **/
2303static void igb_watchdog(unsigned long data)
2304{
2305 struct igb_adapter *adapter = (struct igb_adapter *)data;
2306 /* Do the rest outside of interrupt context */
2307 schedule_work(&adapter->watchdog_task);
2308}
2309
2310static void igb_watchdog_task(struct work_struct *work)
2311{
2312 struct igb_adapter *adapter = container_of(work,
2313 struct igb_adapter, watchdog_task);
2314 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2315 struct net_device *netdev = adapter->netdev;
2316 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2317 u32 link;
7a6ea550 2318 u32 eics = 0;
7a6ea550 2319 int i;
9d5c8243 2320
4d6b725e
AD		 2321 link = igb_has_link(adapter);
2322 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2323 goto link_up;
2324
9d5c8243
AK		 2325 if (link) {
2326 if (!netif_carrier_ok(netdev)) {
2327 u32 ctrl;
2328 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2329 &adapter->link_speed,
2330 &adapter->link_duplex);
2331
2332 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2333 /* Links status message must follow this format */
2334 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2335 "Flow Control: %s\n",
527d47c1 2336 netdev->name,
9d5c8243
AK		 2337 adapter->link_speed,
2338 adapter->link_duplex == FULL_DUPLEX ?
2339 "Full Duplex" : "Half Duplex",
2340 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2341 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2342 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2343 E1000_CTRL_TFCE) ? "TX" : "None")));
2344
2345 /* tweak tx_queue_len according to speed/duplex and
2346 * adjust the timeout factor */
2347 netdev->tx_queue_len = adapter->tx_queue_len;
2348 adapter->tx_timeout_factor = 1;
2349 switch (adapter->link_speed) {
2350 case SPEED_10:
2351 netdev->tx_queue_len = 10;
2352 adapter->tx_timeout_factor = 14;
2353 break;
2354 case SPEED_100:
2355 netdev->tx_queue_len = 100;
2356 /* maybe add some timeout factor ? */
2357 break;
2358 }
2359
2360 netif_carrier_on(netdev);
fd2ea0a7 2361 netif_tx_wake_all_queues(netdev);
9d5c8243 2362
4b1a9877 2363 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2364 if (!test_bit(__IGB_DOWN, &adapter->state))
2365 mod_timer(&adapter->phy_info_timer,
2366 round_jiffies(jiffies + 2 * HZ));
2367 }
2368 } else {
2369 if (netif_carrier_ok(netdev)) {
2370 adapter->link_speed = 0;
2371 adapter->link_duplex = 0;
527d47c1
AD		 2372 /* Links status message must follow this format */
2373 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2374 netdev->name);
9d5c8243 2375 netif_carrier_off(netdev);
fd2ea0a7 2376 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2377
2378 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2379 if (!test_bit(__IGB_DOWN, &adapter->state))
2380 mod_timer(&adapter->phy_info_timer,
2381 round_jiffies(jiffies + 2 * HZ));
2382 }
2383 }
2384
2385link_up:
2386 igb_update_stats(adapter);
2387
4b1a9877 2388 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2389 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2390 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2391 adapter->colc_old = adapter->stats.colc;
2392
2393 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2394 adapter->gorc_old = adapter->stats.gorc;
2395 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2396 adapter->gotc_old = adapter->stats.gotc;
2397
2398 igb_update_adaptive(&adapter->hw);
2399
2400 if (!netif_carrier_ok(netdev)) {
2401 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2402 /* We've lost link, so the controller stops DMA,
2403 * but we've got queued Tx work that's never going
2404 * to get done, so reset controller to flush Tx.
2405 * (Do the reset outside of interrupt context). */
2406 adapter->tx_timeout_count++;
2407 schedule_work(&adapter->reset_task);
2408 }
2409 }
2410
2411 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2412 if (adapter->msix_entries) {
2413 for (i = 0; i < adapter->num_rx_queues; i++)
2414 eics |= adapter->rx_ring[i].eims_value;
2415 wr32(E1000_EICS, eics);
2416 } else {
2417 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2418 }
9d5c8243
AK		 2419
2420 /* Force detection of hung controller every watchdog period */
2421 tx_ring->detect_tx_hung = true;
2422
2423 /* Reset the timer */
2424 if (!test_bit(__IGB_DOWN, &adapter->state))
2425 mod_timer(&adapter->watchdog_timer,
2426 round_jiffies(jiffies + 2 * HZ));
2427}
2428
2429enum latency_range {
2430 lowest_latency = 0,
2431 low_latency = 1,
2432 bulk_latency = 2,
2433 latency_invalid = 255
2434};
2435
2436
6eb5a7f1
AD		 2437/**
2438 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2439 *
2440 * Stores a new ITR value based on strictly on packet size. This
2441 * algorithm is less sophisticated than that used in igb_update_itr,
2442 * due to the difficulty of synchronizing statistics across multiple
2443 * receive rings. The divisors and thresholds used by this fuction
2444 * were determined based on theoretical maximum wire speed and testing
2445 * data, in order to minimize response time while increasing bulk
2446 * throughput.
2447 * This functionality is controlled by the InterruptThrottleRate module
2448 * parameter (see igb_param.c)
2449 * NOTE: This function is called only when operating in a multiqueue
2450 * receive environment.
2451 * @rx_ring: pointer to ring
2452 **/
2453static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2454{
6eb5a7f1
AD		 2455 int new_val = rx_ring->itr_val;
2456 int avg_wire_size = 0;
2457 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2458
6eb5a7f1
AD		 2459 if (!rx_ring->total_packets)
2460 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2461
6eb5a7f1
AD		 2462 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2463 * ints/sec - ITR timer value of 120 ticks.
2464 */
2465 if (adapter->link_speed != SPEED_1000) {
2466 new_val = 120;
2467 goto set_itr_val;
9d5c8243 2468 }
6eb5a7f1 2469 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2470
6eb5a7f1
AD		 2471 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2472 avg_wire_size += 24;
2473
2474 /* Don't starve jumbo frames */
2475 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2476
6eb5a7f1
AD		 2477 /* Give a little boost to mid-size frames */
2478 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2479 new_val = avg_wire_size / 3;
2480 else
2481 new_val = avg_wire_size / 2;
9d5c8243 2482
6eb5a7f1 2483set_itr_val:
9d5c8243
AK		 2484 if (new_val != rx_ring->itr_val) {
2485 rx_ring->itr_val = new_val;
6eb5a7f1 2486 rx_ring->set_itr = 1;
9d5c8243 2487 }
6eb5a7f1
AD		 2488clear_counts:
2489 rx_ring->total_bytes = 0;
2490 rx_ring->total_packets = 0;
9d5c8243
AK		 2491}
2492
2493/**
2494 * igb_update_itr - update the dynamic ITR value based on statistics
2495 * Stores a new ITR value based on packets and byte
2496 * counts during the last interrupt. The advantage of per interrupt
2497 * computation is faster updates and more accurate ITR for the current
2498 * traffic pattern. Constants in this function were computed
2499 * based on theoretical maximum wire speed and thresholds were set based
2500 * on testing data as well as attempting to minimize response time
2501 * while increasing bulk throughput.
2502 * this functionality is controlled by the InterruptThrottleRate module
2503 * parameter (see igb_param.c)
2504 * NOTE: These calculations are only valid when operating in a single-
2505 * queue environment.
2506 * @adapter: pointer to adapter
2507 * @itr_setting: current adapter->itr
2508 * @packets: the number of packets during this measurement interval
2509 * @bytes: the number of bytes during this measurement interval
2510 **/
2511static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2512 int packets, int bytes)
2513{
2514 unsigned int retval = itr_setting;
2515
2516 if (packets == 0)
2517 goto update_itr_done;
2518
2519 switch (itr_setting) {
2520 case lowest_latency:
2521 /* handle TSO and jumbo frames */
2522 if (bytes/packets > 8000)
2523 retval = bulk_latency;
2524 else if ((packets < 5) && (bytes > 512))
2525 retval = low_latency;
2526 break;
2527 case low_latency: /* 50 usec aka 20000 ints/s */
2528 if (bytes > 10000) {
2529 /* this if handles the TSO accounting */
2530 if (bytes/packets > 8000) {
2531 retval = bulk_latency;
2532 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2533 retval = bulk_latency;
2534 } else if ((packets > 35)) {
2535 retval = lowest_latency;
2536 }
2537 } else if (bytes/packets > 2000) {
2538 retval = bulk_latency;
2539 } else if (packets <= 2 && bytes < 512) {
2540 retval = lowest_latency;
2541 }
2542 break;
2543 case bulk_latency: /* 250 usec aka 4000 ints/s */
2544 if (bytes > 25000) {
2545 if (packets > 35)
2546 retval = low_latency;
2547 } else if (bytes < 6000) {
2548 retval = low_latency;
2549 }
2550 break;
2551 }
2552
2553update_itr_done:
2554 return retval;
2555}
2556
6eb5a7f1 2557static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2558{
2559 u16 current_itr;
2560 u32 new_itr = adapter->itr;
2561
2562 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2563 if (adapter->link_speed != SPEED_1000) {
2564 current_itr = 0;
2565 new_itr = 4000;
2566 goto set_itr_now;
2567 }
2568
2569 adapter->rx_itr = igb_update_itr(adapter,
2570 adapter->rx_itr,
2571 adapter->rx_ring->total_packets,
2572 adapter->rx_ring->total_bytes);
9d5c8243 2573
6eb5a7f1 2574 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2575 adapter->tx_itr = igb_update_itr(adapter,
2576 adapter->tx_itr,
2577 adapter->tx_ring->total_packets,
2578 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2579
2580 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2581 } else {
2582 current_itr = adapter->rx_itr;
2583 }
2584
6eb5a7f1
AD		 2585 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2586 if (adapter->itr_setting == 3 &&
2587 current_itr == lowest_latency)
2588 current_itr = low_latency;
2589
9d5c8243
AK		 2590 switch (current_itr) {
2591 /* counts and packets in update_itr are dependent on these numbers */
2592 case lowest_latency:
2593 new_itr = 70000;
2594 break;
2595 case low_latency:
2596 new_itr = 20000; /* aka hwitr = ~200 */
2597 break;
2598 case bulk_latency:
2599 new_itr = 4000;
2600 break;
2601 default:
2602 break;
2603 }
2604
2605set_itr_now:
6eb5a7f1
AD		 2606 adapter->rx_ring->total_bytes = 0;
2607 adapter->rx_ring->total_packets = 0;
2608 if (adapter->rx_ring->buddy) {
2609 adapter->rx_ring->buddy->total_bytes = 0;
2610 adapter->rx_ring->buddy->total_packets = 0;
2611 }
2612
9d5c8243
AK		 2613 if (new_itr != adapter->itr) {
2614 /* this attempts to bias the interrupt rate towards Bulk
2615 * by adding intermediate steps when interrupt rate is
2616 * increasing */
2617 new_itr = new_itr > adapter->itr ?
2618 min(adapter->itr + (new_itr >> 2), new_itr) :
2619 new_itr;
2620 /* Don't write the value here; it resets the adapter's
2621 * internal timer, and causes us to delay far longer than
2622 * we should between interrupts. Instead, we write the ITR
2623 * value at the beginning of the next interrupt so the timing
2624 * ends up being correct.
2625 */
2626 adapter->itr = new_itr;
6eb5a7f1
AD		 2627 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2628 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2629 }
2630
2631 return;
2632}
2633
2634
2635#define IGB_TX_FLAGS_CSUM 0x00000001
2636#define IGB_TX_FLAGS_VLAN 0x00000002
2637#define IGB_TX_FLAGS_TSO 0x00000004
2638#define IGB_TX_FLAGS_IPV4 0x00000008
2639#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2640#define IGB_TX_FLAGS_VLAN_SHIFT 16
2641
2642static inline int igb_tso_adv(struct igb_adapter *adapter,
2643 struct igb_ring *tx_ring,
2644 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2645{
2646 struct e1000_adv_tx_context_desc *context_desc;
2647 unsigned int i;
2648 int err;
2649 struct igb_buffer *buffer_info;
2650 u32 info = 0, tu_cmd = 0;
2651 u32 mss_l4len_idx, l4len;
2652 *hdr_len = 0;
2653
2654 if (skb_header_cloned(skb)) {
2655 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2656 if (err)
2657 return err;
2658 }
2659
2660 l4len = tcp_hdrlen(skb);
2661 *hdr_len += l4len;
2662
2663 if (skb->protocol == htons(ETH_P_IP)) {
2664 struct iphdr *iph = ip_hdr(skb);
2665 iph->tot_len = 0;
2666 iph->check = 0;
2667 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2668 iph->daddr, 0,
2669 IPPROTO_TCP,
2670 0);
2671 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2672 ipv6_hdr(skb)->payload_len = 0;
2673 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2674 &ipv6_hdr(skb)->daddr,
2675 0, IPPROTO_TCP, 0);
2676 }
2677
2678 i = tx_ring->next_to_use;
2679
2680 buffer_info = &tx_ring->buffer_info[i];
2681 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2682 /* VLAN MACLEN IPLEN */
2683 if (tx_flags & IGB_TX_FLAGS_VLAN)
2684 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2685 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2686 *hdr_len += skb_network_offset(skb);
2687 info |= skb_network_header_len(skb);
2688 *hdr_len += skb_network_header_len(skb);
2689 context_desc->vlan_macip_lens = cpu_to_le32(info);
2690
2691 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2692 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2693
2694 if (skb->protocol == htons(ETH_P_IP))
2695 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2696 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2697
2698 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2699
2700 /* MSS L4LEN IDX */
2701 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2702 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2703
7dfc16fa
AD		 2704 /* Context index must be unique per ring. */
2705 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2706 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2707
2708 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2709 context_desc->seqnum_seed = 0;
2710
2711 buffer_info->time_stamp = jiffies;
0e014cb1 2712 buffer_info->next_to_watch = i;
9d5c8243
AK		 2713 buffer_info->dma = 0;
2714 i++;
2715 if (i == tx_ring->count)
2716 i = 0;
2717
2718 tx_ring->next_to_use = i;
2719
2720 return true;
2721}
2722
2723static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2724 struct igb_ring *tx_ring,
2725 struct sk_buff *skb, u32 tx_flags)
2726{
2727 struct e1000_adv_tx_context_desc *context_desc;
2728 unsigned int i;
2729 struct igb_buffer *buffer_info;
2730 u32 info = 0, tu_cmd = 0;
2731
2732 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2733 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2734 i = tx_ring->next_to_use;
2735 buffer_info = &tx_ring->buffer_info[i];
2736 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2737
2738 if (tx_flags & IGB_TX_FLAGS_VLAN)
2739 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2740 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2741 if (skb->ip_summed == CHECKSUM_PARTIAL)
2742 info |= skb_network_header_len(skb);
2743
2744 context_desc->vlan_macip_lens = cpu_to_le32(info);
2745
2746 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2747
2748 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2749 switch (skb->protocol) {
09640e63 2750 case cpu_to_be16(ETH_P_IP):
9d5c8243 2751 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2752 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2753 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2754 break;
09640e63 2755 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2756 /* XXX what about other V6 headers?? */
2757 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2758 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2759 break;
2760 default:
2761 if (unlikely(net_ratelimit()))
2762 dev_warn(&adapter->pdev->dev,
2763 "partial checksum but proto=%x!\n",
2764 skb->protocol);
2765 break;
2766 }
9d5c8243
AK		 2767 }
2768
2769 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2770 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2771 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2772 context_desc->mss_l4len_idx =
2773 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2774
2775 buffer_info->time_stamp = jiffies;
0e014cb1 2776 buffer_info->next_to_watch = i;
9d5c8243
AK		 2777 buffer_info->dma = 0;
2778
2779 i++;
2780 if (i == tx_ring->count)
2781 i = 0;
2782 tx_ring->next_to_use = i;
2783
2784 return true;
2785 }
2786
2787
2788 return false;
2789}
2790
2791#define IGB_MAX_TXD_PWR 16
2792#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2793
2794static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2795 struct igb_ring *tx_ring, struct sk_buff *skb,
2796 unsigned int first)
9d5c8243
AK		 2797{
2798 struct igb_buffer *buffer_info;
2799 unsigned int len = skb_headlen(skb);
2800 unsigned int count = 0, i;
2801 unsigned int f;
2802
2803 i = tx_ring->next_to_use;
2804
2805 buffer_info = &tx_ring->buffer_info[i];
2806 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2807 buffer_info->length = len;
2808 /* set time_stamp *before* dma to help avoid a possible race */
2809 buffer_info->time_stamp = jiffies;
0e014cb1 2810 buffer_info->next_to_watch = i;
9d5c8243
AK		 2811 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2812 PCI_DMA_TODEVICE);
2813 count++;
2814 i++;
2815 if (i == tx_ring->count)
2816 i = 0;
2817
2818 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2819 struct skb_frag_struct *frag;
2820
2821 frag = &skb_shinfo(skb)->frags[f];
2822 len = frag->size;
2823
2824 buffer_info = &tx_ring->buffer_info[i];
2825 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2826 buffer_info->length = len;
2827 buffer_info->time_stamp = jiffies;
0e014cb1 2828 buffer_info->next_to_watch = i;
9d5c8243
AK		 2829 buffer_info->dma = pci_map_page(adapter->pdev,
2830 frag->page,
2831 frag->page_offset,
2832 len,
2833 PCI_DMA_TODEVICE);
2834
2835 count++;
2836 i++;
2837 if (i == tx_ring->count)
2838 i = 0;
2839 }
2840
0e014cb1 2841 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2842 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2843 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2844
2845 return count;
2846}
2847
2848static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2849 struct igb_ring *tx_ring,
2850 int tx_flags, int count, u32 paylen,
2851 u8 hdr_len)
2852{
2853 union e1000_adv_tx_desc *tx_desc = NULL;
2854 struct igb_buffer *buffer_info;
2855 u32 olinfo_status = 0, cmd_type_len;
2856 unsigned int i;
2857
2858 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2859 E1000_ADVTXD_DCMD_DEXT);
2860
2861 if (tx_flags & IGB_TX_FLAGS_VLAN)
2862 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2863
2864 if (tx_flags & IGB_TX_FLAGS_TSO) {
2865 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2866
2867 /* insert tcp checksum */
2868 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2869
2870 /* insert ip checksum */
2871 if (tx_flags & IGB_TX_FLAGS_IPV4)
2872 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2873
2874 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2875 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2876 }
2877
7dfc16fa
AD		 2878 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2879 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2880 IGB_TX_FLAGS_VLAN)))
661086df 2881 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2882
2883 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2884
2885 i = tx_ring->next_to_use;
2886 while (count--) {
2887 buffer_info = &tx_ring->buffer_info[i];
2888 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2889 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2890 tx_desc->read.cmd_type_len =
2891 cpu_to_le32(cmd_type_len | buffer_info->length);
2892 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2893 i++;
2894 if (i == tx_ring->count)
2895 i = 0;
2896 }
2897
2898 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2899 /* Force memory writes to complete before letting h/w
2900 * know there are new descriptors to fetch. (Only
2901 * applicable for weak-ordered memory model archs,
2902 * such as IA-64). */
2903 wmb();
2904
2905 tx_ring->next_to_use = i;
2906 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2907 /* we need this if more than one processor can write to our tail
2908 * at a time, it syncronizes IO on IA64/Altix systems */
2909 mmiowb();
2910}
2911
2912static int __igb_maybe_stop_tx(struct net_device *netdev,
2913 struct igb_ring *tx_ring, int size)
2914{
2915 struct igb_adapter *adapter = netdev_priv(netdev);
2916
661086df 2917 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2918
9d5c8243
AK		 2919 /* Herbert's original patch had:
2920 * smp_mb__after_netif_stop_queue();
2921 * but since that doesn't exist yet, just open code it. */
2922 smp_mb();
2923
2924 /* We need to check again in a case another CPU has just
2925 * made room available. */
2926 if (IGB_DESC_UNUSED(tx_ring) < size)
2927 return -EBUSY;
2928
2929 /* A reprieve! */
661086df 2930 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2931 ++adapter->restart_queue;
2932 return 0;
2933}
2934
2935static int igb_maybe_stop_tx(struct net_device *netdev,
2936 struct igb_ring *tx_ring, int size)
2937{
2938 if (IGB_DESC_UNUSED(tx_ring) >= size)
2939 return 0;
2940 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2941}
2942
2943#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2944
2945static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2946 struct net_device *netdev,
2947 struct igb_ring *tx_ring)
2948{
2949 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2950 unsigned int first;
9d5c8243
AK		 2951 unsigned int tx_flags = 0;
2952 unsigned int len;
9d5c8243
AK		 2953 u8 hdr_len = 0;
2954 int tso = 0;
2955
2956 len = skb_headlen(skb);
2957
2958 if (test_bit(__IGB_DOWN, &adapter->state)) {
2959 dev_kfree_skb_any(skb);
2960 return NETDEV_TX_OK;
2961 }
2962
2963 if (skb->len <= 0) {
2964 dev_kfree_skb_any(skb);
2965 return NETDEV_TX_OK;
2966 }
2967
9d5c8243
AK		 2968 /* need: 1 descriptor per page,
2969 * + 2 desc gap to keep tail from touching head,
2970 * + 1 desc for skb->data,
2971 * + 1 desc for context descriptor,
2972 * otherwise try next time */
2973 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2974 /* this is a hard error */
9d5c8243
AK		 2975 return NETDEV_TX_BUSY;
2976 }
6eb5a7f1 2977 skb_orphan(skb);
9d5c8243
AK		 2978
2979 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2980 tx_flags |= IGB_TX_FLAGS_VLAN;
2981 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2982 }
2983
661086df
PWJ		 2984 if (skb->protocol == htons(ETH_P_IP))
2985 tx_flags |= IGB_TX_FLAGS_IPV4;
2986
0e014cb1
AD		 2987 first = tx_ring->next_to_use;
2988
9d5c8243
AK		 2989 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2990 &hdr_len) : 0;
2991
2992 if (tso < 0) {
2993 dev_kfree_skb_any(skb);
9d5c8243
AK		 2994 return NETDEV_TX_OK;
2995 }
2996
2997 if (tso)
2998 tx_flags |= IGB_TX_FLAGS_TSO;
2999 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3000 if (skb->ip_summed == CHECKSUM_PARTIAL)
3001 tx_flags |= IGB_TX_FLAGS_CSUM;
3002
9d5c8243 3003 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3004 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3005 skb->len, hdr_len);
3006
3007 netdev->trans_start = jiffies;
3008
3009 /* Make sure there is space in the ring for the next send. */
3010 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3011
9d5c8243
AK		 3012 return NETDEV_TX_OK;
3013}
3014
3015static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3016{
3017 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3018 struct igb_ring *tx_ring;
3019
661086df
PWJ		 3020 int r_idx = 0;
3021 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3022 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3023
3024 /* This goes back to the question of how to logically map a tx queue
3025 * to a flow. Right now, performance is impacted slightly negatively
3026 * if using multiple tx queues. If the stack breaks away from a
3027 * single qdisc implementation, we can look at this again. */
3028 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3029}
3030
3031/**
3032 * igb_tx_timeout - Respond to a Tx Hang
3033 * @netdev: network interface device structure
3034 **/
3035static void igb_tx_timeout(struct net_device *netdev)
3036{
3037 struct igb_adapter *adapter = netdev_priv(netdev);
3038 struct e1000_hw *hw = &adapter->hw;
3039
3040 /* Do the reset outside of interrupt context */
3041 adapter->tx_timeout_count++;
3042 schedule_work(&adapter->reset_task);
3043 wr32(E1000_EICS, adapter->eims_enable_mask &
3044 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3045}
3046
3047static void igb_reset_task(struct work_struct *work)
3048{
3049 struct igb_adapter *adapter;
3050 adapter = container_of(work, struct igb_adapter, reset_task);
3051
3052 igb_reinit_locked(adapter);
3053}
3054
3055/**
3056 * igb_get_stats - Get System Network Statistics
3057 * @netdev: network interface device structure
3058 *
3059 * Returns the address of the device statistics structure.
3060 * The statistics are actually updated from the timer callback.
3061 **/
3062static struct net_device_stats *
3063igb_get_stats(struct net_device *netdev)
3064{
3065 struct igb_adapter *adapter = netdev_priv(netdev);
3066
3067 /* only return the current stats */
3068 return &adapter->net_stats;
3069}
3070
3071/**
3072 * igb_change_mtu - Change the Maximum Transfer Unit
3073 * @netdev: network interface device structure
3074 * @new_mtu: new value for maximum frame size
3075 *
3076 * Returns 0 on success, negative on failure
3077 **/
3078static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3079{
3080 struct igb_adapter *adapter = netdev_priv(netdev);
3081 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3082
3083 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3084 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3085 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3086 return -EINVAL;
3087 }
3088
3089#define MAX_STD_JUMBO_FRAME_SIZE 9234
3090 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3091 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3092 return -EINVAL;
3093 }
3094
3095 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3096 msleep(1);
3097 /* igb_down has a dependency on max_frame_size */
3098 adapter->max_frame_size = max_frame;
3099 if (netif_running(netdev))
3100 igb_down(adapter);
3101
3102 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3103 * means we reserve 2 more, this pushes us to allocate from the next
3104 * larger slab size.
3105 * i.e. RXBUFFER_2048 --> size-4096 slab
3106 */
3107
3108 if (max_frame <= IGB_RXBUFFER_256)
3109 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3110 else if (max_frame <= IGB_RXBUFFER_512)
3111 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3112 else if (max_frame <= IGB_RXBUFFER_1024)
3113 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3114 else if (max_frame <= IGB_RXBUFFER_2048)
3115 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3116 else
bf36c1a0
AD		 3117#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3118 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3119#else
3120 adapter->rx_buffer_len = PAGE_SIZE / 2;
3121#endif
9d5c8243
AK		 3122 /* adjust allocation if LPE protects us, and we aren't using SBP */
3123 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3124 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3125 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3126
3127 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3128 netdev->mtu, new_mtu);
3129 netdev->mtu = new_mtu;
3130
3131 if (netif_running(netdev))
3132 igb_up(adapter);
3133 else
3134 igb_reset(adapter);
3135
3136 clear_bit(__IGB_RESETTING, &adapter->state);
3137
3138 return 0;
3139}
3140
3141/**
3142 * igb_update_stats - Update the board statistics counters
3143 * @adapter: board private structure
3144 **/
3145
3146void igb_update_stats(struct igb_adapter *adapter)
3147{
3148 struct e1000_hw *hw = &adapter->hw;
3149 struct pci_dev *pdev = adapter->pdev;
3150 u16 phy_tmp;
3151
3152#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3153
3154 /*
3155 * Prevent stats update while adapter is being reset, or if the pci
3156 * connection is down.
3157 */
3158 if (adapter->link_speed == 0)
3159 return;
3160 if (pci_channel_offline(pdev))
3161 return;
3162
3163 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3164 adapter->stats.gprc += rd32(E1000_GPRC);
3165 adapter->stats.gorc += rd32(E1000_GORCL);
3166 rd32(E1000_GORCH); /* clear GORCL */
3167 adapter->stats.bprc += rd32(E1000_BPRC);
3168 adapter->stats.mprc += rd32(E1000_MPRC);
3169 adapter->stats.roc += rd32(E1000_ROC);
3170
3171 adapter->stats.prc64 += rd32(E1000_PRC64);
3172 adapter->stats.prc127 += rd32(E1000_PRC127);
3173 adapter->stats.prc255 += rd32(E1000_PRC255);
3174 adapter->stats.prc511 += rd32(E1000_PRC511);
3175 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3176 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3177 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3178 adapter->stats.sec += rd32(E1000_SEC);
3179
3180 adapter->stats.mpc += rd32(E1000_MPC);
3181 adapter->stats.scc += rd32(E1000_SCC);
3182 adapter->stats.ecol += rd32(E1000_ECOL);
3183 adapter->stats.mcc += rd32(E1000_MCC);
3184 adapter->stats.latecol += rd32(E1000_LATECOL);
3185 adapter->stats.dc += rd32(E1000_DC);
3186 adapter->stats.rlec += rd32(E1000_RLEC);
3187 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3188 adapter->stats.xontxc += rd32(E1000_XONTXC);
3189 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3190 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3191 adapter->stats.fcruc += rd32(E1000_FCRUC);
3192 adapter->stats.gptc += rd32(E1000_GPTC);
3193 adapter->stats.gotc += rd32(E1000_GOTCL);
3194 rd32(E1000_GOTCH); /* clear GOTCL */
3195 adapter->stats.rnbc += rd32(E1000_RNBC);
3196 adapter->stats.ruc += rd32(E1000_RUC);
3197 adapter->stats.rfc += rd32(E1000_RFC);
3198 adapter->stats.rjc += rd32(E1000_RJC);
3199 adapter->stats.tor += rd32(E1000_TORH);
3200 adapter->stats.tot += rd32(E1000_TOTH);
3201 adapter->stats.tpr += rd32(E1000_TPR);
3202
3203 adapter->stats.ptc64 += rd32(E1000_PTC64);
3204 adapter->stats.ptc127 += rd32(E1000_PTC127);
3205 adapter->stats.ptc255 += rd32(E1000_PTC255);
3206 adapter->stats.ptc511 += rd32(E1000_PTC511);
3207 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3208 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3209
3210 adapter->stats.mptc += rd32(E1000_MPTC);
3211 adapter->stats.bptc += rd32(E1000_BPTC);
3212
3213 /* used for adaptive IFS */
3214
3215 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3216 adapter->stats.tpt += hw->mac.tx_packet_delta;
3217 hw->mac.collision_delta = rd32(E1000_COLC);
3218 adapter->stats.colc += hw->mac.collision_delta;
3219
3220 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3221 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3222 adapter->stats.tncrs += rd32(E1000_TNCRS);
3223 adapter->stats.tsctc += rd32(E1000_TSCTC);
3224 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3225
3226 adapter->stats.iac += rd32(E1000_IAC);
3227 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3228 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3229 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3230 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3231 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3232 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3233 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3234 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3235
3236 /* Fill out the OS statistics structure */
3237 adapter->net_stats.multicast = adapter->stats.mprc;
3238 adapter->net_stats.collisions = adapter->stats.colc;
3239
3240 /* Rx Errors */
3241
3242 /* RLEC on some newer hardware can be incorrect so build
3243 * our own version based on RUC and ROC */
3244 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3245 adapter->stats.crcerrs + adapter->stats.algnerrc +
3246 adapter->stats.ruc + adapter->stats.roc +
3247 adapter->stats.cexterr;
3248 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3249 adapter->stats.roc;
3250 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3251 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3252 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3253
3254 /* Tx Errors */
3255 adapter->net_stats.tx_errors = adapter->stats.ecol +
3256 adapter->stats.latecol;
3257 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3258 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3259 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3260
3261 /* Tx Dropped needs to be maintained elsewhere */
3262
3263 /* Phy Stats */
3264 if (hw->phy.media_type == e1000_media_type_copper) {
3265 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3266 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3267 &phy_tmp))) {
3268 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3269 adapter->phy_stats.idle_errors += phy_tmp;
3270 }
3271 }
3272
3273 /* Management Stats */
3274 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3275 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3276 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3277}
3278
3279
3280static irqreturn_t igb_msix_other(int irq, void *data)
3281{
3282 struct net_device *netdev = data;
3283 struct igb_adapter *adapter = netdev_priv(netdev);
3284 struct e1000_hw *hw = &adapter->hw;
844290e5 3285 u32 icr = rd32(E1000_ICR);
9d5c8243 3286
844290e5 3287 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3288
3289 if(icr & E1000_ICR_DOUTSYNC) {
3290 /* HW is reporting DMA is out of sync */
3291 adapter->stats.doosync++;
3292 }
844290e5
PW		 3293 if (!(icr & E1000_ICR_LSC))
3294 goto no_link_interrupt;
3295 hw->mac.get_link_status = 1;
3296 /* guard against interrupt when we're going down */
3297 if (!test_bit(__IGB_DOWN, &adapter->state))
3298 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3299
9d5c8243 3300no_link_interrupt:
dda0e083 3301 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3302 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3303
3304 return IRQ_HANDLED;
3305}
3306
3307static irqreturn_t igb_msix_tx(int irq, void *data)
3308{
3309 struct igb_ring *tx_ring = data;
3310 struct igb_adapter *adapter = tx_ring->adapter;
3311 struct e1000_hw *hw = &adapter->hw;
3312
421e02f0 3313#ifdef CONFIG_IGB_DCA
7dfc16fa 3314 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3315 igb_update_tx_dca(tx_ring);
3316#endif
9d5c8243
AK		 3317 tx_ring->total_bytes = 0;
3318 tx_ring->total_packets = 0;
661086df
PWJ		 3319
3320 /* auto mask will automatically reenable the interrupt when we write
3321 * EICS */
3b644cf6 3322 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3323 /* Ring was not completely cleaned, so fire another interrupt */
3324 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3325 else
9d5c8243 3326 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3327
9d5c8243
AK		 3328 return IRQ_HANDLED;
3329}
3330
6eb5a7f1
AD		 3331static void igb_write_itr(struct igb_ring *ring)
3332{
3333 struct e1000_hw *hw = &ring->adapter->hw;
3334 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3335 switch (hw->mac.type) {
3336 case e1000_82576:
3337 wr32(ring->itr_register,
3338 ring->itr_val |
3339 0x80000000);
3340 break;
3341 default:
3342 wr32(ring->itr_register,
3343 ring->itr_val |
3344 (ring->itr_val << 16));
3345 break;
3346 }
3347 ring->set_itr = 0;
3348 }
3349}
3350
9d5c8243
AK		 3351static irqreturn_t igb_msix_rx(int irq, void *data)
3352{
3353 struct igb_ring *rx_ring = data;
9d5c8243 3354
844290e5
PW		 3355 /* Write the ITR value calculated at the end of the
3356 * previous interrupt.
3357 */
9d5c8243 3358
6eb5a7f1 3359 igb_write_itr(rx_ring);
9d5c8243 3360
288379f0
BH		 3361 if (napi_schedule_prep(&rx_ring->napi))
3362 __napi_schedule(&rx_ring->napi);
844290e5 3363
421e02f0 3364#ifdef CONFIG_IGB_DCA
8d253320 3365 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3366 igb_update_rx_dca(rx_ring);
3367#endif
3368 return IRQ_HANDLED;
3369}
3370
421e02f0 3371#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3372static void igb_update_rx_dca(struct igb_ring *rx_ring)
3373{
3374 u32 dca_rxctrl;
3375 struct igb_adapter *adapter = rx_ring->adapter;
3376 struct e1000_hw *hw = &adapter->hw;
3377 int cpu = get_cpu();
26bc19ec 3378 int q = rx_ring->reg_idx;
fe4506b6
JC		 3379
3380 if (rx_ring->cpu != cpu) {
3381 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3382 if (hw->mac.type == e1000_82576) {
3383 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3384 dca_rxctrl |= dca_get_tag(cpu) <<
3385 E1000_DCA_RXCTRL_CPUID_SHIFT;
3386 } else {
3387 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3388 dca_rxctrl |= dca_get_tag(cpu);
3389 }
fe4506b6
JC		 3390 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3391 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3392 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3393 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3394 rx_ring->cpu = cpu;
3395 }
3396 put_cpu();
3397}
3398
3399static void igb_update_tx_dca(struct igb_ring *tx_ring)
3400{
3401 u32 dca_txctrl;
3402 struct igb_adapter *adapter = tx_ring->adapter;
3403 struct e1000_hw *hw = &adapter->hw;
3404 int cpu = get_cpu();
26bc19ec 3405 int q = tx_ring->reg_idx;
fe4506b6
JC		 3406
3407 if (tx_ring->cpu != cpu) {
3408 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3409 if (hw->mac.type == e1000_82576) {
3410 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3411 dca_txctrl |= dca_get_tag(cpu) <<
3412 E1000_DCA_TXCTRL_CPUID_SHIFT;
3413 } else {
3414 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3415 dca_txctrl |= dca_get_tag(cpu);
3416 }
fe4506b6
JC		 3417 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3418 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3419 tx_ring->cpu = cpu;
3420 }
3421 put_cpu();
3422}
3423
3424static void igb_setup_dca(struct igb_adapter *adapter)
3425{
3426 int i;
3427
7dfc16fa 3428 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3429 return;
3430
3431 for (i = 0; i < adapter->num_tx_queues; i++) {
3432 adapter->tx_ring[i].cpu = -1;
3433 igb_update_tx_dca(&adapter->tx_ring[i]);
3434 }
3435 for (i = 0; i < adapter->num_rx_queues; i++) {
3436 adapter->rx_ring[i].cpu = -1;
3437 igb_update_rx_dca(&adapter->rx_ring[i]);
3438 }
3439}
3440
3441static int __igb_notify_dca(struct device *dev, void *data)
3442{
3443 struct net_device *netdev = dev_get_drvdata(dev);
3444 struct igb_adapter *adapter = netdev_priv(netdev);
3445 struct e1000_hw *hw = &adapter->hw;
3446 unsigned long event = *(unsigned long *)data;
3447
3448 switch (event) {
3449 case DCA_PROVIDER_ADD:
3450 /* if already enabled, don't do it again */
7dfc16fa 3451 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3452 break;
fe4506b6
JC		 3453 /* Always use CB2 mode, difference is masked
3454 * in the CB driver. */
3455 wr32(E1000_DCA_CTRL, 2);
3456 if (dca_add_requester(dev) == 0) {
bbd98fe4 3457 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3458 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3459 igb_setup_dca(adapter);
3460 break;
3461 }
3462 /* Fall Through since DCA is disabled. */
3463 case DCA_PROVIDER_REMOVE:
7dfc16fa 3464 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3465 /* without this a class_device is left
3466 * hanging around in the sysfs model */
3467 dca_remove_requester(dev);
3468 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3469 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3470 wr32(E1000_DCA_CTRL, 1);
3471 }
3472 break;
3473 }
bbd98fe4 3474
fe4506b6 3475 return 0;
9d5c8243
AK		 3476}
3477
fe4506b6
JC		 3478static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3479 void *p)
3480{
3481 int ret_val;
3482
3483 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3484 __igb_notify_dca);
3485
3486 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3487}
421e02f0 3488#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3489
3490/**
3491 * igb_intr_msi - Interrupt Handler
3492 * @irq: interrupt number
3493 * @data: pointer to a network interface device structure
3494 **/
3495static irqreturn_t igb_intr_msi(int irq, void *data)
3496{
3497 struct net_device *netdev = data;
3498 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3499 struct e1000_hw *hw = &adapter->hw;
3500 /* read ICR disables interrupts using IAM */
3501 u32 icr = rd32(E1000_ICR);
3502
6eb5a7f1 3503 igb_write_itr(adapter->rx_ring);
9d5c8243 3504
dda0e083
AD		 3505 if(icr & E1000_ICR_DOUTSYNC) {
3506 /* HW is reporting DMA is out of sync */
3507 adapter->stats.doosync++;
3508 }
3509
9d5c8243
AK		 3510 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3511 hw->mac.get_link_status = 1;
3512 if (!test_bit(__IGB_DOWN, &adapter->state))
3513 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3514 }
3515
288379f0 3516 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3517
3518 return IRQ_HANDLED;
3519}
3520
3521/**
4a3c6433 3522 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3523 * @irq: interrupt number
3524 * @data: pointer to a network interface device structure
3525 **/
3526static irqreturn_t igb_intr(int irq, void *data)
3527{
3528 struct net_device *netdev = data;
3529 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3530 struct e1000_hw *hw = &adapter->hw;
3531 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3532 * need for the IMC write */
3533 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3534 if (!icr)
3535 return IRQ_NONE; /* Not our interrupt */
3536
6eb5a7f1 3537 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3538
3539 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3540 * not set, then the adapter didn't send an interrupt */
3541 if (!(icr & E1000_ICR_INT_ASSERTED))
3542 return IRQ_NONE;
3543
dda0e083
AD		 3544 if(icr & E1000_ICR_DOUTSYNC) {
3545 /* HW is reporting DMA is out of sync */
3546 adapter->stats.doosync++;
3547 }
3548
9d5c8243
AK		 3549 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3550 hw->mac.get_link_status = 1;
3551 /* guard against interrupt when we're going down */
3552 if (!test_bit(__IGB_DOWN, &adapter->state))
3553 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3554 }
3555
288379f0 3556 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3557
3558 return IRQ_HANDLED;
3559}
3560
3561/**
661086df
PWJ		 3562 * igb_poll - NAPI Rx polling callback
3563 * @napi: napi polling structure
3564 * @budget: count of how many packets we should handle
9d5c8243 3565 **/
661086df 3566static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3567{
661086df
PWJ		 3568 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3569 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3570 struct net_device *netdev = adapter->netdev;
661086df 3571 int tx_clean_complete, work_done = 0;
9d5c8243 3572
661086df 3573 /* this poll routine only supports one tx and one rx queue */
421e02f0 3574#ifdef CONFIG_IGB_DCA
7dfc16fa 3575 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3576 igb_update_tx_dca(&adapter->tx_ring[0]);
3577#endif
661086df 3578 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3579
421e02f0 3580#ifdef CONFIG_IGB_DCA
7dfc16fa 3581 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3582 igb_update_rx_dca(&adapter->rx_ring[0]);
3583#endif
661086df 3584 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3585
3586 /* If no Tx and not enough Rx work done, exit the polling mode */
3587 if ((tx_clean_complete && (work_done < budget)) ||
3588 !netif_running(netdev)) {
9d5c8243 3589 if (adapter->itr_setting & 3)
6eb5a7f1 3590 igb_set_itr(adapter);
288379f0 3591 napi_complete(napi);
9d5c8243
AK		 3592 if (!test_bit(__IGB_DOWN, &adapter->state))
3593 igb_irq_enable(adapter);
3594 return 0;
3595 }
3596
3597 return 1;
3598}
3599
3600static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3601{
3602 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3603 struct igb_adapter *adapter = rx_ring->adapter;
3604 struct e1000_hw *hw = &adapter->hw;
3605 struct net_device *netdev = adapter->netdev;
3606 int work_done = 0;
3607
421e02f0 3608#ifdef CONFIG_IGB_DCA
7dfc16fa 3609 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3610 igb_update_rx_dca(rx_ring);
3611#endif
3b644cf6 3612 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3613
3614
3615 /* If not enough Rx work done, exit the polling mode */
3616 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3617 napi_complete(napi);
9d5c8243 3618
6eb5a7f1
AD		 3619 if (adapter->itr_setting & 3) {
3620 if (adapter->num_rx_queues == 1)
3621 igb_set_itr(adapter);
3622 else
3623 igb_update_ring_itr(rx_ring);
9d5c8243 3624 }
844290e5
PW		 3625
3626 if (!test_bit(__IGB_DOWN, &adapter->state))
3627 wr32(E1000_EIMS, rx_ring->eims_value);
3628
9d5c8243
AK		 3629 return 0;
3630 }
3631
3632 return 1;
3633}
6d8126f9 3634
9d5c8243
AK		 3635/**
3636 * igb_clean_tx_irq - Reclaim resources after transmit completes
3637 * @adapter: board private structure
3638 * returns true if ring is completely cleaned
3639 **/
3b644cf6 3640static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3641{
3b644cf6 3642 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3643 struct net_device *netdev = adapter->netdev;
0e014cb1 3644 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3645 struct igb_buffer *buffer_info;
3646 struct sk_buff *skb;
0e014cb1 3647 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3648 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3649 unsigned int i, eop, count = 0;
3650 bool cleaned = false;
9d5c8243 3651
9d5c8243 3652 i = tx_ring->next_to_clean;
0e014cb1
AD		 3653 eop = tx_ring->buffer_info[i].next_to_watch;
3654 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3655
3656 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3657 (count < tx_ring->count)) {
3658 for (cleaned = false; !cleaned; count++) {
3659 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3660 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3661 cleaned = (i == eop);
9d5c8243
AK		 3662 skb = buffer_info->skb;
3663
3664 if (skb) {
3665 unsigned int segs, bytecount;
3666 /* gso_segs is currently only valid for tcp */
3667 segs = skb_shinfo(skb)->gso_segs ?: 1;
3668 /* multiply data chunks by size of headers */
3669 bytecount = ((segs - 1) * skb_headlen(skb)) +
3670 skb->len;
3671 total_packets += segs;
3672 total_bytes += bytecount;
3673 }
3674
3675 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3676 tx_desc->wb.status = 0;
9d5c8243
AK		 3677
3678 i++;
3679 if (i == tx_ring->count)
3680 i = 0;
9d5c8243 3681 }
0e014cb1
AD		 3682
3683 eop = tx_ring->buffer_info[i].next_to_watch;
3684 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3685 }
3686
9d5c8243
AK		 3687 tx_ring->next_to_clean = i;
3688
fc7d345d 3689 if (unlikely(count &&
9d5c8243
AK		 3690 netif_carrier_ok(netdev) &&
3691 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3692 /* Make sure that anybody stopping the queue after this
3693 * sees the new next_to_clean.
3694 */
3695 smp_mb();
661086df
PWJ		 3696 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3697 !(test_bit(__IGB_DOWN, &adapter->state))) {
3698 netif_wake_subqueue(netdev, tx_ring->queue_index);
3699 ++adapter->restart_queue;
3700 }
9d5c8243
AK		 3701 }
3702
3703 if (tx_ring->detect_tx_hung) {
3704 /* Detect a transmit hang in hardware, this serializes the
3705 * check with the clearing of time_stamp and movement of i */
3706 tx_ring->detect_tx_hung = false;
3707 if (tx_ring->buffer_info[i].time_stamp &&
3708 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3709 (adapter->tx_timeout_factor * HZ))
3710 && !(rd32(E1000_STATUS) &
3711 E1000_STATUS_TXOFF)) {
3712
9d5c8243
AK		 3713 /* detected Tx unit hang */
3714 dev_err(&adapter->pdev->dev,
3715 "Detected Tx Unit Hang\n"
2d064c06 3716 " Tx Queue <%d>\n"
9d5c8243
AK		 3717 " TDH <%x>\n"
3718 " TDT <%x>\n"
3719 " next_to_use <%x>\n"
3720 " next_to_clean <%x>\n"
9d5c8243
AK		 3721 "buffer_info[next_to_clean]\n"
3722 " time_stamp <%lx>\n"
0e014cb1 3723 " next_to_watch <%x>\n"
9d5c8243
AK		 3724 " jiffies <%lx>\n"
3725 " desc.status <%x>\n",
2d064c06 3726 tx_ring->queue_index,
9d5c8243
AK		 3727 readl(adapter->hw.hw_addr + tx_ring->head),
3728 readl(adapter->hw.hw_addr + tx_ring->tail),
3729 tx_ring->next_to_use,
3730 tx_ring->next_to_clean,
9d5c8243 3731 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3732 eop,
9d5c8243 3733 jiffies,
0e014cb1 3734 eop_desc->wb.status);
661086df 3735 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3736 }
3737 }
3738 tx_ring->total_bytes += total_bytes;
3739 tx_ring->total_packets += total_packets;
e21ed353
AD		 3740 tx_ring->tx_stats.bytes += total_bytes;
3741 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3742 adapter->net_stats.tx_bytes += total_bytes;
3743 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3744 return (count < tx_ring->count);
9d5c8243
AK		 3745}
3746
9d5c8243
AK		 3747/**
3748 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3749 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3750 * @status: descriptor status field as written by hardware
3751 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3752 * @skb: pointer to sk_buff to be indicated to stack
3753 **/
d3352520
AD		 3754static void igb_receive_skb(struct igb_ring *ring, u8 status,
3755 union e1000_adv_rx_desc * rx_desc,
3756 struct sk_buff *skb)
3757{
3758 struct igb_adapter * adapter = ring->adapter;
3759 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3760
0c8dfc83 3761 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3762 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3763 if (vlan_extracted)
5c0999b7
HX		 3764 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3765 le16_to_cpu(rx_desc->wb.upper.vlan),
3766 skb);
d3352520 3767 else
5c0999b7 3768 napi_gro_receive(&ring->napi, skb);
d3352520 3769 } else {
d3352520
AD		 3770 if (vlan_extracted)
3771 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3772 le16_to_cpu(rx_desc->wb.upper.vlan));
3773 else
d3352520 3774 netif_receive_skb(skb);
d3352520 3775 }
9d5c8243
AK		 3776}
3777
3778
3779static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3780 u32 status_err, struct sk_buff *skb)
3781{
3782 skb->ip_summed = CHECKSUM_NONE;
3783
3784 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3785 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3786 return;
3787 /* TCP/UDP checksum error bit is set */
3788 if (status_err &
3789 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3790 /* let the stack verify checksum errors */
3791 adapter->hw_csum_err++;
3792 return;
3793 }
3794 /* It must be a TCP or UDP packet with a valid checksum */
3795 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3796 skb->ip_summed = CHECKSUM_UNNECESSARY;
3797
3798 adapter->hw_csum_good++;
3799}
3800
3b644cf6
MW		 3801static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3802 int *work_done, int budget)
9d5c8243 3803{
3b644cf6 3804 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3805 struct net_device *netdev = adapter->netdev;
3806 struct pci_dev *pdev = adapter->pdev;
3807 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3808 struct igb_buffer *buffer_info , *next_buffer;
3809 struct sk_buff *skb;
bf36c1a0 3810 unsigned int i;
9d5c8243
AK		 3811 u32 length, hlen, staterr;
3812 bool cleaned = false;
3813 int cleaned_count = 0;
3814 unsigned int total_bytes = 0, total_packets = 0;
3815
3816 i = rx_ring->next_to_clean;
69d3ca53 3817 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3818 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3819 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3820
3821 while (staterr & E1000_RXD_STAT_DD) {
3822 if (*work_done >= budget)
3823 break;
3824 (*work_done)++;
9d5c8243 3825
69d3ca53
AD		 3826 skb = buffer_info->skb;
3827 prefetch(skb->data - NET_IP_ALIGN);
3828 buffer_info->skb = NULL;
3829
3830 i++;
3831 if (i == rx_ring->count)
3832 i = 0;
3833 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3834 prefetch(next_rxd);
3835 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3836
3837 length = le16_to_cpu(rx_desc->wb.upper.length);
3838 cleaned = true;
3839 cleaned_count++;
3840
bf36c1a0
AD		 3841 if (!adapter->rx_ps_hdr_size) {
3842 pci_unmap_single(pdev, buffer_info->dma,
3843 adapter->rx_buffer_len +
3844 NET_IP_ALIGN,
3845 PCI_DMA_FROMDEVICE);
3846 skb_put(skb, length);
3847 goto send_up;
9d5c8243
AK		 3848 }
3849
69d3ca53
AD		 3850 /* HW will not DMA in data larger than the given buffer, even
3851 * if it parses the (NFS, of course) header to be larger. In
3852 * that case, it fills the header buffer and spills the rest
3853 * into the page.
3854 */
3855 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3856 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3857 if (hlen > adapter->rx_ps_hdr_size)
3858 hlen = adapter->rx_ps_hdr_size;
3859
bf36c1a0
AD		 3860 if (!skb_shinfo(skb)->nr_frags) {
3861 pci_unmap_single(pdev, buffer_info->dma,
3862 adapter->rx_ps_hdr_size +
3863 NET_IP_ALIGN,
3864 PCI_DMA_FROMDEVICE);
3865 skb_put(skb, hlen);
3866 }
3867
3868 if (length) {
9d5c8243 3869 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3870 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3871 buffer_info->page_dma = 0;
bf36c1a0
AD		 3872
3873 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3874 buffer_info->page,
3875 buffer_info->page_offset,
3876 length);
3877
3878 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3879 (page_count(buffer_info->page) != 1))
3880 buffer_info->page = NULL;
3881 else
3882 get_page(buffer_info->page);
9d5c8243
AK		 3883
3884 skb->len += length;
3885 skb->data_len += length;
9d5c8243 3886
bf36c1a0 3887 skb->truesize += length;
9d5c8243 3888 }
9d5c8243 3889
bf36c1a0 3890 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3891 buffer_info->skb = next_buffer->skb;
3892 buffer_info->dma = next_buffer->dma;
3893 next_buffer->skb = skb;
3894 next_buffer->dma = 0;
bf36c1a0
AD		 3895 goto next_desc;
3896 }
69d3ca53 3897send_up:
9d5c8243
AK		 3898 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3899 dev_kfree_skb_irq(skb);
3900 goto next_desc;
3901 }
9d5c8243
AK		 3902
3903 total_bytes += skb->len;
3904 total_packets++;
3905
3906 igb_rx_checksum_adv(adapter, staterr, skb);
3907
3908 skb->protocol = eth_type_trans(skb, netdev);
3909
d3352520 3910 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3911
9d5c8243
AK		 3912next_desc:
3913 rx_desc->wb.upper.status_error = 0;
3914
3915 /* return some buffers to hardware, one at a time is too slow */
3916 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3917 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3918 cleaned_count = 0;
3919 }
3920
3921 /* use prefetched values */
3922 rx_desc = next_rxd;
3923 buffer_info = next_buffer;
9d5c8243
AK		 3924 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3925 }
bf36c1a0 3926
9d5c8243
AK		 3927 rx_ring->next_to_clean = i;
3928 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3929
3930 if (cleaned_count)
3b644cf6 3931 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3932
3933 rx_ring->total_packets += total_packets;
3934 rx_ring->total_bytes += total_bytes;
3935 rx_ring->rx_stats.packets += total_packets;
3936 rx_ring->rx_stats.bytes += total_bytes;
3937 adapter->net_stats.rx_bytes += total_bytes;
3938 adapter->net_stats.rx_packets += total_packets;
3939 return cleaned;
3940}
3941
3942
3943/**
3944 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3945 * @adapter: address of board private structure
3946 **/
3b644cf6 3947static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3948 int cleaned_count)
3949{
3b644cf6 3950 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3951 struct net_device *netdev = adapter->netdev;
3952 struct pci_dev *pdev = adapter->pdev;
3953 union e1000_adv_rx_desc *rx_desc;
3954 struct igb_buffer *buffer_info;
3955 struct sk_buff *skb;
3956 unsigned int i;
db761762 3957 int bufsz;
9d5c8243
AK		 3958
3959 i = rx_ring->next_to_use;
3960 buffer_info = &rx_ring->buffer_info[i];
3961
db761762
AD		 3962 if (adapter->rx_ps_hdr_size)
3963 bufsz = adapter->rx_ps_hdr_size;
3964 else
3965 bufsz = adapter->rx_buffer_len;
3966 bufsz += NET_IP_ALIGN;
3967
9d5c8243
AK		 3968 while (cleaned_count--) {
3969 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3970
bf36c1a0 3971 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3972 if (!buffer_info->page) {
bf36c1a0
AD		 3973 buffer_info->page = alloc_page(GFP_ATOMIC);
3974 if (!buffer_info->page) {
3975 adapter->alloc_rx_buff_failed++;
3976 goto no_buffers;
3977 }
3978 buffer_info->page_offset = 0;
3979 } else {
3980 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3981 }
3982 buffer_info->page_dma =
db761762 3983 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 3984 buffer_info->page_offset,
3985 PAGE_SIZE / 2,
9d5c8243
AK		 3986 PCI_DMA_FROMDEVICE);
3987 }
3988
3989 if (!buffer_info->skb) {
9d5c8243 3990 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 3991 if (!skb) {
3992 adapter->alloc_rx_buff_failed++;
3993 goto no_buffers;
3994 }
3995
3996 /* Make buffer alignment 2 beyond a 16 byte boundary
3997 * this will result in a 16 byte aligned IP header after
3998 * the 14 byte MAC header is removed
3999 */
4000 skb_reserve(skb, NET_IP_ALIGN);
4001
4002 buffer_info->skb = skb;
4003 buffer_info->dma = pci_map_single(pdev, skb->data,
4004 bufsz,
4005 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4006 }
4007 /* Refresh the desc even if buffer_addrs didn't change because
4008 * each write-back erases this info. */
4009 if (adapter->rx_ps_hdr_size) {
4010 rx_desc->read.pkt_addr =
4011 cpu_to_le64(buffer_info->page_dma);
4012 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4013 } else {
4014 rx_desc->read.pkt_addr =
4015 cpu_to_le64(buffer_info->dma);
4016 rx_desc->read.hdr_addr = 0;
4017 }
4018
4019 i++;
4020 if (i == rx_ring->count)
4021 i = 0;
4022 buffer_info = &rx_ring->buffer_info[i];
4023 }
4024
4025no_buffers:
4026 if (rx_ring->next_to_use != i) {
4027 rx_ring->next_to_use = i;
4028 if (i == 0)
4029 i = (rx_ring->count - 1);
4030 else
4031 i--;
4032
4033 /* Force memory writes to complete before letting h/w
4034 * know there are new descriptors to fetch. (Only
4035 * applicable for weak-ordered memory model archs,
4036 * such as IA-64). */
4037 wmb();
4038 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4039 }
4040}
4041
4042/**
4043 * igb_mii_ioctl -
4044 * @netdev:
4045 * @ifreq:
4046 * @cmd:
4047 **/
4048static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4049{
4050 struct igb_adapter *adapter = netdev_priv(netdev);
4051 struct mii_ioctl_data *data = if_mii(ifr);
4052
4053 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4054 return -EOPNOTSUPP;
4055
4056 switch (cmd) {
4057 case SIOCGMIIPHY:
4058 data->phy_id = adapter->hw.phy.addr;
4059 break;
4060 case SIOCGMIIREG:
4061 if (!capable(CAP_NET_ADMIN))
4062 return -EPERM;
f5f4cf08
AD		 4063 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4064 &data->val_out))
9d5c8243
AK		 4065 return -EIO;
4066 break;
4067 case SIOCSMIIREG:
4068 default:
4069 return -EOPNOTSUPP;
4070 }
4071 return 0;
4072}
4073
4074/**
4075 * igb_ioctl -
4076 * @netdev:
4077 * @ifreq:
4078 * @cmd:
4079 **/
4080static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4081{
4082 switch (cmd) {
4083 case SIOCGMIIPHY:
4084 case SIOCGMIIREG:
4085 case SIOCSMIIREG:
4086 return igb_mii_ioctl(netdev, ifr, cmd);
4087 default:
4088 return -EOPNOTSUPP;
4089 }
4090}
4091
4092static void igb_vlan_rx_register(struct net_device *netdev,
4093 struct vlan_group *grp)
4094{
4095 struct igb_adapter *adapter = netdev_priv(netdev);
4096 struct e1000_hw *hw = &adapter->hw;
4097 u32 ctrl, rctl;
4098
4099 igb_irq_disable(adapter);
4100 adapter->vlgrp = grp;
4101
4102 if (grp) {
4103 /* enable VLAN tag insert/strip */
4104 ctrl = rd32(E1000_CTRL);
4105 ctrl |= E1000_CTRL_VME;
4106 wr32(E1000_CTRL, ctrl);
4107
4108 /* enable VLAN receive filtering */
4109 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4110 rctl &= ~E1000_RCTL_CFIEN;
4111 wr32(E1000_RCTL, rctl);
4112 igb_update_mng_vlan(adapter);
4113 wr32(E1000_RLPML,
4114 adapter->max_frame_size + VLAN_TAG_SIZE);
4115 } else {
4116 /* disable VLAN tag insert/strip */
4117 ctrl = rd32(E1000_CTRL);
4118 ctrl &= ~E1000_CTRL_VME;
4119 wr32(E1000_CTRL, ctrl);
4120
9d5c8243
AK		 4121 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4122 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4123 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4124 }
4125 wr32(E1000_RLPML,
4126 adapter->max_frame_size);
4127 }
4128
4129 if (!test_bit(__IGB_DOWN, &adapter->state))
4130 igb_irq_enable(adapter);
4131}
4132
4133static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4134{
4135 struct igb_adapter *adapter = netdev_priv(netdev);
4136 struct e1000_hw *hw = &adapter->hw;
4137 u32 vfta, index;
4138
28b0759c 4139 if ((hw->mng_cookie.status &
9d5c8243
AK		 4140 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4141 (vid == adapter->mng_vlan_id))
4142 return;
4143 /* add VID to filter table */
4144 index = (vid >> 5) & 0x7F;
4145 vfta = array_rd32(E1000_VFTA, index);
4146 vfta |= (1 << (vid & 0x1F));
4147 igb_write_vfta(&adapter->hw, index, vfta);
4148}
4149
4150static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4151{
4152 struct igb_adapter *adapter = netdev_priv(netdev);
4153 struct e1000_hw *hw = &adapter->hw;
4154 u32 vfta, index;
4155
4156 igb_irq_disable(adapter);
4157 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4158
4159 if (!test_bit(__IGB_DOWN, &adapter->state))
4160 igb_irq_enable(adapter);
4161
4162 if ((adapter->hw.mng_cookie.status &
4163 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4164 (vid == adapter->mng_vlan_id)) {
4165 /* release control to f/w */
4166 igb_release_hw_control(adapter);
4167 return;
4168 }
4169
4170 /* remove VID from filter table */
4171 index = (vid >> 5) & 0x7F;
4172 vfta = array_rd32(E1000_VFTA, index);
4173 vfta &= ~(1 << (vid & 0x1F));
4174 igb_write_vfta(&adapter->hw, index, vfta);
4175}
4176
4177static void igb_restore_vlan(struct igb_adapter *adapter)
4178{
4179 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4180
4181 if (adapter->vlgrp) {
4182 u16 vid;
4183 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4184 if (!vlan_group_get_device(adapter->vlgrp, vid))
4185 continue;
4186 igb_vlan_rx_add_vid(adapter->netdev, vid);
4187 }
4188 }
4189}
4190
4191int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4192{
4193 struct e1000_mac_info *mac = &adapter->hw.mac;
4194
4195 mac->autoneg = 0;
4196
4197 /* Fiber NICs only allow 1000 gbps Full duplex */
4198 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4199 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4200 dev_err(&adapter->pdev->dev,
4201 "Unsupported Speed/Duplex configuration\n");
4202 return -EINVAL;
4203 }
4204
4205 switch (spddplx) {
4206 case SPEED_10 + DUPLEX_HALF:
4207 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4208 break;
4209 case SPEED_10 + DUPLEX_FULL:
4210 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4211 break;
4212 case SPEED_100 + DUPLEX_HALF:
4213 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4214 break;
4215 case SPEED_100 + DUPLEX_FULL:
4216 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4217 break;
4218 case SPEED_1000 + DUPLEX_FULL:
4219 mac->autoneg = 1;
4220 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4221 break;
4222 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4223 default:
4224 dev_err(&adapter->pdev->dev,
4225 "Unsupported Speed/Duplex configuration\n");
4226 return -EINVAL;
4227 }
4228 return 0;
4229}
4230
4231
4232static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4233{
4234 struct net_device *netdev = pci_get_drvdata(pdev);
4235 struct igb_adapter *adapter = netdev_priv(netdev);
4236 struct e1000_hw *hw = &adapter->hw;
2d064c06 4237 u32 ctrl, rctl, status;
9d5c8243
AK		 4238 u32 wufc = adapter->wol;
4239#ifdef CONFIG_PM
4240 int retval = 0;
4241#endif
4242
4243 netif_device_detach(netdev);
4244
a88f10ec
AD		 4245 if (netif_running(netdev))
4246 igb_close(netdev);
4247
4248 igb_reset_interrupt_capability(adapter);
4249
4250 igb_free_queues(adapter);
9d5c8243
AK		 4251
4252#ifdef CONFIG_PM
4253 retval = pci_save_state(pdev);
4254 if (retval)
4255 return retval;
4256#endif
4257
4258 status = rd32(E1000_STATUS);
4259 if (status & E1000_STATUS_LU)
4260 wufc &= ~E1000_WUFC_LNKC;
4261
4262 if (wufc) {
4263 igb_setup_rctl(adapter);
4264 igb_set_multi(netdev);
4265
4266 /* turn on all-multi mode if wake on multicast is enabled */
4267 if (wufc & E1000_WUFC_MC) {
4268 rctl = rd32(E1000_RCTL);
4269 rctl |= E1000_RCTL_MPE;
4270 wr32(E1000_RCTL, rctl);
4271 }
4272
4273 ctrl = rd32(E1000_CTRL);
4274 /* advertise wake from D3Cold */
4275 #define E1000_CTRL_ADVD3WUC 0x00100000
4276 /* phy power management enable */
4277 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4278 ctrl |= E1000_CTRL_ADVD3WUC;
4279 wr32(E1000_CTRL, ctrl);
4280
9d5c8243
AK		 4281 /* Allow time for pending master requests to run */
4282 igb_disable_pcie_master(&adapter->hw);
4283
4284 wr32(E1000_WUC, E1000_WUC_PME_EN);
4285 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4286 } else {
4287 wr32(E1000_WUC, 0);
4288 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4289 }
4290
2d064c06
AD		 4291 /* make sure adapter isn't asleep if manageability/wol is enabled */
4292 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4293 pci_enable_wake(pdev, PCI_D3hot, 1);
4294 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4295 } else {
4296 igb_shutdown_fiber_serdes_link_82575(hw);
4297 pci_enable_wake(pdev, PCI_D3hot, 0);
4298 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4299 }
4300
4301 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4302 * would have already happened in close and is redundant. */
4303 igb_release_hw_control(adapter);
4304
4305 pci_disable_device(pdev);
4306
4307 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4308
4309 return 0;
4310}
4311
4312#ifdef CONFIG_PM
4313static int igb_resume(struct pci_dev *pdev)
4314{
4315 struct net_device *netdev = pci_get_drvdata(pdev);
4316 struct igb_adapter *adapter = netdev_priv(netdev);
4317 struct e1000_hw *hw = &adapter->hw;
4318 u32 err;
4319
4320 pci_set_power_state(pdev, PCI_D0);
4321 pci_restore_state(pdev);
42bfd33a 4322
aed5dec3 4323 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4324 if (err) {
4325 dev_err(&pdev->dev,
4326 "igb: Cannot enable PCI device from suspend\n");
4327 return err;
4328 }
4329 pci_set_master(pdev);
4330
4331 pci_enable_wake(pdev, PCI_D3hot, 0);
4332 pci_enable_wake(pdev, PCI_D3cold, 0);
4333
a88f10ec
AD		 4334 igb_set_interrupt_capability(adapter);
4335
4336 if (igb_alloc_queues(adapter)) {
4337 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4338 return -ENOMEM;
9d5c8243
AK		 4339 }
4340
4341 /* e1000_power_up_phy(adapter); */
4342
4343 igb_reset(adapter);
a8564f03
AD		 4344
4345 /* let the f/w know that the h/w is now under the control of the
4346 * driver. */
4347 igb_get_hw_control(adapter);
4348
9d5c8243
AK		 4349 wr32(E1000_WUS, ~0);
4350
a88f10ec
AD		 4351 if (netif_running(netdev)) {
4352 err = igb_open(netdev);
4353 if (err)
4354 return err;
4355 }
9d5c8243
AK		 4356
4357 netif_device_attach(netdev);
4358
9d5c8243
AK		 4359 return 0;
4360}
4361#endif
4362
4363static void igb_shutdown(struct pci_dev *pdev)
4364{
4365 igb_suspend(pdev, PMSG_SUSPEND);
4366}
4367
4368#ifdef CONFIG_NET_POLL_CONTROLLER
4369/*
4370 * Polling 'interrupt' - used by things like netconsole to send skbs
4371 * without having to re-enable interrupts. It's not called while
4372 * the interrupt routine is executing.
4373 */
4374static void igb_netpoll(struct net_device *netdev)
4375{
4376 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4377 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4378 int i;
9d5c8243 4379
eebbbdba
AD		 4380 if (!adapter->msix_entries) {
4381 igb_irq_disable(adapter);
4382 napi_schedule(&adapter->rx_ring[0].napi);
4383 return;
4384 }
9d5c8243 4385
eebbbdba
AD		 4386 for (i = 0; i < adapter->num_tx_queues; i++) {
4387 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4388 wr32(E1000_EIMC, tx_ring->eims_value);
4389 igb_clean_tx_irq(tx_ring);
4390 wr32(E1000_EIMS, tx_ring->eims_value);
4391 }
9d5c8243 4392
eebbbdba
AD		 4393 for (i = 0; i < adapter->num_rx_queues; i++) {
4394 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4395 wr32(E1000_EIMC, rx_ring->eims_value);
4396 napi_schedule(&rx_ring->napi);
4397 }
9d5c8243
AK		 4398}
4399#endif /* CONFIG_NET_POLL_CONTROLLER */
4400
4401/**
4402 * igb_io_error_detected - called when PCI error is detected
4403 * @pdev: Pointer to PCI device
4404 * @state: The current pci connection state
4405 *
4406 * This function is called after a PCI bus error affecting
4407 * this device has been detected.
4408 */
4409static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4410 pci_channel_state_t state)
4411{
4412 struct net_device *netdev = pci_get_drvdata(pdev);
4413 struct igb_adapter *adapter = netdev_priv(netdev);
4414
4415 netif_device_detach(netdev);
4416
4417 if (netif_running(netdev))
4418 igb_down(adapter);
4419 pci_disable_device(pdev);
4420
4421 /* Request a slot slot reset. */
4422 return PCI_ERS_RESULT_NEED_RESET;
4423}
4424
4425/**
4426 * igb_io_slot_reset - called after the pci bus has been reset.
4427 * @pdev: Pointer to PCI device
4428 *
4429 * Restart the card from scratch, as if from a cold-boot. Implementation
4430 * resembles the first-half of the igb_resume routine.
4431 */
4432static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4433{
4434 struct net_device *netdev = pci_get_drvdata(pdev);
4435 struct igb_adapter *adapter = netdev_priv(netdev);
4436 struct e1000_hw *hw = &adapter->hw;
40a914fa 4437 pci_ers_result_t result;
42bfd33a 4438 int err;
9d5c8243 4439
aed5dec3 4440 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4441 dev_err(&pdev->dev,
4442 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4443 result = PCI_ERS_RESULT_DISCONNECT;
4444 } else {
4445 pci_set_master(pdev);
4446 pci_restore_state(pdev);
9d5c8243 4447
40a914fa
AD		 4448 pci_enable_wake(pdev, PCI_D3hot, 0);
4449 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4450
40a914fa
AD		 4451 igb_reset(adapter);
4452 wr32(E1000_WUS, ~0);
4453 result = PCI_ERS_RESULT_RECOVERED;
4454 }
9d5c8243 4455
ea943d41
JK		 4456 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4457 if (err) {
4458 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4459 "failed 0x%0x\n", err);
4460 /* non-fatal, continue */
4461 }
40a914fa
AD		 4462
4463 return result;
9d5c8243
AK		 4464}
4465
4466/**
4467 * igb_io_resume - called when traffic can start flowing again.
4468 * @pdev: Pointer to PCI device
4469 *
4470 * This callback is called when the error recovery driver tells us that
4471 * its OK to resume normal operation. Implementation resembles the
4472 * second-half of the igb_resume routine.
4473 */
4474static void igb_io_resume(struct pci_dev *pdev)
4475{
4476 struct net_device *netdev = pci_get_drvdata(pdev);
4477 struct igb_adapter *adapter = netdev_priv(netdev);
4478
9d5c8243
AK		 4479 if (netif_running(netdev)) {
4480 if (igb_up(adapter)) {
4481 dev_err(&pdev->dev, "igb_up failed after reset\n");
4482 return;
4483 }
4484 }
4485
4486 netif_device_attach(netdev);
4487
4488 /* let the f/w know that the h/w is now under the control of the
4489 * driver. */
4490 igb_get_hw_control(adapter);
9d5c8243
AK		 4491}
4492
4493/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)