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igb: add a flags value to the ring
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 85void igb_update_stats(struct igb_adapter *);
86static int igb_probe(struct pci_dev *, const struct pci_device_id *);
87static void __devexit igb_remove(struct pci_dev *pdev);
88static int igb_sw_init(struct igb_adapter *);
89static int igb_open(struct net_device *);
90static int igb_close(struct net_device *);
91static void igb_configure_tx(struct igb_adapter *);
92static void igb_configure_rx(struct igb_adapter *);
85b430b4 93static void igb_setup_tctl(struct igb_adapter *);
9d5c8243
AK		 94static void igb_setup_rctl(struct igb_adapter *);
95static void igb_clean_all_tx_rings(struct igb_adapter *);
96static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 97static void igb_clean_tx_ring(struct igb_ring *);
98static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 99static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 100static void igb_update_phy_info(unsigned long);
101static void igb_watchdog(unsigned long);
102static void igb_watchdog_task(struct work_struct *);
3b29a56d
SH		 103static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
104 struct net_device *,
105 struct igb_ring *);
106static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
107 struct net_device *);
9d5c8243
AK		 108static struct net_device_stats *igb_get_stats(struct net_device *);
109static int igb_change_mtu(struct net_device *, int);
110static int igb_set_mac(struct net_device *, void *);
68d480c4 111static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 112static irqreturn_t igb_intr(int irq, void *);
113static irqreturn_t igb_intr_msi(int irq, void *);
114static irqreturn_t igb_msix_other(int irq, void *);
047e0030 115static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 116#ifdef CONFIG_IGB_DCA
047e0030 117static void igb_update_dca(struct igb_q_vector *);
fe4506b6 118static void igb_setup_dca(struct igb_adapter *);
421e02f0 119#endif /* CONFIG_IGB_DCA */
047e0030 120static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 121static int igb_poll(struct napi_struct *, int);
047e0030 122static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
3b644cf6 123static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 124static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
125static void igb_tx_timeout(struct net_device *);
126static void igb_reset_task(struct work_struct *);
127static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
128static void igb_vlan_rx_add_vid(struct net_device *, u16);
129static void igb_vlan_rx_kill_vid(struct net_device *, u16);
130static void igb_restore_vlan(struct igb_adapter *);
26ad9178 131static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 132static void igb_ping_all_vfs(struct igb_adapter *);
133static void igb_msg_task(struct igb_adapter *);
134static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
4ae196df 135static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 136static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
137static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 138
c8159b2d
ED		 139static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
140{
141 u32 reg_data;
142
143 reg_data = rd32(E1000_VMOLR(vfn));
144 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
c8159b2d
ED		 145 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
146 E1000_VMOLR_AUPE | /* Accept untagged packets */
147 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
148 wr32(E1000_VMOLR(vfn), reg_data);
149}
150
151static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
152 int vfn)
153{
154 struct e1000_hw *hw = &adapter->hw;
155 u32 vmolr;
156
ae641bdc
AD		 157 /* if it isn't the PF check to see if VFs are enabled and
158 * increase the size to support vlan tags */
159 if (vfn < adapter->vfs_allocated_count &&
160 adapter->vf_data[vfn].vlans_enabled)
161 size += VLAN_TAG_SIZE;
162
c8159b2d
ED		 163 vmolr = rd32(E1000_VMOLR(vfn));
164 vmolr &= ~E1000_VMOLR_RLPML_MASK;
165 vmolr |= size | E1000_VMOLR_LPE;
166 wr32(E1000_VMOLR(vfn), vmolr);
167
168 return 0;
169}
170
9d5c8243 171#ifdef CONFIG_PM
3fe7c4c9 172static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 173static int igb_resume(struct pci_dev *);
174#endif
175static void igb_shutdown(struct pci_dev *);
421e02f0 176#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 177static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
178static struct notifier_block dca_notifier = {
179 .notifier_call = igb_notify_dca,
180 .next = NULL,
181 .priority = 0
182};
183#endif
9d5c8243
AK		 184#ifdef CONFIG_NET_POLL_CONTROLLER
185/* for netdump / net console */
186static void igb_netpoll(struct net_device *);
187#endif
37680117 188#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 189static unsigned int max_vfs = 0;
190module_param(max_vfs, uint, 0);
191MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
192 "per physical function");
193#endif /* CONFIG_PCI_IOV */
194
9d5c8243
AK		 195static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
196 pci_channel_state_t);
197static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
198static void igb_io_resume(struct pci_dev *);
199
200static struct pci_error_handlers igb_err_handler = {
201 .error_detected = igb_io_error_detected,
202 .slot_reset = igb_io_slot_reset,
203 .resume = igb_io_resume,
204};
205
206
207static struct pci_driver igb_driver = {
208 .name = igb_driver_name,
209 .id_table = igb_pci_tbl,
210 .probe = igb_probe,
211 .remove = __devexit_p(igb_remove),
212#ifdef CONFIG_PM
213 /* Power Managment Hooks */
214 .suspend = igb_suspend,
215 .resume = igb_resume,
216#endif
217 .shutdown = igb_shutdown,
218 .err_handler = &igb_err_handler
219};
220
7dfc16fa
AD		 221static int global_quad_port_a; /* global quad port a indication */
222
9d5c8243
AK		 223MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
224MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
225MODULE_LICENSE("GPL");
226MODULE_VERSION(DRV_VERSION);
227
38c845c7
PO		 228/**
229 * Scale the NIC clock cycle by a large factor so that
230 * relatively small clock corrections can be added or
231 * substracted at each clock tick. The drawbacks of a
232 * large factor are a) that the clock register overflows
233 * more quickly (not such a big deal) and b) that the
234 * increment per tick has to fit into 24 bits.
235 *
236 * Note that
237 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
238 * IGB_TSYNC_SCALE
239 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
240 *
241 * The base scale factor is intentionally a power of two
242 * so that the division in %struct timecounter can be done with
243 * a shift.
244 */
245#define IGB_TSYNC_SHIFT (19)
246#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
247
248/**
249 * The duration of one clock cycle of the NIC.
250 *
251 * @todo This hard-coded value is part of the specification and might change
252 * in future hardware revisions. Add revision check.
253 */
254#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
255
256#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
257# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
258#endif
259
260/**
261 * igb_read_clock - read raw cycle counter (to be used by time counter)
262 */
263static cycle_t igb_read_clock(const struct cyclecounter *tc)
264{
265 struct igb_adapter *adapter =
266 container_of(tc, struct igb_adapter, cycles);
267 struct e1000_hw *hw = &adapter->hw;
268 u64 stamp;
269
270 stamp = rd32(E1000_SYSTIML);
271 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
272
273 return stamp;
274}
275
9d5c8243
AK		 276#ifdef DEBUG
277/**
278 * igb_get_hw_dev_name - return device name string
279 * used by hardware layer to print debugging information
280 **/
281char *igb_get_hw_dev_name(struct e1000_hw *hw)
282{
283 struct igb_adapter *adapter = hw->back;
284 return adapter->netdev->name;
285}
38c845c7
PO		 286
287/**
288 * igb_get_time_str - format current NIC and system time as string
289 */
290static char *igb_get_time_str(struct igb_adapter *adapter,
291 char buffer[160])
292{
293 cycle_t hw = adapter->cycles.read(&adapter->cycles);
294 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
295 struct timespec sys;
296 struct timespec delta;
297 getnstimeofday(&sys);
298
299 delta = timespec_sub(nic, sys);
300
301 sprintf(buffer,
33af6bcc
PO		 302 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
303 hw,
38c845c7
PO		 304 (long)nic.tv_sec, nic.tv_nsec,
305 (long)sys.tv_sec, sys.tv_nsec,
306 (long)delta.tv_sec, delta.tv_nsec);
307
308 return buffer;
309}
9d5c8243
AK		 310#endif
311
c493ea45
AD		 312/**
313 * igb_desc_unused - calculate if we have unused descriptors
314 **/
315static int igb_desc_unused(struct igb_ring *ring)
316{
317 if (ring->next_to_clean > ring->next_to_use)
318 return ring->next_to_clean - ring->next_to_use - 1;
319
320 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
321}
322
9d5c8243
AK		 323/**
324 * igb_init_module - Driver Registration Routine
325 *
326 * igb_init_module is the first routine called when the driver is
327 * loaded. All it does is register with the PCI subsystem.
328 **/
329static int __init igb_init_module(void)
330{
331 int ret;
332 printk(KERN_INFO "%s - version %s\n",
333 igb_driver_string, igb_driver_version);
334
335 printk(KERN_INFO "%s\n", igb_copyright);
336
7dfc16fa
AD		 337 global_quad_port_a = 0;
338
421e02f0 339#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 340 dca_register_notify(&dca_notifier);
341#endif
bbd98fe4
AD		 342
343 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 344 return ret;
345}
346
347module_init(igb_init_module);
348
349/**
350 * igb_exit_module - Driver Exit Cleanup Routine
351 *
352 * igb_exit_module is called just before the driver is removed
353 * from memory.
354 **/
355static void __exit igb_exit_module(void)
356{
421e02f0 357#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 358 dca_unregister_notify(&dca_notifier);
359#endif
9d5c8243
AK		 360 pci_unregister_driver(&igb_driver);
361}
362
363module_exit(igb_exit_module);
364
26bc19ec
AD		 365#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
366/**
367 * igb_cache_ring_register - Descriptor ring to register mapping
368 * @adapter: board private structure to initialize
369 *
370 * Once we know the feature-set enabled for the device, we'll cache
371 * the register offset the descriptor ring is assigned to.
372 **/
373static void igb_cache_ring_register(struct igb_adapter *adapter)
374{
375 int i;
047e0030 376 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 377
378 switch (adapter->hw.mac.type) {
379 case e1000_82576:
380 /* The queues are allocated for virtualization such that VF 0
381 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
382 * In order to avoid collision we start at the first free queue
383 * and continue consuming queues in the same sequence
384 */
385 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 386 adapter->rx_ring[i].reg_idx = rbase_offset +
387 Q_IDX_82576(i);
26bc19ec 388 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 389 adapter->tx_ring[i].reg_idx = rbase_offset +
390 Q_IDX_82576(i);
26bc19ec
AD		 391 break;
392 case e1000_82575:
393 default:
394 for (i = 0; i < adapter->num_rx_queues; i++)
395 adapter->rx_ring[i].reg_idx = i;
396 for (i = 0; i < adapter->num_tx_queues; i++)
397 adapter->tx_ring[i].reg_idx = i;
398 break;
399 }
400}
401
047e0030
AD		 402static void igb_free_queues(struct igb_adapter *adapter)
403{
404 kfree(adapter->tx_ring);
405 kfree(adapter->rx_ring);
406
407 adapter->tx_ring = NULL;
408 adapter->rx_ring = NULL;
409
410 adapter->num_rx_queues = 0;
411 adapter->num_tx_queues = 0;
412}
413
9d5c8243
AK		 414/**
415 * igb_alloc_queues - Allocate memory for all rings
416 * @adapter: board private structure to initialize
417 *
418 * We allocate one ring per queue at run-time since we don't know the
419 * number of queues at compile-time.
420 **/
421static int igb_alloc_queues(struct igb_adapter *adapter)
422{
423 int i;
424
425 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
426 sizeof(struct igb_ring), GFP_KERNEL);
427 if (!adapter->tx_ring)
047e0030 428 goto err;
9d5c8243
AK		 429
430 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
431 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 432 if (!adapter->rx_ring)
433 goto err;
6eb5a7f1 434
661086df
PWJ		 435 for (i = 0; i < adapter->num_tx_queues; i++) {
436 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 437 ring->count = adapter->tx_ring_count;
661086df 438 ring->queue_index = i;
80785298 439 ring->pdev = adapter->pdev;
85ad76b2
AD		 440 /* For 82575, context index must be unique per ring. */
441 if (adapter->hw.mac.type == e1000_82575)
442 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
661086df 443 }
85ad76b2 444
9d5c8243
AK		 445 for (i = 0; i < adapter->num_rx_queues; i++) {
446 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 447 ring->count = adapter->rx_ring_count;
844290e5 448 ring->queue_index = i;
80785298 449 ring->pdev = adapter->pdev;
4c844851 450 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 451 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
452 /* set flag indicating ring supports SCTP checksum offload */
453 if (adapter->hw.mac.type >= e1000_82576)
454 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
9d5c8243 455 }
26bc19ec
AD		 456
457 igb_cache_ring_register(adapter);
9d5c8243 458
047e0030 459 return 0;
a88f10ec 460
047e0030
AD		 461err:
462 igb_free_queues(adapter);
d1a8c9e1 463
047e0030 464 return -ENOMEM;
a88f10ec
AD		 465}
466
9d5c8243 467#define IGB_N0_QUEUE -1
047e0030 468static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 469{
470 u32 msixbm = 0;
047e0030 471 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 472 struct e1000_hw *hw = &adapter->hw;
2d064c06 473 u32 ivar, index;
047e0030
AD		 474 int rx_queue = IGB_N0_QUEUE;
475 int tx_queue = IGB_N0_QUEUE;
476
477 if (q_vector->rx_ring)
478 rx_queue = q_vector->rx_ring->reg_idx;
479 if (q_vector->tx_ring)
480 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 481
482 switch (hw->mac.type) {
483 case e1000_82575:
9d5c8243
AK		 484 /* The 82575 assigns vectors using a bitmask, which matches the
485 bitmask for the EICR/EIMS/EIMC registers. To assign one
486 or more queues to a vector, we write the appropriate bits
487 into the MSIXBM register for that vector. */
047e0030 488 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 489 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 490 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 491 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 492 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 493 q_vector->eims_value = msixbm;
2d064c06
AD		 494 break;
495 case e1000_82576:
26bc19ec 496 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 497 Each queue has a single entry in the table to which we write
498 a vector number along with a "valid" bit. Sadly, the layout
499 of the table is somewhat counterintuitive. */
500 if (rx_queue > IGB_N0_QUEUE) {
047e0030 501 index = (rx_queue & 0x7);
2d064c06 502 ivar = array_rd32(E1000_IVAR0, index);
047e0030 503 if (rx_queue < 8) {
26bc19ec
AD		 504 /* vector goes into low byte of register */
505 ivar = ivar & 0xFFFFFF00;
506 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 507 } else {
508 /* vector goes into third byte of register */
509 ivar = ivar & 0xFF00FFFF;
510 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 511 }
2d064c06
AD		 512 array_wr32(E1000_IVAR0, index, ivar);
513 }
514 if (tx_queue > IGB_N0_QUEUE) {
047e0030 515 index = (tx_queue & 0x7);
2d064c06 516 ivar = array_rd32(E1000_IVAR0, index);
047e0030 517 if (tx_queue < 8) {
26bc19ec
AD		 518 /* vector goes into second byte of register */
519 ivar = ivar & 0xFFFF00FF;
520 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 521 } else {
522 /* vector goes into high byte of register */
523 ivar = ivar & 0x00FFFFFF;
524 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 525 }
2d064c06
AD		 526 array_wr32(E1000_IVAR0, index, ivar);
527 }
047e0030 528 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 529 break;
530 default:
531 BUG();
532 break;
533 }
9d5c8243
AK		 534}
535
536/**
537 * igb_configure_msix - Configure MSI-X hardware
538 *
539 * igb_configure_msix sets up the hardware to properly
540 * generate MSI-X interrupts.
541 **/
542static void igb_configure_msix(struct igb_adapter *adapter)
543{
544 u32 tmp;
545 int i, vector = 0;
546 struct e1000_hw *hw = &adapter->hw;
547
548 adapter->eims_enable_mask = 0;
9d5c8243
AK		 549
550 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 551 switch (hw->mac.type) {
552 case e1000_82575:
9d5c8243
AK		 553 tmp = rd32(E1000_CTRL_EXT);
554 /* enable MSI-X PBA support*/
555 tmp |= E1000_CTRL_EXT_PBA_CLR;
556
557 /* Auto-Mask interrupts upon ICR read. */
558 tmp |= E1000_CTRL_EXT_EIAME;
559 tmp |= E1000_CTRL_EXT_IRCA;
560
561 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 562
563 /* enable msix_other interrupt */
564 array_wr32(E1000_MSIXBM(0), vector++,
565 E1000_EIMS_OTHER);
844290e5 566 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 567
2d064c06
AD		 568 break;
569
570 case e1000_82576:
047e0030
AD		 571 /* Turn on MSI-X capability first, or our settings
572 * won't stick. And it will take days to debug. */
573 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
574 E1000_GPIE_PBA | E1000_GPIE_EIAME |
575 E1000_GPIE_NSICR);
576
577 /* enable msix_other interrupt */
578 adapter->eims_other = 1 << vector;
2d064c06 579 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 580
047e0030 581 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 582 break;
583 default:
584 /* do nothing, since nothing else supports MSI-X */
585 break;
586 } /* switch (hw->mac.type) */
047e0030
AD		 587
588 adapter->eims_enable_mask |= adapter->eims_other;
589
590 for (i = 0; i < adapter->num_q_vectors; i++) {
591 struct igb_q_vector *q_vector = adapter->q_vector[i];
592 igb_assign_vector(q_vector, vector++);
593 adapter->eims_enable_mask |= q_vector->eims_value;
594 }
595
9d5c8243
AK		 596 wrfl();
597}
598
599/**
600 * igb_request_msix - Initialize MSI-X interrupts
601 *
602 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
603 * kernel.
604 **/
605static int igb_request_msix(struct igb_adapter *adapter)
606{
607 struct net_device *netdev = adapter->netdev;
047e0030 608 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 609 int i, err = 0, vector = 0;
610
047e0030
AD		 611 err = request_irq(adapter->msix_entries[vector].vector,
612 &igb_msix_other, 0, netdev->name, adapter);
613 if (err)
614 goto out;
615 vector++;
616
617 for (i = 0; i < adapter->num_q_vectors; i++) {
618 struct igb_q_vector *q_vector = adapter->q_vector[i];
619
620 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
621
622 if (q_vector->rx_ring && q_vector->tx_ring)
623 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
624 q_vector->rx_ring->queue_index);
625 else if (q_vector->tx_ring)
626 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
627 q_vector->tx_ring->queue_index);
628 else if (q_vector->rx_ring)
629 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
630 q_vector->rx_ring->queue_index);
9d5c8243 631 else
047e0030
AD		 632 sprintf(q_vector->name, "%s-unused", netdev->name);
633
9d5c8243 634 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 635 &igb_msix_ring, 0, q_vector->name,
636 q_vector);
9d5c8243
AK		 637 if (err)
638 goto out;
9d5c8243
AK		 639 vector++;
640 }
641
9d5c8243
AK		 642 igb_configure_msix(adapter);
643 return 0;
644out:
645 return err;
646}
647
648static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
649{
650 if (adapter->msix_entries) {
651 pci_disable_msix(adapter->pdev);
652 kfree(adapter->msix_entries);
653 adapter->msix_entries = NULL;
047e0030 654 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 655 pci_disable_msi(adapter->pdev);
047e0030 656 }
9d5c8243
AK		 657}
658
047e0030
AD		 659/**
660 * igb_free_q_vectors - Free memory allocated for interrupt vectors
661 * @adapter: board private structure to initialize
662 *
663 * This function frees the memory allocated to the q_vectors. In addition if
664 * NAPI is enabled it will delete any references to the NAPI struct prior
665 * to freeing the q_vector.
666 **/
667static void igb_free_q_vectors(struct igb_adapter *adapter)
668{
669 int v_idx;
670
671 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
672 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
673 adapter->q_vector[v_idx] = NULL;
674 netif_napi_del(&q_vector->napi);
675 kfree(q_vector);
676 }
677 adapter->num_q_vectors = 0;
678}
679
680/**
681 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
682 *
683 * This function resets the device so that it has 0 rx queues, tx queues, and
684 * MSI-X interrupts allocated.
685 */
686static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
687{
688 igb_free_queues(adapter);
689 igb_free_q_vectors(adapter);
690 igb_reset_interrupt_capability(adapter);
691}
9d5c8243
AK		 692
693/**
694 * igb_set_interrupt_capability - set MSI or MSI-X if supported
695 *
696 * Attempt to configure interrupts using the best available
697 * capabilities of the hardware and kernel.
698 **/
699static void igb_set_interrupt_capability(struct igb_adapter *adapter)
700{
701 int err;
702 int numvecs, i;
703
83b7180d 704 /* Number of supported queues. */
83b7180d
AD		 705 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
706 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
707
047e0030
AD		 708 /* start with one vector for every rx queue */
709 numvecs = adapter->num_rx_queues;
710
711 /* if tx handler is seperate add 1 for every tx queue */
712 numvecs += adapter->num_tx_queues;
713
714 /* store the number of vectors reserved for queues */
715 adapter->num_q_vectors = numvecs;
716
717 /* add 1 vector for link status interrupts */
718 numvecs++;
9d5c8243
AK		 719 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
720 GFP_KERNEL);
721 if (!adapter->msix_entries)
722 goto msi_only;
723
724 for (i = 0; i < numvecs; i++)
725 adapter->msix_entries[i].entry = i;
726
727 err = pci_enable_msix(adapter->pdev,
728 adapter->msix_entries,
729 numvecs);
730 if (err == 0)
34a20e89 731 goto out;
9d5c8243
AK		 732
733 igb_reset_interrupt_capability(adapter);
734
735 /* If we can't do MSI-X, try MSI */
736msi_only:
2a3abf6d
AD		 737#ifdef CONFIG_PCI_IOV
738 /* disable SR-IOV for non MSI-X configurations */
739 if (adapter->vf_data) {
740 struct e1000_hw *hw = &adapter->hw;
741 /* disable iov and allow time for transactions to clear */
742 pci_disable_sriov(adapter->pdev);
743 msleep(500);
744
745 kfree(adapter->vf_data);
746 adapter->vf_data = NULL;
747 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
748 msleep(100);
749 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
750 }
751#endif
9d5c8243 752 adapter->num_rx_queues = 1;
661086df 753 adapter->num_tx_queues = 1;
047e0030 754 adapter->num_q_vectors = 1;
9d5c8243 755 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 756 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 757out:
661086df 758 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 759 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 760 return;
761}
762
047e0030
AD		 763/**
764 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
765 * @adapter: board private structure to initialize
766 *
767 * We allocate one q_vector per queue interrupt. If allocation fails we
768 * return -ENOMEM.
769 **/
770static int igb_alloc_q_vectors(struct igb_adapter *adapter)
771{
772 struct igb_q_vector *q_vector;
773 struct e1000_hw *hw = &adapter->hw;
774 int v_idx;
775
776 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
777 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
778 if (!q_vector)
779 goto err_out;
780 q_vector->adapter = adapter;
781 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
782 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
783 q_vector->itr_val = IGB_START_ITR;
784 q_vector->set_itr = 1;
785 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
786 adapter->q_vector[v_idx] = q_vector;
787 }
788 return 0;
789
790err_out:
791 while (v_idx) {
792 v_idx--;
793 q_vector = adapter->q_vector[v_idx];
794 netif_napi_del(&q_vector->napi);
795 kfree(q_vector);
796 adapter->q_vector[v_idx] = NULL;
797 }
798 return -ENOMEM;
799}
800
801static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
802 int ring_idx, int v_idx)
803{
804 struct igb_q_vector *q_vector;
805
806 q_vector = adapter->q_vector[v_idx];
807 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
808 q_vector->rx_ring->q_vector = q_vector;
809 q_vector->itr_val = adapter->itr;
810}
811
812static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
813 int ring_idx, int v_idx)
814{
815 struct igb_q_vector *q_vector;
816
817 q_vector = adapter->q_vector[v_idx];
818 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
819 q_vector->tx_ring->q_vector = q_vector;
820 q_vector->itr_val = adapter->itr;
821}
822
823/**
824 * igb_map_ring_to_vector - maps allocated queues to vectors
825 *
826 * This function maps the recently allocated queues to vectors.
827 **/
828static int igb_map_ring_to_vector(struct igb_adapter *adapter)
829{
830 int i;
831 int v_idx = 0;
832
833 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
834 (adapter->num_q_vectors < adapter->num_tx_queues))
835 return -ENOMEM;
836
837 if (adapter->num_q_vectors >=
838 (adapter->num_rx_queues + adapter->num_tx_queues)) {
839 for (i = 0; i < adapter->num_rx_queues; i++)
840 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
841 for (i = 0; i < adapter->num_tx_queues; i++)
842 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
843 } else {
844 for (i = 0; i < adapter->num_rx_queues; i++) {
845 if (i < adapter->num_tx_queues)
846 igb_map_tx_ring_to_vector(adapter, i, v_idx);
847 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
848 }
849 for (; i < adapter->num_tx_queues; i++)
850 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
851 }
852 return 0;
853}
854
855/**
856 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
857 *
858 * This function initializes the interrupts and allocates all of the queues.
859 **/
860static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
861{
862 struct pci_dev *pdev = adapter->pdev;
863 int err;
864
865 igb_set_interrupt_capability(adapter);
866
867 err = igb_alloc_q_vectors(adapter);
868 if (err) {
869 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
870 goto err_alloc_q_vectors;
871 }
872
873 err = igb_alloc_queues(adapter);
874 if (err) {
875 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
876 goto err_alloc_queues;
877 }
878
879 err = igb_map_ring_to_vector(adapter);
880 if (err) {
881 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
882 goto err_map_queues;
883 }
884
885
886 return 0;
887err_map_queues:
888 igb_free_queues(adapter);
889err_alloc_queues:
890 igb_free_q_vectors(adapter);
891err_alloc_q_vectors:
892 igb_reset_interrupt_capability(adapter);
893 return err;
894}
895
9d5c8243
AK		 896/**
897 * igb_request_irq - initialize interrupts
898 *
899 * Attempts to configure interrupts using the best available
900 * capabilities of the hardware and kernel.
901 **/
902static int igb_request_irq(struct igb_adapter *adapter)
903{
904 struct net_device *netdev = adapter->netdev;
047e0030 905 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 906 struct e1000_hw *hw = &adapter->hw;
907 int err = 0;
908
909 if (adapter->msix_entries) {
910 err = igb_request_msix(adapter);
844290e5 911 if (!err)
9d5c8243 912 goto request_done;
9d5c8243 913 /* fall back to MSI */
047e0030 914 igb_clear_interrupt_scheme(adapter);
9d5c8243 915 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 916 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 917 igb_free_all_tx_resources(adapter);
918 igb_free_all_rx_resources(adapter);
047e0030 919 adapter->num_tx_queues = 1;
9d5c8243 920 adapter->num_rx_queues = 1;
047e0030
AD		 921 adapter->num_q_vectors = 1;
922 err = igb_alloc_q_vectors(adapter);
923 if (err) {
924 dev_err(&pdev->dev,
925 "Unable to allocate memory for vectors\n");
926 goto request_done;
927 }
928 err = igb_alloc_queues(adapter);
929 if (err) {
930 dev_err(&pdev->dev,
931 "Unable to allocate memory for queues\n");
932 igb_free_q_vectors(adapter);
933 goto request_done;
934 }
935 igb_setup_all_tx_resources(adapter);
936 igb_setup_all_rx_resources(adapter);
844290e5 937 } else {
2d064c06
AD		 938 switch (hw->mac.type) {
939 case e1000_82575:
940 wr32(E1000_MSIXBM(0),
047e0030
AD		 941 (E1000_EICR_RX_QUEUE0 |
942 E1000_EICR_TX_QUEUE0 |
943 E1000_EIMS_OTHER));
2d064c06
AD		 944 break;
945 case e1000_82576:
946 wr32(E1000_IVAR0, E1000_IVAR_VALID);
947 break;
948 default:
949 break;
950 }
9d5c8243 951 }
844290e5 952
7dfc16fa 953 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 954 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 955 netdev->name, adapter);
9d5c8243
AK		 956 if (!err)
957 goto request_done;
047e0030 958
9d5c8243
AK		 959 /* fall back to legacy interrupts */
960 igb_reset_interrupt_capability(adapter);
7dfc16fa 961 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 962 }
963
964 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 965 netdev->name, adapter);
9d5c8243 966
6cb5e577 967 if (err)
9d5c8243
AK		 968 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
969 err);
9d5c8243
AK		 970
971request_done:
972 return err;
973}
974
975static void igb_free_irq(struct igb_adapter *adapter)
976{
9d5c8243
AK		 977 if (adapter->msix_entries) {
978 int vector = 0, i;
979
047e0030 980 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 981
047e0030
AD		 982 for (i = 0; i < adapter->num_q_vectors; i++) {
983 struct igb_q_vector *q_vector = adapter->q_vector[i];
984 free_irq(adapter->msix_entries[vector++].vector,
985 q_vector);
986 }
987 } else {
988 free_irq(adapter->pdev->irq, adapter);
9d5c8243 989 }
9d5c8243
AK		 990}
991
992/**
993 * igb_irq_disable - Mask off interrupt generation on the NIC
994 * @adapter: board private structure
995 **/
996static void igb_irq_disable(struct igb_adapter *adapter)
997{
998 struct e1000_hw *hw = &adapter->hw;
999
1000 if (adapter->msix_entries) {
2dfd1212
AD		 1001 u32 regval = rd32(E1000_EIAM);
1002 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1003 wr32(E1000_EIMC, adapter->eims_enable_mask);
1004 regval = rd32(E1000_EIAC);
1005 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1006 }
844290e5
PW		 1007
1008 wr32(E1000_IAM, 0);
9d5c8243
AK		 1009 wr32(E1000_IMC, ~0);
1010 wrfl();
1011 synchronize_irq(adapter->pdev->irq);
1012}
1013
1014/**
1015 * igb_irq_enable - Enable default interrupt generation settings
1016 * @adapter: board private structure
1017 **/
1018static void igb_irq_enable(struct igb_adapter *adapter)
1019{
1020 struct e1000_hw *hw = &adapter->hw;
1021
1022 if (adapter->msix_entries) {
2dfd1212
AD		 1023 u32 regval = rd32(E1000_EIAC);
1024 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1025 regval = rd32(E1000_EIAM);
1026 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1027 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 1028 if (adapter->vfs_allocated_count)
1029 wr32(E1000_MBVFIMR, 0xFF);
1030 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
1031 E1000_IMS_DOUTSYNC));
844290e5
PW		 1032 } else {
1033 wr32(E1000_IMS, IMS_ENABLE_MASK);
1034 wr32(E1000_IAM, IMS_ENABLE_MASK);
1035 }
9d5c8243
AK		 1036}
1037
1038static void igb_update_mng_vlan(struct igb_adapter *adapter)
1039{
1040 struct net_device *netdev = adapter->netdev;
1041 u16 vid = adapter->hw.mng_cookie.vlan_id;
1042 u16 old_vid = adapter->mng_vlan_id;
1043 if (adapter->vlgrp) {
1044 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
1045 if (adapter->hw.mng_cookie.status &
1046 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1047 igb_vlan_rx_add_vid(netdev, vid);
1048 adapter->mng_vlan_id = vid;
1049 } else
1050 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1051
1052 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1053 (vid != old_vid) &&
1054 !vlan_group_get_device(adapter->vlgrp, old_vid))
1055 igb_vlan_rx_kill_vid(netdev, old_vid);
1056 } else
1057 adapter->mng_vlan_id = vid;
1058 }
1059}
1060
1061/**
1062 * igb_release_hw_control - release control of the h/w to f/w
1063 * @adapter: address of board private structure
1064 *
1065 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1066 * For ASF and Pass Through versions of f/w this means that the
1067 * driver is no longer loaded.
1068 *
1069 **/
1070static void igb_release_hw_control(struct igb_adapter *adapter)
1071{
1072 struct e1000_hw *hw = &adapter->hw;
1073 u32 ctrl_ext;
1074
1075 /* Let firmware take over control of h/w */
1076 ctrl_ext = rd32(E1000_CTRL_EXT);
1077 wr32(E1000_CTRL_EXT,
1078 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1079}
1080
1081
1082/**
1083 * igb_get_hw_control - get control of the h/w from f/w
1084 * @adapter: address of board private structure
1085 *
1086 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1087 * For ASF and Pass Through versions of f/w this means that
1088 * the driver is loaded.
1089 *
1090 **/
1091static void igb_get_hw_control(struct igb_adapter *adapter)
1092{
1093 struct e1000_hw *hw = &adapter->hw;
1094 u32 ctrl_ext;
1095
1096 /* Let firmware know the driver has taken over */
1097 ctrl_ext = rd32(E1000_CTRL_EXT);
1098 wr32(E1000_CTRL_EXT,
1099 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1100}
1101
9d5c8243
AK		 1102/**
1103 * igb_configure - configure the hardware for RX and TX
1104 * @adapter: private board structure
1105 **/
1106static void igb_configure(struct igb_adapter *adapter)
1107{
1108 struct net_device *netdev = adapter->netdev;
1109 int i;
1110
1111 igb_get_hw_control(adapter);
ff41f8dc 1112 igb_set_rx_mode(netdev);
9d5c8243
AK		 1113
1114 igb_restore_vlan(adapter);
9d5c8243 1115
85b430b4 1116 igb_setup_tctl(adapter);
9d5c8243 1117 igb_setup_rctl(adapter);
85b430b4
AD		 1118
1119 igb_configure_tx(adapter);
9d5c8243 1120 igb_configure_rx(adapter);
662d7205
AD		 1121
1122 igb_rx_fifo_flush_82575(&adapter->hw);
1123
c493ea45 1124 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1125 * at least 1 descriptor unused to make sure
1126 * next_to_use != next_to_clean */
1127 for (i = 0; i < adapter->num_rx_queues; i++) {
1128 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1129 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1130 }
1131
1132
1133 adapter->tx_queue_len = netdev->tx_queue_len;
1134}
1135
1136
1137/**
1138 * igb_up - Open the interface and prepare it to handle traffic
1139 * @adapter: board private structure
1140 **/
1141
1142int igb_up(struct igb_adapter *adapter)
1143{
1144 struct e1000_hw *hw = &adapter->hw;
1145 int i;
1146
1147 /* hardware has been reset, we need to reload some things */
1148 igb_configure(adapter);
1149
1150 clear_bit(__IGB_DOWN, &adapter->state);
1151
047e0030
AD		 1152 for (i = 0; i < adapter->num_q_vectors; i++) {
1153 struct igb_q_vector *q_vector = adapter->q_vector[i];
1154 napi_enable(&q_vector->napi);
1155 }
844290e5 1156 if (adapter->msix_entries)
9d5c8243 1157 igb_configure_msix(adapter);
9d5c8243 1158
4ae196df 1159 igb_vmm_control(adapter);
e1739522
AD		 1160 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1161
9d5c8243
AK		 1162 /* Clear any pending interrupts. */
1163 rd32(E1000_ICR);
1164 igb_irq_enable(adapter);
1165
4cb9be7a
JB		 1166 netif_tx_start_all_queues(adapter->netdev);
1167
9d5c8243
AK		 1168 /* Fire a link change interrupt to start the watchdog. */
1169 wr32(E1000_ICS, E1000_ICS_LSC);
1170 return 0;
1171}
1172
1173void igb_down(struct igb_adapter *adapter)
1174{
1175 struct e1000_hw *hw = &adapter->hw;
1176 struct net_device *netdev = adapter->netdev;
1177 u32 tctl, rctl;
1178 int i;
1179
1180 /* signal that we're down so the interrupt handler does not
1181 * reschedule our watchdog timer */
1182 set_bit(__IGB_DOWN, &adapter->state);
1183
1184 /* disable receives in the hardware */
1185 rctl = rd32(E1000_RCTL);
1186 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1187 /* flush and sleep below */
1188
fd2ea0a7 1189 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1190
1191 /* disable transmits in the hardware */
1192 tctl = rd32(E1000_TCTL);
1193 tctl &= ~E1000_TCTL_EN;
1194 wr32(E1000_TCTL, tctl);
1195 /* flush both disables and wait for them to finish */
1196 wrfl();
1197 msleep(10);
1198
047e0030
AD		 1199 for (i = 0; i < adapter->num_q_vectors; i++) {
1200 struct igb_q_vector *q_vector = adapter->q_vector[i];
1201 napi_disable(&q_vector->napi);
1202 }
9d5c8243 1203
9d5c8243
AK		 1204 igb_irq_disable(adapter);
1205
1206 del_timer_sync(&adapter->watchdog_timer);
1207 del_timer_sync(&adapter->phy_info_timer);
1208
1209 netdev->tx_queue_len = adapter->tx_queue_len;
1210 netif_carrier_off(netdev);
04fe6358
AD		 1211
1212 /* record the stats before reset*/
1213 igb_update_stats(adapter);
1214
9d5c8243
AK		 1215 adapter->link_speed = 0;
1216 adapter->link_duplex = 0;
1217
3023682e
JK		 1218 if (!pci_channel_offline(adapter->pdev))
1219 igb_reset(adapter);
9d5c8243
AK		 1220 igb_clean_all_tx_rings(adapter);
1221 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1222#ifdef CONFIG_IGB_DCA
1223
1224 /* since we reset the hardware DCA settings were cleared */
1225 igb_setup_dca(adapter);
1226#endif
9d5c8243
AK		 1227}
1228
1229void igb_reinit_locked(struct igb_adapter *adapter)
1230{
1231 WARN_ON(in_interrupt());
1232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1233 msleep(1);
1234 igb_down(adapter);
1235 igb_up(adapter);
1236 clear_bit(__IGB_RESETTING, &adapter->state);
1237}
1238
1239void igb_reset(struct igb_adapter *adapter)
1240{
1241 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1242 struct e1000_mac_info *mac = &hw->mac;
1243 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1244 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1245 u16 hwm;
1246
1247 /* Repartition Pba for greater than 9k mtu
1248 * To take effect CTRL.RST is required.
1249 */
fa4dfae0
AD		 1250 switch (mac->type) {
1251 case e1000_82576:
2d064c06 1252 pba = E1000_PBA_64K;
fa4dfae0
AD		 1253 break;
1254 case e1000_82575:
1255 default:
1256 pba = E1000_PBA_34K;
1257 break;
2d064c06 1258 }
9d5c8243 1259
2d064c06
AD		 1260 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1261 (mac->type < e1000_82576)) {
9d5c8243
AK		 1262 /* adjust PBA for jumbo frames */
1263 wr32(E1000_PBA, pba);
1264
1265 /* To maintain wire speed transmits, the Tx FIFO should be
1266 * large enough to accommodate two full transmit packets,
1267 * rounded up to the next 1KB and expressed in KB. Likewise,
1268 * the Rx FIFO should be large enough to accommodate at least
1269 * one full receive packet and is similarly rounded up and
1270 * expressed in KB. */
1271 pba = rd32(E1000_PBA);
1272 /* upper 16 bits has Tx packet buffer allocation size in KB */
1273 tx_space = pba >> 16;
1274 /* lower 16 bits has Rx packet buffer allocation size in KB */
1275 pba &= 0xffff;
1276 /* the tx fifo also stores 16 bytes of information about the tx
1277 * but don't include ethernet FCS because hardware appends it */
1278 min_tx_space = (adapter->max_frame_size +
85e8d004 1279 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1280 ETH_FCS_LEN) * 2;
1281 min_tx_space = ALIGN(min_tx_space, 1024);
1282 min_tx_space >>= 10;
1283 /* software strips receive CRC, so leave room for it */
1284 min_rx_space = adapter->max_frame_size;
1285 min_rx_space = ALIGN(min_rx_space, 1024);
1286 min_rx_space >>= 10;
1287
1288 /* If current Tx allocation is less than the min Tx FIFO size,
1289 * and the min Tx FIFO size is less than the current Rx FIFO
1290 * allocation, take space away from current Rx allocation */
1291 if (tx_space < min_tx_space &&
1292 ((min_tx_space - tx_space) < pba)) {
1293 pba = pba - (min_tx_space - tx_space);
1294
1295 /* if short on rx space, rx wins and must trump tx
1296 * adjustment */
1297 if (pba < min_rx_space)
1298 pba = min_rx_space;
1299 }
2d064c06 1300 wr32(E1000_PBA, pba);
9d5c8243 1301 }
9d5c8243
AK		 1302
1303 /* flow control settings */
1304 /* The high water mark must be low enough to fit one full frame
1305 * (or the size used for early receive) above it in the Rx FIFO.
1306 * Set it to the lower of:
1307 * - 90% of the Rx FIFO size, or
1308 * - the full Rx FIFO size minus one full frame */
1309 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1310 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1311
2d064c06
AD		 1312 if (mac->type < e1000_82576) {
1313 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1314 fc->low_water = fc->high_water - 8;
1315 } else {
1316 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1317 fc->low_water = fc->high_water - 16;
1318 }
9d5c8243
AK		 1319 fc->pause_time = 0xFFFF;
1320 fc->send_xon = 1;
0cce119a 1321 fc->current_mode = fc->requested_mode;
9d5c8243 1322
4ae196df
AD		 1323 /* disable receive for all VFs and wait one second */
1324 if (adapter->vfs_allocated_count) {
1325 int i;
1326 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1327 adapter->vf_data[i].clear_to_send = false;
1328
1329 /* ping all the active vfs to let them know we are going down */
1330 igb_ping_all_vfs(adapter);
1331
1332 /* disable transmits and receives */
1333 wr32(E1000_VFRE, 0);
1334 wr32(E1000_VFTE, 0);
1335 }
1336
9d5c8243
AK		 1337 /* Allow time for pending master requests to run */
1338 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1339 wr32(E1000_WUC, 0);
1340
1341 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1342 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1343
1344 igb_update_mng_vlan(adapter);
1345
1346 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1347 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1348
1349 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1350 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1351}
1352
2e5c6922
SH		 1353static const struct net_device_ops igb_netdev_ops = {
1354 .ndo_open = igb_open,
1355 .ndo_stop = igb_close,
00829823 1356 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1357 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1358 .ndo_set_rx_mode = igb_set_rx_mode,
1359 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1360 .ndo_set_mac_address = igb_set_mac,
1361 .ndo_change_mtu = igb_change_mtu,
1362 .ndo_do_ioctl = igb_ioctl,
1363 .ndo_tx_timeout = igb_tx_timeout,
1364 .ndo_validate_addr = eth_validate_addr,
1365 .ndo_vlan_rx_register = igb_vlan_rx_register,
1366 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1367 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1368#ifdef CONFIG_NET_POLL_CONTROLLER
1369 .ndo_poll_controller = igb_netpoll,
1370#endif
1371};
1372
9d5c8243
AK		 1373/**
1374 * igb_probe - Device Initialization Routine
1375 * @pdev: PCI device information struct
1376 * @ent: entry in igb_pci_tbl
1377 *
1378 * Returns 0 on success, negative on failure
1379 *
1380 * igb_probe initializes an adapter identified by a pci_dev structure.
1381 * The OS initialization, configuring of the adapter private structure,
1382 * and a hardware reset occur.
1383 **/
1384static int __devinit igb_probe(struct pci_dev *pdev,
1385 const struct pci_device_id *ent)
1386{
1387 struct net_device *netdev;
1388 struct igb_adapter *adapter;
1389 struct e1000_hw *hw;
1390 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1391 unsigned long mmio_start, mmio_len;
2d6a5e95 1392 int err, pci_using_dac;
682337fe 1393 u16 eeprom_data = 0;
9d5c8243
AK		 1394 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1395 u32 part_num;
1396
aed5dec3 1397 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1398 if (err)
1399 return err;
1400
1401 pci_using_dac = 0;
6a35528a 1402 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1403 if (!err) {
6a35528a 1404 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1405 if (!err)
1406 pci_using_dac = 1;
1407 } else {
284901a9 1408 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1409 if (err) {
284901a9 1410 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1411 if (err) {
1412 dev_err(&pdev->dev, "No usable DMA "
1413 "configuration, aborting\n");
1414 goto err_dma;
1415 }
1416 }
1417 }
1418
aed5dec3
AD		 1419 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1420 IORESOURCE_MEM),
1421 igb_driver_name);
9d5c8243
AK		 1422 if (err)
1423 goto err_pci_reg;
1424
19d5afd4 1425 pci_enable_pcie_error_reporting(pdev);
40a914fa 1426
9d5c8243 1427 pci_set_master(pdev);
c682fc23 1428 pci_save_state(pdev);
9d5c8243
AK		 1429
1430 err = -ENOMEM;
1bfaf07b
AD		 1431 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1432 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1433 if (!netdev)
1434 goto err_alloc_etherdev;
1435
1436 SET_NETDEV_DEV(netdev, &pdev->dev);
1437
1438 pci_set_drvdata(pdev, netdev);
1439 adapter = netdev_priv(netdev);
1440 adapter->netdev = netdev;
1441 adapter->pdev = pdev;
1442 hw = &adapter->hw;
1443 hw->back = adapter;
1444 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1445
1446 mmio_start = pci_resource_start(pdev, 0);
1447 mmio_len = pci_resource_len(pdev, 0);
1448
1449 err = -EIO;
28b0759c
AD		 1450 hw->hw_addr = ioremap(mmio_start, mmio_len);
1451 if (!hw->hw_addr)
9d5c8243
AK		 1452 goto err_ioremap;
1453
2e5c6922 1454 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1455 igb_set_ethtool_ops(netdev);
9d5c8243 1456 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1457
1458 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1459
1460 netdev->mem_start = mmio_start;
1461 netdev->mem_end = mmio_start + mmio_len;
1462
9d5c8243
AK		 1463 /* PCI config space info */
1464 hw->vendor_id = pdev->vendor;
1465 hw->device_id = pdev->device;
1466 hw->revision_id = pdev->revision;
1467 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1468 hw->subsystem_device_id = pdev->subsystem_device;
1469
1470 /* setup the private structure */
1471 hw->back = adapter;
1472 /* Copy the default MAC, PHY and NVM function pointers */
1473 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1474 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1475 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1476 /* Initialize skew-specific constants */
1477 err = ei->get_invariants(hw);
1478 if (err)
450c87c8 1479 goto err_sw_init;
9d5c8243 1480
2a3abf6d
AD		 1481#ifdef CONFIG_PCI_IOV
1482 /* since iov functionality isn't critical to base device function we
1483 * can accept failure. If it fails we don't allow iov to be enabled */
1484 if (hw->mac.type == e1000_82576) {
1485 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1486 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1487 int i;
1488 unsigned char mac_addr[ETH_ALEN];
1489
9ca046d5 1490 if (num_vfs) {
2a3abf6d
AD		 1491 adapter->vf_data = kcalloc(num_vfs,
1492 sizeof(struct vf_data_storage),
1493 GFP_KERNEL);
9ca046d5
AD		 1494 if (!adapter->vf_data) {
1495 dev_err(&pdev->dev,
1496 "Could not allocate VF private data - "
1497 "IOV enable failed\n");
2a3abf6d 1498 } else {
9ca046d5
AD		 1499 err = pci_enable_sriov(pdev, num_vfs);
1500 if (!err) {
1501 adapter->vfs_allocated_count = num_vfs;
1502 dev_info(&pdev->dev,
1503 "%d vfs allocated\n",
1504 num_vfs);
1505 for (i = 0;
1506 i < adapter->vfs_allocated_count;
1507 i++) {
1508 random_ether_addr(mac_addr);
1509 igb_set_vf_mac(adapter, i,
1510 mac_addr);
1511 }
1512 } else {
1513 kfree(adapter->vf_data);
1514 adapter->vf_data = NULL;
1515 }
2a3abf6d
AD		 1516 }
1517 }
1518 }
1519
1520#endif
450c87c8 1521 /* setup the private structure */
9d5c8243
AK		 1522 err = igb_sw_init(adapter);
1523 if (err)
1524 goto err_sw_init;
1525
1526 igb_get_bus_info_pcie(hw);
1527
1528 hw->phy.autoneg_wait_to_complete = false;
1529 hw->mac.adaptive_ifs = true;
1530
1531 /* Copper options */
1532 if (hw->phy.media_type == e1000_media_type_copper) {
1533 hw->phy.mdix = AUTO_ALL_MODES;
1534 hw->phy.disable_polarity_correction = false;
1535 hw->phy.ms_type = e1000_ms_hw_default;
1536 }
1537
1538 if (igb_check_reset_block(hw))
1539 dev_info(&pdev->dev,
1540 "PHY reset is blocked due to SOL/IDER session.\n");
1541
1542 netdev->features = NETIF_F_SG |
7d8eb29e 1543 NETIF_F_IP_CSUM |
9d5c8243
AK		 1544 NETIF_F_HW_VLAN_TX |
1545 NETIF_F_HW_VLAN_RX |
1546 NETIF_F_HW_VLAN_FILTER;
1547
7d8eb29e 1548 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1549 netdev->features |= NETIF_F_TSO;
9d5c8243 1550 netdev->features |= NETIF_F_TSO6;
48f29ffc 1551
5c0999b7 1552 netdev->features |= NETIF_F_GRO;
d3352520 1553
48f29ffc
JK		 1554 netdev->vlan_features |= NETIF_F_TSO;
1555 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1556 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1557 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1558 netdev->vlan_features |= NETIF_F_SG;
1559
9d5c8243
AK		 1560 if (pci_using_dac)
1561 netdev->features |= NETIF_F_HIGHDMA;
1562
b9473560
JB		 1563 if (adapter->hw.mac.type == e1000_82576)
1564 netdev->features |= NETIF_F_SCTP_CSUM;
1565
9d5c8243
AK		 1566 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1567
1568 /* before reading the NVM, reset the controller to put the device in a
1569 * known good starting state */
1570 hw->mac.ops.reset_hw(hw);
1571
1572 /* make sure the NVM is good */
1573 if (igb_validate_nvm_checksum(hw) < 0) {
1574 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1575 err = -EIO;
1576 goto err_eeprom;
1577 }
1578
1579 /* copy the MAC address out of the NVM */
1580 if (hw->mac.ops.read_mac_addr(hw))
1581 dev_err(&pdev->dev, "NVM Read Error\n");
1582
1583 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1584 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1585
1586 if (!is_valid_ether_addr(netdev->perm_addr)) {
1587 dev_err(&pdev->dev, "Invalid MAC Address\n");
1588 err = -EIO;
1589 goto err_eeprom;
1590 }
1591
0e340485
AD		 1592 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1593 (unsigned long) adapter);
1594 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1595 (unsigned long) adapter);
9d5c8243
AK		 1596
1597 INIT_WORK(&adapter->reset_task, igb_reset_task);
1598 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1599
450c87c8 1600 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1601 adapter->fc_autoneg = true;
1602 hw->mac.autoneg = true;
1603 hw->phy.autoneg_advertised = 0x2f;
1604
0cce119a
AD		 1605 hw->fc.requested_mode = e1000_fc_default;
1606 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1607
cbd347ad 1608 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1609 adapter->itr = IGB_START_ITR;
1610
1611 igb_validate_mdi_setting(hw);
1612
9d5c8243
AK		 1613 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1614 * enable the ACPI Magic Packet filter
1615 */
1616
a2cf8b6c 1617 if (hw->bus.func == 0)
312c75ae 1618 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1619 else if (hw->bus.func == 1)
1620 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1621
1622 if (eeprom_data & eeprom_apme_mask)
1623 adapter->eeprom_wol |= E1000_WUFC_MAG;
1624
1625 /* now that we have the eeprom settings, apply the special cases where
1626 * the eeprom may be wrong or the board simply won't support wake on
1627 * lan on a particular port */
1628 switch (pdev->device) {
1629 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1630 adapter->eeprom_wol = 0;
1631 break;
1632 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1633 case E1000_DEV_ID_82576_FIBER:
1634 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1635 /* Wake events only supported on port A for dual fiber
1636 * regardless of eeprom setting */
1637 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1638 adapter->eeprom_wol = 0;
1639 break;
c8ea5ea9
AD		 1640 case E1000_DEV_ID_82576_QUAD_COPPER:
1641 /* if quad port adapter, disable WoL on all but port A */
1642 if (global_quad_port_a != 0)
1643 adapter->eeprom_wol = 0;
1644 else
1645 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1646 /* Reset for multiple quad port adapters */
1647 if (++global_quad_port_a == 4)
1648 global_quad_port_a = 0;
1649 break;
9d5c8243
AK		 1650 }
1651
1652 /* initialize the wol settings based on the eeprom settings */
1653 adapter->wol = adapter->eeprom_wol;
e1b86d84 1654 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1655
1656 /* reset the hardware with the new settings */
1657 igb_reset(adapter);
1658
1659 /* let the f/w know that the h/w is now under the control of the
1660 * driver. */
1661 igb_get_hw_control(adapter);
1662
9d5c8243
AK		 1663 strcpy(netdev->name, "eth%d");
1664 err = register_netdev(netdev);
1665 if (err)
1666 goto err_register;
1667
b168dfc5
JB		 1668 /* carrier off reporting is important to ethtool even BEFORE open */
1669 netif_carrier_off(netdev);
1670
421e02f0 1671#ifdef CONFIG_IGB_DCA
bbd98fe4 1672 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1673 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1674 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1675 igb_setup_dca(adapter);
1676 }
1677#endif
1678
38c845c7
PO		 1679 /*
1680 * Initialize hardware timer: we keep it running just in case
1681 * that some program needs it later on.
1682 */
1683 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1684 adapter->cycles.read = igb_read_clock;
1685 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1686 adapter->cycles.mult = 1;
1687 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1688 wr32(E1000_TIMINCA,
1689 (1<<24) |
1690 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1691#if 0
1692 /*
1693 * Avoid rollover while we initialize by resetting the time counter.
1694 */
1695 wr32(E1000_SYSTIML, 0x00000000);
1696 wr32(E1000_SYSTIMH, 0x00000000);
1697#else
1698 /*
1699 * Set registers so that rollover occurs soon to test this.
1700 */
1701 wr32(E1000_SYSTIML, 0x00000000);
1702 wr32(E1000_SYSTIMH, 0xFF800000);
1703#endif
1704 wrfl();
1705 timecounter_init(&adapter->clock,
1706 &adapter->cycles,
1707 ktime_to_ns(ktime_get_real()));
1708
33af6bcc
PO		 1709 /*
1710 * Synchronize our NIC clock against system wall clock. NIC
1711 * time stamp reading requires ~3us per sample, each sample
1712 * was pretty stable even under load => only require 10
1713 * samples for each offset comparison.
1714 */
1715 memset(&adapter->compare, 0, sizeof(adapter->compare));
1716 adapter->compare.source = &adapter->clock;
1717 adapter->compare.target = ktime_get_real;
1718 adapter->compare.num_samples = 10;
1719 timecompare_update(&adapter->compare, 0);
1720
38c845c7
PO		 1721#ifdef DEBUG
1722 {
1723 char buffer[160];
1724 printk(KERN_DEBUG
1725 "igb: %s: hw %p initialized timer\n",
1726 igb_get_time_str(adapter, buffer),
1727 &adapter->hw);
1728 }
1729#endif
1730
9d5c8243
AK		 1731 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1732 /* print bus type/speed/width info */
7c510e4b 1733 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1734 netdev->name,
1735 ((hw->bus.speed == e1000_bus_speed_2500)
1736 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1737 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1738 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1739 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1740 "unknown"),
7c510e4b 1741 netdev->dev_addr);
9d5c8243
AK		 1742
1743 igb_read_part_num(hw, &part_num);
1744 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1745 (part_num >> 8), (part_num & 0xff));
1746
1747 dev_info(&pdev->dev,
1748 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1749 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1750 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1751 adapter->num_rx_queues, adapter->num_tx_queues);
1752
9d5c8243
AK		 1753 return 0;
1754
1755err_register:
1756 igb_release_hw_control(adapter);
1757err_eeprom:
1758 if (!igb_check_reset_block(hw))
f5f4cf08 1759 igb_reset_phy(hw);
9d5c8243
AK		 1760
1761 if (hw->flash_address)
1762 iounmap(hw->flash_address);
9d5c8243 1763err_sw_init:
047e0030 1764 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1765 iounmap(hw->hw_addr);
1766err_ioremap:
1767 free_netdev(netdev);
1768err_alloc_etherdev:
aed5dec3
AD		 1769 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1770 IORESOURCE_MEM));
9d5c8243
AK		 1771err_pci_reg:
1772err_dma:
1773 pci_disable_device(pdev);
1774 return err;
1775}
1776
1777/**
1778 * igb_remove - Device Removal Routine
1779 * @pdev: PCI device information struct
1780 *
1781 * igb_remove is called by the PCI subsystem to alert the driver
1782 * that it should release a PCI device. The could be caused by a
1783 * Hot-Plug event, or because the driver is going to be removed from
1784 * memory.
1785 **/
1786static void __devexit igb_remove(struct pci_dev *pdev)
1787{
1788 struct net_device *netdev = pci_get_drvdata(pdev);
1789 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1790 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1791
1792 /* flush_scheduled work may reschedule our watchdog task, so
1793 * explicitly disable watchdog tasks from being rescheduled */
1794 set_bit(__IGB_DOWN, &adapter->state);
1795 del_timer_sync(&adapter->watchdog_timer);
1796 del_timer_sync(&adapter->phy_info_timer);
1797
1798 flush_scheduled_work();
1799
421e02f0 1800#ifdef CONFIG_IGB_DCA
7dfc16fa 1801 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1802 dev_info(&pdev->dev, "DCA disabled\n");
1803 dca_remove_requester(&pdev->dev);
7dfc16fa 1804 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1805 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1806 }
1807#endif
1808
9d5c8243
AK		 1809 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1810 * would have already happened in close and is redundant. */
1811 igb_release_hw_control(adapter);
1812
1813 unregister_netdev(netdev);
1814
f5f4cf08
AD		 1815 if (!igb_check_reset_block(&adapter->hw))
1816 igb_reset_phy(&adapter->hw);
9d5c8243 1817
047e0030 1818 igb_clear_interrupt_scheme(adapter);
9d5c8243 1819
37680117
AD		 1820#ifdef CONFIG_PCI_IOV
1821 /* reclaim resources allocated to VFs */
1822 if (adapter->vf_data) {
1823 /* disable iov and allow time for transactions to clear */
1824 pci_disable_sriov(pdev);
1825 msleep(500);
1826
1827 kfree(adapter->vf_data);
1828 adapter->vf_data = NULL;
1829 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1830 msleep(100);
1831 dev_info(&pdev->dev, "IOV Disabled\n");
1832 }
1833#endif
28b0759c
AD		 1834 iounmap(hw->hw_addr);
1835 if (hw->flash_address)
1836 iounmap(hw->flash_address);
aed5dec3
AD		 1837 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1838 IORESOURCE_MEM));
9d5c8243
AK		 1839
1840 free_netdev(netdev);
1841
19d5afd4 1842 pci_disable_pcie_error_reporting(pdev);
40a914fa 1843
9d5c8243
AK		 1844 pci_disable_device(pdev);
1845}
1846
1847/**
1848 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1849 * @adapter: board private structure to initialize
1850 *
1851 * igb_sw_init initializes the Adapter private data structure.
1852 * Fields are initialized based on PCI device information and
1853 * OS network device settings (MTU size).
1854 **/
1855static int __devinit igb_sw_init(struct igb_adapter *adapter)
1856{
1857 struct e1000_hw *hw = &adapter->hw;
1858 struct net_device *netdev = adapter->netdev;
1859 struct pci_dev *pdev = adapter->pdev;
1860
1861 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1862
68fd9910
AD		 1863 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1864 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1865 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1866 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1867
661086df
PWJ		 1868 /* This call may decrease the number of queues depending on
1869 * interrupt mode. */
047e0030 1870 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1871 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1872 return -ENOMEM;
1873 }
1874
1875 /* Explicitly disable IRQ since the NIC can be in any state. */
1876 igb_irq_disable(adapter);
1877
1878 set_bit(__IGB_DOWN, &adapter->state);
1879 return 0;
1880}
1881
1882/**
1883 * igb_open - Called when a network interface is made active
1884 * @netdev: network interface device structure
1885 *
1886 * Returns 0 on success, negative value on failure
1887 *
1888 * The open entry point is called when a network interface is made
1889 * active by the system (IFF_UP). At this point all resources needed
1890 * for transmit and receive operations are allocated, the interrupt
1891 * handler is registered with the OS, the watchdog timer is started,
1892 * and the stack is notified that the interface is ready.
1893 **/
1894static int igb_open(struct net_device *netdev)
1895{
1896 struct igb_adapter *adapter = netdev_priv(netdev);
1897 struct e1000_hw *hw = &adapter->hw;
1898 int err;
1899 int i;
1900
1901 /* disallow open during test */
1902 if (test_bit(__IGB_TESTING, &adapter->state))
1903 return -EBUSY;
1904
b168dfc5
JB		 1905 netif_carrier_off(netdev);
1906
9d5c8243
AK		 1907 /* allocate transmit descriptors */
1908 err = igb_setup_all_tx_resources(adapter);
1909 if (err)
1910 goto err_setup_tx;
1911
1912 /* allocate receive descriptors */
1913 err = igb_setup_all_rx_resources(adapter);
1914 if (err)
1915 goto err_setup_rx;
1916
1917 /* e1000_power_up_phy(adapter); */
1918
1919 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1920 if ((adapter->hw.mng_cookie.status &
1921 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1922 igb_update_mng_vlan(adapter);
1923
1924 /* before we allocate an interrupt, we must be ready to handle it.
1925 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1926 * as soon as we call pci_request_irq, so we have to setup our
1927 * clean_rx handler before we do so. */
1928 igb_configure(adapter);
1929
4ae196df 1930 igb_vmm_control(adapter);
e1739522
AD		 1931 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1932
9d5c8243
AK		 1933 err = igb_request_irq(adapter);
1934 if (err)
1935 goto err_req_irq;
1936
1937 /* From here on the code is the same as igb_up() */
1938 clear_bit(__IGB_DOWN, &adapter->state);
1939
047e0030
AD		 1940 for (i = 0; i < adapter->num_q_vectors; i++) {
1941 struct igb_q_vector *q_vector = adapter->q_vector[i];
1942 napi_enable(&q_vector->napi);
1943 }
9d5c8243
AK		 1944
1945 /* Clear any pending interrupts. */
1946 rd32(E1000_ICR);
844290e5
PW		 1947
1948 igb_irq_enable(adapter);
1949
d55b53ff
JK		 1950 netif_tx_start_all_queues(netdev);
1951
9d5c8243
AK		 1952 /* Fire a link status change interrupt to start the watchdog. */
1953 wr32(E1000_ICS, E1000_ICS_LSC);
1954
1955 return 0;
1956
1957err_req_irq:
1958 igb_release_hw_control(adapter);
1959 /* e1000_power_down_phy(adapter); */
1960 igb_free_all_rx_resources(adapter);
1961err_setup_rx:
1962 igb_free_all_tx_resources(adapter);
1963err_setup_tx:
1964 igb_reset(adapter);
1965
1966 return err;
1967}
1968
1969/**
1970 * igb_close - Disables a network interface
1971 * @netdev: network interface device structure
1972 *
1973 * Returns 0, this is not allowed to fail
1974 *
1975 * The close entry point is called when an interface is de-activated
1976 * by the OS. The hardware is still under the driver's control, but
1977 * needs to be disabled. A global MAC reset is issued to stop the
1978 * hardware, and all transmit and receive resources are freed.
1979 **/
1980static int igb_close(struct net_device *netdev)
1981{
1982 struct igb_adapter *adapter = netdev_priv(netdev);
1983
1984 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1985 igb_down(adapter);
1986
1987 igb_free_irq(adapter);
1988
1989 igb_free_all_tx_resources(adapter);
1990 igb_free_all_rx_resources(adapter);
1991
1992 /* kill manageability vlan ID if supported, but not if a vlan with
1993 * the same ID is registered on the host OS (let 8021q kill it) */
1994 if ((adapter->hw.mng_cookie.status &
1995 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1996 !(adapter->vlgrp &&
1997 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1998 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1999
2000 return 0;
2001}
2002
2003/**
2004 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2005 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2006 *
2007 * Return 0 on success, negative on failure
2008 **/
80785298 2009int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2010{
80785298 2011 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 2012 int size;
2013
2014 size = sizeof(struct igb_buffer) * tx_ring->count;
2015 tx_ring->buffer_info = vmalloc(size);
2016 if (!tx_ring->buffer_info)
2017 goto err;
2018 memset(tx_ring->buffer_info, 0, size);
2019
2020 /* round up to nearest 4K */
85e8d004 2021 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2022 tx_ring->size = ALIGN(tx_ring->size, 4096);
2023
2024 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2025 &tx_ring->dma);
2026
2027 if (!tx_ring->desc)
2028 goto err;
2029
9d5c8243
AK		 2030 tx_ring->next_to_use = 0;
2031 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2032 return 0;
2033
2034err:
2035 vfree(tx_ring->buffer_info);
047e0030 2036 dev_err(&pdev->dev,
9d5c8243
AK		 2037 "Unable to allocate memory for the transmit descriptor ring\n");
2038 return -ENOMEM;
2039}
2040
2041/**
2042 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2043 * (Descriptors) for all queues
2044 * @adapter: board private structure
2045 *
2046 * Return 0 on success, negative on failure
2047 **/
2048static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2049{
2050 int i, err = 0;
661086df 2051 int r_idx;
9d5c8243
AK		 2052
2053 for (i = 0; i < adapter->num_tx_queues; i++) {
80785298 2054 err = igb_setup_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2055 if (err) {
2056 dev_err(&adapter->pdev->dev,
2057 "Allocation for Tx Queue %u failed\n", i);
2058 for (i--; i >= 0; i--)
3b644cf6 2059 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2060 break;
2061 }
2062 }
2063
661086df
PWJ		 2064 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2065 r_idx = i % adapter->num_tx_queues;
2066 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2067 }
9d5c8243
AK		 2068 return err;
2069}
2070
2071/**
85b430b4
AD		 2072 * igb_setup_tctl - configure the transmit control registers
2073 * @adapter: Board private structure
9d5c8243 2074 **/
85b430b4 2075static void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2076{
9d5c8243
AK		 2077 struct e1000_hw *hw = &adapter->hw;
2078 u32 tctl;
9d5c8243 2079
85b430b4
AD		 2080 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2081 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2082
2083 /* Program the Transmit Control Register */
9d5c8243
AK		 2084 tctl = rd32(E1000_TCTL);
2085 tctl &= ~E1000_TCTL_CT;
2086 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2087 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2088
2089 igb_config_collision_dist(hw);
2090
9d5c8243
AK		 2091 /* Enable transmits */
2092 tctl |= E1000_TCTL_EN;
2093
2094 wr32(E1000_TCTL, tctl);
2095}
2096
85b430b4
AD		 2097/**
2098 * igb_configure_tx_ring - Configure transmit ring after Reset
2099 * @adapter: board private structure
2100 * @ring: tx ring to configure
2101 *
2102 * Configure a transmit ring after a reset.
2103 **/
2104static void igb_configure_tx_ring(struct igb_adapter *adapter,
2105 struct igb_ring *ring)
2106{
2107 struct e1000_hw *hw = &adapter->hw;
2108 u32 txdctl;
2109 u64 tdba = ring->dma;
2110 int reg_idx = ring->reg_idx;
2111
2112 /* disable the queue */
2113 txdctl = rd32(E1000_TXDCTL(reg_idx));
2114 wr32(E1000_TXDCTL(reg_idx),
2115 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2116 wrfl();
2117 mdelay(10);
2118
2119 wr32(E1000_TDLEN(reg_idx),
2120 ring->count * sizeof(union e1000_adv_tx_desc));
2121 wr32(E1000_TDBAL(reg_idx),
2122 tdba & 0x00000000ffffffffULL);
2123 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2124
fce99e34
AD		 2125 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2126 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2127 writel(0, ring->head);
2128 writel(0, ring->tail);
85b430b4
AD		 2129
2130 txdctl |= IGB_TX_PTHRESH;
2131 txdctl |= IGB_TX_HTHRESH << 8;
2132 txdctl |= IGB_TX_WTHRESH << 16;
2133
2134 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2135 wr32(E1000_TXDCTL(reg_idx), txdctl);
2136}
2137
2138/**
2139 * igb_configure_tx - Configure transmit Unit after Reset
2140 * @adapter: board private structure
2141 *
2142 * Configure the Tx unit of the MAC after a reset.
2143 **/
2144static void igb_configure_tx(struct igb_adapter *adapter)
2145{
2146 int i;
2147
2148 for (i = 0; i < adapter->num_tx_queues; i++)
2149 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
85b430b4
AD		 2150}
2151
9d5c8243
AK		 2152/**
2153 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2154 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2155 *
2156 * Returns 0 on success, negative on failure
2157 **/
80785298 2158int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2159{
80785298 2160 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2161 int size, desc_len;
2162
2163 size = sizeof(struct igb_buffer) * rx_ring->count;
2164 rx_ring->buffer_info = vmalloc(size);
2165 if (!rx_ring->buffer_info)
2166 goto err;
2167 memset(rx_ring->buffer_info, 0, size);
2168
2169 desc_len = sizeof(union e1000_adv_rx_desc);
2170
2171 /* Round up to nearest 4K */
2172 rx_ring->size = rx_ring->count * desc_len;
2173 rx_ring->size = ALIGN(rx_ring->size, 4096);
2174
2175 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2176 &rx_ring->dma);
2177
2178 if (!rx_ring->desc)
2179 goto err;
2180
2181 rx_ring->next_to_clean = 0;
2182 rx_ring->next_to_use = 0;
9d5c8243 2183
9d5c8243
AK		 2184 return 0;
2185
2186err:
2187 vfree(rx_ring->buffer_info);
80785298 2188 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2189 "the receive descriptor ring\n");
2190 return -ENOMEM;
2191}
2192
2193/**
2194 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2195 * (Descriptors) for all queues
2196 * @adapter: board private structure
2197 *
2198 * Return 0 on success, negative on failure
2199 **/
2200static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2201{
2202 int i, err = 0;
2203
2204 for (i = 0; i < adapter->num_rx_queues; i++) {
80785298 2205 err = igb_setup_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2206 if (err) {
2207 dev_err(&adapter->pdev->dev,
2208 "Allocation for Rx Queue %u failed\n", i);
2209 for (i--; i >= 0; i--)
3b644cf6 2210 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2211 break;
2212 }
2213 }
2214
2215 return err;
2216}
2217
2218/**
2219 * igb_setup_rctl - configure the receive control registers
2220 * @adapter: Board private structure
2221 **/
2222static void igb_setup_rctl(struct igb_adapter *adapter)
2223{
2224 struct e1000_hw *hw = &adapter->hw;
2225 u32 rctl;
9d5c8243
AK		 2226
2227 rctl = rd32(E1000_RCTL);
2228
2229 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2230 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2231
69d728ba 2232 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2233 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2234
87cb7e8c
AK		 2235 /*
2236 * enable stripping of CRC. It's unlikely this will break BMC
2237 * redirection as it did with e1000. Newer features require
2238 * that the HW strips the CRC.
73cd78f1 2239 */
87cb7e8c 2240 rctl |= E1000_RCTL_SECRC;
9d5c8243 2241
9b07f3d3 2242 /*
ec54d7d6 2243 * disable store bad packets and clear size bits.
9b07f3d3 2244 */
ec54d7d6 2245 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2246
6ec43fe6
AD		 2247 /* enable LPE to prevent packets larger than max_frame_size */
2248 rctl |= E1000_RCTL_LPE;
9d5c8243 2249
952f72a8
AD		 2250 /* disable queue 0 to prevent tail write w/o re-config */
2251 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2252
e1739522
AD		 2253 /* Attention!!! For SR-IOV PF driver operations you must enable
2254 * queue drop for all VF and PF queues to prevent head of line blocking
2255 * if an un-trusted VF does not provide descriptors to hardware.
2256 */
2257 if (adapter->vfs_allocated_count) {
2258 u32 vmolr;
2259
e1739522
AD		 2260 /* set all queue drop enable bits */
2261 wr32(E1000_QDE, ALL_QUEUES);
e1739522 2262
77a22941 2263 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2264 if (rctl & E1000_RCTL_LPE)
2265 vmolr |= E1000_VMOLR_LPE;
77a22941 2266 if (adapter->num_rx_queues > 1)
e1739522 2267 vmolr |= E1000_VMOLR_RSSE;
77a22941 2268 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2269 }
2270
9d5c8243
AK		 2271 wr32(E1000_RCTL, rctl);
2272}
2273
e1739522
AD		 2274/**
2275 * igb_rlpml_set - set maximum receive packet size
2276 * @adapter: board private structure
2277 *
2278 * Configure maximum receivable packet size.
2279 **/
2280static void igb_rlpml_set(struct igb_adapter *adapter)
2281{
2282 u32 max_frame_size = adapter->max_frame_size;
2283 struct e1000_hw *hw = &adapter->hw;
2284 u16 pf_id = adapter->vfs_allocated_count;
2285
2286 if (adapter->vlgrp)
2287 max_frame_size += VLAN_TAG_SIZE;
2288
2289 /* if vfs are enabled we set RLPML to the largest possible request
2290 * size and set the VMOLR RLPML to the size we need */
2291 if (pf_id) {
2292 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2293 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2294 }
2295
2296 wr32(E1000_RLPML, max_frame_size);
2297}
2298
2299/**
2300 * igb_configure_vt_default_pool - Configure VT default pool
2301 * @adapter: board private structure
2302 *
2303 * Configure the default pool
2304 **/
2305static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2306{
2307 struct e1000_hw *hw = &adapter->hw;
2308 u16 pf_id = adapter->vfs_allocated_count;
2309 u32 vtctl;
2310
2311 /* not in sr-iov mode - do nothing */
2312 if (!pf_id)
2313 return;
2314
2315 vtctl = rd32(E1000_VT_CTL);
2316 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2317 E1000_VT_CTL_DISABLE_DEF_POOL);
2318 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2319 wr32(E1000_VT_CTL, vtctl);
2320}
2321
85b430b4
AD		 2322/**
2323 * igb_configure_rx_ring - Configure a receive ring after Reset
2324 * @adapter: board private structure
2325 * @ring: receive ring to be configured
2326 *
2327 * Configure the Rx unit of the MAC after a reset.
2328 **/
2329static void igb_configure_rx_ring(struct igb_adapter *adapter,
2330 struct igb_ring *ring)
2331{
2332 struct e1000_hw *hw = &adapter->hw;
2333 u64 rdba = ring->dma;
2334 int reg_idx = ring->reg_idx;
952f72a8 2335 u32 srrctl, rxdctl;
85b430b4
AD		 2336
2337 /* disable the queue */
2338 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2339 wr32(E1000_RXDCTL(reg_idx),
2340 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2341
2342 /* Set DMA base address registers */
2343 wr32(E1000_RDBAL(reg_idx),
2344 rdba & 0x00000000ffffffffULL);
2345 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2346 wr32(E1000_RDLEN(reg_idx),
2347 ring->count * sizeof(union e1000_adv_rx_desc));
2348
2349 /* initialize head and tail */
fce99e34
AD		 2350 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2351 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2352 writel(0, ring->head);
2353 writel(0, ring->tail);
85b430b4 2354
952f72a8 2355 /* set descriptor configuration */
4c844851
AD		 2356 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2357 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2358 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2359#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2360 srrctl |= IGB_RXBUFFER_16384 >>
2361 E1000_SRRCTL_BSIZEPKT_SHIFT;
2362#else
2363 srrctl |= (PAGE_SIZE / 2) >>
2364 E1000_SRRCTL_BSIZEPKT_SHIFT;
2365#endif
2366 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2367 } else {
4c844851 2368 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2369 E1000_SRRCTL_BSIZEPKT_SHIFT;
2370 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2371 }
2372
2373 wr32(E1000_SRRCTL(reg_idx), srrctl);
2374
85b430b4
AD		 2375 /* enable receive descriptor fetching */
2376 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2377 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2378 rxdctl &= 0xFFF00000;
2379 rxdctl |= IGB_RX_PTHRESH;
2380 rxdctl |= IGB_RX_HTHRESH << 8;
2381 rxdctl |= IGB_RX_WTHRESH << 16;
2382 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2383}
2384
9d5c8243
AK		 2385/**
2386 * igb_configure_rx - Configure receive Unit after Reset
2387 * @adapter: board private structure
2388 *
2389 * Configure the Rx unit of the MAC after a reset.
2390 **/
2391static void igb_configure_rx(struct igb_adapter *adapter)
2392{
9d5c8243
AK		 2393 struct e1000_hw *hw = &adapter->hw;
2394 u32 rctl, rxcsum;
9107584e 2395 int i;
9d5c8243
AK		 2396
2397 /* disable receives while setting up the descriptors */
2398 rctl = rd32(E1000_RCTL);
2399 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2400 wrfl();
2401 mdelay(10);
2402
2403 if (adapter->itr_setting > 3)
6eb5a7f1 2404 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2405
2406 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2407 * the Base and Length of the Rx Descriptor Ring */
85b430b4
AD		 2408 for (i = 0; i < adapter->num_rx_queues; i++)
2409 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2410
2411 if (adapter->num_rx_queues > 1) {
2412 u32 random[10];
2413 u32 mrqc;
2414 u32 j, shift;
2415 union e1000_reta {
2416 u32 dword;
2417 u8 bytes[4];
2418 } reta;
2419
2420 get_random_bytes(&random[0], 40);
2421
2d064c06
AD		 2422 if (hw->mac.type >= e1000_82576)
2423 shift = 0;
2424 else
2425 shift = 6;
9d5c8243
AK		 2426 for (j = 0; j < (32 * 4); j++) {
2427 reta.bytes[j & 3] =
26bc19ec 2428 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2429 if ((j & 3) == 3)
2430 writel(reta.dword,
2431 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2432 }
e1739522
AD		 2433 if (adapter->vfs_allocated_count)
2434 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2435 else
2436 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2437
2438 /* Fill out hash function seeds */
2439 for (j = 0; j < 10; j++)
2440 array_wr32(E1000_RSSRK(0), j, random[j]);
2441
2442 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2443 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2444 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2445 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2446 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2447 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2448 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2449 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2450
9d5c8243 2451 wr32(E1000_MRQC, mrqc);
2844f797 2452 } else if (adapter->vfs_allocated_count) {
e1739522 2453 /* Enable multi-queue for sr-iov */
2844f797 2454 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2455 }
2456
2844f797
AD		 2457 /* Enable Receive Checksum Offload for TCP and UDP */
2458 rxcsum = rd32(E1000_RXCSUM);
2459 /* Disable raw packet checksumming */
2460 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2461
2462 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2463 /* Enable Receive Checksum Offload for SCTP */
2464 rxcsum |= E1000_RXCSUM_CRCOFL;
2465
7beb0146 2466 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2467 wr32(E1000_RXCSUM, rxcsum);
2468
e1739522
AD		 2469 /* Set the default pool for the PF's first queue */
2470 igb_configure_vt_default_pool(adapter);
2471
68d480c4
AD		 2472 /* set UTA to appropriate mode */
2473 igb_set_uta(adapter);
2474
26ad9178
AD		 2475 /* set the correct pool for the PF default MAC address in entry 0 */
2476 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2477 adapter->vfs_allocated_count);
2478
e1739522 2479 igb_rlpml_set(adapter);
9d5c8243
AK		 2480
2481 /* Enable Receives */
2482 wr32(E1000_RCTL, rctl);
2483}
2484
2485/**
2486 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2487 * @tx_ring: Tx descriptor ring for a specific queue
2488 *
2489 * Free all transmit software resources
2490 **/
68fd9910 2491void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2492{
3b644cf6 2493 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2494
2495 vfree(tx_ring->buffer_info);
2496 tx_ring->buffer_info = NULL;
2497
80785298
AD		 2498 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2499 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2500
2501 tx_ring->desc = NULL;
2502}
2503
2504/**
2505 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2506 * @adapter: board private structure
2507 *
2508 * Free all transmit software resources
2509 **/
2510static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2511{
2512 int i;
2513
2514 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2515 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2516}
2517
80785298 2518static void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
9d5c8243
AK		 2519 struct igb_buffer *buffer_info)
2520{
65689fef 2521 buffer_info->dma = 0;
9d5c8243 2522 if (buffer_info->skb) {
80785298
AD		 2523 skb_dma_unmap(&tx_ring->pdev->dev,
2524 buffer_info->skb,
65689fef 2525 DMA_TO_DEVICE);
9d5c8243
AK		 2526 dev_kfree_skb_any(buffer_info->skb);
2527 buffer_info->skb = NULL;
2528 }
2529 buffer_info->time_stamp = 0;
2530 /* buffer_info must be completely set up in the transmit path */
2531}
2532
2533/**
2534 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2535 * @tx_ring: ring to be cleaned
2536 **/
3b644cf6 2537static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2538{
2539 struct igb_buffer *buffer_info;
2540 unsigned long size;
2541 unsigned int i;
2542
2543 if (!tx_ring->buffer_info)
2544 return;
2545 /* Free all the Tx ring sk_buffs */
2546
2547 for (i = 0; i < tx_ring->count; i++) {
2548 buffer_info = &tx_ring->buffer_info[i];
80785298 2549 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2550 }
2551
2552 size = sizeof(struct igb_buffer) * tx_ring->count;
2553 memset(tx_ring->buffer_info, 0, size);
2554
2555 /* Zero out the descriptor ring */
2556
2557 memset(tx_ring->desc, 0, tx_ring->size);
2558
2559 tx_ring->next_to_use = 0;
2560 tx_ring->next_to_clean = 0;
2561
fce99e34
AD		 2562 writel(0, tx_ring->head);
2563 writel(0, tx_ring->tail);
9d5c8243
AK		 2564}
2565
2566/**
2567 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2568 * @adapter: board private structure
2569 **/
2570static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2571{
2572 int i;
2573
2574 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2575 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2576}
2577
2578/**
2579 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2580 * @rx_ring: ring to clean the resources from
2581 *
2582 * Free all receive software resources
2583 **/
68fd9910 2584void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2585{
3b644cf6 2586 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2587
2588 vfree(rx_ring->buffer_info);
2589 rx_ring->buffer_info = NULL;
2590
80785298
AD		 2591 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2592 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2593
2594 rx_ring->desc = NULL;
2595}
2596
2597/**
2598 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2599 * @adapter: board private structure
2600 *
2601 * Free all receive software resources
2602 **/
2603static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2604{
2605 int i;
2606
2607 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2608 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2609}
2610
2611/**
2612 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2613 * @rx_ring: ring to free buffers from
2614 **/
3b644cf6 2615static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 2616{
2617 struct igb_buffer *buffer_info;
9d5c8243
AK		 2618 unsigned long size;
2619 unsigned int i;
2620
2621 if (!rx_ring->buffer_info)
2622 return;
2623 /* Free all the Rx ring sk_buffs */
2624 for (i = 0; i < rx_ring->count; i++) {
2625 buffer_info = &rx_ring->buffer_info[i];
2626 if (buffer_info->dma) {
80785298
AD		 2627 pci_unmap_single(rx_ring->pdev,
2628 buffer_info->dma,
4c844851 2629 rx_ring->rx_buffer_len,
6ec43fe6 2630 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2631 buffer_info->dma = 0;
2632 }
2633
2634 if (buffer_info->skb) {
2635 dev_kfree_skb(buffer_info->skb);
2636 buffer_info->skb = NULL;
2637 }
6ec43fe6 2638 if (buffer_info->page_dma) {
80785298
AD		 2639 pci_unmap_page(rx_ring->pdev,
2640 buffer_info->page_dma,
6ec43fe6
AD		 2641 PAGE_SIZE / 2,
2642 PCI_DMA_FROMDEVICE);
2643 buffer_info->page_dma = 0;
2644 }
9d5c8243 2645 if (buffer_info->page) {
9d5c8243
AK		 2646 put_page(buffer_info->page);
2647 buffer_info->page = NULL;
bf36c1a0 2648 buffer_info->page_offset = 0;
9d5c8243
AK		 2649 }
2650 }
2651
9d5c8243
AK		 2652 size = sizeof(struct igb_buffer) * rx_ring->count;
2653 memset(rx_ring->buffer_info, 0, size);
2654
2655 /* Zero out the descriptor ring */
2656 memset(rx_ring->desc, 0, rx_ring->size);
2657
2658 rx_ring->next_to_clean = 0;
2659 rx_ring->next_to_use = 0;
2660
fce99e34
AD		 2661 writel(0, rx_ring->head);
2662 writel(0, rx_ring->tail);
9d5c8243
AK		 2663}
2664
2665/**
2666 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2667 * @adapter: board private structure
2668 **/
2669static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2670{
2671 int i;
2672
2673 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2674 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2675}
2676
2677/**
2678 * igb_set_mac - Change the Ethernet Address of the NIC
2679 * @netdev: network interface device structure
2680 * @p: pointer to an address structure
2681 *
2682 * Returns 0 on success, negative on failure
2683 **/
2684static int igb_set_mac(struct net_device *netdev, void *p)
2685{
2686 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2687 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2688 struct sockaddr *addr = p;
2689
2690 if (!is_valid_ether_addr(addr->sa_data))
2691 return -EADDRNOTAVAIL;
2692
2693 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2694 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2695
26ad9178
AD		 2696 /* set the correct pool for the new PF MAC address in entry 0 */
2697 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2698 adapter->vfs_allocated_count);
e1739522 2699
9d5c8243
AK		 2700 return 0;
2701}
2702
2703/**
68d480c4 2704 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2705 * @netdev: network interface device structure
2706 *
68d480c4
AD		 2707 * Writes multicast address list to the MTA hash table.
2708 * Returns: -ENOMEM on failure
2709 * 0 on no addresses written
2710 * X on writing X addresses to MTA
9d5c8243 2711 **/
68d480c4 2712static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2713{
2714 struct igb_adapter *adapter = netdev_priv(netdev);
2715 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2716 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2717 u8 *mta_list;
2718 u32 vmolr = 0;
9d5c8243
AK		 2719 int i;
2720
68d480c4
AD		 2721 if (!netdev->mc_count) {
2722 /* nothing to program, so clear mc list */
2723 igb_update_mc_addr_list(hw, NULL, 0);
2724 igb_restore_vf_multicasts(adapter);
2725 return 0;
2726 }
9d5c8243 2727
68d480c4
AD		 2728 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2729 if (!mta_list)
2730 return -ENOMEM;
ff41f8dc 2731
68d480c4
AD		 2732 /* set vmolr receive overflow multicast bit */
2733 vmolr |= E1000_VMOLR_ROMPE;
2734
2735 /* The shared function expects a packed array of only addresses. */
2736 mc_ptr = netdev->mc_list;
2737
2738 for (i = 0; i < netdev->mc_count; i++) {
2739 if (!mc_ptr)
2740 break;
2741 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2742 mc_ptr = mc_ptr->next;
746b9f02 2743 }
68d480c4
AD		 2744 igb_update_mc_addr_list(hw, mta_list, i);
2745 kfree(mta_list);
2746
2747 return netdev->mc_count;
2748}
2749
2750/**
2751 * igb_write_uc_addr_list - write unicast addresses to RAR table
2752 * @netdev: network interface device structure
2753 *
2754 * Writes unicast address list to the RAR table.
2755 * Returns: -ENOMEM on failure/insufficient address space
2756 * 0 on no addresses written
2757 * X on writing X addresses to the RAR table
2758 **/
2759static int igb_write_uc_addr_list(struct net_device *netdev)
2760{
2761 struct igb_adapter *adapter = netdev_priv(netdev);
2762 struct e1000_hw *hw = &adapter->hw;
2763 unsigned int vfn = adapter->vfs_allocated_count;
2764 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2765 int count = 0;
2766
2767 /* return ENOMEM indicating insufficient memory for addresses */
2768 if (netdev->uc.count > rar_entries)
2769 return -ENOMEM;
9d5c8243 2770
ff41f8dc
AD		 2771 if (netdev->uc.count && rar_entries) {
2772 struct netdev_hw_addr *ha;
2773 list_for_each_entry(ha, &netdev->uc.list, list) {
2774 if (!rar_entries)
2775 break;
26ad9178
AD		 2776 igb_rar_set_qsel(adapter, ha->addr,
2777 rar_entries--,
68d480c4
AD		 2778 vfn);
2779 count++;
ff41f8dc
AD		 2780 }
2781 }
2782 /* write the addresses in reverse order to avoid write combining */
2783 for (; rar_entries > 0 ; rar_entries--) {
2784 wr32(E1000_RAH(rar_entries), 0);
2785 wr32(E1000_RAL(rar_entries), 0);
2786 }
2787 wrfl();
2788
68d480c4
AD		 2789 return count;
2790}
2791
2792/**
2793 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2794 * @netdev: network interface device structure
2795 *
2796 * The set_rx_mode entry point is called whenever the unicast or multicast
2797 * address lists or the network interface flags are updated. This routine is
2798 * responsible for configuring the hardware for proper unicast, multicast,
2799 * promiscuous mode, and all-multi behavior.
2800 **/
2801static void igb_set_rx_mode(struct net_device *netdev)
2802{
2803 struct igb_adapter *adapter = netdev_priv(netdev);
2804 struct e1000_hw *hw = &adapter->hw;
2805 unsigned int vfn = adapter->vfs_allocated_count;
2806 u32 rctl, vmolr = 0;
2807 int count;
2808
2809 /* Check for Promiscuous and All Multicast modes */
2810 rctl = rd32(E1000_RCTL);
2811
2812 /* clear the effected bits */
2813 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2814
2815 if (netdev->flags & IFF_PROMISC) {
2816 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2817 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2818 } else {
2819 if (netdev->flags & IFF_ALLMULTI) {
2820 rctl |= E1000_RCTL_MPE;
2821 vmolr |= E1000_VMOLR_MPME;
2822 } else {
2823 /*
2824 * Write addresses to the MTA, if the attempt fails
2825 * then we should just turn on promiscous mode so
2826 * that we can at least receive multicast traffic
2827 */
2828 count = igb_write_mc_addr_list(netdev);
2829 if (count < 0) {
2830 rctl |= E1000_RCTL_MPE;
2831 vmolr |= E1000_VMOLR_MPME;
2832 } else if (count) {
2833 vmolr |= E1000_VMOLR_ROMPE;
2834 }
2835 }
2836 /*
2837 * Write addresses to available RAR registers, if there is not
2838 * sufficient space to store all the addresses then enable
2839 * unicast promiscous mode
2840 */
2841 count = igb_write_uc_addr_list(netdev);
2842 if (count < 0) {
2843 rctl |= E1000_RCTL_UPE;
2844 vmolr |= E1000_VMOLR_ROPE;
2845 }
2846 rctl |= E1000_RCTL_VFE;
28fc06f5 2847 }
68d480c4 2848 wr32(E1000_RCTL, rctl);
28fc06f5 2849
68d480c4
AD		 2850 /*
2851 * In order to support SR-IOV and eventually VMDq it is necessary to set
2852 * the VMOLR to enable the appropriate modes. Without this workaround
2853 * we will have issues with VLAN tag stripping not being done for frames
2854 * that are only arriving because we are the default pool
2855 */
2856 if (hw->mac.type < e1000_82576)
28fc06f5 2857 return;
9d5c8243 2858
68d480c4
AD		 2859 vmolr |= rd32(E1000_VMOLR(vfn)) &
2860 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2861 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2862 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2863}
2864
2865/* Need to wait a few seconds after link up to get diagnostic information from
2866 * the phy */
2867static void igb_update_phy_info(unsigned long data)
2868{
2869 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2870 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2871}
2872
4d6b725e
AD		 2873/**
2874 * igb_has_link - check shared code for link and determine up/down
2875 * @adapter: pointer to driver private info
2876 **/
2877static bool igb_has_link(struct igb_adapter *adapter)
2878{
2879 struct e1000_hw *hw = &adapter->hw;
2880 bool link_active = false;
2881 s32 ret_val = 0;
2882
2883 /* get_link_status is set on LSC (link status) interrupt or
2884 * rx sequence error interrupt. get_link_status will stay
2885 * false until the e1000_check_for_link establishes link
2886 * for copper adapters ONLY
2887 */
2888 switch (hw->phy.media_type) {
2889 case e1000_media_type_copper:
2890 if (hw->mac.get_link_status) {
2891 ret_val = hw->mac.ops.check_for_link(hw);
2892 link_active = !hw->mac.get_link_status;
2893 } else {
2894 link_active = true;
2895 }
2896 break;
4d6b725e
AD		 2897 case e1000_media_type_internal_serdes:
2898 ret_val = hw->mac.ops.check_for_link(hw);
2899 link_active = hw->mac.serdes_has_link;
2900 break;
2901 default:
2902 case e1000_media_type_unknown:
2903 break;
2904 }
2905
2906 return link_active;
2907}
2908
9d5c8243
AK		 2909/**
2910 * igb_watchdog - Timer Call-back
2911 * @data: pointer to adapter cast into an unsigned long
2912 **/
2913static void igb_watchdog(unsigned long data)
2914{
2915 struct igb_adapter *adapter = (struct igb_adapter *)data;
2916 /* Do the rest outside of interrupt context */
2917 schedule_work(&adapter->watchdog_task);
2918}
2919
2920static void igb_watchdog_task(struct work_struct *work)
2921{
2922 struct igb_adapter *adapter = container_of(work,
2923 struct igb_adapter, watchdog_task);
2924 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2925 struct net_device *netdev = adapter->netdev;
2926 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2927 u32 link;
7a6ea550 2928 int i;
9d5c8243 2929
4d6b725e
AD		 2930 link = igb_has_link(adapter);
2931 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2932 goto link_up;
2933
9d5c8243
AK		 2934 if (link) {
2935 if (!netif_carrier_ok(netdev)) {
2936 u32 ctrl;
2937 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2938 &adapter->link_speed,
2939 &adapter->link_duplex);
2940
2941 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2942 /* Links status message must follow this format */
2943 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2944 "Flow Control: %s\n",
527d47c1 2945 netdev->name,
9d5c8243
AK		 2946 adapter->link_speed,
2947 adapter->link_duplex == FULL_DUPLEX ?
2948 "Full Duplex" : "Half Duplex",
2949 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2950 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2951 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2952 E1000_CTRL_TFCE) ? "TX" : "None")));
2953
2954 /* tweak tx_queue_len according to speed/duplex and
2955 * adjust the timeout factor */
2956 netdev->tx_queue_len = adapter->tx_queue_len;
2957 adapter->tx_timeout_factor = 1;
2958 switch (adapter->link_speed) {
2959 case SPEED_10:
2960 netdev->tx_queue_len = 10;
2961 adapter->tx_timeout_factor = 14;
2962 break;
2963 case SPEED_100:
2964 netdev->tx_queue_len = 100;
2965 /* maybe add some timeout factor ? */
2966 break;
2967 }
2968
2969 netif_carrier_on(netdev);
9d5c8243 2970
4ae196df
AD		 2971 igb_ping_all_vfs(adapter);
2972
4b1a9877 2973 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2974 if (!test_bit(__IGB_DOWN, &adapter->state))
2975 mod_timer(&adapter->phy_info_timer,
2976 round_jiffies(jiffies + 2 * HZ));
2977 }
2978 } else {
2979 if (netif_carrier_ok(netdev)) {
2980 adapter->link_speed = 0;
2981 adapter->link_duplex = 0;
527d47c1
AD		 2982 /* Links status message must follow this format */
2983 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2984 netdev->name);
9d5c8243 2985 netif_carrier_off(netdev);
4b1a9877 2986
4ae196df
AD		 2987 igb_ping_all_vfs(adapter);
2988
4b1a9877 2989 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2990 if (!test_bit(__IGB_DOWN, &adapter->state))
2991 mod_timer(&adapter->phy_info_timer,
2992 round_jiffies(jiffies + 2 * HZ));
2993 }
2994 }
2995
2996link_up:
2997 igb_update_stats(adapter);
2998
4b1a9877 2999 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 3000 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 3001 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 3002 adapter->colc_old = adapter->stats.colc;
3003
3004 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
3005 adapter->gorc_old = adapter->stats.gorc;
3006 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
3007 adapter->gotc_old = adapter->stats.gotc;
3008
3009 igb_update_adaptive(&adapter->hw);
3010
3011 if (!netif_carrier_ok(netdev)) {
c493ea45 3012 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 3013 /* We've lost link, so the controller stops DMA,
3014 * but we've got queued Tx work that's never going
3015 * to get done, so reset controller to flush Tx.
3016 * (Do the reset outside of interrupt context). */
3017 adapter->tx_timeout_count++;
3018 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 3019 /* return immediately since reset is imminent */
3020 return;
9d5c8243
AK		 3021 }
3022 }
3023
3024 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3025 if (adapter->msix_entries) {
047e0030
AD		 3026 u32 eics = 0;
3027 for (i = 0; i < adapter->num_q_vectors; i++) {
3028 struct igb_q_vector *q_vector = adapter->q_vector[i];
3029 eics |= q_vector->eims_value;
3030 }
7a6ea550
AD		 3031 wr32(E1000_EICS, eics);
3032 } else {
3033 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3034 }
9d5c8243
AK		 3035
3036 /* Force detection of hung controller every watchdog period */
3037 tx_ring->detect_tx_hung = true;
3038
3039 /* Reset the timer */
3040 if (!test_bit(__IGB_DOWN, &adapter->state))
3041 mod_timer(&adapter->watchdog_timer,
3042 round_jiffies(jiffies + 2 * HZ));
3043}
3044
3045enum latency_range {
3046 lowest_latency = 0,
3047 low_latency = 1,
3048 bulk_latency = 2,
3049 latency_invalid = 255
3050};
3051
3052
6eb5a7f1
AD		 3053/**
3054 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3055 *
3056 * Stores a new ITR value based on strictly on packet size. This
3057 * algorithm is less sophisticated than that used in igb_update_itr,
3058 * due to the difficulty of synchronizing statistics across multiple
3059 * receive rings. The divisors and thresholds used by this fuction
3060 * were determined based on theoretical maximum wire speed and testing
3061 * data, in order to minimize response time while increasing bulk
3062 * throughput.
3063 * This functionality is controlled by the InterruptThrottleRate module
3064 * parameter (see igb_param.c)
3065 * NOTE: This function is called only when operating in a multiqueue
3066 * receive environment.
047e0030 3067 * @q_vector: pointer to q_vector
6eb5a7f1 3068 **/
047e0030 3069static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3070{
047e0030 3071 int new_val = q_vector->itr_val;
6eb5a7f1 3072 int avg_wire_size = 0;
047e0030 3073 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3074
6eb5a7f1
AD		 3075 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3076 * ints/sec - ITR timer value of 120 ticks.
3077 */
3078 if (adapter->link_speed != SPEED_1000) {
047e0030 3079 new_val = 976;
6eb5a7f1 3080 goto set_itr_val;
9d5c8243 3081 }
047e0030
AD		 3082
3083 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3084 struct igb_ring *ring = q_vector->rx_ring;
3085 avg_wire_size = ring->total_bytes / ring->total_packets;
3086 }
3087
3088 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3089 struct igb_ring *ring = q_vector->tx_ring;
3090 avg_wire_size = max_t(u32, avg_wire_size,
3091 (ring->total_bytes /
3092 ring->total_packets));
3093 }
3094
3095 /* if avg_wire_size isn't set no work was done */
3096 if (!avg_wire_size)
3097 goto clear_counts;
9d5c8243 3098
6eb5a7f1
AD		 3099 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3100 avg_wire_size += 24;
3101
3102 /* Don't starve jumbo frames */
3103 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3104
6eb5a7f1
AD		 3105 /* Give a little boost to mid-size frames */
3106 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3107 new_val = avg_wire_size / 3;
3108 else
3109 new_val = avg_wire_size / 2;
9d5c8243 3110
6eb5a7f1 3111set_itr_val:
047e0030
AD		 3112 if (new_val != q_vector->itr_val) {
3113 q_vector->itr_val = new_val;
3114 q_vector->set_itr = 1;
9d5c8243 3115 }
6eb5a7f1 3116clear_counts:
047e0030
AD		 3117 if (q_vector->rx_ring) {
3118 q_vector->rx_ring->total_bytes = 0;
3119 q_vector->rx_ring->total_packets = 0;
3120 }
3121 if (q_vector->tx_ring) {
3122 q_vector->tx_ring->total_bytes = 0;
3123 q_vector->tx_ring->total_packets = 0;
3124 }
9d5c8243
AK		 3125}
3126
3127/**
3128 * igb_update_itr - update the dynamic ITR value based on statistics
3129 * Stores a new ITR value based on packets and byte
3130 * counts during the last interrupt. The advantage of per interrupt
3131 * computation is faster updates and more accurate ITR for the current
3132 * traffic pattern. Constants in this function were computed
3133 * based on theoretical maximum wire speed and thresholds were set based
3134 * on testing data as well as attempting to minimize response time
3135 * while increasing bulk throughput.
3136 * this functionality is controlled by the InterruptThrottleRate module
3137 * parameter (see igb_param.c)
3138 * NOTE: These calculations are only valid when operating in a single-
3139 * queue environment.
3140 * @adapter: pointer to adapter
047e0030 3141 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3142 * @packets: the number of packets during this measurement interval
3143 * @bytes: the number of bytes during this measurement interval
3144 **/
3145static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3146 int packets, int bytes)
3147{
3148 unsigned int retval = itr_setting;
3149
3150 if (packets == 0)
3151 goto update_itr_done;
3152
3153 switch (itr_setting) {
3154 case lowest_latency:
3155 /* handle TSO and jumbo frames */
3156 if (bytes/packets > 8000)
3157 retval = bulk_latency;
3158 else if ((packets < 5) && (bytes > 512))
3159 retval = low_latency;
3160 break;
3161 case low_latency: /* 50 usec aka 20000 ints/s */
3162 if (bytes > 10000) {
3163 /* this if handles the TSO accounting */
3164 if (bytes/packets > 8000) {
3165 retval = bulk_latency;
3166 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3167 retval = bulk_latency;
3168 } else if ((packets > 35)) {
3169 retval = lowest_latency;
3170 }
3171 } else if (bytes/packets > 2000) {
3172 retval = bulk_latency;
3173 } else if (packets <= 2 && bytes < 512) {
3174 retval = lowest_latency;
3175 }
3176 break;
3177 case bulk_latency: /* 250 usec aka 4000 ints/s */
3178 if (bytes > 25000) {
3179 if (packets > 35)
3180 retval = low_latency;
1e5c3d21 3181 } else if (bytes < 1500) {
9d5c8243
AK		 3182 retval = low_latency;
3183 }
3184 break;
3185 }
3186
3187update_itr_done:
3188 return retval;
3189}
3190
6eb5a7f1 3191static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3192{
047e0030 3193 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3194 u16 current_itr;
047e0030 3195 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3196
3197 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3198 if (adapter->link_speed != SPEED_1000) {
3199 current_itr = 0;
3200 new_itr = 4000;
3201 goto set_itr_now;
3202 }
3203
3204 adapter->rx_itr = igb_update_itr(adapter,
3205 adapter->rx_itr,
3206 adapter->rx_ring->total_packets,
3207 adapter->rx_ring->total_bytes);
9d5c8243 3208
047e0030
AD		 3209 adapter->tx_itr = igb_update_itr(adapter,
3210 adapter->tx_itr,
3211 adapter->tx_ring->total_packets,
3212 adapter->tx_ring->total_bytes);
3213 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3214
6eb5a7f1 3215 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 3216 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3217 current_itr = low_latency;
3218
9d5c8243
AK		 3219 switch (current_itr) {
3220 /* counts and packets in update_itr are dependent on these numbers */
3221 case lowest_latency:
78b1f607 3222 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3223 break;
3224 case low_latency:
78b1f607 3225 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3226 break;
3227 case bulk_latency:
78b1f607 3228 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3229 break;
3230 default:
3231 break;
3232 }
3233
3234set_itr_now:
6eb5a7f1
AD		 3235 adapter->rx_ring->total_bytes = 0;
3236 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3237 adapter->tx_ring->total_bytes = 0;
3238 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3239
047e0030 3240 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3241 /* this attempts to bias the interrupt rate towards Bulk
3242 * by adding intermediate steps when interrupt rate is
3243 * increasing */
047e0030
AD		 3244 new_itr = new_itr > q_vector->itr_val ?
3245 max((new_itr * q_vector->itr_val) /
3246 (new_itr + (q_vector->itr_val >> 2)),
3247 new_itr) :
9d5c8243
AK		 3248 new_itr;
3249 /* Don't write the value here; it resets the adapter's
3250 * internal timer, and causes us to delay far longer than
3251 * we should between interrupts. Instead, we write the ITR
3252 * value at the beginning of the next interrupt so the timing
3253 * ends up being correct.
3254 */
047e0030
AD		 3255 q_vector->itr_val = new_itr;
3256 q_vector->set_itr = 1;
9d5c8243
AK		 3257 }
3258
3259 return;
3260}
3261
9d5c8243
AK		 3262#define IGB_TX_FLAGS_CSUM 0x00000001
3263#define IGB_TX_FLAGS_VLAN 0x00000002
3264#define IGB_TX_FLAGS_TSO 0x00000004
3265#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3266#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3267#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3268#define IGB_TX_FLAGS_VLAN_SHIFT 16
3269
85ad76b2 3270static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3271 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3272{
3273 struct e1000_adv_tx_context_desc *context_desc;
3274 unsigned int i;
3275 int err;
3276 struct igb_buffer *buffer_info;
3277 u32 info = 0, tu_cmd = 0;
3278 u32 mss_l4len_idx, l4len;
3279 *hdr_len = 0;
3280
3281 if (skb_header_cloned(skb)) {
3282 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3283 if (err)
3284 return err;
3285 }
3286
3287 l4len = tcp_hdrlen(skb);
3288 *hdr_len += l4len;
3289
3290 if (skb->protocol == htons(ETH_P_IP)) {
3291 struct iphdr *iph = ip_hdr(skb);
3292 iph->tot_len = 0;
3293 iph->check = 0;
3294 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3295 iph->daddr, 0,
3296 IPPROTO_TCP,
3297 0);
3298 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3299 ipv6_hdr(skb)->payload_len = 0;
3300 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3301 &ipv6_hdr(skb)->daddr,
3302 0, IPPROTO_TCP, 0);
3303 }
3304
3305 i = tx_ring->next_to_use;
3306
3307 buffer_info = &tx_ring->buffer_info[i];
3308 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3309 /* VLAN MACLEN IPLEN */
3310 if (tx_flags & IGB_TX_FLAGS_VLAN)
3311 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3312 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3313 *hdr_len += skb_network_offset(skb);
3314 info |= skb_network_header_len(skb);
3315 *hdr_len += skb_network_header_len(skb);
3316 context_desc->vlan_macip_lens = cpu_to_le32(info);
3317
3318 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3319 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3320
3321 if (skb->protocol == htons(ETH_P_IP))
3322 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3323 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3324
3325 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3326
3327 /* MSS L4LEN IDX */
3328 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3329 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3330
73cd78f1 3331 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3332 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3333 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3334
3335 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3336 context_desc->seqnum_seed = 0;
3337
3338 buffer_info->time_stamp = jiffies;
0e014cb1 3339 buffer_info->next_to_watch = i;
9d5c8243
AK		 3340 buffer_info->dma = 0;
3341 i++;
3342 if (i == tx_ring->count)
3343 i = 0;
3344
3345 tx_ring->next_to_use = i;
3346
3347 return true;
3348}
3349
85ad76b2
AD		 3350static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3351 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3352{
3353 struct e1000_adv_tx_context_desc *context_desc;
80785298 3354 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3355 struct igb_buffer *buffer_info;
3356 u32 info = 0, tu_cmd = 0;
80785298 3357 unsigned int i;
9d5c8243
AK		 3358
3359 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3360 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3361 i = tx_ring->next_to_use;
3362 buffer_info = &tx_ring->buffer_info[i];
3363 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3364
3365 if (tx_flags & IGB_TX_FLAGS_VLAN)
3366 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3367 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3368 if (skb->ip_summed == CHECKSUM_PARTIAL)
3369 info |= skb_network_header_len(skb);
3370
3371 context_desc->vlan_macip_lens = cpu_to_le32(info);
3372
3373 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3374
3375 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3376 __be16 protocol;
3377
3378 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3379 const struct vlan_ethhdr *vhdr =
3380 (const struct vlan_ethhdr*)skb->data;
3381
3382 protocol = vhdr->h_vlan_encapsulated_proto;
3383 } else {
3384 protocol = skb->protocol;
3385 }
3386
3387 switch (protocol) {
09640e63 3388 case cpu_to_be16(ETH_P_IP):
9d5c8243 3389 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3390 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3391 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3392 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3393 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3394 break;
09640e63 3395 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3396 /* XXX what about other V6 headers?? */
3397 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3398 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3399 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3400 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3401 break;
3402 default:
3403 if (unlikely(net_ratelimit()))
80785298 3404 dev_warn(&pdev->dev,
44b0cda3
MW		 3405 "partial checksum but proto=%x!\n",
3406 skb->protocol);
3407 break;
3408 }
9d5c8243
AK		 3409 }
3410
3411 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3412 context_desc->seqnum_seed = 0;
85ad76b2 3413 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3414 context_desc->mss_l4len_idx =
85ad76b2 3415 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3416
3417 buffer_info->time_stamp = jiffies;
0e014cb1 3418 buffer_info->next_to_watch = i;
9d5c8243
AK		 3419 buffer_info->dma = 0;
3420
3421 i++;
3422 if (i == tx_ring->count)
3423 i = 0;
3424 tx_ring->next_to_use = i;
3425
3426 return true;
3427 }
9d5c8243
AK		 3428 return false;
3429}
3430
3431#define IGB_MAX_TXD_PWR 16
3432#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3433
80785298 3434static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3435 unsigned int first)
9d5c8243
AK		 3436{
3437 struct igb_buffer *buffer_info;
80785298 3438 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3439 unsigned int len = skb_headlen(skb);
3440 unsigned int count = 0, i;
3441 unsigned int f;
65689fef 3442 dma_addr_t *map;
9d5c8243
AK		 3443
3444 i = tx_ring->next_to_use;
3445
80785298
AD		 3446 if (skb_dma_map(&pdev->dev, skb, DMA_TO_DEVICE)) {
3447 dev_err(&pdev->dev, "TX DMA map failed\n");
65689fef
AD		 3448 return 0;
3449 }
3450
3451 map = skb_shinfo(skb)->dma_maps;
3452
9d5c8243
AK		 3453 buffer_info = &tx_ring->buffer_info[i];
3454 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3455 buffer_info->length = len;
3456 /* set time_stamp *before* dma to help avoid a possible race */
3457 buffer_info->time_stamp = jiffies;
0e014cb1 3458 buffer_info->next_to_watch = i;
042a53a9 3459 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3460
3461 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3462 struct skb_frag_struct *frag;
3463
65689fef
AD		 3464 i++;
3465 if (i == tx_ring->count)
3466 i = 0;
3467
9d5c8243
AK		 3468 frag = &skb_shinfo(skb)->frags[f];
3469 len = frag->size;
3470
3471 buffer_info = &tx_ring->buffer_info[i];
3472 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3473 buffer_info->length = len;
3474 buffer_info->time_stamp = jiffies;
0e014cb1 3475 buffer_info->next_to_watch = i;
65689fef 3476 buffer_info->dma = map[count];
9d5c8243 3477 count++;
9d5c8243
AK		 3478 }
3479
9d5c8243 3480 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3481 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3482
042a53a9 3483 return count + 1;
9d5c8243
AK		 3484}
3485
85ad76b2 3486static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3487 int tx_flags, int count, u32 paylen,
3488 u8 hdr_len)
3489{
3490 union e1000_adv_tx_desc *tx_desc = NULL;
3491 struct igb_buffer *buffer_info;
3492 u32 olinfo_status = 0, cmd_type_len;
3493 unsigned int i;
3494
3495 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3496 E1000_ADVTXD_DCMD_DEXT);
3497
3498 if (tx_flags & IGB_TX_FLAGS_VLAN)
3499 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3500
33af6bcc
PO		 3501 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3502 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3503
9d5c8243
AK		 3504 if (tx_flags & IGB_TX_FLAGS_TSO) {
3505 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3506
3507 /* insert tcp checksum */
3508 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3509
3510 /* insert ip checksum */
3511 if (tx_flags & IGB_TX_FLAGS_IPV4)
3512 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3513
3514 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3515 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3516 }
3517
85ad76b2
AD		 3518 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3519 (tx_flags & (IGB_TX_FLAGS_CSUM |
3520 IGB_TX_FLAGS_TSO |
7dfc16fa 3521 IGB_TX_FLAGS_VLAN)))
85ad76b2 3522 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3523
3524 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3525
3526 i = tx_ring->next_to_use;
3527 while (count--) {
3528 buffer_info = &tx_ring->buffer_info[i];
3529 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3530 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3531 tx_desc->read.cmd_type_len =
3532 cpu_to_le32(cmd_type_len | buffer_info->length);
3533 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3534 i++;
3535 if (i == tx_ring->count)
3536 i = 0;
3537 }
3538
85ad76b2 3539 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 3540 /* Force memory writes to complete before letting h/w
3541 * know there are new descriptors to fetch. (Only
3542 * applicable for weak-ordered memory model archs,
3543 * such as IA-64). */
3544 wmb();
3545
3546 tx_ring->next_to_use = i;
fce99e34 3547 writel(i, tx_ring->tail);
9d5c8243
AK		 3548 /* we need this if more than one processor can write to our tail
3549 * at a time, it syncronizes IO on IA64/Altix systems */
3550 mmiowb();
3551}
3552
3553static int __igb_maybe_stop_tx(struct net_device *netdev,
3554 struct igb_ring *tx_ring, int size)
3555{
661086df 3556 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3557
9d5c8243
AK		 3558 /* Herbert's original patch had:
3559 * smp_mb__after_netif_stop_queue();
3560 * but since that doesn't exist yet, just open code it. */
3561 smp_mb();
3562
3563 /* We need to check again in a case another CPU has just
3564 * made room available. */
c493ea45 3565 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3566 return -EBUSY;
3567
3568 /* A reprieve! */
661086df 3569 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 3570 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 3571 return 0;
3572}
3573
3574static int igb_maybe_stop_tx(struct net_device *netdev,
3575 struct igb_ring *tx_ring, int size)
3576{
c493ea45 3577 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3578 return 0;
3579 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3580}
3581
3b29a56d
SH		 3582static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3583 struct net_device *netdev,
3584 struct igb_ring *tx_ring)
9d5c8243
AK		 3585{
3586 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3587 unsigned int first;
9d5c8243 3588 unsigned int tx_flags = 0;
9d5c8243 3589 u8 hdr_len = 0;
65689fef 3590 int count = 0;
9d5c8243 3591 int tso = 0;
33af6bcc 3592 union skb_shared_tx *shtx;
9d5c8243 3593
9d5c8243
AK		 3594 if (test_bit(__IGB_DOWN, &adapter->state)) {
3595 dev_kfree_skb_any(skb);
3596 return NETDEV_TX_OK;
3597 }
3598
3599 if (skb->len <= 0) {
3600 dev_kfree_skb_any(skb);
3601 return NETDEV_TX_OK;
3602 }
3603
9d5c8243
AK		 3604 /* need: 1 descriptor per page,
3605 * + 2 desc gap to keep tail from touching head,
3606 * + 1 desc for skb->data,
3607 * + 1 desc for context descriptor,
3608 * otherwise try next time */
3609 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3610 /* this is a hard error */
9d5c8243
AK		 3611 return NETDEV_TX_BUSY;
3612 }
33af6bcc
PO		 3613
3614 /*
3615 * TODO: check that there currently is no other packet with
3616 * time stamping in the queue
3617 *
3618 * When doing time stamping, keep the connection to the socket
3619 * a while longer: it is still needed by skb_hwtstamp_tx(),
3620 * called either in igb_tx_hwtstamp() or by our caller when
3621 * doing software time stamping.
3622 */
3623 shtx = skb_tx(skb);
3624 if (unlikely(shtx->hardware)) {
3625 shtx->in_progress = 1;
3626 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3627 }
9d5c8243
AK		 3628
3629 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3630 tx_flags |= IGB_TX_FLAGS_VLAN;
3631 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3632 }
3633
661086df
PWJ		 3634 if (skb->protocol == htons(ETH_P_IP))
3635 tx_flags |= IGB_TX_FLAGS_IPV4;
3636
0e014cb1 3637 first = tx_ring->next_to_use;
85ad76b2
AD		 3638 if (skb_is_gso(skb)) {
3639 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
3640 if (tso < 0) {
3641 dev_kfree_skb_any(skb);
3642 return NETDEV_TX_OK;
3643 }
9d5c8243
AK		 3644 }
3645
3646 if (tso)
3647 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 3648 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 3649 (skb->ip_summed == CHECKSUM_PARTIAL))
3650 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3651
65689fef
AD		 3652 /*
3653 * count reflects descriptors mapped, if 0 then mapping error
3654 * has occured and we need to rewind the descriptor queue
3655 */
80785298 3656 count = igb_tx_map_adv(tx_ring, skb, first);
65689fef 3657
85ad76b2 3658 if (!count) {
65689fef
AD		 3659 dev_kfree_skb_any(skb);
3660 tx_ring->buffer_info[first].time_stamp = 0;
3661 tx_ring->next_to_use = first;
85ad76b2 3662 return NETDEV_TX_OK;
65689fef 3663 }
9d5c8243 3664
85ad76b2
AD		 3665 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3666
3667 /* Make sure there is space in the ring for the next send. */
3668 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3669
9d5c8243
AK		 3670 return NETDEV_TX_OK;
3671}
3672
3b29a56d
SH		 3673static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3674 struct net_device *netdev)
9d5c8243
AK		 3675{
3676 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3677 struct igb_ring *tx_ring;
3678
661086df 3679 int r_idx = 0;
1bfaf07b 3680 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3681 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3682
3683 /* This goes back to the question of how to logically map a tx queue
3684 * to a flow. Right now, performance is impacted slightly negatively
3685 * if using multiple tx queues. If the stack breaks away from a
3686 * single qdisc implementation, we can look at this again. */
3b29a56d 3687 return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
9d5c8243
AK		 3688}
3689
3690/**
3691 * igb_tx_timeout - Respond to a Tx Hang
3692 * @netdev: network interface device structure
3693 **/
3694static void igb_tx_timeout(struct net_device *netdev)
3695{
3696 struct igb_adapter *adapter = netdev_priv(netdev);
3697 struct e1000_hw *hw = &adapter->hw;
3698
3699 /* Do the reset outside of interrupt context */
3700 adapter->tx_timeout_count++;
3701 schedule_work(&adapter->reset_task);
265de409
AD		 3702 wr32(E1000_EICS,
3703 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3704}
3705
3706static void igb_reset_task(struct work_struct *work)
3707{
3708 struct igb_adapter *adapter;
3709 adapter = container_of(work, struct igb_adapter, reset_task);
3710
3711 igb_reinit_locked(adapter);
3712}
3713
3714/**
3715 * igb_get_stats - Get System Network Statistics
3716 * @netdev: network interface device structure
3717 *
3718 * Returns the address of the device statistics structure.
3719 * The statistics are actually updated from the timer callback.
3720 **/
73cd78f1 3721static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3722{
9d5c8243 3723 /* only return the current stats */
8d24e933 3724 return &netdev->stats;
9d5c8243
AK		 3725}
3726
3727/**
3728 * igb_change_mtu - Change the Maximum Transfer Unit
3729 * @netdev: network interface device structure
3730 * @new_mtu: new value for maximum frame size
3731 *
3732 * Returns 0 on success, negative on failure
3733 **/
3734static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3735{
3736 struct igb_adapter *adapter = netdev_priv(netdev);
3737 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 3738 u32 rx_buffer_len, i;
9d5c8243
AK		 3739
3740 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3741 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3742 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3743 return -EINVAL;
3744 }
3745
9d5c8243
AK		 3746 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3747 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3748 return -EINVAL;
3749 }
3750
3751 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3752 msleep(1);
73cd78f1 3753
9d5c8243
AK		 3754 /* igb_down has a dependency on max_frame_size */
3755 adapter->max_frame_size = max_frame;
9d5c8243
AK		 3756 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3757 * means we reserve 2 more, this pushes us to allocate from the next
3758 * larger slab size.
3759 * i.e. RXBUFFER_2048 --> size-4096 slab
3760 */
3761
7d95b717 3762 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 3763 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3764 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 3765 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 3766 else
4c844851
AD		 3767 rx_buffer_len = IGB_RXBUFFER_128;
3768
3769 if (netif_running(netdev))
3770 igb_down(adapter);
9d5c8243
AK		 3771
3772 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3773 netdev->mtu, new_mtu);
3774 netdev->mtu = new_mtu;
3775
4c844851
AD		 3776 for (i = 0; i < adapter->num_rx_queues; i++)
3777 adapter->rx_ring[i].rx_buffer_len = rx_buffer_len;
3778
9d5c8243
AK		 3779 if (netif_running(netdev))
3780 igb_up(adapter);
3781 else
3782 igb_reset(adapter);
3783
3784 clear_bit(__IGB_RESETTING, &adapter->state);
3785
3786 return 0;
3787}
3788
3789/**
3790 * igb_update_stats - Update the board statistics counters
3791 * @adapter: board private structure
3792 **/
3793
3794void igb_update_stats(struct igb_adapter *adapter)
3795{
8d24e933 3796 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3797 struct e1000_hw *hw = &adapter->hw;
3798 struct pci_dev *pdev = adapter->pdev;
3799 u16 phy_tmp;
3800
3801#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3802
3803 /*
3804 * Prevent stats update while adapter is being reset, or if the pci
3805 * connection is down.
3806 */
3807 if (adapter->link_speed == 0)
3808 return;
3809 if (pci_channel_offline(pdev))
3810 return;
3811
3812 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3813 adapter->stats.gprc += rd32(E1000_GPRC);
3814 adapter->stats.gorc += rd32(E1000_GORCL);
3815 rd32(E1000_GORCH); /* clear GORCL */
3816 adapter->stats.bprc += rd32(E1000_BPRC);
3817 adapter->stats.mprc += rd32(E1000_MPRC);
3818 adapter->stats.roc += rd32(E1000_ROC);
3819
3820 adapter->stats.prc64 += rd32(E1000_PRC64);
3821 adapter->stats.prc127 += rd32(E1000_PRC127);
3822 adapter->stats.prc255 += rd32(E1000_PRC255);
3823 adapter->stats.prc511 += rd32(E1000_PRC511);
3824 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3825 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3826 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3827 adapter->stats.sec += rd32(E1000_SEC);
3828
3829 adapter->stats.mpc += rd32(E1000_MPC);
3830 adapter->stats.scc += rd32(E1000_SCC);
3831 adapter->stats.ecol += rd32(E1000_ECOL);
3832 adapter->stats.mcc += rd32(E1000_MCC);
3833 adapter->stats.latecol += rd32(E1000_LATECOL);
3834 adapter->stats.dc += rd32(E1000_DC);
3835 adapter->stats.rlec += rd32(E1000_RLEC);
3836 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3837 adapter->stats.xontxc += rd32(E1000_XONTXC);
3838 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3839 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3840 adapter->stats.fcruc += rd32(E1000_FCRUC);
3841 adapter->stats.gptc += rd32(E1000_GPTC);
3842 adapter->stats.gotc += rd32(E1000_GOTCL);
3843 rd32(E1000_GOTCH); /* clear GOTCL */
3844 adapter->stats.rnbc += rd32(E1000_RNBC);
3845 adapter->stats.ruc += rd32(E1000_RUC);
3846 adapter->stats.rfc += rd32(E1000_RFC);
3847 adapter->stats.rjc += rd32(E1000_RJC);
3848 adapter->stats.tor += rd32(E1000_TORH);
3849 adapter->stats.tot += rd32(E1000_TOTH);
3850 adapter->stats.tpr += rd32(E1000_TPR);
3851
3852 adapter->stats.ptc64 += rd32(E1000_PTC64);
3853 adapter->stats.ptc127 += rd32(E1000_PTC127);
3854 adapter->stats.ptc255 += rd32(E1000_PTC255);
3855 adapter->stats.ptc511 += rd32(E1000_PTC511);
3856 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3857 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3858
3859 adapter->stats.mptc += rd32(E1000_MPTC);
3860 adapter->stats.bptc += rd32(E1000_BPTC);
3861
3862 /* used for adaptive IFS */
3863
3864 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3865 adapter->stats.tpt += hw->mac.tx_packet_delta;
3866 hw->mac.collision_delta = rd32(E1000_COLC);
3867 adapter->stats.colc += hw->mac.collision_delta;
3868
3869 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3870 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3871 adapter->stats.tncrs += rd32(E1000_TNCRS);
3872 adapter->stats.tsctc += rd32(E1000_TSCTC);
3873 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3874
3875 adapter->stats.iac += rd32(E1000_IAC);
3876 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3877 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3878 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3879 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3880 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3881 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3882 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3883 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3884
3885 /* Fill out the OS statistics structure */
8d24e933
AK		 3886 netdev->stats.multicast = adapter->stats.mprc;
3887 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3888
3889 /* Rx Errors */
3890
8c0ab70a
JDB		 3891 if (hw->mac.type != e1000_82575) {
3892 u32 rqdpc_tmp;
3ea73afa 3893 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3894 int i;
3895 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3896 * Queue Drop Packet Count) stats only gets incremented, if
3897 * the DROP_EN but it set (in the SRRCTL register for that
3898 * queue). If DROP_EN bit is NOT set, then the some what
3899 * equivalent count is stored in RNBC (not per queue basis).
3900 * Also note the drop count is due to lack of available
3901 * descriptors.
3902 */
3903 for (i = 0; i < adapter->num_rx_queues; i++) {
3904 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3905 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3906 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3907 }
8d24e933 3908 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3909 }
3910
3ea73afa
JDB		 3911 /* Note RNBC (Receive No Buffers Count) is an not an exact
3912 * drop count as the hardware FIFO might save the day. Thats
3913 * one of the reason for saving it in rx_fifo_errors, as its
3914 * potentially not a true drop.
3915 */
8d24e933 3916 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3917
9d5c8243 3918 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3919 * our own version based on RUC and ROC */
8d24e933 3920 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3921 adapter->stats.crcerrs + adapter->stats.algnerrc +
3922 adapter->stats.ruc + adapter->stats.roc +
3923 adapter->stats.cexterr;
8d24e933 3924 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3925 adapter->stats.roc;
8d24e933
AK		 3926 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3927 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3928 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3929
3930 /* Tx Errors */
8d24e933 3931 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3932 adapter->stats.latecol;
8d24e933
AK		 3933 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3934 netdev->stats.tx_window_errors = adapter->stats.latecol;
3935 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3936
3937 /* Tx Dropped needs to be maintained elsewhere */
3938
3939 /* Phy Stats */
3940 if (hw->phy.media_type == e1000_media_type_copper) {
3941 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3942 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3943 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3944 adapter->phy_stats.idle_errors += phy_tmp;
3945 }
3946 }
3947
3948 /* Management Stats */
3949 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3950 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3951 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3952}
3953
9d5c8243
AK		 3954static irqreturn_t igb_msix_other(int irq, void *data)
3955{
047e0030 3956 struct igb_adapter *adapter = data;
9d5c8243 3957 struct e1000_hw *hw = &adapter->hw;
844290e5 3958 u32 icr = rd32(E1000_ICR);
844290e5 3959 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3960
047e0030 3961 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3962 /* HW is reporting DMA is out of sync */
3963 adapter->stats.doosync++;
3964 }
eebbbdba 3965
4ae196df
AD		 3966 /* Check for a mailbox event */
3967 if (icr & E1000_ICR_VMMB)
3968 igb_msg_task(adapter);
3969
3970 if (icr & E1000_ICR_LSC) {
3971 hw->mac.get_link_status = 1;
3972 /* guard against interrupt when we're going down */
3973 if (!test_bit(__IGB_DOWN, &adapter->state))
3974 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3975 }
3976
3977 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3978 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3979
3980 return IRQ_HANDLED;
3981}
3982
047e0030 3983static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 3984{
047e0030 3985 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 3986
047e0030
AD		 3987 if (!q_vector->set_itr)
3988 return;
73cd78f1 3989
047e0030
AD		 3990 if (!itr_val)
3991 itr_val = 0x4;
661086df 3992
047e0030
AD		 3993 if (q_vector->itr_shift)
3994 itr_val |= itr_val << q_vector->itr_shift;
661086df 3995 else
047e0030 3996 itr_val |= 0x8000000;
661086df 3997
047e0030
AD		 3998 writel(itr_val, q_vector->itr_register);
3999 q_vector->set_itr = 0;
6eb5a7f1
AD		 4000}
4001
047e0030 4002static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4003{
047e0030 4004 struct igb_q_vector *q_vector = data;
9d5c8243 4005
047e0030
AD		 4006 /* Write the ITR value calculated from the previous interrupt. */
4007 igb_write_itr(q_vector);
9d5c8243 4008
047e0030 4009 napi_schedule(&q_vector->napi);
844290e5 4010
047e0030 4011 return IRQ_HANDLED;
fe4506b6
JC		 4012}
4013
421e02f0 4014#ifdef CONFIG_IGB_DCA
047e0030 4015static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4016{
047e0030 4017 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4018 struct e1000_hw *hw = &adapter->hw;
4019 int cpu = get_cpu();
fe4506b6 4020
047e0030
AD		 4021 if (q_vector->cpu == cpu)
4022 goto out_no_update;
4023
4024 if (q_vector->tx_ring) {
4025 int q = q_vector->tx_ring->reg_idx;
4026 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4027 if (hw->mac.type == e1000_82575) {
4028 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4029 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4030 } else {
047e0030
AD		 4031 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4032 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4033 E1000_DCA_TXCTRL_CPUID_SHIFT;
4034 }
4035 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4036 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4037 }
4038 if (q_vector->rx_ring) {
4039 int q = q_vector->rx_ring->reg_idx;
4040 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4041 if (hw->mac.type == e1000_82575) {
2d064c06 4042 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4043 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4044 } else {
4045 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4046 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4047 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4048 }
fe4506b6
JC		 4049 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4050 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4051 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4052 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4053 }
047e0030
AD		 4054 q_vector->cpu = cpu;
4055out_no_update:
fe4506b6
JC		 4056 put_cpu();
4057}
4058
4059static void igb_setup_dca(struct igb_adapter *adapter)
4060{
7e0e99ef 4061 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4062 int i;
4063
7dfc16fa 4064 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4065 return;
4066
7e0e99ef
AD		 4067 /* Always use CB2 mode, difference is masked in the CB driver. */
4068 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4069
047e0030
AD		 4070 for (i = 0; i < adapter->num_q_vectors; i++) {
4071 struct igb_q_vector *q_vector = adapter->q_vector[i];
4072 q_vector->cpu = -1;
4073 igb_update_dca(q_vector);
fe4506b6
JC		 4074 }
4075}
4076
4077static int __igb_notify_dca(struct device *dev, void *data)
4078{
4079 struct net_device *netdev = dev_get_drvdata(dev);
4080 struct igb_adapter *adapter = netdev_priv(netdev);
4081 struct e1000_hw *hw = &adapter->hw;
4082 unsigned long event = *(unsigned long *)data;
4083
4084 switch (event) {
4085 case DCA_PROVIDER_ADD:
4086 /* if already enabled, don't do it again */
7dfc16fa 4087 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4088 break;
fe4506b6
JC		 4089 /* Always use CB2 mode, difference is masked
4090 * in the CB driver. */
cbd347ad 4091 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4092 if (dca_add_requester(dev) == 0) {
bbd98fe4 4093 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4094 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4095 igb_setup_dca(adapter);
4096 break;
4097 }
4098 /* Fall Through since DCA is disabled. */
4099 case DCA_PROVIDER_REMOVE:
7dfc16fa 4100 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4101 /* without this a class_device is left
047e0030 4102 * hanging around in the sysfs model */
fe4506b6
JC		 4103 dca_remove_requester(dev);
4104 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4105 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4106 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4107 }
4108 break;
4109 }
bbd98fe4 4110
fe4506b6 4111 return 0;
9d5c8243
AK		 4112}
4113
fe4506b6
JC		 4114static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4115 void *p)
4116{
4117 int ret_val;
4118
4119 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4120 __igb_notify_dca);
4121
4122 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4123}
421e02f0 4124#endif /* CONFIG_IGB_DCA */
9d5c8243 4125
4ae196df
AD		 4126static void igb_ping_all_vfs(struct igb_adapter *adapter)
4127{
4128 struct e1000_hw *hw = &adapter->hw;
4129 u32 ping;
4130 int i;
4131
4132 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4133 ping = E1000_PF_CONTROL_MSG;
4134 if (adapter->vf_data[i].clear_to_send)
4135 ping |= E1000_VT_MSGTYPE_CTS;
4136 igb_write_mbx(hw, &ping, 1, i);
4137 }
4138}
4139
4140static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4141 u32 *msgbuf, u32 vf)
4142{
4143 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4144 u16 *hash_list = (u16 *)&msgbuf[1];
4145 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4146 int i;
4147
4148 /* only up to 30 hash values supported */
4149 if (n > 30)
4150 n = 30;
4151
4152 /* salt away the number of multi cast addresses assigned
4153 * to this VF for later use to restore when the PF multi cast
4154 * list changes
4155 */
4156 vf_data->num_vf_mc_hashes = n;
4157
4158 /* VFs are limited to using the MTA hash table for their multicast
4159 * addresses */
4160 for (i = 0; i < n; i++)
a419aef8 4161 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4162
4163 /* Flush and reset the mta with the new values */
ff41f8dc 4164 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4165
4166 return 0;
4167}
4168
4169static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4170{
4171 struct e1000_hw *hw = &adapter->hw;
4172 struct vf_data_storage *vf_data;
4173 int i, j;
4174
4175 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4176 vf_data = &adapter->vf_data[i];
75f4f382 4177 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 4178 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4179 }
4180}
4181
4182static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4183{
4184 struct e1000_hw *hw = &adapter->hw;
4185 u32 pool_mask, reg, vid;
4186 int i;
4187
4188 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4189
4190 /* Find the vlan filter for this id */
4191 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4192 reg = rd32(E1000_VLVF(i));
4193
4194 /* remove the vf from the pool */
4195 reg &= ~pool_mask;
4196
4197 /* if pool is empty then remove entry from vfta */
4198 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4199 (reg & E1000_VLVF_VLANID_ENABLE)) {
4200 reg = 0;
4201 vid = reg & E1000_VLVF_VLANID_MASK;
4202 igb_vfta_set(hw, vid, false);
4203 }
4204
4205 wr32(E1000_VLVF(i), reg);
4206 }
ae641bdc
AD		 4207
4208 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4209}
4210
4211static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4212{
4213 struct e1000_hw *hw = &adapter->hw;
4214 u32 reg, i;
4215
4216 /* It is an error to call this function when VFs are not enabled */
4217 if (!adapter->vfs_allocated_count)
4218 return -1;
4219
4220 /* Find the vlan filter for this id */
4221 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4222 reg = rd32(E1000_VLVF(i));
4223 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4224 vid == (reg & E1000_VLVF_VLANID_MASK))
4225 break;
4226 }
4227
4228 if (add) {
4229 if (i == E1000_VLVF_ARRAY_SIZE) {
4230 /* Did not find a matching VLAN ID entry that was
4231 * enabled. Search for a free filter entry, i.e.
4232 * one without the enable bit set
4233 */
4234 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4235 reg = rd32(E1000_VLVF(i));
4236 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4237 break;
4238 }
4239 }
4240 if (i < E1000_VLVF_ARRAY_SIZE) {
4241 /* Found an enabled/available entry */
4242 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4243
4244 /* if !enabled we need to set this up in vfta */
4245 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4246 /* add VID to filter table, if bit already set
4247 * PF must have added it outside of table */
4248 if (igb_vfta_set(hw, vid, true))
4249 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4250 adapter->vfs_allocated_count);
4ae196df
AD		 4251 reg |= E1000_VLVF_VLANID_ENABLE;
4252 }
cad6d05f
AD		 4253 reg &= ~E1000_VLVF_VLANID_MASK;
4254 reg |= vid;
4ae196df
AD		 4255
4256 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4257
4258 /* do not modify RLPML for PF devices */
4259 if (vf >= adapter->vfs_allocated_count)
4260 return 0;
4261
4262 if (!adapter->vf_data[vf].vlans_enabled) {
4263 u32 size;
4264 reg = rd32(E1000_VMOLR(vf));
4265 size = reg & E1000_VMOLR_RLPML_MASK;
4266 size += 4;
4267 reg &= ~E1000_VMOLR_RLPML_MASK;
4268 reg |= size;
4269 wr32(E1000_VMOLR(vf), reg);
4270 }
4271 adapter->vf_data[vf].vlans_enabled++;
4272
4ae196df
AD		 4273 return 0;
4274 }
4275 } else {
4276 if (i < E1000_VLVF_ARRAY_SIZE) {
4277 /* remove vf from the pool */
4278 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4279 /* if pool is empty then remove entry from vfta */
4280 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4281 reg = 0;
4282 igb_vfta_set(hw, vid, false);
4283 }
4284 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4285
4286 /* do not modify RLPML for PF devices */
4287 if (vf >= adapter->vfs_allocated_count)
4288 return 0;
4289
4290 adapter->vf_data[vf].vlans_enabled--;
4291 if (!adapter->vf_data[vf].vlans_enabled) {
4292 u32 size;
4293 reg = rd32(E1000_VMOLR(vf));
4294 size = reg & E1000_VMOLR_RLPML_MASK;
4295 size -= 4;
4296 reg &= ~E1000_VMOLR_RLPML_MASK;
4297 reg |= size;
4298 wr32(E1000_VMOLR(vf), reg);
4299 }
4ae196df
AD		 4300 return 0;
4301 }
4302 }
4303 return -1;
4304}
4305
4306static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4307{
4308 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4309 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4310
4311 return igb_vlvf_set(adapter, vid, add, vf);
4312}
4313
4314static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4315{
4316 struct e1000_hw *hw = &adapter->hw;
4317
4318 /* disable mailbox functionality for vf */
4319 adapter->vf_data[vf].clear_to_send = false;
4320
4321 /* reset offloads to defaults */
4322 igb_set_vmolr(hw, vf);
4323
4324 /* reset vlans for device */
4325 igb_clear_vf_vfta(adapter, vf);
4326
4327 /* reset multicast table array for vf */
4328 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4329
4330 /* Flush and reset the mta with the new values */
ff41f8dc 4331 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4332}
4333
4334static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4335{
4336 struct e1000_hw *hw = &adapter->hw;
4337 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4338 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4339 u32 reg, msgbuf[3];
4340 u8 *addr = (u8 *)(&msgbuf[1]);
4341
4342 /* process all the same items cleared in a function level reset */
4343 igb_vf_reset_event(adapter, vf);
4344
4345 /* set vf mac address */
26ad9178 4346 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4347
4348 /* enable transmit and receive for vf */
4349 reg = rd32(E1000_VFTE);
4350 wr32(E1000_VFTE, reg | (1 << vf));
4351 reg = rd32(E1000_VFRE);
4352 wr32(E1000_VFRE, reg | (1 << vf));
4353
4354 /* enable mailbox functionality for vf */
4355 adapter->vf_data[vf].clear_to_send = true;
4356
4357 /* reply to reset with ack and vf mac address */
4358 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4359 memcpy(addr, vf_mac, 6);
4360 igb_write_mbx(hw, msgbuf, 3, vf);
4361}
4362
4363static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4364{
4365 unsigned char *addr = (char *)&msg[1];
4366 int err = -1;
4367
4368 if (is_valid_ether_addr(addr))
4369 err = igb_set_vf_mac(adapter, vf, addr);
4370
4371 return err;
4372
4373}
4374
4375static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4376{
4377 struct e1000_hw *hw = &adapter->hw;
4378 u32 msg = E1000_VT_MSGTYPE_NACK;
4379
4380 /* if device isn't clear to send it shouldn't be reading either */
4381 if (!adapter->vf_data[vf].clear_to_send)
4382 igb_write_mbx(hw, &msg, 1, vf);
4383}
4384
4385
4386static void igb_msg_task(struct igb_adapter *adapter)
4387{
4388 struct e1000_hw *hw = &adapter->hw;
4389 u32 vf;
4390
4391 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4392 /* process any reset requests */
4393 if (!igb_check_for_rst(hw, vf)) {
4394 adapter->vf_data[vf].clear_to_send = false;
4395 igb_vf_reset_event(adapter, vf);
4396 }
4397
4398 /* process any messages pending */
4399 if (!igb_check_for_msg(hw, vf))
4400 igb_rcv_msg_from_vf(adapter, vf);
4401
4402 /* process any acks */
4403 if (!igb_check_for_ack(hw, vf))
4404 igb_rcv_ack_from_vf(adapter, vf);
4405
4406 }
4407}
4408
4409static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4410{
4411 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4412 u32 msgbuf[mbx_size];
4413 struct e1000_hw *hw = &adapter->hw;
4414 s32 retval;
4415
4416 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4417
4418 if (retval)
4419 dev_err(&adapter->pdev->dev,
4420 "Error receiving message from VF\n");
4421
4422 /* this is a message we already processed, do nothing */
4423 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4424 return retval;
4425
4426 /*
4427 * until the vf completes a reset it should not be
4428 * allowed to start any configuration.
4429 */
4430
4431 if (msgbuf[0] == E1000_VF_RESET) {
4432 igb_vf_reset_msg(adapter, vf);
4433
4434 return retval;
4435 }
4436
4437 if (!adapter->vf_data[vf].clear_to_send) {
4438 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4439 igb_write_mbx(hw, msgbuf, 1, vf);
4440 return retval;
4441 }
4442
4443 switch ((msgbuf[0] & 0xFFFF)) {
4444 case E1000_VF_SET_MAC_ADDR:
4445 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4446 break;
4447 case E1000_VF_SET_MULTICAST:
4448 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4449 break;
4450 case E1000_VF_SET_LPE:
4451 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4452 break;
4453 case E1000_VF_SET_VLAN:
4454 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4455 break;
4456 default:
4457 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4458 retval = -1;
4459 break;
4460 }
4461
4462 /* notify the VF of the results of what it sent us */
4463 if (retval)
4464 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4465 else
4466 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4467
4468 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4469
4470 igb_write_mbx(hw, msgbuf, 1, vf);
4471
4472 return retval;
4473}
4474
68d480c4
AD		 4475/**
4476 * igb_set_uta - Set unicast filter table address
4477 * @adapter: board private structure
4478 *
4479 * The unicast table address is a register array of 32-bit registers.
4480 * The table is meant to be used in a way similar to how the MTA is used
4481 * however due to certain limitations in the hardware it is necessary to
4482 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4483 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4484 **/
4485static void igb_set_uta(struct igb_adapter *adapter)
4486{
4487 struct e1000_hw *hw = &adapter->hw;
4488 int i;
4489
4490 /* The UTA table only exists on 82576 hardware and newer */
4491 if (hw->mac.type < e1000_82576)
4492 return;
4493
4494 /* we only need to do this if VMDq is enabled */
4495 if (!adapter->vfs_allocated_count)
4496 return;
4497
4498 for (i = 0; i < hw->mac.uta_reg_count; i++)
4499 array_wr32(E1000_UTA, i, ~0);
4500}
4501
9d5c8243
AK		 4502/**
4503 * igb_intr_msi - Interrupt Handler
4504 * @irq: interrupt number
4505 * @data: pointer to a network interface device structure
4506 **/
4507static irqreturn_t igb_intr_msi(int irq, void *data)
4508{
047e0030
AD		 4509 struct igb_adapter *adapter = data;
4510 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4511 struct e1000_hw *hw = &adapter->hw;
4512 /* read ICR disables interrupts using IAM */
4513 u32 icr = rd32(E1000_ICR);
4514
047e0030 4515 igb_write_itr(q_vector);
9d5c8243 4516
047e0030 4517 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4518 /* HW is reporting DMA is out of sync */
4519 adapter->stats.doosync++;
4520 }
4521
9d5c8243
AK		 4522 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4523 hw->mac.get_link_status = 1;
4524 if (!test_bit(__IGB_DOWN, &adapter->state))
4525 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4526 }
4527
047e0030 4528 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4529
4530 return IRQ_HANDLED;
4531}
4532
4533/**
4a3c6433 4534 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4535 * @irq: interrupt number
4536 * @data: pointer to a network interface device structure
4537 **/
4538static irqreturn_t igb_intr(int irq, void *data)
4539{
047e0030
AD		 4540 struct igb_adapter *adapter = data;
4541 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4542 struct e1000_hw *hw = &adapter->hw;
4543 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4544 * need for the IMC write */
4545 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4546 if (!icr)
4547 return IRQ_NONE; /* Not our interrupt */
4548
047e0030 4549 igb_write_itr(q_vector);
9d5c8243
AK		 4550
4551 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4552 * not set, then the adapter didn't send an interrupt */
4553 if (!(icr & E1000_ICR_INT_ASSERTED))
4554 return IRQ_NONE;
4555
047e0030 4556 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4557 /* HW is reporting DMA is out of sync */
4558 adapter->stats.doosync++;
4559 }
4560
9d5c8243
AK		 4561 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4562 hw->mac.get_link_status = 1;
4563 /* guard against interrupt when we're going down */
4564 if (!test_bit(__IGB_DOWN, &adapter->state))
4565 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4566 }
4567
047e0030 4568 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4569
4570 return IRQ_HANDLED;
4571}
4572
047e0030 4573static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4574{
047e0030 4575 struct igb_adapter *adapter = q_vector->adapter;
46544258 4576 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4577
46544258 4578 if (adapter->itr_setting & 3) {
047e0030 4579 if (!adapter->msix_entries)
6eb5a7f1 4580 igb_set_itr(adapter);
46544258 4581 else
047e0030 4582 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4583 }
4584
46544258
AD		 4585 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4586 if (adapter->msix_entries)
047e0030 4587 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4588 else
4589 igb_irq_enable(adapter);
4590 }
9d5c8243
AK		 4591}
4592
46544258
AD		 4593/**
4594 * igb_poll - NAPI Rx polling callback
4595 * @napi: napi polling structure
4596 * @budget: count of how many packets we should handle
4597 **/
4598static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4599{
047e0030
AD		 4600 struct igb_q_vector *q_vector = container_of(napi,
4601 struct igb_q_vector,
4602 napi);
4603 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4604
421e02f0 4605#ifdef CONFIG_IGB_DCA
047e0030
AD		 4606 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4607 igb_update_dca(q_vector);
fe4506b6 4608#endif
047e0030
AD		 4609 if (q_vector->tx_ring)
4610 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4611
047e0030
AD		 4612 if (q_vector->rx_ring)
4613 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4614
4615 if (!tx_clean_complete)
4616 work_done = budget;
46544258 4617
9d5c8243 4618 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4619 if (work_done < budget) {
288379f0 4620 napi_complete(napi);
047e0030 4621 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4622 }
4623
46544258 4624 return work_done;
9d5c8243 4625}
6d8126f9 4626
33af6bcc
PO		 4627/**
4628 * igb_hwtstamp - utility function which checks for TX time stamp
4629 * @adapter: board private structure
4630 * @skb: packet that was just sent
4631 *
4632 * If we were asked to do hardware stamping and such a time stamp is
4633 * available, then it must have been for this skb here because we only
4634 * allow only one such packet into the queue.
4635 */
4636static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4637{
4638 union skb_shared_tx *shtx = skb_tx(skb);
4639 struct e1000_hw *hw = &adapter->hw;
4640
4641 if (unlikely(shtx->hardware)) {
4642 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4643 if (valid) {
4644 u64 regval = rd32(E1000_TXSTMPL);
4645 u64 ns;
4646 struct skb_shared_hwtstamps shhwtstamps;
4647
4648 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4649 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4650 ns = timecounter_cyc2time(&adapter->clock,
4651 regval);
4652 timecompare_update(&adapter->compare, ns);
4653 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4654 shhwtstamps.syststamp =
4655 timecompare_transform(&adapter->compare, ns);
4656 skb_tstamp_tx(skb, &shhwtstamps);
4657 }
33af6bcc
PO		 4658 }
4659}
4660
9d5c8243
AK		 4661/**
4662 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4663 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4664 * returns true if ring is completely cleaned
4665 **/
047e0030 4666static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4667{
047e0030
AD		 4668 struct igb_adapter *adapter = q_vector->adapter;
4669 struct igb_ring *tx_ring = q_vector->tx_ring;
3b644cf6 4670 struct net_device *netdev = adapter->netdev;
0e014cb1 4671 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4672 struct igb_buffer *buffer_info;
4673 struct sk_buff *skb;
0e014cb1 4674 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4675 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4676 unsigned int i, eop, count = 0;
4677 bool cleaned = false;
9d5c8243 4678
9d5c8243 4679 i = tx_ring->next_to_clean;
0e014cb1
AD		 4680 eop = tx_ring->buffer_info[i].next_to_watch;
4681 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4682
4683 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4684 (count < tx_ring->count)) {
4685 for (cleaned = false; !cleaned; count++) {
4686 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4687 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4688 cleaned = (i == eop);
9d5c8243
AK		 4689 skb = buffer_info->skb;
4690
4691 if (skb) {
4692 unsigned int segs, bytecount;
4693 /* gso_segs is currently only valid for tcp */
4694 segs = skb_shinfo(skb)->gso_segs ?: 1;
4695 /* multiply data chunks by size of headers */
4696 bytecount = ((segs - 1) * skb_headlen(skb)) +
4697 skb->len;
4698 total_packets += segs;
4699 total_bytes += bytecount;
33af6bcc
PO		 4700
4701 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4702 }
4703
80785298 4704 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 4705 tx_desc->wb.status = 0;
9d5c8243
AK		 4706
4707 i++;
4708 if (i == tx_ring->count)
4709 i = 0;
9d5c8243 4710 }
0e014cb1
AD		 4711 eop = tx_ring->buffer_info[i].next_to_watch;
4712 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4713 }
4714
9d5c8243
AK		 4715 tx_ring->next_to_clean = i;
4716
fc7d345d 4717 if (unlikely(count &&
9d5c8243 4718 netif_carrier_ok(netdev) &&
c493ea45 4719 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4720 /* Make sure that anybody stopping the queue after this
4721 * sees the new next_to_clean.
4722 */
4723 smp_mb();
661086df
PWJ		 4724 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4725 !(test_bit(__IGB_DOWN, &adapter->state))) {
4726 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 4727 tx_ring->tx_stats.restart_queue++;
661086df 4728 }
9d5c8243
AK		 4729 }
4730
4731 if (tx_ring->detect_tx_hung) {
4732 /* Detect a transmit hang in hardware, this serializes the
4733 * check with the clearing of time_stamp and movement of i */
4734 tx_ring->detect_tx_hung = false;
4735 if (tx_ring->buffer_info[i].time_stamp &&
4736 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4737 (adapter->tx_timeout_factor * HZ))
4738 && !(rd32(E1000_STATUS) &
4739 E1000_STATUS_TXOFF)) {
4740
9d5c8243 4741 /* detected Tx unit hang */
80785298 4742 dev_err(&tx_ring->pdev->dev,
9d5c8243 4743 "Detected Tx Unit Hang\n"
2d064c06 4744 " Tx Queue <%d>\n"
9d5c8243
AK		 4745 " TDH <%x>\n"
4746 " TDT <%x>\n"
4747 " next_to_use <%x>\n"
4748 " next_to_clean <%x>\n"
9d5c8243
AK		 4749 "buffer_info[next_to_clean]\n"
4750 " time_stamp <%lx>\n"
0e014cb1 4751 " next_to_watch <%x>\n"
9d5c8243
AK		 4752 " jiffies <%lx>\n"
4753 " desc.status <%x>\n",
2d064c06 4754 tx_ring->queue_index,
fce99e34
AD		 4755 readl(tx_ring->head),
4756 readl(tx_ring->tail),
9d5c8243
AK		 4757 tx_ring->next_to_use,
4758 tx_ring->next_to_clean,
9d5c8243 4759 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4760 eop,
9d5c8243 4761 jiffies,
0e014cb1 4762 eop_desc->wb.status);
661086df 4763 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4764 }
4765 }
4766 tx_ring->total_bytes += total_bytes;
4767 tx_ring->total_packets += total_packets;
e21ed353
AD		 4768 tx_ring->tx_stats.bytes += total_bytes;
4769 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4770 netdev->stats.tx_bytes += total_bytes;
4771 netdev->stats.tx_packets += total_packets;
0e014cb1 4772 return (count < tx_ring->count);
9d5c8243
AK		 4773}
4774
9d5c8243
AK		 4775/**
4776 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4777 * @q_vector: structure containing interrupt and ring information
4778 * @skb: packet to send up
4779 * @vlan_tag: vlan tag for packet
9d5c8243 4780 **/
047e0030
AD		 4781static void igb_receive_skb(struct igb_q_vector *q_vector,
4782 struct sk_buff *skb,
4783 u16 vlan_tag)
4784{
4785 struct igb_adapter *adapter = q_vector->adapter;
4786
4787 if (vlan_tag)
4788 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4789 vlan_tag, skb);
182ff8df 4790 else
047e0030 4791 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4792}
4793
04a5fcaa 4794static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 4795 u32 status_err, struct sk_buff *skb)
4796{
4797 skb->ip_summed = CHECKSUM_NONE;
4798
4799 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 4800 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
4801 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 4802 return;
85ad76b2 4803
9d5c8243
AK		 4804 /* TCP/UDP checksum error bit is set */
4805 if (status_err &
4806 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4807 /*
4808 * work around errata with sctp packets where the TCPE aka
4809 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4810 * packets, (aka let the stack check the crc32c)
4811 */
85ad76b2
AD		 4812 if ((skb->len == 60) &&
4813 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 4814 ring->rx_stats.csum_err++;
85ad76b2 4815
9d5c8243 4816 /* let the stack verify checksum errors */
9d5c8243
AK		 4817 return;
4818 }
4819 /* It must be a TCP or UDP packet with a valid checksum */
4820 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4821 skb->ip_summed = CHECKSUM_UNNECESSARY;
4822
85ad76b2 4823 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4824}
4825
4c844851 4826static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 4827 union e1000_adv_rx_desc *rx_desc)
4828{
4829 /* HW will not DMA in data larger than the given buffer, even if it
4830 * parses the (NFS, of course) header to be larger. In that case, it
4831 * fills the header buffer and spills the rest into the page.
4832 */
4833 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4834 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 4835 if (hlen > rx_ring->rx_buffer_len)
4836 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 4837 return hlen;
4838}
4839
047e0030
AD		 4840static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4841 int *work_done, int budget)
9d5c8243 4842{
047e0030 4843 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 4844 struct net_device *netdev = adapter->netdev;
047e0030 4845 struct igb_ring *rx_ring = q_vector->rx_ring;
33af6bcc 4846 struct e1000_hw *hw = &adapter->hw;
80785298 4847 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 4848 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4849 struct igb_buffer *buffer_info , *next_buffer;
4850 struct sk_buff *skb;
9d5c8243
AK		 4851 bool cleaned = false;
4852 int cleaned_count = 0;
4853 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4854 unsigned int i;
2d94d8ab
AD		 4855 u32 staterr;
4856 u16 length;
047e0030 4857 u16 vlan_tag;
9d5c8243
AK		 4858
4859 i = rx_ring->next_to_clean;
69d3ca53 4860 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4861 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4862 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4863
4864 while (staterr & E1000_RXD_STAT_DD) {
4865 if (*work_done >= budget)
4866 break;
4867 (*work_done)++;
9d5c8243 4868
69d3ca53
AD		 4869 skb = buffer_info->skb;
4870 prefetch(skb->data - NET_IP_ALIGN);
4871 buffer_info->skb = NULL;
4872
4873 i++;
4874 if (i == rx_ring->count)
4875 i = 0;
4876 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4877 prefetch(next_rxd);
4878 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4879
4880 length = le16_to_cpu(rx_desc->wb.upper.length);
4881 cleaned = true;
4882 cleaned_count++;
4883
2d94d8ab 4884 if (buffer_info->dma) {
bf36c1a0 4885 pci_unmap_single(pdev, buffer_info->dma,
4c844851 4886 rx_ring->rx_buffer_len,
bf36c1a0 4887 PCI_DMA_FROMDEVICE);
91615f76 4888 buffer_info->dma = 0;
4c844851 4889 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 4890 skb_put(skb, length);
4891 goto send_up;
4892 }
4c844851 4893 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 4894 }
4895
4896 if (length) {
9d5c8243 4897 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4898 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4899 buffer_info->page_dma = 0;
bf36c1a0
AD		 4900
4901 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4902 buffer_info->page,
4903 buffer_info->page_offset,
4904 length);
4905
6ec43fe6 4906 if (page_count(buffer_info->page) != 1)
bf36c1a0
AD		 4907 buffer_info->page = NULL;
4908 else
4909 get_page(buffer_info->page);
9d5c8243
AK		 4910
4911 skb->len += length;
4912 skb->data_len += length;
9d5c8243 4913
bf36c1a0 4914 skb->truesize += length;
9d5c8243 4915 }
9d5c8243 4916
bf36c1a0 4917 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4918 buffer_info->skb = next_buffer->skb;
4919 buffer_info->dma = next_buffer->dma;
4920 next_buffer->skb = skb;
4921 next_buffer->dma = 0;
bf36c1a0
AD		 4922 goto next_desc;
4923 }
69d3ca53 4924send_up:
33af6bcc
PO		 4925 /*
4926 * If this bit is set, then the RX registers contain
4927 * the time stamp. No other packet will be time
4928 * stamped until we read these registers, so read the
4929 * registers to make them available again. Because
4930 * only one packet can be time stamped at a time, we
4931 * know that the register values must belong to this
4932 * one here and therefore we don't need to compare
4933 * any of the additional attributes stored for it.
4934 *
4935 * If nothing went wrong, then it should have a
4936 * skb_shared_tx that we can turn into a
4937 * skb_shared_hwtstamps.
4938 *
4939 * TODO: can time stamping be triggered (thus locking
4940 * the registers) without the packet reaching this point
4941 * here? In that case RX time stamping would get stuck.
4942 *
4943 * TODO: in "time stamp all packets" mode this bit is
4944 * not set. Need a global flag for this mode and then
4945 * always read the registers. Cannot be done without
4946 * a race condition.
4947 */
4948 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4949 u64 regval;
4950 u64 ns;
4951 struct skb_shared_hwtstamps *shhwtstamps =
4952 skb_hwtstamps(skb);
4953
4954 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4955 "igb: no RX time stamp available for time stamped packet");
4956 regval = rd32(E1000_RXSTMPL);
4957 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4958 ns = timecounter_cyc2time(&adapter->clock, regval);
4959 timecompare_update(&adapter->compare, ns);
4960 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4961 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4962 shhwtstamps->syststamp =
4963 timecompare_transform(&adapter->compare, ns);
4964 }
4965
9d5c8243
AK		 4966 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4967 dev_kfree_skb_irq(skb);
4968 goto next_desc;
4969 }
9d5c8243
AK		 4970
4971 total_bytes += skb->len;
4972 total_packets++;
4973
85ad76b2 4974 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 4975
4976 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 4977 skb_record_rx_queue(skb, rx_ring->queue_index);
4978
4979 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
4980 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 4981
047e0030 4982 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 4983
9d5c8243
AK		 4984next_desc:
4985 rx_desc->wb.upper.status_error = 0;
4986
4987 /* return some buffers to hardware, one at a time is too slow */
4988 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4989 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4990 cleaned_count = 0;
4991 }
4992
4993 /* use prefetched values */
4994 rx_desc = next_rxd;
4995 buffer_info = next_buffer;
9d5c8243
AK		 4996 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4997 }
bf36c1a0 4998
9d5c8243 4999 rx_ring->next_to_clean = i;
c493ea45 5000 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5001
5002 if (cleaned_count)
3b644cf6 5003 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5004
5005 rx_ring->total_packets += total_packets;
5006 rx_ring->total_bytes += total_bytes;
5007 rx_ring->rx_stats.packets += total_packets;
5008 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5009 netdev->stats.rx_bytes += total_bytes;
5010 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5011 return cleaned;
5012}
5013
9d5c8243
AK		 5014/**
5015 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5016 * @adapter: address of board private structure
5017 **/
3b644cf6 5018static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 5019 int cleaned_count)
5020{
047e0030 5021 struct igb_adapter *adapter = rx_ring->q_vector->adapter;
9d5c8243 5022 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 5023 union e1000_adv_rx_desc *rx_desc;
5024 struct igb_buffer *buffer_info;
5025 struct sk_buff *skb;
5026 unsigned int i;
db761762 5027 int bufsz;
9d5c8243
AK		 5028
5029 i = rx_ring->next_to_use;
5030 buffer_info = &rx_ring->buffer_info[i];
5031
4c844851 5032 bufsz = rx_ring->rx_buffer_len;
db761762 5033
9d5c8243
AK		 5034 while (cleaned_count--) {
5035 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5036
6ec43fe6 5037 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5038 if (!buffer_info->page) {
bf36c1a0
AD		 5039 buffer_info->page = alloc_page(GFP_ATOMIC);
5040 if (!buffer_info->page) {
04a5fcaa 5041 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5042 goto no_buffers;
5043 }
5044 buffer_info->page_offset = 0;
5045 } else {
5046 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5047 }
5048 buffer_info->page_dma =
80785298 5049 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5050 buffer_info->page_offset,
5051 PAGE_SIZE / 2,
9d5c8243
AK		 5052 PCI_DMA_FROMDEVICE);
5053 }
5054
5055 if (!buffer_info->skb) {
89d71a66 5056 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5057 if (!skb) {
04a5fcaa 5058 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5059 goto no_buffers;
5060 }
5061
9d5c8243 5062 buffer_info->skb = skb;
80785298
AD		 5063 buffer_info->dma = pci_map_single(rx_ring->pdev,
5064 skb->data,
9d5c8243
AK		 5065 bufsz,
5066 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5067 }
5068 /* Refresh the desc even if buffer_addrs didn't change because
5069 * each write-back erases this info. */
6ec43fe6 5070 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5071 rx_desc->read.pkt_addr =
5072 cpu_to_le64(buffer_info->page_dma);
5073 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5074 } else {
5075 rx_desc->read.pkt_addr =
5076 cpu_to_le64(buffer_info->dma);
5077 rx_desc->read.hdr_addr = 0;
5078 }
5079
5080 i++;
5081 if (i == rx_ring->count)
5082 i = 0;
5083 buffer_info = &rx_ring->buffer_info[i];
5084 }
5085
5086no_buffers:
5087 if (rx_ring->next_to_use != i) {
5088 rx_ring->next_to_use = i;
5089 if (i == 0)
5090 i = (rx_ring->count - 1);
5091 else
5092 i--;
5093
5094 /* Force memory writes to complete before letting h/w
5095 * know there are new descriptors to fetch. (Only
5096 * applicable for weak-ordered memory model archs,
5097 * such as IA-64). */
5098 wmb();
fce99e34 5099 writel(i, rx_ring->tail);
9d5c8243
AK		 5100 }
5101}
5102
5103/**
5104 * igb_mii_ioctl -
5105 * @netdev:
5106 * @ifreq:
5107 * @cmd:
5108 **/
5109static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5110{
5111 struct igb_adapter *adapter = netdev_priv(netdev);
5112 struct mii_ioctl_data *data = if_mii(ifr);
5113
5114 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5115 return -EOPNOTSUPP;
5116
5117 switch (cmd) {
5118 case SIOCGMIIPHY:
5119 data->phy_id = adapter->hw.phy.addr;
5120 break;
5121 case SIOCGMIIREG:
f5f4cf08
AD		 5122 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5123 &data->val_out))
9d5c8243
AK		 5124 return -EIO;
5125 break;
5126 case SIOCSMIIREG:
5127 default:
5128 return -EOPNOTSUPP;
5129 }
5130 return 0;
5131}
5132
c6cb090b
PO		 5133/**
5134 * igb_hwtstamp_ioctl - control hardware time stamping
5135 * @netdev:
5136 * @ifreq:
5137 * @cmd:
5138 *
33af6bcc
PO		 5139 * Outgoing time stamping can be enabled and disabled. Play nice and
5140 * disable it when requested, although it shouldn't case any overhead
5141 * when no packet needs it. At most one packet in the queue may be
5142 * marked for time stamping, otherwise it would be impossible to tell
5143 * for sure to which packet the hardware time stamp belongs.
5144 *
5145 * Incoming time stamping has to be configured via the hardware
5146 * filters. Not all combinations are supported, in particular event
5147 * type has to be specified. Matching the kind of event packet is
5148 * not supported, with the exception of "all V2 events regardless of
5149 * level 2 or 4".
5150 *
c6cb090b
PO		 5151 **/
5152static int igb_hwtstamp_ioctl(struct net_device *netdev,
5153 struct ifreq *ifr, int cmd)
5154{
33af6bcc
PO		 5155 struct igb_adapter *adapter = netdev_priv(netdev);
5156 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5157 struct hwtstamp_config config;
33af6bcc
PO		 5158 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5159 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
5160 u32 tsync_rx_ctl_type = 0;
5161 u32 tsync_rx_cfg = 0;
5162 int is_l4 = 0;
5163 int is_l2 = 0;
5164 short port = 319; /* PTP */
5165 u32 regval;
c6cb090b
PO		 5166
5167 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5168 return -EFAULT;
5169
5170 /* reserved for future extensions */
5171 if (config.flags)
5172 return -EINVAL;
5173
33af6bcc
PO		 5174 switch (config.tx_type) {
5175 case HWTSTAMP_TX_OFF:
5176 tsync_tx_ctl_bit = 0;
5177 break;
5178 case HWTSTAMP_TX_ON:
5179 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
5180 break;
5181 default:
5182 return -ERANGE;
5183 }
5184
5185 switch (config.rx_filter) {
5186 case HWTSTAMP_FILTER_NONE:
5187 tsync_rx_ctl_bit = 0;
5188 break;
5189 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5190 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5191 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5192 case HWTSTAMP_FILTER_ALL:
5193 /*
5194 * register TSYNCRXCFG must be set, therefore it is not
5195 * possible to time stamp both Sync and Delay_Req messages
5196 * => fall back to time stamping all packets
5197 */
5198 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
5199 config.rx_filter = HWTSTAMP_FILTER_ALL;
5200 break;
5201 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5202 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5203 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
5204 is_l4 = 1;
5205 break;
5206 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5207 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5208 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5209 is_l4 = 1;
5210 break;
5211 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5212 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5213 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5214 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5215 is_l2 = 1;
5216 is_l4 = 1;
5217 config.rx_filter = HWTSTAMP_FILTER_SOME;
5218 break;
5219 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5220 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5221 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5222 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5223 is_l2 = 1;
5224 is_l4 = 1;
5225 config.rx_filter = HWTSTAMP_FILTER_SOME;
5226 break;
5227 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5228 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5229 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5230 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5231 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5232 is_l2 = 1;
5233 break;
5234 default:
5235 return -ERANGE;
5236 }
5237
5238 /* enable/disable TX */
5239 regval = rd32(E1000_TSYNCTXCTL);
5240 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5241 wr32(E1000_TSYNCTXCTL, regval);
5242
5243 /* enable/disable RX, define which PTP packets are time stamped */
5244 regval = rd32(E1000_TSYNCRXCTL);
5245 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5246 regval = (regval & ~0xE) | tsync_rx_ctl_type;
5247 wr32(E1000_TSYNCRXCTL, regval);
5248 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5249
5250 /*
5251 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5252 * (Ethertype to filter on)
5253 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5254 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5255 */
5256 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5257
5258 /* L4 Queue Filter[0]: only filter by source and destination port */
5259 wr32(E1000_SPQF0, htons(port));
5260 wr32(E1000_IMIREXT(0), is_l4 ?
5261 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5262 wr32(E1000_IMIR(0), is_l4 ?
5263 (htons(port)
5264 | (0<<16) /* immediate interrupt disabled */
5265 | 0 /* (1<<17) bit cleared: do not bypass
5266 destination port check */)
5267 : 0);
5268 wr32(E1000_FTQF0, is_l4 ?
5269 (0x11 /* UDP */
5270 | (1<<15) /* VF not compared */
5271 | (1<<27) /* Enable Timestamping */
5272 | (7<<28) /* only source port filter enabled,
5273 source/target address and protocol
5274 masked */)
5275 : ((1<<15) | (15<<28) /* all mask bits set = filter not
5276 enabled */));
5277
5278 wrfl();
5279
5280 adapter->hwtstamp_config = config;
5281
5282 /* clear TX/RX time stamp registers, just to be sure */
5283 regval = rd32(E1000_TXSTMPH);
5284 regval = rd32(E1000_RXSTMPH);
c6cb090b 5285
33af6bcc
PO		 5286 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5287 -EFAULT : 0;
c6cb090b
PO		 5288}
5289
9d5c8243
AK		 5290/**
5291 * igb_ioctl -
5292 * @netdev:
5293 * @ifreq:
5294 * @cmd:
5295 **/
5296static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5297{
5298 switch (cmd) {
5299 case SIOCGMIIPHY:
5300 case SIOCGMIIREG:
5301 case SIOCSMIIREG:
5302 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5303 case SIOCSHWTSTAMP:
5304 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5305 default:
5306 return -EOPNOTSUPP;
5307 }
5308}
5309
009bc06e
AD		 5310s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5311{
5312 struct igb_adapter *adapter = hw->back;
5313 u16 cap_offset;
5314
5315 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5316 if (!cap_offset)
5317 return -E1000_ERR_CONFIG;
5318
5319 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5320
5321 return 0;
5322}
5323
5324s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5325{
5326 struct igb_adapter *adapter = hw->back;
5327 u16 cap_offset;
5328
5329 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5330 if (!cap_offset)
5331 return -E1000_ERR_CONFIG;
5332
5333 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5334
5335 return 0;
5336}
5337
9d5c8243
AK		 5338static void igb_vlan_rx_register(struct net_device *netdev,
5339 struct vlan_group *grp)
5340{
5341 struct igb_adapter *adapter = netdev_priv(netdev);
5342 struct e1000_hw *hw = &adapter->hw;
5343 u32 ctrl, rctl;
5344
5345 igb_irq_disable(adapter);
5346 adapter->vlgrp = grp;
5347
5348 if (grp) {
5349 /* enable VLAN tag insert/strip */
5350 ctrl = rd32(E1000_CTRL);
5351 ctrl |= E1000_CTRL_VME;
5352 wr32(E1000_CTRL, ctrl);
5353
5354 /* enable VLAN receive filtering */
5355 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5356 rctl &= ~E1000_RCTL_CFIEN;
5357 wr32(E1000_RCTL, rctl);
5358 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5359 } else {
5360 /* disable VLAN tag insert/strip */
5361 ctrl = rd32(E1000_CTRL);
5362 ctrl &= ~E1000_CTRL_VME;
5363 wr32(E1000_CTRL, ctrl);
5364
9d5c8243
AK		 5365 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5366 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5367 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5368 }
9d5c8243
AK		 5369 }
5370
e1739522
AD		 5371 igb_rlpml_set(adapter);
5372
9d5c8243
AK		 5373 if (!test_bit(__IGB_DOWN, &adapter->state))
5374 igb_irq_enable(adapter);
5375}
5376
5377static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5378{
5379 struct igb_adapter *adapter = netdev_priv(netdev);
5380 struct e1000_hw *hw = &adapter->hw;
4ae196df 5381 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5382
28b0759c 5383 if ((hw->mng_cookie.status &
9d5c8243
AK		 5384 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5385 (vid == adapter->mng_vlan_id))
5386 return;
4ae196df
AD		 5387
5388 /* add vid to vlvf if sr-iov is enabled,
5389 * if that fails add directly to filter table */
5390 if (igb_vlvf_set(adapter, vid, true, pf_id))
5391 igb_vfta_set(hw, vid, true);
5392
9d5c8243
AK		 5393}
5394
5395static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5396{
5397 struct igb_adapter *adapter = netdev_priv(netdev);
5398 struct e1000_hw *hw = &adapter->hw;
4ae196df 5399 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5400
5401 igb_irq_disable(adapter);
5402 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5403
5404 if (!test_bit(__IGB_DOWN, &adapter->state))
5405 igb_irq_enable(adapter);
5406
5407 if ((adapter->hw.mng_cookie.status &
5408 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5409 (vid == adapter->mng_vlan_id)) {
5410 /* release control to f/w */
5411 igb_release_hw_control(adapter);
5412 return;
5413 }
5414
4ae196df
AD		 5415 /* remove vid from vlvf if sr-iov is enabled,
5416 * if not in vlvf remove from vfta */
5417 if (igb_vlvf_set(adapter, vid, false, pf_id))
5418 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5419}
5420
5421static void igb_restore_vlan(struct igb_adapter *adapter)
5422{
5423 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5424
5425 if (adapter->vlgrp) {
5426 u16 vid;
5427 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5428 if (!vlan_group_get_device(adapter->vlgrp, vid))
5429 continue;
5430 igb_vlan_rx_add_vid(adapter->netdev, vid);
5431 }
5432 }
5433}
5434
5435int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5436{
5437 struct e1000_mac_info *mac = &adapter->hw.mac;
5438
5439 mac->autoneg = 0;
5440
9d5c8243
AK		 5441 switch (spddplx) {
5442 case SPEED_10 + DUPLEX_HALF:
5443 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5444 break;
5445 case SPEED_10 + DUPLEX_FULL:
5446 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5447 break;
5448 case SPEED_100 + DUPLEX_HALF:
5449 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5450 break;
5451 case SPEED_100 + DUPLEX_FULL:
5452 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5453 break;
5454 case SPEED_1000 + DUPLEX_FULL:
5455 mac->autoneg = 1;
5456 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5457 break;
5458 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5459 default:
5460 dev_err(&adapter->pdev->dev,
5461 "Unsupported Speed/Duplex configuration\n");
5462 return -EINVAL;
5463 }
5464 return 0;
5465}
5466
3fe7c4c9 5467static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5468{
5469 struct net_device *netdev = pci_get_drvdata(pdev);
5470 struct igb_adapter *adapter = netdev_priv(netdev);
5471 struct e1000_hw *hw = &adapter->hw;
2d064c06 5472 u32 ctrl, rctl, status;
9d5c8243
AK		 5473 u32 wufc = adapter->wol;
5474#ifdef CONFIG_PM
5475 int retval = 0;
5476#endif
5477
5478 netif_device_detach(netdev);
5479
a88f10ec
AD		 5480 if (netif_running(netdev))
5481 igb_close(netdev);
5482
047e0030 5483 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5484
5485#ifdef CONFIG_PM
5486 retval = pci_save_state(pdev);
5487 if (retval)
5488 return retval;
5489#endif
5490
5491 status = rd32(E1000_STATUS);
5492 if (status & E1000_STATUS_LU)
5493 wufc &= ~E1000_WUFC_LNKC;
5494
5495 if (wufc) {
5496 igb_setup_rctl(adapter);
ff41f8dc 5497 igb_set_rx_mode(netdev);
9d5c8243
AK		 5498
5499 /* turn on all-multi mode if wake on multicast is enabled */
5500 if (wufc & E1000_WUFC_MC) {
5501 rctl = rd32(E1000_RCTL);
5502 rctl |= E1000_RCTL_MPE;
5503 wr32(E1000_RCTL, rctl);
5504 }
5505
5506 ctrl = rd32(E1000_CTRL);
5507 /* advertise wake from D3Cold */
5508 #define E1000_CTRL_ADVD3WUC 0x00100000
5509 /* phy power management enable */
5510 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5511 ctrl |= E1000_CTRL_ADVD3WUC;
5512 wr32(E1000_CTRL, ctrl);
5513
9d5c8243
AK		 5514 /* Allow time for pending master requests to run */
5515 igb_disable_pcie_master(&adapter->hw);
5516
5517 wr32(E1000_WUC, E1000_WUC_PME_EN);
5518 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5519 } else {
5520 wr32(E1000_WUC, 0);
5521 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5522 }
5523
3fe7c4c9
RW		 5524 *enable_wake = wufc || adapter->en_mng_pt;
5525 if (!*enable_wake)
2fb02a26 5526 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5527
5528 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5529 * would have already happened in close and is redundant. */
5530 igb_release_hw_control(adapter);
5531
5532 pci_disable_device(pdev);
5533
9d5c8243
AK		 5534 return 0;
5535}
5536
5537#ifdef CONFIG_PM
3fe7c4c9
RW		 5538static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5539{
5540 int retval;
5541 bool wake;
5542
5543 retval = __igb_shutdown(pdev, &wake);
5544 if (retval)
5545 return retval;
5546
5547 if (wake) {
5548 pci_prepare_to_sleep(pdev);
5549 } else {
5550 pci_wake_from_d3(pdev, false);
5551 pci_set_power_state(pdev, PCI_D3hot);
5552 }
5553
5554 return 0;
5555}
5556
9d5c8243
AK		 5557static int igb_resume(struct pci_dev *pdev)
5558{
5559 struct net_device *netdev = pci_get_drvdata(pdev);
5560 struct igb_adapter *adapter = netdev_priv(netdev);
5561 struct e1000_hw *hw = &adapter->hw;
5562 u32 err;
5563
5564 pci_set_power_state(pdev, PCI_D0);
5565 pci_restore_state(pdev);
42bfd33a 5566
aed5dec3 5567 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5568 if (err) {
5569 dev_err(&pdev->dev,
5570 "igb: Cannot enable PCI device from suspend\n");
5571 return err;
5572 }
5573 pci_set_master(pdev);
5574
5575 pci_enable_wake(pdev, PCI_D3hot, 0);
5576 pci_enable_wake(pdev, PCI_D3cold, 0);
5577
047e0030 5578 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5579 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5580 return -ENOMEM;
9d5c8243
AK		 5581 }
5582
5583 /* e1000_power_up_phy(adapter); */
5584
5585 igb_reset(adapter);
a8564f03
AD		 5586
5587 /* let the f/w know that the h/w is now under the control of the
5588 * driver. */
5589 igb_get_hw_control(adapter);
5590
9d5c8243
AK		 5591 wr32(E1000_WUS, ~0);
5592
a88f10ec
AD		 5593 if (netif_running(netdev)) {
5594 err = igb_open(netdev);
5595 if (err)
5596 return err;
5597 }
9d5c8243
AK		 5598
5599 netif_device_attach(netdev);
5600
9d5c8243
AK		 5601 return 0;
5602}
5603#endif
5604
5605static void igb_shutdown(struct pci_dev *pdev)
5606{
3fe7c4c9
RW		 5607 bool wake;
5608
5609 __igb_shutdown(pdev, &wake);
5610
5611 if (system_state == SYSTEM_POWER_OFF) {
5612 pci_wake_from_d3(pdev, wake);
5613 pci_set_power_state(pdev, PCI_D3hot);
5614 }
9d5c8243
AK		 5615}
5616
5617#ifdef CONFIG_NET_POLL_CONTROLLER
5618/*
5619 * Polling 'interrupt' - used by things like netconsole to send skbs
5620 * without having to re-enable interrupts. It's not called while
5621 * the interrupt routine is executing.
5622 */
5623static void igb_netpoll(struct net_device *netdev)
5624{
5625 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5626 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5627 int i;
9d5c8243 5628
eebbbdba 5629 if (!adapter->msix_entries) {
047e0030 5630 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5631 igb_irq_disable(adapter);
047e0030 5632 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5633 return;
5634 }
9d5c8243 5635
047e0030
AD		 5636 for (i = 0; i < adapter->num_q_vectors; i++) {
5637 struct igb_q_vector *q_vector = adapter->q_vector[i];
5638 wr32(E1000_EIMC, q_vector->eims_value);
5639 napi_schedule(&q_vector->napi);
eebbbdba 5640 }
9d5c8243
AK		 5641}
5642#endif /* CONFIG_NET_POLL_CONTROLLER */
5643
5644/**
5645 * igb_io_error_detected - called when PCI error is detected
5646 * @pdev: Pointer to PCI device
5647 * @state: The current pci connection state
5648 *
5649 * This function is called after a PCI bus error affecting
5650 * this device has been detected.
5651 */
5652static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5653 pci_channel_state_t state)
5654{
5655 struct net_device *netdev = pci_get_drvdata(pdev);
5656 struct igb_adapter *adapter = netdev_priv(netdev);
5657
5658 netif_device_detach(netdev);
5659
59ed6eec
AD		 5660 if (state == pci_channel_io_perm_failure)
5661 return PCI_ERS_RESULT_DISCONNECT;
5662
9d5c8243
AK		 5663 if (netif_running(netdev))
5664 igb_down(adapter);
5665 pci_disable_device(pdev);
5666
5667 /* Request a slot slot reset. */
5668 return PCI_ERS_RESULT_NEED_RESET;
5669}
5670
5671/**
5672 * igb_io_slot_reset - called after the pci bus has been reset.
5673 * @pdev: Pointer to PCI device
5674 *
5675 * Restart the card from scratch, as if from a cold-boot. Implementation
5676 * resembles the first-half of the igb_resume routine.
5677 */
5678static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5679{
5680 struct net_device *netdev = pci_get_drvdata(pdev);
5681 struct igb_adapter *adapter = netdev_priv(netdev);
5682 struct e1000_hw *hw = &adapter->hw;
40a914fa 5683 pci_ers_result_t result;
42bfd33a 5684 int err;
9d5c8243 5685
aed5dec3 5686 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5687 dev_err(&pdev->dev,
5688 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5689 result = PCI_ERS_RESULT_DISCONNECT;
5690 } else {
5691 pci_set_master(pdev);
5692 pci_restore_state(pdev);
9d5c8243 5693
40a914fa
AD		 5694 pci_enable_wake(pdev, PCI_D3hot, 0);
5695 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5696
40a914fa
AD		 5697 igb_reset(adapter);
5698 wr32(E1000_WUS, ~0);
5699 result = PCI_ERS_RESULT_RECOVERED;
5700 }
9d5c8243 5701
ea943d41
JK		 5702 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5703 if (err) {
5704 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5705 "failed 0x%0x\n", err);
5706 /* non-fatal, continue */
5707 }
40a914fa
AD		 5708
5709 return result;
9d5c8243
AK		 5710}
5711
5712/**
5713 * igb_io_resume - called when traffic can start flowing again.
5714 * @pdev: Pointer to PCI device
5715 *
5716 * This callback is called when the error recovery driver tells us that
5717 * its OK to resume normal operation. Implementation resembles the
5718 * second-half of the igb_resume routine.
5719 */
5720static void igb_io_resume(struct pci_dev *pdev)
5721{
5722 struct net_device *netdev = pci_get_drvdata(pdev);
5723 struct igb_adapter *adapter = netdev_priv(netdev);
5724
9d5c8243
AK		 5725 if (netif_running(netdev)) {
5726 if (igb_up(adapter)) {
5727 dev_err(&pdev->dev, "igb_up failed after reset\n");
5728 return;
5729 }
5730 }
5731
5732 netif_device_attach(netdev);
5733
5734 /* let the f/w know that the h/w is now under the control of the
5735 * driver. */
5736 igb_get_hw_control(adapter);
9d5c8243
AK		 5737}
5738
26ad9178
AD		 5739static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5740 u8 qsel)
5741{
5742 u32 rar_low, rar_high;
5743 struct e1000_hw *hw = &adapter->hw;
5744
5745 /* HW expects these in little endian so we reverse the byte order
5746 * from network order (big endian) to little endian
5747 */
5748 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5749 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5750 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5751
5752 /* Indicate to hardware the Address is Valid. */
5753 rar_high |= E1000_RAH_AV;
5754
5755 if (hw->mac.type == e1000_82575)
5756 rar_high |= E1000_RAH_POOL_1 * qsel;
5757 else
5758 rar_high |= E1000_RAH_POOL_1 << qsel;
5759
5760 wr32(E1000_RAL(index), rar_low);
5761 wrfl();
5762 wr32(E1000_RAH(index), rar_high);
5763 wrfl();
5764}
5765
4ae196df
AD		 5766static int igb_set_vf_mac(struct igb_adapter *adapter,
5767 int vf, unsigned char *mac_addr)
5768{
5769 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5770 /* VF MAC addresses start at end of receive addresses and moves
5771 * torwards the first, as a result a collision should not be possible */
5772 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5773
37680117 5774 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5775
26ad9178 5776 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5777
5778 return 0;
5779}
5780
5781static void igb_vmm_control(struct igb_adapter *adapter)
5782{
5783 struct e1000_hw *hw = &adapter->hw;
5784 u32 reg_data;
5785
5786 if (!adapter->vfs_allocated_count)
5787 return;
5788
5789 /* VF's need PF reset indication before they
5790 * can send/receive mail */
5791 reg_data = rd32(E1000_CTRL_EXT);
5792 reg_data |= E1000_CTRL_EXT_PFRSTD;
5793 wr32(E1000_CTRL_EXT, reg_data);
5794
5795 igb_vmdq_set_loopback_pf(hw, true);
5796 igb_vmdq_set_replication_pf(hw, true);
5797}
5798
9d5c8243 5799/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)