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igb: rework use of VMOLR in regards to PF and VFs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
c8ea5ea9 70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
74 /* required last entry */
75 {0, }
76};
77
78MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
79
80void igb_reset(struct igb_adapter *);
81static int igb_setup_all_tx_resources(struct igb_adapter *);
82static int igb_setup_all_rx_resources(struct igb_adapter *);
83static void igb_free_all_tx_resources(struct igb_adapter *);
84static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 85static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 86void igb_update_stats(struct igb_adapter *);
87static int igb_probe(struct pci_dev *, const struct pci_device_id *);
88static void __devexit igb_remove(struct pci_dev *pdev);
89static int igb_sw_init(struct igb_adapter *);
90static int igb_open(struct net_device *);
91static int igb_close(struct net_device *);
92static void igb_configure_tx(struct igb_adapter *);
93static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 94static void igb_clean_all_tx_rings(struct igb_adapter *);
95static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 96static void igb_clean_tx_ring(struct igb_ring *);
97static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 98static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 99static void igb_update_phy_info(unsigned long);
100static void igb_watchdog(unsigned long);
101static void igb_watchdog_task(struct work_struct *);
b1a436c3 102static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
9d5c8243
AK		 103static struct net_device_stats *igb_get_stats(struct net_device *);
104static int igb_change_mtu(struct net_device *, int);
105static int igb_set_mac(struct net_device *, void *);
68d480c4 106static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 107static irqreturn_t igb_intr(int irq, void *);
108static irqreturn_t igb_intr_msi(int irq, void *);
109static irqreturn_t igb_msix_other(int irq, void *);
047e0030 110static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 111#ifdef CONFIG_IGB_DCA
047e0030 112static void igb_update_dca(struct igb_q_vector *);
fe4506b6 113static void igb_setup_dca(struct igb_adapter *);
421e02f0 114#endif /* CONFIG_IGB_DCA */
047e0030 115static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 116static int igb_poll(struct napi_struct *, int);
047e0030 117static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
26ad9178 125static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 126static void igb_ping_all_vfs(struct igb_adapter *);
127static void igb_msg_task(struct igb_adapter *);
4ae196df 128static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 129static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 130static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 131
9d5c8243 132#ifdef CONFIG_PM
3fe7c4c9 133static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 134static int igb_resume(struct pci_dev *);
135#endif
136static void igb_shutdown(struct pci_dev *);
421e02f0 137#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 138static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
139static struct notifier_block dca_notifier = {
140 .notifier_call = igb_notify_dca,
141 .next = NULL,
142 .priority = 0
143};
144#endif
9d5c8243
AK		 145#ifdef CONFIG_NET_POLL_CONTROLLER
146/* for netdump / net console */
147static void igb_netpoll(struct net_device *);
148#endif
37680117 149#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 150static unsigned int max_vfs = 0;
151module_param(max_vfs, uint, 0);
152MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
153 "per physical function");
154#endif /* CONFIG_PCI_IOV */
155
9d5c8243
AK		 156static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
157 pci_channel_state_t);
158static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
159static void igb_io_resume(struct pci_dev *);
160
161static struct pci_error_handlers igb_err_handler = {
162 .error_detected = igb_io_error_detected,
163 .slot_reset = igb_io_slot_reset,
164 .resume = igb_io_resume,
165};
166
167
168static struct pci_driver igb_driver = {
169 .name = igb_driver_name,
170 .id_table = igb_pci_tbl,
171 .probe = igb_probe,
172 .remove = __devexit_p(igb_remove),
173#ifdef CONFIG_PM
174 /* Power Managment Hooks */
175 .suspend = igb_suspend,
176 .resume = igb_resume,
177#endif
178 .shutdown = igb_shutdown,
179 .err_handler = &igb_err_handler
180};
181
7dfc16fa
AD		 182static int global_quad_port_a; /* global quad port a indication */
183
9d5c8243
AK		 184MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
185MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
186MODULE_LICENSE("GPL");
187MODULE_VERSION(DRV_VERSION);
188
38c845c7
PO		 189/**
190 * igb_read_clock - read raw cycle counter (to be used by time counter)
191 */
192static cycle_t igb_read_clock(const struct cyclecounter *tc)
193{
194 struct igb_adapter *adapter =
195 container_of(tc, struct igb_adapter, cycles);
196 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 197 u64 stamp = 0;
198 int shift = 0;
38c845c7 199
c5b9bd5e
AD		 200 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
201 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 202 return stamp;
203}
204
9d5c8243
AK		 205#ifdef DEBUG
206/**
207 * igb_get_hw_dev_name - return device name string
208 * used by hardware layer to print debugging information
209 **/
210char *igb_get_hw_dev_name(struct e1000_hw *hw)
211{
212 struct igb_adapter *adapter = hw->back;
213 return adapter->netdev->name;
214}
38c845c7
PO		 215
216/**
217 * igb_get_time_str - format current NIC and system time as string
218 */
219static char *igb_get_time_str(struct igb_adapter *adapter,
220 char buffer[160])
221{
222 cycle_t hw = adapter->cycles.read(&adapter->cycles);
223 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
224 struct timespec sys;
225 struct timespec delta;
226 getnstimeofday(&sys);
227
228 delta = timespec_sub(nic, sys);
229
230 sprintf(buffer,
33af6bcc
PO		 231 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
232 hw,
38c845c7
PO		 233 (long)nic.tv_sec, nic.tv_nsec,
234 (long)sys.tv_sec, sys.tv_nsec,
235 (long)delta.tv_sec, delta.tv_nsec);
236
237 return buffer;
238}
9d5c8243
AK		 239#endif
240
241/**
242 * igb_init_module - Driver Registration Routine
243 *
244 * igb_init_module is the first routine called when the driver is
245 * loaded. All it does is register with the PCI subsystem.
246 **/
247static int __init igb_init_module(void)
248{
249 int ret;
250 printk(KERN_INFO "%s - version %s\n",
251 igb_driver_string, igb_driver_version);
252
253 printk(KERN_INFO "%s\n", igb_copyright);
254
7dfc16fa
AD		 255 global_quad_port_a = 0;
256
421e02f0 257#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 258 dca_register_notify(&dca_notifier);
259#endif
bbd98fe4
AD		 260
261 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 262 return ret;
263}
264
265module_init(igb_init_module);
266
267/**
268 * igb_exit_module - Driver Exit Cleanup Routine
269 *
270 * igb_exit_module is called just before the driver is removed
271 * from memory.
272 **/
273static void __exit igb_exit_module(void)
274{
421e02f0 275#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 276 dca_unregister_notify(&dca_notifier);
277#endif
9d5c8243
AK		 278 pci_unregister_driver(&igb_driver);
279}
280
281module_exit(igb_exit_module);
282
26bc19ec
AD		 283#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
284/**
285 * igb_cache_ring_register - Descriptor ring to register mapping
286 * @adapter: board private structure to initialize
287 *
288 * Once we know the feature-set enabled for the device, we'll cache
289 * the register offset the descriptor ring is assigned to.
290 **/
291static void igb_cache_ring_register(struct igb_adapter *adapter)
292{
293 int i;
047e0030 294 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 295
296 switch (adapter->hw.mac.type) {
297 case e1000_82576:
298 /* The queues are allocated for virtualization such that VF 0
299 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
300 * In order to avoid collision we start at the first free queue
301 * and continue consuming queues in the same sequence
302 */
303 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 304 adapter->rx_ring[i].reg_idx = rbase_offset +
305 Q_IDX_82576(i);
26bc19ec 306 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 307 adapter->tx_ring[i].reg_idx = rbase_offset +
308 Q_IDX_82576(i);
26bc19ec
AD		 309 break;
310 case e1000_82575:
311 default:
312 for (i = 0; i < adapter->num_rx_queues; i++)
313 adapter->rx_ring[i].reg_idx = i;
314 for (i = 0; i < adapter->num_tx_queues; i++)
315 adapter->tx_ring[i].reg_idx = i;
316 break;
317 }
318}
319
047e0030
AD		 320static void igb_free_queues(struct igb_adapter *adapter)
321{
322 kfree(adapter->tx_ring);
323 kfree(adapter->rx_ring);
324
325 adapter->tx_ring = NULL;
326 adapter->rx_ring = NULL;
327
328 adapter->num_rx_queues = 0;
329 adapter->num_tx_queues = 0;
330}
331
9d5c8243
AK		 332/**
333 * igb_alloc_queues - Allocate memory for all rings
334 * @adapter: board private structure to initialize
335 *
336 * We allocate one ring per queue at run-time since we don't know the
337 * number of queues at compile-time.
338 **/
339static int igb_alloc_queues(struct igb_adapter *adapter)
340{
341 int i;
342
343 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
344 sizeof(struct igb_ring), GFP_KERNEL);
345 if (!adapter->tx_ring)
047e0030 346 goto err;
9d5c8243
AK		 347
348 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
349 sizeof(struct igb_ring), GFP_KERNEL);
047e0030
AD		 350 if (!adapter->rx_ring)
351 goto err;
6eb5a7f1 352
661086df
PWJ		 353 for (i = 0; i < adapter->num_tx_queues; i++) {
354 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 355 ring->count = adapter->tx_ring_count;
661086df 356 ring->queue_index = i;
80785298 357 ring->pdev = adapter->pdev;
e694e964 358 ring->netdev = adapter->netdev;
85ad76b2
AD		 359 /* For 82575, context index must be unique per ring. */
360 if (adapter->hw.mac.type == e1000_82575)
361 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
661086df 362 }
85ad76b2 363
9d5c8243
AK		 364 for (i = 0; i < adapter->num_rx_queues; i++) {
365 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 366 ring->count = adapter->rx_ring_count;
844290e5 367 ring->queue_index = i;
80785298 368 ring->pdev = adapter->pdev;
e694e964 369 ring->netdev = adapter->netdev;
4c844851 370 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 371 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
372 /* set flag indicating ring supports SCTP checksum offload */
373 if (adapter->hw.mac.type >= e1000_82576)
374 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
9d5c8243 375 }
26bc19ec
AD		 376
377 igb_cache_ring_register(adapter);
9d5c8243 378
047e0030 379 return 0;
a88f10ec 380
047e0030
AD		 381err:
382 igb_free_queues(adapter);
d1a8c9e1 383
047e0030 384 return -ENOMEM;
a88f10ec
AD		 385}
386
9d5c8243 387#define IGB_N0_QUEUE -1
047e0030 388static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 389{
390 u32 msixbm = 0;
047e0030 391 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 392 struct e1000_hw *hw = &adapter->hw;
2d064c06 393 u32 ivar, index;
047e0030
AD		 394 int rx_queue = IGB_N0_QUEUE;
395 int tx_queue = IGB_N0_QUEUE;
396
397 if (q_vector->rx_ring)
398 rx_queue = q_vector->rx_ring->reg_idx;
399 if (q_vector->tx_ring)
400 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 401
402 switch (hw->mac.type) {
403 case e1000_82575:
9d5c8243
AK		 404 /* The 82575 assigns vectors using a bitmask, which matches the
405 bitmask for the EICR/EIMS/EIMC registers. To assign one
406 or more queues to a vector, we write the appropriate bits
407 into the MSIXBM register for that vector. */
047e0030 408 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 409 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 410 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 411 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
9d5c8243 412 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 413 q_vector->eims_value = msixbm;
2d064c06
AD		 414 break;
415 case e1000_82576:
26bc19ec 416 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 417 Each queue has a single entry in the table to which we write
418 a vector number along with a "valid" bit. Sadly, the layout
419 of the table is somewhat counterintuitive. */
420 if (rx_queue > IGB_N0_QUEUE) {
047e0030 421 index = (rx_queue & 0x7);
2d064c06 422 ivar = array_rd32(E1000_IVAR0, index);
047e0030 423 if (rx_queue < 8) {
26bc19ec
AD		 424 /* vector goes into low byte of register */
425 ivar = ivar & 0xFFFFFF00;
426 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 427 } else {
428 /* vector goes into third byte of register */
429 ivar = ivar & 0xFF00FFFF;
430 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 431 }
2d064c06
AD		 432 array_wr32(E1000_IVAR0, index, ivar);
433 }
434 if (tx_queue > IGB_N0_QUEUE) {
047e0030 435 index = (tx_queue & 0x7);
2d064c06 436 ivar = array_rd32(E1000_IVAR0, index);
047e0030 437 if (tx_queue < 8) {
26bc19ec
AD		 438 /* vector goes into second byte of register */
439 ivar = ivar & 0xFFFF00FF;
440 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 441 } else {
442 /* vector goes into high byte of register */
443 ivar = ivar & 0x00FFFFFF;
444 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 445 }
2d064c06
AD		 446 array_wr32(E1000_IVAR0, index, ivar);
447 }
047e0030 448 q_vector->eims_value = 1 << msix_vector;
2d064c06
AD		 449 break;
450 default:
451 BUG();
452 break;
453 }
9d5c8243
AK		 454}
455
456/**
457 * igb_configure_msix - Configure MSI-X hardware
458 *
459 * igb_configure_msix sets up the hardware to properly
460 * generate MSI-X interrupts.
461 **/
462static void igb_configure_msix(struct igb_adapter *adapter)
463{
464 u32 tmp;
465 int i, vector = 0;
466 struct e1000_hw *hw = &adapter->hw;
467
468 adapter->eims_enable_mask = 0;
9d5c8243
AK		 469
470 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 471 switch (hw->mac.type) {
472 case e1000_82575:
9d5c8243
AK		 473 tmp = rd32(E1000_CTRL_EXT);
474 /* enable MSI-X PBA support*/
475 tmp |= E1000_CTRL_EXT_PBA_CLR;
476
477 /* Auto-Mask interrupts upon ICR read. */
478 tmp |= E1000_CTRL_EXT_EIAME;
479 tmp |= E1000_CTRL_EXT_IRCA;
480
481 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 482
483 /* enable msix_other interrupt */
484 array_wr32(E1000_MSIXBM(0), vector++,
485 E1000_EIMS_OTHER);
844290e5 486 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 487
2d064c06
AD		 488 break;
489
490 case e1000_82576:
047e0030
AD		 491 /* Turn on MSI-X capability first, or our settings
492 * won't stick. And it will take days to debug. */
493 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
494 E1000_GPIE_PBA | E1000_GPIE_EIAME |
495 E1000_GPIE_NSICR);
496
497 /* enable msix_other interrupt */
498 adapter->eims_other = 1 << vector;
2d064c06 499 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 500
047e0030 501 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 502 break;
503 default:
504 /* do nothing, since nothing else supports MSI-X */
505 break;
506 } /* switch (hw->mac.type) */
047e0030
AD		 507
508 adapter->eims_enable_mask |= adapter->eims_other;
509
510 for (i = 0; i < adapter->num_q_vectors; i++) {
511 struct igb_q_vector *q_vector = adapter->q_vector[i];
512 igb_assign_vector(q_vector, vector++);
513 adapter->eims_enable_mask |= q_vector->eims_value;
514 }
515
9d5c8243
AK		 516 wrfl();
517}
518
519/**
520 * igb_request_msix - Initialize MSI-X interrupts
521 *
522 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
523 * kernel.
524 **/
525static int igb_request_msix(struct igb_adapter *adapter)
526{
527 struct net_device *netdev = adapter->netdev;
047e0030 528 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 529 int i, err = 0, vector = 0;
530
047e0030
AD		 531 err = request_irq(adapter->msix_entries[vector].vector,
532 &igb_msix_other, 0, netdev->name, adapter);
533 if (err)
534 goto out;
535 vector++;
536
537 for (i = 0; i < adapter->num_q_vectors; i++) {
538 struct igb_q_vector *q_vector = adapter->q_vector[i];
539
540 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
541
542 if (q_vector->rx_ring && q_vector->tx_ring)
543 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
544 q_vector->rx_ring->queue_index);
545 else if (q_vector->tx_ring)
546 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
547 q_vector->tx_ring->queue_index);
548 else if (q_vector->rx_ring)
549 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
550 q_vector->rx_ring->queue_index);
9d5c8243 551 else
047e0030
AD		 552 sprintf(q_vector->name, "%s-unused", netdev->name);
553
9d5c8243 554 err = request_irq(adapter->msix_entries[vector].vector,
047e0030
AD		 555 &igb_msix_ring, 0, q_vector->name,
556 q_vector);
9d5c8243
AK		 557 if (err)
558 goto out;
9d5c8243
AK		 559 vector++;
560 }
561
9d5c8243
AK		 562 igb_configure_msix(adapter);
563 return 0;
564out:
565 return err;
566}
567
568static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
569{
570 if (adapter->msix_entries) {
571 pci_disable_msix(adapter->pdev);
572 kfree(adapter->msix_entries);
573 adapter->msix_entries = NULL;
047e0030 574 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 575 pci_disable_msi(adapter->pdev);
047e0030 576 }
9d5c8243
AK		 577}
578
047e0030
AD		 579/**
580 * igb_free_q_vectors - Free memory allocated for interrupt vectors
581 * @adapter: board private structure to initialize
582 *
583 * This function frees the memory allocated to the q_vectors. In addition if
584 * NAPI is enabled it will delete any references to the NAPI struct prior
585 * to freeing the q_vector.
586 **/
587static void igb_free_q_vectors(struct igb_adapter *adapter)
588{
589 int v_idx;
590
591 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
592 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
593 adapter->q_vector[v_idx] = NULL;
594 netif_napi_del(&q_vector->napi);
595 kfree(q_vector);
596 }
597 adapter->num_q_vectors = 0;
598}
599
600/**
601 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
602 *
603 * This function resets the device so that it has 0 rx queues, tx queues, and
604 * MSI-X interrupts allocated.
605 */
606static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
607{
608 igb_free_queues(adapter);
609 igb_free_q_vectors(adapter);
610 igb_reset_interrupt_capability(adapter);
611}
9d5c8243
AK		 612
613/**
614 * igb_set_interrupt_capability - set MSI or MSI-X if supported
615 *
616 * Attempt to configure interrupts using the best available
617 * capabilities of the hardware and kernel.
618 **/
619static void igb_set_interrupt_capability(struct igb_adapter *adapter)
620{
621 int err;
622 int numvecs, i;
623
83b7180d 624 /* Number of supported queues. */
83b7180d
AD		 625 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
626 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
627
047e0030
AD		 628 /* start with one vector for every rx queue */
629 numvecs = adapter->num_rx_queues;
630
631 /* if tx handler is seperate add 1 for every tx queue */
632 numvecs += adapter->num_tx_queues;
633
634 /* store the number of vectors reserved for queues */
635 adapter->num_q_vectors = numvecs;
636
637 /* add 1 vector for link status interrupts */
638 numvecs++;
9d5c8243
AK		 639 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
640 GFP_KERNEL);
641 if (!adapter->msix_entries)
642 goto msi_only;
643
644 for (i = 0; i < numvecs; i++)
645 adapter->msix_entries[i].entry = i;
646
647 err = pci_enable_msix(adapter->pdev,
648 adapter->msix_entries,
649 numvecs);
650 if (err == 0)
34a20e89 651 goto out;
9d5c8243
AK		 652
653 igb_reset_interrupt_capability(adapter);
654
655 /* If we can't do MSI-X, try MSI */
656msi_only:
2a3abf6d
AD		 657#ifdef CONFIG_PCI_IOV
658 /* disable SR-IOV for non MSI-X configurations */
659 if (adapter->vf_data) {
660 struct e1000_hw *hw = &adapter->hw;
661 /* disable iov and allow time for transactions to clear */
662 pci_disable_sriov(adapter->pdev);
663 msleep(500);
664
665 kfree(adapter->vf_data);
666 adapter->vf_data = NULL;
667 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
668 msleep(100);
669 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
670 }
671#endif
4fc82adf
AD		 672 adapter->vfs_allocated_count = 0;
673 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 674 adapter->num_rx_queues = 1;
661086df 675 adapter->num_tx_queues = 1;
047e0030 676 adapter->num_q_vectors = 1;
9d5c8243 677 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 678 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 679out:
661086df 680 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 681 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 682 return;
683}
684
047e0030
AD		 685/**
686 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
687 * @adapter: board private structure to initialize
688 *
689 * We allocate one q_vector per queue interrupt. If allocation fails we
690 * return -ENOMEM.
691 **/
692static int igb_alloc_q_vectors(struct igb_adapter *adapter)
693{
694 struct igb_q_vector *q_vector;
695 struct e1000_hw *hw = &adapter->hw;
696 int v_idx;
697
698 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
699 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
700 if (!q_vector)
701 goto err_out;
702 q_vector->adapter = adapter;
703 q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0;
704 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
705 q_vector->itr_val = IGB_START_ITR;
706 q_vector->set_itr = 1;
707 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
708 adapter->q_vector[v_idx] = q_vector;
709 }
710 return 0;
711
712err_out:
713 while (v_idx) {
714 v_idx--;
715 q_vector = adapter->q_vector[v_idx];
716 netif_napi_del(&q_vector->napi);
717 kfree(q_vector);
718 adapter->q_vector[v_idx] = NULL;
719 }
720 return -ENOMEM;
721}
722
723static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
724 int ring_idx, int v_idx)
725{
726 struct igb_q_vector *q_vector;
727
728 q_vector = adapter->q_vector[v_idx];
729 q_vector->rx_ring = &adapter->rx_ring[ring_idx];
730 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 731 q_vector->itr_val = adapter->rx_itr_setting;
732 if (q_vector->itr_val && q_vector->itr_val <= 3)
733 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 734}
735
736static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
737 int ring_idx, int v_idx)
738{
739 struct igb_q_vector *q_vector;
740
741 q_vector = adapter->q_vector[v_idx];
742 q_vector->tx_ring = &adapter->tx_ring[ring_idx];
743 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 744 q_vector->itr_val = adapter->tx_itr_setting;
745 if (q_vector->itr_val && q_vector->itr_val <= 3)
746 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 747}
748
749/**
750 * igb_map_ring_to_vector - maps allocated queues to vectors
751 *
752 * This function maps the recently allocated queues to vectors.
753 **/
754static int igb_map_ring_to_vector(struct igb_adapter *adapter)
755{
756 int i;
757 int v_idx = 0;
758
759 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
760 (adapter->num_q_vectors < adapter->num_tx_queues))
761 return -ENOMEM;
762
763 if (adapter->num_q_vectors >=
764 (adapter->num_rx_queues + adapter->num_tx_queues)) {
765 for (i = 0; i < adapter->num_rx_queues; i++)
766 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
767 for (i = 0; i < adapter->num_tx_queues; i++)
768 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
769 } else {
770 for (i = 0; i < adapter->num_rx_queues; i++) {
771 if (i < adapter->num_tx_queues)
772 igb_map_tx_ring_to_vector(adapter, i, v_idx);
773 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
774 }
775 for (; i < adapter->num_tx_queues; i++)
776 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
777 }
778 return 0;
779}
780
781/**
782 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
783 *
784 * This function initializes the interrupts and allocates all of the queues.
785 **/
786static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
787{
788 struct pci_dev *pdev = adapter->pdev;
789 int err;
790
791 igb_set_interrupt_capability(adapter);
792
793 err = igb_alloc_q_vectors(adapter);
794 if (err) {
795 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
796 goto err_alloc_q_vectors;
797 }
798
799 err = igb_alloc_queues(adapter);
800 if (err) {
801 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
802 goto err_alloc_queues;
803 }
804
805 err = igb_map_ring_to_vector(adapter);
806 if (err) {
807 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
808 goto err_map_queues;
809 }
810
811
812 return 0;
813err_map_queues:
814 igb_free_queues(adapter);
815err_alloc_queues:
816 igb_free_q_vectors(adapter);
817err_alloc_q_vectors:
818 igb_reset_interrupt_capability(adapter);
819 return err;
820}
821
9d5c8243
AK		 822/**
823 * igb_request_irq - initialize interrupts
824 *
825 * Attempts to configure interrupts using the best available
826 * capabilities of the hardware and kernel.
827 **/
828static int igb_request_irq(struct igb_adapter *adapter)
829{
830 struct net_device *netdev = adapter->netdev;
047e0030 831 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 832 struct e1000_hw *hw = &adapter->hw;
833 int err = 0;
834
835 if (adapter->msix_entries) {
836 err = igb_request_msix(adapter);
844290e5 837 if (!err)
9d5c8243 838 goto request_done;
9d5c8243 839 /* fall back to MSI */
047e0030 840 igb_clear_interrupt_scheme(adapter);
9d5c8243 841 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 842 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 843 igb_free_all_tx_resources(adapter);
844 igb_free_all_rx_resources(adapter);
047e0030 845 adapter->num_tx_queues = 1;
9d5c8243 846 adapter->num_rx_queues = 1;
047e0030
AD		 847 adapter->num_q_vectors = 1;
848 err = igb_alloc_q_vectors(adapter);
849 if (err) {
850 dev_err(&pdev->dev,
851 "Unable to allocate memory for vectors\n");
852 goto request_done;
853 }
854 err = igb_alloc_queues(adapter);
855 if (err) {
856 dev_err(&pdev->dev,
857 "Unable to allocate memory for queues\n");
858 igb_free_q_vectors(adapter);
859 goto request_done;
860 }
861 igb_setup_all_tx_resources(adapter);
862 igb_setup_all_rx_resources(adapter);
844290e5 863 } else {
2d064c06
AD		 864 switch (hw->mac.type) {
865 case e1000_82575:
866 wr32(E1000_MSIXBM(0),
047e0030
AD		 867 (E1000_EICR_RX_QUEUE0 |
868 E1000_EICR_TX_QUEUE0 |
869 E1000_EIMS_OTHER));
2d064c06
AD		 870 break;
871 case e1000_82576:
872 wr32(E1000_IVAR0, E1000_IVAR_VALID);
873 break;
874 default:
875 break;
876 }
9d5c8243 877 }
844290e5 878
7dfc16fa 879 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 880 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
047e0030 881 netdev->name, adapter);
9d5c8243
AK		 882 if (!err)
883 goto request_done;
047e0030 884
9d5c8243
AK		 885 /* fall back to legacy interrupts */
886 igb_reset_interrupt_capability(adapter);
7dfc16fa 887 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 888 }
889
890 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
047e0030 891 netdev->name, adapter);
9d5c8243 892
6cb5e577 893 if (err)
9d5c8243
AK		 894 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
895 err);
9d5c8243
AK		 896
897request_done:
898 return err;
899}
900
901static void igb_free_irq(struct igb_adapter *adapter)
902{
9d5c8243
AK		 903 if (adapter->msix_entries) {
904 int vector = 0, i;
905
047e0030 906 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 907
047e0030
AD		 908 for (i = 0; i < adapter->num_q_vectors; i++) {
909 struct igb_q_vector *q_vector = adapter->q_vector[i];
910 free_irq(adapter->msix_entries[vector++].vector,
911 q_vector);
912 }
913 } else {
914 free_irq(adapter->pdev->irq, adapter);
9d5c8243 915 }
9d5c8243
AK		 916}
917
918/**
919 * igb_irq_disable - Mask off interrupt generation on the NIC
920 * @adapter: board private structure
921 **/
922static void igb_irq_disable(struct igb_adapter *adapter)
923{
924 struct e1000_hw *hw = &adapter->hw;
925
926 if (adapter->msix_entries) {
2dfd1212
AD		 927 u32 regval = rd32(E1000_EIAM);
928 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
929 wr32(E1000_EIMC, adapter->eims_enable_mask);
930 regval = rd32(E1000_EIAC);
931 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 932 }
844290e5
PW		 933
934 wr32(E1000_IAM, 0);
9d5c8243
AK		 935 wr32(E1000_IMC, ~0);
936 wrfl();
937 synchronize_irq(adapter->pdev->irq);
938}
939
940/**
941 * igb_irq_enable - Enable default interrupt generation settings
942 * @adapter: board private structure
943 **/
944static void igb_irq_enable(struct igb_adapter *adapter)
945{
946 struct e1000_hw *hw = &adapter->hw;
947
948 if (adapter->msix_entries) {
2dfd1212
AD		 949 u32 regval = rd32(E1000_EIAC);
950 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
951 regval = rd32(E1000_EIAM);
952 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 953 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 954 if (adapter->vfs_allocated_count)
955 wr32(E1000_MBVFIMR, 0xFF);
956 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
957 E1000_IMS_DOUTSYNC));
844290e5
PW		 958 } else {
959 wr32(E1000_IMS, IMS_ENABLE_MASK);
960 wr32(E1000_IAM, IMS_ENABLE_MASK);
961 }
9d5c8243
AK		 962}
963
964static void igb_update_mng_vlan(struct igb_adapter *adapter)
965{
966 struct net_device *netdev = adapter->netdev;
967 u16 vid = adapter->hw.mng_cookie.vlan_id;
968 u16 old_vid = adapter->mng_vlan_id;
969 if (adapter->vlgrp) {
970 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
971 if (adapter->hw.mng_cookie.status &
972 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
973 igb_vlan_rx_add_vid(netdev, vid);
974 adapter->mng_vlan_id = vid;
975 } else
976 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
977
978 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
979 (vid != old_vid) &&
980 !vlan_group_get_device(adapter->vlgrp, old_vid))
981 igb_vlan_rx_kill_vid(netdev, old_vid);
982 } else
983 adapter->mng_vlan_id = vid;
984 }
985}
986
987/**
988 * igb_release_hw_control - release control of the h/w to f/w
989 * @adapter: address of board private structure
990 *
991 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
992 * For ASF and Pass Through versions of f/w this means that the
993 * driver is no longer loaded.
994 *
995 **/
996static void igb_release_hw_control(struct igb_adapter *adapter)
997{
998 struct e1000_hw *hw = &adapter->hw;
999 u32 ctrl_ext;
1000
1001 /* Let firmware take over control of h/w */
1002 ctrl_ext = rd32(E1000_CTRL_EXT);
1003 wr32(E1000_CTRL_EXT,
1004 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1005}
1006
1007
1008/**
1009 * igb_get_hw_control - get control of the h/w from f/w
1010 * @adapter: address of board private structure
1011 *
1012 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1013 * For ASF and Pass Through versions of f/w this means that
1014 * the driver is loaded.
1015 *
1016 **/
1017static void igb_get_hw_control(struct igb_adapter *adapter)
1018{
1019 struct e1000_hw *hw = &adapter->hw;
1020 u32 ctrl_ext;
1021
1022 /* Let firmware know the driver has taken over */
1023 ctrl_ext = rd32(E1000_CTRL_EXT);
1024 wr32(E1000_CTRL_EXT,
1025 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1026}
1027
9d5c8243
AK		 1028/**
1029 * igb_configure - configure the hardware for RX and TX
1030 * @adapter: private board structure
1031 **/
1032static void igb_configure(struct igb_adapter *adapter)
1033{
1034 struct net_device *netdev = adapter->netdev;
1035 int i;
1036
1037 igb_get_hw_control(adapter);
ff41f8dc 1038 igb_set_rx_mode(netdev);
9d5c8243
AK		 1039
1040 igb_restore_vlan(adapter);
9d5c8243 1041
85b430b4 1042 igb_setup_tctl(adapter);
06cf2666 1043 igb_setup_mrqc(adapter);
9d5c8243 1044 igb_setup_rctl(adapter);
85b430b4
AD		 1045
1046 igb_configure_tx(adapter);
9d5c8243 1047 igb_configure_rx(adapter);
662d7205
AD		 1048
1049 igb_rx_fifo_flush_82575(&adapter->hw);
1050
c493ea45 1051 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1052 * at least 1 descriptor unused to make sure
1053 * next_to_use != next_to_clean */
1054 for (i = 0; i < adapter->num_rx_queues; i++) {
1055 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 1056 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 1057 }
1058
1059
1060 adapter->tx_queue_len = netdev->tx_queue_len;
1061}
1062
1063
1064/**
1065 * igb_up - Open the interface and prepare it to handle traffic
1066 * @adapter: board private structure
1067 **/
1068
1069int igb_up(struct igb_adapter *adapter)
1070{
1071 struct e1000_hw *hw = &adapter->hw;
1072 int i;
1073
1074 /* hardware has been reset, we need to reload some things */
1075 igb_configure(adapter);
1076
1077 clear_bit(__IGB_DOWN, &adapter->state);
1078
047e0030
AD		 1079 for (i = 0; i < adapter->num_q_vectors; i++) {
1080 struct igb_q_vector *q_vector = adapter->q_vector[i];
1081 napi_enable(&q_vector->napi);
1082 }
844290e5 1083 if (adapter->msix_entries)
9d5c8243 1084 igb_configure_msix(adapter);
9d5c8243
AK		 1085
1086 /* Clear any pending interrupts. */
1087 rd32(E1000_ICR);
1088 igb_irq_enable(adapter);
1089
d4960307
AD		 1090 /* notify VFs that reset has been completed */
1091 if (adapter->vfs_allocated_count) {
1092 u32 reg_data = rd32(E1000_CTRL_EXT);
1093 reg_data |= E1000_CTRL_EXT_PFRSTD;
1094 wr32(E1000_CTRL_EXT, reg_data);
1095 }
1096
4cb9be7a
JB		 1097 netif_tx_start_all_queues(adapter->netdev);
1098
9d5c8243
AK		 1099 /* Fire a link change interrupt to start the watchdog. */
1100 wr32(E1000_ICS, E1000_ICS_LSC);
1101 return 0;
1102}
1103
1104void igb_down(struct igb_adapter *adapter)
1105{
1106 struct e1000_hw *hw = &adapter->hw;
1107 struct net_device *netdev = adapter->netdev;
1108 u32 tctl, rctl;
1109 int i;
1110
1111 /* signal that we're down so the interrupt handler does not
1112 * reschedule our watchdog timer */
1113 set_bit(__IGB_DOWN, &adapter->state);
1114
1115 /* disable receives in the hardware */
1116 rctl = rd32(E1000_RCTL);
1117 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1118 /* flush and sleep below */
1119
fd2ea0a7 1120 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1121
1122 /* disable transmits in the hardware */
1123 tctl = rd32(E1000_TCTL);
1124 tctl &= ~E1000_TCTL_EN;
1125 wr32(E1000_TCTL, tctl);
1126 /* flush both disables and wait for them to finish */
1127 wrfl();
1128 msleep(10);
1129
047e0030
AD		 1130 for (i = 0; i < adapter->num_q_vectors; i++) {
1131 struct igb_q_vector *q_vector = adapter->q_vector[i];
1132 napi_disable(&q_vector->napi);
1133 }
9d5c8243 1134
9d5c8243
AK		 1135 igb_irq_disable(adapter);
1136
1137 del_timer_sync(&adapter->watchdog_timer);
1138 del_timer_sync(&adapter->phy_info_timer);
1139
1140 netdev->tx_queue_len = adapter->tx_queue_len;
1141 netif_carrier_off(netdev);
04fe6358
AD		 1142
1143 /* record the stats before reset*/
1144 igb_update_stats(adapter);
1145
9d5c8243
AK		 1146 adapter->link_speed = 0;
1147 adapter->link_duplex = 0;
1148
3023682e
JK		 1149 if (!pci_channel_offline(adapter->pdev))
1150 igb_reset(adapter);
9d5c8243
AK		 1151 igb_clean_all_tx_rings(adapter);
1152 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1153#ifdef CONFIG_IGB_DCA
1154
1155 /* since we reset the hardware DCA settings were cleared */
1156 igb_setup_dca(adapter);
1157#endif
9d5c8243
AK		 1158}
1159
1160void igb_reinit_locked(struct igb_adapter *adapter)
1161{
1162 WARN_ON(in_interrupt());
1163 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1164 msleep(1);
1165 igb_down(adapter);
1166 igb_up(adapter);
1167 clear_bit(__IGB_RESETTING, &adapter->state);
1168}
1169
1170void igb_reset(struct igb_adapter *adapter)
1171{
1172 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1173 struct e1000_mac_info *mac = &hw->mac;
1174 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1175 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1176 u16 hwm;
1177
1178 /* Repartition Pba for greater than 9k mtu
1179 * To take effect CTRL.RST is required.
1180 */
fa4dfae0
AD		 1181 switch (mac->type) {
1182 case e1000_82576:
d249be54
AD		 1183 pba = rd32(E1000_RXPBS);
1184 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1185 break;
1186 case e1000_82575:
1187 default:
1188 pba = E1000_PBA_34K;
1189 break;
2d064c06 1190 }
9d5c8243 1191
2d064c06
AD		 1192 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1193 (mac->type < e1000_82576)) {
9d5c8243
AK		 1194 /* adjust PBA for jumbo frames */
1195 wr32(E1000_PBA, pba);
1196
1197 /* To maintain wire speed transmits, the Tx FIFO should be
1198 * large enough to accommodate two full transmit packets,
1199 * rounded up to the next 1KB and expressed in KB. Likewise,
1200 * the Rx FIFO should be large enough to accommodate at least
1201 * one full receive packet and is similarly rounded up and
1202 * expressed in KB. */
1203 pba = rd32(E1000_PBA);
1204 /* upper 16 bits has Tx packet buffer allocation size in KB */
1205 tx_space = pba >> 16;
1206 /* lower 16 bits has Rx packet buffer allocation size in KB */
1207 pba &= 0xffff;
1208 /* the tx fifo also stores 16 bytes of information about the tx
1209 * but don't include ethernet FCS because hardware appends it */
1210 min_tx_space = (adapter->max_frame_size +
85e8d004 1211 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1212 ETH_FCS_LEN) * 2;
1213 min_tx_space = ALIGN(min_tx_space, 1024);
1214 min_tx_space >>= 10;
1215 /* software strips receive CRC, so leave room for it */
1216 min_rx_space = adapter->max_frame_size;
1217 min_rx_space = ALIGN(min_rx_space, 1024);
1218 min_rx_space >>= 10;
1219
1220 /* If current Tx allocation is less than the min Tx FIFO size,
1221 * and the min Tx FIFO size is less than the current Rx FIFO
1222 * allocation, take space away from current Rx allocation */
1223 if (tx_space < min_tx_space &&
1224 ((min_tx_space - tx_space) < pba)) {
1225 pba = pba - (min_tx_space - tx_space);
1226
1227 /* if short on rx space, rx wins and must trump tx
1228 * adjustment */
1229 if (pba < min_rx_space)
1230 pba = min_rx_space;
1231 }
2d064c06 1232 wr32(E1000_PBA, pba);
9d5c8243 1233 }
9d5c8243
AK		 1234
1235 /* flow control settings */
1236 /* The high water mark must be low enough to fit one full frame
1237 * (or the size used for early receive) above it in the Rx FIFO.
1238 * Set it to the lower of:
1239 * - 90% of the Rx FIFO size, or
1240 * - the full Rx FIFO size minus one full frame */
1241 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1242 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1243
2d064c06
AD		 1244 if (mac->type < e1000_82576) {
1245 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1246 fc->low_water = fc->high_water - 8;
1247 } else {
1248 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1249 fc->low_water = fc->high_water - 16;
1250 }
9d5c8243
AK		 1251 fc->pause_time = 0xFFFF;
1252 fc->send_xon = 1;
0cce119a 1253 fc->current_mode = fc->requested_mode;
9d5c8243 1254
4ae196df
AD		 1255 /* disable receive for all VFs and wait one second */
1256 if (adapter->vfs_allocated_count) {
1257 int i;
1258 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
f2ca0dbe 1259 adapter->vf_data[i].flags = 0;
4ae196df
AD		 1260
1261 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1262 igb_ping_all_vfs(adapter);
4ae196df
AD		 1263
1264 /* disable transmits and receives */
1265 wr32(E1000_VFRE, 0);
1266 wr32(E1000_VFTE, 0);
1267 }
1268
9d5c8243
AK		 1269 /* Allow time for pending master requests to run */
1270 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1271 wr32(E1000_WUC, 0);
1272
1273 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1274 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1275
1276 igb_update_mng_vlan(adapter);
1277
1278 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1279 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1280
1281 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1282 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1283}
1284
2e5c6922
SH		 1285static const struct net_device_ops igb_netdev_ops = {
1286 .ndo_open = igb_open,
1287 .ndo_stop = igb_close,
00829823 1288 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922 1289 .ndo_get_stats = igb_get_stats,
ff41f8dc
AD		 1290 .ndo_set_rx_mode = igb_set_rx_mode,
1291 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1292 .ndo_set_mac_address = igb_set_mac,
1293 .ndo_change_mtu = igb_change_mtu,
1294 .ndo_do_ioctl = igb_ioctl,
1295 .ndo_tx_timeout = igb_tx_timeout,
1296 .ndo_validate_addr = eth_validate_addr,
1297 .ndo_vlan_rx_register = igb_vlan_rx_register,
1298 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1299 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1300#ifdef CONFIG_NET_POLL_CONTROLLER
1301 .ndo_poll_controller = igb_netpoll,
1302#endif
1303};
1304
9d5c8243
AK		 1305/**
1306 * igb_probe - Device Initialization Routine
1307 * @pdev: PCI device information struct
1308 * @ent: entry in igb_pci_tbl
1309 *
1310 * Returns 0 on success, negative on failure
1311 *
1312 * igb_probe initializes an adapter identified by a pci_dev structure.
1313 * The OS initialization, configuring of the adapter private structure,
1314 * and a hardware reset occur.
1315 **/
1316static int __devinit igb_probe(struct pci_dev *pdev,
1317 const struct pci_device_id *ent)
1318{
1319 struct net_device *netdev;
1320 struct igb_adapter *adapter;
1321 struct e1000_hw *hw;
1322 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1323 unsigned long mmio_start, mmio_len;
2d6a5e95 1324 int err, pci_using_dac;
682337fe 1325 u16 eeprom_data = 0;
9d5c8243
AK		 1326 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1327 u32 part_num;
1328
aed5dec3 1329 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1330 if (err)
1331 return err;
1332
1333 pci_using_dac = 0;
6a35528a 1334 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1335 if (!err) {
6a35528a 1336 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1337 if (!err)
1338 pci_using_dac = 1;
1339 } else {
284901a9 1340 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1341 if (err) {
284901a9 1342 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1343 if (err) {
1344 dev_err(&pdev->dev, "No usable DMA "
1345 "configuration, aborting\n");
1346 goto err_dma;
1347 }
1348 }
1349 }
1350
aed5dec3
AD		 1351 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1352 IORESOURCE_MEM),
1353 igb_driver_name);
9d5c8243
AK		 1354 if (err)
1355 goto err_pci_reg;
1356
19d5afd4 1357 pci_enable_pcie_error_reporting(pdev);
40a914fa 1358
9d5c8243 1359 pci_set_master(pdev);
c682fc23 1360 pci_save_state(pdev);
9d5c8243
AK		 1361
1362 err = -ENOMEM;
1bfaf07b
AD		 1363 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1364 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1365 if (!netdev)
1366 goto err_alloc_etherdev;
1367
1368 SET_NETDEV_DEV(netdev, &pdev->dev);
1369
1370 pci_set_drvdata(pdev, netdev);
1371 adapter = netdev_priv(netdev);
1372 adapter->netdev = netdev;
1373 adapter->pdev = pdev;
1374 hw = &adapter->hw;
1375 hw->back = adapter;
1376 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1377
1378 mmio_start = pci_resource_start(pdev, 0);
1379 mmio_len = pci_resource_len(pdev, 0);
1380
1381 err = -EIO;
28b0759c
AD		 1382 hw->hw_addr = ioremap(mmio_start, mmio_len);
1383 if (!hw->hw_addr)
9d5c8243
AK		 1384 goto err_ioremap;
1385
2e5c6922 1386 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1387 igb_set_ethtool_ops(netdev);
9d5c8243 1388 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1389
1390 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1391
1392 netdev->mem_start = mmio_start;
1393 netdev->mem_end = mmio_start + mmio_len;
1394
9d5c8243
AK		 1395 /* PCI config space info */
1396 hw->vendor_id = pdev->vendor;
1397 hw->device_id = pdev->device;
1398 hw->revision_id = pdev->revision;
1399 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1400 hw->subsystem_device_id = pdev->subsystem_device;
1401
1402 /* setup the private structure */
1403 hw->back = adapter;
1404 /* Copy the default MAC, PHY and NVM function pointers */
1405 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1406 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1407 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1408 /* Initialize skew-specific constants */
1409 err = ei->get_invariants(hw);
1410 if (err)
450c87c8 1411 goto err_sw_init;
9d5c8243 1412
2a3abf6d
AD		 1413#ifdef CONFIG_PCI_IOV
1414 /* since iov functionality isn't critical to base device function we
1415 * can accept failure. If it fails we don't allow iov to be enabled */
1416 if (hw->mac.type == e1000_82576) {
1417 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1418 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1419 int i;
1420 unsigned char mac_addr[ETH_ALEN];
1421
9ca046d5 1422 if (num_vfs) {
2a3abf6d
AD		 1423 adapter->vf_data = kcalloc(num_vfs,
1424 sizeof(struct vf_data_storage),
1425 GFP_KERNEL);
9ca046d5
AD		 1426 if (!adapter->vf_data) {
1427 dev_err(&pdev->dev,
1428 "Could not allocate VF private data - "
1429 "IOV enable failed\n");
2a3abf6d 1430 } else {
9ca046d5
AD		 1431 err = pci_enable_sriov(pdev, num_vfs);
1432 if (!err) {
1433 adapter->vfs_allocated_count = num_vfs;
1434 dev_info(&pdev->dev,
1435 "%d vfs allocated\n",
1436 num_vfs);
1437 for (i = 0;
1438 i < adapter->vfs_allocated_count;
1439 i++) {
1440 random_ether_addr(mac_addr);
1441 igb_set_vf_mac(adapter, i,
1442 mac_addr);
1443 }
1444 } else {
1445 kfree(adapter->vf_data);
1446 adapter->vf_data = NULL;
1447 }
2a3abf6d
AD		 1448 }
1449 }
1450 }
1451
1452#endif
450c87c8 1453 /* setup the private structure */
9d5c8243
AK		 1454 err = igb_sw_init(adapter);
1455 if (err)
1456 goto err_sw_init;
1457
1458 igb_get_bus_info_pcie(hw);
1459
1460 hw->phy.autoneg_wait_to_complete = false;
1461 hw->mac.adaptive_ifs = true;
1462
1463 /* Copper options */
1464 if (hw->phy.media_type == e1000_media_type_copper) {
1465 hw->phy.mdix = AUTO_ALL_MODES;
1466 hw->phy.disable_polarity_correction = false;
1467 hw->phy.ms_type = e1000_ms_hw_default;
1468 }
1469
1470 if (igb_check_reset_block(hw))
1471 dev_info(&pdev->dev,
1472 "PHY reset is blocked due to SOL/IDER session.\n");
1473
1474 netdev->features = NETIF_F_SG |
7d8eb29e 1475 NETIF_F_IP_CSUM |
9d5c8243
AK		 1476 NETIF_F_HW_VLAN_TX |
1477 NETIF_F_HW_VLAN_RX |
1478 NETIF_F_HW_VLAN_FILTER;
1479
7d8eb29e 1480 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1481 netdev->features |= NETIF_F_TSO;
9d5c8243 1482 netdev->features |= NETIF_F_TSO6;
48f29ffc 1483
5c0999b7 1484 netdev->features |= NETIF_F_GRO;
d3352520 1485
48f29ffc
JK		 1486 netdev->vlan_features |= NETIF_F_TSO;
1487 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1488 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1489 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1490 netdev->vlan_features |= NETIF_F_SG;
1491
9d5c8243
AK		 1492 if (pci_using_dac)
1493 netdev->features |= NETIF_F_HIGHDMA;
1494
b9473560
JB		 1495 if (adapter->hw.mac.type == e1000_82576)
1496 netdev->features |= NETIF_F_SCTP_CSUM;
1497
9d5c8243
AK		 1498 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1499
1500 /* before reading the NVM, reset the controller to put the device in a
1501 * known good starting state */
1502 hw->mac.ops.reset_hw(hw);
1503
1504 /* make sure the NVM is good */
1505 if (igb_validate_nvm_checksum(hw) < 0) {
1506 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1507 err = -EIO;
1508 goto err_eeprom;
1509 }
1510
1511 /* copy the MAC address out of the NVM */
1512 if (hw->mac.ops.read_mac_addr(hw))
1513 dev_err(&pdev->dev, "NVM Read Error\n");
1514
1515 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1516 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1517
1518 if (!is_valid_ether_addr(netdev->perm_addr)) {
1519 dev_err(&pdev->dev, "Invalid MAC Address\n");
1520 err = -EIO;
1521 goto err_eeprom;
1522 }
1523
0e340485
AD		 1524 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1525 (unsigned long) adapter);
1526 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1527 (unsigned long) adapter);
9d5c8243
AK		 1528
1529 INIT_WORK(&adapter->reset_task, igb_reset_task);
1530 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1531
450c87c8 1532 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1533 adapter->fc_autoneg = true;
1534 hw->mac.autoneg = true;
1535 hw->phy.autoneg_advertised = 0x2f;
1536
0cce119a
AD		 1537 hw->fc.requested_mode = e1000_fc_default;
1538 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1539
9d5c8243
AK		 1540 igb_validate_mdi_setting(hw);
1541
9d5c8243
AK		 1542 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1543 * enable the ACPI Magic Packet filter
1544 */
1545
a2cf8b6c 1546 if (hw->bus.func == 0)
312c75ae 1547 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1548 else if (hw->bus.func == 1)
1549 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1550
1551 if (eeprom_data & eeprom_apme_mask)
1552 adapter->eeprom_wol |= E1000_WUFC_MAG;
1553
1554 /* now that we have the eeprom settings, apply the special cases where
1555 * the eeprom may be wrong or the board simply won't support wake on
1556 * lan on a particular port */
1557 switch (pdev->device) {
1558 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1559 adapter->eeprom_wol = 0;
1560 break;
1561 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1562 case E1000_DEV_ID_82576_FIBER:
1563 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1564 /* Wake events only supported on port A for dual fiber
1565 * regardless of eeprom setting */
1566 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1567 adapter->eeprom_wol = 0;
1568 break;
c8ea5ea9
AD		 1569 case E1000_DEV_ID_82576_QUAD_COPPER:
1570 /* if quad port adapter, disable WoL on all but port A */
1571 if (global_quad_port_a != 0)
1572 adapter->eeprom_wol = 0;
1573 else
1574 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1575 /* Reset for multiple quad port adapters */
1576 if (++global_quad_port_a == 4)
1577 global_quad_port_a = 0;
1578 break;
9d5c8243
AK		 1579 }
1580
1581 /* initialize the wol settings based on the eeprom settings */
1582 adapter->wol = adapter->eeprom_wol;
e1b86d84 1583 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1584
1585 /* reset the hardware with the new settings */
1586 igb_reset(adapter);
1587
1588 /* let the f/w know that the h/w is now under the control of the
1589 * driver. */
1590 igb_get_hw_control(adapter);
1591
9d5c8243
AK		 1592 strcpy(netdev->name, "eth%d");
1593 err = register_netdev(netdev);
1594 if (err)
1595 goto err_register;
1596
b168dfc5
JB		 1597 /* carrier off reporting is important to ethtool even BEFORE open */
1598 netif_carrier_off(netdev);
1599
421e02f0 1600#ifdef CONFIG_IGB_DCA
bbd98fe4 1601 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1602 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1603 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1604 igb_setup_dca(adapter);
1605 }
fe4506b6 1606
38c845c7 1607#endif
38c845c7 1608
c5b9bd5e
AD		 1609 switch (hw->mac.type) {
1610 case e1000_82576:
1611 /*
1612 * Initialize hardware timer: we keep it running just in case
1613 * that some program needs it later on.
1614 */
1615 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1616 adapter->cycles.read = igb_read_clock;
1617 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1618 adapter->cycles.mult = 1;
1619 /**
1620 * Scale the NIC clock cycle by a large factor so that
1621 * relatively small clock corrections can be added or
1622 * substracted at each clock tick. The drawbacks of a large
1623 * factor are a) that the clock register overflows more quickly
1624 * (not such a big deal) and b) that the increment per tick has
1625 * to fit into 24 bits. As a result we need to use a shift of
1626 * 19 so we can fit a value of 16 into the TIMINCA register.
1627 */
1628 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
1629 wr32(E1000_TIMINCA,
1630 (1 << E1000_TIMINCA_16NS_SHIFT) |
1631 (16 << IGB_82576_TSYNC_SHIFT));
1632
1633 /* Set registers so that rollover occurs soon to test this. */
1634 wr32(E1000_SYSTIML, 0x00000000);
1635 wr32(E1000_SYSTIMH, 0xFF800000);
1636 wrfl();
1637
1638 timecounter_init(&adapter->clock,
1639 &adapter->cycles,
1640 ktime_to_ns(ktime_get_real()));
1641 /*
1642 * Synchronize our NIC clock against system wall clock. NIC
1643 * time stamp reading requires ~3us per sample, each sample
1644 * was pretty stable even under load => only require 10
1645 * samples for each offset comparison.
1646 */
1647 memset(&adapter->compare, 0, sizeof(adapter->compare));
1648 adapter->compare.source = &adapter->clock;
1649 adapter->compare.target = ktime_get_real;
1650 adapter->compare.num_samples = 10;
1651 timecompare_update(&adapter->compare, 0);
1652 break;
1653 case e1000_82575:
1654 /* 82575 does not support timesync */
1655 default:
1656 break;
38c845c7 1657 }
38c845c7 1658
9d5c8243
AK		 1659 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1660 /* print bus type/speed/width info */
7c510e4b 1661 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1662 netdev->name,
1663 ((hw->bus.speed == e1000_bus_speed_2500)
1664 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1665 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1666 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1667 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1668 "unknown"),
7c510e4b 1669 netdev->dev_addr);
9d5c8243
AK		 1670
1671 igb_read_part_num(hw, &part_num);
1672 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1673 (part_num >> 8), (part_num & 0xff));
1674
1675 dev_info(&pdev->dev,
1676 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1677 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1678 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1679 adapter->num_rx_queues, adapter->num_tx_queues);
1680
9d5c8243
AK		 1681 return 0;
1682
1683err_register:
1684 igb_release_hw_control(adapter);
1685err_eeprom:
1686 if (!igb_check_reset_block(hw))
f5f4cf08 1687 igb_reset_phy(hw);
9d5c8243
AK		 1688
1689 if (hw->flash_address)
1690 iounmap(hw->flash_address);
9d5c8243 1691err_sw_init:
047e0030 1692 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 1693 iounmap(hw->hw_addr);
1694err_ioremap:
1695 free_netdev(netdev);
1696err_alloc_etherdev:
aed5dec3
AD		 1697 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1698 IORESOURCE_MEM));
9d5c8243
AK		 1699err_pci_reg:
1700err_dma:
1701 pci_disable_device(pdev);
1702 return err;
1703}
1704
1705/**
1706 * igb_remove - Device Removal Routine
1707 * @pdev: PCI device information struct
1708 *
1709 * igb_remove is called by the PCI subsystem to alert the driver
1710 * that it should release a PCI device. The could be caused by a
1711 * Hot-Plug event, or because the driver is going to be removed from
1712 * memory.
1713 **/
1714static void __devexit igb_remove(struct pci_dev *pdev)
1715{
1716 struct net_device *netdev = pci_get_drvdata(pdev);
1717 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1718 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1719
1720 /* flush_scheduled work may reschedule our watchdog task, so
1721 * explicitly disable watchdog tasks from being rescheduled */
1722 set_bit(__IGB_DOWN, &adapter->state);
1723 del_timer_sync(&adapter->watchdog_timer);
1724 del_timer_sync(&adapter->phy_info_timer);
1725
1726 flush_scheduled_work();
1727
421e02f0 1728#ifdef CONFIG_IGB_DCA
7dfc16fa 1729 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1730 dev_info(&pdev->dev, "DCA disabled\n");
1731 dca_remove_requester(&pdev->dev);
7dfc16fa 1732 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1733 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1734 }
1735#endif
1736
9d5c8243
AK		 1737 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1738 * would have already happened in close and is redundant. */
1739 igb_release_hw_control(adapter);
1740
1741 unregister_netdev(netdev);
1742
f5f4cf08
AD		 1743 if (!igb_check_reset_block(&adapter->hw))
1744 igb_reset_phy(&adapter->hw);
9d5c8243 1745
047e0030 1746 igb_clear_interrupt_scheme(adapter);
9d5c8243 1747
37680117
AD		 1748#ifdef CONFIG_PCI_IOV
1749 /* reclaim resources allocated to VFs */
1750 if (adapter->vf_data) {
1751 /* disable iov and allow time for transactions to clear */
1752 pci_disable_sriov(pdev);
1753 msleep(500);
1754
1755 kfree(adapter->vf_data);
1756 adapter->vf_data = NULL;
1757 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1758 msleep(100);
1759 dev_info(&pdev->dev, "IOV Disabled\n");
1760 }
1761#endif
28b0759c
AD		 1762 iounmap(hw->hw_addr);
1763 if (hw->flash_address)
1764 iounmap(hw->flash_address);
aed5dec3
AD		 1765 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1766 IORESOURCE_MEM));
9d5c8243
AK		 1767
1768 free_netdev(netdev);
1769
19d5afd4 1770 pci_disable_pcie_error_reporting(pdev);
40a914fa 1771
9d5c8243
AK		 1772 pci_disable_device(pdev);
1773}
1774
1775/**
1776 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1777 * @adapter: board private structure to initialize
1778 *
1779 * igb_sw_init initializes the Adapter private data structure.
1780 * Fields are initialized based on PCI device information and
1781 * OS network device settings (MTU size).
1782 **/
1783static int __devinit igb_sw_init(struct igb_adapter *adapter)
1784{
1785 struct e1000_hw *hw = &adapter->hw;
1786 struct net_device *netdev = adapter->netdev;
1787 struct pci_dev *pdev = adapter->pdev;
1788
1789 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1790
68fd9910
AD		 1791 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1792 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 1793 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
1794 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
1795
9d5c8243
AK		 1796 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1797 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1798
661086df
PWJ		 1799 /* This call may decrease the number of queues depending on
1800 * interrupt mode. */
047e0030 1801 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 1802 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1803 return -ENOMEM;
1804 }
1805
1806 /* Explicitly disable IRQ since the NIC can be in any state. */
1807 igb_irq_disable(adapter);
1808
1809 set_bit(__IGB_DOWN, &adapter->state);
1810 return 0;
1811}
1812
1813/**
1814 * igb_open - Called when a network interface is made active
1815 * @netdev: network interface device structure
1816 *
1817 * Returns 0 on success, negative value on failure
1818 *
1819 * The open entry point is called when a network interface is made
1820 * active by the system (IFF_UP). At this point all resources needed
1821 * for transmit and receive operations are allocated, the interrupt
1822 * handler is registered with the OS, the watchdog timer is started,
1823 * and the stack is notified that the interface is ready.
1824 **/
1825static int igb_open(struct net_device *netdev)
1826{
1827 struct igb_adapter *adapter = netdev_priv(netdev);
1828 struct e1000_hw *hw = &adapter->hw;
1829 int err;
1830 int i;
1831
1832 /* disallow open during test */
1833 if (test_bit(__IGB_TESTING, &adapter->state))
1834 return -EBUSY;
1835
b168dfc5
JB		 1836 netif_carrier_off(netdev);
1837
9d5c8243
AK		 1838 /* allocate transmit descriptors */
1839 err = igb_setup_all_tx_resources(adapter);
1840 if (err)
1841 goto err_setup_tx;
1842
1843 /* allocate receive descriptors */
1844 err = igb_setup_all_rx_resources(adapter);
1845 if (err)
1846 goto err_setup_rx;
1847
1848 /* e1000_power_up_phy(adapter); */
1849
1850 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1851 if ((adapter->hw.mng_cookie.status &
1852 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1853 igb_update_mng_vlan(adapter);
1854
1855 /* before we allocate an interrupt, we must be ready to handle it.
1856 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1857 * as soon as we call pci_request_irq, so we have to setup our
1858 * clean_rx handler before we do so. */
1859 igb_configure(adapter);
1860
1861 err = igb_request_irq(adapter);
1862 if (err)
1863 goto err_req_irq;
1864
1865 /* From here on the code is the same as igb_up() */
1866 clear_bit(__IGB_DOWN, &adapter->state);
1867
047e0030
AD		 1868 for (i = 0; i < adapter->num_q_vectors; i++) {
1869 struct igb_q_vector *q_vector = adapter->q_vector[i];
1870 napi_enable(&q_vector->napi);
1871 }
9d5c8243
AK		 1872
1873 /* Clear any pending interrupts. */
1874 rd32(E1000_ICR);
844290e5
PW		 1875
1876 igb_irq_enable(adapter);
1877
d4960307
AD		 1878 /* notify VFs that reset has been completed */
1879 if (adapter->vfs_allocated_count) {
1880 u32 reg_data = rd32(E1000_CTRL_EXT);
1881 reg_data |= E1000_CTRL_EXT_PFRSTD;
1882 wr32(E1000_CTRL_EXT, reg_data);
1883 }
1884
d55b53ff
JK		 1885 netif_tx_start_all_queues(netdev);
1886
9d5c8243
AK		 1887 /* Fire a link status change interrupt to start the watchdog. */
1888 wr32(E1000_ICS, E1000_ICS_LSC);
1889
1890 return 0;
1891
1892err_req_irq:
1893 igb_release_hw_control(adapter);
1894 /* e1000_power_down_phy(adapter); */
1895 igb_free_all_rx_resources(adapter);
1896err_setup_rx:
1897 igb_free_all_tx_resources(adapter);
1898err_setup_tx:
1899 igb_reset(adapter);
1900
1901 return err;
1902}
1903
1904/**
1905 * igb_close - Disables a network interface
1906 * @netdev: network interface device structure
1907 *
1908 * Returns 0, this is not allowed to fail
1909 *
1910 * The close entry point is called when an interface is de-activated
1911 * by the OS. The hardware is still under the driver's control, but
1912 * needs to be disabled. A global MAC reset is issued to stop the
1913 * hardware, and all transmit and receive resources are freed.
1914 **/
1915static int igb_close(struct net_device *netdev)
1916{
1917 struct igb_adapter *adapter = netdev_priv(netdev);
1918
1919 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1920 igb_down(adapter);
1921
1922 igb_free_irq(adapter);
1923
1924 igb_free_all_tx_resources(adapter);
1925 igb_free_all_rx_resources(adapter);
1926
1927 /* kill manageability vlan ID if supported, but not if a vlan with
1928 * the same ID is registered on the host OS (let 8021q kill it) */
1929 if ((adapter->hw.mng_cookie.status &
1930 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1931 !(adapter->vlgrp &&
1932 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1933 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1934
1935 return 0;
1936}
1937
1938/**
1939 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 1940 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1941 *
1942 * Return 0 on success, negative on failure
1943 **/
80785298 1944int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1945{
80785298 1946 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 1947 int size;
1948
1949 size = sizeof(struct igb_buffer) * tx_ring->count;
1950 tx_ring->buffer_info = vmalloc(size);
1951 if (!tx_ring->buffer_info)
1952 goto err;
1953 memset(tx_ring->buffer_info, 0, size);
1954
1955 /* round up to nearest 4K */
85e8d004 1956 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1957 tx_ring->size = ALIGN(tx_ring->size, 4096);
1958
1959 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1960 &tx_ring->dma);
1961
1962 if (!tx_ring->desc)
1963 goto err;
1964
9d5c8243
AK		 1965 tx_ring->next_to_use = 0;
1966 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1967 return 0;
1968
1969err:
1970 vfree(tx_ring->buffer_info);
047e0030 1971 dev_err(&pdev->dev,
9d5c8243
AK		 1972 "Unable to allocate memory for the transmit descriptor ring\n");
1973 return -ENOMEM;
1974}
1975
1976/**
1977 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1978 * (Descriptors) for all queues
1979 * @adapter: board private structure
1980 *
1981 * Return 0 on success, negative on failure
1982 **/
1983static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1984{
1985 int i, err = 0;
661086df 1986 int r_idx;
9d5c8243
AK		 1987
1988 for (i = 0; i < adapter->num_tx_queues; i++) {
80785298 1989 err = igb_setup_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1990 if (err) {
1991 dev_err(&adapter->pdev->dev,
1992 "Allocation for Tx Queue %u failed\n", i);
1993 for (i--; i >= 0; i--)
3b644cf6 1994 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1995 break;
1996 }
1997 }
1998
661086df
PWJ		 1999 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
2000 r_idx = i % adapter->num_tx_queues;
2001 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 2002 }
9d5c8243
AK		 2003 return err;
2004}
2005
2006/**
85b430b4
AD		 2007 * igb_setup_tctl - configure the transmit control registers
2008 * @adapter: Board private structure
9d5c8243 2009 **/
d7ee5b3a 2010void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2011{
9d5c8243
AK		 2012 struct e1000_hw *hw = &adapter->hw;
2013 u32 tctl;
9d5c8243 2014
85b430b4
AD		 2015 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2016 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2017
2018 /* Program the Transmit Control Register */
9d5c8243
AK		 2019 tctl = rd32(E1000_TCTL);
2020 tctl &= ~E1000_TCTL_CT;
2021 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2022 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2023
2024 igb_config_collision_dist(hw);
2025
9d5c8243
AK		 2026 /* Enable transmits */
2027 tctl |= E1000_TCTL_EN;
2028
2029 wr32(E1000_TCTL, tctl);
2030}
2031
85b430b4
AD		 2032/**
2033 * igb_configure_tx_ring - Configure transmit ring after Reset
2034 * @adapter: board private structure
2035 * @ring: tx ring to configure
2036 *
2037 * Configure a transmit ring after a reset.
2038 **/
d7ee5b3a
AD		 2039void igb_configure_tx_ring(struct igb_adapter *adapter,
2040 struct igb_ring *ring)
85b430b4
AD		 2041{
2042 struct e1000_hw *hw = &adapter->hw;
2043 u32 txdctl;
2044 u64 tdba = ring->dma;
2045 int reg_idx = ring->reg_idx;
2046
2047 /* disable the queue */
2048 txdctl = rd32(E1000_TXDCTL(reg_idx));
2049 wr32(E1000_TXDCTL(reg_idx),
2050 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2051 wrfl();
2052 mdelay(10);
2053
2054 wr32(E1000_TDLEN(reg_idx),
2055 ring->count * sizeof(union e1000_adv_tx_desc));
2056 wr32(E1000_TDBAL(reg_idx),
2057 tdba & 0x00000000ffffffffULL);
2058 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2059
fce99e34
AD		 2060 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2061 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2062 writel(0, ring->head);
2063 writel(0, ring->tail);
85b430b4
AD		 2064
2065 txdctl |= IGB_TX_PTHRESH;
2066 txdctl |= IGB_TX_HTHRESH << 8;
2067 txdctl |= IGB_TX_WTHRESH << 16;
2068
2069 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2070 wr32(E1000_TXDCTL(reg_idx), txdctl);
2071}
2072
2073/**
2074 * igb_configure_tx - Configure transmit Unit after Reset
2075 * @adapter: board private structure
2076 *
2077 * Configure the Tx unit of the MAC after a reset.
2078 **/
2079static void igb_configure_tx(struct igb_adapter *adapter)
2080{
2081 int i;
2082
2083 for (i = 0; i < adapter->num_tx_queues; i++)
2084 igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
85b430b4
AD		 2085}
2086
9d5c8243
AK		 2087/**
2088 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2089 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2090 *
2091 * Returns 0 on success, negative on failure
2092 **/
80785298 2093int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2094{
80785298 2095 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 2096 int size, desc_len;
2097
2098 size = sizeof(struct igb_buffer) * rx_ring->count;
2099 rx_ring->buffer_info = vmalloc(size);
2100 if (!rx_ring->buffer_info)
2101 goto err;
2102 memset(rx_ring->buffer_info, 0, size);
2103
2104 desc_len = sizeof(union e1000_adv_rx_desc);
2105
2106 /* Round up to nearest 4K */
2107 rx_ring->size = rx_ring->count * desc_len;
2108 rx_ring->size = ALIGN(rx_ring->size, 4096);
2109
2110 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2111 &rx_ring->dma);
2112
2113 if (!rx_ring->desc)
2114 goto err;
2115
2116 rx_ring->next_to_clean = 0;
2117 rx_ring->next_to_use = 0;
9d5c8243 2118
9d5c8243
AK		 2119 return 0;
2120
2121err:
2122 vfree(rx_ring->buffer_info);
80785298 2123 dev_err(&pdev->dev, "Unable to allocate memory for "
9d5c8243
AK		 2124 "the receive descriptor ring\n");
2125 return -ENOMEM;
2126}
2127
2128/**
2129 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2130 * (Descriptors) for all queues
2131 * @adapter: board private structure
2132 *
2133 * Return 0 on success, negative on failure
2134 **/
2135static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2136{
2137 int i, err = 0;
2138
2139 for (i = 0; i < adapter->num_rx_queues; i++) {
80785298 2140 err = igb_setup_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2141 if (err) {
2142 dev_err(&adapter->pdev->dev,
2143 "Allocation for Rx Queue %u failed\n", i);
2144 for (i--; i >= 0; i--)
3b644cf6 2145 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2146 break;
2147 }
2148 }
2149
2150 return err;
2151}
2152
06cf2666
AD		 2153/**
2154 * igb_setup_mrqc - configure the multiple receive queue control registers
2155 * @adapter: Board private structure
2156 **/
2157static void igb_setup_mrqc(struct igb_adapter *adapter)
2158{
2159 struct e1000_hw *hw = &adapter->hw;
2160 u32 mrqc, rxcsum;
2161 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2162 union e1000_reta {
2163 u32 dword;
2164 u8 bytes[4];
2165 } reta;
2166 static const u8 rsshash[40] = {
2167 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2168 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2169 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2170 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2171
2172 /* Fill out hash function seeds */
2173 for (j = 0; j < 10; j++) {
2174 u32 rsskey = rsshash[(j * 4)];
2175 rsskey |= rsshash[(j * 4) + 1] << 8;
2176 rsskey |= rsshash[(j * 4) + 2] << 16;
2177 rsskey |= rsshash[(j * 4) + 3] << 24;
2178 array_wr32(E1000_RSSRK(0), j, rsskey);
2179 }
2180
2181 num_rx_queues = adapter->num_rx_queues;
2182
2183 if (adapter->vfs_allocated_count) {
2184 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2185 switch (hw->mac.type) {
2186 case e1000_82576:
2187 shift = 3;
2188 num_rx_queues = 2;
2189 break;
2190 case e1000_82575:
2191 shift = 2;
2192 shift2 = 6;
2193 default:
2194 break;
2195 }
2196 } else {
2197 if (hw->mac.type == e1000_82575)
2198 shift = 6;
2199 }
2200
2201 for (j = 0; j < (32 * 4); j++) {
2202 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2203 if (shift2)
2204 reta.bytes[j & 3] |= num_rx_queues << shift2;
2205 if ((j & 3) == 3)
2206 wr32(E1000_RETA(j >> 2), reta.dword);
2207 }
2208
2209 /*
2210 * Disable raw packet checksumming so that RSS hash is placed in
2211 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2212 * offloads as they are enabled by default
2213 */
2214 rxcsum = rd32(E1000_RXCSUM);
2215 rxcsum |= E1000_RXCSUM_PCSD;
2216
2217 if (adapter->hw.mac.type >= e1000_82576)
2218 /* Enable Receive Checksum Offload for SCTP */
2219 rxcsum |= E1000_RXCSUM_CRCOFL;
2220
2221 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2222 wr32(E1000_RXCSUM, rxcsum);
2223
2224 /* If VMDq is enabled then we set the appropriate mode for that, else
2225 * we default to RSS so that an RSS hash is calculated per packet even
2226 * if we are only using one queue */
2227 if (adapter->vfs_allocated_count) {
2228 if (hw->mac.type > e1000_82575) {
2229 /* Set the default pool for the PF's first queue */
2230 u32 vtctl = rd32(E1000_VT_CTL);
2231 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2232 E1000_VT_CTL_DISABLE_DEF_POOL);
2233 vtctl |= adapter->vfs_allocated_count <<
2234 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2235 wr32(E1000_VT_CTL, vtctl);
2236 }
2237 if (adapter->num_rx_queues > 1)
2238 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2239 else
2240 mrqc = E1000_MRQC_ENABLE_VMDQ;
2241 } else {
2242 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2243 }
2244 igb_vmm_control(adapter);
2245
2246 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2247 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2248 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2249 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2250 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2251 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2252 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2253 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2254
2255 wr32(E1000_MRQC, mrqc);
2256}
2257
9d5c8243
AK		 2258/**
2259 * igb_setup_rctl - configure the receive control registers
2260 * @adapter: Board private structure
2261 **/
d7ee5b3a 2262void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2263{
2264 struct e1000_hw *hw = &adapter->hw;
2265 u32 rctl;
9d5c8243
AK		 2266
2267 rctl = rd32(E1000_RCTL);
2268
2269 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2270 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2271
69d728ba 2272 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2273 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2274
87cb7e8c
AK		 2275 /*
2276 * enable stripping of CRC. It's unlikely this will break BMC
2277 * redirection as it did with e1000. Newer features require
2278 * that the HW strips the CRC.
73cd78f1 2279 */
87cb7e8c 2280 rctl |= E1000_RCTL_SECRC;
9d5c8243 2281
9b07f3d3 2282 /*
ec54d7d6 2283 * disable store bad packets and clear size bits.
9b07f3d3 2284 */
ec54d7d6 2285 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2286
6ec43fe6
AD		 2287 /* enable LPE to prevent packets larger than max_frame_size */
2288 rctl |= E1000_RCTL_LPE;
9d5c8243 2289
952f72a8
AD		 2290 /* disable queue 0 to prevent tail write w/o re-config */
2291 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2292
e1739522
AD		 2293 /* Attention!!! For SR-IOV PF driver operations you must enable
2294 * queue drop for all VF and PF queues to prevent head of line blocking
2295 * if an un-trusted VF does not provide descriptors to hardware.
2296 */
2297 if (adapter->vfs_allocated_count) {
e1739522
AD		 2298 /* set all queue drop enable bits */
2299 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2300 }
2301
9d5c8243
AK		 2302 wr32(E1000_RCTL, rctl);
2303}
2304
7d5753f0
AD		 2305static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2306 int vfn)
2307{
2308 struct e1000_hw *hw = &adapter->hw;
2309 u32 vmolr;
2310
2311 /* if it isn't the PF check to see if VFs are enabled and
2312 * increase the size to support vlan tags */
2313 if (vfn < adapter->vfs_allocated_count &&
2314 adapter->vf_data[vfn].vlans_enabled)
2315 size += VLAN_TAG_SIZE;
2316
2317 vmolr = rd32(E1000_VMOLR(vfn));
2318 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2319 vmolr |= size | E1000_VMOLR_LPE;
2320 wr32(E1000_VMOLR(vfn), vmolr);
2321
2322 return 0;
2323}
2324
e1739522
AD		 2325/**
2326 * igb_rlpml_set - set maximum receive packet size
2327 * @adapter: board private structure
2328 *
2329 * Configure maximum receivable packet size.
2330 **/
2331static void igb_rlpml_set(struct igb_adapter *adapter)
2332{
2333 u32 max_frame_size = adapter->max_frame_size;
2334 struct e1000_hw *hw = &adapter->hw;
2335 u16 pf_id = adapter->vfs_allocated_count;
2336
2337 if (adapter->vlgrp)
2338 max_frame_size += VLAN_TAG_SIZE;
2339
2340 /* if vfs are enabled we set RLPML to the largest possible request
2341 * size and set the VMOLR RLPML to the size we need */
2342 if (pf_id) {
2343 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2344 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2345 }
2346
2347 wr32(E1000_RLPML, max_frame_size);
2348}
2349
7d5753f0
AD		 2350static inline void igb_set_vmolr(struct igb_adapter *adapter, int vfn)
2351{
2352 struct e1000_hw *hw = &adapter->hw;
2353 u32 vmolr;
2354
2355 /*
2356 * This register exists only on 82576 and newer so if we are older then
2357 * we should exit and do nothing
2358 */
2359 if (hw->mac.type < e1000_82576)
2360 return;
2361
2362 vmolr = rd32(E1000_VMOLR(vfn));
2363 vmolr |= E1000_VMOLR_AUPE | /* Accept untagged packets */
2364 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2365
2366 /* clear all bits that might not be set */
2367 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2368
2369 if (adapter->num_rx_queues > 1 && vfn == adapter->vfs_allocated_count)
2370 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2371 /*
2372 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2373 * multicast packets
2374 */
2375 if (vfn <= adapter->vfs_allocated_count)
2376 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2377
2378 wr32(E1000_VMOLR(vfn), vmolr);
2379}
2380
85b430b4
AD		 2381/**
2382 * igb_configure_rx_ring - Configure a receive ring after Reset
2383 * @adapter: board private structure
2384 * @ring: receive ring to be configured
2385 *
2386 * Configure the Rx unit of the MAC after a reset.
2387 **/
d7ee5b3a
AD		 2388void igb_configure_rx_ring(struct igb_adapter *adapter,
2389 struct igb_ring *ring)
85b430b4
AD		 2390{
2391 struct e1000_hw *hw = &adapter->hw;
2392 u64 rdba = ring->dma;
2393 int reg_idx = ring->reg_idx;
952f72a8 2394 u32 srrctl, rxdctl;
85b430b4
AD		 2395
2396 /* disable the queue */
2397 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2398 wr32(E1000_RXDCTL(reg_idx),
2399 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2400
2401 /* Set DMA base address registers */
2402 wr32(E1000_RDBAL(reg_idx),
2403 rdba & 0x00000000ffffffffULL);
2404 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2405 wr32(E1000_RDLEN(reg_idx),
2406 ring->count * sizeof(union e1000_adv_rx_desc));
2407
2408 /* initialize head and tail */
fce99e34
AD		 2409 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2410 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2411 writel(0, ring->head);
2412 writel(0, ring->tail);
85b430b4 2413
952f72a8 2414 /* set descriptor configuration */
4c844851
AD		 2415 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2416 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2417 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2418#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2419 srrctl |= IGB_RXBUFFER_16384 >>
2420 E1000_SRRCTL_BSIZEPKT_SHIFT;
2421#else
2422 srrctl |= (PAGE_SIZE / 2) >>
2423 E1000_SRRCTL_BSIZEPKT_SHIFT;
2424#endif
2425 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2426 } else {
4c844851 2427 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2428 E1000_SRRCTL_BSIZEPKT_SHIFT;
2429 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2430 }
2431
2432 wr32(E1000_SRRCTL(reg_idx), srrctl);
2433
7d5753f0
AD		 2434 /* set filtering for VMDQ pools */
2435 igb_set_vmolr(adapter, reg_idx & 0x7);
2436
85b430b4
AD		 2437 /* enable receive descriptor fetching */
2438 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2439 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2440 rxdctl &= 0xFFF00000;
2441 rxdctl |= IGB_RX_PTHRESH;
2442 rxdctl |= IGB_RX_HTHRESH << 8;
2443 rxdctl |= IGB_RX_WTHRESH << 16;
2444 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2445}
2446
9d5c8243
AK		 2447/**
2448 * igb_configure_rx - Configure receive Unit after Reset
2449 * @adapter: board private structure
2450 *
2451 * Configure the Rx unit of the MAC after a reset.
2452 **/
2453static void igb_configure_rx(struct igb_adapter *adapter)
2454{
9107584e 2455 int i;
9d5c8243 2456
68d480c4
AD		 2457 /* set UTA to appropriate mode */
2458 igb_set_uta(adapter);
2459
26ad9178
AD		 2460 /* set the correct pool for the PF default MAC address in entry 0 */
2461 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2462 adapter->vfs_allocated_count);
2463
06cf2666
AD		 2464 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2465 * the Base and Length of the Rx Descriptor Ring */
2466 for (i = 0; i < adapter->num_rx_queues; i++)
2467 igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
9d5c8243
AK		 2468}
2469
2470/**
2471 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2472 * @tx_ring: Tx descriptor ring for a specific queue
2473 *
2474 * Free all transmit software resources
2475 **/
68fd9910 2476void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2477{
3b644cf6 2478 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2479
2480 vfree(tx_ring->buffer_info);
2481 tx_ring->buffer_info = NULL;
2482
80785298
AD		 2483 pci_free_consistent(tx_ring->pdev, tx_ring->size,
2484 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 2485
2486 tx_ring->desc = NULL;
2487}
2488
2489/**
2490 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2491 * @adapter: board private structure
2492 *
2493 * Free all transmit software resources
2494 **/
2495static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2496{
2497 int i;
2498
2499 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2500 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2501}
2502
b1a436c3
AD		 2503void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
2504 struct igb_buffer *buffer_info)
9d5c8243 2505{
65689fef 2506 buffer_info->dma = 0;
9d5c8243 2507 if (buffer_info->skb) {
80785298
AD		 2508 skb_dma_unmap(&tx_ring->pdev->dev,
2509 buffer_info->skb,
65689fef 2510 DMA_TO_DEVICE);
9d5c8243
AK		 2511 dev_kfree_skb_any(buffer_info->skb);
2512 buffer_info->skb = NULL;
2513 }
2514 buffer_info->time_stamp = 0;
2515 /* buffer_info must be completely set up in the transmit path */
2516}
2517
2518/**
2519 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2520 * @tx_ring: ring to be cleaned
2521 **/
3b644cf6 2522static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 2523{
2524 struct igb_buffer *buffer_info;
2525 unsigned long size;
2526 unsigned int i;
2527
2528 if (!tx_ring->buffer_info)
2529 return;
2530 /* Free all the Tx ring sk_buffs */
2531
2532 for (i = 0; i < tx_ring->count; i++) {
2533 buffer_info = &tx_ring->buffer_info[i];
80785298 2534 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 2535 }
2536
2537 size = sizeof(struct igb_buffer) * tx_ring->count;
2538 memset(tx_ring->buffer_info, 0, size);
2539
2540 /* Zero out the descriptor ring */
2541
2542 memset(tx_ring->desc, 0, tx_ring->size);
2543
2544 tx_ring->next_to_use = 0;
2545 tx_ring->next_to_clean = 0;
2546
fce99e34
AD		 2547 writel(0, tx_ring->head);
2548 writel(0, tx_ring->tail);
9d5c8243
AK		 2549}
2550
2551/**
2552 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2553 * @adapter: board private structure
2554 **/
2555static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2556{
2557 int i;
2558
2559 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2560 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2561}
2562
2563/**
2564 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2565 * @rx_ring: ring to clean the resources from
2566 *
2567 * Free all receive software resources
2568 **/
68fd9910 2569void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2570{
3b644cf6 2571 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2572
2573 vfree(rx_ring->buffer_info);
2574 rx_ring->buffer_info = NULL;
2575
80785298
AD		 2576 pci_free_consistent(rx_ring->pdev, rx_ring->size,
2577 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 2578
2579 rx_ring->desc = NULL;
2580}
2581
2582/**
2583 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2584 * @adapter: board private structure
2585 *
2586 * Free all receive software resources
2587 **/
2588static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2589{
2590 int i;
2591
2592 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2593 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2594}
2595
2596/**
2597 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2598 * @rx_ring: ring to free buffers from
2599 **/
3b644cf6 2600static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 2601{
2602 struct igb_buffer *buffer_info;
9d5c8243
AK		 2603 unsigned long size;
2604 unsigned int i;
2605
2606 if (!rx_ring->buffer_info)
2607 return;
2608 /* Free all the Rx ring sk_buffs */
2609 for (i = 0; i < rx_ring->count; i++) {
2610 buffer_info = &rx_ring->buffer_info[i];
2611 if (buffer_info->dma) {
80785298
AD		 2612 pci_unmap_single(rx_ring->pdev,
2613 buffer_info->dma,
4c844851 2614 rx_ring->rx_buffer_len,
6ec43fe6 2615 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2616 buffer_info->dma = 0;
2617 }
2618
2619 if (buffer_info->skb) {
2620 dev_kfree_skb(buffer_info->skb);
2621 buffer_info->skb = NULL;
2622 }
6ec43fe6 2623 if (buffer_info->page_dma) {
80785298
AD		 2624 pci_unmap_page(rx_ring->pdev,
2625 buffer_info->page_dma,
6ec43fe6
AD		 2626 PAGE_SIZE / 2,
2627 PCI_DMA_FROMDEVICE);
2628 buffer_info->page_dma = 0;
2629 }
9d5c8243 2630 if (buffer_info->page) {
9d5c8243
AK		 2631 put_page(buffer_info->page);
2632 buffer_info->page = NULL;
bf36c1a0 2633 buffer_info->page_offset = 0;
9d5c8243
AK		 2634 }
2635 }
2636
9d5c8243
AK		 2637 size = sizeof(struct igb_buffer) * rx_ring->count;
2638 memset(rx_ring->buffer_info, 0, size);
2639
2640 /* Zero out the descriptor ring */
2641 memset(rx_ring->desc, 0, rx_ring->size);
2642
2643 rx_ring->next_to_clean = 0;
2644 rx_ring->next_to_use = 0;
2645
fce99e34
AD		 2646 writel(0, rx_ring->head);
2647 writel(0, rx_ring->tail);
9d5c8243
AK		 2648}
2649
2650/**
2651 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2652 * @adapter: board private structure
2653 **/
2654static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2655{
2656 int i;
2657
2658 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2659 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2660}
2661
2662/**
2663 * igb_set_mac - Change the Ethernet Address of the NIC
2664 * @netdev: network interface device structure
2665 * @p: pointer to an address structure
2666 *
2667 * Returns 0 on success, negative on failure
2668 **/
2669static int igb_set_mac(struct net_device *netdev, void *p)
2670{
2671 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2672 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2673 struct sockaddr *addr = p;
2674
2675 if (!is_valid_ether_addr(addr->sa_data))
2676 return -EADDRNOTAVAIL;
2677
2678 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2679 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2680
26ad9178
AD		 2681 /* set the correct pool for the new PF MAC address in entry 0 */
2682 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
2683 adapter->vfs_allocated_count);
e1739522 2684
9d5c8243
AK		 2685 return 0;
2686}
2687
2688/**
68d480c4 2689 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 2690 * @netdev: network interface device structure
2691 *
68d480c4
AD		 2692 * Writes multicast address list to the MTA hash table.
2693 * Returns: -ENOMEM on failure
2694 * 0 on no addresses written
2695 * X on writing X addresses to MTA
9d5c8243 2696 **/
68d480c4 2697static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 2698{
2699 struct igb_adapter *adapter = netdev_priv(netdev);
2700 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 2701 struct dev_mc_list *mc_ptr = netdev->mc_list;
68d480c4
AD		 2702 u8 *mta_list;
2703 u32 vmolr = 0;
9d5c8243
AK		 2704 int i;
2705
68d480c4
AD		 2706 if (!netdev->mc_count) {
2707 /* nothing to program, so clear mc list */
2708 igb_update_mc_addr_list(hw, NULL, 0);
2709 igb_restore_vf_multicasts(adapter);
2710 return 0;
2711 }
9d5c8243 2712
68d480c4
AD		 2713 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2714 if (!mta_list)
2715 return -ENOMEM;
ff41f8dc 2716
68d480c4
AD		 2717 /* set vmolr receive overflow multicast bit */
2718 vmolr |= E1000_VMOLR_ROMPE;
2719
2720 /* The shared function expects a packed array of only addresses. */
2721 mc_ptr = netdev->mc_list;
2722
2723 for (i = 0; i < netdev->mc_count; i++) {
2724 if (!mc_ptr)
2725 break;
2726 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2727 mc_ptr = mc_ptr->next;
746b9f02 2728 }
68d480c4
AD		 2729 igb_update_mc_addr_list(hw, mta_list, i);
2730 kfree(mta_list);
2731
2732 return netdev->mc_count;
2733}
2734
2735/**
2736 * igb_write_uc_addr_list - write unicast addresses to RAR table
2737 * @netdev: network interface device structure
2738 *
2739 * Writes unicast address list to the RAR table.
2740 * Returns: -ENOMEM on failure/insufficient address space
2741 * 0 on no addresses written
2742 * X on writing X addresses to the RAR table
2743 **/
2744static int igb_write_uc_addr_list(struct net_device *netdev)
2745{
2746 struct igb_adapter *adapter = netdev_priv(netdev);
2747 struct e1000_hw *hw = &adapter->hw;
2748 unsigned int vfn = adapter->vfs_allocated_count;
2749 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2750 int count = 0;
2751
2752 /* return ENOMEM indicating insufficient memory for addresses */
2753 if (netdev->uc.count > rar_entries)
2754 return -ENOMEM;
9d5c8243 2755
ff41f8dc
AD		 2756 if (netdev->uc.count && rar_entries) {
2757 struct netdev_hw_addr *ha;
2758 list_for_each_entry(ha, &netdev->uc.list, list) {
2759 if (!rar_entries)
2760 break;
26ad9178
AD		 2761 igb_rar_set_qsel(adapter, ha->addr,
2762 rar_entries--,
68d480c4
AD		 2763 vfn);
2764 count++;
ff41f8dc
AD		 2765 }
2766 }
2767 /* write the addresses in reverse order to avoid write combining */
2768 for (; rar_entries > 0 ; rar_entries--) {
2769 wr32(E1000_RAH(rar_entries), 0);
2770 wr32(E1000_RAL(rar_entries), 0);
2771 }
2772 wrfl();
2773
68d480c4
AD		 2774 return count;
2775}
2776
2777/**
2778 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2779 * @netdev: network interface device structure
2780 *
2781 * The set_rx_mode entry point is called whenever the unicast or multicast
2782 * address lists or the network interface flags are updated. This routine is
2783 * responsible for configuring the hardware for proper unicast, multicast,
2784 * promiscuous mode, and all-multi behavior.
2785 **/
2786static void igb_set_rx_mode(struct net_device *netdev)
2787{
2788 struct igb_adapter *adapter = netdev_priv(netdev);
2789 struct e1000_hw *hw = &adapter->hw;
2790 unsigned int vfn = adapter->vfs_allocated_count;
2791 u32 rctl, vmolr = 0;
2792 int count;
2793
2794 /* Check for Promiscuous and All Multicast modes */
2795 rctl = rd32(E1000_RCTL);
2796
2797 /* clear the effected bits */
2798 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
2799
2800 if (netdev->flags & IFF_PROMISC) {
2801 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2802 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
2803 } else {
2804 if (netdev->flags & IFF_ALLMULTI) {
2805 rctl |= E1000_RCTL_MPE;
2806 vmolr |= E1000_VMOLR_MPME;
2807 } else {
2808 /*
2809 * Write addresses to the MTA, if the attempt fails
2810 * then we should just turn on promiscous mode so
2811 * that we can at least receive multicast traffic
2812 */
2813 count = igb_write_mc_addr_list(netdev);
2814 if (count < 0) {
2815 rctl |= E1000_RCTL_MPE;
2816 vmolr |= E1000_VMOLR_MPME;
2817 } else if (count) {
2818 vmolr |= E1000_VMOLR_ROMPE;
2819 }
2820 }
2821 /*
2822 * Write addresses to available RAR registers, if there is not
2823 * sufficient space to store all the addresses then enable
2824 * unicast promiscous mode
2825 */
2826 count = igb_write_uc_addr_list(netdev);
2827 if (count < 0) {
2828 rctl |= E1000_RCTL_UPE;
2829 vmolr |= E1000_VMOLR_ROPE;
2830 }
2831 rctl |= E1000_RCTL_VFE;
28fc06f5 2832 }
68d480c4 2833 wr32(E1000_RCTL, rctl);
28fc06f5 2834
68d480c4
AD		 2835 /*
2836 * In order to support SR-IOV and eventually VMDq it is necessary to set
2837 * the VMOLR to enable the appropriate modes. Without this workaround
2838 * we will have issues with VLAN tag stripping not being done for frames
2839 * that are only arriving because we are the default pool
2840 */
2841 if (hw->mac.type < e1000_82576)
28fc06f5 2842 return;
9d5c8243 2843
68d480c4
AD		 2844 vmolr |= rd32(E1000_VMOLR(vfn)) &
2845 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
2846 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 2847 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 2848}
2849
2850/* Need to wait a few seconds after link up to get diagnostic information from
2851 * the phy */
2852static void igb_update_phy_info(unsigned long data)
2853{
2854 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2855 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2856}
2857
4d6b725e
AD		 2858/**
2859 * igb_has_link - check shared code for link and determine up/down
2860 * @adapter: pointer to driver private info
2861 **/
2862static bool igb_has_link(struct igb_adapter *adapter)
2863{
2864 struct e1000_hw *hw = &adapter->hw;
2865 bool link_active = false;
2866 s32 ret_val = 0;
2867
2868 /* get_link_status is set on LSC (link status) interrupt or
2869 * rx sequence error interrupt. get_link_status will stay
2870 * false until the e1000_check_for_link establishes link
2871 * for copper adapters ONLY
2872 */
2873 switch (hw->phy.media_type) {
2874 case e1000_media_type_copper:
2875 if (hw->mac.get_link_status) {
2876 ret_val = hw->mac.ops.check_for_link(hw);
2877 link_active = !hw->mac.get_link_status;
2878 } else {
2879 link_active = true;
2880 }
2881 break;
4d6b725e
AD		 2882 case e1000_media_type_internal_serdes:
2883 ret_val = hw->mac.ops.check_for_link(hw);
2884 link_active = hw->mac.serdes_has_link;
2885 break;
2886 default:
2887 case e1000_media_type_unknown:
2888 break;
2889 }
2890
2891 return link_active;
2892}
2893
9d5c8243
AK		 2894/**
2895 * igb_watchdog - Timer Call-back
2896 * @data: pointer to adapter cast into an unsigned long
2897 **/
2898static void igb_watchdog(unsigned long data)
2899{
2900 struct igb_adapter *adapter = (struct igb_adapter *)data;
2901 /* Do the rest outside of interrupt context */
2902 schedule_work(&adapter->watchdog_task);
2903}
2904
2905static void igb_watchdog_task(struct work_struct *work)
2906{
2907 struct igb_adapter *adapter = container_of(work,
2908 struct igb_adapter, watchdog_task);
2909 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2910 struct net_device *netdev = adapter->netdev;
2911 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2912 u32 link;
7a6ea550 2913 int i;
9d5c8243 2914
4d6b725e
AD		 2915 link = igb_has_link(adapter);
2916 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2917 goto link_up;
2918
9d5c8243
AK		 2919 if (link) {
2920 if (!netif_carrier_ok(netdev)) {
2921 u32 ctrl;
2922 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2923 &adapter->link_speed,
2924 &adapter->link_duplex);
2925
2926 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2927 /* Links status message must follow this format */
2928 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2929 "Flow Control: %s\n",
527d47c1 2930 netdev->name,
9d5c8243
AK		 2931 adapter->link_speed,
2932 adapter->link_duplex == FULL_DUPLEX ?
2933 "Full Duplex" : "Half Duplex",
2934 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2935 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2936 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2937 E1000_CTRL_TFCE) ? "TX" : "None")));
2938
2939 /* tweak tx_queue_len according to speed/duplex and
2940 * adjust the timeout factor */
2941 netdev->tx_queue_len = adapter->tx_queue_len;
2942 adapter->tx_timeout_factor = 1;
2943 switch (adapter->link_speed) {
2944 case SPEED_10:
2945 netdev->tx_queue_len = 10;
2946 adapter->tx_timeout_factor = 14;
2947 break;
2948 case SPEED_100:
2949 netdev->tx_queue_len = 100;
2950 /* maybe add some timeout factor ? */
2951 break;
2952 }
2953
2954 netif_carrier_on(netdev);
9d5c8243 2955
4ae196df
AD		 2956 igb_ping_all_vfs(adapter);
2957
4b1a9877 2958 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2959 if (!test_bit(__IGB_DOWN, &adapter->state))
2960 mod_timer(&adapter->phy_info_timer,
2961 round_jiffies(jiffies + 2 * HZ));
2962 }
2963 } else {
2964 if (netif_carrier_ok(netdev)) {
2965 adapter->link_speed = 0;
2966 adapter->link_duplex = 0;
527d47c1
AD		 2967 /* Links status message must follow this format */
2968 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2969 netdev->name);
9d5c8243 2970 netif_carrier_off(netdev);
4b1a9877 2971
4ae196df
AD		 2972 igb_ping_all_vfs(adapter);
2973
4b1a9877 2974 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2975 if (!test_bit(__IGB_DOWN, &adapter->state))
2976 mod_timer(&adapter->phy_info_timer,
2977 round_jiffies(jiffies + 2 * HZ));
2978 }
2979 }
2980
2981link_up:
2982 igb_update_stats(adapter);
2983
4b1a9877 2984 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2985 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2986 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2987 adapter->colc_old = adapter->stats.colc;
2988
2989 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2990 adapter->gorc_old = adapter->stats.gorc;
2991 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2992 adapter->gotc_old = adapter->stats.gotc;
2993
2994 igb_update_adaptive(&adapter->hw);
2995
2996 if (!netif_carrier_ok(netdev)) {
c493ea45 2997 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2998 /* We've lost link, so the controller stops DMA,
2999 * but we've got queued Tx work that's never going
3000 * to get done, so reset controller to flush Tx.
3001 * (Do the reset outside of interrupt context). */
3002 adapter->tx_timeout_count++;
3003 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 3004 /* return immediately since reset is imminent */
3005 return;
9d5c8243
AK		 3006 }
3007 }
3008
3009 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3010 if (adapter->msix_entries) {
047e0030
AD		 3011 u32 eics = 0;
3012 for (i = 0; i < adapter->num_q_vectors; i++) {
3013 struct igb_q_vector *q_vector = adapter->q_vector[i];
3014 eics |= q_vector->eims_value;
3015 }
7a6ea550
AD		 3016 wr32(E1000_EICS, eics);
3017 } else {
3018 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3019 }
9d5c8243
AK		 3020
3021 /* Force detection of hung controller every watchdog period */
3022 tx_ring->detect_tx_hung = true;
3023
3024 /* Reset the timer */
3025 if (!test_bit(__IGB_DOWN, &adapter->state))
3026 mod_timer(&adapter->watchdog_timer,
3027 round_jiffies(jiffies + 2 * HZ));
3028}
3029
3030enum latency_range {
3031 lowest_latency = 0,
3032 low_latency = 1,
3033 bulk_latency = 2,
3034 latency_invalid = 255
3035};
3036
6eb5a7f1
AD		 3037/**
3038 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3039 *
3040 * Stores a new ITR value based on strictly on packet size. This
3041 * algorithm is less sophisticated than that used in igb_update_itr,
3042 * due to the difficulty of synchronizing statistics across multiple
3043 * receive rings. The divisors and thresholds used by this fuction
3044 * were determined based on theoretical maximum wire speed and testing
3045 * data, in order to minimize response time while increasing bulk
3046 * throughput.
3047 * This functionality is controlled by the InterruptThrottleRate module
3048 * parameter (see igb_param.c)
3049 * NOTE: This function is called only when operating in a multiqueue
3050 * receive environment.
047e0030 3051 * @q_vector: pointer to q_vector
6eb5a7f1 3052 **/
047e0030 3053static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3054{
047e0030 3055 int new_val = q_vector->itr_val;
6eb5a7f1 3056 int avg_wire_size = 0;
047e0030 3057 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 3058
6eb5a7f1
AD		 3059 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3060 * ints/sec - ITR timer value of 120 ticks.
3061 */
3062 if (adapter->link_speed != SPEED_1000) {
047e0030 3063 new_val = 976;
6eb5a7f1 3064 goto set_itr_val;
9d5c8243 3065 }
047e0030
AD		 3066
3067 if (q_vector->rx_ring && q_vector->rx_ring->total_packets) {
3068 struct igb_ring *ring = q_vector->rx_ring;
3069 avg_wire_size = ring->total_bytes / ring->total_packets;
3070 }
3071
3072 if (q_vector->tx_ring && q_vector->tx_ring->total_packets) {
3073 struct igb_ring *ring = q_vector->tx_ring;
3074 avg_wire_size = max_t(u32, avg_wire_size,
3075 (ring->total_bytes /
3076 ring->total_packets));
3077 }
3078
3079 /* if avg_wire_size isn't set no work was done */
3080 if (!avg_wire_size)
3081 goto clear_counts;
9d5c8243 3082
6eb5a7f1
AD		 3083 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3084 avg_wire_size += 24;
3085
3086 /* Don't starve jumbo frames */
3087 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3088
6eb5a7f1
AD		 3089 /* Give a little boost to mid-size frames */
3090 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3091 new_val = avg_wire_size / 3;
3092 else
3093 new_val = avg_wire_size / 2;
9d5c8243 3094
6eb5a7f1 3095set_itr_val:
047e0030
AD		 3096 if (new_val != q_vector->itr_val) {
3097 q_vector->itr_val = new_val;
3098 q_vector->set_itr = 1;
9d5c8243 3099 }
6eb5a7f1 3100clear_counts:
047e0030
AD		 3101 if (q_vector->rx_ring) {
3102 q_vector->rx_ring->total_bytes = 0;
3103 q_vector->rx_ring->total_packets = 0;
3104 }
3105 if (q_vector->tx_ring) {
3106 q_vector->tx_ring->total_bytes = 0;
3107 q_vector->tx_ring->total_packets = 0;
3108 }
9d5c8243
AK		 3109}
3110
3111/**
3112 * igb_update_itr - update the dynamic ITR value based on statistics
3113 * Stores a new ITR value based on packets and byte
3114 * counts during the last interrupt. The advantage of per interrupt
3115 * computation is faster updates and more accurate ITR for the current
3116 * traffic pattern. Constants in this function were computed
3117 * based on theoretical maximum wire speed and thresholds were set based
3118 * on testing data as well as attempting to minimize response time
3119 * while increasing bulk throughput.
3120 * this functionality is controlled by the InterruptThrottleRate module
3121 * parameter (see igb_param.c)
3122 * NOTE: These calculations are only valid when operating in a single-
3123 * queue environment.
3124 * @adapter: pointer to adapter
047e0030 3125 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3126 * @packets: the number of packets during this measurement interval
3127 * @bytes: the number of bytes during this measurement interval
3128 **/
3129static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3130 int packets, int bytes)
3131{
3132 unsigned int retval = itr_setting;
3133
3134 if (packets == 0)
3135 goto update_itr_done;
3136
3137 switch (itr_setting) {
3138 case lowest_latency:
3139 /* handle TSO and jumbo frames */
3140 if (bytes/packets > 8000)
3141 retval = bulk_latency;
3142 else if ((packets < 5) && (bytes > 512))
3143 retval = low_latency;
3144 break;
3145 case low_latency: /* 50 usec aka 20000 ints/s */
3146 if (bytes > 10000) {
3147 /* this if handles the TSO accounting */
3148 if (bytes/packets > 8000) {
3149 retval = bulk_latency;
3150 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3151 retval = bulk_latency;
3152 } else if ((packets > 35)) {
3153 retval = lowest_latency;
3154 }
3155 } else if (bytes/packets > 2000) {
3156 retval = bulk_latency;
3157 } else if (packets <= 2 && bytes < 512) {
3158 retval = lowest_latency;
3159 }
3160 break;
3161 case bulk_latency: /* 250 usec aka 4000 ints/s */
3162 if (bytes > 25000) {
3163 if (packets > 35)
3164 retval = low_latency;
1e5c3d21 3165 } else if (bytes < 1500) {
9d5c8243
AK		 3166 retval = low_latency;
3167 }
3168 break;
3169 }
3170
3171update_itr_done:
3172 return retval;
3173}
3174
6eb5a7f1 3175static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3176{
047e0030 3177 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3178 u16 current_itr;
047e0030 3179 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3180
3181 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3182 if (adapter->link_speed != SPEED_1000) {
3183 current_itr = 0;
3184 new_itr = 4000;
3185 goto set_itr_now;
3186 }
3187
3188 adapter->rx_itr = igb_update_itr(adapter,
3189 adapter->rx_itr,
3190 adapter->rx_ring->total_packets,
3191 adapter->rx_ring->total_bytes);
9d5c8243 3192
047e0030
AD		 3193 adapter->tx_itr = igb_update_itr(adapter,
3194 adapter->tx_itr,
3195 adapter->tx_ring->total_packets,
3196 adapter->tx_ring->total_bytes);
3197 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3198
6eb5a7f1 3199 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3200 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3201 current_itr = low_latency;
3202
9d5c8243
AK		 3203 switch (current_itr) {
3204 /* counts and packets in update_itr are dependent on these numbers */
3205 case lowest_latency:
78b1f607 3206 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3207 break;
3208 case low_latency:
78b1f607 3209 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3210 break;
3211 case bulk_latency:
78b1f607 3212 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3213 break;
3214 default:
3215 break;
3216 }
3217
3218set_itr_now:
6eb5a7f1
AD		 3219 adapter->rx_ring->total_bytes = 0;
3220 adapter->rx_ring->total_packets = 0;
047e0030
AD		 3221 adapter->tx_ring->total_bytes = 0;
3222 adapter->tx_ring->total_packets = 0;
6eb5a7f1 3223
047e0030 3224 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3225 /* this attempts to bias the interrupt rate towards Bulk
3226 * by adding intermediate steps when interrupt rate is
3227 * increasing */
047e0030
AD		 3228 new_itr = new_itr > q_vector->itr_val ?
3229 max((new_itr * q_vector->itr_val) /
3230 (new_itr + (q_vector->itr_val >> 2)),
3231 new_itr) :
9d5c8243
AK		 3232 new_itr;
3233 /* Don't write the value here; it resets the adapter's
3234 * internal timer, and causes us to delay far longer than
3235 * we should between interrupts. Instead, we write the ITR
3236 * value at the beginning of the next interrupt so the timing
3237 * ends up being correct.
3238 */
047e0030
AD		 3239 q_vector->itr_val = new_itr;
3240 q_vector->set_itr = 1;
9d5c8243
AK		 3241 }
3242
3243 return;
3244}
3245
9d5c8243
AK		 3246#define IGB_TX_FLAGS_CSUM 0x00000001
3247#define IGB_TX_FLAGS_VLAN 0x00000002
3248#define IGB_TX_FLAGS_TSO 0x00000004
3249#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 3250#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 3251#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3252#define IGB_TX_FLAGS_VLAN_SHIFT 16
3253
85ad76b2 3254static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3255 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3256{
3257 struct e1000_adv_tx_context_desc *context_desc;
3258 unsigned int i;
3259 int err;
3260 struct igb_buffer *buffer_info;
3261 u32 info = 0, tu_cmd = 0;
3262 u32 mss_l4len_idx, l4len;
3263 *hdr_len = 0;
3264
3265 if (skb_header_cloned(skb)) {
3266 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3267 if (err)
3268 return err;
3269 }
3270
3271 l4len = tcp_hdrlen(skb);
3272 *hdr_len += l4len;
3273
3274 if (skb->protocol == htons(ETH_P_IP)) {
3275 struct iphdr *iph = ip_hdr(skb);
3276 iph->tot_len = 0;
3277 iph->check = 0;
3278 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3279 iph->daddr, 0,
3280 IPPROTO_TCP,
3281 0);
3282 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3283 ipv6_hdr(skb)->payload_len = 0;
3284 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3285 &ipv6_hdr(skb)->daddr,
3286 0, IPPROTO_TCP, 0);
3287 }
3288
3289 i = tx_ring->next_to_use;
3290
3291 buffer_info = &tx_ring->buffer_info[i];
3292 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3293 /* VLAN MACLEN IPLEN */
3294 if (tx_flags & IGB_TX_FLAGS_VLAN)
3295 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3296 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3297 *hdr_len += skb_network_offset(skb);
3298 info |= skb_network_header_len(skb);
3299 *hdr_len += skb_network_header_len(skb);
3300 context_desc->vlan_macip_lens = cpu_to_le32(info);
3301
3302 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3303 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3304
3305 if (skb->protocol == htons(ETH_P_IP))
3306 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3307 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3308
3309 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3310
3311 /* MSS L4LEN IDX */
3312 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3313 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3314
73cd78f1 3315 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3316 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3317 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3318
3319 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3320 context_desc->seqnum_seed = 0;
3321
3322 buffer_info->time_stamp = jiffies;
0e014cb1 3323 buffer_info->next_to_watch = i;
9d5c8243
AK		 3324 buffer_info->dma = 0;
3325 i++;
3326 if (i == tx_ring->count)
3327 i = 0;
3328
3329 tx_ring->next_to_use = i;
3330
3331 return true;
3332}
3333
85ad76b2
AD		 3334static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3335 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3336{
3337 struct e1000_adv_tx_context_desc *context_desc;
80785298 3338 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3339 struct igb_buffer *buffer_info;
3340 u32 info = 0, tu_cmd = 0;
80785298 3341 unsigned int i;
9d5c8243
AK		 3342
3343 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3344 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3345 i = tx_ring->next_to_use;
3346 buffer_info = &tx_ring->buffer_info[i];
3347 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3348
3349 if (tx_flags & IGB_TX_FLAGS_VLAN)
3350 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3351 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3352 if (skb->ip_summed == CHECKSUM_PARTIAL)
3353 info |= skb_network_header_len(skb);
3354
3355 context_desc->vlan_macip_lens = cpu_to_le32(info);
3356
3357 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3358
3359 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3360 __be16 protocol;
3361
3362 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3363 const struct vlan_ethhdr *vhdr =
3364 (const struct vlan_ethhdr*)skb->data;
3365
3366 protocol = vhdr->h_vlan_encapsulated_proto;
3367 } else {
3368 protocol = skb->protocol;
3369 }
3370
3371 switch (protocol) {
09640e63 3372 case cpu_to_be16(ETH_P_IP):
9d5c8243 3373 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3374 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3375 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3376 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3377 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3378 break;
09640e63 3379 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3380 /* XXX what about other V6 headers?? */
3381 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3382 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3383 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3384 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3385 break;
3386 default:
3387 if (unlikely(net_ratelimit()))
80785298 3388 dev_warn(&pdev->dev,
44b0cda3
MW		 3389 "partial checksum but proto=%x!\n",
3390 skb->protocol);
3391 break;
3392 }
9d5c8243
AK		 3393 }
3394
3395 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3396 context_desc->seqnum_seed = 0;
85ad76b2 3397 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3398 context_desc->mss_l4len_idx =
85ad76b2 3399 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3400
3401 buffer_info->time_stamp = jiffies;
0e014cb1 3402 buffer_info->next_to_watch = i;
9d5c8243
AK		 3403 buffer_info->dma = 0;
3404
3405 i++;
3406 if (i == tx_ring->count)
3407 i = 0;
3408 tx_ring->next_to_use = i;
3409
3410 return true;
3411 }
9d5c8243
AK		 3412 return false;
3413}
3414
3415#define IGB_MAX_TXD_PWR 16
3416#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3417
80785298 3418static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3419 unsigned int first)
9d5c8243
AK		 3420{
3421 struct igb_buffer *buffer_info;
80785298 3422 struct pci_dev *pdev = tx_ring->pdev;
9d5c8243
AK		 3423 unsigned int len = skb_headlen(skb);
3424 unsigned int count = 0, i;
3425 unsigned int f;
65689fef 3426 dma_addr_t *map;
9d5c8243
AK		 3427
3428 i = tx_ring->next_to_use;
3429
80785298
AD		 3430 if (skb_dma_map(&pdev->dev, skb, DMA_TO_DEVICE)) {
3431 dev_err(&pdev->dev, "TX DMA map failed\n");
65689fef
AD		 3432 return 0;
3433 }
3434
3435 map = skb_shinfo(skb)->dma_maps;
3436
9d5c8243
AK		 3437 buffer_info = &tx_ring->buffer_info[i];
3438 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3439 buffer_info->length = len;
3440 /* set time_stamp *before* dma to help avoid a possible race */
3441 buffer_info->time_stamp = jiffies;
0e014cb1 3442 buffer_info->next_to_watch = i;
042a53a9 3443 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3444
3445 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3446 struct skb_frag_struct *frag;
3447
65689fef
AD		 3448 i++;
3449 if (i == tx_ring->count)
3450 i = 0;
3451
9d5c8243
AK		 3452 frag = &skb_shinfo(skb)->frags[f];
3453 len = frag->size;
3454
3455 buffer_info = &tx_ring->buffer_info[i];
3456 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3457 buffer_info->length = len;
3458 buffer_info->time_stamp = jiffies;
0e014cb1 3459 buffer_info->next_to_watch = i;
65689fef 3460 buffer_info->dma = map[count];
9d5c8243 3461 count++;
9d5c8243
AK		 3462 }
3463
9d5c8243 3464 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3465 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3466
042a53a9 3467 return count + 1;
9d5c8243
AK		 3468}
3469
85ad76b2 3470static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3471 int tx_flags, int count, u32 paylen,
3472 u8 hdr_len)
3473{
3474 union e1000_adv_tx_desc *tx_desc = NULL;
3475 struct igb_buffer *buffer_info;
3476 u32 olinfo_status = 0, cmd_type_len;
3477 unsigned int i;
3478
3479 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3480 E1000_ADVTXD_DCMD_DEXT);
3481
3482 if (tx_flags & IGB_TX_FLAGS_VLAN)
3483 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3484
33af6bcc
PO		 3485 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3486 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3487
9d5c8243
AK		 3488 if (tx_flags & IGB_TX_FLAGS_TSO) {
3489 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3490
3491 /* insert tcp checksum */
3492 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3493
3494 /* insert ip checksum */
3495 if (tx_flags & IGB_TX_FLAGS_IPV4)
3496 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3497
3498 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3499 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3500 }
3501
85ad76b2
AD		 3502 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
3503 (tx_flags & (IGB_TX_FLAGS_CSUM |
3504 IGB_TX_FLAGS_TSO |
7dfc16fa 3505 IGB_TX_FLAGS_VLAN)))
85ad76b2 3506 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3507
3508 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3509
3510 i = tx_ring->next_to_use;
3511 while (count--) {
3512 buffer_info = &tx_ring->buffer_info[i];
3513 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3514 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3515 tx_desc->read.cmd_type_len =
3516 cpu_to_le32(cmd_type_len | buffer_info->length);
3517 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3518 i++;
3519 if (i == tx_ring->count)
3520 i = 0;
3521 }
3522
85ad76b2 3523 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 3524 /* Force memory writes to complete before letting h/w
3525 * know there are new descriptors to fetch. (Only
3526 * applicable for weak-ordered memory model archs,
3527 * such as IA-64). */
3528 wmb();
3529
3530 tx_ring->next_to_use = i;
fce99e34 3531 writel(i, tx_ring->tail);
9d5c8243
AK		 3532 /* we need this if more than one processor can write to our tail
3533 * at a time, it syncronizes IO on IA64/Altix systems */
3534 mmiowb();
3535}
3536
e694e964 3537static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3538{
e694e964
AD		 3539 struct net_device *netdev = tx_ring->netdev;
3540
661086df 3541 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3542
9d5c8243
AK		 3543 /* Herbert's original patch had:
3544 * smp_mb__after_netif_stop_queue();
3545 * but since that doesn't exist yet, just open code it. */
3546 smp_mb();
3547
3548 /* We need to check again in a case another CPU has just
3549 * made room available. */
c493ea45 3550 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3551 return -EBUSY;
3552
3553 /* A reprieve! */
661086df 3554 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 3555 tx_ring->tx_stats.restart_queue++;
9d5c8243
AK		 3556 return 0;
3557}
3558
e694e964 3559static int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 3560{
c493ea45 3561 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 3562 return 0;
e694e964 3563 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 3564}
3565
b1a436c3
AD		 3566netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3567 struct igb_ring *tx_ring)
9d5c8243 3568{
e694e964 3569 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
0e014cb1 3570 unsigned int first;
9d5c8243 3571 unsigned int tx_flags = 0;
9d5c8243 3572 u8 hdr_len = 0;
65689fef 3573 int count = 0;
9d5c8243 3574 int tso = 0;
c5b9bd5e 3575 union skb_shared_tx *shtx = skb_tx(skb);
9d5c8243 3576
9d5c8243
AK		 3577 /* need: 1 descriptor per page,
3578 * + 2 desc gap to keep tail from touching head,
3579 * + 1 desc for skb->data,
3580 * + 1 desc for context descriptor,
3581 * otherwise try next time */
e694e964 3582 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 3583 /* this is a hard error */
9d5c8243
AK		 3584 return NETDEV_TX_BUSY;
3585 }
33af6bcc 3586
33af6bcc
PO		 3587 if (unlikely(shtx->hardware)) {
3588 shtx->in_progress = 1;
3589 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3590 }
9d5c8243
AK		 3591
3592 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3593 tx_flags |= IGB_TX_FLAGS_VLAN;
3594 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3595 }
3596
661086df
PWJ		 3597 if (skb->protocol == htons(ETH_P_IP))
3598 tx_flags |= IGB_TX_FLAGS_IPV4;
3599
0e014cb1 3600 first = tx_ring->next_to_use;
85ad76b2
AD		 3601 if (skb_is_gso(skb)) {
3602 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
3603 if (tso < 0) {
3604 dev_kfree_skb_any(skb);
3605 return NETDEV_TX_OK;
3606 }
9d5c8243
AK		 3607 }
3608
3609 if (tso)
3610 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 3611 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 3612 (skb->ip_summed == CHECKSUM_PARTIAL))
3613 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3614
65689fef
AD		 3615 /*
3616 * count reflects descriptors mapped, if 0 then mapping error
3617 * has occured and we need to rewind the descriptor queue
3618 */
80785298 3619 count = igb_tx_map_adv(tx_ring, skb, first);
65689fef 3620
85ad76b2 3621 if (!count) {
65689fef
AD		 3622 dev_kfree_skb_any(skb);
3623 tx_ring->buffer_info[first].time_stamp = 0;
3624 tx_ring->next_to_use = first;
85ad76b2 3625 return NETDEV_TX_OK;
65689fef 3626 }
9d5c8243 3627
85ad76b2
AD		 3628 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
3629
3630 /* Make sure there is space in the ring for the next send. */
e694e964 3631 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 3632
9d5c8243
AK		 3633 return NETDEV_TX_OK;
3634}
3635
3b29a56d
SH		 3636static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3637 struct net_device *netdev)
9d5c8243
AK		 3638{
3639 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 3640 struct igb_ring *tx_ring;
661086df 3641 int r_idx = 0;
b1a436c3
AD		 3642
3643 if (test_bit(__IGB_DOWN, &adapter->state)) {
3644 dev_kfree_skb_any(skb);
3645 return NETDEV_TX_OK;
3646 }
3647
3648 if (skb->len <= 0) {
3649 dev_kfree_skb_any(skb);
3650 return NETDEV_TX_OK;
3651 }
3652
1bfaf07b 3653 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3654 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3655
3656 /* This goes back to the question of how to logically map a tx queue
3657 * to a flow. Right now, performance is impacted slightly negatively
3658 * if using multiple tx queues. If the stack breaks away from a
3659 * single qdisc implementation, we can look at this again. */
e694e964 3660 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 3661}
3662
3663/**
3664 * igb_tx_timeout - Respond to a Tx Hang
3665 * @netdev: network interface device structure
3666 **/
3667static void igb_tx_timeout(struct net_device *netdev)
3668{
3669 struct igb_adapter *adapter = netdev_priv(netdev);
3670 struct e1000_hw *hw = &adapter->hw;
3671
3672 /* Do the reset outside of interrupt context */
3673 adapter->tx_timeout_count++;
3674 schedule_work(&adapter->reset_task);
265de409
AD		 3675 wr32(E1000_EICS,
3676 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3677}
3678
3679static void igb_reset_task(struct work_struct *work)
3680{
3681 struct igb_adapter *adapter;
3682 adapter = container_of(work, struct igb_adapter, reset_task);
3683
3684 igb_reinit_locked(adapter);
3685}
3686
3687/**
3688 * igb_get_stats - Get System Network Statistics
3689 * @netdev: network interface device structure
3690 *
3691 * Returns the address of the device statistics structure.
3692 * The statistics are actually updated from the timer callback.
3693 **/
73cd78f1 3694static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243 3695{
9d5c8243 3696 /* only return the current stats */
8d24e933 3697 return &netdev->stats;
9d5c8243
AK		 3698}
3699
3700/**
3701 * igb_change_mtu - Change the Maximum Transfer Unit
3702 * @netdev: network interface device structure
3703 * @new_mtu: new value for maximum frame size
3704 *
3705 * Returns 0 on success, negative on failure
3706 **/
3707static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3708{
3709 struct igb_adapter *adapter = netdev_priv(netdev);
3710 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 3711 u32 rx_buffer_len, i;
9d5c8243
AK		 3712
3713 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3714 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3715 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3716 return -EINVAL;
3717 }
3718
9d5c8243
AK		 3719 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3720 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3721 return -EINVAL;
3722 }
3723
3724 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3725 msleep(1);
73cd78f1 3726
9d5c8243
AK		 3727 /* igb_down has a dependency on max_frame_size */
3728 adapter->max_frame_size = max_frame;
9d5c8243
AK		 3729 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3730 * means we reserve 2 more, this pushes us to allocate from the next
3731 * larger slab size.
3732 * i.e. RXBUFFER_2048 --> size-4096 slab
3733 */
3734
7d95b717 3735 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 3736 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 3737 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 3738 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 3739 else
4c844851
AD		 3740 rx_buffer_len = IGB_RXBUFFER_128;
3741
3742 if (netif_running(netdev))
3743 igb_down(adapter);
9d5c8243
AK		 3744
3745 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3746 netdev->mtu, new_mtu);
3747 netdev->mtu = new_mtu;
3748
4c844851
AD		 3749 for (i = 0; i < adapter->num_rx_queues; i++)
3750 adapter->rx_ring[i].rx_buffer_len = rx_buffer_len;
3751
9d5c8243
AK		 3752 if (netif_running(netdev))
3753 igb_up(adapter);
3754 else
3755 igb_reset(adapter);
3756
3757 clear_bit(__IGB_RESETTING, &adapter->state);
3758
3759 return 0;
3760}
3761
3762/**
3763 * igb_update_stats - Update the board statistics counters
3764 * @adapter: board private structure
3765 **/
3766
3767void igb_update_stats(struct igb_adapter *adapter)
3768{
8d24e933 3769 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3770 struct e1000_hw *hw = &adapter->hw;
3771 struct pci_dev *pdev = adapter->pdev;
3772 u16 phy_tmp;
3773
3774#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3775
3776 /*
3777 * Prevent stats update while adapter is being reset, or if the pci
3778 * connection is down.
3779 */
3780 if (adapter->link_speed == 0)
3781 return;
3782 if (pci_channel_offline(pdev))
3783 return;
3784
3785 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3786 adapter->stats.gprc += rd32(E1000_GPRC);
3787 adapter->stats.gorc += rd32(E1000_GORCL);
3788 rd32(E1000_GORCH); /* clear GORCL */
3789 adapter->stats.bprc += rd32(E1000_BPRC);
3790 adapter->stats.mprc += rd32(E1000_MPRC);
3791 adapter->stats.roc += rd32(E1000_ROC);
3792
3793 adapter->stats.prc64 += rd32(E1000_PRC64);
3794 adapter->stats.prc127 += rd32(E1000_PRC127);
3795 adapter->stats.prc255 += rd32(E1000_PRC255);
3796 adapter->stats.prc511 += rd32(E1000_PRC511);
3797 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3798 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3799 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3800 adapter->stats.sec += rd32(E1000_SEC);
3801
3802 adapter->stats.mpc += rd32(E1000_MPC);
3803 adapter->stats.scc += rd32(E1000_SCC);
3804 adapter->stats.ecol += rd32(E1000_ECOL);
3805 adapter->stats.mcc += rd32(E1000_MCC);
3806 adapter->stats.latecol += rd32(E1000_LATECOL);
3807 adapter->stats.dc += rd32(E1000_DC);
3808 adapter->stats.rlec += rd32(E1000_RLEC);
3809 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3810 adapter->stats.xontxc += rd32(E1000_XONTXC);
3811 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3812 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3813 adapter->stats.fcruc += rd32(E1000_FCRUC);
3814 adapter->stats.gptc += rd32(E1000_GPTC);
3815 adapter->stats.gotc += rd32(E1000_GOTCL);
3816 rd32(E1000_GOTCH); /* clear GOTCL */
3817 adapter->stats.rnbc += rd32(E1000_RNBC);
3818 adapter->stats.ruc += rd32(E1000_RUC);
3819 adapter->stats.rfc += rd32(E1000_RFC);
3820 adapter->stats.rjc += rd32(E1000_RJC);
3821 adapter->stats.tor += rd32(E1000_TORH);
3822 adapter->stats.tot += rd32(E1000_TOTH);
3823 adapter->stats.tpr += rd32(E1000_TPR);
3824
3825 adapter->stats.ptc64 += rd32(E1000_PTC64);
3826 adapter->stats.ptc127 += rd32(E1000_PTC127);
3827 adapter->stats.ptc255 += rd32(E1000_PTC255);
3828 adapter->stats.ptc511 += rd32(E1000_PTC511);
3829 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3830 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3831
3832 adapter->stats.mptc += rd32(E1000_MPTC);
3833 adapter->stats.bptc += rd32(E1000_BPTC);
3834
3835 /* used for adaptive IFS */
3836
3837 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3838 adapter->stats.tpt += hw->mac.tx_packet_delta;
3839 hw->mac.collision_delta = rd32(E1000_COLC);
3840 adapter->stats.colc += hw->mac.collision_delta;
3841
3842 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3843 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3844 adapter->stats.tncrs += rd32(E1000_TNCRS);
3845 adapter->stats.tsctc += rd32(E1000_TSCTC);
3846 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3847
3848 adapter->stats.iac += rd32(E1000_IAC);
3849 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3850 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3851 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3852 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3853 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3854 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3855 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3856 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3857
3858 /* Fill out the OS statistics structure */
8d24e933
AK		 3859 netdev->stats.multicast = adapter->stats.mprc;
3860 netdev->stats.collisions = adapter->stats.colc;
9d5c8243
AK		 3861
3862 /* Rx Errors */
3863
8c0ab70a
JDB		 3864 if (hw->mac.type != e1000_82575) {
3865 u32 rqdpc_tmp;
3ea73afa 3866 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3867 int i;
3868 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3869 * Queue Drop Packet Count) stats only gets incremented, if
3870 * the DROP_EN but it set (in the SRRCTL register for that
3871 * queue). If DROP_EN bit is NOT set, then the some what
3872 * equivalent count is stored in RNBC (not per queue basis).
3873 * Also note the drop count is due to lack of available
3874 * descriptors.
3875 */
3876 for (i = 0; i < adapter->num_rx_queues; i++) {
3877 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3878 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3879 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3880 }
8d24e933 3881 netdev->stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3882 }
3883
3ea73afa
JDB		 3884 /* Note RNBC (Receive No Buffers Count) is an not an exact
3885 * drop count as the hardware FIFO might save the day. Thats
3886 * one of the reason for saving it in rx_fifo_errors, as its
3887 * potentially not a true drop.
3888 */
8d24e933 3889 netdev->stats.rx_fifo_errors += adapter->stats.rnbc;
3ea73afa 3890
9d5c8243 3891 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3892 * our own version based on RUC and ROC */
8d24e933 3893 netdev->stats.rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 3894 adapter->stats.crcerrs + adapter->stats.algnerrc +
3895 adapter->stats.ruc + adapter->stats.roc +
3896 adapter->stats.cexterr;
8d24e933 3897 netdev->stats.rx_length_errors = adapter->stats.ruc +
9d5c8243 3898 adapter->stats.roc;
8d24e933
AK		 3899 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
3900 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
3901 netdev->stats.rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 3902
3903 /* Tx Errors */
8d24e933 3904 netdev->stats.tx_errors = adapter->stats.ecol +
9d5c8243 3905 adapter->stats.latecol;
8d24e933
AK		 3906 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
3907 netdev->stats.tx_window_errors = adapter->stats.latecol;
3908 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 3909
3910 /* Tx Dropped needs to be maintained elsewhere */
3911
3912 /* Phy Stats */
3913 if (hw->phy.media_type == e1000_media_type_copper) {
3914 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3915 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3916 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3917 adapter->phy_stats.idle_errors += phy_tmp;
3918 }
3919 }
3920
3921 /* Management Stats */
3922 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3923 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3924 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3925}
3926
9d5c8243
AK		 3927static irqreturn_t igb_msix_other(int irq, void *data)
3928{
047e0030 3929 struct igb_adapter *adapter = data;
9d5c8243 3930 struct e1000_hw *hw = &adapter->hw;
844290e5 3931 u32 icr = rd32(E1000_ICR);
844290e5 3932 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 3933
047e0030 3934 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 3935 /* HW is reporting DMA is out of sync */
3936 adapter->stats.doosync++;
3937 }
eebbbdba 3938
4ae196df
AD		 3939 /* Check for a mailbox event */
3940 if (icr & E1000_ICR_VMMB)
3941 igb_msg_task(adapter);
3942
3943 if (icr & E1000_ICR_LSC) {
3944 hw->mac.get_link_status = 1;
3945 /* guard against interrupt when we're going down */
3946 if (!test_bit(__IGB_DOWN, &adapter->state))
3947 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3948 }
3949
3950 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3951 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3952
3953 return IRQ_HANDLED;
3954}
3955
047e0030 3956static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 3957{
047e0030 3958 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 3959
047e0030
AD		 3960 if (!q_vector->set_itr)
3961 return;
73cd78f1 3962
047e0030
AD		 3963 if (!itr_val)
3964 itr_val = 0x4;
661086df 3965
047e0030
AD		 3966 if (q_vector->itr_shift)
3967 itr_val |= itr_val << q_vector->itr_shift;
661086df 3968 else
047e0030 3969 itr_val |= 0x8000000;
661086df 3970
047e0030
AD		 3971 writel(itr_val, q_vector->itr_register);
3972 q_vector->set_itr = 0;
6eb5a7f1
AD		 3973}
3974
047e0030 3975static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 3976{
047e0030 3977 struct igb_q_vector *q_vector = data;
9d5c8243 3978
047e0030
AD		 3979 /* Write the ITR value calculated from the previous interrupt. */
3980 igb_write_itr(q_vector);
9d5c8243 3981
047e0030 3982 napi_schedule(&q_vector->napi);
844290e5 3983
047e0030 3984 return IRQ_HANDLED;
fe4506b6
JC		 3985}
3986
421e02f0 3987#ifdef CONFIG_IGB_DCA
047e0030 3988static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 3989{
047e0030 3990 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 3991 struct e1000_hw *hw = &adapter->hw;
3992 int cpu = get_cpu();
fe4506b6 3993
047e0030
AD		 3994 if (q_vector->cpu == cpu)
3995 goto out_no_update;
3996
3997 if (q_vector->tx_ring) {
3998 int q = q_vector->tx_ring->reg_idx;
3999 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4000 if (hw->mac.type == e1000_82575) {
4001 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4002 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4003 } else {
047e0030
AD		 4004 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4005 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4006 E1000_DCA_TXCTRL_CPUID_SHIFT;
4007 }
4008 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4009 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4010 }
4011 if (q_vector->rx_ring) {
4012 int q = q_vector->rx_ring->reg_idx;
4013 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4014 if (hw->mac.type == e1000_82575) {
2d064c06 4015 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4016 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4017 } else {
4018 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4019 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4020 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4021 }
fe4506b6
JC		 4022 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4023 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4024 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4025 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4026 }
047e0030
AD		 4027 q_vector->cpu = cpu;
4028out_no_update:
fe4506b6
JC		 4029 put_cpu();
4030}
4031
4032static void igb_setup_dca(struct igb_adapter *adapter)
4033{
7e0e99ef 4034 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4035 int i;
4036
7dfc16fa 4037 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4038 return;
4039
7e0e99ef
AD		 4040 /* Always use CB2 mode, difference is masked in the CB driver. */
4041 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4042
047e0030
AD		 4043 for (i = 0; i < adapter->num_q_vectors; i++) {
4044 struct igb_q_vector *q_vector = adapter->q_vector[i];
4045 q_vector->cpu = -1;
4046 igb_update_dca(q_vector);
fe4506b6
JC		 4047 }
4048}
4049
4050static int __igb_notify_dca(struct device *dev, void *data)
4051{
4052 struct net_device *netdev = dev_get_drvdata(dev);
4053 struct igb_adapter *adapter = netdev_priv(netdev);
4054 struct e1000_hw *hw = &adapter->hw;
4055 unsigned long event = *(unsigned long *)data;
4056
4057 switch (event) {
4058 case DCA_PROVIDER_ADD:
4059 /* if already enabled, don't do it again */
7dfc16fa 4060 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4061 break;
fe4506b6
JC		 4062 /* Always use CB2 mode, difference is masked
4063 * in the CB driver. */
cbd347ad 4064 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 4065 if (dca_add_requester(dev) == 0) {
bbd98fe4 4066 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 4067 dev_info(&adapter->pdev->dev, "DCA enabled\n");
4068 igb_setup_dca(adapter);
4069 break;
4070 }
4071 /* Fall Through since DCA is disabled. */
4072 case DCA_PROVIDER_REMOVE:
7dfc16fa 4073 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4074 /* without this a class_device is left
047e0030 4075 * hanging around in the sysfs model */
fe4506b6
JC		 4076 dca_remove_requester(dev);
4077 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 4078 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4079 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4080 }
4081 break;
4082 }
bbd98fe4 4083
fe4506b6 4084 return 0;
9d5c8243
AK		 4085}
4086
fe4506b6
JC		 4087static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4088 void *p)
4089{
4090 int ret_val;
4091
4092 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4093 __igb_notify_dca);
4094
4095 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4096}
421e02f0 4097#endif /* CONFIG_IGB_DCA */
9d5c8243 4098
4ae196df
AD		 4099static void igb_ping_all_vfs(struct igb_adapter *adapter)
4100{
4101 struct e1000_hw *hw = &adapter->hw;
4102 u32 ping;
4103 int i;
4104
4105 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4106 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4107 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4108 ping |= E1000_VT_MSGTYPE_CTS;
4109 igb_write_mbx(hw, &ping, 1, i);
4110 }
4111}
4112
7d5753f0
AD		 4113static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4114{
4115 struct e1000_hw *hw = &adapter->hw;
4116 u32 vmolr = rd32(E1000_VMOLR(vf));
4117 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4118
4119 vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC |
4120 IGB_VF_FLAG_MULTI_PROMISC);
4121 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4122
4123 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4124 vmolr |= E1000_VMOLR_MPME;
4125 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4126 } else {
4127 /*
4128 * if we have hashes and we are clearing a multicast promisc
4129 * flag we need to write the hashes to the MTA as this step
4130 * was previously skipped
4131 */
4132 if (vf_data->num_vf_mc_hashes > 30) {
4133 vmolr |= E1000_VMOLR_MPME;
4134 } else if (vf_data->num_vf_mc_hashes) {
4135 int j;
4136 vmolr |= E1000_VMOLR_ROMPE;
4137 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4138 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4139 }
4140 }
4141
4142 wr32(E1000_VMOLR(vf), vmolr);
4143
4144 /* there are flags left unprocessed, likely not supported */
4145 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4146 return -EINVAL;
4147
4148 return 0;
4149
4150}
4151
4ae196df
AD		 4152static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4153 u32 *msgbuf, u32 vf)
4154{
4155 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4156 u16 *hash_list = (u16 *)&msgbuf[1];
4157 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4158 int i;
4159
7d5753f0 4160 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4161 * to this VF for later use to restore when the PF multi cast
4162 * list changes
4163 */
4164 vf_data->num_vf_mc_hashes = n;
4165
7d5753f0
AD		 4166 /* only up to 30 hash values supported */
4167 if (n > 30)
4168 n = 30;
4169
4170 /* store the hashes for later use */
4ae196df 4171 for (i = 0; i < n; i++)
a419aef8 4172 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4173
4174 /* Flush and reset the mta with the new values */
ff41f8dc 4175 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4176
4177 return 0;
4178}
4179
4180static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4181{
4182 struct e1000_hw *hw = &adapter->hw;
4183 struct vf_data_storage *vf_data;
4184 int i, j;
4185
4186 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4187 u32 vmolr = rd32(E1000_VMOLR(i));
4188 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4189
4ae196df 4190 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4191
4192 if ((vf_data->num_vf_mc_hashes > 30) ||
4193 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4194 vmolr |= E1000_VMOLR_MPME;
4195 } else if (vf_data->num_vf_mc_hashes) {
4196 vmolr |= E1000_VMOLR_ROMPE;
4197 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4198 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4199 }
4200 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4201 }
4202}
4203
4204static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4205{
4206 struct e1000_hw *hw = &adapter->hw;
4207 u32 pool_mask, reg, vid;
4208 int i;
4209
4210 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4211
4212 /* Find the vlan filter for this id */
4213 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4214 reg = rd32(E1000_VLVF(i));
4215
4216 /* remove the vf from the pool */
4217 reg &= ~pool_mask;
4218
4219 /* if pool is empty then remove entry from vfta */
4220 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4221 (reg & E1000_VLVF_VLANID_ENABLE)) {
4222 reg = 0;
4223 vid = reg & E1000_VLVF_VLANID_MASK;
4224 igb_vfta_set(hw, vid, false);
4225 }
4226
4227 wr32(E1000_VLVF(i), reg);
4228 }
ae641bdc
AD		 4229
4230 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4231}
4232
4233static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4234{
4235 struct e1000_hw *hw = &adapter->hw;
4236 u32 reg, i;
4237
4238 /* It is an error to call this function when VFs are not enabled */
4239 if (!adapter->vfs_allocated_count)
4240 return -1;
4241
4242 /* Find the vlan filter for this id */
4243 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4244 reg = rd32(E1000_VLVF(i));
4245 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4246 vid == (reg & E1000_VLVF_VLANID_MASK))
4247 break;
4248 }
4249
4250 if (add) {
4251 if (i == E1000_VLVF_ARRAY_SIZE) {
4252 /* Did not find a matching VLAN ID entry that was
4253 * enabled. Search for a free filter entry, i.e.
4254 * one without the enable bit set
4255 */
4256 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4257 reg = rd32(E1000_VLVF(i));
4258 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4259 break;
4260 }
4261 }
4262 if (i < E1000_VLVF_ARRAY_SIZE) {
4263 /* Found an enabled/available entry */
4264 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4265
4266 /* if !enabled we need to set this up in vfta */
4267 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4268 /* add VID to filter table, if bit already set
4269 * PF must have added it outside of table */
4270 if (igb_vfta_set(hw, vid, true))
4271 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4272 adapter->vfs_allocated_count);
4ae196df
AD		 4273 reg |= E1000_VLVF_VLANID_ENABLE;
4274 }
cad6d05f
AD		 4275 reg &= ~E1000_VLVF_VLANID_MASK;
4276 reg |= vid;
4ae196df
AD		 4277
4278 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4279
4280 /* do not modify RLPML for PF devices */
4281 if (vf >= adapter->vfs_allocated_count)
4282 return 0;
4283
4284 if (!adapter->vf_data[vf].vlans_enabled) {
4285 u32 size;
4286 reg = rd32(E1000_VMOLR(vf));
4287 size = reg & E1000_VMOLR_RLPML_MASK;
4288 size += 4;
4289 reg &= ~E1000_VMOLR_RLPML_MASK;
4290 reg |= size;
4291 wr32(E1000_VMOLR(vf), reg);
4292 }
4293 adapter->vf_data[vf].vlans_enabled++;
4294
4ae196df
AD		 4295 return 0;
4296 }
4297 } else {
4298 if (i < E1000_VLVF_ARRAY_SIZE) {
4299 /* remove vf from the pool */
4300 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4301 /* if pool is empty then remove entry from vfta */
4302 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4303 reg = 0;
4304 igb_vfta_set(hw, vid, false);
4305 }
4306 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4307
4308 /* do not modify RLPML for PF devices */
4309 if (vf >= adapter->vfs_allocated_count)
4310 return 0;
4311
4312 adapter->vf_data[vf].vlans_enabled--;
4313 if (!adapter->vf_data[vf].vlans_enabled) {
4314 u32 size;
4315 reg = rd32(E1000_VMOLR(vf));
4316 size = reg & E1000_VMOLR_RLPML_MASK;
4317 size -= 4;
4318 reg &= ~E1000_VMOLR_RLPML_MASK;
4319 reg |= size;
4320 wr32(E1000_VMOLR(vf), reg);
4321 }
4ae196df
AD		 4322 return 0;
4323 }
4324 }
4325 return -1;
4326}
4327
4328static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4329{
4330 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4331 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4332
4333 return igb_vlvf_set(adapter, vid, add, vf);
4334}
4335
f2ca0dbe 4336static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 4337{
f2ca0dbe
AD		 4338 /* clear all flags */
4339 adapter->vf_data[vf].flags = 0;
4340 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 4341
4342 /* reset offloads to defaults */
7d5753f0 4343 igb_set_vmolr(adapter, vf);
4ae196df
AD		 4344
4345 /* reset vlans for device */
4346 igb_clear_vf_vfta(adapter, vf);
4347
4348 /* reset multicast table array for vf */
4349 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4350
4351 /* Flush and reset the mta with the new values */
ff41f8dc 4352 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4353}
4354
f2ca0dbe
AD		 4355static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4356{
4357 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4358
4359 /* generate a new mac address as we were hotplug removed/added */
4360 random_ether_addr(vf_mac);
4361
4362 /* process remaining reset events */
4363 igb_vf_reset(adapter, vf);
4364}
4365
4366static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 4367{
4368 struct e1000_hw *hw = &adapter->hw;
4369 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 4370 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 4371 u32 reg, msgbuf[3];
4372 u8 *addr = (u8 *)(&msgbuf[1]);
4373
4374 /* process all the same items cleared in a function level reset */
f2ca0dbe 4375 igb_vf_reset(adapter, vf);
4ae196df
AD		 4376
4377 /* set vf mac address */
26ad9178 4378 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 4379
4380 /* enable transmit and receive for vf */
4381 reg = rd32(E1000_VFTE);
4382 wr32(E1000_VFTE, reg | (1 << vf));
4383 reg = rd32(E1000_VFRE);
4384 wr32(E1000_VFRE, reg | (1 << vf));
4385
f2ca0dbe 4386 adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
4ae196df
AD		 4387
4388 /* reply to reset with ack and vf mac address */
4389 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4390 memcpy(addr, vf_mac, 6);
4391 igb_write_mbx(hw, msgbuf, 3, vf);
4392}
4393
4394static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4395{
f2ca0dbe
AD		 4396 unsigned char *addr = (char *)&msg[1];
4397 int err = -1;
4ae196df 4398
f2ca0dbe
AD		 4399 if (is_valid_ether_addr(addr))
4400 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 4401
f2ca0dbe 4402 return err;
4ae196df
AD		 4403}
4404
4405static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4406{
4407 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4408 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4409 u32 msg = E1000_VT_MSGTYPE_NACK;
4410
4411 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 4412 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
4413 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 4414 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 4415 vf_data->last_nack = jiffies;
4ae196df
AD		 4416 }
4417}
4418
f2ca0dbe 4419static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 4420{
f2ca0dbe
AD		 4421 struct pci_dev *pdev = adapter->pdev;
4422 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 4423 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 4424 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 4425 s32 retval;
4426
f2ca0dbe 4427 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df
AD		 4428
4429 if (retval)
f2ca0dbe 4430 dev_err(&pdev->dev, "Error receiving message from VF\n");
4ae196df
AD		 4431
4432 /* this is a message we already processed, do nothing */
4433 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 4434 return;
4ae196df
AD		 4435
4436 /*
4437 * until the vf completes a reset it should not be
4438 * allowed to start any configuration.
4439 */
4440
4441 if (msgbuf[0] == E1000_VF_RESET) {
4442 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 4443 return;
4ae196df
AD		 4444 }
4445
f2ca0dbe
AD		 4446 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
4447 msgbuf[0] = E1000_VT_MSGTYPE_NACK;
4448 if (time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4449 igb_write_mbx(hw, msgbuf, 1, vf);
4450 vf_data->last_nack = jiffies;
4451 }
4452 return;
4ae196df
AD		 4453 }
4454
4455 switch ((msgbuf[0] & 0xFFFF)) {
4456 case E1000_VF_SET_MAC_ADDR:
4457 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4458 break;
7d5753f0
AD		 4459 case E1000_VF_SET_PROMISC:
4460 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
4461 break;
4ae196df
AD		 4462 case E1000_VF_SET_MULTICAST:
4463 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4464 break;
4465 case E1000_VF_SET_LPE:
4466 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4467 break;
4468 case E1000_VF_SET_VLAN:
4469 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4470 break;
4471 default:
4472 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4473 retval = -1;
4474 break;
4475 }
4476
4477 /* notify the VF of the results of what it sent us */
4478 if (retval)
4479 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4480 else
4481 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4482
4483 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4484
4485 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 4486}
4ae196df 4487
f2ca0dbe
AD		 4488static void igb_msg_task(struct igb_adapter *adapter)
4489{
4490 struct e1000_hw *hw = &adapter->hw;
4491 u32 vf;
4492
4493 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4494 /* process any reset requests */
4495 if (!igb_check_for_rst(hw, vf))
4496 igb_vf_reset_event(adapter, vf);
4497
4498 /* process any messages pending */
4499 if (!igb_check_for_msg(hw, vf))
4500 igb_rcv_msg_from_vf(adapter, vf);
4501
4502 /* process any acks */
4503 if (!igb_check_for_ack(hw, vf))
4504 igb_rcv_ack_from_vf(adapter, vf);
4505 }
4ae196df
AD		 4506}
4507
68d480c4
AD		 4508/**
4509 * igb_set_uta - Set unicast filter table address
4510 * @adapter: board private structure
4511 *
4512 * The unicast table address is a register array of 32-bit registers.
4513 * The table is meant to be used in a way similar to how the MTA is used
4514 * however due to certain limitations in the hardware it is necessary to
4515 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
4516 * enable bit to allow vlan tag stripping when promiscous mode is enabled
4517 **/
4518static void igb_set_uta(struct igb_adapter *adapter)
4519{
4520 struct e1000_hw *hw = &adapter->hw;
4521 int i;
4522
4523 /* The UTA table only exists on 82576 hardware and newer */
4524 if (hw->mac.type < e1000_82576)
4525 return;
4526
4527 /* we only need to do this if VMDq is enabled */
4528 if (!adapter->vfs_allocated_count)
4529 return;
4530
4531 for (i = 0; i < hw->mac.uta_reg_count; i++)
4532 array_wr32(E1000_UTA, i, ~0);
4533}
4534
9d5c8243
AK		 4535/**
4536 * igb_intr_msi - Interrupt Handler
4537 * @irq: interrupt number
4538 * @data: pointer to a network interface device structure
4539 **/
4540static irqreturn_t igb_intr_msi(int irq, void *data)
4541{
047e0030
AD		 4542 struct igb_adapter *adapter = data;
4543 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4544 struct e1000_hw *hw = &adapter->hw;
4545 /* read ICR disables interrupts using IAM */
4546 u32 icr = rd32(E1000_ICR);
4547
047e0030 4548 igb_write_itr(q_vector);
9d5c8243 4549
047e0030 4550 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4551 /* HW is reporting DMA is out of sync */
4552 adapter->stats.doosync++;
4553 }
4554
9d5c8243
AK		 4555 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4556 hw->mac.get_link_status = 1;
4557 if (!test_bit(__IGB_DOWN, &adapter->state))
4558 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4559 }
4560
047e0030 4561 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4562
4563 return IRQ_HANDLED;
4564}
4565
4566/**
4a3c6433 4567 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4568 * @irq: interrupt number
4569 * @data: pointer to a network interface device structure
4570 **/
4571static irqreturn_t igb_intr(int irq, void *data)
4572{
047e0030
AD		 4573 struct igb_adapter *adapter = data;
4574 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 4575 struct e1000_hw *hw = &adapter->hw;
4576 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4577 * need for the IMC write */
4578 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4579 if (!icr)
4580 return IRQ_NONE; /* Not our interrupt */
4581
047e0030 4582 igb_write_itr(q_vector);
9d5c8243
AK		 4583
4584 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4585 * not set, then the adapter didn't send an interrupt */
4586 if (!(icr & E1000_ICR_INT_ASSERTED))
4587 return IRQ_NONE;
4588
047e0030 4589 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4590 /* HW is reporting DMA is out of sync */
4591 adapter->stats.doosync++;
4592 }
4593
9d5c8243
AK		 4594 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4595 hw->mac.get_link_status = 1;
4596 /* guard against interrupt when we're going down */
4597 if (!test_bit(__IGB_DOWN, &adapter->state))
4598 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4599 }
4600
047e0030 4601 napi_schedule(&q_vector->napi);
9d5c8243
AK		 4602
4603 return IRQ_HANDLED;
4604}
4605
047e0030 4606static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 4607{
047e0030 4608 struct igb_adapter *adapter = q_vector->adapter;
46544258 4609 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4610
4fc82adf
AD		 4611 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
4612 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 4613 if (!adapter->msix_entries)
6eb5a7f1 4614 igb_set_itr(adapter);
46544258 4615 else
047e0030 4616 igb_update_ring_itr(q_vector);
9d5c8243
AK		 4617 }
4618
46544258
AD		 4619 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4620 if (adapter->msix_entries)
047e0030 4621 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 4622 else
4623 igb_irq_enable(adapter);
4624 }
9d5c8243
AK		 4625}
4626
46544258
AD		 4627/**
4628 * igb_poll - NAPI Rx polling callback
4629 * @napi: napi polling structure
4630 * @budget: count of how many packets we should handle
4631 **/
4632static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 4633{
047e0030
AD		 4634 struct igb_q_vector *q_vector = container_of(napi,
4635 struct igb_q_vector,
4636 napi);
4637 int tx_clean_complete = 1, work_done = 0;
9d5c8243 4638
421e02f0 4639#ifdef CONFIG_IGB_DCA
047e0030
AD		 4640 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
4641 igb_update_dca(q_vector);
fe4506b6 4642#endif
047e0030
AD		 4643 if (q_vector->tx_ring)
4644 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 4645
047e0030
AD		 4646 if (q_vector->rx_ring)
4647 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
4648
4649 if (!tx_clean_complete)
4650 work_done = budget;
46544258 4651
9d5c8243 4652 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4653 if (work_done < budget) {
288379f0 4654 napi_complete(napi);
047e0030 4655 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 4656 }
4657
46544258 4658 return work_done;
9d5c8243 4659}
6d8126f9 4660
33af6bcc 4661/**
c5b9bd5e 4662 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 4663 * @adapter: board private structure
c5b9bd5e
AD		 4664 * @shhwtstamps: timestamp structure to update
4665 * @regval: unsigned 64bit system time value.
4666 *
4667 * We need to convert the system time value stored in the RX/TXSTMP registers
4668 * into a hwtstamp which can be used by the upper level timestamping functions
4669 */
4670static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
4671 struct skb_shared_hwtstamps *shhwtstamps,
4672 u64 regval)
4673{
4674 u64 ns;
4675
4676 ns = timecounter_cyc2time(&adapter->clock, regval);
4677 timecompare_update(&adapter->compare, ns);
4678 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
4679 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4680 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
4681}
4682
4683/**
4684 * igb_tx_hwtstamp - utility function which checks for TX time stamp
4685 * @q_vector: pointer to q_vector containing needed info
33af6bcc
PO		 4686 * @skb: packet that was just sent
4687 *
4688 * If we were asked to do hardware stamping and such a time stamp is
4689 * available, then it must have been for this skb here because we only
4690 * allow only one such packet into the queue.
4691 */
c5b9bd5e 4692static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
33af6bcc 4693{
c5b9bd5e 4694 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc
PO		 4695 union skb_shared_tx *shtx = skb_tx(skb);
4696 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 4697 struct skb_shared_hwtstamps shhwtstamps;
4698 u64 regval;
33af6bcc 4699
c5b9bd5e
AD		 4700 /* if skb does not support hw timestamp or TX stamp not valid exit */
4701 if (likely(!shtx->hardware) ||
4702 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
4703 return;
4704
4705 regval = rd32(E1000_TXSTMPL);
4706 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4707
4708 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
4709 skb_tstamp_tx(skb, &shhwtstamps);
33af6bcc
PO		 4710}
4711
9d5c8243
AK		 4712/**
4713 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 4714 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 4715 * returns true if ring is completely cleaned
4716 **/
047e0030 4717static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 4718{
047e0030
AD		 4719 struct igb_adapter *adapter = q_vector->adapter;
4720 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 4721 struct net_device *netdev = tx_ring->netdev;
0e014cb1 4722 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4723 struct igb_buffer *buffer_info;
4724 struct sk_buff *skb;
0e014cb1 4725 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4726 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4727 unsigned int i, eop, count = 0;
4728 bool cleaned = false;
9d5c8243 4729
9d5c8243 4730 i = tx_ring->next_to_clean;
0e014cb1
AD		 4731 eop = tx_ring->buffer_info[i].next_to_watch;
4732 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4733
4734 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4735 (count < tx_ring->count)) {
4736 for (cleaned = false; !cleaned; count++) {
4737 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4738 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4739 cleaned = (i == eop);
9d5c8243
AK		 4740 skb = buffer_info->skb;
4741
4742 if (skb) {
4743 unsigned int segs, bytecount;
4744 /* gso_segs is currently only valid for tcp */
4745 segs = skb_shinfo(skb)->gso_segs ?: 1;
4746 /* multiply data chunks by size of headers */
4747 bytecount = ((segs - 1) * skb_headlen(skb)) +
4748 skb->len;
4749 total_packets += segs;
4750 total_bytes += bytecount;
33af6bcc 4751
c5b9bd5e 4752 igb_tx_hwtstamp(q_vector, skb);
9d5c8243
AK		 4753 }
4754
80785298 4755 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 4756 tx_desc->wb.status = 0;
9d5c8243
AK		 4757
4758 i++;
4759 if (i == tx_ring->count)
4760 i = 0;
9d5c8243 4761 }
0e014cb1
AD		 4762 eop = tx_ring->buffer_info[i].next_to_watch;
4763 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4764 }
4765
9d5c8243
AK		 4766 tx_ring->next_to_clean = i;
4767
fc7d345d 4768 if (unlikely(count &&
9d5c8243 4769 netif_carrier_ok(netdev) &&
c493ea45 4770 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4771 /* Make sure that anybody stopping the queue after this
4772 * sees the new next_to_clean.
4773 */
4774 smp_mb();
661086df
PWJ		 4775 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4776 !(test_bit(__IGB_DOWN, &adapter->state))) {
4777 netif_wake_subqueue(netdev, tx_ring->queue_index);
04a5fcaa 4778 tx_ring->tx_stats.restart_queue++;
661086df 4779 }
9d5c8243
AK		 4780 }
4781
4782 if (tx_ring->detect_tx_hung) {
4783 /* Detect a transmit hang in hardware, this serializes the
4784 * check with the clearing of time_stamp and movement of i */
4785 tx_ring->detect_tx_hung = false;
4786 if (tx_ring->buffer_info[i].time_stamp &&
4787 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4788 (adapter->tx_timeout_factor * HZ))
4789 && !(rd32(E1000_STATUS) &
4790 E1000_STATUS_TXOFF)) {
4791
9d5c8243 4792 /* detected Tx unit hang */
80785298 4793 dev_err(&tx_ring->pdev->dev,
9d5c8243 4794 "Detected Tx Unit Hang\n"
2d064c06 4795 " Tx Queue <%d>\n"
9d5c8243
AK		 4796 " TDH <%x>\n"
4797 " TDT <%x>\n"
4798 " next_to_use <%x>\n"
4799 " next_to_clean <%x>\n"
9d5c8243
AK		 4800 "buffer_info[next_to_clean]\n"
4801 " time_stamp <%lx>\n"
0e014cb1 4802 " next_to_watch <%x>\n"
9d5c8243
AK		 4803 " jiffies <%lx>\n"
4804 " desc.status <%x>\n",
2d064c06 4805 tx_ring->queue_index,
fce99e34
AD		 4806 readl(tx_ring->head),
4807 readl(tx_ring->tail),
9d5c8243
AK		 4808 tx_ring->next_to_use,
4809 tx_ring->next_to_clean,
9d5c8243 4810 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4811 eop,
9d5c8243 4812 jiffies,
0e014cb1 4813 eop_desc->wb.status);
661086df 4814 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4815 }
4816 }
4817 tx_ring->total_bytes += total_bytes;
4818 tx_ring->total_packets += total_packets;
e21ed353
AD		 4819 tx_ring->tx_stats.bytes += total_bytes;
4820 tx_ring->tx_stats.packets += total_packets;
8d24e933
AK		 4821 netdev->stats.tx_bytes += total_bytes;
4822 netdev->stats.tx_packets += total_packets;
0e014cb1 4823 return (count < tx_ring->count);
9d5c8243
AK		 4824}
4825
9d5c8243
AK		 4826/**
4827 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 4828 * @q_vector: structure containing interrupt and ring information
4829 * @skb: packet to send up
4830 * @vlan_tag: vlan tag for packet
9d5c8243 4831 **/
047e0030
AD		 4832static void igb_receive_skb(struct igb_q_vector *q_vector,
4833 struct sk_buff *skb,
4834 u16 vlan_tag)
4835{
4836 struct igb_adapter *adapter = q_vector->adapter;
4837
4838 if (vlan_tag)
4839 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
4840 vlan_tag, skb);
182ff8df 4841 else
047e0030 4842 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 4843}
4844
04a5fcaa 4845static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 4846 u32 status_err, struct sk_buff *skb)
4847{
4848 skb->ip_summed = CHECKSUM_NONE;
4849
4850 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 4851 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
4852 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 4853 return;
85ad76b2 4854
9d5c8243
AK		 4855 /* TCP/UDP checksum error bit is set */
4856 if (status_err &
4857 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4858 /*
4859 * work around errata with sctp packets where the TCPE aka
4860 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4861 * packets, (aka let the stack check the crc32c)
4862 */
85ad76b2
AD		 4863 if ((skb->len == 60) &&
4864 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM))
04a5fcaa 4865 ring->rx_stats.csum_err++;
85ad76b2 4866
9d5c8243 4867 /* let the stack verify checksum errors */
9d5c8243
AK		 4868 return;
4869 }
4870 /* It must be a TCP or UDP packet with a valid checksum */
4871 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4872 skb->ip_summed = CHECKSUM_UNNECESSARY;
4873
85ad76b2 4874 dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4875}
4876
c5b9bd5e
AD		 4877static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
4878 struct sk_buff *skb)
4879{
4880 struct igb_adapter *adapter = q_vector->adapter;
4881 struct e1000_hw *hw = &adapter->hw;
4882 u64 regval;
4883
4884 /*
4885 * If this bit is set, then the RX registers contain the time stamp. No
4886 * other packet will be time stamped until we read these registers, so
4887 * read the registers to make them available again. Because only one
4888 * packet can be time stamped at a time, we know that the register
4889 * values must belong to this one here and therefore we don't need to
4890 * compare any of the additional attributes stored for it.
4891 *
4892 * If nothing went wrong, then it should have a skb_shared_tx that we
4893 * can turn into a skb_shared_hwtstamps.
4894 */
4895 if (likely(!(staterr & E1000_RXDADV_STAT_TS)))
4896 return;
4897 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
4898 return;
4899
4900 regval = rd32(E1000_RXSTMPL);
4901 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4902
4903 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
4904}
4c844851 4905static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 4906 union e1000_adv_rx_desc *rx_desc)
4907{
4908 /* HW will not DMA in data larger than the given buffer, even if it
4909 * parses the (NFS, of course) header to be larger. In that case, it
4910 * fills the header buffer and spills the rest into the page.
4911 */
4912 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4913 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 4914 if (hlen > rx_ring->rx_buffer_len)
4915 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 4916 return hlen;
4917}
4918
047e0030
AD		 4919static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
4920 int *work_done, int budget)
9d5c8243 4921{
047e0030 4922 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 4923 struct net_device *netdev = rx_ring->netdev;
80785298 4924 struct pci_dev *pdev = rx_ring->pdev;
9d5c8243
AK		 4925 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4926 struct igb_buffer *buffer_info , *next_buffer;
4927 struct sk_buff *skb;
9d5c8243
AK		 4928 bool cleaned = false;
4929 int cleaned_count = 0;
4930 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 4931 unsigned int i;
2d94d8ab
AD		 4932 u32 staterr;
4933 u16 length;
047e0030 4934 u16 vlan_tag;
9d5c8243
AK		 4935
4936 i = rx_ring->next_to_clean;
69d3ca53 4937 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4938 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4939 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4940
4941 while (staterr & E1000_RXD_STAT_DD) {
4942 if (*work_done >= budget)
4943 break;
4944 (*work_done)++;
9d5c8243 4945
69d3ca53
AD		 4946 skb = buffer_info->skb;
4947 prefetch(skb->data - NET_IP_ALIGN);
4948 buffer_info->skb = NULL;
4949
4950 i++;
4951 if (i == rx_ring->count)
4952 i = 0;
4953 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4954 prefetch(next_rxd);
4955 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4956
4957 length = le16_to_cpu(rx_desc->wb.upper.length);
4958 cleaned = true;
4959 cleaned_count++;
4960
2d94d8ab 4961 if (buffer_info->dma) {
bf36c1a0 4962 pci_unmap_single(pdev, buffer_info->dma,
4c844851 4963 rx_ring->rx_buffer_len,
bf36c1a0 4964 PCI_DMA_FROMDEVICE);
91615f76 4965 buffer_info->dma = 0;
4c844851 4966 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 4967 skb_put(skb, length);
4968 goto send_up;
4969 }
4c844851 4970 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 4971 }
4972
4973 if (length) {
9d5c8243 4974 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4975 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4976 buffer_info->page_dma = 0;
bf36c1a0
AD		 4977
4978 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4979 buffer_info->page,
4980 buffer_info->page_offset,
4981 length);
4982
6ec43fe6 4983 if (page_count(buffer_info->page) != 1)
bf36c1a0
AD		 4984 buffer_info->page = NULL;
4985 else
4986 get_page(buffer_info->page);
9d5c8243
AK		 4987
4988 skb->len += length;
4989 skb->data_len += length;
9d5c8243 4990
bf36c1a0 4991 skb->truesize += length;
9d5c8243 4992 }
9d5c8243 4993
bf36c1a0 4994 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4995 buffer_info->skb = next_buffer->skb;
4996 buffer_info->dma = next_buffer->dma;
4997 next_buffer->skb = skb;
4998 next_buffer->dma = 0;
bf36c1a0
AD		 4999 goto next_desc;
5000 }
69d3ca53 5001send_up:
9d5c8243
AK		 5002 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5003 dev_kfree_skb_irq(skb);
5004 goto next_desc;
5005 }
9d5c8243 5006
c5b9bd5e 5007 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5008 total_bytes += skb->len;
5009 total_packets++;
5010
85ad76b2 5011 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5012
5013 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5014 skb_record_rx_queue(skb, rx_ring->queue_index);
5015
5016 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5017 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5018
047e0030 5019 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5020
9d5c8243
AK		 5021next_desc:
5022 rx_desc->wb.upper.status_error = 0;
5023
5024 /* return some buffers to hardware, one at a time is too slow */
5025 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5026 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5027 cleaned_count = 0;
5028 }
5029
5030 /* use prefetched values */
5031 rx_desc = next_rxd;
5032 buffer_info = next_buffer;
9d5c8243
AK		 5033 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5034 }
bf36c1a0 5035
9d5c8243 5036 rx_ring->next_to_clean = i;
c493ea45 5037 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5038
5039 if (cleaned_count)
3b644cf6 5040 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5041
5042 rx_ring->total_packets += total_packets;
5043 rx_ring->total_bytes += total_bytes;
5044 rx_ring->rx_stats.packets += total_packets;
5045 rx_ring->rx_stats.bytes += total_bytes;
8d24e933
AK		 5046 netdev->stats.rx_bytes += total_bytes;
5047 netdev->stats.rx_packets += total_packets;
9d5c8243
AK		 5048 return cleaned;
5049}
5050
9d5c8243
AK		 5051/**
5052 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5053 * @adapter: address of board private structure
5054 **/
d7ee5b3a 5055void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5056{
e694e964 5057 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5058 union e1000_adv_rx_desc *rx_desc;
5059 struct igb_buffer *buffer_info;
5060 struct sk_buff *skb;
5061 unsigned int i;
db761762 5062 int bufsz;
9d5c8243
AK		 5063
5064 i = rx_ring->next_to_use;
5065 buffer_info = &rx_ring->buffer_info[i];
5066
4c844851 5067 bufsz = rx_ring->rx_buffer_len;
db761762 5068
9d5c8243
AK		 5069 while (cleaned_count--) {
5070 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5071
6ec43fe6 5072 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5073 if (!buffer_info->page) {
bf36c1a0
AD		 5074 buffer_info->page = alloc_page(GFP_ATOMIC);
5075 if (!buffer_info->page) {
04a5fcaa 5076 rx_ring->rx_stats.alloc_failed++;
bf36c1a0
AD		 5077 goto no_buffers;
5078 }
5079 buffer_info->page_offset = 0;
5080 } else {
5081 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5082 }
5083 buffer_info->page_dma =
80785298 5084 pci_map_page(rx_ring->pdev, buffer_info->page,
bf36c1a0
AD		 5085 buffer_info->page_offset,
5086 PAGE_SIZE / 2,
9d5c8243
AK		 5087 PCI_DMA_FROMDEVICE);
5088 }
5089
5090 if (!buffer_info->skb) {
89d71a66 5091 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
9d5c8243 5092 if (!skb) {
04a5fcaa 5093 rx_ring->rx_stats.alloc_failed++;
9d5c8243
AK		 5094 goto no_buffers;
5095 }
5096
9d5c8243 5097 buffer_info->skb = skb;
80785298
AD		 5098 buffer_info->dma = pci_map_single(rx_ring->pdev,
5099 skb->data,
9d5c8243
AK		 5100 bufsz,
5101 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 5102 }
5103 /* Refresh the desc even if buffer_addrs didn't change because
5104 * each write-back erases this info. */
6ec43fe6 5105 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5106 rx_desc->read.pkt_addr =
5107 cpu_to_le64(buffer_info->page_dma);
5108 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5109 } else {
5110 rx_desc->read.pkt_addr =
5111 cpu_to_le64(buffer_info->dma);
5112 rx_desc->read.hdr_addr = 0;
5113 }
5114
5115 i++;
5116 if (i == rx_ring->count)
5117 i = 0;
5118 buffer_info = &rx_ring->buffer_info[i];
5119 }
5120
5121no_buffers:
5122 if (rx_ring->next_to_use != i) {
5123 rx_ring->next_to_use = i;
5124 if (i == 0)
5125 i = (rx_ring->count - 1);
5126 else
5127 i--;
5128
5129 /* Force memory writes to complete before letting h/w
5130 * know there are new descriptors to fetch. (Only
5131 * applicable for weak-ordered memory model archs,
5132 * such as IA-64). */
5133 wmb();
fce99e34 5134 writel(i, rx_ring->tail);
9d5c8243
AK		 5135 }
5136}
5137
5138/**
5139 * igb_mii_ioctl -
5140 * @netdev:
5141 * @ifreq:
5142 * @cmd:
5143 **/
5144static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5145{
5146 struct igb_adapter *adapter = netdev_priv(netdev);
5147 struct mii_ioctl_data *data = if_mii(ifr);
5148
5149 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5150 return -EOPNOTSUPP;
5151
5152 switch (cmd) {
5153 case SIOCGMIIPHY:
5154 data->phy_id = adapter->hw.phy.addr;
5155 break;
5156 case SIOCGMIIREG:
f5f4cf08
AD		 5157 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5158 &data->val_out))
9d5c8243
AK		 5159 return -EIO;
5160 break;
5161 case SIOCSMIIREG:
5162 default:
5163 return -EOPNOTSUPP;
5164 }
5165 return 0;
5166}
5167
c6cb090b
PO		 5168/**
5169 * igb_hwtstamp_ioctl - control hardware time stamping
5170 * @netdev:
5171 * @ifreq:
5172 * @cmd:
5173 *
33af6bcc
PO		 5174 * Outgoing time stamping can be enabled and disabled. Play nice and
5175 * disable it when requested, although it shouldn't case any overhead
5176 * when no packet needs it. At most one packet in the queue may be
5177 * marked for time stamping, otherwise it would be impossible to tell
5178 * for sure to which packet the hardware time stamp belongs.
5179 *
5180 * Incoming time stamping has to be configured via the hardware
5181 * filters. Not all combinations are supported, in particular event
5182 * type has to be specified. Matching the kind of event packet is
5183 * not supported, with the exception of "all V2 events regardless of
5184 * level 2 or 4".
5185 *
c6cb090b
PO		 5186 **/
5187static int igb_hwtstamp_ioctl(struct net_device *netdev,
5188 struct ifreq *ifr, int cmd)
5189{
33af6bcc
PO		 5190 struct igb_adapter *adapter = netdev_priv(netdev);
5191 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5192 struct hwtstamp_config config;
c5b9bd5e
AD		 5193 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5194 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5195 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5196 bool is_l4 = false;
5197 bool is_l2 = false;
33af6bcc 5198 u32 regval;
c6cb090b
PO		 5199
5200 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5201 return -EFAULT;
5202
5203 /* reserved for future extensions */
5204 if (config.flags)
5205 return -EINVAL;
5206
33af6bcc
PO		 5207 switch (config.tx_type) {
5208 case HWTSTAMP_TX_OFF:
c5b9bd5e 5209 tsync_tx_ctl = 0;
33af6bcc 5210 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5211 break;
5212 default:
5213 return -ERANGE;
5214 }
5215
5216 switch (config.rx_filter) {
5217 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5218 tsync_rx_ctl = 0;
33af6bcc
PO		 5219 break;
5220 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5221 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5222 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5223 case HWTSTAMP_FILTER_ALL:
5224 /*
5225 * register TSYNCRXCFG must be set, therefore it is not
5226 * possible to time stamp both Sync and Delay_Req messages
5227 * => fall back to time stamping all packets
5228 */
c5b9bd5e 5229 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 5230 config.rx_filter = HWTSTAMP_FILTER_ALL;
5231 break;
5232 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 5233 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5234 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 5235 is_l4 = true;
33af6bcc
PO		 5236 break;
5237 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 5238 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 5239 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 5240 is_l4 = true;
33af6bcc
PO		 5241 break;
5242 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5243 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 5244 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5245 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 5246 is_l2 = true;
5247 is_l4 = true;
33af6bcc
PO		 5248 config.rx_filter = HWTSTAMP_FILTER_SOME;
5249 break;
5250 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5251 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 5252 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 5253 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 5254 is_l2 = true;
5255 is_l4 = true;
33af6bcc
PO		 5256 config.rx_filter = HWTSTAMP_FILTER_SOME;
5257 break;
5258 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5259 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5260 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 5261 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 5262 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 5263 is_l2 = true;
33af6bcc
PO		 5264 break;
5265 default:
5266 return -ERANGE;
5267 }
5268
c5b9bd5e
AD		 5269 if (hw->mac.type == e1000_82575) {
5270 if (tsync_rx_ctl | tsync_tx_ctl)
5271 return -EINVAL;
5272 return 0;
5273 }
5274
33af6bcc
PO		 5275 /* enable/disable TX */
5276 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 5277 regval &= ~E1000_TSYNCTXCTL_ENABLED;
5278 regval |= tsync_tx_ctl;
33af6bcc
PO		 5279 wr32(E1000_TSYNCTXCTL, regval);
5280
c5b9bd5e 5281 /* enable/disable RX */
33af6bcc 5282 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 5283 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
5284 regval |= tsync_rx_ctl;
33af6bcc 5285 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 5286
c5b9bd5e
AD		 5287 /* define which PTP packets are time stamped */
5288 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 5289
c5b9bd5e
AD		 5290 /* define ethertype filter for timestamped packets */
5291 if (is_l2)
5292 wr32(E1000_ETQF(3),
5293 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
5294 E1000_ETQF_1588 | /* enable timestamping */
5295 ETH_P_1588)); /* 1588 eth protocol type */
5296 else
5297 wr32(E1000_ETQF(3), 0);
5298
5299#define PTP_PORT 319
5300 /* L4 Queue Filter[3]: filter by destination port and protocol */
5301 if (is_l4) {
5302 u32 ftqf = (IPPROTO_UDP /* UDP */
5303 | E1000_FTQF_VF_BP /* VF not compared */
5304 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
5305 | E1000_FTQF_MASK); /* mask all inputs */
5306 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
5307
5308 wr32(E1000_IMIR(3), htons(PTP_PORT));
5309 wr32(E1000_IMIREXT(3),
5310 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
5311 if (hw->mac.type == e1000_82576) {
5312 /* enable source port check */
5313 wr32(E1000_SPQF(3), htons(PTP_PORT));
5314 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
5315 }
5316 wr32(E1000_FTQF(3), ftqf);
5317 } else {
5318 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
5319 }
33af6bcc
PO		 5320 wrfl();
5321
5322 adapter->hwtstamp_config = config;
5323
5324 /* clear TX/RX time stamp registers, just to be sure */
5325 regval = rd32(E1000_TXSTMPH);
5326 regval = rd32(E1000_RXSTMPH);
c6cb090b 5327
33af6bcc
PO		 5328 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5329 -EFAULT : 0;
c6cb090b
PO		 5330}
5331
9d5c8243
AK		 5332/**
5333 * igb_ioctl -
5334 * @netdev:
5335 * @ifreq:
5336 * @cmd:
5337 **/
5338static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5339{
5340 switch (cmd) {
5341 case SIOCGMIIPHY:
5342 case SIOCGMIIREG:
5343 case SIOCSMIIREG:
5344 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5345 case SIOCSHWTSTAMP:
5346 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5347 default:
5348 return -EOPNOTSUPP;
5349 }
5350}
5351
009bc06e
AD		 5352s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5353{
5354 struct igb_adapter *adapter = hw->back;
5355 u16 cap_offset;
5356
5357 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5358 if (!cap_offset)
5359 return -E1000_ERR_CONFIG;
5360
5361 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5362
5363 return 0;
5364}
5365
5366s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5367{
5368 struct igb_adapter *adapter = hw->back;
5369 u16 cap_offset;
5370
5371 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5372 if (!cap_offset)
5373 return -E1000_ERR_CONFIG;
5374
5375 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5376
5377 return 0;
5378}
5379
9d5c8243
AK		 5380static void igb_vlan_rx_register(struct net_device *netdev,
5381 struct vlan_group *grp)
5382{
5383 struct igb_adapter *adapter = netdev_priv(netdev);
5384 struct e1000_hw *hw = &adapter->hw;
5385 u32 ctrl, rctl;
5386
5387 igb_irq_disable(adapter);
5388 adapter->vlgrp = grp;
5389
5390 if (grp) {
5391 /* enable VLAN tag insert/strip */
5392 ctrl = rd32(E1000_CTRL);
5393 ctrl |= E1000_CTRL_VME;
5394 wr32(E1000_CTRL, ctrl);
5395
5396 /* enable VLAN receive filtering */
5397 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5398 rctl &= ~E1000_RCTL_CFIEN;
5399 wr32(E1000_RCTL, rctl);
5400 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5401 } else {
5402 /* disable VLAN tag insert/strip */
5403 ctrl = rd32(E1000_CTRL);
5404 ctrl &= ~E1000_CTRL_VME;
5405 wr32(E1000_CTRL, ctrl);
5406
9d5c8243
AK		 5407 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5408 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5409 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5410 }
9d5c8243
AK		 5411 }
5412
e1739522
AD		 5413 igb_rlpml_set(adapter);
5414
9d5c8243
AK		 5415 if (!test_bit(__IGB_DOWN, &adapter->state))
5416 igb_irq_enable(adapter);
5417}
5418
5419static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5420{
5421 struct igb_adapter *adapter = netdev_priv(netdev);
5422 struct e1000_hw *hw = &adapter->hw;
4ae196df 5423 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5424
28b0759c 5425 if ((hw->mng_cookie.status &
9d5c8243
AK		 5426 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5427 (vid == adapter->mng_vlan_id))
5428 return;
4ae196df
AD		 5429
5430 /* add vid to vlvf if sr-iov is enabled,
5431 * if that fails add directly to filter table */
5432 if (igb_vlvf_set(adapter, vid, true, pf_id))
5433 igb_vfta_set(hw, vid, true);
5434
9d5c8243
AK		 5435}
5436
5437static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5438{
5439 struct igb_adapter *adapter = netdev_priv(netdev);
5440 struct e1000_hw *hw = &adapter->hw;
4ae196df 5441 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5442
5443 igb_irq_disable(adapter);
5444 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5445
5446 if (!test_bit(__IGB_DOWN, &adapter->state))
5447 igb_irq_enable(adapter);
5448
5449 if ((adapter->hw.mng_cookie.status &
5450 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5451 (vid == adapter->mng_vlan_id)) {
5452 /* release control to f/w */
5453 igb_release_hw_control(adapter);
5454 return;
5455 }
5456
4ae196df
AD		 5457 /* remove vid from vlvf if sr-iov is enabled,
5458 * if not in vlvf remove from vfta */
5459 if (igb_vlvf_set(adapter, vid, false, pf_id))
5460 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5461}
5462
5463static void igb_restore_vlan(struct igb_adapter *adapter)
5464{
5465 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5466
5467 if (adapter->vlgrp) {
5468 u16 vid;
5469 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5470 if (!vlan_group_get_device(adapter->vlgrp, vid))
5471 continue;
5472 igb_vlan_rx_add_vid(adapter->netdev, vid);
5473 }
5474 }
5475}
5476
5477int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5478{
5479 struct e1000_mac_info *mac = &adapter->hw.mac;
5480
5481 mac->autoneg = 0;
5482
9d5c8243
AK		 5483 switch (spddplx) {
5484 case SPEED_10 + DUPLEX_HALF:
5485 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5486 break;
5487 case SPEED_10 + DUPLEX_FULL:
5488 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5489 break;
5490 case SPEED_100 + DUPLEX_HALF:
5491 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5492 break;
5493 case SPEED_100 + DUPLEX_FULL:
5494 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5495 break;
5496 case SPEED_1000 + DUPLEX_FULL:
5497 mac->autoneg = 1;
5498 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5499 break;
5500 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5501 default:
5502 dev_err(&adapter->pdev->dev,
5503 "Unsupported Speed/Duplex configuration\n");
5504 return -EINVAL;
5505 }
5506 return 0;
5507}
5508
3fe7c4c9 5509static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5510{
5511 struct net_device *netdev = pci_get_drvdata(pdev);
5512 struct igb_adapter *adapter = netdev_priv(netdev);
5513 struct e1000_hw *hw = &adapter->hw;
2d064c06 5514 u32 ctrl, rctl, status;
9d5c8243
AK		 5515 u32 wufc = adapter->wol;
5516#ifdef CONFIG_PM
5517 int retval = 0;
5518#endif
5519
5520 netif_device_detach(netdev);
5521
a88f10ec
AD		 5522 if (netif_running(netdev))
5523 igb_close(netdev);
5524
047e0030 5525 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 5526
5527#ifdef CONFIG_PM
5528 retval = pci_save_state(pdev);
5529 if (retval)
5530 return retval;
5531#endif
5532
5533 status = rd32(E1000_STATUS);
5534 if (status & E1000_STATUS_LU)
5535 wufc &= ~E1000_WUFC_LNKC;
5536
5537 if (wufc) {
5538 igb_setup_rctl(adapter);
ff41f8dc 5539 igb_set_rx_mode(netdev);
9d5c8243
AK		 5540
5541 /* turn on all-multi mode if wake on multicast is enabled */
5542 if (wufc & E1000_WUFC_MC) {
5543 rctl = rd32(E1000_RCTL);
5544 rctl |= E1000_RCTL_MPE;
5545 wr32(E1000_RCTL, rctl);
5546 }
5547
5548 ctrl = rd32(E1000_CTRL);
5549 /* advertise wake from D3Cold */
5550 #define E1000_CTRL_ADVD3WUC 0x00100000
5551 /* phy power management enable */
5552 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5553 ctrl |= E1000_CTRL_ADVD3WUC;
5554 wr32(E1000_CTRL, ctrl);
5555
9d5c8243
AK		 5556 /* Allow time for pending master requests to run */
5557 igb_disable_pcie_master(&adapter->hw);
5558
5559 wr32(E1000_WUC, E1000_WUC_PME_EN);
5560 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5561 } else {
5562 wr32(E1000_WUC, 0);
5563 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5564 }
5565
3fe7c4c9
RW		 5566 *enable_wake = wufc || adapter->en_mng_pt;
5567 if (!*enable_wake)
2fb02a26 5568 igb_shutdown_serdes_link_82575(hw);
9d5c8243
AK		 5569
5570 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5571 * would have already happened in close and is redundant. */
5572 igb_release_hw_control(adapter);
5573
5574 pci_disable_device(pdev);
5575
9d5c8243
AK		 5576 return 0;
5577}
5578
5579#ifdef CONFIG_PM
3fe7c4c9
RW		 5580static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5581{
5582 int retval;
5583 bool wake;
5584
5585 retval = __igb_shutdown(pdev, &wake);
5586 if (retval)
5587 return retval;
5588
5589 if (wake) {
5590 pci_prepare_to_sleep(pdev);
5591 } else {
5592 pci_wake_from_d3(pdev, false);
5593 pci_set_power_state(pdev, PCI_D3hot);
5594 }
5595
5596 return 0;
5597}
5598
9d5c8243
AK		 5599static int igb_resume(struct pci_dev *pdev)
5600{
5601 struct net_device *netdev = pci_get_drvdata(pdev);
5602 struct igb_adapter *adapter = netdev_priv(netdev);
5603 struct e1000_hw *hw = &adapter->hw;
5604 u32 err;
5605
5606 pci_set_power_state(pdev, PCI_D0);
5607 pci_restore_state(pdev);
42bfd33a 5608
aed5dec3 5609 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5610 if (err) {
5611 dev_err(&pdev->dev,
5612 "igb: Cannot enable PCI device from suspend\n");
5613 return err;
5614 }
5615 pci_set_master(pdev);
5616
5617 pci_enable_wake(pdev, PCI_D3hot, 0);
5618 pci_enable_wake(pdev, PCI_D3cold, 0);
5619
047e0030 5620 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 5621 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5622 return -ENOMEM;
9d5c8243
AK		 5623 }
5624
5625 /* e1000_power_up_phy(adapter); */
5626
5627 igb_reset(adapter);
a8564f03
AD		 5628
5629 /* let the f/w know that the h/w is now under the control of the
5630 * driver. */
5631 igb_get_hw_control(adapter);
5632
9d5c8243
AK		 5633 wr32(E1000_WUS, ~0);
5634
a88f10ec
AD		 5635 if (netif_running(netdev)) {
5636 err = igb_open(netdev);
5637 if (err)
5638 return err;
5639 }
9d5c8243
AK		 5640
5641 netif_device_attach(netdev);
5642
9d5c8243
AK		 5643 return 0;
5644}
5645#endif
5646
5647static void igb_shutdown(struct pci_dev *pdev)
5648{
3fe7c4c9
RW		 5649 bool wake;
5650
5651 __igb_shutdown(pdev, &wake);
5652
5653 if (system_state == SYSTEM_POWER_OFF) {
5654 pci_wake_from_d3(pdev, wake);
5655 pci_set_power_state(pdev, PCI_D3hot);
5656 }
9d5c8243
AK		 5657}
5658
5659#ifdef CONFIG_NET_POLL_CONTROLLER
5660/*
5661 * Polling 'interrupt' - used by things like netconsole to send skbs
5662 * without having to re-enable interrupts. It's not called while
5663 * the interrupt routine is executing.
5664 */
5665static void igb_netpoll(struct net_device *netdev)
5666{
5667 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5668 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5669 int i;
9d5c8243 5670
eebbbdba 5671 if (!adapter->msix_entries) {
047e0030 5672 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 5673 igb_irq_disable(adapter);
047e0030 5674 napi_schedule(&q_vector->napi);
eebbbdba
AD		 5675 return;
5676 }
9d5c8243 5677
047e0030
AD		 5678 for (i = 0; i < adapter->num_q_vectors; i++) {
5679 struct igb_q_vector *q_vector = adapter->q_vector[i];
5680 wr32(E1000_EIMC, q_vector->eims_value);
5681 napi_schedule(&q_vector->napi);
eebbbdba 5682 }
9d5c8243
AK		 5683}
5684#endif /* CONFIG_NET_POLL_CONTROLLER */
5685
5686/**
5687 * igb_io_error_detected - called when PCI error is detected
5688 * @pdev: Pointer to PCI device
5689 * @state: The current pci connection state
5690 *
5691 * This function is called after a PCI bus error affecting
5692 * this device has been detected.
5693 */
5694static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5695 pci_channel_state_t state)
5696{
5697 struct net_device *netdev = pci_get_drvdata(pdev);
5698 struct igb_adapter *adapter = netdev_priv(netdev);
5699
5700 netif_device_detach(netdev);
5701
59ed6eec
AD		 5702 if (state == pci_channel_io_perm_failure)
5703 return PCI_ERS_RESULT_DISCONNECT;
5704
9d5c8243
AK		 5705 if (netif_running(netdev))
5706 igb_down(adapter);
5707 pci_disable_device(pdev);
5708
5709 /* Request a slot slot reset. */
5710 return PCI_ERS_RESULT_NEED_RESET;
5711}
5712
5713/**
5714 * igb_io_slot_reset - called after the pci bus has been reset.
5715 * @pdev: Pointer to PCI device
5716 *
5717 * Restart the card from scratch, as if from a cold-boot. Implementation
5718 * resembles the first-half of the igb_resume routine.
5719 */
5720static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5721{
5722 struct net_device *netdev = pci_get_drvdata(pdev);
5723 struct igb_adapter *adapter = netdev_priv(netdev);
5724 struct e1000_hw *hw = &adapter->hw;
40a914fa 5725 pci_ers_result_t result;
42bfd33a 5726 int err;
9d5c8243 5727
aed5dec3 5728 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5729 dev_err(&pdev->dev,
5730 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5731 result = PCI_ERS_RESULT_DISCONNECT;
5732 } else {
5733 pci_set_master(pdev);
5734 pci_restore_state(pdev);
9d5c8243 5735
40a914fa
AD		 5736 pci_enable_wake(pdev, PCI_D3hot, 0);
5737 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5738
40a914fa
AD		 5739 igb_reset(adapter);
5740 wr32(E1000_WUS, ~0);
5741 result = PCI_ERS_RESULT_RECOVERED;
5742 }
9d5c8243 5743
ea943d41
JK		 5744 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5745 if (err) {
5746 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5747 "failed 0x%0x\n", err);
5748 /* non-fatal, continue */
5749 }
40a914fa
AD		 5750
5751 return result;
9d5c8243
AK		 5752}
5753
5754/**
5755 * igb_io_resume - called when traffic can start flowing again.
5756 * @pdev: Pointer to PCI device
5757 *
5758 * This callback is called when the error recovery driver tells us that
5759 * its OK to resume normal operation. Implementation resembles the
5760 * second-half of the igb_resume routine.
5761 */
5762static void igb_io_resume(struct pci_dev *pdev)
5763{
5764 struct net_device *netdev = pci_get_drvdata(pdev);
5765 struct igb_adapter *adapter = netdev_priv(netdev);
5766
9d5c8243
AK		 5767 if (netif_running(netdev)) {
5768 if (igb_up(adapter)) {
5769 dev_err(&pdev->dev, "igb_up failed after reset\n");
5770 return;
5771 }
5772 }
5773
5774 netif_device_attach(netdev);
5775
5776 /* let the f/w know that the h/w is now under the control of the
5777 * driver. */
5778 igb_get_hw_control(adapter);
9d5c8243
AK		 5779}
5780
26ad9178
AD		 5781static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
5782 u8 qsel)
5783{
5784 u32 rar_low, rar_high;
5785 struct e1000_hw *hw = &adapter->hw;
5786
5787 /* HW expects these in little endian so we reverse the byte order
5788 * from network order (big endian) to little endian
5789 */
5790 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
5791 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
5792 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
5793
5794 /* Indicate to hardware the Address is Valid. */
5795 rar_high |= E1000_RAH_AV;
5796
5797 if (hw->mac.type == e1000_82575)
5798 rar_high |= E1000_RAH_POOL_1 * qsel;
5799 else
5800 rar_high |= E1000_RAH_POOL_1 << qsel;
5801
5802 wr32(E1000_RAL(index), rar_low);
5803 wrfl();
5804 wr32(E1000_RAH(index), rar_high);
5805 wrfl();
5806}
5807
4ae196df
AD		 5808static int igb_set_vf_mac(struct igb_adapter *adapter,
5809 int vf, unsigned char *mac_addr)
5810{
5811 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 5812 /* VF MAC addresses start at end of receive addresses and moves
5813 * torwards the first, as a result a collision should not be possible */
5814 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 5815
37680117 5816 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 5817
26ad9178 5818 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 5819
5820 return 0;
5821}
5822
5823static void igb_vmm_control(struct igb_adapter *adapter)
5824{
5825 struct e1000_hw *hw = &adapter->hw;
10d8e907 5826 u32 reg;
4ae196df 5827
d4960307
AD		 5828 /* replication is not supported for 82575 */
5829 if (hw->mac.type == e1000_82575)
4ae196df
AD		 5830 return;
5831
10d8e907
AD		 5832 /* enable replication vlan tag stripping */
5833 reg = rd32(E1000_RPLOLR);
5834 reg |= E1000_RPLOLR_STRVLAN;
5835 wr32(E1000_RPLOLR, reg);
5836
5837 /* notify HW that the MAC is adding vlan tags */
5838 reg = rd32(E1000_DTXCTL);
5839 reg |= E1000_DTXCTL_VLAN_ADDED;
5840 wr32(E1000_DTXCTL, reg);
5841
d4960307
AD		 5842 if (adapter->vfs_allocated_count) {
5843 igb_vmdq_set_loopback_pf(hw, true);
5844 igb_vmdq_set_replication_pf(hw, true);
5845 } else {
5846 igb_vmdq_set_loopback_pf(hw, false);
5847 igb_vmdq_set_replication_pf(hw, false);
5848 }
4ae196df
AD		 5849}
5850
9d5c8243 5851/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)