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ixgbevf: Fix Driver String
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243 34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
9d5c8243
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
c6cb090b 38#include <linux/net_tstamp.h>
9d5c8243
AK		 39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
46#include <linux/if_ether.h>
40a914fa 47#include <linux/aer.h>
421e02f0 48#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 49#include <linux/dca.h>
50#endif
9d5c8243
AK		 51#include "igb.h"
52
c2b6a059 53#define DRV_VERSION "2.4.13-k2"
9d5c8243
AK		 54char igb_driver_name[] = "igb";
55char igb_driver_version[] = DRV_VERSION;
56static const char igb_driver_string[] =
57 "Intel(R) Gigabit Ethernet Network Driver";
4c4b42cb 58static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
9d5c8243 59
9d5c8243
AK		 60static const struct e1000_info *igb_info_tbl[] = {
61 [board_82575] = &e1000_82575_info,
62};
63
a3aa1884 64static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
90 /* required last entry */
91 {0, }
92};
93
94MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
95
96void igb_reset(struct igb_adapter *);
97static int igb_setup_all_tx_resources(struct igb_adapter *);
98static int igb_setup_all_rx_resources(struct igb_adapter *);
99static void igb_free_all_tx_resources(struct igb_adapter *);
100static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 101static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 102static int igb_probe(struct pci_dev *, const struct pci_device_id *);
103static void __devexit igb_remove(struct pci_dev *pdev);
104static int igb_sw_init(struct igb_adapter *);
105static int igb_open(struct net_device *);
106static int igb_close(struct net_device *);
107static void igb_configure_tx(struct igb_adapter *);
108static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 109static void igb_clean_all_tx_rings(struct igb_adapter *);
110static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 111static void igb_clean_tx_ring(struct igb_ring *);
112static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 113static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 114static void igb_update_phy_info(unsigned long);
115static void igb_watchdog(unsigned long);
116static void igb_watchdog_task(struct work_struct *);
b1a436c3 117static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 118static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
119 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 120static int igb_change_mtu(struct net_device *, int);
121static int igb_set_mac(struct net_device *, void *);
68d480c4 122static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 123static irqreturn_t igb_intr(int irq, void *);
124static irqreturn_t igb_intr_msi(int irq, void *);
125static irqreturn_t igb_msix_other(int irq, void *);
047e0030 126static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 127#ifdef CONFIG_IGB_DCA
047e0030 128static void igb_update_dca(struct igb_q_vector *);
fe4506b6 129static void igb_setup_dca(struct igb_adapter *);
421e02f0 130#endif /* CONFIG_IGB_DCA */
047e0030 131static bool igb_clean_tx_irq(struct igb_q_vector *);
661086df 132static int igb_poll(struct napi_struct *, int);
047e0030 133static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int);
9d5c8243
AK		 134static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
135static void igb_tx_timeout(struct net_device *);
136static void igb_reset_task(struct work_struct *);
137static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
138static void igb_vlan_rx_add_vid(struct net_device *, u16);
139static void igb_vlan_rx_kill_vid(struct net_device *, u16);
140static void igb_restore_vlan(struct igb_adapter *);
26ad9178 141static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 142static void igb_ping_all_vfs(struct igb_adapter *);
143static void igb_msg_task(struct igb_adapter *);
4ae196df 144static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 145static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 146static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 147static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
148static int igb_ndo_set_vf_vlan(struct net_device *netdev,
149 int vf, u16 vlan, u8 qos);
150static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
151static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
152 struct ifla_vf_info *ivi);
17dc566c 153static void igb_check_vf_rate_limit(struct igb_adapter *);
9d5c8243 154
9d5c8243 155#ifdef CONFIG_PM
3fe7c4c9 156static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 157static int igb_resume(struct pci_dev *);
158#endif
159static void igb_shutdown(struct pci_dev *);
421e02f0 160#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 161static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
162static struct notifier_block dca_notifier = {
163 .notifier_call = igb_notify_dca,
164 .next = NULL,
165 .priority = 0
166};
167#endif
9d5c8243
AK		 168#ifdef CONFIG_NET_POLL_CONTROLLER
169/* for netdump / net console */
170static void igb_netpoll(struct net_device *);
171#endif
37680117 172#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 173static unsigned int max_vfs = 0;
174module_param(max_vfs, uint, 0);
175MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
176 "per physical function");
177#endif /* CONFIG_PCI_IOV */
178
9d5c8243
AK		 179static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
180 pci_channel_state_t);
181static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
182static void igb_io_resume(struct pci_dev *);
183
184static struct pci_error_handlers igb_err_handler = {
185 .error_detected = igb_io_error_detected,
186 .slot_reset = igb_io_slot_reset,
187 .resume = igb_io_resume,
188};
189
190
191static struct pci_driver igb_driver = {
192 .name = igb_driver_name,
193 .id_table = igb_pci_tbl,
194 .probe = igb_probe,
195 .remove = __devexit_p(igb_remove),
196#ifdef CONFIG_PM
197 /* Power Managment Hooks */
198 .suspend = igb_suspend,
199 .resume = igb_resume,
200#endif
201 .shutdown = igb_shutdown,
202 .err_handler = &igb_err_handler
203};
204
205MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
206MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
207MODULE_LICENSE("GPL");
208MODULE_VERSION(DRV_VERSION);
209
c97ec42a
TI		 210struct igb_reg_info {
211 u32 ofs;
212 char *name;
213};
214
215static const struct igb_reg_info igb_reg_info_tbl[] = {
216
217 /* General Registers */
218 {E1000_CTRL, "CTRL"},
219 {E1000_STATUS, "STATUS"},
220 {E1000_CTRL_EXT, "CTRL_EXT"},
221
222 /* Interrupt Registers */
223 {E1000_ICR, "ICR"},
224
225 /* RX Registers */
226 {E1000_RCTL, "RCTL"},
227 {E1000_RDLEN(0), "RDLEN"},
228 {E1000_RDH(0), "RDH"},
229 {E1000_RDT(0), "RDT"},
230 {E1000_RXDCTL(0), "RXDCTL"},
231 {E1000_RDBAL(0), "RDBAL"},
232 {E1000_RDBAH(0), "RDBAH"},
233
234 /* TX Registers */
235 {E1000_TCTL, "TCTL"},
236 {E1000_TDBAL(0), "TDBAL"},
237 {E1000_TDBAH(0), "TDBAH"},
238 {E1000_TDLEN(0), "TDLEN"},
239 {E1000_TDH(0), "TDH"},
240 {E1000_TDT(0), "TDT"},
241 {E1000_TXDCTL(0), "TXDCTL"},
242 {E1000_TDFH, "TDFH"},
243 {E1000_TDFT, "TDFT"},
244 {E1000_TDFHS, "TDFHS"},
245 {E1000_TDFPC, "TDFPC"},
246
247 /* List Terminator */
248 {}
249};
250
251/*
252 * igb_regdump - register printout routine
253 */
254static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
255{
256 int n = 0;
257 char rname[16];
258 u32 regs[8];
259
260 switch (reginfo->ofs) {
261 case E1000_RDLEN(0):
262 for (n = 0; n < 4; n++)
263 regs[n] = rd32(E1000_RDLEN(n));
264 break;
265 case E1000_RDH(0):
266 for (n = 0; n < 4; n++)
267 regs[n] = rd32(E1000_RDH(n));
268 break;
269 case E1000_RDT(0):
270 for (n = 0; n < 4; n++)
271 regs[n] = rd32(E1000_RDT(n));
272 break;
273 case E1000_RXDCTL(0):
274 for (n = 0; n < 4; n++)
275 regs[n] = rd32(E1000_RXDCTL(n));
276 break;
277 case E1000_RDBAL(0):
278 for (n = 0; n < 4; n++)
279 regs[n] = rd32(E1000_RDBAL(n));
280 break;
281 case E1000_RDBAH(0):
282 for (n = 0; n < 4; n++)
283 regs[n] = rd32(E1000_RDBAH(n));
284 break;
285 case E1000_TDBAL(0):
286 for (n = 0; n < 4; n++)
287 regs[n] = rd32(E1000_RDBAL(n));
288 break;
289 case E1000_TDBAH(0):
290 for (n = 0; n < 4; n++)
291 regs[n] = rd32(E1000_TDBAH(n));
292 break;
293 case E1000_TDLEN(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_TDLEN(n));
296 break;
297 case E1000_TDH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_TDH(n));
300 break;
301 case E1000_TDT(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_TDT(n));
304 break;
305 case E1000_TXDCTL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_TXDCTL(n));
308 break;
309 default:
310 printk(KERN_INFO "%-15s %08x\n",
311 reginfo->name, rd32(reginfo->ofs));
312 return;
313 }
314
315 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
316 printk(KERN_INFO "%-15s ", rname);
317 for (n = 0; n < 4; n++)
318 printk(KERN_CONT "%08x ", regs[n]);
319 printk(KERN_CONT "\n");
320}
321
322/*
323 * igb_dump - Print registers, tx-rings and rx-rings
324 */
325static void igb_dump(struct igb_adapter *adapter)
326{
327 struct net_device *netdev = adapter->netdev;
328 struct e1000_hw *hw = &adapter->hw;
329 struct igb_reg_info *reginfo;
330 int n = 0;
331 struct igb_ring *tx_ring;
332 union e1000_adv_tx_desc *tx_desc;
333 struct my_u0 { u64 a; u64 b; } *u0;
334 struct igb_buffer *buffer_info;
335 struct igb_ring *rx_ring;
336 union e1000_adv_rx_desc *rx_desc;
337 u32 staterr;
338 int i = 0;
339
340 if (!netif_msg_hw(adapter))
341 return;
342
343 /* Print netdevice Info */
344 if (netdev) {
345 dev_info(&adapter->pdev->dev, "Net device Info\n");
346 printk(KERN_INFO "Device Name state "
347 "trans_start last_rx\n");
348 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
349 netdev->name,
350 netdev->state,
351 netdev->trans_start,
352 netdev->last_rx);
353 }
354
355 /* Print Registers */
356 dev_info(&adapter->pdev->dev, "Register Dump\n");
357 printk(KERN_INFO " Register Name Value\n");
358 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
359 reginfo->name; reginfo++) {
360 igb_regdump(hw, reginfo);
361 }
362
363 /* Print TX Ring Summary */
364 if (!netdev || !netif_running(netdev))
365 goto exit;
366
367 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
368 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]"
369 " leng ntw timestamp\n");
370 for (n = 0; n < adapter->num_tx_queues; n++) {
371 tx_ring = adapter->tx_ring[n];
372 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
373 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
374 n, tx_ring->next_to_use, tx_ring->next_to_clean,
375 (u64)buffer_info->dma,
376 buffer_info->length,
377 buffer_info->next_to_watch,
378 (u64)buffer_info->time_stamp);
379 }
380
381 /* Print TX Rings */
382 if (!netif_msg_tx_done(adapter))
383 goto rx_ring_summary;
384
385 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
386
387 /* Transmit Descriptor Formats
388 *
389 * Advanced Transmit Descriptor
390 * +--------------------------------------------------------------+
391 * 0 | Buffer Address [63:0] |
392 * +--------------------------------------------------------------+
393 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
394 * +--------------------------------------------------------------+
395 * 63 46 45 40 39 38 36 35 32 31 24 15 0
396 */
397
398 for (n = 0; n < adapter->num_tx_queues; n++) {
399 tx_ring = adapter->tx_ring[n];
400 printk(KERN_INFO "------------------------------------\n");
401 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
402 printk(KERN_INFO "------------------------------------\n");
403 printk(KERN_INFO "T [desc] [address 63:0 ] "
404 "[PlPOCIStDDM Ln] [bi->dma ] "
405 "leng ntw timestamp bi->skb\n");
406
407 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
408 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
409 buffer_info = &tx_ring->buffer_info[i];
410 u0 = (struct my_u0 *)tx_desc;
411 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
412 " %04X %3X %016llX %p", i,
413 le64_to_cpu(u0->a),
414 le64_to_cpu(u0->b),
415 (u64)buffer_info->dma,
416 buffer_info->length,
417 buffer_info->next_to_watch,
418 (u64)buffer_info->time_stamp,
419 buffer_info->skb);
420 if (i == tx_ring->next_to_use &&
421 i == tx_ring->next_to_clean)
422 printk(KERN_CONT " NTC/U\n");
423 else if (i == tx_ring->next_to_use)
424 printk(KERN_CONT " NTU\n");
425 else if (i == tx_ring->next_to_clean)
426 printk(KERN_CONT " NTC\n");
427 else
428 printk(KERN_CONT "\n");
429
430 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
431 print_hex_dump(KERN_INFO, "",
432 DUMP_PREFIX_ADDRESS,
433 16, 1, phys_to_virt(buffer_info->dma),
434 buffer_info->length, true);
435 }
436 }
437
438 /* Print RX Rings Summary */
439rx_ring_summary:
440 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
441 printk(KERN_INFO "Queue [NTU] [NTC]\n");
442 for (n = 0; n < adapter->num_rx_queues; n++) {
443 rx_ring = adapter->rx_ring[n];
444 printk(KERN_INFO " %5d %5X %5X\n", n,
445 rx_ring->next_to_use, rx_ring->next_to_clean);
446 }
447
448 /* Print RX Rings */
449 if (!netif_msg_rx_status(adapter))
450 goto exit;
451
452 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
453
454 /* Advanced Receive Descriptor (Read) Format
455 * 63 1 0
456 * +-----------------------------------------------------+
457 * 0 | Packet Buffer Address [63:1] |A0/NSE|
458 * +----------------------------------------------+------+
459 * 8 | Header Buffer Address [63:1] | DD |
460 * +-----------------------------------------------------+
461 *
462 *
463 * Advanced Receive Descriptor (Write-Back) Format
464 *
465 * 63 48 47 32 31 30 21 20 17 16 4 3 0
466 * +------------------------------------------------------+
467 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
468 * | Checksum Ident | | | | Type | Type |
469 * +------------------------------------------------------+
470 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
471 * +------------------------------------------------------+
472 * 63 48 47 32 31 20 19 0
473 */
474
475 for (n = 0; n < adapter->num_rx_queues; n++) {
476 rx_ring = adapter->rx_ring[n];
477 printk(KERN_INFO "------------------------------------\n");
478 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
479 printk(KERN_INFO "------------------------------------\n");
480 printk(KERN_INFO "R [desc] [ PktBuf A0] "
481 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
482 "<-- Adv Rx Read format\n");
483 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
484 "[vl er S cks ln] ---------------- [bi->skb] "
485 "<-- Adv Rx Write-Back format\n");
486
487 for (i = 0; i < rx_ring->count; i++) {
488 buffer_info = &rx_ring->buffer_info[i];
489 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
490 u0 = (struct my_u0 *)rx_desc;
491 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
492 if (staterr & E1000_RXD_STAT_DD) {
493 /* Descriptor Done */
494 printk(KERN_INFO "RWB[0x%03X] %016llX "
495 "%016llX ---------------- %p", i,
496 le64_to_cpu(u0->a),
497 le64_to_cpu(u0->b),
498 buffer_info->skb);
499 } else {
500 printk(KERN_INFO "R [0x%03X] %016llX "
501 "%016llX %016llX %p", i,
502 le64_to_cpu(u0->a),
503 le64_to_cpu(u0->b),
504 (u64)buffer_info->dma,
505 buffer_info->skb);
506
507 if (netif_msg_pktdata(adapter)) {
508 print_hex_dump(KERN_INFO, "",
509 DUMP_PREFIX_ADDRESS,
510 16, 1,
511 phys_to_virt(buffer_info->dma),
512 rx_ring->rx_buffer_len, true);
513 if (rx_ring->rx_buffer_len
514 < IGB_RXBUFFER_1024)
515 print_hex_dump(KERN_INFO, "",
516 DUMP_PREFIX_ADDRESS,
517 16, 1,
518 phys_to_virt(
519 buffer_info->page_dma +
520 buffer_info->page_offset),
521 PAGE_SIZE/2, true);
522 }
523 }
524
525 if (i == rx_ring->next_to_use)
526 printk(KERN_CONT " NTU\n");
527 else if (i == rx_ring->next_to_clean)
528 printk(KERN_CONT " NTC\n");
529 else
530 printk(KERN_CONT "\n");
531
532 }
533 }
534
535exit:
536 return;
537}
538
539
38c845c7
PO		 540/**
541 * igb_read_clock - read raw cycle counter (to be used by time counter)
542 */
543static cycle_t igb_read_clock(const struct cyclecounter *tc)
544{
545 struct igb_adapter *adapter =
546 container_of(tc, struct igb_adapter, cycles);
547 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 548 u64 stamp = 0;
549 int shift = 0;
38c845c7 550
55cac248
AD		 551 /*
552 * The timestamp latches on lowest register read. For the 82580
553 * the lowest register is SYSTIMR instead of SYSTIML. However we never
554 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
555 */
556 if (hw->mac.type == e1000_82580) {
557 stamp = rd32(E1000_SYSTIMR) >> 8;
558 shift = IGB_82580_TSYNC_SHIFT;
559 }
560
c5b9bd5e
AD		 561 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
562 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 563 return stamp;
564}
565
9d5c8243 566/**
c041076a 567 * igb_get_hw_dev - return device
9d5c8243
AK		 568 * used by hardware layer to print debugging information
569 **/
c041076a 570struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 571{
572 struct igb_adapter *adapter = hw->back;
c041076a 573 return adapter->netdev;
9d5c8243 574}
38c845c7 575
9d5c8243
AK		 576/**
577 * igb_init_module - Driver Registration Routine
578 *
579 * igb_init_module is the first routine called when the driver is
580 * loaded. All it does is register with the PCI subsystem.
581 **/
582static int __init igb_init_module(void)
583{
584 int ret;
585 printk(KERN_INFO "%s - version %s\n",
586 igb_driver_string, igb_driver_version);
587
588 printk(KERN_INFO "%s\n", igb_copyright);
589
421e02f0 590#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 591 dca_register_notify(&dca_notifier);
592#endif
bbd98fe4 593 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 594 return ret;
595}
596
597module_init(igb_init_module);
598
599/**
600 * igb_exit_module - Driver Exit Cleanup Routine
601 *
602 * igb_exit_module is called just before the driver is removed
603 * from memory.
604 **/
605static void __exit igb_exit_module(void)
606{
421e02f0 607#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 608 dca_unregister_notify(&dca_notifier);
609#endif
9d5c8243
AK		 610 pci_unregister_driver(&igb_driver);
611}
612
613module_exit(igb_exit_module);
614
26bc19ec
AD		 615#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
616/**
617 * igb_cache_ring_register - Descriptor ring to register mapping
618 * @adapter: board private structure to initialize
619 *
620 * Once we know the feature-set enabled for the device, we'll cache
621 * the register offset the descriptor ring is assigned to.
622 **/
623static void igb_cache_ring_register(struct igb_adapter *adapter)
624{
ee1b9f06 625 int i = 0, j = 0;
047e0030 626 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 627
628 switch (adapter->hw.mac.type) {
629 case e1000_82576:
630 /* The queues are allocated for virtualization such that VF 0
631 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
632 * In order to avoid collision we start at the first free queue
633 * and continue consuming queues in the same sequence
634 */
ee1b9f06 635 if (adapter->vfs_allocated_count) {
a99955fc 636 for (; i < adapter->rss_queues; i++)
3025a446
AD		 637 adapter->rx_ring[i]->reg_idx = rbase_offset +
638 Q_IDX_82576(i);
ee1b9f06 639 }
26bc19ec 640 case e1000_82575:
55cac248 641 case e1000_82580:
d2ba2ed8 642 case e1000_i350:
26bc19ec 643 default:
ee1b9f06 644 for (; i < adapter->num_rx_queues; i++)
3025a446 645 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 646 for (; j < adapter->num_tx_queues; j++)
3025a446 647 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 648 break;
649 }
650}
651
047e0030
AD		 652static void igb_free_queues(struct igb_adapter *adapter)
653{
3025a446 654 int i;
047e0030 655
3025a446
AD		 656 for (i = 0; i < adapter->num_tx_queues; i++) {
657 kfree(adapter->tx_ring[i]);
658 adapter->tx_ring[i] = NULL;
659 }
660 for (i = 0; i < adapter->num_rx_queues; i++) {
661 kfree(adapter->rx_ring[i]);
662 adapter->rx_ring[i] = NULL;
663 }
047e0030
AD		 664 adapter->num_rx_queues = 0;
665 adapter->num_tx_queues = 0;
666}
667
9d5c8243
AK		 668/**
669 * igb_alloc_queues - Allocate memory for all rings
670 * @adapter: board private structure to initialize
671 *
672 * We allocate one ring per queue at run-time since we don't know the
673 * number of queues at compile-time.
674 **/
675static int igb_alloc_queues(struct igb_adapter *adapter)
676{
3025a446 677 struct igb_ring *ring;
9d5c8243
AK		 678 int i;
679
661086df 680 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 681 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
682 if (!ring)
683 goto err;
68fd9910 684 ring->count = adapter->tx_ring_count;
661086df 685 ring->queue_index = i;
59d71989 686 ring->dev = &adapter->pdev->dev;
e694e964 687 ring->netdev = adapter->netdev;
85ad76b2
AD		 688 /* For 82575, context index must be unique per ring. */
689 if (adapter->hw.mac.type == e1000_82575)
690 ring->flags = IGB_RING_FLAG_TX_CTX_IDX;
3025a446 691 adapter->tx_ring[i] = ring;
661086df 692 }
85ad76b2 693
9d5c8243 694 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 695 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
696 if (!ring)
697 goto err;
68fd9910 698 ring->count = adapter->rx_ring_count;
844290e5 699 ring->queue_index = i;
59d71989 700 ring->dev = &adapter->pdev->dev;
e694e964 701 ring->netdev = adapter->netdev;
4c844851 702 ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
85ad76b2
AD		 703 ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */
704 /* set flag indicating ring supports SCTP checksum offload */
705 if (adapter->hw.mac.type >= e1000_82576)
706 ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM;
3025a446 707 adapter->rx_ring[i] = ring;
9d5c8243 708 }
26bc19ec
AD		 709
710 igb_cache_ring_register(adapter);
9d5c8243 711
047e0030 712 return 0;
a88f10ec 713
047e0030
AD		 714err:
715 igb_free_queues(adapter);
d1a8c9e1 716
047e0030 717 return -ENOMEM;
a88f10ec
AD		 718}
719
9d5c8243 720#define IGB_N0_QUEUE -1
047e0030 721static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243
AK		 722{
723 u32 msixbm = 0;
047e0030 724 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 725 struct e1000_hw *hw = &adapter->hw;
2d064c06 726 u32 ivar, index;
047e0030
AD		 727 int rx_queue = IGB_N0_QUEUE;
728 int tx_queue = IGB_N0_QUEUE;
729
730 if (q_vector->rx_ring)
731 rx_queue = q_vector->rx_ring->reg_idx;
732 if (q_vector->tx_ring)
733 tx_queue = q_vector->tx_ring->reg_idx;
2d064c06
AD		 734
735 switch (hw->mac.type) {
736 case e1000_82575:
9d5c8243
AK		 737 /* The 82575 assigns vectors using a bitmask, which matches the
738 bitmask for the EICR/EIMS/EIMC registers. To assign one
739 or more queues to a vector, we write the appropriate bits
740 into the MSIXBM register for that vector. */
047e0030 741 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 742 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 743 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 744 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 745 if (!adapter->msix_entries && msix_vector == 0)
746 msixbm |= E1000_EIMS_OTHER;
9d5c8243 747 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 748 q_vector->eims_value = msixbm;
2d064c06
AD		 749 break;
750 case e1000_82576:
26bc19ec 751 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 752 Each queue has a single entry in the table to which we write
753 a vector number along with a "valid" bit. Sadly, the layout
754 of the table is somewhat counterintuitive. */
755 if (rx_queue > IGB_N0_QUEUE) {
047e0030 756 index = (rx_queue & 0x7);
2d064c06 757 ivar = array_rd32(E1000_IVAR0, index);
047e0030 758 if (rx_queue < 8) {
26bc19ec
AD		 759 /* vector goes into low byte of register */
760 ivar = ivar & 0xFFFFFF00;
761 ivar |= msix_vector | E1000_IVAR_VALID;
047e0030
AD		 762 } else {
763 /* vector goes into third byte of register */
764 ivar = ivar & 0xFF00FFFF;
765 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
2d064c06 766 }
2d064c06
AD		 767 array_wr32(E1000_IVAR0, index, ivar);
768 }
769 if (tx_queue > IGB_N0_QUEUE) {
047e0030 770 index = (tx_queue & 0x7);
2d064c06 771 ivar = array_rd32(E1000_IVAR0, index);
047e0030 772 if (tx_queue < 8) {
26bc19ec
AD		 773 /* vector goes into second byte of register */
774 ivar = ivar & 0xFFFF00FF;
775 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
047e0030
AD		 776 } else {
777 /* vector goes into high byte of register */
778 ivar = ivar & 0x00FFFFFF;
779 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
2d064c06 780 }
2d064c06
AD		 781 array_wr32(E1000_IVAR0, index, ivar);
782 }
047e0030 783 q_vector->eims_value = 1 << msix_vector;
2d064c06 784 break;
55cac248 785 case e1000_82580:
d2ba2ed8 786 case e1000_i350:
55cac248
AD		 787 /* 82580 uses the same table-based approach as 82576 but has fewer
788 entries as a result we carry over for queues greater than 4. */
789 if (rx_queue > IGB_N0_QUEUE) {
790 index = (rx_queue >> 1);
791 ivar = array_rd32(E1000_IVAR0, index);
792 if (rx_queue & 0x1) {
793 /* vector goes into third byte of register */
794 ivar = ivar & 0xFF00FFFF;
795 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
796 } else {
797 /* vector goes into low byte of register */
798 ivar = ivar & 0xFFFFFF00;
799 ivar |= msix_vector | E1000_IVAR_VALID;
800 }
801 array_wr32(E1000_IVAR0, index, ivar);
802 }
803 if (tx_queue > IGB_N0_QUEUE) {
804 index = (tx_queue >> 1);
805 ivar = array_rd32(E1000_IVAR0, index);
806 if (tx_queue & 0x1) {
807 /* vector goes into high byte of register */
808 ivar = ivar & 0x00FFFFFF;
809 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
810 } else {
811 /* vector goes into second byte of register */
812 ivar = ivar & 0xFFFF00FF;
813 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
814 }
815 array_wr32(E1000_IVAR0, index, ivar);
816 }
817 q_vector->eims_value = 1 << msix_vector;
818 break;
2d064c06
AD		 819 default:
820 BUG();
821 break;
822 }
26b39276
AD		 823
824 /* add q_vector eims value to global eims_enable_mask */
825 adapter->eims_enable_mask |= q_vector->eims_value;
826
827 /* configure q_vector to set itr on first interrupt */
828 q_vector->set_itr = 1;
9d5c8243
AK		 829}
830
831/**
832 * igb_configure_msix - Configure MSI-X hardware
833 *
834 * igb_configure_msix sets up the hardware to properly
835 * generate MSI-X interrupts.
836 **/
837static void igb_configure_msix(struct igb_adapter *adapter)
838{
839 u32 tmp;
840 int i, vector = 0;
841 struct e1000_hw *hw = &adapter->hw;
842
843 adapter->eims_enable_mask = 0;
9d5c8243
AK		 844
845 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 846 switch (hw->mac.type) {
847 case e1000_82575:
9d5c8243
AK		 848 tmp = rd32(E1000_CTRL_EXT);
849 /* enable MSI-X PBA support*/
850 tmp |= E1000_CTRL_EXT_PBA_CLR;
851
852 /* Auto-Mask interrupts upon ICR read. */
853 tmp |= E1000_CTRL_EXT_EIAME;
854 tmp |= E1000_CTRL_EXT_IRCA;
855
856 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 857
858 /* enable msix_other interrupt */
859 array_wr32(E1000_MSIXBM(0), vector++,
860 E1000_EIMS_OTHER);
844290e5 861 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 862
2d064c06
AD		 863 break;
864
865 case e1000_82576:
55cac248 866 case e1000_82580:
d2ba2ed8 867 case e1000_i350:
047e0030
AD		 868 /* Turn on MSI-X capability first, or our settings
869 * won't stick. And it will take days to debug. */
870 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
871 E1000_GPIE_PBA | E1000_GPIE_EIAME |
872 E1000_GPIE_NSICR);
873
874 /* enable msix_other interrupt */
875 adapter->eims_other = 1 << vector;
2d064c06 876 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 877
047e0030 878 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 879 break;
880 default:
881 /* do nothing, since nothing else supports MSI-X */
882 break;
883 } /* switch (hw->mac.type) */
047e0030
AD		 884
885 adapter->eims_enable_mask |= adapter->eims_other;
886
26b39276
AD		 887 for (i = 0; i < adapter->num_q_vectors; i++)
888 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 889
9d5c8243
AK		 890 wrfl();
891}
892
893/**
894 * igb_request_msix - Initialize MSI-X interrupts
895 *
896 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
897 * kernel.
898 **/
899static int igb_request_msix(struct igb_adapter *adapter)
900{
901 struct net_device *netdev = adapter->netdev;
047e0030 902 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 903 int i, err = 0, vector = 0;
904
047e0030 905 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 906 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 907 if (err)
908 goto out;
909 vector++;
910
911 for (i = 0; i < adapter->num_q_vectors; i++) {
912 struct igb_q_vector *q_vector = adapter->q_vector[i];
913
914 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
915
916 if (q_vector->rx_ring && q_vector->tx_ring)
917 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
918 q_vector->rx_ring->queue_index);
919 else if (q_vector->tx_ring)
920 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
921 q_vector->tx_ring->queue_index);
922 else if (q_vector->rx_ring)
923 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
924 q_vector->rx_ring->queue_index);
9d5c8243 925 else
047e0030
AD		 926 sprintf(q_vector->name, "%s-unused", netdev->name);
927
9d5c8243 928 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 929 igb_msix_ring, 0, q_vector->name,
047e0030 930 q_vector);
9d5c8243
AK		 931 if (err)
932 goto out;
9d5c8243
AK		 933 vector++;
934 }
935
9d5c8243
AK		 936 igb_configure_msix(adapter);
937 return 0;
938out:
939 return err;
940}
941
942static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
943{
944 if (adapter->msix_entries) {
945 pci_disable_msix(adapter->pdev);
946 kfree(adapter->msix_entries);
947 adapter->msix_entries = NULL;
047e0030 948 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 949 pci_disable_msi(adapter->pdev);
047e0030 950 }
9d5c8243
AK		 951}
952
047e0030
AD		 953/**
954 * igb_free_q_vectors - Free memory allocated for interrupt vectors
955 * @adapter: board private structure to initialize
956 *
957 * This function frees the memory allocated to the q_vectors. In addition if
958 * NAPI is enabled it will delete any references to the NAPI struct prior
959 * to freeing the q_vector.
960 **/
961static void igb_free_q_vectors(struct igb_adapter *adapter)
962{
963 int v_idx;
964
965 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
966 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
967 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 968 if (!q_vector)
969 continue;
047e0030
AD		 970 netif_napi_del(&q_vector->napi);
971 kfree(q_vector);
972 }
973 adapter->num_q_vectors = 0;
974}
975
976/**
977 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
978 *
979 * This function resets the device so that it has 0 rx queues, tx queues, and
980 * MSI-X interrupts allocated.
981 */
982static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
983{
984 igb_free_queues(adapter);
985 igb_free_q_vectors(adapter);
986 igb_reset_interrupt_capability(adapter);
987}
9d5c8243
AK		 988
989/**
990 * igb_set_interrupt_capability - set MSI or MSI-X if supported
991 *
992 * Attempt to configure interrupts using the best available
993 * capabilities of the hardware and kernel.
994 **/
21adef3e 995static int igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 996{
997 int err;
998 int numvecs, i;
999
83b7180d 1000 /* Number of supported queues. */
a99955fc 1001 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1002 if (adapter->vfs_allocated_count)
1003 adapter->num_tx_queues = 1;
1004 else
1005 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1006
047e0030
AD		 1007 /* start with one vector for every rx queue */
1008 numvecs = adapter->num_rx_queues;
1009
3ad2f3fb 1010 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1011 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1012 numvecs += adapter->num_tx_queues;
047e0030
AD		 1013
1014 /* store the number of vectors reserved for queues */
1015 adapter->num_q_vectors = numvecs;
1016
1017 /* add 1 vector for link status interrupts */
1018 numvecs++;
9d5c8243
AK		 1019 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1020 GFP_KERNEL);
1021 if (!adapter->msix_entries)
1022 goto msi_only;
1023
1024 for (i = 0; i < numvecs; i++)
1025 adapter->msix_entries[i].entry = i;
1026
1027 err = pci_enable_msix(adapter->pdev,
1028 adapter->msix_entries,
1029 numvecs);
1030 if (err == 0)
34a20e89 1031 goto out;
9d5c8243
AK		 1032
1033 igb_reset_interrupt_capability(adapter);
1034
1035 /* If we can't do MSI-X, try MSI */
1036msi_only:
2a3abf6d
AD		 1037#ifdef CONFIG_PCI_IOV
1038 /* disable SR-IOV for non MSI-X configurations */
1039 if (adapter->vf_data) {
1040 struct e1000_hw *hw = &adapter->hw;
1041 /* disable iov and allow time for transactions to clear */
1042 pci_disable_sriov(adapter->pdev);
1043 msleep(500);
1044
1045 kfree(adapter->vf_data);
1046 adapter->vf_data = NULL;
1047 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1048 msleep(100);
1049 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1050 }
1051#endif
4fc82adf 1052 adapter->vfs_allocated_count = 0;
a99955fc 1053 adapter->rss_queues = 1;
4fc82adf 1054 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1055 adapter->num_rx_queues = 1;
661086df 1056 adapter->num_tx_queues = 1;
047e0030 1057 adapter->num_q_vectors = 1;
9d5c8243 1058 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1059 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1060out:
21adef3e
BH		 1061 /* Notify the stack of the (possibly) reduced queue counts. */
1062 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1063 return netif_set_real_num_rx_queues(adapter->netdev,
1064 adapter->num_rx_queues);
9d5c8243
AK		 1065}
1066
047e0030
AD		 1067/**
1068 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1069 * @adapter: board private structure to initialize
1070 *
1071 * We allocate one q_vector per queue interrupt. If allocation fails we
1072 * return -ENOMEM.
1073 **/
1074static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1075{
1076 struct igb_q_vector *q_vector;
1077 struct e1000_hw *hw = &adapter->hw;
1078 int v_idx;
1079
1080 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1081 q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL);
1082 if (!q_vector)
1083 goto err_out;
1084 q_vector->adapter = adapter;
047e0030
AD		 1085 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1086 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1087 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1088 adapter->q_vector[v_idx] = q_vector;
1089 }
1090 return 0;
1091
1092err_out:
fe0592b4 1093 igb_free_q_vectors(adapter);
047e0030
AD		 1094 return -ENOMEM;
1095}
1096
1097static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1098 int ring_idx, int v_idx)
1099{
3025a446 1100 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1101
3025a446 1102 q_vector->rx_ring = adapter->rx_ring[ring_idx];
047e0030 1103 q_vector->rx_ring->q_vector = q_vector;
4fc82adf
AD		 1104 q_vector->itr_val = adapter->rx_itr_setting;
1105 if (q_vector->itr_val && q_vector->itr_val <= 3)
1106 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1107}
1108
1109static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1110 int ring_idx, int v_idx)
1111{
3025a446 1112 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1113
3025a446 1114 q_vector->tx_ring = adapter->tx_ring[ring_idx];
047e0030 1115 q_vector->tx_ring->q_vector = q_vector;
4fc82adf
AD		 1116 q_vector->itr_val = adapter->tx_itr_setting;
1117 if (q_vector->itr_val && q_vector->itr_val <= 3)
1118 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1119}
1120
1121/**
1122 * igb_map_ring_to_vector - maps allocated queues to vectors
1123 *
1124 * This function maps the recently allocated queues to vectors.
1125 **/
1126static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1127{
1128 int i;
1129 int v_idx = 0;
1130
1131 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1132 (adapter->num_q_vectors < adapter->num_tx_queues))
1133 return -ENOMEM;
1134
1135 if (adapter->num_q_vectors >=
1136 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1137 for (i = 0; i < adapter->num_rx_queues; i++)
1138 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1139 for (i = 0; i < adapter->num_tx_queues; i++)
1140 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1141 } else {
1142 for (i = 0; i < adapter->num_rx_queues; i++) {
1143 if (i < adapter->num_tx_queues)
1144 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1145 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1146 }
1147 for (; i < adapter->num_tx_queues; i++)
1148 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1149 }
1150 return 0;
1151}
1152
1153/**
1154 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1155 *
1156 * This function initializes the interrupts and allocates all of the queues.
1157 **/
1158static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1159{
1160 struct pci_dev *pdev = adapter->pdev;
1161 int err;
1162
21adef3e
BH		 1163 err = igb_set_interrupt_capability(adapter);
1164 if (err)
1165 return err;
047e0030
AD		 1166
1167 err = igb_alloc_q_vectors(adapter);
1168 if (err) {
1169 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1170 goto err_alloc_q_vectors;
1171 }
1172
1173 err = igb_alloc_queues(adapter);
1174 if (err) {
1175 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1176 goto err_alloc_queues;
1177 }
1178
1179 err = igb_map_ring_to_vector(adapter);
1180 if (err) {
1181 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1182 goto err_map_queues;
1183 }
1184
1185
1186 return 0;
1187err_map_queues:
1188 igb_free_queues(adapter);
1189err_alloc_queues:
1190 igb_free_q_vectors(adapter);
1191err_alloc_q_vectors:
1192 igb_reset_interrupt_capability(adapter);
1193 return err;
1194}
1195
9d5c8243
AK		 1196/**
1197 * igb_request_irq - initialize interrupts
1198 *
1199 * Attempts to configure interrupts using the best available
1200 * capabilities of the hardware and kernel.
1201 **/
1202static int igb_request_irq(struct igb_adapter *adapter)
1203{
1204 struct net_device *netdev = adapter->netdev;
047e0030 1205 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1206 int err = 0;
1207
1208 if (adapter->msix_entries) {
1209 err = igb_request_msix(adapter);
844290e5 1210 if (!err)
9d5c8243 1211 goto request_done;
9d5c8243 1212 /* fall back to MSI */
047e0030 1213 igb_clear_interrupt_scheme(adapter);
9d5c8243 1214 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1215 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1216 igb_free_all_tx_resources(adapter);
1217 igb_free_all_rx_resources(adapter);
047e0030 1218 adapter->num_tx_queues = 1;
9d5c8243 1219 adapter->num_rx_queues = 1;
047e0030
AD		 1220 adapter->num_q_vectors = 1;
1221 err = igb_alloc_q_vectors(adapter);
1222 if (err) {
1223 dev_err(&pdev->dev,
1224 "Unable to allocate memory for vectors\n");
1225 goto request_done;
1226 }
1227 err = igb_alloc_queues(adapter);
1228 if (err) {
1229 dev_err(&pdev->dev,
1230 "Unable to allocate memory for queues\n");
1231 igb_free_q_vectors(adapter);
1232 goto request_done;
1233 }
1234 igb_setup_all_tx_resources(adapter);
1235 igb_setup_all_rx_resources(adapter);
844290e5 1236 } else {
feeb2721 1237 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243 1238 }
844290e5 1239
7dfc16fa 1240 if (adapter->flags & IGB_FLAG_HAS_MSI) {
a0607fd3 1241 err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
047e0030 1242 netdev->name, adapter);
9d5c8243
AK		 1243 if (!err)
1244 goto request_done;
047e0030 1245
9d5c8243
AK		 1246 /* fall back to legacy interrupts */
1247 igb_reset_interrupt_capability(adapter);
7dfc16fa 1248 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1249 }
1250
a0607fd3 1251 err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1252 netdev->name, adapter);
9d5c8243 1253
6cb5e577 1254 if (err)
9d5c8243
AK		 1255 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
1256 err);
9d5c8243
AK		 1257
1258request_done:
1259 return err;
1260}
1261
1262static void igb_free_irq(struct igb_adapter *adapter)
1263{
9d5c8243
AK		 1264 if (adapter->msix_entries) {
1265 int vector = 0, i;
1266
047e0030 1267 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1268
047e0030
AD		 1269 for (i = 0; i < adapter->num_q_vectors; i++) {
1270 struct igb_q_vector *q_vector = adapter->q_vector[i];
1271 free_irq(adapter->msix_entries[vector++].vector,
1272 q_vector);
1273 }
1274 } else {
1275 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1276 }
9d5c8243
AK		 1277}
1278
1279/**
1280 * igb_irq_disable - Mask off interrupt generation on the NIC
1281 * @adapter: board private structure
1282 **/
1283static void igb_irq_disable(struct igb_adapter *adapter)
1284{
1285 struct e1000_hw *hw = &adapter->hw;
1286
25568a53
AD		 1287 /*
1288 * we need to be careful when disabling interrupts. The VFs are also
1289 * mapped into these registers and so clearing the bits can cause
1290 * issues on the VF drivers so we only need to clear what we set
1291 */
9d5c8243 1292 if (adapter->msix_entries) {
2dfd1212
AD		 1293 u32 regval = rd32(E1000_EIAM);
1294 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1295 wr32(E1000_EIMC, adapter->eims_enable_mask);
1296 regval = rd32(E1000_EIAC);
1297 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1298 }
844290e5
PW		 1299
1300 wr32(E1000_IAM, 0);
9d5c8243
AK		 1301 wr32(E1000_IMC, ~0);
1302 wrfl();
81a61859
ET		 1303 if (adapter->msix_entries) {
1304 int i;
1305 for (i = 0; i < adapter->num_q_vectors; i++)
1306 synchronize_irq(adapter->msix_entries[i].vector);
1307 } else {
1308 synchronize_irq(adapter->pdev->irq);
1309 }
9d5c8243
AK		 1310}
1311
1312/**
1313 * igb_irq_enable - Enable default interrupt generation settings
1314 * @adapter: board private structure
1315 **/
1316static void igb_irq_enable(struct igb_adapter *adapter)
1317{
1318 struct e1000_hw *hw = &adapter->hw;
1319
1320 if (adapter->msix_entries) {
25568a53 1321 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
2dfd1212
AD		 1322 u32 regval = rd32(E1000_EIAC);
1323 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1324 regval = rd32(E1000_EIAM);
1325 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1326 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1327 if (adapter->vfs_allocated_count) {
4ae196df 1328 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1329 ims |= E1000_IMS_VMMB;
1330 }
55cac248
AD		 1331 if (adapter->hw.mac.type == e1000_82580)
1332 ims |= E1000_IMS_DRSTA;
1333
25568a53 1334 wr32(E1000_IMS, ims);
844290e5 1335 } else {
55cac248
AD		 1336 wr32(E1000_IMS, IMS_ENABLE_MASK |
1337 E1000_IMS_DRSTA);
1338 wr32(E1000_IAM, IMS_ENABLE_MASK |
1339 E1000_IMS_DRSTA);
844290e5 1340 }
9d5c8243
AK		 1341}
1342
1343static void igb_update_mng_vlan(struct igb_adapter *adapter)
1344{
51466239 1345 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1346 u16 vid = adapter->hw.mng_cookie.vlan_id;
1347 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1348
1349 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1350 /* add VID to filter table */
1351 igb_vfta_set(hw, vid, true);
1352 adapter->mng_vlan_id = vid;
1353 } else {
1354 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1355 }
1356
1357 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1358 (vid != old_vid) &&
1359 !vlan_group_get_device(adapter->vlgrp, old_vid)) {
1360 /* remove VID from filter table */
1361 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1362 }
1363}
1364
1365/**
1366 * igb_release_hw_control - release control of the h/w to f/w
1367 * @adapter: address of board private structure
1368 *
1369 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1370 * For ASF and Pass Through versions of f/w this means that the
1371 * driver is no longer loaded.
1372 *
1373 **/
1374static void igb_release_hw_control(struct igb_adapter *adapter)
1375{
1376 struct e1000_hw *hw = &adapter->hw;
1377 u32 ctrl_ext;
1378
1379 /* Let firmware take over control of h/w */
1380 ctrl_ext = rd32(E1000_CTRL_EXT);
1381 wr32(E1000_CTRL_EXT,
1382 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1383}
1384
9d5c8243
AK		 1385/**
1386 * igb_get_hw_control - get control of the h/w from f/w
1387 * @adapter: address of board private structure
1388 *
1389 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1390 * For ASF and Pass Through versions of f/w this means that
1391 * the driver is loaded.
1392 *
1393 **/
1394static void igb_get_hw_control(struct igb_adapter *adapter)
1395{
1396 struct e1000_hw *hw = &adapter->hw;
1397 u32 ctrl_ext;
1398
1399 /* Let firmware know the driver has taken over */
1400 ctrl_ext = rd32(E1000_CTRL_EXT);
1401 wr32(E1000_CTRL_EXT,
1402 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1403}
1404
9d5c8243
AK		 1405/**
1406 * igb_configure - configure the hardware for RX and TX
1407 * @adapter: private board structure
1408 **/
1409static void igb_configure(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
1412 int i;
1413
1414 igb_get_hw_control(adapter);
ff41f8dc 1415 igb_set_rx_mode(netdev);
9d5c8243
AK		 1416
1417 igb_restore_vlan(adapter);
9d5c8243 1418
85b430b4 1419 igb_setup_tctl(adapter);
06cf2666 1420 igb_setup_mrqc(adapter);
9d5c8243 1421 igb_setup_rctl(adapter);
85b430b4
AD		 1422
1423 igb_configure_tx(adapter);
9d5c8243 1424 igb_configure_rx(adapter);
662d7205
AD		 1425
1426 igb_rx_fifo_flush_82575(&adapter->hw);
1427
c493ea45 1428 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1429 * at least 1 descriptor unused to make sure
1430 * next_to_use != next_to_clean */
1431 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1432 struct igb_ring *ring = adapter->rx_ring[i];
c493ea45 1433 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243 1434 }
9d5c8243
AK		 1435}
1436
88a268c1
NN		 1437/**
1438 * igb_power_up_link - Power up the phy/serdes link
1439 * @adapter: address of board private structure
1440 **/
1441void igb_power_up_link(struct igb_adapter *adapter)
1442{
1443 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1444 igb_power_up_phy_copper(&adapter->hw);
1445 else
1446 igb_power_up_serdes_link_82575(&adapter->hw);
1447}
1448
1449/**
1450 * igb_power_down_link - Power down the phy/serdes link
1451 * @adapter: address of board private structure
1452 */
1453static void igb_power_down_link(struct igb_adapter *adapter)
1454{
1455 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1456 igb_power_down_phy_copper_82575(&adapter->hw);
1457 else
1458 igb_shutdown_serdes_link_82575(&adapter->hw);
1459}
9d5c8243
AK		 1460
1461/**
1462 * igb_up - Open the interface and prepare it to handle traffic
1463 * @adapter: board private structure
1464 **/
9d5c8243
AK		 1465int igb_up(struct igb_adapter *adapter)
1466{
1467 struct e1000_hw *hw = &adapter->hw;
1468 int i;
1469
1470 /* hardware has been reset, we need to reload some things */
1471 igb_configure(adapter);
1472
1473 clear_bit(__IGB_DOWN, &adapter->state);
1474
047e0030
AD		 1475 for (i = 0; i < adapter->num_q_vectors; i++) {
1476 struct igb_q_vector *q_vector = adapter->q_vector[i];
1477 napi_enable(&q_vector->napi);
1478 }
844290e5 1479 if (adapter->msix_entries)
9d5c8243 1480 igb_configure_msix(adapter);
feeb2721
AD		 1481 else
1482 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1483
1484 /* Clear any pending interrupts. */
1485 rd32(E1000_ICR);
1486 igb_irq_enable(adapter);
1487
d4960307
AD		 1488 /* notify VFs that reset has been completed */
1489 if (adapter->vfs_allocated_count) {
1490 u32 reg_data = rd32(E1000_CTRL_EXT);
1491 reg_data |= E1000_CTRL_EXT_PFRSTD;
1492 wr32(E1000_CTRL_EXT, reg_data);
1493 }
1494
4cb9be7a
JB		 1495 netif_tx_start_all_queues(adapter->netdev);
1496
25568a53
AD		 1497 /* start the watchdog. */
1498 hw->mac.get_link_status = 1;
1499 schedule_work(&adapter->watchdog_task);
1500
9d5c8243
AK		 1501 return 0;
1502}
1503
1504void igb_down(struct igb_adapter *adapter)
1505{
9d5c8243 1506 struct net_device *netdev = adapter->netdev;
330a6d6a 1507 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1508 u32 tctl, rctl;
1509 int i;
1510
1511 /* signal that we're down so the interrupt handler does not
1512 * reschedule our watchdog timer */
1513 set_bit(__IGB_DOWN, &adapter->state);
1514
1515 /* disable receives in the hardware */
1516 rctl = rd32(E1000_RCTL);
1517 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1518 /* flush and sleep below */
1519
fd2ea0a7 1520 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1521
1522 /* disable transmits in the hardware */
1523 tctl = rd32(E1000_TCTL);
1524 tctl &= ~E1000_TCTL_EN;
1525 wr32(E1000_TCTL, tctl);
1526 /* flush both disables and wait for them to finish */
1527 wrfl();
1528 msleep(10);
1529
047e0030
AD		 1530 for (i = 0; i < adapter->num_q_vectors; i++) {
1531 struct igb_q_vector *q_vector = adapter->q_vector[i];
1532 napi_disable(&q_vector->napi);
1533 }
9d5c8243 1534
9d5c8243
AK		 1535 igb_irq_disable(adapter);
1536
1537 del_timer_sync(&adapter->watchdog_timer);
1538 del_timer_sync(&adapter->phy_info_timer);
1539
9d5c8243 1540 netif_carrier_off(netdev);
04fe6358
AD		 1541
1542 /* record the stats before reset*/
12dcd86b
ED		 1543 spin_lock(&adapter->stats64_lock);
1544 igb_update_stats(adapter, &adapter->stats64);
1545 spin_unlock(&adapter->stats64_lock);
04fe6358 1546
9d5c8243
AK		 1547 adapter->link_speed = 0;
1548 adapter->link_duplex = 0;
1549
3023682e
JK		 1550 if (!pci_channel_offline(adapter->pdev))
1551 igb_reset(adapter);
9d5c8243
AK		 1552 igb_clean_all_tx_rings(adapter);
1553 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1554#ifdef CONFIG_IGB_DCA
1555
1556 /* since we reset the hardware DCA settings were cleared */
1557 igb_setup_dca(adapter);
1558#endif
9d5c8243
AK		 1559}
1560
1561void igb_reinit_locked(struct igb_adapter *adapter)
1562{
1563 WARN_ON(in_interrupt());
1564 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1565 msleep(1);
1566 igb_down(adapter);
1567 igb_up(adapter);
1568 clear_bit(__IGB_RESETTING, &adapter->state);
1569}
1570
1571void igb_reset(struct igb_adapter *adapter)
1572{
090b1795 1573 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1574 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1575 struct e1000_mac_info *mac = &hw->mac;
1576 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1577 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1578 u16 hwm;
1579
1580 /* Repartition Pba for greater than 9k mtu
1581 * To take effect CTRL.RST is required.
1582 */
fa4dfae0 1583 switch (mac->type) {
d2ba2ed8 1584 case e1000_i350:
55cac248
AD		 1585 case e1000_82580:
1586 pba = rd32(E1000_RXPBS);
1587 pba = igb_rxpbs_adjust_82580(pba);
1588 break;
fa4dfae0 1589 case e1000_82576:
d249be54
AD		 1590 pba = rd32(E1000_RXPBS);
1591 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1592 break;
1593 case e1000_82575:
1594 default:
1595 pba = E1000_PBA_34K;
1596 break;
2d064c06 1597 }
9d5c8243 1598
2d064c06
AD		 1599 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1600 (mac->type < e1000_82576)) {
9d5c8243
AK		 1601 /* adjust PBA for jumbo frames */
1602 wr32(E1000_PBA, pba);
1603
1604 /* To maintain wire speed transmits, the Tx FIFO should be
1605 * large enough to accommodate two full transmit packets,
1606 * rounded up to the next 1KB and expressed in KB. Likewise,
1607 * the Rx FIFO should be large enough to accommodate at least
1608 * one full receive packet and is similarly rounded up and
1609 * expressed in KB. */
1610 pba = rd32(E1000_PBA);
1611 /* upper 16 bits has Tx packet buffer allocation size in KB */
1612 tx_space = pba >> 16;
1613 /* lower 16 bits has Rx packet buffer allocation size in KB */
1614 pba &= 0xffff;
1615 /* the tx fifo also stores 16 bytes of information about the tx
1616 * but don't include ethernet FCS because hardware appends it */
1617 min_tx_space = (adapter->max_frame_size +
85e8d004 1618 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1619 ETH_FCS_LEN) * 2;
1620 min_tx_space = ALIGN(min_tx_space, 1024);
1621 min_tx_space >>= 10;
1622 /* software strips receive CRC, so leave room for it */
1623 min_rx_space = adapter->max_frame_size;
1624 min_rx_space = ALIGN(min_rx_space, 1024);
1625 min_rx_space >>= 10;
1626
1627 /* If current Tx allocation is less than the min Tx FIFO size,
1628 * and the min Tx FIFO size is less than the current Rx FIFO
1629 * allocation, take space away from current Rx allocation */
1630 if (tx_space < min_tx_space &&
1631 ((min_tx_space - tx_space) < pba)) {
1632 pba = pba - (min_tx_space - tx_space);
1633
1634 /* if short on rx space, rx wins and must trump tx
1635 * adjustment */
1636 if (pba < min_rx_space)
1637 pba = min_rx_space;
1638 }
2d064c06 1639 wr32(E1000_PBA, pba);
9d5c8243 1640 }
9d5c8243
AK		 1641
1642 /* flow control settings */
1643 /* The high water mark must be low enough to fit one full frame
1644 * (or the size used for early receive) above it in the Rx FIFO.
1645 * Set it to the lower of:
1646 * - 90% of the Rx FIFO size, or
1647 * - the full Rx FIFO size minus one full frame */
1648 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1649 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1650
d405ea3e
AD		 1651 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1652 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1653 fc->pause_time = 0xFFFF;
1654 fc->send_xon = 1;
0cce119a 1655 fc->current_mode = fc->requested_mode;
9d5c8243 1656
4ae196df
AD		 1657 /* disable receive for all VFs and wait one second */
1658 if (adapter->vfs_allocated_count) {
1659 int i;
1660 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1661 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1662
1663 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1664 igb_ping_all_vfs(adapter);
4ae196df
AD		 1665
1666 /* disable transmits and receives */
1667 wr32(E1000_VFRE, 0);
1668 wr32(E1000_VFTE, 0);
1669 }
1670
9d5c8243 1671 /* Allow time for pending master requests to run */
330a6d6a 1672 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1673 wr32(E1000_WUC, 0);
1674
330a6d6a 1675 if (hw->mac.ops.init_hw(hw))
090b1795 1676 dev_err(&pdev->dev, "Hardware Error\n");
9d5c8243 1677
55cac248
AD		 1678 if (hw->mac.type == e1000_82580) {
1679 u32 reg = rd32(E1000_PCIEMISC);
1680 wr32(E1000_PCIEMISC,
1681 reg & ~E1000_PCIEMISC_LX_DECISION);
1682 }
88a268c1
NN		 1683 if (!netif_running(adapter->netdev))
1684 igb_power_down_link(adapter);
1685
9d5c8243
AK		 1686 igb_update_mng_vlan(adapter);
1687
1688 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1689 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1690
330a6d6a 1691 igb_get_phy_info(hw);
9d5c8243
AK		 1692}
1693
2e5c6922 1694static const struct net_device_ops igb_netdev_ops = {
559e9c49 1695 .ndo_open = igb_open,
2e5c6922 1696 .ndo_stop = igb_close,
00829823 1697 .ndo_start_xmit = igb_xmit_frame_adv,
12dcd86b 1698 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc
AD		 1699 .ndo_set_rx_mode = igb_set_rx_mode,
1700 .ndo_set_multicast_list = igb_set_rx_mode,
2e5c6922
SH		 1701 .ndo_set_mac_address = igb_set_mac,
1702 .ndo_change_mtu = igb_change_mtu,
1703 .ndo_do_ioctl = igb_ioctl,
1704 .ndo_tx_timeout = igb_tx_timeout,
1705 .ndo_validate_addr = eth_validate_addr,
1706 .ndo_vlan_rx_register = igb_vlan_rx_register,
1707 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1708 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1709 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1710 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1711 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1712 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1713#ifdef CONFIG_NET_POLL_CONTROLLER
1714 .ndo_poll_controller = igb_netpoll,
1715#endif
1716};
1717
9d5c8243
AK		 1718/**
1719 * igb_probe - Device Initialization Routine
1720 * @pdev: PCI device information struct
1721 * @ent: entry in igb_pci_tbl
1722 *
1723 * Returns 0 on success, negative on failure
1724 *
1725 * igb_probe initializes an adapter identified by a pci_dev structure.
1726 * The OS initialization, configuring of the adapter private structure,
1727 * and a hardware reset occur.
1728 **/
1729static int __devinit igb_probe(struct pci_dev *pdev,
1730 const struct pci_device_id *ent)
1731{
1732 struct net_device *netdev;
1733 struct igb_adapter *adapter;
1734 struct e1000_hw *hw;
4337e993 1735 u16 eeprom_data = 0;
9835fd73 1736 s32 ret_val;
4337e993 1737 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1738 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1739 unsigned long mmio_start, mmio_len;
2d6a5e95 1740 int err, pci_using_dac;
9d5c8243 1741 u16 eeprom_apme_mask = IGB_EEPROM_APME;
9835fd73 1742 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1743
bded64a7
AG		 1744 /* Catch broken hardware that put the wrong VF device ID in
1745 * the PCIe SR-IOV capability.
1746 */
1747 if (pdev->is_virtfn) {
1748 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1749 pci_name(pdev), pdev->vendor, pdev->device);
1750 return -EINVAL;
1751 }
1752
aed5dec3 1753 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1754 if (err)
1755 return err;
1756
1757 pci_using_dac = 0;
59d71989 1758 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1759 if (!err) {
59d71989 1760 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1761 if (!err)
1762 pci_using_dac = 1;
1763 } else {
59d71989 1764 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1765 if (err) {
59d71989 1766 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1767 if (err) {
1768 dev_err(&pdev->dev, "No usable DMA "
1769 "configuration, aborting\n");
1770 goto err_dma;
1771 }
1772 }
1773 }
1774
aed5dec3
AD		 1775 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1776 IORESOURCE_MEM),
1777 igb_driver_name);
9d5c8243
AK		 1778 if (err)
1779 goto err_pci_reg;
1780
19d5afd4 1781 pci_enable_pcie_error_reporting(pdev);
40a914fa 1782
9d5c8243 1783 pci_set_master(pdev);
c682fc23 1784 pci_save_state(pdev);
9d5c8243
AK		 1785
1786 err = -ENOMEM;
1bfaf07b
AD		 1787 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1788 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1789 if (!netdev)
1790 goto err_alloc_etherdev;
1791
1792 SET_NETDEV_DEV(netdev, &pdev->dev);
1793
1794 pci_set_drvdata(pdev, netdev);
1795 adapter = netdev_priv(netdev);
1796 adapter->netdev = netdev;
1797 adapter->pdev = pdev;
1798 hw = &adapter->hw;
1799 hw->back = adapter;
1800 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1801
1802 mmio_start = pci_resource_start(pdev, 0);
1803 mmio_len = pci_resource_len(pdev, 0);
1804
1805 err = -EIO;
28b0759c
AD		 1806 hw->hw_addr = ioremap(mmio_start, mmio_len);
1807 if (!hw->hw_addr)
9d5c8243
AK		 1808 goto err_ioremap;
1809
2e5c6922 1810 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1811 igb_set_ethtool_ops(netdev);
9d5c8243 1812 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1813
1814 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1815
1816 netdev->mem_start = mmio_start;
1817 netdev->mem_end = mmio_start + mmio_len;
1818
9d5c8243
AK		 1819 /* PCI config space info */
1820 hw->vendor_id = pdev->vendor;
1821 hw->device_id = pdev->device;
1822 hw->revision_id = pdev->revision;
1823 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1824 hw->subsystem_device_id = pdev->subsystem_device;
1825
9d5c8243
AK		 1826 /* Copy the default MAC, PHY and NVM function pointers */
1827 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1828 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1829 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1830 /* Initialize skew-specific constants */
1831 err = ei->get_invariants(hw);
1832 if (err)
450c87c8 1833 goto err_sw_init;
9d5c8243 1834
450c87c8 1835 /* setup the private structure */
9d5c8243
AK		 1836 err = igb_sw_init(adapter);
1837 if (err)
1838 goto err_sw_init;
1839
1840 igb_get_bus_info_pcie(hw);
1841
1842 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1843
1844 /* Copper options */
1845 if (hw->phy.media_type == e1000_media_type_copper) {
1846 hw->phy.mdix = AUTO_ALL_MODES;
1847 hw->phy.disable_polarity_correction = false;
1848 hw->phy.ms_type = e1000_ms_hw_default;
1849 }
1850
1851 if (igb_check_reset_block(hw))
1852 dev_info(&pdev->dev,
1853 "PHY reset is blocked due to SOL/IDER session.\n");
1854
1855 netdev->features = NETIF_F_SG |
7d8eb29e 1856 NETIF_F_IP_CSUM |
9d5c8243
AK		 1857 NETIF_F_HW_VLAN_TX |
1858 NETIF_F_HW_VLAN_RX |
1859 NETIF_F_HW_VLAN_FILTER;
1860
7d8eb29e 1861 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1862 netdev->features |= NETIF_F_TSO;
9d5c8243 1863 netdev->features |= NETIF_F_TSO6;
5c0999b7 1864 netdev->features |= NETIF_F_GRO;
d3352520 1865
48f29ffc
JK		 1866 netdev->vlan_features |= NETIF_F_TSO;
1867 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1868 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 1869 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
48f29ffc
JK		 1870 netdev->vlan_features |= NETIF_F_SG;
1871
7b872a55 1872 if (pci_using_dac) {
9d5c8243 1873 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1874 netdev->vlan_features |= NETIF_F_HIGHDMA;
1875 }
9d5c8243 1876
5b043fb0 1877 if (hw->mac.type >= e1000_82576)
b9473560
JB		 1878 netdev->features |= NETIF_F_SCTP_CSUM;
1879
330a6d6a 1880 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1881
1882 /* before reading the NVM, reset the controller to put the device in a
1883 * known good starting state */
1884 hw->mac.ops.reset_hw(hw);
1885
1886 /* make sure the NVM is good */
1887 if (igb_validate_nvm_checksum(hw) < 0) {
1888 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1889 err = -EIO;
1890 goto err_eeprom;
1891 }
1892
1893 /* copy the MAC address out of the NVM */
1894 if (hw->mac.ops.read_mac_addr(hw))
1895 dev_err(&pdev->dev, "NVM Read Error\n");
1896
1897 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1898 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1899
1900 if (!is_valid_ether_addr(netdev->perm_addr)) {
1901 dev_err(&pdev->dev, "Invalid MAC Address\n");
1902 err = -EIO;
1903 goto err_eeprom;
1904 }
1905
c061b18d 1906 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 1907 (unsigned long) adapter);
c061b18d 1908 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 1909 (unsigned long) adapter);
9d5c8243
AK		 1910
1911 INIT_WORK(&adapter->reset_task, igb_reset_task);
1912 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1913
450c87c8 1914 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1915 adapter->fc_autoneg = true;
1916 hw->mac.autoneg = true;
1917 hw->phy.autoneg_advertised = 0x2f;
1918
0cce119a
AD		 1919 hw->fc.requested_mode = e1000_fc_default;
1920 hw->fc.current_mode = e1000_fc_default;
9d5c8243 1921
9d5c8243
AK		 1922 igb_validate_mdi_setting(hw);
1923
9d5c8243
AK		 1924 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1925 * enable the ACPI Magic Packet filter
1926 */
1927
a2cf8b6c 1928 if (hw->bus.func == 0)
312c75ae 1929 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
55cac248
AD		 1930 else if (hw->mac.type == e1000_82580)
1931 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1932 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1933 &eeprom_data);
a2cf8b6c
AD		 1934 else if (hw->bus.func == 1)
1935 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1936
1937 if (eeprom_data & eeprom_apme_mask)
1938 adapter->eeprom_wol |= E1000_WUFC_MAG;
1939
1940 /* now that we have the eeprom settings, apply the special cases where
1941 * the eeprom may be wrong or the board simply won't support wake on
1942 * lan on a particular port */
1943 switch (pdev->device) {
1944 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1945 adapter->eeprom_wol = 0;
1946 break;
1947 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1948 case E1000_DEV_ID_82576_FIBER:
1949 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1950 /* Wake events only supported on port A for dual fiber
1951 * regardless of eeprom setting */
1952 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1953 adapter->eeprom_wol = 0;
1954 break;
c8ea5ea9 1955 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 1956 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 1957 /* if quad port adapter, disable WoL on all but port A */
1958 if (global_quad_port_a != 0)
1959 adapter->eeprom_wol = 0;
1960 else
1961 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1962 /* Reset for multiple quad port adapters */
1963 if (++global_quad_port_a == 4)
1964 global_quad_port_a = 0;
1965 break;
9d5c8243
AK		 1966 }
1967
1968 /* initialize the wol settings based on the eeprom settings */
1969 adapter->wol = adapter->eeprom_wol;
e1b86d84 1970 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1971
1972 /* reset the hardware with the new settings */
1973 igb_reset(adapter);
1974
1975 /* let the f/w know that the h/w is now under the control of the
1976 * driver. */
1977 igb_get_hw_control(adapter);
1978
9d5c8243
AK		 1979 strcpy(netdev->name, "eth%d");
1980 err = register_netdev(netdev);
1981 if (err)
1982 goto err_register;
1983
b168dfc5
JB		 1984 /* carrier off reporting is important to ethtool even BEFORE open */
1985 netif_carrier_off(netdev);
1986
421e02f0 1987#ifdef CONFIG_IGB_DCA
bbd98fe4 1988 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1989 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1990 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1991 igb_setup_dca(adapter);
1992 }
fe4506b6 1993
38c845c7 1994#endif
9d5c8243
AK		 1995 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1996 /* print bus type/speed/width info */
7c510e4b 1997 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 1998 netdev->name,
559e9c49 1999 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2000 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2001 "unknown"),
59c3de89
AD		 2002 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2003 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2004 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2005 "unknown"),
7c510e4b 2006 netdev->dev_addr);
9d5c8243 2007
9835fd73
CW		 2008 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2009 if (ret_val)
2010 strcpy(part_str, "Unknown");
2011 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2012 dev_info(&pdev->dev,
2013 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2014 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2015 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 2016 adapter->num_rx_queues, adapter->num_tx_queues);
2017
9d5c8243
AK		 2018 return 0;
2019
2020err_register:
2021 igb_release_hw_control(adapter);
2022err_eeprom:
2023 if (!igb_check_reset_block(hw))
f5f4cf08 2024 igb_reset_phy(hw);
9d5c8243
AK		 2025
2026 if (hw->flash_address)
2027 iounmap(hw->flash_address);
9d5c8243 2028err_sw_init:
047e0030 2029 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2030 iounmap(hw->hw_addr);
2031err_ioremap:
2032 free_netdev(netdev);
2033err_alloc_etherdev:
559e9c49
AD		 2034 pci_release_selected_regions(pdev,
2035 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2036err_pci_reg:
2037err_dma:
2038 pci_disable_device(pdev);
2039 return err;
2040}
2041
2042/**
2043 * igb_remove - Device Removal Routine
2044 * @pdev: PCI device information struct
2045 *
2046 * igb_remove is called by the PCI subsystem to alert the driver
2047 * that it should release a PCI device. The could be caused by a
2048 * Hot-Plug event, or because the driver is going to be removed from
2049 * memory.
2050 **/
2051static void __devexit igb_remove(struct pci_dev *pdev)
2052{
2053 struct net_device *netdev = pci_get_drvdata(pdev);
2054 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2055 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2056
760141a5
TH		 2057 /*
2058 * The watchdog timer may be rescheduled, so explicitly
2059 * disable watchdog from being rescheduled.
2060 */
9d5c8243
AK		 2061 set_bit(__IGB_DOWN, &adapter->state);
2062 del_timer_sync(&adapter->watchdog_timer);
2063 del_timer_sync(&adapter->phy_info_timer);
2064
760141a5
TH		 2065 cancel_work_sync(&adapter->reset_task);
2066 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2067
421e02f0 2068#ifdef CONFIG_IGB_DCA
7dfc16fa 2069 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2070 dev_info(&pdev->dev, "DCA disabled\n");
2071 dca_remove_requester(&pdev->dev);
7dfc16fa 2072 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2073 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2074 }
2075#endif
2076
9d5c8243
AK		 2077 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2078 * would have already happened in close and is redundant. */
2079 igb_release_hw_control(adapter);
2080
2081 unregister_netdev(netdev);
2082
047e0030 2083 igb_clear_interrupt_scheme(adapter);
9d5c8243 2084
37680117
AD		 2085#ifdef CONFIG_PCI_IOV
2086 /* reclaim resources allocated to VFs */
2087 if (adapter->vf_data) {
2088 /* disable iov and allow time for transactions to clear */
2089 pci_disable_sriov(pdev);
2090 msleep(500);
2091
2092 kfree(adapter->vf_data);
2093 adapter->vf_data = NULL;
2094 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2095 msleep(100);
2096 dev_info(&pdev->dev, "IOV Disabled\n");
2097 }
2098#endif
559e9c49 2099
28b0759c
AD		 2100 iounmap(hw->hw_addr);
2101 if (hw->flash_address)
2102 iounmap(hw->flash_address);
559e9c49
AD		 2103 pci_release_selected_regions(pdev,
2104 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2105
2106 free_netdev(netdev);
2107
19d5afd4 2108 pci_disable_pcie_error_reporting(pdev);
40a914fa 2109
9d5c8243
AK		 2110 pci_disable_device(pdev);
2111}
2112
a6b623e0
AD		 2113/**
2114 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2115 * @adapter: board private structure to initialize
2116 *
2117 * This function initializes the vf specific data storage and then attempts to
2118 * allocate the VFs. The reason for ordering it this way is because it is much
2119 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2120 * the memory for the VFs.
2121 **/
2122static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2123{
2124#ifdef CONFIG_PCI_IOV
2125 struct pci_dev *pdev = adapter->pdev;
2126
a6b623e0
AD		 2127 if (adapter->vfs_allocated_count) {
2128 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2129 sizeof(struct vf_data_storage),
2130 GFP_KERNEL);
2131 /* if allocation failed then we do not support SR-IOV */
2132 if (!adapter->vf_data) {
2133 adapter->vfs_allocated_count = 0;
2134 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2135 "Data Storage\n");
2136 }
2137 }
2138
2139 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
2140 kfree(adapter->vf_data);
2141 adapter->vf_data = NULL;
2142#endif /* CONFIG_PCI_IOV */
2143 adapter->vfs_allocated_count = 0;
2144#ifdef CONFIG_PCI_IOV
2145 } else {
2146 unsigned char mac_addr[ETH_ALEN];
2147 int i;
2148 dev_info(&pdev->dev, "%d vfs allocated\n",
2149 adapter->vfs_allocated_count);
2150 for (i = 0; i < adapter->vfs_allocated_count; i++) {
2151 random_ether_addr(mac_addr);
2152 igb_set_vf_mac(adapter, i, mac_addr);
2153 }
2154 }
2155#endif /* CONFIG_PCI_IOV */
2156}
2157
115f459a
AD		 2158
2159/**
2160 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2161 * @adapter: board private structure to initialize
2162 *
2163 * igb_init_hw_timer initializes the function pointer and values for the hw
2164 * timer found in hardware.
2165 **/
2166static void igb_init_hw_timer(struct igb_adapter *adapter)
2167{
2168 struct e1000_hw *hw = &adapter->hw;
2169
2170 switch (hw->mac.type) {
d2ba2ed8 2171 case e1000_i350:
55cac248
AD		 2172 case e1000_82580:
2173 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2174 adapter->cycles.read = igb_read_clock;
2175 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2176 adapter->cycles.mult = 1;
2177 /*
2178 * The 82580 timesync updates the system timer every 8ns by 8ns
2179 * and the value cannot be shifted. Instead we need to shift
2180 * the registers to generate a 64bit timer value. As a result
2181 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2182 * 24 in order to generate a larger value for synchronization.
2183 */
2184 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2185 /* disable system timer temporarily by setting bit 31 */
2186 wr32(E1000_TSAUXC, 0x80000000);
2187 wrfl();
2188
2189 /* Set registers so that rollover occurs soon to test this. */
2190 wr32(E1000_SYSTIMR, 0x00000000);
2191 wr32(E1000_SYSTIML, 0x80000000);
2192 wr32(E1000_SYSTIMH, 0x000000FF);
2193 wrfl();
2194
2195 /* enable system timer by clearing bit 31 */
2196 wr32(E1000_TSAUXC, 0x0);
2197 wrfl();
2198
2199 timecounter_init(&adapter->clock,
2200 &adapter->cycles,
2201 ktime_to_ns(ktime_get_real()));
2202 /*
2203 * Synchronize our NIC clock against system wall clock. NIC
2204 * time stamp reading requires ~3us per sample, each sample
2205 * was pretty stable even under load => only require 10
2206 * samples for each offset comparison.
2207 */
2208 memset(&adapter->compare, 0, sizeof(adapter->compare));
2209 adapter->compare.source = &adapter->clock;
2210 adapter->compare.target = ktime_get_real;
2211 adapter->compare.num_samples = 10;
2212 timecompare_update(&adapter->compare, 0);
2213 break;
115f459a
AD		 2214 case e1000_82576:
2215 /*
2216 * Initialize hardware timer: we keep it running just in case
2217 * that some program needs it later on.
2218 */
2219 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2220 adapter->cycles.read = igb_read_clock;
2221 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2222 adapter->cycles.mult = 1;
2223 /**
2224 * Scale the NIC clock cycle by a large factor so that
2225 * relatively small clock corrections can be added or
2226 * substracted at each clock tick. The drawbacks of a large
2227 * factor are a) that the clock register overflows more quickly
2228 * (not such a big deal) and b) that the increment per tick has
2229 * to fit into 24 bits. As a result we need to use a shift of
2230 * 19 so we can fit a value of 16 into the TIMINCA register.
2231 */
2232 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2233 wr32(E1000_TIMINCA,
2234 (1 << E1000_TIMINCA_16NS_SHIFT) |
2235 (16 << IGB_82576_TSYNC_SHIFT));
2236
2237 /* Set registers so that rollover occurs soon to test this. */
2238 wr32(E1000_SYSTIML, 0x00000000);
2239 wr32(E1000_SYSTIMH, 0xFF800000);
2240 wrfl();
2241
2242 timecounter_init(&adapter->clock,
2243 &adapter->cycles,
2244 ktime_to_ns(ktime_get_real()));
2245 /*
2246 * Synchronize our NIC clock against system wall clock. NIC
2247 * time stamp reading requires ~3us per sample, each sample
2248 * was pretty stable even under load => only require 10
2249 * samples for each offset comparison.
2250 */
2251 memset(&adapter->compare, 0, sizeof(adapter->compare));
2252 adapter->compare.source = &adapter->clock;
2253 adapter->compare.target = ktime_get_real;
2254 adapter->compare.num_samples = 10;
2255 timecompare_update(&adapter->compare, 0);
2256 break;
2257 case e1000_82575:
2258 /* 82575 does not support timesync */
2259 default:
2260 break;
2261 }
2262
2263}
2264
9d5c8243
AK		 2265/**
2266 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2267 * @adapter: board private structure to initialize
2268 *
2269 * igb_sw_init initializes the Adapter private data structure.
2270 * Fields are initialized based on PCI device information and
2271 * OS network device settings (MTU size).
2272 **/
2273static int __devinit igb_sw_init(struct igb_adapter *adapter)
2274{
2275 struct e1000_hw *hw = &adapter->hw;
2276 struct net_device *netdev = adapter->netdev;
2277 struct pci_dev *pdev = adapter->pdev;
2278
2279 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2280
68fd9910
AD		 2281 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2282 adapter->rx_ring_count = IGB_DEFAULT_RXD;
4fc82adf
AD		 2283 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2284 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2285
9d5c8243
AK		 2286 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2287 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2288
12dcd86b 2289 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2290#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2291 switch (hw->mac.type) {
2292 case e1000_82576:
2293 case e1000_i350:
9b082d73
SA		 2294 if (max_vfs > 7) {
2295 dev_warn(&pdev->dev,
2296 "Maximum of 7 VFs per PF, using max\n");
2297 adapter->vfs_allocated_count = 7;
2298 } else
2299 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2300 break;
2301 default:
2302 break;
2303 }
a6b623e0 2304#endif /* CONFIG_PCI_IOV */
a99955fc
AD		 2305 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2306
2307 /*
2308 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2309 * then we should combine the queues into a queue pair in order to
2310 * conserve interrupts due to limited supply
2311 */
2312 if ((adapter->rss_queues > 4) ||
2313 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2314 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2315
a6b623e0 2316 /* This call may decrease the number of queues */
047e0030 2317 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2318 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2319 return -ENOMEM;
2320 }
2321
115f459a 2322 igb_init_hw_timer(adapter);
a6b623e0
AD		 2323 igb_probe_vfs(adapter);
2324
9d5c8243
AK		 2325 /* Explicitly disable IRQ since the NIC can be in any state. */
2326 igb_irq_disable(adapter);
2327
2328 set_bit(__IGB_DOWN, &adapter->state);
2329 return 0;
2330}
2331
2332/**
2333 * igb_open - Called when a network interface is made active
2334 * @netdev: network interface device structure
2335 *
2336 * Returns 0 on success, negative value on failure
2337 *
2338 * The open entry point is called when a network interface is made
2339 * active by the system (IFF_UP). At this point all resources needed
2340 * for transmit and receive operations are allocated, the interrupt
2341 * handler is registered with the OS, the watchdog timer is started,
2342 * and the stack is notified that the interface is ready.
2343 **/
2344static int igb_open(struct net_device *netdev)
2345{
2346 struct igb_adapter *adapter = netdev_priv(netdev);
2347 struct e1000_hw *hw = &adapter->hw;
2348 int err;
2349 int i;
2350
2351 /* disallow open during test */
2352 if (test_bit(__IGB_TESTING, &adapter->state))
2353 return -EBUSY;
2354
b168dfc5
JB		 2355 netif_carrier_off(netdev);
2356
9d5c8243
AK		 2357 /* allocate transmit descriptors */
2358 err = igb_setup_all_tx_resources(adapter);
2359 if (err)
2360 goto err_setup_tx;
2361
2362 /* allocate receive descriptors */
2363 err = igb_setup_all_rx_resources(adapter);
2364 if (err)
2365 goto err_setup_rx;
2366
88a268c1 2367 igb_power_up_link(adapter);
9d5c8243 2368
9d5c8243
AK		 2369 /* before we allocate an interrupt, we must be ready to handle it.
2370 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2371 * as soon as we call pci_request_irq, so we have to setup our
2372 * clean_rx handler before we do so. */
2373 igb_configure(adapter);
2374
2375 err = igb_request_irq(adapter);
2376 if (err)
2377 goto err_req_irq;
2378
2379 /* From here on the code is the same as igb_up() */
2380 clear_bit(__IGB_DOWN, &adapter->state);
2381
047e0030
AD		 2382 for (i = 0; i < adapter->num_q_vectors; i++) {
2383 struct igb_q_vector *q_vector = adapter->q_vector[i];
2384 napi_enable(&q_vector->napi);
2385 }
9d5c8243
AK		 2386
2387 /* Clear any pending interrupts. */
2388 rd32(E1000_ICR);
844290e5
PW		 2389
2390 igb_irq_enable(adapter);
2391
d4960307
AD		 2392 /* notify VFs that reset has been completed */
2393 if (adapter->vfs_allocated_count) {
2394 u32 reg_data = rd32(E1000_CTRL_EXT);
2395 reg_data |= E1000_CTRL_EXT_PFRSTD;
2396 wr32(E1000_CTRL_EXT, reg_data);
2397 }
2398
d55b53ff
JK		 2399 netif_tx_start_all_queues(netdev);
2400
25568a53
AD		 2401 /* start the watchdog. */
2402 hw->mac.get_link_status = 1;
2403 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2404
2405 return 0;
2406
2407err_req_irq:
2408 igb_release_hw_control(adapter);
88a268c1 2409 igb_power_down_link(adapter);
9d5c8243
AK		 2410 igb_free_all_rx_resources(adapter);
2411err_setup_rx:
2412 igb_free_all_tx_resources(adapter);
2413err_setup_tx:
2414 igb_reset(adapter);
2415
2416 return err;
2417}
2418
2419/**
2420 * igb_close - Disables a network interface
2421 * @netdev: network interface device structure
2422 *
2423 * Returns 0, this is not allowed to fail
2424 *
2425 * The close entry point is called when an interface is de-activated
2426 * by the OS. The hardware is still under the driver's control, but
2427 * needs to be disabled. A global MAC reset is issued to stop the
2428 * hardware, and all transmit and receive resources are freed.
2429 **/
2430static int igb_close(struct net_device *netdev)
2431{
2432 struct igb_adapter *adapter = netdev_priv(netdev);
2433
2434 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2435 igb_down(adapter);
2436
2437 igb_free_irq(adapter);
2438
2439 igb_free_all_tx_resources(adapter);
2440 igb_free_all_rx_resources(adapter);
2441
9d5c8243
AK		 2442 return 0;
2443}
2444
2445/**
2446 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2447 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2448 *
2449 * Return 0 on success, negative on failure
2450 **/
80785298 2451int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2452{
59d71989 2453 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2454 int size;
2455
2456 size = sizeof(struct igb_buffer) * tx_ring->count;
89bf67f1 2457 tx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2458 if (!tx_ring->buffer_info)
2459 goto err;
9d5c8243
AK		 2460
2461 /* round up to nearest 4K */
85e8d004 2462 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2463 tx_ring->size = ALIGN(tx_ring->size, 4096);
2464
59d71989
AD		 2465 tx_ring->desc = dma_alloc_coherent(dev,
2466 tx_ring->size,
2467 &tx_ring->dma,
2468 GFP_KERNEL);
9d5c8243
AK		 2469
2470 if (!tx_ring->desc)
2471 goto err;
2472
9d5c8243
AK		 2473 tx_ring->next_to_use = 0;
2474 tx_ring->next_to_clean = 0;
9d5c8243
AK		 2475 return 0;
2476
2477err:
2478 vfree(tx_ring->buffer_info);
59d71989 2479 dev_err(dev,
9d5c8243
AK		 2480 "Unable to allocate memory for the transmit descriptor ring\n");
2481 return -ENOMEM;
2482}
2483
2484/**
2485 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2486 * (Descriptors) for all queues
2487 * @adapter: board private structure
2488 *
2489 * Return 0 on success, negative on failure
2490 **/
2491static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2492{
439705e1 2493 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2494 int i, err = 0;
2495
2496 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2497 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2498 if (err) {
439705e1 2499 dev_err(&pdev->dev,
9d5c8243
AK		 2500 "Allocation for Tx Queue %u failed\n", i);
2501 for (i--; i >= 0; i--)
3025a446 2502 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2503 break;
2504 }
2505 }
2506
a99955fc 2507 for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) {
439705e1 2508 int r_idx = i % adapter->num_tx_queues;
3025a446 2509 adapter->multi_tx_table[i] = adapter->tx_ring[r_idx];
eebbbdba 2510 }
9d5c8243
AK		 2511 return err;
2512}
2513
2514/**
85b430b4
AD		 2515 * igb_setup_tctl - configure the transmit control registers
2516 * @adapter: Board private structure
9d5c8243 2517 **/
d7ee5b3a 2518void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2519{
9d5c8243
AK		 2520 struct e1000_hw *hw = &adapter->hw;
2521 u32 tctl;
9d5c8243 2522
85b430b4
AD		 2523 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2524 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2525
2526 /* Program the Transmit Control Register */
9d5c8243
AK		 2527 tctl = rd32(E1000_TCTL);
2528 tctl &= ~E1000_TCTL_CT;
2529 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2530 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2531
2532 igb_config_collision_dist(hw);
2533
9d5c8243
AK		 2534 /* Enable transmits */
2535 tctl |= E1000_TCTL_EN;
2536
2537 wr32(E1000_TCTL, tctl);
2538}
2539
85b430b4
AD		 2540/**
2541 * igb_configure_tx_ring - Configure transmit ring after Reset
2542 * @adapter: board private structure
2543 * @ring: tx ring to configure
2544 *
2545 * Configure a transmit ring after a reset.
2546 **/
d7ee5b3a
AD		 2547void igb_configure_tx_ring(struct igb_adapter *adapter,
2548 struct igb_ring *ring)
85b430b4
AD		 2549{
2550 struct e1000_hw *hw = &adapter->hw;
2551 u32 txdctl;
2552 u64 tdba = ring->dma;
2553 int reg_idx = ring->reg_idx;
2554
2555 /* disable the queue */
2556 txdctl = rd32(E1000_TXDCTL(reg_idx));
2557 wr32(E1000_TXDCTL(reg_idx),
2558 txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
2559 wrfl();
2560 mdelay(10);
2561
2562 wr32(E1000_TDLEN(reg_idx),
2563 ring->count * sizeof(union e1000_adv_tx_desc));
2564 wr32(E1000_TDBAL(reg_idx),
2565 tdba & 0x00000000ffffffffULL);
2566 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2567
fce99e34
AD		 2568 ring->head = hw->hw_addr + E1000_TDH(reg_idx);
2569 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2570 writel(0, ring->head);
2571 writel(0, ring->tail);
85b430b4
AD		 2572
2573 txdctl |= IGB_TX_PTHRESH;
2574 txdctl |= IGB_TX_HTHRESH << 8;
2575 txdctl |= IGB_TX_WTHRESH << 16;
2576
2577 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2578 wr32(E1000_TXDCTL(reg_idx), txdctl);
2579}
2580
2581/**
2582 * igb_configure_tx - Configure transmit Unit after Reset
2583 * @adapter: board private structure
2584 *
2585 * Configure the Tx unit of the MAC after a reset.
2586 **/
2587static void igb_configure_tx(struct igb_adapter *adapter)
2588{
2589 int i;
2590
2591 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2592 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2593}
2594
9d5c8243
AK		 2595/**
2596 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2597 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2598 *
2599 * Returns 0 on success, negative on failure
2600 **/
80785298 2601int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2602{
59d71989 2603 struct device *dev = rx_ring->dev;
9d5c8243
AK		 2604 int size, desc_len;
2605
2606 size = sizeof(struct igb_buffer) * rx_ring->count;
89bf67f1 2607 rx_ring->buffer_info = vzalloc(size);
9d5c8243
AK		 2608 if (!rx_ring->buffer_info)
2609 goto err;
9d5c8243
AK		 2610
2611 desc_len = sizeof(union e1000_adv_rx_desc);
2612
2613 /* Round up to nearest 4K */
2614 rx_ring->size = rx_ring->count * desc_len;
2615 rx_ring->size = ALIGN(rx_ring->size, 4096);
2616
59d71989
AD		 2617 rx_ring->desc = dma_alloc_coherent(dev,
2618 rx_ring->size,
2619 &rx_ring->dma,
2620 GFP_KERNEL);
9d5c8243
AK		 2621
2622 if (!rx_ring->desc)
2623 goto err;
2624
2625 rx_ring->next_to_clean = 0;
2626 rx_ring->next_to_use = 0;
9d5c8243 2627
9d5c8243
AK		 2628 return 0;
2629
2630err:
2631 vfree(rx_ring->buffer_info);
439705e1 2632 rx_ring->buffer_info = NULL;
59d71989
AD		 2633 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2634 " ring\n");
9d5c8243
AK		 2635 return -ENOMEM;
2636}
2637
2638/**
2639 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2640 * (Descriptors) for all queues
2641 * @adapter: board private structure
2642 *
2643 * Return 0 on success, negative on failure
2644 **/
2645static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2646{
439705e1 2647 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2648 int i, err = 0;
2649
2650 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2651 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2652 if (err) {
439705e1 2653 dev_err(&pdev->dev,
9d5c8243
AK		 2654 "Allocation for Rx Queue %u failed\n", i);
2655 for (i--; i >= 0; i--)
3025a446 2656 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2657 break;
2658 }
2659 }
2660
2661 return err;
2662}
2663
06cf2666
AD		 2664/**
2665 * igb_setup_mrqc - configure the multiple receive queue control registers
2666 * @adapter: Board private structure
2667 **/
2668static void igb_setup_mrqc(struct igb_adapter *adapter)
2669{
2670 struct e1000_hw *hw = &adapter->hw;
2671 u32 mrqc, rxcsum;
2672 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2673 union e1000_reta {
2674 u32 dword;
2675 u8 bytes[4];
2676 } reta;
2677 static const u8 rsshash[40] = {
2678 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2679 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2680 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2681 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2682
2683 /* Fill out hash function seeds */
2684 for (j = 0; j < 10; j++) {
2685 u32 rsskey = rsshash[(j * 4)];
2686 rsskey |= rsshash[(j * 4) + 1] << 8;
2687 rsskey |= rsshash[(j * 4) + 2] << 16;
2688 rsskey |= rsshash[(j * 4) + 3] << 24;
2689 array_wr32(E1000_RSSRK(0), j, rsskey);
2690 }
2691
a99955fc 2692 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2693
2694 if (adapter->vfs_allocated_count) {
2695 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2696 switch (hw->mac.type) {
d2ba2ed8 2697 case e1000_i350:
55cac248
AD		 2698 case e1000_82580:
2699 num_rx_queues = 1;
2700 shift = 0;
2701 break;
06cf2666
AD		 2702 case e1000_82576:
2703 shift = 3;
2704 num_rx_queues = 2;
2705 break;
2706 case e1000_82575:
2707 shift = 2;
2708 shift2 = 6;
2709 default:
2710 break;
2711 }
2712 } else {
2713 if (hw->mac.type == e1000_82575)
2714 shift = 6;
2715 }
2716
2717 for (j = 0; j < (32 * 4); j++) {
2718 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2719 if (shift2)
2720 reta.bytes[j & 3] |= num_rx_queues << shift2;
2721 if ((j & 3) == 3)
2722 wr32(E1000_RETA(j >> 2), reta.dword);
2723 }
2724
2725 /*
2726 * Disable raw packet checksumming so that RSS hash is placed in
2727 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2728 * offloads as they are enabled by default
2729 */
2730 rxcsum = rd32(E1000_RXCSUM);
2731 rxcsum |= E1000_RXCSUM_PCSD;
2732
2733 if (adapter->hw.mac.type >= e1000_82576)
2734 /* Enable Receive Checksum Offload for SCTP */
2735 rxcsum |= E1000_RXCSUM_CRCOFL;
2736
2737 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2738 wr32(E1000_RXCSUM, rxcsum);
2739
2740 /* If VMDq is enabled then we set the appropriate mode for that, else
2741 * we default to RSS so that an RSS hash is calculated per packet even
2742 * if we are only using one queue */
2743 if (adapter->vfs_allocated_count) {
2744 if (hw->mac.type > e1000_82575) {
2745 /* Set the default pool for the PF's first queue */
2746 u32 vtctl = rd32(E1000_VT_CTL);
2747 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2748 E1000_VT_CTL_DISABLE_DEF_POOL);
2749 vtctl |= adapter->vfs_allocated_count <<
2750 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2751 wr32(E1000_VT_CTL, vtctl);
2752 }
a99955fc 2753 if (adapter->rss_queues > 1)
06cf2666
AD		 2754 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2755 else
2756 mrqc = E1000_MRQC_ENABLE_VMDQ;
2757 } else {
2758 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2759 }
2760 igb_vmm_control(adapter);
2761
4478a9cd
AD		 2762 /*
2763 * Generate RSS hash based on TCP port numbers and/or
2764 * IPv4/v6 src and dst addresses since UDP cannot be
2765 * hashed reliably due to IP fragmentation
2766 */
2767 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2768 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2769 E1000_MRQC_RSS_FIELD_IPV6 |
2770 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2771 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2772
2773 wr32(E1000_MRQC, mrqc);
2774}
2775
9d5c8243
AK		 2776/**
2777 * igb_setup_rctl - configure the receive control registers
2778 * @adapter: Board private structure
2779 **/
d7ee5b3a 2780void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2781{
2782 struct e1000_hw *hw = &adapter->hw;
2783 u32 rctl;
9d5c8243
AK		 2784
2785 rctl = rd32(E1000_RCTL);
2786
2787 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2788 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2789
69d728ba 2790 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2791 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2792
87cb7e8c
AK		 2793 /*
2794 * enable stripping of CRC. It's unlikely this will break BMC
2795 * redirection as it did with e1000. Newer features require
2796 * that the HW strips the CRC.
73cd78f1 2797 */
87cb7e8c 2798 rctl |= E1000_RCTL_SECRC;
9d5c8243 2799
559e9c49 2800 /* disable store bad packets and clear size bits. */
ec54d7d6 2801 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2802
6ec43fe6
AD		 2803 /* enable LPE to prevent packets larger than max_frame_size */
2804 rctl |= E1000_RCTL_LPE;
9d5c8243 2805
952f72a8
AD		 2806 /* disable queue 0 to prevent tail write w/o re-config */
2807 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2808
e1739522
AD		 2809 /* Attention!!! For SR-IOV PF driver operations you must enable
2810 * queue drop for all VF and PF queues to prevent head of line blocking
2811 * if an un-trusted VF does not provide descriptors to hardware.
2812 */
2813 if (adapter->vfs_allocated_count) {
e1739522
AD		 2814 /* set all queue drop enable bits */
2815 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2816 }
2817
9d5c8243
AK		 2818 wr32(E1000_RCTL, rctl);
2819}
2820
7d5753f0
AD		 2821static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2822 int vfn)
2823{
2824 struct e1000_hw *hw = &adapter->hw;
2825 u32 vmolr;
2826
2827 /* if it isn't the PF check to see if VFs are enabled and
2828 * increase the size to support vlan tags */
2829 if (vfn < adapter->vfs_allocated_count &&
2830 adapter->vf_data[vfn].vlans_enabled)
2831 size += VLAN_TAG_SIZE;
2832
2833 vmolr = rd32(E1000_VMOLR(vfn));
2834 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2835 vmolr |= size | E1000_VMOLR_LPE;
2836 wr32(E1000_VMOLR(vfn), vmolr);
2837
2838 return 0;
2839}
2840
e1739522
AD		 2841/**
2842 * igb_rlpml_set - set maximum receive packet size
2843 * @adapter: board private structure
2844 *
2845 * Configure maximum receivable packet size.
2846 **/
2847static void igb_rlpml_set(struct igb_adapter *adapter)
2848{
2849 u32 max_frame_size = adapter->max_frame_size;
2850 struct e1000_hw *hw = &adapter->hw;
2851 u16 pf_id = adapter->vfs_allocated_count;
2852
2853 if (adapter->vlgrp)
2854 max_frame_size += VLAN_TAG_SIZE;
2855
2856 /* if vfs are enabled we set RLPML to the largest possible request
2857 * size and set the VMOLR RLPML to the size we need */
2858 if (pf_id) {
2859 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
7d5753f0 2860 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 2861 }
2862
2863 wr32(E1000_RLPML, max_frame_size);
2864}
2865
8151d294
WM		 2866static inline void igb_set_vmolr(struct igb_adapter *adapter,
2867 int vfn, bool aupe)
7d5753f0
AD		 2868{
2869 struct e1000_hw *hw = &adapter->hw;
2870 u32 vmolr;
2871
2872 /*
2873 * This register exists only on 82576 and newer so if we are older then
2874 * we should exit and do nothing
2875 */
2876 if (hw->mac.type < e1000_82576)
2877 return;
2878
2879 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 2880 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
2881 if (aupe)
2882 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
2883 else
2884 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 2885
2886 /* clear all bits that might not be set */
2887 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
2888
a99955fc 2889 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 2890 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
2891 /*
2892 * for VMDq only allow the VFs and pool 0 to accept broadcast and
2893 * multicast packets
2894 */
2895 if (vfn <= adapter->vfs_allocated_count)
2896 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
2897
2898 wr32(E1000_VMOLR(vfn), vmolr);
2899}
2900
85b430b4
AD		 2901/**
2902 * igb_configure_rx_ring - Configure a receive ring after Reset
2903 * @adapter: board private structure
2904 * @ring: receive ring to be configured
2905 *
2906 * Configure the Rx unit of the MAC after a reset.
2907 **/
d7ee5b3a
AD		 2908void igb_configure_rx_ring(struct igb_adapter *adapter,
2909 struct igb_ring *ring)
85b430b4
AD		 2910{
2911 struct e1000_hw *hw = &adapter->hw;
2912 u64 rdba = ring->dma;
2913 int reg_idx = ring->reg_idx;
952f72a8 2914 u32 srrctl, rxdctl;
85b430b4
AD		 2915
2916 /* disable the queue */
2917 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2918 wr32(E1000_RXDCTL(reg_idx),
2919 rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
2920
2921 /* Set DMA base address registers */
2922 wr32(E1000_RDBAL(reg_idx),
2923 rdba & 0x00000000ffffffffULL);
2924 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
2925 wr32(E1000_RDLEN(reg_idx),
2926 ring->count * sizeof(union e1000_adv_rx_desc));
2927
2928 /* initialize head and tail */
fce99e34
AD		 2929 ring->head = hw->hw_addr + E1000_RDH(reg_idx);
2930 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
2931 writel(0, ring->head);
2932 writel(0, ring->tail);
85b430b4 2933
952f72a8 2934 /* set descriptor configuration */
4c844851
AD		 2935 if (ring->rx_buffer_len < IGB_RXBUFFER_1024) {
2936 srrctl = ALIGN(ring->rx_buffer_len, 64) <<
952f72a8
AD		 2937 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2938#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
2939 srrctl |= IGB_RXBUFFER_16384 >>
2940 E1000_SRRCTL_BSIZEPKT_SHIFT;
2941#else
2942 srrctl |= (PAGE_SIZE / 2) >>
2943 E1000_SRRCTL_BSIZEPKT_SHIFT;
2944#endif
2945 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2946 } else {
4c844851 2947 srrctl = ALIGN(ring->rx_buffer_len, 1024) >>
952f72a8
AD		 2948 E1000_SRRCTL_BSIZEPKT_SHIFT;
2949 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2950 }
757b77e2
NN		 2951 if (hw->mac.type == e1000_82580)
2952 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 2953 /* Only set Drop Enable if we are supporting multiple queues */
2954 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
2955 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 2956
2957 wr32(E1000_SRRCTL(reg_idx), srrctl);
2958
7d5753f0 2959 /* set filtering for VMDQ pools */
8151d294 2960 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 2961
85b430b4
AD		 2962 /* enable receive descriptor fetching */
2963 rxdctl = rd32(E1000_RXDCTL(reg_idx));
2964 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2965 rxdctl &= 0xFFF00000;
2966 rxdctl |= IGB_RX_PTHRESH;
2967 rxdctl |= IGB_RX_HTHRESH << 8;
2968 rxdctl |= IGB_RX_WTHRESH << 16;
2969 wr32(E1000_RXDCTL(reg_idx), rxdctl);
2970}
2971
9d5c8243
AK		 2972/**
2973 * igb_configure_rx - Configure receive Unit after Reset
2974 * @adapter: board private structure
2975 *
2976 * Configure the Rx unit of the MAC after a reset.
2977 **/
2978static void igb_configure_rx(struct igb_adapter *adapter)
2979{
9107584e 2980 int i;
9d5c8243 2981
68d480c4
AD		 2982 /* set UTA to appropriate mode */
2983 igb_set_uta(adapter);
2984
26ad9178
AD		 2985 /* set the correct pool for the PF default MAC address in entry 0 */
2986 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
2987 adapter->vfs_allocated_count);
2988
06cf2666
AD		 2989 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2990 * the Base and Length of the Rx Descriptor Ring */
2991 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 2992 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 2993}
2994
2995/**
2996 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2997 * @tx_ring: Tx descriptor ring for a specific queue
2998 *
2999 * Free all transmit software resources
3000 **/
68fd9910 3001void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3002{
3b644cf6 3003 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 3004
3005 vfree(tx_ring->buffer_info);
3006 tx_ring->buffer_info = NULL;
3007
439705e1
AD		 3008 /* if not set, then don't free */
3009 if (!tx_ring->desc)
3010 return;
3011
59d71989
AD		 3012 dma_free_coherent(tx_ring->dev, tx_ring->size,
3013 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3014
3015 tx_ring->desc = NULL;
3016}
3017
3018/**
3019 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3020 * @adapter: board private structure
3021 *
3022 * Free all transmit software resources
3023 **/
3024static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3025{
3026 int i;
3027
3028 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3029 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3030}
3031
b1a436c3
AD		 3032void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring,
3033 struct igb_buffer *buffer_info)
9d5c8243 3034{
6366ad33
AD		 3035 if (buffer_info->dma) {
3036 if (buffer_info->mapped_as_page)
59d71989 3037 dma_unmap_page(tx_ring->dev,
6366ad33
AD		 3038 buffer_info->dma,
3039 buffer_info->length,
59d71989 3040 DMA_TO_DEVICE);
6366ad33 3041 else
59d71989 3042 dma_unmap_single(tx_ring->dev,
6366ad33
AD		 3043 buffer_info->dma,
3044 buffer_info->length,
59d71989 3045 DMA_TO_DEVICE);
6366ad33
AD		 3046 buffer_info->dma = 0;
3047 }
9d5c8243
AK		 3048 if (buffer_info->skb) {
3049 dev_kfree_skb_any(buffer_info->skb);
3050 buffer_info->skb = NULL;
3051 }
3052 buffer_info->time_stamp = 0;
6366ad33
AD		 3053 buffer_info->length = 0;
3054 buffer_info->next_to_watch = 0;
3055 buffer_info->mapped_as_page = false;
9d5c8243
AK		 3056}
3057
3058/**
3059 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3060 * @tx_ring: ring to be cleaned
3061 **/
3b644cf6 3062static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243
AK		 3063{
3064 struct igb_buffer *buffer_info;
3065 unsigned long size;
3066 unsigned int i;
3067
3068 if (!tx_ring->buffer_info)
3069 return;
3070 /* Free all the Tx ring sk_buffs */
3071
3072 for (i = 0; i < tx_ring->count; i++) {
3073 buffer_info = &tx_ring->buffer_info[i];
80785298 3074 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3075 }
3076
3077 size = sizeof(struct igb_buffer) * tx_ring->count;
3078 memset(tx_ring->buffer_info, 0, size);
3079
3080 /* Zero out the descriptor ring */
9d5c8243
AK		 3081 memset(tx_ring->desc, 0, tx_ring->size);
3082
3083 tx_ring->next_to_use = 0;
3084 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3085}
3086
3087/**
3088 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3089 * @adapter: board private structure
3090 **/
3091static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3092{
3093 int i;
3094
3095 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3096 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3097}
3098
3099/**
3100 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3101 * @rx_ring: ring to clean the resources from
3102 *
3103 * Free all receive software resources
3104 **/
68fd9910 3105void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3106{
3b644cf6 3107 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 3108
3109 vfree(rx_ring->buffer_info);
3110 rx_ring->buffer_info = NULL;
3111
439705e1
AD		 3112 /* if not set, then don't free */
3113 if (!rx_ring->desc)
3114 return;
3115
59d71989
AD		 3116 dma_free_coherent(rx_ring->dev, rx_ring->size,
3117 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3118
3119 rx_ring->desc = NULL;
3120}
3121
3122/**
3123 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3124 * @adapter: board private structure
3125 *
3126 * Free all receive software resources
3127 **/
3128static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3129{
3130 int i;
3131
3132 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3133 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3134}
3135
3136/**
3137 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3138 * @rx_ring: ring to free buffers from
3139 **/
3b644cf6 3140static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243
AK		 3141{
3142 struct igb_buffer *buffer_info;
9d5c8243
AK		 3143 unsigned long size;
3144 unsigned int i;
3145
3146 if (!rx_ring->buffer_info)
3147 return;
439705e1 3148
9d5c8243
AK		 3149 /* Free all the Rx ring sk_buffs */
3150 for (i = 0; i < rx_ring->count; i++) {
3151 buffer_info = &rx_ring->buffer_info[i];
3152 if (buffer_info->dma) {
59d71989 3153 dma_unmap_single(rx_ring->dev,
80785298 3154 buffer_info->dma,
4c844851 3155 rx_ring->rx_buffer_len,
59d71989 3156 DMA_FROM_DEVICE);
9d5c8243
AK		 3157 buffer_info->dma = 0;
3158 }
3159
3160 if (buffer_info->skb) {
3161 dev_kfree_skb(buffer_info->skb);
3162 buffer_info->skb = NULL;
3163 }
6ec43fe6 3164 if (buffer_info->page_dma) {
59d71989 3165 dma_unmap_page(rx_ring->dev,
80785298 3166 buffer_info->page_dma,
6ec43fe6 3167 PAGE_SIZE / 2,
59d71989 3168 DMA_FROM_DEVICE);
6ec43fe6
AD		 3169 buffer_info->page_dma = 0;
3170 }
9d5c8243 3171 if (buffer_info->page) {
9d5c8243
AK		 3172 put_page(buffer_info->page);
3173 buffer_info->page = NULL;
bf36c1a0 3174 buffer_info->page_offset = 0;
9d5c8243
AK		 3175 }
3176 }
3177
9d5c8243
AK		 3178 size = sizeof(struct igb_buffer) * rx_ring->count;
3179 memset(rx_ring->buffer_info, 0, size);
3180
3181 /* Zero out the descriptor ring */
3182 memset(rx_ring->desc, 0, rx_ring->size);
3183
3184 rx_ring->next_to_clean = 0;
3185 rx_ring->next_to_use = 0;
9d5c8243
AK		 3186}
3187
3188/**
3189 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3190 * @adapter: board private structure
3191 **/
3192static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3193{
3194 int i;
3195
3196 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3197 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3198}
3199
3200/**
3201 * igb_set_mac - Change the Ethernet Address of the NIC
3202 * @netdev: network interface device structure
3203 * @p: pointer to an address structure
3204 *
3205 * Returns 0 on success, negative on failure
3206 **/
3207static int igb_set_mac(struct net_device *netdev, void *p)
3208{
3209 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3210 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3211 struct sockaddr *addr = p;
3212
3213 if (!is_valid_ether_addr(addr->sa_data))
3214 return -EADDRNOTAVAIL;
3215
3216 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3217 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3218
26ad9178
AD		 3219 /* set the correct pool for the new PF MAC address in entry 0 */
3220 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3221 adapter->vfs_allocated_count);
e1739522 3222
9d5c8243
AK		 3223 return 0;
3224}
3225
3226/**
68d480c4 3227 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3228 * @netdev: network interface device structure
3229 *
68d480c4
AD		 3230 * Writes multicast address list to the MTA hash table.
3231 * Returns: -ENOMEM on failure
3232 * 0 on no addresses written
3233 * X on writing X addresses to MTA
9d5c8243 3234 **/
68d480c4 3235static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3236{
3237 struct igb_adapter *adapter = netdev_priv(netdev);
3238 struct e1000_hw *hw = &adapter->hw;
22bedad3 3239 struct netdev_hw_addr *ha;
68d480c4 3240 u8 *mta_list;
9d5c8243
AK		 3241 int i;
3242
4cd24eaf 3243 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3244 /* nothing to program, so clear mc list */
3245 igb_update_mc_addr_list(hw, NULL, 0);
3246 igb_restore_vf_multicasts(adapter);
3247 return 0;
3248 }
9d5c8243 3249
4cd24eaf 3250 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3251 if (!mta_list)
3252 return -ENOMEM;
ff41f8dc 3253
68d480c4 3254 /* The shared function expects a packed array of only addresses. */
48e2f183 3255 i = 0;
22bedad3
JP		 3256 netdev_for_each_mc_addr(ha, netdev)
3257 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3258
68d480c4
AD		 3259 igb_update_mc_addr_list(hw, mta_list, i);
3260 kfree(mta_list);
3261
4cd24eaf 3262 return netdev_mc_count(netdev);
68d480c4
AD		 3263}
3264
3265/**
3266 * igb_write_uc_addr_list - write unicast addresses to RAR table
3267 * @netdev: network interface device structure
3268 *
3269 * Writes unicast address list to the RAR table.
3270 * Returns: -ENOMEM on failure/insufficient address space
3271 * 0 on no addresses written
3272 * X on writing X addresses to the RAR table
3273 **/
3274static int igb_write_uc_addr_list(struct net_device *netdev)
3275{
3276 struct igb_adapter *adapter = netdev_priv(netdev);
3277 struct e1000_hw *hw = &adapter->hw;
3278 unsigned int vfn = adapter->vfs_allocated_count;
3279 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3280 int count = 0;
3281
3282 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3283 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3284 return -ENOMEM;
9d5c8243 3285
32e7bfc4 3286 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3287 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3288
3289 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3290 if (!rar_entries)
3291 break;
26ad9178
AD		 3292 igb_rar_set_qsel(adapter, ha->addr,
3293 rar_entries--,
68d480c4
AD		 3294 vfn);
3295 count++;
ff41f8dc
AD		 3296 }
3297 }
3298 /* write the addresses in reverse order to avoid write combining */
3299 for (; rar_entries > 0 ; rar_entries--) {
3300 wr32(E1000_RAH(rar_entries), 0);
3301 wr32(E1000_RAL(rar_entries), 0);
3302 }
3303 wrfl();
3304
68d480c4
AD		 3305 return count;
3306}
3307
3308/**
3309 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3310 * @netdev: network interface device structure
3311 *
3312 * The set_rx_mode entry point is called whenever the unicast or multicast
3313 * address lists or the network interface flags are updated. This routine is
3314 * responsible for configuring the hardware for proper unicast, multicast,
3315 * promiscuous mode, and all-multi behavior.
3316 **/
3317static void igb_set_rx_mode(struct net_device *netdev)
3318{
3319 struct igb_adapter *adapter = netdev_priv(netdev);
3320 struct e1000_hw *hw = &adapter->hw;
3321 unsigned int vfn = adapter->vfs_allocated_count;
3322 u32 rctl, vmolr = 0;
3323 int count;
3324
3325 /* Check for Promiscuous and All Multicast modes */
3326 rctl = rd32(E1000_RCTL);
3327
3328 /* clear the effected bits */
3329 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3330
3331 if (netdev->flags & IFF_PROMISC) {
3332 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3333 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3334 } else {
3335 if (netdev->flags & IFF_ALLMULTI) {
3336 rctl |= E1000_RCTL_MPE;
3337 vmolr |= E1000_VMOLR_MPME;
3338 } else {
3339 /*
3340 * Write addresses to the MTA, if the attempt fails
3341 * then we should just turn on promiscous mode so
3342 * that we can at least receive multicast traffic
3343 */
3344 count = igb_write_mc_addr_list(netdev);
3345 if (count < 0) {
3346 rctl |= E1000_RCTL_MPE;
3347 vmolr |= E1000_VMOLR_MPME;
3348 } else if (count) {
3349 vmolr |= E1000_VMOLR_ROMPE;
3350 }
3351 }
3352 /*
3353 * Write addresses to available RAR registers, if there is not
3354 * sufficient space to store all the addresses then enable
3355 * unicast promiscous mode
3356 */
3357 count = igb_write_uc_addr_list(netdev);
3358 if (count < 0) {
3359 rctl |= E1000_RCTL_UPE;
3360 vmolr |= E1000_VMOLR_ROPE;
3361 }
3362 rctl |= E1000_RCTL_VFE;
28fc06f5 3363 }
68d480c4 3364 wr32(E1000_RCTL, rctl);
28fc06f5 3365
68d480c4
AD		 3366 /*
3367 * In order to support SR-IOV and eventually VMDq it is necessary to set
3368 * the VMOLR to enable the appropriate modes. Without this workaround
3369 * we will have issues with VLAN tag stripping not being done for frames
3370 * that are only arriving because we are the default pool
3371 */
3372 if (hw->mac.type < e1000_82576)
28fc06f5 3373 return;
9d5c8243 3374
68d480c4
AD		 3375 vmolr |= rd32(E1000_VMOLR(vfn)) &
3376 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3377 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3378 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3379}
3380
13800469
GR		 3381static void igb_check_wvbr(struct igb_adapter *adapter)
3382{
3383 struct e1000_hw *hw = &adapter->hw;
3384 u32 wvbr = 0;
3385
3386 switch (hw->mac.type) {
3387 case e1000_82576:
3388 case e1000_i350:
3389 if (!(wvbr = rd32(E1000_WVBR)))
3390 return;
3391 break;
3392 default:
3393 break;
3394 }
3395
3396 adapter->wvbr |= wvbr;
3397}
3398
3399#define IGB_STAGGERED_QUEUE_OFFSET 8
3400
3401static void igb_spoof_check(struct igb_adapter *adapter)
3402{
3403 int j;
3404
3405 if (!adapter->wvbr)
3406 return;
3407
3408 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3409 if (adapter->wvbr & (1 << j) ||
3410 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3411 dev_warn(&adapter->pdev->dev,
3412 "Spoof event(s) detected on VF %d\n", j);
3413 adapter->wvbr &=
3414 ~((1 << j) |
3415 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3416 }
3417 }
3418}
3419
9d5c8243
AK		 3420/* Need to wait a few seconds after link up to get diagnostic information from
3421 * the phy */
3422static void igb_update_phy_info(unsigned long data)
3423{
3424 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3425 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3426}
3427
4d6b725e
AD		 3428/**
3429 * igb_has_link - check shared code for link and determine up/down
3430 * @adapter: pointer to driver private info
3431 **/
3145535a 3432bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3433{
3434 struct e1000_hw *hw = &adapter->hw;
3435 bool link_active = false;
3436 s32 ret_val = 0;
3437
3438 /* get_link_status is set on LSC (link status) interrupt or
3439 * rx sequence error interrupt. get_link_status will stay
3440 * false until the e1000_check_for_link establishes link
3441 * for copper adapters ONLY
3442 */
3443 switch (hw->phy.media_type) {
3444 case e1000_media_type_copper:
3445 if (hw->mac.get_link_status) {
3446 ret_val = hw->mac.ops.check_for_link(hw);
3447 link_active = !hw->mac.get_link_status;
3448 } else {
3449 link_active = true;
3450 }
3451 break;
4d6b725e
AD		 3452 case e1000_media_type_internal_serdes:
3453 ret_val = hw->mac.ops.check_for_link(hw);
3454 link_active = hw->mac.serdes_has_link;
3455 break;
3456 default:
3457 case e1000_media_type_unknown:
3458 break;
3459 }
3460
3461 return link_active;
3462}
3463
9d5c8243
AK		 3464/**
3465 * igb_watchdog - Timer Call-back
3466 * @data: pointer to adapter cast into an unsigned long
3467 **/
3468static void igb_watchdog(unsigned long data)
3469{
3470 struct igb_adapter *adapter = (struct igb_adapter *)data;
3471 /* Do the rest outside of interrupt context */
3472 schedule_work(&adapter->watchdog_task);
3473}
3474
3475static void igb_watchdog_task(struct work_struct *work)
3476{
3477 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3478 struct igb_adapter,
3479 watchdog_task);
9d5c8243 3480 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3481 struct net_device *netdev = adapter->netdev;
9d5c8243 3482 u32 link;
7a6ea550 3483 int i;
9d5c8243 3484
4d6b725e 3485 link = igb_has_link(adapter);
9d5c8243
AK		 3486 if (link) {
3487 if (!netif_carrier_ok(netdev)) {
3488 u32 ctrl;
330a6d6a
AD		 3489 hw->mac.ops.get_speed_and_duplex(hw,
3490 &adapter->link_speed,
3491 &adapter->link_duplex);
9d5c8243
AK		 3492
3493 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 3494 /* Links status message must follow this format */
3495 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 3496 "Flow Control: %s\n",
559e9c49
AD		 3497 netdev->name,
3498 adapter->link_speed,
3499 adapter->link_duplex == FULL_DUPLEX ?
9d5c8243 3500 "Full Duplex" : "Half Duplex",
559e9c49
AD		 3501 ((ctrl & E1000_CTRL_TFCE) &&
3502 (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
3503 ((ctrl & E1000_CTRL_RFCE) ? "RX" :
3504 ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None")));
9d5c8243 3505
d07f3e37 3506 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3507 adapter->tx_timeout_factor = 1;
3508 switch (adapter->link_speed) {
3509 case SPEED_10:
9d5c8243
AK		 3510 adapter->tx_timeout_factor = 14;
3511 break;
3512 case SPEED_100:
9d5c8243
AK		 3513 /* maybe add some timeout factor ? */
3514 break;
3515 }
3516
3517 netif_carrier_on(netdev);
9d5c8243 3518
4ae196df 3519 igb_ping_all_vfs(adapter);
17dc566c 3520 igb_check_vf_rate_limit(adapter);
4ae196df 3521
4b1a9877 3522 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3523 if (!test_bit(__IGB_DOWN, &adapter->state))
3524 mod_timer(&adapter->phy_info_timer,
3525 round_jiffies(jiffies + 2 * HZ));
3526 }
3527 } else {
3528 if (netif_carrier_ok(netdev)) {
3529 adapter->link_speed = 0;
3530 adapter->link_duplex = 0;
527d47c1
AD		 3531 /* Links status message must follow this format */
3532 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3533 netdev->name);
9d5c8243 3534 netif_carrier_off(netdev);
4b1a9877 3535
4ae196df
AD		 3536 igb_ping_all_vfs(adapter);
3537
4b1a9877 3538 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3539 if (!test_bit(__IGB_DOWN, &adapter->state))
3540 mod_timer(&adapter->phy_info_timer,
3541 round_jiffies(jiffies + 2 * HZ));
3542 }
3543 }
3544
12dcd86b
ED		 3545 spin_lock(&adapter->stats64_lock);
3546 igb_update_stats(adapter, &adapter->stats64);
3547 spin_unlock(&adapter->stats64_lock);
9d5c8243 3548
dbabb065 3549 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3550 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3551 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3552 /* We've lost link, so the controller stops DMA,
3553 * but we've got queued Tx work that's never going
3554 * to get done, so reset controller to flush Tx.
3555 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3556 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3557 adapter->tx_timeout_count++;
3558 schedule_work(&adapter->reset_task);
3559 /* return immediately since reset is imminent */
3560 return;
3561 }
9d5c8243 3562 }
9d5c8243 3563
dbabb065
AD		 3564 /* Force detection of hung controller every watchdog period */
3565 tx_ring->detect_tx_hung = true;
3566 }
f7ba205e 3567
9d5c8243 3568 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3569 if (adapter->msix_entries) {
047e0030
AD		 3570 u32 eics = 0;
3571 for (i = 0; i < adapter->num_q_vectors; i++) {
3572 struct igb_q_vector *q_vector = adapter->q_vector[i];
3573 eics |= q_vector->eims_value;
3574 }
7a6ea550
AD		 3575 wr32(E1000_EICS, eics);
3576 } else {
3577 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3578 }
9d5c8243 3579
13800469
GR		 3580 igb_spoof_check(adapter);
3581
9d5c8243
AK		 3582 /* Reset the timer */
3583 if (!test_bit(__IGB_DOWN, &adapter->state))
3584 mod_timer(&adapter->watchdog_timer,
3585 round_jiffies(jiffies + 2 * HZ));
3586}
3587
3588enum latency_range {
3589 lowest_latency = 0,
3590 low_latency = 1,
3591 bulk_latency = 2,
3592 latency_invalid = 255
3593};
3594
6eb5a7f1
AD		 3595/**
3596 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3597 *
3598 * Stores a new ITR value based on strictly on packet size. This
3599 * algorithm is less sophisticated than that used in igb_update_itr,
3600 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3601 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3602 * were determined based on theoretical maximum wire speed and testing
3603 * data, in order to minimize response time while increasing bulk
3604 * throughput.
3605 * This functionality is controlled by the InterruptThrottleRate module
3606 * parameter (see igb_param.c)
3607 * NOTE: This function is called only when operating in a multiqueue
3608 * receive environment.
047e0030 3609 * @q_vector: pointer to q_vector
6eb5a7f1 3610 **/
047e0030 3611static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3612{
047e0030 3613 int new_val = q_vector->itr_val;
6eb5a7f1 3614 int avg_wire_size = 0;
047e0030 3615 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b
ED		 3616 struct igb_ring *ring;
3617 unsigned int packets;
9d5c8243 3618
6eb5a7f1
AD		 3619 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3620 * ints/sec - ITR timer value of 120 ticks.
3621 */
3622 if (adapter->link_speed != SPEED_1000) {
047e0030 3623 new_val = 976;
6eb5a7f1 3624 goto set_itr_val;
9d5c8243 3625 }
047e0030 3626
12dcd86b
ED		 3627 ring = q_vector->rx_ring;
3628 if (ring) {
3629 packets = ACCESS_ONCE(ring->total_packets);
3630
3631 if (packets)
3632 avg_wire_size = ring->total_bytes / packets;
047e0030
AD		 3633 }
3634
12dcd86b
ED		 3635 ring = q_vector->tx_ring;
3636 if (ring) {
3637 packets = ACCESS_ONCE(ring->total_packets);
3638
3639 if (packets)
3640 avg_wire_size = max_t(u32, avg_wire_size,
3641 ring->total_bytes / packets);
047e0030
AD		 3642 }
3643
3644 /* if avg_wire_size isn't set no work was done */
3645 if (!avg_wire_size)
3646 goto clear_counts;
9d5c8243 3647
6eb5a7f1
AD		 3648 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3649 avg_wire_size += 24;
3650
3651 /* Don't starve jumbo frames */
3652 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3653
6eb5a7f1
AD		 3654 /* Give a little boost to mid-size frames */
3655 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3656 new_val = avg_wire_size / 3;
3657 else
3658 new_val = avg_wire_size / 2;
9d5c8243 3659
abe1c363
NN		 3660 /* when in itr mode 3 do not exceed 20K ints/sec */
3661 if (adapter->rx_itr_setting == 3 && new_val < 196)
3662 new_val = 196;
3663
6eb5a7f1 3664set_itr_val:
047e0030
AD		 3665 if (new_val != q_vector->itr_val) {
3666 q_vector->itr_val = new_val;
3667 q_vector->set_itr = 1;
9d5c8243 3668 }
6eb5a7f1 3669clear_counts:
047e0030
AD		 3670 if (q_vector->rx_ring) {
3671 q_vector->rx_ring->total_bytes = 0;
3672 q_vector->rx_ring->total_packets = 0;
3673 }
3674 if (q_vector->tx_ring) {
3675 q_vector->tx_ring->total_bytes = 0;
3676 q_vector->tx_ring->total_packets = 0;
3677 }
9d5c8243
AK		 3678}
3679
3680/**
3681 * igb_update_itr - update the dynamic ITR value based on statistics
3682 * Stores a new ITR value based on packets and byte
3683 * counts during the last interrupt. The advantage of per interrupt
3684 * computation is faster updates and more accurate ITR for the current
3685 * traffic pattern. Constants in this function were computed
3686 * based on theoretical maximum wire speed and thresholds were set based
3687 * on testing data as well as attempting to minimize response time
3688 * while increasing bulk throughput.
3689 * this functionality is controlled by the InterruptThrottleRate module
3690 * parameter (see igb_param.c)
3691 * NOTE: These calculations are only valid when operating in a single-
3692 * queue environment.
3693 * @adapter: pointer to adapter
047e0030 3694 * @itr_setting: current q_vector->itr_val
9d5c8243
AK		 3695 * @packets: the number of packets during this measurement interval
3696 * @bytes: the number of bytes during this measurement interval
3697 **/
3698static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
3699 int packets, int bytes)
3700{
3701 unsigned int retval = itr_setting;
3702
3703 if (packets == 0)
3704 goto update_itr_done;
3705
3706 switch (itr_setting) {
3707 case lowest_latency:
3708 /* handle TSO and jumbo frames */
3709 if (bytes/packets > 8000)
3710 retval = bulk_latency;
3711 else if ((packets < 5) && (bytes > 512))
3712 retval = low_latency;
3713 break;
3714 case low_latency: /* 50 usec aka 20000 ints/s */
3715 if (bytes > 10000) {
3716 /* this if handles the TSO accounting */
3717 if (bytes/packets > 8000) {
3718 retval = bulk_latency;
3719 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3720 retval = bulk_latency;
3721 } else if ((packets > 35)) {
3722 retval = lowest_latency;
3723 }
3724 } else if (bytes/packets > 2000) {
3725 retval = bulk_latency;
3726 } else if (packets <= 2 && bytes < 512) {
3727 retval = lowest_latency;
3728 }
3729 break;
3730 case bulk_latency: /* 250 usec aka 4000 ints/s */
3731 if (bytes > 25000) {
3732 if (packets > 35)
3733 retval = low_latency;
1e5c3d21 3734 } else if (bytes < 1500) {
9d5c8243
AK		 3735 retval = low_latency;
3736 }
3737 break;
3738 }
3739
3740update_itr_done:
3741 return retval;
3742}
3743
6eb5a7f1 3744static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243 3745{
047e0030 3746 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243 3747 u16 current_itr;
047e0030 3748 u32 new_itr = q_vector->itr_val;
9d5c8243
AK		 3749
3750 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3751 if (adapter->link_speed != SPEED_1000) {
3752 current_itr = 0;
3753 new_itr = 4000;
3754 goto set_itr_now;
3755 }
3756
3757 adapter->rx_itr = igb_update_itr(adapter,
3758 adapter->rx_itr,
3025a446
AD		 3759 q_vector->rx_ring->total_packets,
3760 q_vector->rx_ring->total_bytes);
9d5c8243 3761
047e0030
AD		 3762 adapter->tx_itr = igb_update_itr(adapter,
3763 adapter->tx_itr,
3025a446
AD		 3764 q_vector->tx_ring->total_packets,
3765 q_vector->tx_ring->total_bytes);
047e0030 3766 current_itr = max(adapter->rx_itr, adapter->tx_itr);
9d5c8243 3767
6eb5a7f1 3768 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4fc82adf 3769 if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 3770 current_itr = low_latency;
3771
9d5c8243
AK		 3772 switch (current_itr) {
3773 /* counts and packets in update_itr are dependent on these numbers */
3774 case lowest_latency:
78b1f607 3775 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 3776 break;
3777 case low_latency:
78b1f607 3778 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 3779 break;
3780 case bulk_latency:
78b1f607 3781 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 3782 break;
3783 default:
3784 break;
3785 }
3786
3787set_itr_now:
3025a446
AD		 3788 q_vector->rx_ring->total_bytes = 0;
3789 q_vector->rx_ring->total_packets = 0;
3790 q_vector->tx_ring->total_bytes = 0;
3791 q_vector->tx_ring->total_packets = 0;
6eb5a7f1 3792
047e0030 3793 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3794 /* this attempts to bias the interrupt rate towards Bulk
3795 * by adding intermediate steps when interrupt rate is
3796 * increasing */
047e0030
AD		 3797 new_itr = new_itr > q_vector->itr_val ?
3798 max((new_itr * q_vector->itr_val) /
3799 (new_itr + (q_vector->itr_val >> 2)),
3800 new_itr) :
9d5c8243
AK		 3801 new_itr;
3802 /* Don't write the value here; it resets the adapter's
3803 * internal timer, and causes us to delay far longer than
3804 * we should between interrupts. Instead, we write the ITR
3805 * value at the beginning of the next interrupt so the timing
3806 * ends up being correct.
3807 */
047e0030
AD		 3808 q_vector->itr_val = new_itr;
3809 q_vector->set_itr = 1;
9d5c8243 3810 }
9d5c8243
AK		 3811}
3812
9d5c8243
AK		 3813#define IGB_TX_FLAGS_CSUM 0x00000001
3814#define IGB_TX_FLAGS_VLAN 0x00000002
3815#define IGB_TX_FLAGS_TSO 0x00000004
3816#define IGB_TX_FLAGS_IPV4 0x00000008
cdfd01fc
AD		 3817#define IGB_TX_FLAGS_TSTAMP 0x00000010
3818#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
3819#define IGB_TX_FLAGS_VLAN_SHIFT 16
9d5c8243 3820
85ad76b2 3821static inline int igb_tso_adv(struct igb_ring *tx_ring,
9d5c8243
AK		 3822 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3823{
3824 struct e1000_adv_tx_context_desc *context_desc;
3825 unsigned int i;
3826 int err;
3827 struct igb_buffer *buffer_info;
3828 u32 info = 0, tu_cmd = 0;
91d4ee33
NN		 3829 u32 mss_l4len_idx;
3830 u8 l4len;
9d5c8243
AK		 3831
3832 if (skb_header_cloned(skb)) {
3833 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3834 if (err)
3835 return err;
3836 }
3837
3838 l4len = tcp_hdrlen(skb);
3839 *hdr_len += l4len;
3840
3841 if (skb->protocol == htons(ETH_P_IP)) {
3842 struct iphdr *iph = ip_hdr(skb);
3843 iph->tot_len = 0;
3844 iph->check = 0;
3845 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3846 iph->daddr, 0,
3847 IPPROTO_TCP,
3848 0);
8e1e8a47 3849 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 3850 ipv6_hdr(skb)->payload_len = 0;
3851 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3852 &ipv6_hdr(skb)->daddr,
3853 0, IPPROTO_TCP, 0);
3854 }
3855
3856 i = tx_ring->next_to_use;
3857
3858 buffer_info = &tx_ring->buffer_info[i];
3859 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3860 /* VLAN MACLEN IPLEN */
3861 if (tx_flags & IGB_TX_FLAGS_VLAN)
3862 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3863 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3864 *hdr_len += skb_network_offset(skb);
3865 info |= skb_network_header_len(skb);
3866 *hdr_len += skb_network_header_len(skb);
3867 context_desc->vlan_macip_lens = cpu_to_le32(info);
3868
3869 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3870 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3871
3872 if (skb->protocol == htons(ETH_P_IP))
3873 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3874 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3875
3876 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3877
3878 /* MSS L4LEN IDX */
3879 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3880 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3881
73cd78f1 3882 /* For 82575, context index must be unique per ring. */
85ad76b2
AD		 3883 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
3884 mss_l4len_idx |= tx_ring->reg_idx << 4;
9d5c8243
AK		 3885
3886 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3887 context_desc->seqnum_seed = 0;
3888
3889 buffer_info->time_stamp = jiffies;
0e014cb1 3890 buffer_info->next_to_watch = i;
9d5c8243
AK		 3891 buffer_info->dma = 0;
3892 i++;
3893 if (i == tx_ring->count)
3894 i = 0;
3895
3896 tx_ring->next_to_use = i;
3897
3898 return true;
3899}
3900
85ad76b2
AD		 3901static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring,
3902 struct sk_buff *skb, u32 tx_flags)
9d5c8243
AK		 3903{
3904 struct e1000_adv_tx_context_desc *context_desc;
59d71989 3905 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3906 struct igb_buffer *buffer_info;
3907 u32 info = 0, tu_cmd = 0;
80785298 3908 unsigned int i;
9d5c8243
AK		 3909
3910 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3911 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3912 i = tx_ring->next_to_use;
3913 buffer_info = &tx_ring->buffer_info[i];
3914 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3915
3916 if (tx_flags & IGB_TX_FLAGS_VLAN)
3917 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
cdfd01fc 3918
9d5c8243
AK		 3919 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3920 if (skb->ip_summed == CHECKSUM_PARTIAL)
3921 info |= skb_network_header_len(skb);
3922
3923 context_desc->vlan_macip_lens = cpu_to_le32(info);
3924
3925 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3926
3927 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3928 __be16 protocol;
3929
3930 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3931 const struct vlan_ethhdr *vhdr =
3932 (const struct vlan_ethhdr*)skb->data;
3933
3934 protocol = vhdr->h_vlan_encapsulated_proto;
3935 } else {
3936 protocol = skb->protocol;
3937 }
3938
3939 switch (protocol) {
09640e63 3940 case cpu_to_be16(ETH_P_IP):
9d5c8243 3941 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3942 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3943 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3944 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3945 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3946 break;
09640e63 3947 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3948 /* XXX what about other V6 headers?? */
3949 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3950 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3951 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3952 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3953 break;
3954 default:
3955 if (unlikely(net_ratelimit()))
59d71989 3956 dev_warn(dev,
44b0cda3
MW		 3957 "partial checksum but proto=%x!\n",
3958 skb->protocol);
3959 break;
3960 }
9d5c8243
AK		 3961 }
3962
3963 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3964 context_desc->seqnum_seed = 0;
85ad76b2 3965 if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)
7dfc16fa 3966 context_desc->mss_l4len_idx =
85ad76b2 3967 cpu_to_le32(tx_ring->reg_idx << 4);
9d5c8243
AK		 3968
3969 buffer_info->time_stamp = jiffies;
0e014cb1 3970 buffer_info->next_to_watch = i;
9d5c8243
AK		 3971 buffer_info->dma = 0;
3972
3973 i++;
3974 if (i == tx_ring->count)
3975 i = 0;
3976 tx_ring->next_to_use = i;
3977
3978 return true;
3979 }
9d5c8243
AK		 3980 return false;
3981}
3982
3983#define IGB_MAX_TXD_PWR 16
3984#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3985
80785298 3986static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb,
0e014cb1 3987 unsigned int first)
9d5c8243
AK		 3988{
3989 struct igb_buffer *buffer_info;
59d71989 3990 struct device *dev = tx_ring->dev;
2873957d 3991 unsigned int hlen = skb_headlen(skb);
9d5c8243
AK		 3992 unsigned int count = 0, i;
3993 unsigned int f;
2873957d 3994 u16 gso_segs = skb_shinfo(skb)->gso_segs ?: 1;
9d5c8243
AK		 3995
3996 i = tx_ring->next_to_use;
3997
3998 buffer_info = &tx_ring->buffer_info[i];
2873957d
NN		 3999 BUG_ON(hlen >= IGB_MAX_DATA_PER_TXD);
4000 buffer_info->length = hlen;
9d5c8243
AK		 4001 /* set time_stamp *before* dma to help avoid a possible race */
4002 buffer_info->time_stamp = jiffies;
0e014cb1 4003 buffer_info->next_to_watch = i;
2873957d 4004 buffer_info->dma = dma_map_single(dev, skb->data, hlen,
59d71989
AD		 4005 DMA_TO_DEVICE);
4006 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33 4007 goto dma_error;
9d5c8243
AK		 4008
4009 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2873957d
NN		 4010 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[f];
4011 unsigned int len = frag->size;
9d5c8243 4012
8581145f 4013 count++;
65689fef
AD		 4014 i++;
4015 if (i == tx_ring->count)
4016 i = 0;
4017
9d5c8243
AK		 4018 buffer_info = &tx_ring->buffer_info[i];
4019 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
4020 buffer_info->length = len;
4021 buffer_info->time_stamp = jiffies;
0e014cb1 4022 buffer_info->next_to_watch = i;
6366ad33 4023 buffer_info->mapped_as_page = true;
59d71989 4024 buffer_info->dma = dma_map_page(dev,
6366ad33
AD		 4025 frag->page,
4026 frag->page_offset,
4027 len,
59d71989
AD		 4028 DMA_TO_DEVICE);
4029 if (dma_mapping_error(dev, buffer_info->dma))
6366ad33
AD		 4030 goto dma_error;
4031
9d5c8243
AK		 4032 }
4033
9d5c8243 4034 tx_ring->buffer_info[i].skb = skb;
2244d07b 4035 tx_ring->buffer_info[i].tx_flags = skb_shinfo(skb)->tx_flags;
2873957d
NN		 4036 /* multiply data chunks by size of headers */
4037 tx_ring->buffer_info[i].bytecount = ((gso_segs - 1) * hlen) + skb->len;
4038 tx_ring->buffer_info[i].gso_segs = gso_segs;
0e014cb1 4039 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 4040
cdfd01fc 4041 return ++count;
6366ad33
AD		 4042
4043dma_error:
59d71989 4044 dev_err(dev, "TX DMA map failed\n");
6366ad33
AD		 4045
4046 /* clear timestamp and dma mappings for failed buffer_info mapping */
4047 buffer_info->dma = 0;
4048 buffer_info->time_stamp = 0;
4049 buffer_info->length = 0;
4050 buffer_info->next_to_watch = 0;
4051 buffer_info->mapped_as_page = false;
6366ad33
AD		 4052
4053 /* clear timestamp and dma mappings for remaining portion of packet */
a77ff709
NN		 4054 while (count--) {
4055 if (i == 0)
4056 i = tx_ring->count;
6366ad33 4057 i--;
6366ad33
AD		 4058 buffer_info = &tx_ring->buffer_info[i];
4059 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
4060 }
4061
4062 return 0;
9d5c8243
AK		 4063}
4064
85ad76b2 4065static inline void igb_tx_queue_adv(struct igb_ring *tx_ring,
91d4ee33 4066 u32 tx_flags, int count, u32 paylen,
9d5c8243
AK		 4067 u8 hdr_len)
4068{
cdfd01fc 4069 union e1000_adv_tx_desc *tx_desc;
9d5c8243
AK		 4070 struct igb_buffer *buffer_info;
4071 u32 olinfo_status = 0, cmd_type_len;
cdfd01fc 4072 unsigned int i = tx_ring->next_to_use;
9d5c8243
AK		 4073
4074 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
4075 E1000_ADVTXD_DCMD_DEXT);
4076
4077 if (tx_flags & IGB_TX_FLAGS_VLAN)
4078 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
4079
33af6bcc
PO		 4080 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4081 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
4082
9d5c8243
AK		 4083 if (tx_flags & IGB_TX_FLAGS_TSO) {
4084 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
4085
4086 /* insert tcp checksum */
4087 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4088
4089 /* insert ip checksum */
4090 if (tx_flags & IGB_TX_FLAGS_IPV4)
4091 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4092
4093 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
4094 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4095 }
4096
85ad76b2
AD		 4097 if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
4098 (tx_flags & (IGB_TX_FLAGS_CSUM |
4099 IGB_TX_FLAGS_TSO |
7dfc16fa 4100 IGB_TX_FLAGS_VLAN)))
85ad76b2 4101 olinfo_status |= tx_ring->reg_idx << 4;
9d5c8243
AK		 4102
4103 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
4104
cdfd01fc 4105 do {
9d5c8243
AK		 4106 buffer_info = &tx_ring->buffer_info[i];
4107 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4108 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
4109 tx_desc->read.cmd_type_len =
4110 cpu_to_le32(cmd_type_len | buffer_info->length);
4111 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
cdfd01fc 4112 count--;
9d5c8243
AK		 4113 i++;
4114 if (i == tx_ring->count)
4115 i = 0;
cdfd01fc 4116 } while (count > 0);
9d5c8243 4117
85ad76b2 4118 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
9d5c8243
AK		 4119 /* Force memory writes to complete before letting h/w
4120 * know there are new descriptors to fetch. (Only
4121 * applicable for weak-ordered memory model archs,
4122 * such as IA-64). */
4123 wmb();
4124
4125 tx_ring->next_to_use = i;
fce99e34 4126 writel(i, tx_ring->tail);
9d5c8243
AK		 4127 /* we need this if more than one processor can write to our tail
4128 * at a time, it syncronizes IO on IA64/Altix systems */
4129 mmiowb();
4130}
4131
e694e964 4132static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4133{
e694e964
AD		 4134 struct net_device *netdev = tx_ring->netdev;
4135
661086df 4136 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4137
9d5c8243
AK		 4138 /* Herbert's original patch had:
4139 * smp_mb__after_netif_stop_queue();
4140 * but since that doesn't exist yet, just open code it. */
4141 smp_mb();
4142
4143 /* We need to check again in a case another CPU has just
4144 * made room available. */
c493ea45 4145 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4146 return -EBUSY;
4147
4148 /* A reprieve! */
661086df 4149 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4150
4151 u64_stats_update_begin(&tx_ring->tx_syncp2);
4152 tx_ring->tx_stats.restart_queue2++;
4153 u64_stats_update_end(&tx_ring->tx_syncp2);
4154
9d5c8243
AK		 4155 return 0;
4156}
4157
717ba089 4158static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size)
9d5c8243 4159{
c493ea45 4160 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4161 return 0;
e694e964 4162 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4163}
4164
b1a436c3
AD		 4165netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
4166 struct igb_ring *tx_ring)
9d5c8243 4167{
cdfd01fc 4168 int tso = 0, count;
91d4ee33
NN		 4169 u32 tx_flags = 0;
4170 u16 first;
4171 u8 hdr_len = 0;
9d5c8243 4172
9d5c8243
AK		 4173 /* need: 1 descriptor per page,
4174 * + 2 desc gap to keep tail from touching head,
4175 * + 1 desc for skb->data,
4176 * + 1 desc for context descriptor,
4177 * otherwise try next time */
e694e964 4178 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4179 /* this is a hard error */
9d5c8243
AK		 4180 return NETDEV_TX_BUSY;
4181 }
33af6bcc 4182
2244d07b
OH		 4183 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4184 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4185 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4186 }
9d5c8243 4187
eab6d18d 4188 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4189 tx_flags |= IGB_TX_FLAGS_VLAN;
4190 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4191 }
4192
661086df
PWJ		 4193 if (skb->protocol == htons(ETH_P_IP))
4194 tx_flags |= IGB_TX_FLAGS_IPV4;
4195
0e014cb1 4196 first = tx_ring->next_to_use;
85ad76b2
AD		 4197 if (skb_is_gso(skb)) {
4198 tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len);
cdfd01fc 4199
85ad76b2
AD		 4200 if (tso < 0) {
4201 dev_kfree_skb_any(skb);
4202 return NETDEV_TX_OK;
4203 }
9d5c8243
AK		 4204 }
4205
4206 if (tso)
4207 tx_flags |= IGB_TX_FLAGS_TSO;
85ad76b2 4208 else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) &&
bc1cbd34
AD		 4209 (skb->ip_summed == CHECKSUM_PARTIAL))
4210 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 4211
65689fef 4212 /*
cdfd01fc 4213 * count reflects descriptors mapped, if 0 or less then mapping error
65689fef
AD		 4214 * has occured and we need to rewind the descriptor queue
4215 */
80785298 4216 count = igb_tx_map_adv(tx_ring, skb, first);
6366ad33 4217 if (!count) {
65689fef
AD		 4218 dev_kfree_skb_any(skb);
4219 tx_ring->buffer_info[first].time_stamp = 0;
4220 tx_ring->next_to_use = first;
85ad76b2 4221 return NETDEV_TX_OK;
65689fef 4222 }
9d5c8243 4223
85ad76b2
AD		 4224 igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len);
4225
4226 /* Make sure there is space in the ring for the next send. */
e694e964 4227 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4228
9d5c8243
AK		 4229 return NETDEV_TX_OK;
4230}
4231
3b29a56d
SH		 4232static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
4233 struct net_device *netdev)
9d5c8243
AK		 4234{
4235 struct igb_adapter *adapter = netdev_priv(netdev);
661086df 4236 struct igb_ring *tx_ring;
661086df 4237 int r_idx = 0;
b1a436c3
AD		 4238
4239 if (test_bit(__IGB_DOWN, &adapter->state)) {
4240 dev_kfree_skb_any(skb);
4241 return NETDEV_TX_OK;
4242 }
4243
4244 if (skb->len <= 0) {
4245 dev_kfree_skb_any(skb);
4246 return NETDEV_TX_OK;
4247 }
4248
1bfaf07b 4249 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 4250 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 4251
4252 /* This goes back to the question of how to logically map a tx queue
4253 * to a flow. Right now, performance is impacted slightly negatively
4254 * if using multiple tx queues. If the stack breaks away from a
4255 * single qdisc implementation, we can look at this again. */
e694e964 4256 return igb_xmit_frame_ring_adv(skb, tx_ring);
9d5c8243
AK		 4257}
4258
4259/**
4260 * igb_tx_timeout - Respond to a Tx Hang
4261 * @netdev: network interface device structure
4262 **/
4263static void igb_tx_timeout(struct net_device *netdev)
4264{
4265 struct igb_adapter *adapter = netdev_priv(netdev);
4266 struct e1000_hw *hw = &adapter->hw;
4267
4268 /* Do the reset outside of interrupt context */
4269 adapter->tx_timeout_count++;
f7ba205e 4270
55cac248
AD		 4271 if (hw->mac.type == e1000_82580)
4272 hw->dev_spec._82575.global_device_reset = true;
4273
9d5c8243 4274 schedule_work(&adapter->reset_task);
265de409
AD		 4275 wr32(E1000_EICS,
4276 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4277}
4278
4279static void igb_reset_task(struct work_struct *work)
4280{
4281 struct igb_adapter *adapter;
4282 adapter = container_of(work, struct igb_adapter, reset_task);
4283
c97ec42a
TI		 4284 igb_dump(adapter);
4285 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4286 igb_reinit_locked(adapter);
4287}
4288
4289/**
12dcd86b 4290 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4291 * @netdev: network interface device structure
12dcd86b 4292 * @stats: rtnl_link_stats64 pointer
9d5c8243 4293 *
9d5c8243 4294 **/
12dcd86b
ED		 4295static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4296 struct rtnl_link_stats64 *stats)
9d5c8243 4297{
12dcd86b
ED		 4298 struct igb_adapter *adapter = netdev_priv(netdev);
4299
4300 spin_lock(&adapter->stats64_lock);
4301 igb_update_stats(adapter, &adapter->stats64);
4302 memcpy(stats, &adapter->stats64, sizeof(*stats));
4303 spin_unlock(&adapter->stats64_lock);
4304
4305 return stats;
9d5c8243
AK		 4306}
4307
4308/**
4309 * igb_change_mtu - Change the Maximum Transfer Unit
4310 * @netdev: network interface device structure
4311 * @new_mtu: new value for maximum frame size
4312 *
4313 * Returns 0 on success, negative on failure
4314 **/
4315static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4316{
4317 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4318 struct pci_dev *pdev = adapter->pdev;
9d5c8243 4319 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4c844851 4320 u32 rx_buffer_len, i;
9d5c8243 4321
c809d227 4322 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4323 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4324 return -EINVAL;
4325 }
4326
9d5c8243 4327 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4328 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4329 return -EINVAL;
4330 }
4331
4332 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4333 msleep(1);
73cd78f1 4334
9d5c8243
AK		 4335 /* igb_down has a dependency on max_frame_size */
4336 adapter->max_frame_size = max_frame;
559e9c49 4337
9d5c8243
AK		 4338 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
4339 * means we reserve 2 more, this pushes us to allocate from the next
4340 * larger slab size.
4341 * i.e. RXBUFFER_2048 --> size-4096 slab
4342 */
4343
757b77e2
NN		 4344 if (adapter->hw.mac.type == e1000_82580)
4345 max_frame += IGB_TS_HDR_LEN;
4346
7d95b717 4347 if (max_frame <= IGB_RXBUFFER_1024)
4c844851 4348 rx_buffer_len = IGB_RXBUFFER_1024;
6ec43fe6 4349 else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)
4c844851 4350 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
6ec43fe6 4351 else
4c844851
AD		 4352 rx_buffer_len = IGB_RXBUFFER_128;
4353
757b77e2
NN		 4354 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN + IGB_TS_HDR_LEN) ||
4355 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN))
4356 rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE + IGB_TS_HDR_LEN;
4357
4358 if ((adapter->hw.mac.type == e1000_82580) &&
4359 (rx_buffer_len == IGB_RXBUFFER_128))
4360 rx_buffer_len += IGB_RXBUFFER_64;
4361
4c844851
AD		 4362 if (netif_running(netdev))
4363 igb_down(adapter);
9d5c8243 4364
090b1795 4365 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4366 netdev->mtu, new_mtu);
4367 netdev->mtu = new_mtu;
4368
4c844851 4369 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 4370 adapter->rx_ring[i]->rx_buffer_len = rx_buffer_len;
4c844851 4371
9d5c8243
AK		 4372 if (netif_running(netdev))
4373 igb_up(adapter);
4374 else
4375 igb_reset(adapter);
4376
4377 clear_bit(__IGB_RESETTING, &adapter->state);
4378
4379 return 0;
4380}
4381
4382/**
4383 * igb_update_stats - Update the board statistics counters
4384 * @adapter: board private structure
4385 **/
4386
12dcd86b
ED		 4387void igb_update_stats(struct igb_adapter *adapter,
4388 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4389{
4390 struct e1000_hw *hw = &adapter->hw;
4391 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4392 u32 reg, mpc;
9d5c8243 4393 u16 phy_tmp;
3f9c0164
AD		 4394 int i;
4395 u64 bytes, packets;
12dcd86b
ED		 4396 unsigned int start;
4397 u64 _bytes, _packets;
9d5c8243
AK		 4398
4399#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4400
4401 /*
4402 * Prevent stats update while adapter is being reset, or if the pci
4403 * connection is down.
4404 */
4405 if (adapter->link_speed == 0)
4406 return;
4407 if (pci_channel_offline(pdev))
4408 return;
4409
3f9c0164
AD		 4410 bytes = 0;
4411 packets = 0;
4412 for (i = 0; i < adapter->num_rx_queues; i++) {
4413 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446 4414 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4415
3025a446 4416 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4417 net_stats->rx_fifo_errors += rqdpc_tmp;
12dcd86b
ED		 4418
4419 do {
4420 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4421 _bytes = ring->rx_stats.bytes;
4422 _packets = ring->rx_stats.packets;
4423 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4424 bytes += _bytes;
4425 packets += _packets;
3f9c0164
AD		 4426 }
4427
128e45eb
AD		 4428 net_stats->rx_bytes = bytes;
4429 net_stats->rx_packets = packets;
3f9c0164
AD		 4430
4431 bytes = 0;
4432 packets = 0;
4433 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4434 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4435 do {
4436 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4437 _bytes = ring->tx_stats.bytes;
4438 _packets = ring->tx_stats.packets;
4439 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4440 bytes += _bytes;
4441 packets += _packets;
3f9c0164 4442 }
128e45eb
AD		 4443 net_stats->tx_bytes = bytes;
4444 net_stats->tx_packets = packets;
3f9c0164
AD		 4445
4446 /* read stats registers */
9d5c8243
AK		 4447 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4448 adapter->stats.gprc += rd32(E1000_GPRC);
4449 adapter->stats.gorc += rd32(E1000_GORCL);
4450 rd32(E1000_GORCH); /* clear GORCL */
4451 adapter->stats.bprc += rd32(E1000_BPRC);
4452 adapter->stats.mprc += rd32(E1000_MPRC);
4453 adapter->stats.roc += rd32(E1000_ROC);
4454
4455 adapter->stats.prc64 += rd32(E1000_PRC64);
4456 adapter->stats.prc127 += rd32(E1000_PRC127);
4457 adapter->stats.prc255 += rd32(E1000_PRC255);
4458 adapter->stats.prc511 += rd32(E1000_PRC511);
4459 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4460 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4461 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4462 adapter->stats.sec += rd32(E1000_SEC);
4463
fa3d9a6d
MW		 4464 mpc = rd32(E1000_MPC);
4465 adapter->stats.mpc += mpc;
4466 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4467 adapter->stats.scc += rd32(E1000_SCC);
4468 adapter->stats.ecol += rd32(E1000_ECOL);
4469 adapter->stats.mcc += rd32(E1000_MCC);
4470 adapter->stats.latecol += rd32(E1000_LATECOL);
4471 adapter->stats.dc += rd32(E1000_DC);
4472 adapter->stats.rlec += rd32(E1000_RLEC);
4473 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4474 adapter->stats.xontxc += rd32(E1000_XONTXC);
4475 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4476 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4477 adapter->stats.fcruc += rd32(E1000_FCRUC);
4478 adapter->stats.gptc += rd32(E1000_GPTC);
4479 adapter->stats.gotc += rd32(E1000_GOTCL);
4480 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4481 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4482 adapter->stats.ruc += rd32(E1000_RUC);
4483 adapter->stats.rfc += rd32(E1000_RFC);
4484 adapter->stats.rjc += rd32(E1000_RJC);
4485 adapter->stats.tor += rd32(E1000_TORH);
4486 adapter->stats.tot += rd32(E1000_TOTH);
4487 adapter->stats.tpr += rd32(E1000_TPR);
4488
4489 adapter->stats.ptc64 += rd32(E1000_PTC64);
4490 adapter->stats.ptc127 += rd32(E1000_PTC127);
4491 adapter->stats.ptc255 += rd32(E1000_PTC255);
4492 adapter->stats.ptc511 += rd32(E1000_PTC511);
4493 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4494 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4495
4496 adapter->stats.mptc += rd32(E1000_MPTC);
4497 adapter->stats.bptc += rd32(E1000_BPTC);
4498
2d0b0f69
NN		 4499 adapter->stats.tpt += rd32(E1000_TPT);
4500 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4501
4502 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4503 /* read internal phy specific stats */
4504 reg = rd32(E1000_CTRL_EXT);
4505 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4506 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4507 adapter->stats.tncrs += rd32(E1000_TNCRS);
4508 }
4509
9d5c8243
AK		 4510 adapter->stats.tsctc += rd32(E1000_TSCTC);
4511 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4512
4513 adapter->stats.iac += rd32(E1000_IAC);
4514 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4515 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4516 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4517 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4518 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4519 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4520 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4521 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4522
4523 /* Fill out the OS statistics structure */
128e45eb
AD		 4524 net_stats->multicast = adapter->stats.mprc;
4525 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4526
4527 /* Rx Errors */
4528
4529 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4530 * our own version based on RUC and ROC */
128e45eb 4531 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4532 adapter->stats.crcerrs + adapter->stats.algnerrc +
4533 adapter->stats.ruc + adapter->stats.roc +
4534 adapter->stats.cexterr;
128e45eb
AD		 4535 net_stats->rx_length_errors = adapter->stats.ruc +
4536 adapter->stats.roc;
4537 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4538 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4539 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4540
4541 /* Tx Errors */
128e45eb
AD		 4542 net_stats->tx_errors = adapter->stats.ecol +
4543 adapter->stats.latecol;
4544 net_stats->tx_aborted_errors = adapter->stats.ecol;
4545 net_stats->tx_window_errors = adapter->stats.latecol;
4546 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4547
4548 /* Tx Dropped needs to be maintained elsewhere */
4549
4550 /* Phy Stats */
4551 if (hw->phy.media_type == e1000_media_type_copper) {
4552 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4553 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4554 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4555 adapter->phy_stats.idle_errors += phy_tmp;
4556 }
4557 }
4558
4559 /* Management Stats */
4560 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4561 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4562 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4563
4564 /* OS2BMC Stats */
4565 reg = rd32(E1000_MANC);
4566 if (reg & E1000_MANC_EN_BMC2OS) {
4567 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4568 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4569 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4570 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4571 }
9d5c8243
AK		 4572}
4573
9d5c8243
AK		 4574static irqreturn_t igb_msix_other(int irq, void *data)
4575{
047e0030 4576 struct igb_adapter *adapter = data;
9d5c8243 4577 struct e1000_hw *hw = &adapter->hw;
844290e5 4578 u32 icr = rd32(E1000_ICR);
844290e5 4579 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4580
7f081d40
AD		 4581 if (icr & E1000_ICR_DRSTA)
4582 schedule_work(&adapter->reset_task);
4583
047e0030 4584 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4585 /* HW is reporting DMA is out of sync */
4586 adapter->stats.doosync++;
13800469
GR		 4587 /* The DMA Out of Sync is also indication of a spoof event
4588 * in IOV mode. Check the Wrong VM Behavior register to
4589 * see if it is really a spoof event. */
4590 igb_check_wvbr(adapter);
dda0e083 4591 }
eebbbdba 4592
4ae196df
AD		 4593 /* Check for a mailbox event */
4594 if (icr & E1000_ICR_VMMB)
4595 igb_msg_task(adapter);
4596
4597 if (icr & E1000_ICR_LSC) {
4598 hw->mac.get_link_status = 1;
4599 /* guard against interrupt when we're going down */
4600 if (!test_bit(__IGB_DOWN, &adapter->state))
4601 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4602 }
4603
25568a53
AD		 4604 if (adapter->vfs_allocated_count)
4605 wr32(E1000_IMS, E1000_IMS_LSC |
4606 E1000_IMS_VMMB |
4607 E1000_IMS_DOUTSYNC);
4608 else
4609 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 4610 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4611
4612 return IRQ_HANDLED;
4613}
4614
047e0030 4615static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4616{
26b39276 4617 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4618 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4619
047e0030
AD		 4620 if (!q_vector->set_itr)
4621 return;
73cd78f1 4622
047e0030
AD		 4623 if (!itr_val)
4624 itr_val = 0x4;
661086df 4625
26b39276
AD		 4626 if (adapter->hw.mac.type == e1000_82575)
4627 itr_val |= itr_val << 16;
661086df 4628 else
047e0030 4629 itr_val |= 0x8000000;
661086df 4630
047e0030
AD		 4631 writel(itr_val, q_vector->itr_register);
4632 q_vector->set_itr = 0;
6eb5a7f1
AD		 4633}
4634
047e0030 4635static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4636{
047e0030 4637 struct igb_q_vector *q_vector = data;
9d5c8243 4638
047e0030
AD		 4639 /* Write the ITR value calculated from the previous interrupt. */
4640 igb_write_itr(q_vector);
9d5c8243 4641
047e0030 4642 napi_schedule(&q_vector->napi);
844290e5 4643
047e0030 4644 return IRQ_HANDLED;
fe4506b6
JC		 4645}
4646
421e02f0 4647#ifdef CONFIG_IGB_DCA
047e0030 4648static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4649{
047e0030 4650 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4651 struct e1000_hw *hw = &adapter->hw;
4652 int cpu = get_cpu();
fe4506b6 4653
047e0030
AD		 4654 if (q_vector->cpu == cpu)
4655 goto out_no_update;
4656
4657 if (q_vector->tx_ring) {
4658 int q = q_vector->tx_ring->reg_idx;
4659 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4660 if (hw->mac.type == e1000_82575) {
4661 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4662 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4663 } else {
047e0030
AD		 4664 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4665 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4666 E1000_DCA_TXCTRL_CPUID_SHIFT;
4667 }
4668 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4669 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4670 }
4671 if (q_vector->rx_ring) {
4672 int q = q_vector->rx_ring->reg_idx;
4673 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4674 if (hw->mac.type == e1000_82575) {
2d064c06 4675 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4676 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4677 } else {
4678 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4679 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4680 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4681 }
fe4506b6
JC		 4682 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4683 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4684 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4685 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4686 }
047e0030
AD		 4687 q_vector->cpu = cpu;
4688out_no_update:
fe4506b6
JC		 4689 put_cpu();
4690}
4691
4692static void igb_setup_dca(struct igb_adapter *adapter)
4693{
7e0e99ef 4694 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4695 int i;
4696
7dfc16fa 4697 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4698 return;
4699
7e0e99ef
AD		 4700 /* Always use CB2 mode, difference is masked in the CB driver. */
4701 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4702
047e0030 4703 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4704 adapter->q_vector[i]->cpu = -1;
4705 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4706 }
4707}
4708
4709static int __igb_notify_dca(struct device *dev, void *data)
4710{
4711 struct net_device *netdev = dev_get_drvdata(dev);
4712 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4713 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4714 struct e1000_hw *hw = &adapter->hw;
4715 unsigned long event = *(unsigned long *)data;
4716
4717 switch (event) {
4718 case DCA_PROVIDER_ADD:
4719 /* if already enabled, don't do it again */
7dfc16fa 4720 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4721 break;
fe4506b6 4722 if (dca_add_requester(dev) == 0) {
bbd98fe4 4723 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4724 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4725 igb_setup_dca(adapter);
4726 break;
4727 }
4728 /* Fall Through since DCA is disabled. */
4729 case DCA_PROVIDER_REMOVE:
7dfc16fa 4730 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4731 /* without this a class_device is left
047e0030 4732 * hanging around in the sysfs model */
fe4506b6 4733 dca_remove_requester(dev);
090b1795 4734 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4735 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4736 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4737 }
4738 break;
4739 }
bbd98fe4 4740
fe4506b6 4741 return 0;
9d5c8243
AK		 4742}
4743
fe4506b6
JC		 4744static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4745 void *p)
4746{
4747 int ret_val;
4748
4749 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4750 __igb_notify_dca);
4751
4752 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4753}
421e02f0 4754#endif /* CONFIG_IGB_DCA */
9d5c8243 4755
4ae196df
AD		 4756static void igb_ping_all_vfs(struct igb_adapter *adapter)
4757{
4758 struct e1000_hw *hw = &adapter->hw;
4759 u32 ping;
4760 int i;
4761
4762 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4763 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 4764 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 4765 ping |= E1000_VT_MSGTYPE_CTS;
4766 igb_write_mbx(hw, &ping, 1, i);
4767 }
4768}
4769
7d5753f0
AD		 4770static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4771{
4772 struct e1000_hw *hw = &adapter->hw;
4773 u32 vmolr = rd32(E1000_VMOLR(vf));
4774 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4775
d85b9004 4776 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 4777 IGB_VF_FLAG_MULTI_PROMISC);
4778 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4779
4780 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
4781 vmolr |= E1000_VMOLR_MPME;
d85b9004 4782 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 4783 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
4784 } else {
4785 /*
4786 * if we have hashes and we are clearing a multicast promisc
4787 * flag we need to write the hashes to the MTA as this step
4788 * was previously skipped
4789 */
4790 if (vf_data->num_vf_mc_hashes > 30) {
4791 vmolr |= E1000_VMOLR_MPME;
4792 } else if (vf_data->num_vf_mc_hashes) {
4793 int j;
4794 vmolr |= E1000_VMOLR_ROMPE;
4795 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4796 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4797 }
4798 }
4799
4800 wr32(E1000_VMOLR(vf), vmolr);
4801
4802 /* there are flags left unprocessed, likely not supported */
4803 if (*msgbuf & E1000_VT_MSGINFO_MASK)
4804 return -EINVAL;
4805
4806 return 0;
4807
4808}
4809
4ae196df
AD		 4810static int igb_set_vf_multicasts(struct igb_adapter *adapter,
4811 u32 *msgbuf, u32 vf)
4812{
4813 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4814 u16 *hash_list = (u16 *)&msgbuf[1];
4815 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4816 int i;
4817
7d5753f0 4818 /* salt away the number of multicast addresses assigned
4ae196df
AD		 4819 * to this VF for later use to restore when the PF multi cast
4820 * list changes
4821 */
4822 vf_data->num_vf_mc_hashes = n;
4823
7d5753f0
AD		 4824 /* only up to 30 hash values supported */
4825 if (n > 30)
4826 n = 30;
4827
4828 /* store the hashes for later use */
4ae196df 4829 for (i = 0; i < n; i++)
a419aef8 4830 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 4831
4832 /* Flush and reset the mta with the new values */
ff41f8dc 4833 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 4834
4835 return 0;
4836}
4837
4838static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
4839{
4840 struct e1000_hw *hw = &adapter->hw;
4841 struct vf_data_storage *vf_data;
4842 int i, j;
4843
4844 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 4845 u32 vmolr = rd32(E1000_VMOLR(i));
4846 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
4847
4ae196df 4848 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 4849
4850 if ((vf_data->num_vf_mc_hashes > 30) ||
4851 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
4852 vmolr |= E1000_VMOLR_MPME;
4853 } else if (vf_data->num_vf_mc_hashes) {
4854 vmolr |= E1000_VMOLR_ROMPE;
4855 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4856 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
4857 }
4858 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 4859 }
4860}
4861
4862static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
4863{
4864 struct e1000_hw *hw = &adapter->hw;
4865 u32 pool_mask, reg, vid;
4866 int i;
4867
4868 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4869
4870 /* Find the vlan filter for this id */
4871 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4872 reg = rd32(E1000_VLVF(i));
4873
4874 /* remove the vf from the pool */
4875 reg &= ~pool_mask;
4876
4877 /* if pool is empty then remove entry from vfta */
4878 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4879 (reg & E1000_VLVF_VLANID_ENABLE)) {
4880 reg = 0;
4881 vid = reg & E1000_VLVF_VLANID_MASK;
4882 igb_vfta_set(hw, vid, false);
4883 }
4884
4885 wr32(E1000_VLVF(i), reg);
4886 }
ae641bdc
AD		 4887
4888 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 4889}
4890
4891static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4892{
4893 struct e1000_hw *hw = &adapter->hw;
4894 u32 reg, i;
4895
51466239
AD		 4896 /* The vlvf table only exists on 82576 hardware and newer */
4897 if (hw->mac.type < e1000_82576)
4898 return -1;
4899
4900 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 4901 if (!adapter->vfs_allocated_count)
4902 return -1;
4903
4904 /* Find the vlan filter for this id */
4905 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4906 reg = rd32(E1000_VLVF(i));
4907 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4908 vid == (reg & E1000_VLVF_VLANID_MASK))
4909 break;
4910 }
4911
4912 if (add) {
4913 if (i == E1000_VLVF_ARRAY_SIZE) {
4914 /* Did not find a matching VLAN ID entry that was
4915 * enabled. Search for a free filter entry, i.e.
4916 * one without the enable bit set
4917 */
4918 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4919 reg = rd32(E1000_VLVF(i));
4920 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4921 break;
4922 }
4923 }
4924 if (i < E1000_VLVF_ARRAY_SIZE) {
4925 /* Found an enabled/available entry */
4926 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4927
4928 /* if !enabled we need to set this up in vfta */
4929 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 4930 /* add VID to filter table */
4931 igb_vfta_set(hw, vid, true);
4ae196df
AD		 4932 reg |= E1000_VLVF_VLANID_ENABLE;
4933 }
cad6d05f
AD		 4934 reg &= ~E1000_VLVF_VLANID_MASK;
4935 reg |= vid;
4ae196df 4936 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4937
4938 /* do not modify RLPML for PF devices */
4939 if (vf >= adapter->vfs_allocated_count)
4940 return 0;
4941
4942 if (!adapter->vf_data[vf].vlans_enabled) {
4943 u32 size;
4944 reg = rd32(E1000_VMOLR(vf));
4945 size = reg & E1000_VMOLR_RLPML_MASK;
4946 size += 4;
4947 reg &= ~E1000_VMOLR_RLPML_MASK;
4948 reg |= size;
4949 wr32(E1000_VMOLR(vf), reg);
4950 }
ae641bdc 4951
51466239 4952 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 4953 return 0;
4954 }
4955 } else {
4956 if (i < E1000_VLVF_ARRAY_SIZE) {
4957 /* remove vf from the pool */
4958 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4959 /* if pool is empty then remove entry from vfta */
4960 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4961 reg = 0;
4962 igb_vfta_set(hw, vid, false);
4963 }
4964 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 4965
4966 /* do not modify RLPML for PF devices */
4967 if (vf >= adapter->vfs_allocated_count)
4968 return 0;
4969
4970 adapter->vf_data[vf].vlans_enabled--;
4971 if (!adapter->vf_data[vf].vlans_enabled) {
4972 u32 size;
4973 reg = rd32(E1000_VMOLR(vf));
4974 size = reg & E1000_VMOLR_RLPML_MASK;
4975 size -= 4;
4976 reg &= ~E1000_VMOLR_RLPML_MASK;
4977 reg |= size;
4978 wr32(E1000_VMOLR(vf), reg);
4979 }
4ae196df
AD		 4980 }
4981 }
8151d294
WM		 4982 return 0;
4983}
4984
4985static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4986{
4987 struct e1000_hw *hw = &adapter->hw;
4988
4989 if (vid)
4990 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
4991 else
4992 wr32(E1000_VMVIR(vf), 0);
4993}
4994
4995static int igb_ndo_set_vf_vlan(struct net_device *netdev,
4996 int vf, u16 vlan, u8 qos)
4997{
4998 int err = 0;
4999 struct igb_adapter *adapter = netdev_priv(netdev);
5000
5001 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5002 return -EINVAL;
5003 if (vlan || qos) {
5004 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5005 if (err)
5006 goto out;
5007 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5008 igb_set_vmolr(adapter, vf, !vlan);
5009 adapter->vf_data[vf].pf_vlan = vlan;
5010 adapter->vf_data[vf].pf_qos = qos;
5011 dev_info(&adapter->pdev->dev,
5012 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5013 if (test_bit(__IGB_DOWN, &adapter->state)) {
5014 dev_warn(&adapter->pdev->dev,
5015 "The VF VLAN has been set,"
5016 " but the PF device is not up.\n");
5017 dev_warn(&adapter->pdev->dev,
5018 "Bring the PF device up before"
5019 " attempting to use the VF device.\n");
5020 }
5021 } else {
5022 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5023 false, vf);
5024 igb_set_vmvir(adapter, vlan, vf);
5025 igb_set_vmolr(adapter, vf, true);
5026 adapter->vf_data[vf].pf_vlan = 0;
5027 adapter->vf_data[vf].pf_qos = 0;
5028 }
5029out:
5030 return err;
4ae196df
AD		 5031}
5032
5033static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5034{
5035 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5036 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5037
5038 return igb_vlvf_set(adapter, vid, add, vf);
5039}
5040
f2ca0dbe 5041static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5042{
8fa7e0f7
GR		 5043 /* clear flags - except flag that indicates PF has set the MAC */
5044 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5045 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5046
5047 /* reset offloads to defaults */
8151d294 5048 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5049
5050 /* reset vlans for device */
5051 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5052 if (adapter->vf_data[vf].pf_vlan)
5053 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5054 adapter->vf_data[vf].pf_vlan,
5055 adapter->vf_data[vf].pf_qos);
5056 else
5057 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5058
5059 /* reset multicast table array for vf */
5060 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5061
5062 /* Flush and reset the mta with the new values */
ff41f8dc 5063 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5064}
5065
f2ca0dbe
AD		 5066static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5067{
5068 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5069
5070 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 5071 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5072 random_ether_addr(vf_mac);
f2ca0dbe
AD		 5073
5074 /* process remaining reset events */
5075 igb_vf_reset(adapter, vf);
5076}
5077
5078static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5079{
5080 struct e1000_hw *hw = &adapter->hw;
5081 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5082 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5083 u32 reg, msgbuf[3];
5084 u8 *addr = (u8 *)(&msgbuf[1]);
5085
5086 /* process all the same items cleared in a function level reset */
f2ca0dbe 5087 igb_vf_reset(adapter, vf);
4ae196df
AD		 5088
5089 /* set vf mac address */
26ad9178 5090 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5091
5092 /* enable transmit and receive for vf */
5093 reg = rd32(E1000_VFTE);
5094 wr32(E1000_VFTE, reg | (1 << vf));
5095 reg = rd32(E1000_VFRE);
5096 wr32(E1000_VFRE, reg | (1 << vf));
5097
8fa7e0f7 5098 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5099
5100 /* reply to reset with ack and vf mac address */
5101 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5102 memcpy(addr, vf_mac, 6);
5103 igb_write_mbx(hw, msgbuf, 3, vf);
5104}
5105
5106static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5107{
de42edde
GR		 5108 /*
5109 * The VF MAC Address is stored in a packed array of bytes
5110 * starting at the second 32 bit word of the msg array
5111 */
f2ca0dbe
AD		 5112 unsigned char *addr = (char *)&msg[1];
5113 int err = -1;
4ae196df 5114
f2ca0dbe
AD		 5115 if (is_valid_ether_addr(addr))
5116 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5117
f2ca0dbe 5118 return err;
4ae196df
AD		 5119}
5120
5121static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5122{
5123 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5124 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5125 u32 msg = E1000_VT_MSGTYPE_NACK;
5126
5127 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5128 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5129 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5130 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5131 vf_data->last_nack = jiffies;
4ae196df
AD		 5132 }
5133}
5134
f2ca0dbe 5135static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5136{
f2ca0dbe
AD		 5137 struct pci_dev *pdev = adapter->pdev;
5138 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5139 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5140 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5141 s32 retval;
5142
f2ca0dbe 5143 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5144
fef45f4c
AD		 5145 if (retval) {
5146 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5147 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5148 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5149 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5150 return;
5151 goto out;
5152 }
4ae196df
AD		 5153
5154 /* this is a message we already processed, do nothing */
5155 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5156 return;
4ae196df
AD		 5157
5158 /*
5159 * until the vf completes a reset it should not be
5160 * allowed to start any configuration.
5161 */
5162
5163 if (msgbuf[0] == E1000_VF_RESET) {
5164 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5165 return;
4ae196df
AD		 5166 }
5167
f2ca0dbe 5168 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5169 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5170 return;
5171 retval = -1;
5172 goto out;
4ae196df
AD		 5173 }
5174
5175 switch ((msgbuf[0] & 0xFFFF)) {
5176 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5177 retval = -EINVAL;
5178 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5179 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5180 else
5181 dev_warn(&pdev->dev,
5182 "VF %d attempted to override administratively "
5183 "set MAC address\nReload the VF driver to "
5184 "resume operations\n", vf);
4ae196df 5185 break;
7d5753f0
AD		 5186 case E1000_VF_SET_PROMISC:
5187 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5188 break;
4ae196df
AD		 5189 case E1000_VF_SET_MULTICAST:
5190 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5191 break;
5192 case E1000_VF_SET_LPE:
5193 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5194 break;
5195 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5196 retval = -1;
5197 if (vf_data->pf_vlan)
5198 dev_warn(&pdev->dev,
5199 "VF %d attempted to override administratively "
5200 "set VLAN tag\nReload the VF driver to "
5201 "resume operations\n", vf);
8151d294
WM		 5202 else
5203 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5204 break;
5205 default:
090b1795 5206 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5207 retval = -1;
5208 break;
5209 }
5210
fef45f4c
AD		 5211 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5212out:
4ae196df
AD		 5213 /* notify the VF of the results of what it sent us */
5214 if (retval)
5215 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5216 else
5217 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5218
4ae196df 5219 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5220}
4ae196df 5221
f2ca0dbe
AD		 5222static void igb_msg_task(struct igb_adapter *adapter)
5223{
5224 struct e1000_hw *hw = &adapter->hw;
5225 u32 vf;
5226
5227 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5228 /* process any reset requests */
5229 if (!igb_check_for_rst(hw, vf))
5230 igb_vf_reset_event(adapter, vf);
5231
5232 /* process any messages pending */
5233 if (!igb_check_for_msg(hw, vf))
5234 igb_rcv_msg_from_vf(adapter, vf);
5235
5236 /* process any acks */
5237 if (!igb_check_for_ack(hw, vf))
5238 igb_rcv_ack_from_vf(adapter, vf);
5239 }
4ae196df
AD		 5240}
5241
68d480c4
AD		 5242/**
5243 * igb_set_uta - Set unicast filter table address
5244 * @adapter: board private structure
5245 *
5246 * The unicast table address is a register array of 32-bit registers.
5247 * The table is meant to be used in a way similar to how the MTA is used
5248 * however due to certain limitations in the hardware it is necessary to
5249 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous
5250 * enable bit to allow vlan tag stripping when promiscous mode is enabled
5251 **/
5252static void igb_set_uta(struct igb_adapter *adapter)
5253{
5254 struct e1000_hw *hw = &adapter->hw;
5255 int i;
5256
5257 /* The UTA table only exists on 82576 hardware and newer */
5258 if (hw->mac.type < e1000_82576)
5259 return;
5260
5261 /* we only need to do this if VMDq is enabled */
5262 if (!adapter->vfs_allocated_count)
5263 return;
5264
5265 for (i = 0; i < hw->mac.uta_reg_count; i++)
5266 array_wr32(E1000_UTA, i, ~0);
5267}
5268
9d5c8243
AK		 5269/**
5270 * igb_intr_msi - Interrupt Handler
5271 * @irq: interrupt number
5272 * @data: pointer to a network interface device structure
5273 **/
5274static irqreturn_t igb_intr_msi(int irq, void *data)
5275{
047e0030
AD		 5276 struct igb_adapter *adapter = data;
5277 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5278 struct e1000_hw *hw = &adapter->hw;
5279 /* read ICR disables interrupts using IAM */
5280 u32 icr = rd32(E1000_ICR);
5281
047e0030 5282 igb_write_itr(q_vector);
9d5c8243 5283
7f081d40
AD		 5284 if (icr & E1000_ICR_DRSTA)
5285 schedule_work(&adapter->reset_task);
5286
047e0030 5287 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5288 /* HW is reporting DMA is out of sync */
5289 adapter->stats.doosync++;
5290 }
5291
9d5c8243
AK		 5292 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5293 hw->mac.get_link_status = 1;
5294 if (!test_bit(__IGB_DOWN, &adapter->state))
5295 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5296 }
5297
047e0030 5298 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5299
5300 return IRQ_HANDLED;
5301}
5302
5303/**
4a3c6433 5304 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5305 * @irq: interrupt number
5306 * @data: pointer to a network interface device structure
5307 **/
5308static irqreturn_t igb_intr(int irq, void *data)
5309{
047e0030
AD		 5310 struct igb_adapter *adapter = data;
5311 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5312 struct e1000_hw *hw = &adapter->hw;
5313 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5314 * need for the IMC write */
5315 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5316 if (!icr)
5317 return IRQ_NONE; /* Not our interrupt */
5318
047e0030 5319 igb_write_itr(q_vector);
9d5c8243
AK		 5320
5321 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5322 * not set, then the adapter didn't send an interrupt */
5323 if (!(icr & E1000_ICR_INT_ASSERTED))
5324 return IRQ_NONE;
5325
7f081d40
AD		 5326 if (icr & E1000_ICR_DRSTA)
5327 schedule_work(&adapter->reset_task);
5328
047e0030 5329 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5330 /* HW is reporting DMA is out of sync */
5331 adapter->stats.doosync++;
5332 }
5333
9d5c8243
AK		 5334 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5335 hw->mac.get_link_status = 1;
5336 /* guard against interrupt when we're going down */
5337 if (!test_bit(__IGB_DOWN, &adapter->state))
5338 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5339 }
5340
047e0030 5341 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5342
5343 return IRQ_HANDLED;
5344}
5345
047e0030 5346static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5347{
047e0030 5348 struct igb_adapter *adapter = q_vector->adapter;
46544258 5349 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5350
4fc82adf
AD		 5351 if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) ||
5352 (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) {
047e0030 5353 if (!adapter->msix_entries)
6eb5a7f1 5354 igb_set_itr(adapter);
46544258 5355 else
047e0030 5356 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5357 }
5358
46544258
AD		 5359 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5360 if (adapter->msix_entries)
047e0030 5361 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5362 else
5363 igb_irq_enable(adapter);
5364 }
9d5c8243
AK		 5365}
5366
46544258
AD		 5367/**
5368 * igb_poll - NAPI Rx polling callback
5369 * @napi: napi polling structure
5370 * @budget: count of how many packets we should handle
5371 **/
5372static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5373{
047e0030
AD		 5374 struct igb_q_vector *q_vector = container_of(napi,
5375 struct igb_q_vector,
5376 napi);
5377 int tx_clean_complete = 1, work_done = 0;
9d5c8243 5378
421e02f0 5379#ifdef CONFIG_IGB_DCA
047e0030
AD		 5380 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5381 igb_update_dca(q_vector);
fe4506b6 5382#endif
047e0030
AD		 5383 if (q_vector->tx_ring)
5384 tx_clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5385
047e0030
AD		 5386 if (q_vector->rx_ring)
5387 igb_clean_rx_irq_adv(q_vector, &work_done, budget);
5388
5389 if (!tx_clean_complete)
5390 work_done = budget;
46544258 5391
9d5c8243 5392 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 5393 if (work_done < budget) {
288379f0 5394 napi_complete(napi);
047e0030 5395 igb_ring_irq_enable(q_vector);
9d5c8243
AK		 5396 }
5397
46544258 5398 return work_done;
9d5c8243 5399}
6d8126f9 5400
33af6bcc 5401/**
c5b9bd5e 5402 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5403 * @adapter: board private structure
c5b9bd5e
AD		 5404 * @shhwtstamps: timestamp structure to update
5405 * @regval: unsigned 64bit system time value.
5406 *
5407 * We need to convert the system time value stored in the RX/TXSTMP registers
5408 * into a hwtstamp which can be used by the upper level timestamping functions
5409 */
5410static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5411 struct skb_shared_hwtstamps *shhwtstamps,
5412 u64 regval)
5413{
5414 u64 ns;
5415
55cac248
AD		 5416 /*
5417 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5418 * 24 to match clock shift we setup earlier.
5419 */
5420 if (adapter->hw.mac.type == e1000_82580)
5421 regval <<= IGB_82580_TSYNC_SHIFT;
5422
c5b9bd5e
AD		 5423 ns = timecounter_cyc2time(&adapter->clock, regval);
5424 timecompare_update(&adapter->compare, ns);
5425 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5426 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5427 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5428}
5429
5430/**
5431 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5432 * @q_vector: pointer to q_vector containing needed info
2873957d 5433 * @buffer: pointer to igb_buffer structure
33af6bcc
PO		 5434 *
5435 * If we were asked to do hardware stamping and such a time stamp is
5436 * available, then it must have been for this skb here because we only
5437 * allow only one such packet into the queue.
5438 */
2873957d 5439static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct igb_buffer *buffer_info)
33af6bcc 5440{
c5b9bd5e 5441 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc 5442 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5443 struct skb_shared_hwtstamps shhwtstamps;
5444 u64 regval;
33af6bcc 5445
c5b9bd5e 5446 /* if skb does not support hw timestamp or TX stamp not valid exit */
2244d07b 5447 if (likely(!(buffer_info->tx_flags & SKBTX_HW_TSTAMP)) ||
c5b9bd5e
AD		 5448 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5449 return;
5450
5451 regval = rd32(E1000_TXSTMPL);
5452 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5453
5454 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
2873957d 5455 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
33af6bcc
PO		 5456}
5457
9d5c8243
AK		 5458/**
5459 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5460 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5461 * returns true if ring is completely cleaned
5462 **/
047e0030 5463static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5464{
047e0030
AD		 5465 struct igb_adapter *adapter = q_vector->adapter;
5466 struct igb_ring *tx_ring = q_vector->tx_ring;
e694e964 5467 struct net_device *netdev = tx_ring->netdev;
0e014cb1 5468 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5469 struct igb_buffer *buffer_info;
0e014cb1 5470 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5471 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 5472 unsigned int i, eop, count = 0;
5473 bool cleaned = false;
9d5c8243 5474
9d5c8243 5475 i = tx_ring->next_to_clean;
0e014cb1
AD		 5476 eop = tx_ring->buffer_info[i].next_to_watch;
5477 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5478
5479 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
5480 (count < tx_ring->count)) {
2d0bb1c1 5481 rmb(); /* read buffer_info after eop_desc status */
0e014cb1
AD		 5482 for (cleaned = false; !cleaned; count++) {
5483 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 5484 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 5485 cleaned = (i == eop);
9d5c8243 5486
2873957d
NN		 5487 if (buffer_info->skb) {
5488 total_bytes += buffer_info->bytecount;
9d5c8243 5489 /* gso_segs is currently only valid for tcp */
2873957d
NN		 5490 total_packets += buffer_info->gso_segs;
5491 igb_tx_hwtstamp(q_vector, buffer_info);
9d5c8243
AK		 5492 }
5493
80785298 5494 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
0e014cb1 5495 tx_desc->wb.status = 0;
9d5c8243
AK		 5496
5497 i++;
5498 if (i == tx_ring->count)
5499 i = 0;
9d5c8243 5500 }
0e014cb1
AD		 5501 eop = tx_ring->buffer_info[i].next_to_watch;
5502 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
5503 }
5504
9d5c8243
AK		 5505 tx_ring->next_to_clean = i;
5506
fc7d345d 5507 if (unlikely(count &&
9d5c8243 5508 netif_carrier_ok(netdev) &&
c493ea45 5509 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 5510 /* Make sure that anybody stopping the queue after this
5511 * sees the new next_to_clean.
5512 */
5513 smp_mb();
661086df
PWJ		 5514 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
5515 !(test_bit(__IGB_DOWN, &adapter->state))) {
5516 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 5517
5518 u64_stats_update_begin(&tx_ring->tx_syncp);
04a5fcaa 5519 tx_ring->tx_stats.restart_queue++;
12dcd86b 5520 u64_stats_update_end(&tx_ring->tx_syncp);
661086df 5521 }
9d5c8243
AK		 5522 }
5523
5524 if (tx_ring->detect_tx_hung) {
5525 /* Detect a transmit hang in hardware, this serializes the
5526 * check with the clearing of time_stamp and movement of i */
5527 tx_ring->detect_tx_hung = false;
5528 if (tx_ring->buffer_info[i].time_stamp &&
5529 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
8e95a202
JP		 5530 (adapter->tx_timeout_factor * HZ)) &&
5531 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5532
9d5c8243 5533 /* detected Tx unit hang */
59d71989 5534 dev_err(tx_ring->dev,
9d5c8243 5535 "Detected Tx Unit Hang\n"
2d064c06 5536 " Tx Queue <%d>\n"
9d5c8243
AK		 5537 " TDH <%x>\n"
5538 " TDT <%x>\n"
5539 " next_to_use <%x>\n"
5540 " next_to_clean <%x>\n"
9d5c8243
AK		 5541 "buffer_info[next_to_clean]\n"
5542 " time_stamp <%lx>\n"
0e014cb1 5543 " next_to_watch <%x>\n"
9d5c8243
AK		 5544 " jiffies <%lx>\n"
5545 " desc.status <%x>\n",
2d064c06 5546 tx_ring->queue_index,
fce99e34
AD		 5547 readl(tx_ring->head),
5548 readl(tx_ring->tail),
9d5c8243
AK		 5549 tx_ring->next_to_use,
5550 tx_ring->next_to_clean,
f7ba205e 5551 tx_ring->buffer_info[eop].time_stamp,
0e014cb1 5552 eop,
9d5c8243 5553 jiffies,
0e014cb1 5554 eop_desc->wb.status);
661086df 5555 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 5556 }
5557 }
5558 tx_ring->total_bytes += total_bytes;
5559 tx_ring->total_packets += total_packets;
12dcd86b 5560 u64_stats_update_begin(&tx_ring->tx_syncp);
e21ed353
AD		 5561 tx_ring->tx_stats.bytes += total_bytes;
5562 tx_ring->tx_stats.packets += total_packets;
12dcd86b 5563 u64_stats_update_end(&tx_ring->tx_syncp);
807540ba 5564 return count < tx_ring->count;
9d5c8243
AK		 5565}
5566
9d5c8243
AK		 5567/**
5568 * igb_receive_skb - helper function to handle rx indications
047e0030
AD		 5569 * @q_vector: structure containing interrupt and ring information
5570 * @skb: packet to send up
5571 * @vlan_tag: vlan tag for packet
9d5c8243 5572 **/
047e0030
AD		 5573static void igb_receive_skb(struct igb_q_vector *q_vector,
5574 struct sk_buff *skb,
5575 u16 vlan_tag)
5576{
5577 struct igb_adapter *adapter = q_vector->adapter;
5578
31b24b95 5579 if (vlan_tag && adapter->vlgrp)
047e0030
AD		 5580 vlan_gro_receive(&q_vector->napi, adapter->vlgrp,
5581 vlan_tag, skb);
182ff8df 5582 else
047e0030 5583 napi_gro_receive(&q_vector->napi, skb);
9d5c8243
AK		 5584}
5585
04a5fcaa 5586static inline void igb_rx_checksum_adv(struct igb_ring *ring,
9d5c8243
AK		 5587 u32 status_err, struct sk_buff *skb)
5588{
bc8acf2c 5589 skb_checksum_none_assert(skb);
9d5c8243
AK		 5590
5591 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
85ad76b2
AD		 5592 if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) ||
5593 (status_err & E1000_RXD_STAT_IXSM))
9d5c8243 5594 return;
85ad76b2 5595
9d5c8243
AK		 5596 /* TCP/UDP checksum error bit is set */
5597 if (status_err &
5598 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5599 /*
5600 * work around errata with sctp packets where the TCPE aka
5601 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5602 * packets, (aka let the stack check the crc32c)
5603 */
85ad76b2 5604 if ((skb->len == 60) &&
12dcd86b
ED		 5605 (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) {
5606 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 5607 ring->rx_stats.csum_err++;
12dcd86b
ED		 5608 u64_stats_update_end(&ring->rx_syncp);
5609 }
9d5c8243 5610 /* let the stack verify checksum errors */
9d5c8243
AK		 5611 return;
5612 }
5613 /* It must be a TCP or UDP packet with a valid checksum */
5614 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
5615 skb->ip_summed = CHECKSUM_UNNECESSARY;
5616
59d71989 5617 dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 5618}
5619
757b77e2 5620static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr,
c5b9bd5e
AD		 5621 struct sk_buff *skb)
5622{
5623 struct igb_adapter *adapter = q_vector->adapter;
5624 struct e1000_hw *hw = &adapter->hw;
5625 u64 regval;
5626
5627 /*
5628 * If this bit is set, then the RX registers contain the time stamp. No
5629 * other packet will be time stamped until we read these registers, so
5630 * read the registers to make them available again. Because only one
5631 * packet can be time stamped at a time, we know that the register
5632 * values must belong to this one here and therefore we don't need to
5633 * compare any of the additional attributes stored for it.
5634 *
2244d07b 5635 * If nothing went wrong, then it should have a shared tx_flags that we
c5b9bd5e
AD		 5636 * can turn into a skb_shared_hwtstamps.
5637 */
757b77e2
NN		 5638 if (staterr & E1000_RXDADV_STAT_TSIP) {
5639 u32 *stamp = (u32 *)skb->data;
5640 regval = le32_to_cpu(*(stamp + 2));
5641 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5642 skb_pull(skb, IGB_TS_HDR_LEN);
5643 } else {
5644 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5645 return;
c5b9bd5e 5646
757b77e2
NN		 5647 regval = rd32(E1000_RXSTMPL);
5648 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5649 }
c5b9bd5e
AD		 5650
5651 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5652}
4c844851 5653static inline u16 igb_get_hlen(struct igb_ring *rx_ring,
2d94d8ab
AD		 5654 union e1000_adv_rx_desc *rx_desc)
5655{
5656 /* HW will not DMA in data larger than the given buffer, even if it
5657 * parses the (NFS, of course) header to be larger. In that case, it
5658 * fills the header buffer and spills the rest into the page.
5659 */
5660 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5661 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4c844851
AD		 5662 if (hlen > rx_ring->rx_buffer_len)
5663 hlen = rx_ring->rx_buffer_len;
2d94d8ab
AD		 5664 return hlen;
5665}
5666
047e0030
AD		 5667static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector,
5668 int *work_done, int budget)
9d5c8243 5669{
047e0030 5670 struct igb_ring *rx_ring = q_vector->rx_ring;
e694e964 5671 struct net_device *netdev = rx_ring->netdev;
59d71989 5672 struct device *dev = rx_ring->dev;
9d5c8243
AK		 5673 union e1000_adv_rx_desc *rx_desc , *next_rxd;
5674 struct igb_buffer *buffer_info , *next_buffer;
5675 struct sk_buff *skb;
9d5c8243
AK		 5676 bool cleaned = false;
5677 int cleaned_count = 0;
d1eff350 5678 int current_node = numa_node_id();
9d5c8243 5679 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1 5680 unsigned int i;
2d94d8ab
AD		 5681 u32 staterr;
5682 u16 length;
047e0030 5683 u16 vlan_tag;
9d5c8243
AK		 5684
5685 i = rx_ring->next_to_clean;
69d3ca53 5686 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 5687 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5688 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5689
5690 while (staterr & E1000_RXD_STAT_DD) {
5691 if (*work_done >= budget)
5692 break;
5693 (*work_done)++;
2d0bb1c1 5694 rmb(); /* read descriptor and rx_buffer_info after status DD */
9d5c8243 5695
69d3ca53
AD		 5696 skb = buffer_info->skb;
5697 prefetch(skb->data - NET_IP_ALIGN);
5698 buffer_info->skb = NULL;
5699
5700 i++;
5701 if (i == rx_ring->count)
5702 i = 0;
42d0781a 5703
69d3ca53
AD		 5704 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
5705 prefetch(next_rxd);
5706 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 5707
5708 length = le16_to_cpu(rx_desc->wb.upper.length);
5709 cleaned = true;
5710 cleaned_count++;
5711
2d94d8ab 5712 if (buffer_info->dma) {
59d71989 5713 dma_unmap_single(dev, buffer_info->dma,
4c844851 5714 rx_ring->rx_buffer_len,
59d71989 5715 DMA_FROM_DEVICE);
91615f76 5716 buffer_info->dma = 0;
4c844851 5717 if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) {
6ec43fe6
AD		 5718 skb_put(skb, length);
5719 goto send_up;
5720 }
4c844851 5721 skb_put(skb, igb_get_hlen(rx_ring, rx_desc));
bf36c1a0
AD		 5722 }
5723
5724 if (length) {
59d71989
AD		 5725 dma_unmap_page(dev, buffer_info->page_dma,
5726 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9d5c8243 5727 buffer_info->page_dma = 0;
bf36c1a0 5728
aa913403 5729 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 5730 buffer_info->page,
5731 buffer_info->page_offset,
5732 length);
5733
d1eff350
AD		 5734 if ((page_count(buffer_info->page) != 1) ||
5735 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 5736 buffer_info->page = NULL;
5737 else
5738 get_page(buffer_info->page);
9d5c8243
AK		 5739
5740 skb->len += length;
5741 skb->data_len += length;
bf36c1a0 5742 skb->truesize += length;
9d5c8243 5743 }
9d5c8243 5744
bf36c1a0 5745 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 5746 buffer_info->skb = next_buffer->skb;
5747 buffer_info->dma = next_buffer->dma;
5748 next_buffer->skb = skb;
5749 next_buffer->dma = 0;
bf36c1a0
AD		 5750 goto next_desc;
5751 }
69d3ca53 5752send_up:
9d5c8243
AK		 5753 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
5754 dev_kfree_skb_irq(skb);
5755 goto next_desc;
5756 }
9d5c8243 5757
757b77e2
NN		 5758 if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS))
5759 igb_rx_hwtstamp(q_vector, staterr, skb);
9d5c8243
AK		 5760 total_bytes += skb->len;
5761 total_packets++;
5762
85ad76b2 5763 igb_rx_checksum_adv(rx_ring, staterr, skb);
9d5c8243
AK		 5764
5765 skb->protocol = eth_type_trans(skb, netdev);
047e0030
AD		 5766 skb_record_rx_queue(skb, rx_ring->queue_index);
5767
5768 vlan_tag = ((staterr & E1000_RXD_STAT_VP) ?
5769 le16_to_cpu(rx_desc->wb.upper.vlan) : 0);
9d5c8243 5770
047e0030 5771 igb_receive_skb(q_vector, skb, vlan_tag);
9d5c8243 5772
9d5c8243
AK		 5773next_desc:
5774 rx_desc->wb.upper.status_error = 0;
5775
5776 /* return some buffers to hardware, one at a time is too slow */
5777 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 5778 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5779 cleaned_count = 0;
5780 }
5781
5782 /* use prefetched values */
5783 rx_desc = next_rxd;
5784 buffer_info = next_buffer;
9d5c8243
AK		 5785 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
5786 }
bf36c1a0 5787
9d5c8243 5788 rx_ring->next_to_clean = i;
c493ea45 5789 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 5790
5791 if (cleaned_count)
3b644cf6 5792 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 5793
5794 rx_ring->total_packets += total_packets;
5795 rx_ring->total_bytes += total_bytes;
12dcd86b 5796 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 5797 rx_ring->rx_stats.packets += total_packets;
5798 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 5799 u64_stats_update_end(&rx_ring->rx_syncp);
9d5c8243
AK		 5800 return cleaned;
5801}
5802
9d5c8243
AK		 5803/**
5804 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
5805 * @adapter: address of board private structure
5806 **/
d7ee5b3a 5807void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count)
9d5c8243 5808{
e694e964 5809 struct net_device *netdev = rx_ring->netdev;
9d5c8243
AK		 5810 union e1000_adv_rx_desc *rx_desc;
5811 struct igb_buffer *buffer_info;
5812 struct sk_buff *skb;
5813 unsigned int i;
db761762 5814 int bufsz;
9d5c8243
AK		 5815
5816 i = rx_ring->next_to_use;
5817 buffer_info = &rx_ring->buffer_info[i];
5818
4c844851 5819 bufsz = rx_ring->rx_buffer_len;
db761762 5820
9d5c8243
AK		 5821 while (cleaned_count--) {
5822 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
5823
6ec43fe6 5824 if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) {
9d5c8243 5825 if (!buffer_info->page) {
42d0781a 5826 buffer_info->page = netdev_alloc_page(netdev);
12dcd86b
ED		 5827 if (unlikely(!buffer_info->page)) {
5828 u64_stats_update_begin(&rx_ring->rx_syncp);
04a5fcaa 5829 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5830 u64_stats_update_end(&rx_ring->rx_syncp);
bf36c1a0
AD		 5831 goto no_buffers;
5832 }
5833 buffer_info->page_offset = 0;
5834 } else {
5835 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 5836 }
5837 buffer_info->page_dma =
59d71989 5838 dma_map_page(rx_ring->dev, buffer_info->page,
bf36c1a0
AD		 5839 buffer_info->page_offset,
5840 PAGE_SIZE / 2,
59d71989
AD		 5841 DMA_FROM_DEVICE);
5842 if (dma_mapping_error(rx_ring->dev,
5843 buffer_info->page_dma)) {
42d0781a 5844 buffer_info->page_dma = 0;
12dcd86b 5845 u64_stats_update_begin(&rx_ring->rx_syncp);
42d0781a 5846 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5847 u64_stats_update_end(&rx_ring->rx_syncp);
42d0781a
AD		 5848 goto no_buffers;
5849 }
9d5c8243
AK		 5850 }
5851
42d0781a
AD		 5852 skb = buffer_info->skb;
5853 if (!skb) {
89d71a66 5854 skb = netdev_alloc_skb_ip_align(netdev, bufsz);
12dcd86b
ED		 5855 if (unlikely(!skb)) {
5856 u64_stats_update_begin(&rx_ring->rx_syncp);
04a5fcaa 5857 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5858 u64_stats_update_end(&rx_ring->rx_syncp);
9d5c8243
AK		 5859 goto no_buffers;
5860 }
5861
9d5c8243 5862 buffer_info->skb = skb;
42d0781a
AD		 5863 }
5864 if (!buffer_info->dma) {
59d71989 5865 buffer_info->dma = dma_map_single(rx_ring->dev,
80785298 5866 skb->data,
9d5c8243 5867 bufsz,
59d71989
AD		 5868 DMA_FROM_DEVICE);
5869 if (dma_mapping_error(rx_ring->dev,
5870 buffer_info->dma)) {
42d0781a 5871 buffer_info->dma = 0;
12dcd86b 5872 u64_stats_update_begin(&rx_ring->rx_syncp);
42d0781a 5873 rx_ring->rx_stats.alloc_failed++;
12dcd86b 5874 u64_stats_update_end(&rx_ring->rx_syncp);
42d0781a
AD		 5875 goto no_buffers;
5876 }
9d5c8243
AK		 5877 }
5878 /* Refresh the desc even if buffer_addrs didn't change because
5879 * each write-back erases this info. */
6ec43fe6 5880 if (bufsz < IGB_RXBUFFER_1024) {
9d5c8243
AK		 5881 rx_desc->read.pkt_addr =
5882 cpu_to_le64(buffer_info->page_dma);
5883 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
5884 } else {
42d0781a 5885 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
9d5c8243
AK		 5886 rx_desc->read.hdr_addr = 0;
5887 }
5888
5889 i++;
5890 if (i == rx_ring->count)
5891 i = 0;
5892 buffer_info = &rx_ring->buffer_info[i];
5893 }
5894
5895no_buffers:
5896 if (rx_ring->next_to_use != i) {
5897 rx_ring->next_to_use = i;
5898 if (i == 0)
5899 i = (rx_ring->count - 1);
5900 else
5901 i--;
5902
5903 /* Force memory writes to complete before letting h/w
5904 * know there are new descriptors to fetch. (Only
5905 * applicable for weak-ordered memory model archs,
5906 * such as IA-64). */
5907 wmb();
fce99e34 5908 writel(i, rx_ring->tail);
9d5c8243
AK		 5909 }
5910}
5911
5912/**
5913 * igb_mii_ioctl -
5914 * @netdev:
5915 * @ifreq:
5916 * @cmd:
5917 **/
5918static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5919{
5920 struct igb_adapter *adapter = netdev_priv(netdev);
5921 struct mii_ioctl_data *data = if_mii(ifr);
5922
5923 if (adapter->hw.phy.media_type != e1000_media_type_copper)
5924 return -EOPNOTSUPP;
5925
5926 switch (cmd) {
5927 case SIOCGMIIPHY:
5928 data->phy_id = adapter->hw.phy.addr;
5929 break;
5930 case SIOCGMIIREG:
f5f4cf08
AD		 5931 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
5932 &data->val_out))
9d5c8243
AK		 5933 return -EIO;
5934 break;
5935 case SIOCSMIIREG:
5936 default:
5937 return -EOPNOTSUPP;
5938 }
5939 return 0;
5940}
5941
c6cb090b
PO		 5942/**
5943 * igb_hwtstamp_ioctl - control hardware time stamping
5944 * @netdev:
5945 * @ifreq:
5946 * @cmd:
5947 *
33af6bcc
PO		 5948 * Outgoing time stamping can be enabled and disabled. Play nice and
5949 * disable it when requested, although it shouldn't case any overhead
5950 * when no packet needs it. At most one packet in the queue may be
5951 * marked for time stamping, otherwise it would be impossible to tell
5952 * for sure to which packet the hardware time stamp belongs.
5953 *
5954 * Incoming time stamping has to be configured via the hardware
5955 * filters. Not all combinations are supported, in particular event
5956 * type has to be specified. Matching the kind of event packet is
5957 * not supported, with the exception of "all V2 events regardless of
5958 * level 2 or 4".
5959 *
c6cb090b
PO		 5960 **/
5961static int igb_hwtstamp_ioctl(struct net_device *netdev,
5962 struct ifreq *ifr, int cmd)
5963{
33af6bcc
PO		 5964 struct igb_adapter *adapter = netdev_priv(netdev);
5965 struct e1000_hw *hw = &adapter->hw;
c6cb090b 5966 struct hwtstamp_config config;
c5b9bd5e
AD		 5967 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
5968 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 5969 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 5970 bool is_l4 = false;
5971 bool is_l2 = false;
33af6bcc 5972 u32 regval;
c6cb090b
PO		 5973
5974 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5975 return -EFAULT;
5976
5977 /* reserved for future extensions */
5978 if (config.flags)
5979 return -EINVAL;
5980
33af6bcc
PO		 5981 switch (config.tx_type) {
5982 case HWTSTAMP_TX_OFF:
c5b9bd5e 5983 tsync_tx_ctl = 0;
33af6bcc 5984 case HWTSTAMP_TX_ON:
33af6bcc
PO		 5985 break;
5986 default:
5987 return -ERANGE;
5988 }
5989
5990 switch (config.rx_filter) {
5991 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 5992 tsync_rx_ctl = 0;
33af6bcc
PO		 5993 break;
5994 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5995 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5996 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5997 case HWTSTAMP_FILTER_ALL:
5998 /*
5999 * register TSYNCRXCFG must be set, therefore it is not
6000 * possible to time stamp both Sync and Delay_Req messages
6001 * => fall back to time stamping all packets
6002 */
c5b9bd5e 6003 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 6004 config.rx_filter = HWTSTAMP_FILTER_ALL;
6005 break;
6006 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 6007 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6008 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 6009 is_l4 = true;
33af6bcc
PO		 6010 break;
6011 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 6012 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6013 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 6014 is_l4 = true;
33af6bcc
PO		 6015 break;
6016 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6017 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 6018 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6019 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 6020 is_l2 = true;
6021 is_l4 = true;
33af6bcc
PO		 6022 config.rx_filter = HWTSTAMP_FILTER_SOME;
6023 break;
6024 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6025 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 6026 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6027 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 6028 is_l2 = true;
6029 is_l4 = true;
33af6bcc
PO		 6030 config.rx_filter = HWTSTAMP_FILTER_SOME;
6031 break;
6032 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6033 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6034 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 6035 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 6036 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 6037 is_l2 = true;
33af6bcc
PO		 6038 break;
6039 default:
6040 return -ERANGE;
6041 }
6042
c5b9bd5e
AD		 6043 if (hw->mac.type == e1000_82575) {
6044 if (tsync_rx_ctl | tsync_tx_ctl)
6045 return -EINVAL;
6046 return 0;
6047 }
6048
757b77e2
NN		 6049 /*
6050 * Per-packet timestamping only works if all packets are
6051 * timestamped, so enable timestamping in all packets as
6052 * long as one rx filter was configured.
6053 */
6054 if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
6055 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6056 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6057 }
6058
33af6bcc
PO		 6059 /* enable/disable TX */
6060 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 6061 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6062 regval |= tsync_tx_ctl;
33af6bcc
PO		 6063 wr32(E1000_TSYNCTXCTL, regval);
6064
c5b9bd5e 6065 /* enable/disable RX */
33af6bcc 6066 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 6067 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6068 regval |= tsync_rx_ctl;
33af6bcc 6069 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 6070
c5b9bd5e
AD		 6071 /* define which PTP packets are time stamped */
6072 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 6073
c5b9bd5e
AD		 6074 /* define ethertype filter for timestamped packets */
6075 if (is_l2)
6076 wr32(E1000_ETQF(3),
6077 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6078 E1000_ETQF_1588 | /* enable timestamping */
6079 ETH_P_1588)); /* 1588 eth protocol type */
6080 else
6081 wr32(E1000_ETQF(3), 0);
6082
6083#define PTP_PORT 319
6084 /* L4 Queue Filter[3]: filter by destination port and protocol */
6085 if (is_l4) {
6086 u32 ftqf = (IPPROTO_UDP /* UDP */
6087 | E1000_FTQF_VF_BP /* VF not compared */
6088 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6089 | E1000_FTQF_MASK); /* mask all inputs */
6090 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6091
6092 wr32(E1000_IMIR(3), htons(PTP_PORT));
6093 wr32(E1000_IMIREXT(3),
6094 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6095 if (hw->mac.type == e1000_82576) {
6096 /* enable source port check */
6097 wr32(E1000_SPQF(3), htons(PTP_PORT));
6098 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6099 }
6100 wr32(E1000_FTQF(3), ftqf);
6101 } else {
6102 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6103 }
33af6bcc
PO		 6104 wrfl();
6105
6106 adapter->hwtstamp_config = config;
6107
6108 /* clear TX/RX time stamp registers, just to be sure */
6109 regval = rd32(E1000_TXSTMPH);
6110 regval = rd32(E1000_RXSTMPH);
c6cb090b 6111
33af6bcc
PO		 6112 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6113 -EFAULT : 0;
c6cb090b
PO		 6114}
6115
9d5c8243
AK		 6116/**
6117 * igb_ioctl -
6118 * @netdev:
6119 * @ifreq:
6120 * @cmd:
6121 **/
6122static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6123{
6124 switch (cmd) {
6125 case SIOCGMIIPHY:
6126 case SIOCGMIIREG:
6127 case SIOCSMIIREG:
6128 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 6129 case SIOCSHWTSTAMP:
6130 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6131 default:
6132 return -EOPNOTSUPP;
6133 }
6134}
6135
009bc06e
AD		 6136s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6137{
6138 struct igb_adapter *adapter = hw->back;
6139 u16 cap_offset;
6140
6141 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6142 if (!cap_offset)
6143 return -E1000_ERR_CONFIG;
6144
6145 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6146
6147 return 0;
6148}
6149
6150s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6151{
6152 struct igb_adapter *adapter = hw->back;
6153 u16 cap_offset;
6154
6155 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
6156 if (!cap_offset)
6157 return -E1000_ERR_CONFIG;
6158
6159 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6160
6161 return 0;
6162}
6163
9d5c8243
AK		 6164static void igb_vlan_rx_register(struct net_device *netdev,
6165 struct vlan_group *grp)
6166{
6167 struct igb_adapter *adapter = netdev_priv(netdev);
6168 struct e1000_hw *hw = &adapter->hw;
6169 u32 ctrl, rctl;
6170
6171 igb_irq_disable(adapter);
6172 adapter->vlgrp = grp;
6173
6174 if (grp) {
6175 /* enable VLAN tag insert/strip */
6176 ctrl = rd32(E1000_CTRL);
6177 ctrl |= E1000_CTRL_VME;
6178 wr32(E1000_CTRL, ctrl);
6179
51466239 6180 /* Disable CFI check */
9d5c8243 6181 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6182 rctl &= ~E1000_RCTL_CFIEN;
6183 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6184 } else {
6185 /* disable VLAN tag insert/strip */
6186 ctrl = rd32(E1000_CTRL);
6187 ctrl &= ~E1000_CTRL_VME;
6188 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6189 }
6190
e1739522
AD		 6191 igb_rlpml_set(adapter);
6192
9d5c8243
AK		 6193 if (!test_bit(__IGB_DOWN, &adapter->state))
6194 igb_irq_enable(adapter);
6195}
6196
6197static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6198{
6199 struct igb_adapter *adapter = netdev_priv(netdev);
6200 struct e1000_hw *hw = &adapter->hw;
4ae196df 6201 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6202
51466239
AD		 6203 /* attempt to add filter to vlvf array */
6204 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6205
51466239
AD		 6206 /* add the filter since PF can receive vlans w/o entry in vlvf */
6207 igb_vfta_set(hw, vid, true);
9d5c8243
AK		 6208}
6209
6210static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6211{
6212 struct igb_adapter *adapter = netdev_priv(netdev);
6213 struct e1000_hw *hw = &adapter->hw;
4ae196df 6214 int pf_id = adapter->vfs_allocated_count;
51466239 6215 s32 err;
9d5c8243
AK		 6216
6217 igb_irq_disable(adapter);
6218 vlan_group_set_device(adapter->vlgrp, vid, NULL);
6219
6220 if (!test_bit(__IGB_DOWN, &adapter->state))
6221 igb_irq_enable(adapter);
6222
51466239
AD		 6223 /* remove vlan from VLVF table array */
6224 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6225
51466239
AD		 6226 /* if vid was not present in VLVF just remove it from table */
6227 if (err)
4ae196df 6228 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 6229}
6230
6231static void igb_restore_vlan(struct igb_adapter *adapter)
6232{
6233 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
6234
6235 if (adapter->vlgrp) {
6236 u16 vid;
b738127d 6237 for (vid = 0; vid < VLAN_N_VID; vid++) {
9d5c8243
AK		 6238 if (!vlan_group_get_device(adapter->vlgrp, vid))
6239 continue;
6240 igb_vlan_rx_add_vid(adapter->netdev, vid);
6241 }
6242 }
6243}
6244
6245int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
6246{
090b1795 6247 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6248 struct e1000_mac_info *mac = &adapter->hw.mac;
6249
6250 mac->autoneg = 0;
6251
cd2638a8
CW		 6252 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6253 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6254 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
6255 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6256 return -EINVAL;
6257 }
6258
9d5c8243
AK		 6259 switch (spddplx) {
6260 case SPEED_10 + DUPLEX_HALF:
6261 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6262 break;
6263 case SPEED_10 + DUPLEX_FULL:
6264 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6265 break;
6266 case SPEED_100 + DUPLEX_HALF:
6267 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6268 break;
6269 case SPEED_100 + DUPLEX_FULL:
6270 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6271 break;
6272 case SPEED_1000 + DUPLEX_FULL:
6273 mac->autoneg = 1;
6274 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6275 break;
6276 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6277 default:
090b1795 6278 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9d5c8243
AK		 6279 return -EINVAL;
6280 }
6281 return 0;
6282}
6283
3fe7c4c9 6284static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6285{
6286 struct net_device *netdev = pci_get_drvdata(pdev);
6287 struct igb_adapter *adapter = netdev_priv(netdev);
6288 struct e1000_hw *hw = &adapter->hw;
2d064c06 6289 u32 ctrl, rctl, status;
9d5c8243
AK		 6290 u32 wufc = adapter->wol;
6291#ifdef CONFIG_PM
6292 int retval = 0;
6293#endif
6294
6295 netif_device_detach(netdev);
6296
a88f10ec
AD		 6297 if (netif_running(netdev))
6298 igb_close(netdev);
6299
047e0030 6300 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6301
6302#ifdef CONFIG_PM
6303 retval = pci_save_state(pdev);
6304 if (retval)
6305 return retval;
6306#endif
6307
6308 status = rd32(E1000_STATUS);
6309 if (status & E1000_STATUS_LU)
6310 wufc &= ~E1000_WUFC_LNKC;
6311
6312 if (wufc) {
6313 igb_setup_rctl(adapter);
ff41f8dc 6314 igb_set_rx_mode(netdev);
9d5c8243
AK		 6315
6316 /* turn on all-multi mode if wake on multicast is enabled */
6317 if (wufc & E1000_WUFC_MC) {
6318 rctl = rd32(E1000_RCTL);
6319 rctl |= E1000_RCTL_MPE;
6320 wr32(E1000_RCTL, rctl);
6321 }
6322
6323 ctrl = rd32(E1000_CTRL);
6324 /* advertise wake from D3Cold */
6325 #define E1000_CTRL_ADVD3WUC 0x00100000
6326 /* phy power management enable */
6327 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6328 ctrl |= E1000_CTRL_ADVD3WUC;
6329 wr32(E1000_CTRL, ctrl);
6330
9d5c8243 6331 /* Allow time for pending master requests to run */
330a6d6a 6332 igb_disable_pcie_master(hw);
9d5c8243
AK		 6333
6334 wr32(E1000_WUC, E1000_WUC_PME_EN);
6335 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6336 } else {
6337 wr32(E1000_WUC, 0);
6338 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6339 }
6340
3fe7c4c9
RW		 6341 *enable_wake = wufc || adapter->en_mng_pt;
6342 if (!*enable_wake)
88a268c1
NN		 6343 igb_power_down_link(adapter);
6344 else
6345 igb_power_up_link(adapter);
9d5c8243
AK		 6346
6347 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6348 * would have already happened in close and is redundant. */
6349 igb_release_hw_control(adapter);
6350
6351 pci_disable_device(pdev);
6352
9d5c8243
AK		 6353 return 0;
6354}
6355
6356#ifdef CONFIG_PM
3fe7c4c9
RW		 6357static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6358{
6359 int retval;
6360 bool wake;
6361
6362 retval = __igb_shutdown(pdev, &wake);
6363 if (retval)
6364 return retval;
6365
6366 if (wake) {
6367 pci_prepare_to_sleep(pdev);
6368 } else {
6369 pci_wake_from_d3(pdev, false);
6370 pci_set_power_state(pdev, PCI_D3hot);
6371 }
6372
6373 return 0;
6374}
6375
9d5c8243
AK		 6376static int igb_resume(struct pci_dev *pdev)
6377{
6378 struct net_device *netdev = pci_get_drvdata(pdev);
6379 struct igb_adapter *adapter = netdev_priv(netdev);
6380 struct e1000_hw *hw = &adapter->hw;
6381 u32 err;
6382
6383 pci_set_power_state(pdev, PCI_D0);
6384 pci_restore_state(pdev);
b94f2d77 6385 pci_save_state(pdev);
42bfd33a 6386
aed5dec3 6387 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6388 if (err) {
6389 dev_err(&pdev->dev,
6390 "igb: Cannot enable PCI device from suspend\n");
6391 return err;
6392 }
6393 pci_set_master(pdev);
6394
6395 pci_enable_wake(pdev, PCI_D3hot, 0);
6396 pci_enable_wake(pdev, PCI_D3cold, 0);
6397
047e0030 6398 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6399 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6400 return -ENOMEM;
9d5c8243
AK		 6401 }
6402
9d5c8243 6403 igb_reset(adapter);
a8564f03
AD		 6404
6405 /* let the f/w know that the h/w is now under the control of the
6406 * driver. */
6407 igb_get_hw_control(adapter);
6408
9d5c8243
AK		 6409 wr32(E1000_WUS, ~0);
6410
a88f10ec
AD		 6411 if (netif_running(netdev)) {
6412 err = igb_open(netdev);
6413 if (err)
6414 return err;
6415 }
9d5c8243
AK		 6416
6417 netif_device_attach(netdev);
6418
9d5c8243
AK		 6419 return 0;
6420}
6421#endif
6422
6423static void igb_shutdown(struct pci_dev *pdev)
6424{
3fe7c4c9
RW		 6425 bool wake;
6426
6427 __igb_shutdown(pdev, &wake);
6428
6429 if (system_state == SYSTEM_POWER_OFF) {
6430 pci_wake_from_d3(pdev, wake);
6431 pci_set_power_state(pdev, PCI_D3hot);
6432 }
9d5c8243
AK		 6433}
6434
6435#ifdef CONFIG_NET_POLL_CONTROLLER
6436/*
6437 * Polling 'interrupt' - used by things like netconsole to send skbs
6438 * without having to re-enable interrupts. It's not called while
6439 * the interrupt routine is executing.
6440 */
6441static void igb_netpoll(struct net_device *netdev)
6442{
6443 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6444 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6445 int i;
9d5c8243 6446
eebbbdba 6447 if (!adapter->msix_entries) {
047e0030 6448 struct igb_q_vector *q_vector = adapter->q_vector[0];
eebbbdba 6449 igb_irq_disable(adapter);
047e0030 6450 napi_schedule(&q_vector->napi);
eebbbdba
AD		 6451 return;
6452 }
9d5c8243 6453
047e0030
AD		 6454 for (i = 0; i < adapter->num_q_vectors; i++) {
6455 struct igb_q_vector *q_vector = adapter->q_vector[i];
6456 wr32(E1000_EIMC, q_vector->eims_value);
6457 napi_schedule(&q_vector->napi);
eebbbdba 6458 }
9d5c8243
AK		 6459}
6460#endif /* CONFIG_NET_POLL_CONTROLLER */
6461
6462/**
6463 * igb_io_error_detected - called when PCI error is detected
6464 * @pdev: Pointer to PCI device
6465 * @state: The current pci connection state
6466 *
6467 * This function is called after a PCI bus error affecting
6468 * this device has been detected.
6469 */
6470static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6471 pci_channel_state_t state)
6472{
6473 struct net_device *netdev = pci_get_drvdata(pdev);
6474 struct igb_adapter *adapter = netdev_priv(netdev);
6475
6476 netif_device_detach(netdev);
6477
59ed6eec
AD		 6478 if (state == pci_channel_io_perm_failure)
6479 return PCI_ERS_RESULT_DISCONNECT;
6480
9d5c8243
AK		 6481 if (netif_running(netdev))
6482 igb_down(adapter);
6483 pci_disable_device(pdev);
6484
6485 /* Request a slot slot reset. */
6486 return PCI_ERS_RESULT_NEED_RESET;
6487}
6488
6489/**
6490 * igb_io_slot_reset - called after the pci bus has been reset.
6491 * @pdev: Pointer to PCI device
6492 *
6493 * Restart the card from scratch, as if from a cold-boot. Implementation
6494 * resembles the first-half of the igb_resume routine.
6495 */
6496static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6497{
6498 struct net_device *netdev = pci_get_drvdata(pdev);
6499 struct igb_adapter *adapter = netdev_priv(netdev);
6500 struct e1000_hw *hw = &adapter->hw;
40a914fa 6501 pci_ers_result_t result;
42bfd33a 6502 int err;
9d5c8243 6503
aed5dec3 6504 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6505 dev_err(&pdev->dev,
6506 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6507 result = PCI_ERS_RESULT_DISCONNECT;
6508 } else {
6509 pci_set_master(pdev);
6510 pci_restore_state(pdev);
b94f2d77 6511 pci_save_state(pdev);
9d5c8243 6512
40a914fa
AD		 6513 pci_enable_wake(pdev, PCI_D3hot, 0);
6514 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6515
40a914fa
AD		 6516 igb_reset(adapter);
6517 wr32(E1000_WUS, ~0);
6518 result = PCI_ERS_RESULT_RECOVERED;
6519 }
9d5c8243 6520
ea943d41
JK		 6521 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6522 if (err) {
6523 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6524 "failed 0x%0x\n", err);
6525 /* non-fatal, continue */
6526 }
40a914fa
AD		 6527
6528 return result;
9d5c8243
AK		 6529}
6530
6531/**
6532 * igb_io_resume - called when traffic can start flowing again.
6533 * @pdev: Pointer to PCI device
6534 *
6535 * This callback is called when the error recovery driver tells us that
6536 * its OK to resume normal operation. Implementation resembles the
6537 * second-half of the igb_resume routine.
6538 */
6539static void igb_io_resume(struct pci_dev *pdev)
6540{
6541 struct net_device *netdev = pci_get_drvdata(pdev);
6542 struct igb_adapter *adapter = netdev_priv(netdev);
6543
9d5c8243
AK		 6544 if (netif_running(netdev)) {
6545 if (igb_up(adapter)) {
6546 dev_err(&pdev->dev, "igb_up failed after reset\n");
6547 return;
6548 }
6549 }
6550
6551 netif_device_attach(netdev);
6552
6553 /* let the f/w know that the h/w is now under the control of the
6554 * driver. */
6555 igb_get_hw_control(adapter);
9d5c8243
AK		 6556}
6557
26ad9178
AD		 6558static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6559 u8 qsel)
6560{
6561 u32 rar_low, rar_high;
6562 struct e1000_hw *hw = &adapter->hw;
6563
6564 /* HW expects these in little endian so we reverse the byte order
6565 * from network order (big endian) to little endian
6566 */
6567 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6568 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6569 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6570
6571 /* Indicate to hardware the Address is Valid. */
6572 rar_high |= E1000_RAH_AV;
6573
6574 if (hw->mac.type == e1000_82575)
6575 rar_high |= E1000_RAH_POOL_1 * qsel;
6576 else
6577 rar_high |= E1000_RAH_POOL_1 << qsel;
6578
6579 wr32(E1000_RAL(index), rar_low);
6580 wrfl();
6581 wr32(E1000_RAH(index), rar_high);
6582 wrfl();
6583}
6584
4ae196df
AD		 6585static int igb_set_vf_mac(struct igb_adapter *adapter,
6586 int vf, unsigned char *mac_addr)
6587{
6588 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6589 /* VF MAC addresses start at end of receive addresses and moves
6590 * torwards the first, as a result a collision should not be possible */
6591 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6592
37680117 6593 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6594
26ad9178 6595 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6596
6597 return 0;
6598}
6599
8151d294
WM		 6600static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6601{
6602 struct igb_adapter *adapter = netdev_priv(netdev);
6603 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6604 return -EINVAL;
6605 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6606 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6607 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6608 " change effective.");
6609 if (test_bit(__IGB_DOWN, &adapter->state)) {
6610 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6611 " but the PF device is not up.\n");
6612 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6613 " attempting to use the VF device.\n");
6614 }
6615 return igb_set_vf_mac(adapter, vf, mac);
6616}
6617
17dc566c
LL		 6618static int igb_link_mbps(int internal_link_speed)
6619{
6620 switch (internal_link_speed) {
6621 case SPEED_100:
6622 return 100;
6623 case SPEED_1000:
6624 return 1000;
6625 default:
6626 return 0;
6627 }
6628}
6629
6630static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6631 int link_speed)
6632{
6633 int rf_dec, rf_int;
6634 u32 bcnrc_val;
6635
6636 if (tx_rate != 0) {
6637 /* Calculate the rate factor values to set */
6638 rf_int = link_speed / tx_rate;
6639 rf_dec = (link_speed - (rf_int * tx_rate));
6640 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6641
6642 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6643 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6644 E1000_RTTBCNRC_RF_INT_MASK);
6645 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6646 } else {
6647 bcnrc_val = 0;
6648 }
6649
6650 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
6651 wr32(E1000_RTTBCNRC, bcnrc_val);
6652}
6653
6654static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6655{
6656 int actual_link_speed, i;
6657 bool reset_rate = false;
6658
6659 /* VF TX rate limit was not set or not supported */
6660 if ((adapter->vf_rate_link_speed == 0) ||
6661 (adapter->hw.mac.type != e1000_82576))
6662 return;
6663
6664 actual_link_speed = igb_link_mbps(adapter->link_speed);
6665 if (actual_link_speed != adapter->vf_rate_link_speed) {
6666 reset_rate = true;
6667 adapter->vf_rate_link_speed = 0;
6668 dev_info(&adapter->pdev->dev,
6669 "Link speed has been changed. VF Transmit "
6670 "rate is disabled\n");
6671 }
6672
6673 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6674 if (reset_rate)
6675 adapter->vf_data[i].tx_rate = 0;
6676
6677 igb_set_vf_rate_limit(&adapter->hw, i,
6678 adapter->vf_data[i].tx_rate,
6679 actual_link_speed);
6680 }
6681}
6682
8151d294
WM		 6683static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6684{
17dc566c
LL		 6685 struct igb_adapter *adapter = netdev_priv(netdev);
6686 struct e1000_hw *hw = &adapter->hw;
6687 int actual_link_speed;
6688
6689 if (hw->mac.type != e1000_82576)
6690 return -EOPNOTSUPP;
6691
6692 actual_link_speed = igb_link_mbps(adapter->link_speed);
6693 if ((vf >= adapter->vfs_allocated_count) ||
6694 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6695 (tx_rate < 0) || (tx_rate > actual_link_speed))
6696 return -EINVAL;
6697
6698 adapter->vf_rate_link_speed = actual_link_speed;
6699 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
6700 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
6701
6702 return 0;
8151d294
WM		 6703}
6704
6705static int igb_ndo_get_vf_config(struct net_device *netdev,
6706 int vf, struct ifla_vf_info *ivi)
6707{
6708 struct igb_adapter *adapter = netdev_priv(netdev);
6709 if (vf >= adapter->vfs_allocated_count)
6710 return -EINVAL;
6711 ivi->vf = vf;
6712 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 6713 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 6714 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6715 ivi->qos = adapter->vf_data[vf].pf_qos;
6716 return 0;
6717}
6718
4ae196df
AD		 6719static void igb_vmm_control(struct igb_adapter *adapter)
6720{
6721 struct e1000_hw *hw = &adapter->hw;
10d8e907 6722 u32 reg;
4ae196df 6723
52a1dd4d
AD		 6724 switch (hw->mac.type) {
6725 case e1000_82575:
6726 default:
6727 /* replication is not supported for 82575 */
4ae196df 6728 return;
52a1dd4d
AD		 6729 case e1000_82576:
6730 /* notify HW that the MAC is adding vlan tags */
6731 reg = rd32(E1000_DTXCTL);
6732 reg |= E1000_DTXCTL_VLAN_ADDED;
6733 wr32(E1000_DTXCTL, reg);
6734 case e1000_82580:
6735 /* enable replication vlan tag stripping */
6736 reg = rd32(E1000_RPLOLR);
6737 reg |= E1000_RPLOLR_STRVLAN;
6738 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 6739 case e1000_i350:
6740 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 6741 break;
6742 }
10d8e907 6743
d4960307
AD		 6744 if (adapter->vfs_allocated_count) {
6745 igb_vmdq_set_loopback_pf(hw, true);
6746 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 6747 igb_vmdq_set_anti_spoofing_pf(hw, true,
6748 adapter->vfs_allocated_count);
d4960307
AD		 6749 } else {
6750 igb_vmdq_set_loopback_pf(hw, false);
6751 igb_vmdq_set_replication_pf(hw, false);
6752 }
4ae196df
AD		 6753}
6754
9d5c8243 6755/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)