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e1000: Removing the unused macro PAGE_USE_COUNT()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
71 {0, }
72};
73
74MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
75
76void igb_reset(struct igb_adapter *);
77static int igb_setup_all_tx_resources(struct igb_adapter *);
78static int igb_setup_all_rx_resources(struct igb_adapter *);
79static void igb_free_all_tx_resources(struct igb_adapter *);
80static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
109static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 110#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
421e02f0 114#endif /* CONFIG_IGB_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 119static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
120static void igb_tx_timeout(struct net_device *);
121static void igb_reset_task(struct work_struct *);
122static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
123static void igb_vlan_rx_add_vid(struct net_device *, u16);
124static void igb_vlan_rx_kill_vid(struct net_device *, u16);
125static void igb_restore_vlan(struct igb_adapter *);
126
127static int igb_suspend(struct pci_dev *, pm_message_t);
128#ifdef CONFIG_PM
129static int igb_resume(struct pci_dev *);
130#endif
131static void igb_shutdown(struct pci_dev *);
421e02f0 132#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 133static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
134static struct notifier_block dca_notifier = {
135 .notifier_call = igb_notify_dca,
136 .next = NULL,
137 .priority = 0
138};
139#endif
9d5c8243
AK		 140
141#ifdef CONFIG_NET_POLL_CONTROLLER
142/* for netdump / net console */
143static void igb_netpoll(struct net_device *);
144#endif
145
146static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
147 pci_channel_state_t);
148static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
149static void igb_io_resume(struct pci_dev *);
150
151static struct pci_error_handlers igb_err_handler = {
152 .error_detected = igb_io_error_detected,
153 .slot_reset = igb_io_slot_reset,
154 .resume = igb_io_resume,
155};
156
157
158static struct pci_driver igb_driver = {
159 .name = igb_driver_name,
160 .id_table = igb_pci_tbl,
161 .probe = igb_probe,
162 .remove = __devexit_p(igb_remove),
163#ifdef CONFIG_PM
164 /* Power Managment Hooks */
165 .suspend = igb_suspend,
166 .resume = igb_resume,
167#endif
168 .shutdown = igb_shutdown,
169 .err_handler = &igb_err_handler
170};
171
7dfc16fa
AD		 172static int global_quad_port_a; /* global quad port a indication */
173
9d5c8243
AK		 174MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
175MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
176MODULE_LICENSE("GPL");
177MODULE_VERSION(DRV_VERSION);
178
38c845c7
PO		 179/**
180 * Scale the NIC clock cycle by a large factor so that
181 * relatively small clock corrections can be added or
182 * substracted at each clock tick. The drawbacks of a
183 * large factor are a) that the clock register overflows
184 * more quickly (not such a big deal) and b) that the
185 * increment per tick has to fit into 24 bits.
186 *
187 * Note that
188 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
189 * IGB_TSYNC_SCALE
190 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
191 *
192 * The base scale factor is intentionally a power of two
193 * so that the division in %struct timecounter can be done with
194 * a shift.
195 */
196#define IGB_TSYNC_SHIFT (19)
197#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
198
199/**
200 * The duration of one clock cycle of the NIC.
201 *
202 * @todo This hard-coded value is part of the specification and might change
203 * in future hardware revisions. Add revision check.
204 */
205#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
206
207#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
208# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
209#endif
210
211/**
212 * igb_read_clock - read raw cycle counter (to be used by time counter)
213 */
214static cycle_t igb_read_clock(const struct cyclecounter *tc)
215{
216 struct igb_adapter *adapter =
217 container_of(tc, struct igb_adapter, cycles);
218 struct e1000_hw *hw = &adapter->hw;
219 u64 stamp;
220
221 stamp = rd32(E1000_SYSTIML);
222 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
223
224 return stamp;
225}
226
9d5c8243
AK		 227#ifdef DEBUG
228/**
229 * igb_get_hw_dev_name - return device name string
230 * used by hardware layer to print debugging information
231 **/
232char *igb_get_hw_dev_name(struct e1000_hw *hw)
233{
234 struct igb_adapter *adapter = hw->back;
235 return adapter->netdev->name;
236}
38c845c7
PO		 237
238/**
239 * igb_get_time_str - format current NIC and system time as string
240 */
241static char *igb_get_time_str(struct igb_adapter *adapter,
242 char buffer[160])
243{
244 cycle_t hw = adapter->cycles.read(&adapter->cycles);
245 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
246 struct timespec sys;
247 struct timespec delta;
248 getnstimeofday(&sys);
249
250 delta = timespec_sub(nic, sys);
251
252 sprintf(buffer,
33af6bcc
PO		 253 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
254 hw,
38c845c7
PO		 255 (long)nic.tv_sec, nic.tv_nsec,
256 (long)sys.tv_sec, sys.tv_nsec,
257 (long)delta.tv_sec, delta.tv_nsec);
258
259 return buffer;
260}
9d5c8243
AK		 261#endif
262
263/**
264 * igb_init_module - Driver Registration Routine
265 *
266 * igb_init_module is the first routine called when the driver is
267 * loaded. All it does is register with the PCI subsystem.
268 **/
269static int __init igb_init_module(void)
270{
271 int ret;
272 printk(KERN_INFO "%s - version %s\n",
273 igb_driver_string, igb_driver_version);
274
275 printk(KERN_INFO "%s\n", igb_copyright);
276
7dfc16fa
AD		 277 global_quad_port_a = 0;
278
421e02f0 279#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 280 dca_register_notify(&dca_notifier);
281#endif
bbd98fe4
AD		 282
283 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 284 return ret;
285}
286
287module_init(igb_init_module);
288
289/**
290 * igb_exit_module - Driver Exit Cleanup Routine
291 *
292 * igb_exit_module is called just before the driver is removed
293 * from memory.
294 **/
295static void __exit igb_exit_module(void)
296{
421e02f0 297#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 298 dca_unregister_notify(&dca_notifier);
299#endif
9d5c8243
AK		 300 pci_unregister_driver(&igb_driver);
301}
302
303module_exit(igb_exit_module);
304
26bc19ec
AD		 305#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
306/**
307 * igb_cache_ring_register - Descriptor ring to register mapping
308 * @adapter: board private structure to initialize
309 *
310 * Once we know the feature-set enabled for the device, we'll cache
311 * the register offset the descriptor ring is assigned to.
312 **/
313static void igb_cache_ring_register(struct igb_adapter *adapter)
314{
315 int i;
316
317 switch (adapter->hw.mac.type) {
318 case e1000_82576:
319 /* The queues are allocated for virtualization such that VF 0
320 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
321 * In order to avoid collision we start at the first free queue
322 * and continue consuming queues in the same sequence
323 */
324 for (i = 0; i < adapter->num_rx_queues; i++)
325 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
326 for (i = 0; i < adapter->num_tx_queues; i++)
327 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
328 break;
329 case e1000_82575:
330 default:
331 for (i = 0; i < adapter->num_rx_queues; i++)
332 adapter->rx_ring[i].reg_idx = i;
333 for (i = 0; i < adapter->num_tx_queues; i++)
334 adapter->tx_ring[i].reg_idx = i;
335 break;
336 }
337}
338
9d5c8243
AK		 339/**
340 * igb_alloc_queues - Allocate memory for all rings
341 * @adapter: board private structure to initialize
342 *
343 * We allocate one ring per queue at run-time since we don't know the
344 * number of queues at compile-time.
345 **/
346static int igb_alloc_queues(struct igb_adapter *adapter)
347{
348 int i;
349
350 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
351 sizeof(struct igb_ring), GFP_KERNEL);
352 if (!adapter->tx_ring)
353 return -ENOMEM;
354
355 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
356 sizeof(struct igb_ring), GFP_KERNEL);
357 if (!adapter->rx_ring) {
358 kfree(adapter->tx_ring);
359 return -ENOMEM;
360 }
361
6eb5a7f1
AD		 362 adapter->rx_ring->buddy = adapter->tx_ring;
363
661086df
PWJ		 364 for (i = 0; i < adapter->num_tx_queues; i++) {
365 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 366 ring->count = adapter->tx_ring_count;
661086df
PWJ		 367 ring->adapter = adapter;
368 ring->queue_index = i;
369 }
9d5c8243
AK		 370 for (i = 0; i < adapter->num_rx_queues; i++) {
371 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 372 ring->count = adapter->rx_ring_count;
9d5c8243 373 ring->adapter = adapter;
844290e5 374 ring->queue_index = i;
9d5c8243
AK		 375 ring->itr_register = E1000_ITR;
376
844290e5 377 /* set a default napi handler for each rx_ring */
661086df 378 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 379 }
26bc19ec
AD		 380
381 igb_cache_ring_register(adapter);
9d5c8243
AK		 382 return 0;
383}
384
a88f10ec
AD		 385static void igb_free_queues(struct igb_adapter *adapter)
386{
387 int i;
388
389 for (i = 0; i < adapter->num_rx_queues; i++)
390 netif_napi_del(&adapter->rx_ring[i].napi);
391
392 kfree(adapter->tx_ring);
393 kfree(adapter->rx_ring);
394}
395
9d5c8243
AK		 396#define IGB_N0_QUEUE -1
397static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
398 int tx_queue, int msix_vector)
399{
400 u32 msixbm = 0;
401 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 402 u32 ivar, index;
403
404 switch (hw->mac.type) {
405 case e1000_82575:
9d5c8243
AK		 406 /* The 82575 assigns vectors using a bitmask, which matches the
407 bitmask for the EICR/EIMS/EIMC registers. To assign one
408 or more queues to a vector, we write the appropriate bits
409 into the MSIXBM register for that vector. */
410 if (rx_queue > IGB_N0_QUEUE) {
411 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
412 adapter->rx_ring[rx_queue].eims_value = msixbm;
413 }
414 if (tx_queue > IGB_N0_QUEUE) {
415 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
416 adapter->tx_ring[tx_queue].eims_value =
417 E1000_EICR_TX_QUEUE0 << tx_queue;
418 }
419 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 420 break;
421 case e1000_82576:
26bc19ec 422 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 423 Each queue has a single entry in the table to which we write
424 a vector number along with a "valid" bit. Sadly, the layout
425 of the table is somewhat counterintuitive. */
426 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 427 index = (rx_queue >> 1);
2d064c06 428 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 429 if (rx_queue & 0x1) {
2d064c06
AD		 430 /* vector goes into third byte of register */
431 ivar = ivar & 0xFF00FFFF;
432 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 433 } else {
434 /* vector goes into low byte of register */
435 ivar = ivar & 0xFFFFFF00;
436 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 437 }
438 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
439 array_wr32(E1000_IVAR0, index, ivar);
440 }
441 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 442 index = (tx_queue >> 1);
2d064c06 443 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 444 if (tx_queue & 0x1) {
2d064c06
AD		 445 /* vector goes into high byte of register */
446 ivar = ivar & 0x00FFFFFF;
447 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 448 } else {
449 /* vector goes into second byte of register */
450 ivar = ivar & 0xFFFF00FF;
451 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 452 }
453 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
454 array_wr32(E1000_IVAR0, index, ivar);
455 }
456 break;
457 default:
458 BUG();
459 break;
460 }
9d5c8243
AK		 461}
462
463/**
464 * igb_configure_msix - Configure MSI-X hardware
465 *
466 * igb_configure_msix sets up the hardware to properly
467 * generate MSI-X interrupts.
468 **/
469static void igb_configure_msix(struct igb_adapter *adapter)
470{
471 u32 tmp;
472 int i, vector = 0;
473 struct e1000_hw *hw = &adapter->hw;
474
475 adapter->eims_enable_mask = 0;
2d064c06
AD		 476 if (hw->mac.type == e1000_82576)
477 /* Turn on MSI-X capability first, or our settings
478 * won't stick. And it will take days to debug. */
479 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 480 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 481 E1000_GPIE_NSICR);
9d5c8243
AK		 482
483 for (i = 0; i < adapter->num_tx_queues; i++) {
484 struct igb_ring *tx_ring = &adapter->tx_ring[i];
485 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
486 adapter->eims_enable_mask |= tx_ring->eims_value;
487 if (tx_ring->itr_val)
6eb5a7f1 488 writel(tx_ring->itr_val,
9d5c8243
AK		 489 hw->hw_addr + tx_ring->itr_register);
490 else
491 writel(1, hw->hw_addr + tx_ring->itr_register);
492 }
493
494 for (i = 0; i < adapter->num_rx_queues; i++) {
495 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 496 rx_ring->buddy = NULL;
9d5c8243
AK		 497 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
498 adapter->eims_enable_mask |= rx_ring->eims_value;
499 if (rx_ring->itr_val)
6eb5a7f1 500 writel(rx_ring->itr_val,
9d5c8243
AK		 501 hw->hw_addr + rx_ring->itr_register);
502 else
503 writel(1, hw->hw_addr + rx_ring->itr_register);
504 }
505
506
507 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 508 switch (hw->mac.type) {
509 case e1000_82575:
9d5c8243
AK		 510 array_wr32(E1000_MSIXBM(0), vector++,
511 E1000_EIMS_OTHER);
512
9d5c8243
AK		 513 tmp = rd32(E1000_CTRL_EXT);
514 /* enable MSI-X PBA support*/
515 tmp |= E1000_CTRL_EXT_PBA_CLR;
516
517 /* Auto-Mask interrupts upon ICR read. */
518 tmp |= E1000_CTRL_EXT_EIAME;
519 tmp |= E1000_CTRL_EXT_IRCA;
520
521 wr32(E1000_CTRL_EXT, tmp);
522 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 523 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 524
2d064c06
AD		 525 break;
526
527 case e1000_82576:
528 tmp = (vector++ | E1000_IVAR_VALID) << 8;
529 wr32(E1000_IVAR_MISC, tmp);
530
531 adapter->eims_enable_mask = (1 << (vector)) - 1;
532 adapter->eims_other = 1 << (vector - 1);
533 break;
534 default:
535 /* do nothing, since nothing else supports MSI-X */
536 break;
537 } /* switch (hw->mac.type) */
9d5c8243
AK		 538 wrfl();
539}
540
541/**
542 * igb_request_msix - Initialize MSI-X interrupts
543 *
544 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
545 * kernel.
546 **/
547static int igb_request_msix(struct igb_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 int i, err = 0, vector = 0;
551
552 vector = 0;
553
554 for (i = 0; i < adapter->num_tx_queues; i++) {
555 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 556 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 557 err = request_irq(adapter->msix_entries[vector].vector,
558 &igb_msix_tx, 0, ring->name,
559 &(adapter->tx_ring[i]));
560 if (err)
561 goto out;
562 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 563 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 564 vector++;
565 }
566 for (i = 0; i < adapter->num_rx_queues; i++) {
567 struct igb_ring *ring = &(adapter->rx_ring[i]);
568 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 569 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 570 else
571 memcpy(ring->name, netdev->name, IFNAMSIZ);
572 err = request_irq(adapter->msix_entries[vector].vector,
573 &igb_msix_rx, 0, ring->name,
574 &(adapter->rx_ring[i]));
575 if (err)
576 goto out;
577 ring->itr_register = E1000_EITR(0) + (vector << 2);
578 ring->itr_val = adapter->itr;
844290e5
PW		 579 /* overwrite the poll routine for MSIX, we've already done
580 * netif_napi_add */
581 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 582 vector++;
583 }
584
585 err = request_irq(adapter->msix_entries[vector].vector,
586 &igb_msix_other, 0, netdev->name, netdev);
587 if (err)
588 goto out;
589
9d5c8243
AK		 590 igb_configure_msix(adapter);
591 return 0;
592out:
593 return err;
594}
595
596static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
597{
598 if (adapter->msix_entries) {
599 pci_disable_msix(adapter->pdev);
600 kfree(adapter->msix_entries);
601 adapter->msix_entries = NULL;
7dfc16fa 602 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 603 pci_disable_msi(adapter->pdev);
604 return;
605}
606
607
608/**
609 * igb_set_interrupt_capability - set MSI or MSI-X if supported
610 *
611 * Attempt to configure interrupts using the best available
612 * capabilities of the hardware and kernel.
613 **/
614static void igb_set_interrupt_capability(struct igb_adapter *adapter)
615{
616 int err;
617 int numvecs, i;
618
83b7180d
AD		 619 /* Number of supported queues. */
620 /* Having more queues than CPUs doesn't make sense. */
621 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
622 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
623
9d5c8243
AK		 624 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
625 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
626 GFP_KERNEL);
627 if (!adapter->msix_entries)
628 goto msi_only;
629
630 for (i = 0; i < numvecs; i++)
631 adapter->msix_entries[i].entry = i;
632
633 err = pci_enable_msix(adapter->pdev,
634 adapter->msix_entries,
635 numvecs);
636 if (err == 0)
34a20e89 637 goto out;
9d5c8243
AK		 638
639 igb_reset_interrupt_capability(adapter);
640
641 /* If we can't do MSI-X, try MSI */
642msi_only:
643 adapter->num_rx_queues = 1;
661086df 644 adapter->num_tx_queues = 1;
9d5c8243 645 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 646 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 647out:
661086df 648 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 649 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 650 return;
651}
652
653/**
654 * igb_request_irq - initialize interrupts
655 *
656 * Attempts to configure interrupts using the best available
657 * capabilities of the hardware and kernel.
658 **/
659static int igb_request_irq(struct igb_adapter *adapter)
660{
661 struct net_device *netdev = adapter->netdev;
662 struct e1000_hw *hw = &adapter->hw;
663 int err = 0;
664
665 if (adapter->msix_entries) {
666 err = igb_request_msix(adapter);
844290e5 667 if (!err)
9d5c8243 668 goto request_done;
9d5c8243
AK		 669 /* fall back to MSI */
670 igb_reset_interrupt_capability(adapter);
671 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 672 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 673 igb_free_all_tx_resources(adapter);
674 igb_free_all_rx_resources(adapter);
675 adapter->num_rx_queues = 1;
676 igb_alloc_queues(adapter);
844290e5 677 } else {
2d064c06
AD		 678 switch (hw->mac.type) {
679 case e1000_82575:
680 wr32(E1000_MSIXBM(0),
681 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
682 break;
683 case e1000_82576:
684 wr32(E1000_IVAR0, E1000_IVAR_VALID);
685 break;
686 default:
687 break;
688 }
9d5c8243 689 }
844290e5 690
7dfc16fa 691 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 692 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
693 netdev->name, netdev);
694 if (!err)
695 goto request_done;
696 /* fall back to legacy interrupts */
697 igb_reset_interrupt_capability(adapter);
7dfc16fa 698 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 699 }
700
701 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
702 netdev->name, netdev);
703
6cb5e577 704 if (err)
9d5c8243
AK		 705 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
706 err);
9d5c8243
AK		 707
708request_done:
709 return err;
710}
711
712static void igb_free_irq(struct igb_adapter *adapter)
713{
714 struct net_device *netdev = adapter->netdev;
715
716 if (adapter->msix_entries) {
717 int vector = 0, i;
718
719 for (i = 0; i < adapter->num_tx_queues; i++)
720 free_irq(adapter->msix_entries[vector++].vector,
721 &(adapter->tx_ring[i]));
722 for (i = 0; i < adapter->num_rx_queues; i++)
723 free_irq(adapter->msix_entries[vector++].vector,
724 &(adapter->rx_ring[i]));
725
726 free_irq(adapter->msix_entries[vector++].vector, netdev);
727 return;
728 }
729
730 free_irq(adapter->pdev->irq, netdev);
731}
732
733/**
734 * igb_irq_disable - Mask off interrupt generation on the NIC
735 * @adapter: board private structure
736 **/
737static void igb_irq_disable(struct igb_adapter *adapter)
738{
739 struct e1000_hw *hw = &adapter->hw;
740
741 if (adapter->msix_entries) {
844290e5 742 wr32(E1000_EIAM, 0);
9d5c8243
AK		 743 wr32(E1000_EIMC, ~0);
744 wr32(E1000_EIAC, 0);
745 }
844290e5
PW		 746
747 wr32(E1000_IAM, 0);
9d5c8243
AK		 748 wr32(E1000_IMC, ~0);
749 wrfl();
750 synchronize_irq(adapter->pdev->irq);
751}
752
753/**
754 * igb_irq_enable - Enable default interrupt generation settings
755 * @adapter: board private structure
756 **/
757static void igb_irq_enable(struct igb_adapter *adapter)
758{
759 struct e1000_hw *hw = &adapter->hw;
760
761 if (adapter->msix_entries) {
844290e5
PW		 762 wr32(E1000_EIAC, adapter->eims_enable_mask);
763 wr32(E1000_EIAM, adapter->eims_enable_mask);
764 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 765 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 766 } else {
767 wr32(E1000_IMS, IMS_ENABLE_MASK);
768 wr32(E1000_IAM, IMS_ENABLE_MASK);
769 }
9d5c8243
AK		 770}
771
772static void igb_update_mng_vlan(struct igb_adapter *adapter)
773{
774 struct net_device *netdev = adapter->netdev;
775 u16 vid = adapter->hw.mng_cookie.vlan_id;
776 u16 old_vid = adapter->mng_vlan_id;
777 if (adapter->vlgrp) {
778 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
779 if (adapter->hw.mng_cookie.status &
780 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
781 igb_vlan_rx_add_vid(netdev, vid);
782 adapter->mng_vlan_id = vid;
783 } else
784 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
785
786 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
787 (vid != old_vid) &&
788 !vlan_group_get_device(adapter->vlgrp, old_vid))
789 igb_vlan_rx_kill_vid(netdev, old_vid);
790 } else
791 adapter->mng_vlan_id = vid;
792 }
793}
794
795/**
796 * igb_release_hw_control - release control of the h/w to f/w
797 * @adapter: address of board private structure
798 *
799 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
800 * For ASF and Pass Through versions of f/w this means that the
801 * driver is no longer loaded.
802 *
803 **/
804static void igb_release_hw_control(struct igb_adapter *adapter)
805{
806 struct e1000_hw *hw = &adapter->hw;
807 u32 ctrl_ext;
808
809 /* Let firmware take over control of h/w */
810 ctrl_ext = rd32(E1000_CTRL_EXT);
811 wr32(E1000_CTRL_EXT,
812 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
813}
814
815
816/**
817 * igb_get_hw_control - get control of the h/w from f/w
818 * @adapter: address of board private structure
819 *
820 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
821 * For ASF and Pass Through versions of f/w this means that
822 * the driver is loaded.
823 *
824 **/
825static void igb_get_hw_control(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 u32 ctrl_ext;
829
830 /* Let firmware know the driver has taken over */
831 ctrl_ext = rd32(E1000_CTRL_EXT);
832 wr32(E1000_CTRL_EXT,
833 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
834}
835
9d5c8243
AK		 836/**
837 * igb_configure - configure the hardware for RX and TX
838 * @adapter: private board structure
839 **/
840static void igb_configure(struct igb_adapter *adapter)
841{
842 struct net_device *netdev = adapter->netdev;
843 int i;
844
845 igb_get_hw_control(adapter);
846 igb_set_multi(netdev);
847
848 igb_restore_vlan(adapter);
9d5c8243
AK		 849
850 igb_configure_tx(adapter);
851 igb_setup_rctl(adapter);
852 igb_configure_rx(adapter);
662d7205
AD		 853
854 igb_rx_fifo_flush_82575(&adapter->hw);
855
9d5c8243
AK		 856 /* call IGB_DESC_UNUSED which always leaves
857 * at least 1 descriptor unused to make sure
858 * next_to_use != next_to_clean */
859 for (i = 0; i < adapter->num_rx_queues; i++) {
860 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 861 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 862 }
863
864
865 adapter->tx_queue_len = netdev->tx_queue_len;
866}
867
868
869/**
870 * igb_up - Open the interface and prepare it to handle traffic
871 * @adapter: board private structure
872 **/
873
874int igb_up(struct igb_adapter *adapter)
875{
876 struct e1000_hw *hw = &adapter->hw;
877 int i;
878
879 /* hardware has been reset, we need to reload some things */
880 igb_configure(adapter);
881
882 clear_bit(__IGB_DOWN, &adapter->state);
883
844290e5
PW		 884 for (i = 0; i < adapter->num_rx_queues; i++)
885 napi_enable(&adapter->rx_ring[i].napi);
886 if (adapter->msix_entries)
9d5c8243 887 igb_configure_msix(adapter);
9d5c8243
AK		 888
889 /* Clear any pending interrupts. */
890 rd32(E1000_ICR);
891 igb_irq_enable(adapter);
892
893 /* Fire a link change interrupt to start the watchdog. */
894 wr32(E1000_ICS, E1000_ICS_LSC);
895 return 0;
896}
897
898void igb_down(struct igb_adapter *adapter)
899{
900 struct e1000_hw *hw = &adapter->hw;
901 struct net_device *netdev = adapter->netdev;
902 u32 tctl, rctl;
903 int i;
904
905 /* signal that we're down so the interrupt handler does not
906 * reschedule our watchdog timer */
907 set_bit(__IGB_DOWN, &adapter->state);
908
909 /* disable receives in the hardware */
910 rctl = rd32(E1000_RCTL);
911 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
912 /* flush and sleep below */
913
fd2ea0a7 914 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 915
916 /* disable transmits in the hardware */
917 tctl = rd32(E1000_TCTL);
918 tctl &= ~E1000_TCTL_EN;
919 wr32(E1000_TCTL, tctl);
920 /* flush both disables and wait for them to finish */
921 wrfl();
922 msleep(10);
923
844290e5
PW		 924 for (i = 0; i < adapter->num_rx_queues; i++)
925 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 926
9d5c8243
AK		 927 igb_irq_disable(adapter);
928
929 del_timer_sync(&adapter->watchdog_timer);
930 del_timer_sync(&adapter->phy_info_timer);
931
932 netdev->tx_queue_len = adapter->tx_queue_len;
933 netif_carrier_off(netdev);
04fe6358
AD		 934
935 /* record the stats before reset*/
936 igb_update_stats(adapter);
937
9d5c8243
AK		 938 adapter->link_speed = 0;
939 adapter->link_duplex = 0;
940
3023682e
JK		 941 if (!pci_channel_offline(adapter->pdev))
942 igb_reset(adapter);
9d5c8243
AK		 943 igb_clean_all_tx_rings(adapter);
944 igb_clean_all_rx_rings(adapter);
945}
946
947void igb_reinit_locked(struct igb_adapter *adapter)
948{
949 WARN_ON(in_interrupt());
950 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
951 msleep(1);
952 igb_down(adapter);
953 igb_up(adapter);
954 clear_bit(__IGB_RESETTING, &adapter->state);
955}
956
957void igb_reset(struct igb_adapter *adapter)
958{
959 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 960 struct e1000_mac_info *mac = &hw->mac;
961 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 962 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
963 u16 hwm;
964
965 /* Repartition Pba for greater than 9k mtu
966 * To take effect CTRL.RST is required.
967 */
fa4dfae0
AD		 968 switch (mac->type) {
969 case e1000_82576:
2d064c06 970 pba = E1000_PBA_64K;
fa4dfae0
AD		 971 break;
972 case e1000_82575:
973 default:
974 pba = E1000_PBA_34K;
975 break;
2d064c06 976 }
9d5c8243 977
2d064c06
AD		 978 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
979 (mac->type < e1000_82576)) {
9d5c8243
AK		 980 /* adjust PBA for jumbo frames */
981 wr32(E1000_PBA, pba);
982
983 /* To maintain wire speed transmits, the Tx FIFO should be
984 * large enough to accommodate two full transmit packets,
985 * rounded up to the next 1KB and expressed in KB. Likewise,
986 * the Rx FIFO should be large enough to accommodate at least
987 * one full receive packet and is similarly rounded up and
988 * expressed in KB. */
989 pba = rd32(E1000_PBA);
990 /* upper 16 bits has Tx packet buffer allocation size in KB */
991 tx_space = pba >> 16;
992 /* lower 16 bits has Rx packet buffer allocation size in KB */
993 pba &= 0xffff;
994 /* the tx fifo also stores 16 bytes of information about the tx
995 * but don't include ethernet FCS because hardware appends it */
996 min_tx_space = (adapter->max_frame_size +
85e8d004 997 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 998 ETH_FCS_LEN) * 2;
999 min_tx_space = ALIGN(min_tx_space, 1024);
1000 min_tx_space >>= 10;
1001 /* software strips receive CRC, so leave room for it */
1002 min_rx_space = adapter->max_frame_size;
1003 min_rx_space = ALIGN(min_rx_space, 1024);
1004 min_rx_space >>= 10;
1005
1006 /* If current Tx allocation is less than the min Tx FIFO size,
1007 * and the min Tx FIFO size is less than the current Rx FIFO
1008 * allocation, take space away from current Rx allocation */
1009 if (tx_space < min_tx_space &&
1010 ((min_tx_space - tx_space) < pba)) {
1011 pba = pba - (min_tx_space - tx_space);
1012
1013 /* if short on rx space, rx wins and must trump tx
1014 * adjustment */
1015 if (pba < min_rx_space)
1016 pba = min_rx_space;
1017 }
2d064c06 1018 wr32(E1000_PBA, pba);
9d5c8243 1019 }
9d5c8243
AK		 1020
1021 /* flow control settings */
1022 /* The high water mark must be low enough to fit one full frame
1023 * (or the size used for early receive) above it in the Rx FIFO.
1024 * Set it to the lower of:
1025 * - 90% of the Rx FIFO size, or
1026 * - the full Rx FIFO size minus one full frame */
1027 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1028 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1029
2d064c06
AD		 1030 if (mac->type < e1000_82576) {
1031 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1032 fc->low_water = fc->high_water - 8;
1033 } else {
1034 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1035 fc->low_water = fc->high_water - 16;
1036 }
9d5c8243
AK		 1037 fc->pause_time = 0xFFFF;
1038 fc->send_xon = 1;
1039 fc->type = fc->original_type;
1040
1041 /* Allow time for pending master requests to run */
1042 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1043 wr32(E1000_WUC, 0);
1044
1045 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1046 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1047
1048 igb_update_mng_vlan(adapter);
1049
1050 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1051 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1052
1053 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1054 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1055}
1056
2e5c6922
SH		 1057static const struct net_device_ops igb_netdev_ops = {
1058 .ndo_open = igb_open,
1059 .ndo_stop = igb_close,
00829823 1060 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1061 .ndo_get_stats = igb_get_stats,
1062 .ndo_set_multicast_list = igb_set_multi,
1063 .ndo_set_mac_address = igb_set_mac,
1064 .ndo_change_mtu = igb_change_mtu,
1065 .ndo_do_ioctl = igb_ioctl,
1066 .ndo_tx_timeout = igb_tx_timeout,
1067 .ndo_validate_addr = eth_validate_addr,
1068 .ndo_vlan_rx_register = igb_vlan_rx_register,
1069 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1070 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1071#ifdef CONFIG_NET_POLL_CONTROLLER
1072 .ndo_poll_controller = igb_netpoll,
1073#endif
1074};
1075
9d5c8243
AK		 1076/**
1077 * igb_probe - Device Initialization Routine
1078 * @pdev: PCI device information struct
1079 * @ent: entry in igb_pci_tbl
1080 *
1081 * Returns 0 on success, negative on failure
1082 *
1083 * igb_probe initializes an adapter identified by a pci_dev structure.
1084 * The OS initialization, configuring of the adapter private structure,
1085 * and a hardware reset occur.
1086 **/
1087static int __devinit igb_probe(struct pci_dev *pdev,
1088 const struct pci_device_id *ent)
1089{
1090 struct net_device *netdev;
1091 struct igb_adapter *adapter;
1092 struct e1000_hw *hw;
c54106bb 1093 struct pci_dev *us_dev;
9d5c8243
AK		 1094 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1095 unsigned long mmio_start, mmio_len;
450c87c8 1096 int err, pci_using_dac, pos;
c54106bb 1097 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1098 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1099 u32 part_num;
1100
aed5dec3 1101 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1102 if (err)
1103 return err;
1104
1105 pci_using_dac = 0;
1106 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1107 if (!err) {
1108 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1109 if (!err)
1110 pci_using_dac = 1;
1111 } else {
1112 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1113 if (err) {
1114 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1115 if (err) {
1116 dev_err(&pdev->dev, "No usable DMA "
1117 "configuration, aborting\n");
1118 goto err_dma;
1119 }
1120 }
1121 }
1122
c54106bb
AD		 1123 /* 82575 requires that the pci-e link partner disable the L0s state */
1124 switch (pdev->device) {
1125 case E1000_DEV_ID_82575EB_COPPER:
1126 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1127 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1128 us_dev = pdev->bus->self;
1129 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1130 if (pos) {
1131 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1132 &state);
1133 state &= ~PCIE_LINK_STATE_L0S;
1134 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1135 state);
ac450208
BH		 1136 dev_info(&pdev->dev,
1137 "Disabling ASPM L0s upstream switch port %s\n",
1138 pci_name(us_dev));
c54106bb
AD		 1139 }
1140 default:
1141 break;
1142 }
1143
aed5dec3
AD		 1144 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1145 IORESOURCE_MEM),
1146 igb_driver_name);
9d5c8243
AK		 1147 if (err)
1148 goto err_pci_reg;
1149
ea943d41
JK		 1150 err = pci_enable_pcie_error_reporting(pdev);
1151 if (err) {
1152 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1153 "0x%x\n", err);
1154 /* non-fatal, continue */
1155 }
40a914fa 1156
9d5c8243 1157 pci_set_master(pdev);
c682fc23 1158 pci_save_state(pdev);
9d5c8243
AK		 1159
1160 err = -ENOMEM;
661086df 1161 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1162 if (!netdev)
1163 goto err_alloc_etherdev;
1164
1165 SET_NETDEV_DEV(netdev, &pdev->dev);
1166
1167 pci_set_drvdata(pdev, netdev);
1168 adapter = netdev_priv(netdev);
1169 adapter->netdev = netdev;
1170 adapter->pdev = pdev;
1171 hw = &adapter->hw;
1172 hw->back = adapter;
1173 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1174
1175 mmio_start = pci_resource_start(pdev, 0);
1176 mmio_len = pci_resource_len(pdev, 0);
1177
1178 err = -EIO;
28b0759c
AD		 1179 hw->hw_addr = ioremap(mmio_start, mmio_len);
1180 if (!hw->hw_addr)
9d5c8243
AK		 1181 goto err_ioremap;
1182
2e5c6922 1183 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1184 igb_set_ethtool_ops(netdev);
9d5c8243 1185 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1186
1187 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1188
1189 netdev->mem_start = mmio_start;
1190 netdev->mem_end = mmio_start + mmio_len;
1191
9d5c8243
AK		 1192 /* PCI config space info */
1193 hw->vendor_id = pdev->vendor;
1194 hw->device_id = pdev->device;
1195 hw->revision_id = pdev->revision;
1196 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1197 hw->subsystem_device_id = pdev->subsystem_device;
1198
1199 /* setup the private structure */
1200 hw->back = adapter;
1201 /* Copy the default MAC, PHY and NVM function pointers */
1202 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1203 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1204 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1205 /* Initialize skew-specific constants */
1206 err = ei->get_invariants(hw);
1207 if (err)
450c87c8 1208 goto err_sw_init;
9d5c8243 1209
450c87c8 1210 /* setup the private structure */
9d5c8243
AK		 1211 err = igb_sw_init(adapter);
1212 if (err)
1213 goto err_sw_init;
1214
1215 igb_get_bus_info_pcie(hw);
1216
7dfc16fa
AD		 1217 /* set flags */
1218 switch (hw->mac.type) {
7dfc16fa 1219 case e1000_82575:
7dfc16fa
AD		 1220 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1221 break;
bbd98fe4 1222 case e1000_82576:
7dfc16fa
AD		 1223 default:
1224 break;
1225 }
1226
9d5c8243
AK		 1227 hw->phy.autoneg_wait_to_complete = false;
1228 hw->mac.adaptive_ifs = true;
1229
1230 /* Copper options */
1231 if (hw->phy.media_type == e1000_media_type_copper) {
1232 hw->phy.mdix = AUTO_ALL_MODES;
1233 hw->phy.disable_polarity_correction = false;
1234 hw->phy.ms_type = e1000_ms_hw_default;
1235 }
1236
1237 if (igb_check_reset_block(hw))
1238 dev_info(&pdev->dev,
1239 "PHY reset is blocked due to SOL/IDER session.\n");
1240
1241 netdev->features = NETIF_F_SG |
7d8eb29e 1242 NETIF_F_IP_CSUM |
9d5c8243
AK		 1243 NETIF_F_HW_VLAN_TX |
1244 NETIF_F_HW_VLAN_RX |
1245 NETIF_F_HW_VLAN_FILTER;
1246
7d8eb29e 1247 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1248 netdev->features |= NETIF_F_TSO;
9d5c8243 1249 netdev->features |= NETIF_F_TSO6;
48f29ffc 1250
5c0999b7 1251 netdev->features |= NETIF_F_GRO;
d3352520 1252
48f29ffc
JK		 1253 netdev->vlan_features |= NETIF_F_TSO;
1254 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1255 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1256 netdev->vlan_features |= NETIF_F_SG;
1257
9d5c8243
AK		 1258 if (pci_using_dac)
1259 netdev->features |= NETIF_F_HIGHDMA;
1260
9d5c8243
AK		 1261 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1262
1263 /* before reading the NVM, reset the controller to put the device in a
1264 * known good starting state */
1265 hw->mac.ops.reset_hw(hw);
1266
1267 /* make sure the NVM is good */
1268 if (igb_validate_nvm_checksum(hw) < 0) {
1269 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1270 err = -EIO;
1271 goto err_eeprom;
1272 }
1273
1274 /* copy the MAC address out of the NVM */
1275 if (hw->mac.ops.read_mac_addr(hw))
1276 dev_err(&pdev->dev, "NVM Read Error\n");
1277
1278 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1279 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1280
1281 if (!is_valid_ether_addr(netdev->perm_addr)) {
1282 dev_err(&pdev->dev, "Invalid MAC Address\n");
1283 err = -EIO;
1284 goto err_eeprom;
1285 }
1286
1287 init_timer(&adapter->watchdog_timer);
1288 adapter->watchdog_timer.function = &igb_watchdog;
1289 adapter->watchdog_timer.data = (unsigned long) adapter;
1290
1291 init_timer(&adapter->phy_info_timer);
1292 adapter->phy_info_timer.function = &igb_update_phy_info;
1293 adapter->phy_info_timer.data = (unsigned long) adapter;
1294
1295 INIT_WORK(&adapter->reset_task, igb_reset_task);
1296 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1297
450c87c8 1298 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1299 adapter->fc_autoneg = true;
1300 hw->mac.autoneg = true;
1301 hw->phy.autoneg_advertised = 0x2f;
1302
1303 hw->fc.original_type = e1000_fc_default;
1304 hw->fc.type = e1000_fc_default;
1305
cbd347ad 1306 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1307 adapter->itr = IGB_START_ITR;
1308
1309 igb_validate_mdi_setting(hw);
1310
1311 adapter->rx_csum = 1;
1312
1313 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1314 * enable the ACPI Magic Packet filter
1315 */
1316
1317 if (hw->bus.func == 0 ||
1318 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1319 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1320
1321 if (eeprom_data & eeprom_apme_mask)
1322 adapter->eeprom_wol |= E1000_WUFC_MAG;
1323
1324 /* now that we have the eeprom settings, apply the special cases where
1325 * the eeprom may be wrong or the board simply won't support wake on
1326 * lan on a particular port */
1327 switch (pdev->device) {
1328 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1329 adapter->eeprom_wol = 0;
1330 break;
1331 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1332 case E1000_DEV_ID_82576_FIBER:
1333 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1334 /* Wake events only supported on port A for dual fiber
1335 * regardless of eeprom setting */
1336 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1337 adapter->eeprom_wol = 0;
1338 break;
1339 }
1340
1341 /* initialize the wol settings based on the eeprom settings */
1342 adapter->wol = adapter->eeprom_wol;
e1b86d84 1343 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1344
1345 /* reset the hardware with the new settings */
1346 igb_reset(adapter);
1347
1348 /* let the f/w know that the h/w is now under the control of the
1349 * driver. */
1350 igb_get_hw_control(adapter);
1351
1352 /* tell the stack to leave us alone until igb_open() is called */
1353 netif_carrier_off(netdev);
fd2ea0a7 1354 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1355
1356 strcpy(netdev->name, "eth%d");
1357 err = register_netdev(netdev);
1358 if (err)
1359 goto err_register;
1360
421e02f0 1361#ifdef CONFIG_IGB_DCA
bbd98fe4 1362 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1363 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1364 dev_info(&pdev->dev, "DCA enabled\n");
1365 /* Always use CB2 mode, difference is masked
1366 * in the CB driver. */
cbd347ad 1367 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6
JC		 1368 igb_setup_dca(adapter);
1369 }
1370#endif
1371
38c845c7
PO		 1372 /*
1373 * Initialize hardware timer: we keep it running just in case
1374 * that some program needs it later on.
1375 */
1376 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1377 adapter->cycles.read = igb_read_clock;
1378 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1379 adapter->cycles.mult = 1;
1380 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1381 wr32(E1000_TIMINCA,
1382 (1<<24) |
1383 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1384#if 0
1385 /*
1386 * Avoid rollover while we initialize by resetting the time counter.
1387 */
1388 wr32(E1000_SYSTIML, 0x00000000);
1389 wr32(E1000_SYSTIMH, 0x00000000);
1390#else
1391 /*
1392 * Set registers so that rollover occurs soon to test this.
1393 */
1394 wr32(E1000_SYSTIML, 0x00000000);
1395 wr32(E1000_SYSTIMH, 0xFF800000);
1396#endif
1397 wrfl();
1398 timecounter_init(&adapter->clock,
1399 &adapter->cycles,
1400 ktime_to_ns(ktime_get_real()));
1401
33af6bcc
PO		 1402 /*
1403 * Synchronize our NIC clock against system wall clock. NIC
1404 * time stamp reading requires ~3us per sample, each sample
1405 * was pretty stable even under load => only require 10
1406 * samples for each offset comparison.
1407 */
1408 memset(&adapter->compare, 0, sizeof(adapter->compare));
1409 adapter->compare.source = &adapter->clock;
1410 adapter->compare.target = ktime_get_real;
1411 adapter->compare.num_samples = 10;
1412 timecompare_update(&adapter->compare, 0);
1413
38c845c7
PO		 1414#ifdef DEBUG
1415 {
1416 char buffer[160];
1417 printk(KERN_DEBUG
1418 "igb: %s: hw %p initialized timer\n",
1419 igb_get_time_str(adapter, buffer),
1420 &adapter->hw);
1421 }
1422#endif
1423
9d5c8243
AK		 1424 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1425 /* print bus type/speed/width info */
7c510e4b 1426 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1427 netdev->name,
1428 ((hw->bus.speed == e1000_bus_speed_2500)
1429 ? "2.5Gb/s" : "unknown"),
1430 ((hw->bus.width == e1000_bus_width_pcie_x4)
1431 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1432 ? "Width x1" : "unknown"),
7c510e4b 1433 netdev->dev_addr);
9d5c8243
AK		 1434
1435 igb_read_part_num(hw, &part_num);
1436 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1437 (part_num >> 8), (part_num & 0xff));
1438
1439 dev_info(&pdev->dev,
1440 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1441 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1442 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1443 adapter->num_rx_queues, adapter->num_tx_queues);
1444
9d5c8243
AK		 1445 return 0;
1446
1447err_register:
1448 igb_release_hw_control(adapter);
1449err_eeprom:
1450 if (!igb_check_reset_block(hw))
f5f4cf08 1451 igb_reset_phy(hw);
9d5c8243
AK		 1452
1453 if (hw->flash_address)
1454 iounmap(hw->flash_address);
1455
a88f10ec 1456 igb_free_queues(adapter);
9d5c8243 1457err_sw_init:
9d5c8243
AK		 1458 iounmap(hw->hw_addr);
1459err_ioremap:
1460 free_netdev(netdev);
1461err_alloc_etherdev:
aed5dec3
AD		 1462 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1463 IORESOURCE_MEM));
9d5c8243
AK		 1464err_pci_reg:
1465err_dma:
1466 pci_disable_device(pdev);
1467 return err;
1468}
1469
1470/**
1471 * igb_remove - Device Removal Routine
1472 * @pdev: PCI device information struct
1473 *
1474 * igb_remove is called by the PCI subsystem to alert the driver
1475 * that it should release a PCI device. The could be caused by a
1476 * Hot-Plug event, or because the driver is going to be removed from
1477 * memory.
1478 **/
1479static void __devexit igb_remove(struct pci_dev *pdev)
1480{
1481 struct net_device *netdev = pci_get_drvdata(pdev);
1482 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1483 struct e1000_hw *hw = &adapter->hw;
ea943d41 1484 int err;
9d5c8243
AK		 1485
1486 /* flush_scheduled work may reschedule our watchdog task, so
1487 * explicitly disable watchdog tasks from being rescheduled */
1488 set_bit(__IGB_DOWN, &adapter->state);
1489 del_timer_sync(&adapter->watchdog_timer);
1490 del_timer_sync(&adapter->phy_info_timer);
1491
1492 flush_scheduled_work();
1493
421e02f0 1494#ifdef CONFIG_IGB_DCA
7dfc16fa 1495 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1496 dev_info(&pdev->dev, "DCA disabled\n");
1497 dca_remove_requester(&pdev->dev);
7dfc16fa 1498 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1499 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1500 }
1501#endif
1502
9d5c8243
AK		 1503 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1504 * would have already happened in close and is redundant. */
1505 igb_release_hw_control(adapter);
1506
1507 unregister_netdev(netdev);
1508
f5f4cf08
AD		 1509 if (!igb_check_reset_block(&adapter->hw))
1510 igb_reset_phy(&adapter->hw);
9d5c8243 1511
9d5c8243
AK		 1512 igb_reset_interrupt_capability(adapter);
1513
a88f10ec 1514 igb_free_queues(adapter);
9d5c8243 1515
28b0759c
AD		 1516 iounmap(hw->hw_addr);
1517 if (hw->flash_address)
1518 iounmap(hw->flash_address);
aed5dec3
AD		 1519 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1520 IORESOURCE_MEM));
9d5c8243
AK		 1521
1522 free_netdev(netdev);
1523
ea943d41
JK		 1524 err = pci_disable_pcie_error_reporting(pdev);
1525 if (err)
1526 dev_err(&pdev->dev,
1527 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1528
9d5c8243
AK		 1529 pci_disable_device(pdev);
1530}
1531
1532/**
1533 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1534 * @adapter: board private structure to initialize
1535 *
1536 * igb_sw_init initializes the Adapter private data structure.
1537 * Fields are initialized based on PCI device information and
1538 * OS network device settings (MTU size).
1539 **/
1540static int __devinit igb_sw_init(struct igb_adapter *adapter)
1541{
1542 struct e1000_hw *hw = &adapter->hw;
1543 struct net_device *netdev = adapter->netdev;
1544 struct pci_dev *pdev = adapter->pdev;
1545
1546 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1547
68fd9910
AD		 1548 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1549 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1550 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1551 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1552 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1553 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1554
661086df
PWJ		 1555 /* This call may decrease the number of queues depending on
1556 * interrupt mode. */
9d5c8243
AK		 1557 igb_set_interrupt_capability(adapter);
1558
1559 if (igb_alloc_queues(adapter)) {
1560 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1561 return -ENOMEM;
1562 }
1563
1564 /* Explicitly disable IRQ since the NIC can be in any state. */
1565 igb_irq_disable(adapter);
1566
1567 set_bit(__IGB_DOWN, &adapter->state);
1568 return 0;
1569}
1570
1571/**
1572 * igb_open - Called when a network interface is made active
1573 * @netdev: network interface device structure
1574 *
1575 * Returns 0 on success, negative value on failure
1576 *
1577 * The open entry point is called when a network interface is made
1578 * active by the system (IFF_UP). At this point all resources needed
1579 * for transmit and receive operations are allocated, the interrupt
1580 * handler is registered with the OS, the watchdog timer is started,
1581 * and the stack is notified that the interface is ready.
1582 **/
1583static int igb_open(struct net_device *netdev)
1584{
1585 struct igb_adapter *adapter = netdev_priv(netdev);
1586 struct e1000_hw *hw = &adapter->hw;
1587 int err;
1588 int i;
1589
1590 /* disallow open during test */
1591 if (test_bit(__IGB_TESTING, &adapter->state))
1592 return -EBUSY;
1593
1594 /* allocate transmit descriptors */
1595 err = igb_setup_all_tx_resources(adapter);
1596 if (err)
1597 goto err_setup_tx;
1598
1599 /* allocate receive descriptors */
1600 err = igb_setup_all_rx_resources(adapter);
1601 if (err)
1602 goto err_setup_rx;
1603
1604 /* e1000_power_up_phy(adapter); */
1605
1606 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1607 if ((adapter->hw.mng_cookie.status &
1608 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1609 igb_update_mng_vlan(adapter);
1610
1611 /* before we allocate an interrupt, we must be ready to handle it.
1612 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1613 * as soon as we call pci_request_irq, so we have to setup our
1614 * clean_rx handler before we do so. */
1615 igb_configure(adapter);
1616
1617 err = igb_request_irq(adapter);
1618 if (err)
1619 goto err_req_irq;
1620
1621 /* From here on the code is the same as igb_up() */
1622 clear_bit(__IGB_DOWN, &adapter->state);
1623
844290e5
PW		 1624 for (i = 0; i < adapter->num_rx_queues; i++)
1625 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1626
1627 /* Clear any pending interrupts. */
1628 rd32(E1000_ICR);
844290e5
PW		 1629
1630 igb_irq_enable(adapter);
1631
d55b53ff
JK		 1632 netif_tx_start_all_queues(netdev);
1633
9d5c8243
AK		 1634 /* Fire a link status change interrupt to start the watchdog. */
1635 wr32(E1000_ICS, E1000_ICS_LSC);
1636
1637 return 0;
1638
1639err_req_irq:
1640 igb_release_hw_control(adapter);
1641 /* e1000_power_down_phy(adapter); */
1642 igb_free_all_rx_resources(adapter);
1643err_setup_rx:
1644 igb_free_all_tx_resources(adapter);
1645err_setup_tx:
1646 igb_reset(adapter);
1647
1648 return err;
1649}
1650
1651/**
1652 * igb_close - Disables a network interface
1653 * @netdev: network interface device structure
1654 *
1655 * Returns 0, this is not allowed to fail
1656 *
1657 * The close entry point is called when an interface is de-activated
1658 * by the OS. The hardware is still under the driver's control, but
1659 * needs to be disabled. A global MAC reset is issued to stop the
1660 * hardware, and all transmit and receive resources are freed.
1661 **/
1662static int igb_close(struct net_device *netdev)
1663{
1664 struct igb_adapter *adapter = netdev_priv(netdev);
1665
1666 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1667 igb_down(adapter);
1668
1669 igb_free_irq(adapter);
1670
1671 igb_free_all_tx_resources(adapter);
1672 igb_free_all_rx_resources(adapter);
1673
1674 /* kill manageability vlan ID if supported, but not if a vlan with
1675 * the same ID is registered on the host OS (let 8021q kill it) */
1676 if ((adapter->hw.mng_cookie.status &
1677 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1678 !(adapter->vlgrp &&
1679 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1680 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1681
1682 return 0;
1683}
1684
1685/**
1686 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1687 * @adapter: board private structure
1688 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1689 *
1690 * Return 0 on success, negative on failure
1691 **/
9d5c8243
AK		 1692int igb_setup_tx_resources(struct igb_adapter *adapter,
1693 struct igb_ring *tx_ring)
1694{
1695 struct pci_dev *pdev = adapter->pdev;
1696 int size;
1697
1698 size = sizeof(struct igb_buffer) * tx_ring->count;
1699 tx_ring->buffer_info = vmalloc(size);
1700 if (!tx_ring->buffer_info)
1701 goto err;
1702 memset(tx_ring->buffer_info, 0, size);
1703
1704 /* round up to nearest 4K */
85e8d004 1705 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1706 tx_ring->size = ALIGN(tx_ring->size, 4096);
1707
1708 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1709 &tx_ring->dma);
1710
1711 if (!tx_ring->desc)
1712 goto err;
1713
1714 tx_ring->adapter = adapter;
1715 tx_ring->next_to_use = 0;
1716 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1717 return 0;
1718
1719err:
1720 vfree(tx_ring->buffer_info);
1721 dev_err(&adapter->pdev->dev,
1722 "Unable to allocate memory for the transmit descriptor ring\n");
1723 return -ENOMEM;
1724}
1725
1726/**
1727 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1728 * (Descriptors) for all queues
1729 * @adapter: board private structure
1730 *
1731 * Return 0 on success, negative on failure
1732 **/
1733static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1734{
1735 int i, err = 0;
661086df 1736 int r_idx;
9d5c8243
AK		 1737
1738 for (i = 0; i < adapter->num_tx_queues; i++) {
1739 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1740 if (err) {
1741 dev_err(&adapter->pdev->dev,
1742 "Allocation for Tx Queue %u failed\n", i);
1743 for (i--; i >= 0; i--)
3b644cf6 1744 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1745 break;
1746 }
1747 }
1748
661086df
PWJ		 1749 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1750 r_idx = i % adapter->num_tx_queues;
1751 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1752 }
9d5c8243
AK		 1753 return err;
1754}
1755
1756/**
1757 * igb_configure_tx - Configure transmit Unit after Reset
1758 * @adapter: board private structure
1759 *
1760 * Configure the Tx unit of the MAC after a reset.
1761 **/
1762static void igb_configure_tx(struct igb_adapter *adapter)
1763{
0e014cb1 1764 u64 tdba;
9d5c8243
AK		 1765 struct e1000_hw *hw = &adapter->hw;
1766 u32 tctl;
1767 u32 txdctl, txctrl;
26bc19ec 1768 int i, j;
9d5c8243
AK		 1769
1770 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1771 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1772 j = ring->reg_idx;
1773 wr32(E1000_TDLEN(j),
85e8d004 1774 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1775 tdba = ring->dma;
26bc19ec 1776 wr32(E1000_TDBAL(j),
73cd78f1 1777 tdba & 0x00000000ffffffffULL);
26bc19ec 1778 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1779
26bc19ec
AD		 1780 ring->head = E1000_TDH(j);
1781 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1782 writel(0, hw->hw_addr + ring->tail);
1783 writel(0, hw->hw_addr + ring->head);
26bc19ec 1784 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1785 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1786 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1787
1788 /* Turn off Relaxed Ordering on head write-backs. The
1789 * writebacks MUST be delivered in order or it will
1790 * completely screw up our bookeeping.
1791 */
26bc19ec 1792 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1793 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1794 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1795 }
1796
9d5c8243
AK		 1797 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1798
1799 /* Program the Transmit Control Register */
1800
1801 tctl = rd32(E1000_TCTL);
1802 tctl &= ~E1000_TCTL_CT;
1803 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1804 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1805
1806 igb_config_collision_dist(hw);
1807
1808 /* Setup Transmit Descriptor Settings for eop descriptor */
1809 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1810
1811 /* Enable transmits */
1812 tctl |= E1000_TCTL_EN;
1813
1814 wr32(E1000_TCTL, tctl);
1815}
1816
1817/**
1818 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1819 * @adapter: board private structure
1820 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1821 *
1822 * Returns 0 on success, negative on failure
1823 **/
9d5c8243
AK		 1824int igb_setup_rx_resources(struct igb_adapter *adapter,
1825 struct igb_ring *rx_ring)
1826{
1827 struct pci_dev *pdev = adapter->pdev;
1828 int size, desc_len;
1829
1830 size = sizeof(struct igb_buffer) * rx_ring->count;
1831 rx_ring->buffer_info = vmalloc(size);
1832 if (!rx_ring->buffer_info)
1833 goto err;
1834 memset(rx_ring->buffer_info, 0, size);
1835
1836 desc_len = sizeof(union e1000_adv_rx_desc);
1837
1838 /* Round up to nearest 4K */
1839 rx_ring->size = rx_ring->count * desc_len;
1840 rx_ring->size = ALIGN(rx_ring->size, 4096);
1841
1842 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1843 &rx_ring->dma);
1844
1845 if (!rx_ring->desc)
1846 goto err;
1847
1848 rx_ring->next_to_clean = 0;
1849 rx_ring->next_to_use = 0;
9d5c8243
AK		 1850
1851 rx_ring->adapter = adapter;
9d5c8243
AK		 1852
1853 return 0;
1854
1855err:
1856 vfree(rx_ring->buffer_info);
1857 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1858 "the receive descriptor ring\n");
1859 return -ENOMEM;
1860}
1861
1862/**
1863 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1864 * (Descriptors) for all queues
1865 * @adapter: board private structure
1866 *
1867 * Return 0 on success, negative on failure
1868 **/
1869static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1870{
1871 int i, err = 0;
1872
1873 for (i = 0; i < adapter->num_rx_queues; i++) {
1874 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1875 if (err) {
1876 dev_err(&adapter->pdev->dev,
1877 "Allocation for Rx Queue %u failed\n", i);
1878 for (i--; i >= 0; i--)
3b644cf6 1879 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1880 break;
1881 }
1882 }
1883
1884 return err;
1885}
1886
1887/**
1888 * igb_setup_rctl - configure the receive control registers
1889 * @adapter: Board private structure
1890 **/
1891static void igb_setup_rctl(struct igb_adapter *adapter)
1892{
1893 struct e1000_hw *hw = &adapter->hw;
1894 u32 rctl;
1895 u32 srrctl = 0;
26bc19ec 1896 int i, j;
9d5c8243
AK		 1897
1898 rctl = rd32(E1000_RCTL);
1899
1900 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1901 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1902
69d728ba 1903 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1904 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1905
87cb7e8c
AK		 1906 /*
1907 * enable stripping of CRC. It's unlikely this will break BMC
1908 * redirection as it did with e1000. Newer features require
1909 * that the HW strips the CRC.
73cd78f1 1910 */
87cb7e8c 1911 rctl |= E1000_RCTL_SECRC;
9d5c8243 1912
9b07f3d3 1913 /*
ec54d7d6 1914 * disable store bad packets and clear size bits.
9b07f3d3 1915 */
ec54d7d6 1916 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1917
ec54d7d6 1918 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1919 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1920
1921 /* Setup buffer sizes */
1922 switch (adapter->rx_buffer_len) {
1923 case IGB_RXBUFFER_256:
1924 rctl |= E1000_RCTL_SZ_256;
1925 break;
1926 case IGB_RXBUFFER_512:
1927 rctl |= E1000_RCTL_SZ_512;
1928 break;
1929 default:
1930 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1931 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1932 break;
9d5c8243
AK		 1933 }
1934
1935 /* 82575 and greater support packet-split where the protocol
1936 * header is placed in skb->data and the packet data is
1937 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1938 * In the case of a non-split, skb->data is linearly filled,
1939 * followed by the page buffers. Therefore, skb->data is
1940 * sized to hold the largest protocol header.
1941 */
1942 /* allocations using alloc_page take too long for regular MTU
1943 * so only enable packet split for jumbo frames */
ec54d7d6 1944 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1945 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1946 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1947 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1948 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1949 } else {
1950 adapter->rx_ps_hdr_size = 0;
1951 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1952 }
1953
26bc19ec
AD		 1954 for (i = 0; i < adapter->num_rx_queues; i++) {
1955 j = adapter->rx_ring[i].reg_idx;
1956 wr32(E1000_SRRCTL(j), srrctl);
1957 }
9d5c8243
AK		 1958
1959 wr32(E1000_RCTL, rctl);
1960}
1961
1962/**
1963 * igb_configure_rx - Configure receive Unit after Reset
1964 * @adapter: board private structure
1965 *
1966 * Configure the Rx unit of the MAC after a reset.
1967 **/
1968static void igb_configure_rx(struct igb_adapter *adapter)
1969{
1970 u64 rdba;
1971 struct e1000_hw *hw = &adapter->hw;
1972 u32 rctl, rxcsum;
1973 u32 rxdctl;
9107584e 1974 int i;
9d5c8243
AK		 1975
1976 /* disable receives while setting up the descriptors */
1977 rctl = rd32(E1000_RCTL);
1978 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1979 wrfl();
1980 mdelay(10);
1981
1982 if (adapter->itr_setting > 3)
6eb5a7f1 1983 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1984
1985 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1986 * the Base and Length of the Rx Descriptor Ring */
1987 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 1988 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 1989 int j = ring->reg_idx;
9d5c8243 1990 rdba = ring->dma;
26bc19ec 1991 wr32(E1000_RDBAL(j),
73cd78f1 1992 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1993 wr32(E1000_RDBAH(j), rdba >> 32);
1994 wr32(E1000_RDLEN(j),
73cd78f1 1995 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 1996
26bc19ec
AD		 1997 ring->head = E1000_RDH(j);
1998 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1999 writel(0, hw->hw_addr + ring->tail);
2000 writel(0, hw->hw_addr + ring->head);
2001
26bc19ec 2002 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2003 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2004 rxdctl &= 0xFFF00000;
2005 rxdctl |= IGB_RX_PTHRESH;
2006 rxdctl |= IGB_RX_HTHRESH << 8;
2007 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2008 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2009 }
2010
2011 if (adapter->num_rx_queues > 1) {
2012 u32 random[10];
2013 u32 mrqc;
2014 u32 j, shift;
2015 union e1000_reta {
2016 u32 dword;
2017 u8 bytes[4];
2018 } reta;
2019
2020 get_random_bytes(&random[0], 40);
2021
2d064c06
AD		 2022 if (hw->mac.type >= e1000_82576)
2023 shift = 0;
2024 else
2025 shift = 6;
9d5c8243
AK		 2026 for (j = 0; j < (32 * 4); j++) {
2027 reta.bytes[j & 3] =
26bc19ec 2028 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2029 if ((j & 3) == 3)
2030 writel(reta.dword,
2031 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2032 }
2033 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2034
2035 /* Fill out hash function seeds */
2036 for (j = 0; j < 10; j++)
2037 array_wr32(E1000_RSSRK(0), j, random[j]);
2038
2039 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2040 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2041 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2042 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2043 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2044 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2045 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2046 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2047
2048
2049 wr32(E1000_MRQC, mrqc);
2050
2051 /* Multiqueue and raw packet checksumming are mutually
2052 * exclusive. Note that this not the same as TCP/IP
2053 * checksumming, which works fine. */
2054 rxcsum = rd32(E1000_RXCSUM);
2055 rxcsum |= E1000_RXCSUM_PCSD;
2056 wr32(E1000_RXCSUM, rxcsum);
2057 } else {
2058 /* Enable Receive Checksum Offload for TCP and UDP */
2059 rxcsum = rd32(E1000_RXCSUM);
56fbbb4e
AD		 2060 if (adapter->rx_csum)
2061 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2062 else
2063 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2064
9d5c8243
AK		 2065 wr32(E1000_RXCSUM, rxcsum);
2066 }
2067
2068 if (adapter->vlgrp)
2069 wr32(E1000_RLPML,
2070 adapter->max_frame_size + VLAN_TAG_SIZE);
2071 else
2072 wr32(E1000_RLPML, adapter->max_frame_size);
2073
2074 /* Enable Receives */
2075 wr32(E1000_RCTL, rctl);
2076}
2077
2078/**
2079 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2080 * @tx_ring: Tx descriptor ring for a specific queue
2081 *
2082 * Free all transmit software resources
2083 **/
68fd9910 2084void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2085{
3b644cf6 2086 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2087
3b644cf6 2088 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2089
2090 vfree(tx_ring->buffer_info);
2091 tx_ring->buffer_info = NULL;
2092
2093 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2094
2095 tx_ring->desc = NULL;
2096}
2097
2098/**
2099 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2100 * @adapter: board private structure
2101 *
2102 * Free all transmit software resources
2103 **/
2104static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2105{
2106 int i;
2107
2108 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2109 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2110}
2111
2112static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2113 struct igb_buffer *buffer_info)
2114{
2115 if (buffer_info->dma) {
2116 pci_unmap_page(adapter->pdev,
2117 buffer_info->dma,
2118 buffer_info->length,
2119 PCI_DMA_TODEVICE);
2120 buffer_info->dma = 0;
2121 }
2122 if (buffer_info->skb) {
2123 dev_kfree_skb_any(buffer_info->skb);
2124 buffer_info->skb = NULL;
2125 }
2126 buffer_info->time_stamp = 0;
73cd78f1 2127 buffer_info->next_to_watch = 0;
9d5c8243
AK		 2128 /* buffer_info must be completely set up in the transmit path */
2129}
2130
2131/**
2132 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2133 * @tx_ring: ring to be cleaned
2134 **/
3b644cf6 2135static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2136{
3b644cf6 2137 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2138 struct igb_buffer *buffer_info;
2139 unsigned long size;
2140 unsigned int i;
2141
2142 if (!tx_ring->buffer_info)
2143 return;
2144 /* Free all the Tx ring sk_buffs */
2145
2146 for (i = 0; i < tx_ring->count; i++) {
2147 buffer_info = &tx_ring->buffer_info[i];
2148 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2149 }
2150
2151 size = sizeof(struct igb_buffer) * tx_ring->count;
2152 memset(tx_ring->buffer_info, 0, size);
2153
2154 /* Zero out the descriptor ring */
2155
2156 memset(tx_ring->desc, 0, tx_ring->size);
2157
2158 tx_ring->next_to_use = 0;
2159 tx_ring->next_to_clean = 0;
2160
2161 writel(0, adapter->hw.hw_addr + tx_ring->head);
2162 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2163}
2164
2165/**
2166 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2167 * @adapter: board private structure
2168 **/
2169static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2170{
2171 int i;
2172
2173 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2174 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2175}
2176
2177/**
2178 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2179 * @rx_ring: ring to clean the resources from
2180 *
2181 * Free all receive software resources
2182 **/
68fd9910 2183void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2184{
3b644cf6 2185 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2186
3b644cf6 2187 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2188
2189 vfree(rx_ring->buffer_info);
2190 rx_ring->buffer_info = NULL;
2191
2192 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2193
2194 rx_ring->desc = NULL;
2195}
2196
2197/**
2198 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2199 * @adapter: board private structure
2200 *
2201 * Free all receive software resources
2202 **/
2203static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2204{
2205 int i;
2206
2207 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2208 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2209}
2210
2211/**
2212 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2213 * @rx_ring: ring to free buffers from
2214 **/
3b644cf6 2215static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2216{
3b644cf6 2217 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2218 struct igb_buffer *buffer_info;
2219 struct pci_dev *pdev = adapter->pdev;
2220 unsigned long size;
2221 unsigned int i;
2222
2223 if (!rx_ring->buffer_info)
2224 return;
2225 /* Free all the Rx ring sk_buffs */
2226 for (i = 0; i < rx_ring->count; i++) {
2227 buffer_info = &rx_ring->buffer_info[i];
2228 if (buffer_info->dma) {
2229 if (adapter->rx_ps_hdr_size)
2230 pci_unmap_single(pdev, buffer_info->dma,
2231 adapter->rx_ps_hdr_size,
2232 PCI_DMA_FROMDEVICE);
2233 else
2234 pci_unmap_single(pdev, buffer_info->dma,
2235 adapter->rx_buffer_len,
2236 PCI_DMA_FROMDEVICE);
2237 buffer_info->dma = 0;
2238 }
2239
2240 if (buffer_info->skb) {
2241 dev_kfree_skb(buffer_info->skb);
2242 buffer_info->skb = NULL;
2243 }
2244 if (buffer_info->page) {
bf36c1a0
AD		 2245 if (buffer_info->page_dma)
2246 pci_unmap_page(pdev, buffer_info->page_dma,
2247 PAGE_SIZE / 2,
2248 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2249 put_page(buffer_info->page);
2250 buffer_info->page = NULL;
2251 buffer_info->page_dma = 0;
bf36c1a0 2252 buffer_info->page_offset = 0;
9d5c8243
AK		 2253 }
2254 }
2255
9d5c8243
AK		 2256 size = sizeof(struct igb_buffer) * rx_ring->count;
2257 memset(rx_ring->buffer_info, 0, size);
2258
2259 /* Zero out the descriptor ring */
2260 memset(rx_ring->desc, 0, rx_ring->size);
2261
2262 rx_ring->next_to_clean = 0;
2263 rx_ring->next_to_use = 0;
2264
2265 writel(0, adapter->hw.hw_addr + rx_ring->head);
2266 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2267}
2268
2269/**
2270 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2271 * @adapter: board private structure
2272 **/
2273static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2274{
2275 int i;
2276
2277 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2278 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2279}
2280
2281/**
2282 * igb_set_mac - Change the Ethernet Address of the NIC
2283 * @netdev: network interface device structure
2284 * @p: pointer to an address structure
2285 *
2286 * Returns 0 on success, negative on failure
2287 **/
2288static int igb_set_mac(struct net_device *netdev, void *p)
2289{
2290 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2291 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2292 struct sockaddr *addr = p;
2293
2294 if (!is_valid_ether_addr(addr->sa_data))
2295 return -EADDRNOTAVAIL;
2296
2297 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2298 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2299
28b0759c 2300 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243
AK		 2301
2302 return 0;
2303}
2304
2305/**
2306 * igb_set_multi - Multicast and Promiscuous mode set
2307 * @netdev: network interface device structure
2308 *
2309 * The set_multi entry point is called whenever the multicast address
2310 * list or the network interface flags are updated. This routine is
2311 * responsible for configuring the hardware for proper multicast,
2312 * promiscuous mode, and all-multi behavior.
2313 **/
2314static void igb_set_multi(struct net_device *netdev)
2315{
2316 struct igb_adapter *adapter = netdev_priv(netdev);
2317 struct e1000_hw *hw = &adapter->hw;
2318 struct e1000_mac_info *mac = &hw->mac;
2319 struct dev_mc_list *mc_ptr;
2320 u8 *mta_list;
2321 u32 rctl;
2322 int i;
2323
2324 /* Check for Promiscuous and All Multicast modes */
2325
2326 rctl = rd32(E1000_RCTL);
2327
746b9f02 2328 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2329 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2330 rctl &= ~E1000_RCTL_VFE;
2331 } else {
2332 if (netdev->flags & IFF_ALLMULTI) {
2333 rctl |= E1000_RCTL_MPE;
2334 rctl &= ~E1000_RCTL_UPE;
2335 } else
2336 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2337 rctl |= E1000_RCTL_VFE;
746b9f02 2338 }
9d5c8243
AK		 2339 wr32(E1000_RCTL, rctl);
2340
2341 if (!netdev->mc_count) {
2342 /* nothing to program, so clear mc list */
8a900862
AD		 2343 igb_update_mc_addr_list(hw, NULL, 0, 1,
2344 mac->rar_entry_count);
9d5c8243
AK		 2345 return;
2346 }
2347
2348 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2349 if (!mta_list)
2350 return;
2351
2352 /* The shared function expects a packed array of only addresses. */
2353 mc_ptr = netdev->mc_list;
2354
2355 for (i = 0; i < netdev->mc_count; i++) {
2356 if (!mc_ptr)
2357 break;
2358 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2359 mc_ptr = mc_ptr->next;
2360 }
8a900862 2361 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2362 kfree(mta_list);
2363}
2364
2365/* Need to wait a few seconds after link up to get diagnostic information from
2366 * the phy */
2367static void igb_update_phy_info(unsigned long data)
2368{
2369 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2370 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2371}
2372
4d6b725e
AD		 2373/**
2374 * igb_has_link - check shared code for link and determine up/down
2375 * @adapter: pointer to driver private info
2376 **/
2377static bool igb_has_link(struct igb_adapter *adapter)
2378{
2379 struct e1000_hw *hw = &adapter->hw;
2380 bool link_active = false;
2381 s32 ret_val = 0;
2382
2383 /* get_link_status is set on LSC (link status) interrupt or
2384 * rx sequence error interrupt. get_link_status will stay
2385 * false until the e1000_check_for_link establishes link
2386 * for copper adapters ONLY
2387 */
2388 switch (hw->phy.media_type) {
2389 case e1000_media_type_copper:
2390 if (hw->mac.get_link_status) {
2391 ret_val = hw->mac.ops.check_for_link(hw);
2392 link_active = !hw->mac.get_link_status;
2393 } else {
2394 link_active = true;
2395 }
2396 break;
2397 case e1000_media_type_fiber:
2398 ret_val = hw->mac.ops.check_for_link(hw);
2399 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2400 break;
2401 case e1000_media_type_internal_serdes:
2402 ret_val = hw->mac.ops.check_for_link(hw);
2403 link_active = hw->mac.serdes_has_link;
2404 break;
2405 default:
2406 case e1000_media_type_unknown:
2407 break;
2408 }
2409
2410 return link_active;
2411}
2412
9d5c8243
AK		 2413/**
2414 * igb_watchdog - Timer Call-back
2415 * @data: pointer to adapter cast into an unsigned long
2416 **/
2417static void igb_watchdog(unsigned long data)
2418{
2419 struct igb_adapter *adapter = (struct igb_adapter *)data;
2420 /* Do the rest outside of interrupt context */
2421 schedule_work(&adapter->watchdog_task);
2422}
2423
2424static void igb_watchdog_task(struct work_struct *work)
2425{
2426 struct igb_adapter *adapter = container_of(work,
2427 struct igb_adapter, watchdog_task);
2428 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2429 struct net_device *netdev = adapter->netdev;
2430 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2431 u32 link;
7a6ea550 2432 u32 eics = 0;
7a6ea550 2433 int i;
9d5c8243 2434
4d6b725e
AD		 2435 link = igb_has_link(adapter);
2436 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2437 goto link_up;
2438
9d5c8243
AK		 2439 if (link) {
2440 if (!netif_carrier_ok(netdev)) {
2441 u32 ctrl;
2442 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2443 &adapter->link_speed,
2444 &adapter->link_duplex);
2445
2446 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2447 /* Links status message must follow this format */
2448 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2449 "Flow Control: %s\n",
527d47c1 2450 netdev->name,
9d5c8243
AK		 2451 adapter->link_speed,
2452 adapter->link_duplex == FULL_DUPLEX ?
2453 "Full Duplex" : "Half Duplex",
2454 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2455 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2456 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2457 E1000_CTRL_TFCE) ? "TX" : "None")));
2458
2459 /* tweak tx_queue_len according to speed/duplex and
2460 * adjust the timeout factor */
2461 netdev->tx_queue_len = adapter->tx_queue_len;
2462 adapter->tx_timeout_factor = 1;
2463 switch (adapter->link_speed) {
2464 case SPEED_10:
2465 netdev->tx_queue_len = 10;
2466 adapter->tx_timeout_factor = 14;
2467 break;
2468 case SPEED_100:
2469 netdev->tx_queue_len = 100;
2470 /* maybe add some timeout factor ? */
2471 break;
2472 }
2473
2474 netif_carrier_on(netdev);
fd2ea0a7 2475 netif_tx_wake_all_queues(netdev);
9d5c8243 2476
4b1a9877 2477 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2478 if (!test_bit(__IGB_DOWN, &adapter->state))
2479 mod_timer(&adapter->phy_info_timer,
2480 round_jiffies(jiffies + 2 * HZ));
2481 }
2482 } else {
2483 if (netif_carrier_ok(netdev)) {
2484 adapter->link_speed = 0;
2485 adapter->link_duplex = 0;
527d47c1
AD		 2486 /* Links status message must follow this format */
2487 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2488 netdev->name);
9d5c8243 2489 netif_carrier_off(netdev);
fd2ea0a7 2490 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2491
2492 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2493 if (!test_bit(__IGB_DOWN, &adapter->state))
2494 mod_timer(&adapter->phy_info_timer,
2495 round_jiffies(jiffies + 2 * HZ));
2496 }
2497 }
2498
2499link_up:
2500 igb_update_stats(adapter);
2501
4b1a9877 2502 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2503 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2504 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2505 adapter->colc_old = adapter->stats.colc;
2506
2507 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2508 adapter->gorc_old = adapter->stats.gorc;
2509 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2510 adapter->gotc_old = adapter->stats.gotc;
2511
2512 igb_update_adaptive(&adapter->hw);
2513
2514 if (!netif_carrier_ok(netdev)) {
2515 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2516 /* We've lost link, so the controller stops DMA,
2517 * but we've got queued Tx work that's never going
2518 * to get done, so reset controller to flush Tx.
2519 * (Do the reset outside of interrupt context). */
2520 adapter->tx_timeout_count++;
2521 schedule_work(&adapter->reset_task);
2522 }
2523 }
2524
2525 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2526 if (adapter->msix_entries) {
2527 for (i = 0; i < adapter->num_rx_queues; i++)
2528 eics |= adapter->rx_ring[i].eims_value;
2529 wr32(E1000_EICS, eics);
2530 } else {
2531 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2532 }
9d5c8243
AK		 2533
2534 /* Force detection of hung controller every watchdog period */
2535 tx_ring->detect_tx_hung = true;
2536
2537 /* Reset the timer */
2538 if (!test_bit(__IGB_DOWN, &adapter->state))
2539 mod_timer(&adapter->watchdog_timer,
2540 round_jiffies(jiffies + 2 * HZ));
2541}
2542
2543enum latency_range {
2544 lowest_latency = 0,
2545 low_latency = 1,
2546 bulk_latency = 2,
2547 latency_invalid = 255
2548};
2549
2550
6eb5a7f1
AD		 2551/**
2552 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2553 *
2554 * Stores a new ITR value based on strictly on packet size. This
2555 * algorithm is less sophisticated than that used in igb_update_itr,
2556 * due to the difficulty of synchronizing statistics across multiple
2557 * receive rings. The divisors and thresholds used by this fuction
2558 * were determined based on theoretical maximum wire speed and testing
2559 * data, in order to minimize response time while increasing bulk
2560 * throughput.
2561 * This functionality is controlled by the InterruptThrottleRate module
2562 * parameter (see igb_param.c)
2563 * NOTE: This function is called only when operating in a multiqueue
2564 * receive environment.
2565 * @rx_ring: pointer to ring
2566 **/
2567static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2568{
6eb5a7f1
AD		 2569 int new_val = rx_ring->itr_val;
2570 int avg_wire_size = 0;
2571 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2572
6eb5a7f1
AD		 2573 if (!rx_ring->total_packets)
2574 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2575
6eb5a7f1
AD		 2576 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2577 * ints/sec - ITR timer value of 120 ticks.
2578 */
2579 if (adapter->link_speed != SPEED_1000) {
2580 new_val = 120;
2581 goto set_itr_val;
9d5c8243 2582 }
6eb5a7f1 2583 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2584
6eb5a7f1
AD		 2585 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2586 avg_wire_size += 24;
2587
2588 /* Don't starve jumbo frames */
2589 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2590
6eb5a7f1
AD		 2591 /* Give a little boost to mid-size frames */
2592 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2593 new_val = avg_wire_size / 3;
2594 else
2595 new_val = avg_wire_size / 2;
9d5c8243 2596
6eb5a7f1 2597set_itr_val:
9d5c8243
AK		 2598 if (new_val != rx_ring->itr_val) {
2599 rx_ring->itr_val = new_val;
6eb5a7f1 2600 rx_ring->set_itr = 1;
9d5c8243 2601 }
6eb5a7f1
AD		 2602clear_counts:
2603 rx_ring->total_bytes = 0;
2604 rx_ring->total_packets = 0;
9d5c8243
AK		 2605}
2606
2607/**
2608 * igb_update_itr - update the dynamic ITR value based on statistics
2609 * Stores a new ITR value based on packets and byte
2610 * counts during the last interrupt. The advantage of per interrupt
2611 * computation is faster updates and more accurate ITR for the current
2612 * traffic pattern. Constants in this function were computed
2613 * based on theoretical maximum wire speed and thresholds were set based
2614 * on testing data as well as attempting to minimize response time
2615 * while increasing bulk throughput.
2616 * this functionality is controlled by the InterruptThrottleRate module
2617 * parameter (see igb_param.c)
2618 * NOTE: These calculations are only valid when operating in a single-
2619 * queue environment.
2620 * @adapter: pointer to adapter
2621 * @itr_setting: current adapter->itr
2622 * @packets: the number of packets during this measurement interval
2623 * @bytes: the number of bytes during this measurement interval
2624 **/
2625static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2626 int packets, int bytes)
2627{
2628 unsigned int retval = itr_setting;
2629
2630 if (packets == 0)
2631 goto update_itr_done;
2632
2633 switch (itr_setting) {
2634 case lowest_latency:
2635 /* handle TSO and jumbo frames */
2636 if (bytes/packets > 8000)
2637 retval = bulk_latency;
2638 else if ((packets < 5) && (bytes > 512))
2639 retval = low_latency;
2640 break;
2641 case low_latency: /* 50 usec aka 20000 ints/s */
2642 if (bytes > 10000) {
2643 /* this if handles the TSO accounting */
2644 if (bytes/packets > 8000) {
2645 retval = bulk_latency;
2646 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2647 retval = bulk_latency;
2648 } else if ((packets > 35)) {
2649 retval = lowest_latency;
2650 }
2651 } else if (bytes/packets > 2000) {
2652 retval = bulk_latency;
2653 } else if (packets <= 2 && bytes < 512) {
2654 retval = lowest_latency;
2655 }
2656 break;
2657 case bulk_latency: /* 250 usec aka 4000 ints/s */
2658 if (bytes > 25000) {
2659 if (packets > 35)
2660 retval = low_latency;
1e5c3d21 2661 } else if (bytes < 1500) {
9d5c8243
AK		 2662 retval = low_latency;
2663 }
2664 break;
2665 }
2666
2667update_itr_done:
2668 return retval;
2669}
2670
6eb5a7f1 2671static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2672{
2673 u16 current_itr;
2674 u32 new_itr = adapter->itr;
2675
2676 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2677 if (adapter->link_speed != SPEED_1000) {
2678 current_itr = 0;
2679 new_itr = 4000;
2680 goto set_itr_now;
2681 }
2682
2683 adapter->rx_itr = igb_update_itr(adapter,
2684 adapter->rx_itr,
2685 adapter->rx_ring->total_packets,
2686 adapter->rx_ring->total_bytes);
9d5c8243 2687
6eb5a7f1 2688 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2689 adapter->tx_itr = igb_update_itr(adapter,
2690 adapter->tx_itr,
2691 adapter->tx_ring->total_packets,
2692 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2693 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2694 } else {
2695 current_itr = adapter->rx_itr;
2696 }
2697
6eb5a7f1 2698 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2699 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2700 current_itr = low_latency;
2701
9d5c8243
AK		 2702 switch (current_itr) {
2703 /* counts and packets in update_itr are dependent on these numbers */
2704 case lowest_latency:
2705 new_itr = 70000;
2706 break;
2707 case low_latency:
2708 new_itr = 20000; /* aka hwitr = ~200 */
2709 break;
2710 case bulk_latency:
2711 new_itr = 4000;
2712 break;
2713 default:
2714 break;
2715 }
2716
2717set_itr_now:
6eb5a7f1
AD		 2718 adapter->rx_ring->total_bytes = 0;
2719 adapter->rx_ring->total_packets = 0;
2720 if (adapter->rx_ring->buddy) {
2721 adapter->rx_ring->buddy->total_bytes = 0;
2722 adapter->rx_ring->buddy->total_packets = 0;
2723 }
2724
9d5c8243
AK		 2725 if (new_itr != adapter->itr) {
2726 /* this attempts to bias the interrupt rate towards Bulk
2727 * by adding intermediate steps when interrupt rate is
2728 * increasing */
2729 new_itr = new_itr > adapter->itr ?
2730 min(adapter->itr + (new_itr >> 2), new_itr) :
2731 new_itr;
2732 /* Don't write the value here; it resets the adapter's
2733 * internal timer, and causes us to delay far longer than
2734 * we should between interrupts. Instead, we write the ITR
2735 * value at the beginning of the next interrupt so the timing
2736 * ends up being correct.
2737 */
2738 adapter->itr = new_itr;
6eb5a7f1
AD		 2739 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2740 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2741 }
2742
2743 return;
2744}
2745
2746
2747#define IGB_TX_FLAGS_CSUM 0x00000001
2748#define IGB_TX_FLAGS_VLAN 0x00000002
2749#define IGB_TX_FLAGS_TSO 0x00000004
2750#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2751#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2752#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2753#define IGB_TX_FLAGS_VLAN_SHIFT 16
2754
2755static inline int igb_tso_adv(struct igb_adapter *adapter,
2756 struct igb_ring *tx_ring,
2757 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2758{
2759 struct e1000_adv_tx_context_desc *context_desc;
2760 unsigned int i;
2761 int err;
2762 struct igb_buffer *buffer_info;
2763 u32 info = 0, tu_cmd = 0;
2764 u32 mss_l4len_idx, l4len;
2765 *hdr_len = 0;
2766
2767 if (skb_header_cloned(skb)) {
2768 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2769 if (err)
2770 return err;
2771 }
2772
2773 l4len = tcp_hdrlen(skb);
2774 *hdr_len += l4len;
2775
2776 if (skb->protocol == htons(ETH_P_IP)) {
2777 struct iphdr *iph = ip_hdr(skb);
2778 iph->tot_len = 0;
2779 iph->check = 0;
2780 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2781 iph->daddr, 0,
2782 IPPROTO_TCP,
2783 0);
2784 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2785 ipv6_hdr(skb)->payload_len = 0;
2786 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2787 &ipv6_hdr(skb)->daddr,
2788 0, IPPROTO_TCP, 0);
2789 }
2790
2791 i = tx_ring->next_to_use;
2792
2793 buffer_info = &tx_ring->buffer_info[i];
2794 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2795 /* VLAN MACLEN IPLEN */
2796 if (tx_flags & IGB_TX_FLAGS_VLAN)
2797 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2798 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2799 *hdr_len += skb_network_offset(skb);
2800 info |= skb_network_header_len(skb);
2801 *hdr_len += skb_network_header_len(skb);
2802 context_desc->vlan_macip_lens = cpu_to_le32(info);
2803
2804 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2805 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2806
2807 if (skb->protocol == htons(ETH_P_IP))
2808 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2809 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2810
2811 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2812
2813 /* MSS L4LEN IDX */
2814 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2815 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2816
73cd78f1 2817 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 2818 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2819 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2820
2821 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2822 context_desc->seqnum_seed = 0;
2823
2824 buffer_info->time_stamp = jiffies;
0e014cb1 2825 buffer_info->next_to_watch = i;
9d5c8243
AK		 2826 buffer_info->dma = 0;
2827 i++;
2828 if (i == tx_ring->count)
2829 i = 0;
2830
2831 tx_ring->next_to_use = i;
2832
2833 return true;
2834}
2835
2836static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2837 struct igb_ring *tx_ring,
2838 struct sk_buff *skb, u32 tx_flags)
2839{
2840 struct e1000_adv_tx_context_desc *context_desc;
2841 unsigned int i;
2842 struct igb_buffer *buffer_info;
2843 u32 info = 0, tu_cmd = 0;
2844
2845 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2846 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2847 i = tx_ring->next_to_use;
2848 buffer_info = &tx_ring->buffer_info[i];
2849 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2850
2851 if (tx_flags & IGB_TX_FLAGS_VLAN)
2852 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2853 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2854 if (skb->ip_summed == CHECKSUM_PARTIAL)
2855 info |= skb_network_header_len(skb);
2856
2857 context_desc->vlan_macip_lens = cpu_to_le32(info);
2858
2859 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2860
2861 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2862 switch (skb->protocol) {
09640e63 2863 case cpu_to_be16(ETH_P_IP):
9d5c8243 2864 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2865 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2866 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2867 break;
09640e63 2868 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2869 /* XXX what about other V6 headers?? */
2870 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2871 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2872 break;
2873 default:
2874 if (unlikely(net_ratelimit()))
2875 dev_warn(&adapter->pdev->dev,
2876 "partial checksum but proto=%x!\n",
2877 skb->protocol);
2878 break;
2879 }
9d5c8243
AK		 2880 }
2881
2882 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2883 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2884 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2885 context_desc->mss_l4len_idx =
2886 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 2887 else
2888 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 2889
2890 buffer_info->time_stamp = jiffies;
0e014cb1 2891 buffer_info->next_to_watch = i;
9d5c8243
AK		 2892 buffer_info->dma = 0;
2893
2894 i++;
2895 if (i == tx_ring->count)
2896 i = 0;
2897 tx_ring->next_to_use = i;
2898
2899 return true;
2900 }
9d5c8243
AK		 2901 return false;
2902}
2903
2904#define IGB_MAX_TXD_PWR 16
2905#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2906
2907static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2908 struct igb_ring *tx_ring, struct sk_buff *skb,
2909 unsigned int first)
9d5c8243
AK		 2910{
2911 struct igb_buffer *buffer_info;
2912 unsigned int len = skb_headlen(skb);
2913 unsigned int count = 0, i;
2914 unsigned int f;
2915
2916 i = tx_ring->next_to_use;
2917
2918 buffer_info = &tx_ring->buffer_info[i];
2919 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2920 buffer_info->length = len;
2921 /* set time_stamp *before* dma to help avoid a possible race */
2922 buffer_info->time_stamp = jiffies;
0e014cb1 2923 buffer_info->next_to_watch = i;
9d5c8243
AK		 2924 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2925 PCI_DMA_TODEVICE);
2926 count++;
2927 i++;
2928 if (i == tx_ring->count)
2929 i = 0;
2930
2931 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2932 struct skb_frag_struct *frag;
2933
2934 frag = &skb_shinfo(skb)->frags[f];
2935 len = frag->size;
2936
2937 buffer_info = &tx_ring->buffer_info[i];
2938 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2939 buffer_info->length = len;
2940 buffer_info->time_stamp = jiffies;
0e014cb1 2941 buffer_info->next_to_watch = i;
9d5c8243
AK		 2942 buffer_info->dma = pci_map_page(adapter->pdev,
2943 frag->page,
2944 frag->page_offset,
2945 len,
2946 PCI_DMA_TODEVICE);
2947
2948 count++;
2949 i++;
2950 if (i == tx_ring->count)
2951 i = 0;
2952 }
2953
0e014cb1 2954 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2955 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2956 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2957
2958 return count;
2959}
2960
2961static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2962 struct igb_ring *tx_ring,
2963 int tx_flags, int count, u32 paylen,
2964 u8 hdr_len)
2965{
2966 union e1000_adv_tx_desc *tx_desc = NULL;
2967 struct igb_buffer *buffer_info;
2968 u32 olinfo_status = 0, cmd_type_len;
2969 unsigned int i;
2970
2971 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2972 E1000_ADVTXD_DCMD_DEXT);
2973
2974 if (tx_flags & IGB_TX_FLAGS_VLAN)
2975 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2976
33af6bcc
PO		 2977 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
2978 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
2979
9d5c8243
AK		 2980 if (tx_flags & IGB_TX_FLAGS_TSO) {
2981 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2982
2983 /* insert tcp checksum */
2984 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2985
2986 /* insert ip checksum */
2987 if (tx_flags & IGB_TX_FLAGS_IPV4)
2988 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2989
2990 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2991 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2992 }
2993
7dfc16fa
AD		 2994 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2995 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2996 IGB_TX_FLAGS_VLAN)))
661086df 2997 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2998
2999 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3000
3001 i = tx_ring->next_to_use;
3002 while (count--) {
3003 buffer_info = &tx_ring->buffer_info[i];
3004 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3005 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3006 tx_desc->read.cmd_type_len =
3007 cpu_to_le32(cmd_type_len | buffer_info->length);
3008 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3009 i++;
3010 if (i == tx_ring->count)
3011 i = 0;
3012 }
3013
3014 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3015 /* Force memory writes to complete before letting h/w
3016 * know there are new descriptors to fetch. (Only
3017 * applicable for weak-ordered memory model archs,
3018 * such as IA-64). */
3019 wmb();
3020
3021 tx_ring->next_to_use = i;
3022 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3023 /* we need this if more than one processor can write to our tail
3024 * at a time, it syncronizes IO on IA64/Altix systems */
3025 mmiowb();
3026}
3027
3028static int __igb_maybe_stop_tx(struct net_device *netdev,
3029 struct igb_ring *tx_ring, int size)
3030{
3031 struct igb_adapter *adapter = netdev_priv(netdev);
3032
661086df 3033 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3034
9d5c8243
AK		 3035 /* Herbert's original patch had:
3036 * smp_mb__after_netif_stop_queue();
3037 * but since that doesn't exist yet, just open code it. */
3038 smp_mb();
3039
3040 /* We need to check again in a case another CPU has just
3041 * made room available. */
3042 if (IGB_DESC_UNUSED(tx_ring) < size)
3043 return -EBUSY;
3044
3045 /* A reprieve! */
661086df 3046 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3047 ++adapter->restart_queue;
3048 return 0;
3049}
3050
3051static int igb_maybe_stop_tx(struct net_device *netdev,
3052 struct igb_ring *tx_ring, int size)
3053{
3054 if (IGB_DESC_UNUSED(tx_ring) >= size)
3055 return 0;
3056 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3057}
3058
9d5c8243
AK		 3059static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3060 struct net_device *netdev,
3061 struct igb_ring *tx_ring)
3062{
3063 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3064 unsigned int first;
9d5c8243 3065 unsigned int tx_flags = 0;
9d5c8243
AK		 3066 u8 hdr_len = 0;
3067 int tso = 0;
33af6bcc 3068 union skb_shared_tx *shtx;
9d5c8243 3069
9d5c8243
AK		 3070 if (test_bit(__IGB_DOWN, &adapter->state)) {
3071 dev_kfree_skb_any(skb);
3072 return NETDEV_TX_OK;
3073 }
3074
3075 if (skb->len <= 0) {
3076 dev_kfree_skb_any(skb);
3077 return NETDEV_TX_OK;
3078 }
3079
9d5c8243
AK		 3080 /* need: 1 descriptor per page,
3081 * + 2 desc gap to keep tail from touching head,
3082 * + 1 desc for skb->data,
3083 * + 1 desc for context descriptor,
3084 * otherwise try next time */
3085 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3086 /* this is a hard error */
9d5c8243
AK		 3087 return NETDEV_TX_BUSY;
3088 }
33af6bcc
PO		 3089
3090 /*
3091 * TODO: check that there currently is no other packet with
3092 * time stamping in the queue
3093 *
3094 * When doing time stamping, keep the connection to the socket
3095 * a while longer: it is still needed by skb_hwtstamp_tx(),
3096 * called either in igb_tx_hwtstamp() or by our caller when
3097 * doing software time stamping.
3098 */
3099 shtx = skb_tx(skb);
3100 if (unlikely(shtx->hardware)) {
3101 shtx->in_progress = 1;
3102 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3103 } else if (likely(!shtx->software)) {
3104 /*
3105 * TODO: can this be solved in dev.c:dev_hard_start_xmit()?
3106 * There are probably unmodified driver which do something
3107 * like this and thus don't work in combination with
3108 * SOF_TIMESTAMPING_TX_SOFTWARE.
3109 */
3110 skb_orphan(skb);
3111 }
9d5c8243
AK		 3112
3113 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3114 tx_flags |= IGB_TX_FLAGS_VLAN;
3115 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3116 }
3117
661086df
PWJ		 3118 if (skb->protocol == htons(ETH_P_IP))
3119 tx_flags |= IGB_TX_FLAGS_IPV4;
3120
0e014cb1 3121 first = tx_ring->next_to_use;
9d5c8243
AK		 3122 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3123 &hdr_len) : 0;
3124
3125 if (tso < 0) {
3126 dev_kfree_skb_any(skb);
9d5c8243
AK		 3127 return NETDEV_TX_OK;
3128 }
3129
3130 if (tso)
3131 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3132 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3133 (skb->ip_summed == CHECKSUM_PARTIAL))
3134 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3135
9d5c8243 3136 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3137 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3138 skb->len, hdr_len);
3139
3140 netdev->trans_start = jiffies;
3141
3142 /* Make sure there is space in the ring for the next send. */
3143 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3144
9d5c8243
AK		 3145 return NETDEV_TX_OK;
3146}
3147
3148static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3149{
3150 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3151 struct igb_ring *tx_ring;
3152
661086df
PWJ		 3153 int r_idx = 0;
3154 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3155 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3156
3157 /* This goes back to the question of how to logically map a tx queue
3158 * to a flow. Right now, performance is impacted slightly negatively
3159 * if using multiple tx queues. If the stack breaks away from a
3160 * single qdisc implementation, we can look at this again. */
3161 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3162}
3163
3164/**
3165 * igb_tx_timeout - Respond to a Tx Hang
3166 * @netdev: network interface device structure
3167 **/
3168static void igb_tx_timeout(struct net_device *netdev)
3169{
3170 struct igb_adapter *adapter = netdev_priv(netdev);
3171 struct e1000_hw *hw = &adapter->hw;
3172
3173 /* Do the reset outside of interrupt context */
3174 adapter->tx_timeout_count++;
3175 schedule_work(&adapter->reset_task);
265de409
AD		 3176 wr32(E1000_EICS,
3177 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3178}
3179
3180static void igb_reset_task(struct work_struct *work)
3181{
3182 struct igb_adapter *adapter;
3183 adapter = container_of(work, struct igb_adapter, reset_task);
3184
3185 igb_reinit_locked(adapter);
3186}
3187
3188/**
3189 * igb_get_stats - Get System Network Statistics
3190 * @netdev: network interface device structure
3191 *
3192 * Returns the address of the device statistics structure.
3193 * The statistics are actually updated from the timer callback.
3194 **/
73cd78f1 3195static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3196{
3197 struct igb_adapter *adapter = netdev_priv(netdev);
3198
3199 /* only return the current stats */
3200 return &adapter->net_stats;
3201}
3202
3203/**
3204 * igb_change_mtu - Change the Maximum Transfer Unit
3205 * @netdev: network interface device structure
3206 * @new_mtu: new value for maximum frame size
3207 *
3208 * Returns 0 on success, negative on failure
3209 **/
3210static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3211{
3212 struct igb_adapter *adapter = netdev_priv(netdev);
3213 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3214
3215 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3216 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3217 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3218 return -EINVAL;
3219 }
3220
3221#define MAX_STD_JUMBO_FRAME_SIZE 9234
3222 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3223 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3224 return -EINVAL;
3225 }
3226
3227 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3228 msleep(1);
73cd78f1 3229
9d5c8243
AK		 3230 /* igb_down has a dependency on max_frame_size */
3231 adapter->max_frame_size = max_frame;
3232 if (netif_running(netdev))
3233 igb_down(adapter);
3234
3235 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3236 * means we reserve 2 more, this pushes us to allocate from the next
3237 * larger slab size.
3238 * i.e. RXBUFFER_2048 --> size-4096 slab
3239 */
3240
3241 if (max_frame <= IGB_RXBUFFER_256)
3242 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3243 else if (max_frame <= IGB_RXBUFFER_512)
3244 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3245 else if (max_frame <= IGB_RXBUFFER_1024)
3246 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3247 else if (max_frame <= IGB_RXBUFFER_2048)
3248 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3249 else
bf36c1a0
AD		 3250#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3251 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3252#else
3253 adapter->rx_buffer_len = PAGE_SIZE / 2;
3254#endif
9d5c8243
AK		 3255 /* adjust allocation if LPE protects us, and we aren't using SBP */
3256 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3257 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3258 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3259
3260 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3261 netdev->mtu, new_mtu);
3262 netdev->mtu = new_mtu;
3263
3264 if (netif_running(netdev))
3265 igb_up(adapter);
3266 else
3267 igb_reset(adapter);
3268
3269 clear_bit(__IGB_RESETTING, &adapter->state);
3270
3271 return 0;
3272}
3273
3274/**
3275 * igb_update_stats - Update the board statistics counters
3276 * @adapter: board private structure
3277 **/
3278
3279void igb_update_stats(struct igb_adapter *adapter)
3280{
3281 struct e1000_hw *hw = &adapter->hw;
3282 struct pci_dev *pdev = adapter->pdev;
3283 u16 phy_tmp;
3284
3285#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3286
3287 /*
3288 * Prevent stats update while adapter is being reset, or if the pci
3289 * connection is down.
3290 */
3291 if (adapter->link_speed == 0)
3292 return;
3293 if (pci_channel_offline(pdev))
3294 return;
3295
3296 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3297 adapter->stats.gprc += rd32(E1000_GPRC);
3298 adapter->stats.gorc += rd32(E1000_GORCL);
3299 rd32(E1000_GORCH); /* clear GORCL */
3300 adapter->stats.bprc += rd32(E1000_BPRC);
3301 adapter->stats.mprc += rd32(E1000_MPRC);
3302 adapter->stats.roc += rd32(E1000_ROC);
3303
3304 adapter->stats.prc64 += rd32(E1000_PRC64);
3305 adapter->stats.prc127 += rd32(E1000_PRC127);
3306 adapter->stats.prc255 += rd32(E1000_PRC255);
3307 adapter->stats.prc511 += rd32(E1000_PRC511);
3308 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3309 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3310 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3311 adapter->stats.sec += rd32(E1000_SEC);
3312
3313 adapter->stats.mpc += rd32(E1000_MPC);
3314 adapter->stats.scc += rd32(E1000_SCC);
3315 adapter->stats.ecol += rd32(E1000_ECOL);
3316 adapter->stats.mcc += rd32(E1000_MCC);
3317 adapter->stats.latecol += rd32(E1000_LATECOL);
3318 adapter->stats.dc += rd32(E1000_DC);
3319 adapter->stats.rlec += rd32(E1000_RLEC);
3320 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3321 adapter->stats.xontxc += rd32(E1000_XONTXC);
3322 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3323 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3324 adapter->stats.fcruc += rd32(E1000_FCRUC);
3325 adapter->stats.gptc += rd32(E1000_GPTC);
3326 adapter->stats.gotc += rd32(E1000_GOTCL);
3327 rd32(E1000_GOTCH); /* clear GOTCL */
3328 adapter->stats.rnbc += rd32(E1000_RNBC);
3329 adapter->stats.ruc += rd32(E1000_RUC);
3330 adapter->stats.rfc += rd32(E1000_RFC);
3331 adapter->stats.rjc += rd32(E1000_RJC);
3332 adapter->stats.tor += rd32(E1000_TORH);
3333 adapter->stats.tot += rd32(E1000_TOTH);
3334 adapter->stats.tpr += rd32(E1000_TPR);
3335
3336 adapter->stats.ptc64 += rd32(E1000_PTC64);
3337 adapter->stats.ptc127 += rd32(E1000_PTC127);
3338 adapter->stats.ptc255 += rd32(E1000_PTC255);
3339 adapter->stats.ptc511 += rd32(E1000_PTC511);
3340 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3341 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3342
3343 adapter->stats.mptc += rd32(E1000_MPTC);
3344 adapter->stats.bptc += rd32(E1000_BPTC);
3345
3346 /* used for adaptive IFS */
3347
3348 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3349 adapter->stats.tpt += hw->mac.tx_packet_delta;
3350 hw->mac.collision_delta = rd32(E1000_COLC);
3351 adapter->stats.colc += hw->mac.collision_delta;
3352
3353 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3354 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3355 adapter->stats.tncrs += rd32(E1000_TNCRS);
3356 adapter->stats.tsctc += rd32(E1000_TSCTC);
3357 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3358
3359 adapter->stats.iac += rd32(E1000_IAC);
3360 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3361 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3362 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3363 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3364 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3365 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3366 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3367 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3368
3369 /* Fill out the OS statistics structure */
3370 adapter->net_stats.multicast = adapter->stats.mprc;
3371 adapter->net_stats.collisions = adapter->stats.colc;
3372
3373 /* Rx Errors */
3374
3375 /* RLEC on some newer hardware can be incorrect so build
3376 * our own version based on RUC and ROC */
3377 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3378 adapter->stats.crcerrs + adapter->stats.algnerrc +
3379 adapter->stats.ruc + adapter->stats.roc +
3380 adapter->stats.cexterr;
3381 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3382 adapter->stats.roc;
3383 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3384 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3385 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3386
3387 /* Tx Errors */
3388 adapter->net_stats.tx_errors = adapter->stats.ecol +
3389 adapter->stats.latecol;
3390 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3391 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3392 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3393
3394 /* Tx Dropped needs to be maintained elsewhere */
3395
3396 /* Phy Stats */
3397 if (hw->phy.media_type == e1000_media_type_copper) {
3398 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3399 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3400 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3401 adapter->phy_stats.idle_errors += phy_tmp;
3402 }
3403 }
3404
3405 /* Management Stats */
3406 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3407 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3408 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3409}
3410
9d5c8243
AK		 3411static irqreturn_t igb_msix_other(int irq, void *data)
3412{
3413 struct net_device *netdev = data;
3414 struct igb_adapter *adapter = netdev_priv(netdev);
3415 struct e1000_hw *hw = &adapter->hw;
844290e5 3416 u32 icr = rd32(E1000_ICR);
9d5c8243 3417
844290e5 3418 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3419
3420 if(icr & E1000_ICR_DOUTSYNC) {
3421 /* HW is reporting DMA is out of sync */
3422 adapter->stats.doosync++;
3423 }
844290e5
PW		 3424 if (!(icr & E1000_ICR_LSC))
3425 goto no_link_interrupt;
3426 hw->mac.get_link_status = 1;
3427 /* guard against interrupt when we're going down */
3428 if (!test_bit(__IGB_DOWN, &adapter->state))
3429 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3430
9d5c8243 3431no_link_interrupt:
dda0e083 3432 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3433 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3434
3435 return IRQ_HANDLED;
3436}
3437
3438static irqreturn_t igb_msix_tx(int irq, void *data)
3439{
3440 struct igb_ring *tx_ring = data;
3441 struct igb_adapter *adapter = tx_ring->adapter;
3442 struct e1000_hw *hw = &adapter->hw;
3443
421e02f0 3444#ifdef CONFIG_IGB_DCA
7dfc16fa 3445 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3446 igb_update_tx_dca(tx_ring);
3447#endif
73cd78f1 3448
9d5c8243
AK		 3449 tx_ring->total_bytes = 0;
3450 tx_ring->total_packets = 0;
661086df
PWJ		 3451
3452 /* auto mask will automatically reenable the interrupt when we write
3453 * EICS */
3b644cf6 3454 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3455 /* Ring was not completely cleaned, so fire another interrupt */
3456 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3457 else
9d5c8243 3458 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3459
9d5c8243
AK		 3460 return IRQ_HANDLED;
3461}
3462
6eb5a7f1
AD		 3463static void igb_write_itr(struct igb_ring *ring)
3464{
3465 struct e1000_hw *hw = &ring->adapter->hw;
3466 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3467 switch (hw->mac.type) {
3468 case e1000_82576:
73cd78f1 3469 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3470 0x80000000);
3471 break;
3472 default:
73cd78f1 3473 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3474 (ring->itr_val << 16));
3475 break;
3476 }
3477 ring->set_itr = 0;
3478 }
3479}
3480
9d5c8243
AK		 3481static irqreturn_t igb_msix_rx(int irq, void *data)
3482{
3483 struct igb_ring *rx_ring = data;
9d5c8243 3484
844290e5
PW		 3485 /* Write the ITR value calculated at the end of the
3486 * previous interrupt.
3487 */
9d5c8243 3488
6eb5a7f1 3489 igb_write_itr(rx_ring);
9d5c8243 3490
288379f0
BH		 3491 if (napi_schedule_prep(&rx_ring->napi))
3492 __napi_schedule(&rx_ring->napi);
844290e5 3493
421e02f0 3494#ifdef CONFIG_IGB_DCA
8d253320 3495 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3496 igb_update_rx_dca(rx_ring);
3497#endif
3498 return IRQ_HANDLED;
3499}
3500
421e02f0 3501#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3502static void igb_update_rx_dca(struct igb_ring *rx_ring)
3503{
3504 u32 dca_rxctrl;
3505 struct igb_adapter *adapter = rx_ring->adapter;
3506 struct e1000_hw *hw = &adapter->hw;
3507 int cpu = get_cpu();
26bc19ec 3508 int q = rx_ring->reg_idx;
fe4506b6
JC		 3509
3510 if (rx_ring->cpu != cpu) {
3511 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3512 if (hw->mac.type == e1000_82576) {
3513 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3514 dca_rxctrl |= dca_get_tag(cpu) <<
3515 E1000_DCA_RXCTRL_CPUID_SHIFT;
3516 } else {
3517 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3518 dca_rxctrl |= dca_get_tag(cpu);
3519 }
fe4506b6
JC		 3520 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3521 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3522 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3523 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3524 rx_ring->cpu = cpu;
3525 }
3526 put_cpu();
3527}
3528
3529static void igb_update_tx_dca(struct igb_ring *tx_ring)
3530{
3531 u32 dca_txctrl;
3532 struct igb_adapter *adapter = tx_ring->adapter;
3533 struct e1000_hw *hw = &adapter->hw;
3534 int cpu = get_cpu();
26bc19ec 3535 int q = tx_ring->reg_idx;
fe4506b6
JC		 3536
3537 if (tx_ring->cpu != cpu) {
3538 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3539 if (hw->mac.type == e1000_82576) {
3540 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3541 dca_txctrl |= dca_get_tag(cpu) <<
3542 E1000_DCA_TXCTRL_CPUID_SHIFT;
3543 } else {
3544 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3545 dca_txctrl |= dca_get_tag(cpu);
3546 }
fe4506b6
JC		 3547 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3548 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3549 tx_ring->cpu = cpu;
3550 }
3551 put_cpu();
3552}
3553
3554static void igb_setup_dca(struct igb_adapter *adapter)
3555{
3556 int i;
3557
7dfc16fa 3558 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3559 return;
3560
3561 for (i = 0; i < adapter->num_tx_queues; i++) {
3562 adapter->tx_ring[i].cpu = -1;
3563 igb_update_tx_dca(&adapter->tx_ring[i]);
3564 }
3565 for (i = 0; i < adapter->num_rx_queues; i++) {
3566 adapter->rx_ring[i].cpu = -1;
3567 igb_update_rx_dca(&adapter->rx_ring[i]);
3568 }
3569}
3570
3571static int __igb_notify_dca(struct device *dev, void *data)
3572{
3573 struct net_device *netdev = dev_get_drvdata(dev);
3574 struct igb_adapter *adapter = netdev_priv(netdev);
3575 struct e1000_hw *hw = &adapter->hw;
3576 unsigned long event = *(unsigned long *)data;
3577
3578 switch (event) {
3579 case DCA_PROVIDER_ADD:
3580 /* if already enabled, don't do it again */
7dfc16fa 3581 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3582 break;
fe4506b6
JC		 3583 /* Always use CB2 mode, difference is masked
3584 * in the CB driver. */
cbd347ad 3585 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3586 if (dca_add_requester(dev) == 0) {
bbd98fe4 3587 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3588 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3589 igb_setup_dca(adapter);
3590 break;
3591 }
3592 /* Fall Through since DCA is disabled. */
3593 case DCA_PROVIDER_REMOVE:
7dfc16fa 3594 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3595 /* without this a class_device is left
3596 * hanging around in the sysfs model */
3597 dca_remove_requester(dev);
3598 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3599 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3600 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3601 }
3602 break;
3603 }
bbd98fe4 3604
fe4506b6 3605 return 0;
9d5c8243
AK		 3606}
3607
fe4506b6
JC		 3608static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3609 void *p)
3610{
3611 int ret_val;
3612
3613 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3614 __igb_notify_dca);
3615
3616 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3617}
421e02f0 3618#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3619
3620/**
3621 * igb_intr_msi - Interrupt Handler
3622 * @irq: interrupt number
3623 * @data: pointer to a network interface device structure
3624 **/
3625static irqreturn_t igb_intr_msi(int irq, void *data)
3626{
3627 struct net_device *netdev = data;
3628 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3629 struct e1000_hw *hw = &adapter->hw;
3630 /* read ICR disables interrupts using IAM */
3631 u32 icr = rd32(E1000_ICR);
3632
6eb5a7f1 3633 igb_write_itr(adapter->rx_ring);
9d5c8243 3634
dda0e083
AD		 3635 if(icr & E1000_ICR_DOUTSYNC) {
3636 /* HW is reporting DMA is out of sync */
3637 adapter->stats.doosync++;
3638 }
3639
9d5c8243
AK		 3640 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3641 hw->mac.get_link_status = 1;
3642 if (!test_bit(__IGB_DOWN, &adapter->state))
3643 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3644 }
3645
288379f0 3646 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3647
3648 return IRQ_HANDLED;
3649}
3650
3651/**
4a3c6433 3652 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3653 * @irq: interrupt number
3654 * @data: pointer to a network interface device structure
3655 **/
3656static irqreturn_t igb_intr(int irq, void *data)
3657{
3658 struct net_device *netdev = data;
3659 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3660 struct e1000_hw *hw = &adapter->hw;
3661 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3662 * need for the IMC write */
3663 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3664 if (!icr)
3665 return IRQ_NONE; /* Not our interrupt */
3666
6eb5a7f1 3667 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3668
3669 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3670 * not set, then the adapter didn't send an interrupt */
3671 if (!(icr & E1000_ICR_INT_ASSERTED))
3672 return IRQ_NONE;
3673
dda0e083
AD		 3674 if(icr & E1000_ICR_DOUTSYNC) {
3675 /* HW is reporting DMA is out of sync */
3676 adapter->stats.doosync++;
3677 }
3678
9d5c8243
AK		 3679 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3680 hw->mac.get_link_status = 1;
3681 /* guard against interrupt when we're going down */
3682 if (!test_bit(__IGB_DOWN, &adapter->state))
3683 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3684 }
3685
288379f0 3686 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3687
3688 return IRQ_HANDLED;
3689}
3690
3691/**
661086df
PWJ		 3692 * igb_poll - NAPI Rx polling callback
3693 * @napi: napi polling structure
3694 * @budget: count of how many packets we should handle
9d5c8243 3695 **/
661086df 3696static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3697{
661086df
PWJ		 3698 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3699 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3700 struct net_device *netdev = adapter->netdev;
661086df 3701 int tx_clean_complete, work_done = 0;
9d5c8243 3702
661086df 3703 /* this poll routine only supports one tx and one rx queue */
421e02f0 3704#ifdef CONFIG_IGB_DCA
7dfc16fa 3705 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3706 igb_update_tx_dca(&adapter->tx_ring[0]);
3707#endif
661086df 3708 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3709
421e02f0 3710#ifdef CONFIG_IGB_DCA
7dfc16fa 3711 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3712 igb_update_rx_dca(&adapter->rx_ring[0]);
3713#endif
661086df 3714 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3715
3716 /* If no Tx and not enough Rx work done, exit the polling mode */
3717 if ((tx_clean_complete && (work_done < budget)) ||
3718 !netif_running(netdev)) {
9d5c8243 3719 if (adapter->itr_setting & 3)
6eb5a7f1 3720 igb_set_itr(adapter);
288379f0 3721 napi_complete(napi);
9d5c8243
AK		 3722 if (!test_bit(__IGB_DOWN, &adapter->state))
3723 igb_irq_enable(adapter);
3724 return 0;
3725 }
3726
3727 return 1;
3728}
3729
3730static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3731{
3732 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3733 struct igb_adapter *adapter = rx_ring->adapter;
3734 struct e1000_hw *hw = &adapter->hw;
3735 struct net_device *netdev = adapter->netdev;
3736 int work_done = 0;
3737
421e02f0 3738#ifdef CONFIG_IGB_DCA
7dfc16fa 3739 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3740 igb_update_rx_dca(rx_ring);
3741#endif
3b644cf6 3742 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 3743
9d5c8243
AK		 3744 /* If not enough Rx work done, exit the polling mode */
3745 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3746 napi_complete(napi);
9d5c8243 3747
6eb5a7f1
AD		 3748 if (adapter->itr_setting & 3) {
3749 if (adapter->num_rx_queues == 1)
3750 igb_set_itr(adapter);
3751 else
3752 igb_update_ring_itr(rx_ring);
9d5c8243 3753 }
844290e5
PW		 3754 if (!test_bit(__IGB_DOWN, &adapter->state))
3755 wr32(E1000_EIMS, rx_ring->eims_value);
3756
9d5c8243
AK		 3757 return 0;
3758 }
3759
3760 return 1;
3761}
6d8126f9 3762
33af6bcc
PO		 3763/**
3764 * igb_hwtstamp - utility function which checks for TX time stamp
3765 * @adapter: board private structure
3766 * @skb: packet that was just sent
3767 *
3768 * If we were asked to do hardware stamping and such a time stamp is
3769 * available, then it must have been for this skb here because we only
3770 * allow only one such packet into the queue.
3771 */
3772static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
3773{
3774 union skb_shared_tx *shtx = skb_tx(skb);
3775 struct e1000_hw *hw = &adapter->hw;
3776
3777 if (unlikely(shtx->hardware)) {
3778 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
3779 if (valid) {
3780 u64 regval = rd32(E1000_TXSTMPL);
3781 u64 ns;
3782 struct skb_shared_hwtstamps shhwtstamps;
3783
3784 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3785 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
3786 ns = timecounter_cyc2time(&adapter->clock,
3787 regval);
3788 timecompare_update(&adapter->compare, ns);
3789 shhwtstamps.hwtstamp = ns_to_ktime(ns);
3790 shhwtstamps.syststamp =
3791 timecompare_transform(&adapter->compare, ns);
3792 skb_tstamp_tx(skb, &shhwtstamps);
3793 }
3794
3795 /* delayed orphaning: skb_tstamp_tx() needs the socket */
3796 skb_orphan(skb);
3797 }
3798}
3799
9d5c8243
AK		 3800/**
3801 * igb_clean_tx_irq - Reclaim resources after transmit completes
3802 * @adapter: board private structure
3803 * returns true if ring is completely cleaned
3804 **/
3b644cf6 3805static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3806{
3b644cf6 3807 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3808 struct net_device *netdev = adapter->netdev;
0e014cb1 3809 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3810 struct igb_buffer *buffer_info;
3811 struct sk_buff *skb;
0e014cb1 3812 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3813 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3814 unsigned int i, eop, count = 0;
3815 bool cleaned = false;
9d5c8243 3816
9d5c8243 3817 i = tx_ring->next_to_clean;
0e014cb1
AD		 3818 eop = tx_ring->buffer_info[i].next_to_watch;
3819 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3820
3821 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3822 (count < tx_ring->count)) {
3823 for (cleaned = false; !cleaned; count++) {
3824 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3825 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3826 cleaned = (i == eop);
9d5c8243
AK		 3827 skb = buffer_info->skb;
3828
3829 if (skb) {
3830 unsigned int segs, bytecount;
3831 /* gso_segs is currently only valid for tcp */
3832 segs = skb_shinfo(skb)->gso_segs ?: 1;
3833 /* multiply data chunks by size of headers */
3834 bytecount = ((segs - 1) * skb_headlen(skb)) +
3835 skb->len;
3836 total_packets += segs;
3837 total_bytes += bytecount;
33af6bcc
PO		 3838
3839 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 3840 }
3841
3842 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3843 tx_desc->wb.status = 0;
9d5c8243
AK		 3844
3845 i++;
3846 if (i == tx_ring->count)
3847 i = 0;
9d5c8243 3848 }
0e014cb1
AD		 3849 eop = tx_ring->buffer_info[i].next_to_watch;
3850 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3851 }
3852
9d5c8243
AK		 3853 tx_ring->next_to_clean = i;
3854
fc7d345d 3855 if (unlikely(count &&
9d5c8243
AK		 3856 netif_carrier_ok(netdev) &&
3857 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3858 /* Make sure that anybody stopping the queue after this
3859 * sees the new next_to_clean.
3860 */
3861 smp_mb();
661086df
PWJ		 3862 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3863 !(test_bit(__IGB_DOWN, &adapter->state))) {
3864 netif_wake_subqueue(netdev, tx_ring->queue_index);
3865 ++adapter->restart_queue;
3866 }
9d5c8243
AK		 3867 }
3868
3869 if (tx_ring->detect_tx_hung) {
3870 /* Detect a transmit hang in hardware, this serializes the
3871 * check with the clearing of time_stamp and movement of i */
3872 tx_ring->detect_tx_hung = false;
3873 if (tx_ring->buffer_info[i].time_stamp &&
3874 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3875 (adapter->tx_timeout_factor * HZ))
3876 && !(rd32(E1000_STATUS) &
3877 E1000_STATUS_TXOFF)) {
3878
9d5c8243
AK		 3879 /* detected Tx unit hang */
3880 dev_err(&adapter->pdev->dev,
3881 "Detected Tx Unit Hang\n"
2d064c06 3882 " Tx Queue <%d>\n"
9d5c8243
AK		 3883 " TDH <%x>\n"
3884 " TDT <%x>\n"
3885 " next_to_use <%x>\n"
3886 " next_to_clean <%x>\n"
9d5c8243
AK		 3887 "buffer_info[next_to_clean]\n"
3888 " time_stamp <%lx>\n"
0e014cb1 3889 " next_to_watch <%x>\n"
9d5c8243
AK		 3890 " jiffies <%lx>\n"
3891 " desc.status <%x>\n",
2d064c06 3892 tx_ring->queue_index,
9d5c8243
AK		 3893 readl(adapter->hw.hw_addr + tx_ring->head),
3894 readl(adapter->hw.hw_addr + tx_ring->tail),
3895 tx_ring->next_to_use,
3896 tx_ring->next_to_clean,
9d5c8243 3897 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3898 eop,
9d5c8243 3899 jiffies,
0e014cb1 3900 eop_desc->wb.status);
661086df 3901 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3902 }
3903 }
3904 tx_ring->total_bytes += total_bytes;
3905 tx_ring->total_packets += total_packets;
e21ed353
AD		 3906 tx_ring->tx_stats.bytes += total_bytes;
3907 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3908 adapter->net_stats.tx_bytes += total_bytes;
3909 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3910 return (count < tx_ring->count);
9d5c8243
AK		 3911}
3912
9d5c8243
AK		 3913/**
3914 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3915 * @ring: pointer to receive ring receving this packet
9d5c8243 3916 * @status: descriptor status field as written by hardware
73cd78f1 3917 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 3918 * @skb: pointer to sk_buff to be indicated to stack
3919 **/
d3352520
AD		 3920static void igb_receive_skb(struct igb_ring *ring, u8 status,
3921 union e1000_adv_rx_desc * rx_desc,
3922 struct sk_buff *skb)
3923{
3924 struct igb_adapter * adapter = ring->adapter;
3925 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3926
0c8dfc83 3927 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3928 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3929 if (vlan_extracted)
5c0999b7
HX		 3930 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3931 le16_to_cpu(rx_desc->wb.upper.vlan),
3932 skb);
d3352520 3933 else
5c0999b7 3934 napi_gro_receive(&ring->napi, skb);
d3352520 3935 } else {
d3352520
AD		 3936 if (vlan_extracted)
3937 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3938 le16_to_cpu(rx_desc->wb.upper.vlan));
3939 else
d3352520 3940 netif_receive_skb(skb);
d3352520 3941 }
9d5c8243
AK		 3942}
3943
9d5c8243
AK		 3944static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3945 u32 status_err, struct sk_buff *skb)
3946{
3947 skb->ip_summed = CHECKSUM_NONE;
3948
3949 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3950 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3951 return;
3952 /* TCP/UDP checksum error bit is set */
3953 if (status_err &
3954 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3955 /* let the stack verify checksum errors */
3956 adapter->hw_csum_err++;
3957 return;
3958 }
3959 /* It must be a TCP or UDP packet with a valid checksum */
3960 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3961 skb->ip_summed = CHECKSUM_UNNECESSARY;
3962
3963 adapter->hw_csum_good++;
3964}
3965
3b644cf6
MW		 3966static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3967 int *work_done, int budget)
9d5c8243 3968{
3b644cf6 3969 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3970 struct net_device *netdev = adapter->netdev;
33af6bcc 3971 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3972 struct pci_dev *pdev = adapter->pdev;
3973 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3974 struct igb_buffer *buffer_info , *next_buffer;
3975 struct sk_buff *skb;
9d5c8243
AK		 3976 bool cleaned = false;
3977 int cleaned_count = 0;
3978 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 3979 unsigned int i;
3980 u32 length, hlen, staterr;
9d5c8243
AK		 3981
3982 i = rx_ring->next_to_clean;
69d3ca53 3983 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3984 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3985 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3986
3987 while (staterr & E1000_RXD_STAT_DD) {
3988 if (*work_done >= budget)
3989 break;
3990 (*work_done)++;
9d5c8243 3991
69d3ca53
AD		 3992 skb = buffer_info->skb;
3993 prefetch(skb->data - NET_IP_ALIGN);
3994 buffer_info->skb = NULL;
3995
3996 i++;
3997 if (i == rx_ring->count)
3998 i = 0;
3999 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4000 prefetch(next_rxd);
4001 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4002
4003 length = le16_to_cpu(rx_desc->wb.upper.length);
4004 cleaned = true;
4005 cleaned_count++;
4006
bf36c1a0
AD		 4007 if (!adapter->rx_ps_hdr_size) {
4008 pci_unmap_single(pdev, buffer_info->dma,
4009 adapter->rx_buffer_len +
4010 NET_IP_ALIGN,
4011 PCI_DMA_FROMDEVICE);
4012 skb_put(skb, length);
4013 goto send_up;
9d5c8243
AK		 4014 }
4015
69d3ca53
AD		 4016 /* HW will not DMA in data larger than the given buffer, even
4017 * if it parses the (NFS, of course) header to be larger. In
4018 * that case, it fills the header buffer and spills the rest
4019 * into the page.
4020 */
4021 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4022 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4023 if (hlen > adapter->rx_ps_hdr_size)
4024 hlen = adapter->rx_ps_hdr_size;
4025
bf36c1a0
AD		 4026 if (!skb_shinfo(skb)->nr_frags) {
4027 pci_unmap_single(pdev, buffer_info->dma,
73cd78f1 4028 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
bf36c1a0
AD		 4029 PCI_DMA_FROMDEVICE);
4030 skb_put(skb, hlen);
4031 }
4032
4033 if (length) {
9d5c8243 4034 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4035 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4036 buffer_info->page_dma = 0;
bf36c1a0
AD		 4037
4038 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4039 buffer_info->page,
4040 buffer_info->page_offset,
4041 length);
4042
4043 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4044 (page_count(buffer_info->page) != 1))
4045 buffer_info->page = NULL;
4046 else
4047 get_page(buffer_info->page);
9d5c8243
AK		 4048
4049 skb->len += length;
4050 skb->data_len += length;
9d5c8243 4051
bf36c1a0 4052 skb->truesize += length;
9d5c8243 4053 }
9d5c8243 4054
bf36c1a0 4055 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4056 buffer_info->skb = next_buffer->skb;
4057 buffer_info->dma = next_buffer->dma;
4058 next_buffer->skb = skb;
4059 next_buffer->dma = 0;
bf36c1a0
AD		 4060 goto next_desc;
4061 }
69d3ca53 4062send_up:
33af6bcc
PO		 4063 /*
4064 * If this bit is set, then the RX registers contain
4065 * the time stamp. No other packet will be time
4066 * stamped until we read these registers, so read the
4067 * registers to make them available again. Because
4068 * only one packet can be time stamped at a time, we
4069 * know that the register values must belong to this
4070 * one here and therefore we don't need to compare
4071 * any of the additional attributes stored for it.
4072 *
4073 * If nothing went wrong, then it should have a
4074 * skb_shared_tx that we can turn into a
4075 * skb_shared_hwtstamps.
4076 *
4077 * TODO: can time stamping be triggered (thus locking
4078 * the registers) without the packet reaching this point
4079 * here? In that case RX time stamping would get stuck.
4080 *
4081 * TODO: in "time stamp all packets" mode this bit is
4082 * not set. Need a global flag for this mode and then
4083 * always read the registers. Cannot be done without
4084 * a race condition.
4085 */
4086 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4087 u64 regval;
4088 u64 ns;
4089 struct skb_shared_hwtstamps *shhwtstamps =
4090 skb_hwtstamps(skb);
4091
4092 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4093 "igb: no RX time stamp available for time stamped packet");
4094 regval = rd32(E1000_RXSTMPL);
4095 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4096 ns = timecounter_cyc2time(&adapter->clock, regval);
4097 timecompare_update(&adapter->compare, ns);
4098 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4099 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4100 shhwtstamps->syststamp =
4101 timecompare_transform(&adapter->compare, ns);
4102 }
4103
9d5c8243
AK		 4104 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4105 dev_kfree_skb_irq(skb);
4106 goto next_desc;
4107 }
9d5c8243
AK		 4108
4109 total_bytes += skb->len;
4110 total_packets++;
4111
4112 igb_rx_checksum_adv(adapter, staterr, skb);
4113
4114 skb->protocol = eth_type_trans(skb, netdev);
4115
d3352520 4116 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4117
9d5c8243
AK		 4118next_desc:
4119 rx_desc->wb.upper.status_error = 0;
4120
4121 /* return some buffers to hardware, one at a time is too slow */
4122 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4123 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4124 cleaned_count = 0;
4125 }
4126
4127 /* use prefetched values */
4128 rx_desc = next_rxd;
4129 buffer_info = next_buffer;
9d5c8243
AK		 4130 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4131 }
bf36c1a0 4132
9d5c8243
AK		 4133 rx_ring->next_to_clean = i;
4134 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4135
4136 if (cleaned_count)
3b644cf6 4137 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4138
4139 rx_ring->total_packets += total_packets;
4140 rx_ring->total_bytes += total_bytes;
4141 rx_ring->rx_stats.packets += total_packets;
4142 rx_ring->rx_stats.bytes += total_bytes;
4143 adapter->net_stats.rx_bytes += total_bytes;
4144 adapter->net_stats.rx_packets += total_packets;
4145 return cleaned;
4146}
4147
9d5c8243
AK		 4148/**
4149 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4150 * @adapter: address of board private structure
4151 **/
3b644cf6 4152static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4153 int cleaned_count)
4154{
3b644cf6 4155 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4156 struct net_device *netdev = adapter->netdev;
4157 struct pci_dev *pdev = adapter->pdev;
4158 union e1000_adv_rx_desc *rx_desc;
4159 struct igb_buffer *buffer_info;
4160 struct sk_buff *skb;
4161 unsigned int i;
db761762 4162 int bufsz;
9d5c8243
AK		 4163
4164 i = rx_ring->next_to_use;
4165 buffer_info = &rx_ring->buffer_info[i];
4166
db761762
AD		 4167 if (adapter->rx_ps_hdr_size)
4168 bufsz = adapter->rx_ps_hdr_size;
4169 else
4170 bufsz = adapter->rx_buffer_len;
4171 bufsz += NET_IP_ALIGN;
4172
9d5c8243
AK		 4173 while (cleaned_count--) {
4174 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4175
bf36c1a0 4176 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4177 if (!buffer_info->page) {
bf36c1a0
AD		 4178 buffer_info->page = alloc_page(GFP_ATOMIC);
4179 if (!buffer_info->page) {
4180 adapter->alloc_rx_buff_failed++;
4181 goto no_buffers;
4182 }
4183 buffer_info->page_offset = 0;
4184 } else {
4185 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4186 }
4187 buffer_info->page_dma =
db761762 4188 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4189 buffer_info->page_offset,
4190 PAGE_SIZE / 2,
9d5c8243
AK		 4191 PCI_DMA_FROMDEVICE);
4192 }
4193
4194 if (!buffer_info->skb) {
9d5c8243 4195 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4196 if (!skb) {
4197 adapter->alloc_rx_buff_failed++;
4198 goto no_buffers;
4199 }
4200
4201 /* Make buffer alignment 2 beyond a 16 byte boundary
4202 * this will result in a 16 byte aligned IP header after
4203 * the 14 byte MAC header is removed
4204 */
4205 skb_reserve(skb, NET_IP_ALIGN);
4206
4207 buffer_info->skb = skb;
4208 buffer_info->dma = pci_map_single(pdev, skb->data,
4209 bufsz,
4210 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4211 }
4212 /* Refresh the desc even if buffer_addrs didn't change because
4213 * each write-back erases this info. */
4214 if (adapter->rx_ps_hdr_size) {
4215 rx_desc->read.pkt_addr =
4216 cpu_to_le64(buffer_info->page_dma);
4217 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4218 } else {
4219 rx_desc->read.pkt_addr =
4220 cpu_to_le64(buffer_info->dma);
4221 rx_desc->read.hdr_addr = 0;
4222 }
4223
4224 i++;
4225 if (i == rx_ring->count)
4226 i = 0;
4227 buffer_info = &rx_ring->buffer_info[i];
4228 }
4229
4230no_buffers:
4231 if (rx_ring->next_to_use != i) {
4232 rx_ring->next_to_use = i;
4233 if (i == 0)
4234 i = (rx_ring->count - 1);
4235 else
4236 i--;
4237
4238 /* Force memory writes to complete before letting h/w
4239 * know there are new descriptors to fetch. (Only
4240 * applicable for weak-ordered memory model archs,
4241 * such as IA-64). */
4242 wmb();
4243 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4244 }
4245}
4246
4247/**
4248 * igb_mii_ioctl -
4249 * @netdev:
4250 * @ifreq:
4251 * @cmd:
4252 **/
4253static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4254{
4255 struct igb_adapter *adapter = netdev_priv(netdev);
4256 struct mii_ioctl_data *data = if_mii(ifr);
4257
4258 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4259 return -EOPNOTSUPP;
4260
4261 switch (cmd) {
4262 case SIOCGMIIPHY:
4263 data->phy_id = adapter->hw.phy.addr;
4264 break;
4265 case SIOCGMIIREG:
4266 if (!capable(CAP_NET_ADMIN))
4267 return -EPERM;
f5f4cf08
AD		 4268 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4269 &data->val_out))
9d5c8243
AK		 4270 return -EIO;
4271 break;
4272 case SIOCSMIIREG:
4273 default:
4274 return -EOPNOTSUPP;
4275 }
4276 return 0;
4277}
4278
c6cb090b
PO		 4279/**
4280 * igb_hwtstamp_ioctl - control hardware time stamping
4281 * @netdev:
4282 * @ifreq:
4283 * @cmd:
4284 *
33af6bcc
PO		 4285 * Outgoing time stamping can be enabled and disabled. Play nice and
4286 * disable it when requested, although it shouldn't case any overhead
4287 * when no packet needs it. At most one packet in the queue may be
4288 * marked for time stamping, otherwise it would be impossible to tell
4289 * for sure to which packet the hardware time stamp belongs.
4290 *
4291 * Incoming time stamping has to be configured via the hardware
4292 * filters. Not all combinations are supported, in particular event
4293 * type has to be specified. Matching the kind of event packet is
4294 * not supported, with the exception of "all V2 events regardless of
4295 * level 2 or 4".
4296 *
c6cb090b
PO		 4297 **/
4298static int igb_hwtstamp_ioctl(struct net_device *netdev,
4299 struct ifreq *ifr, int cmd)
4300{
33af6bcc
PO		 4301 struct igb_adapter *adapter = netdev_priv(netdev);
4302 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4303 struct hwtstamp_config config;
33af6bcc
PO		 4304 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4305 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4306 u32 tsync_rx_ctl_type = 0;
4307 u32 tsync_rx_cfg = 0;
4308 int is_l4 = 0;
4309 int is_l2 = 0;
4310 short port = 319; /* PTP */
4311 u32 regval;
c6cb090b
PO		 4312
4313 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4314 return -EFAULT;
4315
4316 /* reserved for future extensions */
4317 if (config.flags)
4318 return -EINVAL;
4319
33af6bcc
PO		 4320 switch (config.tx_type) {
4321 case HWTSTAMP_TX_OFF:
4322 tsync_tx_ctl_bit = 0;
4323 break;
4324 case HWTSTAMP_TX_ON:
4325 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4326 break;
4327 default:
4328 return -ERANGE;
4329 }
4330
4331 switch (config.rx_filter) {
4332 case HWTSTAMP_FILTER_NONE:
4333 tsync_rx_ctl_bit = 0;
4334 break;
4335 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4336 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4337 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4338 case HWTSTAMP_FILTER_ALL:
4339 /*
4340 * register TSYNCRXCFG must be set, therefore it is not
4341 * possible to time stamp both Sync and Delay_Req messages
4342 * => fall back to time stamping all packets
4343 */
4344 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4345 config.rx_filter = HWTSTAMP_FILTER_ALL;
4346 break;
4347 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4348 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4349 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4350 is_l4 = 1;
4351 break;
4352 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4353 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4354 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4355 is_l4 = 1;
4356 break;
4357 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4358 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4359 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4360 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4361 is_l2 = 1;
4362 is_l4 = 1;
4363 config.rx_filter = HWTSTAMP_FILTER_SOME;
4364 break;
4365 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4366 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4367 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4368 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4369 is_l2 = 1;
4370 is_l4 = 1;
4371 config.rx_filter = HWTSTAMP_FILTER_SOME;
4372 break;
4373 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4374 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4375 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4376 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4377 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4378 is_l2 = 1;
4379 break;
4380 default:
4381 return -ERANGE;
4382 }
4383
4384 /* enable/disable TX */
4385 regval = rd32(E1000_TSYNCTXCTL);
4386 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4387 wr32(E1000_TSYNCTXCTL, regval);
4388
4389 /* enable/disable RX, define which PTP packets are time stamped */
4390 regval = rd32(E1000_TSYNCRXCTL);
4391 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4392 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4393 wr32(E1000_TSYNCRXCTL, regval);
4394 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4395
4396 /*
4397 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4398 * (Ethertype to filter on)
4399 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4400 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4401 */
4402 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4403
4404 /* L4 Queue Filter[0]: only filter by source and destination port */
4405 wr32(E1000_SPQF0, htons(port));
4406 wr32(E1000_IMIREXT(0), is_l4 ?
4407 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4408 wr32(E1000_IMIR(0), is_l4 ?
4409 (htons(port)
4410 | (0<<16) /* immediate interrupt disabled */
4411 | 0 /* (1<<17) bit cleared: do not bypass
4412 destination port check */)
4413 : 0);
4414 wr32(E1000_FTQF0, is_l4 ?
4415 (0x11 /* UDP */
4416 | (1<<15) /* VF not compared */
4417 | (1<<27) /* Enable Timestamping */
4418 | (7<<28) /* only source port filter enabled,
4419 source/target address and protocol
4420 masked */)
4421 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4422 enabled */));
4423
4424 wrfl();
4425
4426 adapter->hwtstamp_config = config;
4427
4428 /* clear TX/RX time stamp registers, just to be sure */
4429 regval = rd32(E1000_TXSTMPH);
4430 regval = rd32(E1000_RXSTMPH);
c6cb090b 4431
33af6bcc
PO		 4432 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4433 -EFAULT : 0;
c6cb090b
PO		 4434}
4435
9d5c8243
AK		 4436/**
4437 * igb_ioctl -
4438 * @netdev:
4439 * @ifreq:
4440 * @cmd:
4441 **/
4442static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4443{
4444 switch (cmd) {
4445 case SIOCGMIIPHY:
4446 case SIOCGMIIREG:
4447 case SIOCSMIIREG:
4448 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 4449 case SIOCSHWTSTAMP:
4450 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 4451 default:
4452 return -EOPNOTSUPP;
4453 }
4454}
4455
4456static void igb_vlan_rx_register(struct net_device *netdev,
4457 struct vlan_group *grp)
4458{
4459 struct igb_adapter *adapter = netdev_priv(netdev);
4460 struct e1000_hw *hw = &adapter->hw;
4461 u32 ctrl, rctl;
4462
4463 igb_irq_disable(adapter);
4464 adapter->vlgrp = grp;
4465
4466 if (grp) {
4467 /* enable VLAN tag insert/strip */
4468 ctrl = rd32(E1000_CTRL);
4469 ctrl |= E1000_CTRL_VME;
4470 wr32(E1000_CTRL, ctrl);
4471
4472 /* enable VLAN receive filtering */
4473 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4474 rctl &= ~E1000_RCTL_CFIEN;
4475 wr32(E1000_RCTL, rctl);
4476 igb_update_mng_vlan(adapter);
4477 wr32(E1000_RLPML,
4478 adapter->max_frame_size + VLAN_TAG_SIZE);
4479 } else {
4480 /* disable VLAN tag insert/strip */
4481 ctrl = rd32(E1000_CTRL);
4482 ctrl &= ~E1000_CTRL_VME;
4483 wr32(E1000_CTRL, ctrl);
4484
9d5c8243
AK		 4485 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4486 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4487 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4488 }
4489 wr32(E1000_RLPML,
4490 adapter->max_frame_size);
4491 }
4492
4493 if (!test_bit(__IGB_DOWN, &adapter->state))
4494 igb_irq_enable(adapter);
4495}
4496
4497static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4498{
4499 struct igb_adapter *adapter = netdev_priv(netdev);
4500 struct e1000_hw *hw = &adapter->hw;
4501 u32 vfta, index;
4502
28b0759c 4503 if ((hw->mng_cookie.status &
9d5c8243
AK		 4504 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4505 (vid == adapter->mng_vlan_id))
4506 return;
4507 /* add VID to filter table */
4508 index = (vid >> 5) & 0x7F;
4509 vfta = array_rd32(E1000_VFTA, index);
4510 vfta |= (1 << (vid & 0x1F));
4511 igb_write_vfta(&adapter->hw, index, vfta);
4512}
4513
4514static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4515{
4516 struct igb_adapter *adapter = netdev_priv(netdev);
4517 struct e1000_hw *hw = &adapter->hw;
4518 u32 vfta, index;
4519
4520 igb_irq_disable(adapter);
4521 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4522
4523 if (!test_bit(__IGB_DOWN, &adapter->state))
4524 igb_irq_enable(adapter);
4525
4526 if ((adapter->hw.mng_cookie.status &
4527 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4528 (vid == adapter->mng_vlan_id)) {
4529 /* release control to f/w */
4530 igb_release_hw_control(adapter);
4531 return;
4532 }
4533
4534 /* remove VID from filter table */
4535 index = (vid >> 5) & 0x7F;
4536 vfta = array_rd32(E1000_VFTA, index);
4537 vfta &= ~(1 << (vid & 0x1F));
4538 igb_write_vfta(&adapter->hw, index, vfta);
4539}
4540
4541static void igb_restore_vlan(struct igb_adapter *adapter)
4542{
4543 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4544
4545 if (adapter->vlgrp) {
4546 u16 vid;
4547 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4548 if (!vlan_group_get_device(adapter->vlgrp, vid))
4549 continue;
4550 igb_vlan_rx_add_vid(adapter->netdev, vid);
4551 }
4552 }
4553}
4554
4555int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4556{
4557 struct e1000_mac_info *mac = &adapter->hw.mac;
4558
4559 mac->autoneg = 0;
4560
4561 /* Fiber NICs only allow 1000 gbps Full duplex */
4562 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4563 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4564 dev_err(&adapter->pdev->dev,
4565 "Unsupported Speed/Duplex configuration\n");
4566 return -EINVAL;
4567 }
4568
4569 switch (spddplx) {
4570 case SPEED_10 + DUPLEX_HALF:
4571 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4572 break;
4573 case SPEED_10 + DUPLEX_FULL:
4574 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4575 break;
4576 case SPEED_100 + DUPLEX_HALF:
4577 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4578 break;
4579 case SPEED_100 + DUPLEX_FULL:
4580 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4581 break;
4582 case SPEED_1000 + DUPLEX_FULL:
4583 mac->autoneg = 1;
4584 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4585 break;
4586 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4587 default:
4588 dev_err(&adapter->pdev->dev,
4589 "Unsupported Speed/Duplex configuration\n");
4590 return -EINVAL;
4591 }
4592 return 0;
4593}
4594
9d5c8243
AK		 4595static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4596{
4597 struct net_device *netdev = pci_get_drvdata(pdev);
4598 struct igb_adapter *adapter = netdev_priv(netdev);
4599 struct e1000_hw *hw = &adapter->hw;
2d064c06 4600 u32 ctrl, rctl, status;
9d5c8243
AK		 4601 u32 wufc = adapter->wol;
4602#ifdef CONFIG_PM
4603 int retval = 0;
4604#endif
4605
4606 netif_device_detach(netdev);
4607
a88f10ec
AD		 4608 if (netif_running(netdev))
4609 igb_close(netdev);
4610
4611 igb_reset_interrupt_capability(adapter);
4612
4613 igb_free_queues(adapter);
9d5c8243
AK		 4614
4615#ifdef CONFIG_PM
4616 retval = pci_save_state(pdev);
4617 if (retval)
4618 return retval;
4619#endif
4620
4621 status = rd32(E1000_STATUS);
4622 if (status & E1000_STATUS_LU)
4623 wufc &= ~E1000_WUFC_LNKC;
4624
4625 if (wufc) {
4626 igb_setup_rctl(adapter);
4627 igb_set_multi(netdev);
4628
4629 /* turn on all-multi mode if wake on multicast is enabled */
4630 if (wufc & E1000_WUFC_MC) {
4631 rctl = rd32(E1000_RCTL);
4632 rctl |= E1000_RCTL_MPE;
4633 wr32(E1000_RCTL, rctl);
4634 }
4635
4636 ctrl = rd32(E1000_CTRL);
4637 /* advertise wake from D3Cold */
4638 #define E1000_CTRL_ADVD3WUC 0x00100000
4639 /* phy power management enable */
4640 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4641 ctrl |= E1000_CTRL_ADVD3WUC;
4642 wr32(E1000_CTRL, ctrl);
4643
9d5c8243
AK		 4644 /* Allow time for pending master requests to run */
4645 igb_disable_pcie_master(&adapter->hw);
4646
4647 wr32(E1000_WUC, E1000_WUC_PME_EN);
4648 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4649 } else {
4650 wr32(E1000_WUC, 0);
4651 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4652 }
4653
2d064c06
AD		 4654 /* make sure adapter isn't asleep if manageability/wol is enabled */
4655 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4656 pci_enable_wake(pdev, PCI_D3hot, 1);
4657 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4658 } else {
4659 igb_shutdown_fiber_serdes_link_82575(hw);
4660 pci_enable_wake(pdev, PCI_D3hot, 0);
4661 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4662 }
4663
4664 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4665 * would have already happened in close and is redundant. */
4666 igb_release_hw_control(adapter);
4667
4668 pci_disable_device(pdev);
4669
4670 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4671
4672 return 0;
4673}
4674
4675#ifdef CONFIG_PM
4676static int igb_resume(struct pci_dev *pdev)
4677{
4678 struct net_device *netdev = pci_get_drvdata(pdev);
4679 struct igb_adapter *adapter = netdev_priv(netdev);
4680 struct e1000_hw *hw = &adapter->hw;
4681 u32 err;
4682
4683 pci_set_power_state(pdev, PCI_D0);
4684 pci_restore_state(pdev);
42bfd33a 4685
aed5dec3 4686 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4687 if (err) {
4688 dev_err(&pdev->dev,
4689 "igb: Cannot enable PCI device from suspend\n");
4690 return err;
4691 }
4692 pci_set_master(pdev);
4693
4694 pci_enable_wake(pdev, PCI_D3hot, 0);
4695 pci_enable_wake(pdev, PCI_D3cold, 0);
4696
a88f10ec
AD		 4697 igb_set_interrupt_capability(adapter);
4698
4699 if (igb_alloc_queues(adapter)) {
4700 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4701 return -ENOMEM;
9d5c8243
AK		 4702 }
4703
4704 /* e1000_power_up_phy(adapter); */
4705
4706 igb_reset(adapter);
a8564f03
AD		 4707
4708 /* let the f/w know that the h/w is now under the control of the
4709 * driver. */
4710 igb_get_hw_control(adapter);
4711
9d5c8243
AK		 4712 wr32(E1000_WUS, ~0);
4713
a88f10ec
AD		 4714 if (netif_running(netdev)) {
4715 err = igb_open(netdev);
4716 if (err)
4717 return err;
4718 }
9d5c8243
AK		 4719
4720 netif_device_attach(netdev);
4721
9d5c8243
AK		 4722 return 0;
4723}
4724#endif
4725
4726static void igb_shutdown(struct pci_dev *pdev)
4727{
4728 igb_suspend(pdev, PMSG_SUSPEND);
4729}
4730
4731#ifdef CONFIG_NET_POLL_CONTROLLER
4732/*
4733 * Polling 'interrupt' - used by things like netconsole to send skbs
4734 * without having to re-enable interrupts. It's not called while
4735 * the interrupt routine is executing.
4736 */
4737static void igb_netpoll(struct net_device *netdev)
4738{
4739 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4740 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4741 int i;
9d5c8243 4742
eebbbdba
AD		 4743 if (!adapter->msix_entries) {
4744 igb_irq_disable(adapter);
4745 napi_schedule(&adapter->rx_ring[0].napi);
4746 return;
4747 }
9d5c8243 4748
eebbbdba
AD		 4749 for (i = 0; i < adapter->num_tx_queues; i++) {
4750 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4751 wr32(E1000_EIMC, tx_ring->eims_value);
4752 igb_clean_tx_irq(tx_ring);
4753 wr32(E1000_EIMS, tx_ring->eims_value);
4754 }
9d5c8243 4755
eebbbdba
AD		 4756 for (i = 0; i < adapter->num_rx_queues; i++) {
4757 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4758 wr32(E1000_EIMC, rx_ring->eims_value);
4759 napi_schedule(&rx_ring->napi);
4760 }
9d5c8243
AK		 4761}
4762#endif /* CONFIG_NET_POLL_CONTROLLER */
4763
4764/**
4765 * igb_io_error_detected - called when PCI error is detected
4766 * @pdev: Pointer to PCI device
4767 * @state: The current pci connection state
4768 *
4769 * This function is called after a PCI bus error affecting
4770 * this device has been detected.
4771 */
4772static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4773 pci_channel_state_t state)
4774{
4775 struct net_device *netdev = pci_get_drvdata(pdev);
4776 struct igb_adapter *adapter = netdev_priv(netdev);
4777
4778 netif_device_detach(netdev);
4779
4780 if (netif_running(netdev))
4781 igb_down(adapter);
4782 pci_disable_device(pdev);
4783
4784 /* Request a slot slot reset. */
4785 return PCI_ERS_RESULT_NEED_RESET;
4786}
4787
4788/**
4789 * igb_io_slot_reset - called after the pci bus has been reset.
4790 * @pdev: Pointer to PCI device
4791 *
4792 * Restart the card from scratch, as if from a cold-boot. Implementation
4793 * resembles the first-half of the igb_resume routine.
4794 */
4795static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4796{
4797 struct net_device *netdev = pci_get_drvdata(pdev);
4798 struct igb_adapter *adapter = netdev_priv(netdev);
4799 struct e1000_hw *hw = &adapter->hw;
40a914fa 4800 pci_ers_result_t result;
42bfd33a 4801 int err;
9d5c8243 4802
aed5dec3 4803 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4804 dev_err(&pdev->dev,
4805 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4806 result = PCI_ERS_RESULT_DISCONNECT;
4807 } else {
4808 pci_set_master(pdev);
4809 pci_restore_state(pdev);
9d5c8243 4810
40a914fa
AD		 4811 pci_enable_wake(pdev, PCI_D3hot, 0);
4812 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4813
40a914fa
AD		 4814 igb_reset(adapter);
4815 wr32(E1000_WUS, ~0);
4816 result = PCI_ERS_RESULT_RECOVERED;
4817 }
9d5c8243 4818
ea943d41
JK		 4819 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4820 if (err) {
4821 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4822 "failed 0x%0x\n", err);
4823 /* non-fatal, continue */
4824 }
40a914fa
AD		 4825
4826 return result;
9d5c8243
AK		 4827}
4828
4829/**
4830 * igb_io_resume - called when traffic can start flowing again.
4831 * @pdev: Pointer to PCI device
4832 *
4833 * This callback is called when the error recovery driver tells us that
4834 * its OK to resume normal operation. Implementation resembles the
4835 * second-half of the igb_resume routine.
4836 */
4837static void igb_io_resume(struct pci_dev *pdev)
4838{
4839 struct net_device *netdev = pci_get_drvdata(pdev);
4840 struct igb_adapter *adapter = netdev_priv(netdev);
4841
9d5c8243
AK		 4842 if (netif_running(netdev)) {
4843 if (igb_up(adapter)) {
4844 dev_err(&pdev->dev, "igb_up failed after reset\n");
4845 return;
4846 }
4847 }
4848
4849 netif_device_attach(netdev);
4850
4851 /* let the f/w know that the h/w is now under the control of the
4852 * driver. */
4853 igb_get_hw_control(adapter);
9d5c8243
AK		 4854}
4855
4856/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)