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igb: add 82576 MAC support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
fe4506b6
JC		 44#ifdef CONFIG_DCA
45#include <linux/dca.h>
46#endif
9d5c8243
AK		 47#include "igb.h"
48
0024fd00 49#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 50char igb_driver_name[] = "igb";
51char igb_driver_version[] = DRV_VERSION;
52static const char igb_driver_string[] =
53 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 54static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243
AK		 55
56
57static const struct e1000_info *igb_info_tbl[] = {
58 [board_82575] = &e1000_82575_info,
59};
60
61static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 80static void igb_free_tx_resources(struct igb_ring *);
81static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 82void igb_update_stats(struct igb_adapter *);
83static int igb_probe(struct pci_dev *, const struct pci_device_id *);
84static void __devexit igb_remove(struct pci_dev *pdev);
85static int igb_sw_init(struct igb_adapter *);
86static int igb_open(struct net_device *);
87static int igb_close(struct net_device *);
88static void igb_configure_tx(struct igb_adapter *);
89static void igb_configure_rx(struct igb_adapter *);
90static void igb_setup_rctl(struct igb_adapter *);
91static void igb_clean_all_tx_rings(struct igb_adapter *);
92static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 93static void igb_clean_tx_ring(struct igb_ring *);
94static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 95static void igb_set_multi(struct net_device *);
96static void igb_update_phy_info(unsigned long);
97static void igb_watchdog(unsigned long);
98static void igb_watchdog_task(struct work_struct *);
99static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
100 struct igb_ring *);
101static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
102static struct net_device_stats *igb_get_stats(struct net_device *);
103static int igb_change_mtu(struct net_device *, int);
104static int igb_set_mac(struct net_device *, void *);
105static irqreturn_t igb_intr(int irq, void *);
106static irqreturn_t igb_intr_msi(int irq, void *);
107static irqreturn_t igb_msix_other(int irq, void *);
108static irqreturn_t igb_msix_rx(int irq, void *);
109static irqreturn_t igb_msix_tx(int irq, void *);
110static int igb_clean_rx_ring_msix(struct napi_struct *, int);
fe4506b6
JC		 111#ifdef CONFIG_DCA
112static void igb_update_rx_dca(struct igb_ring *);
113static void igb_update_tx_dca(struct igb_ring *);
114static void igb_setup_dca(struct igb_adapter *);
115#endif /* CONFIG_DCA */
3b644cf6 116static bool igb_clean_tx_irq(struct igb_ring *);
661086df 117static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 118static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
119static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 120static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121static void igb_tx_timeout(struct net_device *);
122static void igb_reset_task(struct work_struct *);
123static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124static void igb_vlan_rx_add_vid(struct net_device *, u16);
125static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126static void igb_restore_vlan(struct igb_adapter *);
127
128static int igb_suspend(struct pci_dev *, pm_message_t);
129#ifdef CONFIG_PM
130static int igb_resume(struct pci_dev *);
131#endif
132static void igb_shutdown(struct pci_dev *);
fe4506b6
JC		 133#ifdef CONFIG_DCA
134static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
135static struct notifier_block dca_notifier = {
136 .notifier_call = igb_notify_dca,
137 .next = NULL,
138 .priority = 0
139};
140#endif
9d5c8243
AK		 141
142#ifdef CONFIG_NET_POLL_CONTROLLER
143/* for netdump / net console */
144static void igb_netpoll(struct net_device *);
145#endif
146
147static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
148 pci_channel_state_t);
149static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
150static void igb_io_resume(struct pci_dev *);
151
152static struct pci_error_handlers igb_err_handler = {
153 .error_detected = igb_io_error_detected,
154 .slot_reset = igb_io_slot_reset,
155 .resume = igb_io_resume,
156};
157
158
159static struct pci_driver igb_driver = {
160 .name = igb_driver_name,
161 .id_table = igb_pci_tbl,
162 .probe = igb_probe,
163 .remove = __devexit_p(igb_remove),
164#ifdef CONFIG_PM
165 /* Power Managment Hooks */
166 .suspend = igb_suspend,
167 .resume = igb_resume,
168#endif
169 .shutdown = igb_shutdown,
170 .err_handler = &igb_err_handler
171};
172
173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
204 ret = pci_register_driver(&igb_driver);
fe4506b6
JC		 205#ifdef CONFIG_DCA
206 dca_register_notify(&dca_notifier);
207#endif
9d5c8243
AK		 208 return ret;
209}
210
211module_init(igb_init_module);
212
213/**
214 * igb_exit_module - Driver Exit Cleanup Routine
215 *
216 * igb_exit_module is called just before the driver is removed
217 * from memory.
218 **/
219static void __exit igb_exit_module(void)
220{
fe4506b6
JC		 221#ifdef CONFIG_DCA
222 dca_unregister_notify(&dca_notifier);
223#endif
9d5c8243
AK		 224 pci_unregister_driver(&igb_driver);
225}
226
227module_exit(igb_exit_module);
228
229/**
230 * igb_alloc_queues - Allocate memory for all rings
231 * @adapter: board private structure to initialize
232 *
233 * We allocate one ring per queue at run-time since we don't know the
234 * number of queues at compile-time.
235 **/
236static int igb_alloc_queues(struct igb_adapter *adapter)
237{
238 int i;
239
240 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
241 sizeof(struct igb_ring), GFP_KERNEL);
242 if (!adapter->tx_ring)
243 return -ENOMEM;
244
245 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
246 sizeof(struct igb_ring), GFP_KERNEL);
247 if (!adapter->rx_ring) {
248 kfree(adapter->tx_ring);
249 return -ENOMEM;
250 }
251
661086df
PWJ		 252 for (i = 0; i < adapter->num_tx_queues; i++) {
253 struct igb_ring *ring = &(adapter->tx_ring[i]);
254 ring->adapter = adapter;
255 ring->queue_index = i;
256 }
9d5c8243
AK		 257 for (i = 0; i < adapter->num_rx_queues; i++) {
258 struct igb_ring *ring = &(adapter->rx_ring[i]);
259 ring->adapter = adapter;
844290e5 260 ring->queue_index = i;
9d5c8243
AK		 261 ring->itr_register = E1000_ITR;
262
844290e5 263 /* set a default napi handler for each rx_ring */
661086df 264 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 265 }
266 return 0;
267}
268
269#define IGB_N0_QUEUE -1
270static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
271 int tx_queue, int msix_vector)
272{
273 u32 msixbm = 0;
274 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 275 u32 ivar, index;
276
277 switch (hw->mac.type) {
278 case e1000_82575:
9d5c8243
AK		 279 /* The 82575 assigns vectors using a bitmask, which matches the
280 bitmask for the EICR/EIMS/EIMC registers. To assign one
281 or more queues to a vector, we write the appropriate bits
282 into the MSIXBM register for that vector. */
283 if (rx_queue > IGB_N0_QUEUE) {
284 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
285 adapter->rx_ring[rx_queue].eims_value = msixbm;
286 }
287 if (tx_queue > IGB_N0_QUEUE) {
288 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
289 adapter->tx_ring[tx_queue].eims_value =
290 E1000_EICR_TX_QUEUE0 << tx_queue;
291 }
292 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 293 break;
294 case e1000_82576:
295 /* Kawela uses a table-based method for assigning vectors.
296 Each queue has a single entry in the table to which we write
297 a vector number along with a "valid" bit. Sadly, the layout
298 of the table is somewhat counterintuitive. */
299 if (rx_queue > IGB_N0_QUEUE) {
300 index = (rx_queue & 0x7);
301 ivar = array_rd32(E1000_IVAR0, index);
302 if (rx_queue < 8) {
303 /* vector goes into low byte of register */
304 ivar = ivar & 0xFFFFFF00;
305 ivar |= msix_vector | E1000_IVAR_VALID;
306 } else {
307 /* vector goes into third byte of register */
308 ivar = ivar & 0xFF00FFFF;
309 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
310 }
311 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
312 array_wr32(E1000_IVAR0, index, ivar);
313 }
314 if (tx_queue > IGB_N0_QUEUE) {
315 index = (tx_queue & 0x7);
316 ivar = array_rd32(E1000_IVAR0, index);
317 if (tx_queue < 8) {
318 /* vector goes into second byte of register */
319 ivar = ivar & 0xFFFF00FF;
320 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
321 } else {
322 /* vector goes into high byte of register */
323 ivar = ivar & 0x00FFFFFF;
324 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
325 }
326 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
327 array_wr32(E1000_IVAR0, index, ivar);
328 }
329 break;
330 default:
331 BUG();
332 break;
333 }
9d5c8243
AK		 334}
335
336/**
337 * igb_configure_msix - Configure MSI-X hardware
338 *
339 * igb_configure_msix sets up the hardware to properly
340 * generate MSI-X interrupts.
341 **/
342static void igb_configure_msix(struct igb_adapter *adapter)
343{
344 u32 tmp;
345 int i, vector = 0;
346 struct e1000_hw *hw = &adapter->hw;
347
348 adapter->eims_enable_mask = 0;
2d064c06
AD		 349 if (hw->mac.type == e1000_82576)
350 /* Turn on MSI-X capability first, or our settings
351 * won't stick. And it will take days to debug. */
352 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
353 E1000_GPIE_PBA | E1000_GPIE_EIAME |
354 E1000_GPIE_NSICR);
9d5c8243
AK		 355
356 for (i = 0; i < adapter->num_tx_queues; i++) {
357 struct igb_ring *tx_ring = &adapter->tx_ring[i];
358 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
359 adapter->eims_enable_mask |= tx_ring->eims_value;
360 if (tx_ring->itr_val)
361 writel(1000000000 / (tx_ring->itr_val * 256),
362 hw->hw_addr + tx_ring->itr_register);
363 else
364 writel(1, hw->hw_addr + tx_ring->itr_register);
365 }
366
367 for (i = 0; i < adapter->num_rx_queues; i++) {
368 struct igb_ring *rx_ring = &adapter->rx_ring[i];
369 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
370 adapter->eims_enable_mask |= rx_ring->eims_value;
371 if (rx_ring->itr_val)
372 writel(1000000000 / (rx_ring->itr_val * 256),
373 hw->hw_addr + rx_ring->itr_register);
374 else
375 writel(1, hw->hw_addr + rx_ring->itr_register);
376 }
377
378
379 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 380 switch (hw->mac.type) {
381 case e1000_82575:
9d5c8243
AK		 382 array_wr32(E1000_MSIXBM(0), vector++,
383 E1000_EIMS_OTHER);
384
9d5c8243
AK		 385 tmp = rd32(E1000_CTRL_EXT);
386 /* enable MSI-X PBA support*/
387 tmp |= E1000_CTRL_EXT_PBA_CLR;
388
389 /* Auto-Mask interrupts upon ICR read. */
390 tmp |= E1000_CTRL_EXT_EIAME;
391 tmp |= E1000_CTRL_EXT_IRCA;
392
393 wr32(E1000_CTRL_EXT, tmp);
394 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 395 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 396
2d064c06
AD		 397 break;
398
399 case e1000_82576:
400 tmp = (vector++ | E1000_IVAR_VALID) << 8;
401 wr32(E1000_IVAR_MISC, tmp);
402
403 adapter->eims_enable_mask = (1 << (vector)) - 1;
404 adapter->eims_other = 1 << (vector - 1);
405 break;
406 default:
407 /* do nothing, since nothing else supports MSI-X */
408 break;
409 } /* switch (hw->mac.type) */
9d5c8243
AK		 410 wrfl();
411}
412
413/**
414 * igb_request_msix - Initialize MSI-X interrupts
415 *
416 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
417 * kernel.
418 **/
419static int igb_request_msix(struct igb_adapter *adapter)
420{
421 struct net_device *netdev = adapter->netdev;
422 int i, err = 0, vector = 0;
423
424 vector = 0;
425
426 for (i = 0; i < adapter->num_tx_queues; i++) {
427 struct igb_ring *ring = &(adapter->tx_ring[i]);
428 sprintf(ring->name, "%s-tx%d", netdev->name, i);
429 err = request_irq(adapter->msix_entries[vector].vector,
430 &igb_msix_tx, 0, ring->name,
431 &(adapter->tx_ring[i]));
432 if (err)
433 goto out;
434 ring->itr_register = E1000_EITR(0) + (vector << 2);
435 ring->itr_val = adapter->itr;
436 vector++;
437 }
438 for (i = 0; i < adapter->num_rx_queues; i++) {
439 struct igb_ring *ring = &(adapter->rx_ring[i]);
440 if (strlen(netdev->name) < (IFNAMSIZ - 5))
441 sprintf(ring->name, "%s-rx%d", netdev->name, i);
442 else
443 memcpy(ring->name, netdev->name, IFNAMSIZ);
444 err = request_irq(adapter->msix_entries[vector].vector,
445 &igb_msix_rx, 0, ring->name,
446 &(adapter->rx_ring[i]));
447 if (err)
448 goto out;
449 ring->itr_register = E1000_EITR(0) + (vector << 2);
450 ring->itr_val = adapter->itr;
844290e5
PW		 451 /* overwrite the poll routine for MSIX, we've already done
452 * netif_napi_add */
453 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 454 vector++;
455 }
456
457 err = request_irq(adapter->msix_entries[vector].vector,
458 &igb_msix_other, 0, netdev->name, netdev);
459 if (err)
460 goto out;
461
9d5c8243
AK		 462 igb_configure_msix(adapter);
463 return 0;
464out:
465 return err;
466}
467
468static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
469{
470 if (adapter->msix_entries) {
471 pci_disable_msix(adapter->pdev);
472 kfree(adapter->msix_entries);
473 adapter->msix_entries = NULL;
474 } else if (adapter->msi_enabled)
475 pci_disable_msi(adapter->pdev);
476 return;
477}
478
479
480/**
481 * igb_set_interrupt_capability - set MSI or MSI-X if supported
482 *
483 * Attempt to configure interrupts using the best available
484 * capabilities of the hardware and kernel.
485 **/
486static void igb_set_interrupt_capability(struct igb_adapter *adapter)
487{
488 int err;
489 int numvecs, i;
490
491 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
492 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
493 GFP_KERNEL);
494 if (!adapter->msix_entries)
495 goto msi_only;
496
497 for (i = 0; i < numvecs; i++)
498 adapter->msix_entries[i].entry = i;
499
500 err = pci_enable_msix(adapter->pdev,
501 adapter->msix_entries,
502 numvecs);
503 if (err == 0)
504 return;
505
506 igb_reset_interrupt_capability(adapter);
507
508 /* If we can't do MSI-X, try MSI */
509msi_only:
510 adapter->num_rx_queues = 1;
661086df 511 adapter->num_tx_queues = 1;
9d5c8243
AK		 512 if (!pci_enable_msi(adapter->pdev))
513 adapter->msi_enabled = 1;
661086df
PWJ		 514
515#ifdef CONFIG_NETDEVICES_MULTIQUEUE
516 /* Notify the stack of the (possibly) reduced Tx Queue count. */
517 adapter->netdev->egress_subqueue_count = adapter->num_tx_queues;
518#endif
9d5c8243
AK		 519 return;
520}
521
522/**
523 * igb_request_irq - initialize interrupts
524 *
525 * Attempts to configure interrupts using the best available
526 * capabilities of the hardware and kernel.
527 **/
528static int igb_request_irq(struct igb_adapter *adapter)
529{
530 struct net_device *netdev = adapter->netdev;
531 struct e1000_hw *hw = &adapter->hw;
532 int err = 0;
533
534 if (adapter->msix_entries) {
535 err = igb_request_msix(adapter);
844290e5 536 if (!err)
9d5c8243 537 goto request_done;
9d5c8243
AK		 538 /* fall back to MSI */
539 igb_reset_interrupt_capability(adapter);
540 if (!pci_enable_msi(adapter->pdev))
541 adapter->msi_enabled = 1;
542 igb_free_all_tx_resources(adapter);
543 igb_free_all_rx_resources(adapter);
544 adapter->num_rx_queues = 1;
545 igb_alloc_queues(adapter);
844290e5 546 } else {
2d064c06
AD		 547 switch (hw->mac.type) {
548 case e1000_82575:
549 wr32(E1000_MSIXBM(0),
550 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
551 break;
552 case e1000_82576:
553 wr32(E1000_IVAR0, E1000_IVAR_VALID);
554 break;
555 default:
556 break;
557 }
9d5c8243 558 }
844290e5 559
9d5c8243
AK		 560 if (adapter->msi_enabled) {
561 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
562 netdev->name, netdev);
563 if (!err)
564 goto request_done;
565 /* fall back to legacy interrupts */
566 igb_reset_interrupt_capability(adapter);
567 adapter->msi_enabled = 0;
568 }
569
570 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
571 netdev->name, netdev);
572
6cb5e577 573 if (err)
9d5c8243
AK		 574 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
575 err);
9d5c8243
AK		 576
577request_done:
578 return err;
579}
580
581static void igb_free_irq(struct igb_adapter *adapter)
582{
583 struct net_device *netdev = adapter->netdev;
584
585 if (adapter->msix_entries) {
586 int vector = 0, i;
587
588 for (i = 0; i < adapter->num_tx_queues; i++)
589 free_irq(adapter->msix_entries[vector++].vector,
590 &(adapter->tx_ring[i]));
591 for (i = 0; i < adapter->num_rx_queues; i++)
592 free_irq(adapter->msix_entries[vector++].vector,
593 &(adapter->rx_ring[i]));
594
595 free_irq(adapter->msix_entries[vector++].vector, netdev);
596 return;
597 }
598
599 free_irq(adapter->pdev->irq, netdev);
600}
601
602/**
603 * igb_irq_disable - Mask off interrupt generation on the NIC
604 * @adapter: board private structure
605 **/
606static void igb_irq_disable(struct igb_adapter *adapter)
607{
608 struct e1000_hw *hw = &adapter->hw;
609
610 if (adapter->msix_entries) {
844290e5 611 wr32(E1000_EIAM, 0);
9d5c8243
AK		 612 wr32(E1000_EIMC, ~0);
613 wr32(E1000_EIAC, 0);
614 }
844290e5
PW		 615
616 wr32(E1000_IAM, 0);
9d5c8243
AK		 617 wr32(E1000_IMC, ~0);
618 wrfl();
619 synchronize_irq(adapter->pdev->irq);
620}
621
622/**
623 * igb_irq_enable - Enable default interrupt generation settings
624 * @adapter: board private structure
625 **/
626static void igb_irq_enable(struct igb_adapter *adapter)
627{
628 struct e1000_hw *hw = &adapter->hw;
629
630 if (adapter->msix_entries) {
844290e5
PW		 631 wr32(E1000_EIAC, adapter->eims_enable_mask);
632 wr32(E1000_EIAM, adapter->eims_enable_mask);
633 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 634 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 635 } else {
636 wr32(E1000_IMS, IMS_ENABLE_MASK);
637 wr32(E1000_IAM, IMS_ENABLE_MASK);
638 }
9d5c8243
AK		 639}
640
641static void igb_update_mng_vlan(struct igb_adapter *adapter)
642{
643 struct net_device *netdev = adapter->netdev;
644 u16 vid = adapter->hw.mng_cookie.vlan_id;
645 u16 old_vid = adapter->mng_vlan_id;
646 if (adapter->vlgrp) {
647 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
648 if (adapter->hw.mng_cookie.status &
649 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
650 igb_vlan_rx_add_vid(netdev, vid);
651 adapter->mng_vlan_id = vid;
652 } else
653 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
654
655 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
656 (vid != old_vid) &&
657 !vlan_group_get_device(adapter->vlgrp, old_vid))
658 igb_vlan_rx_kill_vid(netdev, old_vid);
659 } else
660 adapter->mng_vlan_id = vid;
661 }
662}
663
664/**
665 * igb_release_hw_control - release control of the h/w to f/w
666 * @adapter: address of board private structure
667 *
668 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
669 * For ASF and Pass Through versions of f/w this means that the
670 * driver is no longer loaded.
671 *
672 **/
673static void igb_release_hw_control(struct igb_adapter *adapter)
674{
675 struct e1000_hw *hw = &adapter->hw;
676 u32 ctrl_ext;
677
678 /* Let firmware take over control of h/w */
679 ctrl_ext = rd32(E1000_CTRL_EXT);
680 wr32(E1000_CTRL_EXT,
681 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
682}
683
684
685/**
686 * igb_get_hw_control - get control of the h/w from f/w
687 * @adapter: address of board private structure
688 *
689 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
690 * For ASF and Pass Through versions of f/w this means that
691 * the driver is loaded.
692 *
693 **/
694static void igb_get_hw_control(struct igb_adapter *adapter)
695{
696 struct e1000_hw *hw = &adapter->hw;
697 u32 ctrl_ext;
698
699 /* Let firmware know the driver has taken over */
700 ctrl_ext = rd32(E1000_CTRL_EXT);
701 wr32(E1000_CTRL_EXT,
702 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
703}
704
705static void igb_init_manageability(struct igb_adapter *adapter)
706{
707 struct e1000_hw *hw = &adapter->hw;
708
709 if (adapter->en_mng_pt) {
710 u32 manc2h = rd32(E1000_MANC2H);
711 u32 manc = rd32(E1000_MANC);
712
9d5c8243
AK		 713 /* enable receiving management packets to the host */
714 /* this will probably generate destination unreachable messages
715 * from the host OS, but the packets will be handled on SMBUS */
716 manc |= E1000_MANC_EN_MNG2HOST;
717#define E1000_MNG2HOST_PORT_623 (1 << 5)
718#define E1000_MNG2HOST_PORT_664 (1 << 6)
719 manc2h |= E1000_MNG2HOST_PORT_623;
720 manc2h |= E1000_MNG2HOST_PORT_664;
721 wr32(E1000_MANC2H, manc2h);
722
723 wr32(E1000_MANC, manc);
724 }
725}
726
9d5c8243
AK		 727/**
728 * igb_configure - configure the hardware for RX and TX
729 * @adapter: private board structure
730 **/
731static void igb_configure(struct igb_adapter *adapter)
732{
733 struct net_device *netdev = adapter->netdev;
734 int i;
735
736 igb_get_hw_control(adapter);
737 igb_set_multi(netdev);
738
739 igb_restore_vlan(adapter);
740 igb_init_manageability(adapter);
741
742 igb_configure_tx(adapter);
743 igb_setup_rctl(adapter);
744 igb_configure_rx(adapter);
662d7205
AD		 745
746 igb_rx_fifo_flush_82575(&adapter->hw);
747
9d5c8243
AK		 748 /* call IGB_DESC_UNUSED which always leaves
749 * at least 1 descriptor unused to make sure
750 * next_to_use != next_to_clean */
751 for (i = 0; i < adapter->num_rx_queues; i++) {
752 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 753 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 754 }
755
756
757 adapter->tx_queue_len = netdev->tx_queue_len;
758}
759
760
761/**
762 * igb_up - Open the interface and prepare it to handle traffic
763 * @adapter: board private structure
764 **/
765
766int igb_up(struct igb_adapter *adapter)
767{
768 struct e1000_hw *hw = &adapter->hw;
769 int i;
770
771 /* hardware has been reset, we need to reload some things */
772 igb_configure(adapter);
773
774 clear_bit(__IGB_DOWN, &adapter->state);
775
844290e5
PW		 776 for (i = 0; i < adapter->num_rx_queues; i++)
777 napi_enable(&adapter->rx_ring[i].napi);
778 if (adapter->msix_entries)
9d5c8243 779 igb_configure_msix(adapter);
9d5c8243
AK		 780
781 /* Clear any pending interrupts. */
782 rd32(E1000_ICR);
783 igb_irq_enable(adapter);
784
785 /* Fire a link change interrupt to start the watchdog. */
786 wr32(E1000_ICS, E1000_ICS_LSC);
787 return 0;
788}
789
790void igb_down(struct igb_adapter *adapter)
791{
792 struct e1000_hw *hw = &adapter->hw;
793 struct net_device *netdev = adapter->netdev;
794 u32 tctl, rctl;
795 int i;
796
797 /* signal that we're down so the interrupt handler does not
798 * reschedule our watchdog timer */
799 set_bit(__IGB_DOWN, &adapter->state);
800
801 /* disable receives in the hardware */
802 rctl = rd32(E1000_RCTL);
803 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
804 /* flush and sleep below */
805
806 netif_stop_queue(netdev);
661086df
PWJ		 807#ifdef CONFIG_NETDEVICES_MULTIQUEUE
808 for (i = 0; i < adapter->num_tx_queues; i++)
809 netif_stop_subqueue(netdev, i);
810#endif
9d5c8243
AK		 811
812 /* disable transmits in the hardware */
813 tctl = rd32(E1000_TCTL);
814 tctl &= ~E1000_TCTL_EN;
815 wr32(E1000_TCTL, tctl);
816 /* flush both disables and wait for them to finish */
817 wrfl();
818 msleep(10);
819
844290e5
PW		 820 for (i = 0; i < adapter->num_rx_queues; i++)
821 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 822
9d5c8243
AK		 823 igb_irq_disable(adapter);
824
825 del_timer_sync(&adapter->watchdog_timer);
826 del_timer_sync(&adapter->phy_info_timer);
827
828 netdev->tx_queue_len = adapter->tx_queue_len;
829 netif_carrier_off(netdev);
830 adapter->link_speed = 0;
831 adapter->link_duplex = 0;
832
3023682e
JK		 833 if (!pci_channel_offline(adapter->pdev))
834 igb_reset(adapter);
9d5c8243
AK		 835 igb_clean_all_tx_rings(adapter);
836 igb_clean_all_rx_rings(adapter);
837}
838
839void igb_reinit_locked(struct igb_adapter *adapter)
840{
841 WARN_ON(in_interrupt());
842 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
843 msleep(1);
844 igb_down(adapter);
845 igb_up(adapter);
846 clear_bit(__IGB_RESETTING, &adapter->state);
847}
848
849void igb_reset(struct igb_adapter *adapter)
850{
851 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 852 struct e1000_mac_info *mac = &hw->mac;
853 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 854 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
855 u16 hwm;
856
857 /* Repartition Pba for greater than 9k mtu
858 * To take effect CTRL.RST is required.
859 */
2d064c06 860 if (mac->type != e1000_82576) {
9d5c8243 861 pba = E1000_PBA_34K;
2d064c06
AD		 862 }
863 else {
864 pba = E1000_PBA_64K;
865 }
9d5c8243 866
2d064c06
AD		 867 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
868 (mac->type < e1000_82576)) {
9d5c8243
AK		 869 /* adjust PBA for jumbo frames */
870 wr32(E1000_PBA, pba);
871
872 /* To maintain wire speed transmits, the Tx FIFO should be
873 * large enough to accommodate two full transmit packets,
874 * rounded up to the next 1KB and expressed in KB. Likewise,
875 * the Rx FIFO should be large enough to accommodate at least
876 * one full receive packet and is similarly rounded up and
877 * expressed in KB. */
878 pba = rd32(E1000_PBA);
879 /* upper 16 bits has Tx packet buffer allocation size in KB */
880 tx_space = pba >> 16;
881 /* lower 16 bits has Rx packet buffer allocation size in KB */
882 pba &= 0xffff;
883 /* the tx fifo also stores 16 bytes of information about the tx
884 * but don't include ethernet FCS because hardware appends it */
885 min_tx_space = (adapter->max_frame_size +
886 sizeof(struct e1000_tx_desc) -
887 ETH_FCS_LEN) * 2;
888 min_tx_space = ALIGN(min_tx_space, 1024);
889 min_tx_space >>= 10;
890 /* software strips receive CRC, so leave room for it */
891 min_rx_space = adapter->max_frame_size;
892 min_rx_space = ALIGN(min_rx_space, 1024);
893 min_rx_space >>= 10;
894
895 /* If current Tx allocation is less than the min Tx FIFO size,
896 * and the min Tx FIFO size is less than the current Rx FIFO
897 * allocation, take space away from current Rx allocation */
898 if (tx_space < min_tx_space &&
899 ((min_tx_space - tx_space) < pba)) {
900 pba = pba - (min_tx_space - tx_space);
901
902 /* if short on rx space, rx wins and must trump tx
903 * adjustment */
904 if (pba < min_rx_space)
905 pba = min_rx_space;
906 }
2d064c06 907 wr32(E1000_PBA, pba);
9d5c8243 908 }
9d5c8243
AK		 909
910 /* flow control settings */
911 /* The high water mark must be low enough to fit one full frame
912 * (or the size used for early receive) above it in the Rx FIFO.
913 * Set it to the lower of:
914 * - 90% of the Rx FIFO size, or
915 * - the full Rx FIFO size minus one full frame */
916 hwm = min(((pba << 10) * 9 / 10),
2d064c06 917 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 918
2d064c06
AD		 919 if (mac->type < e1000_82576) {
920 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
921 fc->low_water = fc->high_water - 8;
922 } else {
923 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
924 fc->low_water = fc->high_water - 16;
925 }
9d5c8243
AK		 926 fc->pause_time = 0xFFFF;
927 fc->send_xon = 1;
928 fc->type = fc->original_type;
929
930 /* Allow time for pending master requests to run */
931 adapter->hw.mac.ops.reset_hw(&adapter->hw);
932 wr32(E1000_WUC, 0);
933
934 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
935 dev_err(&adapter->pdev->dev, "Hardware Error\n");
936
937 igb_update_mng_vlan(adapter);
938
939 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
940 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
941
942 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 943 if (adapter->hw.phy.ops.get_phy_info)
944 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 945}
946
42bfd33a
TI		 947/**
948 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
949 * @pdev: PCI device information struct
950 *
951 * Returns true if an adapter needs ioport resources
952 **/
953static int igb_is_need_ioport(struct pci_dev *pdev)
954{
955 switch (pdev->device) {
956 /* Currently there are no adapters that need ioport resources */
957 default:
958 return false;
959 }
960}
961
9d5c8243
AK		 962/**
963 * igb_probe - Device Initialization Routine
964 * @pdev: PCI device information struct
965 * @ent: entry in igb_pci_tbl
966 *
967 * Returns 0 on success, negative on failure
968 *
969 * igb_probe initializes an adapter identified by a pci_dev structure.
970 * The OS initialization, configuring of the adapter private structure,
971 * and a hardware reset occur.
972 **/
973static int __devinit igb_probe(struct pci_dev *pdev,
974 const struct pci_device_id *ent)
975{
976 struct net_device *netdev;
977 struct igb_adapter *adapter;
978 struct e1000_hw *hw;
979 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
980 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 981 int i, err, pci_using_dac;
982 u16 eeprom_data = 0;
983 u16 eeprom_apme_mask = IGB_EEPROM_APME;
984 u32 part_num;
42bfd33a 985 int bars, need_ioport;
9d5c8243 986
42bfd33a
TI		 987 /* do not allocate ioport bars when not needed */
988 need_ioport = igb_is_need_ioport(pdev);
989 if (need_ioport) {
990 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
991 err = pci_enable_device(pdev);
992 } else {
993 bars = pci_select_bars(pdev, IORESOURCE_MEM);
994 err = pci_enable_device_mem(pdev);
995 }
9d5c8243
AK		 996 if (err)
997 return err;
998
999 pci_using_dac = 0;
1000 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1001 if (!err) {
1002 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1003 if (!err)
1004 pci_using_dac = 1;
1005 } else {
1006 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1007 if (err) {
1008 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1009 if (err) {
1010 dev_err(&pdev->dev, "No usable DMA "
1011 "configuration, aborting\n");
1012 goto err_dma;
1013 }
1014 }
1015 }
1016
42bfd33a 1017 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1018 if (err)
1019 goto err_pci_reg;
1020
1021 pci_set_master(pdev);
c682fc23 1022 pci_save_state(pdev);
9d5c8243
AK		 1023
1024 err = -ENOMEM;
661086df
PWJ		 1025#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1026 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
1027#else
9d5c8243 1028 netdev = alloc_etherdev(sizeof(struct igb_adapter));
661086df 1029#endif /* CONFIG_NETDEVICES_MULTIQUEUE */
9d5c8243
AK		 1030 if (!netdev)
1031 goto err_alloc_etherdev;
1032
1033 SET_NETDEV_DEV(netdev, &pdev->dev);
1034
1035 pci_set_drvdata(pdev, netdev);
1036 adapter = netdev_priv(netdev);
1037 adapter->netdev = netdev;
1038 adapter->pdev = pdev;
1039 hw = &adapter->hw;
1040 hw->back = adapter;
1041 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1042 adapter->bars = bars;
1043 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1044
1045 mmio_start = pci_resource_start(pdev, 0);
1046 mmio_len = pci_resource_len(pdev, 0);
1047
1048 err = -EIO;
1049 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1050 if (!adapter->hw.hw_addr)
1051 goto err_ioremap;
1052
1053 netdev->open = &igb_open;
1054 netdev->stop = &igb_close;
1055 netdev->get_stats = &igb_get_stats;
1056 netdev->set_multicast_list = &igb_set_multi;
1057 netdev->set_mac_address = &igb_set_mac;
1058 netdev->change_mtu = &igb_change_mtu;
1059 netdev->do_ioctl = &igb_ioctl;
1060 igb_set_ethtool_ops(netdev);
1061 netdev->tx_timeout = &igb_tx_timeout;
1062 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1063 netdev->vlan_rx_register = igb_vlan_rx_register;
1064 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
1065 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
1066#ifdef CONFIG_NET_POLL_CONTROLLER
1067 netdev->poll_controller = igb_netpoll;
1068#endif
1069 netdev->hard_start_xmit = &igb_xmit_frame_adv;
1070
1071 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1072
1073 netdev->mem_start = mmio_start;
1074 netdev->mem_end = mmio_start + mmio_len;
1075
9d5c8243
AK		 1076 /* PCI config space info */
1077 hw->vendor_id = pdev->vendor;
1078 hw->device_id = pdev->device;
1079 hw->revision_id = pdev->revision;
1080 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1081 hw->subsystem_device_id = pdev->subsystem_device;
1082
1083 /* setup the private structure */
1084 hw->back = adapter;
1085 /* Copy the default MAC, PHY and NVM function pointers */
1086 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1087 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1088 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1089 /* Initialize skew-specific constants */
1090 err = ei->get_invariants(hw);
1091 if (err)
1092 goto err_hw_init;
1093
1094 err = igb_sw_init(adapter);
1095 if (err)
1096 goto err_sw_init;
1097
1098 igb_get_bus_info_pcie(hw);
1099
1100 hw->phy.autoneg_wait_to_complete = false;
1101 hw->mac.adaptive_ifs = true;
1102
1103 /* Copper options */
1104 if (hw->phy.media_type == e1000_media_type_copper) {
1105 hw->phy.mdix = AUTO_ALL_MODES;
1106 hw->phy.disable_polarity_correction = false;
1107 hw->phy.ms_type = e1000_ms_hw_default;
1108 }
1109
1110 if (igb_check_reset_block(hw))
1111 dev_info(&pdev->dev,
1112 "PHY reset is blocked due to SOL/IDER session.\n");
1113
1114 netdev->features = NETIF_F_SG |
1115 NETIF_F_HW_CSUM |
1116 NETIF_F_HW_VLAN_TX |
1117 NETIF_F_HW_VLAN_RX |
1118 NETIF_F_HW_VLAN_FILTER;
1119
1120 netdev->features |= NETIF_F_TSO;
9d5c8243 1121 netdev->features |= NETIF_F_TSO6;
48f29ffc
JK		 1122
1123 netdev->vlan_features |= NETIF_F_TSO;
1124 netdev->vlan_features |= NETIF_F_TSO6;
1125 netdev->vlan_features |= NETIF_F_HW_CSUM;
1126 netdev->vlan_features |= NETIF_F_SG;
1127
9d5c8243
AK		 1128 if (pci_using_dac)
1129 netdev->features |= NETIF_F_HIGHDMA;
1130
661086df
PWJ		 1131#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1132 netdev->features |= NETIF_F_MULTI_QUEUE;
1133#endif
1134
9d5c8243
AK		 1135 netdev->features |= NETIF_F_LLTX;
1136 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1137
1138 /* before reading the NVM, reset the controller to put the device in a
1139 * known good starting state */
1140 hw->mac.ops.reset_hw(hw);
1141
1142 /* make sure the NVM is good */
1143 if (igb_validate_nvm_checksum(hw) < 0) {
1144 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1145 err = -EIO;
1146 goto err_eeprom;
1147 }
1148
1149 /* copy the MAC address out of the NVM */
1150 if (hw->mac.ops.read_mac_addr(hw))
1151 dev_err(&pdev->dev, "NVM Read Error\n");
1152
1153 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1154 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1155
1156 if (!is_valid_ether_addr(netdev->perm_addr)) {
1157 dev_err(&pdev->dev, "Invalid MAC Address\n");
1158 err = -EIO;
1159 goto err_eeprom;
1160 }
1161
1162 init_timer(&adapter->watchdog_timer);
1163 adapter->watchdog_timer.function = &igb_watchdog;
1164 adapter->watchdog_timer.data = (unsigned long) adapter;
1165
1166 init_timer(&adapter->phy_info_timer);
1167 adapter->phy_info_timer.function = &igb_update_phy_info;
1168 adapter->phy_info_timer.data = (unsigned long) adapter;
1169
1170 INIT_WORK(&adapter->reset_task, igb_reset_task);
1171 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1172
1173 /* Initialize link & ring properties that are user-changeable */
1174 adapter->tx_ring->count = 256;
1175 for (i = 0; i < adapter->num_tx_queues; i++)
1176 adapter->tx_ring[i].count = adapter->tx_ring->count;
1177 adapter->rx_ring->count = 256;
1178 for (i = 0; i < adapter->num_rx_queues; i++)
1179 adapter->rx_ring[i].count = adapter->rx_ring->count;
1180
1181 adapter->fc_autoneg = true;
1182 hw->mac.autoneg = true;
1183 hw->phy.autoneg_advertised = 0x2f;
1184
1185 hw->fc.original_type = e1000_fc_default;
1186 hw->fc.type = e1000_fc_default;
1187
1188 adapter->itr_setting = 3;
1189 adapter->itr = IGB_START_ITR;
1190
1191 igb_validate_mdi_setting(hw);
1192
1193 adapter->rx_csum = 1;
1194
1195 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1196 * enable the ACPI Magic Packet filter
1197 */
1198
1199 if (hw->bus.func == 0 ||
1200 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1201 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1202 &eeprom_data);
1203
1204 if (eeprom_data & eeprom_apme_mask)
1205 adapter->eeprom_wol |= E1000_WUFC_MAG;
1206
1207 /* now that we have the eeprom settings, apply the special cases where
1208 * the eeprom may be wrong or the board simply won't support wake on
1209 * lan on a particular port */
1210 switch (pdev->device) {
1211 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2d064c06 1212 case E1000_DEV_ID_82576_QUAD_COPPER:
9d5c8243
AK		 1213 adapter->eeprom_wol = 0;
1214 break;
1215 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1216 case E1000_DEV_ID_82576_FIBER:
1217 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1218 /* Wake events only supported on port A for dual fiber
1219 * regardless of eeprom setting */
1220 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1221 adapter->eeprom_wol = 0;
1222 break;
1223 }
1224
1225 /* initialize the wol settings based on the eeprom settings */
1226 adapter->wol = adapter->eeprom_wol;
1227
1228 /* reset the hardware with the new settings */
1229 igb_reset(adapter);
1230
1231 /* let the f/w know that the h/w is now under the control of the
1232 * driver. */
1233 igb_get_hw_control(adapter);
1234
1235 /* tell the stack to leave us alone until igb_open() is called */
1236 netif_carrier_off(netdev);
1237 netif_stop_queue(netdev);
661086df
PWJ		 1238#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1239 for (i = 0; i < adapter->num_tx_queues; i++)
1240 netif_stop_subqueue(netdev, i);
1241#endif
9d5c8243
AK		 1242
1243 strcpy(netdev->name, "eth%d");
1244 err = register_netdev(netdev);
1245 if (err)
1246 goto err_register;
1247
fe4506b6
JC		 1248#ifdef CONFIG_DCA
1249 if (dca_add_requester(&pdev->dev) == 0) {
1250 adapter->dca_enabled = true;
1251 dev_info(&pdev->dev, "DCA enabled\n");
1252 /* Always use CB2 mode, difference is masked
1253 * in the CB driver. */
1254 wr32(E1000_DCA_CTRL, 2);
1255 igb_setup_dca(adapter);
1256 }
1257#endif
1258
9d5c8243
AK		 1259 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1260 /* print bus type/speed/width info */
1261 dev_info(&pdev->dev,
1262 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1263 netdev->name,
1264 ((hw->bus.speed == e1000_bus_speed_2500)
1265 ? "2.5Gb/s" : "unknown"),
1266 ((hw->bus.width == e1000_bus_width_pcie_x4)
1267 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1268 ? "Width x1" : "unknown"),
1269 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1270 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1271
1272 igb_read_part_num(hw, &part_num);
1273 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1274 (part_num >> 8), (part_num & 0xff));
1275
1276 dev_info(&pdev->dev,
1277 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1278 adapter->msix_entries ? "MSI-X" :
1279 adapter->msi_enabled ? "MSI" : "legacy",
1280 adapter->num_rx_queues, adapter->num_tx_queues);
1281
9d5c8243
AK		 1282 return 0;
1283
1284err_register:
1285 igb_release_hw_control(adapter);
1286err_eeprom:
1287 if (!igb_check_reset_block(hw))
1288 hw->phy.ops.reset_phy(hw);
1289
1290 if (hw->flash_address)
1291 iounmap(hw->flash_address);
1292
1293 igb_remove_device(hw);
1294 kfree(adapter->tx_ring);
1295 kfree(adapter->rx_ring);
1296err_sw_init:
1297err_hw_init:
1298 iounmap(hw->hw_addr);
1299err_ioremap:
1300 free_netdev(netdev);
1301err_alloc_etherdev:
42bfd33a 1302 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1303err_pci_reg:
1304err_dma:
1305 pci_disable_device(pdev);
1306 return err;
1307}
1308
1309/**
1310 * igb_remove - Device Removal Routine
1311 * @pdev: PCI device information struct
1312 *
1313 * igb_remove is called by the PCI subsystem to alert the driver
1314 * that it should release a PCI device. The could be caused by a
1315 * Hot-Plug event, or because the driver is going to be removed from
1316 * memory.
1317 **/
1318static void __devexit igb_remove(struct pci_dev *pdev)
1319{
1320 struct net_device *netdev = pci_get_drvdata(pdev);
1321 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1322 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1323
1324 /* flush_scheduled work may reschedule our watchdog task, so
1325 * explicitly disable watchdog tasks from being rescheduled */
1326 set_bit(__IGB_DOWN, &adapter->state);
1327 del_timer_sync(&adapter->watchdog_timer);
1328 del_timer_sync(&adapter->phy_info_timer);
1329
1330 flush_scheduled_work();
1331
fe4506b6
JC		 1332#ifdef CONFIG_DCA
1333 if (adapter->dca_enabled) {
1334 dev_info(&pdev->dev, "DCA disabled\n");
1335 dca_remove_requester(&pdev->dev);
1336 adapter->dca_enabled = false;
1337 wr32(E1000_DCA_CTRL, 1);
1338 }
1339#endif
1340
9d5c8243
AK		 1341 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1342 * would have already happened in close and is redundant. */
1343 igb_release_hw_control(adapter);
1344
1345 unregister_netdev(netdev);
1346
1347 if (!igb_check_reset_block(&adapter->hw))
1348 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1349
1350 igb_remove_device(&adapter->hw);
1351 igb_reset_interrupt_capability(adapter);
1352
1353 kfree(adapter->tx_ring);
1354 kfree(adapter->rx_ring);
1355
1356 iounmap(adapter->hw.hw_addr);
1357 if (adapter->hw.flash_address)
1358 iounmap(adapter->hw.flash_address);
42bfd33a 1359 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1360
1361 free_netdev(netdev);
1362
1363 pci_disable_device(pdev);
1364}
1365
1366/**
1367 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1368 * @adapter: board private structure to initialize
1369 *
1370 * igb_sw_init initializes the Adapter private data structure.
1371 * Fields are initialized based on PCI device information and
1372 * OS network device settings (MTU size).
1373 **/
1374static int __devinit igb_sw_init(struct igb_adapter *adapter)
1375{
1376 struct e1000_hw *hw = &adapter->hw;
1377 struct net_device *netdev = adapter->netdev;
1378 struct pci_dev *pdev = adapter->pdev;
1379
1380 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1381
1382 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1383 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1384 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1385 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1386
1387 /* Number of supported queues. */
1388 /* Having more queues than CPUs doesn't make sense. */
661086df
PWJ		 1389 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
1390#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1391 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
1392#else
9d5c8243 1393 adapter->num_tx_queues = 1;
661086df 1394#endif /* CONFIG_NET_MULTI_QUEUE_DEVICE */
9d5c8243 1395
661086df
PWJ		 1396 /* This call may decrease the number of queues depending on
1397 * interrupt mode. */
9d5c8243
AK		 1398 igb_set_interrupt_capability(adapter);
1399
1400 if (igb_alloc_queues(adapter)) {
1401 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1402 return -ENOMEM;
1403 }
1404
1405 /* Explicitly disable IRQ since the NIC can be in any state. */
1406 igb_irq_disable(adapter);
1407
1408 set_bit(__IGB_DOWN, &adapter->state);
1409 return 0;
1410}
1411
1412/**
1413 * igb_open - Called when a network interface is made active
1414 * @netdev: network interface device structure
1415 *
1416 * Returns 0 on success, negative value on failure
1417 *
1418 * The open entry point is called when a network interface is made
1419 * active by the system (IFF_UP). At this point all resources needed
1420 * for transmit and receive operations are allocated, the interrupt
1421 * handler is registered with the OS, the watchdog timer is started,
1422 * and the stack is notified that the interface is ready.
1423 **/
1424static int igb_open(struct net_device *netdev)
1425{
1426 struct igb_adapter *adapter = netdev_priv(netdev);
1427 struct e1000_hw *hw = &adapter->hw;
1428 int err;
1429 int i;
1430
1431 /* disallow open during test */
1432 if (test_bit(__IGB_TESTING, &adapter->state))
1433 return -EBUSY;
1434
1435 /* allocate transmit descriptors */
1436 err = igb_setup_all_tx_resources(adapter);
1437 if (err)
1438 goto err_setup_tx;
1439
1440 /* allocate receive descriptors */
1441 err = igb_setup_all_rx_resources(adapter);
1442 if (err)
1443 goto err_setup_rx;
1444
1445 /* e1000_power_up_phy(adapter); */
1446
1447 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1448 if ((adapter->hw.mng_cookie.status &
1449 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1450 igb_update_mng_vlan(adapter);
1451
1452 /* before we allocate an interrupt, we must be ready to handle it.
1453 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1454 * as soon as we call pci_request_irq, so we have to setup our
1455 * clean_rx handler before we do so. */
1456 igb_configure(adapter);
1457
1458 err = igb_request_irq(adapter);
1459 if (err)
1460 goto err_req_irq;
1461
1462 /* From here on the code is the same as igb_up() */
1463 clear_bit(__IGB_DOWN, &adapter->state);
1464
844290e5
PW		 1465 for (i = 0; i < adapter->num_rx_queues; i++)
1466 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1467
1468 /* Clear any pending interrupts. */
1469 rd32(E1000_ICR);
844290e5
PW		 1470
1471 igb_irq_enable(adapter);
1472
9d5c8243
AK		 1473 /* Fire a link status change interrupt to start the watchdog. */
1474 wr32(E1000_ICS, E1000_ICS_LSC);
1475
1476 return 0;
1477
1478err_req_irq:
1479 igb_release_hw_control(adapter);
1480 /* e1000_power_down_phy(adapter); */
1481 igb_free_all_rx_resources(adapter);
1482err_setup_rx:
1483 igb_free_all_tx_resources(adapter);
1484err_setup_tx:
1485 igb_reset(adapter);
1486
1487 return err;
1488}
1489
1490/**
1491 * igb_close - Disables a network interface
1492 * @netdev: network interface device structure
1493 *
1494 * Returns 0, this is not allowed to fail
1495 *
1496 * The close entry point is called when an interface is de-activated
1497 * by the OS. The hardware is still under the driver's control, but
1498 * needs to be disabled. A global MAC reset is issued to stop the
1499 * hardware, and all transmit and receive resources are freed.
1500 **/
1501static int igb_close(struct net_device *netdev)
1502{
1503 struct igb_adapter *adapter = netdev_priv(netdev);
1504
1505 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1506 igb_down(adapter);
1507
1508 igb_free_irq(adapter);
1509
1510 igb_free_all_tx_resources(adapter);
1511 igb_free_all_rx_resources(adapter);
1512
1513 /* kill manageability vlan ID if supported, but not if a vlan with
1514 * the same ID is registered on the host OS (let 8021q kill it) */
1515 if ((adapter->hw.mng_cookie.status &
1516 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1517 !(adapter->vlgrp &&
1518 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1519 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1520
1521 return 0;
1522}
1523
1524/**
1525 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1526 * @adapter: board private structure
1527 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1528 *
1529 * Return 0 on success, negative on failure
1530 **/
1531
1532int igb_setup_tx_resources(struct igb_adapter *adapter,
1533 struct igb_ring *tx_ring)
1534{
1535 struct pci_dev *pdev = adapter->pdev;
1536 int size;
1537
1538 size = sizeof(struct igb_buffer) * tx_ring->count;
1539 tx_ring->buffer_info = vmalloc(size);
1540 if (!tx_ring->buffer_info)
1541 goto err;
1542 memset(tx_ring->buffer_info, 0, size);
1543
1544 /* round up to nearest 4K */
1545 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1546 + sizeof(u32);
1547 tx_ring->size = ALIGN(tx_ring->size, 4096);
1548
1549 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1550 &tx_ring->dma);
1551
1552 if (!tx_ring->desc)
1553 goto err;
1554
1555 tx_ring->adapter = adapter;
1556 tx_ring->next_to_use = 0;
1557 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1558 return 0;
1559
1560err:
1561 vfree(tx_ring->buffer_info);
1562 dev_err(&adapter->pdev->dev,
1563 "Unable to allocate memory for the transmit descriptor ring\n");
1564 return -ENOMEM;
1565}
1566
1567/**
1568 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1569 * (Descriptors) for all queues
1570 * @adapter: board private structure
1571 *
1572 * Return 0 on success, negative on failure
1573 **/
1574static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1575{
1576 int i, err = 0;
661086df
PWJ		 1577#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1578 int r_idx;
1579#endif
9d5c8243
AK		 1580
1581 for (i = 0; i < adapter->num_tx_queues; i++) {
1582 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1583 if (err) {
1584 dev_err(&adapter->pdev->dev,
1585 "Allocation for Tx Queue %u failed\n", i);
1586 for (i--; i >= 0; i--)
3b644cf6 1587 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1588 break;
1589 }
1590 }
1591
661086df
PWJ		 1592#ifdef CONFIG_NETDEVICES_MULTIQUEUE
1593 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1594 r_idx = i % adapter->num_tx_queues;
1595 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1596 }
1597#endif
9d5c8243
AK		 1598 return err;
1599}
1600
1601/**
1602 * igb_configure_tx - Configure transmit Unit after Reset
1603 * @adapter: board private structure
1604 *
1605 * Configure the Tx unit of the MAC after a reset.
1606 **/
1607static void igb_configure_tx(struct igb_adapter *adapter)
1608{
1609 u64 tdba, tdwba;
1610 struct e1000_hw *hw = &adapter->hw;
1611 u32 tctl;
1612 u32 txdctl, txctrl;
1613 int i;
1614
1615 for (i = 0; i < adapter->num_tx_queues; i++) {
1616 struct igb_ring *ring = &(adapter->tx_ring[i]);
1617
1618 wr32(E1000_TDLEN(i),
1619 ring->count * sizeof(struct e1000_tx_desc));
1620 tdba = ring->dma;
1621 wr32(E1000_TDBAL(i),
1622 tdba & 0x00000000ffffffffULL);
1623 wr32(E1000_TDBAH(i), tdba >> 32);
1624
1625 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1626 tdwba |= 1; /* enable head wb */
1627 wr32(E1000_TDWBAL(i),
1628 tdwba & 0x00000000ffffffffULL);
1629 wr32(E1000_TDWBAH(i), tdwba >> 32);
1630
1631 ring->head = E1000_TDH(i);
1632 ring->tail = E1000_TDT(i);
1633 writel(0, hw->hw_addr + ring->tail);
1634 writel(0, hw->hw_addr + ring->head);
1635 txdctl = rd32(E1000_TXDCTL(i));
1636 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1637 wr32(E1000_TXDCTL(i), txdctl);
1638
1639 /* Turn off Relaxed Ordering on head write-backs. The
1640 * writebacks MUST be delivered in order or it will
1641 * completely screw up our bookeeping.
1642 */
1643 txctrl = rd32(E1000_DCA_TXCTRL(i));
1644 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1645 wr32(E1000_DCA_TXCTRL(i), txctrl);
1646 }
1647
1648
1649
1650 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1651
1652 /* Program the Transmit Control Register */
1653
1654 tctl = rd32(E1000_TCTL);
1655 tctl &= ~E1000_TCTL_CT;
1656 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1657 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1658
1659 igb_config_collision_dist(hw);
1660
1661 /* Setup Transmit Descriptor Settings for eop descriptor */
1662 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1663
1664 /* Enable transmits */
1665 tctl |= E1000_TCTL_EN;
1666
1667 wr32(E1000_TCTL, tctl);
1668}
1669
1670/**
1671 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1672 * @adapter: board private structure
1673 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1674 *
1675 * Returns 0 on success, negative on failure
1676 **/
1677
1678int igb_setup_rx_resources(struct igb_adapter *adapter,
1679 struct igb_ring *rx_ring)
1680{
1681 struct pci_dev *pdev = adapter->pdev;
1682 int size, desc_len;
1683
1684 size = sizeof(struct igb_buffer) * rx_ring->count;
1685 rx_ring->buffer_info = vmalloc(size);
1686 if (!rx_ring->buffer_info)
1687 goto err;
1688 memset(rx_ring->buffer_info, 0, size);
1689
1690 desc_len = sizeof(union e1000_adv_rx_desc);
1691
1692 /* Round up to nearest 4K */
1693 rx_ring->size = rx_ring->count * desc_len;
1694 rx_ring->size = ALIGN(rx_ring->size, 4096);
1695
1696 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1697 &rx_ring->dma);
1698
1699 if (!rx_ring->desc)
1700 goto err;
1701
1702 rx_ring->next_to_clean = 0;
1703 rx_ring->next_to_use = 0;
1704 rx_ring->pending_skb = NULL;
1705
1706 rx_ring->adapter = adapter;
9d5c8243
AK		 1707
1708 return 0;
1709
1710err:
1711 vfree(rx_ring->buffer_info);
1712 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1713 "the receive descriptor ring\n");
1714 return -ENOMEM;
1715}
1716
1717/**
1718 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1719 * (Descriptors) for all queues
1720 * @adapter: board private structure
1721 *
1722 * Return 0 on success, negative on failure
1723 **/
1724static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1725{
1726 int i, err = 0;
1727
1728 for (i = 0; i < adapter->num_rx_queues; i++) {
1729 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1730 if (err) {
1731 dev_err(&adapter->pdev->dev,
1732 "Allocation for Rx Queue %u failed\n", i);
1733 for (i--; i >= 0; i--)
3b644cf6 1734 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1735 break;
1736 }
1737 }
1738
1739 return err;
1740}
1741
1742/**
1743 * igb_setup_rctl - configure the receive control registers
1744 * @adapter: Board private structure
1745 **/
1746static void igb_setup_rctl(struct igb_adapter *adapter)
1747{
1748 struct e1000_hw *hw = &adapter->hw;
1749 u32 rctl;
1750 u32 srrctl = 0;
1751 int i;
1752
1753 rctl = rd32(E1000_RCTL);
1754
1755 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1756
1757 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1758 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1759 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1760
87cb7e8c
AK		 1761 /*
1762 * enable stripping of CRC. It's unlikely this will break BMC
1763 * redirection as it did with e1000. Newer features require
1764 * that the HW strips the CRC.
9d5c8243 1765 */
87cb7e8c 1766 rctl |= E1000_RCTL_SECRC;
9d5c8243
AK		 1767
1768 rctl &= ~E1000_RCTL_SBP;
1769
1770 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1771 rctl &= ~E1000_RCTL_LPE;
1772 else
1773 rctl |= E1000_RCTL_LPE;
1774 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1775 /* Setup buffer sizes */
1776 rctl &= ~E1000_RCTL_SZ_4096;
1777 rctl |= E1000_RCTL_BSEX;
1778 switch (adapter->rx_buffer_len) {
1779 case IGB_RXBUFFER_256:
1780 rctl |= E1000_RCTL_SZ_256;
1781 rctl &= ~E1000_RCTL_BSEX;
1782 break;
1783 case IGB_RXBUFFER_512:
1784 rctl |= E1000_RCTL_SZ_512;
1785 rctl &= ~E1000_RCTL_BSEX;
1786 break;
1787 case IGB_RXBUFFER_1024:
1788 rctl |= E1000_RCTL_SZ_1024;
1789 rctl &= ~E1000_RCTL_BSEX;
1790 break;
1791 case IGB_RXBUFFER_2048:
1792 default:
1793 rctl |= E1000_RCTL_SZ_2048;
1794 rctl &= ~E1000_RCTL_BSEX;
1795 break;
1796 case IGB_RXBUFFER_4096:
1797 rctl |= E1000_RCTL_SZ_4096;
1798 break;
1799 case IGB_RXBUFFER_8192:
1800 rctl |= E1000_RCTL_SZ_8192;
1801 break;
1802 case IGB_RXBUFFER_16384:
1803 rctl |= E1000_RCTL_SZ_16384;
1804 break;
1805 }
1806 } else {
1807 rctl &= ~E1000_RCTL_BSEX;
1808 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1809 }
1810
1811 /* 82575 and greater support packet-split where the protocol
1812 * header is placed in skb->data and the packet data is
1813 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1814 * In the case of a non-split, skb->data is linearly filled,
1815 * followed by the page buffers. Therefore, skb->data is
1816 * sized to hold the largest protocol header.
1817 */
1818 /* allocations using alloc_page take too long for regular MTU
1819 * so only enable packet split for jumbo frames */
1820 if (rctl & E1000_RCTL_LPE) {
1821 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1822 srrctl = adapter->rx_ps_hdr_size <<
1823 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1824 /* buffer size is ALWAYS one page */
1825 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1826 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1827 } else {
1828 adapter->rx_ps_hdr_size = 0;
1829 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1830 }
1831
1832 for (i = 0; i < adapter->num_rx_queues; i++)
1833 wr32(E1000_SRRCTL(i), srrctl);
1834
1835 wr32(E1000_RCTL, rctl);
1836}
1837
1838/**
1839 * igb_configure_rx - Configure receive Unit after Reset
1840 * @adapter: board private structure
1841 *
1842 * Configure the Rx unit of the MAC after a reset.
1843 **/
1844static void igb_configure_rx(struct igb_adapter *adapter)
1845{
1846 u64 rdba;
1847 struct e1000_hw *hw = &adapter->hw;
1848 u32 rctl, rxcsum;
1849 u32 rxdctl;
1850 int i;
1851
1852 /* disable receives while setting up the descriptors */
1853 rctl = rd32(E1000_RCTL);
1854 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1855 wrfl();
1856 mdelay(10);
1857
1858 if (adapter->itr_setting > 3)
1859 wr32(E1000_ITR,
1860 1000000000 / (adapter->itr * 256));
1861
1862 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1863 * the Base and Length of the Rx Descriptor Ring */
1864 for (i = 0; i < adapter->num_rx_queues; i++) {
1865 struct igb_ring *ring = &(adapter->rx_ring[i]);
1866 rdba = ring->dma;
1867 wr32(E1000_RDBAL(i),
1868 rdba & 0x00000000ffffffffULL);
1869 wr32(E1000_RDBAH(i), rdba >> 32);
1870 wr32(E1000_RDLEN(i),
1871 ring->count * sizeof(union e1000_adv_rx_desc));
1872
1873 ring->head = E1000_RDH(i);
1874 ring->tail = E1000_RDT(i);
1875 writel(0, hw->hw_addr + ring->tail);
1876 writel(0, hw->hw_addr + ring->head);
1877
1878 rxdctl = rd32(E1000_RXDCTL(i));
1879 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1880 rxdctl &= 0xFFF00000;
1881 rxdctl |= IGB_RX_PTHRESH;
1882 rxdctl |= IGB_RX_HTHRESH << 8;
1883 rxdctl |= IGB_RX_WTHRESH << 16;
1884 wr32(E1000_RXDCTL(i), rxdctl);
1885 }
1886
1887 if (adapter->num_rx_queues > 1) {
1888 u32 random[10];
1889 u32 mrqc;
1890 u32 j, shift;
1891 union e1000_reta {
1892 u32 dword;
1893 u8 bytes[4];
1894 } reta;
1895
1896 get_random_bytes(&random[0], 40);
1897
2d064c06
AD		 1898 if (hw->mac.type >= e1000_82576)
1899 shift = 0;
1900 else
1901 shift = 6;
9d5c8243
AK		 1902 for (j = 0; j < (32 * 4); j++) {
1903 reta.bytes[j & 3] =
1904 (j % adapter->num_rx_queues) << shift;
1905 if ((j & 3) == 3)
1906 writel(reta.dword,
1907 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1908 }
1909 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1910
1911 /* Fill out hash function seeds */
1912 for (j = 0; j < 10; j++)
1913 array_wr32(E1000_RSSRK(0), j, random[j]);
1914
1915 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1916 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1917 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1918 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1919 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1920 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1921 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1922 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1923
1924
1925 wr32(E1000_MRQC, mrqc);
1926
1927 /* Multiqueue and raw packet checksumming are mutually
1928 * exclusive. Note that this not the same as TCP/IP
1929 * checksumming, which works fine. */
1930 rxcsum = rd32(E1000_RXCSUM);
1931 rxcsum |= E1000_RXCSUM_PCSD;
1932 wr32(E1000_RXCSUM, rxcsum);
1933 } else {
1934 /* Enable Receive Checksum Offload for TCP and UDP */
1935 rxcsum = rd32(E1000_RXCSUM);
1936 if (adapter->rx_csum) {
1937 rxcsum |= E1000_RXCSUM_TUOFL;
1938
1939 /* Enable IPv4 payload checksum for UDP fragments
1940 * Must be used in conjunction with packet-split. */
1941 if (adapter->rx_ps_hdr_size)
1942 rxcsum |= E1000_RXCSUM_IPPCSE;
1943 } else {
1944 rxcsum &= ~E1000_RXCSUM_TUOFL;
1945 /* don't need to clear IPPCSE as it defaults to 0 */
1946 }
1947 wr32(E1000_RXCSUM, rxcsum);
1948 }
1949
1950 if (adapter->vlgrp)
1951 wr32(E1000_RLPML,
1952 adapter->max_frame_size + VLAN_TAG_SIZE);
1953 else
1954 wr32(E1000_RLPML, adapter->max_frame_size);
1955
1956 /* Enable Receives */
1957 wr32(E1000_RCTL, rctl);
1958}
1959
1960/**
1961 * igb_free_tx_resources - Free Tx Resources per Queue
1962 * @adapter: board private structure
1963 * @tx_ring: Tx descriptor ring for a specific queue
1964 *
1965 * Free all transmit software resources
1966 **/
3b644cf6 1967static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1968{
3b644cf6 1969 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1970
3b644cf6 1971 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1972
1973 vfree(tx_ring->buffer_info);
1974 tx_ring->buffer_info = NULL;
1975
1976 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1977
1978 tx_ring->desc = NULL;
1979}
1980
1981/**
1982 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1983 * @adapter: board private structure
1984 *
1985 * Free all transmit software resources
1986 **/
1987static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1988{
1989 int i;
1990
1991 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1992 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1993}
1994
1995static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1996 struct igb_buffer *buffer_info)
1997{
1998 if (buffer_info->dma) {
1999 pci_unmap_page(adapter->pdev,
2000 buffer_info->dma,
2001 buffer_info->length,
2002 PCI_DMA_TODEVICE);
2003 buffer_info->dma = 0;
2004 }
2005 if (buffer_info->skb) {
2006 dev_kfree_skb_any(buffer_info->skb);
2007 buffer_info->skb = NULL;
2008 }
2009 buffer_info->time_stamp = 0;
2010 /* buffer_info must be completely set up in the transmit path */
2011}
2012
2013/**
2014 * igb_clean_tx_ring - Free Tx Buffers
2015 * @adapter: board private structure
2016 * @tx_ring: ring to be cleaned
2017 **/
3b644cf6 2018static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2019{
3b644cf6 2020 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2021 struct igb_buffer *buffer_info;
2022 unsigned long size;
2023 unsigned int i;
2024
2025 if (!tx_ring->buffer_info)
2026 return;
2027 /* Free all the Tx ring sk_buffs */
2028
2029 for (i = 0; i < tx_ring->count; i++) {
2030 buffer_info = &tx_ring->buffer_info[i];
2031 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2032 }
2033
2034 size = sizeof(struct igb_buffer) * tx_ring->count;
2035 memset(tx_ring->buffer_info, 0, size);
2036
2037 /* Zero out the descriptor ring */
2038
2039 memset(tx_ring->desc, 0, tx_ring->size);
2040
2041 tx_ring->next_to_use = 0;
2042 tx_ring->next_to_clean = 0;
2043
2044 writel(0, adapter->hw.hw_addr + tx_ring->head);
2045 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2046}
2047
2048/**
2049 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2050 * @adapter: board private structure
2051 **/
2052static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2053{
2054 int i;
2055
2056 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2057 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2058}
2059
2060/**
2061 * igb_free_rx_resources - Free Rx Resources
2062 * @adapter: board private structure
2063 * @rx_ring: ring to clean the resources from
2064 *
2065 * Free all receive software resources
2066 **/
3b644cf6 2067static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2068{
3b644cf6 2069 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2070
3b644cf6 2071 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2072
2073 vfree(rx_ring->buffer_info);
2074 rx_ring->buffer_info = NULL;
2075
2076 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2077
2078 rx_ring->desc = NULL;
2079}
2080
2081/**
2082 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2083 * @adapter: board private structure
2084 *
2085 * Free all receive software resources
2086 **/
2087static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2088{
2089 int i;
2090
2091 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2092 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2093}
2094
2095/**
2096 * igb_clean_rx_ring - Free Rx Buffers per Queue
2097 * @adapter: board private structure
2098 * @rx_ring: ring to free buffers from
2099 **/
3b644cf6 2100static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2101{
3b644cf6 2102 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2103 struct igb_buffer *buffer_info;
2104 struct pci_dev *pdev = adapter->pdev;
2105 unsigned long size;
2106 unsigned int i;
2107
2108 if (!rx_ring->buffer_info)
2109 return;
2110 /* Free all the Rx ring sk_buffs */
2111 for (i = 0; i < rx_ring->count; i++) {
2112 buffer_info = &rx_ring->buffer_info[i];
2113 if (buffer_info->dma) {
2114 if (adapter->rx_ps_hdr_size)
2115 pci_unmap_single(pdev, buffer_info->dma,
2116 adapter->rx_ps_hdr_size,
2117 PCI_DMA_FROMDEVICE);
2118 else
2119 pci_unmap_single(pdev, buffer_info->dma,
2120 adapter->rx_buffer_len,
2121 PCI_DMA_FROMDEVICE);
2122 buffer_info->dma = 0;
2123 }
2124
2125 if (buffer_info->skb) {
2126 dev_kfree_skb(buffer_info->skb);
2127 buffer_info->skb = NULL;
2128 }
2129 if (buffer_info->page) {
2130 pci_unmap_page(pdev, buffer_info->page_dma,
2131 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2132 put_page(buffer_info->page);
2133 buffer_info->page = NULL;
2134 buffer_info->page_dma = 0;
2135 }
2136 }
2137
2138 /* there also may be some cached data from a chained receive */
2139 if (rx_ring->pending_skb) {
2140 dev_kfree_skb(rx_ring->pending_skb);
2141 rx_ring->pending_skb = NULL;
2142 }
2143
2144 size = sizeof(struct igb_buffer) * rx_ring->count;
2145 memset(rx_ring->buffer_info, 0, size);
2146
2147 /* Zero out the descriptor ring */
2148 memset(rx_ring->desc, 0, rx_ring->size);
2149
2150 rx_ring->next_to_clean = 0;
2151 rx_ring->next_to_use = 0;
2152
2153 writel(0, adapter->hw.hw_addr + rx_ring->head);
2154 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2155}
2156
2157/**
2158 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2159 * @adapter: board private structure
2160 **/
2161static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2162{
2163 int i;
2164
2165 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2166 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2167}
2168
2169/**
2170 * igb_set_mac - Change the Ethernet Address of the NIC
2171 * @netdev: network interface device structure
2172 * @p: pointer to an address structure
2173 *
2174 * Returns 0 on success, negative on failure
2175 **/
2176static int igb_set_mac(struct net_device *netdev, void *p)
2177{
2178 struct igb_adapter *adapter = netdev_priv(netdev);
2179 struct sockaddr *addr = p;
2180
2181 if (!is_valid_ether_addr(addr->sa_data))
2182 return -EADDRNOTAVAIL;
2183
2184 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2185 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2186
2187 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2188
2189 return 0;
2190}
2191
2192/**
2193 * igb_set_multi - Multicast and Promiscuous mode set
2194 * @netdev: network interface device structure
2195 *
2196 * The set_multi entry point is called whenever the multicast address
2197 * list or the network interface flags are updated. This routine is
2198 * responsible for configuring the hardware for proper multicast,
2199 * promiscuous mode, and all-multi behavior.
2200 **/
2201static void igb_set_multi(struct net_device *netdev)
2202{
2203 struct igb_adapter *adapter = netdev_priv(netdev);
2204 struct e1000_hw *hw = &adapter->hw;
2205 struct e1000_mac_info *mac = &hw->mac;
2206 struct dev_mc_list *mc_ptr;
2207 u8 *mta_list;
2208 u32 rctl;
2209 int i;
2210
2211 /* Check for Promiscuous and All Multicast modes */
2212
2213 rctl = rd32(E1000_RCTL);
2214
2215 if (netdev->flags & IFF_PROMISC)
2216 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2217 else if (netdev->flags & IFF_ALLMULTI) {
2218 rctl |= E1000_RCTL_MPE;
2219 rctl &= ~E1000_RCTL_UPE;
2220 } else
2221 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2222
2223 wr32(E1000_RCTL, rctl);
2224
2225 if (!netdev->mc_count) {
2226 /* nothing to program, so clear mc list */
2d064c06 2227 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2228 mac->rar_entry_count);
2229 return;
2230 }
2231
2232 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2233 if (!mta_list)
2234 return;
2235
2236 /* The shared function expects a packed array of only addresses. */
2237 mc_ptr = netdev->mc_list;
2238
2239 for (i = 0; i < netdev->mc_count; i++) {
2240 if (!mc_ptr)
2241 break;
2242 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2243 mc_ptr = mc_ptr->next;
2244 }
2d064c06
AD		 2245 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2246 mac->rar_entry_count);
9d5c8243
AK		 2247 kfree(mta_list);
2248}
2249
2250/* Need to wait a few seconds after link up to get diagnostic information from
2251 * the phy */
2252static void igb_update_phy_info(unsigned long data)
2253{
2254 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2255 if (adapter->hw.phy.ops.get_phy_info)
2256 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2257}
2258
2259/**
2260 * igb_watchdog - Timer Call-back
2261 * @data: pointer to adapter cast into an unsigned long
2262 **/
2263static void igb_watchdog(unsigned long data)
2264{
2265 struct igb_adapter *adapter = (struct igb_adapter *)data;
2266 /* Do the rest outside of interrupt context */
2267 schedule_work(&adapter->watchdog_task);
2268}
2269
2270static void igb_watchdog_task(struct work_struct *work)
2271{
2272 struct igb_adapter *adapter = container_of(work,
2273 struct igb_adapter, watchdog_task);
2274 struct e1000_hw *hw = &adapter->hw;
2275
2276 struct net_device *netdev = adapter->netdev;
2277 struct igb_ring *tx_ring = adapter->tx_ring;
2278 struct e1000_mac_info *mac = &adapter->hw.mac;
2279 u32 link;
2280 s32 ret_val;
661086df
PWJ		 2281#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2282 int i;
2283#endif
9d5c8243
AK		 2284
2285 if ((netif_carrier_ok(netdev)) &&
2286 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2287 goto link_up;
2288
2289 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2290 if ((ret_val == E1000_ERR_PHY) &&
2291 (hw->phy.type == e1000_phy_igp_3) &&
2292 (rd32(E1000_CTRL) &
2293 E1000_PHY_CTRL_GBE_DISABLE))
2294 dev_info(&adapter->pdev->dev,
2295 "Gigabit has been disabled, downgrading speed\n");
2296
2297 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2298 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2299 link = mac->serdes_has_link;
2300 else
2301 link = rd32(E1000_STATUS) &
2302 E1000_STATUS_LU;
2303
2304 if (link) {
2305 if (!netif_carrier_ok(netdev)) {
2306 u32 ctrl;
2307 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2308 &adapter->link_speed,
2309 &adapter->link_duplex);
2310
2311 ctrl = rd32(E1000_CTRL);
2312 dev_info(&adapter->pdev->dev,
2313 "NIC Link is Up %d Mbps %s, "
2314 "Flow Control: %s\n",
2315 adapter->link_speed,
2316 adapter->link_duplex == FULL_DUPLEX ?
2317 "Full Duplex" : "Half Duplex",
2318 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2319 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2320 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2321 E1000_CTRL_TFCE) ? "TX" : "None")));
2322
2323 /* tweak tx_queue_len according to speed/duplex and
2324 * adjust the timeout factor */
2325 netdev->tx_queue_len = adapter->tx_queue_len;
2326 adapter->tx_timeout_factor = 1;
2327 switch (adapter->link_speed) {
2328 case SPEED_10:
2329 netdev->tx_queue_len = 10;
2330 adapter->tx_timeout_factor = 14;
2331 break;
2332 case SPEED_100:
2333 netdev->tx_queue_len = 100;
2334 /* maybe add some timeout factor ? */
2335 break;
2336 }
2337
2338 netif_carrier_on(netdev);
2339 netif_wake_queue(netdev);
661086df
PWJ		 2340#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2341 for (i = 0; i < adapter->num_tx_queues; i++)
2342 netif_wake_subqueue(netdev, i);
2343#endif
9d5c8243
AK		 2344
2345 if (!test_bit(__IGB_DOWN, &adapter->state))
2346 mod_timer(&adapter->phy_info_timer,
2347 round_jiffies(jiffies + 2 * HZ));
2348 }
2349 } else {
2350 if (netif_carrier_ok(netdev)) {
2351 adapter->link_speed = 0;
2352 adapter->link_duplex = 0;
2353 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2354 netif_carrier_off(netdev);
2355 netif_stop_queue(netdev);
661086df
PWJ		 2356#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2357 for (i = 0; i < adapter->num_tx_queues; i++)
2358 netif_stop_subqueue(netdev, i);
2359#endif
9d5c8243
AK		 2360 if (!test_bit(__IGB_DOWN, &adapter->state))
2361 mod_timer(&adapter->phy_info_timer,
2362 round_jiffies(jiffies + 2 * HZ));
2363 }
2364 }
2365
2366link_up:
2367 igb_update_stats(adapter);
2368
2369 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2370 adapter->tpt_old = adapter->stats.tpt;
2371 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2372 adapter->colc_old = adapter->stats.colc;
2373
2374 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2375 adapter->gorc_old = adapter->stats.gorc;
2376 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2377 adapter->gotc_old = adapter->stats.gotc;
2378
2379 igb_update_adaptive(&adapter->hw);
2380
2381 if (!netif_carrier_ok(netdev)) {
2382 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2383 /* We've lost link, so the controller stops DMA,
2384 * but we've got queued Tx work that's never going
2385 * to get done, so reset controller to flush Tx.
2386 * (Do the reset outside of interrupt context). */
2387 adapter->tx_timeout_count++;
2388 schedule_work(&adapter->reset_task);
2389 }
2390 }
2391
2392 /* Cause software interrupt to ensure rx ring is cleaned */
2393 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2394
2395 /* Force detection of hung controller every watchdog period */
2396 tx_ring->detect_tx_hung = true;
2397
2398 /* Reset the timer */
2399 if (!test_bit(__IGB_DOWN, &adapter->state))
2400 mod_timer(&adapter->watchdog_timer,
2401 round_jiffies(jiffies + 2 * HZ));
2402}
2403
2404enum latency_range {
2405 lowest_latency = 0,
2406 low_latency = 1,
2407 bulk_latency = 2,
2408 latency_invalid = 255
2409};
2410
2411
2412static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2413 struct igb_ring *rx_ring)
2414{
2415 struct e1000_hw *hw = &adapter->hw;
2416 int new_val;
2417
2418 new_val = rx_ring->itr_val / 2;
2419 if (new_val < IGB_MIN_DYN_ITR)
2420 new_val = IGB_MIN_DYN_ITR;
2421
2422 if (new_val != rx_ring->itr_val) {
2423 rx_ring->itr_val = new_val;
2424 wr32(rx_ring->itr_register,
2425 1000000000 / (new_val * 256));
2426 }
2427}
2428
2429static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2430 struct igb_ring *rx_ring)
2431{
2432 struct e1000_hw *hw = &adapter->hw;
2433 int new_val;
2434
2435 new_val = rx_ring->itr_val * 2;
2436 if (new_val > IGB_MAX_DYN_ITR)
2437 new_val = IGB_MAX_DYN_ITR;
2438
2439 if (new_val != rx_ring->itr_val) {
2440 rx_ring->itr_val = new_val;
2441 wr32(rx_ring->itr_register,
2442 1000000000 / (new_val * 256));
2443 }
2444}
2445
2446/**
2447 * igb_update_itr - update the dynamic ITR value based on statistics
2448 * Stores a new ITR value based on packets and byte
2449 * counts during the last interrupt. The advantage of per interrupt
2450 * computation is faster updates and more accurate ITR for the current
2451 * traffic pattern. Constants in this function were computed
2452 * based on theoretical maximum wire speed and thresholds were set based
2453 * on testing data as well as attempting to minimize response time
2454 * while increasing bulk throughput.
2455 * this functionality is controlled by the InterruptThrottleRate module
2456 * parameter (see igb_param.c)
2457 * NOTE: These calculations are only valid when operating in a single-
2458 * queue environment.
2459 * @adapter: pointer to adapter
2460 * @itr_setting: current adapter->itr
2461 * @packets: the number of packets during this measurement interval
2462 * @bytes: the number of bytes during this measurement interval
2463 **/
2464static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2465 int packets, int bytes)
2466{
2467 unsigned int retval = itr_setting;
2468
2469 if (packets == 0)
2470 goto update_itr_done;
2471
2472 switch (itr_setting) {
2473 case lowest_latency:
2474 /* handle TSO and jumbo frames */
2475 if (bytes/packets > 8000)
2476 retval = bulk_latency;
2477 else if ((packets < 5) && (bytes > 512))
2478 retval = low_latency;
2479 break;
2480 case low_latency: /* 50 usec aka 20000 ints/s */
2481 if (bytes > 10000) {
2482 /* this if handles the TSO accounting */
2483 if (bytes/packets > 8000) {
2484 retval = bulk_latency;
2485 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2486 retval = bulk_latency;
2487 } else if ((packets > 35)) {
2488 retval = lowest_latency;
2489 }
2490 } else if (bytes/packets > 2000) {
2491 retval = bulk_latency;
2492 } else if (packets <= 2 && bytes < 512) {
2493 retval = lowest_latency;
2494 }
2495 break;
2496 case bulk_latency: /* 250 usec aka 4000 ints/s */
2497 if (bytes > 25000) {
2498 if (packets > 35)
2499 retval = low_latency;
2500 } else if (bytes < 6000) {
2501 retval = low_latency;
2502 }
2503 break;
2504 }
2505
2506update_itr_done:
2507 return retval;
2508}
2509
2510static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2511 int rx_only)
2512{
2513 u16 current_itr;
2514 u32 new_itr = adapter->itr;
2515
2516 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2517 if (adapter->link_speed != SPEED_1000) {
2518 current_itr = 0;
2519 new_itr = 4000;
2520 goto set_itr_now;
2521 }
2522
2523 adapter->rx_itr = igb_update_itr(adapter,
2524 adapter->rx_itr,
2525 adapter->rx_ring->total_packets,
2526 adapter->rx_ring->total_bytes);
2527 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2528 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2529 adapter->rx_itr = low_latency;
2530
2531 if (!rx_only) {
2532 adapter->tx_itr = igb_update_itr(adapter,
2533 adapter->tx_itr,
2534 adapter->tx_ring->total_packets,
2535 adapter->tx_ring->total_bytes);
2536 /* conservative mode (itr 3) eliminates the
2537 * lowest_latency setting */
2538 if (adapter->itr_setting == 3 &&
2539 adapter->tx_itr == lowest_latency)
2540 adapter->tx_itr = low_latency;
2541
2542 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2543 } else {
2544 current_itr = adapter->rx_itr;
2545 }
2546
2547 switch (current_itr) {
2548 /* counts and packets in update_itr are dependent on these numbers */
2549 case lowest_latency:
2550 new_itr = 70000;
2551 break;
2552 case low_latency:
2553 new_itr = 20000; /* aka hwitr = ~200 */
2554 break;
2555 case bulk_latency:
2556 new_itr = 4000;
2557 break;
2558 default:
2559 break;
2560 }
2561
2562set_itr_now:
2563 if (new_itr != adapter->itr) {
2564 /* this attempts to bias the interrupt rate towards Bulk
2565 * by adding intermediate steps when interrupt rate is
2566 * increasing */
2567 new_itr = new_itr > adapter->itr ?
2568 min(adapter->itr + (new_itr >> 2), new_itr) :
2569 new_itr;
2570 /* Don't write the value here; it resets the adapter's
2571 * internal timer, and causes us to delay far longer than
2572 * we should between interrupts. Instead, we write the ITR
2573 * value at the beginning of the next interrupt so the timing
2574 * ends up being correct.
2575 */
2576 adapter->itr = new_itr;
2577 adapter->set_itr = 1;
2578 }
2579
2580 return;
2581}
2582
2583
2584#define IGB_TX_FLAGS_CSUM 0x00000001
2585#define IGB_TX_FLAGS_VLAN 0x00000002
2586#define IGB_TX_FLAGS_TSO 0x00000004
2587#define IGB_TX_FLAGS_IPV4 0x00000008
2588#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2589#define IGB_TX_FLAGS_VLAN_SHIFT 16
2590
2591static inline int igb_tso_adv(struct igb_adapter *adapter,
2592 struct igb_ring *tx_ring,
2593 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2594{
2595 struct e1000_adv_tx_context_desc *context_desc;
2596 unsigned int i;
2597 int err;
2598 struct igb_buffer *buffer_info;
2599 u32 info = 0, tu_cmd = 0;
2600 u32 mss_l4len_idx, l4len;
2601 *hdr_len = 0;
2602
2603 if (skb_header_cloned(skb)) {
2604 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2605 if (err)
2606 return err;
2607 }
2608
2609 l4len = tcp_hdrlen(skb);
2610 *hdr_len += l4len;
2611
2612 if (skb->protocol == htons(ETH_P_IP)) {
2613 struct iphdr *iph = ip_hdr(skb);
2614 iph->tot_len = 0;
2615 iph->check = 0;
2616 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2617 iph->daddr, 0,
2618 IPPROTO_TCP,
2619 0);
2620 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2621 ipv6_hdr(skb)->payload_len = 0;
2622 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2623 &ipv6_hdr(skb)->daddr,
2624 0, IPPROTO_TCP, 0);
2625 }
2626
2627 i = tx_ring->next_to_use;
2628
2629 buffer_info = &tx_ring->buffer_info[i];
2630 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2631 /* VLAN MACLEN IPLEN */
2632 if (tx_flags & IGB_TX_FLAGS_VLAN)
2633 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2634 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2635 *hdr_len += skb_network_offset(skb);
2636 info |= skb_network_header_len(skb);
2637 *hdr_len += skb_network_header_len(skb);
2638 context_desc->vlan_macip_lens = cpu_to_le32(info);
2639
2640 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2641 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2642
2643 if (skb->protocol == htons(ETH_P_IP))
2644 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2645 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2646
2647 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2648
2649 /* MSS L4LEN IDX */
2650 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2651 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2652
2653 /* Context index must be unique per ring. Luckily, so is the interrupt
2654 * mask value. */
2655 mss_l4len_idx |= tx_ring->eims_value >> 4;
2656
2657 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2658 context_desc->seqnum_seed = 0;
2659
2660 buffer_info->time_stamp = jiffies;
2661 buffer_info->dma = 0;
2662 i++;
2663 if (i == tx_ring->count)
2664 i = 0;
2665
2666 tx_ring->next_to_use = i;
2667
2668 return true;
2669}
2670
2671static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2672 struct igb_ring *tx_ring,
2673 struct sk_buff *skb, u32 tx_flags)
2674{
2675 struct e1000_adv_tx_context_desc *context_desc;
2676 unsigned int i;
2677 struct igb_buffer *buffer_info;
2678 u32 info = 0, tu_cmd = 0;
2679
2680 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2681 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2682 i = tx_ring->next_to_use;
2683 buffer_info = &tx_ring->buffer_info[i];
2684 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2685
2686 if (tx_flags & IGB_TX_FLAGS_VLAN)
2687 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2688 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2689 if (skb->ip_summed == CHECKSUM_PARTIAL)
2690 info |= skb_network_header_len(skb);
2691
2692 context_desc->vlan_macip_lens = cpu_to_le32(info);
2693
2694 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2695
2696 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2697 switch (skb->protocol) {
2698 case __constant_htons(ETH_P_IP):
9d5c8243 2699 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2700 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2701 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2702 break;
2703 case __constant_htons(ETH_P_IPV6):
2704 /* XXX what about other V6 headers?? */
2705 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2706 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2707 break;
2708 default:
2709 if (unlikely(net_ratelimit()))
2710 dev_warn(&adapter->pdev->dev,
2711 "partial checksum but proto=%x!\n",
2712 skb->protocol);
2713 break;
2714 }
9d5c8243
AK		 2715 }
2716
2717 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2718 context_desc->seqnum_seed = 0;
2719 context_desc->mss_l4len_idx =
661086df 2720 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2721
2722 buffer_info->time_stamp = jiffies;
2723 buffer_info->dma = 0;
2724
2725 i++;
2726 if (i == tx_ring->count)
2727 i = 0;
2728 tx_ring->next_to_use = i;
2729
2730 return true;
2731 }
2732
2733
2734 return false;
2735}
2736
2737#define IGB_MAX_TXD_PWR 16
2738#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2739
2740static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2741 struct igb_ring *tx_ring,
2742 struct sk_buff *skb)
2743{
2744 struct igb_buffer *buffer_info;
2745 unsigned int len = skb_headlen(skb);
2746 unsigned int count = 0, i;
2747 unsigned int f;
2748
2749 i = tx_ring->next_to_use;
2750
2751 buffer_info = &tx_ring->buffer_info[i];
2752 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2753 buffer_info->length = len;
2754 /* set time_stamp *before* dma to help avoid a possible race */
2755 buffer_info->time_stamp = jiffies;
2756 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2757 PCI_DMA_TODEVICE);
2758 count++;
2759 i++;
2760 if (i == tx_ring->count)
2761 i = 0;
2762
2763 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2764 struct skb_frag_struct *frag;
2765
2766 frag = &skb_shinfo(skb)->frags[f];
2767 len = frag->size;
2768
2769 buffer_info = &tx_ring->buffer_info[i];
2770 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2771 buffer_info->length = len;
2772 buffer_info->time_stamp = jiffies;
2773 buffer_info->dma = pci_map_page(adapter->pdev,
2774 frag->page,
2775 frag->page_offset,
2776 len,
2777 PCI_DMA_TODEVICE);
2778
2779 count++;
2780 i++;
2781 if (i == tx_ring->count)
2782 i = 0;
2783 }
2784
2785 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2786 tx_ring->buffer_info[i].skb = skb;
2787
2788 return count;
2789}
2790
2791static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2792 struct igb_ring *tx_ring,
2793 int tx_flags, int count, u32 paylen,
2794 u8 hdr_len)
2795{
2796 union e1000_adv_tx_desc *tx_desc = NULL;
2797 struct igb_buffer *buffer_info;
2798 u32 olinfo_status = 0, cmd_type_len;
2799 unsigned int i;
2800
2801 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2802 E1000_ADVTXD_DCMD_DEXT);
2803
2804 if (tx_flags & IGB_TX_FLAGS_VLAN)
2805 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2806
2807 if (tx_flags & IGB_TX_FLAGS_TSO) {
2808 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2809
2810 /* insert tcp checksum */
2811 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2812
2813 /* insert ip checksum */
2814 if (tx_flags & IGB_TX_FLAGS_IPV4)
2815 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2816
2817 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2818 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2819 }
2820
2821 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2822 IGB_TX_FLAGS_VLAN))
661086df 2823 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2824
2825 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2826
2827 i = tx_ring->next_to_use;
2828 while (count--) {
2829 buffer_info = &tx_ring->buffer_info[i];
2830 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2831 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2832 tx_desc->read.cmd_type_len =
2833 cpu_to_le32(cmd_type_len | buffer_info->length);
2834 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2835 i++;
2836 if (i == tx_ring->count)
2837 i = 0;
2838 }
2839
2840 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2841 /* Force memory writes to complete before letting h/w
2842 * know there are new descriptors to fetch. (Only
2843 * applicable for weak-ordered memory model archs,
2844 * such as IA-64). */
2845 wmb();
2846
2847 tx_ring->next_to_use = i;
2848 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2849 /* we need this if more than one processor can write to our tail
2850 * at a time, it syncronizes IO on IA64/Altix systems */
2851 mmiowb();
2852}
2853
2854static int __igb_maybe_stop_tx(struct net_device *netdev,
2855 struct igb_ring *tx_ring, int size)
2856{
2857 struct igb_adapter *adapter = netdev_priv(netdev);
2858
661086df
PWJ		 2859#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2860 netif_stop_subqueue(netdev, tx_ring->queue_index);
2861#else
9d5c8243 2862 netif_stop_queue(netdev);
661086df
PWJ		 2863#endif
2864
9d5c8243
AK		 2865 /* Herbert's original patch had:
2866 * smp_mb__after_netif_stop_queue();
2867 * but since that doesn't exist yet, just open code it. */
2868 smp_mb();
2869
2870 /* We need to check again in a case another CPU has just
2871 * made room available. */
2872 if (IGB_DESC_UNUSED(tx_ring) < size)
2873 return -EBUSY;
2874
2875 /* A reprieve! */
661086df
PWJ		 2876#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2877 netif_wake_subqueue(netdev, tx_ring->queue_index);
2878#else
2879 netif_wake_queue(netdev);
2880#endif
9d5c8243
AK		 2881 ++adapter->restart_queue;
2882 return 0;
2883}
2884
2885static int igb_maybe_stop_tx(struct net_device *netdev,
2886 struct igb_ring *tx_ring, int size)
2887{
2888 if (IGB_DESC_UNUSED(tx_ring) >= size)
2889 return 0;
2890 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2891}
2892
2893#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2894
2895static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2896 struct net_device *netdev,
2897 struct igb_ring *tx_ring)
2898{
2899 struct igb_adapter *adapter = netdev_priv(netdev);
2900 unsigned int tx_flags = 0;
2901 unsigned int len;
9d5c8243
AK		 2902 u8 hdr_len = 0;
2903 int tso = 0;
2904
2905 len = skb_headlen(skb);
2906
2907 if (test_bit(__IGB_DOWN, &adapter->state)) {
2908 dev_kfree_skb_any(skb);
2909 return NETDEV_TX_OK;
2910 }
2911
2912 if (skb->len <= 0) {
2913 dev_kfree_skb_any(skb);
2914 return NETDEV_TX_OK;
2915 }
2916
9d5c8243
AK		 2917 /* need: 1 descriptor per page,
2918 * + 2 desc gap to keep tail from touching head,
2919 * + 1 desc for skb->data,
2920 * + 1 desc for context descriptor,
2921 * otherwise try next time */
2922 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2923 /* this is a hard error */
9d5c8243
AK		 2924 return NETDEV_TX_BUSY;
2925 }
2926
2927 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2928 tx_flags |= IGB_TX_FLAGS_VLAN;
2929 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2930 }
2931
661086df
PWJ		 2932 if (skb->protocol == htons(ETH_P_IP))
2933 tx_flags |= IGB_TX_FLAGS_IPV4;
2934
9d5c8243
AK		 2935 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2936 &hdr_len) : 0;
2937
2938 if (tso < 0) {
2939 dev_kfree_skb_any(skb);
9d5c8243
AK		 2940 return NETDEV_TX_OK;
2941 }
2942
2943 if (tso)
2944 tx_flags |= IGB_TX_FLAGS_TSO;
2945 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2946 if (skb->ip_summed == CHECKSUM_PARTIAL)
2947 tx_flags |= IGB_TX_FLAGS_CSUM;
2948
9d5c8243
AK		 2949 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2950 igb_tx_map_adv(adapter, tx_ring, skb),
2951 skb->len, hdr_len);
2952
2953 netdev->trans_start = jiffies;
2954
2955 /* Make sure there is space in the ring for the next send. */
2956 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2957
9d5c8243
AK		 2958 return NETDEV_TX_OK;
2959}
2960
2961static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2962{
2963 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 2964 struct igb_ring *tx_ring;
2965
2966#ifdef CONFIG_NETDEVICES_MULTIQUEUE
2967 int r_idx = 0;
2968 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
2969 tx_ring = adapter->multi_tx_table[r_idx];
2970#else
2971 tx_ring = &adapter->tx_ring[0];
2972#endif
2973
9d5c8243
AK		 2974
2975 /* This goes back to the question of how to logically map a tx queue
2976 * to a flow. Right now, performance is impacted slightly negatively
2977 * if using multiple tx queues. If the stack breaks away from a
2978 * single qdisc implementation, we can look at this again. */
2979 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2980}
2981
2982/**
2983 * igb_tx_timeout - Respond to a Tx Hang
2984 * @netdev: network interface device structure
2985 **/
2986static void igb_tx_timeout(struct net_device *netdev)
2987{
2988 struct igb_adapter *adapter = netdev_priv(netdev);
2989 struct e1000_hw *hw = &adapter->hw;
2990
2991 /* Do the reset outside of interrupt context */
2992 adapter->tx_timeout_count++;
2993 schedule_work(&adapter->reset_task);
2994 wr32(E1000_EICS, adapter->eims_enable_mask &
2995 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2996}
2997
2998static void igb_reset_task(struct work_struct *work)
2999{
3000 struct igb_adapter *adapter;
3001 adapter = container_of(work, struct igb_adapter, reset_task);
3002
3003 igb_reinit_locked(adapter);
3004}
3005
3006/**
3007 * igb_get_stats - Get System Network Statistics
3008 * @netdev: network interface device structure
3009 *
3010 * Returns the address of the device statistics structure.
3011 * The statistics are actually updated from the timer callback.
3012 **/
3013static struct net_device_stats *
3014igb_get_stats(struct net_device *netdev)
3015{
3016 struct igb_adapter *adapter = netdev_priv(netdev);
3017
3018 /* only return the current stats */
3019 return &adapter->net_stats;
3020}
3021
3022/**
3023 * igb_change_mtu - Change the Maximum Transfer Unit
3024 * @netdev: network interface device structure
3025 * @new_mtu: new value for maximum frame size
3026 *
3027 * Returns 0 on success, negative on failure
3028 **/
3029static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3030{
3031 struct igb_adapter *adapter = netdev_priv(netdev);
3032 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3033
3034 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3035 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3036 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3037 return -EINVAL;
3038 }
3039
3040#define MAX_STD_JUMBO_FRAME_SIZE 9234
3041 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3042 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3043 return -EINVAL;
3044 }
3045
3046 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3047 msleep(1);
3048 /* igb_down has a dependency on max_frame_size */
3049 adapter->max_frame_size = max_frame;
3050 if (netif_running(netdev))
3051 igb_down(adapter);
3052
3053 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3054 * means we reserve 2 more, this pushes us to allocate from the next
3055 * larger slab size.
3056 * i.e. RXBUFFER_2048 --> size-4096 slab
3057 */
3058
3059 if (max_frame <= IGB_RXBUFFER_256)
3060 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3061 else if (max_frame <= IGB_RXBUFFER_512)
3062 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3063 else if (max_frame <= IGB_RXBUFFER_1024)
3064 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3065 else if (max_frame <= IGB_RXBUFFER_2048)
3066 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3067 else
3068 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
3069 /* adjust allocation if LPE protects us, and we aren't using SBP */
3070 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3071 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3072 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3073
3074 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3075 netdev->mtu, new_mtu);
3076 netdev->mtu = new_mtu;
3077
3078 if (netif_running(netdev))
3079 igb_up(adapter);
3080 else
3081 igb_reset(adapter);
3082
3083 clear_bit(__IGB_RESETTING, &adapter->state);
3084
3085 return 0;
3086}
3087
3088/**
3089 * igb_update_stats - Update the board statistics counters
3090 * @adapter: board private structure
3091 **/
3092
3093void igb_update_stats(struct igb_adapter *adapter)
3094{
3095 struct e1000_hw *hw = &adapter->hw;
3096 struct pci_dev *pdev = adapter->pdev;
3097 u16 phy_tmp;
3098
3099#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3100
3101 /*
3102 * Prevent stats update while adapter is being reset, or if the pci
3103 * connection is down.
3104 */
3105 if (adapter->link_speed == 0)
3106 return;
3107 if (pci_channel_offline(pdev))
3108 return;
3109
3110 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3111 adapter->stats.gprc += rd32(E1000_GPRC);
3112 adapter->stats.gorc += rd32(E1000_GORCL);
3113 rd32(E1000_GORCH); /* clear GORCL */
3114 adapter->stats.bprc += rd32(E1000_BPRC);
3115 adapter->stats.mprc += rd32(E1000_MPRC);
3116 adapter->stats.roc += rd32(E1000_ROC);
3117
3118 adapter->stats.prc64 += rd32(E1000_PRC64);
3119 adapter->stats.prc127 += rd32(E1000_PRC127);
3120 adapter->stats.prc255 += rd32(E1000_PRC255);
3121 adapter->stats.prc511 += rd32(E1000_PRC511);
3122 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3123 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3124 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3125 adapter->stats.sec += rd32(E1000_SEC);
3126
3127 adapter->stats.mpc += rd32(E1000_MPC);
3128 adapter->stats.scc += rd32(E1000_SCC);
3129 adapter->stats.ecol += rd32(E1000_ECOL);
3130 adapter->stats.mcc += rd32(E1000_MCC);
3131 adapter->stats.latecol += rd32(E1000_LATECOL);
3132 adapter->stats.dc += rd32(E1000_DC);
3133 adapter->stats.rlec += rd32(E1000_RLEC);
3134 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3135 adapter->stats.xontxc += rd32(E1000_XONTXC);
3136 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3137 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3138 adapter->stats.fcruc += rd32(E1000_FCRUC);
3139 adapter->stats.gptc += rd32(E1000_GPTC);
3140 adapter->stats.gotc += rd32(E1000_GOTCL);
3141 rd32(E1000_GOTCH); /* clear GOTCL */
3142 adapter->stats.rnbc += rd32(E1000_RNBC);
3143 adapter->stats.ruc += rd32(E1000_RUC);
3144 adapter->stats.rfc += rd32(E1000_RFC);
3145 adapter->stats.rjc += rd32(E1000_RJC);
3146 adapter->stats.tor += rd32(E1000_TORH);
3147 adapter->stats.tot += rd32(E1000_TOTH);
3148 adapter->stats.tpr += rd32(E1000_TPR);
3149
3150 adapter->stats.ptc64 += rd32(E1000_PTC64);
3151 adapter->stats.ptc127 += rd32(E1000_PTC127);
3152 adapter->stats.ptc255 += rd32(E1000_PTC255);
3153 adapter->stats.ptc511 += rd32(E1000_PTC511);
3154 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3155 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3156
3157 adapter->stats.mptc += rd32(E1000_MPTC);
3158 adapter->stats.bptc += rd32(E1000_BPTC);
3159
3160 /* used for adaptive IFS */
3161
3162 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3163 adapter->stats.tpt += hw->mac.tx_packet_delta;
3164 hw->mac.collision_delta = rd32(E1000_COLC);
3165 adapter->stats.colc += hw->mac.collision_delta;
3166
3167 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3168 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3169 adapter->stats.tncrs += rd32(E1000_TNCRS);
3170 adapter->stats.tsctc += rd32(E1000_TSCTC);
3171 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3172
3173 adapter->stats.iac += rd32(E1000_IAC);
3174 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3175 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3176 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3177 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3178 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3179 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3180 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3181 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3182
3183 /* Fill out the OS statistics structure */
3184 adapter->net_stats.multicast = adapter->stats.mprc;
3185 adapter->net_stats.collisions = adapter->stats.colc;
3186
3187 /* Rx Errors */
3188
3189 /* RLEC on some newer hardware can be incorrect so build
3190 * our own version based on RUC and ROC */
3191 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3192 adapter->stats.crcerrs + adapter->stats.algnerrc +
3193 adapter->stats.ruc + adapter->stats.roc +
3194 adapter->stats.cexterr;
3195 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3196 adapter->stats.roc;
3197 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3198 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3199 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3200
3201 /* Tx Errors */
3202 adapter->net_stats.tx_errors = adapter->stats.ecol +
3203 adapter->stats.latecol;
3204 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3205 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3206 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3207
3208 /* Tx Dropped needs to be maintained elsewhere */
3209
3210 /* Phy Stats */
3211 if (hw->phy.media_type == e1000_media_type_copper) {
3212 if ((adapter->link_speed == SPEED_1000) &&
3213 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3214 &phy_tmp))) {
3215 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3216 adapter->phy_stats.idle_errors += phy_tmp;
3217 }
3218 }
3219
3220 /* Management Stats */
3221 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3222 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3223 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3224}
3225
3226
3227static irqreturn_t igb_msix_other(int irq, void *data)
3228{
3229 struct net_device *netdev = data;
3230 struct igb_adapter *adapter = netdev_priv(netdev);
3231 struct e1000_hw *hw = &adapter->hw;
844290e5 3232 u32 icr = rd32(E1000_ICR);
9d5c8243 3233
844290e5
PW		 3234 /* reading ICR causes bit 31 of EICR to be cleared */
3235 if (!(icr & E1000_ICR_LSC))
3236 goto no_link_interrupt;
3237 hw->mac.get_link_status = 1;
3238 /* guard against interrupt when we're going down */
3239 if (!test_bit(__IGB_DOWN, &adapter->state))
3240 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3241
9d5c8243
AK		 3242no_link_interrupt:
3243 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3244 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3245
3246 return IRQ_HANDLED;
3247}
3248
3249static irqreturn_t igb_msix_tx(int irq, void *data)
3250{
3251 struct igb_ring *tx_ring = data;
3252 struct igb_adapter *adapter = tx_ring->adapter;
3253 struct e1000_hw *hw = &adapter->hw;
3254
3255 if (!tx_ring->itr_val)
3256 wr32(E1000_EIMC, tx_ring->eims_value);
fe4506b6
JC		 3257#ifdef CONFIG_DCA
3258 if (adapter->dca_enabled)
3259 igb_update_tx_dca(tx_ring);
3260#endif
9d5c8243
AK		 3261 tx_ring->total_bytes = 0;
3262 tx_ring->total_packets = 0;
661086df
PWJ		 3263
3264 /* auto mask will automatically reenable the interrupt when we write
3265 * EICS */
3b644cf6 3266 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3267 /* Ring was not completely cleaned, so fire another interrupt */
3268 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3269 else
9d5c8243 3270 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3271
9d5c8243
AK		 3272 return IRQ_HANDLED;
3273}
3274
3275static irqreturn_t igb_msix_rx(int irq, void *data)
3276{
3277 struct igb_ring *rx_ring = data;
3278 struct igb_adapter *adapter = rx_ring->adapter;
3279 struct e1000_hw *hw = &adapter->hw;
3280
844290e5
PW		 3281 /* Write the ITR value calculated at the end of the
3282 * previous interrupt.
3283 */
9d5c8243 3284
844290e5
PW		 3285 if (adapter->set_itr) {
3286 wr32(rx_ring->itr_register,
3287 1000000000 / (rx_ring->itr_val * 256));
3288 adapter->set_itr = 0;
9d5c8243
AK		 3289 }
3290
844290e5
PW		 3291 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3292 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3293
fe4506b6
JC		 3294#ifdef CONFIG_DCA
3295 if (adapter->dca_enabled)
3296 igb_update_rx_dca(rx_ring);
3297#endif
3298 return IRQ_HANDLED;
3299}
3300
3301#ifdef CONFIG_DCA
3302static void igb_update_rx_dca(struct igb_ring *rx_ring)
3303{
3304 u32 dca_rxctrl;
3305 struct igb_adapter *adapter = rx_ring->adapter;
3306 struct e1000_hw *hw = &adapter->hw;
3307 int cpu = get_cpu();
3308 int q = rx_ring - adapter->rx_ring;
3309
3310 if (rx_ring->cpu != cpu) {
3311 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3312 if (hw->mac.type == e1000_82576) {
3313 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3314 dca_rxctrl |= dca_get_tag(cpu) <<
3315 E1000_DCA_RXCTRL_CPUID_SHIFT;
3316 } else {
3317 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3318 dca_rxctrl |= dca_get_tag(cpu);
3319 }
fe4506b6
JC		 3320 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3321 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3322 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3323 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3324 rx_ring->cpu = cpu;
3325 }
3326 put_cpu();
3327}
3328
3329static void igb_update_tx_dca(struct igb_ring *tx_ring)
3330{
3331 u32 dca_txctrl;
3332 struct igb_adapter *adapter = tx_ring->adapter;
3333 struct e1000_hw *hw = &adapter->hw;
3334 int cpu = get_cpu();
3335 int q = tx_ring - adapter->tx_ring;
3336
3337 if (tx_ring->cpu != cpu) {
3338 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3339 if (hw->mac.type == e1000_82576) {
3340 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3341 dca_txctrl |= dca_get_tag(cpu) <<
3342 E1000_DCA_TXCTRL_CPUID_SHIFT;
3343 } else {
3344 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3345 dca_txctrl |= dca_get_tag(cpu);
3346 }
fe4506b6
JC		 3347 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3348 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3349 tx_ring->cpu = cpu;
3350 }
3351 put_cpu();
3352}
3353
3354static void igb_setup_dca(struct igb_adapter *adapter)
3355{
3356 int i;
3357
3358 if (!(adapter->dca_enabled))
3359 return;
3360
3361 for (i = 0; i < adapter->num_tx_queues; i++) {
3362 adapter->tx_ring[i].cpu = -1;
3363 igb_update_tx_dca(&adapter->tx_ring[i]);
3364 }
3365 for (i = 0; i < adapter->num_rx_queues; i++) {
3366 adapter->rx_ring[i].cpu = -1;
3367 igb_update_rx_dca(&adapter->rx_ring[i]);
3368 }
3369}
3370
3371static int __igb_notify_dca(struct device *dev, void *data)
3372{
3373 struct net_device *netdev = dev_get_drvdata(dev);
3374 struct igb_adapter *adapter = netdev_priv(netdev);
3375 struct e1000_hw *hw = &adapter->hw;
3376 unsigned long event = *(unsigned long *)data;
3377
3378 switch (event) {
3379 case DCA_PROVIDER_ADD:
3380 /* if already enabled, don't do it again */
3381 if (adapter->dca_enabled)
3382 break;
3383 adapter->dca_enabled = true;
3384 /* Always use CB2 mode, difference is masked
3385 * in the CB driver. */
3386 wr32(E1000_DCA_CTRL, 2);
3387 if (dca_add_requester(dev) == 0) {
3388 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3389 igb_setup_dca(adapter);
3390 break;
3391 }
3392 /* Fall Through since DCA is disabled. */
3393 case DCA_PROVIDER_REMOVE:
3394 if (adapter->dca_enabled) {
3395 /* without this a class_device is left
3396 * hanging around in the sysfs model */
3397 dca_remove_requester(dev);
3398 dev_info(&adapter->pdev->dev, "DCA disabled\n");
3399 adapter->dca_enabled = false;
3400 wr32(E1000_DCA_CTRL, 1);
3401 }
3402 break;
3403 }
3404
3405 return 0;
9d5c8243
AK		 3406}
3407
fe4506b6
JC		 3408static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3409 void *p)
3410{
3411 int ret_val;
3412
3413 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3414 __igb_notify_dca);
3415
3416 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3417}
3418#endif /* CONFIG_DCA */
9d5c8243
AK		 3419
3420/**
3421 * igb_intr_msi - Interrupt Handler
3422 * @irq: interrupt number
3423 * @data: pointer to a network interface device structure
3424 **/
3425static irqreturn_t igb_intr_msi(int irq, void *data)
3426{
3427 struct net_device *netdev = data;
3428 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3429 struct e1000_hw *hw = &adapter->hw;
3430 /* read ICR disables interrupts using IAM */
3431 u32 icr = rd32(E1000_ICR);
3432
3433 /* Write the ITR value calculated at the end of the
3434 * previous interrupt.
3435 */
3436 if (adapter->set_itr) {
844290e5 3437 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3438 adapter->set_itr = 0;
3439 }
3440
9d5c8243
AK		 3441 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3442 hw->mac.get_link_status = 1;
3443 if (!test_bit(__IGB_DOWN, &adapter->state))
3444 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3445 }
3446
844290e5 3447 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3448
3449 return IRQ_HANDLED;
3450}
3451
3452/**
3453 * igb_intr - Interrupt Handler
3454 * @irq: interrupt number
3455 * @data: pointer to a network interface device structure
3456 **/
3457static irqreturn_t igb_intr(int irq, void *data)
3458{
3459 struct net_device *netdev = data;
3460 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3461 struct e1000_hw *hw = &adapter->hw;
3462 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3463 * need for the IMC write */
3464 u32 icr = rd32(E1000_ICR);
3465 u32 eicr = 0;
3466 if (!icr)
3467 return IRQ_NONE; /* Not our interrupt */
3468
3469 /* Write the ITR value calculated at the end of the
3470 * previous interrupt.
3471 */
3472 if (adapter->set_itr) {
844290e5 3473 wr32(E1000_ITR, 1000000000 / (adapter->itr * 256));
9d5c8243
AK		 3474 adapter->set_itr = 0;
3475 }
3476
3477 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3478 * not set, then the adapter didn't send an interrupt */
3479 if (!(icr & E1000_ICR_INT_ASSERTED))
3480 return IRQ_NONE;
3481
3482 eicr = rd32(E1000_EICR);
3483
3484 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3485 hw->mac.get_link_status = 1;
3486 /* guard against interrupt when we're going down */
3487 if (!test_bit(__IGB_DOWN, &adapter->state))
3488 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3489 }
3490
844290e5 3491 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3492
3493 return IRQ_HANDLED;
3494}
3495
3496/**
661086df
PWJ		 3497 * igb_poll - NAPI Rx polling callback
3498 * @napi: napi polling structure
3499 * @budget: count of how many packets we should handle
9d5c8243 3500 **/
661086df 3501static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3502{
661086df
PWJ		 3503 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3504 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3505 struct net_device *netdev = adapter->netdev;
661086df 3506 int tx_clean_complete, work_done = 0;
9d5c8243 3507
661086df 3508 /* this poll routine only supports one tx and one rx queue */
fe4506b6
JC		 3509#ifdef CONFIG_DCA
3510 if (adapter->dca_enabled)
3511 igb_update_tx_dca(&adapter->tx_ring[0]);
3512#endif
661086df 3513 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6
JC		 3514
3515#ifdef CONFIG_DCA
3516 if (adapter->dca_enabled)
3517 igb_update_rx_dca(&adapter->rx_ring[0]);
3518#endif
661086df 3519 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3520
3521 /* If no Tx and not enough Rx work done, exit the polling mode */
3522 if ((tx_clean_complete && (work_done < budget)) ||
3523 !netif_running(netdev)) {
9d5c8243
AK		 3524 if (adapter->itr_setting & 3)
3525 igb_set_itr(adapter, E1000_ITR, false);
3526 netif_rx_complete(netdev, napi);
3527 if (!test_bit(__IGB_DOWN, &adapter->state))
3528 igb_irq_enable(adapter);
3529 return 0;
3530 }
3531
3532 return 1;
3533}
3534
3535static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3536{
3537 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3538 struct igb_adapter *adapter = rx_ring->adapter;
3539 struct e1000_hw *hw = &adapter->hw;
3540 struct net_device *netdev = adapter->netdev;
3541 int work_done = 0;
3542
3543 /* Keep link state information with original netdev */
3544 if (!netif_carrier_ok(netdev))
3545 goto quit_polling;
3546
fe4506b6
JC		 3547#ifdef CONFIG_DCA
3548 if (adapter->dca_enabled)
3549 igb_update_rx_dca(rx_ring);
3550#endif
3b644cf6 3551 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3552
3553
3554 /* If not enough Rx work done, exit the polling mode */
3555 if ((work_done == 0) || !netif_running(netdev)) {
3556quit_polling:
3557 netif_rx_complete(netdev, napi);
3558
3559 wr32(E1000_EIMS, rx_ring->eims_value);
3560 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3561 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3562 int mean_size = rx_ring->total_bytes /
3563 rx_ring->total_packets;
3564 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3565 igb_raise_rx_eitr(adapter, rx_ring);
3566 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3567 igb_lower_rx_eitr(adapter, rx_ring);
3568 }
844290e5
PW		 3569
3570 if (!test_bit(__IGB_DOWN, &adapter->state))
3571 wr32(E1000_EIMS, rx_ring->eims_value);
3572
9d5c8243
AK		 3573 return 0;
3574 }
3575
3576 return 1;
3577}
6d8126f9
AV		 3578
3579static inline u32 get_head(struct igb_ring *tx_ring)
3580{
3581 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3582 return le32_to_cpu(*(volatile __le32 *)end);
3583}
3584
9d5c8243
AK		 3585/**
3586 * igb_clean_tx_irq - Reclaim resources after transmit completes
3587 * @adapter: board private structure
3588 * returns true if ring is completely cleaned
3589 **/
3b644cf6 3590static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3591{
3b644cf6 3592 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3593 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3594 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3595 struct e1000_tx_desc *tx_desc;
3596 struct igb_buffer *buffer_info;
3597 struct sk_buff *skb;
3598 unsigned int i;
3599 u32 head, oldhead;
3600 unsigned int count = 0;
3601 bool cleaned = false;
3602 bool retval = true;
3603 unsigned int total_bytes = 0, total_packets = 0;
3604
3605 rmb();
6d8126f9 3606 head = get_head(tx_ring);
9d5c8243
AK		 3607 i = tx_ring->next_to_clean;
3608 while (1) {
3609 while (i != head) {
3610 cleaned = true;
3611 tx_desc = E1000_TX_DESC(*tx_ring, i);
3612 buffer_info = &tx_ring->buffer_info[i];
3613 skb = buffer_info->skb;
3614
3615 if (skb) {
3616 unsigned int segs, bytecount;
3617 /* gso_segs is currently only valid for tcp */
3618 segs = skb_shinfo(skb)->gso_segs ?: 1;
3619 /* multiply data chunks by size of headers */
3620 bytecount = ((segs - 1) * skb_headlen(skb)) +
3621 skb->len;
3622 total_packets += segs;
3623 total_bytes += bytecount;
3624 }
3625
3626 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3627 tx_desc->upper.data = 0;
3628
3629 i++;
3630 if (i == tx_ring->count)
3631 i = 0;
3632
3633 count++;
3634 if (count == IGB_MAX_TX_CLEAN) {
3635 retval = false;
3636 goto done_cleaning;
3637 }
3638 }
3639 oldhead = head;
3640 rmb();
6d8126f9 3641 head = get_head(tx_ring);
9d5c8243
AK		 3642 if (head == oldhead)
3643 goto done_cleaning;
3644 } /* while (1) */
3645
3646done_cleaning:
3647 tx_ring->next_to_clean = i;
3648
3649 if (unlikely(cleaned &&
3650 netif_carrier_ok(netdev) &&
3651 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3652 /* Make sure that anybody stopping the queue after this
3653 * sees the new next_to_clean.
3654 */
3655 smp_mb();
661086df
PWJ		 3656#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3657 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3658 !(test_bit(__IGB_DOWN, &adapter->state))) {
3659 netif_wake_subqueue(netdev, tx_ring->queue_index);
3660 ++adapter->restart_queue;
3661 }
3662#else
9d5c8243
AK		 3663 if (netif_queue_stopped(netdev) &&
3664 !(test_bit(__IGB_DOWN, &adapter->state))) {
3665 netif_wake_queue(netdev);
3666 ++adapter->restart_queue;
3667 }
661086df 3668#endif
9d5c8243
AK		 3669 }
3670
3671 if (tx_ring->detect_tx_hung) {
3672 /* Detect a transmit hang in hardware, this serializes the
3673 * check with the clearing of time_stamp and movement of i */
3674 tx_ring->detect_tx_hung = false;
3675 if (tx_ring->buffer_info[i].time_stamp &&
3676 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3677 (adapter->tx_timeout_factor * HZ))
3678 && !(rd32(E1000_STATUS) &
3679 E1000_STATUS_TXOFF)) {
3680
3681 tx_desc = E1000_TX_DESC(*tx_ring, i);
3682 /* detected Tx unit hang */
3683 dev_err(&adapter->pdev->dev,
3684 "Detected Tx Unit Hang\n"
2d064c06 3685 " Tx Queue <%d>\n"
9d5c8243
AK		 3686 " TDH <%x>\n"
3687 " TDT <%x>\n"
3688 " next_to_use <%x>\n"
3689 " next_to_clean <%x>\n"
3690 " head (WB) <%x>\n"
3691 "buffer_info[next_to_clean]\n"
3692 " time_stamp <%lx>\n"
3693 " jiffies <%lx>\n"
3694 " desc.status <%x>\n",
2d064c06 3695 tx_ring->queue_index,
9d5c8243
AK		 3696 readl(adapter->hw.hw_addr + tx_ring->head),
3697 readl(adapter->hw.hw_addr + tx_ring->tail),
3698 tx_ring->next_to_use,
3699 tx_ring->next_to_clean,
3700 head,
3701 tx_ring->buffer_info[i].time_stamp,
3702 jiffies,
3703 tx_desc->upper.fields.status);
661086df
PWJ		 3704#ifdef CONFIG_NETDEVICES_MULTIQUEUE
3705 netif_stop_subqueue(netdev, tx_ring->queue_index);
3706#else
9d5c8243 3707 netif_stop_queue(netdev);
661086df 3708#endif
9d5c8243
AK		 3709 }
3710 }
3711 tx_ring->total_bytes += total_bytes;
3712 tx_ring->total_packets += total_packets;
e21ed353
AD		 3713 tx_ring->tx_stats.bytes += total_bytes;
3714 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3715 adapter->net_stats.tx_bytes += total_bytes;
3716 adapter->net_stats.tx_packets += total_packets;
3717 return retval;
3718}
3719
3720
3721/**
3722 * igb_receive_skb - helper function to handle rx indications
3723 * @adapter: board private structure
3724 * @status: descriptor status field as written by hardware
3725 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3726 * @skb: pointer to sk_buff to be indicated to stack
3727 **/
6d8126f9 3728static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
9d5c8243
AK		 3729 struct sk_buff *skb)
3730{
3731 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3732 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
38b22195 3733 le16_to_cpu(vlan));
9d5c8243
AK		 3734 else
3735 netif_receive_skb(skb);
3736}
3737
3738
3739static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3740 u32 status_err, struct sk_buff *skb)
3741{
3742 skb->ip_summed = CHECKSUM_NONE;
3743
3744 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3745 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3746 return;
3747 /* TCP/UDP checksum error bit is set */
3748 if (status_err &
3749 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3750 /* let the stack verify checksum errors */
3751 adapter->hw_csum_err++;
3752 return;
3753 }
3754 /* It must be a TCP or UDP packet with a valid checksum */
3755 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3756 skb->ip_summed = CHECKSUM_UNNECESSARY;
3757
3758 adapter->hw_csum_good++;
3759}
3760
3b644cf6
MW		 3761static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3762 int *work_done, int budget)
9d5c8243 3763{
3b644cf6 3764 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3765 struct net_device *netdev = adapter->netdev;
3766 struct pci_dev *pdev = adapter->pdev;
3767 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3768 struct igb_buffer *buffer_info , *next_buffer;
3769 struct sk_buff *skb;
3770 unsigned int i, j;
3771 u32 length, hlen, staterr;
3772 bool cleaned = false;
3773 int cleaned_count = 0;
3774 unsigned int total_bytes = 0, total_packets = 0;
3775
3776 i = rx_ring->next_to_clean;
3777 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3778 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3779
3780 while (staterr & E1000_RXD_STAT_DD) {
3781 if (*work_done >= budget)
3782 break;
3783 (*work_done)++;
3784 buffer_info = &rx_ring->buffer_info[i];
3785
3786 /* HW will not DMA in data larger than the given buffer, even
3787 * if it parses the (NFS, of course) header to be larger. In
3788 * that case, it fills the header buffer and spills the rest
3789 * into the page.
3790 */
7deb07b1
AV		 3791 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3792 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3793 if (hlen > adapter->rx_ps_hdr_size)
3794 hlen = adapter->rx_ps_hdr_size;
3795
3796 length = le16_to_cpu(rx_desc->wb.upper.length);
3797 cleaned = true;
3798 cleaned_count++;
3799
3800 if (rx_ring->pending_skb != NULL) {
3801 skb = rx_ring->pending_skb;
3802 rx_ring->pending_skb = NULL;
3803 j = rx_ring->pending_skb_page;
3804 } else {
3805 skb = buffer_info->skb;
3806 prefetch(skb->data - NET_IP_ALIGN);
3807 buffer_info->skb = NULL;
3808 if (hlen) {
3809 pci_unmap_single(pdev, buffer_info->dma,
3810 adapter->rx_ps_hdr_size +
3811 NET_IP_ALIGN,
3812 PCI_DMA_FROMDEVICE);
3813 skb_put(skb, hlen);
3814 } else {
3815 pci_unmap_single(pdev, buffer_info->dma,
3816 adapter->rx_buffer_len +
3817 NET_IP_ALIGN,
3818 PCI_DMA_FROMDEVICE);
3819 skb_put(skb, length);
3820 goto send_up;
3821 }
3822 j = 0;
3823 }
3824
3825 while (length) {
3826 pci_unmap_page(pdev, buffer_info->page_dma,
3827 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3828 buffer_info->page_dma = 0;
3829 skb_fill_page_desc(skb, j, buffer_info->page,
3830 0, length);
3831 buffer_info->page = NULL;
3832
3833 skb->len += length;
3834 skb->data_len += length;
3835 skb->truesize += length;
3836 rx_desc->wb.upper.status_error = 0;
3837 if (staterr & E1000_RXD_STAT_EOP)
3838 break;
3839
3840 j++;
3841 cleaned_count++;
3842 i++;
3843 if (i == rx_ring->count)
3844 i = 0;
3845
3846 buffer_info = &rx_ring->buffer_info[i];
3847 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3848 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3849 length = le16_to_cpu(rx_desc->wb.upper.length);
3850 if (!(staterr & E1000_RXD_STAT_DD)) {
3851 rx_ring->pending_skb = skb;
3852 rx_ring->pending_skb_page = j;
3853 goto out;
3854 }
3855 }
3856send_up:
9d5c8243
AK		 3857 i++;
3858 if (i == rx_ring->count)
3859 i = 0;
3860 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3861 prefetch(next_rxd);
3862 next_buffer = &rx_ring->buffer_info[i];
3863
3864 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3865 dev_kfree_skb_irq(skb);
3866 goto next_desc;
3867 }
3868 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3869
3870 total_bytes += skb->len;
3871 total_packets++;
3872
3873 igb_rx_checksum_adv(adapter, staterr, skb);
3874
3875 skb->protocol = eth_type_trans(skb, netdev);
3876
3877 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3878
3879 netdev->last_rx = jiffies;
3880
3881next_desc:
3882 rx_desc->wb.upper.status_error = 0;
3883
3884 /* return some buffers to hardware, one at a time is too slow */
3885 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3886 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3887 cleaned_count = 0;
3888 }
3889
3890 /* use prefetched values */
3891 rx_desc = next_rxd;
3892 buffer_info = next_buffer;
3893
3894 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3895 }
3896out:
3897 rx_ring->next_to_clean = i;
3898 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3899
3900 if (cleaned_count)
3b644cf6 3901 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3902
3903 rx_ring->total_packets += total_packets;
3904 rx_ring->total_bytes += total_bytes;
3905 rx_ring->rx_stats.packets += total_packets;
3906 rx_ring->rx_stats.bytes += total_bytes;
3907 adapter->net_stats.rx_bytes += total_bytes;
3908 adapter->net_stats.rx_packets += total_packets;
3909 return cleaned;
3910}
3911
3912
3913/**
3914 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3915 * @adapter: address of board private structure
3916 **/
3b644cf6 3917static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3918 int cleaned_count)
3919{
3b644cf6 3920 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3921 struct net_device *netdev = adapter->netdev;
3922 struct pci_dev *pdev = adapter->pdev;
3923 union e1000_adv_rx_desc *rx_desc;
3924 struct igb_buffer *buffer_info;
3925 struct sk_buff *skb;
3926 unsigned int i;
3927
3928 i = rx_ring->next_to_use;
3929 buffer_info = &rx_ring->buffer_info[i];
3930
3931 while (cleaned_count--) {
3932 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3933
3934 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3935 buffer_info->page = alloc_page(GFP_ATOMIC);
3936 if (!buffer_info->page) {
3937 adapter->alloc_rx_buff_failed++;
3938 goto no_buffers;
3939 }
3940 buffer_info->page_dma =
3941 pci_map_page(pdev,
3942 buffer_info->page,
3943 0, PAGE_SIZE,
3944 PCI_DMA_FROMDEVICE);
3945 }
3946
3947 if (!buffer_info->skb) {
3948 int bufsz;
3949
3950 if (adapter->rx_ps_hdr_size)
3951 bufsz = adapter->rx_ps_hdr_size;
3952 else
3953 bufsz = adapter->rx_buffer_len;
3954 bufsz += NET_IP_ALIGN;
3955 skb = netdev_alloc_skb(netdev, bufsz);
3956
3957 if (!skb) {
3958 adapter->alloc_rx_buff_failed++;
3959 goto no_buffers;
3960 }
3961
3962 /* Make buffer alignment 2 beyond a 16 byte boundary
3963 * this will result in a 16 byte aligned IP header after
3964 * the 14 byte MAC header is removed
3965 */
3966 skb_reserve(skb, NET_IP_ALIGN);
3967
3968 buffer_info->skb = skb;
3969 buffer_info->dma = pci_map_single(pdev, skb->data,
3970 bufsz,
3971 PCI_DMA_FROMDEVICE);
3972
3973 }
3974 /* Refresh the desc even if buffer_addrs didn't change because
3975 * each write-back erases this info. */
3976 if (adapter->rx_ps_hdr_size) {
3977 rx_desc->read.pkt_addr =
3978 cpu_to_le64(buffer_info->page_dma);
3979 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3980 } else {
3981 rx_desc->read.pkt_addr =
3982 cpu_to_le64(buffer_info->dma);
3983 rx_desc->read.hdr_addr = 0;
3984 }
3985
3986 i++;
3987 if (i == rx_ring->count)
3988 i = 0;
3989 buffer_info = &rx_ring->buffer_info[i];
3990 }
3991
3992no_buffers:
3993 if (rx_ring->next_to_use != i) {
3994 rx_ring->next_to_use = i;
3995 if (i == 0)
3996 i = (rx_ring->count - 1);
3997 else
3998 i--;
3999
4000 /* Force memory writes to complete before letting h/w
4001 * know there are new descriptors to fetch. (Only
4002 * applicable for weak-ordered memory model archs,
4003 * such as IA-64). */
4004 wmb();
4005 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4006 }
4007}
4008
4009/**
4010 * igb_mii_ioctl -
4011 * @netdev:
4012 * @ifreq:
4013 * @cmd:
4014 **/
4015static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4016{
4017 struct igb_adapter *adapter = netdev_priv(netdev);
4018 struct mii_ioctl_data *data = if_mii(ifr);
4019
4020 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4021 return -EOPNOTSUPP;
4022
4023 switch (cmd) {
4024 case SIOCGMIIPHY:
4025 data->phy_id = adapter->hw.phy.addr;
4026 break;
4027 case SIOCGMIIREG:
4028 if (!capable(CAP_NET_ADMIN))
4029 return -EPERM;
4030 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
4031 data->reg_num
4032 & 0x1F, &data->val_out))
4033 return -EIO;
4034 break;
4035 case SIOCSMIIREG:
4036 default:
4037 return -EOPNOTSUPP;
4038 }
4039 return 0;
4040}
4041
4042/**
4043 * igb_ioctl -
4044 * @netdev:
4045 * @ifreq:
4046 * @cmd:
4047 **/
4048static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4049{
4050 switch (cmd) {
4051 case SIOCGMIIPHY:
4052 case SIOCGMIIREG:
4053 case SIOCSMIIREG:
4054 return igb_mii_ioctl(netdev, ifr, cmd);
4055 default:
4056 return -EOPNOTSUPP;
4057 }
4058}
4059
4060static void igb_vlan_rx_register(struct net_device *netdev,
4061 struct vlan_group *grp)
4062{
4063 struct igb_adapter *adapter = netdev_priv(netdev);
4064 struct e1000_hw *hw = &adapter->hw;
4065 u32 ctrl, rctl;
4066
4067 igb_irq_disable(adapter);
4068 adapter->vlgrp = grp;
4069
4070 if (grp) {
4071 /* enable VLAN tag insert/strip */
4072 ctrl = rd32(E1000_CTRL);
4073 ctrl |= E1000_CTRL_VME;
4074 wr32(E1000_CTRL, ctrl);
4075
4076 /* enable VLAN receive filtering */
4077 rctl = rd32(E1000_RCTL);
4078 rctl |= E1000_RCTL_VFE;
4079 rctl &= ~E1000_RCTL_CFIEN;
4080 wr32(E1000_RCTL, rctl);
4081 igb_update_mng_vlan(adapter);
4082 wr32(E1000_RLPML,
4083 adapter->max_frame_size + VLAN_TAG_SIZE);
4084 } else {
4085 /* disable VLAN tag insert/strip */
4086 ctrl = rd32(E1000_CTRL);
4087 ctrl &= ~E1000_CTRL_VME;
4088 wr32(E1000_CTRL, ctrl);
4089
4090 /* disable VLAN filtering */
4091 rctl = rd32(E1000_RCTL);
4092 rctl &= ~E1000_RCTL_VFE;
4093 wr32(E1000_RCTL, rctl);
4094 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4095 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4096 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4097 }
4098 wr32(E1000_RLPML,
4099 adapter->max_frame_size);
4100 }
4101
4102 if (!test_bit(__IGB_DOWN, &adapter->state))
4103 igb_irq_enable(adapter);
4104}
4105
4106static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4107{
4108 struct igb_adapter *adapter = netdev_priv(netdev);
4109 struct e1000_hw *hw = &adapter->hw;
4110 u32 vfta, index;
4111
4112 if ((adapter->hw.mng_cookie.status &
4113 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4114 (vid == adapter->mng_vlan_id))
4115 return;
4116 /* add VID to filter table */
4117 index = (vid >> 5) & 0x7F;
4118 vfta = array_rd32(E1000_VFTA, index);
4119 vfta |= (1 << (vid & 0x1F));
4120 igb_write_vfta(&adapter->hw, index, vfta);
4121}
4122
4123static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4124{
4125 struct igb_adapter *adapter = netdev_priv(netdev);
4126 struct e1000_hw *hw = &adapter->hw;
4127 u32 vfta, index;
4128
4129 igb_irq_disable(adapter);
4130 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4131
4132 if (!test_bit(__IGB_DOWN, &adapter->state))
4133 igb_irq_enable(adapter);
4134
4135 if ((adapter->hw.mng_cookie.status &
4136 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4137 (vid == adapter->mng_vlan_id)) {
4138 /* release control to f/w */
4139 igb_release_hw_control(adapter);
4140 return;
4141 }
4142
4143 /* remove VID from filter table */
4144 index = (vid >> 5) & 0x7F;
4145 vfta = array_rd32(E1000_VFTA, index);
4146 vfta &= ~(1 << (vid & 0x1F));
4147 igb_write_vfta(&adapter->hw, index, vfta);
4148}
4149
4150static void igb_restore_vlan(struct igb_adapter *adapter)
4151{
4152 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4153
4154 if (adapter->vlgrp) {
4155 u16 vid;
4156 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4157 if (!vlan_group_get_device(adapter->vlgrp, vid))
4158 continue;
4159 igb_vlan_rx_add_vid(adapter->netdev, vid);
4160 }
4161 }
4162}
4163
4164int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4165{
4166 struct e1000_mac_info *mac = &adapter->hw.mac;
4167
4168 mac->autoneg = 0;
4169
4170 /* Fiber NICs only allow 1000 gbps Full duplex */
4171 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4172 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4173 dev_err(&adapter->pdev->dev,
4174 "Unsupported Speed/Duplex configuration\n");
4175 return -EINVAL;
4176 }
4177
4178 switch (spddplx) {
4179 case SPEED_10 + DUPLEX_HALF:
4180 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4181 break;
4182 case SPEED_10 + DUPLEX_FULL:
4183 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4184 break;
4185 case SPEED_100 + DUPLEX_HALF:
4186 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4187 break;
4188 case SPEED_100 + DUPLEX_FULL:
4189 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4190 break;
4191 case SPEED_1000 + DUPLEX_FULL:
4192 mac->autoneg = 1;
4193 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4194 break;
4195 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4196 default:
4197 dev_err(&adapter->pdev->dev,
4198 "Unsupported Speed/Duplex configuration\n");
4199 return -EINVAL;
4200 }
4201 return 0;
4202}
4203
4204
4205static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4206{
4207 struct net_device *netdev = pci_get_drvdata(pdev);
4208 struct igb_adapter *adapter = netdev_priv(netdev);
4209 struct e1000_hw *hw = &adapter->hw;
2d064c06 4210 u32 ctrl, rctl, status;
9d5c8243
AK		 4211 u32 wufc = adapter->wol;
4212#ifdef CONFIG_PM
4213 int retval = 0;
4214#endif
4215
4216 netif_device_detach(netdev);
4217
4218 if (netif_running(netdev)) {
4219 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4220 igb_down(adapter);
4221 igb_free_irq(adapter);
4222 }
4223
4224#ifdef CONFIG_PM
4225 retval = pci_save_state(pdev);
4226 if (retval)
4227 return retval;
4228#endif
4229
4230 status = rd32(E1000_STATUS);
4231 if (status & E1000_STATUS_LU)
4232 wufc &= ~E1000_WUFC_LNKC;
4233
4234 if (wufc) {
4235 igb_setup_rctl(adapter);
4236 igb_set_multi(netdev);
4237
4238 /* turn on all-multi mode if wake on multicast is enabled */
4239 if (wufc & E1000_WUFC_MC) {
4240 rctl = rd32(E1000_RCTL);
4241 rctl |= E1000_RCTL_MPE;
4242 wr32(E1000_RCTL, rctl);
4243 }
4244
4245 ctrl = rd32(E1000_CTRL);
4246 /* advertise wake from D3Cold */
4247 #define E1000_CTRL_ADVD3WUC 0x00100000
4248 /* phy power management enable */
4249 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4250 ctrl |= E1000_CTRL_ADVD3WUC;
4251 wr32(E1000_CTRL, ctrl);
4252
9d5c8243
AK		 4253 /* Allow time for pending master requests to run */
4254 igb_disable_pcie_master(&adapter->hw);
4255
4256 wr32(E1000_WUC, E1000_WUC_PME_EN);
4257 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4258 } else {
4259 wr32(E1000_WUC, 0);
4260 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4261 }
4262
2d064c06
AD		 4263 /* make sure adapter isn't asleep if manageability/wol is enabled */
4264 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4265 pci_enable_wake(pdev, PCI_D3hot, 1);
4266 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4267 } else {
4268 igb_shutdown_fiber_serdes_link_82575(hw);
4269 pci_enable_wake(pdev, PCI_D3hot, 0);
4270 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4271 }
4272
4273 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4274 * would have already happened in close and is redundant. */
4275 igb_release_hw_control(adapter);
4276
4277 pci_disable_device(pdev);
4278
4279 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4280
4281 return 0;
4282}
4283
4284#ifdef CONFIG_PM
4285static int igb_resume(struct pci_dev *pdev)
4286{
4287 struct net_device *netdev = pci_get_drvdata(pdev);
4288 struct igb_adapter *adapter = netdev_priv(netdev);
4289 struct e1000_hw *hw = &adapter->hw;
4290 u32 err;
4291
4292 pci_set_power_state(pdev, PCI_D0);
4293 pci_restore_state(pdev);
42bfd33a
TI		 4294
4295 if (adapter->need_ioport)
4296 err = pci_enable_device(pdev);
4297 else
4298 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4299 if (err) {
4300 dev_err(&pdev->dev,
4301 "igb: Cannot enable PCI device from suspend\n");
4302 return err;
4303 }
4304 pci_set_master(pdev);
4305
4306 pci_enable_wake(pdev, PCI_D3hot, 0);
4307 pci_enable_wake(pdev, PCI_D3cold, 0);
4308
4309 if (netif_running(netdev)) {
4310 err = igb_request_irq(adapter);
4311 if (err)
4312 return err;
4313 }
4314
4315 /* e1000_power_up_phy(adapter); */
4316
4317 igb_reset(adapter);
4318 wr32(E1000_WUS, ~0);
4319
4320 igb_init_manageability(adapter);
4321
4322 if (netif_running(netdev))
4323 igb_up(adapter);
4324
4325 netif_device_attach(netdev);
4326
4327 /* let the f/w know that the h/w is now under the control of the
4328 * driver. */
4329 igb_get_hw_control(adapter);
4330
4331 return 0;
4332}
4333#endif
4334
4335static void igb_shutdown(struct pci_dev *pdev)
4336{
4337 igb_suspend(pdev, PMSG_SUSPEND);
4338}
4339
4340#ifdef CONFIG_NET_POLL_CONTROLLER
4341/*
4342 * Polling 'interrupt' - used by things like netconsole to send skbs
4343 * without having to re-enable interrupts. It's not called while
4344 * the interrupt routine is executing.
4345 */
4346static void igb_netpoll(struct net_device *netdev)
4347{
4348 struct igb_adapter *adapter = netdev_priv(netdev);
4349 int i;
4350 int work_done = 0;
4351
4352 igb_irq_disable(adapter);
4353 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4354 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4355
4356 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4357 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4358 &work_done,
4359 adapter->rx_ring[i].napi.weight);
4360
4361 igb_irq_enable(adapter);
4362}
4363#endif /* CONFIG_NET_POLL_CONTROLLER */
4364
4365/**
4366 * igb_io_error_detected - called when PCI error is detected
4367 * @pdev: Pointer to PCI device
4368 * @state: The current pci connection state
4369 *
4370 * This function is called after a PCI bus error affecting
4371 * this device has been detected.
4372 */
4373static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4374 pci_channel_state_t state)
4375{
4376 struct net_device *netdev = pci_get_drvdata(pdev);
4377 struct igb_adapter *adapter = netdev_priv(netdev);
4378
4379 netif_device_detach(netdev);
4380
4381 if (netif_running(netdev))
4382 igb_down(adapter);
4383 pci_disable_device(pdev);
4384
4385 /* Request a slot slot reset. */
4386 return PCI_ERS_RESULT_NEED_RESET;
4387}
4388
4389/**
4390 * igb_io_slot_reset - called after the pci bus has been reset.
4391 * @pdev: Pointer to PCI device
4392 *
4393 * Restart the card from scratch, as if from a cold-boot. Implementation
4394 * resembles the first-half of the igb_resume routine.
4395 */
4396static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4397{
4398 struct net_device *netdev = pci_get_drvdata(pdev);
4399 struct igb_adapter *adapter = netdev_priv(netdev);
4400 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4401 int err;
9d5c8243 4402
42bfd33a
TI		 4403 if (adapter->need_ioport)
4404 err = pci_enable_device(pdev);
4405 else
4406 err = pci_enable_device_mem(pdev);
4407 if (err) {
9d5c8243
AK		 4408 dev_err(&pdev->dev,
4409 "Cannot re-enable PCI device after reset.\n");
4410 return PCI_ERS_RESULT_DISCONNECT;
4411 }
4412 pci_set_master(pdev);
c682fc23 4413 pci_restore_state(pdev);
9d5c8243
AK		 4414
4415 pci_enable_wake(pdev, PCI_D3hot, 0);
4416 pci_enable_wake(pdev, PCI_D3cold, 0);
4417
4418 igb_reset(adapter);
4419 wr32(E1000_WUS, ~0);
4420
4421 return PCI_ERS_RESULT_RECOVERED;
4422}
4423
4424/**
4425 * igb_io_resume - called when traffic can start flowing again.
4426 * @pdev: Pointer to PCI device
4427 *
4428 * This callback is called when the error recovery driver tells us that
4429 * its OK to resume normal operation. Implementation resembles the
4430 * second-half of the igb_resume routine.
4431 */
4432static void igb_io_resume(struct pci_dev *pdev)
4433{
4434 struct net_device *netdev = pci_get_drvdata(pdev);
4435 struct igb_adapter *adapter = netdev_priv(netdev);
4436
4437 igb_init_manageability(adapter);
4438
4439 if (netif_running(netdev)) {
4440 if (igb_up(adapter)) {
4441 dev_err(&pdev->dev, "igb_up failed after reset\n");
4442 return;
4443 }
4444 }
4445
4446 netif_device_attach(netdev);
4447
4448 /* let the f/w know that the h/w is now under the control of the
4449 * driver. */
4450 igb_get_hw_control(adapter);
4451
4452}
4453
4454/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)