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1d3bb996 DG |
1 | /* |
2 | * drivers/net/ibm_newemac/core.h | |
3 | * | |
4 | * Driver for PowerPC 4xx on-chip ethernet controller. | |
5 | * | |
17cf803a BH |
6 | * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. |
7 | * <benh@kernel.crashing.org> | |
8 | * | |
9 | * Based on the arch/ppc version of the driver: | |
10 | * | |
1d3bb996 DG |
11 | * Copyright (c) 2004, 2005 Zultys Technologies. |
12 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> | |
13 | * | |
14 | * Based on original work by | |
15 | * Armin Kuster <akuster@mvista.com> | |
16 | * Johnnie Peters <jpeters@mvista.com> | |
17 | * Copyright 2000, 2001 MontaVista Softare Inc. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | */ | |
25 | #ifndef __IBM_NEWEMAC_CORE_H | |
26 | #define __IBM_NEWEMAC_CORE_H | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/spinlock.h> | |
55b6c8e9 | 36 | #include <linux/of_platform.h> |
1d3bb996 | 37 | |
1d3bb996 DG |
38 | #include <asm/io.h> |
39 | #include <asm/dcr.h> | |
40 | ||
41 | #include "emac.h" | |
42 | #include "phy.h" | |
43 | #include "zmii.h" | |
44 | #include "rgmii.h" | |
45 | #include "mal.h" | |
46 | #include "tah.h" | |
47 | #include "debug.h" | |
48 | ||
49 | #define NUM_TX_BUFF CONFIG_IBM_NEW_EMAC_TXB | |
50 | #define NUM_RX_BUFF CONFIG_IBM_NEW_EMAC_RXB | |
51 | ||
52 | /* Simple sanity check */ | |
53 | #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256 | |
54 | #error Invalid number of buffer descriptors (greater than 256) | |
55 | #endif | |
56 | ||
57 | #define EMAC_MIN_MTU 46 | |
58 | ||
59 | /* Maximum L2 header length (VLAN tagged, no FCS) */ | |
60 | #define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4) | |
61 | ||
62 | /* RX BD size for the given MTU */ | |
63 | static inline int emac_rx_size(int mtu) | |
64 | { | |
65 | if (mtu > ETH_DATA_LEN) | |
66 | return MAL_MAX_RX_SIZE; | |
67 | else | |
68 | return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD); | |
69 | } | |
70 | ||
71 | #define EMAC_DMA_ALIGN(x) ALIGN((x), dma_get_cache_alignment()) | |
72 | ||
73 | #define EMAC_RX_SKB_HEADROOM \ | |
74 | EMAC_DMA_ALIGN(CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM) | |
75 | ||
76 | /* Size of RX skb for the given MTU */ | |
77 | static inline int emac_rx_skb_size(int mtu) | |
78 | { | |
79 | int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu)); | |
80 | return EMAC_DMA_ALIGN(size + 2) + EMAC_RX_SKB_HEADROOM; | |
81 | } | |
82 | ||
83 | /* RX DMA sync size */ | |
84 | static inline int emac_rx_sync_size(int mtu) | |
85 | { | |
86 | return EMAC_DMA_ALIGN(emac_rx_size(mtu) + 2); | |
87 | } | |
88 | ||
89 | /* Driver statistcs is split into two parts to make it more cache friendly: | |
90 | * - normal statistics (packet count, etc) | |
91 | * - error statistics | |
92 | * | |
93 | * When statistics is requested by ethtool, these parts are concatenated, | |
94 | * normal one goes first. | |
95 | * | |
96 | * Please, keep these structures in sync with emac_stats_keys. | |
97 | */ | |
98 | ||
99 | /* Normal TX/RX Statistics */ | |
100 | struct emac_stats { | |
101 | u64 rx_packets; | |
102 | u64 rx_bytes; | |
103 | u64 tx_packets; | |
104 | u64 tx_bytes; | |
105 | u64 rx_packets_csum; | |
106 | u64 tx_packets_csum; | |
107 | }; | |
108 | ||
109 | /* Error statistics */ | |
110 | struct emac_error_stats { | |
111 | u64 tx_undo; | |
112 | ||
113 | /* Software RX Errors */ | |
114 | u64 rx_dropped_stack; | |
115 | u64 rx_dropped_oom; | |
116 | u64 rx_dropped_error; | |
117 | u64 rx_dropped_resize; | |
118 | u64 rx_dropped_mtu; | |
119 | u64 rx_stopped; | |
120 | /* BD reported RX errors */ | |
121 | u64 rx_bd_errors; | |
122 | u64 rx_bd_overrun; | |
123 | u64 rx_bd_bad_packet; | |
124 | u64 rx_bd_runt_packet; | |
125 | u64 rx_bd_short_event; | |
126 | u64 rx_bd_alignment_error; | |
127 | u64 rx_bd_bad_fcs; | |
128 | u64 rx_bd_packet_too_long; | |
129 | u64 rx_bd_out_of_range; | |
130 | u64 rx_bd_in_range; | |
131 | /* EMAC IRQ reported RX errors */ | |
132 | u64 rx_parity; | |
133 | u64 rx_fifo_overrun; | |
134 | u64 rx_overrun; | |
135 | u64 rx_bad_packet; | |
136 | u64 rx_runt_packet; | |
137 | u64 rx_short_event; | |
138 | u64 rx_alignment_error; | |
139 | u64 rx_bad_fcs; | |
140 | u64 rx_packet_too_long; | |
141 | u64 rx_out_of_range; | |
142 | u64 rx_in_range; | |
143 | ||
144 | /* Software TX Errors */ | |
145 | u64 tx_dropped; | |
146 | /* BD reported TX errors */ | |
147 | u64 tx_bd_errors; | |
148 | u64 tx_bd_bad_fcs; | |
149 | u64 tx_bd_carrier_loss; | |
150 | u64 tx_bd_excessive_deferral; | |
151 | u64 tx_bd_excessive_collisions; | |
152 | u64 tx_bd_late_collision; | |
153 | u64 tx_bd_multple_collisions; | |
154 | u64 tx_bd_single_collision; | |
155 | u64 tx_bd_underrun; | |
156 | u64 tx_bd_sqe; | |
157 | /* EMAC IRQ reported TX errors */ | |
158 | u64 tx_parity; | |
159 | u64 tx_underrun; | |
160 | u64 tx_sqe; | |
161 | u64 tx_errors; | |
162 | }; | |
163 | ||
164 | #define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \ | |
165 | sizeof(struct emac_error_stats)) \ | |
166 | / sizeof(u64)) | |
167 | ||
168 | struct emac_instance { | |
169 | struct net_device *ndev; | |
170 | struct resource rsrc_regs; | |
171 | struct emac_regs __iomem *emacp; | |
172 | struct of_device *ofdev; | |
173 | struct device_node **blist; /* bootlist entry */ | |
174 | ||
175 | /* MAL linkage */ | |
176 | u32 mal_ph; | |
177 | struct of_device *mal_dev; | |
178 | u32 mal_rx_chan; | |
179 | u32 mal_tx_chan; | |
180 | struct mal_instance *mal; | |
181 | struct mal_commac commac; | |
182 | ||
183 | /* PHY infos */ | |
184 | u32 phy_mode; | |
185 | u32 phy_map; | |
186 | u32 phy_address; | |
187 | u32 phy_feat_exc; | |
188 | struct mii_phy phy; | |
189 | struct mutex link_lock; | |
190 | struct delayed_work link_work; | |
191 | int link_polling; | |
192 | ||
9e3cb294 VG |
193 | /* GPCS PHY infos */ |
194 | u32 gpcs_address; | |
195 | ||
1d3bb996 DG |
196 | /* Shared MDIO if any */ |
197 | u32 mdio_ph; | |
198 | struct of_device *mdio_dev; | |
199 | struct emac_instance *mdio_instance; | |
200 | struct mutex mdio_lock; | |
201 | ||
202 | /* ZMII infos if any */ | |
203 | u32 zmii_ph; | |
204 | u32 zmii_port; | |
205 | struct of_device *zmii_dev; | |
206 | ||
207 | /* RGMII infos if any */ | |
208 | u32 rgmii_ph; | |
209 | u32 rgmii_port; | |
210 | struct of_device *rgmii_dev; | |
211 | ||
212 | /* TAH infos if any */ | |
213 | u32 tah_ph; | |
214 | u32 tah_port; | |
215 | struct of_device *tah_dev; | |
216 | ||
217 | /* IRQs */ | |
218 | int wol_irq; | |
219 | int emac_irq; | |
220 | ||
221 | /* OPB bus frequency in Mhz */ | |
222 | u32 opb_bus_freq; | |
223 | ||
224 | /* Cell index within an ASIC (for clk mgmnt) */ | |
225 | u32 cell_index; | |
226 | ||
227 | /* Max supported MTU */ | |
228 | u32 max_mtu; | |
229 | ||
230 | /* Feature bits (from probe table) */ | |
231 | unsigned int features; | |
232 | ||
233 | /* Tx and Rx fifo sizes & other infos in bytes */ | |
234 | u32 tx_fifo_size; | |
235 | u32 tx_fifo_size_gige; | |
236 | u32 rx_fifo_size; | |
237 | u32 rx_fifo_size_gige; | |
238 | u32 fifo_entry_size; | |
239 | u32 mal_burst_size; /* move to MAL ? */ | |
240 | ||
05781ccd GE |
241 | /* IAHT and GAHT filter parameterization */ |
242 | u32 xaht_slots_shift; | |
243 | u32 xaht_width_shift; | |
244 | ||
1d3bb996 DG |
245 | /* Descriptor management |
246 | */ | |
247 | struct mal_descriptor *tx_desc; | |
248 | int tx_cnt; | |
249 | int tx_slot; | |
250 | int ack_slot; | |
251 | ||
252 | struct mal_descriptor *rx_desc; | |
253 | int rx_slot; | |
254 | struct sk_buff *rx_sg_skb; /* 1 */ | |
255 | int rx_skb_size; | |
256 | int rx_sync_size; | |
257 | ||
258 | struct sk_buff *tx_skb[NUM_TX_BUFF]; | |
259 | struct sk_buff *rx_skb[NUM_RX_BUFF]; | |
260 | ||
261 | /* Stats | |
262 | */ | |
263 | struct emac_error_stats estats; | |
264 | struct net_device_stats nstats; | |
265 | struct emac_stats stats; | |
266 | ||
267 | /* Misc | |
268 | */ | |
269 | int reset_failed; | |
270 | int stop_timeout; /* in us */ | |
271 | int no_mcast; | |
272 | int mcast_pending; | |
61dbcece | 273 | int opened; |
1d3bb996 DG |
274 | struct work_struct reset_work; |
275 | spinlock_t lock; | |
276 | }; | |
277 | ||
278 | /* | |
279 | * Features of various EMAC implementations | |
280 | */ | |
281 | ||
282 | /* | |
283 | * No flow control on 40x according to the original driver | |
284 | */ | |
285 | #define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001 | |
286 | /* | |
287 | * Cell is an EMAC4 | |
288 | */ | |
289 | #define EMAC_FTR_EMAC4 0x00000002 | |
290 | /* | |
291 | * For the 440SPe, AMCC inexplicably changed the polarity of | |
292 | * the "operation complete" bit in the MII control register. | |
293 | */ | |
294 | #define EMAC_FTR_STACR_OC_INVERT 0x00000004 | |
295 | /* | |
296 | * Set if we have a TAH. | |
297 | */ | |
298 | #define EMAC_FTR_HAS_TAH 0x00000008 | |
299 | /* | |
300 | * Set if we have a ZMII. | |
301 | */ | |
302 | #define EMAC_FTR_HAS_ZMII 0x00000010 | |
303 | /* | |
304 | * Set if we have a RGMII. | |
305 | */ | |
306 | #define EMAC_FTR_HAS_RGMII 0x00000020 | |
307 | /* | |
bff713b5 | 308 | * Set if we have new type STACR with STAOPC |
1d3bb996 | 309 | */ |
bff713b5 | 310 | #define EMAC_FTR_HAS_NEW_STACR 0x00000040 |
0925ab5d VB |
311 | /* |
312 | * Set if we need phy clock workaround for 440gx | |
313 | */ | |
314 | #define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080 | |
11121e30 VB |
315 | /* |
316 | * Set if we need phy clock workaround for 440ep or 440gr | |
317 | */ | |
318 | #define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100 | |
05781ccd GE |
319 | /* |
320 | * The 405EX and 460EX contain the EMAC4SYNC core | |
321 | */ | |
322 | #define EMAC_FTR_EMAC4SYNC 0x00000200 | |
9e3cb294 VG |
323 | /* |
324 | * Set if we need phy clock workaround for 460ex or 460gt | |
325 | */ | |
326 | #define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400 | |
1d3bb996 DG |
327 | |
328 | ||
329 | /* Right now, we don't quite handle the always/possible masks on the | |
330 | * most optimal way as we don't have a way to say something like | |
331 | * always EMAC4. Patches welcome. | |
332 | */ | |
333 | enum { | |
334 | EMAC_FTRS_ALWAYS = 0, | |
335 | ||
336 | EMAC_FTRS_POSSIBLE = | |
337 | #ifdef CONFIG_IBM_NEW_EMAC_EMAC4 | |
05781ccd GE |
338 | EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC | |
339 | EMAC_FTR_HAS_NEW_STACR | | |
0925ab5d | 340 | EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX | |
1d3bb996 DG |
341 | #endif |
342 | #ifdef CONFIG_IBM_NEW_EMAC_TAH | |
343 | EMAC_FTR_HAS_TAH | | |
344 | #endif | |
345 | #ifdef CONFIG_IBM_NEW_EMAC_ZMII | |
346 | EMAC_FTR_HAS_ZMII | | |
347 | #endif | |
348 | #ifdef CONFIG_IBM_NEW_EMAC_RGMII | |
349 | EMAC_FTR_HAS_RGMII | | |
b68d185a JB |
350 | #endif |
351 | #ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL | |
352 | EMAC_FTR_NO_FLOW_CONTROL_40x | | |
1d3bb996 | 353 | #endif |
9e3cb294 | 354 | EMAC_FTR_460EX_PHY_CLK_FIX | |
11121e30 | 355 | EMAC_FTR_440EP_PHY_CLK_FIX, |
1d3bb996 DG |
356 | }; |
357 | ||
358 | static inline int emac_has_feature(struct emac_instance *dev, | |
359 | unsigned long feature) | |
360 | { | |
361 | return (EMAC_FTRS_ALWAYS & feature) || | |
362 | (EMAC_FTRS_POSSIBLE & dev->features & feature); | |
363 | } | |
364 | ||
05781ccd GE |
365 | /* |
366 | * Various instances of the EMAC core have varying 1) number of | |
367 | * address match slots, 2) width of the registers for handling address | |
368 | * match slots, 3) number of registers for handling address match | |
369 | * slots and 4) base offset for those registers. | |
370 | * | |
371 | * These macros and inlines handle these differences based on | |
372 | * parameters supplied by the device structure which are, in turn, | |
373 | * initialized based on the "compatible" entry in the device tree. | |
374 | */ | |
375 | ||
376 | #define EMAC4_XAHT_SLOTS_SHIFT 6 | |
377 | #define EMAC4_XAHT_WIDTH_SHIFT 4 | |
378 | ||
379 | #define EMAC4SYNC_XAHT_SLOTS_SHIFT 8 | |
380 | #define EMAC4SYNC_XAHT_WIDTH_SHIFT 5 | |
381 | ||
382 | #define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift) | |
383 | #define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift) | |
384 | #define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \ | |
385 | (dev)->xaht_width_shift)) | |
386 | ||
387 | #define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \ | |
388 | ((EMAC_XAHT_SLOTS(dev) - 1) - \ | |
389 | ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \ | |
390 | (dev)->xaht_slots_shift))) | |
391 | ||
392 | #define EMAC_XAHT_SLOT_TO_REG(dev, slot) \ | |
393 | ((slot) >> (dev)->xaht_width_shift) | |
394 | ||
395 | #define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \ | |
396 | ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \ | |
397 | ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1))) | |
398 | ||
399 | static inline u32 *emac_xaht_base(struct emac_instance *dev) | |
400 | { | |
401 | struct emac_regs __iomem *p = dev->emacp; | |
402 | int offset; | |
403 | ||
404 | /* The first IAHT entry always is the base of the block of | |
405 | * IAHT and GAHT registers. | |
406 | */ | |
407 | if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) | |
408 | offset = offsetof(struct emac_regs, u1.emac4sync.iaht1); | |
409 | else | |
410 | offset = offsetof(struct emac_regs, u0.emac4.iaht1); | |
411 | ||
412 | return ((u32 *)((ptrdiff_t)p + offset)); | |
413 | } | |
414 | ||
415 | static inline u32 *emac_gaht_base(struct emac_instance *dev) | |
416 | { | |
417 | /* GAHT registers always come after an identical number of | |
418 | * IAHT registers. | |
419 | */ | |
420 | return (emac_xaht_base(dev) + EMAC_XAHT_REGS(dev)); | |
421 | } | |
422 | ||
423 | static inline u32 *emac_iaht_base(struct emac_instance *dev) | |
424 | { | |
425 | /* IAHT registers always come before an identical number of | |
426 | * GAHT registers. | |
427 | */ | |
428 | return (emac_xaht_base(dev)); | |
429 | } | |
1d3bb996 DG |
430 | |
431 | /* Ethtool get_regs complex data. | |
432 | * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH | |
433 | * when available. | |
434 | * | |
435 | * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, | |
436 | * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. | |
437 | * Each register component is preceded with emac_ethtool_regs_subhdr. | |
438 | * Order of the optional headers follows their relative bit posititions | |
439 | * in emac_ethtool_regs_hdr.components | |
440 | */ | |
441 | #define EMAC_ETHTOOL_REGS_ZMII 0x00000001 | |
442 | #define EMAC_ETHTOOL_REGS_RGMII 0x00000002 | |
443 | #define EMAC_ETHTOOL_REGS_TAH 0x00000004 | |
444 | ||
445 | struct emac_ethtool_regs_hdr { | |
446 | u32 components; | |
447 | }; | |
448 | ||
449 | struct emac_ethtool_regs_subhdr { | |
450 | u32 version; | |
451 | u32 index; | |
452 | }; | |
453 | ||
05781ccd GE |
454 | #define EMAC_ETHTOOL_REGS_VER 0 |
455 | #define EMAC_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ | |
456 | (dev)->rsrc_regs.start + 1) | |
457 | #define EMAC4_ETHTOOL_REGS_VER 1 | |
458 | #define EMAC4_ETHTOOL_REGS_SIZE(dev) ((dev)->rsrc_regs.end - \ | |
459 | (dev)->rsrc_regs.start + 1) | |
460 | ||
1d3bb996 | 461 | #endif /* __IBM_NEWEMAC_CORE_H */ |