Commit | Line | Data |
---|---|---|
0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.h |
3 | * | |
4 | * Gianfar Ethernet Driver | |
5 | * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 | |
6 | * Based on 8260_io/fcc_enet.c | |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
1da177e4 LT |
10 | * |
11 | * Copyright (c) 2002-2004 Freescale Semiconductor, Inc. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | * | |
18 | * Still left to do: | |
19 | * -Add support for module parameters | |
1da177e4 LT |
20 | * -Add patch for ethtool phys id |
21 | */ | |
22 | #ifndef __GIANFAR_H | |
23 | #define __GIANFAR_H | |
24 | ||
1da177e4 LT |
25 | #include <linux/kernel.h> |
26 | #include <linux/sched.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/mm.h> | |
bb40dcbb AF |
38 | #include <linux/mii.h> |
39 | #include <linux/phy.h> | |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/uaccess.h> | |
44 | #include <linux/module.h> | |
1da177e4 LT |
45 | #include <linux/crc32.h> |
46 | #include <linux/workqueue.h> | |
47 | #include <linux/ethtool.h> | |
bb40dcbb AF |
48 | #include <linux/fsl_devices.h> |
49 | #include "gianfar_mii.h" | |
1da177e4 LT |
50 | |
51 | /* The maximum number of packets to be handled in one call of gfar_poll */ | |
52 | #define GFAR_DEV_WEIGHT 64 | |
53 | ||
0bbaf069 KG |
54 | /* Length for FCB */ |
55 | #define GMAC_FCB_LEN 8 | |
56 | ||
57 | /* Default padding amount */ | |
58 | #define DEFAULT_PADDING 2 | |
59 | ||
1da177e4 LT |
60 | /* Number of bytes to align the rx bufs to */ |
61 | #define RXBUF_ALIGNMENT 64 | |
62 | ||
63 | /* The number of bytes which composes a unit for the purpose of | |
64 | * allocating data buffers. ie-for any given MTU, the data buffer | |
65 | * will be the next highest multiple of 512 bytes. */ | |
66 | #define INCREMENTAL_BUFFER_SIZE 512 | |
67 | ||
68 | ||
69 | #define MAC_ADDR_LEN 6 | |
70 | ||
71 | #define PHY_INIT_TIMEOUT 100000 | |
72 | #define GFAR_PHY_CHANGE_TIME 2 | |
73 | ||
bb40dcbb | 74 | #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, " |
1da177e4 LT |
75 | #define DRV_NAME "gfar-enet" |
76 | extern const char gfar_driver_name[]; | |
77 | extern const char gfar_driver_version[]; | |
78 | ||
79 | /* These need to be powers of 2 for this driver */ | |
1da177e4 LT |
80 | #define DEFAULT_TX_RING_SIZE 256 |
81 | #define DEFAULT_RX_RING_SIZE 256 | |
1da177e4 LT |
82 | |
83 | #define GFAR_RX_MAX_RING_SIZE 256 | |
84 | #define GFAR_TX_MAX_RING_SIZE 256 | |
85 | ||
7f7f5316 AF |
86 | #define GFAR_MAX_FIFO_THRESHOLD 511 |
87 | #define GFAR_MAX_FIFO_STARVE 511 | |
88 | #define GFAR_MAX_FIFO_STARVE_OFF 511 | |
89 | ||
1da177e4 LT |
90 | #define DEFAULT_RX_BUFFER_SIZE 1536 |
91 | #define TX_RING_MOD_MASK(size) (size-1) | |
92 | #define RX_RING_MOD_MASK(size) (size-1) | |
93 | #define JUMBO_BUFFER_SIZE 9728 | |
94 | #define JUMBO_FRAME_SIZE 9600 | |
95 | ||
7f7f5316 AF |
96 | #define DEFAULT_FIFO_TX_THR 0x100 |
97 | #define DEFAULT_FIFO_TX_STARVE 0x40 | |
98 | #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 | |
99 | #define DEFAULT_BD_STASH 1 | |
a3cb96a1 | 100 | #define DEFAULT_STASH_LENGTH 96 |
7f7f5316 AF |
101 | #define DEFAULT_STASH_INDEX 0 |
102 | ||
103 | /* The number of Exact Match registers */ | |
104 | #define GFAR_EM_NUM 15 | |
105 | ||
1da177e4 | 106 | /* Latency of interface clock in nanoseconds */ |
0bbaf069 | 107 | /* Interface clock latency , in this case, means the |
1da177e4 LT |
108 | * time described by a value of 1 in the interrupt |
109 | * coalescing registers' time fields. Since those fields | |
110 | * refer to the time it takes for 64 clocks to pass, the | |
111 | * latencies are as such: | |
112 | * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick | |
113 | * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick | |
114 | * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick | |
115 | */ | |
116 | #define GFAR_GBIT_TIME 512 | |
117 | #define GFAR_100_TIME 2560 | |
118 | #define GFAR_10_TIME 25600 | |
119 | ||
120 | #define DEFAULT_TX_COALESCE 1 | |
121 | #define DEFAULT_TXCOUNT 16 | |
2f448911 | 122 | #define DEFAULT_TXTIME 21 |
1da177e4 | 123 | |
d080cd63 DH |
124 | #define DEFAULT_RXTIME 21 |
125 | ||
d080cd63 DH |
126 | #define DEFAULT_RX_COALESCE 0 |
127 | #define DEFAULT_RXCOUNT 0 | |
1da177e4 | 128 | |
1da177e4 LT |
129 | #define MIIMCFG_INIT_VALUE 0x00000007 |
130 | #define MIIMCFG_RESET 0x80000000 | |
131 | #define MIIMIND_BUSY 0x00000001 | |
132 | ||
d3c12873 KJ |
133 | /* TBI register addresses */ |
134 | #define MII_TBICON 0x11 | |
135 | ||
136 | /* TBICON register bit fields */ | |
137 | #define TBICON_CLK_SELECT 0x0020 | |
138 | ||
1da177e4 LT |
139 | /* MAC register bits */ |
140 | #define MACCFG1_SOFT_RESET 0x80000000 | |
141 | #define MACCFG1_RESET_RX_MC 0x00080000 | |
142 | #define MACCFG1_RESET_TX_MC 0x00040000 | |
143 | #define MACCFG1_RESET_RX_FUN 0x00020000 | |
144 | #define MACCFG1_RESET_TX_FUN 0x00010000 | |
145 | #define MACCFG1_LOOPBACK 0x00000100 | |
146 | #define MACCFG1_RX_FLOW 0x00000020 | |
147 | #define MACCFG1_TX_FLOW 0x00000010 | |
148 | #define MACCFG1_SYNCD_RX_EN 0x00000008 | |
149 | #define MACCFG1_RX_EN 0x00000004 | |
150 | #define MACCFG1_SYNCD_TX_EN 0x00000002 | |
151 | #define MACCFG1_TX_EN 0x00000001 | |
152 | ||
153 | #define MACCFG2_INIT_SETTINGS 0x00007205 | |
154 | #define MACCFG2_FULL_DUPLEX 0x00000001 | |
155 | #define MACCFG2_IF 0x00000300 | |
156 | #define MACCFG2_MII 0x00000100 | |
157 | #define MACCFG2_GMII 0x00000200 | |
158 | #define MACCFG2_HUGEFRAME 0x00000020 | |
159 | #define MACCFG2_LENGTHCHECK 0x00000010 | |
d87eb127 | 160 | #define MACCFG2_MPEN 0x00000008 |
1da177e4 LT |
161 | |
162 | #define ECNTRL_INIT_SETTINGS 0x00001000 | |
163 | #define ECNTRL_TBI_MODE 0x00000020 | |
e8a2b6a4 | 164 | #define ECNTRL_REDUCED_MODE 0x00000010 |
7f7f5316 | 165 | #define ECNTRL_R100 0x00000008 |
e8a2b6a4 AF |
166 | #define ECNTRL_REDUCED_MII_MODE 0x00000004 |
167 | #define ECNTRL_SGMII_MODE 0x00000002 | |
1da177e4 LT |
168 | |
169 | #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE | |
170 | ||
171 | #define MINFLR_INIT_SETTINGS 0x00000040 | |
172 | ||
173 | /* Init to do tx snooping for buffers and descriptors */ | |
174 | #define DMACTRL_INIT_SETTINGS 0x000000c3 | |
175 | #define DMACTRL_GRS 0x00000010 | |
176 | #define DMACTRL_GTS 0x00000008 | |
177 | ||
178 | #define TSTAT_CLEAR_THALT 0x80000000 | |
179 | ||
180 | /* Interrupt coalescing macros */ | |
181 | #define IC_ICEN 0x80000000 | |
182 | #define IC_ICFT_MASK 0x1fe00000 | |
183 | #define IC_ICFT_SHIFT 21 | |
184 | #define mk_ic_icft(x) \ | |
185 | (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) | |
186 | #define IC_ICTT_MASK 0x0000ffff | |
187 | #define mk_ic_ictt(x) (x&IC_ICTT_MASK) | |
188 | ||
189 | #define mk_ic_value(count, time) (IC_ICEN | \ | |
190 | mk_ic_icft(count) | \ | |
191 | mk_ic_ictt(time)) | |
b46a8454 DH |
192 | #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ |
193 | IC_ICFT_SHIFT) | |
194 | #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) | |
195 | ||
196 | #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) | |
197 | #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) | |
1da177e4 | 198 | |
0bbaf069 KG |
199 | #define RCTRL_PAL_MASK 0x001f0000 |
200 | #define RCTRL_VLEX 0x00002000 | |
201 | #define RCTRL_FILREN 0x00001000 | |
202 | #define RCTRL_GHTX 0x00000400 | |
203 | #define RCTRL_IPCSEN 0x00000200 | |
204 | #define RCTRL_TUCSEN 0x00000100 | |
205 | #define RCTRL_PRSDEP_MASK 0x000000c0 | |
206 | #define RCTRL_PRSDEP_INIT 0x000000c0 | |
1da177e4 | 207 | #define RCTRL_PROM 0x00000008 |
7f7f5316 | 208 | #define RCTRL_EMEN 0x00000002 |
0bbaf069 KG |
209 | #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \ |
210 | | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT) | |
211 | #define RCTRL_EXTHASH (RCTRL_GHTX) | |
212 | #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) | |
7f7f5316 | 213 | #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) |
0bbaf069 KG |
214 | |
215 | ||
1da177e4 LT |
216 | #define RSTAT_CLEAR_RHALT 0x00800000 |
217 | ||
0bbaf069 KG |
218 | #define TCTRL_IPCSEN 0x00004000 |
219 | #define TCTRL_TUCSEN 0x00002000 | |
220 | #define TCTRL_VLINS 0x00001000 | |
221 | #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) | |
222 | ||
1da177e4 LT |
223 | #define IEVENT_INIT_CLEAR 0xffffffff |
224 | #define IEVENT_BABR 0x80000000 | |
225 | #define IEVENT_RXC 0x40000000 | |
226 | #define IEVENT_BSY 0x20000000 | |
227 | #define IEVENT_EBERR 0x10000000 | |
228 | #define IEVENT_MSRO 0x04000000 | |
229 | #define IEVENT_GTSC 0x02000000 | |
230 | #define IEVENT_BABT 0x01000000 | |
231 | #define IEVENT_TXC 0x00800000 | |
232 | #define IEVENT_TXE 0x00400000 | |
233 | #define IEVENT_TXB 0x00200000 | |
234 | #define IEVENT_TXF 0x00100000 | |
235 | #define IEVENT_LC 0x00040000 | |
236 | #define IEVENT_CRL 0x00020000 | |
237 | #define IEVENT_XFUN 0x00010000 | |
238 | #define IEVENT_RXB0 0x00008000 | |
d87eb127 | 239 | #define IEVENT_MAG 0x00000800 |
1da177e4 LT |
240 | #define IEVENT_GRSC 0x00000100 |
241 | #define IEVENT_RXF0 0x00000080 | |
0bbaf069 KG |
242 | #define IEVENT_FIR 0x00000008 |
243 | #define IEVENT_FIQ 0x00000004 | |
244 | #define IEVENT_DPE 0x00000002 | |
245 | #define IEVENT_PERR 0x00000001 | |
1da177e4 LT |
246 | #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0) |
247 | #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) | |
d080cd63 | 248 | #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) |
1da177e4 LT |
249 | #define IEVENT_ERR_MASK \ |
250 | (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ | |
251 | IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ | |
d87eb127 SW |
252 | | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ |
253 | | IEVENT_MAG) | |
1da177e4 LT |
254 | |
255 | #define IMASK_INIT_CLEAR 0x00000000 | |
256 | #define IMASK_BABR 0x80000000 | |
257 | #define IMASK_RXC 0x40000000 | |
258 | #define IMASK_BSY 0x20000000 | |
259 | #define IMASK_EBERR 0x10000000 | |
260 | #define IMASK_MSRO 0x04000000 | |
261 | #define IMASK_GRSC 0x02000000 | |
262 | #define IMASK_BABT 0x01000000 | |
263 | #define IMASK_TXC 0x00800000 | |
264 | #define IMASK_TXEEN 0x00400000 | |
265 | #define IMASK_TXBEN 0x00200000 | |
266 | #define IMASK_TXFEN 0x00100000 | |
267 | #define IMASK_LC 0x00040000 | |
268 | #define IMASK_CRL 0x00020000 | |
269 | #define IMASK_XFUN 0x00010000 | |
270 | #define IMASK_RXB0 0x00008000 | |
d87eb127 | 271 | #define IMASK_MAG 0x00000800 |
1da177e4 LT |
272 | #define IMASK_GTSC 0x00000100 |
273 | #define IMASK_RXFEN0 0x00000080 | |
0bbaf069 KG |
274 | #define IMASK_FIR 0x00000008 |
275 | #define IMASK_FIQ 0x00000004 | |
276 | #define IMASK_DPE 0x00000002 | |
277 | #define IMASK_PERR 0x00000001 | |
1da177e4 LT |
278 | #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ |
279 | IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ | |
0bbaf069 KG |
280 | IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ |
281 | | IMASK_PERR) | |
d080cd63 DH |
282 | #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \ |
283 | & IMASK_DEFAULT) | |
1da177e4 | 284 | |
7f7f5316 AF |
285 | /* Fifo management */ |
286 | #define FIFO_TX_THR_MASK 0x01ff | |
287 | #define FIFO_TX_STARVE_MASK 0x01ff | |
288 | #define FIFO_TX_STARVE_OFF_MASK 0x01ff | |
1da177e4 LT |
289 | |
290 | /* Attribute fields */ | |
291 | ||
292 | /* This enables rx snooping for buffers and descriptors */ | |
1da177e4 | 293 | #define ATTR_BDSTASH 0x00000800 |
1da177e4 | 294 | |
1da177e4 | 295 | #define ATTR_BUFSTASH 0x00004000 |
1da177e4 LT |
296 | |
297 | #define ATTR_SNOOPING 0x000000c0 | |
7f7f5316 | 298 | #define ATTR_INIT_SETTINGS ATTR_SNOOPING |
1da177e4 LT |
299 | |
300 | #define ATTRELI_INIT_SETTINGS 0x0 | |
7f7f5316 AF |
301 | #define ATTRELI_EL_MASK 0x3fff0000 |
302 | #define ATTRELI_EL(x) (x << 16) | |
303 | #define ATTRELI_EI_MASK 0x00003fff | |
304 | #define ATTRELI_EI(x) (x) | |
1da177e4 LT |
305 | |
306 | ||
307 | /* TxBD status field bits */ | |
308 | #define TXBD_READY 0x8000 | |
309 | #define TXBD_PADCRC 0x4000 | |
310 | #define TXBD_WRAP 0x2000 | |
311 | #define TXBD_INTERRUPT 0x1000 | |
312 | #define TXBD_LAST 0x0800 | |
313 | #define TXBD_CRC 0x0400 | |
314 | #define TXBD_DEF 0x0200 | |
315 | #define TXBD_HUGEFRAME 0x0080 | |
316 | #define TXBD_LATECOLLISION 0x0080 | |
317 | #define TXBD_RETRYLIMIT 0x0040 | |
318 | #define TXBD_RETRYCOUNTMASK 0x003c | |
319 | #define TXBD_UNDERRUN 0x0002 | |
0bbaf069 KG |
320 | #define TXBD_TOE 0x0002 |
321 | ||
322 | /* Tx FCB param bits */ | |
323 | #define TXFCB_VLN 0x80 | |
324 | #define TXFCB_IP 0x40 | |
325 | #define TXFCB_IP6 0x20 | |
326 | #define TXFCB_TUP 0x10 | |
327 | #define TXFCB_UDP 0x08 | |
328 | #define TXFCB_CIP 0x04 | |
329 | #define TXFCB_CTU 0x02 | |
330 | #define TXFCB_NPH 0x01 | |
331 | #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) | |
1da177e4 LT |
332 | |
333 | /* RxBD status field bits */ | |
334 | #define RXBD_EMPTY 0x8000 | |
335 | #define RXBD_RO1 0x4000 | |
336 | #define RXBD_WRAP 0x2000 | |
337 | #define RXBD_INTERRUPT 0x1000 | |
338 | #define RXBD_LAST 0x0800 | |
339 | #define RXBD_FIRST 0x0400 | |
340 | #define RXBD_MISS 0x0100 | |
341 | #define RXBD_BROADCAST 0x0080 | |
342 | #define RXBD_MULTICAST 0x0040 | |
343 | #define RXBD_LARGE 0x0020 | |
344 | #define RXBD_NONOCTET 0x0010 | |
345 | #define RXBD_SHORT 0x0008 | |
346 | #define RXBD_CRCERR 0x0004 | |
347 | #define RXBD_OVERRUN 0x0002 | |
348 | #define RXBD_TRUNCATED 0x0001 | |
349 | #define RXBD_STATS 0x01ff | |
99da5003 AF |
350 | #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ |
351 | | RXBD_CRCERR | RXBD_OVERRUN \ | |
352 | | RXBD_TRUNCATED) | |
1da177e4 | 353 | |
0bbaf069 KG |
354 | /* Rx FCB status field bits */ |
355 | #define RXFCB_VLN 0x8000 | |
356 | #define RXFCB_IP 0x4000 | |
357 | #define RXFCB_IP6 0x2000 | |
358 | #define RXFCB_TUP 0x1000 | |
359 | #define RXFCB_CIP 0x0800 | |
360 | #define RXFCB_CTU 0x0400 | |
361 | #define RXFCB_EIP 0x0200 | |
362 | #define RXFCB_ETU 0x0100 | |
7f7f5316 | 363 | #define RXFCB_CSUM_MASK 0x0f00 |
0bbaf069 KG |
364 | #define RXFCB_PERR_MASK 0x000c |
365 | #define RXFCB_PERR_BADL3 0x0008 | |
366 | ||
1da177e4 LT |
367 | struct txbd8 |
368 | { | |
369 | u16 status; /* Status Fields */ | |
370 | u16 length; /* Buffer length */ | |
371 | u32 bufPtr; /* Buffer Pointer */ | |
372 | }; | |
373 | ||
0bbaf069 | 374 | struct txfcb { |
7f7f5316 | 375 | u8 flags; |
0bbaf069 KG |
376 | u8 reserved; |
377 | u8 l4os; /* Level 4 Header Offset */ | |
378 | u8 l3os; /* Level 3 Header Offset */ | |
379 | u16 phcs; /* Pseudo-header Checksum */ | |
380 | u16 vlctl; /* VLAN control word */ | |
381 | }; | |
382 | ||
1da177e4 LT |
383 | struct rxbd8 |
384 | { | |
385 | u16 status; /* Status Fields */ | |
386 | u16 length; /* Buffer Length */ | |
387 | u32 bufPtr; /* Buffer Pointer */ | |
388 | }; | |
389 | ||
0bbaf069 | 390 | struct rxfcb { |
7f7f5316 | 391 | u16 flags; |
0bbaf069 KG |
392 | u8 rq; /* Receive Queue index */ |
393 | u8 pro; /* Layer 4 Protocol */ | |
394 | u16 reserved; | |
395 | u16 vlctl; /* VLAN control word */ | |
396 | }; | |
397 | ||
1da177e4 LT |
398 | struct rmon_mib |
399 | { | |
400 | u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ | |
401 | u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ | |
402 | u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ | |
403 | u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ | |
404 | u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ | |
405 | u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ | |
406 | u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ | |
407 | u32 rbyt; /* 0x.69c - Receive Byte Counter */ | |
408 | u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ | |
409 | u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ | |
410 | u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ | |
411 | u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ | |
412 | u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ | |
413 | u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ | |
414 | u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ | |
415 | u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ | |
416 | u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ | |
417 | u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ | |
418 | u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ | |
419 | u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ | |
420 | u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ | |
421 | u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ | |
422 | u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ | |
423 | u32 rdrp; /* 0x.6dc - Receive Drop Counter */ | |
424 | u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ | |
425 | u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ | |
426 | u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ | |
427 | u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ | |
428 | u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ | |
429 | u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ | |
430 | u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ | |
431 | u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ | |
432 | u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ | |
433 | u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ | |
434 | u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ | |
435 | u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ | |
436 | u8 res1[4]; | |
437 | u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ | |
438 | u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ | |
439 | u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ | |
440 | u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ | |
441 | u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ | |
442 | u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ | |
443 | u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ | |
444 | u32 car1; /* 0x.730 - Carry Register One */ | |
445 | u32 car2; /* 0x.734 - Carry Register Two */ | |
446 | u32 cam1; /* 0x.738 - Carry Mask Register One */ | |
447 | u32 cam2; /* 0x.73c - Carry Mask Register Two */ | |
448 | }; | |
449 | ||
450 | struct gfar_extra_stats { | |
451 | u64 kernel_dropped; | |
452 | u64 rx_large; | |
453 | u64 rx_short; | |
454 | u64 rx_nonoctet; | |
455 | u64 rx_crcerr; | |
456 | u64 rx_overrun; | |
457 | u64 rx_bsy; | |
458 | u64 rx_babr; | |
459 | u64 rx_trunc; | |
460 | u64 eberr; | |
461 | u64 tx_babt; | |
462 | u64 tx_underrun; | |
463 | u64 rx_skbmissing; | |
464 | u64 tx_timeout; | |
465 | }; | |
466 | ||
467 | #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) | |
468 | #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64)) | |
469 | ||
470 | /* Number of stats in the stats structure (ignore car and cam regs)*/ | |
471 | #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) | |
472 | ||
473 | #define GFAR_INFOSTR_LEN 32 | |
474 | ||
475 | struct gfar_stats { | |
476 | u64 extra[GFAR_EXTRA_STATS_LEN]; | |
477 | u64 rmon[GFAR_RMON_LEN]; | |
478 | }; | |
479 | ||
480 | ||
481 | struct gfar { | |
0bbaf069 KG |
482 | u32 tsec_id; /* 0x.000 - Controller ID register */ |
483 | u8 res1[12]; | |
484 | u32 ievent; /* 0x.010 - Interrupt Event Register */ | |
485 | u32 imask; /* 0x.014 - Interrupt Mask Register */ | |
486 | u32 edis; /* 0x.018 - Error Disabled Register */ | |
1da177e4 | 487 | u8 res2[4]; |
0bbaf069 KG |
488 | u32 ecntrl; /* 0x.020 - Ethernet Control Register */ |
489 | u32 minflr; /* 0x.024 - Minimum Frame Length Register */ | |
490 | u32 ptv; /* 0x.028 - Pause Time Value Register */ | |
491 | u32 dmactrl; /* 0x.02c - DMA Control Register */ | |
492 | u32 tbipa; /* 0x.030 - TBI PHY Address Register */ | |
1da177e4 | 493 | u8 res3[88]; |
0bbaf069 | 494 | u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ |
1da177e4 | 495 | u8 res4[8]; |
0bbaf069 | 496 | u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ |
1da177e4 | 497 | u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ |
0bbaf069 KG |
498 | u8 res5[4]; |
499 | u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */ | |
500 | u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */ | |
501 | u8 res6[84]; | |
502 | u32 tctrl; /* 0x.100 - Transmit Control Register */ | |
503 | u32 tstat; /* 0x.104 - Transmit Status Register */ | |
504 | u32 dfvlan; /* 0x.108 - Default VLAN Control word */ | |
505 | u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ | |
506 | u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ | |
507 | u32 tqueue; /* 0x.114 - Transmit queue control register */ | |
508 | u8 res7[40]; | |
509 | u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ | |
510 | u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ | |
511 | u8 res8[52]; | |
512 | u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ | |
513 | u8 res9a[4]; | |
514 | u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ | |
515 | u8 res9b[4]; | |
516 | u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ | |
517 | u8 res9c[4]; | |
518 | u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ | |
519 | u8 res9d[4]; | |
520 | u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ | |
521 | u8 res9e[4]; | |
522 | u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ | |
523 | u8 res9f[4]; | |
524 | u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ | |
525 | u8 res9g[4]; | |
526 | u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ | |
527 | u8 res9h[4]; | |
528 | u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ | |
529 | u8 res9[64]; | |
530 | u32 tbaseh; /* 0x.200 - TxBD base address high */ | |
531 | u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ | |
532 | u8 res10a[4]; | |
533 | u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ | |
534 | u8 res10b[4]; | |
535 | u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ | |
536 | u8 res10c[4]; | |
537 | u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ | |
538 | u8 res10d[4]; | |
539 | u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ | |
540 | u8 res10e[4]; | |
541 | u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ | |
542 | u8 res10f[4]; | |
543 | u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ | |
544 | u8 res10g[4]; | |
545 | u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ | |
546 | u8 res10[192]; | |
547 | u32 rctrl; /* 0x.300 - Receive Control Register */ | |
548 | u32 rstat; /* 0x.304 - Receive Status Register */ | |
549 | u8 res12[8]; | |
550 | u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ | |
551 | u32 rqueue; /* 0x.314 - Receive queue control register */ | |
552 | u8 res13[24]; | |
553 | u32 rbifx; /* 0x.330 - Receive bit field extract control register */ | |
554 | u32 rqfar; /* 0x.334 - Receive queue filing table address register */ | |
555 | u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ | |
556 | u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ | |
557 | u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ | |
558 | u8 res14[56]; | |
559 | u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ | |
560 | u8 res15a[4]; | |
561 | u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ | |
562 | u8 res15b[4]; | |
563 | u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ | |
564 | u8 res15c[4]; | |
565 | u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ | |
566 | u8 res15d[4]; | |
567 | u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ | |
568 | u8 res15e[4]; | |
569 | u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ | |
570 | u8 res15f[4]; | |
571 | u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ | |
572 | u8 res15g[4]; | |
573 | u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ | |
574 | u8 res15h[4]; | |
575 | u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ | |
576 | u8 res16[64]; | |
577 | u32 rbaseh; /* 0x.400 - RxBD base address high */ | |
578 | u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ | |
579 | u8 res17a[4]; | |
580 | u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ | |
581 | u8 res17b[4]; | |
582 | u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ | |
583 | u8 res17c[4]; | |
584 | u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ | |
585 | u8 res17d[4]; | |
586 | u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ | |
587 | u8 res17e[4]; | |
588 | u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ | |
589 | u8 res17f[4]; | |
590 | u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ | |
591 | u8 res17g[4]; | |
592 | u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ | |
593 | u8 res17[192]; | |
594 | u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ | |
595 | u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ | |
596 | u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ | |
597 | u32 hafdup; /* 0x.50c - Half Duplex Register */ | |
598 | u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ | |
1da177e4 | 599 | u8 res18[12]; |
bb40dcbb | 600 | u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ |
1da177e4 | 601 | u8 res19[4]; |
0bbaf069 KG |
602 | u32 ifstat; /* 0x.53c - Interface Status Register */ |
603 | u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ | |
604 | u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ | |
605 | u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ | |
606 | u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ | |
607 | u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ | |
608 | u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ | |
609 | u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ | |
610 | u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ | |
611 | u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ | |
612 | u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ | |
613 | u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ | |
614 | u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ | |
615 | u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ | |
616 | u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ | |
617 | u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ | |
618 | u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ | |
619 | u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ | |
620 | u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ | |
621 | u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ | |
622 | u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ | |
623 | u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ | |
624 | u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ | |
625 | u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ | |
626 | u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ | |
627 | u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ | |
628 | u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ | |
629 | u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ | |
630 | u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ | |
631 | u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ | |
632 | u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ | |
633 | u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ | |
634 | u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ | |
635 | u8 res20[192]; | |
636 | struct rmon_mib rmon; /* 0x.680-0x.73c */ | |
637 | u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ | |
638 | u8 res21[188]; | |
639 | u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ | |
640 | u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ | |
641 | u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ | |
642 | u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ | |
643 | u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ | |
644 | u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ | |
645 | u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ | |
646 | u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ | |
1da177e4 | 647 | u8 res22[96]; |
0bbaf069 KG |
648 | u32 gaddr0; /* 0x.880 - Group address register 0 */ |
649 | u32 gaddr1; /* 0x.884 - Group address register 1 */ | |
650 | u32 gaddr2; /* 0x.888 - Group address register 2 */ | |
651 | u32 gaddr3; /* 0x.88c - Group address register 3 */ | |
652 | u32 gaddr4; /* 0x.890 - Group address register 4 */ | |
653 | u32 gaddr5; /* 0x.894 - Group address register 5 */ | |
654 | u32 gaddr6; /* 0x.898 - Group address register 6 */ | |
655 | u32 gaddr7; /* 0x.89c - Group address register 7 */ | |
656 | u8 res23a[352]; | |
657 | u32 fifocfg; /* 0x.a00 - FIFO interface config register */ | |
658 | u8 res23b[252]; | |
659 | u8 res23c[248]; | |
660 | u32 attr; /* 0x.bf8 - Attributes Register */ | |
661 | u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ | |
1da177e4 LT |
662 | u8 res24[1024]; |
663 | ||
664 | }; | |
665 | ||
b31a1d8b AF |
666 | /* Flags related to gianfar device features */ |
667 | #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 | |
668 | #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 | |
669 | #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 | |
670 | #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 | |
671 | #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 | |
672 | #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 | |
673 | #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 | |
674 | #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080 | |
675 | #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 | |
676 | #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 | |
677 | #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 | |
678 | ||
1da177e4 LT |
679 | /* Struct stolen almost completely (and shamelessly) from the FCC enet source |
680 | * (Ok, that's not so true anymore, but there is a family resemblence) | |
681 | * The GFAR buffer descriptors track the ring buffers. The rx_bd_base | |
682 | * and tx_bd_base always point to the currently available buffer. | |
683 | * The dirty_tx tracks the current buffer that is being sent by the | |
684 | * controller. The cur_tx and dirty_tx are equal under both completely | |
685 | * empty and completely full conditions. The empty/ready indicator in | |
686 | * the buffer descriptor determines the actual condition. | |
687 | */ | |
688 | struct gfar_private { | |
fef6108d AF |
689 | /* Fields controlled by TX lock */ |
690 | spinlock_t txlock; | |
691 | ||
692 | /* Pointer to the array of skbuffs */ | |
1da177e4 | 693 | struct sk_buff ** tx_skbuff; |
1da177e4 | 694 | |
fef6108d | 695 | /* next free skb in the array */ |
1da177e4 | 696 | u16 skb_curtx; |
1da177e4 | 697 | |
fef6108d | 698 | /* First skb in line to be transmitted */ |
1da177e4 LT |
699 | u16 skb_dirtytx; |
700 | ||
701 | /* Configuration info for the coalescing features */ | |
702 | unsigned char txcoalescing; | |
b46a8454 | 703 | unsigned long txic; |
fef6108d AF |
704 | |
705 | /* Buffer descriptor pointers */ | |
706 | struct txbd8 *tx_bd_base; /* First tx buffer descriptor */ | |
707 | struct txbd8 *cur_tx; /* Next free ring entry */ | |
708 | struct txbd8 *dirty_tx; /* First buffer in line | |
709 | to be transmitted */ | |
710 | unsigned int tx_ring_size; | |
711 | ||
712 | /* RX Locked fields */ | |
713 | spinlock_t rxlock; | |
714 | ||
b31a1d8b | 715 | struct device_node *node; |
bea3348e SH |
716 | struct net_device *dev; |
717 | struct napi_struct napi; | |
718 | ||
fef6108d AF |
719 | /* skb array and index */ |
720 | struct sk_buff ** rx_skbuff; | |
721 | u16 skb_currx; | |
722 | ||
723 | /* RX Coalescing values */ | |
1da177e4 | 724 | unsigned char rxcoalescing; |
b46a8454 | 725 | unsigned long rxic; |
1da177e4 | 726 | |
fef6108d | 727 | struct rxbd8 *rx_bd_base; /* First Rx buffers */ |
1da177e4 | 728 | struct rxbd8 *cur_rx; /* Next free rx ring entry */ |
fef6108d AF |
729 | |
730 | /* RX parameters */ | |
731 | unsigned int rx_ring_size; | |
1da177e4 LT |
732 | unsigned int rx_buffer_size; |
733 | unsigned int rx_stash_size; | |
7f7f5316 | 734 | unsigned int rx_stash_index; |
fef6108d AF |
735 | |
736 | struct vlan_group *vlgrp; | |
737 | ||
738 | /* Unprotected fields */ | |
739 | /* Pointer to the GFAR memory mapped Registers */ | |
740 | struct gfar __iomem *regs; | |
741 | ||
742 | /* Hash registers and their width */ | |
743 | u32 __iomem *hash_regs[16]; | |
744 | int hash_width; | |
745 | ||
746 | /* global parameters */ | |
7f7f5316 AF |
747 | unsigned int fifo_threshold; |
748 | unsigned int fifo_starve; | |
749 | unsigned int fifo_starve_off; | |
1da177e4 | 750 | |
d87eb127 SW |
751 | /* Bitfield update lock */ |
752 | spinlock_t bflock; | |
753 | ||
b31a1d8b AF |
754 | phy_interface_t interface; |
755 | char phy_bus_id[BUS_ID_SIZE]; | |
756 | u32 device_flags; | |
0bbaf069 KG |
757 | unsigned char vlan_enable:1, |
758 | rx_csum_enable:1, | |
7f7f5316 | 759 | extended_hash:1, |
d87eb127 SW |
760 | bd_stash_en:1, |
761 | wol_en:1; /* Wake-on-LAN enabled */ | |
0bbaf069 | 762 | unsigned short padding; |
fef6108d | 763 | |
1da177e4 LT |
764 | unsigned int interruptTransmit; |
765 | unsigned int interruptReceive; | |
766 | unsigned int interruptError; | |
fef6108d | 767 | |
fef6108d | 768 | /* PHY stuff */ |
bb40dcbb | 769 | struct phy_device *phydev; |
b31a1d8b | 770 | struct phy_device *tbiphy; |
bb40dcbb | 771 | struct mii_bus *mii_bus; |
1da177e4 LT |
772 | int oldspeed; |
773 | int oldduplex; | |
774 | int oldlink; | |
0bbaf069 KG |
775 | |
776 | uint32_t msg_enable; | |
fef6108d | 777 | |
ab939905 | 778 | struct work_struct reset_task; |
fef6108d | 779 | /* Network Statistics */ |
fef6108d | 780 | struct gfar_extra_stats extra_stats; |
1da177e4 LT |
781 | }; |
782 | ||
cc8c6e37 | 783 | static inline u32 gfar_read(volatile unsigned __iomem *addr) |
1da177e4 LT |
784 | { |
785 | u32 val; | |
786 | val = in_be32(addr); | |
787 | return val; | |
788 | } | |
789 | ||
cc8c6e37 | 790 | static inline void gfar_write(volatile unsigned __iomem *addr, u32 val) |
1da177e4 LT |
791 | { |
792 | out_be32(addr, val); | |
793 | } | |
794 | ||
7d12e780 | 795 | extern irqreturn_t gfar_receive(int irq, void *dev_id); |
bb40dcbb AF |
796 | extern int startup_gfar(struct net_device *dev); |
797 | extern void stop_gfar(struct net_device *dev); | |
798 | extern void gfar_halt(struct net_device *dev); | |
799 | extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, | |
800 | int enable, u32 regnum, u32 read); | |
7f7f5316 | 801 | void gfar_init_sysfs(struct net_device *dev); |
f162b9d5 AF |
802 | int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id, |
803 | int regnum, u16 value); | |
804 | int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum); | |
bb40dcbb | 805 | |
1da177e4 | 806 | #endif /* __GIANFAR_H */ |