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48257c4f PA |
1 | /* |
2 | * FCC driver for Motorola MPC82xx (PQ2). | |
3 | * | |
4 | * Copyright (c) 2003 Intracom S.A. | |
5 | * by Pantelis Antoniou <panto@intracom.gr> | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. | |
8 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public License | |
11 | * version 2. This program is licensed "as is" without any warranty of any | |
12 | * kind, whether express or implied. | |
13 | */ | |
14 | ||
48257c4f PA |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/ptrace.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/netdevice.h> | |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/skbuff.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/mii.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/bitops.h> | |
35 | #include <linux/fs.h> | |
f7b99969 | 36 | #include <linux/platform_device.h> |
5b4b8454 | 37 | #include <linux/phy.h> |
48257c4f PA |
38 | |
39 | #include <asm/immap_cpm2.h> | |
40 | #include <asm/mpc8260.h> | |
41 | #include <asm/cpm2.h> | |
42 | ||
43 | #include <asm/pgtable.h> | |
44 | #include <asm/irq.h> | |
45 | #include <asm/uaccess.h> | |
46 | ||
47 | #include "fs_enet.h" | |
48 | ||
49 | /*************************************************/ | |
50 | ||
51 | /* FCC access macros */ | |
52 | ||
53 | #define __fcc_out32(addr, x) out_be32((unsigned *)addr, x) | |
54 | #define __fcc_out16(addr, x) out_be16((unsigned short *)addr, x) | |
55 | #define __fcc_out8(addr, x) out_8((unsigned char *)addr, x) | |
56 | #define __fcc_in32(addr) in_be32((unsigned *)addr) | |
57 | #define __fcc_in16(addr) in_be16((unsigned short *)addr) | |
58 | #define __fcc_in8(addr) in_8((unsigned char *)addr) | |
59 | ||
60 | /* parameter space */ | |
61 | ||
62 | /* write, read, set bits, clear bits */ | |
63 | #define W32(_p, _m, _v) __fcc_out32(&(_p)->_m, (_v)) | |
64 | #define R32(_p, _m) __fcc_in32(&(_p)->_m) | |
65 | #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v)) | |
66 | #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v)) | |
67 | ||
68 | #define W16(_p, _m, _v) __fcc_out16(&(_p)->_m, (_v)) | |
69 | #define R16(_p, _m) __fcc_in16(&(_p)->_m) | |
70 | #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v)) | |
71 | #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v)) | |
72 | ||
73 | #define W8(_p, _m, _v) __fcc_out8(&(_p)->_m, (_v)) | |
74 | #define R8(_p, _m) __fcc_in8(&(_p)->_m) | |
75 | #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v)) | |
76 | #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v)) | |
77 | ||
78 | /*************************************************/ | |
79 | ||
80 | #define FCC_MAX_MULTICAST_ADDRS 64 | |
81 | ||
82 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
83 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) | |
84 | #define mk_mii_end 0 | |
85 | ||
86 | #define MAX_CR_CMD_LOOPS 10000 | |
87 | ||
88 | static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 mcn, u32 op) | |
89 | { | |
90 | const struct fs_platform_info *fpi = fep->fpi; | |
91 | ||
92 | cpm2_map_t *immap = fs_enet_immap; | |
93 | cpm_cpm2_t *cpmp = &immap->im_cpm; | |
94 | u32 v; | |
95 | int i; | |
96 | ||
97 | /* Currently I don't know what feature call will look like. But | |
98 | I guess there'd be something like do_cpm_cmd() which will require page & sblock */ | |
99 | v = mk_cr_cmd(fpi->cp_page, fpi->cp_block, mcn, op); | |
100 | W32(cpmp, cp_cpcr, v | CPM_CR_FLG); | |
101 | for (i = 0; i < MAX_CR_CMD_LOOPS; i++) | |
102 | if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0) | |
103 | break; | |
104 | ||
105 | if (i >= MAX_CR_CMD_LOOPS) { | |
106 | printk(KERN_ERR "%s(): Not able to issue CPM command\n", | |
107 | __FUNCTION__); | |
108 | return 1; | |
109 | } | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
114 | static int do_pd_setup(struct fs_enet_private *fep) | |
115 | { | |
116 | struct platform_device *pdev = to_platform_device(fep->dev); | |
117 | struct resource *r; | |
118 | ||
119 | /* Fill out IRQ field */ | |
120 | fep->interrupt = platform_get_irq(pdev, 0); | |
48944738 DV |
121 | if (fep->interrupt < 0) |
122 | return -EINVAL; | |
48257c4f PA |
123 | |
124 | /* Attach the memory for the FCC Parameter RAM */ | |
125 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram"); | |
5b4b8454 | 126 | fep->fcc.ep = (void *)ioremap(r->start, r->end - r->start + 1); |
48257c4f PA |
127 | if (fep->fcc.ep == NULL) |
128 | return -EINVAL; | |
129 | ||
130 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs"); | |
5b4b8454 | 131 | fep->fcc.fccp = (void *)ioremap(r->start, r->end - r->start + 1); |
48257c4f PA |
132 | if (fep->fcc.fccp == NULL) |
133 | return -EINVAL; | |
134 | ||
5b4b8454 VB |
135 | if (fep->fpi->fcc_regs_c) { |
136 | ||
137 | fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c; | |
138 | } else { | |
139 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
140 | "fcc_regs_c"); | |
141 | fep->fcc.fcccp = (void *)ioremap(r->start, | |
142 | r->end - r->start + 1); | |
143 | } | |
48257c4f PA |
144 | |
145 | if (fep->fcc.fcccp == NULL) | |
146 | return -EINVAL; | |
147 | ||
5b4b8454 VB |
148 | fep->fcc.mem = (void *)fep->fpi->mem_offset; |
149 | if (fep->fcc.mem == NULL) | |
150 | return -EINVAL; | |
151 | ||
48257c4f PA |
152 | return 0; |
153 | } | |
154 | ||
155 | #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB) | |
156 | #define FCC_RX_EVENT (FCC_ENET_RXF) | |
157 | #define FCC_TX_EVENT (FCC_ENET_TXB) | |
158 | #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY) | |
159 | ||
160 | static int setup_data(struct net_device *dev) | |
161 | { | |
162 | struct fs_enet_private *fep = netdev_priv(dev); | |
163 | const struct fs_platform_info *fpi = fep->fpi; | |
164 | ||
165 | fep->fcc.idx = fs_get_fcc_index(fpi->fs_no); | |
166 | if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */ | |
167 | return -EINVAL; | |
168 | ||
48257c4f PA |
169 | if (do_pd_setup(fep) != 0) |
170 | return -EINVAL; | |
171 | ||
172 | fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK; | |
173 | fep->ev_rx = FCC_RX_EVENT; | |
174 | fep->ev_tx = FCC_TX_EVENT; | |
175 | fep->ev_err = FCC_ERR_EVENT_MSK; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | static int allocate_bd(struct net_device *dev) | |
181 | { | |
182 | struct fs_enet_private *fep = netdev_priv(dev); | |
183 | const struct fs_platform_info *fpi = fep->fpi; | |
184 | ||
185 | fep->ring_base = dma_alloc_coherent(fep->dev, | |
186 | (fpi->tx_ring + fpi->rx_ring) * | |
187 | sizeof(cbd_t), &fep->ring_mem_addr, | |
188 | GFP_KERNEL); | |
189 | if (fep->ring_base == NULL) | |
190 | return -ENOMEM; | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | static void free_bd(struct net_device *dev) | |
196 | { | |
197 | struct fs_enet_private *fep = netdev_priv(dev); | |
198 | const struct fs_platform_info *fpi = fep->fpi; | |
199 | ||
200 | if (fep->ring_base) | |
201 | dma_free_coherent(fep->dev, | |
202 | (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t), | |
203 | fep->ring_base, fep->ring_mem_addr); | |
204 | } | |
205 | ||
206 | static void cleanup_data(struct net_device *dev) | |
207 | { | |
208 | /* nothing */ | |
209 | } | |
210 | ||
211 | static void set_promiscuous_mode(struct net_device *dev) | |
212 | { | |
213 | struct fs_enet_private *fep = netdev_priv(dev); | |
214 | fcc_t *fccp = fep->fcc.fccp; | |
215 | ||
216 | S32(fccp, fcc_fpsmr, FCC_PSMR_PRO); | |
217 | } | |
218 | ||
219 | static void set_multicast_start(struct net_device *dev) | |
220 | { | |
221 | struct fs_enet_private *fep = netdev_priv(dev); | |
222 | fcc_enet_t *ep = fep->fcc.ep; | |
223 | ||
224 | W32(ep, fen_gaddrh, 0); | |
225 | W32(ep, fen_gaddrl, 0); | |
226 | } | |
227 | ||
228 | static void set_multicast_one(struct net_device *dev, const u8 *mac) | |
229 | { | |
230 | struct fs_enet_private *fep = netdev_priv(dev); | |
231 | fcc_enet_t *ep = fep->fcc.ep; | |
232 | u16 taddrh, taddrm, taddrl; | |
233 | ||
234 | taddrh = ((u16)mac[5] << 8) | mac[4]; | |
235 | taddrm = ((u16)mac[3] << 8) | mac[2]; | |
236 | taddrl = ((u16)mac[1] << 8) | mac[0]; | |
237 | ||
238 | W16(ep, fen_taddrh, taddrh); | |
239 | W16(ep, fen_taddrm, taddrm); | |
240 | W16(ep, fen_taddrl, taddrl); | |
241 | fcc_cr_cmd(fep, 0x0C, CPM_CR_SET_GADDR); | |
242 | } | |
243 | ||
244 | static void set_multicast_finish(struct net_device *dev) | |
245 | { | |
246 | struct fs_enet_private *fep = netdev_priv(dev); | |
247 | fcc_t *fccp = fep->fcc.fccp; | |
248 | fcc_enet_t *ep = fep->fcc.ep; | |
249 | ||
250 | /* clear promiscuous always */ | |
251 | C32(fccp, fcc_fpsmr, FCC_PSMR_PRO); | |
252 | ||
253 | /* if all multi or too many multicasts; just enable all */ | |
254 | if ((dev->flags & IFF_ALLMULTI) != 0 || | |
255 | dev->mc_count > FCC_MAX_MULTICAST_ADDRS) { | |
256 | ||
257 | W32(ep, fen_gaddrh, 0xffffffff); | |
258 | W32(ep, fen_gaddrl, 0xffffffff); | |
259 | } | |
260 | ||
261 | /* read back */ | |
262 | fep->fcc.gaddrh = R32(ep, fen_gaddrh); | |
263 | fep->fcc.gaddrl = R32(ep, fen_gaddrl); | |
264 | } | |
265 | ||
266 | static void set_multicast_list(struct net_device *dev) | |
267 | { | |
268 | struct dev_mc_list *pmc; | |
269 | ||
270 | if ((dev->flags & IFF_PROMISC) == 0) { | |
271 | set_multicast_start(dev); | |
272 | for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next) | |
273 | set_multicast_one(dev, pmc->dmi_addr); | |
274 | set_multicast_finish(dev); | |
275 | } else | |
276 | set_promiscuous_mode(dev); | |
277 | } | |
278 | ||
279 | static void restart(struct net_device *dev) | |
280 | { | |
281 | struct fs_enet_private *fep = netdev_priv(dev); | |
282 | const struct fs_platform_info *fpi = fep->fpi; | |
283 | fcc_t *fccp = fep->fcc.fccp; | |
284 | fcc_c_t *fcccp = fep->fcc.fcccp; | |
285 | fcc_enet_t *ep = fep->fcc.ep; | |
286 | dma_addr_t rx_bd_base_phys, tx_bd_base_phys; | |
287 | u16 paddrh, paddrm, paddrl; | |
288 | u16 mem_addr; | |
289 | const unsigned char *mac; | |
290 | int i; | |
291 | ||
292 | C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); | |
293 | ||
294 | /* clear everything (slow & steady does it) */ | |
295 | for (i = 0; i < sizeof(*ep); i++) | |
296 | __fcc_out8((char *)ep + i, 0); | |
297 | ||
298 | /* get physical address */ | |
299 | rx_bd_base_phys = fep->ring_mem_addr; | |
300 | tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring; | |
301 | ||
302 | /* point to bds */ | |
303 | W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys); | |
304 | W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys); | |
305 | ||
306 | /* Set maximum bytes per receive buffer. | |
307 | * It must be a multiple of 32. | |
308 | */ | |
309 | W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE); | |
310 | ||
311 | W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24); | |
312 | W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24); | |
313 | ||
314 | /* Allocate space in the reserved FCC area of DPRAM for the | |
315 | * internal buffers. No one uses this space (yet), so we | |
316 | * can do this. Later, we will add resource management for | |
317 | * this area. | |
318 | */ | |
319 | ||
320 | mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */ | |
321 | ||
322 | W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff)); | |
323 | W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff)); | |
324 | W16(ep, fen_padptr, mem_addr + 64); | |
325 | ||
326 | /* fill with special symbol... */ | |
327 | memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32); | |
328 | ||
329 | W32(ep, fen_genfcc.fcc_rbptr, 0); | |
330 | W32(ep, fen_genfcc.fcc_tbptr, 0); | |
331 | W32(ep, fen_genfcc.fcc_rcrc, 0); | |
332 | W32(ep, fen_genfcc.fcc_tcrc, 0); | |
333 | W16(ep, fen_genfcc.fcc_res1, 0); | |
334 | W32(ep, fen_genfcc.fcc_res2, 0); | |
335 | ||
336 | /* no CAM */ | |
337 | W32(ep, fen_camptr, 0); | |
338 | ||
339 | /* Set CRC preset and mask */ | |
340 | W32(ep, fen_cmask, 0xdebb20e3); | |
341 | W32(ep, fen_cpres, 0xffffffff); | |
342 | ||
343 | W32(ep, fen_crcec, 0); /* CRC Error counter */ | |
344 | W32(ep, fen_alec, 0); /* alignment error counter */ | |
345 | W32(ep, fen_disfc, 0); /* discard frame counter */ | |
346 | W16(ep, fen_retlim, 15); /* Retry limit threshold */ | |
347 | W16(ep, fen_pper, 0); /* Normal persistence */ | |
348 | ||
349 | /* set group address */ | |
350 | W32(ep, fen_gaddrh, fep->fcc.gaddrh); | |
351 | W32(ep, fen_gaddrl, fep->fcc.gaddrh); | |
352 | ||
353 | /* Clear hash filter tables */ | |
354 | W32(ep, fen_iaddrh, 0); | |
355 | W32(ep, fen_iaddrl, 0); | |
356 | ||
357 | /* Clear the Out-of-sequence TxBD */ | |
358 | W16(ep, fen_tfcstat, 0); | |
359 | W16(ep, fen_tfclen, 0); | |
360 | W32(ep, fen_tfcptr, 0); | |
361 | ||
362 | W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */ | |
363 | W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */ | |
364 | ||
365 | /* set address */ | |
366 | mac = dev->dev_addr; | |
367 | paddrh = ((u16)mac[5] << 8) | mac[4]; | |
368 | paddrm = ((u16)mac[3] << 8) | mac[2]; | |
369 | paddrl = ((u16)mac[1] << 8) | mac[0]; | |
370 | ||
371 | W16(ep, fen_paddrh, paddrh); | |
372 | W16(ep, fen_paddrm, paddrm); | |
373 | W16(ep, fen_paddrl, paddrl); | |
374 | ||
375 | W16(ep, fen_taddrh, 0); | |
376 | W16(ep, fen_taddrm, 0); | |
377 | W16(ep, fen_taddrl, 0); | |
378 | ||
379 | W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */ | |
380 | W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ | |
381 | ||
382 | /* Clear stat counters, in case we ever enable RMON */ | |
383 | W32(ep, fen_octc, 0); | |
384 | W32(ep, fen_colc, 0); | |
385 | W32(ep, fen_broc, 0); | |
386 | W32(ep, fen_mulc, 0); | |
387 | W32(ep, fen_uspc, 0); | |
388 | W32(ep, fen_frgc, 0); | |
389 | W32(ep, fen_ospc, 0); | |
390 | W32(ep, fen_jbrc, 0); | |
391 | W32(ep, fen_p64c, 0); | |
392 | W32(ep, fen_p65c, 0); | |
393 | W32(ep, fen_p128c, 0); | |
394 | W32(ep, fen_p256c, 0); | |
395 | W32(ep, fen_p512c, 0); | |
396 | W32(ep, fen_p1024c, 0); | |
397 | ||
398 | W16(ep, fen_rfthr, 0); /* Suggested by manual */ | |
399 | W16(ep, fen_rfcnt, 0); | |
400 | W16(ep, fen_cftype, 0); | |
401 | ||
402 | fs_init_bds(dev); | |
403 | ||
404 | /* adjust to speed (for RMII mode) */ | |
405 | if (fpi->use_rmii) { | |
5b4b8454 | 406 | if (fep->phydev->speed == 100) |
48257c4f PA |
407 | C8(fcccp, fcc_gfemr, 0x20); |
408 | else | |
409 | S8(fcccp, fcc_gfemr, 0x20); | |
410 | } | |
411 | ||
412 | fcc_cr_cmd(fep, 0x0c, CPM_CR_INIT_TRX); | |
413 | ||
414 | /* clear events */ | |
415 | W16(fccp, fcc_fcce, 0xffff); | |
416 | ||
417 | /* Enable interrupts we wish to service */ | |
418 | W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB); | |
419 | ||
420 | /* Set GFMR to enable Ethernet operating mode */ | |
421 | W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET); | |
422 | ||
423 | /* set sync/delimiters */ | |
424 | W16(fccp, fcc_fdsr, 0xd555); | |
425 | ||
426 | W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC); | |
427 | ||
428 | if (fpi->use_rmii) | |
429 | S32(fccp, fcc_fpsmr, FCC_PSMR_RMII); | |
430 | ||
431 | /* adjust to duplex mode */ | |
5b4b8454 | 432 | if (fep->phydev->duplex) |
48257c4f PA |
433 | S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); |
434 | else | |
435 | C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); | |
436 | ||
437 | S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); | |
438 | } | |
439 | ||
440 | static void stop(struct net_device *dev) | |
441 | { | |
442 | struct fs_enet_private *fep = netdev_priv(dev); | |
443 | fcc_t *fccp = fep->fcc.fccp; | |
444 | ||
445 | /* stop ethernet */ | |
446 | C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); | |
447 | ||
448 | /* clear events */ | |
449 | W16(fccp, fcc_fcce, 0xffff); | |
450 | ||
451 | /* clear interrupt mask */ | |
452 | W16(fccp, fcc_fccm, 0); | |
453 | ||
454 | fs_cleanup_bds(dev); | |
455 | } | |
456 | ||
457 | static void pre_request_irq(struct net_device *dev, int irq) | |
458 | { | |
459 | /* nothing */ | |
460 | } | |
461 | ||
462 | static void post_free_irq(struct net_device *dev, int irq) | |
463 | { | |
464 | /* nothing */ | |
465 | } | |
466 | ||
467 | static void napi_clear_rx_event(struct net_device *dev) | |
468 | { | |
469 | struct fs_enet_private *fep = netdev_priv(dev); | |
470 | fcc_t *fccp = fep->fcc.fccp; | |
471 | ||
472 | W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK); | |
473 | } | |
474 | ||
475 | static void napi_enable_rx(struct net_device *dev) | |
476 | { | |
477 | struct fs_enet_private *fep = netdev_priv(dev); | |
478 | fcc_t *fccp = fep->fcc.fccp; | |
479 | ||
480 | S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK); | |
481 | } | |
482 | ||
483 | static void napi_disable_rx(struct net_device *dev) | |
484 | { | |
485 | struct fs_enet_private *fep = netdev_priv(dev); | |
486 | fcc_t *fccp = fep->fcc.fccp; | |
487 | ||
488 | C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK); | |
489 | } | |
490 | ||
491 | static void rx_bd_done(struct net_device *dev) | |
492 | { | |
493 | /* nothing */ | |
494 | } | |
495 | ||
496 | static void tx_kickstart(struct net_device *dev) | |
497 | { | |
5b4b8454 VB |
498 | struct fs_enet_private *fep = netdev_priv(dev); |
499 | fcc_t *fccp = fep->fcc.fccp; | |
500 | ||
501 | S32(fccp, fcc_ftodr, 0x80); | |
48257c4f PA |
502 | } |
503 | ||
504 | static u32 get_int_events(struct net_device *dev) | |
505 | { | |
506 | struct fs_enet_private *fep = netdev_priv(dev); | |
507 | fcc_t *fccp = fep->fcc.fccp; | |
508 | ||
509 | return (u32)R16(fccp, fcc_fcce); | |
510 | } | |
511 | ||
512 | static void clear_int_events(struct net_device *dev, u32 int_events) | |
513 | { | |
514 | struct fs_enet_private *fep = netdev_priv(dev); | |
515 | fcc_t *fccp = fep->fcc.fccp; | |
516 | ||
517 | W16(fccp, fcc_fcce, int_events & 0xffff); | |
518 | } | |
519 | ||
520 | static void ev_error(struct net_device *dev, u32 int_events) | |
521 | { | |
522 | printk(KERN_WARNING DRV_MODULE_NAME | |
523 | ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events); | |
524 | } | |
525 | ||
526 | int get_regs(struct net_device *dev, void *p, int *sizep) | |
527 | { | |
528 | struct fs_enet_private *fep = netdev_priv(dev); | |
529 | ||
530 | if (*sizep < sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t)) | |
531 | return -EINVAL; | |
532 | ||
533 | memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t)); | |
534 | p = (char *)p + sizeof(fcc_t); | |
535 | ||
536 | memcpy_fromio(p, fep->fcc.fcccp, sizeof(fcc_c_t)); | |
537 | p = (char *)p + sizeof(fcc_c_t); | |
538 | ||
539 | memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t)); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | int get_regs_len(struct net_device *dev) | |
545 | { | |
546 | return sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t); | |
547 | } | |
548 | ||
549 | /* Some transmit errors cause the transmitter to shut | |
550 | * down. We now issue a restart transmit. Since the | |
551 | * errors close the BD and update the pointers, the restart | |
552 | * _should_ pick up without having to reset any of our | |
553 | * pointers either. Also, To workaround 8260 device erratum | |
554 | * CPM37, we must disable and then re-enable the transmitter | |
555 | * following a Late Collision, Underrun, or Retry Limit error. | |
556 | */ | |
557 | void tx_restart(struct net_device *dev) | |
558 | { | |
559 | struct fs_enet_private *fep = netdev_priv(dev); | |
560 | fcc_t *fccp = fep->fcc.fccp; | |
561 | ||
562 | C32(fccp, fcc_gfmr, FCC_GFMR_ENT); | |
563 | udelay(10); | |
564 | S32(fccp, fcc_gfmr, FCC_GFMR_ENT); | |
565 | ||
566 | fcc_cr_cmd(fep, 0x0C, CPM_CR_RESTART_TX); | |
567 | } | |
568 | ||
569 | /*************************************************************************/ | |
570 | ||
571 | const struct fs_ops fs_fcc_ops = { | |
572 | .setup_data = setup_data, | |
573 | .cleanup_data = cleanup_data, | |
574 | .set_multicast_list = set_multicast_list, | |
575 | .restart = restart, | |
576 | .stop = stop, | |
577 | .pre_request_irq = pre_request_irq, | |
578 | .post_free_irq = post_free_irq, | |
579 | .napi_clear_rx_event = napi_clear_rx_event, | |
580 | .napi_enable_rx = napi_enable_rx, | |
581 | .napi_disable_rx = napi_disable_rx, | |
582 | .rx_bd_done = rx_bd_done, | |
583 | .tx_kickstart = tx_kickstart, | |
584 | .get_int_events = get_int_events, | |
585 | .clear_int_events = clear_int_events, | |
586 | .ev_error = ev_error, | |
587 | .get_regs = get_regs, | |
588 | .get_regs_len = get_regs_len, | |
589 | .tx_restart = tx_restart, | |
590 | .allocate_bd = allocate_bd, | |
591 | .free_bd = free_bd, | |
592 | }; |