Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
5 | * This version of the driver is specific to the FADS implementation, | |
6 | * since the board contains control registers external to the processor | |
7 | * for the control of the LevelOne LXT970 transceiver. The MPC860T manual | |
8 | * describes connections using the internal parallel port I/O, which | |
9 | * is basically all of Port D. | |
10 | * | |
7dd6a2aa | 11 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
12 | * pages and then divide them into 2K frame buffers. This way I know I |
13 | * have buffers large enough to hold one frame within one buffer descriptor. | |
14 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
15 | * will be much more memory efficient and will easily handle lots of | |
16 | * small packets. | |
17 | * | |
18 | * Much better multiple PHY support by Magnus Damm. | |
19 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
20 | * | |
562d2f8c GU |
21 | * Support for FEC controller of ColdFire processors. |
22 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
23 | * |
24 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 25 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
26 | */ |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/kernel.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/ptrace.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/workqueue.h> | |
44 | #include <linux/bitops.h> | |
45 | ||
46 | #include <asm/irq.h> | |
47 | #include <asm/uaccess.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/pgtable.h> | |
080853af | 50 | #include <asm/cacheflush.h> |
1da177e4 | 51 | |
7dd6a2aa | 52 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ |
562d2f8c | 53 | defined(CONFIG_M5272) || defined(CONFIG_M528x) || \ |
6b265293 | 54 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
1da177e4 LT |
55 | #include <asm/coldfire.h> |
56 | #include <asm/mcfsim.h> | |
57 | #include "fec.h" | |
58 | #else | |
59 | #include <asm/8xx_immap.h> | |
60 | #include <asm/mpc8xx.h> | |
61 | #include "commproc.h" | |
62 | #endif | |
63 | ||
64 | #if defined(CONFIG_FEC2) | |
65 | #define FEC_MAX_PORTS 2 | |
66 | #else | |
67 | #define FEC_MAX_PORTS 1 | |
68 | #endif | |
69 | ||
70 | /* | |
71 | * Define the fixed address of the FEC hardware. | |
72 | */ | |
73 | static unsigned int fec_hw[] = { | |
74 | #if defined(CONFIG_M5272) | |
75 | (MCF_MBAR + 0x840), | |
76 | #elif defined(CONFIG_M527x) | |
77 | (MCF_MBAR + 0x1000), | |
78 | (MCF_MBAR + 0x1800), | |
7dd6a2aa | 79 | #elif defined(CONFIG_M523x) || defined(CONFIG_M528x) |
1da177e4 | 80 | (MCF_MBAR + 0x1000), |
562d2f8c GU |
81 | #elif defined(CONFIG_M520x) |
82 | (MCF_MBAR+0x30000), | |
6b265293 MW |
83 | #elif defined(CONFIG_M532x) |
84 | (MCF_MBAR+0xfc030000), | |
1da177e4 LT |
85 | #else |
86 | &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec), | |
87 | #endif | |
88 | }; | |
89 | ||
90 | static unsigned char fec_mac_default[] = { | |
91 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
92 | }; | |
93 | ||
94 | /* | |
95 | * Some hardware gets it MAC address out of local flash memory. | |
96 | * if this is non-zero then assume it is the address to get MAC from. | |
97 | */ | |
98 | #if defined(CONFIG_NETtel) | |
99 | #define FEC_FLASHMAC 0xf0006006 | |
100 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
101 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
102 | #elif defined(CONFIG_CANCam) |
103 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
104 | #elif defined (CONFIG_M5272C3) |
105 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
106 | #elif defined(CONFIG_MOD5272) | |
107 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
108 | #else |
109 | #define FEC_FLASHMAC 0 | |
110 | #endif | |
111 | ||
1da177e4 LT |
112 | /* Forward declarations of some structures to support different PHYs |
113 | */ | |
114 | ||
115 | typedef struct { | |
116 | uint mii_data; | |
117 | void (*funct)(uint mii_reg, struct net_device *dev); | |
118 | } phy_cmd_t; | |
119 | ||
120 | typedef struct { | |
121 | uint id; | |
122 | char *name; | |
123 | ||
124 | const phy_cmd_t *config; | |
125 | const phy_cmd_t *startup; | |
126 | const phy_cmd_t *ack_int; | |
127 | const phy_cmd_t *shutdown; | |
128 | } phy_info_t; | |
129 | ||
130 | /* The number of Tx and Rx buffers. These are allocated from the page | |
131 | * pool. The code may assume these are power of two, so it it best | |
132 | * to keep them that size. | |
133 | * We don't need to allocate pages for the transmitter. We just use | |
134 | * the skbuffer directly. | |
135 | */ | |
136 | #define FEC_ENET_RX_PAGES 8 | |
137 | #define FEC_ENET_RX_FRSIZE 2048 | |
138 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
139 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
140 | #define FEC_ENET_TX_FRSIZE 2048 | |
141 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
142 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
143 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
144 | ||
562d2f8c | 145 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 146 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
147 | #endif |
148 | ||
1da177e4 LT |
149 | /* Interrupt events/masks. |
150 | */ | |
151 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ | |
152 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
153 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
154 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
155 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
156 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
157 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
158 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
159 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
160 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
161 | ||
162 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
163 | */ | |
164 | #define PKT_MAXBUF_SIZE 1518 | |
165 | #define PKT_MINBUF_SIZE 64 | |
166 | #define PKT_MAXBLR_SIZE 1520 | |
167 | ||
168 | ||
169 | /* | |
6b265293 | 170 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
171 | * size bits. Other FEC hardware does not, so we need to take that into |
172 | * account when setting it. | |
173 | */ | |
562d2f8c | 174 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
6b265293 | 175 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
1da177e4 LT |
176 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
177 | #else | |
178 | #define OPT_FRAME_SIZE 0 | |
179 | #endif | |
180 | ||
181 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
182 | * tx_bd_base always point to the base of the buffer descriptors. The | |
183 | * cur_rx and cur_tx point to the currently available buffer. | |
184 | * The dirty_tx tracks the current buffer that is being sent by the | |
185 | * controller. The cur_tx and dirty_tx are equal under both completely | |
186 | * empty and completely full conditions. The empty/ready indicator in | |
187 | * the buffer descriptor determines the actual condition. | |
188 | */ | |
189 | struct fec_enet_private { | |
190 | /* Hardware registers of the FEC device */ | |
191 | volatile fec_t *hwp; | |
192 | ||
cb84d6e7 GU |
193 | struct net_device *netdev; |
194 | ||
1da177e4 LT |
195 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
196 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
197 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
198 | ushort skb_cur; | |
199 | ushort skb_dirty; | |
200 | ||
201 | /* CPM dual port RAM relative addresses. | |
202 | */ | |
203 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ | |
204 | cbd_t *tx_bd_base; | |
205 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ | |
206 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ | |
207 | struct net_device_stats stats; | |
208 | uint tx_full; | |
209 | spinlock_t lock; | |
210 | ||
211 | uint phy_id; | |
212 | uint phy_id_done; | |
213 | uint phy_status; | |
214 | uint phy_speed; | |
7dd6a2aa | 215 | phy_info_t const *phy; |
1da177e4 LT |
216 | struct work_struct phy_task; |
217 | ||
218 | uint sequence_done; | |
219 | uint mii_phy_task_queued; | |
220 | ||
221 | uint phy_addr; | |
222 | ||
223 | int index; | |
224 | int opened; | |
225 | int link; | |
226 | int old_link; | |
227 | int full_duplex; | |
1da177e4 LT |
228 | }; |
229 | ||
230 | static int fec_enet_open(struct net_device *dev); | |
231 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
232 | static void fec_enet_mii(struct net_device *dev); | |
7d12e780 | 233 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
234 | static void fec_enet_tx(struct net_device *dev); |
235 | static void fec_enet_rx(struct net_device *dev); | |
236 | static int fec_enet_close(struct net_device *dev); | |
237 | static struct net_device_stats *fec_enet_get_stats(struct net_device *dev); | |
238 | static void set_multicast_list(struct net_device *dev); | |
239 | static void fec_restart(struct net_device *dev, int duplex); | |
240 | static void fec_stop(struct net_device *dev); | |
241 | static void fec_set_mac_address(struct net_device *dev); | |
242 | ||
243 | ||
244 | /* MII processing. We keep this as simple as possible. Requests are | |
245 | * placed on the list (if there is room). When the request is finished | |
246 | * by the MII, an optional function may be called. | |
247 | */ | |
248 | typedef struct mii_list { | |
249 | uint mii_regval; | |
250 | void (*mii_func)(uint val, struct net_device *dev); | |
251 | struct mii_list *mii_next; | |
252 | } mii_list_t; | |
253 | ||
254 | #define NMII 20 | |
7dd6a2aa GU |
255 | static mii_list_t mii_cmds[NMII]; |
256 | static mii_list_t *mii_free; | |
257 | static mii_list_t *mii_head; | |
258 | static mii_list_t *mii_tail; | |
1da177e4 | 259 | |
6aa20a22 | 260 | static int mii_queue(struct net_device *dev, int request, |
1da177e4 LT |
261 | void (*func)(uint, struct net_device *)); |
262 | ||
263 | /* Make MII read/write commands for the FEC. | |
264 | */ | |
265 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
266 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | |
267 | (VAL & 0xffff)) | |
268 | #define mk_mii_end 0 | |
269 | ||
270 | /* Transmitter timeout. | |
271 | */ | |
272 | #define TX_TIMEOUT (2*HZ) | |
273 | ||
274 | /* Register definitions for the PHY. | |
275 | */ | |
276 | ||
277 | #define MII_REG_CR 0 /* Control Register */ | |
278 | #define MII_REG_SR 1 /* Status Register */ | |
279 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | |
280 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | |
6aa20a22 | 281 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
1da177e4 LT |
282 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
283 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | |
284 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | |
285 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | |
286 | ||
287 | /* values for phy_status */ | |
288 | ||
289 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | |
290 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | |
291 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | |
292 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | |
6aa20a22 | 293 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
1da177e4 | 294 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
6aa20a22 | 295 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
1da177e4 LT |
296 | |
297 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | |
298 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | |
299 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | |
300 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | |
301 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | |
6aa20a22 | 302 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
1da177e4 | 303 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
6aa20a22 | 304 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
1da177e4 LT |
305 | |
306 | ||
307 | static int | |
308 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
309 | { | |
310 | struct fec_enet_private *fep; | |
311 | volatile fec_t *fecp; | |
312 | volatile cbd_t *bdp; | |
0e702ab3 | 313 | unsigned short status; |
1da177e4 LT |
314 | |
315 | fep = netdev_priv(dev); | |
316 | fecp = (volatile fec_t*)dev->base_addr; | |
317 | ||
318 | if (!fep->link) { | |
319 | /* Link is down or autonegotiation is in progress. */ | |
320 | return 1; | |
321 | } | |
322 | ||
323 | /* Fill in a Tx ring entry */ | |
324 | bdp = fep->cur_tx; | |
325 | ||
0e702ab3 | 326 | status = bdp->cbd_sc; |
1da177e4 | 327 | #ifndef final_version |
0e702ab3 | 328 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
329 | /* Ooops. All transmit buffers are full. Bail out. |
330 | * This should not happen, since dev->tbusy should be set. | |
331 | */ | |
332 | printk("%s: tx queue full!.\n", dev->name); | |
333 | return 1; | |
334 | } | |
335 | #endif | |
336 | ||
337 | /* Clear all of the status flags. | |
338 | */ | |
0e702ab3 | 339 | status &= ~BD_ENET_TX_STATS; |
1da177e4 LT |
340 | |
341 | /* Set buffer length and buffer pointer. | |
342 | */ | |
343 | bdp->cbd_bufaddr = __pa(skb->data); | |
344 | bdp->cbd_datlen = skb->len; | |
345 | ||
346 | /* | |
347 | * On some FEC implementations data must be aligned on | |
348 | * 4-byte boundaries. Use bounce buffers to copy data | |
349 | * and get it aligned. Ugh. | |
350 | */ | |
351 | if (bdp->cbd_bufaddr & 0x3) { | |
352 | unsigned int index; | |
353 | index = bdp - fep->tx_bd_base; | |
354 | memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen); | |
355 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); | |
356 | } | |
357 | ||
358 | /* Save skb pointer. | |
359 | */ | |
360 | fep->tx_skbuff[fep->skb_cur] = skb; | |
361 | ||
362 | fep->stats.tx_bytes += skb->len; | |
363 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; | |
6aa20a22 | 364 | |
1da177e4 LT |
365 | /* Push the data cache so the CPM does not get stale memory |
366 | * data. | |
367 | */ | |
368 | flush_dcache_range((unsigned long)skb->data, | |
369 | (unsigned long)skb->data + skb->len); | |
370 | ||
371 | spin_lock_irq(&fep->lock); | |
372 | ||
0e702ab3 GU |
373 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
374 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 LT |
375 | */ |
376 | ||
0e702ab3 | 377 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 378 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 379 | bdp->cbd_sc = status; |
1da177e4 LT |
380 | |
381 | dev->trans_start = jiffies; | |
382 | ||
383 | /* Trigger transmission start */ | |
0e702ab3 | 384 | fecp->fec_x_des_active = 0; |
1da177e4 LT |
385 | |
386 | /* If this was the last BD in the ring, start at the beginning again. | |
387 | */ | |
0e702ab3 | 388 | if (status & BD_ENET_TX_WRAP) { |
1da177e4 LT |
389 | bdp = fep->tx_bd_base; |
390 | } else { | |
391 | bdp++; | |
392 | } | |
393 | ||
394 | if (bdp == fep->dirty_tx) { | |
395 | fep->tx_full = 1; | |
396 | netif_stop_queue(dev); | |
397 | } | |
398 | ||
399 | fep->cur_tx = (cbd_t *)bdp; | |
400 | ||
401 | spin_unlock_irq(&fep->lock); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | static void | |
407 | fec_timeout(struct net_device *dev) | |
408 | { | |
409 | struct fec_enet_private *fep = netdev_priv(dev); | |
410 | ||
411 | printk("%s: transmit timed out.\n", dev->name); | |
412 | fep->stats.tx_errors++; | |
413 | #ifndef final_version | |
414 | { | |
415 | int i; | |
416 | cbd_t *bdp; | |
417 | ||
418 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | |
419 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | |
420 | (unsigned long)fep->dirty_tx, | |
421 | (unsigned long)fep->cur_rx); | |
422 | ||
423 | bdp = fep->tx_bd_base; | |
424 | printk(" tx: %u buffers\n", TX_RING_SIZE); | |
425 | for (i = 0 ; i < TX_RING_SIZE; i++) { | |
6aa20a22 | 426 | printk(" %08x: %04x %04x %08x\n", |
1da177e4 LT |
427 | (uint) bdp, |
428 | bdp->cbd_sc, | |
429 | bdp->cbd_datlen, | |
430 | (int) bdp->cbd_bufaddr); | |
431 | bdp++; | |
432 | } | |
433 | ||
434 | bdp = fep->rx_bd_base; | |
435 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); | |
436 | for (i = 0 ; i < RX_RING_SIZE; i++) { | |
437 | printk(" %08x: %04x %04x %08x\n", | |
438 | (uint) bdp, | |
439 | bdp->cbd_sc, | |
440 | bdp->cbd_datlen, | |
441 | (int) bdp->cbd_bufaddr); | |
442 | bdp++; | |
443 | } | |
444 | } | |
445 | #endif | |
7dd6a2aa | 446 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
447 | netif_wake_queue(dev); |
448 | } | |
449 | ||
450 | /* The interrupt handler. | |
451 | * This is called from the MPC core interrupt. | |
452 | */ | |
453 | static irqreturn_t | |
7d12e780 | 454 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
455 | { |
456 | struct net_device *dev = dev_id; | |
457 | volatile fec_t *fecp; | |
458 | uint int_events; | |
459 | int handled = 0; | |
460 | ||
461 | fecp = (volatile fec_t*)dev->base_addr; | |
462 | ||
463 | /* Get the interrupt events that caused us to be here. | |
464 | */ | |
465 | while ((int_events = fecp->fec_ievent) != 0) { | |
466 | fecp->fec_ievent = int_events; | |
467 | ||
468 | /* Handle receive event in its own function. | |
469 | */ | |
470 | if (int_events & FEC_ENET_RXF) { | |
471 | handled = 1; | |
472 | fec_enet_rx(dev); | |
473 | } | |
474 | ||
475 | /* Transmit OK, or non-fatal error. Update the buffer | |
476 | descriptors. FEC handles all errors, we just discover | |
477 | them as part of the transmit process. | |
478 | */ | |
479 | if (int_events & FEC_ENET_TXF) { | |
480 | handled = 1; | |
481 | fec_enet_tx(dev); | |
482 | } | |
483 | ||
484 | if (int_events & FEC_ENET_MII) { | |
485 | handled = 1; | |
486 | fec_enet_mii(dev); | |
487 | } | |
6aa20a22 | 488 | |
1da177e4 LT |
489 | } |
490 | return IRQ_RETVAL(handled); | |
491 | } | |
492 | ||
493 | ||
494 | static void | |
495 | fec_enet_tx(struct net_device *dev) | |
496 | { | |
497 | struct fec_enet_private *fep; | |
498 | volatile cbd_t *bdp; | |
0e702ab3 | 499 | unsigned short status; |
1da177e4 LT |
500 | struct sk_buff *skb; |
501 | ||
502 | fep = netdev_priv(dev); | |
503 | spin_lock(&fep->lock); | |
504 | bdp = fep->dirty_tx; | |
505 | ||
0e702ab3 | 506 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
1da177e4 LT |
507 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
508 | ||
509 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
510 | /* Check for errors. */ | |
0e702ab3 | 511 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
512 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
513 | BD_ENET_TX_CSL)) { | |
514 | fep->stats.tx_errors++; | |
0e702ab3 | 515 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
1da177e4 | 516 | fep->stats.tx_heartbeat_errors++; |
0e702ab3 | 517 | if (status & BD_ENET_TX_LC) /* Late collision */ |
1da177e4 | 518 | fep->stats.tx_window_errors++; |
0e702ab3 | 519 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
1da177e4 | 520 | fep->stats.tx_aborted_errors++; |
0e702ab3 | 521 | if (status & BD_ENET_TX_UN) /* Underrun */ |
1da177e4 | 522 | fep->stats.tx_fifo_errors++; |
0e702ab3 | 523 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
1da177e4 LT |
524 | fep->stats.tx_carrier_errors++; |
525 | } else { | |
526 | fep->stats.tx_packets++; | |
527 | } | |
528 | ||
529 | #ifndef final_version | |
0e702ab3 | 530 | if (status & BD_ENET_TX_READY) |
1da177e4 LT |
531 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
532 | #endif | |
533 | /* Deferred means some collisions occurred during transmit, | |
534 | * but we eventually sent the packet OK. | |
535 | */ | |
0e702ab3 | 536 | if (status & BD_ENET_TX_DEF) |
1da177e4 | 537 | fep->stats.collisions++; |
6aa20a22 | 538 | |
1da177e4 LT |
539 | /* Free the sk buffer associated with this last transmit. |
540 | */ | |
541 | dev_kfree_skb_any(skb); | |
542 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
543 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 544 | |
1da177e4 LT |
545 | /* Update pointer to next buffer descriptor to be transmitted. |
546 | */ | |
0e702ab3 | 547 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
548 | bdp = fep->tx_bd_base; |
549 | else | |
550 | bdp++; | |
6aa20a22 | 551 | |
1da177e4 LT |
552 | /* Since we have freed up a buffer, the ring is no longer |
553 | * full. | |
554 | */ | |
555 | if (fep->tx_full) { | |
556 | fep->tx_full = 0; | |
557 | if (netif_queue_stopped(dev)) | |
558 | netif_wake_queue(dev); | |
559 | } | |
560 | } | |
561 | fep->dirty_tx = (cbd_t *)bdp; | |
562 | spin_unlock(&fep->lock); | |
563 | } | |
564 | ||
565 | ||
566 | /* During a receive, the cur_rx points to the current incoming buffer. | |
567 | * When we update through the ring, if the next incoming buffer has | |
568 | * not been given to the system, we just set the empty indicator, | |
569 | * effectively tossing the packet. | |
570 | */ | |
571 | static void | |
572 | fec_enet_rx(struct net_device *dev) | |
573 | { | |
574 | struct fec_enet_private *fep; | |
575 | volatile fec_t *fecp; | |
576 | volatile cbd_t *bdp; | |
0e702ab3 | 577 | unsigned short status; |
1da177e4 LT |
578 | struct sk_buff *skb; |
579 | ushort pkt_len; | |
580 | __u8 *data; | |
6aa20a22 | 581 | |
0e702ab3 GU |
582 | #ifdef CONFIG_M532x |
583 | flush_cache_all(); | |
6aa20a22 | 584 | #endif |
1da177e4 LT |
585 | |
586 | fep = netdev_priv(dev); | |
587 | fecp = (volatile fec_t*)dev->base_addr; | |
588 | ||
589 | /* First, grab all of the stats for the incoming packet. | |
590 | * These get messed up if we get called due to a busy condition. | |
591 | */ | |
592 | bdp = fep->cur_rx; | |
593 | ||
0e702ab3 | 594 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 LT |
595 | |
596 | #ifndef final_version | |
597 | /* Since we have allocated space to hold a complete frame, | |
598 | * the last indicator should be set. | |
599 | */ | |
0e702ab3 | 600 | if ((status & BD_ENET_RX_LAST) == 0) |
1da177e4 LT |
601 | printk("FEC ENET: rcv is not +last\n"); |
602 | #endif | |
603 | ||
604 | if (!fep->opened) | |
605 | goto rx_processing_done; | |
606 | ||
607 | /* Check for errors. */ | |
0e702ab3 | 608 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
1da177e4 | 609 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
6aa20a22 | 610 | fep->stats.rx_errors++; |
0e702ab3 | 611 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
1da177e4 LT |
612 | /* Frame too long or too short. */ |
613 | fep->stats.rx_length_errors++; | |
614 | } | |
0e702ab3 | 615 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
1da177e4 | 616 | fep->stats.rx_frame_errors++; |
0e702ab3 | 617 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
1da177e4 | 618 | fep->stats.rx_crc_errors++; |
0e702ab3 GU |
619 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
620 | fep->stats.rx_fifo_errors++; | |
1da177e4 LT |
621 | } |
622 | ||
623 | /* Report late collisions as a frame error. | |
624 | * On this error, the BD is closed, but we don't know what we | |
625 | * have in the buffer. So, just drop this frame on the floor. | |
626 | */ | |
0e702ab3 | 627 | if (status & BD_ENET_RX_CL) { |
1da177e4 LT |
628 | fep->stats.rx_errors++; |
629 | fep->stats.rx_frame_errors++; | |
630 | goto rx_processing_done; | |
631 | } | |
632 | ||
633 | /* Process the incoming frame. | |
634 | */ | |
635 | fep->stats.rx_packets++; | |
636 | pkt_len = bdp->cbd_datlen; | |
637 | fep->stats.rx_bytes += pkt_len; | |
638 | data = (__u8*)__va(bdp->cbd_bufaddr); | |
639 | ||
640 | /* This does 16 byte alignment, exactly what we need. | |
641 | * The packet length includes FCS, but we don't want to | |
642 | * include that when passing upstream as it messes up | |
643 | * bridging applications. | |
644 | */ | |
645 | skb = dev_alloc_skb(pkt_len-4); | |
646 | ||
647 | if (skb == NULL) { | |
648 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | |
649 | fep->stats.rx_dropped++; | |
650 | } else { | |
1da177e4 | 651 | skb_put(skb,pkt_len-4); /* Make room */ |
8c7b7faa | 652 | skb_copy_to_linear_data(skb, data, pkt_len-4); |
1da177e4 LT |
653 | skb->protocol=eth_type_trans(skb,dev); |
654 | netif_rx(skb); | |
655 | } | |
656 | rx_processing_done: | |
657 | ||
658 | /* Clear the status flags for this buffer. | |
659 | */ | |
0e702ab3 | 660 | status &= ~BD_ENET_RX_STATS; |
1da177e4 LT |
661 | |
662 | /* Mark the buffer empty. | |
663 | */ | |
0e702ab3 GU |
664 | status |= BD_ENET_RX_EMPTY; |
665 | bdp->cbd_sc = status; | |
1da177e4 LT |
666 | |
667 | /* Update BD pointer to next entry. | |
668 | */ | |
0e702ab3 | 669 | if (status & BD_ENET_RX_WRAP) |
1da177e4 LT |
670 | bdp = fep->rx_bd_base; |
671 | else | |
672 | bdp++; | |
6aa20a22 | 673 | |
1da177e4 LT |
674 | #if 1 |
675 | /* Doing this here will keep the FEC running while we process | |
676 | * incoming frames. On a heavily loaded network, we should be | |
677 | * able to keep up at the expense of system resources. | |
678 | */ | |
0e702ab3 | 679 | fecp->fec_r_des_active = 0; |
1da177e4 | 680 | #endif |
0e702ab3 | 681 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
1da177e4 LT |
682 | fep->cur_rx = (cbd_t *)bdp; |
683 | ||
684 | #if 0 | |
685 | /* Doing this here will allow us to process all frames in the | |
686 | * ring before the FEC is allowed to put more there. On a heavily | |
687 | * loaded network, some frames may be lost. Unfortunately, this | |
688 | * increases the interrupt overhead since we can potentially work | |
689 | * our way back to the interrupt return only to come right back | |
690 | * here. | |
691 | */ | |
0e702ab3 | 692 | fecp->fec_r_des_active = 0; |
1da177e4 LT |
693 | #endif |
694 | } | |
695 | ||
696 | ||
0e702ab3 | 697 | /* called from interrupt context */ |
1da177e4 LT |
698 | static void |
699 | fec_enet_mii(struct net_device *dev) | |
700 | { | |
701 | struct fec_enet_private *fep; | |
702 | volatile fec_t *ep; | |
703 | mii_list_t *mip; | |
704 | uint mii_reg; | |
705 | ||
706 | fep = netdev_priv(dev); | |
707 | ep = fep->hwp; | |
708 | mii_reg = ep->fec_mii_data; | |
0e702ab3 GU |
709 | |
710 | spin_lock(&fep->lock); | |
6aa20a22 | 711 | |
1da177e4 LT |
712 | if ((mip = mii_head) == NULL) { |
713 | printk("MII and no head!\n"); | |
0e702ab3 | 714 | goto unlock; |
1da177e4 LT |
715 | } |
716 | ||
717 | if (mip->mii_func != NULL) | |
718 | (*(mip->mii_func))(mii_reg, dev); | |
719 | ||
720 | mii_head = mip->mii_next; | |
721 | mip->mii_next = mii_free; | |
722 | mii_free = mip; | |
723 | ||
724 | if ((mip = mii_head) != NULL) | |
725 | ep->fec_mii_data = mip->mii_regval; | |
0e702ab3 GU |
726 | |
727 | unlock: | |
728 | spin_unlock(&fep->lock); | |
1da177e4 LT |
729 | } |
730 | ||
731 | static int | |
732 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | |
733 | { | |
734 | struct fec_enet_private *fep; | |
735 | unsigned long flags; | |
736 | mii_list_t *mip; | |
737 | int retval; | |
738 | ||
739 | /* Add PHY address to register command. | |
740 | */ | |
741 | fep = netdev_priv(dev); | |
742 | regval |= fep->phy_addr << 23; | |
743 | ||
744 | retval = 0; | |
745 | ||
0e702ab3 | 746 | spin_lock_irqsave(&fep->lock,flags); |
1da177e4 LT |
747 | |
748 | if ((mip = mii_free) != NULL) { | |
749 | mii_free = mip->mii_next; | |
750 | mip->mii_regval = regval; | |
751 | mip->mii_func = func; | |
752 | mip->mii_next = NULL; | |
753 | if (mii_head) { | |
754 | mii_tail->mii_next = mip; | |
755 | mii_tail = mip; | |
756 | } | |
757 | else { | |
758 | mii_head = mii_tail = mip; | |
759 | fep->hwp->fec_mii_data = regval; | |
760 | } | |
761 | } | |
762 | else { | |
763 | retval = 1; | |
764 | } | |
765 | ||
0e702ab3 | 766 | spin_unlock_irqrestore(&fep->lock,flags); |
1da177e4 LT |
767 | |
768 | return(retval); | |
769 | } | |
770 | ||
771 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | |
772 | { | |
773 | int k; | |
774 | ||
775 | if(!c) | |
776 | return; | |
777 | ||
778 | for(k = 0; (c+k)->mii_data != mk_mii_end; k++) { | |
779 | mii_queue(dev, (c+k)->mii_data, (c+k)->funct); | |
780 | } | |
781 | } | |
782 | ||
783 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | |
784 | { | |
785 | struct fec_enet_private *fep = netdev_priv(dev); | |
786 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 787 | uint status; |
1da177e4 | 788 | |
7dd6a2aa | 789 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
1da177e4 LT |
790 | |
791 | if (mii_reg & 0x0004) | |
7dd6a2aa | 792 | status |= PHY_STAT_LINK; |
1da177e4 | 793 | if (mii_reg & 0x0010) |
7dd6a2aa | 794 | status |= PHY_STAT_FAULT; |
1da177e4 | 795 | if (mii_reg & 0x0020) |
7dd6a2aa GU |
796 | status |= PHY_STAT_ANC; |
797 | ||
798 | *s = status; | |
1da177e4 LT |
799 | } |
800 | ||
801 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | |
802 | { | |
803 | struct fec_enet_private *fep = netdev_priv(dev); | |
804 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 805 | uint status; |
1da177e4 | 806 | |
7dd6a2aa | 807 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
1da177e4 LT |
808 | |
809 | if (mii_reg & 0x1000) | |
7dd6a2aa | 810 | status |= PHY_CONF_ANE; |
1da177e4 | 811 | if (mii_reg & 0x4000) |
7dd6a2aa GU |
812 | status |= PHY_CONF_LOOP; |
813 | *s = status; | |
1da177e4 LT |
814 | } |
815 | ||
816 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | |
817 | { | |
818 | struct fec_enet_private *fep = netdev_priv(dev); | |
819 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 820 | uint status; |
1da177e4 | 821 | |
7dd6a2aa | 822 | status = *s & ~(PHY_CONF_SPMASK); |
1da177e4 LT |
823 | |
824 | if (mii_reg & 0x0020) | |
7dd6a2aa | 825 | status |= PHY_CONF_10HDX; |
1da177e4 | 826 | if (mii_reg & 0x0040) |
7dd6a2aa | 827 | status |= PHY_CONF_10FDX; |
1da177e4 | 828 | if (mii_reg & 0x0080) |
7dd6a2aa | 829 | status |= PHY_CONF_100HDX; |
1da177e4 | 830 | if (mii_reg & 0x00100) |
7dd6a2aa GU |
831 | status |= PHY_CONF_100FDX; |
832 | *s = status; | |
1da177e4 LT |
833 | } |
834 | ||
835 | /* ------------------------------------------------------------------------- */ | |
836 | /* The Level one LXT970 is used by many boards */ | |
837 | ||
838 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | |
839 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
840 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
841 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
842 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | |
843 | ||
844 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | |
845 | { | |
846 | struct fec_enet_private *fep = netdev_priv(dev); | |
847 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 848 | uint status; |
1da177e4 | 849 | |
7dd6a2aa | 850 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
851 | if (mii_reg & 0x0800) { |
852 | if (mii_reg & 0x1000) | |
7dd6a2aa | 853 | status |= PHY_STAT_100FDX; |
1da177e4 | 854 | else |
7dd6a2aa | 855 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
856 | } else { |
857 | if (mii_reg & 0x1000) | |
7dd6a2aa | 858 | status |= PHY_STAT_10FDX; |
1da177e4 | 859 | else |
7dd6a2aa | 860 | status |= PHY_STAT_10HDX; |
1da177e4 | 861 | } |
7dd6a2aa | 862 | *s = status; |
1da177e4 LT |
863 | } |
864 | ||
7dd6a2aa | 865 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
1da177e4 LT |
866 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
867 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
868 | { mk_mii_end, } | |
7dd6a2aa GU |
869 | }; |
870 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
871 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
872 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
873 | { mk_mii_end, } | |
7dd6a2aa GU |
874 | }; |
875 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { | |
1da177e4 LT |
876 | /* read SR and ISR to acknowledge */ |
877 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
878 | { mk_mii_read(MII_LXT970_ISR), NULL }, | |
879 | ||
880 | /* find out the current status */ | |
881 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | |
882 | { mk_mii_end, } | |
7dd6a2aa GU |
883 | }; |
884 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
885 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
886 | { mk_mii_end, } | |
7dd6a2aa GU |
887 | }; |
888 | static phy_info_t const phy_info_lxt970 = { | |
6aa20a22 | 889 | .id = 0x07810000, |
7dd6a2aa GU |
890 | .name = "LXT970", |
891 | .config = phy_cmd_lxt970_config, | |
892 | .startup = phy_cmd_lxt970_startup, | |
893 | .ack_int = phy_cmd_lxt970_ack_int, | |
894 | .shutdown = phy_cmd_lxt970_shutdown | |
1da177e4 | 895 | }; |
6aa20a22 | 896 | |
1da177e4 LT |
897 | /* ------------------------------------------------------------------------- */ |
898 | /* The Level one LXT971 is used on some of my custom boards */ | |
899 | ||
900 | /* register definitions for the 971 */ | |
901 | ||
902 | #define MII_LXT971_PCR 16 /* Port Control Register */ | |
903 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | |
904 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
905 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
906 | #define MII_LXT971_LCR 20 /* LED Control Register */ | |
907 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | |
908 | ||
6aa20a22 | 909 | /* |
1da177e4 LT |
910 | * I had some nice ideas of running the MDIO faster... |
911 | * The 971 should support 8MHz and I tried it, but things acted really | |
912 | * weird, so 2.5 MHz ought to be enough for anyone... | |
913 | */ | |
914 | ||
915 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | |
916 | { | |
917 | struct fec_enet_private *fep = netdev_priv(dev); | |
918 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 919 | uint status; |
1da177e4 | 920 | |
7dd6a2aa | 921 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
1da177e4 LT |
922 | |
923 | if (mii_reg & 0x0400) { | |
924 | fep->link = 1; | |
7dd6a2aa | 925 | status |= PHY_STAT_LINK; |
1da177e4 LT |
926 | } else { |
927 | fep->link = 0; | |
928 | } | |
929 | if (mii_reg & 0x0080) | |
7dd6a2aa | 930 | status |= PHY_STAT_ANC; |
1da177e4 LT |
931 | if (mii_reg & 0x4000) { |
932 | if (mii_reg & 0x0200) | |
7dd6a2aa | 933 | status |= PHY_STAT_100FDX; |
1da177e4 | 934 | else |
7dd6a2aa | 935 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
936 | } else { |
937 | if (mii_reg & 0x0200) | |
7dd6a2aa | 938 | status |= PHY_STAT_10FDX; |
1da177e4 | 939 | else |
7dd6a2aa | 940 | status |= PHY_STAT_10HDX; |
1da177e4 LT |
941 | } |
942 | if (mii_reg & 0x0008) | |
7dd6a2aa | 943 | status |= PHY_STAT_FAULT; |
1da177e4 | 944 | |
7dd6a2aa GU |
945 | *s = status; |
946 | } | |
6aa20a22 | 947 | |
7dd6a2aa | 948 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
6aa20a22 | 949 | /* limit to 10MBit because my prototype board |
1da177e4 LT |
950 | * doesn't work with 100. */ |
951 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
952 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
953 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
954 | { mk_mii_end, } | |
7dd6a2aa GU |
955 | }; |
956 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
957 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
958 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
959 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ | |
960 | /* Somehow does the 971 tell me that the link is down | |
961 | * the first read after power-up. | |
962 | * read here to get a valid value in ack_int */ | |
6aa20a22 | 963 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 964 | { mk_mii_end, } |
7dd6a2aa GU |
965 | }; |
966 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { | |
967 | /* acknowledge the int before reading status ! */ | |
968 | { mk_mii_read(MII_LXT971_ISR), NULL }, | |
1da177e4 LT |
969 | /* find out the current status */ |
970 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
971 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
1da177e4 | 972 | { mk_mii_end, } |
7dd6a2aa GU |
973 | }; |
974 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
975 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
976 | { mk_mii_end, } | |
7dd6a2aa GU |
977 | }; |
978 | static phy_info_t const phy_info_lxt971 = { | |
6aa20a22 | 979 | .id = 0x0001378e, |
7dd6a2aa GU |
980 | .name = "LXT971", |
981 | .config = phy_cmd_lxt971_config, | |
982 | .startup = phy_cmd_lxt971_startup, | |
983 | .ack_int = phy_cmd_lxt971_ack_int, | |
984 | .shutdown = phy_cmd_lxt971_shutdown | |
1da177e4 LT |
985 | }; |
986 | ||
987 | /* ------------------------------------------------------------------------- */ | |
988 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | |
989 | ||
990 | /* register definitions */ | |
991 | ||
992 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | |
993 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | |
994 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | |
995 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | |
996 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | |
997 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | |
998 | ||
999 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | |
1000 | { | |
1001 | struct fec_enet_private *fep = netdev_priv(dev); | |
1002 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1003 | uint status; |
1da177e4 | 1004 | |
7dd6a2aa | 1005 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
1006 | |
1007 | switch((mii_reg >> 2) & 7) { | |
7dd6a2aa GU |
1008 | case 1: status |= PHY_STAT_10HDX; break; |
1009 | case 2: status |= PHY_STAT_100HDX; break; | |
1010 | case 5: status |= PHY_STAT_10FDX; break; | |
1011 | case 6: status |= PHY_STAT_100FDX; break; | |
1da177e4 LT |
1012 | } |
1013 | ||
7dd6a2aa GU |
1014 | *s = status; |
1015 | } | |
1016 | ||
1017 | static phy_cmd_t const phy_cmd_qs6612_config[] = { | |
6aa20a22 | 1018 | /* The PHY powers up isolated on the RPX, |
1da177e4 LT |
1019 | * so send a command to allow operation. |
1020 | */ | |
1021 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | |
1022 | ||
1023 | /* parse cr and anar to get some info */ | |
1024 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1025 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1026 | { mk_mii_end, } | |
7dd6a2aa GU |
1027 | }; |
1028 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1029 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
1030 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1031 | { mk_mii_end, } | |
7dd6a2aa GU |
1032 | }; |
1033 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { | |
1da177e4 LT |
1034 | /* we need to read ISR, SR and ANER to acknowledge */ |
1035 | { mk_mii_read(MII_QS6612_ISR), NULL }, | |
1036 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1037 | { mk_mii_read(MII_REG_ANER), NULL }, | |
1038 | ||
1039 | /* read pcr to get info */ | |
1040 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | |
1041 | { mk_mii_end, } | |
7dd6a2aa GU |
1042 | }; |
1043 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1044 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
1045 | { mk_mii_end, } | |
7dd6a2aa GU |
1046 | }; |
1047 | static phy_info_t const phy_info_qs6612 = { | |
6aa20a22 | 1048 | .id = 0x00181440, |
7dd6a2aa GU |
1049 | .name = "QS6612", |
1050 | .config = phy_cmd_qs6612_config, | |
1051 | .startup = phy_cmd_qs6612_startup, | |
1052 | .ack_int = phy_cmd_qs6612_ack_int, | |
1053 | .shutdown = phy_cmd_qs6612_shutdown | |
1da177e4 LT |
1054 | }; |
1055 | ||
1056 | /* ------------------------------------------------------------------------- */ | |
1057 | /* AMD AM79C874 phy */ | |
1058 | ||
1059 | /* register definitions for the 874 */ | |
1060 | ||
1061 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ | |
1062 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ | |
1063 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | |
1064 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ | |
1065 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ | |
1066 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | |
1067 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ | |
1068 | ||
1069 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) | |
1070 | { | |
1071 | struct fec_enet_private *fep = netdev_priv(dev); | |
1072 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1073 | uint status; |
1da177e4 | 1074 | |
7dd6a2aa | 1075 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
1da177e4 LT |
1076 | |
1077 | if (mii_reg & 0x0080) | |
7dd6a2aa | 1078 | status |= PHY_STAT_ANC; |
1da177e4 | 1079 | if (mii_reg & 0x0400) |
7dd6a2aa | 1080 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
1da177e4 | 1081 | else |
7dd6a2aa GU |
1082 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
1083 | ||
1084 | *s = status; | |
1da177e4 LT |
1085 | } |
1086 | ||
7dd6a2aa | 1087 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
1da177e4 LT |
1088 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1089 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1090 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1091 | { mk_mii_end, } | |
7dd6a2aa GU |
1092 | }; |
1093 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1094 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
1095 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1096 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1097 | { mk_mii_end, } |
7dd6a2aa GU |
1098 | }; |
1099 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { | |
1da177e4 LT |
1100 | /* find out the current status */ |
1101 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1102 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1103 | /* we only need to read ISR to acknowledge */ | |
1104 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | |
1105 | { mk_mii_end, } | |
7dd6a2aa GU |
1106 | }; |
1107 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1108 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
1109 | { mk_mii_end, } | |
7dd6a2aa GU |
1110 | }; |
1111 | static phy_info_t const phy_info_am79c874 = { | |
1112 | .id = 0x00022561, | |
1113 | .name = "AM79C874", | |
1114 | .config = phy_cmd_am79c874_config, | |
1115 | .startup = phy_cmd_am79c874_startup, | |
1116 | .ack_int = phy_cmd_am79c874_ack_int, | |
1117 | .shutdown = phy_cmd_am79c874_shutdown | |
1da177e4 LT |
1118 | }; |
1119 | ||
7dd6a2aa | 1120 | |
1da177e4 LT |
1121 | /* ------------------------------------------------------------------------- */ |
1122 | /* Kendin KS8721BL phy */ | |
1123 | ||
1124 | /* register definitions for the 8721 */ | |
1125 | ||
1126 | #define MII_KS8721BL_RXERCR 21 | |
1127 | #define MII_KS8721BL_ICSR 22 | |
1128 | #define MII_KS8721BL_PHYCR 31 | |
1129 | ||
7dd6a2aa | 1130 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
1da177e4 LT |
1131 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1132 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1133 | { mk_mii_end, } | |
7dd6a2aa GU |
1134 | }; |
1135 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1136 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
1137 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1138 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1139 | { mk_mii_end, } |
7dd6a2aa GU |
1140 | }; |
1141 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { | |
1da177e4 LT |
1142 | /* find out the current status */ |
1143 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1144 | /* we only need to read ISR to acknowledge */ | |
1145 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, | |
1146 | { mk_mii_end, } | |
7dd6a2aa GU |
1147 | }; |
1148 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1149 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
1150 | { mk_mii_end, } | |
7dd6a2aa GU |
1151 | }; |
1152 | static phy_info_t const phy_info_ks8721bl = { | |
6aa20a22 | 1153 | .id = 0x00022161, |
7dd6a2aa GU |
1154 | .name = "KS8721BL", |
1155 | .config = phy_cmd_ks8721bl_config, | |
1156 | .startup = phy_cmd_ks8721bl_startup, | |
1157 | .ack_int = phy_cmd_ks8721bl_ack_int, | |
1158 | .shutdown = phy_cmd_ks8721bl_shutdown | |
1da177e4 LT |
1159 | }; |
1160 | ||
562d2f8c GU |
1161 | /* ------------------------------------------------------------------------- */ |
1162 | /* register definitions for the DP83848 */ | |
1163 | ||
1164 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ | |
1165 | ||
1166 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) | |
1167 | { | |
1168 | struct fec_enet_private *fep = dev->priv; | |
1169 | volatile uint *s = &(fep->phy_status); | |
1170 | ||
1171 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); | |
1172 | ||
1173 | /* Link up */ | |
1174 | if (mii_reg & 0x0001) { | |
1175 | fep->link = 1; | |
1176 | *s |= PHY_STAT_LINK; | |
1177 | } else | |
1178 | fep->link = 0; | |
1179 | /* Status of link */ | |
1180 | if (mii_reg & 0x0010) /* Autonegotioation complete */ | |
1181 | *s |= PHY_STAT_ANC; | |
1182 | if (mii_reg & 0x0002) { /* 10MBps? */ | |
1183 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1184 | *s |= PHY_STAT_10FDX; | |
1185 | else | |
1186 | *s |= PHY_STAT_10HDX; | |
1187 | } else { /* 100 Mbps? */ | |
1188 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1189 | *s |= PHY_STAT_100FDX; | |
1190 | else | |
1191 | *s |= PHY_STAT_100HDX; | |
1192 | } | |
1193 | if (mii_reg & 0x0008) | |
1194 | *s |= PHY_STAT_FAULT; | |
1195 | } | |
1196 | ||
1197 | static phy_info_t phy_info_dp83848= { | |
1198 | 0x020005c9, | |
1199 | "DP83848", | |
1200 | ||
1201 | (const phy_cmd_t []) { /* config */ | |
1202 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1203 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1204 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, | |
1205 | { mk_mii_end, } | |
1206 | }, | |
1207 | (const phy_cmd_t []) { /* startup - enable interrupts */ | |
1208 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1209 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1210 | { mk_mii_end, } | |
1211 | }, | |
1212 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ | |
1213 | { mk_mii_end, } | |
1214 | }, | |
1215 | (const phy_cmd_t []) { /* shutdown */ | |
1216 | { mk_mii_end, } | |
1217 | }, | |
1218 | }; | |
1219 | ||
1da177e4 LT |
1220 | /* ------------------------------------------------------------------------- */ |
1221 | ||
7dd6a2aa | 1222 | static phy_info_t const * const phy_info[] = { |
1da177e4 LT |
1223 | &phy_info_lxt970, |
1224 | &phy_info_lxt971, | |
1225 | &phy_info_qs6612, | |
1226 | &phy_info_am79c874, | |
1227 | &phy_info_ks8721bl, | |
562d2f8c | 1228 | &phy_info_dp83848, |
1da177e4 LT |
1229 | NULL |
1230 | }; | |
1231 | ||
1232 | /* ------------------------------------------------------------------------- */ | |
6b265293 | 1233 | #if !defined(CONFIG_M532x) |
1da177e4 LT |
1234 | #ifdef CONFIG_RPXCLASSIC |
1235 | static void | |
1236 | mii_link_interrupt(void *dev_id); | |
1237 | #else | |
1238 | static irqreturn_t | |
7d12e780 | 1239 | mii_link_interrupt(int irq, void * dev_id); |
1da177e4 | 1240 | #endif |
6b265293 | 1241 | #endif |
1da177e4 LT |
1242 | |
1243 | #if defined(CONFIG_M5272) | |
1244 | ||
1245 | /* | |
1246 | * Code specific to Coldfire 5272 setup. | |
1247 | */ | |
1248 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1249 | { | |
1250 | volatile unsigned long *icrp; | |
7dd6a2aa GU |
1251 | static const struct idesc { |
1252 | char *name; | |
1253 | unsigned short irq; | |
7d12e780 | 1254 | irq_handler_t handler; |
7dd6a2aa GU |
1255 | } *idp, id[] = { |
1256 | { "fec(RX)", 86, fec_enet_interrupt }, | |
1257 | { "fec(TX)", 87, fec_enet_interrupt }, | |
1258 | { "fec(OTHER)", 88, fec_enet_interrupt }, | |
1259 | { "fec(MII)", 66, mii_link_interrupt }, | |
1260 | { NULL }, | |
1261 | }; | |
1da177e4 LT |
1262 | |
1263 | /* Setup interrupt handlers. */ | |
7dd6a2aa GU |
1264 | for (idp = id; idp->name; idp++) { |
1265 | if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0) | |
1266 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); | |
1267 | } | |
1da177e4 LT |
1268 | |
1269 | /* Unmask interrupt at ColdFire 5272 SIM */ | |
1270 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3); | |
1271 | *icrp = 0x00000ddd; | |
1272 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
1273 | *icrp = (*icrp & 0x70777777) | 0x0d000000; | |
1274 | } | |
1275 | ||
1276 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1277 | { | |
1278 | volatile fec_t *fecp; | |
1279 | ||
1280 | fecp = fep->hwp; | |
1281 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1282 | fecp->fec_x_cntrl = 0x00; | |
1283 | ||
1284 | /* | |
1285 | * Set MII speed to 2.5 MHz | |
1286 | * See 5272 manual section 11.5.8: MSCR | |
1287 | */ | |
1288 | fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2; | |
1289 | fecp->fec_mii_speed = fep->phy_speed; | |
1290 | ||
1291 | fec_restart(dev, 0); | |
1292 | } | |
1293 | ||
1294 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1295 | { | |
1296 | struct fec_enet_private *fep = netdev_priv(dev); | |
1297 | volatile fec_t *fecp; | |
7dd6a2aa | 1298 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1299 | |
1300 | fecp = fep->hwp; | |
1301 | ||
7dd6a2aa | 1302 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1303 | /* |
1304 | * Get MAC address from FLASH. | |
1305 | * If it is all 1's or 0's, use the default. | |
1306 | */ | |
7dd6a2aa | 1307 | iap = (unsigned char *)FEC_FLASHMAC; |
1da177e4 LT |
1308 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1309 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1310 | iap = fec_mac_default; | |
1311 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1312 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1313 | iap = fec_mac_default; | |
1314 | } else { | |
1315 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1316 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1317 | iap = &tmpaddr[0]; | |
1318 | } | |
1319 | ||
7dd6a2aa | 1320 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1321 | |
1322 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1323 | if (iap == fec_mac_default) |
1324 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1325 | } |
1326 | ||
1327 | static void __inline__ fec_enable_phy_intr(void) | |
1328 | { | |
1329 | } | |
1330 | ||
1331 | static void __inline__ fec_disable_phy_intr(void) | |
1332 | { | |
1333 | volatile unsigned long *icrp; | |
1334 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
1335 | *icrp = (*icrp & 0x70777777) | 0x08000000; | |
1336 | } | |
1337 | ||
1338 | static void __inline__ fec_phy_ack_intr(void) | |
1339 | { | |
1340 | volatile unsigned long *icrp; | |
1341 | /* Acknowledge the interrupt */ | |
1342 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
1343 | *icrp = (*icrp & 0x77777777) | 0x08000000; | |
1344 | } | |
1345 | ||
1346 | static void __inline__ fec_localhw_setup(void) | |
1347 | { | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * Do not need to make region uncached on 5272. | |
1352 | */ | |
1353 | static void __inline__ fec_uncache(unsigned long addr) | |
1354 | { | |
1355 | } | |
1356 | ||
1357 | /* ------------------------------------------------------------------------- */ | |
1358 | ||
7dd6a2aa | 1359 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) |
1da177e4 LT |
1360 | |
1361 | /* | |
7dd6a2aa GU |
1362 | * Code specific to Coldfire 5230/5231/5232/5234/5235, |
1363 | * the 5270/5271/5274/5275 and 5280/5282 setups. | |
1da177e4 LT |
1364 | */ |
1365 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1366 | { | |
1367 | struct fec_enet_private *fep; | |
1368 | int b; | |
7dd6a2aa GU |
1369 | static const struct idesc { |
1370 | char *name; | |
1371 | unsigned short irq; | |
1372 | } *idp, id[] = { | |
1373 | { "fec(TXF)", 23 }, | |
1374 | { "fec(TXB)", 24 }, | |
1375 | { "fec(TXFIFO)", 25 }, | |
1376 | { "fec(TXCR)", 26 }, | |
1377 | { "fec(RXF)", 27 }, | |
1378 | { "fec(RXB)", 28 }, | |
1379 | { "fec(MII)", 29 }, | |
1380 | { "fec(LC)", 30 }, | |
1381 | { "fec(HBERR)", 31 }, | |
1382 | { "fec(GRA)", 32 }, | |
1383 | { "fec(EBERR)", 33 }, | |
1384 | { "fec(BABT)", 34 }, | |
1385 | { "fec(BABR)", 35 }, | |
1386 | { NULL }, | |
1387 | }; | |
1da177e4 LT |
1388 | |
1389 | fep = netdev_priv(dev); | |
1390 | b = (fep->index) ? 128 : 64; | |
1391 | ||
1392 | /* Setup interrupt handlers. */ | |
7dd6a2aa GU |
1393 | for (idp = id; idp->name; idp++) { |
1394 | if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0) | |
1395 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); | |
1396 | } | |
1da177e4 LT |
1397 | |
1398 | /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */ | |
1399 | { | |
1400 | volatile unsigned char *icrp; | |
1401 | volatile unsigned long *imrp; | |
83901fc1 | 1402 | int i, ilip; |
1da177e4 LT |
1403 | |
1404 | b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0; | |
1405 | icrp = (volatile unsigned char *) (MCF_IPSBAR + b + | |
1406 | MCFINTC_ICR0); | |
83901fc1 WC |
1407 | for (i = 23, ilip = 0x28; (i < 36); i++) |
1408 | icrp[i] = ilip--; | |
1da177e4 LT |
1409 | |
1410 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1411 | MCFINTC_IMRH); | |
1412 | *imrp &= ~0x0000000f; | |
1413 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1414 | MCFINTC_IMRL); | |
1415 | *imrp &= ~0xff800001; | |
1416 | } | |
1417 | ||
1418 | #if defined(CONFIG_M528x) | |
1419 | /* Set up gpio outputs for MII lines */ | |
1420 | { | |
7dd6a2aa GU |
1421 | volatile u16 *gpio_paspar; |
1422 | volatile u8 *gpio_pehlpar; | |
6aa20a22 | 1423 | |
7dd6a2aa GU |
1424 | gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056); |
1425 | gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058); | |
1426 | *gpio_paspar |= 0x0f00; | |
1427 | *gpio_pehlpar = 0xc0; | |
1da177e4 LT |
1428 | } |
1429 | #endif | |
1430 | } | |
1431 | ||
1432 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1433 | { | |
1434 | volatile fec_t *fecp; | |
1435 | ||
1436 | fecp = fep->hwp; | |
1437 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1438 | fecp->fec_x_cntrl = 0x00; | |
1439 | ||
1440 | /* | |
1441 | * Set MII speed to 2.5 MHz | |
1442 | * See 5282 manual section 17.5.4.7: MSCR | |
1443 | */ | |
1444 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1445 | fecp->fec_mii_speed = fep->phy_speed; | |
1446 | ||
1447 | fec_restart(dev, 0); | |
1448 | } | |
1449 | ||
1450 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1451 | { | |
1452 | struct fec_enet_private *fep = netdev_priv(dev); | |
1453 | volatile fec_t *fecp; | |
7dd6a2aa | 1454 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1455 | |
1456 | fecp = fep->hwp; | |
1457 | ||
7dd6a2aa | 1458 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1459 | /* |
1460 | * Get MAC address from FLASH. | |
1461 | * If it is all 1's or 0's, use the default. | |
1462 | */ | |
7dd6a2aa | 1463 | iap = FEC_FLASHMAC; |
1da177e4 LT |
1464 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1465 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1466 | iap = fec_mac_default; | |
1467 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1468 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1469 | iap = fec_mac_default; | |
1470 | } else { | |
1471 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1472 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1473 | iap = &tmpaddr[0]; | |
1474 | } | |
1475 | ||
7dd6a2aa | 1476 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1477 | |
1478 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1479 | if (iap == fec_mac_default) |
1480 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1481 | } |
1482 | ||
1483 | static void __inline__ fec_enable_phy_intr(void) | |
1484 | { | |
1485 | } | |
1486 | ||
1487 | static void __inline__ fec_disable_phy_intr(void) | |
1488 | { | |
1489 | } | |
1490 | ||
1491 | static void __inline__ fec_phy_ack_intr(void) | |
1492 | { | |
1493 | } | |
1494 | ||
1495 | static void __inline__ fec_localhw_setup(void) | |
1496 | { | |
1497 | } | |
1498 | ||
1499 | /* | |
1500 | * Do not need to make region uncached on 5272. | |
1501 | */ | |
1502 | static void __inline__ fec_uncache(unsigned long addr) | |
1503 | { | |
1504 | } | |
1505 | ||
1506 | /* ------------------------------------------------------------------------- */ | |
1507 | ||
562d2f8c GU |
1508 | #elif defined(CONFIG_M520x) |
1509 | ||
1510 | /* | |
1511 | * Code specific to Coldfire 520x | |
1512 | */ | |
1513 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1514 | { | |
1515 | struct fec_enet_private *fep; | |
1516 | int b; | |
1517 | static const struct idesc { | |
1518 | char *name; | |
1519 | unsigned short irq; | |
1520 | } *idp, id[] = { | |
1521 | { "fec(TXF)", 23 }, | |
1522 | { "fec(TXB)", 24 }, | |
1523 | { "fec(TXFIFO)", 25 }, | |
1524 | { "fec(TXCR)", 26 }, | |
1525 | { "fec(RXF)", 27 }, | |
1526 | { "fec(RXB)", 28 }, | |
1527 | { "fec(MII)", 29 }, | |
1528 | { "fec(LC)", 30 }, | |
1529 | { "fec(HBERR)", 31 }, | |
1530 | { "fec(GRA)", 32 }, | |
1531 | { "fec(EBERR)", 33 }, | |
1532 | { "fec(BABT)", 34 }, | |
1533 | { "fec(BABR)", 35 }, | |
1534 | { NULL }, | |
1535 | }; | |
1536 | ||
1537 | fep = netdev_priv(dev); | |
1538 | b = 64 + 13; | |
1539 | ||
1540 | /* Setup interrupt handlers. */ | |
1541 | for (idp = id; idp->name; idp++) { | |
1542 | if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0) | |
1543 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); | |
1544 | } | |
1545 | ||
1546 | /* Unmask interrupts at ColdFire interrupt controller */ | |
1547 | { | |
1548 | volatile unsigned char *icrp; | |
1549 | volatile unsigned long *imrp; | |
1550 | ||
1551 | icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1552 | MCFINTC_ICR0); | |
1553 | for (b = 36; (b < 49); b++) | |
1554 | icrp[b] = 0x04; | |
1555 | imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1556 | MCFINTC_IMRH); | |
1557 | *imrp &= ~0x0001FFF0; | |
1558 | } | |
1559 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0; | |
1560 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f; | |
1561 | } | |
1562 | ||
1563 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1564 | { | |
1565 | volatile fec_t *fecp; | |
1566 | ||
1567 | fecp = fep->hwp; | |
1568 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1569 | fecp->fec_x_cntrl = 0x00; | |
1570 | ||
1571 | /* | |
1572 | * Set MII speed to 2.5 MHz | |
1573 | * See 5282 manual section 17.5.4.7: MSCR | |
1574 | */ | |
1575 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1576 | fecp->fec_mii_speed = fep->phy_speed; | |
1577 | ||
1578 | fec_restart(dev, 0); | |
1579 | } | |
1580 | ||
1581 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1582 | { | |
1583 | struct fec_enet_private *fep = netdev_priv(dev); | |
1584 | volatile fec_t *fecp; | |
1585 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1586 | ||
1587 | fecp = fep->hwp; | |
1588 | ||
1589 | if (FEC_FLASHMAC) { | |
1590 | /* | |
1591 | * Get MAC address from FLASH. | |
1592 | * If it is all 1's or 0's, use the default. | |
1593 | */ | |
1594 | iap = FEC_FLASHMAC; | |
1595 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1596 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1597 | iap = fec_mac_default; | |
1598 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1599 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1600 | iap = fec_mac_default; | |
1601 | } else { | |
1602 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1603 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1604 | iap = &tmpaddr[0]; | |
1605 | } | |
1606 | ||
1607 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1608 | ||
1609 | /* Adjust MAC if using default MAC address */ | |
1610 | if (iap == fec_mac_default) | |
1611 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1612 | } | |
1613 | ||
1614 | static void __inline__ fec_enable_phy_intr(void) | |
1615 | { | |
1616 | } | |
1617 | ||
1618 | static void __inline__ fec_disable_phy_intr(void) | |
1619 | { | |
1620 | } | |
1621 | ||
1622 | static void __inline__ fec_phy_ack_intr(void) | |
1623 | { | |
1624 | } | |
1625 | ||
1626 | static void __inline__ fec_localhw_setup(void) | |
1627 | { | |
1628 | } | |
1629 | ||
1630 | static void __inline__ fec_uncache(unsigned long addr) | |
1631 | { | |
1632 | } | |
1633 | ||
1634 | /* ------------------------------------------------------------------------- */ | |
1635 | ||
6b265293 MW |
1636 | #elif defined(CONFIG_M532x) |
1637 | /* | |
1638 | * Code specific for M532x | |
1639 | */ | |
1640 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1641 | { | |
1642 | struct fec_enet_private *fep; | |
1643 | int b; | |
1644 | static const struct idesc { | |
1645 | char *name; | |
1646 | unsigned short irq; | |
1647 | } *idp, id[] = { | |
1648 | { "fec(TXF)", 36 }, | |
1649 | { "fec(TXB)", 37 }, | |
1650 | { "fec(TXFIFO)", 38 }, | |
1651 | { "fec(TXCR)", 39 }, | |
1652 | { "fec(RXF)", 40 }, | |
1653 | { "fec(RXB)", 41 }, | |
1654 | { "fec(MII)", 42 }, | |
1655 | { "fec(LC)", 43 }, | |
1656 | { "fec(HBERR)", 44 }, | |
1657 | { "fec(GRA)", 45 }, | |
1658 | { "fec(EBERR)", 46 }, | |
1659 | { "fec(BABT)", 47 }, | |
1660 | { "fec(BABR)", 48 }, | |
1661 | { NULL }, | |
1662 | }; | |
1663 | ||
1664 | fep = netdev_priv(dev); | |
1665 | b = (fep->index) ? 128 : 64; | |
1666 | ||
1667 | /* Setup interrupt handlers. */ | |
1668 | for (idp = id; idp->name; idp++) { | |
1669 | if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0) | |
6aa20a22 | 1670 | printk("FEC: Could not allocate %s IRQ(%d)!\n", |
6b265293 MW |
1671 | idp->name, b+idp->irq); |
1672 | } | |
1673 | ||
1674 | /* Unmask interrupts */ | |
1675 | MCF_INTC0_ICR36 = 0x2; | |
1676 | MCF_INTC0_ICR37 = 0x2; | |
1677 | MCF_INTC0_ICR38 = 0x2; | |
1678 | MCF_INTC0_ICR39 = 0x2; | |
1679 | MCF_INTC0_ICR40 = 0x2; | |
1680 | MCF_INTC0_ICR41 = 0x2; | |
1681 | MCF_INTC0_ICR42 = 0x2; | |
1682 | MCF_INTC0_ICR43 = 0x2; | |
1683 | MCF_INTC0_ICR44 = 0x2; | |
1684 | MCF_INTC0_ICR45 = 0x2; | |
1685 | MCF_INTC0_ICR46 = 0x2; | |
1686 | MCF_INTC0_ICR47 = 0x2; | |
1687 | MCF_INTC0_ICR48 = 0x2; | |
1688 | ||
1689 | MCF_INTC0_IMRH &= ~( | |
1690 | MCF_INTC_IMRH_INT_MASK36 | | |
1691 | MCF_INTC_IMRH_INT_MASK37 | | |
1692 | MCF_INTC_IMRH_INT_MASK38 | | |
1693 | MCF_INTC_IMRH_INT_MASK39 | | |
1694 | MCF_INTC_IMRH_INT_MASK40 | | |
1695 | MCF_INTC_IMRH_INT_MASK41 | | |
1696 | MCF_INTC_IMRH_INT_MASK42 | | |
1697 | MCF_INTC_IMRH_INT_MASK43 | | |
1698 | MCF_INTC_IMRH_INT_MASK44 | | |
1699 | MCF_INTC_IMRH_INT_MASK45 | | |
1700 | MCF_INTC_IMRH_INT_MASK46 | | |
1701 | MCF_INTC_IMRH_INT_MASK47 | | |
1702 | MCF_INTC_IMRH_INT_MASK48 ); | |
1703 | ||
1704 | /* Set up gpio outputs for MII lines */ | |
1705 | MCF_GPIO_PAR_FECI2C |= (0 | | |
1706 | MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | | |
1707 | MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); | |
1708 | MCF_GPIO_PAR_FEC = (0 | | |
1709 | MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | | |
1710 | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); | |
1711 | } | |
1712 | ||
1713 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1714 | { | |
1715 | volatile fec_t *fecp; | |
1716 | ||
1717 | fecp = fep->hwp; | |
1718 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1719 | fecp->fec_x_cntrl = 0x00; | |
1720 | ||
1721 | /* | |
1722 | * Set MII speed to 2.5 MHz | |
1723 | */ | |
1724 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1725 | fecp->fec_mii_speed = fep->phy_speed; | |
1726 | ||
1727 | fec_restart(dev, 0); | |
1728 | } | |
1729 | ||
1730 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1731 | { | |
1732 | struct fec_enet_private *fep = netdev_priv(dev); | |
1733 | volatile fec_t *fecp; | |
1734 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1735 | ||
1736 | fecp = fep->hwp; | |
1737 | ||
1738 | if (FEC_FLASHMAC) { | |
1739 | /* | |
1740 | * Get MAC address from FLASH. | |
1741 | * If it is all 1's or 0's, use the default. | |
1742 | */ | |
1743 | iap = FEC_FLASHMAC; | |
1744 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1745 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1746 | iap = fec_mac_default; | |
1747 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1748 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1749 | iap = fec_mac_default; | |
1750 | } else { | |
1751 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1752 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1753 | iap = &tmpaddr[0]; | |
1754 | } | |
1755 | ||
1756 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1757 | ||
1758 | /* Adjust MAC if using default MAC address */ | |
1759 | if (iap == fec_mac_default) | |
1760 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1761 | } | |
1762 | ||
1763 | static void __inline__ fec_enable_phy_intr(void) | |
1764 | { | |
1765 | } | |
1766 | ||
1767 | static void __inline__ fec_disable_phy_intr(void) | |
1768 | { | |
1769 | } | |
1770 | ||
1771 | static void __inline__ fec_phy_ack_intr(void) | |
1772 | { | |
1773 | } | |
1774 | ||
1775 | static void __inline__ fec_localhw_setup(void) | |
1776 | { | |
1777 | } | |
1778 | ||
1779 | /* | |
1780 | * Do not need to make region uncached on 532x. | |
1781 | */ | |
1782 | static void __inline__ fec_uncache(unsigned long addr) | |
1783 | { | |
1784 | } | |
1785 | ||
1786 | /* ------------------------------------------------------------------------- */ | |
1787 | ||
1788 | ||
1da177e4 LT |
1789 | #else |
1790 | ||
1791 | /* | |
7dd6a2aa | 1792 | * Code specific to the MPC860T setup. |
1da177e4 LT |
1793 | */ |
1794 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1795 | { | |
1796 | volatile immap_t *immap; | |
1797 | ||
1798 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | |
1799 | ||
1800 | if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) | |
1801 | panic("Could not allocate FEC IRQ!"); | |
1802 | ||
1803 | #ifdef CONFIG_RPXCLASSIC | |
1804 | /* Make Port C, bit 15 an input that causes interrupts. | |
1805 | */ | |
1806 | immap->im_ioport.iop_pcpar &= ~0x0001; | |
1807 | immap->im_ioport.iop_pcdir &= ~0x0001; | |
1808 | immap->im_ioport.iop_pcso &= ~0x0001; | |
1809 | immap->im_ioport.iop_pcint |= 0x0001; | |
1810 | cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); | |
1811 | ||
1812 | /* Make LEDS reflect Link status. | |
1813 | */ | |
1814 | *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; | |
1815 | #endif | |
1816 | #ifdef CONFIG_FADS | |
1817 | if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0) | |
1818 | panic("Could not allocate MII IRQ!"); | |
1819 | #endif | |
1820 | } | |
1821 | ||
1822 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1823 | { | |
1da177e4 | 1824 | bd_t *bd; |
1da177e4 | 1825 | |
1da177e4 | 1826 | bd = (bd_t *)__res; |
7dd6a2aa | 1827 | memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN); |
1da177e4 LT |
1828 | |
1829 | #ifdef CONFIG_RPXCLASSIC | |
1830 | /* The Embedded Planet boards have only one MAC address in | |
1831 | * the EEPROM, but can have two Ethernet ports. For the | |
1832 | * FEC port, we create another address by setting one of | |
1833 | * the address bits above something that would have (up to | |
1834 | * now) been allocated. | |
1835 | */ | |
7dd6a2aa | 1836 | dev->dev_adrd[3] |= 0x80; |
1da177e4 | 1837 | #endif |
1da177e4 LT |
1838 | } |
1839 | ||
1840 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1841 | { | |
1842 | extern uint _get_IMMR(void); | |
1843 | volatile immap_t *immap; | |
1844 | volatile fec_t *fecp; | |
1845 | ||
1846 | fecp = fep->hwp; | |
1847 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | |
1848 | ||
1849 | /* Configure all of port D for MII. | |
1850 | */ | |
1851 | immap->im_ioport.iop_pdpar = 0x1fff; | |
1852 | ||
1853 | /* Bits moved from Rev. D onward. | |
1854 | */ | |
1855 | if ((_get_IMMR() & 0xffff) < 0x0501) | |
1856 | immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ | |
1857 | else | |
1858 | immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ | |
6aa20a22 | 1859 | |
1da177e4 LT |
1860 | /* Set MII speed to 2.5 MHz |
1861 | */ | |
6aa20a22 | 1862 | fecp->fec_mii_speed = fep->phy_speed = |
1da177e4 LT |
1863 | ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e; |
1864 | } | |
1865 | ||
1866 | static void __inline__ fec_enable_phy_intr(void) | |
1867 | { | |
1868 | volatile fec_t *fecp; | |
1869 | ||
1870 | fecp = fep->hwp; | |
1871 | ||
6aa20a22 | 1872 | /* Enable MII command finished interrupt |
1da177e4 LT |
1873 | */ |
1874 | fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; | |
1875 | } | |
1876 | ||
1877 | static void __inline__ fec_disable_phy_intr(void) | |
1878 | { | |
1879 | } | |
1880 | ||
1881 | static void __inline__ fec_phy_ack_intr(void) | |
1882 | { | |
1883 | } | |
1884 | ||
1885 | static void __inline__ fec_localhw_setup(void) | |
1886 | { | |
1887 | volatile fec_t *fecp; | |
1888 | ||
1889 | fecp = fep->hwp; | |
1890 | fecp->fec_r_hash = PKT_MAXBUF_SIZE; | |
1891 | /* Enable big endian and don't care about SDMA FC. | |
1892 | */ | |
1893 | fecp->fec_fun_code = 0x78000000; | |
1894 | } | |
1895 | ||
1896 | static void __inline__ fec_uncache(unsigned long addr) | |
1897 | { | |
1898 | pte_t *pte; | |
1899 | pte = va_to_pte(mem_addr); | |
1900 | pte_val(*pte) |= _PAGE_NO_CACHE; | |
1901 | flush_tlb_page(init_mm.mmap, mem_addr); | |
1902 | } | |
1903 | ||
1904 | #endif | |
1905 | ||
1906 | /* ------------------------------------------------------------------------- */ | |
1907 | ||
1908 | static void mii_display_status(struct net_device *dev) | |
1909 | { | |
1910 | struct fec_enet_private *fep = netdev_priv(dev); | |
1911 | volatile uint *s = &(fep->phy_status); | |
1912 | ||
1913 | if (!fep->link && !fep->old_link) { | |
1914 | /* Link is still down - don't print anything */ | |
1915 | return; | |
1916 | } | |
1917 | ||
1918 | printk("%s: status: ", dev->name); | |
1919 | ||
1920 | if (!fep->link) { | |
1921 | printk("link down"); | |
1922 | } else { | |
1923 | printk("link up"); | |
1924 | ||
1925 | switch(*s & PHY_STAT_SPMASK) { | |
1926 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; | |
1927 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; | |
1928 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; | |
1929 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; | |
1930 | default: | |
1931 | printk(", Unknown speed/duplex"); | |
1932 | } | |
1933 | ||
1934 | if (*s & PHY_STAT_ANC) | |
1935 | printk(", auto-negotiation complete"); | |
1936 | } | |
1937 | ||
1938 | if (*s & PHY_STAT_FAULT) | |
1939 | printk(", remote fault"); | |
1940 | ||
1941 | printk(".\n"); | |
1942 | } | |
1943 | ||
cb84d6e7 | 1944 | static void mii_display_config(struct work_struct *work) |
1da177e4 | 1945 | { |
cb84d6e7 GU |
1946 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1947 | struct net_device *dev = fep->netdev; | |
7dd6a2aa | 1948 | uint status = fep->phy_status; |
1da177e4 LT |
1949 | |
1950 | /* | |
1951 | ** When we get here, phy_task is already removed from | |
1952 | ** the workqueue. It is thus safe to allow to reuse it. | |
1953 | */ | |
1954 | fep->mii_phy_task_queued = 0; | |
1955 | printk("%s: config: auto-negotiation ", dev->name); | |
1956 | ||
7dd6a2aa | 1957 | if (status & PHY_CONF_ANE) |
1da177e4 LT |
1958 | printk("on"); |
1959 | else | |
1960 | printk("off"); | |
1961 | ||
7dd6a2aa | 1962 | if (status & PHY_CONF_100FDX) |
1da177e4 | 1963 | printk(", 100FDX"); |
7dd6a2aa | 1964 | if (status & PHY_CONF_100HDX) |
1da177e4 | 1965 | printk(", 100HDX"); |
7dd6a2aa | 1966 | if (status & PHY_CONF_10FDX) |
1da177e4 | 1967 | printk(", 10FDX"); |
7dd6a2aa | 1968 | if (status & PHY_CONF_10HDX) |
1da177e4 | 1969 | printk(", 10HDX"); |
7dd6a2aa | 1970 | if (!(status & PHY_CONF_SPMASK)) |
1da177e4 LT |
1971 | printk(", No speed/duplex selected?"); |
1972 | ||
7dd6a2aa | 1973 | if (status & PHY_CONF_LOOP) |
1da177e4 | 1974 | printk(", loopback enabled"); |
6aa20a22 | 1975 | |
1da177e4 LT |
1976 | printk(".\n"); |
1977 | ||
1978 | fep->sequence_done = 1; | |
1979 | } | |
1980 | ||
cb84d6e7 | 1981 | static void mii_relink(struct work_struct *work) |
1da177e4 | 1982 | { |
cb84d6e7 GU |
1983 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1984 | struct net_device *dev = fep->netdev; | |
1da177e4 LT |
1985 | int duplex; |
1986 | ||
1987 | /* | |
1988 | ** When we get here, phy_task is already removed from | |
1989 | ** the workqueue. It is thus safe to allow to reuse it. | |
1990 | */ | |
1991 | fep->mii_phy_task_queued = 0; | |
1992 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | |
1993 | mii_display_status(dev); | |
1994 | fep->old_link = fep->link; | |
1995 | ||
1996 | if (fep->link) { | |
1997 | duplex = 0; | |
6aa20a22 | 1998 | if (fep->phy_status |
1da177e4 LT |
1999 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
2000 | duplex = 1; | |
2001 | fec_restart(dev, duplex); | |
2002 | } | |
2003 | else | |
2004 | fec_stop(dev); | |
2005 | ||
2006 | #if 0 | |
2007 | enable_irq(fep->mii_irq); | |
2008 | #endif | |
2009 | ||
2010 | } | |
2011 | ||
2012 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ | |
2013 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | |
2014 | { | |
2015 | struct fec_enet_private *fep = netdev_priv(dev); | |
2016 | ||
2017 | /* | |
2018 | ** We cannot queue phy_task twice in the workqueue. It | |
2019 | ** would cause an endless loop in the workqueue. | |
2020 | ** Fortunately, if the last mii_relink entry has not yet been | |
2021 | ** executed now, it will do the job for the current interrupt, | |
2022 | ** which is just what we want. | |
2023 | */ | |
2024 | if (fep->mii_phy_task_queued) | |
2025 | return; | |
2026 | ||
2027 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 2028 | INIT_WORK(&fep->phy_task, mii_relink); |
1da177e4 LT |
2029 | schedule_work(&fep->phy_task); |
2030 | } | |
2031 | ||
7dd6a2aa | 2032 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
1da177e4 LT |
2033 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
2034 | { | |
2035 | struct fec_enet_private *fep = netdev_priv(dev); | |
2036 | ||
2037 | if (fep->mii_phy_task_queued) | |
2038 | return; | |
2039 | ||
2040 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 2041 | INIT_WORK(&fep->phy_task, mii_display_config); |
1da177e4 LT |
2042 | schedule_work(&fep->phy_task); |
2043 | } | |
2044 | ||
7dd6a2aa GU |
2045 | phy_cmd_t const phy_cmd_relink[] = { |
2046 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, | |
2047 | { mk_mii_end, } | |
2048 | }; | |
2049 | phy_cmd_t const phy_cmd_config[] = { | |
2050 | { mk_mii_read(MII_REG_CR), mii_queue_config }, | |
2051 | { mk_mii_end, } | |
2052 | }; | |
1da177e4 LT |
2053 | |
2054 | /* Read remainder of PHY ID. | |
2055 | */ | |
2056 | static void | |
2057 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | |
2058 | { | |
2059 | struct fec_enet_private *fep; | |
2060 | int i; | |
2061 | ||
2062 | fep = netdev_priv(dev); | |
2063 | fep->phy_id |= (mii_reg & 0xffff); | |
2064 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); | |
2065 | ||
2066 | for(i = 0; phy_info[i]; i++) { | |
2067 | if(phy_info[i]->id == (fep->phy_id >> 4)) | |
2068 | break; | |
2069 | } | |
2070 | ||
2071 | if (phy_info[i]) | |
2072 | printk(" -- %s\n", phy_info[i]->name); | |
2073 | else | |
2074 | printk(" -- unknown PHY!\n"); | |
6aa20a22 | 2075 | |
1da177e4 LT |
2076 | fep->phy = phy_info[i]; |
2077 | fep->phy_id_done = 1; | |
2078 | } | |
2079 | ||
2080 | /* Scan all of the MII PHY addresses looking for someone to respond | |
2081 | * with a valid ID. This usually happens quickly. | |
2082 | */ | |
2083 | static void | |
2084 | mii_discover_phy(uint mii_reg, struct net_device *dev) | |
2085 | { | |
2086 | struct fec_enet_private *fep; | |
2087 | volatile fec_t *fecp; | |
2088 | uint phytype; | |
2089 | ||
2090 | fep = netdev_priv(dev); | |
2091 | fecp = fep->hwp; | |
2092 | ||
2093 | if (fep->phy_addr < 32) { | |
2094 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | |
6aa20a22 | 2095 | |
1da177e4 LT |
2096 | /* Got first part of ID, now get remainder. |
2097 | */ | |
2098 | fep->phy_id = phytype << 16; | |
2099 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), | |
2100 | mii_discover_phy3); | |
2101 | } | |
2102 | else { | |
2103 | fep->phy_addr++; | |
2104 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | |
2105 | mii_discover_phy); | |
2106 | } | |
2107 | } else { | |
2108 | printk("FEC: No PHY device found.\n"); | |
2109 | /* Disable external MII interface */ | |
2110 | fecp->fec_mii_speed = fep->phy_speed = 0; | |
2111 | fec_disable_phy_intr(); | |
2112 | } | |
2113 | } | |
2114 | ||
2115 | /* This interrupt occurs when the PHY detects a link change. | |
2116 | */ | |
2117 | #ifdef CONFIG_RPXCLASSIC | |
2118 | static void | |
2119 | mii_link_interrupt(void *dev_id) | |
2120 | #else | |
2121 | static irqreturn_t | |
7d12e780 | 2122 | mii_link_interrupt(int irq, void * dev_id) |
1da177e4 LT |
2123 | #endif |
2124 | { | |
2125 | struct net_device *dev = dev_id; | |
2126 | struct fec_enet_private *fep = netdev_priv(dev); | |
2127 | ||
2128 | fec_phy_ack_intr(); | |
2129 | ||
2130 | #if 0 | |
2131 | disable_irq(fep->mii_irq); /* disable now, enable later */ | |
2132 | #endif | |
2133 | ||
2134 | mii_do_cmd(dev, fep->phy->ack_int); | |
2135 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | |
2136 | ||
2137 | return IRQ_HANDLED; | |
2138 | } | |
2139 | ||
2140 | static int | |
2141 | fec_enet_open(struct net_device *dev) | |
2142 | { | |
2143 | struct fec_enet_private *fep = netdev_priv(dev); | |
2144 | ||
2145 | /* I should reset the ring buffers here, but I don't yet know | |
2146 | * a simple way to do that. | |
2147 | */ | |
2148 | fec_set_mac_address(dev); | |
2149 | ||
2150 | fep->sequence_done = 0; | |
2151 | fep->link = 0; | |
2152 | ||
2153 | if (fep->phy) { | |
2154 | mii_do_cmd(dev, fep->phy->ack_int); | |
2155 | mii_do_cmd(dev, fep->phy->config); | |
2156 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | |
2157 | ||
6b265293 MW |
2158 | /* Poll until the PHY tells us its configuration |
2159 | * (not link state). | |
2160 | * Request is initiated by mii_do_cmd above, but answer | |
2161 | * comes by interrupt. | |
2162 | * This should take about 25 usec per register at 2.5 MHz, | |
2163 | * and we read approximately 5 registers. | |
1da177e4 LT |
2164 | */ |
2165 | while(!fep->sequence_done) | |
2166 | schedule(); | |
2167 | ||
2168 | mii_do_cmd(dev, fep->phy->startup); | |
2169 | ||
2170 | /* Set the initial link state to true. A lot of hardware | |
2171 | * based on this device does not implement a PHY interrupt, | |
2172 | * so we are never notified of link change. | |
2173 | */ | |
2174 | fep->link = 1; | |
2175 | } else { | |
2176 | fep->link = 1; /* lets just try it and see */ | |
2177 | /* no phy, go full duplex, it's most likely a hub chip */ | |
2178 | fec_restart(dev, 1); | |
2179 | } | |
2180 | ||
2181 | netif_start_queue(dev); | |
2182 | fep->opened = 1; | |
2183 | return 0; /* Success */ | |
2184 | } | |
2185 | ||
2186 | static int | |
2187 | fec_enet_close(struct net_device *dev) | |
2188 | { | |
2189 | struct fec_enet_private *fep = netdev_priv(dev); | |
2190 | ||
2191 | /* Don't know what to do yet. | |
2192 | */ | |
2193 | fep->opened = 0; | |
2194 | netif_stop_queue(dev); | |
2195 | fec_stop(dev); | |
2196 | ||
2197 | return 0; | |
2198 | } | |
2199 | ||
2200 | static struct net_device_stats *fec_enet_get_stats(struct net_device *dev) | |
2201 | { | |
2202 | struct fec_enet_private *fep = netdev_priv(dev); | |
2203 | ||
2204 | return &fep->stats; | |
2205 | } | |
2206 | ||
2207 | /* Set or clear the multicast filter for this adaptor. | |
2208 | * Skeleton taken from sunlance driver. | |
2209 | * The CPM Ethernet implementation allows Multicast as well as individual | |
2210 | * MAC address filtering. Some of the drivers check to make sure it is | |
2211 | * a group multicast address, and discard those that are not. I guess I | |
2212 | * will do the same for now, but just remove the test if you want | |
2213 | * individual filtering as well (do the upper net layers want or support | |
2214 | * this kind of feature?). | |
2215 | */ | |
2216 | ||
2217 | #define HASH_BITS 6 /* #bits in hash */ | |
2218 | #define CRC32_POLY 0xEDB88320 | |
2219 | ||
2220 | static void set_multicast_list(struct net_device *dev) | |
2221 | { | |
2222 | struct fec_enet_private *fep; | |
2223 | volatile fec_t *ep; | |
2224 | struct dev_mc_list *dmi; | |
2225 | unsigned int i, j, bit, data, crc; | |
2226 | unsigned char hash; | |
2227 | ||
2228 | fep = netdev_priv(dev); | |
2229 | ep = fep->hwp; | |
2230 | ||
2231 | if (dev->flags&IFF_PROMISC) { | |
1da177e4 LT |
2232 | ep->fec_r_cntrl |= 0x0008; |
2233 | } else { | |
2234 | ||
2235 | ep->fec_r_cntrl &= ~0x0008; | |
2236 | ||
2237 | if (dev->flags & IFF_ALLMULTI) { | |
2238 | /* Catch all multicast addresses, so set the | |
2239 | * filter to all 1's. | |
2240 | */ | |
2241 | ep->fec_hash_table_high = 0xffffffff; | |
2242 | ep->fec_hash_table_low = 0xffffffff; | |
2243 | } else { | |
2244 | /* Clear filter and add the addresses in hash register. | |
2245 | */ | |
2246 | ep->fec_hash_table_high = 0; | |
2247 | ep->fec_hash_table_low = 0; | |
6aa20a22 | 2248 | |
1da177e4 LT |
2249 | dmi = dev->mc_list; |
2250 | ||
2251 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) | |
2252 | { | |
2253 | /* Only support group multicast for now. | |
2254 | */ | |
2255 | if (!(dmi->dmi_addr[0] & 1)) | |
2256 | continue; | |
6aa20a22 | 2257 | |
1da177e4 LT |
2258 | /* calculate crc32 value of mac address |
2259 | */ | |
2260 | crc = 0xffffffff; | |
2261 | ||
2262 | for (i = 0; i < dmi->dmi_addrlen; i++) | |
2263 | { | |
2264 | data = dmi->dmi_addr[i]; | |
2265 | for (bit = 0; bit < 8; bit++, data >>= 1) | |
2266 | { | |
2267 | crc = (crc >> 1) ^ | |
2268 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | /* only upper 6 bits (HASH_BITS) are used | |
2273 | which point to specific bit in he hash registers | |
2274 | */ | |
2275 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
6aa20a22 | 2276 | |
1da177e4 LT |
2277 | if (hash > 31) |
2278 | ep->fec_hash_table_high |= 1 << (hash - 32); | |
2279 | else | |
2280 | ep->fec_hash_table_low |= 1 << hash; | |
2281 | } | |
2282 | } | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | /* Set a MAC change in hardware. | |
2287 | */ | |
2288 | static void | |
2289 | fec_set_mac_address(struct net_device *dev) | |
2290 | { | |
1da177e4 LT |
2291 | volatile fec_t *fecp; |
2292 | ||
7dd6a2aa | 2293 | fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp; |
1da177e4 LT |
2294 | |
2295 | /* Set station address. */ | |
7dd6a2aa GU |
2296 | fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
2297 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24); | |
2298 | fecp->fec_addr_high = (dev->dev_addr[5] << 16) | | |
2299 | (dev->dev_addr[4] << 24); | |
1da177e4 LT |
2300 | |
2301 | } | |
2302 | ||
2303 | /* Initialize the FEC Ethernet on 860T (or ColdFire 5272). | |
2304 | */ | |
2305 | /* | |
2306 | * XXX: We need to clean up on failure exits here. | |
2307 | */ | |
2308 | int __init fec_enet_init(struct net_device *dev) | |
2309 | { | |
2310 | struct fec_enet_private *fep = netdev_priv(dev); | |
2311 | unsigned long mem_addr; | |
2312 | volatile cbd_t *bdp; | |
2313 | cbd_t *cbd_base; | |
2314 | volatile fec_t *fecp; | |
2315 | int i, j; | |
2316 | static int index = 0; | |
2317 | ||
2318 | /* Only allow us to be probed once. */ | |
2319 | if (index >= FEC_MAX_PORTS) | |
2320 | return -ENXIO; | |
2321 | ||
562d2f8c GU |
2322 | /* Allocate memory for buffer descriptors. |
2323 | */ | |
2324 | mem_addr = __get_free_page(GFP_KERNEL); | |
2325 | if (mem_addr == 0) { | |
2326 | printk("FEC: allocate descriptor memory failed?\n"); | |
2327 | return -ENOMEM; | |
2328 | } | |
2329 | ||
1da177e4 LT |
2330 | /* Create an Ethernet device instance. |
2331 | */ | |
2332 | fecp = (volatile fec_t *) fec_hw[index]; | |
2333 | ||
2334 | fep->index = index; | |
2335 | fep->hwp = fecp; | |
cb84d6e7 | 2336 | fep->netdev = dev; |
1da177e4 LT |
2337 | |
2338 | /* Whack a reset. We should wait for this. | |
2339 | */ | |
2340 | fecp->fec_ecntrl = 1; | |
2341 | udelay(10); | |
2342 | ||
1da177e4 LT |
2343 | /* Set the Ethernet address. If using multiple Enets on the 8xx, |
2344 | * this needs some work to get unique addresses. | |
2345 | * | |
2346 | * This is our default MAC address unless the user changes | |
2347 | * it via eth_mac_addr (our dev->set_mac_addr handler). | |
2348 | */ | |
2349 | fec_get_mac(dev); | |
2350 | ||
1da177e4 LT |
2351 | cbd_base = (cbd_t *)mem_addr; |
2352 | /* XXX: missing check for allocation failure */ | |
2353 | ||
2354 | fec_uncache(mem_addr); | |
2355 | ||
2356 | /* Set receive and transmit descriptor base. | |
2357 | */ | |
2358 | fep->rx_bd_base = cbd_base; | |
2359 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
2360 | ||
2361 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2362 | fep->cur_rx = fep->rx_bd_base; | |
2363 | ||
2364 | fep->skb_cur = fep->skb_dirty = 0; | |
2365 | ||
2366 | /* Initialize the receive buffer descriptors. | |
2367 | */ | |
2368 | bdp = fep->rx_bd_base; | |
2369 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | |
2370 | ||
2371 | /* Allocate a page. | |
2372 | */ | |
2373 | mem_addr = __get_free_page(GFP_KERNEL); | |
2374 | /* XXX: missing check for allocation failure */ | |
2375 | ||
2376 | fec_uncache(mem_addr); | |
2377 | ||
2378 | /* Initialize the BD for every fragment in the page. | |
2379 | */ | |
2380 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { | |
2381 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2382 | bdp->cbd_bufaddr = __pa(mem_addr); | |
2383 | mem_addr += FEC_ENET_RX_FRSIZE; | |
2384 | bdp++; | |
2385 | } | |
2386 | } | |
2387 | ||
2388 | /* Set the last buffer to wrap. | |
2389 | */ | |
2390 | bdp--; | |
2391 | bdp->cbd_sc |= BD_SC_WRAP; | |
2392 | ||
2393 | /* ...and the same for transmmit. | |
2394 | */ | |
2395 | bdp = fep->tx_bd_base; | |
2396 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { | |
2397 | if (j >= FEC_ENET_TX_FRPPG) { | |
2398 | mem_addr = __get_free_page(GFP_KERNEL); | |
2399 | j = 1; | |
2400 | } else { | |
2401 | mem_addr += FEC_ENET_TX_FRSIZE; | |
2402 | j++; | |
2403 | } | |
2404 | fep->tx_bounce[i] = (unsigned char *) mem_addr; | |
2405 | ||
2406 | /* Initialize the BD for every fragment in the page. | |
2407 | */ | |
2408 | bdp->cbd_sc = 0; | |
2409 | bdp->cbd_bufaddr = 0; | |
2410 | bdp++; | |
2411 | } | |
2412 | ||
2413 | /* Set the last buffer to wrap. | |
2414 | */ | |
2415 | bdp--; | |
2416 | bdp->cbd_sc |= BD_SC_WRAP; | |
2417 | ||
2418 | /* Set receive and transmit descriptor base. | |
2419 | */ | |
2420 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); | |
2421 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); | |
2422 | ||
2423 | /* Install our interrupt handlers. This varies depending on | |
2424 | * the architecture. | |
2425 | */ | |
2426 | fec_request_intrs(dev); | |
2427 | ||
562d2f8c GU |
2428 | fecp->fec_hash_table_high = 0; |
2429 | fecp->fec_hash_table_low = 0; | |
2430 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | |
2431 | fecp->fec_ecntrl = 2; | |
6b265293 | 2432 | fecp->fec_r_des_active = 0; |
562d2f8c | 2433 | |
1da177e4 LT |
2434 | dev->base_addr = (unsigned long)fecp; |
2435 | ||
2436 | /* The FEC Ethernet specific entries in the device structure. */ | |
2437 | dev->open = fec_enet_open; | |
2438 | dev->hard_start_xmit = fec_enet_start_xmit; | |
2439 | dev->tx_timeout = fec_timeout; | |
2440 | dev->watchdog_timeo = TX_TIMEOUT; | |
2441 | dev->stop = fec_enet_close; | |
2442 | dev->get_stats = fec_enet_get_stats; | |
2443 | dev->set_multicast_list = set_multicast_list; | |
2444 | ||
2445 | for (i=0; i<NMII-1; i++) | |
2446 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | |
2447 | mii_free = mii_cmds; | |
2448 | ||
2449 | /* setup MII interface */ | |
2450 | fec_set_mii(dev, fep); | |
2451 | ||
6b265293 MW |
2452 | /* Clear and enable interrupts */ |
2453 | fecp->fec_ievent = 0xffc00000; | |
2454 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB | | |
2455 | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII); | |
2456 | ||
1da177e4 LT |
2457 | /* Queue up command to detect the PHY and initialize the |
2458 | * remainder of the interface. | |
2459 | */ | |
2460 | fep->phy_id_done = 0; | |
2461 | fep->phy_addr = 0; | |
2462 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | |
2463 | ||
2464 | index++; | |
2465 | return 0; | |
2466 | } | |
2467 | ||
2468 | /* This function is called to start or restart the FEC during a link | |
2469 | * change. This only happens when switching between half and full | |
2470 | * duplex. | |
2471 | */ | |
2472 | static void | |
2473 | fec_restart(struct net_device *dev, int duplex) | |
2474 | { | |
2475 | struct fec_enet_private *fep; | |
2476 | volatile cbd_t *bdp; | |
2477 | volatile fec_t *fecp; | |
2478 | int i; | |
2479 | ||
2480 | fep = netdev_priv(dev); | |
2481 | fecp = fep->hwp; | |
2482 | ||
2483 | /* Whack a reset. We should wait for this. | |
2484 | */ | |
2485 | fecp->fec_ecntrl = 1; | |
2486 | udelay(10); | |
2487 | ||
1da177e4 LT |
2488 | /* Clear any outstanding interrupt. |
2489 | */ | |
7dd6a2aa | 2490 | fecp->fec_ievent = 0xffc00000; |
1da177e4 LT |
2491 | fec_enable_phy_intr(); |
2492 | ||
2493 | /* Set station address. | |
2494 | */ | |
7dd6a2aa | 2495 | fec_set_mac_address(dev); |
1da177e4 LT |
2496 | |
2497 | /* Reset all multicast. | |
2498 | */ | |
2499 | fecp->fec_hash_table_high = 0; | |
2500 | fecp->fec_hash_table_low = 0; | |
2501 | ||
2502 | /* Set maximum receive buffer size. | |
2503 | */ | |
2504 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | |
2505 | ||
2506 | fec_localhw_setup(); | |
2507 | ||
2508 | /* Set receive and transmit descriptor base. | |
2509 | */ | |
2510 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); | |
2511 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); | |
2512 | ||
2513 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2514 | fep->cur_rx = fep->rx_bd_base; | |
2515 | ||
2516 | /* Reset SKB transmit buffers. | |
2517 | */ | |
2518 | fep->skb_cur = fep->skb_dirty = 0; | |
2519 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | |
2520 | if (fep->tx_skbuff[i] != NULL) { | |
2521 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
2522 | fep->tx_skbuff[i] = NULL; | |
2523 | } | |
2524 | } | |
2525 | ||
2526 | /* Initialize the receive buffer descriptors. | |
2527 | */ | |
2528 | bdp = fep->rx_bd_base; | |
2529 | for (i=0; i<RX_RING_SIZE; i++) { | |
2530 | ||
2531 | /* Initialize the BD for every fragment in the page. | |
2532 | */ | |
2533 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2534 | bdp++; | |
2535 | } | |
2536 | ||
2537 | /* Set the last buffer to wrap. | |
2538 | */ | |
2539 | bdp--; | |
2540 | bdp->cbd_sc |= BD_SC_WRAP; | |
2541 | ||
2542 | /* ...and the same for transmmit. | |
2543 | */ | |
2544 | bdp = fep->tx_bd_base; | |
2545 | for (i=0; i<TX_RING_SIZE; i++) { | |
2546 | ||
2547 | /* Initialize the BD for every fragment in the page. | |
2548 | */ | |
2549 | bdp->cbd_sc = 0; | |
2550 | bdp->cbd_bufaddr = 0; | |
2551 | bdp++; | |
2552 | } | |
2553 | ||
2554 | /* Set the last buffer to wrap. | |
2555 | */ | |
2556 | bdp--; | |
2557 | bdp->cbd_sc |= BD_SC_WRAP; | |
2558 | ||
2559 | /* Enable MII mode. | |
2560 | */ | |
2561 | if (duplex) { | |
2562 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */ | |
2563 | fecp->fec_x_cntrl = 0x04; /* FD enable */ | |
2564 | } | |
2565 | else { | |
2566 | /* MII enable|No Rcv on Xmit */ | |
2567 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06; | |
2568 | fecp->fec_x_cntrl = 0x00; | |
2569 | } | |
2570 | fep->full_duplex = duplex; | |
2571 | ||
2572 | /* Set MII speed. | |
2573 | */ | |
2574 | fecp->fec_mii_speed = fep->phy_speed; | |
2575 | ||
2576 | /* And last, enable the transmit and receive processing. | |
2577 | */ | |
2578 | fecp->fec_ecntrl = 2; | |
6b265293 MW |
2579 | fecp->fec_r_des_active = 0; |
2580 | ||
2581 | /* Enable interrupts we wish to service. | |
2582 | */ | |
2583 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB | | |
2584 | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII); | |
1da177e4 LT |
2585 | } |
2586 | ||
2587 | static void | |
2588 | fec_stop(struct net_device *dev) | |
2589 | { | |
2590 | volatile fec_t *fecp; | |
2591 | struct fec_enet_private *fep; | |
2592 | ||
2593 | fep = netdev_priv(dev); | |
2594 | fecp = fep->hwp; | |
2595 | ||
677177c5 PDM |
2596 | /* |
2597 | ** We cannot expect a graceful transmit stop without link !!! | |
2598 | */ | |
2599 | if (fep->link) | |
2600 | { | |
2601 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ | |
2602 | udelay(10); | |
2603 | if (!(fecp->fec_ievent & FEC_ENET_GRA)) | |
2604 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
2605 | } | |
1da177e4 LT |
2606 | |
2607 | /* Whack a reset. We should wait for this. | |
2608 | */ | |
2609 | fecp->fec_ecntrl = 1; | |
2610 | udelay(10); | |
2611 | ||
2612 | /* Clear outstanding MII command interrupts. | |
2613 | */ | |
2614 | fecp->fec_ievent = FEC_ENET_MII; | |
2615 | fec_enable_phy_intr(); | |
2616 | ||
2617 | fecp->fec_imask = FEC_ENET_MII; | |
2618 | fecp->fec_mii_speed = fep->phy_speed; | |
2619 | } | |
2620 | ||
2621 | static int __init fec_enet_module_init(void) | |
2622 | { | |
2623 | struct net_device *dev; | |
7dd6a2aa GU |
2624 | int i, j, err; |
2625 | ||
2626 | printk("FEC ENET Version 0.2\n"); | |
1da177e4 LT |
2627 | |
2628 | for (i = 0; (i < FEC_MAX_PORTS); i++) { | |
2629 | dev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
2630 | if (!dev) | |
2631 | return -ENOMEM; | |
2632 | err = fec_enet_init(dev); | |
2633 | if (err) { | |
2634 | free_netdev(dev); | |
2635 | continue; | |
2636 | } | |
2637 | if (register_netdev(dev) != 0) { | |
2638 | /* XXX: missing cleanup here */ | |
2639 | free_netdev(dev); | |
2640 | return -EIO; | |
2641 | } | |
7dd6a2aa GU |
2642 | |
2643 | printk("%s: ethernet ", dev->name); | |
2644 | for (j = 0; (j < 5); j++) | |
2645 | printk("%02x:", dev->dev_addr[j]); | |
2646 | printk("%02x\n", dev->dev_addr[5]); | |
1da177e4 LT |
2647 | } |
2648 | return 0; | |
2649 | } | |
2650 | ||
2651 | module_init(fec_enet_module_init); | |
2652 | ||
2653 | MODULE_LICENSE("GPL"); |