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[netdrvr] Remove Linux-specific changelogs from several Becker template drivers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / fealnx.c
CommitLineData
1da177e4
LT		 1/*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25*/
26
27#define DRV_NAME "fealnx"
28#define DRV_VERSION "2.51"
29#define DRV_RELDATE "Nov-17-2001"
30
31static int debug; /* 1-> print debug message */
32static int max_interrupt_work = 20;
33
34/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35static int multicast_filter_limit = 32;
36
37/* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38/* Setting to > 1518 effectively disables this feature. */
39static int rx_copybreak;
40
41/* Used to pass the media type, etc. */
42/* Both 'options[]' and 'full_duplex[]' should exist for driver */
43/* interoperability. */
44/* The media type is usually passed in 'options[]'. */
45#define MAX_UNITS 8 /* More are supported, limit only on options */
46static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49/* Operational parameters that are set at compile time. */
50/* Keep the ring sizes a power of two for compile efficiency. */
51/* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52/* Making the Tx ring too large decreases the effectiveness of channel */
53/* bonding and packet priority. */
54/* There are no ill effects from too-large receive rings. */
55// 88-12-9 modify,
56// #define TX_RING_SIZE 16
57// #define RX_RING_SIZE 32
58#define TX_RING_SIZE 6
59#define RX_RING_SIZE 12
60#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63/* Operational parameters that usually are not changed. */
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (2*HZ)
66
67#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70/* Include files, designed to support most kernel versions 2.0.0 and later. */
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
77#include <linux/slab.h>
78#include <linux/interrupt.h>
79#include <linux/pci.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/init.h>
84#include <linux/mii.h>
85#include <linux/ethtool.h>
86#include <linux/crc32.h>
87#include <linux/delay.h>
88#include <linux/bitops.h>
89
90#include <asm/processor.h> /* Processor type for cache alignment. */
91#include <asm/io.h>
92#include <asm/uaccess.h>
93
94/* These identify the driver base version and may not be removed. */
95static char version[] __devinitdata =
96KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99/* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101#ifndef __alpha__
102#define USE_IO_OPS
103#endif
104
105/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106/* This is only in the support-all-kernels source code. */
107
108#define RUN_AT(x) (jiffies + (x))
109
110MODULE_AUTHOR("Myson or whoever");
111MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112MODULE_LICENSE("GPL");
113module_param(max_interrupt_work, int, 0);
114//MODULE_PARM(min_pci_latency, "i");
115module_param(debug, int, 0);
116module_param(rx_copybreak, int, 0);
117module_param(multicast_filter_limit, int, 0);
118module_param_array(options, int, NULL, 0);
119module_param_array(full_duplex, int, NULL, 0);
120MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
121MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
122MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
123MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
124MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
125MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
126
127#define MIN_REGION_SIZE 136
128
1da177e4
LT		 129/* A chip capabilities table, matching the entries in pci_tbl[] above. */
130enum chip_capability_flags {
131 HAS_MII_XCVR,
132 HAS_CHIP_XCVR,
133};
134
135/* 89/6/13 add, */
136/* for different PHY */
137enum phy_type_flags {
138 MysonPHY = 1,
139 AhdocPHY = 2,
140 SeeqPHY = 3,
141 MarvellPHY = 4,
142 Myson981 = 5,
143 LevelOnePHY = 6,
144 OtherPHY = 10,
145};
146
147struct chip_info {
148 char *chip_name;
149 int io_size;
150 int flags;
151};
152
f71e1309 153static const struct chip_info skel_netdrv_tbl[] = {
1da177e4
LT		 154 {"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
155 {"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR},
156 {"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
157};
158
159/* Offsets to the Command and Status Registers. */
160enum fealnx_offsets {
161 PAR0 = 0x0, /* physical address 0-3 */
162 PAR1 = 0x04, /* physical address 4-5 */
163 MAR0 = 0x08, /* multicast address 0-3 */
164 MAR1 = 0x0C, /* multicast address 4-7 */
165 FAR0 = 0x10, /* flow-control address 0-3 */
166 FAR1 = 0x14, /* flow-control address 4-5 */
167 TCRRCR = 0x18, /* receive & transmit configuration */
168 BCR = 0x1C, /* bus command */
169 TXPDR = 0x20, /* transmit polling demand */
170 RXPDR = 0x24, /* receive polling demand */
171 RXCWP = 0x28, /* receive current word pointer */
172 TXLBA = 0x2C, /* transmit list base address */
173 RXLBA = 0x30, /* receive list base address */
174 ISR = 0x34, /* interrupt status */
175 IMR = 0x38, /* interrupt mask */
176 FTH = 0x3C, /* flow control high/low threshold */
177 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
178 TALLY = 0x44, /* tally counters for crc and mpa */
179 TSR = 0x48, /* tally counter for transmit status */
180 BMCRSR = 0x4c, /* basic mode control and status */
181 PHYIDENTIFIER = 0x50, /* phy identifier */
182 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
183 partner ability */
184 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
185 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
186};
187
188/* Bits in the interrupt status/enable registers. */
189/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
190enum intr_status_bits {
191 RFCON = 0x00020000, /* receive flow control xon packet */
192 RFCOFF = 0x00010000, /* receive flow control xoff packet */
193 LSCStatus = 0x00008000, /* link status change */
194 ANCStatus = 0x00004000, /* autonegotiation completed */
195 FBE = 0x00002000, /* fatal bus error */
196 FBEMask = 0x00001800, /* mask bit12-11 */
197 ParityErr = 0x00000000, /* parity error */
198 TargetErr = 0x00001000, /* target abort */
199 MasterErr = 0x00000800, /* master error */
200 TUNF = 0x00000400, /* transmit underflow */
201 ROVF = 0x00000200, /* receive overflow */
202 ETI = 0x00000100, /* transmit early int */
203 ERI = 0x00000080, /* receive early int */
204 CNTOVF = 0x00000040, /* counter overflow */
205 RBU = 0x00000020, /* receive buffer unavailable */
206 TBU = 0x00000010, /* transmit buffer unavilable */
207 TI = 0x00000008, /* transmit interrupt */
208 RI = 0x00000004, /* receive interrupt */
209 RxErr = 0x00000002, /* receive error */
210};
211
212/* Bits in the NetworkConfig register, W for writing, R for reading */
213/* FIXME: some names are invented by me. Marked with (name?) */
214/* If you have docs and know bit names, please fix 'em */
215enum rx_mode_bits {
216 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
217 CR_W_FD = 0x00100000, /* full duplex */
218 CR_W_PS10 = 0x00080000, /* 10 mbit */
219 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
220 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
221 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
222 CR_W_RXMODEMASK = 0x000000e0,
223 CR_W_PROM = 0x00000080, /* promiscuous mode */
224 CR_W_AB = 0x00000040, /* accept broadcast */
225 CR_W_AM = 0x00000020, /* accept mutlicast */
226 CR_W_ARP = 0x00000008, /* receive runt pkt */
227 CR_W_ALP = 0x00000004, /* receive long pkt */
228 CR_W_SEP = 0x00000002, /* receive error pkt */
229 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
230
231 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
232 CR_R_FD = 0x00100000, /* full duplex detected */
233 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
234 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
235};
236
237/* The Tulip Rx and Tx buffer descriptors. */
238struct fealnx_desc {
239 s32 status;
240 s32 control;
241 u32 buffer;
242 u32 next_desc;
243 struct fealnx_desc *next_desc_logical;
244 struct sk_buff *skbuff;
245 u32 reserved1;
246 u32 reserved2;
247};
248
249/* Bits in network_desc.status */
250enum rx_desc_status_bits {
251 RXOWN = 0x80000000, /* own bit */
252 FLNGMASK = 0x0fff0000, /* frame length */
253 FLNGShift = 16,
254 MARSTATUS = 0x00004000, /* multicast address received */
255 BARSTATUS = 0x00002000, /* broadcast address received */
256 PHYSTATUS = 0x00001000, /* physical address received */
257 RXFSD = 0x00000800, /* first descriptor */
258 RXLSD = 0x00000400, /* last descriptor */
259 ErrorSummary = 0x80, /* error summary */
260 RUNT = 0x40, /* runt packet received */
261 LONG = 0x20, /* long packet received */
262 FAE = 0x10, /* frame align error */
263 CRC = 0x08, /* crc error */
264 RXER = 0x04, /* receive error */
265};
266
267enum rx_desc_control_bits {
268 RXIC = 0x00800000, /* interrupt control */
269 RBSShift = 0,
270};
271
272enum tx_desc_status_bits {
273 TXOWN = 0x80000000, /* own bit */
274 JABTO = 0x00004000, /* jabber timeout */
275 CSL = 0x00002000, /* carrier sense lost */
276 LC = 0x00001000, /* late collision */
277 EC = 0x00000800, /* excessive collision */
278 UDF = 0x00000400, /* fifo underflow */
279 DFR = 0x00000200, /* deferred */
280 HF = 0x00000100, /* heartbeat fail */
281 NCRMask = 0x000000ff, /* collision retry count */
282 NCRShift = 0,
283};
284
285enum tx_desc_control_bits {
286 TXIC = 0x80000000, /* interrupt control */
287 ETIControl = 0x40000000, /* early transmit interrupt */
288 TXLD = 0x20000000, /* last descriptor */
289 TXFD = 0x10000000, /* first descriptor */
290 CRCEnable = 0x08000000, /* crc control */
291 PADEnable = 0x04000000, /* padding control */
292 RetryTxLC = 0x02000000, /* retry late collision */
293 PKTSMask = 0x3ff800, /* packet size bit21-11 */
294 PKTSShift = 11,
295 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
296 TBSShift = 0,
297};
298
299/* BootROM/EEPROM/MII Management Register */
300#define MASK_MIIR_MII_READ 0x00000000
301#define MASK_MIIR_MII_WRITE 0x00000008
302#define MASK_MIIR_MII_MDO 0x00000004
303#define MASK_MIIR_MII_MDI 0x00000002
304#define MASK_MIIR_MII_MDC 0x00000001
305
306/* ST+OP+PHYAD+REGAD+TA */
307#define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308#define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
309
310/* ------------------------------------------------------------------------- */
311/* Constants for Myson PHY */
312/* ------------------------------------------------------------------------- */
313#define MysonPHYID 0xd0000302
314/* 89-7-27 add, (begin) */
315#define MysonPHYID0 0x0302
316#define StatusRegister 18
317#define SPEED100 0x0400 // bit10
318#define FULLMODE 0x0800 // bit11
319/* 89-7-27 add, (end) */
320
321/* ------------------------------------------------------------------------- */
322/* Constants for Seeq 80225 PHY */
323/* ------------------------------------------------------------------------- */
324#define SeeqPHYID0 0x0016
325
326#define MIIRegister18 18
327#define SPD_DET_100 0x80
328#define DPLX_DET_FULL 0x40
329
330/* ------------------------------------------------------------------------- */
331/* Constants for Ahdoc 101 PHY */
332/* ------------------------------------------------------------------------- */
333#define AhdocPHYID0 0x0022
334
335#define DiagnosticReg 18
336#define DPLX_FULL 0x0800
337#define Speed_100 0x0400
338
339/* 89/6/13 add, */
340/* -------------------------------------------------------------------------- */
341/* Constants */
342/* -------------------------------------------------------------------------- */
343#define MarvellPHYID0 0x0141
344#define LevelOnePHYID0 0x0013
345
346#define MII1000BaseTControlReg 9
347#define MII1000BaseTStatusReg 10
348#define SpecificReg 17
349
350/* for 1000BaseT Control Register */
351#define PHYAbletoPerform1000FullDuplex 0x0200
352#define PHYAbletoPerform1000HalfDuplex 0x0100
353#define PHY1000AbilityMask 0x300
354
355// for phy specific status register, marvell phy.
356#define SpeedMask 0x0c000
357#define Speed_1000M 0x08000
358#define Speed_100M 0x4000
359#define Speed_10M 0
360#define Full_Duplex 0x2000
361
362// 89/12/29 add, for phy specific status register, levelone phy, (begin)
363#define LXT1000_100M 0x08000
364#define LXT1000_1000M 0x0c000
365#define LXT1000_Full 0x200
366// 89/12/29 add, for phy specific status register, levelone phy, (end)
367
368/* for 3-in-1 case, BMCRSR register */
369#define LinkIsUp2 0x00040000
370
371/* for PHY */
372#define LinkIsUp 0x0004
373
374
375struct netdev_private {
376 /* Descriptor rings first for alignment. */
377 struct fealnx_desc *rx_ring;
378 struct fealnx_desc *tx_ring;
379
380 dma_addr_t rx_ring_dma;
381 dma_addr_t tx_ring_dma;
382
383 spinlock_t lock;
384
385 struct net_device_stats stats;
386
387 /* Media monitoring timer. */
388 struct timer_list timer;
389
390 /* Reset timer */
391 struct timer_list reset_timer;
392 int reset_timer_armed;
393 unsigned long crvalue_sv;
394 unsigned long imrvalue_sv;
395
396 /* Frequently used values: keep some adjacent for cache effect. */
397 int flags;
398 struct pci_dev *pci_dev;
399 unsigned long crvalue;
400 unsigned long bcrvalue;
401 unsigned long imrvalue;
402 struct fealnx_desc *cur_rx;
403 struct fealnx_desc *lack_rxbuf;
404 int really_rx_count;
405 struct fealnx_desc *cur_tx;
406 struct fealnx_desc *cur_tx_copy;
407 int really_tx_count;
408 int free_tx_count;
409 unsigned int rx_buf_sz; /* Based on MTU+slack. */
410
411 /* These values are keep track of the transceiver/media in use. */
412 unsigned int linkok;
413 unsigned int line_speed;
414 unsigned int duplexmode;
415 unsigned int default_port:4; /* Last dev->if_port value. */
416 unsigned int PHYType;
417
418 /* MII transceiver section. */
419 int mii_cnt; /* MII device addresses. */
420 unsigned char phys[2]; /* MII device addresses. */
421 struct mii_if_info mii;
422 void __iomem *mem;
423};
424
425
426static int mdio_read(struct net_device *dev, int phy_id, int location);
427static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
428static int netdev_open(struct net_device *dev);
429static void getlinktype(struct net_device *dev);
430static void getlinkstatus(struct net_device *dev);
431static void netdev_timer(unsigned long data);
432static void reset_timer(unsigned long data);
433static void tx_timeout(struct net_device *dev);
434static void init_ring(struct net_device *dev);
435static int start_tx(struct sk_buff *skb, struct net_device *dev);
436static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
437static int netdev_rx(struct net_device *dev);
438static void set_rx_mode(struct net_device *dev);
439static void __set_rx_mode(struct net_device *dev);
440static struct net_device_stats *get_stats(struct net_device *dev);
441static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
442static struct ethtool_ops netdev_ethtool_ops;
443static int netdev_close(struct net_device *dev);
444static void reset_rx_descriptors(struct net_device *dev);
445static void reset_tx_descriptors(struct net_device *dev);
446
447static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
448{
449 int delay = 0x1000;
450 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
451 while (--delay) {
452 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
453 break;
454 }
455}
456
457
458static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
459{
460 int delay = 0x1000;
461 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
462 while (--delay) {
463 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
464 == (CR_R_RXSTOP+CR_R_TXSTOP) )
465 break;
466 }
467}
468
469
470static int __devinit fealnx_init_one(struct pci_dev *pdev,
471 const struct pci_device_id *ent)
472{
473 struct netdev_private *np;
474 int i, option, err, irq;
475 static int card_idx = -1;
476 char boardname[12];
477 void __iomem *ioaddr;
478 unsigned long len;
479 unsigned int chip_id = ent->driver_data;
480 struct net_device *dev;
481 void *ring_space;
482 dma_addr_t ring_dma;
483#ifdef USE_IO_OPS
484 int bar = 0;
485#else
486 int bar = 1;
487#endif
488
489/* when built into the kernel, we only print version if device is found */
490#ifndef MODULE
491 static int printed_version;
492 if (!printed_version++)
493 printk(version);
494#endif
495
496 card_idx++;
497 sprintf(boardname, "fealnx%d", card_idx);
498
499 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
500
501 i = pci_enable_device(pdev);
502 if (i) return i;
503 pci_set_master(pdev);
504
505 len = pci_resource_len(pdev, bar);
506 if (len < MIN_REGION_SIZE) {
507 printk(KERN_ERR "%s: region size %ld too small, aborting\n",
508 boardname, len);
509 return -ENODEV;
510 }
511
512 i = pci_request_regions(pdev, boardname);
513 if (i) return i;
514
515 irq = pdev->irq;
516
517 ioaddr = pci_iomap(pdev, bar, len);
518 if (!ioaddr) {
519 err = -ENOMEM;
520 goto err_out_res;
521 }
522
523 dev = alloc_etherdev(sizeof(struct netdev_private));
524 if (!dev) {
525 err = -ENOMEM;
526 goto err_out_unmap;
527 }
528 SET_MODULE_OWNER(dev);
529 SET_NETDEV_DEV(dev, &pdev->dev);
530
531 /* read ethernet id */
532 for (i = 0; i < 6; ++i)
533 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
534
535 /* Reset the chip to erase previous misconfiguration. */
536 iowrite32(0x00000001, ioaddr + BCR);
537
538 dev->base_addr = (unsigned long)ioaddr;
539 dev->irq = irq;
540
541 /* Make certain the descriptor lists are aligned. */
542 np = netdev_priv(dev);
543 np->mem = ioaddr;
544 spin_lock_init(&np->lock);
545 np->pci_dev = pdev;
546 np->flags = skel_netdrv_tbl[chip_id].flags;
547 pci_set_drvdata(pdev, dev);
548 np->mii.dev = dev;
549 np->mii.mdio_read = mdio_read;
550 np->mii.mdio_write = mdio_write;
551 np->mii.phy_id_mask = 0x1f;
552 np->mii.reg_num_mask = 0x1f;
553
554 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
555 if (!ring_space) {
556 err = -ENOMEM;
557 goto err_out_free_dev;
558 }
559 np->rx_ring = (struct fealnx_desc *)ring_space;
560 np->rx_ring_dma = ring_dma;
561
562 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
563 if (!ring_space) {
564 err = -ENOMEM;
565 goto err_out_free_rx;
566 }
567 np->tx_ring = (struct fealnx_desc *)ring_space;
568 np->tx_ring_dma = ring_dma;
569
570 /* find the connected MII xcvrs */
571 if (np->flags == HAS_MII_XCVR) {
572 int phy, phy_idx = 0;
573
574 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
575 int mii_status = mdio_read(dev, phy, 1);
576
577 if (mii_status != 0xffff && mii_status != 0x0000) {
578 np->phys[phy_idx++] = phy;
579 printk(KERN_INFO
580 "%s: MII PHY found at address %d, status "
581 "0x%4.4x.\n", dev->name, phy, mii_status);
582 /* get phy type */
583 {
584 unsigned int data;
585
586 data = mdio_read(dev, np->phys[0], 2);
587 if (data == SeeqPHYID0)
588 np->PHYType = SeeqPHY;
589 else if (data == AhdocPHYID0)
590 np->PHYType = AhdocPHY;
591 else if (data == MarvellPHYID0)
592 np->PHYType = MarvellPHY;
593 else if (data == MysonPHYID0)
594 np->PHYType = Myson981;
595 else if (data == LevelOnePHYID0)
596 np->PHYType = LevelOnePHY;
597 else
598 np->PHYType = OtherPHY;
599 }
600 }
601 }
602
603 np->mii_cnt = phy_idx;
604 if (phy_idx == 0) {
605 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
606 "not operate correctly.\n", dev->name);
607 }
608 } else {
609 np->phys[0] = 32;
610/* 89/6/23 add, (begin) */
611 /* get phy type */
612 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
613 np->PHYType = MysonPHY;
614 else
615 np->PHYType = OtherPHY;
616 }
617 np->mii.phy_id = np->phys[0];
618
619 if (dev->mem_start)
620 option = dev->mem_start;
621
622 /* The lower four bits are the media type. */
623 if (option > 0) {
624 if (option & 0x200)
625 np->mii.full_duplex = 1;
626 np->default_port = option & 15;
627 }
628
629 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
630 np->mii.full_duplex = full_duplex[card_idx];
631
632 if (np->mii.full_duplex) {
633 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
634/* 89/6/13 add, (begin) */
635// if (np->PHYType==MarvellPHY)
636 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
637 unsigned int data;
638
639 data = mdio_read(dev, np->phys[0], 9);
640 data = (data & 0xfcff) | 0x0200;
641 mdio_write(dev, np->phys[0], 9, data);
642 }
643/* 89/6/13 add, (end) */
644 if (np->flags == HAS_MII_XCVR)
645 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
646 else
647 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
648 np->mii.force_media = 1;
649 }
650
651 /* The chip-specific entries in the device structure. */
652 dev->open = &netdev_open;
653 dev->hard_start_xmit = &start_tx;
654 dev->stop = &netdev_close;
655 dev->get_stats = &get_stats;
656 dev->set_multicast_list = &set_rx_mode;
657 dev->do_ioctl = &mii_ioctl;
658 dev->ethtool_ops = &netdev_ethtool_ops;
659 dev->tx_timeout = &tx_timeout;
660 dev->watchdog_timeo = TX_TIMEOUT;
661
662 err = register_netdev(dev);
663 if (err)
664 goto err_out_free_tx;
665
666 printk(KERN_INFO "%s: %s at %p, ",
667 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
668 for (i = 0; i < 5; i++)
669 printk("%2.2x:", dev->dev_addr[i]);
670 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
671
672 return 0;
673
674err_out_free_tx:
675 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
676err_out_free_rx:
677 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
678err_out_free_dev:
679 free_netdev(dev);
680err_out_unmap:
681 pci_iounmap(pdev, ioaddr);
682err_out_res:
683 pci_release_regions(pdev);
684 return err;
685}
686
687
688static void __devexit fealnx_remove_one(struct pci_dev *pdev)
689{
690 struct net_device *dev = pci_get_drvdata(pdev);
691
692 if (dev) {
693 struct netdev_private *np = netdev_priv(dev);
694
695 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
696 np->tx_ring_dma);
697 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
698 np->rx_ring_dma);
699 unregister_netdev(dev);
700 pci_iounmap(pdev, np->mem);
701 free_netdev(dev);
702 pci_release_regions(pdev);
703 pci_set_drvdata(pdev, NULL);
704 } else
705 printk(KERN_ERR "fealnx: remove for unknown device\n");
706}
707
708
709static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
710{
711 ulong miir;
712 int i;
713 unsigned int mask, data;
714
715 /* enable MII output */
716 miir = (ulong) ioread32(miiport);
717 miir &= 0xfffffff0;
718
719 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
720
721 /* send 32 1's preamble */
722 for (i = 0; i < 32; i++) {
723 /* low MDC; MDO is already high (miir) */
724 miir &= ~MASK_MIIR_MII_MDC;
725 iowrite32(miir, miiport);
726
727 /* high MDC */
728 miir |= MASK_MIIR_MII_MDC;
729 iowrite32(miir, miiport);
730 }
731
732 /* calculate ST+OP+PHYAD+REGAD+TA */
733 data = opcode | (phyad << 7) | (regad << 2);
734
735 /* sent out */
736 mask = 0x8000;
737 while (mask) {
738 /* low MDC, prepare MDO */
739 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
740 if (mask & data)
741 miir |= MASK_MIIR_MII_MDO;
742
743 iowrite32(miir, miiport);
744 /* high MDC */
745 miir |= MASK_MIIR_MII_MDC;
746 iowrite32(miir, miiport);
747 udelay(30);
748
749 /* next */
750 mask >>= 1;
751 if (mask == 0x2 && opcode == OP_READ)
752 miir &= ~MASK_MIIR_MII_WRITE;
753 }
754 return miir;
755}
756
757
758static int mdio_read(struct net_device *dev, int phyad, int regad)
759{
760 struct netdev_private *np = netdev_priv(dev);
761 void __iomem *miiport = np->mem + MANAGEMENT;
762 ulong miir;
763 unsigned int mask, data;
764
765 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
766
767 /* read data */
768 mask = 0x8000;
769 data = 0;
770 while (mask) {
771 /* low MDC */
772 miir &= ~MASK_MIIR_MII_MDC;
773 iowrite32(miir, miiport);
774
775 /* read MDI */
776 miir = ioread32(miiport);
777 if (miir & MASK_MIIR_MII_MDI)
778 data |= mask;
779
780 /* high MDC, and wait */
781 miir |= MASK_MIIR_MII_MDC;
782 iowrite32(miir, miiport);
783 udelay(30);
784
785 /* next */
786 mask >>= 1;
787 }
788
789 /* low MDC */
790 miir &= ~MASK_MIIR_MII_MDC;
791 iowrite32(miir, miiport);
792
793 return data & 0xffff;
794}
795
796
797static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
798{
799 struct netdev_private *np = netdev_priv(dev);
800 void __iomem *miiport = np->mem + MANAGEMENT;
801 ulong miir;
802 unsigned int mask;
803
804 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
805
806 /* write data */
807 mask = 0x8000;
808 while (mask) {
809 /* low MDC, prepare MDO */
810 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
811 if (mask & data)
812 miir |= MASK_MIIR_MII_MDO;
813 iowrite32(miir, miiport);
814
815 /* high MDC */
816 miir |= MASK_MIIR_MII_MDC;
817 iowrite32(miir, miiport);
818
819 /* next */
820 mask >>= 1;
821 }
822
823 /* low MDC */
824 miir &= ~MASK_MIIR_MII_MDC;
825 iowrite32(miir, miiport);
826}
827
828
829static int netdev_open(struct net_device *dev)
830{
831 struct netdev_private *np = netdev_priv(dev);
832 void __iomem *ioaddr = np->mem;
833 int i;
834
835 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
836
1fb9df5d 837 if (request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev))
1da177e4
LT		 838 return -EAGAIN;
839
840 for (i = 0; i < 3; i++)
841 iowrite16(((unsigned short*)dev->dev_addr)[i],
842 ioaddr + PAR0 + i*2);
843
844 init_ring(dev);
845
846 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
847 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
848
849 /* Initialize other registers. */
850 /* Configure the PCI bus bursts and FIFO thresholds.
851 486: Set 8 longword burst.
852 586: no burst limit.
853 Burst length 5:3
854 0 0 0 1
855 0 0 1 4
856 0 1 0 8
857 0 1 1 16
858 1 0 0 32
859 1 0 1 64
860 1 1 0 128
861 1 1 1 256
862 Wait the specified 50 PCI cycles after a reset by initializing
863 Tx and Rx queues and the address filter list.
864 FIXME (Ueimor): optimistic for alpha + posted writes ? */
865#if defined(__powerpc__) || defined(__sparc__)
866// 89/9/1 modify,
867// np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
868 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
869 np->crvalue = 0xe00; /* rx 128 burst length */
870#elif defined(__alpha__) || defined(__x86_64__)
871// 89/9/1 modify,
872// np->bcrvalue=0x38; /* little-endian, 256 burst length */
873 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
874 np->crvalue = 0xe00; /* rx 128 burst length */
875#elif defined(__i386__)
876#if defined(MODULE)
877// 89/9/1 modify,
878// np->bcrvalue=0x38; /* little-endian, 256 burst length */
879 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
880 np->crvalue = 0xe00; /* rx 128 burst length */
881#else
882 /* When not a module we can work around broken '486 PCI boards. */
883#define x86 boot_cpu_data.x86
884// 89/9/1 modify,
885// np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
886 np->bcrvalue = 0x10;
887 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
888 if (x86 <= 4)
889 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
890 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
891#endif
892#else
893// 89/9/1 modify,
894// np->bcrvalue=0x38;
895 np->bcrvalue = 0x10;
896 np->crvalue = 0xe00; /* rx 128 burst length */
897#warning Processor architecture undefined!
898#endif
899// 89/12/29 add,
900// 90/1/16 modify,
901// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
902 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
903 if (np->pci_dev->device == 0x891) {
904 np->bcrvalue |= 0x200; /* set PROG bit */
905 np->crvalue |= CR_W_ENH; /* set enhanced bit */
906 np->imrvalue |= ETI;
907 }
908 iowrite32(np->bcrvalue, ioaddr + BCR);
909
910 if (dev->if_port == 0)
911 dev->if_port = np->default_port;
912
913 iowrite32(0, ioaddr + RXPDR);
914// 89/9/1 modify,
915// np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
916 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
917 np->mii.full_duplex = np->mii.force_media;
918 getlinkstatus(dev);
919 if (np->linkok)
920 getlinktype(dev);
921 __set_rx_mode(dev);
922
923 netif_start_queue(dev);
924
925 /* Clear and Enable interrupts by setting the interrupt mask. */
926 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
927 iowrite32(np->imrvalue, ioaddr + IMR);
928
929 if (debug)
930 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
931
932 /* Set the timer to check for link beat. */
933 init_timer(&np->timer);
934 np->timer.expires = RUN_AT(3 * HZ);
935 np->timer.data = (unsigned long) dev;
936 np->timer.function = &netdev_timer;
937
938 /* timer handler */
939 add_timer(&np->timer);
940
941 init_timer(&np->reset_timer);
942 np->reset_timer.data = (unsigned long) dev;
943 np->reset_timer.function = &reset_timer;
944 np->reset_timer_armed = 0;
945
946 return 0;
947}
948
949
950static void getlinkstatus(struct net_device *dev)
951/* function: Routine will read MII Status Register to get link status. */
952/* input : dev... pointer to the adapter block. */
953/* output : none. */
954{
955 struct netdev_private *np = netdev_priv(dev);
956 unsigned int i, DelayTime = 0x1000;
957
958 np->linkok = 0;
959
960 if (np->PHYType == MysonPHY) {
961 for (i = 0; i < DelayTime; ++i) {
962 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
963 np->linkok = 1;
964 return;
965 }
966 udelay(100);
967 }
968 } else {
969 for (i = 0; i < DelayTime; ++i) {
970 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
971 np->linkok = 1;
972 return;
973 }
974 udelay(100);
975 }
976 }
977}
978
979
980static void getlinktype(struct net_device *dev)
981{
982 struct netdev_private *np = netdev_priv(dev);
983
984 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
985 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
986 np->duplexmode = 2; /* full duplex */
987 else
988 np->duplexmode = 1; /* half duplex */
989 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
990 np->line_speed = 1; /* 10M */
991 else
992 np->line_speed = 2; /* 100M */
993 } else {
994 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
995 unsigned int data;
996
997 data = mdio_read(dev, np->phys[0], MIIRegister18);
998 if (data & SPD_DET_100)
999 np->line_speed = 2; /* 100M */
1000 else
1001 np->line_speed = 1; /* 10M */
1002 if (data & DPLX_DET_FULL)
1003 np->duplexmode = 2; /* full duplex mode */
1004 else
1005 np->duplexmode = 1; /* half duplex mode */
1006 } else if (np->PHYType == AhdocPHY) {
1007 unsigned int data;
1008
1009 data = mdio_read(dev, np->phys[0], DiagnosticReg);
1010 if (data & Speed_100)
1011 np->line_speed = 2; /* 100M */
1012 else
1013 np->line_speed = 1; /* 10M */
1014 if (data & DPLX_FULL)
1015 np->duplexmode = 2; /* full duplex mode */
1016 else
1017 np->duplexmode = 1; /* half duplex mode */
1018 }
1019/* 89/6/13 add, (begin) */
1020 else if (np->PHYType == MarvellPHY) {
1021 unsigned int data;
1022
1023 data = mdio_read(dev, np->phys[0], SpecificReg);
1024 if (data & Full_Duplex)
1025 np->duplexmode = 2; /* full duplex mode */
1026 else
1027 np->duplexmode = 1; /* half duplex mode */
1028 data &= SpeedMask;
1029 if (data == Speed_1000M)
1030 np->line_speed = 3; /* 1000M */
1031 else if (data == Speed_100M)
1032 np->line_speed = 2; /* 100M */
1033 else
1034 np->line_speed = 1; /* 10M */
1035 }
1036/* 89/6/13 add, (end) */
1037/* 89/7/27 add, (begin) */
1038 else if (np->PHYType == Myson981) {
1039 unsigned int data;
1040
1041 data = mdio_read(dev, np->phys[0], StatusRegister);
1042
1043 if (data & SPEED100)
1044 np->line_speed = 2;
1045 else
1046 np->line_speed = 1;
1047
1048 if (data & FULLMODE)
1049 np->duplexmode = 2;
1050 else
1051 np->duplexmode = 1;
1052 }
1053/* 89/7/27 add, (end) */
1054/* 89/12/29 add */
1055 else if (np->PHYType == LevelOnePHY) {
1056 unsigned int data;
1057
1058 data = mdio_read(dev, np->phys[0], SpecificReg);
1059 if (data & LXT1000_Full)
1060 np->duplexmode = 2; /* full duplex mode */
1061 else
1062 np->duplexmode = 1; /* half duplex mode */
1063 data &= SpeedMask;
1064 if (data == LXT1000_1000M)
1065 np->line_speed = 3; /* 1000M */
1066 else if (data == LXT1000_100M)
1067 np->line_speed = 2; /* 100M */
1068 else
1069 np->line_speed = 1; /* 10M */
1070 }
1071 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1072 if (np->line_speed == 1)
1073 np->crvalue |= CR_W_PS10;
1074 else if (np->line_speed == 3)
1075 np->crvalue |= CR_W_PS1000;
1076 if (np->duplexmode == 2)
1077 np->crvalue |= CR_W_FD;
1078 }
1079}
1080
1081
1082/* Take lock before calling this */
1083static void allocate_rx_buffers(struct net_device *dev)
1084{
1085 struct netdev_private *np = netdev_priv(dev);
1086
1087 /* allocate skb for rx buffers */
1088 while (np->really_rx_count != RX_RING_SIZE) {
1089 struct sk_buff *skb;
1090
1091 skb = dev_alloc_skb(np->rx_buf_sz);
1092 if (skb == NULL)
1093 break; /* Better luck next round. */
1094
1095 while (np->lack_rxbuf->skbuff)
1096 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1097
1098 skb->dev = dev; /* Mark as being used by this device. */
1099 np->lack_rxbuf->skbuff = skb;
689be439 1100 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1da177e4
LT		 1101 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1102 np->lack_rxbuf->status = RXOWN;
1103 ++np->really_rx_count;
1104 }
1105}
1106
1107
1108static void netdev_timer(unsigned long data)
1109{
1110 struct net_device *dev = (struct net_device *) data;
1111 struct netdev_private *np = netdev_priv(dev);
1112 void __iomem *ioaddr = np->mem;
1113 int old_crvalue = np->crvalue;
1114 unsigned int old_linkok = np->linkok;
1115 unsigned long flags;
1116
1117 if (debug)
1118 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1119 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1120 ioread32(ioaddr + TCRRCR));
1121
1122 spin_lock_irqsave(&np->lock, flags);
1123
1124 if (np->flags == HAS_MII_XCVR) {
1125 getlinkstatus(dev);
1126 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1127 getlinktype(dev);
1128 if (np->crvalue != old_crvalue) {
1129 stop_nic_rxtx(ioaddr, np->crvalue);
1130 iowrite32(np->crvalue, ioaddr + TCRRCR);
1131 }
1132 }
1133 }
1134
1135 allocate_rx_buffers(dev);
1136
1137 spin_unlock_irqrestore(&np->lock, flags);
1138
1139 np->timer.expires = RUN_AT(10 * HZ);
1140 add_timer(&np->timer);
1141}
1142
1143
1144/* Take lock before calling */
1145/* Reset chip and disable rx, tx and interrupts */
1146static void reset_and_disable_rxtx(struct net_device *dev)
1147{
1148 struct netdev_private *np = netdev_priv(dev);
1149 void __iomem *ioaddr = np->mem;
1150 int delay=51;
1151
1152 /* Reset the chip's Tx and Rx processes. */
1153 stop_nic_rxtx(ioaddr, 0);
1154
1155 /* Disable interrupts by clearing the interrupt mask. */
1156 iowrite32(0, ioaddr + IMR);
1157
1158 /* Reset the chip to erase previous misconfiguration. */
1159 iowrite32(0x00000001, ioaddr + BCR);
1160
1161 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1162 We surely wait too long (address+data phase). Who cares? */
1163 while (--delay) {
1164 ioread32(ioaddr + BCR);
1165 rmb();
1166 }
1167}
1168
1169
1170/* Take lock before calling */
1171/* Restore chip after reset */
1172static void enable_rxtx(struct net_device *dev)
1173{
1174 struct netdev_private *np = netdev_priv(dev);
1175 void __iomem *ioaddr = np->mem;
1176
1177 reset_rx_descriptors(dev);
1178
1179 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1180 ioaddr + TXLBA);
1181 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1182 ioaddr + RXLBA);
1183
1184 iowrite32(np->bcrvalue, ioaddr + BCR);
1185
1186 iowrite32(0, ioaddr + RXPDR);
1187 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1188
1189 /* Clear and Enable interrupts by setting the interrupt mask. */
1190 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1191 iowrite32(np->imrvalue, ioaddr + IMR);
1192
1193 iowrite32(0, ioaddr + TXPDR);
1194}
1195
1196
1197static void reset_timer(unsigned long data)
1198{
1199 struct net_device *dev = (struct net_device *) data;
1200 struct netdev_private *np = netdev_priv(dev);
1201 unsigned long flags;
1202
1203 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1204
1205 spin_lock_irqsave(&np->lock, flags);
1206 np->crvalue = np->crvalue_sv;
1207 np->imrvalue = np->imrvalue_sv;
1208
1209 reset_and_disable_rxtx(dev);
1210 /* works for me without this:
1211 reset_tx_descriptors(dev); */
1212 enable_rxtx(dev);
1213 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1214
1215 np->reset_timer_armed = 0;
1216
1217 spin_unlock_irqrestore(&np->lock, flags);
1218}
1219
1220
1221static void tx_timeout(struct net_device *dev)
1222{
1223 struct netdev_private *np = netdev_priv(dev);
1224 void __iomem *ioaddr = np->mem;
1225 unsigned long flags;
1226 int i;
1227
1228 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1229 " resetting...\n", dev->name, ioread32(ioaddr + ISR));
1230
1231 {
1232 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1233 for (i = 0; i < RX_RING_SIZE; i++)
1234 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1235 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1236 for (i = 0; i < TX_RING_SIZE; i++)
1237 printk(" %4.4x", np->tx_ring[i].status);
1238 printk("\n");
1239 }
1240
1241 spin_lock_irqsave(&np->lock, flags);
1242
1243 reset_and_disable_rxtx(dev);
1244 reset_tx_descriptors(dev);
1245 enable_rxtx(dev);
1246
1247 spin_unlock_irqrestore(&np->lock, flags);
1248
1249 dev->trans_start = jiffies;
1250 np->stats.tx_errors++;
1251 netif_wake_queue(dev); /* or .._start_.. ?? */
1252}
1253
1254
1255/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1256static void init_ring(struct net_device *dev)
1257{
1258 struct netdev_private *np = netdev_priv(dev);
1259 int i;
1260
1261 /* initialize rx variables */
1262 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1263 np->cur_rx = &np->rx_ring[0];
1264 np->lack_rxbuf = np->rx_ring;
1265 np->really_rx_count = 0;
1266
1267 /* initial rx descriptors. */
1268 for (i = 0; i < RX_RING_SIZE; i++) {
1269 np->rx_ring[i].status = 0;
1270 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1271 np->rx_ring[i].next_desc = np->rx_ring_dma +
1272 (i + 1)*sizeof(struct fealnx_desc);
1273 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1274 np->rx_ring[i].skbuff = NULL;
1275 }
1276
1277 /* for the last rx descriptor */
1278 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1279 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1280
1281 /* allocate skb for rx buffers */
1282 for (i = 0; i < RX_RING_SIZE; i++) {
1283 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1284
1285 if (skb == NULL) {
1286 np->lack_rxbuf = &np->rx_ring[i];
1287 break;
1288 }
1289
1290 ++np->really_rx_count;
1291 np->rx_ring[i].skbuff = skb;
1292 skb->dev = dev; /* Mark as being used by this device. */
689be439 1293 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1da177e4
LT		 1294 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1295 np->rx_ring[i].status = RXOWN;
1296 np->rx_ring[i].control |= RXIC;
1297 }
1298
1299 /* initialize tx variables */
1300 np->cur_tx = &np->tx_ring[0];
1301 np->cur_tx_copy = &np->tx_ring[0];
1302 np->really_tx_count = 0;
1303 np->free_tx_count = TX_RING_SIZE;
1304
1305 for (i = 0; i < TX_RING_SIZE; i++) {
1306 np->tx_ring[i].status = 0;
1307 /* do we need np->tx_ring[i].control = XXX; ?? */
1308 np->tx_ring[i].next_desc = np->tx_ring_dma +
1309 (i + 1)*sizeof(struct fealnx_desc);
1310 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1311 np->tx_ring[i].skbuff = NULL;
1312 }
1313
1314 /* for the last tx descriptor */
1315 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1316 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1317}
1318
1319
1320static int start_tx(struct sk_buff *skb, struct net_device *dev)
1321{
1322 struct netdev_private *np = netdev_priv(dev);
1323 unsigned long flags;
1324
1325 spin_lock_irqsave(&np->lock, flags);
1326
1327 np->cur_tx_copy->skbuff = skb;
1328
1329#define one_buffer
1330#define BPT 1022
1331#if defined(one_buffer)
1332 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1333 skb->len, PCI_DMA_TODEVICE);
1334 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1335 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1336 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1337// 89/12/29 add,
1338 if (np->pci_dev->device == 0x891)
1339 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1340 np->cur_tx_copy->status = TXOWN;
1341 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1342 --np->free_tx_count;
1343#elif defined(two_buffer)
1344 if (skb->len > BPT) {
1345 struct fealnx_desc *next;
1346
1347 /* for the first descriptor */
1348 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1349 BPT, PCI_DMA_TODEVICE);
1350 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1351 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1352 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1353
1354 /* for the last descriptor */
1355 next = np->cur_tx_copy->next_desc_logical;
1356 next->skbuff = skb;
1357 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1358 next->control |= (skb->len << PKTSShift); /* pkt size */
1359 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1360// 89/12/29 add,
1361 if (np->pci_dev->device == 0x891)
1362 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1363 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1364 skb->len - BPT, PCI_DMA_TODEVICE);
1365
1366 next->status = TXOWN;
1367 np->cur_tx_copy->status = TXOWN;
1368
1369 np->cur_tx_copy = next->next_desc_logical;
1370 np->free_tx_count -= 2;
1371 } else {
1372 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1373 skb->len, PCI_DMA_TODEVICE);
1374 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1375 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1376 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1377// 89/12/29 add,
1378 if (np->pci_dev->device == 0x891)
1379 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1380 np->cur_tx_copy->status = TXOWN;
1381 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1382 --np->free_tx_count;
1383 }
1384#endif
1385
1386 if (np->free_tx_count < 2)
1387 netif_stop_queue(dev);
1388 ++np->really_tx_count;
1389 iowrite32(0, np->mem + TXPDR);
1390 dev->trans_start = jiffies;
1391
1392 spin_unlock_irqrestore(&np->lock, flags);
1393 return 0;
1394}
1395
1396
1397/* Take lock before calling */
1398/* Chip probably hosed tx ring. Clean up. */
1399static void reset_tx_descriptors(struct net_device *dev)
1400{
1401 struct netdev_private *np = netdev_priv(dev);
1402 struct fealnx_desc *cur;
1403 int i;
1404
1405 /* initialize tx variables */
1406 np->cur_tx = &np->tx_ring[0];
1407 np->cur_tx_copy = &np->tx_ring[0];
1408 np->really_tx_count = 0;
1409 np->free_tx_count = TX_RING_SIZE;
1410
1411 for (i = 0; i < TX_RING_SIZE; i++) {
1412 cur = &np->tx_ring[i];
1413 if (cur->skbuff) {
1414 pci_unmap_single(np->pci_dev, cur->buffer,
1415 cur->skbuff->len, PCI_DMA_TODEVICE);
400de2c0 1416 dev_kfree_skb_any(cur->skbuff);
1da177e4
LT		 1417 cur->skbuff = NULL;
1418 }
1419 cur->status = 0;
1420 cur->control = 0; /* needed? */
1421 /* probably not needed. We do it for purely paranoid reasons */
1422 cur->next_desc = np->tx_ring_dma +
1423 (i + 1)*sizeof(struct fealnx_desc);
1424 cur->next_desc_logical = &np->tx_ring[i + 1];
1425 }
1426 /* for the last tx descriptor */
1427 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1428 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1429}
1430
1431
1432/* Take lock and stop rx before calling this */
1433static void reset_rx_descriptors(struct net_device *dev)
1434{
1435 struct netdev_private *np = netdev_priv(dev);
1436 struct fealnx_desc *cur = np->cur_rx;
1437 int i;
1438
1439 allocate_rx_buffers(dev);
1440
1441 for (i = 0; i < RX_RING_SIZE; i++) {
1442 if (cur->skbuff)
1443 cur->status = RXOWN;
1444 cur = cur->next_desc_logical;
1445 }
1446
1447 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1448 np->mem + RXLBA);
1449}
1450
1451
1452/* The interrupt handler does all of the Rx thread work and cleans up
1453 after the Tx thread. */
1454static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1455{
1456 struct net_device *dev = (struct net_device *) dev_instance;
1457 struct netdev_private *np = netdev_priv(dev);
1458 void __iomem *ioaddr = np->mem;
1459 long boguscnt = max_interrupt_work;
1460 unsigned int num_tx = 0;
1461 int handled = 0;
1462
1463 spin_lock(&np->lock);
1464
1465 iowrite32(0, ioaddr + IMR);
1466
1467 do {
1468 u32 intr_status = ioread32(ioaddr + ISR);
1469
1470 /* Acknowledge all of the current interrupt sources ASAP. */
1471 iowrite32(intr_status, ioaddr + ISR);
1472
1473 if (debug)
1474 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1475 intr_status);
1476
1477 if (!(intr_status & np->imrvalue))
1478 break;
1479
1480 handled = 1;
1481
1482// 90/1/16 delete,
1483//
1484// if (intr_status & FBE)
1485// { /* fatal error */
1486// stop_nic_tx(ioaddr, 0);
1487// stop_nic_rx(ioaddr, 0);
1488// break;
1489// };
1490
1491 if (intr_status & TUNF)
1492 iowrite32(0, ioaddr + TXPDR);
1493
1494 if (intr_status & CNTOVF) {
1495 /* missed pkts */
1496 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1497
1498 /* crc error */
1499 np->stats.rx_crc_errors +=
1500 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1501 }
1502
1503 if (intr_status & (RI | RBU)) {
1504 if (intr_status & RI)
1505 netdev_rx(dev);
1506 else {
1507 stop_nic_rx(ioaddr, np->crvalue);
1508 reset_rx_descriptors(dev);
1509 iowrite32(np->crvalue, ioaddr + TCRRCR);
1510 }
1511 }
1512
1513 while (np->really_tx_count) {
1514 long tx_status = np->cur_tx->status;
1515 long tx_control = np->cur_tx->control;
1516
1517 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1518 struct fealnx_desc *next;
1519
1520 next = np->cur_tx->next_desc_logical;
1521 tx_status = next->status;
1522 tx_control = next->control;
1523 }
1524
1525 if (tx_status & TXOWN)
1526 break;
1527
1528 if (!(np->crvalue & CR_W_ENH)) {
1529 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1530 np->stats.tx_errors++;
1531 if (tx_status & EC)
1532 np->stats.tx_aborted_errors++;
1533 if (tx_status & CSL)
1534 np->stats.tx_carrier_errors++;
1535 if (tx_status & LC)
1536 np->stats.tx_window_errors++;
1537 if (tx_status & UDF)
1538 np->stats.tx_fifo_errors++;
1539 if ((tx_status & HF) && np->mii.full_duplex == 0)
1540 np->stats.tx_heartbeat_errors++;
1541
1542 } else {
1543 np->stats.tx_bytes +=
1544 ((tx_control & PKTSMask) >> PKTSShift);
1545
1546 np->stats.collisions +=
1547 ((tx_status & NCRMask) >> NCRShift);
1548 np->stats.tx_packets++;
1549 }
1550 } else {
1551 np->stats.tx_bytes +=
1552 ((tx_control & PKTSMask) >> PKTSShift);
1553 np->stats.tx_packets++;
1554 }
1555
1556 /* Free the original skb. */
1557 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1558 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1559 dev_kfree_skb_irq(np->cur_tx->skbuff);
1560 np->cur_tx->skbuff = NULL;
1561 --np->really_tx_count;
1562 if (np->cur_tx->control & TXLD) {
1563 np->cur_tx = np->cur_tx->next_desc_logical;
1564 ++np->free_tx_count;
1565 } else {
1566 np->cur_tx = np->cur_tx->next_desc_logical;
1567 np->cur_tx = np->cur_tx->next_desc_logical;
1568 np->free_tx_count += 2;
1569 }
1570 num_tx++;
1571 } /* end of for loop */
1572
1573 if (num_tx && np->free_tx_count >= 2)
1574 netif_wake_queue(dev);
1575
1576 /* read transmit status for enhanced mode only */
1577 if (np->crvalue & CR_W_ENH) {
1578 long data;
1579
1580 data = ioread32(ioaddr + TSR);
1581 np->stats.tx_errors += (data & 0xff000000) >> 24;
1582 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1583 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1584 np->stats.collisions += (data & 0x0000ffff);
1585 }
1586
1587 if (--boguscnt < 0) {
1588 printk(KERN_WARNING "%s: Too much work at interrupt, "
1589 "status=0x%4.4x.\n", dev->name, intr_status);
1590 if (!np->reset_timer_armed) {
1591 np->reset_timer_armed = 1;
1592 np->reset_timer.expires = RUN_AT(HZ/2);
1593 add_timer(&np->reset_timer);
1594 stop_nic_rxtx(ioaddr, 0);
1595 netif_stop_queue(dev);
1596 /* or netif_tx_disable(dev); ?? */
1597 /* Prevent other paths from enabling tx,rx,intrs */
1598 np->crvalue_sv = np->crvalue;
1599 np->imrvalue_sv = np->imrvalue;
1600 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1601 np->imrvalue = 0;
1602 }
1603
1604 break;
1605 }
1606 } while (1);
1607
1608 /* read the tally counters */
1609 /* missed pkts */
1610 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1611
1612 /* crc error */
1613 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1614
1615 if (debug)
1616 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1617 dev->name, ioread32(ioaddr + ISR));
1618
1619 iowrite32(np->imrvalue, ioaddr + IMR);
1620
1621 spin_unlock(&np->lock);
1622
1623 return IRQ_RETVAL(handled);
1624}
1625
1626
1627/* This routine is logically part of the interrupt handler, but separated
1628 for clarity and better register allocation. */
1629static int netdev_rx(struct net_device *dev)
1630{
1631 struct netdev_private *np = netdev_priv(dev);
1632 void __iomem *ioaddr = np->mem;
1633
1634 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1635 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1636 s32 rx_status = np->cur_rx->status;
1637
1638 if (np->really_rx_count == 0)
1639 break;
1640
1641 if (debug)
1642 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1643
1644 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1645 || (rx_status & ErrorSummary)) {
1646 if (rx_status & ErrorSummary) { /* there was a fatal error */
1647 if (debug)
1648 printk(KERN_DEBUG
1649 "%s: Receive error, Rx status %8.8x.\n",
1650 dev->name, rx_status);
1651
1652 np->stats.rx_errors++; /* end of a packet. */
1653 if (rx_status & (LONG | RUNT))
1654 np->stats.rx_length_errors++;
1655 if (rx_status & RXER)
1656 np->stats.rx_frame_errors++;
1657 if (rx_status & CRC)
1658 np->stats.rx_crc_errors++;
1659 } else {
1660 int need_to_reset = 0;
1661 int desno = 0;
1662
1663 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1664 struct fealnx_desc *cur;
1665
1666 /* check this packet is received completely? */
1667 cur = np->cur_rx;
1668 while (desno <= np->really_rx_count) {
1669 ++desno;
1670 if ((!(cur->status & RXOWN))
1671 && (cur->status & RXLSD))
1672 break;
1673 /* goto next rx descriptor */
1674 cur = cur->next_desc_logical;
1675 }
1676 if (desno > np->really_rx_count)
1677 need_to_reset = 1;
1678 } else /* RXLSD did not find, something error */
1679 need_to_reset = 1;
1680
1681 if (need_to_reset == 0) {
1682 int i;
1683
1684 np->stats.rx_length_errors++;
1685
1686 /* free all rx descriptors related this long pkt */
1687 for (i = 0; i < desno; ++i) {
1688 if (!np->cur_rx->skbuff) {
1689 printk(KERN_DEBUG
1690 "%s: I'm scared\n", dev->name);
1691 break;
1692 }
1693 np->cur_rx->status = RXOWN;
1694 np->cur_rx = np->cur_rx->next_desc_logical;
1695 }
1696 continue;
1697 } else { /* rx error, need to reset this chip */
1698 stop_nic_rx(ioaddr, np->crvalue);
1699 reset_rx_descriptors(dev);
1700 iowrite32(np->crvalue, ioaddr + TCRRCR);
1701 }
1702 break; /* exit the while loop */
1703 }
1704 } else { /* this received pkt is ok */
1705
1706 struct sk_buff *skb;
1707 /* Omit the four octet CRC from the length. */
1708 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1709
1710#ifndef final_version
1711 if (debug)
1712 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1713 " status %x.\n", pkt_len, rx_status);
1714#endif
1715
1716 /* Check if the packet is long enough to accept without copying
1717 to a minimally-sized skbuff. */
1718 if (pkt_len < rx_copybreak &&
1719 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1720 skb->dev = dev;
1721 skb_reserve(skb, 2); /* 16 byte align the IP header */
1722 pci_dma_sync_single_for_cpu(np->pci_dev,
1723 np->cur_rx->buffer,
1724 np->rx_buf_sz,
1725 PCI_DMA_FROMDEVICE);
1726 /* Call copy + cksum if available. */
1727
1728#if ! defined(__alpha__)
1729 eth_copy_and_sum(skb,
689be439 1730 np->cur_rx->skbuff->data, pkt_len, 0);
1da177e4
LT		 1731 skb_put(skb, pkt_len);
1732#else
1733 memcpy(skb_put(skb, pkt_len),
689be439 1734 np->cur_rx->skbuff->data, pkt_len);
1da177e4
LT		 1735#endif
1736 pci_dma_sync_single_for_device(np->pci_dev,
1737 np->cur_rx->buffer,
1738 np->rx_buf_sz,
1739 PCI_DMA_FROMDEVICE);
1740 } else {
1741 pci_unmap_single(np->pci_dev,
1742 np->cur_rx->buffer,
1743 np->rx_buf_sz,
1744 PCI_DMA_FROMDEVICE);
1745 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1746 np->cur_rx->skbuff = NULL;
1747 --np->really_rx_count;
1748 }
1749 skb->protocol = eth_type_trans(skb, dev);
1750 netif_rx(skb);
1751 dev->last_rx = jiffies;
1752 np->stats.rx_packets++;
1753 np->stats.rx_bytes += pkt_len;
1754 }
1755
1756 np->cur_rx = np->cur_rx->next_desc_logical;
1757 } /* end of while loop */
1758
1759 /* allocate skb for rx buffers */
1760 allocate_rx_buffers(dev);
1761
1762 return 0;
1763}
1764
1765
1766static struct net_device_stats *get_stats(struct net_device *dev)
1767{
1768 struct netdev_private *np = netdev_priv(dev);
1769 void __iomem *ioaddr = np->mem;
1770
1771 /* The chip only need report frame silently dropped. */
1772 if (netif_running(dev)) {
1773 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1774 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1775 }
1776
1777 return &np->stats;
1778}
1779
1780
1781/* for dev->set_multicast_list */
1782static void set_rx_mode(struct net_device *dev)
1783{
1784 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1785 unsigned long flags;
1786 spin_lock_irqsave(lp, flags);
1787 __set_rx_mode(dev);
1788 spin_unlock_irqrestore(lp, flags);
1789}
1790
1791
1792/* Take lock before calling */
1793static void __set_rx_mode(struct net_device *dev)
1794{
1795 struct netdev_private *np = netdev_priv(dev);
1796 void __iomem *ioaddr = np->mem;
1797 u32 mc_filter[2]; /* Multicast hash filter */
1798 u32 rx_mode;
1799
1800 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1801 /* Unconditionally log net taps. */
1802 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1803 memset(mc_filter, 0xff, sizeof(mc_filter));
1804 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1805 } else if ((dev->mc_count > multicast_filter_limit)
1806 || (dev->flags & IFF_ALLMULTI)) {
1807 /* Too many to match, or accept all multicasts. */
1808 memset(mc_filter, 0xff, sizeof(mc_filter));
1809 rx_mode = CR_W_AB | CR_W_AM;
1810 } else {
1811 struct dev_mc_list *mclist;
1812 int i;
1813
1814 memset(mc_filter, 0, sizeof(mc_filter));
1815 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1816 i++, mclist = mclist->next) {
1817 unsigned int bit;
1818 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1819 mc_filter[bit >> 5] |= (1 << bit);
1820 }
1821 rx_mode = CR_W_AB | CR_W_AM;
1822 }
1823
1824 stop_nic_rxtx(ioaddr, np->crvalue);
1825
1826 iowrite32(mc_filter[0], ioaddr + MAR0);
1827 iowrite32(mc_filter[1], ioaddr + MAR1);
1828 np->crvalue &= ~CR_W_RXMODEMASK;
1829 np->crvalue |= rx_mode;
1830 iowrite32(np->crvalue, ioaddr + TCRRCR);
1831}
1832
1833static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1834{
1835 struct netdev_private *np = netdev_priv(dev);
1836
1837 strcpy(info->driver, DRV_NAME);
1838 strcpy(info->version, DRV_VERSION);
1839 strcpy(info->bus_info, pci_name(np->pci_dev));
1840}
1841
1842static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1843{
1844 struct netdev_private *np = netdev_priv(dev);
1845 int rc;
1846
1847 spin_lock_irq(&np->lock);
1848 rc = mii_ethtool_gset(&np->mii, cmd);
1849 spin_unlock_irq(&np->lock);
1850
1851 return rc;
1852}
1853
1854static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1855{
1856 struct netdev_private *np = netdev_priv(dev);
1857 int rc;
1858
1859 spin_lock_irq(&np->lock);
1860 rc = mii_ethtool_sset(&np->mii, cmd);
1861 spin_unlock_irq(&np->lock);
1862
1863 return rc;
1864}
1865
1866static int netdev_nway_reset(struct net_device *dev)
1867{
1868 struct netdev_private *np = netdev_priv(dev);
1869 return mii_nway_restart(&np->mii);
1870}
1871
1872static u32 netdev_get_link(struct net_device *dev)
1873{
1874 struct netdev_private *np = netdev_priv(dev);
1875 return mii_link_ok(&np->mii);
1876}
1877
1878static u32 netdev_get_msglevel(struct net_device *dev)
1879{
1880 return debug;
1881}
1882
1883static void netdev_set_msglevel(struct net_device *dev, u32 value)
1884{
1885 debug = value;
1886}
1887
1888static struct ethtool_ops netdev_ethtool_ops = {
1889 .get_drvinfo = netdev_get_drvinfo,
1890 .get_settings = netdev_get_settings,
1891 .set_settings = netdev_set_settings,
1892 .nway_reset = netdev_nway_reset,
1893 .get_link = netdev_get_link,
1894 .get_msglevel = netdev_get_msglevel,
1895 .set_msglevel = netdev_set_msglevel,
1896 .get_sg = ethtool_op_get_sg,
1897 .get_tx_csum = ethtool_op_get_tx_csum,
1898};
1899
1900static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1901{
1902 struct netdev_private *np = netdev_priv(dev);
1903 int rc;
1904
1905 if (!netif_running(dev))
1906 return -EINVAL;
1907
1908 spin_lock_irq(&np->lock);
1909 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1910 spin_unlock_irq(&np->lock);
1911
1912 return rc;
1913}
1914
1915
1916static int netdev_close(struct net_device *dev)
1917{
1918 struct netdev_private *np = netdev_priv(dev);
1919 void __iomem *ioaddr = np->mem;
1920 int i;
1921
1922 netif_stop_queue(dev);
1923
1924 /* Disable interrupts by clearing the interrupt mask. */
1925 iowrite32(0x0000, ioaddr + IMR);
1926
1927 /* Stop the chip's Tx and Rx processes. */
1928 stop_nic_rxtx(ioaddr, 0);
1929
1930 del_timer_sync(&np->timer);
1931 del_timer_sync(&np->reset_timer);
1932
1933 free_irq(dev->irq, dev);
1934
1935 /* Free all the skbuffs in the Rx queue. */
1936 for (i = 0; i < RX_RING_SIZE; i++) {
1937 struct sk_buff *skb = np->rx_ring[i].skbuff;
1938
1939 np->rx_ring[i].status = 0;
1940 if (skb) {
1941 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1942 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1943 dev_kfree_skb(skb);
1944 np->rx_ring[i].skbuff = NULL;
1945 }
1946 }
1947
1948 for (i = 0; i < TX_RING_SIZE; i++) {
1949 struct sk_buff *skb = np->tx_ring[i].skbuff;
1950
1951 if (skb) {
1952 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1953 skb->len, PCI_DMA_TODEVICE);
1954 dev_kfree_skb(skb);
1955 np->tx_ring[i].skbuff = NULL;
1956 }
1957 }
1958
1959 return 0;
1960}
1961
1962static struct pci_device_id fealnx_pci_tbl[] = {
1963 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1964 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1965 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1966 {} /* terminate list */
1967};
1968MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1969
1970
1971static struct pci_driver fealnx_driver = {
1972 .name = "fealnx",
1973 .id_table = fealnx_pci_tbl,
1974 .probe = fealnx_init_one,
1975 .remove = __devexit_p(fealnx_remove_one),
1976};
1977
1978static int __init fealnx_init(void)
1979{
1980/* when a module, this is printed whether or not devices are found in probe */
1981#ifdef MODULE
1982 printk(version);
1983#endif
1984
1985 return pci_module_init(&fealnx_driver);
1986}
1987
1988static void __exit fealnx_exit(void)
1989{
1990 pci_unregister_driver(&fealnx_driver);
1991}
1992
1993module_init(fealnx_init);
1994module_exit(fealnx_exit);
kernel source for telekom puls (alcatel/mediatek)