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Merge branch 'iommu/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / xilinx / ll_temac_main.c
CommitLineData
92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/init.h>
33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
9f1a1fca 41#include <linux/of_address.h>
92744989
GL		 42#include <linux/skbuff.h>
43#include <linux/spinlock.h>
44#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45#include <linux/udp.h> /* needed for sizeof(udphdr) */
46#include <linux/phy.h>
47#include <linux/in.h>
48#include <linux/io.h>
49#include <linux/ip.h>
5a0e3ad6 50#include <linux/slab.h>
ffbc03bc 51#include <linux/interrupt.h>
84cac398 52#include <linux/dma-mapping.h>
92744989
GL		 53
54#include "ll_temac.h"
55
56#define TX_BD_NUM 64
57#define RX_BD_NUM 128
58
59/* ---------------------------------------------------------------------
60 * Low level register access functions
61 */
62
63u32 temac_ior(struct temac_local *lp, int offset)
64{
65 return in_be32((u32 *)(lp->regs + offset));
66}
67
68void temac_iow(struct temac_local *lp, int offset, u32 value)
69{
70 out_be32((u32 *) (lp->regs + offset), value);
71}
72
73int temac_indirect_busywait(struct temac_local *lp)
74{
75 long end = jiffies + 2;
76
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
79 WARN_ON(1);
80 return -ETIMEDOUT;
81 }
82 msleep(1);
83 }
84 return 0;
85}
86
87/**
88 * temac_indirect_in32
89 *
90 * lp->indirect_mutex must be held when calling this function
91 */
92u32 temac_indirect_in32(struct temac_local *lp, int reg)
93{
94 u32 val;
95
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
100 return -ETIMEDOUT;
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
102
103 return val;
104}
105
106/**
107 * temac_indirect_out32
108 *
109 * lp->indirect_mutex must be held when calling this function
110 */
111void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112{
113 if (temac_indirect_busywait(lp))
114 return;
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
f79d7e6f 117 temac_indirect_busywait(lp);
92744989
GL		 118}
119
e44171f1
JL		 120/**
121 * temac_dma_in32 - Memory mapped DMA read, this function expects a
122 * register input that is based on DCR word addresses which
123 * are then converted to memory mapped byte addresses
124 */
92744989
GL		 125static u32 temac_dma_in32(struct temac_local *lp, int reg)
126{
e44171f1 127 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
92744989
GL		 128}
129
e44171f1
JL		 130/**
131 * temac_dma_out32 - Memory mapped DMA read, this function expects a
132 * register input that is based on DCR word addresses which
133 * are then converted to memory mapped byte addresses
134 */
92744989 135static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
e44171f1
JL		 136{
137 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
138}
139
140/* DMA register access functions can be DCR based or memory mapped.
141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
142 * memory mapped.
143 */
144#ifdef CONFIG_PPC_DCR
145
146/**
147 * temac_dma_dcr_in32 - DCR based DMA read
148 */
149static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
150{
151 return dcr_read(lp->sdma_dcrs, reg);
152}
153
154/**
155 * temac_dma_dcr_out32 - DCR based DMA write
156 */
157static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 158{
159 dcr_write(lp->sdma_dcrs, reg, value);
160}
161
e44171f1
JL		 162/**
163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
164 * I/O functions
165 */
2dc11581 166static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 167 struct device_node *np)
168{
169 unsigned int dcrs;
170
171 /* setup the dcr address mapping if it's in the device tree */
172
173 dcrs = dcr_resource_start(np, 0);
174 if (dcrs != 0) {
175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176 lp->dma_in = temac_dma_dcr_in;
177 lp->dma_out = temac_dma_dcr_out;
178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
179 return 0;
180 }
181 /* no DCR in the device tree, indicate a failure */
182 return -1;
183}
184
185#else
186
187/*
188 * temac_dcr_setup - This is a stub for when DCR is not supported,
189 * such as with MicroBlaze
190 */
2dc11581 191static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 192 struct device_node *np)
193{
194 return -1;
195}
196
197#endif
198
301e9d96
DK		 199/**
200 * * temac_dma_bd_release - Release buffer descriptor rings
201 */
202static void temac_dma_bd_release(struct net_device *ndev)
203{
204 struct temac_local *lp = netdev_priv(ndev);
205 int i;
206
50ec1538
RR		 207 /* Reset Local Link (DMA) */
208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
209
301e9d96
DK		 210 for (i = 0; i < RX_BD_NUM; i++) {
211 if (!lp->rx_skb[i])
212 break;
213 else {
214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216 dev_kfree_skb(lp->rx_skb[i]);
217 }
218 }
219 if (lp->rx_bd_v)
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 lp->rx_bd_v, lp->rx_bd_p);
223 if (lp->tx_bd_v)
224 dma_free_coherent(ndev->dev.parent,
225 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226 lp->tx_bd_v, lp->tx_bd_p);
227 if (lp->rx_skb)
228 kfree(lp->rx_skb);
229}
230
92744989
GL		 231/**
232 * temac_dma_bd_init - Setup buffer descriptor rings
233 */
234static int temac_dma_bd_init(struct net_device *ndev)
235{
236 struct temac_local *lp = netdev_priv(ndev);
237 struct sk_buff *skb;
238 int i;
239
5d66fe92 240 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
fe62c298
DK		 241 if (!lp->rx_skb) {
242 dev_err(&ndev->dev,
243 "can't allocate memory for DMA RX buffer\n");
244 goto out;
245 }
92744989 246 /* allocate the tx and rx ring buffer descriptors. */
b595076a 247 /* returns a virtual address and a physical address. */
92744989
GL		 248 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
249 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
250 &lp->tx_bd_p, GFP_KERNEL);
fe62c298
DK		 251 if (!lp->tx_bd_v) {
252 dev_err(&ndev->dev,
253 "unable to allocate DMA TX buffer descriptors");
254 goto out;
255 }
92744989
GL		 256 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
257 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
258 &lp->rx_bd_p, GFP_KERNEL);
fe62c298
DK		 259 if (!lp->rx_bd_v) {
260 dev_err(&ndev->dev,
261 "unable to allocate DMA RX buffer descriptors");
262 goto out;
263 }
92744989
GL		 264
265 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
266 for (i = 0; i < TX_BD_NUM; i++) {
267 lp->tx_bd_v[i].next = lp->tx_bd_p +
268 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
269 }
270
271 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
272 for (i = 0; i < RX_BD_NUM; i++) {
273 lp->rx_bd_v[i].next = lp->rx_bd_p +
274 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
275
e44171f1
JL		 276 skb = netdev_alloc_skb_ip_align(ndev,
277 XTE_MAX_JUMBO_FRAME_SIZE);
278
92744989
GL		 279 if (skb == 0) {
280 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
fe62c298 281 goto out;
92744989
GL		 282 }
283 lp->rx_skb[i] = skb;
92744989
GL		 284 /* returns physical address of skb->data */
285 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
286 skb->data,
287 XTE_MAX_JUMBO_FRAME_SIZE,
288 DMA_FROM_DEVICE);
289 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
290 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
291 }
292
e44171f1 293 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
92744989
GL		 294 CHNL_CTRL_IRQ_EN |
295 CHNL_CTRL_IRQ_DLY_EN |
296 CHNL_CTRL_IRQ_COAL_EN);
297 /* 0x10220483 */
298 /* 0x00100483 */
23ecc4bd 299 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
92744989
GL		 300 CHNL_CTRL_IRQ_EN |
301 CHNL_CTRL_IRQ_DLY_EN |
302 CHNL_CTRL_IRQ_COAL_EN |
303 CHNL_CTRL_IRQ_IOE);
304 /* 0xff010283 */
305
e44171f1
JL		 306 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
307 lp->dma_out(lp, RX_TAILDESC_PTR,
92744989 308 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
e44171f1 309 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
92744989
GL		 310
311 return 0;
fe62c298
DK		 312
313out:
301e9d96 314 temac_dma_bd_release(ndev);
fe62c298 315 return -ENOMEM;
92744989
GL		 316}
317
318/* ---------------------------------------------------------------------
319 * net_device_ops
320 */
321
322static int temac_set_mac_address(struct net_device *ndev, void *address)
323{
324 struct temac_local *lp = netdev_priv(ndev);
325
326 if (address)
327 memcpy(ndev->dev_addr, address, ETH_ALEN);
328
329 if (!is_valid_ether_addr(ndev->dev_addr))
330 random_ether_addr(ndev->dev_addr);
331
332 /* set up unicast MAC address filter set its mac address */
333 mutex_lock(&lp->indirect_mutex);
334 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
335 (ndev->dev_addr[0]) |
336 (ndev->dev_addr[1] << 8) |
337 (ndev->dev_addr[2] << 16) |
338 (ndev->dev_addr[3] << 24));
339 /* There are reserved bits in EUAW1
340 * so don't affect them Set MAC bits [47:32] in EUAW1 */
341 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
342 (ndev->dev_addr[4] & 0x000000ff) |
343 (ndev->dev_addr[5] << 8));
344 mutex_unlock(&lp->indirect_mutex);
345
346 return 0;
347}
348
8ea7a37c
SM		 349static int netdev_set_mac_address(struct net_device *ndev, void *p)
350{
351 struct sockaddr *addr = p;
352
353 return temac_set_mac_address(ndev, addr->sa_data);
354}
355
92744989
GL		 356static void temac_set_multicast_list(struct net_device *ndev)
357{
358 struct temac_local *lp = netdev_priv(ndev);
359 u32 multi_addr_msw, multi_addr_lsw, val;
360 int i;
361
362 mutex_lock(&lp->indirect_mutex);
8e95a202 363 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 364 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 365 /*
366 * We must make the kernel realise we had to move
367 * into promisc mode or we start all out war on
368 * the cable. If it was a promisc request the
369 * flag is already set. If not we assert it.
370 */
371 ndev->flags |= IFF_PROMISC;
372 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
373 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 374 } else if (!netdev_mc_empty(ndev)) {
22bedad3 375 struct netdev_hw_addr *ha;
92744989 376
f9dcbcc9 377 i = 0;
22bedad3 378 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 379 if (i >= MULTICAST_CAM_TABLE_NUM)
380 break;
22bedad3
JP		 381 multi_addr_msw = ((ha->addr[3] << 24) |
382 (ha->addr[2] << 16) |
383 (ha->addr[1] << 8) |
384 (ha->addr[0]));
92744989
GL		 385 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
386 multi_addr_msw);
22bedad3
JP		 387 multi_addr_lsw = ((ha->addr[5] << 8) |
388 (ha->addr[4]) | (i << 16));
92744989
GL		 389 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
390 multi_addr_lsw);
f9dcbcc9 391 i++;
92744989
GL		 392 }
393 } else {
394 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
395 temac_indirect_out32(lp, XTE_AFM_OFFSET,
396 val & ~XTE_AFM_EPPRM_MASK);
397 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
398 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
399 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
400 }
401 mutex_unlock(&lp->indirect_mutex);
402}
403
404struct temac_option {
405 int flg;
406 u32 opt;
407 u32 reg;
408 u32 m_or;
409 u32 m_and;
410} temac_options[] = {
411 /* Turn on jumbo packet support for both Rx and Tx */
412 {
413 .opt = XTE_OPTION_JUMBO,
414 .reg = XTE_TXC_OFFSET,
415 .m_or = XTE_TXC_TXJMBO_MASK,
416 },
417 {
418 .opt = XTE_OPTION_JUMBO,
419 .reg = XTE_RXC1_OFFSET,
420 .m_or =XTE_RXC1_RXJMBO_MASK,
421 },
422 /* Turn on VLAN packet support for both Rx and Tx */
423 {
424 .opt = XTE_OPTION_VLAN,
425 .reg = XTE_TXC_OFFSET,
426 .m_or =XTE_TXC_TXVLAN_MASK,
427 },
428 {
429 .opt = XTE_OPTION_VLAN,
430 .reg = XTE_RXC1_OFFSET,
431 .m_or =XTE_RXC1_RXVLAN_MASK,
432 },
433 /* Turn on FCS stripping on receive packets */
434 {
435 .opt = XTE_OPTION_FCS_STRIP,
436 .reg = XTE_RXC1_OFFSET,
437 .m_or =XTE_RXC1_RXFCS_MASK,
438 },
439 /* Turn on FCS insertion on transmit packets */
440 {
441 .opt = XTE_OPTION_FCS_INSERT,
442 .reg = XTE_TXC_OFFSET,
443 .m_or =XTE_TXC_TXFCS_MASK,
444 },
445 /* Turn on length/type field checking on receive packets */
446 {
447 .opt = XTE_OPTION_LENTYPE_ERR,
448 .reg = XTE_RXC1_OFFSET,
449 .m_or =XTE_RXC1_RXLT_MASK,
450 },
451 /* Turn on flow control */
452 {
453 .opt = XTE_OPTION_FLOW_CONTROL,
454 .reg = XTE_FCC_OFFSET,
455 .m_or =XTE_FCC_RXFLO_MASK,
456 },
457 /* Turn on flow control */
458 {
459 .opt = XTE_OPTION_FLOW_CONTROL,
460 .reg = XTE_FCC_OFFSET,
461 .m_or =XTE_FCC_TXFLO_MASK,
462 },
463 /* Turn on promiscuous frame filtering (all frames are received ) */
464 {
465 .opt = XTE_OPTION_PROMISC,
466 .reg = XTE_AFM_OFFSET,
467 .m_or =XTE_AFM_EPPRM_MASK,
468 },
469 /* Enable transmitter if not already enabled */
470 {
471 .opt = XTE_OPTION_TXEN,
472 .reg = XTE_TXC_OFFSET,
473 .m_or =XTE_TXC_TXEN_MASK,
474 },
475 /* Enable receiver? */
476 {
477 .opt = XTE_OPTION_RXEN,
478 .reg = XTE_RXC1_OFFSET,
479 .m_or =XTE_RXC1_RXEN_MASK,
480 },
481 {}
482};
483
484/**
485 * temac_setoptions
486 */
487static u32 temac_setoptions(struct net_device *ndev, u32 options)
488{
489 struct temac_local *lp = netdev_priv(ndev);
490 struct temac_option *tp = &temac_options[0];
491 int reg;
492
493 mutex_lock(&lp->indirect_mutex);
494 while (tp->opt) {
495 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
496 if (options & tp->opt)
497 reg |= tp->m_or;
498 temac_indirect_out32(lp, tp->reg, reg);
499 tp++;
500 }
501 lp->options |= options;
502 mutex_unlock(&lp->indirect_mutex);
503
807540ba 504 return 0;
92744989
GL		 505}
506
421f91d2 507/* Initialize temac */
92744989
GL		 508static void temac_device_reset(struct net_device *ndev)
509{
510 struct temac_local *lp = netdev_priv(ndev);
511 u32 timeout;
512 u32 val;
513
514 /* Perform a software reset */
515
516 /* 0x300 host enable bit ? */
517 /* reset PHY through control register ?:1 */
518
519 dev_dbg(&ndev->dev, "%s()\n", __func__);
520
521 mutex_lock(&lp->indirect_mutex);
522 /* Reset the receiver and wait for it to finish reset */
523 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
524 timeout = 1000;
525 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
526 udelay(1);
527 if (--timeout == 0) {
528 dev_err(&ndev->dev,
529 "temac_device_reset RX reset timeout!!\n");
530 break;
531 }
532 }
533
534 /* Reset the transmitter and wait for it to finish reset */
535 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
536 timeout = 1000;
537 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
538 udelay(1);
539 if (--timeout == 0) {
540 dev_err(&ndev->dev,
541 "temac_device_reset TX reset timeout!!\n");
542 break;
543 }
544 }
545
546 /* Disable the receiver */
547 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
548 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
549
550 /* Reset Local Link (DMA) */
e44171f1 551 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 552 timeout = 1000;
e44171f1 553 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 554 udelay(1);
555 if (--timeout == 0) {
556 dev_err(&ndev->dev,
557 "temac_device_reset DMA reset timeout!!\n");
558 break;
559 }
560 }
e44171f1 561 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 562
fe62c298
DK		 563 if (temac_dma_bd_init(ndev)) {
564 dev_err(&ndev->dev,
565 "temac_device_reset descriptor allocation failed\n");
566 }
92744989
GL		 567
568 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
569 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
571 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
572
573 mutex_unlock(&lp->indirect_mutex);
574
575 /* Sync default options with HW
576 * but leave receiver and transmitter disabled. */
577 temac_setoptions(ndev,
578 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
579
580 temac_set_mac_address(ndev, NULL);
581
582 /* Set address filter table */
583 temac_set_multicast_list(ndev);
584 if (temac_setoptions(ndev, lp->options))
585 dev_err(&ndev->dev, "Error setting TEMAC options\n");
586
587 /* Init Driver variable */
1ae5dc34 588 ndev->trans_start = jiffies; /* prevent tx timeout */
92744989
GL		 589}
590
591void temac_adjust_link(struct net_device *ndev)
592{
593 struct temac_local *lp = netdev_priv(ndev);
594 struct phy_device *phy = lp->phy_dev;
595 u32 mii_speed;
596 int link_state;
597
598 /* hash together the state values to decide if something has changed */
599 link_state = phy->speed | (phy->duplex << 1) | phy->link;
600
601 mutex_lock(&lp->indirect_mutex);
602 if (lp->last_link != link_state) {
603 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
604 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
605
606 switch (phy->speed) {
607 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
608 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
609 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
610 }
611
612 /* Write new speed setting out to TEMAC */
613 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
614 lp->last_link = link_state;
615 phy_print_status(phy);
616 }
617 mutex_unlock(&lp->indirect_mutex);
618}
619
620static void temac_start_xmit_done(struct net_device *ndev)
621{
622 struct temac_local *lp = netdev_priv(ndev);
623 struct cdmac_bd *cur_p;
624 unsigned int stat = 0;
625
626 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
627 stat = cur_p->app0;
628
629 while (stat & STS_CTRL_APP0_CMPLT) {
630 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
631 DMA_TO_DEVICE);
632 if (cur_p->app4)
633 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
634 cur_p->app0 = 0;
23ecc4bd
BH		 635 cur_p->app1 = 0;
636 cur_p->app2 = 0;
637 cur_p->app3 = 0;
638 cur_p->app4 = 0;
92744989
GL		 639
640 ndev->stats.tx_packets++;
641 ndev->stats.tx_bytes += cur_p->len;
642
643 lp->tx_bd_ci++;
644 if (lp->tx_bd_ci >= TX_BD_NUM)
645 lp->tx_bd_ci = 0;
646
647 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
648 stat = cur_p->app0;
649 }
650
651 netif_wake_queue(ndev);
652}
653
23ecc4bd
BH		 654static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
655{
656 struct cdmac_bd *cur_p;
657 int tail;
658
659 tail = lp->tx_bd_tail;
660 cur_p = &lp->tx_bd_v[tail];
661
662 do {
663 if (cur_p->app0)
664 return NETDEV_TX_BUSY;
665
666 tail++;
667 if (tail >= TX_BD_NUM)
668 tail = 0;
669
670 cur_p = &lp->tx_bd_v[tail];
671 num_frag--;
672 } while (num_frag >= 0);
673
674 return 0;
675}
676
92744989
GL		 677static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
678{
679 struct temac_local *lp = netdev_priv(ndev);
680 struct cdmac_bd *cur_p;
681 dma_addr_t start_p, tail_p;
682 int ii;
683 unsigned long num_frag;
684 skb_frag_t *frag;
685
686 num_frag = skb_shinfo(skb)->nr_frags;
687 frag = &skb_shinfo(skb)->frags[0];
688 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
689 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
690
23ecc4bd 691 if (temac_check_tx_bd_space(lp, num_frag)) {
92744989
GL		 692 if (!netif_queue_stopped(ndev)) {
693 netif_stop_queue(ndev);
694 return NETDEV_TX_BUSY;
695 }
696 return NETDEV_TX_BUSY;
697 }
698
699 cur_p->app0 = 0;
700 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 701 unsigned int csum_start_off = skb_checksum_start_offset(skb);
23ecc4bd
BH		 702 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
703
704 cur_p->app0 |= 1; /* TX Checksum Enabled */
705 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
706 cur_p->app2 = 0; /* initial checksum seed */
92744989 707 }
23ecc4bd 708
92744989
GL		 709 cur_p->app0 |= STS_CTRL_APP0_SOP;
710 cur_p->len = skb_headlen(skb);
711 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
712 DMA_TO_DEVICE);
713 cur_p->app4 = (unsigned long)skb;
714
715 for (ii = 0; ii < num_frag; ii++) {
716 lp->tx_bd_tail++;
717 if (lp->tx_bd_tail >= TX_BD_NUM)
718 lp->tx_bd_tail = 0;
719
720 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
721 cur_p->phys = dma_map_single(ndev->dev.parent,
3ed6f695 722 skb_frag_address(frag),
2edcd4ca
SR		 723 skb_frag_size(frag), DMA_TO_DEVICE);
724 cur_p->len = skb_frag_size(frag);
92744989
GL		 725 cur_p->app0 = 0;
726 frag++;
727 }
728 cur_p->app0 |= STS_CTRL_APP0_EOP;
729
730 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
731 lp->tx_bd_tail++;
732 if (lp->tx_bd_tail >= TX_BD_NUM)
733 lp->tx_bd_tail = 0;
734
93e0ed15
RC		 735 skb_tx_timestamp(skb);
736
92744989 737 /* Kick off the transfer */
e44171f1 738 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 739
6ed10654 740 return NETDEV_TX_OK;
92744989
GL		 741}
742
743
744static void ll_temac_recv(struct net_device *ndev)
745{
746 struct temac_local *lp = netdev_priv(ndev);
747 struct sk_buff *skb, *new_skb;
748 unsigned int bdstat;
749 struct cdmac_bd *cur_p;
750 dma_addr_t tail_p;
751 int length;
92744989
GL		 752 unsigned long flags;
753
754 spin_lock_irqsave(&lp->rx_lock, flags);
755
756 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
757 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
758
759 bdstat = cur_p->app0;
760 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
761
762 skb = lp->rx_skb[lp->rx_bd_ci];
c3b7c12c 763 length = cur_p->app4 & 0x3FFF;
92744989 764
33646d7f 765 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
92744989
GL		 766 DMA_FROM_DEVICE);
767
768 skb_put(skb, length);
769 skb->dev = ndev;
770 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 771 skb_checksum_none_assert(skb);
92744989 772
23ecc4bd
BH		 773 /* if we're doing rx csum offload, set it up */
774 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
775 (skb->protocol == __constant_htons(ETH_P_IP)) &&
776 (skb->len > 64)) {
777
778 skb->csum = cur_p->app3 & 0xFFFF;
779 skb->ip_summed = CHECKSUM_COMPLETE;
780 }
781
93e0ed15
RC		 782 if (!skb_defer_rx_timestamp(skb))
783 netif_rx(skb);
92744989
GL		 784
785 ndev->stats.rx_packets++;
786 ndev->stats.rx_bytes += length;
787
e44171f1
JL		 788 new_skb = netdev_alloc_skb_ip_align(ndev,
789 XTE_MAX_JUMBO_FRAME_SIZE);
790
92744989
GL		 791 if (new_skb == 0) {
792 dev_err(&ndev->dev, "no memory for new sk_buff\n");
793 spin_unlock_irqrestore(&lp->rx_lock, flags);
794 return;
795 }
796
92744989
GL		 797 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
798 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
799 XTE_MAX_JUMBO_FRAME_SIZE,
800 DMA_FROM_DEVICE);
801 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
802 lp->rx_skb[lp->rx_bd_ci] = new_skb;
803
804 lp->rx_bd_ci++;
805 if (lp->rx_bd_ci >= RX_BD_NUM)
806 lp->rx_bd_ci = 0;
807
808 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
809 bdstat = cur_p->app0;
810 }
e44171f1 811 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 812
813 spin_unlock_irqrestore(&lp->rx_lock, flags);
814}
815
816static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
817{
818 struct net_device *ndev = _ndev;
819 struct temac_local *lp = netdev_priv(ndev);
820 unsigned int status;
821
e44171f1
JL		 822 status = lp->dma_in(lp, TX_IRQ_REG);
823 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 824
825 if (status & (IRQ_COAL | IRQ_DLY))
826 temac_start_xmit_done(lp->ndev);
827 if (status & 0x080)
828 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
829
830 return IRQ_HANDLED;
831}
832
833static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
834{
835 struct net_device *ndev = _ndev;
836 struct temac_local *lp = netdev_priv(ndev);
837 unsigned int status;
838
839 /* Read and clear the status registers */
e44171f1
JL		 840 status = lp->dma_in(lp, RX_IRQ_REG);
841 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 842
843 if (status & (IRQ_COAL | IRQ_DLY))
844 ll_temac_recv(lp->ndev);
845
846 return IRQ_HANDLED;
847}
848
849static int temac_open(struct net_device *ndev)
850{
851 struct temac_local *lp = netdev_priv(ndev);
852 int rc;
853
854 dev_dbg(&ndev->dev, "temac_open()\n");
855
856 if (lp->phy_node) {
857 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
858 temac_adjust_link, 0, 0);
859 if (!lp->phy_dev) {
860 dev_err(lp->dev, "of_phy_connect() failed\n");
861 return -ENODEV;
862 }
863
864 phy_start(lp->phy_dev);
865 }
866
50ec1538
RR		 867 temac_device_reset(ndev);
868
92744989
GL		 869 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
870 if (rc)
871 goto err_tx_irq;
872 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
873 if (rc)
874 goto err_rx_irq;
875
92744989
GL		 876 return 0;
877
878 err_rx_irq:
879 free_irq(lp->tx_irq, ndev);
880 err_tx_irq:
881 if (lp->phy_dev)
882 phy_disconnect(lp->phy_dev);
883 lp->phy_dev = NULL;
884 dev_err(lp->dev, "request_irq() failed\n");
885 return rc;
886}
887
888static int temac_stop(struct net_device *ndev)
889{
890 struct temac_local *lp = netdev_priv(ndev);
891
892 dev_dbg(&ndev->dev, "temac_close()\n");
893
894 free_irq(lp->tx_irq, ndev);
895 free_irq(lp->rx_irq, ndev);
896
897 if (lp->phy_dev)
898 phy_disconnect(lp->phy_dev);
899 lp->phy_dev = NULL;
900
301e9d96
DK		 901 temac_dma_bd_release(ndev);
902
92744989
GL		 903 return 0;
904}
905
906#ifdef CONFIG_NET_POLL_CONTROLLER
907static void
908temac_poll_controller(struct net_device *ndev)
909{
910 struct temac_local *lp = netdev_priv(ndev);
911
912 disable_irq(lp->tx_irq);
913 disable_irq(lp->rx_irq);
914
8539992f
MS		 915 ll_temac_rx_irq(lp->tx_irq, ndev);
916 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 917
918 enable_irq(lp->tx_irq);
919 enable_irq(lp->rx_irq);
920}
921#endif
922
923static const struct net_device_ops temac_netdev_ops = {
924 .ndo_open = temac_open,
925 .ndo_stop = temac_stop,
926 .ndo_start_xmit = temac_start_xmit,
8ea7a37c 927 .ndo_set_mac_address = netdev_set_mac_address,
60eb5fd1 928 .ndo_validate_addr = eth_validate_addr,
92744989
GL		 929#ifdef CONFIG_NET_POLL_CONTROLLER
930 .ndo_poll_controller = temac_poll_controller,
931#endif
932};
933
934/* ---------------------------------------------------------------------
935 * SYSFS device attributes
936 */
937static ssize_t temac_show_llink_regs(struct device *dev,
938 struct device_attribute *attr, char *buf)
939{
940 struct net_device *ndev = dev_get_drvdata(dev);
941 struct temac_local *lp = netdev_priv(ndev);
942 int i, len = 0;
943
944 for (i = 0; i < 0x11; i++)
e44171f1 945 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 946 (i % 8) == 7 ? "\n" : " ");
947 len += sprintf(buf + len, "\n");
948
949 return len;
950}
951
952static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
953
954static struct attribute *temac_device_attrs[] = {
955 &dev_attr_llink_regs.attr,
956 NULL,
957};
958
959static const struct attribute_group temac_attr_group = {
960 .attrs = temac_device_attrs,
961};
962
9eac2d4d
R		 963/* ethtool support */
964static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
965{
966 struct temac_local *lp = netdev_priv(ndev);
967 return phy_ethtool_gset(lp->phy_dev, cmd);
968}
969
970static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
971{
972 struct temac_local *lp = netdev_priv(ndev);
973 return phy_ethtool_sset(lp->phy_dev, cmd);
974}
975
976static int temac_nway_reset(struct net_device *ndev)
977{
978 struct temac_local *lp = netdev_priv(ndev);
979 return phy_start_aneg(lp->phy_dev);
980}
981
982static const struct ethtool_ops temac_ethtool_ops = {
983 .get_settings = temac_get_settings,
984 .set_settings = temac_set_settings,
985 .nway_reset = temac_nway_reset,
986 .get_link = ethtool_op_get_link,
987};
988
74888760 989static int __devinit temac_of_probe(struct platform_device *op)
92744989
GL		 990{
991 struct device_node *np;
992 struct temac_local *lp;
993 struct net_device *ndev;
994 const void *addr;
23ecc4bd 995 __be32 *p;
92744989 996 int size, rc = 0;
92744989
GL		 997
998 /* Init network device structure */
999 ndev = alloc_etherdev(sizeof(*lp));
1000 if (!ndev) {
1001 dev_err(&op->dev, "could not allocate device.\n");
1002 return -ENOMEM;
1003 }
1004 ether_setup(ndev);
1005 dev_set_drvdata(&op->dev, ndev);
1006 SET_NETDEV_DEV(ndev, &op->dev);
1007 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1008 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
1009 ndev->netdev_ops = &temac_netdev_ops;
9eac2d4d 1010 ndev->ethtool_ops = &temac_ethtool_ops;
92744989
GL		 1011#if 0
1012 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1013 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1014 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1015 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1016 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
1017 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
1018 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
1019 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1020 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1021 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1022 ndev->features |= NETIF_F_LRO; /* large receive offload */
1023#endif
1024
1025 /* setup temac private info structure */
1026 lp = netdev_priv(ndev);
1027 lp->ndev = ndev;
1028 lp->dev = &op->dev;
1029 lp->options = XTE_OPTION_DEFAULTS;
1030 spin_lock_init(&lp->rx_lock);
1031 mutex_init(&lp->indirect_mutex);
1032
1033 /* map device registers */
61c7a080 1034 lp->regs = of_iomap(op->dev.of_node, 0);
92744989
GL		 1035 if (!lp->regs) {
1036 dev_err(&op->dev, "could not map temac regs.\n");
1037 goto nodev;
1038 }
1039
23ecc4bd
BH		 1040 /* Setup checksum offload, but default to off if not specified */
1041 lp->temac_features = 0;
1042 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1043 if (p && be32_to_cpu(*p)) {
1044 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1045 /* Can checksum TCP/UDP over IPv4. */
1046 ndev->features |= NETIF_F_IP_CSUM;
1047 }
1048 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1049 if (p && be32_to_cpu(*p))
1050 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1051
92744989 1052 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
61c7a080 1053 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
92744989
GL		 1054 if (!np) {
1055 dev_err(&op->dev, "could not find DMA node\n");
dfe1e8ed 1056 goto err_iounmap;
92744989
GL		 1057 }
1058
e44171f1
JL		 1059 /* Setup the DMA register accesses, could be DCR or memory mapped */
1060 if (temac_dcr_setup(lp, op, np)) {
1061
1062 /* no DCR in the device tree, try non-DCR */
1063 lp->sdma_regs = of_iomap(np, 0);
1064 if (lp->sdma_regs) {
1065 lp->dma_in = temac_dma_in32;
1066 lp->dma_out = temac_dma_out32;
1067 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1068 } else {
1069 dev_err(&op->dev, "unable to map DMA registers\n");
7cc36f6f 1070 of_node_put(np);
dfe1e8ed 1071 goto err_iounmap;
e44171f1 1072 }
92744989 1073 }
92744989
GL		 1074
1075 lp->rx_irq = irq_of_parse_and_map(np, 0);
1076 lp->tx_irq = irq_of_parse_and_map(np, 1);
7cc36f6f
KV		 1077
1078 of_node_put(np); /* Finished with the DMA node; drop the reference */
1079
755fae0a 1080 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
92744989
GL		 1081 dev_err(&op->dev, "could not determine irqs\n");
1082 rc = -ENOMEM;
dfe1e8ed 1083 goto err_iounmap_2;
92744989
GL		 1084 }
1085
92744989
GL		 1086
1087 /* Retrieve the MAC address */
61c7a080 1088 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
92744989
GL		 1089 if ((!addr) || (size != 6)) {
1090 dev_err(&op->dev, "could not find MAC address\n");
1091 rc = -ENODEV;
dfe1e8ed 1092 goto err_iounmap_2;
92744989
GL		 1093 }
1094 temac_set_mac_address(ndev, (void *)addr);
1095
61c7a080 1096 rc = temac_mdio_setup(lp, op->dev.of_node);
92744989
GL		 1097 if (rc)
1098 dev_warn(&op->dev, "error registering MDIO bus\n");
1099
61c7a080 1100 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
92744989
GL		 1101 if (lp->phy_node)
1102 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1103
1104 /* Add the device attributes */
1105 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1106 if (rc) {
1107 dev_err(lp->dev, "Error creating sysfs files\n");
dfe1e8ed 1108 goto err_iounmap_2;
92744989
GL		 1109 }
1110
1111 rc = register_netdev(lp->ndev);
1112 if (rc) {
1113 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1114 goto err_register_ndev;
1115 }
1116
1117 return 0;
1118
1119 err_register_ndev:
1120 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
dfe1e8ed
DK		 1121 err_iounmap_2:
1122 if (lp->sdma_regs)
1123 iounmap(lp->sdma_regs);
1124 err_iounmap:
1125 iounmap(lp->regs);
92744989
GL		 1126 nodev:
1127 free_netdev(ndev);
1128 ndev = NULL;
1129 return rc;
1130}
1131
2dc11581 1132static int __devexit temac_of_remove(struct platform_device *op)
92744989
GL		 1133{
1134 struct net_device *ndev = dev_get_drvdata(&op->dev);
1135 struct temac_local *lp = netdev_priv(ndev);
1136
1137 temac_mdio_teardown(lp);
1138 unregister_netdev(ndev);
1139 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1140 if (lp->phy_node)
1141 of_node_put(lp->phy_node);
1142 lp->phy_node = NULL;
1143 dev_set_drvdata(&op->dev, NULL);
dfe1e8ed
DK		 1144 iounmap(lp->regs);
1145 if (lp->sdma_regs)
1146 iounmap(lp->sdma_regs);
92744989
GL		 1147 free_netdev(ndev);
1148 return 0;
1149}
1150
1151static struct of_device_id temac_of_match[] __devinitdata = {
1152 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1153 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1154 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1155 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1156 {},
1157};
1158MODULE_DEVICE_TABLE(of, temac_of_match);
1159
74888760 1160static struct platform_driver temac_of_driver = {
92744989
GL		 1161 .probe = temac_of_probe,
1162 .remove = __devexit_p(temac_of_remove),
1163 .driver = {
1164 .owner = THIS_MODULE,
1165 .name = "xilinx_temac",
4018294b 1166 .of_match_table = temac_of_match,
92744989
GL		 1167 },
1168};
1169
1170static int __init temac_init(void)
1171{
74888760 1172 return platform_driver_register(&temac_of_driver);
92744989
GL		 1173}
1174module_init(temac_init);
1175
1176static void __exit temac_exit(void)
1177{
74888760 1178 platform_driver_unregister(&temac_of_driver);
92744989
GL		 1179}
1180module_exit(temac_exit);
1181
1182MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1183MODULE_AUTHOR("Yoshio Kashiwagi");
1184MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)