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ethtool: Update ethtool_rxnfc::rule_cnt on return from ETHTOOL_GRXCLSRLALL
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / sun / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
a6b7a407 10#include <linux/interrupt.h>
a3138df9
DM		 11#include <linux/pci.h>
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/ethtool.h>
15#include <linux/etherdevice.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/bitops.h>
19#include <linux/mii.h>
01789349 20#include <linux/if.h>
a3138df9
DM		 21#include <linux/if_ether.h>
22#include <linux/if_vlan.h>
23#include <linux/ip.h>
24#include <linux/in.h>
25#include <linux/ipv6.h>
26#include <linux/log2.h>
27#include <linux/jiffies.h>
28#include <linux/crc32.h>
ccffad25 29#include <linux/list.h>
5a0e3ad6 30#include <linux/slab.h>
a3138df9
DM		 31
32#include <linux/io.h>
a3138df9 33#include <linux/of_device.h>
a3138df9
DM		 34
35#include "niu.h"
36
37#define DRV_MODULE_NAME "niu"
3cfa856d
DM		 38#define DRV_MODULE_VERSION "1.1"
39#define DRV_MODULE_RELDATE "Apr 22, 2010"
a3138df9
DM		 40
41static char version[] __devinitdata =
42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
43
44MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
45MODULE_DESCRIPTION("NIU ethernet driver");
46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
a3138df9
DM		 49#ifndef readq
50static u64 readq(void __iomem *reg)
51{
e23a59e1 52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 53}
54
55static void writeq(u64 val, void __iomem *reg)
56{
57 writel(val & 0xffffffff, reg);
58 writel(val >> 32, reg + 0x4UL);
59}
60#endif
61
a3aa1884 62static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
64 {}
65};
66
67MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
68
69#define NIU_TX_TIMEOUT (5 * HZ)
70
71#define nr64(reg) readq(np->regs + (reg))
72#define nw64(reg, val) writeq((val), np->regs + (reg))
73
74#define nr64_mac(reg) readq(np->mac_regs + (reg))
75#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
76
77#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
78#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
79
80#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
81#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
82
83#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
84#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
85
86#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
87
88static int niu_debug;
89static int debug = -1;
90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "NIU debug level");
92
a3138df9
DM		 93#define niu_lock_parent(np, flags) \
94 spin_lock_irqsave(&np->parent->lock, flags)
95#define niu_unlock_parent(np, flags) \
96 spin_unlock_irqrestore(&np->parent->lock, flags)
97
5fbd7e24
MW		 98static int serdes_init_10g_serdes(struct niu *np);
99
a3138df9
DM		 100static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
101 u64 bits, int limit, int delay)
102{
103 while (--limit >= 0) {
104 u64 val = nr64_mac(reg);
105
106 if (!(val & bits))
107 break;
108 udelay(delay);
109 }
110 if (limit < 0)
111 return -ENODEV;
112 return 0;
113}
114
115static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
116 u64 bits, int limit, int delay,
117 const char *reg_name)
118{
119 int err;
120
121 nw64_mac(reg, bits);
122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
123 if (err)
f10a1f2e
JP		 124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
125 (unsigned long long)bits, reg_name,
126 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 127 return err;
128}
129
130#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
131({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
133})
134
135static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
136 u64 bits, int limit, int delay)
137{
138 while (--limit >= 0) {
139 u64 val = nr64_ipp(reg);
140
141 if (!(val & bits))
142 break;
143 udelay(delay);
144 }
145 if (limit < 0)
146 return -ENODEV;
147 return 0;
148}
149
150static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
151 u64 bits, int limit, int delay,
152 const char *reg_name)
153{
154 int err;
155 u64 val;
156
157 val = nr64_ipp(reg);
158 val |= bits;
159 nw64_ipp(reg, val);
160
161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
162 if (err)
f10a1f2e
JP		 163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
164 (unsigned long long)bits, reg_name,
165 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 166 return err;
167}
168
169#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
170({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
172})
173
174static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
175 u64 bits, int limit, int delay)
176{
177 while (--limit >= 0) {
178 u64 val = nr64(reg);
179
180 if (!(val & bits))
181 break;
182 udelay(delay);
183 }
184 if (limit < 0)
185 return -ENODEV;
186 return 0;
187}
188
189#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
190({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
192})
193
194static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay,
196 const char *reg_name)
197{
198 int err;
199
200 nw64(reg, bits);
201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
202 if (err)
f10a1f2e
JP		 203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
204 (unsigned long long)bits, reg_name,
205 (unsigned long long)nr64(reg));
a3138df9
DM		 206 return err;
207}
208
209#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
210({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
212})
213
214static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
215{
216 u64 val = (u64) lp->timer;
217
218 if (on)
219 val |= LDG_IMGMT_ARM;
220
221 nw64(LDG_IMGMT(lp->ldg_num), val);
222}
223
224static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
225{
226 unsigned long mask_reg, bits;
227 u64 val;
228
229 if (ldn < 0 || ldn > LDN_MAX)
230 return -EINVAL;
231
232 if (ldn < 64) {
233 mask_reg = LD_IM0(ldn);
234 bits = LD_IM0_MASK;
235 } else {
236 mask_reg = LD_IM1(ldn - 64);
237 bits = LD_IM1_MASK;
238 }
239
240 val = nr64(mask_reg);
241 if (on)
242 val &= ~bits;
243 else
244 val |= bits;
245 nw64(mask_reg, val);
246
247 return 0;
248}
249
250static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
251{
252 struct niu_parent *parent = np->parent;
253 int i;
254
255 for (i = 0; i <= LDN_MAX; i++) {
256 int err;
257
258 if (parent->ldg_map[i] != lp->ldg_num)
259 continue;
260
261 err = niu_ldn_irq_enable(np, i, on);
262 if (err)
263 return err;
264 }
265 return 0;
266}
267
268static int niu_enable_interrupts(struct niu *np, int on)
269{
270 int i;
271
272 for (i = 0; i < np->num_ldg; i++) {
273 struct niu_ldg *lp = &np->ldg[i];
274 int err;
275
276 err = niu_enable_ldn_in_ldg(np, lp, on);
277 if (err)
278 return err;
279 }
280 for (i = 0; i < np->num_ldg; i++)
281 niu_ldg_rearm(np, &np->ldg[i], on);
282
283 return 0;
284}
285
286static u32 phy_encode(u32 type, int port)
287{
807540ba 288 return type << (port * 2);
a3138df9
DM		 289}
290
291static u32 phy_decode(u32 val, int port)
292{
293 return (val >> (port * 2)) & PORT_TYPE_MASK;
294}
295
296static int mdio_wait(struct niu *np)
297{
298 int limit = 1000;
299 u64 val;
300
301 while (--limit > 0) {
302 val = nr64(MIF_FRAME_OUTPUT);
303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
304 return val & MIF_FRAME_OUTPUT_DATA;
305
306 udelay(10);
307 }
308
309 return -ENODEV;
310}
311
312static int mdio_read(struct niu *np, int port, int dev, int reg)
313{
314 int err;
315
316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
317 err = mdio_wait(np);
318 if (err < 0)
319 return err;
320
321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
322 return mdio_wait(np);
323}
324
325static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
326{
327 int err;
328
329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
330 err = mdio_wait(np);
331 if (err < 0)
332 return err;
333
334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
335 err = mdio_wait(np);
336 if (err < 0)
337 return err;
338
339 return 0;
340}
341
342static int mii_read(struct niu *np, int port, int reg)
343{
344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
345 return mdio_wait(np);
346}
347
348static int mii_write(struct niu *np, int port, int reg, int data)
349{
350 int err;
351
352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
353 err = mdio_wait(np);
354 if (err < 0)
355 return err;
356
357 return 0;
358}
359
360static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
361{
362 int err;
363
364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
365 ESR2_TI_PLL_TX_CFG_L(channel),
366 val & 0xffff);
367 if (!err)
368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
369 ESR2_TI_PLL_TX_CFG_H(channel),
370 val >> 16);
371 return err;
372}
373
374static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
375{
376 int err;
377
378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
379 ESR2_TI_PLL_RX_CFG_L(channel),
380 val & 0xffff);
381 if (!err)
382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
383 ESR2_TI_PLL_RX_CFG_H(channel),
384 val >> 16);
385 return err;
386}
387
388/* Mode is always 10G fiber. */
e3e081e1 389static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 390{
391 struct niu_link_config *lp = &np->link_config;
392 u32 tx_cfg, rx_cfg;
393 unsigned long i;
394
395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
398 PLL_RX_CFG_EQ_LP_ADAPTIVE);
399
400 if (lp->loopback_mode == LOOPBACK_PHY) {
401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
402
403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
405
406 tx_cfg |= PLL_TX_CFG_ENTEST;
407 rx_cfg |= PLL_RX_CFG_ENTEST;
408 }
409
410 /* Initialize all 4 lanes of the SERDES. */
411 for (i = 0; i < 4; i++) {
412 int err = esr2_set_tx_cfg(np, i, tx_cfg);
413 if (err)
414 return err;
415 }
416
417 for (i = 0; i < 4; i++) {
418 int err = esr2_set_rx_cfg(np, i, rx_cfg);
419 if (err)
420 return err;
421 }
422
423 return 0;
424}
425
e3e081e1
SB		 426static int serdes_init_niu_1g_serdes(struct niu *np)
427{
428 struct niu_link_config *lp = &np->link_config;
429 u16 pll_cfg, pll_sts;
430 int max_retry = 100;
51e0f058 431 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 432 u32 tx_cfg, rx_cfg;
433 unsigned long i;
434 int err;
435
436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
437 PLL_TX_CFG_RATE_HALF);
438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
440 PLL_RX_CFG_RATE_HALF);
441
442 if (np->port == 0)
443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
444
445 if (lp->loopback_mode == LOOPBACK_PHY) {
446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
447
448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
449 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
450
451 tx_cfg |= PLL_TX_CFG_ENTEST;
452 rx_cfg |= PLL_RX_CFG_ENTEST;
453 }
454
455 /* Initialize PLL for 1G */
456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
457
458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
459 ESR2_TI_PLL_CFG_L, pll_cfg);
460 if (err) {
f10a1f2e
JP		 461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
462 np->port, __func__);
e3e081e1
SB		 463 return err;
464 }
465
466 pll_sts = PLL_CFG_ENPLL;
467
468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_STS_L, pll_sts);
470 if (err) {
f10a1f2e
JP		 471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
472 np->port, __func__);
e3e081e1
SB		 473 return err;
474 }
475
476 udelay(200);
477
478 /* Initialize all 4 lanes of the SERDES. */
479 for (i = 0; i < 4; i++) {
480 err = esr2_set_tx_cfg(np, i, tx_cfg);
481 if (err)
482 return err;
483 }
484
485 for (i = 0; i < 4; i++) {
486 err = esr2_set_rx_cfg(np, i, rx_cfg);
487 if (err)
488 return err;
489 }
490
491 switch (np->port) {
492 case 0:
493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
494 mask = val;
495 break;
496
497 case 1:
498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
499 mask = val;
500 break;
501
502 default:
503 return -EINVAL;
504 }
505
506 while (max_retry--) {
507 sig = nr64(ESR_INT_SIGNALS);
508 if ((sig & mask) == val)
509 break;
510
511 mdelay(500);
512 }
513
514 if ((sig & mask) != val) {
f10a1f2e
JP		 515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
516 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 517 return -ENODEV;
518 }
519
520 return 0;
521}
522
523static int serdes_init_niu_10g_serdes(struct niu *np)
524{
525 struct niu_link_config *lp = &np->link_config;
526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
527 int max_retry = 100;
51e0f058 528 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 529 unsigned long i;
530 int err;
531
532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
535 PLL_RX_CFG_EQ_LP_ADAPTIVE);
536
537 if (lp->loopback_mode == LOOPBACK_PHY) {
538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
539
540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
541 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
542
543 tx_cfg |= PLL_TX_CFG_ENTEST;
544 rx_cfg |= PLL_RX_CFG_ENTEST;
545 }
546
547 /* Initialize PLL for 10G */
548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
549
550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
552 if (err) {
f10a1f2e
JP		 553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
554 np->port, __func__);
e3e081e1
SB		 555 return err;
556 }
557
558 pll_sts = PLL_CFG_ENPLL;
559
560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
562 if (err) {
f10a1f2e
JP		 563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
564 np->port, __func__);
e3e081e1
SB		 565 return err;
566 }
567
568 udelay(200);
569
570 /* Initialize all 4 lanes of the SERDES. */
571 for (i = 0; i < 4; i++) {
572 err = esr2_set_tx_cfg(np, i, tx_cfg);
573 if (err)
574 return err;
575 }
576
577 for (i = 0; i < 4; i++) {
578 err = esr2_set_rx_cfg(np, i, rx_cfg);
579 if (err)
580 return err;
581 }
582
583 /* check if serdes is ready */
584
585 switch (np->port) {
586 case 0:
587 mask = ESR_INT_SIGNALS_P0_BITS;
588 val = (ESR_INT_SRDY0_P0 |
589 ESR_INT_DET0_P0 |
590 ESR_INT_XSRDY_P0 |
591 ESR_INT_XDP_P0_CH3 |
592 ESR_INT_XDP_P0_CH2 |
593 ESR_INT_XDP_P0_CH1 |
594 ESR_INT_XDP_P0_CH0);
595 break;
596
597 case 1:
598 mask = ESR_INT_SIGNALS_P1_BITS;
599 val = (ESR_INT_SRDY0_P1 |
600 ESR_INT_DET0_P1 |
601 ESR_INT_XSRDY_P1 |
602 ESR_INT_XDP_P1_CH3 |
603 ESR_INT_XDP_P1_CH2 |
604 ESR_INT_XDP_P1_CH1 |
605 ESR_INT_XDP_P1_CH0);
606 break;
607
608 default:
609 return -EINVAL;
610 }
611
612 while (max_retry--) {
613 sig = nr64(ESR_INT_SIGNALS);
614 if ((sig & mask) == val)
615 break;
616
617 mdelay(500);
618 }
619
620 if ((sig & mask) != val) {
f10a1f2e
JP		 621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
622 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 623
624 /* 10G failed, try initializing at 1G */
625 err = serdes_init_niu_1g_serdes(np);
626 if (!err) {
627 np->flags &= ~NIU_FLAGS_10G;
628 np->mac_xcvr = MAC_XCVR_PCS;
629 } else {
f10a1f2e
JP		 630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
631 np->port);
e3e081e1
SB		 632 return -ENODEV;
633 }
634 }
635 return 0;
636}
637
a3138df9
DM		 638static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
639{
640 int err;
641
642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
643 if (err >= 0) {
644 *val = (err & 0xffff);
645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
646 ESR_RXTX_CTRL_H(chan));
647 if (err >= 0)
648 *val |= ((err & 0xffff) << 16);
649 err = 0;
650 }
651 return err;
652}
653
654static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
655{
656 int err;
657
658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
659 ESR_GLUE_CTRL0_L(chan));
660 if (err >= 0) {
661 *val = (err & 0xffff);
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
663 ESR_GLUE_CTRL0_H(chan));
664 if (err >= 0) {
665 *val |= ((err & 0xffff) << 16);
666 err = 0;
667 }
668 }
669 return err;
670}
671
672static int esr_read_reset(struct niu *np, u32 *val)
673{
674 int err;
675
676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
677 ESR_RXTX_RESET_CTRL_L);
678 if (err >= 0) {
679 *val = (err & 0xffff);
680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
681 ESR_RXTX_RESET_CTRL_H);
682 if (err >= 0) {
683 *val |= ((err & 0xffff) << 16);
684 err = 0;
685 }
686 }
687 return err;
688}
689
690static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
691{
692 int err;
693
694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
695 ESR_RXTX_CTRL_L(chan), val & 0xffff);
696 if (!err)
697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
698 ESR_RXTX_CTRL_H(chan), (val >> 16));
699 return err;
700}
701
702static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
703{
704 int err;
705
706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
707 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
708 if (!err)
709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
710 ESR_GLUE_CTRL0_H(chan), (val >> 16));
711 return err;
712}
713
714static int esr_reset(struct niu *np)
715{
f166400b 716 u32 uninitialized_var(reset);
a3138df9
DM		 717 int err;
718
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_RESET_CTRL_L, 0x0000);
721 if (err)
722 return err;
723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 ESR_RXTX_RESET_CTRL_H, 0xffff);
725 if (err)
726 return err;
727 udelay(200);
728
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
730 ESR_RXTX_RESET_CTRL_L, 0xffff);
731 if (err)
732 return err;
733 udelay(200);
734
735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 ESR_RXTX_RESET_CTRL_H, 0x0000);
737 if (err)
738 return err;
739 udelay(200);
740
741 err = esr_read_reset(np, &reset);
742 if (err)
743 return err;
744 if (reset != 0) {
f10a1f2e
JP		 745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
746 np->port, reset);
a3138df9
DM		 747 return -ENODEV;
748 }
749
750 return 0;
751}
752
753static int serdes_init_10g(struct niu *np)
754{
755 struct niu_link_config *lp = &np->link_config;
756 unsigned long ctrl_reg, test_cfg_reg, i;
757 u64 ctrl_val, test_cfg_val, sig, mask, val;
758 int err;
759
760 switch (np->port) {
761 case 0:
762 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
763 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
764 break;
765 case 1:
766 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
767 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
768 break;
769
770 default:
771 return -EINVAL;
772 }
773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
774 ENET_SERDES_CTRL_SDET_1 |
775 ENET_SERDES_CTRL_SDET_2 |
776 ENET_SERDES_CTRL_SDET_3 |
777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
785 test_cfg_val = 0;
786
787 if (lp->loopback_mode == LOOPBACK_PHY) {
788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_0_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_1_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_2_SHIFT) |
794 (ENET_TEST_MD_PAD_LOOPBACK <<
795 ENET_SERDES_TEST_MD_3_SHIFT));
796 }
797
798 nw64(ctrl_reg, ctrl_val);
799 nw64(test_cfg_reg, test_cfg_val);
800
801 /* Initialize all 4 lanes of the SERDES. */
802 for (i = 0; i < 4; i++) {
803 u32 rxtx_ctrl, glue0;
804
805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
806 if (err)
807 return err;
808 err = esr_read_glue0(np, i, &glue0);
809 if (err)
810 return err;
811
812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
815
816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
817 ESR_GLUE_CTRL0_THCNT |
818 ESR_GLUE_CTRL0_BLTIME);
819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
822 (BLTIME_300_CYCLES <<
823 ESR_GLUE_CTRL0_BLTIME_SHIFT));
824
825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
826 if (err)
827 return err;
828 err = esr_write_glue0(np, i, glue0);
829 if (err)
830 return err;
831 }
832
833 err = esr_reset(np);
834 if (err)
835 return err;
836
837 sig = nr64(ESR_INT_SIGNALS);
838 switch (np->port) {
839 case 0:
840 mask = ESR_INT_SIGNALS_P0_BITS;
841 val = (ESR_INT_SRDY0_P0 |
842 ESR_INT_DET0_P0 |
843 ESR_INT_XSRDY_P0 |
844 ESR_INT_XDP_P0_CH3 |
845 ESR_INT_XDP_P0_CH2 |
846 ESR_INT_XDP_P0_CH1 |
847 ESR_INT_XDP_P0_CH0);
848 break;
849
850 case 1:
851 mask = ESR_INT_SIGNALS_P1_BITS;
852 val = (ESR_INT_SRDY0_P1 |
853 ESR_INT_DET0_P1 |
854 ESR_INT_XSRDY_P1 |
855 ESR_INT_XDP_P1_CH3 |
856 ESR_INT_XDP_P1_CH2 |
857 ESR_INT_XDP_P1_CH1 |
858 ESR_INT_XDP_P1_CH0);
859 break;
860
861 default:
862 return -EINVAL;
863 }
864
865 if ((sig & mask) != val) {
a5d6ab56
MW		 866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
868 return 0;
869 }
f10a1f2e
JP		 870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
871 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 872 return -ENODEV;
873 }
a5d6ab56
MW		 874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 876 return 0;
877}
878
879static int serdes_init_1g(struct niu *np)
880{
881 u64 val;
882
883 val = nr64(ENET_SERDES_1_PLL_CFG);
884 val &= ~ENET_SERDES_PLL_FBDIV2;
885 switch (np->port) {
886 case 0:
887 val |= ENET_SERDES_PLL_HRATE0;
888 break;
889 case 1:
890 val |= ENET_SERDES_PLL_HRATE1;
891 break;
892 case 2:
893 val |= ENET_SERDES_PLL_HRATE2;
894 break;
895 case 3:
896 val |= ENET_SERDES_PLL_HRATE3;
897 break;
898 default:
899 return -EINVAL;
900 }
901 nw64(ENET_SERDES_1_PLL_CFG, val);
902
903 return 0;
904}
905
5fbd7e24
MW		 906static int serdes_init_1g_serdes(struct niu *np)
907{
908 struct niu_link_config *lp = &np->link_config;
909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
910 u64 ctrl_val, test_cfg_val, sig, mask, val;
911 int err;
912 u64 reset_val, val_rd;
913
914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
916 ENET_SERDES_PLL_FBDIV0;
917 switch (np->port) {
918 case 0:
919 reset_val = ENET_SERDES_RESET_0;
920 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
921 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
922 pll_cfg = ENET_SERDES_0_PLL_CFG;
923 break;
924 case 1:
925 reset_val = ENET_SERDES_RESET_1;
926 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
927 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
928 pll_cfg = ENET_SERDES_1_PLL_CFG;
929 break;
930
931 default:
932 return -EINVAL;
933 }
934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
935 ENET_SERDES_CTRL_SDET_1 |
936 ENET_SERDES_CTRL_SDET_2 |
937 ENET_SERDES_CTRL_SDET_3 |
938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
946 test_cfg_val = 0;
947
948 if (lp->loopback_mode == LOOPBACK_PHY) {
949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_0_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_1_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_2_SHIFT) |
955 (ENET_TEST_MD_PAD_LOOPBACK <<
956 ENET_SERDES_TEST_MD_3_SHIFT));
957 }
958
959 nw64(ENET_SERDES_RESET, reset_val);
960 mdelay(20);
961 val_rd = nr64(ENET_SERDES_RESET);
962 val_rd &= ~reset_val;
963 nw64(pll_cfg, val);
964 nw64(ctrl_reg, ctrl_val);
965 nw64(test_cfg_reg, test_cfg_val);
966 nw64(ENET_SERDES_RESET, val_rd);
967 mdelay(2000);
968
969 /* Initialize all 4 lanes of the SERDES. */
970 for (i = 0; i < 4; i++) {
971 u32 rxtx_ctrl, glue0;
972
973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
974 if (err)
975 return err;
976 err = esr_read_glue0(np, i, &glue0);
977 if (err)
978 return err;
979
980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
983
984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
985 ESR_GLUE_CTRL0_THCNT |
986 ESR_GLUE_CTRL0_BLTIME);
987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
990 (BLTIME_300_CYCLES <<
991 ESR_GLUE_CTRL0_BLTIME_SHIFT));
992
993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
994 if (err)
995 return err;
996 err = esr_write_glue0(np, i, glue0);
997 if (err)
998 return err;
999 }
1000
1001
1002 sig = nr64(ESR_INT_SIGNALS);
1003 switch (np->port) {
1004 case 0:
1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1006 mask = val;
1007 break;
1008
1009 case 1:
1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1011 mask = val;
1012 break;
1013
1014 default:
1015 return -EINVAL;
1016 }
1017
1018 if ((sig & mask) != val) {
f10a1f2e
JP		 1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1021 return -ENODEV;
1022 }
1023
1024 return 0;
1025}
1026
1027static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028{
1029 struct niu_link_config *lp = &np->link_config;
1030 int link_up;
1031 u64 val;
1032 u16 current_speed;
1033 unsigned long flags;
1034 u8 current_duplex;
1035
1036 link_up = 0;
1037 current_speed = SPEED_INVALID;
1038 current_duplex = DUPLEX_INVALID;
1039
1040 spin_lock_irqsave(&np->lock, flags);
1041
1042 val = nr64_pcs(PCS_MII_STAT);
1043
1044 if (val & PCS_MII_STAT_LINK_STATUS) {
1045 link_up = 1;
1046 current_speed = SPEED_1000;
1047 current_duplex = DUPLEX_FULL;
1048 }
1049
1050 lp->active_speed = current_speed;
1051 lp->active_duplex = current_duplex;
1052 spin_unlock_irqrestore(&np->lock, flags);
1053
1054 *link_up_p = link_up;
1055 return 0;
1056}
1057
5fbd7e24
MW		 1058static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059{
1060 unsigned long flags;
1061 struct niu_link_config *lp = &np->link_config;
1062 int link_up = 0;
1063 int link_ok = 1;
1064 u64 val, val2;
1065 u16 current_speed;
1066 u8 current_duplex;
1067
1068 if (!(np->flags & NIU_FLAGS_10G))
1069 return link_status_1g_serdes(np, link_up_p);
1070
1071 current_speed = SPEED_INVALID;
1072 current_duplex = DUPLEX_INVALID;
1073 spin_lock_irqsave(&np->lock, flags);
1074
1075 val = nr64_xpcs(XPCS_STATUS(0));
1076 val2 = nr64_mac(XMAC_INTER2);
1077 if (val2 & 0x01000000)
1078 link_ok = 0;
1079
1080 if ((val & 0x1000ULL) && link_ok) {
1081 link_up = 1;
1082 current_speed = SPEED_10000;
1083 current_duplex = DUPLEX_FULL;
1084 }
1085 lp->active_speed = current_speed;
1086 lp->active_duplex = current_duplex;
1087 spin_unlock_irqrestore(&np->lock, flags);
1088 *link_up_p = link_up;
1089 return 0;
1090}
1091
38bb045d
CB		 1092static int link_status_mii(struct niu *np, int *link_up_p)
1093{
1094 struct niu_link_config *lp = &np->link_config;
1095 int err;
1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097 int supported, advertising, active_speed, active_duplex;
1098
1099 err = mii_read(np, np->phy_addr, MII_BMCR);
1100 if (unlikely(err < 0))
1101 return err;
1102 bmcr = err;
1103
1104 err = mii_read(np, np->phy_addr, MII_BMSR);
1105 if (unlikely(err < 0))
1106 return err;
1107 bmsr = err;
1108
1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110 if (unlikely(err < 0))
1111 return err;
1112 advert = err;
1113
1114 err = mii_read(np, np->phy_addr, MII_LPA);
1115 if (unlikely(err < 0))
1116 return err;
1117 lpa = err;
1118
1119 if (likely(bmsr & BMSR_ESTATEN)) {
1120 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121 if (unlikely(err < 0))
1122 return err;
1123 estatus = err;
1124
1125 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126 if (unlikely(err < 0))
1127 return err;
1128 ctrl1000 = err;
1129
1130 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131 if (unlikely(err < 0))
1132 return err;
1133 stat1000 = err;
1134 } else
1135 estatus = ctrl1000 = stat1000 = 0;
1136
1137 supported = 0;
1138 if (bmsr & BMSR_ANEGCAPABLE)
1139 supported |= SUPPORTED_Autoneg;
1140 if (bmsr & BMSR_10HALF)
1141 supported |= SUPPORTED_10baseT_Half;
1142 if (bmsr & BMSR_10FULL)
1143 supported |= SUPPORTED_10baseT_Full;
1144 if (bmsr & BMSR_100HALF)
1145 supported |= SUPPORTED_100baseT_Half;
1146 if (bmsr & BMSR_100FULL)
1147 supported |= SUPPORTED_100baseT_Full;
1148 if (estatus & ESTATUS_1000_THALF)
1149 supported |= SUPPORTED_1000baseT_Half;
1150 if (estatus & ESTATUS_1000_TFULL)
1151 supported |= SUPPORTED_1000baseT_Full;
1152 lp->supported = supported;
1153
1154 advertising = 0;
1155 if (advert & ADVERTISE_10HALF)
1156 advertising |= ADVERTISED_10baseT_Half;
1157 if (advert & ADVERTISE_10FULL)
1158 advertising |= ADVERTISED_10baseT_Full;
1159 if (advert & ADVERTISE_100HALF)
1160 advertising |= ADVERTISED_100baseT_Half;
1161 if (advert & ADVERTISE_100FULL)
1162 advertising |= ADVERTISED_100baseT_Full;
1163 if (ctrl1000 & ADVERTISE_1000HALF)
1164 advertising |= ADVERTISED_1000baseT_Half;
1165 if (ctrl1000 & ADVERTISE_1000FULL)
1166 advertising |= ADVERTISED_1000baseT_Full;
1167
1168 if (bmcr & BMCR_ANENABLE) {
1169 int neg, neg1000;
1170
1171 lp->active_autoneg = 1;
1172 advertising |= ADVERTISED_Autoneg;
1173
1174 neg = advert & lpa;
1175 neg1000 = (ctrl1000 << 2) & stat1000;
1176
1177 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1178 active_speed = SPEED_1000;
1179 else if (neg & LPA_100)
1180 active_speed = SPEED_100;
1181 else if (neg & (LPA_10HALF | LPA_10FULL))
1182 active_speed = SPEED_10;
1183 else
1184 active_speed = SPEED_INVALID;
1185
1186 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1187 active_duplex = DUPLEX_FULL;
1188 else if (active_speed != SPEED_INVALID)
1189 active_duplex = DUPLEX_HALF;
1190 else
1191 active_duplex = DUPLEX_INVALID;
1192 } else {
1193 lp->active_autoneg = 0;
1194
1195 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1196 active_speed = SPEED_1000;
1197 else if (bmcr & BMCR_SPEED100)
1198 active_speed = SPEED_100;
1199 else
1200 active_speed = SPEED_10;
1201
1202 if (bmcr & BMCR_FULLDPLX)
1203 active_duplex = DUPLEX_FULL;
1204 else
1205 active_duplex = DUPLEX_HALF;
1206 }
1207
1208 lp->active_advertising = advertising;
1209 lp->active_speed = active_speed;
1210 lp->active_duplex = active_duplex;
1211 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1212
1213 return 0;
1214}
1215
5fbd7e24
MW		 1216static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1217{
1218 struct niu_link_config *lp = &np->link_config;
1219 u16 current_speed, bmsr;
1220 unsigned long flags;
1221 u8 current_duplex;
1222 int err, link_up;
1223
1224 link_up = 0;
1225 current_speed = SPEED_INVALID;
1226 current_duplex = DUPLEX_INVALID;
1227
1228 spin_lock_irqsave(&np->lock, flags);
1229
1230 err = -EINVAL;
1231
1232 err = mii_read(np, np->phy_addr, MII_BMSR);
1233 if (err < 0)
1234 goto out;
1235
1236 bmsr = err;
1237 if (bmsr & BMSR_LSTATUS) {
f344c25d 1238 u16 adv, lpa;
5fbd7e24
MW		 1239
1240 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1241 if (err < 0)
1242 goto out;
1243 adv = err;
1244
1245 err = mii_read(np, np->phy_addr, MII_LPA);
1246 if (err < 0)
1247 goto out;
1248 lpa = err;
1249
5fbd7e24
MW		 1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251 if (err < 0)
1252 goto out;
5fbd7e24
MW		 1253 link_up = 1;
1254 current_speed = SPEED_1000;
1255 current_duplex = DUPLEX_FULL;
1256
1257 }
1258 lp->active_speed = current_speed;
1259 lp->active_duplex = current_duplex;
1260 err = 0;
1261
1262out:
1263 spin_unlock_irqrestore(&np->lock, flags);
1264
1265 *link_up_p = link_up;
1266 return err;
1267}
1268
38bb045d
CB		 1269static int link_status_1g(struct niu *np, int *link_up_p)
1270{
1271 struct niu_link_config *lp = &np->link_config;
1272 unsigned long flags;
1273 int err;
1274
1275 spin_lock_irqsave(&np->lock, flags);
1276
1277 err = link_status_mii(np, link_up_p);
1278 lp->supported |= SUPPORTED_TP;
1279 lp->active_advertising |= ADVERTISED_TP;
1280
1281 spin_unlock_irqrestore(&np->lock, flags);
1282 return err;
1283}
1284
a3138df9
DM		 1285static int bcm8704_reset(struct niu *np)
1286{
1287 int err, limit;
1288
1289 err = mdio_read(np, np->phy_addr,
1290 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1291 if (err < 0 || err == 0xffff)
a3138df9
DM		 1292 return err;
1293 err |= BMCR_RESET;
1294 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1295 MII_BMCR, err);
1296 if (err)
1297 return err;
1298
1299 limit = 1000;
1300 while (--limit >= 0) {
1301 err = mdio_read(np, np->phy_addr,
1302 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1303 if (err < 0)
1304 return err;
1305 if (!(err & BMCR_RESET))
1306 break;
1307 }
1308 if (limit < 0) {
f10a1f2e
JP		 1309 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1310 np->port, (err & 0xffff));
a3138df9
DM		 1311 return -ENODEV;
1312 }
1313 return 0;
1314}
1315
1316/* When written, certain PHY registers need to be read back twice
1317 * in order for the bits to settle properly.
1318 */
1319static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1320{
1321 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1322 if (err < 0)
1323 return err;
1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1325 if (err < 0)
1326 return err;
1327 return 0;
1328}
1329
a5d6ab56
MW		 1330static int bcm8706_init_user_dev3(struct niu *np)
1331{
1332 int err;
1333
1334
1335 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1336 BCM8704_USER_OPT_DIGITAL_CTRL);
1337 if (err < 0)
1338 return err;
1339 err &= ~USER_ODIG_CTRL_GPIOS;
1340 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1341 err |= USER_ODIG_CTRL_RESV2;
1342 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1343 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1344 if (err)
1345 return err;
1346
1347 mdelay(1000);
1348
1349 return 0;
1350}
1351
a3138df9
DM		 1352static int bcm8704_init_user_dev3(struct niu *np)
1353{
1354 int err;
1355
1356 err = mdio_write(np, np->phy_addr,
1357 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1358 (USER_CONTROL_OPTXRST_LVL |
1359 USER_CONTROL_OPBIASFLT_LVL |
1360 USER_CONTROL_OBTMPFLT_LVL |
1361 USER_CONTROL_OPPRFLT_LVL |
1362 USER_CONTROL_OPTXFLT_LVL |
1363 USER_CONTROL_OPRXLOS_LVL |
1364 USER_CONTROL_OPRXFLT_LVL |
1365 USER_CONTROL_OPTXON_LVL |
1366 (0x3f << USER_CONTROL_RES1_SHIFT)));
1367 if (err)
1368 return err;
1369
1370 err = mdio_write(np, np->phy_addr,
1371 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1372 (USER_PMD_TX_CTL_XFP_CLKEN |
1373 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1374 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1375 USER_PMD_TX_CTL_TSCK_LPWREN));
1376 if (err)
1377 return err;
1378
1379 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1380 if (err)
1381 return err;
1382 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1383 if (err)
1384 return err;
1385
1386 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1387 BCM8704_USER_OPT_DIGITAL_CTRL);
1388 if (err < 0)
1389 return err;
1390 err &= ~USER_ODIG_CTRL_GPIOS;
1391 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1392 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1393 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1394 if (err)
1395 return err;
1396
1397 mdelay(1000);
1398
1399 return 0;
1400}
1401
b0de8e40
ML		 1402static int mrvl88x2011_act_led(struct niu *np, int val)
1403{
1404 int err;
1405
1406 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1407 MRVL88X2011_LED_8_TO_11_CTL);
1408 if (err < 0)
1409 return err;
1410
1411 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1412 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1413
1414 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1415 MRVL88X2011_LED_8_TO_11_CTL, err);
1416}
1417
1418static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1419{
1420 int err;
1421
1422 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1423 MRVL88X2011_LED_BLINK_CTL);
1424 if (err >= 0) {
1425 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1426 err |= (rate << 4);
1427
1428 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1429 MRVL88X2011_LED_BLINK_CTL, err);
1430 }
1431
1432 return err;
1433}
1434
1435static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1436{
1437 int err;
1438
1439 /* Set LED functions */
1440 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1441 if (err)
1442 return err;
1443
1444 /* led activity */
1445 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1446 if (err)
1447 return err;
1448
1449 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1450 MRVL88X2011_GENERAL_CTL);
1451 if (err < 0)
1452 return err;
1453
1454 err |= MRVL88X2011_ENA_XFPREFCLK;
1455
1456 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1457 MRVL88X2011_GENERAL_CTL, err);
1458 if (err < 0)
1459 return err;
1460
1461 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1462 MRVL88X2011_PMA_PMD_CTL_1);
1463 if (err < 0)
1464 return err;
1465
1466 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1467 err |= MRVL88X2011_LOOPBACK;
1468 else
1469 err &= ~MRVL88X2011_LOOPBACK;
1470
1471 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1472 MRVL88X2011_PMA_PMD_CTL_1, err);
1473 if (err < 0)
1474 return err;
1475
1476 /* Enable PMD */
1477 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1478 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1479}
1480
a5d6ab56
MW		 1481
1482static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1483{
a3138df9 1484 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1485 int err = 0;
a3138df9
DM		 1486
1487#if 1
1488 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1489 MII_STAT1000);
1490 if (err < 0)
1491 return err;
f10a1f2e 1492 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1493
1494 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1495 if (err < 0)
1496 return err;
f10a1f2e 1497 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1498
1499 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1500 MII_NWAYTEST);
1501 if (err < 0)
1502 return err;
f10a1f2e 1503 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1504#endif
1505
1506 /* XXX dig this out it might not be so useful XXX */
1507 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1508 BCM8704_USER_ANALOG_STATUS0);
1509 if (err < 0)
1510 return err;
1511 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1512 BCM8704_USER_ANALOG_STATUS0);
1513 if (err < 0)
1514 return err;
1515 analog_stat0 = err;
1516
1517 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1518 BCM8704_USER_TX_ALARM_STATUS);
1519 if (err < 0)
1520 return err;
1521 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1522 BCM8704_USER_TX_ALARM_STATUS);
1523 if (err < 0)
1524 return err;
1525 tx_alarm_status = err;
1526
1527 if (analog_stat0 != 0x03fc) {
1528 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1529 pr_info("Port %u cable not connected or bad cable\n",
1530 np->port);
a3138df9 1531 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1532 pr_info("Port %u optical module is bad or missing\n",
1533 np->port);
a3138df9
DM		 1534 }
1535 }
1536
1537 return 0;
1538}
1539
a5d6ab56
MW		 1540static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1541{
1542 struct niu_link_config *lp = &np->link_config;
1543 int err;
1544
1545 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1546 MII_BMCR);
1547 if (err < 0)
1548 return err;
1549
1550 err &= ~BMCR_LOOPBACK;
1551
1552 if (lp->loopback_mode == LOOPBACK_MAC)
1553 err |= BMCR_LOOPBACK;
1554
1555 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1556 MII_BMCR, err);
1557 if (err)
1558 return err;
1559
1560 return 0;
1561}
1562
1563static int xcvr_init_10g_bcm8706(struct niu *np)
1564{
1565 int err = 0;
1566 u64 val;
1567
1568 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1569 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1570 return err;
1571
1572 val = nr64_mac(XMAC_CONFIG);
1573 val &= ~XMAC_CONFIG_LED_POLARITY;
1574 val |= XMAC_CONFIG_FORCE_LED_ON;
1575 nw64_mac(XMAC_CONFIG, val);
1576
1577 val = nr64(MIF_CONFIG);
1578 val |= MIF_CONFIG_INDIRECT_MODE;
1579 nw64(MIF_CONFIG, val);
1580
1581 err = bcm8704_reset(np);
1582 if (err)
1583 return err;
1584
1585 err = xcvr_10g_set_lb_bcm870x(np);
1586 if (err)
1587 return err;
1588
1589 err = bcm8706_init_user_dev3(np);
1590 if (err)
1591 return err;
1592
1593 err = xcvr_diag_bcm870x(np);
1594 if (err)
1595 return err;
1596
1597 return 0;
1598}
1599
1600static int xcvr_init_10g_bcm8704(struct niu *np)
1601{
1602 int err;
1603
1604 err = bcm8704_reset(np);
1605 if (err)
1606 return err;
1607
1608 err = bcm8704_init_user_dev3(np);
1609 if (err)
1610 return err;
1611
1612 err = xcvr_10g_set_lb_bcm870x(np);
1613 if (err)
1614 return err;
1615
1616 err = xcvr_diag_bcm870x(np);
1617 if (err)
1618 return err;
1619
1620 return 0;
1621}
1622
b0de8e40
ML		 1623static int xcvr_init_10g(struct niu *np)
1624{
1625 int phy_id, err;
1626 u64 val;
1627
1628 val = nr64_mac(XMAC_CONFIG);
1629 val &= ~XMAC_CONFIG_LED_POLARITY;
1630 val |= XMAC_CONFIG_FORCE_LED_ON;
1631 nw64_mac(XMAC_CONFIG, val);
1632
1633 /* XXX shared resource, lock parent XXX */
1634 val = nr64(MIF_CONFIG);
1635 val |= MIF_CONFIG_INDIRECT_MODE;
1636 nw64(MIF_CONFIG, val);
1637
1638 phy_id = phy_decode(np->parent->port_phy, np->port);
1639 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1640
1641 /* handle different phy types */
1642 switch (phy_id & NIU_PHY_ID_MASK) {
1643 case NIU_PHY_ID_MRVL88X2011:
1644 err = xcvr_init_10g_mrvl88x2011(np);
1645 break;
1646
1647 default: /* bcom 8704 */
1648 err = xcvr_init_10g_bcm8704(np);
1649 break;
1650 }
1651
f344c25d 1652 return err;
b0de8e40
ML		 1653}
1654
a3138df9
DM		 1655static int mii_reset(struct niu *np)
1656{
1657 int limit, err;
1658
1659 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1660 if (err)
1661 return err;
1662
1663 limit = 1000;
1664 while (--limit >= 0) {
1665 udelay(500);
1666 err = mii_read(np, np->phy_addr, MII_BMCR);
1667 if (err < 0)
1668 return err;
1669 if (!(err & BMCR_RESET))
1670 break;
1671 }
1672 if (limit < 0) {
f10a1f2e
JP		 1673 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1674 np->port, err);
a3138df9
DM		 1675 return -ENODEV;
1676 }
1677
1678 return 0;
1679}
1680
5fbd7e24
MW		 1681static int xcvr_init_1g_rgmii(struct niu *np)
1682{
1683 int err;
1684 u64 val;
1685 u16 bmcr, bmsr, estat;
1686
1687 val = nr64(MIF_CONFIG);
1688 val &= ~MIF_CONFIG_INDIRECT_MODE;
1689 nw64(MIF_CONFIG, val);
1690
1691 err = mii_reset(np);
1692 if (err)
1693 return err;
1694
1695 err = mii_read(np, np->phy_addr, MII_BMSR);
1696 if (err < 0)
1697 return err;
1698 bmsr = err;
1699
1700 estat = 0;
1701 if (bmsr & BMSR_ESTATEN) {
1702 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1703 if (err < 0)
1704 return err;
1705 estat = err;
1706 }
1707
1708 bmcr = 0;
1709 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1710 if (err)
1711 return err;
1712
1713 if (bmsr & BMSR_ESTATEN) {
1714 u16 ctrl1000 = 0;
1715
1716 if (estat & ESTATUS_1000_TFULL)
1717 ctrl1000 |= ADVERTISE_1000FULL;
1718 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1719 if (err)
1720 return err;
1721 }
1722
1723 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1724
1725 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1726 if (err)
1727 return err;
1728
1729 err = mii_read(np, np->phy_addr, MII_BMCR);
1730 if (err < 0)
1731 return err;
1732 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1733
1734 err = mii_read(np, np->phy_addr, MII_BMSR);
1735 if (err < 0)
1736 return err;
1737
1738 return 0;
1739}
1740
a3138df9
DM		 1741static int mii_init_common(struct niu *np)
1742{
1743 struct niu_link_config *lp = &np->link_config;
1744 u16 bmcr, bmsr, adv, estat;
1745 int err;
1746
1747 err = mii_reset(np);
1748 if (err)
1749 return err;
1750
1751 err = mii_read(np, np->phy_addr, MII_BMSR);
1752 if (err < 0)
1753 return err;
1754 bmsr = err;
1755
1756 estat = 0;
1757 if (bmsr & BMSR_ESTATEN) {
1758 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1759 if (err < 0)
1760 return err;
1761 estat = err;
1762 }
1763
1764 bmcr = 0;
1765 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1766 if (err)
1767 return err;
1768
1769 if (lp->loopback_mode == LOOPBACK_MAC) {
1770 bmcr |= BMCR_LOOPBACK;
1771 if (lp->active_speed == SPEED_1000)
1772 bmcr |= BMCR_SPEED1000;
1773 if (lp->active_duplex == DUPLEX_FULL)
1774 bmcr |= BMCR_FULLDPLX;
1775 }
1776
1777 if (lp->loopback_mode == LOOPBACK_PHY) {
1778 u16 aux;
1779
1780 aux = (BCM5464R_AUX_CTL_EXT_LB |
1781 BCM5464R_AUX_CTL_WRITE_1);
1782 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1783 if (err)
1784 return err;
1785 }
1786
38bb045d
CB		 1787 if (lp->autoneg) {
1788 u16 ctrl1000;
1789
1790 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1791 if ((bmsr & BMSR_10HALF) &&
1792 (lp->advertising & ADVERTISED_10baseT_Half))
1793 adv |= ADVERTISE_10HALF;
1794 if ((bmsr & BMSR_10FULL) &&
1795 (lp->advertising & ADVERTISED_10baseT_Full))
1796 adv |= ADVERTISE_10FULL;
1797 if ((bmsr & BMSR_100HALF) &&
1798 (lp->advertising & ADVERTISED_100baseT_Half))
1799 adv |= ADVERTISE_100HALF;
1800 if ((bmsr & BMSR_100FULL) &&
1801 (lp->advertising & ADVERTISED_100baseT_Full))
1802 adv |= ADVERTISE_100FULL;
1803 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1804 if (err)
1805 return err;
38bb045d
CB		 1806
1807 if (likely(bmsr & BMSR_ESTATEN)) {
1808 ctrl1000 = 0;
1809 if ((estat & ESTATUS_1000_THALF) &&
1810 (lp->advertising & ADVERTISED_1000baseT_Half))
1811 ctrl1000 |= ADVERTISE_1000HALF;
1812 if ((estat & ESTATUS_1000_TFULL) &&
1813 (lp->advertising & ADVERTISED_1000baseT_Full))
1814 ctrl1000 |= ADVERTISE_1000FULL;
1815 err = mii_write(np, np->phy_addr,
1816 MII_CTRL1000, ctrl1000);
1817 if (err)
1818 return err;
1819 }
1820
1821 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1822 } else {
1823 /* !lp->autoneg */
1824 int fulldpx;
1825
1826 if (lp->duplex == DUPLEX_FULL) {
1827 bmcr |= BMCR_FULLDPLX;
1828 fulldpx = 1;
1829 } else if (lp->duplex == DUPLEX_HALF)
1830 fulldpx = 0;
1831 else
1832 return -EINVAL;
1833
1834 if (lp->speed == SPEED_1000) {
1835 /* if X-full requested while not supported, or
1836 X-half requested while not supported... */
1837 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1838 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1839 return -EINVAL;
1840 bmcr |= BMCR_SPEED1000;
1841 } else if (lp->speed == SPEED_100) {
1842 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1843 (!fulldpx && !(bmsr & BMSR_100HALF)))
1844 return -EINVAL;
1845 bmcr |= BMCR_SPEED100;
1846 } else if (lp->speed == SPEED_10) {
1847 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1848 (!fulldpx && !(bmsr & BMSR_10HALF)))
1849 return -EINVAL;
1850 } else
1851 return -EINVAL;
a3138df9 1852 }
a3138df9
DM		 1853
1854 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1855 if (err)
1856 return err;
1857
38bb045d 1858#if 0
a3138df9
DM		 1859 err = mii_read(np, np->phy_addr, MII_BMCR);
1860 if (err < 0)
1861 return err;
38bb045d
CB		 1862 bmcr = err;
1863
a3138df9
DM		 1864 err = mii_read(np, np->phy_addr, MII_BMSR);
1865 if (err < 0)
1866 return err;
38bb045d
CB		 1867 bmsr = err;
1868
f10a1f2e 1869 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1870 np->port, bmcr, bmsr);
1871#endif
1872
1873 return 0;
1874}
1875
1876static int xcvr_init_1g(struct niu *np)
1877{
1878 u64 val;
1879
1880 /* XXX shared resource, lock parent XXX */
1881 val = nr64(MIF_CONFIG);
1882 val &= ~MIF_CONFIG_INDIRECT_MODE;
1883 nw64(MIF_CONFIG, val);
1884
1885 return mii_init_common(np);
1886}
1887
1888static int niu_xcvr_init(struct niu *np)
1889{
1890 const struct niu_phy_ops *ops = np->phy_ops;
1891 int err;
1892
1893 err = 0;
1894 if (ops->xcvr_init)
1895 err = ops->xcvr_init(np);
1896
1897 return err;
1898}
1899
1900static int niu_serdes_init(struct niu *np)
1901{
1902 const struct niu_phy_ops *ops = np->phy_ops;
1903 int err;
1904
1905 err = 0;
1906 if (ops->serdes_init)
1907 err = ops->serdes_init(np);
1908
1909 return err;
1910}
1911
1912static void niu_init_xif(struct niu *);
0c3b091b 1913static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1914
1915static int niu_link_status_common(struct niu *np, int link_up)
1916{
1917 struct niu_link_config *lp = &np->link_config;
1918 struct net_device *dev = np->dev;
1919 unsigned long flags;
1920
1921 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1922 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1923 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1924 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1925 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1926 "10Mbit/sec",
1927 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1928
1929 spin_lock_irqsave(&np->lock, flags);
1930 niu_init_xif(np);
0c3b091b 1931 niu_handle_led(np, 1);
a3138df9
DM		 1932 spin_unlock_irqrestore(&np->lock, flags);
1933
1934 netif_carrier_on(dev);
1935 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1936 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1937 spin_lock_irqsave(&np->lock, flags);
1938 niu_handle_led(np, 0);
1939 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1940 netif_carrier_off(dev);
1941 }
1942
1943 return 0;
1944}
1945
b0de8e40 1946static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1947{
b0de8e40 1948 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1949
1950 link_up = 0;
1951
b0de8e40
ML		 1952 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1953 MRVL88X2011_10G_PMD_STATUS_2);
1954 if (err < 0)
1955 goto out;
a3138df9 1956
b0de8e40
ML		 1957 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1958 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1959 MRVL88X2011_PMA_PMD_STATUS_1);
1960 if (err < 0)
1961 goto out;
1962
1963 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1964
1965 /* Check PMC Register : 3.0001.2 == 1: read twice */
1966 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1967 MRVL88X2011_PMA_PMD_STATUS_1);
1968 if (err < 0)
1969 goto out;
1970
1971 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1972 MRVL88X2011_PMA_PMD_STATUS_1);
1973 if (err < 0)
1974 goto out;
1975
1976 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1977
1978 /* Check XGXS Register : 4.0018.[0-3,12] */
1979 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1980 MRVL88X2011_10G_XGXS_LANE_STAT);
1981 if (err < 0)
a3138df9
DM		 1982 goto out;
1983
b0de8e40
ML		 1984 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1985 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1986 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1987 0x800))
1988 link_up = (pma_status && pcs_status) ? 1 : 0;
1989
1990 np->link_config.active_speed = SPEED_10000;
1991 np->link_config.active_duplex = DUPLEX_FULL;
1992 err = 0;
1993out:
1994 mrvl88x2011_act_led(np, (link_up ?
1995 MRVL88X2011_LED_CTL_PCS_ACT :
1996 MRVL88X2011_LED_CTL_OFF));
1997
1998 *link_up_p = link_up;
1999 return err;
2000}
2001
a5d6ab56
MW		 2002static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2003{
2004 int err, link_up;
2005 link_up = 0;
2006
2007 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2008 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2009 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2010 goto out;
2011 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2012 err = 0;
2013 goto out;
2014 }
2015
2016 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2017 BCM8704_PCS_10G_R_STATUS);
2018 if (err < 0)
2019 goto out;
2020
2021 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2022 err = 0;
2023 goto out;
2024 }
2025
2026 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2027 BCM8704_PHYXS_XGXS_LANE_STAT);
2028 if (err < 0)
2029 goto out;
2030 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2031 PHYXS_XGXS_LANE_STAT_MAGIC |
2032 PHYXS_XGXS_LANE_STAT_PATTEST |
2033 PHYXS_XGXS_LANE_STAT_LANE3 |
2034 PHYXS_XGXS_LANE_STAT_LANE2 |
2035 PHYXS_XGXS_LANE_STAT_LANE1 |
2036 PHYXS_XGXS_LANE_STAT_LANE0)) {
2037 err = 0;
2038 np->link_config.active_speed = SPEED_INVALID;
2039 np->link_config.active_duplex = DUPLEX_INVALID;
2040 goto out;
2041 }
2042
2043 link_up = 1;
2044 np->link_config.active_speed = SPEED_10000;
2045 np->link_config.active_duplex = DUPLEX_FULL;
2046 err = 0;
2047
2048out:
2049 *link_up_p = link_up;
a5d6ab56
MW		 2050 return err;
2051}
2052
b0de8e40
ML		 2053static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2054{
2055 int err, link_up;
2056
2057 link_up = 0;
2058
a3138df9
DM		 2059 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2060 BCM8704_PMD_RCV_SIGDET);
2061 if (err < 0)
2062 goto out;
2063 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2064 err = 0;
2065 goto out;
2066 }
2067
2068 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2069 BCM8704_PCS_10G_R_STATUS);
2070 if (err < 0)
2071 goto out;
2072 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2073 err = 0;
2074 goto out;
2075 }
2076
2077 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2078 BCM8704_PHYXS_XGXS_LANE_STAT);
2079 if (err < 0)
2080 goto out;
2081
2082 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2083 PHYXS_XGXS_LANE_STAT_MAGIC |
2084 PHYXS_XGXS_LANE_STAT_LANE3 |
2085 PHYXS_XGXS_LANE_STAT_LANE2 |
2086 PHYXS_XGXS_LANE_STAT_LANE1 |
2087 PHYXS_XGXS_LANE_STAT_LANE0)) {
2088 err = 0;
2089 goto out;
2090 }
2091
2092 link_up = 1;
2093 np->link_config.active_speed = SPEED_10000;
2094 np->link_config.active_duplex = DUPLEX_FULL;
2095 err = 0;
2096
2097out:
b0de8e40
ML		 2098 *link_up_p = link_up;
2099 return err;
2100}
2101
2102static int link_status_10g(struct niu *np, int *link_up_p)
2103{
2104 unsigned long flags;
2105 int err = -EINVAL;
2106
2107 spin_lock_irqsave(&np->lock, flags);
2108
2109 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2110 int phy_id;
2111
2112 phy_id = phy_decode(np->parent->port_phy, np->port);
2113 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2114
2115 /* handle different phy types */
2116 switch (phy_id & NIU_PHY_ID_MASK) {
2117 case NIU_PHY_ID_MRVL88X2011:
2118 err = link_status_10g_mrvl(np, link_up_p);
2119 break;
2120
2121 default: /* bcom 8704 */
2122 err = link_status_10g_bcom(np, link_up_p);
2123 break;
2124 }
2125 }
2126
a3138df9
DM		 2127 spin_unlock_irqrestore(&np->lock, flags);
2128
a3138df9
DM		 2129 return err;
2130}
2131
a5d6ab56
MW		 2132static int niu_10g_phy_present(struct niu *np)
2133{
2134 u64 sig, mask, val;
2135
2136 sig = nr64(ESR_INT_SIGNALS);
2137 switch (np->port) {
2138 case 0:
2139 mask = ESR_INT_SIGNALS_P0_BITS;
2140 val = (ESR_INT_SRDY0_P0 |
2141 ESR_INT_DET0_P0 |
2142 ESR_INT_XSRDY_P0 |
2143 ESR_INT_XDP_P0_CH3 |
2144 ESR_INT_XDP_P0_CH2 |
2145 ESR_INT_XDP_P0_CH1 |
2146 ESR_INT_XDP_P0_CH0);
2147 break;
2148
2149 case 1:
2150 mask = ESR_INT_SIGNALS_P1_BITS;
2151 val = (ESR_INT_SRDY0_P1 |
2152 ESR_INT_DET0_P1 |
2153 ESR_INT_XSRDY_P1 |
2154 ESR_INT_XDP_P1_CH3 |
2155 ESR_INT_XDP_P1_CH2 |
2156 ESR_INT_XDP_P1_CH1 |
2157 ESR_INT_XDP_P1_CH0);
2158 break;
2159
2160 default:
2161 return 0;
2162 }
2163
2164 if ((sig & mask) != val)
2165 return 0;
2166 return 1;
2167}
2168
2169static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2170{
2171 unsigned long flags;
2172 int err = 0;
2173 int phy_present;
2174 int phy_present_prev;
2175
2176 spin_lock_irqsave(&np->lock, flags);
2177
2178 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2179 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2180 1 : 0;
2181 phy_present = niu_10g_phy_present(np);
2182 if (phy_present != phy_present_prev) {
2183 /* state change */
2184 if (phy_present) {
9c5cd670 2185 /* A NEM was just plugged in */
a5d6ab56
MW		 2186 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2187 if (np->phy_ops->xcvr_init)
2188 err = np->phy_ops->xcvr_init(np);
2189 if (err) {
9c5cd670
TC		 2190 err = mdio_read(np, np->phy_addr,
2191 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2192 if (err == 0xffff) {
2193 /* No mdio, back-to-back XAUI */
2194 goto out;
2195 }
a5d6ab56
MW		 2196 /* debounce */
2197 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2198 }
2199 } else {
2200 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2201 *link_up_p = 0;
f10a1f2e
JP		 2202 netif_warn(np, link, np->dev,
2203 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2204 }
2205 }
9c5cd670
TC		 2206out:
2207 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2208 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2209 if (err == 0xffff) {
2210 /* No mdio, back-to-back XAUI: it is C10NEM */
2211 *link_up_p = 1;
2212 np->link_config.active_speed = SPEED_10000;
2213 np->link_config.active_duplex = DUPLEX_FULL;
2214 }
2215 }
a5d6ab56
MW		 2216 }
2217
2218 spin_unlock_irqrestore(&np->lock, flags);
2219
9c5cd670 2220 return 0;
a5d6ab56
MW		 2221}
2222
a3138df9
DM		 2223static int niu_link_status(struct niu *np, int *link_up_p)
2224{
2225 const struct niu_phy_ops *ops = np->phy_ops;
2226 int err;
2227
2228 err = 0;
2229 if (ops->link_status)
2230 err = ops->link_status(np, link_up_p);
2231
2232 return err;
2233}
2234
2235static void niu_timer(unsigned long __opaque)
2236{
2237 struct niu *np = (struct niu *) __opaque;
2238 unsigned long off;
2239 int err, link_up;
2240
2241 err = niu_link_status(np, &link_up);
2242 if (!err)
2243 niu_link_status_common(np, link_up);
2244
2245 if (netif_carrier_ok(np->dev))
2246 off = 5 * HZ;
2247 else
2248 off = 1 * HZ;
2249 np->timer.expires = jiffies + off;
2250
2251 add_timer(&np->timer);
2252}
2253
5fbd7e24
MW		 2254static const struct niu_phy_ops phy_ops_10g_serdes = {
2255 .serdes_init = serdes_init_10g_serdes,
2256 .link_status = link_status_10g_serdes,
2257};
2258
e3e081e1
SB		 2259static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2260 .serdes_init = serdes_init_niu_10g_serdes,
2261 .link_status = link_status_10g_serdes,
2262};
2263
2264static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2265 .serdes_init = serdes_init_niu_1g_serdes,
2266 .link_status = link_status_1g_serdes,
2267};
2268
5fbd7e24
MW		 2269static const struct niu_phy_ops phy_ops_1g_rgmii = {
2270 .xcvr_init = xcvr_init_1g_rgmii,
2271 .link_status = link_status_1g_rgmii,
2272};
2273
a3138df9 2274static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2275 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2276 .xcvr_init = xcvr_init_10g,
2277 .link_status = link_status_10g,
2278};
2279
2280static const struct niu_phy_ops phy_ops_10g_fiber = {
2281 .serdes_init = serdes_init_10g,
2282 .xcvr_init = xcvr_init_10g,
2283 .link_status = link_status_10g,
2284};
2285
a5d6ab56
MW		 2286static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2287 .serdes_init = serdes_init_10g,
2288 .xcvr_init = xcvr_init_10g_bcm8706,
2289 .link_status = link_status_10g_hotplug,
2290};
2291
9c5cd670
TC		 2292static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2293 .serdes_init = serdes_init_niu_10g_fiber,
2294 .xcvr_init = xcvr_init_10g_bcm8706,
2295 .link_status = link_status_10g_hotplug,
2296};
2297
a3138df9
DM		 2298static const struct niu_phy_ops phy_ops_10g_copper = {
2299 .serdes_init = serdes_init_10g,
2300 .link_status = link_status_10g, /* XXX */
2301};
2302
2303static const struct niu_phy_ops phy_ops_1g_fiber = {
2304 .serdes_init = serdes_init_1g,
2305 .xcvr_init = xcvr_init_1g,
2306 .link_status = link_status_1g,
2307};
2308
2309static const struct niu_phy_ops phy_ops_1g_copper = {
2310 .xcvr_init = xcvr_init_1g,
2311 .link_status = link_status_1g,
2312};
2313
2314struct niu_phy_template {
2315 const struct niu_phy_ops *ops;
2316 u32 phy_addr_base;
2317};
2318
e3e081e1 2319static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2320 .ops = &phy_ops_10g_fiber_niu,
2321 .phy_addr_base = 16,
2322};
2323
e3e081e1
SB		 2324static const struct niu_phy_template phy_template_niu_10g_serdes = {
2325 .ops = &phy_ops_10g_serdes_niu,
2326 .phy_addr_base = 0,
2327};
2328
2329static const struct niu_phy_template phy_template_niu_1g_serdes = {
2330 .ops = &phy_ops_1g_serdes_niu,
2331 .phy_addr_base = 0,
2332};
2333
a3138df9
DM		 2334static const struct niu_phy_template phy_template_10g_fiber = {
2335 .ops = &phy_ops_10g_fiber,
2336 .phy_addr_base = 8,
2337};
2338
a5d6ab56
MW		 2339static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2340 .ops = &phy_ops_10g_fiber_hotplug,
2341 .phy_addr_base = 8,
2342};
2343
9c5cd670
TC		 2344static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2345 .ops = &phy_ops_niu_10g_hotplug,
2346 .phy_addr_base = 8,
2347};
2348
a3138df9
DM		 2349static const struct niu_phy_template phy_template_10g_copper = {
2350 .ops = &phy_ops_10g_copper,
2351 .phy_addr_base = 10,
2352};
2353
2354static const struct niu_phy_template phy_template_1g_fiber = {
2355 .ops = &phy_ops_1g_fiber,
2356 .phy_addr_base = 0,
2357};
2358
2359static const struct niu_phy_template phy_template_1g_copper = {
2360 .ops = &phy_ops_1g_copper,
2361 .phy_addr_base = 0,
2362};
2363
5fbd7e24
MW		 2364static const struct niu_phy_template phy_template_1g_rgmii = {
2365 .ops = &phy_ops_1g_rgmii,
2366 .phy_addr_base = 0,
2367};
2368
2369static const struct niu_phy_template phy_template_10g_serdes = {
2370 .ops = &phy_ops_10g_serdes,
2371 .phy_addr_base = 0,
2372};
2373
2374static int niu_atca_port_num[4] = {
2375 0, 0, 11, 10
2376};
2377
2378static int serdes_init_10g_serdes(struct niu *np)
2379{
2380 struct niu_link_config *lp = &np->link_config;
2381 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2382 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2383
2384 switch (np->port) {
2385 case 0:
5fbd7e24
MW		 2386 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2387 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2388 pll_cfg = ENET_SERDES_0_PLL_CFG;
2389 break;
2390 case 1:
5fbd7e24
MW		 2391 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2392 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2393 pll_cfg = ENET_SERDES_1_PLL_CFG;
2394 break;
2395
2396 default:
2397 return -EINVAL;
2398 }
2399 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2400 ENET_SERDES_CTRL_SDET_1 |
2401 ENET_SERDES_CTRL_SDET_2 |
2402 ENET_SERDES_CTRL_SDET_3 |
2403 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2404 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2405 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2406 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2407 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2408 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2409 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2410 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2411 test_cfg_val = 0;
2412
2413 if (lp->loopback_mode == LOOPBACK_PHY) {
2414 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2415 ENET_SERDES_TEST_MD_0_SHIFT) |
2416 (ENET_TEST_MD_PAD_LOOPBACK <<
2417 ENET_SERDES_TEST_MD_1_SHIFT) |
2418 (ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_2_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_3_SHIFT));
2422 }
2423
2424 esr_reset(np);
2425 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2426 nw64(ctrl_reg, ctrl_val);
2427 nw64(test_cfg_reg, test_cfg_val);
2428
2429 /* Initialize all 4 lanes of the SERDES. */
2430 for (i = 0; i < 4; i++) {
2431 u32 rxtx_ctrl, glue0;
7c34eb89 2432 int err;
5fbd7e24
MW		 2433
2434 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2435 if (err)
2436 return err;
2437 err = esr_read_glue0(np, i, &glue0);
2438 if (err)
2439 return err;
2440
2441 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2442 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2443 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2444
2445 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2446 ESR_GLUE_CTRL0_THCNT |
2447 ESR_GLUE_CTRL0_BLTIME);
2448 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2449 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2450 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2451 (BLTIME_300_CYCLES <<
2452 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2453
2454 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2455 if (err)
2456 return err;
2457 err = esr_write_glue0(np, i, glue0);
2458 if (err)
2459 return err;
2460 }
2461
2462
2463 sig = nr64(ESR_INT_SIGNALS);
2464 switch (np->port) {
2465 case 0:
2466 mask = ESR_INT_SIGNALS_P0_BITS;
2467 val = (ESR_INT_SRDY0_P0 |
2468 ESR_INT_DET0_P0 |
2469 ESR_INT_XSRDY_P0 |
2470 ESR_INT_XDP_P0_CH3 |
2471 ESR_INT_XDP_P0_CH2 |
2472 ESR_INT_XDP_P0_CH1 |
2473 ESR_INT_XDP_P0_CH0);
2474 break;
2475
2476 case 1:
2477 mask = ESR_INT_SIGNALS_P1_BITS;
2478 val = (ESR_INT_SRDY0_P1 |
2479 ESR_INT_DET0_P1 |
2480 ESR_INT_XSRDY_P1 |
2481 ESR_INT_XDP_P1_CH3 |
2482 ESR_INT_XDP_P1_CH2 |
2483 ESR_INT_XDP_P1_CH1 |
2484 ESR_INT_XDP_P1_CH0);
2485 break;
2486
2487 default:
2488 return -EINVAL;
2489 }
2490
2491 if ((sig & mask) != val) {
2492 int err;
2493 err = serdes_init_1g_serdes(np);
2494 if (!err) {
2495 np->flags &= ~NIU_FLAGS_10G;
2496 np->mac_xcvr = MAC_XCVR_PCS;
2497 } else {
f10a1f2e
JP		 2498 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2499 np->port);
5fbd7e24
MW		 2500 return -ENODEV;
2501 }
2502 }
2503
2504 return 0;
2505}
2506
a3138df9
DM		 2507static int niu_determine_phy_disposition(struct niu *np)
2508{
2509 struct niu_parent *parent = np->parent;
2510 u8 plat_type = parent->plat_type;
2511 const struct niu_phy_template *tp;
2512 u32 phy_addr_off = 0;
2513
2514 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2515 switch (np->flags &
2516 (NIU_FLAGS_10G |
2517 NIU_FLAGS_FIBER |
2518 NIU_FLAGS_XCVR_SERDES)) {
2519 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2520 /* 10G Serdes */
2521 tp = &phy_template_niu_10g_serdes;
2522 break;
2523 case NIU_FLAGS_XCVR_SERDES:
2524 /* 1G Serdes */
2525 tp = &phy_template_niu_1g_serdes;
2526 break;
2527 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2528 /* 10G Fiber */
2529 default:
9c5cd670
TC		 2530 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2531 tp = &phy_template_niu_10g_hotplug;
2532 if (np->port == 0)
2533 phy_addr_off = 8;
2534 if (np->port == 1)
2535 phy_addr_off = 12;
2536 } else {
2537 tp = &phy_template_niu_10g_fiber;
2538 phy_addr_off += np->port;
2539 }
e3e081e1
SB		 2540 break;
2541 }
a3138df9 2542 } else {
5fbd7e24
MW		 2543 switch (np->flags &
2544 (NIU_FLAGS_10G |
2545 NIU_FLAGS_FIBER |
2546 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2547 case 0:
2548 /* 1G copper */
2549 tp = &phy_template_1g_copper;
2550 if (plat_type == PLAT_TYPE_VF_P0)
2551 phy_addr_off = 10;
2552 else if (plat_type == PLAT_TYPE_VF_P1)
2553 phy_addr_off = 26;
2554
2555 phy_addr_off += (np->port ^ 0x3);
2556 break;
2557
2558 case NIU_FLAGS_10G:
2559 /* 10G copper */
e0d8496a 2560 tp = &phy_template_10g_copper;
a3138df9
DM		 2561 break;
2562
2563 case NIU_FLAGS_FIBER:
2564 /* 1G fiber */
2565 tp = &phy_template_1g_fiber;
2566 break;
2567
2568 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2569 /* 10G fiber */
2570 tp = &phy_template_10g_fiber;
2571 if (plat_type == PLAT_TYPE_VF_P0 ||
2572 plat_type == PLAT_TYPE_VF_P1)
2573 phy_addr_off = 8;
2574 phy_addr_off += np->port;
a5d6ab56
MW		 2575 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2576 tp = &phy_template_10g_fiber_hotplug;
2577 if (np->port == 0)
2578 phy_addr_off = 8;
2579 if (np->port == 1)
2580 phy_addr_off = 12;
2581 }
a3138df9
DM		 2582 break;
2583
5fbd7e24
MW		 2584 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2585 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2586 case NIU_FLAGS_XCVR_SERDES:
2587 switch(np->port) {
2588 case 0:
2589 case 1:
2590 tp = &phy_template_10g_serdes;
2591 break;
2592 case 2:
2593 case 3:
2594 tp = &phy_template_1g_rgmii;
2595 break;
2596 default:
2597 return -EINVAL;
2598 break;
2599 }
2600 phy_addr_off = niu_atca_port_num[np->port];
2601 break;
2602
a3138df9
DM		 2603 default:
2604 return -EINVAL;
2605 }
2606 }
2607
2608 np->phy_ops = tp->ops;
2609 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2610
2611 return 0;
2612}
2613
2614static int niu_init_link(struct niu *np)
2615{
2616 struct niu_parent *parent = np->parent;
2617 int err, ignore;
2618
2619 if (parent->plat_type == PLAT_TYPE_NIU) {
2620 err = niu_xcvr_init(np);
2621 if (err)
2622 return err;
2623 msleep(200);
2624 }
2625 err = niu_serdes_init(np);
9c5cd670 2626 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2627 return err;
2628 msleep(200);
2629 err = niu_xcvr_init(np);
9c5cd670 2630 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2631 niu_link_status(np, &ignore);
2632 return 0;
2633}
2634
2635static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2636{
2637 u16 reg0 = addr[4] << 8 | addr[5];
2638 u16 reg1 = addr[2] << 8 | addr[3];
2639 u16 reg2 = addr[0] << 8 | addr[1];
2640
2641 if (np->flags & NIU_FLAGS_XMAC) {
2642 nw64_mac(XMAC_ADDR0, reg0);
2643 nw64_mac(XMAC_ADDR1, reg1);
2644 nw64_mac(XMAC_ADDR2, reg2);
2645 } else {
2646 nw64_mac(BMAC_ADDR0, reg0);
2647 nw64_mac(BMAC_ADDR1, reg1);
2648 nw64_mac(BMAC_ADDR2, reg2);
2649 }
2650}
2651
2652static int niu_num_alt_addr(struct niu *np)
2653{
2654 if (np->flags & NIU_FLAGS_XMAC)
2655 return XMAC_NUM_ALT_ADDR;
2656 else
2657 return BMAC_NUM_ALT_ADDR;
2658}
2659
2660static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2661{
2662 u16 reg0 = addr[4] << 8 | addr[5];
2663 u16 reg1 = addr[2] << 8 | addr[3];
2664 u16 reg2 = addr[0] << 8 | addr[1];
2665
2666 if (index >= niu_num_alt_addr(np))
2667 return -EINVAL;
2668
2669 if (np->flags & NIU_FLAGS_XMAC) {
2670 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2671 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2672 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2673 } else {
2674 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2677 }
2678
2679 return 0;
2680}
2681
2682static int niu_enable_alt_mac(struct niu *np, int index, int on)
2683{
2684 unsigned long reg;
2685 u64 val, mask;
2686
2687 if (index >= niu_num_alt_addr(np))
2688 return -EINVAL;
2689
fa907895 2690 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2691 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2692 mask = 1 << index;
2693 } else {
a3138df9 2694 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2695 mask = 1 << (index + 1);
2696 }
a3138df9
DM		 2697
2698 val = nr64_mac(reg);
2699 if (on)
2700 val |= mask;
2701 else
2702 val &= ~mask;
2703 nw64_mac(reg, val);
2704
2705 return 0;
2706}
2707
2708static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2709 int num, int mac_pref)
2710{
2711 u64 val = nr64_mac(reg);
2712 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2713 val |= num;
2714 if (mac_pref)
2715 val |= HOST_INFO_MPR;
2716 nw64_mac(reg, val);
2717}
2718
2719static int __set_rdc_table_num(struct niu *np,
2720 int xmac_index, int bmac_index,
2721 int rdc_table_num, int mac_pref)
2722{
2723 unsigned long reg;
2724
2725 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2726 return -EINVAL;
2727 if (np->flags & NIU_FLAGS_XMAC)
2728 reg = XMAC_HOST_INFO(xmac_index);
2729 else
2730 reg = BMAC_HOST_INFO(bmac_index);
2731 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2732 return 0;
2733}
2734
2735static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2736 int mac_pref)
2737{
2738 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2739}
2740
2741static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2742 int mac_pref)
2743{
2744 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2745}
2746
2747static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2748 int table_num, int mac_pref)
2749{
2750 if (idx >= niu_num_alt_addr(np))
2751 return -EINVAL;
2752 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2753}
2754
2755static u64 vlan_entry_set_parity(u64 reg_val)
2756{
2757 u64 port01_mask;
2758 u64 port23_mask;
2759
2760 port01_mask = 0x00ff;
2761 port23_mask = 0xff00;
2762
2763 if (hweight64(reg_val & port01_mask) & 1)
2764 reg_val |= ENET_VLAN_TBL_PARITY0;
2765 else
2766 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2767
2768 if (hweight64(reg_val & port23_mask) & 1)
2769 reg_val |= ENET_VLAN_TBL_PARITY1;
2770 else
2771 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2772
2773 return reg_val;
2774}
2775
2776static void vlan_tbl_write(struct niu *np, unsigned long index,
2777 int port, int vpr, int rdc_table)
2778{
2779 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2780
2781 reg_val &= ~((ENET_VLAN_TBL_VPR |
2782 ENET_VLAN_TBL_VLANRDCTBLN) <<
2783 ENET_VLAN_TBL_SHIFT(port));
2784 if (vpr)
2785 reg_val |= (ENET_VLAN_TBL_VPR <<
2786 ENET_VLAN_TBL_SHIFT(port));
2787 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2788
2789 reg_val = vlan_entry_set_parity(reg_val);
2790
2791 nw64(ENET_VLAN_TBL(index), reg_val);
2792}
2793
2794static void vlan_tbl_clear(struct niu *np)
2795{
2796 int i;
2797
2798 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2799 nw64(ENET_VLAN_TBL(i), 0);
2800}
2801
2802static int tcam_wait_bit(struct niu *np, u64 bit)
2803{
2804 int limit = 1000;
2805
2806 while (--limit > 0) {
2807 if (nr64(TCAM_CTL) & bit)
2808 break;
2809 udelay(1);
2810 }
d2a928e4 2811 if (limit <= 0)
a3138df9
DM		 2812 return -ENODEV;
2813
2814 return 0;
2815}
2816
2817static int tcam_flush(struct niu *np, int index)
2818{
2819 nw64(TCAM_KEY_0, 0x00);
2820 nw64(TCAM_KEY_MASK_0, 0xff);
2821 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2822
2823 return tcam_wait_bit(np, TCAM_CTL_STAT);
2824}
2825
2826#if 0
2827static int tcam_read(struct niu *np, int index,
2828 u64 *key, u64 *mask)
2829{
2830 int err;
2831
2832 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2833 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2834 if (!err) {
2835 key[0] = nr64(TCAM_KEY_0);
2836 key[1] = nr64(TCAM_KEY_1);
2837 key[2] = nr64(TCAM_KEY_2);
2838 key[3] = nr64(TCAM_KEY_3);
2839 mask[0] = nr64(TCAM_KEY_MASK_0);
2840 mask[1] = nr64(TCAM_KEY_MASK_1);
2841 mask[2] = nr64(TCAM_KEY_MASK_2);
2842 mask[3] = nr64(TCAM_KEY_MASK_3);
2843 }
2844 return err;
2845}
2846#endif
2847
2848static int tcam_write(struct niu *np, int index,
2849 u64 *key, u64 *mask)
2850{
2851 nw64(TCAM_KEY_0, key[0]);
2852 nw64(TCAM_KEY_1, key[1]);
2853 nw64(TCAM_KEY_2, key[2]);
2854 nw64(TCAM_KEY_3, key[3]);
2855 nw64(TCAM_KEY_MASK_0, mask[0]);
2856 nw64(TCAM_KEY_MASK_1, mask[1]);
2857 nw64(TCAM_KEY_MASK_2, mask[2]);
2858 nw64(TCAM_KEY_MASK_3, mask[3]);
2859 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2860
2861 return tcam_wait_bit(np, TCAM_CTL_STAT);
2862}
2863
2864#if 0
2865static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2866{
2867 int err;
2868
2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2870 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2871 if (!err)
2872 *data = nr64(TCAM_KEY_1);
2873
2874 return err;
2875}
2876#endif
2877
2878static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2879{
2880 nw64(TCAM_KEY_1, assoc_data);
2881 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2882
2883 return tcam_wait_bit(np, TCAM_CTL_STAT);
2884}
2885
2886static void tcam_enable(struct niu *np, int on)
2887{
2888 u64 val = nr64(FFLP_CFG_1);
2889
2890 if (on)
2891 val &= ~FFLP_CFG_1_TCAM_DIS;
2892 else
2893 val |= FFLP_CFG_1_TCAM_DIS;
2894 nw64(FFLP_CFG_1, val);
2895}
2896
2897static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2898{
2899 u64 val = nr64(FFLP_CFG_1);
2900
2901 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2902 FFLP_CFG_1_CAMLAT |
2903 FFLP_CFG_1_CAMRATIO);
2904 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2905 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2906 nw64(FFLP_CFG_1, val);
2907
2908 val = nr64(FFLP_CFG_1);
2909 val |= FFLP_CFG_1_FFLPINITDONE;
2910 nw64(FFLP_CFG_1, val);
2911}
2912
2913static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2914 int on)
2915{
2916 unsigned long reg;
2917 u64 val;
2918
2919 if (class < CLASS_CODE_ETHERTYPE1 ||
2920 class > CLASS_CODE_ETHERTYPE2)
2921 return -EINVAL;
2922
2923 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2924 val = nr64(reg);
2925 if (on)
2926 val |= L2_CLS_VLD;
2927 else
2928 val &= ~L2_CLS_VLD;
2929 nw64(reg, val);
2930
2931 return 0;
2932}
2933
2934#if 0
2935static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2936 u64 ether_type)
2937{
2938 unsigned long reg;
2939 u64 val;
2940
2941 if (class < CLASS_CODE_ETHERTYPE1 ||
2942 class > CLASS_CODE_ETHERTYPE2 ||
2943 (ether_type & ~(u64)0xffff) != 0)
2944 return -EINVAL;
2945
2946 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2947 val = nr64(reg);
2948 val &= ~L2_CLS_ETYPE;
2949 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2950 nw64(reg, val);
2951
2952 return 0;
2953}
2954#endif
2955
2956static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2957 int on)
2958{
2959 unsigned long reg;
2960 u64 val;
2961
2962 if (class < CLASS_CODE_USER_PROG1 ||
2963 class > CLASS_CODE_USER_PROG4)
2964 return -EINVAL;
2965
2966 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2967 val = nr64(reg);
2968 if (on)
2969 val |= L3_CLS_VALID;
2970 else
2971 val &= ~L3_CLS_VALID;
2972 nw64(reg, val);
2973
2974 return 0;
2975}
2976
a3138df9
DM		 2977static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2978 int ipv6, u64 protocol_id,
2979 u64 tos_mask, u64 tos_val)
2980{
2981 unsigned long reg;
2982 u64 val;
2983
2984 if (class < CLASS_CODE_USER_PROG1 ||
2985 class > CLASS_CODE_USER_PROG4 ||
2986 (protocol_id & ~(u64)0xff) != 0 ||
2987 (tos_mask & ~(u64)0xff) != 0 ||
2988 (tos_val & ~(u64)0xff) != 0)
2989 return -EINVAL;
2990
2991 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2992 val = nr64(reg);
2993 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2994 L3_CLS_TOSMASK | L3_CLS_TOS);
2995 if (ipv6)
2996 val |= L3_CLS_IPVER;
2997 val |= (protocol_id << L3_CLS_PID_SHIFT);
2998 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2999 val |= (tos_val << L3_CLS_TOS_SHIFT);
3000 nw64(reg, val);
3001
3002 return 0;
3003}
a3138df9
DM		 3004
3005static int tcam_early_init(struct niu *np)
3006{
3007 unsigned long i;
3008 int err;
3009
3010 tcam_enable(np, 0);
3011 tcam_set_lat_and_ratio(np,
3012 DEFAULT_TCAM_LATENCY,
3013 DEFAULT_TCAM_ACCESS_RATIO);
3014 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3015 err = tcam_user_eth_class_enable(np, i, 0);
3016 if (err)
3017 return err;
3018 }
3019 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3020 err = tcam_user_ip_class_enable(np, i, 0);
3021 if (err)
3022 return err;
3023 }
3024
3025 return 0;
3026}
3027
3028static int tcam_flush_all(struct niu *np)
3029{
3030 unsigned long i;
3031
3032 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3033 int err = tcam_flush(np, i);
3034 if (err)
3035 return err;
3036 }
3037 return 0;
3038}
3039
3040static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3041{
807540ba 3042 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
a3138df9
DM		 3043}
3044
3045#if 0
3046static int hash_read(struct niu *np, unsigned long partition,
3047 unsigned long index, unsigned long num_entries,
3048 u64 *data)
3049{
3050 u64 val = hash_addr_regval(index, num_entries);
3051 unsigned long i;
3052
3053 if (partition >= FCRAM_NUM_PARTITIONS ||
3054 index + num_entries > FCRAM_SIZE)
3055 return -EINVAL;
3056
3057 nw64(HASH_TBL_ADDR(partition), val);
3058 for (i = 0; i < num_entries; i++)
3059 data[i] = nr64(HASH_TBL_DATA(partition));
3060
3061 return 0;
3062}
3063#endif
3064
3065static int hash_write(struct niu *np, unsigned long partition,
3066 unsigned long index, unsigned long num_entries,
3067 u64 *data)
3068{
3069 u64 val = hash_addr_regval(index, num_entries);
3070 unsigned long i;
3071
3072 if (partition >= FCRAM_NUM_PARTITIONS ||
3073 index + (num_entries * 8) > FCRAM_SIZE)
3074 return -EINVAL;
3075
3076 nw64(HASH_TBL_ADDR(partition), val);
3077 for (i = 0; i < num_entries; i++)
3078 nw64(HASH_TBL_DATA(partition), data[i]);
3079
3080 return 0;
3081}
3082
3083static void fflp_reset(struct niu *np)
3084{
3085 u64 val;
3086
3087 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3088 udelay(10);
3089 nw64(FFLP_CFG_1, 0);
3090
3091 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3092 nw64(FFLP_CFG_1, val);
3093}
3094
3095static void fflp_set_timings(struct niu *np)
3096{
3097 u64 val = nr64(FFLP_CFG_1);
3098
3099 val &= ~FFLP_CFG_1_FFLPINITDONE;
3100 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3101 nw64(FFLP_CFG_1, val);
3102
3103 val = nr64(FFLP_CFG_1);
3104 val |= FFLP_CFG_1_FFLPINITDONE;
3105 nw64(FFLP_CFG_1, val);
3106
3107 val = nr64(FCRAM_REF_TMR);
3108 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3109 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3110 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3111 nw64(FCRAM_REF_TMR, val);
3112}
3113
3114static int fflp_set_partition(struct niu *np, u64 partition,
3115 u64 mask, u64 base, int enable)
3116{
3117 unsigned long reg;
3118 u64 val;
3119
3120 if (partition >= FCRAM_NUM_PARTITIONS ||
3121 (mask & ~(u64)0x1f) != 0 ||
3122 (base & ~(u64)0x1f) != 0)
3123 return -EINVAL;
3124
3125 reg = FLW_PRT_SEL(partition);
3126
3127 val = nr64(reg);
3128 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3129 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3130 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3131 if (enable)
3132 val |= FLW_PRT_SEL_EXT;
3133 nw64(reg, val);
3134
3135 return 0;
3136}
3137
3138static int fflp_disable_all_partitions(struct niu *np)
3139{
3140 unsigned long i;
3141
3142 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3143 int err = fflp_set_partition(np, 0, 0, 0, 0);
3144 if (err)
3145 return err;
3146 }
3147 return 0;
3148}
3149
3150static void fflp_llcsnap_enable(struct niu *np, int on)
3151{
3152 u64 val = nr64(FFLP_CFG_1);
3153
3154 if (on)
3155 val |= FFLP_CFG_1_LLCSNAP;
3156 else
3157 val &= ~FFLP_CFG_1_LLCSNAP;
3158 nw64(FFLP_CFG_1, val);
3159}
3160
3161static void fflp_errors_enable(struct niu *np, int on)
3162{
3163 u64 val = nr64(FFLP_CFG_1);
3164
3165 if (on)
3166 val &= ~FFLP_CFG_1_ERRORDIS;
3167 else
3168 val |= FFLP_CFG_1_ERRORDIS;
3169 nw64(FFLP_CFG_1, val);
3170}
3171
3172static int fflp_hash_clear(struct niu *np)
3173{
3174 struct fcram_hash_ipv4 ent;
3175 unsigned long i;
3176
3177 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3178 memset(&ent, 0, sizeof(ent));
3179 ent.header = HASH_HEADER_EXT;
3180
3181 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3182 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3183 if (err)
3184 return err;
3185 }
3186 return 0;
3187}
3188
3189static int fflp_early_init(struct niu *np)
3190{
3191 struct niu_parent *parent;
3192 unsigned long flags;
3193 int err;
3194
3195 niu_lock_parent(np, flags);
3196
3197 parent = np->parent;
3198 err = 0;
3199 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3200 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3201 fflp_reset(np);
3202 fflp_set_timings(np);
3203 err = fflp_disable_all_partitions(np);
3204 if (err) {
f10a1f2e
JP		 3205 netif_printk(np, probe, KERN_DEBUG, np->dev,
3206 "fflp_disable_all_partitions failed, err=%d\n",
3207 err);
a3138df9
DM		 3208 goto out;
3209 }
3210 }
3211
3212 err = tcam_early_init(np);
3213 if (err) {
f10a1f2e
JP		 3214 netif_printk(np, probe, KERN_DEBUG, np->dev,
3215 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3216 goto out;
3217 }
3218 fflp_llcsnap_enable(np, 1);
3219 fflp_errors_enable(np, 0);
3220 nw64(H1POLY, 0);
3221 nw64(H2POLY, 0);
3222
3223 err = tcam_flush_all(np);
3224 if (err) {
f10a1f2e
JP		 3225 netif_printk(np, probe, KERN_DEBUG, np->dev,
3226 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3227 goto out;
3228 }
3229 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3230 err = fflp_hash_clear(np);
3231 if (err) {
f10a1f2e
JP		 3232 netif_printk(np, probe, KERN_DEBUG, np->dev,
3233 "fflp_hash_clear failed, err=%d\n",
3234 err);
a3138df9
DM		 3235 goto out;
3236 }
3237 }
3238
3239 vlan_tbl_clear(np);
3240
a3138df9
DM		 3241 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3242 }
3243out:
3244 niu_unlock_parent(np, flags);
3245 return err;
3246}
3247
3248static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3249{
3250 if (class_code < CLASS_CODE_USER_PROG1 ||
3251 class_code > CLASS_CODE_SCTP_IPV6)
3252 return -EINVAL;
3253
3254 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3255 return 0;
3256}
3257
3258static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3259{
3260 if (class_code < CLASS_CODE_USER_PROG1 ||
3261 class_code > CLASS_CODE_SCTP_IPV6)
3262 return -EINVAL;
3263
3264 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3265 return 0;
3266}
3267
2d96cf8c
SB		 3268/* Entries for the ports are interleaved in the TCAM */
3269static u16 tcam_get_index(struct niu *np, u16 idx)
3270{
3271 /* One entry reserved for IP fragment rule */
3272 if (idx >= (np->clas.tcam_sz - 1))
3273 idx = 0;
807540ba 3274 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
2d96cf8c
SB		 3275}
3276
3277static u16 tcam_get_size(struct niu *np)
3278{
3279 /* One entry reserved for IP fragment rule */
3280 return np->clas.tcam_sz - 1;
3281}
3282
3283static u16 tcam_get_valid_entry_cnt(struct niu *np)
3284{
3285 /* One entry reserved for IP fragment rule */
3286 return np->clas.tcam_valid_entries - 1;
3287}
3288
a3138df9
DM		 3289static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3290 u32 offset, u32 size)
3291{
3292 int i = skb_shinfo(skb)->nr_frags;
a3138df9 3293
134b413c 3294 __skb_fill_page_desc(skb, i, page, offset, size);
a3138df9
DM		 3295
3296 skb->len += size;
3297 skb->data_len += size;
3298 skb->truesize += size;
3299
3300 skb_shinfo(skb)->nr_frags = i + 1;
3301}
3302
3303static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3304{
3305 a >>= PAGE_SHIFT;
3306 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3307
807540ba 3308 return a & (MAX_RBR_RING_SIZE - 1);
a3138df9
DM		 3309}
3310
3311static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3312 struct page ***link)
3313{
3314 unsigned int h = niu_hash_rxaddr(rp, addr);
3315 struct page *p, **pp;
3316
3317 addr &= PAGE_MASK;
3318 pp = &rp->rxhash[h];
3319 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3320 if (p->index == addr) {
3321 *link = pp;
a0387169 3322 goto found;
a3138df9
DM		 3323 }
3324 }
a0387169 3325 BUG();
a3138df9 3326
a0387169 3327found:
a3138df9
DM		 3328 return p;
3329}
3330
3331static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3332{
3333 unsigned int h = niu_hash_rxaddr(rp, base);
3334
3335 page->index = base;
3336 page->mapping = (struct address_space *) rp->rxhash[h];
3337 rp->rxhash[h] = page;
3338}
3339
3340static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3341 gfp_t mask, int start_index)
3342{
3343 struct page *page;
3344 u64 addr;
3345 int i;
3346
3347 page = alloc_page(mask);
3348 if (!page)
3349 return -ENOMEM;
3350
3351 addr = np->ops->map_page(np->device, page, 0,
3352 PAGE_SIZE, DMA_FROM_DEVICE);
3353
3354 niu_hash_page(rp, page, addr);
3355 if (rp->rbr_blocks_per_page > 1)
3356 atomic_add(rp->rbr_blocks_per_page - 1,
3357 &compound_head(page)->_count);
3358
3359 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3360 __le32 *rbr = &rp->rbr[start_index + i];
3361
3362 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3363 addr += rp->rbr_block_size;
3364 }
3365
3366 return 0;
3367}
3368
3369static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3370{
3371 int index = rp->rbr_index;
3372
3373 rp->rbr_pending++;
3374 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3375 int err = niu_rbr_add_page(np, rp, mask, index);
3376
3377 if (unlikely(err)) {
3378 rp->rbr_pending--;
3379 return;
3380 }
3381
3382 rp->rbr_index += rp->rbr_blocks_per_page;
3383 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3384 if (rp->rbr_index == rp->rbr_table_size)
3385 rp->rbr_index = 0;
3386
3387 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3388 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3389 rp->rbr_pending = 0;
3390 }
3391 }
3392}
3393
3394static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3395{
3396 unsigned int index = rp->rcr_index;
3397 int num_rcr = 0;
3398
3399 rp->rx_dropped++;
3400 while (1) {
3401 struct page *page, **link;
3402 u64 addr, val;
3403 u32 rcr_size;
3404
3405 num_rcr++;
3406
3407 val = le64_to_cpup(&rp->rcr[index]);
3408 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3409 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3410 page = niu_find_rxpage(rp, addr, &link);
3411
3412 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3413 RCR_ENTRY_PKTBUFSZ_SHIFT];
3414 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3415 *link = (struct page *) page->mapping;
3416 np->ops->unmap_page(np->device, page->index,
3417 PAGE_SIZE, DMA_FROM_DEVICE);
3418 page->index = 0;
3419 page->mapping = NULL;
3420 __free_page(page);
3421 rp->rbr_refill_pending++;
3422 }
3423
3424 index = NEXT_RCR(rp, index);
3425 if (!(val & RCR_ENTRY_MULTI))
3426 break;
3427
3428 }
3429 rp->rcr_index = index;
3430
3431 return num_rcr;
3432}
3433
4099e012
DM		 3434static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3435 struct rx_ring_info *rp)
a3138df9
DM		 3436{
3437 unsigned int index = rp->rcr_index;
3cfa856d 3438 struct rx_pkt_hdr1 *rh;
a3138df9
DM		 3439 struct sk_buff *skb;
3440 int len, num_rcr;
3441
3442 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3443 if (unlikely(!skb))
3444 return niu_rx_pkt_ignore(np, rp);
3445
3446 num_rcr = 0;
3447 while (1) {
3448 struct page *page, **link;
3449 u32 rcr_size, append_size;
3450 u64 addr, val, off;
3451
3452 num_rcr++;
3453
3454 val = le64_to_cpup(&rp->rcr[index]);
3455
3456 len = (val & RCR_ENTRY_L2_LEN) >>
3457 RCR_ENTRY_L2_LEN_SHIFT;
3458 len -= ETH_FCS_LEN;
3459
3460 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3461 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3462 page = niu_find_rxpage(rp, addr, &link);
3463
3464 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3465 RCR_ENTRY_PKTBUFSZ_SHIFT];
3466
3467 off = addr & ~PAGE_MASK;
3468 append_size = rcr_size;
3469 if (num_rcr == 1) {
3470 int ptype;
3471
a3138df9
DM		 3472 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3473 if ((ptype == RCR_PKT_TYPE_TCP ||
3474 ptype == RCR_PKT_TYPE_UDP) &&
3475 !(val & (RCR_ENTRY_NOPORT |
3476 RCR_ENTRY_ERROR)))
3477 skb->ip_summed = CHECKSUM_UNNECESSARY;
3478 else
bc8acf2c 3479 skb_checksum_none_assert(skb);
3cfa856d 3480 } else if (!(val & RCR_ENTRY_MULTI))
a3138df9
DM		 3481 append_size = len - skb->len;
3482
3483 niu_rx_skb_append(skb, page, off, append_size);
3484 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3485 *link = (struct page *) page->mapping;
3486 np->ops->unmap_page(np->device, page->index,
3487 PAGE_SIZE, DMA_FROM_DEVICE);
3488 page->index = 0;
3489 page->mapping = NULL;
3490 rp->rbr_refill_pending++;
3491 } else
3492 get_page(page);
3493
3494 index = NEXT_RCR(rp, index);
3495 if (!(val & RCR_ENTRY_MULTI))
3496 break;
3497
3498 }
3499 rp->rcr_index = index;
3500
3cfa856d
DM		 3501 len += sizeof(*rh);
3502 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3503 __pskb_pull_tail(skb, len);
3504
3505 rh = (struct rx_pkt_hdr1 *) skb->data;
3506 if (np->dev->features & NETIF_F_RXHASH)
3507 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3508 (u32)rh->hashval2_1 << 16 |
3509 (u32)rh->hashval1_1 << 8 |
3510 (u32)rh->hashval1_2 << 0);
3511 skb_pull(skb, sizeof(*rh));
a3138df9
DM		 3512
3513 rp->rx_packets++;
3514 rp->rx_bytes += skb->len;
3515
3516 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3517 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3518 napi_gro_receive(napi, skb);
a3138df9
DM		 3519
3520 return num_rcr;
3521}
3522
3523static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3524{
3525 int blocks_per_page = rp->rbr_blocks_per_page;
3526 int err, index = rp->rbr_index;
3527
3528 err = 0;
3529 while (index < (rp->rbr_table_size - blocks_per_page)) {
3530 err = niu_rbr_add_page(np, rp, mask, index);
3531 if (err)
3532 break;
3533
3534 index += blocks_per_page;
3535 }
3536
3537 rp->rbr_index = index;
3538 return err;
3539}
3540
3541static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3542{
3543 int i;
3544
3545 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3546 struct page *page;
3547
3548 page = rp->rxhash[i];
3549 while (page) {
3550 struct page *next = (struct page *) page->mapping;
3551 u64 base = page->index;
3552
3553 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3554 DMA_FROM_DEVICE);
3555 page->index = 0;
3556 page->mapping = NULL;
3557
3558 __free_page(page);
3559
3560 page = next;
3561 }
3562 }
3563
3564 for (i = 0; i < rp->rbr_table_size; i++)
3565 rp->rbr[i] = cpu_to_le32(0);
3566 rp->rbr_index = 0;
3567}
3568
3569static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3570{
3571 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3572 struct sk_buff *skb = tb->skb;
3573 struct tx_pkt_hdr *tp;
3574 u64 tx_flags;
3575 int i, len;
3576
3577 tp = (struct tx_pkt_hdr *) skb->data;
3578 tx_flags = le64_to_cpup(&tp->flags);
3579
3580 rp->tx_packets++;
3581 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3582 ((tx_flags & TXHDR_PAD) / 2));
3583
3584 len = skb_headlen(skb);
3585 np->ops->unmap_single(np->device, tb->mapping,
3586 len, DMA_TO_DEVICE);
3587
3588 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3589 rp->mark_pending--;
3590
3591 tb->skb = NULL;
3592 do {
3593 idx = NEXT_TX(rp, idx);
3594 len -= MAX_TX_DESC_LEN;
3595 } while (len > 0);
3596
3597 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3598 tb = &rp->tx_buffs[idx];
3599 BUG_ON(tb->skb != NULL);
3600 np->ops->unmap_page(np->device, tb->mapping,
3601 skb_shinfo(skb)->frags[i].size,
3602 DMA_TO_DEVICE);
3603 idx = NEXT_TX(rp, idx);
3604 }
3605
3606 dev_kfree_skb(skb);
3607
3608 return idx;
3609}
3610
3611#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3612
3613static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3614{
b4c21639 3615 struct netdev_queue *txq;
a3138df9 3616 u16 pkt_cnt, tmp;
b4c21639 3617 int cons, index;
a3138df9
DM		 3618 u64 cs;
3619
b4c21639
DM		 3620 index = (rp - np->tx_rings);
3621 txq = netdev_get_tx_queue(np->dev, index);
3622
a3138df9
DM		 3623 cs = rp->tx_cs;
3624 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3625 goto out;
3626
3627 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3628 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3629 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3630
3631 rp->last_pkt_cnt = tmp;
3632
3633 cons = rp->cons;
3634
f10a1f2e
JP		 3635 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3636 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3637
3638 while (pkt_cnt--)
3639 cons = release_tx_packet(np, rp, cons);
3640
3641 rp->cons = cons;
3642 smp_mb();
3643
3644out:
b4c21639 3645 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3646 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3647 __netif_tx_lock(txq, smp_processor_id());
3648 if (netif_tx_queue_stopped(txq) &&
a3138df9 3649 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3650 netif_tx_wake_queue(txq);
3651 __netif_tx_unlock(txq);
a3138df9
DM		 3652 }
3653}
3654
b8a606b8
JDB		 3655static inline void niu_sync_rx_discard_stats(struct niu *np,
3656 struct rx_ring_info *rp,
3657 const int limit)
3658{
3659 /* This elaborate scheme is needed for reading the RX discard
3660 * counters, as they are only 16-bit and can overflow quickly,
3661 * and because the overflow indication bit is not usable as
3662 * the counter value does not wrap, but remains at max value
3663 * 0xFFFF.
3664 *
3665 * In theory and in practice counters can be lost in between
3666 * reading nr64() and clearing the counter nw64(). For this
3667 * reason, the number of counter clearings nw64() is
3668 * limited/reduced though the limit parameter.
3669 */
3670 int rx_channel = rp->rx_channel;
3671 u32 misc, wred;
3672
3673 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3674 * following discard events: IPP (Input Port Process),
3675 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3676 * Block Ring) prefetch buffer is empty.
3677 */
3678 misc = nr64(RXMISC(rx_channel));
3679 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3680 nw64(RXMISC(rx_channel), 0);
3681 rp->rx_errors += misc & RXMISC_COUNT;
3682
3683 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3684 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3685 rx_channel);
d231776f 3686
f10a1f2e
JP		 3687 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3688 "rx-%d: MISC drop=%u over=%u\n",
3689 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3690 }
3691
3692 /* WRED (Weighted Random Early Discard) by hardware */
3693 wred = nr64(RED_DIS_CNT(rx_channel));
3694 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3695 nw64(RED_DIS_CNT(rx_channel), 0);
3696 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3697
3698 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3699 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3700
f10a1f2e
JP		 3701 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3702 "rx-%d: WRED drop=%u over=%u\n",
3703 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3704 }
3705}
3706
4099e012
DM		 3707static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3708 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3709{
3710 int qlen, rcr_done = 0, work_done = 0;
3711 struct rxdma_mailbox *mbox = rp->mbox;
3712 u64 stat;
3713
3714#if 1
3715 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3716 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3717#else
3718 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3719 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3720#endif
3721 mbox->rx_dma_ctl_stat = 0;
3722 mbox->rcrstat_a = 0;
3723
f10a1f2e
JP		 3724 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3725 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3726 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3727
3728 rcr_done = work_done = 0;
3729 qlen = min(qlen, budget);
3730 while (work_done < qlen) {
4099e012 3731 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3732 work_done++;
3733 }
3734
3735 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3736 unsigned int i;
3737
3738 for (i = 0; i < rp->rbr_refill_pending; i++)
3739 niu_rbr_refill(np, rp, GFP_ATOMIC);
3740 rp->rbr_refill_pending = 0;
3741 }
3742
3743 stat = (RX_DMA_CTL_STAT_MEX |
3744 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3745 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3746
3747 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3748
e98def1f
JDB		 3749 /* Only sync discards stats when qlen indicate potential for drops */
3750 if (qlen > 10)
3751 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3752
a3138df9
DM		 3753 return work_done;
3754}
3755
3756static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3757{
3758 u64 v0 = lp->v0;
3759 u32 tx_vec = (v0 >> 32);
3760 u32 rx_vec = (v0 & 0xffffffff);
3761 int i, work_done = 0;
3762
f10a1f2e
JP		 3763 netif_printk(np, intr, KERN_DEBUG, np->dev,
3764 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3765
3766 for (i = 0; i < np->num_tx_rings; i++) {
3767 struct tx_ring_info *rp = &np->tx_rings[i];
3768 if (tx_vec & (1 << rp->tx_channel))
3769 niu_tx_work(np, rp);
3770 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3771 }
3772
3773 for (i = 0; i < np->num_rx_rings; i++) {
3774 struct rx_ring_info *rp = &np->rx_rings[i];
3775
3776 if (rx_vec & (1 << rp->rx_channel)) {
3777 int this_work_done;
3778
4099e012 3779 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3780 budget);
3781
3782 budget -= this_work_done;
3783 work_done += this_work_done;
3784 }
3785 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3786 }
3787
3788 return work_done;
3789}
3790
3791static int niu_poll(struct napi_struct *napi, int budget)
3792{
3793 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3794 struct niu *np = lp->np;
3795 int work_done;
3796
3797 work_done = niu_poll_core(np, lp, budget);
3798
3799 if (work_done < budget) {
288379f0 3800 napi_complete(napi);
a3138df9
DM		 3801 niu_ldg_rearm(np, lp, 1);
3802 }
3803 return work_done;
3804}
3805
3806static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3807 u64 stat)
3808{
f10a1f2e 3809 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3810
3811 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3812 pr_cont("RBR_TMOUT ");
a3138df9 3813 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3814 pr_cont("RSP_CNT ");
a3138df9 3815 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3816 pr_cont("BYTE_EN_BUS ");
a3138df9 3817 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3818 pr_cont("RSP_DAT ");
a3138df9 3819 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3820 pr_cont("RCR_ACK ");
a3138df9 3821 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3822 pr_cont("RCR_SHA_PAR ");
a3138df9 3823 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3824 pr_cont("RBR_PRE_PAR ");
a3138df9 3825 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3826 pr_cont("CONFIG ");
a3138df9 3827 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3828 pr_cont("RCRINCON ");
a3138df9 3829 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3830 pr_cont("RCRFULL ");
a3138df9 3831 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3832 pr_cont("RBRFULL ");
a3138df9 3833 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3834 pr_cont("RBRLOGPAGE ");
a3138df9 3835 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3836 pr_cont("CFIGLOGPAGE ");
a3138df9 3837 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3838 pr_cont("DC_FIDO ");
a3138df9 3839
f10a1f2e 3840 pr_cont(")\n");
a3138df9
DM		 3841}
3842
3843static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3844{
3845 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3846 int err = 0;
3847
a3138df9
DM		 3848
3849 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3850 RX_DMA_CTL_STAT_PORT_FATAL))
3851 err = -EINVAL;
3852
406f353c 3853 if (err) {
f10a1f2e
JP		 3854 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3855 rp->rx_channel,
3856 (unsigned long long) stat);
406f353c
MW		 3857
3858 niu_log_rxchan_errors(np, rp, stat);
3859 }
3860
a3138df9
DM		 3861 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3862 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3863
3864 return err;
3865}
3866
3867static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3868 u64 cs)
3869{
f10a1f2e 3870 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3871
3872 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3873 pr_cont("MBOX ");
a3138df9 3874 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3875 pr_cont("PKT_SIZE ");
a3138df9 3876 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3877 pr_cont("TX_RING_OFLOW ");
a3138df9 3878 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3879 pr_cont("PREF_BUF_PAR ");
a3138df9 3880 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3881 pr_cont("NACK_PREF ");
a3138df9 3882 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3883 pr_cont("NACK_PKT_RD ");
a3138df9 3884 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3885 pr_cont("CONF_PART ");
a3138df9 3886 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3887 pr_cont("PKT_PTR ");
a3138df9 3888
f10a1f2e 3889 pr_cont(")\n");
a3138df9
DM		 3890}
3891
3892static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3893{
3894 u64 cs, logh, logl;
3895
3896 cs = nr64(TX_CS(rp->tx_channel));
3897 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3898 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3899
f10a1f2e
JP		 3900 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3901 rp->tx_channel,
3902 (unsigned long long)cs,
3903 (unsigned long long)logh,
3904 (unsigned long long)logl);
a3138df9
DM		 3905
3906 niu_log_txchan_errors(np, rp, cs);
3907
3908 return -ENODEV;
3909}
3910
3911static int niu_mif_interrupt(struct niu *np)
3912{
3913 u64 mif_status = nr64(MIF_STATUS);
3914 int phy_mdint = 0;
3915
3916 if (np->flags & NIU_FLAGS_XMAC) {
3917 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3918
3919 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3920 phy_mdint = 1;
3921 }
3922
f10a1f2e
JP		 3923 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3924 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3925
3926 return -ENODEV;
3927}
3928
3929static void niu_xmac_interrupt(struct niu *np)
3930{
3931 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3932 u64 val;
3933
3934 val = nr64_mac(XTXMAC_STATUS);
3935 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3936 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3937 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3938 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3939 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3940 mp->tx_fifo_errors++;
3941 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3942 mp->tx_overflow_errors++;
3943 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3944 mp->tx_max_pkt_size_errors++;
3945 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3946 mp->tx_underflow_errors++;
3947
3948 val = nr64_mac(XRXMAC_STATUS);
3949 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3950 mp->rx_local_faults++;
3951 if (val & XRXMAC_STATUS_RFLT_DET)
3952 mp->rx_remote_faults++;
3953 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3954 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3955 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3956 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3957 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3958 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3959 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3960 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3961 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3962 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3963 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3964 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3965 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3966 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3967 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3968 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3969 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3970 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3971 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3972 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3973 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3974 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3975 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3976 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3977 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3978 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3979 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3980 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3981 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3982 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3983 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3984 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3985 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3986 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3987 if (val & XRXMAC_STATUS_RXUFLOW)
3988 mp->rx_underflows++;
3989 if (val & XRXMAC_STATUS_RXOFLOW)
3990 mp->rx_overflows++;
3991
3992 val = nr64_mac(XMAC_FC_STAT);
3993 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3994 mp->pause_off_state++;
3995 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3996 mp->pause_on_state++;
3997 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3998 mp->pause_received++;
3999}
4000
4001static void niu_bmac_interrupt(struct niu *np)
4002{
4003 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4004 u64 val;
4005
4006 val = nr64_mac(BTXMAC_STATUS);
4007 if (val & BTXMAC_STATUS_UNDERRUN)
4008 mp->tx_underflow_errors++;
4009 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4010 mp->tx_max_pkt_size_errors++;
4011 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4012 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4013 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4014 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4015
4016 val = nr64_mac(BRXMAC_STATUS);
4017 if (val & BRXMAC_STATUS_OVERFLOW)
4018 mp->rx_overflows++;
4019 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4020 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4021 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4022 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4023 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4024 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4025 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4026 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4027
4028 val = nr64_mac(BMAC_CTRL_STATUS);
4029 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4030 mp->pause_off_state++;
4031 if (val & BMAC_CTRL_STATUS_PAUSE)
4032 mp->pause_on_state++;
4033 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4034 mp->pause_received++;
4035}
4036
4037static int niu_mac_interrupt(struct niu *np)
4038{
4039 if (np->flags & NIU_FLAGS_XMAC)
4040 niu_xmac_interrupt(np);
4041 else
4042 niu_bmac_interrupt(np);
4043
4044 return 0;
4045}
4046
4047static void niu_log_device_error(struct niu *np, u64 stat)
4048{
f10a1f2e 4049 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4050
4051 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4052 pr_cont("META2 ");
a3138df9 4053 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4054 pr_cont("META1 ");
a3138df9 4055 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4056 pr_cont("PEU ");
a3138df9 4057 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4058 pr_cont("TXC ");
a3138df9 4059 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4060 pr_cont("RDMC ");
a3138df9 4061 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4062 pr_cont("TDMC ");
a3138df9 4063 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4064 pr_cont("ZCP ");
a3138df9 4065 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4066 pr_cont("FFLP ");
a3138df9 4067 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4068 pr_cont("IPP ");
a3138df9 4069 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4070 pr_cont("MAC ");
a3138df9 4071 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4072 pr_cont("SMX ");
a3138df9 4073
f10a1f2e 4074 pr_cont(")\n");
a3138df9
DM		 4075}
4076
4077static int niu_device_error(struct niu *np)
4078{
4079 u64 stat = nr64(SYS_ERR_STAT);
4080
f10a1f2e
JP		 4081 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4082 (unsigned long long)stat);
a3138df9
DM		 4083
4084 niu_log_device_error(np, stat);
4085
4086 return -ENODEV;
4087}
4088
406f353c
MW		 4089static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4090 u64 v0, u64 v1, u64 v2)
a3138df9 4091{
406f353c 4092
a3138df9
DM		 4093 int i, err = 0;
4094
406f353c
MW		 4095 lp->v0 = v0;
4096 lp->v1 = v1;
4097 lp->v2 = v2;
4098
a3138df9
DM		 4099 if (v1 & 0x00000000ffffffffULL) {
4100 u32 rx_vec = (v1 & 0xffffffff);
4101
4102 for (i = 0; i < np->num_rx_rings; i++) {
4103 struct rx_ring_info *rp = &np->rx_rings[i];
4104
4105 if (rx_vec & (1 << rp->rx_channel)) {
4106 int r = niu_rx_error(np, rp);
406f353c 4107 if (r) {
a3138df9 4108 err = r;
406f353c
MW		 4109 } else {
4110 if (!v0)
4111 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4112 RX_DMA_CTL_STAT_MEX);
4113 }
a3138df9
DM		 4114 }
4115 }
4116 }
4117 if (v1 & 0x7fffffff00000000ULL) {
4118 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4119
4120 for (i = 0; i < np->num_tx_rings; i++) {
4121 struct tx_ring_info *rp = &np->tx_rings[i];
4122
4123 if (tx_vec & (1 << rp->tx_channel)) {
4124 int r = niu_tx_error(np, rp);
4125 if (r)
4126 err = r;
4127 }
4128 }
4129 }
4130 if ((v0 | v1) & 0x8000000000000000ULL) {
4131 int r = niu_mif_interrupt(np);
4132 if (r)
4133 err = r;
4134 }
4135 if (v2) {
4136 if (v2 & 0x01ef) {
4137 int r = niu_mac_interrupt(np);
4138 if (r)
4139 err = r;
4140 }
4141 if (v2 & 0x0210) {
4142 int r = niu_device_error(np);
4143 if (r)
4144 err = r;
4145 }
4146 }
4147
4148 if (err)
4149 niu_enable_interrupts(np, 0);
4150
406f353c 4151 return err;
a3138df9
DM		 4152}
4153
4154static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4155 int ldn)
4156{
4157 struct rxdma_mailbox *mbox = rp->mbox;
4158 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4159
4160 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4161 RX_DMA_CTL_STAT_RCRTO);
4162 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4163
f10a1f2e
JP		 4164 netif_printk(np, intr, KERN_DEBUG, np->dev,
4165 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4166}
4167
4168static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4169 int ldn)
4170{
4171 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4172
f10a1f2e
JP		 4173 netif_printk(np, intr, KERN_DEBUG, np->dev,
4174 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4175}
4176
4177static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4178{
4179 struct niu_parent *parent = np->parent;
4180 u32 rx_vec, tx_vec;
4181 int i;
4182
4183 tx_vec = (v0 >> 32);
4184 rx_vec = (v0 & 0xffffffff);
4185
4186 for (i = 0; i < np->num_rx_rings; i++) {
4187 struct rx_ring_info *rp = &np->rx_rings[i];
4188 int ldn = LDN_RXDMA(rp->rx_channel);
4189
4190 if (parent->ldg_map[ldn] != ldg)
4191 continue;
4192
4193 nw64(LD_IM0(ldn), LD_IM0_MASK);
4194 if (rx_vec & (1 << rp->rx_channel))
4195 niu_rxchan_intr(np, rp, ldn);
4196 }
4197
4198 for (i = 0; i < np->num_tx_rings; i++) {
4199 struct tx_ring_info *rp = &np->tx_rings[i];
4200 int ldn = LDN_TXDMA(rp->tx_channel);
4201
4202 if (parent->ldg_map[ldn] != ldg)
4203 continue;
4204
4205 nw64(LD_IM0(ldn), LD_IM0_MASK);
4206 if (tx_vec & (1 << rp->tx_channel))
4207 niu_txchan_intr(np, rp, ldn);
4208 }
4209}
4210
4211static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4212 u64 v0, u64 v1, u64 v2)
4213{
288379f0 4214 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4215 lp->v0 = v0;
4216 lp->v1 = v1;
4217 lp->v2 = v2;
4218 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4219 __napi_schedule(&lp->napi);
a3138df9
DM		 4220 }
4221}
4222
4223static irqreturn_t niu_interrupt(int irq, void *dev_id)
4224{
4225 struct niu_ldg *lp = dev_id;
4226 struct niu *np = lp->np;
4227 int ldg = lp->ldg_num;
4228 unsigned long flags;
4229 u64 v0, v1, v2;
4230
4231 if (netif_msg_intr(np))
f10a1f2e
JP		 4232 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4233 __func__, lp, ldg);
a3138df9
DM		 4234
4235 spin_lock_irqsave(&np->lock, flags);
4236
4237 v0 = nr64(LDSV0(ldg));
4238 v1 = nr64(LDSV1(ldg));
4239 v2 = nr64(LDSV2(ldg));
4240
4241 if (netif_msg_intr(np))
02b1bae5 4242 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4243 (unsigned long long) v0,
4244 (unsigned long long) v1,
4245 (unsigned long long) v2);
4246
4247 if (unlikely(!v0 && !v1 && !v2)) {
4248 spin_unlock_irqrestore(&np->lock, flags);
4249 return IRQ_NONE;
4250 }
4251
4252 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4253 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4254 if (err)
4255 goto out;
4256 }
4257 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4258 niu_schedule_napi(np, lp, v0, v1, v2);
4259 else
4260 niu_ldg_rearm(np, lp, 1);
4261out:
4262 spin_unlock_irqrestore(&np->lock, flags);
4263
4264 return IRQ_HANDLED;
4265}
4266
4267static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4268{
4269 if (rp->mbox) {
4270 np->ops->free_coherent(np->device,
4271 sizeof(struct rxdma_mailbox),
4272 rp->mbox, rp->mbox_dma);
4273 rp->mbox = NULL;
4274 }
4275 if (rp->rcr) {
4276 np->ops->free_coherent(np->device,
4277 MAX_RCR_RING_SIZE * sizeof(__le64),
4278 rp->rcr, rp->rcr_dma);
4279 rp->rcr = NULL;
4280 rp->rcr_table_size = 0;
4281 rp->rcr_index = 0;
4282 }
4283 if (rp->rbr) {
4284 niu_rbr_free(np, rp);
4285
4286 np->ops->free_coherent(np->device,
4287 MAX_RBR_RING_SIZE * sizeof(__le32),
4288 rp->rbr, rp->rbr_dma);
4289 rp->rbr = NULL;
4290 rp->rbr_table_size = 0;
4291 rp->rbr_index = 0;
4292 }
4293 kfree(rp->rxhash);
4294 rp->rxhash = NULL;
4295}
4296
4297static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4298{
4299 if (rp->mbox) {
4300 np->ops->free_coherent(np->device,
4301 sizeof(struct txdma_mailbox),
4302 rp->mbox, rp->mbox_dma);
4303 rp->mbox = NULL;
4304 }
4305 if (rp->descr) {
4306 int i;
4307
4308 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4309 if (rp->tx_buffs[i].skb)
4310 (void) release_tx_packet(np, rp, i);
4311 }
4312
4313 np->ops->free_coherent(np->device,
4314 MAX_TX_RING_SIZE * sizeof(__le64),
4315 rp->descr, rp->descr_dma);
4316 rp->descr = NULL;
4317 rp->pending = 0;
4318 rp->prod = 0;
4319 rp->cons = 0;
4320 rp->wrap_bit = 0;
4321 }
4322}
4323
4324static void niu_free_channels(struct niu *np)
4325{
4326 int i;
4327
4328 if (np->rx_rings) {
4329 for (i = 0; i < np->num_rx_rings; i++) {
4330 struct rx_ring_info *rp = &np->rx_rings[i];
4331
4332 niu_free_rx_ring_info(np, rp);
4333 }
4334 kfree(np->rx_rings);
4335 np->rx_rings = NULL;
4336 np->num_rx_rings = 0;
4337 }
4338
4339 if (np->tx_rings) {
4340 for (i = 0; i < np->num_tx_rings; i++) {
4341 struct tx_ring_info *rp = &np->tx_rings[i];
4342
4343 niu_free_tx_ring_info(np, rp);
4344 }
4345 kfree(np->tx_rings);
4346 np->tx_rings = NULL;
4347 np->num_tx_rings = 0;
4348 }
4349}
4350
4351static int niu_alloc_rx_ring_info(struct niu *np,
4352 struct rx_ring_info *rp)
4353{
4354 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4355
4356 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4357 GFP_KERNEL);
4358 if (!rp->rxhash)
4359 return -ENOMEM;
4360
4361 rp->mbox = np->ops->alloc_coherent(np->device,
4362 sizeof(struct rxdma_mailbox),
4363 &rp->mbox_dma, GFP_KERNEL);
4364 if (!rp->mbox)
4365 return -ENOMEM;
4366 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4367 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4368 rp->mbox);
a3138df9
DM		 4369 return -EINVAL;
4370 }
4371
4372 rp->rcr = np->ops->alloc_coherent(np->device,
4373 MAX_RCR_RING_SIZE * sizeof(__le64),
4374 &rp->rcr_dma, GFP_KERNEL);
4375 if (!rp->rcr)
4376 return -ENOMEM;
4377 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4378 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4379 rp->rcr);
a3138df9
DM		 4380 return -EINVAL;
4381 }
4382 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4383 rp->rcr_index = 0;
4384
4385 rp->rbr = np->ops->alloc_coherent(np->device,
4386 MAX_RBR_RING_SIZE * sizeof(__le32),
4387 &rp->rbr_dma, GFP_KERNEL);
4388 if (!rp->rbr)
4389 return -ENOMEM;
4390 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4391 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4392 rp->rbr);
a3138df9
DM		 4393 return -EINVAL;
4394 }
4395 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4396 rp->rbr_index = 0;
4397 rp->rbr_pending = 0;
4398
4399 return 0;
4400}
4401
4402static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4403{
4404 int mtu = np->dev->mtu;
4405
4406 /* These values are recommended by the HW designers for fair
4407 * utilization of DRR amongst the rings.
4408 */
4409 rp->max_burst = mtu + 32;
4410 if (rp->max_burst > 4096)
4411 rp->max_burst = 4096;
4412}
4413
4414static int niu_alloc_tx_ring_info(struct niu *np,
4415 struct tx_ring_info *rp)
4416{
4417 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4418
4419 rp->mbox = np->ops->alloc_coherent(np->device,
4420 sizeof(struct txdma_mailbox),
4421 &rp->mbox_dma, GFP_KERNEL);
4422 if (!rp->mbox)
4423 return -ENOMEM;
4424 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4425 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4426 rp->mbox);
a3138df9
DM		 4427 return -EINVAL;
4428 }
4429
4430 rp->descr = np->ops->alloc_coherent(np->device,
4431 MAX_TX_RING_SIZE * sizeof(__le64),
4432 &rp->descr_dma, GFP_KERNEL);
4433 if (!rp->descr)
4434 return -ENOMEM;
4435 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4436 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4437 rp->descr);
a3138df9
DM		 4438 return -EINVAL;
4439 }
4440
4441 rp->pending = MAX_TX_RING_SIZE;
4442 rp->prod = 0;
4443 rp->cons = 0;
4444 rp->wrap_bit = 0;
4445
4446 /* XXX make these configurable... XXX */
4447 rp->mark_freq = rp->pending / 4;
4448
4449 niu_set_max_burst(np, rp);
4450
4451 return 0;
4452}
4453
4454static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4455{
81429973 4456 u16 bss;
a3138df9 4457
81429973 4458 bss = min(PAGE_SHIFT, 15);
a3138df9 4459
81429973
OJ		 4460 rp->rbr_block_size = 1 << bss;
4461 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4462
4463 rp->rbr_sizes[0] = 256;
4464 rp->rbr_sizes[1] = 1024;
4465 if (np->dev->mtu > ETH_DATA_LEN) {
4466 switch (PAGE_SIZE) {
4467 case 4 * 1024:
4468 rp->rbr_sizes[2] = 4096;
4469 break;
4470
4471 default:
4472 rp->rbr_sizes[2] = 8192;
4473 break;
4474 }
4475 } else {
4476 rp->rbr_sizes[2] = 2048;
4477 }
4478 rp->rbr_sizes[3] = rp->rbr_block_size;
4479}
4480
4481static int niu_alloc_channels(struct niu *np)
4482{
4483 struct niu_parent *parent = np->parent;
4484 int first_rx_channel, first_tx_channel;
9690c636
DM		 4485 int num_rx_rings, num_tx_rings;
4486 struct rx_ring_info *rx_rings;
4487 struct tx_ring_info *tx_rings;
a3138df9
DM		 4488 int i, port, err;
4489
4490 port = np->port;
4491 first_rx_channel = first_tx_channel = 0;
4492 for (i = 0; i < port; i++) {
4493 first_rx_channel += parent->rxchan_per_port[i];
4494 first_tx_channel += parent->txchan_per_port[i];
4495 }
4496
9690c636
DM		 4497 num_rx_rings = parent->rxchan_per_port[port];
4498 num_tx_rings = parent->txchan_per_port[port];
a3138df9 4499
9690c636
DM		 4500 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4501 GFP_KERNEL);
a3138df9 4502 err = -ENOMEM;
9690c636 4503 if (!rx_rings)
a3138df9
DM		 4504 goto out_err;
4505
9690c636
DM		 4506 np->num_rx_rings = num_rx_rings;
4507 smp_wmb();
4508 np->rx_rings = rx_rings;
4509
4510 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4511
a3138df9
DM		 4512 for (i = 0; i < np->num_rx_rings; i++) {
4513 struct rx_ring_info *rp = &np->rx_rings[i];
4514
4515 rp->np = np;
4516 rp->rx_channel = first_rx_channel + i;
4517
4518 err = niu_alloc_rx_ring_info(np, rp);
4519 if (err)
4520 goto out_err;
4521
4522 niu_size_rbr(np, rp);
4523
4524 /* XXX better defaults, configurable, etc... XXX */
4525 rp->nonsyn_window = 64;
4526 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4527 rp->syn_window = 64;
4528 rp->syn_threshold = rp->rcr_table_size - 64;
4529 rp->rcr_pkt_threshold = 16;
4530 rp->rcr_timeout = 8;
4531 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4532 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4533 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4534
4535 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4536 if (err)
4537 return err;
4538 }
4539
9690c636
DM		 4540 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4541 GFP_KERNEL);
a3138df9 4542 err = -ENOMEM;
9690c636 4543 if (!tx_rings)
a3138df9
DM		 4544 goto out_err;
4545
9690c636
DM		 4546 np->num_tx_rings = num_tx_rings;
4547 smp_wmb();
4548 np->tx_rings = tx_rings;
4549
4550 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4551
a3138df9
DM		 4552 for (i = 0; i < np->num_tx_rings; i++) {
4553 struct tx_ring_info *rp = &np->tx_rings[i];
4554
4555 rp->np = np;
4556 rp->tx_channel = first_tx_channel + i;
4557
4558 err = niu_alloc_tx_ring_info(np, rp);
4559 if (err)
4560 goto out_err;
4561 }
4562
4563 return 0;
4564
4565out_err:
4566 niu_free_channels(np);
4567 return err;
4568}
4569
4570static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4571{
4572 int limit = 1000;
4573
4574 while (--limit > 0) {
4575 u64 val = nr64(TX_CS(channel));
4576 if (val & TX_CS_SNG_STATE)
4577 return 0;
4578 }
4579 return -ENODEV;
4580}
4581
4582static int niu_tx_channel_stop(struct niu *np, int channel)
4583{
4584 u64 val = nr64(TX_CS(channel));
4585
4586 val |= TX_CS_STOP_N_GO;
4587 nw64(TX_CS(channel), val);
4588
4589 return niu_tx_cs_sng_poll(np, channel);
4590}
4591
4592static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4593{
4594 int limit = 1000;
4595
4596 while (--limit > 0) {
4597 u64 val = nr64(TX_CS(channel));
4598 if (!(val & TX_CS_RST))
4599 return 0;
4600 }
4601 return -ENODEV;
4602}
4603
4604static int niu_tx_channel_reset(struct niu *np, int channel)
4605{
4606 u64 val = nr64(TX_CS(channel));
4607 int err;
4608
4609 val |= TX_CS_RST;
4610 nw64(TX_CS(channel), val);
4611
4612 err = niu_tx_cs_reset_poll(np, channel);
4613 if (!err)
4614 nw64(TX_RING_KICK(channel), 0);
4615
4616 return err;
4617}
4618
4619static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4620{
4621 u64 val;
4622
4623 nw64(TX_LOG_MASK1(channel), 0);
4624 nw64(TX_LOG_VAL1(channel), 0);
4625 nw64(TX_LOG_MASK2(channel), 0);
4626 nw64(TX_LOG_VAL2(channel), 0);
4627 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4628 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4629 nw64(TX_LOG_PAGE_HDL(channel), 0);
4630
4631 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4632 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4633 nw64(TX_LOG_PAGE_VLD(channel), val);
4634
4635 /* XXX TXDMA 32bit mode? XXX */
4636
4637 return 0;
4638}
4639
4640static void niu_txc_enable_port(struct niu *np, int on)
4641{
4642 unsigned long flags;
4643 u64 val, mask;
4644
4645 niu_lock_parent(np, flags);
4646 val = nr64(TXC_CONTROL);
4647 mask = (u64)1 << np->port;
4648 if (on) {
4649 val |= TXC_CONTROL_ENABLE | mask;
4650 } else {
4651 val &= ~mask;
4652 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4653 val &= ~TXC_CONTROL_ENABLE;
4654 }
4655 nw64(TXC_CONTROL, val);
4656 niu_unlock_parent(np, flags);
4657}
4658
4659static void niu_txc_set_imask(struct niu *np, u64 imask)
4660{
4661 unsigned long flags;
4662 u64 val;
4663
4664 niu_lock_parent(np, flags);
4665 val = nr64(TXC_INT_MASK);
4666 val &= ~TXC_INT_MASK_VAL(np->port);
4667 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4668 niu_unlock_parent(np, flags);
4669}
4670
4671static void niu_txc_port_dma_enable(struct niu *np, int on)
4672{
4673 u64 val = 0;
4674
4675 if (on) {
4676 int i;
4677
4678 for (i = 0; i < np->num_tx_rings; i++)
4679 val |= (1 << np->tx_rings[i].tx_channel);
4680 }
4681 nw64(TXC_PORT_DMA(np->port), val);
4682}
4683
4684static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4685{
4686 int err, channel = rp->tx_channel;
4687 u64 val, ring_len;
4688
4689 err = niu_tx_channel_stop(np, channel);
4690 if (err)
4691 return err;
4692
4693 err = niu_tx_channel_reset(np, channel);
4694 if (err)
4695 return err;
4696
4697 err = niu_tx_channel_lpage_init(np, channel);
4698 if (err)
4699 return err;
4700
4701 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4702 nw64(TX_ENT_MSK(channel), 0);
4703
4704 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4705 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4706 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4707 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4708 return -EINVAL;
4709 }
4710
4711 /* The length field in TX_RNG_CFIG is measured in 64-byte
4712 * blocks. rp->pending is the number of TX descriptors in
4713 * our ring, 8 bytes each, thus we divide by 8 bytes more
4714 * to get the proper value the chip wants.
4715 */
4716 ring_len = (rp->pending / 8);
4717
4718 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4719 rp->descr_dma);
4720 nw64(TX_RNG_CFIG(channel), val);
4721
4722 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4723 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4724 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4725 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4726 return -EINVAL;
4727 }
4728 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4729 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4730
4731 nw64(TX_CS(channel), 0);
4732
4733 rp->last_pkt_cnt = 0;
4734
4735 return 0;
4736}
4737
4738static void niu_init_rdc_groups(struct niu *np)
4739{
4740 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4741 int i, first_table_num = tp->first_table_num;
4742
4743 for (i = 0; i < tp->num_tables; i++) {
4744 struct rdc_table *tbl = &tp->tables[i];
4745 int this_table = first_table_num + i;
4746 int slot;
4747
4748 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4749 nw64(RDC_TBL(this_table, slot),
4750 tbl->rxdma_channel[slot]);
4751 }
4752
4753 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4754}
4755
4756static void niu_init_drr_weight(struct niu *np)
4757{
4758 int type = phy_decode(np->parent->port_phy, np->port);
4759 u64 val;
4760
4761 switch (type) {
4762 case PORT_TYPE_10G:
4763 val = PT_DRR_WEIGHT_DEFAULT_10G;
4764 break;
4765
4766 case PORT_TYPE_1G:
4767 default:
4768 val = PT_DRR_WEIGHT_DEFAULT_1G;
4769 break;
4770 }
4771 nw64(PT_DRR_WT(np->port), val);
4772}
4773
4774static int niu_init_hostinfo(struct niu *np)
4775{
4776 struct niu_parent *parent = np->parent;
4777 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4778 int i, err, num_alt = niu_num_alt_addr(np);
4779 int first_rdc_table = tp->first_table_num;
4780
4781 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4782 if (err)
4783 return err;
4784
4785 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4786 if (err)
4787 return err;
4788
4789 for (i = 0; i < num_alt; i++) {
4790 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4791 if (err)
4792 return err;
4793 }
4794
4795 return 0;
4796}
4797
4798static int niu_rx_channel_reset(struct niu *np, int channel)
4799{
4800 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4801 RXDMA_CFIG1_RST, 1000, 10,
4802 "RXDMA_CFIG1");
4803}
4804
4805static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4806{
4807 u64 val;
4808
4809 nw64(RX_LOG_MASK1(channel), 0);
4810 nw64(RX_LOG_VAL1(channel), 0);
4811 nw64(RX_LOG_MASK2(channel), 0);
4812 nw64(RX_LOG_VAL2(channel), 0);
4813 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4814 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4815 nw64(RX_LOG_PAGE_HDL(channel), 0);
4816
4817 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4818 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4819 nw64(RX_LOG_PAGE_VLD(channel), val);
4820
4821 return 0;
4822}
4823
4824static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4825{
4826 u64 val;
4827
4828 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4829 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4830 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4831 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4832 nw64(RDC_RED_PARA(rp->rx_channel), val);
4833}
4834
4835static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4836{
4837 u64 val = 0;
4838
efb6c736 4839 *ret = 0;
a3138df9
DM		 4840 switch (rp->rbr_block_size) {
4841 case 4 * 1024:
4842 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4843 break;
4844 case 8 * 1024:
4845 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4846 break;
4847 case 16 * 1024:
4848 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4849 break;
4850 case 32 * 1024:
4851 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4852 break;
4853 default:
4854 return -EINVAL;
4855 }
4856 val |= RBR_CFIG_B_VLD2;
4857 switch (rp->rbr_sizes[2]) {
4858 case 2 * 1024:
4859 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4860 break;
4861 case 4 * 1024:
4862 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4863 break;
4864 case 8 * 1024:
4865 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4866 break;
4867 case 16 * 1024:
4868 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4869 break;
4870
4871 default:
4872 return -EINVAL;
4873 }
4874 val |= RBR_CFIG_B_VLD1;
4875 switch (rp->rbr_sizes[1]) {
4876 case 1 * 1024:
4877 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4878 break;
4879 case 2 * 1024:
4880 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4881 break;
4882 case 4 * 1024:
4883 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4884 break;
4885 case 8 * 1024:
4886 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4887 break;
4888
4889 default:
4890 return -EINVAL;
4891 }
4892 val |= RBR_CFIG_B_VLD0;
4893 switch (rp->rbr_sizes[0]) {
4894 case 256:
4895 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4896 break;
4897 case 512:
4898 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4899 break;
4900 case 1 * 1024:
4901 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4902 break;
4903 case 2 * 1024:
4904 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4905 break;
4906
4907 default:
4908 return -EINVAL;
4909 }
4910
4911 *ret = val;
4912 return 0;
4913}
4914
4915static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4916{
4917 u64 val = nr64(RXDMA_CFIG1(channel));
4918 int limit;
4919
4920 if (on)
4921 val |= RXDMA_CFIG1_EN;
4922 else
4923 val &= ~RXDMA_CFIG1_EN;
4924 nw64(RXDMA_CFIG1(channel), val);
4925
4926 limit = 1000;
4927 while (--limit > 0) {
4928 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4929 break;
4930 udelay(10);
4931 }
4932 if (limit <= 0)
4933 return -ENODEV;
4934 return 0;
4935}
4936
4937static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4938{
4939 int err, channel = rp->rx_channel;
4940 u64 val;
4941
4942 err = niu_rx_channel_reset(np, channel);
4943 if (err)
4944 return err;
4945
4946 err = niu_rx_channel_lpage_init(np, channel);
4947 if (err)
4948 return err;
4949
4950 niu_rx_channel_wred_init(np, rp);
4951
4952 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4953 nw64(RX_DMA_CTL_STAT(channel),
4954 (RX_DMA_CTL_STAT_MEX |
4955 RX_DMA_CTL_STAT_RCRTHRES |
4956 RX_DMA_CTL_STAT_RCRTO |
4957 RX_DMA_CTL_STAT_RBR_EMPTY));
4958 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3cfa856d
DM		 4959 nw64(RXDMA_CFIG2(channel),
4960 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4961 RXDMA_CFIG2_FULL_HDR));
a3138df9
DM		 4962 nw64(RBR_CFIG_A(channel),
4963 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4964 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4965 err = niu_compute_rbr_cfig_b(rp, &val);
4966 if (err)
4967 return err;
4968 nw64(RBR_CFIG_B(channel), val);
4969 nw64(RCRCFIG_A(channel),
4970 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4971 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4972 nw64(RCRCFIG_B(channel),
4973 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4974 RCRCFIG_B_ENTOUT |
4975 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4976
4977 err = niu_enable_rx_channel(np, channel, 1);
4978 if (err)
4979 return err;
4980
4981 nw64(RBR_KICK(channel), rp->rbr_index);
4982
4983 val = nr64(RX_DMA_CTL_STAT(channel));
4984 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4985 nw64(RX_DMA_CTL_STAT(channel), val);
4986
4987 return 0;
4988}
4989
4990static int niu_init_rx_channels(struct niu *np)
4991{
4992 unsigned long flags;
4993 u64 seed = jiffies_64;
4994 int err, i;
4995
4996 niu_lock_parent(np, flags);
4997 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4998 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4999 niu_unlock_parent(np, flags);
5000
5001 /* XXX RXDMA 32bit mode? XXX */
5002
5003 niu_init_rdc_groups(np);
5004 niu_init_drr_weight(np);
5005
5006 err = niu_init_hostinfo(np);
5007 if (err)
5008 return err;
5009
5010 for (i = 0; i < np->num_rx_rings; i++) {
5011 struct rx_ring_info *rp = &np->rx_rings[i];
5012
5013 err = niu_init_one_rx_channel(np, rp);
5014 if (err)
5015 return err;
5016 }
5017
5018 return 0;
5019}
5020
5021static int niu_set_ip_frag_rule(struct niu *np)
5022{
5023 struct niu_parent *parent = np->parent;
5024 struct niu_classifier *cp = &np->clas;
5025 struct niu_tcam_entry *tp;
5026 int index, err;
5027
2d96cf8c 5028 index = cp->tcam_top;
a3138df9
DM		 5029 tp = &parent->tcam[index];
5030
5031 /* Note that the noport bit is the same in both ipv4 and
5032 * ipv6 format TCAM entries.
5033 */
5034 memset(tp, 0, sizeof(*tp));
5035 tp->key[1] = TCAM_V4KEY1_NOPORT;
5036 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5037 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5038 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5039 err = tcam_write(np, index, tp->key, tp->key_mask);
5040 if (err)
5041 return err;
5042 err = tcam_assoc_write(np, index, tp->assoc_data);
5043 if (err)
5044 return err;
2d96cf8c
SB		 5045 tp->valid = 1;
5046 cp->tcam_valid_entries++;
a3138df9
DM		 5047
5048 return 0;
5049}
5050
5051static int niu_init_classifier_hw(struct niu *np)
5052{
5053 struct niu_parent *parent = np->parent;
5054 struct niu_classifier *cp = &np->clas;
5055 int i, err;
5056
5057 nw64(H1POLY, cp->h1_init);
5058 nw64(H2POLY, cp->h2_init);
5059
5060 err = niu_init_hostinfo(np);
5061 if (err)
5062 return err;
5063
5064 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5065 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5066
5067 vlan_tbl_write(np, i, np->port,
5068 vp->vlan_pref, vp->rdc_num);
5069 }
5070
5071 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5072 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5073
5074 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5075 ap->rdc_num, ap->mac_pref);
5076 if (err)
5077 return err;
5078 }
5079
5080 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5081 int index = i - CLASS_CODE_USER_PROG1;
5082
5083 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5084 if (err)
5085 return err;
5086 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5087 if (err)
5088 return err;
5089 }
5090
5091 err = niu_set_ip_frag_rule(np);
5092 if (err)
5093 return err;
5094
5095 tcam_enable(np, 1);
5096
5097 return 0;
5098}
5099
5100static int niu_zcp_write(struct niu *np, int index, u64 *data)
5101{
5102 nw64(ZCP_RAM_DATA0, data[0]);
5103 nw64(ZCP_RAM_DATA1, data[1]);
5104 nw64(ZCP_RAM_DATA2, data[2]);
5105 nw64(ZCP_RAM_DATA3, data[3]);
5106 nw64(ZCP_RAM_DATA4, data[4]);
5107 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5108 nw64(ZCP_RAM_ACC,
5109 (ZCP_RAM_ACC_WRITE |
5110 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5111 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5112
5113 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5114 1000, 100);
5115}
5116
5117static int niu_zcp_read(struct niu *np, int index, u64 *data)
5118{
5119 int err;
5120
5121 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5122 1000, 100);
5123 if (err) {
f10a1f2e
JP		 5124 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5125 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5126 return err;
5127 }
5128
5129 nw64(ZCP_RAM_ACC,
5130 (ZCP_RAM_ACC_READ |
5131 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5132 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5133
5134 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5135 1000, 100);
5136 if (err) {
f10a1f2e
JP		 5137 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5138 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5139 return err;
5140 }
5141
5142 data[0] = nr64(ZCP_RAM_DATA0);
5143 data[1] = nr64(ZCP_RAM_DATA1);
5144 data[2] = nr64(ZCP_RAM_DATA2);
5145 data[3] = nr64(ZCP_RAM_DATA3);
5146 data[4] = nr64(ZCP_RAM_DATA4);
5147
5148 return 0;
5149}
5150
5151static void niu_zcp_cfifo_reset(struct niu *np)
5152{
5153 u64 val = nr64(RESET_CFIFO);
5154
5155 val |= RESET_CFIFO_RST(np->port);
5156 nw64(RESET_CFIFO, val);
5157 udelay(10);
5158
5159 val &= ~RESET_CFIFO_RST(np->port);
5160 nw64(RESET_CFIFO, val);
5161}
5162
5163static int niu_init_zcp(struct niu *np)
5164{
5165 u64 data[5], rbuf[5];
5166 int i, max, err;
5167
5168 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5169 if (np->port == 0 || np->port == 1)
5170 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5171 else
5172 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5173 } else
5174 max = NIU_CFIFO_ENTRIES;
5175
5176 data[0] = 0;
5177 data[1] = 0;
5178 data[2] = 0;
5179 data[3] = 0;
5180 data[4] = 0;
5181
5182 for (i = 0; i < max; i++) {
5183 err = niu_zcp_write(np, i, data);
5184 if (err)
5185 return err;
5186 err = niu_zcp_read(np, i, rbuf);
5187 if (err)
5188 return err;
5189 }
5190
5191 niu_zcp_cfifo_reset(np);
5192 nw64(CFIFO_ECC(np->port), 0);
5193 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5194 (void) nr64(ZCP_INT_STAT);
5195 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5196
5197 return 0;
5198}
5199
5200static void niu_ipp_write(struct niu *np, int index, u64 *data)
5201{
5202 u64 val = nr64_ipp(IPP_CFIG);
5203
5204 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5205 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5206 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5207 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5208 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5209 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5210 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5211 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5212}
5213
5214static void niu_ipp_read(struct niu *np, int index, u64 *data)
5215{
5216 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5217 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5218 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5219 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5220 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5221 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5222}
5223
5224static int niu_ipp_reset(struct niu *np)
5225{
5226 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5227 1000, 100, "IPP_CFIG");
5228}
5229
5230static int niu_init_ipp(struct niu *np)
5231{
5232 u64 data[5], rbuf[5], val;
5233 int i, max, err;
5234
5235 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5236 if (np->port == 0 || np->port == 1)
5237 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5238 else
5239 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5240 } else
5241 max = NIU_DFIFO_ENTRIES;
5242
5243 data[0] = 0;
5244 data[1] = 0;
5245 data[2] = 0;
5246 data[3] = 0;
5247 data[4] = 0;
5248
5249 for (i = 0; i < max; i++) {
5250 niu_ipp_write(np, i, data);
5251 niu_ipp_read(np, i, rbuf);
5252 }
5253
5254 (void) nr64_ipp(IPP_INT_STAT);
5255 (void) nr64_ipp(IPP_INT_STAT);
5256
5257 err = niu_ipp_reset(np);
5258 if (err)
5259 return err;
5260
5261 (void) nr64_ipp(IPP_PKT_DIS);
5262 (void) nr64_ipp(IPP_BAD_CS_CNT);
5263 (void) nr64_ipp(IPP_ECC);
5264
5265 (void) nr64_ipp(IPP_INT_STAT);
5266
5267 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5268
5269 val = nr64_ipp(IPP_CFIG);
5270 val &= ~IPP_CFIG_IP_MAX_PKT;
5271 val |= (IPP_CFIG_IPP_ENABLE |
5272 IPP_CFIG_DFIFO_ECC_EN |
5273 IPP_CFIG_DROP_BAD_CRC |
5274 IPP_CFIG_CKSUM_EN |
5275 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5276 nw64_ipp(IPP_CFIG, val);
5277
5278 return 0;
5279}
5280
0c3b091b 5281static void niu_handle_led(struct niu *np, int status)
a3138df9 5282{
a3138df9 5283 u64 val;
a3138df9
DM		 5284 val = nr64_mac(XMAC_CONFIG);
5285
5286 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5287 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5288 if (status) {
a3138df9
DM		 5289 val |= XMAC_CONFIG_LED_POLARITY;
5290 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5291 } else {
5292 val |= XMAC_CONFIG_FORCE_LED_ON;
5293 val &= ~XMAC_CONFIG_LED_POLARITY;
5294 }
5295 }
5296
0c3b091b
ML		 5297 nw64_mac(XMAC_CONFIG, val);
5298}
5299
5300static void niu_init_xif_xmac(struct niu *np)
5301{
5302 struct niu_link_config *lp = &np->link_config;
5303 u64 val;
5304
5fbd7e24
MW		 5305 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5306 val = nr64(MIF_CONFIG);
5307 val |= MIF_CONFIG_ATCA_GE;
5308 nw64(MIF_CONFIG, val);
5309 }
5310
0c3b091b 5311 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5312 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5313
5314 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5315
5316 if (lp->loopback_mode == LOOPBACK_MAC) {
5317 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5318 val |= XMAC_CONFIG_LOOPBACK;
5319 } else {
5320 val &= ~XMAC_CONFIG_LOOPBACK;
5321 }
5322
5323 if (np->flags & NIU_FLAGS_10G) {
5324 val &= ~XMAC_CONFIG_LFS_DISABLE;
5325 } else {
5326 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5327 if (!(np->flags & NIU_FLAGS_FIBER) &&
5328 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5329 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5330 else
5331 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5332 }
5333
5334 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5335
5336 if (lp->active_speed == SPEED_100)
5337 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5338 else
5339 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5340
5341 nw64_mac(XMAC_CONFIG, val);
5342
5343 val = nr64_mac(XMAC_CONFIG);
5344 val &= ~XMAC_CONFIG_MODE_MASK;
5345 if (np->flags & NIU_FLAGS_10G) {
5346 val |= XMAC_CONFIG_MODE_XGMII;
5347 } else {
38bb045d 5348 if (lp->active_speed == SPEED_1000)
a3138df9 5349 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5350 else
5351 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5352 }
5353
5354 nw64_mac(XMAC_CONFIG, val);
5355}
5356
5357static void niu_init_xif_bmac(struct niu *np)
5358{
5359 struct niu_link_config *lp = &np->link_config;
5360 u64 val;
5361
5362 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5363
5364 if (lp->loopback_mode == LOOPBACK_MAC)
5365 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5366 else
5367 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5368
5369 if (lp->active_speed == SPEED_1000)
5370 val |= BMAC_XIF_CONFIG_GMII_MODE;
5371 else
5372 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5373
5374 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5375 BMAC_XIF_CONFIG_LED_POLARITY);
5376
5377 if (!(np->flags & NIU_FLAGS_10G) &&
5378 !(np->flags & NIU_FLAGS_FIBER) &&
5379 lp->active_speed == SPEED_100)
5380 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5381 else
5382 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5383
5384 nw64_mac(BMAC_XIF_CONFIG, val);
5385}
5386
5387static void niu_init_xif(struct niu *np)
5388{
5389 if (np->flags & NIU_FLAGS_XMAC)
5390 niu_init_xif_xmac(np);
5391 else
5392 niu_init_xif_bmac(np);
5393}
5394
5395static void niu_pcs_mii_reset(struct niu *np)
5396{
5fbd7e24 5397 int limit = 1000;
a3138df9
DM		 5398 u64 val = nr64_pcs(PCS_MII_CTL);
5399 val |= PCS_MII_CTL_RST;
5400 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5401 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5402 udelay(100);
5403 val = nr64_pcs(PCS_MII_CTL);
5404 }
a3138df9
DM		 5405}
5406
5407static void niu_xpcs_reset(struct niu *np)
5408{
5fbd7e24 5409 int limit = 1000;
a3138df9
DM		 5410 u64 val = nr64_xpcs(XPCS_CONTROL1);
5411 val |= XPCS_CONTROL1_RESET;
5412 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5413 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5414 udelay(100);
5415 val = nr64_xpcs(XPCS_CONTROL1);
5416 }
a3138df9
DM		 5417}
5418
5419static int niu_init_pcs(struct niu *np)
5420{
5421 struct niu_link_config *lp = &np->link_config;
5422 u64 val;
5423
5fbd7e24
MW		 5424 switch (np->flags & (NIU_FLAGS_10G |
5425 NIU_FLAGS_FIBER |
5426 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5427 case NIU_FLAGS_FIBER:
5428 /* 1G fiber */
5429 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5430 nw64_pcs(PCS_DPATH_MODE, 0);
5431 niu_pcs_mii_reset(np);
5432 break;
5433
5434 case NIU_FLAGS_10G:
5435 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5436 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5437 /* 10G SERDES */
a3138df9
DM		 5438 if (!(np->flags & NIU_FLAGS_XMAC))
5439 return -EINVAL;
5440
5441 /* 10G copper or fiber */
5442 val = nr64_mac(XMAC_CONFIG);
5443 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5444 nw64_mac(XMAC_CONFIG, val);
5445
5446 niu_xpcs_reset(np);
5447
5448 val = nr64_xpcs(XPCS_CONTROL1);
5449 if (lp->loopback_mode == LOOPBACK_PHY)
5450 val |= XPCS_CONTROL1_LOOPBACK;
5451 else
5452 val &= ~XPCS_CONTROL1_LOOPBACK;
5453 nw64_xpcs(XPCS_CONTROL1, val);
5454
5455 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5456 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5457 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5458 break;
5459
5fbd7e24
MW		 5460
5461 case NIU_FLAGS_XCVR_SERDES:
5462 /* 1G SERDES */
5463 niu_pcs_mii_reset(np);
5464 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5465 nw64_pcs(PCS_DPATH_MODE, 0);
5466 break;
5467
a3138df9
DM		 5468 case 0:
5469 /* 1G copper */
5fbd7e24
MW		 5470 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5471 /* 1G RGMII FIBER */
a3138df9
DM		 5472 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5473 niu_pcs_mii_reset(np);
5474 break;
5475
5476 default:
5477 return -EINVAL;
5478 }
5479
5480 return 0;
5481}
5482
5483static int niu_reset_tx_xmac(struct niu *np)
5484{
5485 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5486 (XTXMAC_SW_RST_REG_RS |
5487 XTXMAC_SW_RST_SOFT_RST),
5488 1000, 100, "XTXMAC_SW_RST");
5489}
5490
5491static int niu_reset_tx_bmac(struct niu *np)
5492{
5493 int limit;
5494
5495 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5496 limit = 1000;
5497 while (--limit >= 0) {
5498 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5499 break;
5500 udelay(100);
5501 }
5502 if (limit < 0) {
f10a1f2e 5503 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5504 np->port,
5505 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5506 return -ENODEV;
5507 }
5508
5509 return 0;
5510}
5511
5512static int niu_reset_tx_mac(struct niu *np)
5513{
5514 if (np->flags & NIU_FLAGS_XMAC)
5515 return niu_reset_tx_xmac(np);
5516 else
5517 return niu_reset_tx_bmac(np);
5518}
5519
5520static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5521{
5522 u64 val;
5523
5524 val = nr64_mac(XMAC_MIN);
5525 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5526 XMAC_MIN_RX_MIN_PKT_SIZE);
5527 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5528 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5529 nw64_mac(XMAC_MIN, val);
5530
5531 nw64_mac(XMAC_MAX, max);
5532
5533 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5534
5535 val = nr64_mac(XMAC_IPG);
5536 if (np->flags & NIU_FLAGS_10G) {
5537 val &= ~XMAC_IPG_IPG_XGMII;
5538 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5539 } else {
5540 val &= ~XMAC_IPG_IPG_MII_GMII;
5541 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5542 }
5543 nw64_mac(XMAC_IPG, val);
5544
5545 val = nr64_mac(XMAC_CONFIG);
5546 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5547 XMAC_CONFIG_STRETCH_MODE |
5548 XMAC_CONFIG_VAR_MIN_IPG_EN |
5549 XMAC_CONFIG_TX_ENABLE);
5550 nw64_mac(XMAC_CONFIG, val);
5551
5552 nw64_mac(TXMAC_FRM_CNT, 0);
5553 nw64_mac(TXMAC_BYTE_CNT, 0);
5554}
5555
5556static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5557{
5558 u64 val;
5559
5560 nw64_mac(BMAC_MIN_FRAME, min);
5561 nw64_mac(BMAC_MAX_FRAME, max);
5562
5563 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5564 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5565 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5566
5567 val = nr64_mac(BTXMAC_CONFIG);
5568 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5569 BTXMAC_CONFIG_ENABLE);
5570 nw64_mac(BTXMAC_CONFIG, val);
5571}
5572
5573static void niu_init_tx_mac(struct niu *np)
5574{
5575 u64 min, max;
5576
5577 min = 64;
5578 if (np->dev->mtu > ETH_DATA_LEN)
5579 max = 9216;
5580 else
5581 max = 1522;
5582
5583 /* The XMAC_MIN register only accepts values for TX min which
5584 * have the low 3 bits cleared.
5585 */
8c87df45 5586 BUG_ON(min & 0x7);
a3138df9
DM		 5587
5588 if (np->flags & NIU_FLAGS_XMAC)
5589 niu_init_tx_xmac(np, min, max);
5590 else
5591 niu_init_tx_bmac(np, min, max);
5592}
5593
5594static int niu_reset_rx_xmac(struct niu *np)
5595{
5596 int limit;
5597
5598 nw64_mac(XRXMAC_SW_RST,
5599 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5600 limit = 1000;
5601 while (--limit >= 0) {
5602 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5603 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5604 break;
a3138df9
DM		 5605 udelay(100);
5606 }
5607 if (limit < 0) {
f10a1f2e 5608 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5609 np->port,
5610 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5611 return -ENODEV;
5612 }
5613
5614 return 0;
5615}
5616
5617static int niu_reset_rx_bmac(struct niu *np)
5618{
5619 int limit;
5620
5621 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5622 limit = 1000;
5623 while (--limit >= 0) {
5624 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5625 break;
5626 udelay(100);
5627 }
5628 if (limit < 0) {
f10a1f2e 5629 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5630 np->port,
5631 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5632 return -ENODEV;
5633 }
5634
5635 return 0;
5636}
5637
5638static int niu_reset_rx_mac(struct niu *np)
5639{
5640 if (np->flags & NIU_FLAGS_XMAC)
5641 return niu_reset_rx_xmac(np);
5642 else
5643 return niu_reset_rx_bmac(np);
5644}
5645
5646static void niu_init_rx_xmac(struct niu *np)
5647{
5648 struct niu_parent *parent = np->parent;
5649 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5650 int first_rdc_table = tp->first_table_num;
5651 unsigned long i;
5652 u64 val;
5653
5654 nw64_mac(XMAC_ADD_FILT0, 0);
5655 nw64_mac(XMAC_ADD_FILT1, 0);
5656 nw64_mac(XMAC_ADD_FILT2, 0);
5657 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5658 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5659 for (i = 0; i < MAC_NUM_HASH; i++)
5660 nw64_mac(XMAC_HASH_TBL(i), 0);
5661 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5662 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5663 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5664
5665 val = nr64_mac(XMAC_CONFIG);
5666 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5667 XMAC_CONFIG_PROMISCUOUS |
5668 XMAC_CONFIG_PROMISC_GROUP |
5669 XMAC_CONFIG_ERR_CHK_DIS |
5670 XMAC_CONFIG_RX_CRC_CHK_DIS |
5671 XMAC_CONFIG_RESERVED_MULTICAST |
5672 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5673 XMAC_CONFIG_ADDR_FILTER_EN |
5674 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5675 XMAC_CONFIG_STRIP_CRC |
5676 XMAC_CONFIG_PASS_FLOW_CTRL |
5677 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5678 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5679 nw64_mac(XMAC_CONFIG, val);
5680
5681 nw64_mac(RXMAC_BT_CNT, 0);
5682 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5683 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5684 nw64_mac(RXMAC_FRAG_CNT, 0);
5685 nw64_mac(RXMAC_HIST_CNT1, 0);
5686 nw64_mac(RXMAC_HIST_CNT2, 0);
5687 nw64_mac(RXMAC_HIST_CNT3, 0);
5688 nw64_mac(RXMAC_HIST_CNT4, 0);
5689 nw64_mac(RXMAC_HIST_CNT5, 0);
5690 nw64_mac(RXMAC_HIST_CNT6, 0);
5691 nw64_mac(RXMAC_HIST_CNT7, 0);
5692 nw64_mac(RXMAC_MPSZER_CNT, 0);
5693 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5694 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5695 nw64_mac(LINK_FAULT_CNT, 0);
5696}
5697
5698static void niu_init_rx_bmac(struct niu *np)
5699{
5700 struct niu_parent *parent = np->parent;
5701 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5702 int first_rdc_table = tp->first_table_num;
5703 unsigned long i;
5704 u64 val;
5705
5706 nw64_mac(BMAC_ADD_FILT0, 0);
5707 nw64_mac(BMAC_ADD_FILT1, 0);
5708 nw64_mac(BMAC_ADD_FILT2, 0);
5709 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5710 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5711 for (i = 0; i < MAC_NUM_HASH; i++)
5712 nw64_mac(BMAC_HASH_TBL(i), 0);
5713 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5714 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5715 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5716
5717 val = nr64_mac(BRXMAC_CONFIG);
5718 val &= ~(BRXMAC_CONFIG_ENABLE |
5719 BRXMAC_CONFIG_STRIP_PAD |
5720 BRXMAC_CONFIG_STRIP_FCS |
5721 BRXMAC_CONFIG_PROMISC |
5722 BRXMAC_CONFIG_PROMISC_GRP |
5723 BRXMAC_CONFIG_ADDR_FILT_EN |
5724 BRXMAC_CONFIG_DISCARD_DIS);
5725 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5726 nw64_mac(BRXMAC_CONFIG, val);
5727
5728 val = nr64_mac(BMAC_ADDR_CMPEN);
5729 val |= BMAC_ADDR_CMPEN_EN0;
5730 nw64_mac(BMAC_ADDR_CMPEN, val);
5731}
5732
5733static void niu_init_rx_mac(struct niu *np)
5734{
5735 niu_set_primary_mac(np, np->dev->dev_addr);
5736
5737 if (np->flags & NIU_FLAGS_XMAC)
5738 niu_init_rx_xmac(np);
5739 else
5740 niu_init_rx_bmac(np);
5741}
5742
5743static void niu_enable_tx_xmac(struct niu *np, int on)
5744{
5745 u64 val = nr64_mac(XMAC_CONFIG);
5746
5747 if (on)
5748 val |= XMAC_CONFIG_TX_ENABLE;
5749 else
5750 val &= ~XMAC_CONFIG_TX_ENABLE;
5751 nw64_mac(XMAC_CONFIG, val);
5752}
5753
5754static void niu_enable_tx_bmac(struct niu *np, int on)
5755{
5756 u64 val = nr64_mac(BTXMAC_CONFIG);
5757
5758 if (on)
5759 val |= BTXMAC_CONFIG_ENABLE;
5760 else
5761 val &= ~BTXMAC_CONFIG_ENABLE;
5762 nw64_mac(BTXMAC_CONFIG, val);
5763}
5764
5765static void niu_enable_tx_mac(struct niu *np, int on)
5766{
5767 if (np->flags & NIU_FLAGS_XMAC)
5768 niu_enable_tx_xmac(np, on);
5769 else
5770 niu_enable_tx_bmac(np, on);
5771}
5772
5773static void niu_enable_rx_xmac(struct niu *np, int on)
5774{
5775 u64 val = nr64_mac(XMAC_CONFIG);
5776
5777 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5778 XMAC_CONFIG_PROMISCUOUS);
5779
5780 if (np->flags & NIU_FLAGS_MCAST)
5781 val |= XMAC_CONFIG_HASH_FILTER_EN;
5782 if (np->flags & NIU_FLAGS_PROMISC)
5783 val |= XMAC_CONFIG_PROMISCUOUS;
5784
5785 if (on)
5786 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5787 else
5788 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5789 nw64_mac(XMAC_CONFIG, val);
5790}
5791
5792static void niu_enable_rx_bmac(struct niu *np, int on)
5793{
5794 u64 val = nr64_mac(BRXMAC_CONFIG);
5795
5796 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5797 BRXMAC_CONFIG_PROMISC);
5798
5799 if (np->flags & NIU_FLAGS_MCAST)
5800 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5801 if (np->flags & NIU_FLAGS_PROMISC)
5802 val |= BRXMAC_CONFIG_PROMISC;
5803
5804 if (on)
5805 val |= BRXMAC_CONFIG_ENABLE;
5806 else
5807 val &= ~BRXMAC_CONFIG_ENABLE;
5808 nw64_mac(BRXMAC_CONFIG, val);
5809}
5810
5811static void niu_enable_rx_mac(struct niu *np, int on)
5812{
5813 if (np->flags & NIU_FLAGS_XMAC)
5814 niu_enable_rx_xmac(np, on);
5815 else
5816 niu_enable_rx_bmac(np, on);
5817}
5818
5819static int niu_init_mac(struct niu *np)
5820{
5821 int err;
5822
5823 niu_init_xif(np);
5824 err = niu_init_pcs(np);
5825 if (err)
5826 return err;
5827
5828 err = niu_reset_tx_mac(np);
5829 if (err)
5830 return err;
5831 niu_init_tx_mac(np);
5832 err = niu_reset_rx_mac(np);
5833 if (err)
5834 return err;
5835 niu_init_rx_mac(np);
5836
5837 /* This looks hookey but the RX MAC reset we just did will
5838 * undo some of the state we setup in niu_init_tx_mac() so we
5839 * have to call it again. In particular, the RX MAC reset will
5840 * set the XMAC_MAX register back to it's default value.
5841 */
5842 niu_init_tx_mac(np);
5843 niu_enable_tx_mac(np, 1);
5844
5845 niu_enable_rx_mac(np, 1);
5846
5847 return 0;
5848}
5849
5850static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5851{
5852 (void) niu_tx_channel_stop(np, rp->tx_channel);
5853}
5854
5855static void niu_stop_tx_channels(struct niu *np)
5856{
5857 int i;
5858
5859 for (i = 0; i < np->num_tx_rings; i++) {
5860 struct tx_ring_info *rp = &np->tx_rings[i];
5861
5862 niu_stop_one_tx_channel(np, rp);
5863 }
5864}
5865
5866static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5867{
5868 (void) niu_tx_channel_reset(np, rp->tx_channel);
5869}
5870
5871static void niu_reset_tx_channels(struct niu *np)
5872{
5873 int i;
5874
5875 for (i = 0; i < np->num_tx_rings; i++) {
5876 struct tx_ring_info *rp = &np->tx_rings[i];
5877
5878 niu_reset_one_tx_channel(np, rp);
5879 }
5880}
5881
5882static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5883{
5884 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5885}
5886
5887static void niu_stop_rx_channels(struct niu *np)
5888{
5889 int i;
5890
5891 for (i = 0; i < np->num_rx_rings; i++) {
5892 struct rx_ring_info *rp = &np->rx_rings[i];
5893
5894 niu_stop_one_rx_channel(np, rp);
5895 }
5896}
5897
5898static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5899{
5900 int channel = rp->rx_channel;
5901
5902 (void) niu_rx_channel_reset(np, channel);
5903 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5904 nw64(RX_DMA_CTL_STAT(channel), 0);
5905 (void) niu_enable_rx_channel(np, channel, 0);
5906}
5907
5908static void niu_reset_rx_channels(struct niu *np)
5909{
5910 int i;
5911
5912 for (i = 0; i < np->num_rx_rings; i++) {
5913 struct rx_ring_info *rp = &np->rx_rings[i];
5914
5915 niu_reset_one_rx_channel(np, rp);
5916 }
5917}
5918
5919static void niu_disable_ipp(struct niu *np)
5920{
5921 u64 rd, wr, val;
5922 int limit;
5923
5924 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5925 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5926 limit = 100;
5927 while (--limit >= 0 && (rd != wr)) {
5928 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5929 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5930 }
5931 if (limit < 0 &&
5932 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5933 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5934 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5935 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5936 }
5937
5938 val = nr64_ipp(IPP_CFIG);
5939 val &= ~(IPP_CFIG_IPP_ENABLE |
5940 IPP_CFIG_DFIFO_ECC_EN |
5941 IPP_CFIG_DROP_BAD_CRC |
5942 IPP_CFIG_CKSUM_EN);
5943 nw64_ipp(IPP_CFIG, val);
5944
5945 (void) niu_ipp_reset(np);
5946}
5947
5948static int niu_init_hw(struct niu *np)
5949{
5950 int i, err;
5951
f10a1f2e 5952 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5953 niu_txc_enable_port(np, 1);
5954 niu_txc_port_dma_enable(np, 1);
5955 niu_txc_set_imask(np, 0);
5956
f10a1f2e 5957 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5958 for (i = 0; i < np->num_tx_rings; i++) {
5959 struct tx_ring_info *rp = &np->tx_rings[i];
5960
5961 err = niu_init_one_tx_channel(np, rp);
5962 if (err)
5963 return err;
5964 }
5965
f10a1f2e 5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5967 err = niu_init_rx_channels(np);
5968 if (err)
5969 goto out_uninit_tx_channels;
5970
f10a1f2e 5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5972 err = niu_init_classifier_hw(np);
5973 if (err)
5974 goto out_uninit_rx_channels;
5975
f10a1f2e 5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5977 err = niu_init_zcp(np);
5978 if (err)
5979 goto out_uninit_rx_channels;
5980
f10a1f2e 5981 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5982 err = niu_init_ipp(np);
5983 if (err)
5984 goto out_uninit_rx_channels;
5985
f10a1f2e 5986 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5987 err = niu_init_mac(np);
5988 if (err)
5989 goto out_uninit_ipp;
5990
5991 return 0;
5992
5993out_uninit_ipp:
f10a1f2e 5994 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5995 niu_disable_ipp(np);
5996
5997out_uninit_rx_channels:
f10a1f2e 5998 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 5999 niu_stop_rx_channels(np);
6000 niu_reset_rx_channels(np);
6001
6002out_uninit_tx_channels:
f10a1f2e 6003 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 6004 niu_stop_tx_channels(np);
6005 niu_reset_tx_channels(np);
6006
6007 return err;
6008}
6009
6010static void niu_stop_hw(struct niu *np)
6011{
f10a1f2e 6012 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6013 niu_enable_interrupts(np, 0);
6014
f10a1f2e 6015 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6016 niu_enable_rx_mac(np, 0);
6017
f10a1f2e 6018 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6019 niu_disable_ipp(np);
6020
f10a1f2e 6021 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6022 niu_stop_tx_channels(np);
6023
f10a1f2e 6024 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6025 niu_stop_rx_channels(np);
6026
f10a1f2e 6027 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6028 niu_reset_tx_channels(np);
6029
f10a1f2e 6030 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6031 niu_reset_rx_channels(np);
6032}
6033
70340d72
RO		 6034static void niu_set_irq_name(struct niu *np)
6035{
6036 int port = np->port;
6037 int i, j = 1;
6038
6039 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6040
6041 if (port == 0) {
6042 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6043 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6044 j = 3;
6045 }
6046
6047 for (i = 0; i < np->num_ldg - j; i++) {
6048 if (i < np->num_rx_rings)
6049 sprintf(np->irq_name[i+j], "%s-rx-%d",
6050 np->dev->name, i);
6051 else if (i < np->num_tx_rings + np->num_rx_rings)
6052 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6053 i - np->num_rx_rings);
6054 }
6055}
6056
a3138df9
DM		 6057static int niu_request_irq(struct niu *np)
6058{
6059 int i, j, err;
6060
70340d72
RO		 6061 niu_set_irq_name(np);
6062
a3138df9
DM		 6063 err = 0;
6064 for (i = 0; i < np->num_ldg; i++) {
6065 struct niu_ldg *lp = &np->ldg[i];
6066
ab392d2d 6067 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
70340d72 6068 np->irq_name[i], lp);
a3138df9
DM		 6069 if (err)
6070 goto out_free_irqs;
6071
6072 }
6073
6074 return 0;
6075
6076out_free_irqs:
6077 for (j = 0; j < i; j++) {
6078 struct niu_ldg *lp = &np->ldg[j];
6079
6080 free_irq(lp->irq, lp);
6081 }
6082 return err;
6083}
6084
6085static void niu_free_irq(struct niu *np)
6086{
6087 int i;
6088
6089 for (i = 0; i < np->num_ldg; i++) {
6090 struct niu_ldg *lp = &np->ldg[i];
6091
6092 free_irq(lp->irq, lp);
6093 }
6094}
6095
6096static void niu_enable_napi(struct niu *np)
6097{
6098 int i;
6099
6100 for (i = 0; i < np->num_ldg; i++)
6101 napi_enable(&np->ldg[i].napi);
6102}
6103
6104static void niu_disable_napi(struct niu *np)
6105{
6106 int i;
6107
6108 for (i = 0; i < np->num_ldg; i++)
6109 napi_disable(&np->ldg[i].napi);
6110}
6111
6112static int niu_open(struct net_device *dev)
6113{
6114 struct niu *np = netdev_priv(dev);
6115 int err;
6116
6117 netif_carrier_off(dev);
6118
6119 err = niu_alloc_channels(np);
6120 if (err)
6121 goto out_err;
6122
6123 err = niu_enable_interrupts(np, 0);
6124 if (err)
6125 goto out_free_channels;
6126
6127 err = niu_request_irq(np);
6128 if (err)
6129 goto out_free_channels;
6130
6131 niu_enable_napi(np);
6132
6133 spin_lock_irq(&np->lock);
6134
6135 err = niu_init_hw(np);
6136 if (!err) {
6137 init_timer(&np->timer);
6138 np->timer.expires = jiffies + HZ;
6139 np->timer.data = (unsigned long) np;
6140 np->timer.function = niu_timer;
6141
6142 err = niu_enable_interrupts(np, 1);
6143 if (err)
6144 niu_stop_hw(np);
6145 }
6146
6147 spin_unlock_irq(&np->lock);
6148
6149 if (err) {
6150 niu_disable_napi(np);
6151 goto out_free_irq;
6152 }
6153
b4c21639 6154 netif_tx_start_all_queues(dev);
a3138df9
DM		 6155
6156 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6157 netif_carrier_on(dev);
6158
6159 add_timer(&np->timer);
6160
6161 return 0;
6162
6163out_free_irq:
6164 niu_free_irq(np);
6165
6166out_free_channels:
6167 niu_free_channels(np);
6168
6169out_err:
6170 return err;
6171}
6172
6173static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6174{
6175 cancel_work_sync(&np->reset_task);
6176
6177 niu_disable_napi(np);
b4c21639 6178 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6179
6180 del_timer_sync(&np->timer);
6181
6182 spin_lock_irq(&np->lock);
6183
6184 niu_stop_hw(np);
6185
6186 spin_unlock_irq(&np->lock);
6187}
6188
6189static int niu_close(struct net_device *dev)
6190{
6191 struct niu *np = netdev_priv(dev);
6192
6193 niu_full_shutdown(np, dev);
6194
6195 niu_free_irq(np);
6196
6197 niu_free_channels(np);
6198
0c3b091b
ML		 6199 niu_handle_led(np, 0);
6200
a3138df9
DM		 6201 return 0;
6202}
6203
6204static void niu_sync_xmac_stats(struct niu *np)
6205{
6206 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6207
6208 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6209 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6210
6211 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6212 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6213 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6214 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6215 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6216 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6217 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6218 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6219 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6220 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6221 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6222 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6223 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6224 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6225 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6226 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6227}
6228
6229static void niu_sync_bmac_stats(struct niu *np)
6230{
6231 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6232
6233 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6234 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6235
6236 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6237 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6238 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6239 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6240}
6241
6242static void niu_sync_mac_stats(struct niu *np)
6243{
6244 if (np->flags & NIU_FLAGS_XMAC)
6245 niu_sync_xmac_stats(np);
6246 else
6247 niu_sync_bmac_stats(np);
6248}
6249
1a7a1032 6250static void niu_get_rx_stats(struct niu *np,
6251 struct rtnl_link_stats64 *stats)
a3138df9 6252{
1a7a1032 6253 u64 pkts, dropped, errors, bytes;
9690c636 6254 struct rx_ring_info *rx_rings;
a3138df9
DM		 6255 int i;
6256
6257 pkts = dropped = errors = bytes = 0;
9690c636
DM		 6258
6259 rx_rings = ACCESS_ONCE(np->rx_rings);
6260 if (!rx_rings)
6261 goto no_rings;
6262
a3138df9 6263 for (i = 0; i < np->num_rx_rings; i++) {
9690c636 6264 struct rx_ring_info *rp = &rx_rings[i];
a3138df9 6265
b8a606b8
JDB		 6266 niu_sync_rx_discard_stats(np, rp, 0);
6267
a3138df9
DM		 6268 pkts += rp->rx_packets;
6269 bytes += rp->rx_bytes;
6270 dropped += rp->rx_dropped;
6271 errors += rp->rx_errors;
6272 }
9690c636
DM		 6273
6274no_rings:
1a7a1032 6275 stats->rx_packets = pkts;
6276 stats->rx_bytes = bytes;
6277 stats->rx_dropped = dropped;
6278 stats->rx_errors = errors;
a3138df9
DM		 6279}
6280
1a7a1032 6281static void niu_get_tx_stats(struct niu *np,
6282 struct rtnl_link_stats64 *stats)
a3138df9 6283{
1a7a1032 6284 u64 pkts, errors, bytes;
9690c636 6285 struct tx_ring_info *tx_rings;
a3138df9
DM		 6286 int i;
6287
6288 pkts = errors = bytes = 0;
9690c636
DM		 6289
6290 tx_rings = ACCESS_ONCE(np->tx_rings);
6291 if (!tx_rings)
6292 goto no_rings;
6293
a3138df9 6294 for (i = 0; i < np->num_tx_rings; i++) {
9690c636 6295 struct tx_ring_info *rp = &tx_rings[i];
a3138df9
DM		 6296
6297 pkts += rp->tx_packets;
6298 bytes += rp->tx_bytes;
6299 errors += rp->tx_errors;
6300 }
9690c636
DM		 6301
6302no_rings:
1a7a1032 6303 stats->tx_packets = pkts;
6304 stats->tx_bytes = bytes;
6305 stats->tx_errors = errors;
a3138df9
DM		 6306}
6307
1a7a1032 6308static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev,
6309 struct rtnl_link_stats64 *stats)
a3138df9
DM		 6310{
6311 struct niu *np = netdev_priv(dev);
6312
9690c636 6313 if (netif_running(dev)) {
1a7a1032 6314 niu_get_rx_stats(np, stats);
6315 niu_get_tx_stats(np, stats);
9690c636 6316 }
1a7a1032 6317
6318 return stats;
a3138df9
DM		 6319}
6320
6321static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6322{
6323 int i;
6324
6325 for (i = 0; i < 16; i++)
6326 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6327}
6328
6329static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6330{
6331 int i;
6332
6333 for (i = 0; i < 16; i++)
6334 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6335}
6336
6337static void niu_load_hash(struct niu *np, u16 *hash)
6338{
6339 if (np->flags & NIU_FLAGS_XMAC)
6340 niu_load_hash_xmac(np, hash);
6341 else
6342 niu_load_hash_bmac(np, hash);
6343}
6344
6345static void niu_set_rx_mode(struct net_device *dev)
6346{
6347 struct niu *np = netdev_priv(dev);
6348 int i, alt_cnt, err;
ccffad25 6349 struct netdev_hw_addr *ha;
a3138df9
DM		 6350 unsigned long flags;
6351 u16 hash[16] = { 0, };
6352
6353 spin_lock_irqsave(&np->lock, flags);
6354 niu_enable_rx_mac(np, 0);
6355
6356 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6357 if (dev->flags & IFF_PROMISC)
6358 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6359 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6360 np->flags |= NIU_FLAGS_MCAST;
6361
32e7bfc4 6362 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6363 if (alt_cnt > niu_num_alt_addr(np)) {
6364 alt_cnt = 0;
6365 np->flags |= NIU_FLAGS_PROMISC;
6366 }
6367
6368 if (alt_cnt) {
6369 int index = 0;
6370
32e7bfc4 6371 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6372 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6373 if (err)
f10a1f2e
JP		 6374 netdev_warn(dev, "Error %d adding alt mac %d\n",
6375 err, index);
a3138df9
DM		 6376 err = niu_enable_alt_mac(np, index, 1);
6377 if (err)
f10a1f2e
JP		 6378 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6379 err, index);
a3138df9
DM		 6380
6381 index++;
6382 }
6383 } else {
3b5bcede
MW		 6384 int alt_start;
6385 if (np->flags & NIU_FLAGS_XMAC)
6386 alt_start = 0;
6387 else
6388 alt_start = 1;
6389 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6390 err = niu_enable_alt_mac(np, i, 0);
6391 if (err)
f10a1f2e
JP		 6392 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6393 err, i);
a3138df9
DM		 6394 }
6395 }
6396 if (dev->flags & IFF_ALLMULTI) {
6397 for (i = 0; i < 16; i++)
6398 hash[i] = 0xffff;
4cd24eaf 6399 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6400 netdev_for_each_mc_addr(ha, dev) {
6401 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6402
6403 crc >>= 24;
6404 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6405 }
6406 }
6407
6408 if (np->flags & NIU_FLAGS_MCAST)
6409 niu_load_hash(np, hash);
6410
6411 niu_enable_rx_mac(np, 1);
6412 spin_unlock_irqrestore(&np->lock, flags);
6413}
6414
6415static int niu_set_mac_addr(struct net_device *dev, void *p)
6416{
6417 struct niu *np = netdev_priv(dev);
6418 struct sockaddr *addr = p;
6419 unsigned long flags;
6420
6421 if (!is_valid_ether_addr(addr->sa_data))
6422 return -EINVAL;
6423
6424 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6425
6426 if (!netif_running(dev))
6427 return 0;
6428
6429 spin_lock_irqsave(&np->lock, flags);
6430 niu_enable_rx_mac(np, 0);
6431 niu_set_primary_mac(np, dev->dev_addr);
6432 niu_enable_rx_mac(np, 1);
6433 spin_unlock_irqrestore(&np->lock, flags);
6434
6435 return 0;
6436}
6437
6438static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6439{
6440 return -EOPNOTSUPP;
6441}
6442
6443static void niu_netif_stop(struct niu *np)
6444{
6445 np->dev->trans_start = jiffies; /* prevent tx timeout */
6446
6447 niu_disable_napi(np);
6448
6449 netif_tx_disable(np->dev);
6450}
6451
6452static void niu_netif_start(struct niu *np)
6453{
6454 /* NOTE: unconditional netif_wake_queue is only appropriate
6455 * so long as all callers are assured to have free tx slots
6456 * (such as after niu_init_hw).
6457 */
b4c21639 6458 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6459
6460 niu_enable_napi(np);
6461
6462 niu_enable_interrupts(np, 1);
6463}
6464
cff502a3
SB		 6465static void niu_reset_buffers(struct niu *np)
6466{
6467 int i, j, k, err;
6468
6469 if (np->rx_rings) {
6470 for (i = 0; i < np->num_rx_rings; i++) {
6471 struct rx_ring_info *rp = &np->rx_rings[i];
6472
6473 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6474 struct page *page;
6475
6476 page = rp->rxhash[j];
6477 while (page) {
6478 struct page *next =
6479 (struct page *) page->mapping;
6480 u64 base = page->index;
6481 base = base >> RBR_DESCR_ADDR_SHIFT;
6482 rp->rbr[k++] = cpu_to_le32(base);
6483 page = next;
6484 }
6485 }
6486 for (; k < MAX_RBR_RING_SIZE; k++) {
6487 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6488 if (unlikely(err))
6489 break;
6490 }
6491
6492 rp->rbr_index = rp->rbr_table_size - 1;
6493 rp->rcr_index = 0;
6494 rp->rbr_pending = 0;
6495 rp->rbr_refill_pending = 0;
6496 }
6497 }
6498 if (np->tx_rings) {
6499 for (i = 0; i < np->num_tx_rings; i++) {
6500 struct tx_ring_info *rp = &np->tx_rings[i];
6501
6502 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6503 if (rp->tx_buffs[j].skb)
6504 (void) release_tx_packet(np, rp, j);
6505 }
6506
6507 rp->pending = MAX_TX_RING_SIZE;
6508 rp->prod = 0;
6509 rp->cons = 0;
6510 rp->wrap_bit = 0;
6511 }
6512 }
6513}
6514
a3138df9
DM		 6515static void niu_reset_task(struct work_struct *work)
6516{
6517 struct niu *np = container_of(work, struct niu, reset_task);
6518 unsigned long flags;
6519 int err;
6520
6521 spin_lock_irqsave(&np->lock, flags);
6522 if (!netif_running(np->dev)) {
6523 spin_unlock_irqrestore(&np->lock, flags);
6524 return;
6525 }
6526
6527 spin_unlock_irqrestore(&np->lock, flags);
6528
6529 del_timer_sync(&np->timer);
6530
6531 niu_netif_stop(np);
6532
6533 spin_lock_irqsave(&np->lock, flags);
6534
6535 niu_stop_hw(np);
6536
cff502a3
SB		 6537 spin_unlock_irqrestore(&np->lock, flags);
6538
6539 niu_reset_buffers(np);
6540
6541 spin_lock_irqsave(&np->lock, flags);
6542
a3138df9
DM		 6543 err = niu_init_hw(np);
6544 if (!err) {
6545 np->timer.expires = jiffies + HZ;
6546 add_timer(&np->timer);
6547 niu_netif_start(np);
6548 }
6549
6550 spin_unlock_irqrestore(&np->lock, flags);
6551}
6552
6553static void niu_tx_timeout(struct net_device *dev)
6554{
6555 struct niu *np = netdev_priv(dev);
6556
f10a1f2e 6557 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6558 dev->name);
6559
6560 schedule_work(&np->reset_task);
6561}
6562
6563static void niu_set_txd(struct tx_ring_info *rp, int index,
6564 u64 mapping, u64 len, u64 mark,
6565 u64 n_frags)
6566{
6567 __le64 *desc = &rp->descr[index];
6568
6569 *desc = cpu_to_le64(mark |
6570 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6571 (len << TX_DESC_TR_LEN_SHIFT) |
6572 (mapping & TX_DESC_SAD));
6573}
6574
6575static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6576 u64 pad_bytes, u64 len)
6577{
6578 u16 eth_proto, eth_proto_inner;
6579 u64 csum_bits, l3off, ihl, ret;
6580 u8 ip_proto;
6581 int ipv6;
6582
6583 eth_proto = be16_to_cpu(ehdr->h_proto);
6584 eth_proto_inner = eth_proto;
6585 if (eth_proto == ETH_P_8021Q) {
6586 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6587 __be16 val = vp->h_vlan_encapsulated_proto;
6588
6589 eth_proto_inner = be16_to_cpu(val);
6590 }
6591
6592 ipv6 = ihl = 0;
6593 switch (skb->protocol) {
09640e63 6594 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6595 ip_proto = ip_hdr(skb)->protocol;
6596 ihl = ip_hdr(skb)->ihl;
6597 break;
09640e63 6598 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6599 ip_proto = ipv6_hdr(skb)->nexthdr;
6600 ihl = (40 >> 2);
6601 ipv6 = 1;
6602 break;
6603 default:
6604 ip_proto = ihl = 0;
6605 break;
6606 }
6607
6608 csum_bits = TXHDR_CSUM_NONE;
6609 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6610 u64 start, stuff;
6611
6612 csum_bits = (ip_proto == IPPROTO_TCP ?
6613 TXHDR_CSUM_TCP :
6614 (ip_proto == IPPROTO_UDP ?
6615 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6616
0d0b1672 6617 start = skb_checksum_start_offset(skb) -
a3138df9
DM		 6618 (pad_bytes + sizeof(struct tx_pkt_hdr));
6619 stuff = start + skb->csum_offset;
6620
6621 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6622 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6623 }
6624
6625 l3off = skb_network_offset(skb) -
6626 (pad_bytes + sizeof(struct tx_pkt_hdr));
6627
6628 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6629 (len << TXHDR_LEN_SHIFT) |
6630 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6631 (ihl << TXHDR_IHL_SHIFT) |
6632 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6633 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6634 (ipv6 ? TXHDR_IP_VER : 0) |
6635 csum_bits);
6636
6637 return ret;
6638}
6639
61357325
SH		 6640static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6641 struct net_device *dev)
a3138df9
DM		 6642{
6643 struct niu *np = netdev_priv(dev);
6644 unsigned long align, headroom;
b4c21639 6645 struct netdev_queue *txq;
a3138df9
DM		 6646 struct tx_ring_info *rp;
6647 struct tx_pkt_hdr *tp;
6648 unsigned int len, nfg;
6649 struct ethhdr *ehdr;
6650 int prod, i, tlen;
6651 u64 mapping, mrk;
6652
b4c21639
DM		 6653 i = skb_get_queue_mapping(skb);
6654 rp = &np->tx_rings[i];
6655 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6656
6657 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6658 netif_tx_stop_queue(txq);
f10a1f2e 6659 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6660 rp->tx_errors++;
6661 return NETDEV_TX_BUSY;
6662 }
6663
6664 if (skb->len < ETH_ZLEN) {
6665 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6666
6667 if (skb_pad(skb, pad_bytes))
6668 goto out;
6669 skb_put(skb, pad_bytes);
6670 }
6671
6672 len = sizeof(struct tx_pkt_hdr) + 15;
6673 if (skb_headroom(skb) < len) {
6674 struct sk_buff *skb_new;
6675
6676 skb_new = skb_realloc_headroom(skb, len);
6677 if (!skb_new) {
6678 rp->tx_errors++;
6679 goto out_drop;
6680 }
6681 kfree_skb(skb);
6682 skb = skb_new;
3ebebccf
DM		 6683 } else
6684 skb_orphan(skb);
a3138df9
DM		 6685
6686 align = ((unsigned long) skb->data & (16 - 1));
6687 headroom = align + sizeof(struct tx_pkt_hdr);
6688
6689 ehdr = (struct ethhdr *) skb->data;
6690 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6691
6692 len = skb->len - sizeof(struct tx_pkt_hdr);
6693 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6694 tp->resv = 0;
6695
6696 len = skb_headlen(skb);
6697 mapping = np->ops->map_single(np->device, skb->data,
6698 len, DMA_TO_DEVICE);
6699
6700 prod = rp->prod;
6701
6702 rp->tx_buffs[prod].skb = skb;
6703 rp->tx_buffs[prod].mapping = mapping;
6704
6705 mrk = TX_DESC_SOP;
6706 if (++rp->mark_counter == rp->mark_freq) {
6707 rp->mark_counter = 0;
6708 mrk |= TX_DESC_MARK;
6709 rp->mark_pending++;
6710 }
6711
6712 tlen = len;
6713 nfg = skb_shinfo(skb)->nr_frags;
6714 while (tlen > 0) {
6715 tlen -= MAX_TX_DESC_LEN;
6716 nfg++;
6717 }
6718
6719 while (len > 0) {
6720 unsigned int this_len = len;
6721
6722 if (this_len > MAX_TX_DESC_LEN)
6723 this_len = MAX_TX_DESC_LEN;
6724
6725 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6726 mrk = nfg = 0;
6727
6728 prod = NEXT_TX(rp, prod);
6729 mapping += this_len;
6730 len -= this_len;
6731 }
6732
6733 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6734 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6735
6736 len = frag->size;
134b413c 6737 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
a3138df9
DM		 6738 frag->page_offset, len,
6739 DMA_TO_DEVICE);
6740
6741 rp->tx_buffs[prod].skb = NULL;
6742 rp->tx_buffs[prod].mapping = mapping;
6743
6744 niu_set_txd(rp, prod, mapping, len, 0, 0);
6745
6746 prod = NEXT_TX(rp, prod);
6747 }
6748
6749 if (prod < rp->prod)
6750 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6751 rp->prod = prod;
6752
6753 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6754
6755 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6756 netif_tx_stop_queue(txq);
a3138df9 6757 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6758 netif_tx_wake_queue(txq);
a3138df9
DM		 6759 }
6760
a3138df9
DM		 6761out:
6762 return NETDEV_TX_OK;
6763
6764out_drop:
6765 rp->tx_errors++;
6766 kfree_skb(skb);
6767 goto out;
6768}
6769
6770static int niu_change_mtu(struct net_device *dev, int new_mtu)
6771{
6772 struct niu *np = netdev_priv(dev);
6773 int err, orig_jumbo, new_jumbo;
6774
6775 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6776 return -EINVAL;
6777
6778 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6779 new_jumbo = (new_mtu > ETH_DATA_LEN);
6780
6781 dev->mtu = new_mtu;
6782
6783 if (!netif_running(dev) ||
6784 (orig_jumbo == new_jumbo))
6785 return 0;
6786
6787 niu_full_shutdown(np, dev);
6788
6789 niu_free_channels(np);
6790
6791 niu_enable_napi(np);
6792
6793 err = niu_alloc_channels(np);
6794 if (err)
6795 return err;
6796
6797 spin_lock_irq(&np->lock);
6798
6799 err = niu_init_hw(np);
6800 if (!err) {
6801 init_timer(&np->timer);
6802 np->timer.expires = jiffies + HZ;
6803 np->timer.data = (unsigned long) np;
6804 np->timer.function = niu_timer;
6805
6806 err = niu_enable_interrupts(np, 1);
6807 if (err)
6808 niu_stop_hw(np);
6809 }
6810
6811 spin_unlock_irq(&np->lock);
6812
6813 if (!err) {
b4c21639 6814 netif_tx_start_all_queues(dev);
a3138df9
DM		 6815 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6816 netif_carrier_on(dev);
6817
6818 add_timer(&np->timer);
6819 }
6820
6821 return err;
6822}
6823
6824static void niu_get_drvinfo(struct net_device *dev,
6825 struct ethtool_drvinfo *info)
6826{
6827 struct niu *np = netdev_priv(dev);
6828 struct niu_vpd *vpd = &np->vpd;
6829
6830 strcpy(info->driver, DRV_MODULE_NAME);
6831 strcpy(info->version, DRV_MODULE_VERSION);
6832 sprintf(info->fw_version, "%d.%d",
6833 vpd->fcode_major, vpd->fcode_minor);
6834 if (np->parent->plat_type != PLAT_TYPE_NIU)
6835 strcpy(info->bus_info, pci_name(np->pdev));
6836}
6837
6838static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6839{
6840 struct niu *np = netdev_priv(dev);
6841 struct niu_link_config *lp;
6842
6843 lp = &np->link_config;
6844
6845 memset(cmd, 0, sizeof(*cmd));
6846 cmd->phy_address = np->phy_addr;
6847 cmd->supported = lp->supported;
38bb045d
CB		 6848 cmd->advertising = lp->active_advertising;
6849 cmd->autoneg = lp->active_autoneg;
70739497 6850 ethtool_cmd_speed_set(cmd, lp->active_speed);
a3138df9 6851 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6852 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6853 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6854 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6855
6856 return 0;
6857}
6858
6859static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6860{
38bb045d
CB		 6861 struct niu *np = netdev_priv(dev);
6862 struct niu_link_config *lp = &np->link_config;
6863
6864 lp->advertising = cmd->advertising;
25db0338 6865 lp->speed = ethtool_cmd_speed(cmd);
38bb045d
CB		 6866 lp->duplex = cmd->duplex;
6867 lp->autoneg = cmd->autoneg;
6868 return niu_init_link(np);
a3138df9
DM		 6869}
6870
6871static u32 niu_get_msglevel(struct net_device *dev)
6872{
6873 struct niu *np = netdev_priv(dev);
6874 return np->msg_enable;
6875}
6876
6877static void niu_set_msglevel(struct net_device *dev, u32 value)
6878{
6879 struct niu *np = netdev_priv(dev);
6880 np->msg_enable = value;
6881}
6882
38bb045d
CB		 6883static int niu_nway_reset(struct net_device *dev)
6884{
6885 struct niu *np = netdev_priv(dev);
6886
6887 if (np->link_config.autoneg)
6888 return niu_init_link(np);
6889
6890 return 0;
6891}
6892
a3138df9
DM		 6893static int niu_get_eeprom_len(struct net_device *dev)
6894{
6895 struct niu *np = netdev_priv(dev);
6896
6897 return np->eeprom_len;
6898}
6899
6900static int niu_get_eeprom(struct net_device *dev,
6901 struct ethtool_eeprom *eeprom, u8 *data)
6902{
6903 struct niu *np = netdev_priv(dev);
6904 u32 offset, len, val;
6905
6906 offset = eeprom->offset;
6907 len = eeprom->len;
6908
6909 if (offset + len < offset)
6910 return -EINVAL;
6911 if (offset >= np->eeprom_len)
6912 return -EINVAL;
6913 if (offset + len > np->eeprom_len)
6914 len = eeprom->len = np->eeprom_len - offset;
6915
6916 if (offset & 3) {
6917 u32 b_offset, b_count;
6918
6919 b_offset = offset & 3;
6920 b_count = 4 - b_offset;
6921 if (b_count > len)
6922 b_count = len;
6923
6924 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6925 memcpy(data, ((char *)&val) + b_offset, b_count);
6926 data += b_count;
6927 len -= b_count;
6928 offset += b_count;
6929 }
6930 while (len >= 4) {
6931 val = nr64(ESPC_NCR(offset / 4));
6932 memcpy(data, &val, 4);
6933 data += 4;
6934 len -= 4;
6935 offset += 4;
6936 }
6937 if (len) {
6938 val = nr64(ESPC_NCR(offset / 4));
6939 memcpy(data, &val, len);
6940 }
6941 return 0;
6942}
6943
2d96cf8c
SB		 6944static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6945{
6946 switch (flow_type) {
6947 case TCP_V4_FLOW:
6948 case TCP_V6_FLOW:
6949 *pid = IPPROTO_TCP;
6950 break;
6951 case UDP_V4_FLOW:
6952 case UDP_V6_FLOW:
6953 *pid = IPPROTO_UDP;
6954 break;
6955 case SCTP_V4_FLOW:
6956 case SCTP_V6_FLOW:
6957 *pid = IPPROTO_SCTP;
6958 break;
6959 case AH_V4_FLOW:
6960 case AH_V6_FLOW:
6961 *pid = IPPROTO_AH;
6962 break;
6963 case ESP_V4_FLOW:
6964 case ESP_V6_FLOW:
6965 *pid = IPPROTO_ESP;
6966 break;
6967 default:
6968 *pid = 0;
6969 break;
6970 }
6971}
6972
6973static int niu_class_to_ethflow(u64 class, int *flow_type)
6974{
6975 switch (class) {
6976 case CLASS_CODE_TCP_IPV4:
6977 *flow_type = TCP_V4_FLOW;
6978 break;
6979 case CLASS_CODE_UDP_IPV4:
6980 *flow_type = UDP_V4_FLOW;
6981 break;
6982 case CLASS_CODE_AH_ESP_IPV4:
6983 *flow_type = AH_V4_FLOW;
6984 break;
6985 case CLASS_CODE_SCTP_IPV4:
6986 *flow_type = SCTP_V4_FLOW;
6987 break;
6988 case CLASS_CODE_TCP_IPV6:
6989 *flow_type = TCP_V6_FLOW;
6990 break;
6991 case CLASS_CODE_UDP_IPV6:
6992 *flow_type = UDP_V6_FLOW;
6993 break;
6994 case CLASS_CODE_AH_ESP_IPV6:
6995 *flow_type = AH_V6_FLOW;
6996 break;
6997 case CLASS_CODE_SCTP_IPV6:
6998 *flow_type = SCTP_V6_FLOW;
6999 break;
7000 case CLASS_CODE_USER_PROG1:
7001 case CLASS_CODE_USER_PROG2:
7002 case CLASS_CODE_USER_PROG3:
7003 case CLASS_CODE_USER_PROG4:
7004 *flow_type = IP_USER_FLOW;
7005 break;
7006 default:
7007 return 0;
7008 }
7009
7010 return 1;
7011}
7012
b4653e99
SB		 7013static int niu_ethflow_to_class(int flow_type, u64 *class)
7014{
7015 switch (flow_type) {
7016 case TCP_V4_FLOW:
7017 *class = CLASS_CODE_TCP_IPV4;
7018 break;
7019 case UDP_V4_FLOW:
7020 *class = CLASS_CODE_UDP_IPV4;
7021 break;
c44d7995 7022 case AH_ESP_V4_FLOW:
2d96cf8c
SB		 7023 case AH_V4_FLOW:
7024 case ESP_V4_FLOW:
b4653e99
SB		 7025 *class = CLASS_CODE_AH_ESP_IPV4;
7026 break;
7027 case SCTP_V4_FLOW:
7028 *class = CLASS_CODE_SCTP_IPV4;
7029 break;
7030 case TCP_V6_FLOW:
7031 *class = CLASS_CODE_TCP_IPV6;
7032 break;
7033 case UDP_V6_FLOW:
7034 *class = CLASS_CODE_UDP_IPV6;
7035 break;
c44d7995 7036 case AH_ESP_V6_FLOW:
2d96cf8c
SB		 7037 case AH_V6_FLOW:
7038 case ESP_V6_FLOW:
b4653e99
SB		 7039 *class = CLASS_CODE_AH_ESP_IPV6;
7040 break;
7041 case SCTP_V6_FLOW:
7042 *class = CLASS_CODE_SCTP_IPV6;
7043 break;
7044 default:
38c080ff 7045 return 0;
b4653e99
SB		 7046 }
7047
7048 return 1;
7049}
7050
7051static u64 niu_flowkey_to_ethflow(u64 flow_key)
7052{
7053 u64 ethflow = 0;
7054
b4653e99
SB		 7055 if (flow_key & FLOW_KEY_L2DA)
7056 ethflow |= RXH_L2DA;
7057 if (flow_key & FLOW_KEY_VLAN)
7058 ethflow |= RXH_VLAN;
7059 if (flow_key & FLOW_KEY_IPSA)
7060 ethflow |= RXH_IP_SRC;
7061 if (flow_key & FLOW_KEY_IPDA)
7062 ethflow |= RXH_IP_DST;
7063 if (flow_key & FLOW_KEY_PROTO)
7064 ethflow |= RXH_L3_PROTO;
7065 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7066 ethflow |= RXH_L4_B_0_1;
7067 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7068 ethflow |= RXH_L4_B_2_3;
7069
7070 return ethflow;
7071
7072}
7073
7074static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7075{
7076 u64 key = 0;
7077
b4653e99
SB		 7078 if (ethflow & RXH_L2DA)
7079 key |= FLOW_KEY_L2DA;
7080 if (ethflow & RXH_VLAN)
7081 key |= FLOW_KEY_VLAN;
7082 if (ethflow & RXH_IP_SRC)
7083 key |= FLOW_KEY_IPSA;
7084 if (ethflow & RXH_IP_DST)
7085 key |= FLOW_KEY_IPDA;
7086 if (ethflow & RXH_L3_PROTO)
7087 key |= FLOW_KEY_PROTO;
7088 if (ethflow & RXH_L4_B_0_1)
7089 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7090 if (ethflow & RXH_L4_B_2_3)
7091 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7092
7093 *flow_key = key;
7094
7095 return 1;
7096
7097}
7098
2d96cf8c 7099static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7100{
b4653e99
SB		 7101 u64 class;
7102
2d96cf8c 7103 nfc->data = 0;
b4653e99 7104
2d96cf8c 7105 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7106 return -EINVAL;
7107
7108 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7109 TCAM_KEY_DISC)
2d96cf8c 7110 nfc->data = RXH_DISCARD;
b4653e99 7111 else
2d96cf8c 7112 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7113 CLASS_CODE_USER_PROG1]);
7114 return 0;
7115}
7116
2d96cf8c
SB		 7117static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7118 struct ethtool_rx_flow_spec *fsp)
7119{
ed440e82
HH		 7120 u32 tmp;
7121 u16 prt;
2d96cf8c 7122
ed440e82
HH		 7123 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7124 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7125
7126 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7127 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7128
7129 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7130 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7131
7132 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7133 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
2d96cf8c
SB		 7134
7135 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7136 TCAM_V4KEY2_TOS_SHIFT;
7137 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7138 TCAM_V4KEY2_TOS_SHIFT;
7139
7140 switch (fsp->flow_type) {
7141 case TCP_V4_FLOW:
7142 case UDP_V4_FLOW:
7143 case SCTP_V4_FLOW:
ed440e82
HH		 7144 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7145 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7146 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7147
7148 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7149 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7150 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c 7151
ed440e82
HH		 7152 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7153 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7154 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7155
7156 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7157 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7158 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c
SB		 7159 break;
7160 case AH_V4_FLOW:
7161 case ESP_V4_FLOW:
ed440e82 7162 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7163 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7164 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c 7165
ed440e82
HH		 7166 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7167 TCAM_V4KEY2_PORT_SPI_SHIFT;
7168 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c
SB		 7169 break;
7170 case IP_USER_FLOW:
ed440e82 7171 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7172 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7173 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c 7174
ed440e82
HH		 7175 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7176 TCAM_V4KEY2_PORT_SPI_SHIFT;
7177 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c
SB		 7178
7179 fsp->h_u.usr_ip4_spec.proto =
7180 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7181 TCAM_V4KEY2_PROTO_SHIFT;
7182 fsp->m_u.usr_ip4_spec.proto =
7183 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7184 TCAM_V4KEY2_PROTO_SHIFT;
7185
7186 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7187 break;
7188 default:
7189 break;
7190 }
7191}
7192
7193static int niu_get_ethtool_tcam_entry(struct niu *np,
7194 struct ethtool_rxnfc *nfc)
7195{
7196 struct niu_parent *parent = np->parent;
7197 struct niu_tcam_entry *tp;
7198 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7199 u16 idx;
7200 u64 class;
7201 int ret = 0;
7202
7203 idx = tcam_get_index(np, (u16)nfc->fs.location);
7204
7205 tp = &parent->tcam[idx];
7206 if (!tp->valid) {
f10a1f2e
JP		 7207 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7208 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7209 return -EINVAL;
7210 }
7211
7212 /* fill the flow spec entry */
7213 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7214 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7215 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7216
7217 if (ret < 0) {
f10a1f2e
JP		 7218 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7219 parent->index);
2d96cf8c
SB		 7220 ret = -EINVAL;
7221 goto out;
7222 }
7223
7224 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7225 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7226 TCAM_V4KEY2_PROTO_SHIFT;
7227 if (proto == IPPROTO_ESP) {
7228 if (fsp->flow_type == AH_V4_FLOW)
7229 fsp->flow_type = ESP_V4_FLOW;
7230 else
7231 fsp->flow_type = ESP_V6_FLOW;
7232 }
7233 }
7234
7235 switch (fsp->flow_type) {
7236 case TCP_V4_FLOW:
7237 case UDP_V4_FLOW:
7238 case SCTP_V4_FLOW:
7239 case AH_V4_FLOW:
7240 case ESP_V4_FLOW:
7241 niu_get_ip4fs_from_tcam_key(tp, fsp);
7242 break;
7243 case TCP_V6_FLOW:
7244 case UDP_V6_FLOW:
7245 case SCTP_V6_FLOW:
7246 case AH_V6_FLOW:
7247 case ESP_V6_FLOW:
7248 /* Not yet implemented */
7249 ret = -EINVAL;
7250 break;
7251 case IP_USER_FLOW:
7252 niu_get_ip4fs_from_tcam_key(tp, fsp);
7253 break;
7254 default:
7255 ret = -EINVAL;
7256 break;
7257 }
7258
7259 if (ret < 0)
7260 goto out;
7261
7262 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7263 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7264 else
7265 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7266 TCAM_ASSOCDATA_OFFSET_SHIFT;
7267
7268 /* put the tcam size here */
7269 nfc->data = tcam_get_size(np);
7270out:
7271 return ret;
7272}
7273
7274static int niu_get_ethtool_tcam_all(struct niu *np,
7275 struct ethtool_rxnfc *nfc,
7276 u32 *rule_locs)
7277{
7278 struct niu_parent *parent = np->parent;
7279 struct niu_tcam_entry *tp;
7280 int i, idx, cnt;
2d96cf8c 7281 unsigned long flags;
ee9c5cfa 7282 int ret = 0;
2d96cf8c
SB		 7283
7284 /* put the tcam size here */
7285 nfc->data = tcam_get_size(np);
7286
7287 niu_lock_parent(np, flags);
2d96cf8c
SB		 7288 for (cnt = 0, i = 0; i < nfc->data; i++) {
7289 idx = tcam_get_index(np, i);
7290 tp = &parent->tcam[idx];
7291 if (!tp->valid)
7292 continue;
ee9c5cfa
BH		 7293 if (cnt == nfc->rule_cnt) {
7294 ret = -EMSGSIZE;
7295 break;
7296 }
2d96cf8c
SB		 7297 rule_locs[cnt] = i;
7298 cnt++;
7299 }
7300 niu_unlock_parent(np, flags);
7301
473e64ee
BH		 7302 nfc->rule_cnt = cnt;
7303
ee9c5cfa 7304 return ret;
2d96cf8c
SB		 7305}
7306
7307static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 7308 u32 *rule_locs)
b4653e99
SB		 7309{
7310 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7311 int ret = 0;
7312
7313 switch (cmd->cmd) {
7314 case ETHTOOL_GRXFH:
7315 ret = niu_get_hash_opts(np, cmd);
7316 break;
7317 case ETHTOOL_GRXRINGS:
7318 cmd->data = np->num_rx_rings;
7319 break;
7320 case ETHTOOL_GRXCLSRLCNT:
7321 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7322 break;
7323 case ETHTOOL_GRXCLSRULE:
7324 ret = niu_get_ethtool_tcam_entry(np, cmd);
7325 break;
7326 case ETHTOOL_GRXCLSRLALL:
815c7db5 7327 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
2d96cf8c
SB		 7328 break;
7329 default:
7330 ret = -EINVAL;
7331 break;
7332 }
7333
7334 return ret;
7335}
7336
7337static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7338{
b4653e99
SB		 7339 u64 class;
7340 u64 flow_key = 0;
7341 unsigned long flags;
7342
2d96cf8c 7343 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7344 return -EINVAL;
7345
7346 if (class < CLASS_CODE_USER_PROG1 ||
7347 class > CLASS_CODE_SCTP_IPV6)
7348 return -EINVAL;
7349
2d96cf8c 7350 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7351 niu_lock_parent(np, flags);
7352 flow_key = np->parent->tcam_key[class -
7353 CLASS_CODE_USER_PROG1];
7354 flow_key |= TCAM_KEY_DISC;
7355 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7356 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7357 niu_unlock_parent(np, flags);
7358 return 0;
7359 } else {
7360 /* Discard was set before, but is not set now */
7361 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7362 TCAM_KEY_DISC) {
7363 niu_lock_parent(np, flags);
7364 flow_key = np->parent->tcam_key[class -
7365 CLASS_CODE_USER_PROG1];
7366 flow_key &= ~TCAM_KEY_DISC;
7367 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7368 flow_key);
7369 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7370 flow_key;
7371 niu_unlock_parent(np, flags);
7372 }
7373 }
7374
2d96cf8c 7375 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7376 return -EINVAL;
7377
7378 niu_lock_parent(np, flags);
7379 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7380 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7381 niu_unlock_parent(np, flags);
7382
7383 return 0;
7384}
7385
2d96cf8c
SB		 7386static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7387 struct niu_tcam_entry *tp,
7388 int l2_rdc_tab, u64 class)
7389{
7390 u8 pid = 0;
7391 u32 sip, dip, sipm, dipm, spi, spim;
7392 u16 sport, dport, spm, dpm;
7393
7394 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7395 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7396 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7397 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7398
7399 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7400 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7401 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7402 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7403
7404 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7405 tp->key[3] |= dip;
7406
7407 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7408 tp->key_mask[3] |= dipm;
7409
7410 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7411 TCAM_V4KEY2_TOS_SHIFT);
7412 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7413 TCAM_V4KEY2_TOS_SHIFT);
7414 switch (fsp->flow_type) {
7415 case TCP_V4_FLOW:
7416 case UDP_V4_FLOW:
7417 case SCTP_V4_FLOW:
7418 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7419 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7420 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7421 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7422
7423 tp->key[2] |= (((u64)sport << 16) | dport);
7424 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7425 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7426 break;
7427 case AH_V4_FLOW:
7428 case ESP_V4_FLOW:
7429 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7430 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7431
7432 tp->key[2] |= spi;
7433 tp->key_mask[2] |= spim;
7434 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7435 break;
7436 case IP_USER_FLOW:
7437 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7438 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7439
7440 tp->key[2] |= spi;
7441 tp->key_mask[2] |= spim;
7442 pid = fsp->h_u.usr_ip4_spec.proto;
7443 break;
7444 default:
7445 break;
7446 }
7447
7448 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7449 if (pid) {
7450 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7451 }
7452}
7453
7454static int niu_add_ethtool_tcam_entry(struct niu *np,
7455 struct ethtool_rxnfc *nfc)
7456{
7457 struct niu_parent *parent = np->parent;
7458 struct niu_tcam_entry *tp;
7459 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7460 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7461 int l2_rdc_table = rdc_table->first_table_num;
7462 u16 idx;
7463 u64 class;
7464 unsigned long flags;
7465 int err, ret;
7466
7467 ret = 0;
7468
7469 idx = nfc->fs.location;
7470 if (idx >= tcam_get_size(np))
7471 return -EINVAL;
7472
7473 if (fsp->flow_type == IP_USER_FLOW) {
7474 int i;
7475 int add_usr_cls = 0;
2d96cf8c
SB		 7476 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7477 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7478
e0de7c93
BH		 7479 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7480 return -EINVAL;
7481
2d96cf8c
SB		 7482 niu_lock_parent(np, flags);
7483
7484 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7485 if (parent->l3_cls[i]) {
7486 if (uspec->proto == parent->l3_cls_pid[i]) {
7487 class = parent->l3_cls[i];
7488 parent->l3_cls_refcnt[i]++;
7489 add_usr_cls = 1;
7490 break;
7491 }
7492 } else {
7493 /* Program new user IP class */
7494 switch (i) {
7495 case 0:
7496 class = CLASS_CODE_USER_PROG1;
7497 break;
7498 case 1:
7499 class = CLASS_CODE_USER_PROG2;
7500 break;
7501 case 2:
7502 class = CLASS_CODE_USER_PROG3;
7503 break;
7504 case 3:
7505 class = CLASS_CODE_USER_PROG4;
7506 break;
7507 default:
7508 break;
7509 }
e0de7c93 7510 ret = tcam_user_ip_class_set(np, class, 0,
2d96cf8c
SB		 7511 uspec->proto,
7512 uspec->tos,
7513 umask->tos);
7514 if (ret)
7515 goto out;
7516
7517 ret = tcam_user_ip_class_enable(np, class, 1);
7518 if (ret)
7519 goto out;
7520 parent->l3_cls[i] = class;
7521 parent->l3_cls_pid[i] = uspec->proto;
7522 parent->l3_cls_refcnt[i]++;
7523 add_usr_cls = 1;
7524 break;
7525 }
7526 }
7527 if (!add_usr_cls) {
f10a1f2e
JP		 7528 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7529 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7530 ret = -EINVAL;
7531 goto out;
7532 }
7533 niu_unlock_parent(np, flags);
7534 } else {
7535 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7536 return -EINVAL;
7537 }
7538 }
7539
7540 niu_lock_parent(np, flags);
7541
7542 idx = tcam_get_index(np, idx);
7543 tp = &parent->tcam[idx];
7544
7545 memset(tp, 0, sizeof(*tp));
7546
7547 /* fill in the tcam key and mask */
7548 switch (fsp->flow_type) {
7549 case TCP_V4_FLOW:
7550 case UDP_V4_FLOW:
7551 case SCTP_V4_FLOW:
7552 case AH_V4_FLOW:
7553 case ESP_V4_FLOW:
7554 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7555 break;
7556 case TCP_V6_FLOW:
7557 case UDP_V6_FLOW:
7558 case SCTP_V6_FLOW:
7559 case AH_V6_FLOW:
7560 case ESP_V6_FLOW:
7561 /* Not yet implemented */
f10a1f2e
JP		 7562 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7563 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7564 ret = -EINVAL;
7565 goto out;
7566 case IP_USER_FLOW:
e0de7c93 7567 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
2d96cf8c
SB		 7568 break;
7569 default:
f10a1f2e
JP		 7570 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7571 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7572 ret = -EINVAL;
7573 goto out;
7574 }
7575
7576 /* fill in the assoc data */
7577 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7578 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7579 } else {
7580 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7581 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7582 parent->index, __func__,
7583 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7584 ret = -EINVAL;
7585 goto out;
7586 }
7587 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7588 (fsp->ring_cookie <<
7589 TCAM_ASSOCDATA_OFFSET_SHIFT));
7590 }
7591
7592 err = tcam_write(np, idx, tp->key, tp->key_mask);
7593 if (err) {
7594 ret = -EINVAL;
7595 goto out;
7596 }
7597 err = tcam_assoc_write(np, idx, tp->assoc_data);
7598 if (err) {
7599 ret = -EINVAL;
7600 goto out;
7601 }
7602
7603 /* validate the entry */
7604 tp->valid = 1;
7605 np->clas.tcam_valid_entries++;
7606out:
7607 niu_unlock_parent(np, flags);
7608
7609 return ret;
7610}
7611
7612static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7613{
7614 struct niu_parent *parent = np->parent;
7615 struct niu_tcam_entry *tp;
7616 u16 idx;
7617 unsigned long flags;
7618 u64 class;
7619 int ret = 0;
7620
7621 if (loc >= tcam_get_size(np))
7622 return -EINVAL;
7623
7624 niu_lock_parent(np, flags);
7625
7626 idx = tcam_get_index(np, loc);
7627 tp = &parent->tcam[idx];
7628
7629 /* if the entry is of a user defined class, then update*/
7630 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7631 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7632
7633 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7634 int i;
7635 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7636 if (parent->l3_cls[i] == class) {
7637 parent->l3_cls_refcnt[i]--;
7638 if (!parent->l3_cls_refcnt[i]) {
7639 /* disable class */
7640 ret = tcam_user_ip_class_enable(np,
7641 class,
7642 0);
7643 if (ret)
7644 goto out;
7645 parent->l3_cls[i] = 0;
7646 parent->l3_cls_pid[i] = 0;
7647 }
7648 break;
7649 }
7650 }
7651 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7652 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7653 parent->index, __func__,
7654 (unsigned long long)class);
2d96cf8c
SB		 7655 ret = -EINVAL;
7656 goto out;
7657 }
7658 }
7659
7660 ret = tcam_flush(np, idx);
7661 if (ret)
7662 goto out;
7663
7664 /* invalidate the entry */
7665 tp->valid = 0;
7666 np->clas.tcam_valid_entries--;
7667out:
7668 niu_unlock_parent(np, flags);
7669
7670 return ret;
7671}
7672
7673static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7674{
7675 struct niu *np = netdev_priv(dev);
7676 int ret = 0;
7677
7678 switch (cmd->cmd) {
7679 case ETHTOOL_SRXFH:
7680 ret = niu_set_hash_opts(np, cmd);
7681 break;
7682 case ETHTOOL_SRXCLSRLINS:
7683 ret = niu_add_ethtool_tcam_entry(np, cmd);
7684 break;
7685 case ETHTOOL_SRXCLSRLDEL:
7686 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7687 break;
7688 default:
7689 ret = -EINVAL;
7690 break;
7691 }
7692
7693 return ret;
7694}
7695
a3138df9
DM		 7696static const struct {
7697 const char string[ETH_GSTRING_LEN];
7698} niu_xmac_stat_keys[] = {
7699 { "tx_frames" },
7700 { "tx_bytes" },
7701 { "tx_fifo_errors" },
7702 { "tx_overflow_errors" },
7703 { "tx_max_pkt_size_errors" },
7704 { "tx_underflow_errors" },
7705 { "rx_local_faults" },
7706 { "rx_remote_faults" },
7707 { "rx_link_faults" },
7708 { "rx_align_errors" },
7709 { "rx_frags" },
7710 { "rx_mcasts" },
7711 { "rx_bcasts" },
7712 { "rx_hist_cnt1" },
7713 { "rx_hist_cnt2" },
7714 { "rx_hist_cnt3" },
7715 { "rx_hist_cnt4" },
7716 { "rx_hist_cnt5" },
7717 { "rx_hist_cnt6" },
7718 { "rx_hist_cnt7" },
7719 { "rx_octets" },
7720 { "rx_code_violations" },
7721 { "rx_len_errors" },
7722 { "rx_crc_errors" },
7723 { "rx_underflows" },
7724 { "rx_overflows" },
7725 { "pause_off_state" },
7726 { "pause_on_state" },
7727 { "pause_received" },
7728};
7729
7730#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7731
7732static const struct {
7733 const char string[ETH_GSTRING_LEN];
7734} niu_bmac_stat_keys[] = {
7735 { "tx_underflow_errors" },
7736 { "tx_max_pkt_size_errors" },
7737 { "tx_bytes" },
7738 { "tx_frames" },
7739 { "rx_overflows" },
7740 { "rx_frames" },
7741 { "rx_align_errors" },
7742 { "rx_crc_errors" },
7743 { "rx_len_errors" },
7744 { "pause_off_state" },
7745 { "pause_on_state" },
7746 { "pause_received" },
7747};
7748
7749#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7750
7751static const struct {
7752 const char string[ETH_GSTRING_LEN];
7753} niu_rxchan_stat_keys[] = {
7754 { "rx_channel" },
7755 { "rx_packets" },
7756 { "rx_bytes" },
7757 { "rx_dropped" },
7758 { "rx_errors" },
7759};
7760
7761#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7762
7763static const struct {
7764 const char string[ETH_GSTRING_LEN];
7765} niu_txchan_stat_keys[] = {
7766 { "tx_channel" },
7767 { "tx_packets" },
7768 { "tx_bytes" },
7769 { "tx_errors" },
7770};
7771
7772#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7773
7774static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7775{
7776 struct niu *np = netdev_priv(dev);
7777 int i;
7778
7779 if (stringset != ETH_SS_STATS)
7780 return;
7781
7782 if (np->flags & NIU_FLAGS_XMAC) {
7783 memcpy(data, niu_xmac_stat_keys,
7784 sizeof(niu_xmac_stat_keys));
7785 data += sizeof(niu_xmac_stat_keys);
7786 } else {
7787 memcpy(data, niu_bmac_stat_keys,
7788 sizeof(niu_bmac_stat_keys));
7789 data += sizeof(niu_bmac_stat_keys);
7790 }
7791 for (i = 0; i < np->num_rx_rings; i++) {
7792 memcpy(data, niu_rxchan_stat_keys,
7793 sizeof(niu_rxchan_stat_keys));
7794 data += sizeof(niu_rxchan_stat_keys);
7795 }
7796 for (i = 0; i < np->num_tx_rings; i++) {
7797 memcpy(data, niu_txchan_stat_keys,
7798 sizeof(niu_txchan_stat_keys));
7799 data += sizeof(niu_txchan_stat_keys);
7800 }
7801}
7802
15f0a394 7803static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7804{
7805 struct niu *np = netdev_priv(dev);
7806
15f0a394
BH		 7807 if (stringset != ETH_SS_STATS)
7808 return -EINVAL;
7809
807540ba 7810 return (np->flags & NIU_FLAGS_XMAC ?
a3138df9
DM		 7811 NUM_XMAC_STAT_KEYS :
7812 NUM_BMAC_STAT_KEYS) +
7813 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
807540ba 7814 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
a3138df9
DM		 7815}
7816
7817static void niu_get_ethtool_stats(struct net_device *dev,
7818 struct ethtool_stats *stats, u64 *data)
7819{
7820 struct niu *np = netdev_priv(dev);
7821 int i;
7822
7823 niu_sync_mac_stats(np);
7824 if (np->flags & NIU_FLAGS_XMAC) {
7825 memcpy(data, &np->mac_stats.xmac,
7826 sizeof(struct niu_xmac_stats));
7827 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7828 } else {
7829 memcpy(data, &np->mac_stats.bmac,
7830 sizeof(struct niu_bmac_stats));
7831 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7832 }
7833 for (i = 0; i < np->num_rx_rings; i++) {
7834 struct rx_ring_info *rp = &np->rx_rings[i];
7835
b8a606b8
JDB		 7836 niu_sync_rx_discard_stats(np, rp, 0);
7837
a3138df9
DM		 7838 data[0] = rp->rx_channel;
7839 data[1] = rp->rx_packets;
7840 data[2] = rp->rx_bytes;
7841 data[3] = rp->rx_dropped;
7842 data[4] = rp->rx_errors;
7843 data += 5;
7844 }
7845 for (i = 0; i < np->num_tx_rings; i++) {
7846 struct tx_ring_info *rp = &np->tx_rings[i];
7847
7848 data[0] = rp->tx_channel;
7849 data[1] = rp->tx_packets;
7850 data[2] = rp->tx_bytes;
7851 data[3] = rp->tx_errors;
7852 data += 4;
7853 }
7854}
7855
7856static u64 niu_led_state_save(struct niu *np)
7857{
7858 if (np->flags & NIU_FLAGS_XMAC)
7859 return nr64_mac(XMAC_CONFIG);
7860 else
7861 return nr64_mac(BMAC_XIF_CONFIG);
7862}
7863
7864static void niu_led_state_restore(struct niu *np, u64 val)
7865{
7866 if (np->flags & NIU_FLAGS_XMAC)
7867 nw64_mac(XMAC_CONFIG, val);
7868 else
7869 nw64_mac(BMAC_XIF_CONFIG, val);
7870}
7871
7872static void niu_force_led(struct niu *np, int on)
7873{
7874 u64 val, reg, bit;
7875
7876 if (np->flags & NIU_FLAGS_XMAC) {
7877 reg = XMAC_CONFIG;
7878 bit = XMAC_CONFIG_FORCE_LED_ON;
7879 } else {
7880 reg = BMAC_XIF_CONFIG;
7881 bit = BMAC_XIF_CONFIG_LINK_LED;
7882 }
7883
7884 val = nr64_mac(reg);
7885 if (on)
7886 val |= bit;
7887 else
7888 val &= ~bit;
7889 nw64_mac(reg, val);
7890}
7891
7bc93714 7892static int niu_set_phys_id(struct net_device *dev,
7893 enum ethtool_phys_id_state state)
7894
a3138df9
DM		 7895{
7896 struct niu *np = netdev_priv(dev);
a3138df9
DM		 7897
7898 if (!netif_running(dev))
7899 return -EAGAIN;
7900
7bc93714 7901 switch (state) {
7902 case ETHTOOL_ID_ACTIVE:
7903 np->orig_led_state = niu_led_state_save(np);
fce55922 7904 return 1; /* cycle on/off once per second */
a3138df9 7905
7bc93714 7906 case ETHTOOL_ID_ON:
7907 niu_force_led(np, 1);
7908 break;
a3138df9 7909
7bc93714 7910 case ETHTOOL_ID_OFF:
7911 niu_force_led(np, 0);
7912 break;
a3138df9 7913
7bc93714 7914 case ETHTOOL_ID_INACTIVE:
7915 niu_led_state_restore(np, np->orig_led_state);
a3138df9 7916 }
a3138df9
DM		 7917
7918 return 0;
7919}
7920
7921static const struct ethtool_ops niu_ethtool_ops = {
7922 .get_drvinfo = niu_get_drvinfo,
7923 .get_link = ethtool_op_get_link,
7924 .get_msglevel = niu_get_msglevel,
7925 .set_msglevel = niu_set_msglevel,
38bb045d 7926 .nway_reset = niu_nway_reset,
a3138df9
DM		 7927 .get_eeprom_len = niu_get_eeprom_len,
7928 .get_eeprom = niu_get_eeprom,
7929 .get_settings = niu_get_settings,
7930 .set_settings = niu_set_settings,
7931 .get_strings = niu_get_strings,
15f0a394 7932 .get_sset_count = niu_get_sset_count,
a3138df9 7933 .get_ethtool_stats = niu_get_ethtool_stats,
7bc93714 7934 .set_phys_id = niu_set_phys_id,
2d96cf8c
SB		 7935 .get_rxnfc = niu_get_nfc,
7936 .set_rxnfc = niu_set_nfc,
a3138df9
DM		 7937};
7938
7939static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7940 int ldg, int ldn)
7941{
7942 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7943 return -EINVAL;
7944 if (ldn < 0 || ldn > LDN_MAX)
7945 return -EINVAL;
7946
7947 parent->ldg_map[ldn] = ldg;
7948
7949 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7950 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7951 * the firmware, and we're not supposed to change them.
7952 * Validate the mapping, because if it's wrong we probably
7953 * won't get any interrupts and that's painful to debug.
7954 */
7955 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7956 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7957 np->port, ldn, ldg,
7958 (unsigned long long) nr64(LDG_NUM(ldn)));
7959 return -EINVAL;
7960 }
7961 } else
7962 nw64(LDG_NUM(ldn), ldg);
7963
7964 return 0;
7965}
7966
7967static int niu_set_ldg_timer_res(struct niu *np, int res)
7968{
7969 if (res < 0 || res > LDG_TIMER_RES_VAL)
7970 return -EINVAL;
7971
7972
7973 nw64(LDG_TIMER_RES, res);
7974
7975 return 0;
7976}
7977
7978static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7979{
7980 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7981 (func < 0 || func > 3) ||
7982 (vector < 0 || vector > 0x1f))
7983 return -EINVAL;
7984
7985 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7986
7987 return 0;
7988}
7989
7990static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7991{
7992 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7993 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7994 int limit;
7995
7996 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7997 return -EINVAL;
7998
7999 frame = frame_base;
8000 nw64(ESPC_PIO_STAT, frame);
8001 limit = 64;
8002 do {
8003 udelay(5);
8004 frame = nr64(ESPC_PIO_STAT);
8005 if (frame & ESPC_PIO_STAT_READ_END)
8006 break;
8007 } while (limit--);
8008 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8009 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8010 (unsigned long long) frame);
8011 return -ENODEV;
8012 }
8013
8014 frame = frame_base;
8015 nw64(ESPC_PIO_STAT, frame);
8016 limit = 64;
8017 do {
8018 udelay(5);
8019 frame = nr64(ESPC_PIO_STAT);
8020 if (frame & ESPC_PIO_STAT_READ_END)
8021 break;
8022 } while (limit--);
8023 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8024 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8025 (unsigned long long) frame);
8026 return -ENODEV;
8027 }
8028
8029 frame = nr64(ESPC_PIO_STAT);
8030 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8031}
8032
8033static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8034{
8035 int err = niu_pci_eeprom_read(np, off);
8036 u16 val;
8037
8038 if (err < 0)
8039 return err;
8040 val = (err << 8);
8041 err = niu_pci_eeprom_read(np, off + 1);
8042 if (err < 0)
8043 return err;
8044 val |= (err & 0xff);
8045
8046 return val;
8047}
8048
8049static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8050{
8051 int err = niu_pci_eeprom_read(np, off);
8052 u16 val;
8053
8054 if (err < 0)
8055 return err;
8056
8057 val = (err & 0xff);
8058 err = niu_pci_eeprom_read(np, off + 1);
8059 if (err < 0)
8060 return err;
8061
8062 val |= (err & 0xff) << 8;
8063
8064 return val;
8065}
8066
8067static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8068 u32 off,
8069 char *namebuf,
8070 int namebuf_len)
8071{
8072 int i;
8073
8074 for (i = 0; i < namebuf_len; i++) {
8075 int err = niu_pci_eeprom_read(np, off + i);
8076 if (err < 0)
8077 return err;
8078 *namebuf++ = err;
8079 if (!err)
8080 break;
8081 }
8082 if (i >= namebuf_len)
8083 return -EINVAL;
8084
8085 return i + 1;
8086}
8087
8088static void __devinit niu_vpd_parse_version(struct niu *np)
8089{
8090 struct niu_vpd *vpd = &np->vpd;
8091 int len = strlen(vpd->version) + 1;
8092 const char *s = vpd->version;
8093 int i;
8094
8095 for (i = 0; i < len - 5; i++) {
9ea2bdab 8096 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8097 break;
8098 }
8099 if (i >= len - 5)
8100 return;
8101
8102 s += i + 5;
8103 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8104
f10a1f2e
JP		 8105 netif_printk(np, probe, KERN_DEBUG, np->dev,
8106 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8107 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8108 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8109 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8110 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8111 np->flags |= NIU_FLAGS_VPD_VALID;
8112}
8113
8114/* ESPC_PIO_EN_ENABLE must be set */
8115static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8116 u32 start, u32 end)
8117{
8118 unsigned int found_mask = 0;
8119#define FOUND_MASK_MODEL 0x00000001
8120#define FOUND_MASK_BMODEL 0x00000002
8121#define FOUND_MASK_VERS 0x00000004
8122#define FOUND_MASK_MAC 0x00000008
8123#define FOUND_MASK_NMAC 0x00000010
8124#define FOUND_MASK_PHY 0x00000020
8125#define FOUND_MASK_ALL 0x0000003f
8126
f10a1f2e
JP		 8127 netif_printk(np, probe, KERN_DEBUG, np->dev,
8128 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9 8129 while (start < end) {
f344c25d 8130 int len, err, prop_len;
a3138df9
DM		 8131 char namebuf[64];
8132 u8 *prop_buf;
8133 int max_len;
8134
8135 if (found_mask == FOUND_MASK_ALL) {
8136 niu_vpd_parse_version(np);
8137 return 1;
8138 }
8139
8140 err = niu_pci_eeprom_read(np, start + 2);
8141 if (err < 0)
8142 return err;
8143 len = err;
8144 start += 3;
8145
a3138df9
DM		 8146 prop_len = niu_pci_eeprom_read(np, start + 4);
8147 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8148 if (err < 0)
8149 return err;
8150
8151 prop_buf = NULL;
8152 max_len = 0;
8153 if (!strcmp(namebuf, "model")) {
8154 prop_buf = np->vpd.model;
8155 max_len = NIU_VPD_MODEL_MAX;
8156 found_mask |= FOUND_MASK_MODEL;
8157 } else if (!strcmp(namebuf, "board-model")) {
8158 prop_buf = np->vpd.board_model;
8159 max_len = NIU_VPD_BD_MODEL_MAX;
8160 found_mask |= FOUND_MASK_BMODEL;
8161 } else if (!strcmp(namebuf, "version")) {
8162 prop_buf = np->vpd.version;
8163 max_len = NIU_VPD_VERSION_MAX;
8164 found_mask |= FOUND_MASK_VERS;
8165 } else if (!strcmp(namebuf, "local-mac-address")) {
8166 prop_buf = np->vpd.local_mac;
8167 max_len = ETH_ALEN;
8168 found_mask |= FOUND_MASK_MAC;
8169 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8170 prop_buf = &np->vpd.mac_num;
8171 max_len = 1;
8172 found_mask |= FOUND_MASK_NMAC;
8173 } else if (!strcmp(namebuf, "phy-type")) {
8174 prop_buf = np->vpd.phy_type;
8175 max_len = NIU_VPD_PHY_TYPE_MAX;
8176 found_mask |= FOUND_MASK_PHY;
8177 }
8178
8179 if (max_len && prop_len > max_len) {
f10a1f2e 8180 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8181 return -EINVAL;
8182 }
8183
8184 if (prop_buf) {
8185 u32 off = start + 5 + err;
8186 int i;
8187
f10a1f2e
JP		 8188 netif_printk(np, probe, KERN_DEBUG, np->dev,
8189 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8190 namebuf, prop_len);
a3138df9
DM		 8191 for (i = 0; i < prop_len; i++)
8192 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8193 }
8194
8195 start += len;
8196 }
8197
8198 return 0;
8199}
8200
8201/* ESPC_PIO_EN_ENABLE must be set */
8202static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8203{
8204 u32 offset;
8205 int err;
8206
8207 err = niu_pci_eeprom_read16_swp(np, start + 1);
8208 if (err < 0)
8209 return;
8210
8211 offset = err + 3;
8212
8213 while (start + offset < ESPC_EEPROM_SIZE) {
8214 u32 here = start + offset;
8215 u32 end;
8216
8217 err = niu_pci_eeprom_read(np, here);
8218 if (err != 0x90)
8219 return;
8220
8221 err = niu_pci_eeprom_read16_swp(np, here + 1);
8222 if (err < 0)
8223 return;
8224
8225 here = start + offset + 3;
8226 end = start + offset + err;
8227
8228 offset += err;
8229
8230 err = niu_pci_vpd_scan_props(np, here, end);
8231 if (err < 0 || err == 1)
8232 return;
8233 }
8234}
8235
8236/* ESPC_PIO_EN_ENABLE must be set */
8237static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8238{
8239 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8240 int err;
8241
8242 while (start < end) {
8243 ret = start;
8244
8245 /* ROM header signature? */
8246 err = niu_pci_eeprom_read16(np, start + 0);
8247 if (err != 0x55aa)
8248 return 0;
8249
8250 /* Apply offset to PCI data structure. */
8251 err = niu_pci_eeprom_read16(np, start + 23);
8252 if (err < 0)
8253 return 0;
8254 start += err;
8255
8256 /* Check for "PCIR" signature. */
8257 err = niu_pci_eeprom_read16(np, start + 0);
8258 if (err != 0x5043)
8259 return 0;
8260 err = niu_pci_eeprom_read16(np, start + 2);
8261 if (err != 0x4952)
8262 return 0;
8263
8264 /* Check for OBP image type. */
8265 err = niu_pci_eeprom_read(np, start + 20);
8266 if (err < 0)
8267 return 0;
8268 if (err != 0x01) {
8269 err = niu_pci_eeprom_read(np, ret + 2);
8270 if (err < 0)
8271 return 0;
8272
8273 start = ret + (err * 512);
8274 continue;
8275 }
8276
8277 err = niu_pci_eeprom_read16_swp(np, start + 8);
8278 if (err < 0)
8279 return err;
8280 ret += err;
8281
8282 err = niu_pci_eeprom_read(np, ret + 0);
8283 if (err != 0x82)
8284 return 0;
8285
8286 return ret;
8287 }
8288
8289 return 0;
8290}
8291
8292static int __devinit niu_phy_type_prop_decode(struct niu *np,
8293 const char *phy_prop)
8294{
8295 if (!strcmp(phy_prop, "mif")) {
8296 /* 1G copper, MII */
8297 np->flags &= ~(NIU_FLAGS_FIBER |
8298 NIU_FLAGS_10G);
8299 np->mac_xcvr = MAC_XCVR_MII;
8300 } else if (!strcmp(phy_prop, "xgf")) {
8301 /* 10G fiber, XPCS */
8302 np->flags |= (NIU_FLAGS_10G |
8303 NIU_FLAGS_FIBER);
8304 np->mac_xcvr = MAC_XCVR_XPCS;
8305 } else if (!strcmp(phy_prop, "pcs")) {
8306 /* 1G fiber, PCS */
8307 np->flags &= ~NIU_FLAGS_10G;
8308 np->flags |= NIU_FLAGS_FIBER;
8309 np->mac_xcvr = MAC_XCVR_PCS;
8310 } else if (!strcmp(phy_prop, "xgc")) {
8311 /* 10G copper, XPCS */
8312 np->flags |= NIU_FLAGS_10G;
8313 np->flags &= ~NIU_FLAGS_FIBER;
8314 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8315 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8316 /* 10G Serdes or 1G Serdes, default to 10G */
8317 np->flags |= NIU_FLAGS_10G;
8318 np->flags &= ~NIU_FLAGS_FIBER;
8319 np->flags |= NIU_FLAGS_XCVR_SERDES;
8320 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8321 } else {
8322 return -EINVAL;
8323 }
8324 return 0;
8325}
8326
7f7c4072
MW		 8327static int niu_pci_vpd_get_nports(struct niu *np)
8328{
8329 int ports = 0;
8330
f9af8574
MW		 8331 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8332 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8333 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8335 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8336 ports = 4;
f9af8574
MW		 8337 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8338 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8339 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8340 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8341 ports = 2;
8342 }
8343
8344 return ports;
8345}
8346
a3138df9
DM		 8347static void __devinit niu_pci_vpd_validate(struct niu *np)
8348{
8349 struct net_device *dev = np->dev;
8350 struct niu_vpd *vpd = &np->vpd;
8351 u8 val8;
8352
8353 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8354 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8355
8356 np->flags &= ~NIU_FLAGS_VPD_VALID;
8357 return;
8358 }
8359
f9af8574
MW		 8360 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8361 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8362 np->flags |= NIU_FLAGS_10G;
8363 np->flags &= ~NIU_FLAGS_FIBER;
8364 np->flags |= NIU_FLAGS_XCVR_SERDES;
8365 np->mac_xcvr = MAC_XCVR_PCS;
8366 if (np->port > 1) {
8367 np->flags |= NIU_FLAGS_FIBER;
8368 np->flags &= ~NIU_FLAGS_10G;
8369 }
8370 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8371 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8372 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8373 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8374 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8375 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8376 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8377 np->vpd.phy_type);
f10a1f2e 8378 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8379 np->flags &= ~NIU_FLAGS_VPD_VALID;
8380 return;
8381 }
8382
8383 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8384
8385 val8 = dev->perm_addr[5];
8386 dev->perm_addr[5] += np->port;
8387 if (dev->perm_addr[5] < val8)
8388 dev->perm_addr[4]++;
8389
8390 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8391}
8392
8393static int __devinit niu_pci_probe_sprom(struct niu *np)
8394{
8395 struct net_device *dev = np->dev;
8396 int len, i;
8397 u64 val, sum;
8398 u8 val8;
8399
8400 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8401 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8402 len = val / 4;
8403
8404 np->eeprom_len = len;
8405
f10a1f2e
JP		 8406 netif_printk(np, probe, KERN_DEBUG, np->dev,
8407 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8408
8409 sum = 0;
8410 for (i = 0; i < len; i++) {
8411 val = nr64(ESPC_NCR(i));
8412 sum += (val >> 0) & 0xff;
8413 sum += (val >> 8) & 0xff;
8414 sum += (val >> 16) & 0xff;
8415 sum += (val >> 24) & 0xff;
8416 }
f10a1f2e
JP		 8417 netif_printk(np, probe, KERN_DEBUG, np->dev,
8418 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8419 if ((sum & 0xff) != 0xab) {
f10a1f2e 8420 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8421 return -EINVAL;
8422 }
8423
8424 val = nr64(ESPC_PHY_TYPE);
8425 switch (np->port) {
8426 case 0:
a9d41192 8427 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8428 ESPC_PHY_TYPE_PORT0_SHIFT;
8429 break;
8430 case 1:
a9d41192 8431 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8432 ESPC_PHY_TYPE_PORT1_SHIFT;
8433 break;
8434 case 2:
a9d41192 8435 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8436 ESPC_PHY_TYPE_PORT2_SHIFT;
8437 break;
8438 case 3:
a9d41192 8439 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8440 ESPC_PHY_TYPE_PORT3_SHIFT;
8441 break;
8442 default:
f10a1f2e 8443 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8444 np->port);
8445 return -EINVAL;
8446 }
f10a1f2e
JP		 8447 netif_printk(np, probe, KERN_DEBUG, np->dev,
8448 "SPROM: PHY type %x\n", val8);
a3138df9 8449
a9d41192 8450 switch (val8) {
a3138df9
DM		 8451 case ESPC_PHY_TYPE_1G_COPPER:
8452 /* 1G copper, MII */
8453 np->flags &= ~(NIU_FLAGS_FIBER |
8454 NIU_FLAGS_10G);
8455 np->mac_xcvr = MAC_XCVR_MII;
8456 break;
8457
8458 case ESPC_PHY_TYPE_1G_FIBER:
8459 /* 1G fiber, PCS */
8460 np->flags &= ~NIU_FLAGS_10G;
8461 np->flags |= NIU_FLAGS_FIBER;
8462 np->mac_xcvr = MAC_XCVR_PCS;
8463 break;
8464
8465 case ESPC_PHY_TYPE_10G_COPPER:
8466 /* 10G copper, XPCS */
8467 np->flags |= NIU_FLAGS_10G;
8468 np->flags &= ~NIU_FLAGS_FIBER;
8469 np->mac_xcvr = MAC_XCVR_XPCS;
8470 break;
8471
8472 case ESPC_PHY_TYPE_10G_FIBER:
8473 /* 10G fiber, XPCS */
8474 np->flags |= (NIU_FLAGS_10G |
8475 NIU_FLAGS_FIBER);
8476 np->mac_xcvr = MAC_XCVR_XPCS;
8477 break;
8478
8479 default:
f10a1f2e 8480 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8481 return -EINVAL;
8482 }
8483
8484 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8485 netif_printk(np, probe, KERN_DEBUG, np->dev,
8486 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8487 dev->perm_addr[0] = (val >> 0) & 0xff;
8488 dev->perm_addr[1] = (val >> 8) & 0xff;
8489 dev->perm_addr[2] = (val >> 16) & 0xff;
8490 dev->perm_addr[3] = (val >> 24) & 0xff;
8491
8492 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8493 netif_printk(np, probe, KERN_DEBUG, np->dev,
8494 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8495 dev->perm_addr[4] = (val >> 0) & 0xff;
8496 dev->perm_addr[5] = (val >> 8) & 0xff;
8497
8498 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8499 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8500 dev->perm_addr);
a3138df9
DM		 8501 return -EINVAL;
8502 }
8503
8504 val8 = dev->perm_addr[5];
8505 dev->perm_addr[5] += np->port;
8506 if (dev->perm_addr[5] < val8)
8507 dev->perm_addr[4]++;
8508
8509 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8510
8511 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8512 netif_printk(np, probe, KERN_DEBUG, np->dev,
8513 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8514 if (val >= 8 * 4)
a3138df9
DM		 8515 return -EINVAL;
8516
8517 for (i = 0; i < val; i += 4) {
8518 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8519
8520 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8521 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8522 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8523 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8524 }
8525 np->vpd.model[val] = '\0';
8526
8527 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8528 netif_printk(np, probe, KERN_DEBUG, np->dev,
8529 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8530 if (val >= 4 * 4)
a3138df9
DM		 8531 return -EINVAL;
8532
8533 for (i = 0; i < val; i += 4) {
8534 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8535
8536 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8537 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8538 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8539 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8540 }
8541 np->vpd.board_model[val] = '\0';
8542
8543 np->vpd.mac_num =
8544 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8545 netif_printk(np, probe, KERN_DEBUG, np->dev,
8546 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8547
8548 return 0;
8549}
8550
8551static int __devinit niu_get_and_validate_port(struct niu *np)
8552{
8553 struct niu_parent *parent = np->parent;
8554
8555 if (np->port <= 1)
8556 np->flags |= NIU_FLAGS_XMAC;
8557
8558 if (!parent->num_ports) {
8559 if (parent->plat_type == PLAT_TYPE_NIU) {
8560 parent->num_ports = 2;
8561 } else {
7f7c4072
MW		 8562 parent->num_ports = niu_pci_vpd_get_nports(np);
8563 if (!parent->num_ports) {
8564 /* Fall back to SPROM as last resort.
8565 * This will fail on most cards.
8566 */
8567 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8568 ESPC_NUM_PORTS_MACS_VAL;
8569
be0c007a
DM		 8570 /* All of the current probing methods fail on
8571 * Maramba on-board parts.
8572 */
7f7c4072 8573 if (!parent->num_ports)
be0c007a 8574 parent->num_ports = 4;
7f7c4072 8575 }
a3138df9
DM		 8576 }
8577 }
8578
a3138df9
DM		 8579 if (np->port >= parent->num_ports)
8580 return -ENODEV;
8581
8582 return 0;
8583}
8584
8585static int __devinit phy_record(struct niu_parent *parent,
8586 struct phy_probe_info *p,
8587 int dev_id_1, int dev_id_2, u8 phy_port,
8588 int type)
8589{
8590 u32 id = (dev_id_1 << 16) | dev_id_2;
8591 u8 idx;
8592
8593 if (dev_id_1 < 0 || dev_id_2 < 0)
8594 return 0;
8595 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8596 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8597 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8598 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8599 return 0;
8600 } else {
8601 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8602 return 0;
8603 }
8604
8605 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8606 parent->index, id,
f10a1f2e
JP		 8607 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8608 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8609 phy_port);
8610
8611 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8612 pr_err("Too many PHY ports\n");
a3138df9
DM		 8613 return -EINVAL;
8614 }
8615 idx = p->cur[type];
8616 p->phy_id[type][idx] = id;
8617 p->phy_port[type][idx] = phy_port;
8618 p->cur[type] = idx + 1;
8619 return 0;
8620}
8621
8622static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8623{
8624 int i;
8625
8626 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8627 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8628 return 1;
8629 }
8630 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8631 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8632 return 1;
8633 }
8634
8635 return 0;
8636}
8637
8638static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8639{
8640 int port, cnt;
8641
8642 cnt = 0;
8643 *lowest = 32;
8644 for (port = 8; port < 32; port++) {
8645 if (port_has_10g(p, port)) {
8646 if (!cnt)
8647 *lowest = port;
8648 cnt++;
8649 }
8650 }
8651
8652 return cnt;
8653}
8654
8655static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8656{
8657 *lowest = 32;
8658 if (p->cur[PHY_TYPE_MII])
8659 *lowest = p->phy_port[PHY_TYPE_MII][0];
8660
8661 return p->cur[PHY_TYPE_MII];
8662}
8663
8664static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8665{
8666 int num_ports = parent->num_ports;
8667 int i;
8668
8669 for (i = 0; i < num_ports; i++) {
8670 parent->rxchan_per_port[i] = (16 / num_ports);
8671 parent->txchan_per_port[i] = (16 / num_ports);
8672
f10a1f2e 8673 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8674 parent->index, i,
8675 parent->rxchan_per_port[i],
8676 parent->txchan_per_port[i]);
8677 }
8678}
8679
8680static void __devinit niu_divide_channels(struct niu_parent *parent,
8681 int num_10g, int num_1g)
8682{
8683 int num_ports = parent->num_ports;
8684 int rx_chans_per_10g, rx_chans_per_1g;
8685 int tx_chans_per_10g, tx_chans_per_1g;
8686 int i, tot_rx, tot_tx;
8687
8688 if (!num_10g || !num_1g) {
8689 rx_chans_per_10g = rx_chans_per_1g =
8690 (NIU_NUM_RXCHAN / num_ports);
8691 tx_chans_per_10g = tx_chans_per_1g =
8692 (NIU_NUM_TXCHAN / num_ports);
8693 } else {
8694 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8695 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8696 (rx_chans_per_1g * num_1g)) /
8697 num_10g;
8698
8699 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8700 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8701 (tx_chans_per_1g * num_1g)) /
8702 num_10g;
8703 }
8704
8705 tot_rx = tot_tx = 0;
8706 for (i = 0; i < num_ports; i++) {
8707 int type = phy_decode(parent->port_phy, i);
8708
8709 if (type == PORT_TYPE_10G) {
8710 parent->rxchan_per_port[i] = rx_chans_per_10g;
8711 parent->txchan_per_port[i] = tx_chans_per_10g;
8712 } else {
8713 parent->rxchan_per_port[i] = rx_chans_per_1g;
8714 parent->txchan_per_port[i] = tx_chans_per_1g;
8715 }
f10a1f2e 8716 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8717 parent->index, i,
8718 parent->rxchan_per_port[i],
8719 parent->txchan_per_port[i]);
8720 tot_rx += parent->rxchan_per_port[i];
8721 tot_tx += parent->txchan_per_port[i];
8722 }
8723
8724 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8725 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8726 parent->index, tot_rx);
8727 for (i = 0; i < num_ports; i++)
8728 parent->rxchan_per_port[i] = 1;
8729 }
8730 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8731 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8732 parent->index, tot_tx);
8733 for (i = 0; i < num_ports; i++)
8734 parent->txchan_per_port[i] = 1;
8735 }
8736 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8737 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8738 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8739 }
8740}
8741
8742static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8743 int num_10g, int num_1g)
8744{
8745 int i, num_ports = parent->num_ports;
8746 int rdc_group, rdc_groups_per_port;
8747 int rdc_channel_base;
8748
8749 rdc_group = 0;
8750 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8751
8752 rdc_channel_base = 0;
8753
8754 for (i = 0; i < num_ports; i++) {
8755 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8756 int grp, num_channels = parent->rxchan_per_port[i];
8757 int this_channel_offset;
8758
8759 tp->first_table_num = rdc_group;
8760 tp->num_tables = rdc_groups_per_port;
8761 this_channel_offset = 0;
8762 for (grp = 0; grp < tp->num_tables; grp++) {
8763 struct rdc_table *rt = &tp->tables[grp];
8764 int slot;
8765
f10a1f2e 8766 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8767 parent->index, i, tp->first_table_num + grp);
8768 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8769 rt->rxdma_channel[slot] =
8770 rdc_channel_base + this_channel_offset;
8771
f10a1f2e 8772 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8773
8774 if (++this_channel_offset == num_channels)
8775 this_channel_offset = 0;
8776 }
f10a1f2e 8777 pr_cont("]\n");
a3138df9
DM		 8778 }
8779
8780 parent->rdc_default[i] = rdc_channel_base;
8781
8782 rdc_channel_base += num_channels;
8783 rdc_group += rdc_groups_per_port;
8784 }
8785}
8786
8787static int __devinit fill_phy_probe_info(struct niu *np,
8788 struct niu_parent *parent,
8789 struct phy_probe_info *info)
8790{
8791 unsigned long flags;
8792 int port, err;
8793
8794 memset(info, 0, sizeof(*info));
8795
8796 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8797 niu_lock_parent(np, flags);
8798 err = 0;
8799 for (port = 8; port < 32; port++) {
8800 int dev_id_1, dev_id_2;
8801
8802 dev_id_1 = mdio_read(np, port,
8803 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8804 dev_id_2 = mdio_read(np, port,
8805 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8806 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8807 PHY_TYPE_PMA_PMD);
8808 if (err)
8809 break;
8810 dev_id_1 = mdio_read(np, port,
8811 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8812 dev_id_2 = mdio_read(np, port,
8813 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8814 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8815 PHY_TYPE_PCS);
8816 if (err)
8817 break;
8818 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8819 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8820 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8821 PHY_TYPE_MII);
8822 if (err)
8823 break;
8824 }
8825 niu_unlock_parent(np, flags);
8826
8827 return err;
8828}
8829
8830static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8831{
8832 struct phy_probe_info *info = &parent->phy_probe_info;
8833 int lowest_10g, lowest_1g;
8834 int num_10g, num_1g;
8835 u32 val;
8836 int err;
8837
e3e081e1
SB		 8838 num_10g = num_1g = 0;
8839
f9af8574
MW		 8840 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8841 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8842 num_10g = 0;
8843 num_1g = 2;
8844 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8845 parent->num_ports = 4;
8846 val = (phy_encode(PORT_TYPE_1G, 0) |
8847 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8848 phy_encode(PORT_TYPE_1G, 2) |
8849 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8850 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8851 num_10g = 2;
8852 num_1g = 0;
8853 parent->num_ports = 2;
8854 val = (phy_encode(PORT_TYPE_10G, 0) |
8855 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8856 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8857 (parent->plat_type == PLAT_TYPE_NIU)) {
8858 /* this is the Monza case */
8859 if (np->flags & NIU_FLAGS_10G) {
8860 val = (phy_encode(PORT_TYPE_10G, 0) |
8861 phy_encode(PORT_TYPE_10G, 1));
8862 } else {
8863 val = (phy_encode(PORT_TYPE_1G, 0) |
8864 phy_encode(PORT_TYPE_1G, 1));
8865 }
5fbd7e24
MW		 8866 } else {
8867 err = fill_phy_probe_info(np, parent, info);
8868 if (err)
8869 return err;
a3138df9 8870
5fbd7e24
MW		 8871 num_10g = count_10g_ports(info, &lowest_10g);
8872 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8873
5fbd7e24
MW		 8874 switch ((num_10g << 4) | num_1g) {
8875 case 0x24:
8876 if (lowest_1g == 10)
8877 parent->plat_type = PLAT_TYPE_VF_P0;
8878 else if (lowest_1g == 26)
8879 parent->plat_type = PLAT_TYPE_VF_P1;
8880 else
8881 goto unknown_vg_1g_port;
a3138df9 8882
5fbd7e24
MW		 8883 /* fallthru */
8884 case 0x22:
a3138df9 8885 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8886 phy_encode(PORT_TYPE_10G, 1) |
8887 phy_encode(PORT_TYPE_1G, 2) |
8888 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8889 break;
a3138df9 8890
5fbd7e24
MW		 8891 case 0x20:
8892 val = (phy_encode(PORT_TYPE_10G, 0) |
8893 phy_encode(PORT_TYPE_10G, 1));
8894 break;
a3138df9 8895
5fbd7e24
MW		 8896 case 0x10:
8897 val = phy_encode(PORT_TYPE_10G, np->port);
8898 break;
a3138df9 8899
5fbd7e24
MW		 8900 case 0x14:
8901 if (lowest_1g == 10)
8902 parent->plat_type = PLAT_TYPE_VF_P0;
8903 else if (lowest_1g == 26)
8904 parent->plat_type = PLAT_TYPE_VF_P1;
8905 else
8906 goto unknown_vg_1g_port;
8907
8908 /* fallthru */
8909 case 0x13:
8910 if ((lowest_10g & 0x7) == 0)
8911 val = (phy_encode(PORT_TYPE_10G, 0) |
8912 phy_encode(PORT_TYPE_1G, 1) |
8913 phy_encode(PORT_TYPE_1G, 2) |
8914 phy_encode(PORT_TYPE_1G, 3));
8915 else
8916 val = (phy_encode(PORT_TYPE_1G, 0) |
8917 phy_encode(PORT_TYPE_10G, 1) |
8918 phy_encode(PORT_TYPE_1G, 2) |
8919 phy_encode(PORT_TYPE_1G, 3));
8920 break;
8921
8922 case 0x04:
8923 if (lowest_1g == 10)
8924 parent->plat_type = PLAT_TYPE_VF_P0;
8925 else if (lowest_1g == 26)
8926 parent->plat_type = PLAT_TYPE_VF_P1;
8927 else
8928 goto unknown_vg_1g_port;
8929
8930 val = (phy_encode(PORT_TYPE_1G, 0) |
8931 phy_encode(PORT_TYPE_1G, 1) |
8932 phy_encode(PORT_TYPE_1G, 2) |
8933 phy_encode(PORT_TYPE_1G, 3));
8934 break;
8935
8936 default:
f10a1f2e 8937 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8938 num_10g, num_1g);
8939 return -EINVAL;
8940 }
a3138df9
DM		 8941 }
8942
8943 parent->port_phy = val;
8944
8945 if (parent->plat_type == PLAT_TYPE_NIU)
8946 niu_n2_divide_channels(parent);
8947 else
8948 niu_divide_channels(parent, num_10g, num_1g);
8949
8950 niu_divide_rdc_groups(parent, num_10g, num_1g);
8951
8952 return 0;
8953
8954unknown_vg_1g_port:
f10a1f2e 8955 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8956 return -EINVAL;
8957}
8958
8959static int __devinit niu_probe_ports(struct niu *np)
8960{
8961 struct niu_parent *parent = np->parent;
8962 int err, i;
8963
a3138df9
DM		 8964 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8965 err = walk_phys(np, parent);
8966 if (err)
8967 return err;
8968
8969 niu_set_ldg_timer_res(np, 2);
8970 for (i = 0; i <= LDN_MAX; i++)
8971 niu_ldn_irq_enable(np, i, 0);
8972 }
8973
8974 if (parent->port_phy == PORT_PHY_INVALID)
8975 return -EINVAL;
8976
8977 return 0;
8978}
8979
8980static int __devinit niu_classifier_swstate_init(struct niu *np)
8981{
8982 struct niu_classifier *cp = &np->clas;
8983
2d96cf8c
SB		 8984 cp->tcam_top = (u16) np->port;
8985 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8986 cp->h1_init = 0xffffffff;
8987 cp->h2_init = 0xffff;
8988
8989 return fflp_early_init(np);
8990}
8991
8992static void __devinit niu_link_config_init(struct niu *np)
8993{
8994 struct niu_link_config *lp = &np->link_config;
8995
8996 lp->advertising = (ADVERTISED_10baseT_Half |
8997 ADVERTISED_10baseT_Full |
8998 ADVERTISED_100baseT_Half |
8999 ADVERTISED_100baseT_Full |
9000 ADVERTISED_1000baseT_Half |
9001 ADVERTISED_1000baseT_Full |
9002 ADVERTISED_10000baseT_Full |
9003 ADVERTISED_Autoneg);
9004 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 9005 lp->duplex = DUPLEX_FULL;
9006 lp->active_duplex = DUPLEX_INVALID;
9007 lp->autoneg = 1;
a3138df9
DM		 9008#if 0
9009 lp->loopback_mode = LOOPBACK_MAC;
9010 lp->active_speed = SPEED_10000;
9011 lp->active_duplex = DUPLEX_FULL;
9012#else
9013 lp->loopback_mode = LOOPBACK_DISABLED;
9014#endif
9015}
9016
9017static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9018{
9019 switch (np->port) {
9020 case 0:
9021 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9022 np->ipp_off = 0x00000;
9023 np->pcs_off = 0x04000;
9024 np->xpcs_off = 0x02000;
9025 break;
9026
9027 case 1:
9028 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9029 np->ipp_off = 0x08000;
9030 np->pcs_off = 0x0a000;
9031 np->xpcs_off = 0x08000;
9032 break;
9033
9034 case 2:
9035 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9036 np->ipp_off = 0x04000;
9037 np->pcs_off = 0x0e000;
9038 np->xpcs_off = ~0UL;
9039 break;
9040
9041 case 3:
9042 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9043 np->ipp_off = 0x0c000;
9044 np->pcs_off = 0x12000;
9045 np->xpcs_off = ~0UL;
9046 break;
9047
9048 default:
f10a1f2e 9049 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9050 return -EINVAL;
9051 }
9052
9053 return 0;
9054}
9055
9056static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9057{
9058 struct msix_entry msi_vec[NIU_NUM_LDG];
9059 struct niu_parent *parent = np->parent;
9060 struct pci_dev *pdev = np->pdev;
9061 int i, num_irqs, err;
9062 u8 first_ldg;
9063
9064 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9065 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9066 ldg_num_map[i] = first_ldg + i;
9067
9068 num_irqs = (parent->rxchan_per_port[np->port] +
9069 parent->txchan_per_port[np->port] +
9070 (np->port == 0 ? 3 : 1));
9071 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9072
9073retry:
9074 for (i = 0; i < num_irqs; i++) {
9075 msi_vec[i].vector = 0;
9076 msi_vec[i].entry = i;
9077 }
9078
9079 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9080 if (err < 0) {
9081 np->flags &= ~NIU_FLAGS_MSIX;
9082 return;
9083 }
9084 if (err > 0) {
9085 num_irqs = err;
9086 goto retry;
9087 }
9088
9089 np->flags |= NIU_FLAGS_MSIX;
9090 for (i = 0; i < num_irqs; i++)
9091 np->ldg[i].irq = msi_vec[i].vector;
9092 np->num_ldg = num_irqs;
9093}
9094
9095static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9096{
9097#ifdef CONFIG_SPARC64
2dc11581 9098 struct platform_device *op = np->op;
a3138df9
DM		 9099 const u32 *int_prop;
9100 int i;
9101
61c7a080 9102 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
a3138df9
DM		 9103 if (!int_prop)
9104 return -ENODEV;
9105
1636f8ac 9106 for (i = 0; i < op->archdata.num_irqs; i++) {
a3138df9 9107 ldg_num_map[i] = int_prop[i];
1636f8ac 9108 np->ldg[i].irq = op->archdata.irqs[i];
a3138df9
DM		 9109 }
9110
1636f8ac 9111 np->num_ldg = op->archdata.num_irqs;
a3138df9
DM		 9112
9113 return 0;
9114#else
9115 return -EINVAL;
9116#endif
9117}
9118
9119static int __devinit niu_ldg_init(struct niu *np)
9120{
9121 struct niu_parent *parent = np->parent;
9122 u8 ldg_num_map[NIU_NUM_LDG];
9123 int first_chan, num_chan;
9124 int i, err, ldg_rotor;
9125 u8 port;
9126
9127 np->num_ldg = 1;
9128 np->ldg[0].irq = np->dev->irq;
9129 if (parent->plat_type == PLAT_TYPE_NIU) {
9130 err = niu_n2_irq_init(np, ldg_num_map);
9131 if (err)
9132 return err;
9133 } else
9134 niu_try_msix(np, ldg_num_map);
9135
9136 port = np->port;
9137 for (i = 0; i < np->num_ldg; i++) {
9138 struct niu_ldg *lp = &np->ldg[i];
9139
9140 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9141
9142 lp->np = np;
9143 lp->ldg_num = ldg_num_map[i];
9144 lp->timer = 2; /* XXX */
9145
9146 /* On N2 NIU the firmware has setup the SID mappings so they go
9147 * to the correct values that will route the LDG to the proper
9148 * interrupt in the NCU interrupt table.
9149 */
9150 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9151 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9152 if (err)
9153 return err;
9154 }
9155 }
9156
9157 /* We adopt the LDG assignment ordering used by the N2 NIU
9158 * 'interrupt' properties because that simplifies a lot of
9159 * things. This ordering is:
9160 *
9161 * MAC
9162 * MIF (if port zero)
9163 * SYSERR (if port zero)
9164 * RX channels
9165 * TX channels
9166 */
9167
9168 ldg_rotor = 0;
9169
9170 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9171 LDN_MAC(port));
9172 if (err)
9173 return err;
9174
9175 ldg_rotor++;
9176 if (ldg_rotor == np->num_ldg)
9177 ldg_rotor = 0;
9178
9179 if (port == 0) {
9180 err = niu_ldg_assign_ldn(np, parent,
9181 ldg_num_map[ldg_rotor],
9182 LDN_MIF);
9183 if (err)
9184 return err;
9185
9186 ldg_rotor++;
9187 if (ldg_rotor == np->num_ldg)
9188 ldg_rotor = 0;
9189
9190 err = niu_ldg_assign_ldn(np, parent,
9191 ldg_num_map[ldg_rotor],
9192 LDN_DEVICE_ERROR);
9193 if (err)
9194 return err;
9195
9196 ldg_rotor++;
9197 if (ldg_rotor == np->num_ldg)
9198 ldg_rotor = 0;
9199
9200 }
9201
9202 first_chan = 0;
9203 for (i = 0; i < port; i++)
956837f7 9204 first_chan += parent->rxchan_per_port[i];
a3138df9
DM		 9205 num_chan = parent->rxchan_per_port[port];
9206
9207 for (i = first_chan; i < (first_chan + num_chan); i++) {
9208 err = niu_ldg_assign_ldn(np, parent,
9209 ldg_num_map[ldg_rotor],
9210 LDN_RXDMA(i));
9211 if (err)
9212 return err;
9213 ldg_rotor++;
9214 if (ldg_rotor == np->num_ldg)
9215 ldg_rotor = 0;
9216 }
9217
9218 first_chan = 0;
9219 for (i = 0; i < port; i++)
956837f7 9220 first_chan += parent->txchan_per_port[i];
a3138df9
DM		 9221 num_chan = parent->txchan_per_port[port];
9222 for (i = first_chan; i < (first_chan + num_chan); i++) {
9223 err = niu_ldg_assign_ldn(np, parent,
9224 ldg_num_map[ldg_rotor],
9225 LDN_TXDMA(i));
9226 if (err)
9227 return err;
9228 ldg_rotor++;
9229 if (ldg_rotor == np->num_ldg)
9230 ldg_rotor = 0;
9231 }
9232
9233 return 0;
9234}
9235
9236static void __devexit niu_ldg_free(struct niu *np)
9237{
9238 if (np->flags & NIU_FLAGS_MSIX)
9239 pci_disable_msix(np->pdev);
9240}
9241
9242static int __devinit niu_get_of_props(struct niu *np)
9243{
9244#ifdef CONFIG_SPARC64
9245 struct net_device *dev = np->dev;
9246 struct device_node *dp;
9247 const char *phy_type;
9248 const u8 *mac_addr;
f9af8574 9249 const char *model;
a3138df9
DM		 9250 int prop_len;
9251
9252 if (np->parent->plat_type == PLAT_TYPE_NIU)
61c7a080 9253 dp = np->op->dev.of_node;
a3138df9
DM		 9254 else
9255 dp = pci_device_to_OF_node(np->pdev);
9256
9257 phy_type = of_get_property(dp, "phy-type", &prop_len);
9258 if (!phy_type) {
f10a1f2e
JP		 9259 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9260 dp->full_name);
a3138df9
DM		 9261 return -EINVAL;
9262 }
9263
9264 if (!strcmp(phy_type, "none"))
9265 return -ENODEV;
9266
9267 strcpy(np->vpd.phy_type, phy_type);
9268
9269 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9270 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9271 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9272 return -EINVAL;
9273 }
9274
9275 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9276 if (!mac_addr) {
f10a1f2e
JP		 9277 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9278 dp->full_name);
a3138df9
DM		 9279 return -EINVAL;
9280 }
9281 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9282 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9283 dp->full_name, prop_len);
a3138df9
DM		 9284 }
9285 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9286 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9287 netdev_err(dev, "%s: OF MAC address is invalid\n",
9288 dp->full_name);
9289 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9290 return -EINVAL;
9291 }
9292
9293 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9294
9295 model = of_get_property(dp, "model", &prop_len);
9296
9297 if (model)
9298 strcpy(np->vpd.model, model);
a3138df9 9299
9c5cd670
TC		 9300 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9301 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9302 NIU_FLAGS_HOTPLUG_PHY);
9303 }
9304
a3138df9
DM		 9305 return 0;
9306#else
9307 return -EINVAL;
9308#endif
9309}
9310
9311static int __devinit niu_get_invariants(struct niu *np)
9312{
9313 int err, have_props;
9314 u32 offset;
9315
9316 err = niu_get_of_props(np);
9317 if (err == -ENODEV)
9318 return err;
9319
9320 have_props = !err;
9321
a3138df9
DM		 9322 err = niu_init_mac_ipp_pcs_base(np);
9323 if (err)
9324 return err;
9325
7f7c4072
MW		 9326 if (have_props) {
9327 err = niu_get_and_validate_port(np);
9328 if (err)
9329 return err;
9330
9331 } else {
a3138df9
DM		 9332 if (np->parent->plat_type == PLAT_TYPE_NIU)
9333 return -EINVAL;
9334
9335 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9336 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9337 netif_printk(np, probe, KERN_DEBUG, np->dev,
9338 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9339 if (offset)
9340 niu_pci_vpd_fetch(np, offset);
9341 nw64(ESPC_PIO_EN, 0);
9342
7f7c4072 9343 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9344 niu_pci_vpd_validate(np);
7f7c4072
MW		 9345 err = niu_get_and_validate_port(np);
9346 if (err)
9347 return err;
9348 }
a3138df9
DM		 9349
9350 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9351 err = niu_get_and_validate_port(np);
9352 if (err)
9353 return err;
a3138df9
DM		 9354 err = niu_pci_probe_sprom(np);
9355 if (err)
9356 return err;
9357 }
9358 }
9359
9360 err = niu_probe_ports(np);
9361 if (err)
9362 return err;
9363
9364 niu_ldg_init(np);
9365
9366 niu_classifier_swstate_init(np);
9367 niu_link_config_init(np);
9368
9369 err = niu_determine_phy_disposition(np);
9370 if (!err)
9371 err = niu_init_link(np);
9372
9373 return err;
9374}
9375
9376static LIST_HEAD(niu_parent_list);
9377static DEFINE_MUTEX(niu_parent_lock);
9378static int niu_parent_index;
9379
9380static ssize_t show_port_phy(struct device *dev,
9381 struct device_attribute *attr, char *buf)
9382{
9383 struct platform_device *plat_dev = to_platform_device(dev);
9384 struct niu_parent *p = plat_dev->dev.platform_data;
9385 u32 port_phy = p->port_phy;
9386 char *orig_buf = buf;
9387 int i;
9388
9389 if (port_phy == PORT_PHY_UNKNOWN ||
9390 port_phy == PORT_PHY_INVALID)
9391 return 0;
9392
9393 for (i = 0; i < p->num_ports; i++) {
9394 const char *type_str;
9395 int type;
9396
9397 type = phy_decode(port_phy, i);
9398 if (type == PORT_TYPE_10G)
9399 type_str = "10G";
9400 else
9401 type_str = "1G";
9402 buf += sprintf(buf,
9403 (i == 0) ? "%s" : " %s",
9404 type_str);
9405 }
9406 buf += sprintf(buf, "\n");
9407 return buf - orig_buf;
9408}
9409
9410static ssize_t show_plat_type(struct device *dev,
9411 struct device_attribute *attr, char *buf)
9412{
9413 struct platform_device *plat_dev = to_platform_device(dev);
9414 struct niu_parent *p = plat_dev->dev.platform_data;
9415 const char *type_str;
9416
9417 switch (p->plat_type) {
9418 case PLAT_TYPE_ATLAS:
9419 type_str = "atlas";
9420 break;
9421 case PLAT_TYPE_NIU:
9422 type_str = "niu";
9423 break;
9424 case PLAT_TYPE_VF_P0:
9425 type_str = "vf_p0";
9426 break;
9427 case PLAT_TYPE_VF_P1:
9428 type_str = "vf_p1";
9429 break;
9430 default:
9431 type_str = "unknown";
9432 break;
9433 }
9434
9435 return sprintf(buf, "%s\n", type_str);
9436}
9437
9438static ssize_t __show_chan_per_port(struct device *dev,
9439 struct device_attribute *attr, char *buf,
9440 int rx)
9441{
9442 struct platform_device *plat_dev = to_platform_device(dev);
9443 struct niu_parent *p = plat_dev->dev.platform_data;
9444 char *orig_buf = buf;
9445 u8 *arr;
9446 int i;
9447
9448 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9449
9450 for (i = 0; i < p->num_ports; i++) {
9451 buf += sprintf(buf,
9452 (i == 0) ? "%d" : " %d",
9453 arr[i]);
9454 }
9455 buf += sprintf(buf, "\n");
9456
9457 return buf - orig_buf;
9458}
9459
9460static ssize_t show_rxchan_per_port(struct device *dev,
9461 struct device_attribute *attr, char *buf)
9462{
9463 return __show_chan_per_port(dev, attr, buf, 1);
9464}
9465
9466static ssize_t show_txchan_per_port(struct device *dev,
9467 struct device_attribute *attr, char *buf)
9468{
9469 return __show_chan_per_port(dev, attr, buf, 1);
9470}
9471
9472static ssize_t show_num_ports(struct device *dev,
9473 struct device_attribute *attr, char *buf)
9474{
9475 struct platform_device *plat_dev = to_platform_device(dev);
9476 struct niu_parent *p = plat_dev->dev.platform_data;
9477
9478 return sprintf(buf, "%d\n", p->num_ports);
9479}
9480
9481static struct device_attribute niu_parent_attributes[] = {
9482 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9483 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9484 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9485 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9486 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9487 {}
9488};
9489
9490static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9491 union niu_parent_id *id,
9492 u8 ptype)
9493{
9494 struct platform_device *plat_dev;
9495 struct niu_parent *p;
9496 int i;
9497
a769f496 9498 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
a3138df9 9499 NULL, 0);
58f3e0a8 9500 if (IS_ERR(plat_dev))
a3138df9
DM		 9501 return NULL;
9502
9503 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9504 int err = device_create_file(&plat_dev->dev,
9505 &niu_parent_attributes[i]);
9506 if (err)
9507 goto fail_unregister;
9508 }
9509
9510 p = kzalloc(sizeof(*p), GFP_KERNEL);
9511 if (!p)
9512 goto fail_unregister;
9513
9514 p->index = niu_parent_index++;
9515
9516 plat_dev->dev.platform_data = p;
9517 p->plat_dev = plat_dev;
9518
9519 memcpy(&p->id, id, sizeof(*id));
9520 p->plat_type = ptype;
9521 INIT_LIST_HEAD(&p->list);
9522 atomic_set(&p->refcnt, 0);
9523 list_add(&p->list, &niu_parent_list);
9524 spin_lock_init(&p->lock);
9525
9526 p->rxdma_clock_divider = 7500;
9527
9528 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9529 if (p->plat_type == PLAT_TYPE_NIU)
9530 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9531
9532 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9533 int index = i - CLASS_CODE_USER_PROG1;
9534
9535 p->tcam_key[index] = TCAM_KEY_TSEL;
9536 p->flow_key[index] = (FLOW_KEY_IPSA |
9537 FLOW_KEY_IPDA |
9538 FLOW_KEY_PROTO |
9539 (FLOW_KEY_L4_BYTE12 <<
9540 FLOW_KEY_L4_0_SHIFT) |
9541 (FLOW_KEY_L4_BYTE12 <<
9542 FLOW_KEY_L4_1_SHIFT));
9543 }
9544
9545 for (i = 0; i < LDN_MAX + 1; i++)
9546 p->ldg_map[i] = LDG_INVALID;
9547
9548 return p;
9549
9550fail_unregister:
9551 platform_device_unregister(plat_dev);
9552 return NULL;
9553}
9554
9555static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9556 union niu_parent_id *id,
9557 u8 ptype)
9558{
9559 struct niu_parent *p, *tmp;
9560 int port = np->port;
9561
a3138df9
DM		 9562 mutex_lock(&niu_parent_lock);
9563 p = NULL;
9564 list_for_each_entry(tmp, &niu_parent_list, list) {
9565 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9566 p = tmp;
9567 break;
9568 }
9569 }
9570 if (!p)
9571 p = niu_new_parent(np, id, ptype);
9572
9573 if (p) {
9574 char port_name[6];
9575 int err;
9576
9577 sprintf(port_name, "port%d", port);
9578 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9579 &np->device->kobj,
9580 port_name);
9581 if (!err) {
9582 p->ports[port] = np;
9583 atomic_inc(&p->refcnt);
9584 }
9585 }
9586 mutex_unlock(&niu_parent_lock);
9587
9588 return p;
9589}
9590
9591static void niu_put_parent(struct niu *np)
9592{
9593 struct niu_parent *p = np->parent;
9594 u8 port = np->port;
9595 char port_name[6];
9596
9597 BUG_ON(!p || p->ports[port] != np);
9598
f10a1f2e
JP		 9599 netif_printk(np, probe, KERN_DEBUG, np->dev,
9600 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9601
9602 sprintf(port_name, "port%d", port);
9603
9604 mutex_lock(&niu_parent_lock);
9605
9606 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9607
9608 p->ports[port] = NULL;
9609 np->parent = NULL;
9610
9611 if (atomic_dec_and_test(&p->refcnt)) {
9612 list_del(&p->list);
9613 platform_device_unregister(p->plat_dev);
9614 }
9615
9616 mutex_unlock(&niu_parent_lock);
9617}
9618
9619static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9620 u64 *handle, gfp_t flag)
9621{
9622 dma_addr_t dh;
9623 void *ret;
9624
9625 ret = dma_alloc_coherent(dev, size, &dh, flag);
9626 if (ret)
9627 *handle = dh;
9628 return ret;
9629}
9630
9631static void niu_pci_free_coherent(struct device *dev, size_t size,
9632 void *cpu_addr, u64 handle)
9633{
9634 dma_free_coherent(dev, size, cpu_addr, handle);
9635}
9636
9637static u64 niu_pci_map_page(struct device *dev, struct page *page,
9638 unsigned long offset, size_t size,
9639 enum dma_data_direction direction)
9640{
9641 return dma_map_page(dev, page, offset, size, direction);
9642}
9643
9644static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9645 size_t size, enum dma_data_direction direction)
9646{
a08b32df 9647 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9648}
9649
9650static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9651 size_t size,
9652 enum dma_data_direction direction)
9653{
9654 return dma_map_single(dev, cpu_addr, size, direction);
9655}
9656
9657static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9658 size_t size,
9659 enum dma_data_direction direction)
9660{
9661 dma_unmap_single(dev, dma_address, size, direction);
9662}
9663
9664static const struct niu_ops niu_pci_ops = {
9665 .alloc_coherent = niu_pci_alloc_coherent,
9666 .free_coherent = niu_pci_free_coherent,
9667 .map_page = niu_pci_map_page,
9668 .unmap_page = niu_pci_unmap_page,
9669 .map_single = niu_pci_map_single,
9670 .unmap_single = niu_pci_unmap_single,
9671};
9672
9673static void __devinit niu_driver_version(void)
9674{
9675 static int niu_version_printed;
9676
9677 if (niu_version_printed++ == 0)
9678 pr_info("%s", version);
9679}
9680
9681static struct net_device * __devinit niu_alloc_and_init(
9682 struct device *gen_dev, struct pci_dev *pdev,
2dc11581 9683 struct platform_device *op, const struct niu_ops *ops,
a3138df9
DM		 9684 u8 port)
9685{
b4c21639 9686 struct net_device *dev;
a3138df9
DM		 9687 struct niu *np;
9688
b4c21639 9689 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9690 if (!dev) {
f10a1f2e 9691 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9692 return NULL;
9693 }
9694
9695 SET_NETDEV_DEV(dev, gen_dev);
9696
9697 np = netdev_priv(dev);
9698 np->dev = dev;
9699 np->pdev = pdev;
9700 np->op = op;
9701 np->device = gen_dev;
9702 np->ops = ops;
9703
9704 np->msg_enable = niu_debug;
9705
9706 spin_lock_init(&np->lock);
9707 INIT_WORK(&np->reset_task, niu_reset_task);
9708
9709 np->port = port;
9710
9711 return dev;
9712}
9713
2c9171d4
SH		 9714static const struct net_device_ops niu_netdev_ops = {
9715 .ndo_open = niu_open,
9716 .ndo_stop = niu_close,
00829823 9717 .ndo_start_xmit = niu_start_xmit,
1a7a1032 9718 .ndo_get_stats64 = niu_get_stats,
01789349 9719 .ndo_set_rx_mode = niu_set_rx_mode,
2c9171d4
SH		 9720 .ndo_validate_addr = eth_validate_addr,
9721 .ndo_set_mac_address = niu_set_mac_addr,
9722 .ndo_do_ioctl = niu_ioctl,
9723 .ndo_tx_timeout = niu_tx_timeout,
9724 .ndo_change_mtu = niu_change_mtu,
9725};
9726
a3138df9
DM		 9727static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9728{
2c9171d4 9729 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9730 dev->ethtool_ops = &niu_ethtool_ops;
9731 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9732}
9733
9734static void __devinit niu_device_announce(struct niu *np)
9735{
9736 struct net_device *dev = np->dev;
a3138df9 9737
e174961c 9738 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9739
5fbd7e24
MW		 9740 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9741 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9742 dev->name,
9743 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9744 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9745 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9746 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9747 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9748 np->vpd.phy_type);
9749 } else {
9750 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9751 dev->name,
9752 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9753 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9754 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9755 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9756 "COPPER")),
5fbd7e24
MW		 9757 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9758 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9759 np->vpd.phy_type);
9760 }
a3138df9
DM		 9761}
9762
3cfa856d
DM		 9763static void __devinit niu_set_basic_features(struct net_device *dev)
9764{
3cd8ef4b
MM		 9765 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9766 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
3cfa856d
DM		 9767}
9768
a3138df9
DM		 9769static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9770 const struct pci_device_id *ent)
9771{
a3138df9
DM		 9772 union niu_parent_id parent_id;
9773 struct net_device *dev;
9774 struct niu *np;
9775 int err, pos;
9776 u64 dma_mask;
9777 u16 val16;
9778
9779 niu_driver_version();
9780
9781 err = pci_enable_device(pdev);
9782 if (err) {
f10a1f2e 9783 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9784 return err;
9785 }
9786
9787 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9788 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9789 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9790 err = -ENODEV;
9791 goto err_out_disable_pdev;
9792 }
9793
9794 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9795 if (err) {
f10a1f2e 9796 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9797 goto err_out_disable_pdev;
9798 }
9799
d3aa0cb4 9800 pos = pci_pcie_cap(pdev);
a3138df9 9801 if (pos <= 0) {
f10a1f2e 9802 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9803 goto err_out_free_res;
9804 }
9805
9806 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9807 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9808 if (!dev) {
9809 err = -ENOMEM;
9810 goto err_out_free_res;
9811 }
9812 np = netdev_priv(dev);
9813
9814 memset(&parent_id, 0, sizeof(parent_id));
9815 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9816 parent_id.pci.bus = pdev->bus->number;
9817 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9818
9819 np->parent = niu_get_parent(np, &parent_id,
9820 PLAT_TYPE_ATLAS);
9821 if (!np->parent) {
9822 err = -ENOMEM;
9823 goto err_out_free_dev;
9824 }
9825
9826 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9827 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9828 val16 |= (PCI_EXP_DEVCTL_CERE |
9829 PCI_EXP_DEVCTL_NFERE |
9830 PCI_EXP_DEVCTL_FERE |
9831 PCI_EXP_DEVCTL_URRE |
9832 PCI_EXP_DEVCTL_RELAX_EN);
9833 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9834
8cbd9623 9835 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9836 err = pci_set_dma_mask(pdev, dma_mask);
9837 if (!err) {
9838 dev->features |= NETIF_F_HIGHDMA;
9839 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9840 if (err) {
f10a1f2e 9841 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9842 goto err_out_release_parent;
9843 }
9844 }
284901a9
YH		 9845 if (err || dma_mask == DMA_BIT_MASK(32)) {
9846 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9847 if (err) {
f10a1f2e 9848 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9849 goto err_out_release_parent;
9850 }
9851 }
9852
3cfa856d 9853 niu_set_basic_features(dev);
a3138df9 9854
01789349
JP		 9855 dev->priv_flags |= IFF_UNICAST_FLT;
9856
19ecb6ba 9857 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9858 if (!np->regs) {
f10a1f2e 9859 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9860 err = -ENOMEM;
9861 goto err_out_release_parent;
9862 }
9863
9864 pci_set_master(pdev);
9865 pci_save_state(pdev);
9866
9867 dev->irq = pdev->irq;
9868
9869 niu_assign_netdev_ops(dev);
9870
9871 err = niu_get_invariants(np);
9872 if (err) {
9873 if (err != -ENODEV)
f10a1f2e 9874 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9875 goto err_out_iounmap;
9876 }
9877
9878 err = register_netdev(dev);
9879 if (err) {
f10a1f2e 9880 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9881 goto err_out_iounmap;
9882 }
9883
9884 pci_set_drvdata(pdev, dev);
9885
9886 niu_device_announce(np);
9887
9888 return 0;
9889
9890err_out_iounmap:
9891 if (np->regs) {
9892 iounmap(np->regs);
9893 np->regs = NULL;
9894 }
9895
9896err_out_release_parent:
9897 niu_put_parent(np);
9898
9899err_out_free_dev:
9900 free_netdev(dev);
9901
9902err_out_free_res:
9903 pci_release_regions(pdev);
9904
9905err_out_disable_pdev:
9906 pci_disable_device(pdev);
9907 pci_set_drvdata(pdev, NULL);
9908
9909 return err;
9910}
9911
9912static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9913{
9914 struct net_device *dev = pci_get_drvdata(pdev);
9915
9916 if (dev) {
9917 struct niu *np = netdev_priv(dev);
9918
9919 unregister_netdev(dev);
9920 if (np->regs) {
9921 iounmap(np->regs);
9922 np->regs = NULL;
9923 }
9924
9925 niu_ldg_free(np);
9926
9927 niu_put_parent(np);
9928
9929 free_netdev(dev);
9930 pci_release_regions(pdev);
9931 pci_disable_device(pdev);
9932 pci_set_drvdata(pdev, NULL);
9933 }
9934}
9935
9936static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9937{
9938 struct net_device *dev = pci_get_drvdata(pdev);
9939 struct niu *np = netdev_priv(dev);
9940 unsigned long flags;
9941
9942 if (!netif_running(dev))
9943 return 0;
9944
23f333a2 9945 flush_work_sync(&np->reset_task);
a3138df9
DM		 9946 niu_netif_stop(np);
9947
9948 del_timer_sync(&np->timer);
9949
9950 spin_lock_irqsave(&np->lock, flags);
9951 niu_enable_interrupts(np, 0);
9952 spin_unlock_irqrestore(&np->lock, flags);
9953
9954 netif_device_detach(dev);
9955
9956 spin_lock_irqsave(&np->lock, flags);
9957 niu_stop_hw(np);
9958 spin_unlock_irqrestore(&np->lock, flags);
9959
9960 pci_save_state(pdev);
9961
9962 return 0;
9963}
9964
9965static int niu_resume(struct pci_dev *pdev)
9966{
9967 struct net_device *dev = pci_get_drvdata(pdev);
9968 struct niu *np = netdev_priv(dev);
9969 unsigned long flags;
9970 int err;
9971
9972 if (!netif_running(dev))
9973 return 0;
9974
9975 pci_restore_state(pdev);
9976
9977 netif_device_attach(dev);
9978
9979 spin_lock_irqsave(&np->lock, flags);
9980
9981 err = niu_init_hw(np);
9982 if (!err) {
9983 np->timer.expires = jiffies + HZ;
9984 add_timer(&np->timer);
9985 niu_netif_start(np);
9986 }
9987
9988 spin_unlock_irqrestore(&np->lock, flags);
9989
9990 return err;
9991}
9992
9993static struct pci_driver niu_pci_driver = {
9994 .name = DRV_MODULE_NAME,
9995 .id_table = niu_pci_tbl,
9996 .probe = niu_pci_init_one,
9997 .remove = __devexit_p(niu_pci_remove_one),
9998 .suspend = niu_suspend,
9999 .resume = niu_resume,
10000};
10001
10002#ifdef CONFIG_SPARC64
10003static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10004 u64 *dma_addr, gfp_t flag)
10005{
10006 unsigned long order = get_order(size);
10007 unsigned long page = __get_free_pages(flag, order);
10008
10009 if (page == 0UL)
10010 return NULL;
10011 memset((char *)page, 0, PAGE_SIZE << order);
10012 *dma_addr = __pa(page);
10013
10014 return (void *) page;
10015}
10016
10017static void niu_phys_free_coherent(struct device *dev, size_t size,
10018 void *cpu_addr, u64 handle)
10019{
10020 unsigned long order = get_order(size);
10021
10022 free_pages((unsigned long) cpu_addr, order);
10023}
10024
10025static u64 niu_phys_map_page(struct device *dev, struct page *page,
10026 unsigned long offset, size_t size,
10027 enum dma_data_direction direction)
10028{
10029 return page_to_phys(page) + offset;
10030}
10031
10032static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10033 size_t size, enum dma_data_direction direction)
10034{
10035 /* Nothing to do. */
10036}
10037
10038static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10039 size_t size,
10040 enum dma_data_direction direction)
10041{
10042 return __pa(cpu_addr);
10043}
10044
10045static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10046 size_t size,
10047 enum dma_data_direction direction)
10048{
10049 /* Nothing to do. */
10050}
10051
10052static const struct niu_ops niu_phys_ops = {
10053 .alloc_coherent = niu_phys_alloc_coherent,
10054 .free_coherent = niu_phys_free_coherent,
10055 .map_page = niu_phys_map_page,
10056 .unmap_page = niu_phys_unmap_page,
10057 .map_single = niu_phys_map_single,
10058 .unmap_single = niu_phys_unmap_single,
10059};
10060
74888760 10061static int __devinit niu_of_probe(struct platform_device *op)
a3138df9
DM		 10062{
10063 union niu_parent_id parent_id;
10064 struct net_device *dev;
10065 struct niu *np;
10066 const u32 *reg;
10067 int err;
10068
10069 niu_driver_version();
10070
61c7a080 10071 reg = of_get_property(op->dev.of_node, "reg", NULL);
a3138df9 10072 if (!reg) {
f10a1f2e 10073 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
61c7a080 10074 op->dev.of_node->full_name);
a3138df9
DM		 10075 return -ENODEV;
10076 }
10077
10078 dev = niu_alloc_and_init(&op->dev, NULL, op,
10079 &niu_phys_ops, reg[0] & 0x1);
10080 if (!dev) {
10081 err = -ENOMEM;
10082 goto err_out;
10083 }
10084 np = netdev_priv(dev);
10085
10086 memset(&parent_id, 0, sizeof(parent_id));
61c7a080 10087 parent_id.of = of_get_parent(op->dev.of_node);
a3138df9
DM		 10088
10089 np->parent = niu_get_parent(np, &parent_id,
10090 PLAT_TYPE_NIU);
10091 if (!np->parent) {
10092 err = -ENOMEM;
10093 goto err_out_free_dev;
10094 }
10095
3cfa856d 10096 niu_set_basic_features(dev);
a3138df9
DM		 10097
10098 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10099 resource_size(&op->resource[1]),
a3138df9
DM		 10100 "niu regs");
10101 if (!np->regs) {
f10a1f2e 10102 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10103 err = -ENOMEM;
10104 goto err_out_release_parent;
10105 }
10106
10107 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10108 resource_size(&op->resource[2]),
a3138df9
DM		 10109 "niu vregs-1");
10110 if (!np->vir_regs_1) {
f10a1f2e 10111 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10112 err = -ENOMEM;
10113 goto err_out_iounmap;
10114 }
10115
10116 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10117 resource_size(&op->resource[3]),
a3138df9
DM		 10118 "niu vregs-2");
10119 if (!np->vir_regs_2) {
f10a1f2e 10120 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10121 err = -ENOMEM;
10122 goto err_out_iounmap;
10123 }
10124
10125 niu_assign_netdev_ops(dev);
10126
10127 err = niu_get_invariants(np);
10128 if (err) {
10129 if (err != -ENODEV)
f10a1f2e 10130 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10131 goto err_out_iounmap;
10132 }
10133
10134 err = register_netdev(dev);
10135 if (err) {
f10a1f2e 10136 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10137 goto err_out_iounmap;
10138 }
10139
10140 dev_set_drvdata(&op->dev, dev);
10141
10142 niu_device_announce(np);
10143
10144 return 0;
10145
10146err_out_iounmap:
10147 if (np->vir_regs_1) {
10148 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10149 resource_size(&op->resource[2]));
a3138df9
DM		 10150 np->vir_regs_1 = NULL;
10151 }
10152
10153 if (np->vir_regs_2) {
10154 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10155 resource_size(&op->resource[3]));
a3138df9
DM		 10156 np->vir_regs_2 = NULL;
10157 }
10158
10159 if (np->regs) {
10160 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10161 resource_size(&op->resource[1]));
a3138df9
DM		 10162 np->regs = NULL;
10163 }
10164
10165err_out_release_parent:
10166 niu_put_parent(np);
10167
10168err_out_free_dev:
10169 free_netdev(dev);
10170
10171err_out:
10172 return err;
10173}
10174
2dc11581 10175static int __devexit niu_of_remove(struct platform_device *op)
a3138df9
DM		 10176{
10177 struct net_device *dev = dev_get_drvdata(&op->dev);
10178
10179 if (dev) {
10180 struct niu *np = netdev_priv(dev);
10181
10182 unregister_netdev(dev);
10183
10184 if (np->vir_regs_1) {
10185 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10186 resource_size(&op->resource[2]));
a3138df9
DM		 10187 np->vir_regs_1 = NULL;
10188 }
10189
10190 if (np->vir_regs_2) {
10191 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10192 resource_size(&op->resource[3]));
a3138df9
DM		 10193 np->vir_regs_2 = NULL;
10194 }
10195
10196 if (np->regs) {
10197 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10198 resource_size(&op->resource[1]));
a3138df9
DM		 10199 np->regs = NULL;
10200 }
10201
10202 niu_ldg_free(np);
10203
10204 niu_put_parent(np);
10205
10206 free_netdev(dev);
10207 dev_set_drvdata(&op->dev, NULL);
10208 }
10209 return 0;
10210}
10211
fd098316 10212static const struct of_device_id niu_match[] = {
a3138df9
DM		 10213 {
10214 .name = "network",
10215 .compatible = "SUNW,niusl",
10216 },
10217 {},
10218};
10219MODULE_DEVICE_TABLE(of, niu_match);
10220
74888760 10221static struct platform_driver niu_of_driver = {
4018294b
GL		 10222 .driver = {
10223 .name = "niu",
10224 .owner = THIS_MODULE,
10225 .of_match_table = niu_match,
10226 },
a3138df9
DM		 10227 .probe = niu_of_probe,
10228 .remove = __devexit_p(niu_of_remove),
10229};
10230
10231#endif /* CONFIG_SPARC64 */
10232
10233static int __init niu_init(void)
10234{
10235 int err = 0;
10236
81429973 10237 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10238
10239 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10240
10241#ifdef CONFIG_SPARC64
74888760 10242 err = platform_driver_register(&niu_of_driver);
a3138df9
DM		 10243#endif
10244
10245 if (!err) {
10246 err = pci_register_driver(&niu_pci_driver);
10247#ifdef CONFIG_SPARC64
10248 if (err)
74888760 10249 platform_driver_unregister(&niu_of_driver);
a3138df9
DM		 10250#endif
10251 }
10252
10253 return err;
10254}
10255
10256static void __exit niu_exit(void)
10257{
10258 pci_unregister_driver(&niu_pci_driver);
10259#ifdef CONFIG_SPARC64
74888760 10260 platform_driver_unregister(&niu_of_driver);
a3138df9
DM		 10261#endif
10262}
10263
10264module_init(niu_init);
10265module_exit(niu_exit);
kernel source for telekom puls (alcatel/mediatek)