[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_hwtstamp.c

/*******************************************************************************
  Copyright (C) 2013  Vayavya Labs Pvt Ltd

  This implements all the API for managing HW timestamp & PTP.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/io.h>
#include <linux/delay.h>
#include "common.h"
#include "stmmac_ptp.h"

static void stmmac_config_hw_tstamping(void __iomem *ioaddr, u32 data)
{
	writel(data, ioaddr + PTP_TCR);
}

static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr,
					      u32 ptp_clock, int gmac4)
{
	u32 value = readl(ioaddr + PTP_TCR);
	unsigned long data;
	u32 reg_value;

	/* For GMAC3.x, 4.x versions, convert the ptp_clock to nano second
	 *	formula = (1/ptp_clock) * 1000000000
	 * where ptp_clock is 50MHz if fine method is used to update system
	 */
	if (value & PTP_TCR_TSCFUPDT)
		data = (1000000000ULL / 50000000);
	else
		data = (1000000000ULL / ptp_clock);

	/* 0.465ns accuracy */
	if (!(value & PTP_TCR_TSCTRLSSR))
		data = (data * 1000) / 465;

	data &= PTP_SSIR_SSINC_MASK;

	reg_value = data;
	if (gmac4)
		reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;

	writel(reg_value, ioaddr + PTP_SSIR);

	return data;
}

static int stmmac_init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
{
	int limit;
	u32 value;

	writel(sec, ioaddr + PTP_STSUR);
	writel(nsec, ioaddr + PTP_STNSUR);
	/* issue command to initialize the system time value */
	value = readl(ioaddr + PTP_TCR);
	value |= PTP_TCR_TSINIT;
	writel(value, ioaddr + PTP_TCR);

	/* wait for present system time initialize to complete */
	limit = 10;
	while (limit--) {
		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSINIT))
			break;
		mdelay(10);
	}
	if (limit < 0)
		return -EBUSY;

	return 0;
}

static int stmmac_config_addend(void __iomem *ioaddr, u32 addend)
{
	u32 value;
	int limit;

	writel(addend, ioaddr + PTP_TAR);
	/* issue command to update the addend value */
	value = readl(ioaddr + PTP_TCR);
	value |= PTP_TCR_TSADDREG;
	writel(value, ioaddr + PTP_TCR);

	/* wait for present addend update to complete */
	limit = 10;
	while (limit--) {
		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
			break;
		mdelay(10);
	}
	if (limit < 0)
		return -EBUSY;

	return 0;
}

static int stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
				 int add_sub, int gmac4)
{
	u32 value;
	int limit;

	if (add_sub) {
		/* If the new sec value needs to be subtracted with
		 * the system time, then MAC_STSUR reg should be
		 * programmed with (2^32 – <new_sec_value>)
		 */
		if (gmac4)
			sec = (100000000ULL - sec);

		value = readl(ioaddr + PTP_TCR);
		if (value & PTP_TCR_TSCTRLSSR)
			nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
		else
			nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
	}

	writel(sec, ioaddr + PTP_STSUR);
	value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
	writel(value, ioaddr + PTP_STNSUR);

	/* issue command to initialize the system time value */
	value = readl(ioaddr + PTP_TCR);
	value |= PTP_TCR_TSUPDT;
	writel(value, ioaddr + PTP_TCR);

	/* wait for present system time adjust/update to complete */
	limit = 10;
	while (limit--) {
		if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
			break;
		mdelay(10);
	}
	if (limit < 0)
		return -EBUSY;

	return 0;
}

static u64 stmmac_get_systime(void __iomem *ioaddr)
{
	u64 ns;

	/* Get the TSSS value */
	ns = readl(ioaddr + PTP_STNSR);
	/* Get the TSS and convert sec time value to nanosecond */
	ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;

	return ns;
}

const struct stmmac_hwtimestamp stmmac_ptp = {
	.config_hw_tstamping = stmmac_config_hw_tstamping,
	.init_systime = stmmac_init_systime,
	.config_sub_second_increment = stmmac_config_sub_second_increment,
	.config_addend = stmmac_config_addend,
	.adjust_systime = stmmac_adjust_systime,
	.get_systime = stmmac_get_systime,
};
Commit	Line	Data
891434b1 RK	1	/*******************************************************************************
	2	Copyright (C) 2013 Vayavya Labs Pvt Ltd
	3
	4	This implements all the API for managing HW timestamp & PTP.
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
891434b1 RK	15	The full GNU General Public License is included in this distribution in
	16	the file called "COPYING".
	17
	18	Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
	19	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	20	*******************************************************************************/
	21
	22	#include <linux/io.h>
	23	#include <linux/delay.h>
	24	#include "common.h"
	25	#include "stmmac_ptp.h"
	26
	27	static void stmmac_config_hw_tstamping(void __iomem *ioaddr, u32 data)
	28	{
	29	writel(data, ioaddr + PTP_TCR);
	30	}
	31
19d857c9	32	static u32 stmmac_config_sub_second_increment(void __iomem *ioaddr,
ba1ffd74	33	u32 ptp_clock, int gmac4)
891434b1 RK	34	{
	35	u32 value = readl(ioaddr + PTP_TCR);
	36	unsigned long data;
06dcd2d7	37	u32 reg_value;
891434b1	38
ba1ffd74 GC	39	/* For GMAC3.x, 4.x versions, convert the ptp_clock to nano second
	40	* formula = (1/ptp_clock) * 1000000000
	41	* where ptp_clock is 50MHz if fine method is used to update system
891434b1	42	*/
ba1ffd74 GC	43	if (value & PTP_TCR_TSCFUPDT)
	44	data = (1000000000ULL / 50000000);
	45	else
	46	data = (1000000000ULL / ptp_clock);
891434b1 RK	47
891434b1 RK	48	/* 0.465ns accuracy */
0cf91580 SZ	49	if (!(value & PTP_TCR_TSCTRLSSR))
0cf91580 SZ	50	data = (data * 1000) / 465;
891434b1	51
ba1ffd74 GC	52	data &= PTP_SSIR_SSINC_MASK;
ba1ffd74 GC	53
06dcd2d7	54	reg_value = data;
ba1ffd74	55	if (gmac4)
06dcd2d7	56	reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
ba1ffd74	57
06dcd2d7	58	writel(reg_value, ioaddr + PTP_SSIR);
19d857c9 PR	59
19d857c9 PR	60	return data;
891434b1 RK	61	}
	62
	63	static int stmmac_init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
	64	{
	65	int limit;
	66	u32 value;
	67
	68	writel(sec, ioaddr + PTP_STSUR);
	69	writel(nsec, ioaddr + PTP_STNSUR);
	70	/* issue command to initialize the system time value */
	71	value = readl(ioaddr + PTP_TCR);
	72	value \|= PTP_TCR_TSINIT;
	73	writel(value, ioaddr + PTP_TCR);
	74
	75	/* wait for present system time initialize to complete */
	76	limit = 10;
	77	while (limit--) {
	78	if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSINIT))
	79	break;
	80	mdelay(10);
	81	}
	82	if (limit < 0)
	83	return -EBUSY;
	84
	85	return 0;
	86	}
	87
	88	static int stmmac_config_addend(void __iomem *ioaddr, u32 addend)
	89	{
	90	u32 value;
	91	int limit;
	92
	93	writel(addend, ioaddr + PTP_TAR);
	94	/* issue command to update the addend value */
	95	value = readl(ioaddr + PTP_TCR);
	96	value \|= PTP_TCR_TSADDREG;
	97	writel(value, ioaddr + PTP_TCR);
	98
	99	/* wait for present addend update to complete */
	100	limit = 10;
	101	while (limit--) {
	102	if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
	103	break;
	104	mdelay(10);
	105	}
	106	if (limit < 0)
	107	return -EBUSY;
	108
	109	return 0;
	110	}
	111
92ba6888	112	static int stmmac_adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
ba1ffd74	113	int add_sub, int gmac4)
92ba6888 RK	114	{
	115	u32 value;
	116	int limit;
	117
ba1ffd74 GC	118	if (add_sub) {
	119	/* If the new sec value needs to be subtracted with
	120	* the system time, then MAC_STSUR reg should be
	121	* programmed with (2^32 – <new_sec_value>)
	122	*/
	123	if (gmac4)
	124	sec = (100000000ULL - sec);
	125
	126	value = readl(ioaddr + PTP_TCR);
	127	if (value & PTP_TCR_TSCTRLSSR)
	128	nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
	129	else
	130	nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
	131	}
	132
92ba6888	133	writel(sec, ioaddr + PTP_STSUR);
ba1ffd74 GC	134	value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) \| nsec;
	135	writel(value, ioaddr + PTP_STNSUR);
	136
92ba6888 RK	137	/* issue command to initialize the system time value */
	138	value = readl(ioaddr + PTP_TCR);
	139	value \|= PTP_TCR_TSUPDT;
	140	writel(value, ioaddr + PTP_TCR);
	141
	142	/* wait for present system time adjust/update to complete */
	143	limit = 10;
	144	while (limit--) {
	145	if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
	146	break;
	147	mdelay(10);
	148	}
	149	if (limit < 0)
	150	return -EBUSY;
	151
	152	return 0;
	153	}
	154
	155	static u64 stmmac_get_systime(void __iomem *ioaddr)
	156	{
	157	u64 ns;
	158
ba1ffd74	159	/* Get the TSSS value */
92ba6888	160	ns = readl(ioaddr + PTP_STNSR);
ba1ffd74	161	/* Get the TSS and convert sec time value to nanosecond */
92ba6888 RK	162	ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;
	163
	164	return ns;
	165	}
	166
891434b1 RK	167	const struct stmmac_hwtimestamp stmmac_ptp = {
	168	.config_hw_tstamping = stmmac_config_hw_tstamping,
	169	.init_systime = stmmac_init_systime,
	170	.config_sub_second_increment = stmmac_config_sub_second_increment,
	171	.config_addend = stmmac_config_addend,
92ba6888 RK	172	.adjust_systime = stmmac_adjust_systime,
92ba6888 RK	173	.get_systime = stmmac_get_systime,
891434b1	174	};