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afd4aea0 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2006-2010 Solarflare Communications Inc. |
afd4aea0 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d614cfbc | 16 | #include <linux/random.h> |
afd4aea0 BH |
17 | #include "net_driver.h" |
18 | #include "bitfield.h" | |
19 | #include "efx.h" | |
20 | #include "nic.h" | |
afd4aea0 BH |
21 | #include "spi.h" |
22 | #include "regs.h" | |
23 | #include "io.h" | |
24 | #include "phy.h" | |
25 | #include "workarounds.h" | |
26 | #include "mcdi.h" | |
27 | #include "mcdi_pcol.h" | |
d4f2cecc | 28 | #include "selftest.h" |
afd4aea0 BH |
29 | |
30 | /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ | |
31 | ||
32 | static void siena_init_wol(struct efx_nic *efx); | |
d4f2cecc | 33 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method); |
afd4aea0 BH |
34 | |
35 | ||
36 | static void siena_push_irq_moderation(struct efx_channel *channel) | |
37 | { | |
38 | efx_dword_t timer_cmd; | |
39 | ||
40 | if (channel->irq_moderation) | |
41 | EFX_POPULATE_DWORD_2(timer_cmd, | |
42 | FRF_CZ_TC_TIMER_MODE, | |
43 | FFE_CZ_TIMER_MODE_INT_HLDOFF, | |
44 | FRF_CZ_TC_TIMER_VAL, | |
45 | channel->irq_moderation - 1); | |
46 | else | |
47 | EFX_POPULATE_DWORD_2(timer_cmd, | |
48 | FRF_CZ_TC_TIMER_MODE, | |
49 | FFE_CZ_TIMER_MODE_DIS, | |
50 | FRF_CZ_TC_TIMER_VAL, 0); | |
51 | efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, | |
52 | channel->channel); | |
53 | } | |
54 | ||
afd4aea0 BH |
55 | static int siena_mdio_write(struct net_device *net_dev, |
56 | int prtad, int devad, u16 addr, u16 value) | |
57 | { | |
58 | struct efx_nic *efx = netdev_priv(net_dev); | |
59 | uint32_t status; | |
60 | int rc; | |
61 | ||
62 | rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad, | |
63 | addr, value, &status); | |
64 | if (rc) | |
65 | return rc; | |
66 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
67 | return -EIO; | |
68 | ||
69 | return 0; | |
70 | } | |
71 | ||
72 | static int siena_mdio_read(struct net_device *net_dev, | |
73 | int prtad, int devad, u16 addr) | |
74 | { | |
75 | struct efx_nic *efx = netdev_priv(net_dev); | |
76 | uint16_t value; | |
77 | uint32_t status; | |
78 | int rc; | |
79 | ||
80 | rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad, | |
81 | addr, &value, &status); | |
82 | if (rc) | |
83 | return rc; | |
84 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
85 | return -EIO; | |
86 | ||
87 | return (int)value; | |
88 | } | |
89 | ||
90 | /* This call is responsible for hooking in the MAC and PHY operations */ | |
91 | static int siena_probe_port(struct efx_nic *efx) | |
92 | { | |
93 | int rc; | |
94 | ||
95 | /* Hook in PHY operations table */ | |
96 | efx->phy_op = &efx_mcdi_phy_ops; | |
97 | ||
98 | /* Set up MDIO structure for PHY */ | |
99 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
100 | efx->mdio.mdio_read = siena_mdio_read; | |
101 | efx->mdio.mdio_write = siena_mdio_write; | |
102 | ||
7a6b8f6f | 103 | /* Fill out MDIO structure, loopback modes, and initial link state */ |
afd4aea0 BH |
104 | rc = efx->phy_op->probe(efx); |
105 | if (rc != 0) | |
106 | return rc; | |
107 | ||
afd4aea0 BH |
108 | /* Allocate buffer for stats */ |
109 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, | |
110 | MC_CMD_MAC_NSTATS * sizeof(u64)); | |
111 | if (rc) | |
112 | return rc; | |
62776d03 BH |
113 | netif_dbg(efx, probe, efx->net_dev, |
114 | "stats buffer at %llx (virt %p phys %llx)\n", | |
115 | (u64)efx->stats_buffer.dma_addr, | |
116 | efx->stats_buffer.addr, | |
117 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
afd4aea0 BH |
118 | |
119 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
d215697f | 124 | static void siena_remove_port(struct efx_nic *efx) |
afd4aea0 | 125 | { |
ff3b00a0 | 126 | efx->phy_op->remove(efx); |
afd4aea0 BH |
127 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
128 | } | |
129 | ||
d5e8cc6c BH |
130 | void siena_prepare_flush(struct efx_nic *efx) |
131 | { | |
132 | if (efx->fc_disable++ == 0) | |
133 | efx_mcdi_set_mac(efx); | |
134 | } | |
135 | ||
136 | void siena_finish_flush(struct efx_nic *efx) | |
137 | { | |
138 | if (--efx->fc_disable == 0) | |
139 | efx_mcdi_set_mac(efx); | |
140 | } | |
141 | ||
afd4aea0 BH |
142 | static const struct efx_nic_register_test siena_register_tests[] = { |
143 | { FR_AZ_ADR_REGION, | |
4cddca54 | 144 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
afd4aea0 BH |
145 | { FR_CZ_USR_EV_CFG, |
146 | EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, | |
147 | { FR_AZ_RX_CFG, | |
148 | EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, | |
149 | { FR_AZ_TX_CFG, | |
150 | EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, | |
151 | { FR_AZ_TX_RESERVED, | |
152 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, | |
153 | { FR_AZ_SRM_TX_DC_CFG, | |
154 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, | |
155 | { FR_AZ_RX_DC_CFG, | |
156 | EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, | |
157 | { FR_AZ_RX_DC_PF_WM, | |
158 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, | |
159 | { FR_BZ_DP_CTRL, | |
160 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, | |
161 | { FR_BZ_RX_RSS_TKEY, | |
162 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
163 | { FR_CZ_RX_RSS_IPV6_REG1, | |
164 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
165 | { FR_CZ_RX_RSS_IPV6_REG2, | |
166 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
167 | { FR_CZ_RX_RSS_IPV6_REG3, | |
168 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, | |
169 | }; | |
170 | ||
d4f2cecc | 171 | static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) |
afd4aea0 | 172 | { |
ef492f11 | 173 | enum reset_type reset_method = RESET_TYPE_ALL; |
d4f2cecc BH |
174 | int rc, rc2; |
175 | ||
176 | efx_reset_down(efx, reset_method); | |
177 | ||
178 | /* Reset the chip immediately so that it is completely | |
179 | * quiescent regardless of what any VF driver does. | |
180 | */ | |
181 | rc = siena_reset_hw(efx, reset_method); | |
182 | if (rc) | |
183 | goto out; | |
184 | ||
185 | tests->registers = | |
186 | efx_nic_test_registers(efx, siena_register_tests, | |
187 | ARRAY_SIZE(siena_register_tests)) | |
188 | ? -1 : 1; | |
189 | ||
190 | rc = siena_reset_hw(efx, reset_method); | |
191 | out: | |
192 | rc2 = efx_reset_up(efx, reset_method, rc == 0); | |
193 | return rc ? rc : rc2; | |
afd4aea0 BH |
194 | } |
195 | ||
196 | /************************************************************************** | |
197 | * | |
198 | * Device reset | |
199 | * | |
200 | ************************************************************************** | |
201 | */ | |
202 | ||
0e2a9c7c BH |
203 | static enum reset_type siena_map_reset_reason(enum reset_type reason) |
204 | { | |
626950db | 205 | return RESET_TYPE_RECOVER_OR_ALL; |
0e2a9c7c BH |
206 | } |
207 | ||
208 | static int siena_map_reset_flags(u32 *flags) | |
209 | { | |
210 | enum { | |
211 | SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER | | |
212 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | | |
213 | ETH_RESET_PHY), | |
214 | SIENA_RESET_MC = (SIENA_RESET_PORT | | |
215 | ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT), | |
216 | }; | |
217 | ||
218 | if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) { | |
219 | *flags &= ~SIENA_RESET_MC; | |
220 | return RESET_TYPE_WORLD; | |
221 | } | |
222 | ||
223 | if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) { | |
224 | *flags &= ~SIENA_RESET_PORT; | |
225 | return RESET_TYPE_ALL; | |
226 | } | |
227 | ||
228 | /* no invisible reset implemented */ | |
229 | ||
230 | return -EINVAL; | |
231 | } | |
232 | ||
afd4aea0 BH |
233 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) |
234 | { | |
8b2103ad SH |
235 | int rc; |
236 | ||
237 | /* Recover from a failed assertion pre-reset */ | |
238 | rc = efx_mcdi_handle_assertion(efx); | |
239 | if (rc) | |
240 | return rc; | |
afd4aea0 BH |
241 | |
242 | if (method == RESET_TYPE_WORLD) | |
243 | return efx_mcdi_reset_mc(efx); | |
244 | else | |
245 | return efx_mcdi_reset_port(efx); | |
246 | } | |
247 | ||
626950db AR |
248 | #ifdef CONFIG_EEH |
249 | /* When a PCI device is isolated from the bus, a subsequent MMIO read is | |
250 | * required for the kernel EEH mechanisms to notice. As the Solarflare driver | |
251 | * was written to minimise MMIO read (for latency) then a periodic call to check | |
252 | * the EEH status of the device is required so that device recovery can happen | |
253 | * in a timely fashion. | |
254 | */ | |
255 | static void siena_monitor(struct efx_nic *efx) | |
256 | { | |
257 | struct eeh_dev *eehdev = | |
258 | of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev)); | |
259 | ||
260 | eeh_dev_check_failure(eehdev); | |
261 | } | |
262 | #endif | |
263 | ||
afd4aea0 BH |
264 | static int siena_probe_nvconfig(struct efx_nic *efx) |
265 | { | |
cc180b69 BH |
266 | u32 caps = 0; |
267 | int rc; | |
268 | ||
269 | rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps); | |
270 | ||
271 | efx->timer_quantum_ns = | |
272 | (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ? | |
273 | 3072 : 6144; /* 768 cycles */ | |
274 | return rc; | |
afd4aea0 BH |
275 | } |
276 | ||
28e47c49 BH |
277 | static void siena_dimension_resources(struct efx_nic *efx) |
278 | { | |
279 | /* Each port has a small block of internal SRAM dedicated to | |
280 | * the buffer table and descriptor caches. In theory we can | |
281 | * map both blocks to one port, but we don't. | |
282 | */ | |
283 | efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2); | |
284 | } | |
285 | ||
afd4aea0 BH |
286 | static int siena_probe_nic(struct efx_nic *efx) |
287 | { | |
288 | struct siena_nic_data *nic_data; | |
3db1cd5c | 289 | bool already_attached = false; |
d42a8f46 | 290 | efx_oword_t reg; |
afd4aea0 BH |
291 | int rc; |
292 | ||
293 | /* Allocate storage for hardware specific data */ | |
294 | nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); | |
295 | if (!nic_data) | |
296 | return -ENOMEM; | |
297 | efx->nic_data = nic_data; | |
298 | ||
299 | if (efx_nic_fpga_ver(efx) != 0) { | |
62776d03 BH |
300 | netif_err(efx, probe, efx->net_dev, |
301 | "Siena FPGA not supported\n"); | |
afd4aea0 BH |
302 | rc = -ENODEV; |
303 | goto fail1; | |
304 | } | |
305 | ||
d42a8f46 | 306 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); |
3df95ce9 | 307 | efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; |
d42a8f46 | 308 | |
afd4aea0 BH |
309 | efx_mcdi_init(efx); |
310 | ||
311 | /* Recover from a failed assertion before probing */ | |
312 | rc = efx_mcdi_handle_assertion(efx); | |
313 | if (rc) | |
86c432ca | 314 | goto fail1; |
afd4aea0 | 315 | |
afd4aea0 BH |
316 | /* Let the BMC know that the driver is now in charge of link and |
317 | * filter settings. We must do this before we reset the NIC */ | |
318 | rc = efx_mcdi_drv_attach(efx, true, &already_attached); | |
319 | if (rc) { | |
62776d03 BH |
320 | netif_err(efx, probe, efx->net_dev, |
321 | "Unable to register driver with MCPU\n"); | |
afd4aea0 BH |
322 | goto fail2; |
323 | } | |
324 | if (already_attached) | |
325 | /* Not a fatal error */ | |
62776d03 BH |
326 | netif_err(efx, probe, efx->net_dev, |
327 | "Host already registered with MCPU\n"); | |
afd4aea0 BH |
328 | |
329 | /* Now we can reset the NIC */ | |
330 | rc = siena_reset_hw(efx, RESET_TYPE_ALL); | |
331 | if (rc) { | |
62776d03 | 332 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
afd4aea0 BH |
333 | goto fail3; |
334 | } | |
335 | ||
336 | siena_init_wol(efx); | |
337 | ||
338 | /* Allocate memory for INT_KER */ | |
339 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
340 | if (rc) | |
341 | goto fail4; | |
342 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
343 | ||
62776d03 BH |
344 | netif_dbg(efx, probe, efx->net_dev, |
345 | "INT_KER at %llx (virt %p phys %llx)\n", | |
346 | (unsigned long long)efx->irq_status.dma_addr, | |
347 | efx->irq_status.addr, | |
348 | (unsigned long long)virt_to_phys(efx->irq_status.addr)); | |
afd4aea0 BH |
349 | |
350 | /* Read in the non-volatile configuration */ | |
351 | rc = siena_probe_nvconfig(efx); | |
352 | if (rc == -EINVAL) { | |
62776d03 BH |
353 | netif_err(efx, probe, efx->net_dev, |
354 | "NVRAM is invalid therefore using defaults\n"); | |
afd4aea0 BH |
355 | efx->phy_type = PHY_TYPE_NONE; |
356 | efx->mdio.prtad = MDIO_PRTAD_NONE; | |
357 | } else if (rc) { | |
358 | goto fail5; | |
359 | } | |
360 | ||
55c5e0f8 BH |
361 | rc = efx_mcdi_mon_probe(efx); |
362 | if (rc) | |
363 | goto fail5; | |
364 | ||
cd2d5b52 | 365 | efx_sriov_probe(efx); |
7c236c43 | 366 | efx_ptp_probe(efx); |
cd2d5b52 | 367 | |
afd4aea0 BH |
368 | return 0; |
369 | ||
370 | fail5: | |
371 | efx_nic_free_buffer(efx, &efx->irq_status); | |
372 | fail4: | |
373 | fail3: | |
374 | efx_mcdi_drv_attach(efx, false, NULL); | |
375 | fail2: | |
376 | fail1: | |
377 | kfree(efx->nic_data); | |
378 | return rc; | |
379 | } | |
380 | ||
381 | /* This call performs hardware-specific global initialisation, such as | |
382 | * defining the descriptor cache sizes and number of RSS channels. | |
383 | * It does not set up any buffers, descriptor rings or event queues. | |
384 | */ | |
385 | static int siena_init_nic(struct efx_nic *efx) | |
386 | { | |
387 | efx_oword_t temp; | |
388 | int rc; | |
389 | ||
390 | /* Recover from a failed assertion post-reset */ | |
391 | rc = efx_mcdi_handle_assertion(efx); | |
392 | if (rc) | |
393 | return rc; | |
394 | ||
395 | /* Squash TX of packets of 16 bytes or less */ | |
396 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); | |
397 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); | |
398 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); | |
399 | ||
400 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
401 | * descriptors (which is bad). | |
402 | */ | |
403 | efx_reado(efx, &temp, FR_AZ_TX_CFG); | |
404 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); | |
405 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); | |
406 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); | |
407 | ||
408 | efx_reado(efx, &temp, FR_AZ_RX_CFG); | |
409 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); | |
410 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
411 | /* Enable hash insertion. This is broken for the 'Falcon' hash |
412 | * if IPv6 hashing is also enabled, so also select Toeplitz | |
413 | * TCP/IPv4 and IPv4 hashes. */ | |
414 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1); | |
415 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1); | |
416 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1); | |
85740cdf BH |
417 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE, |
418 | EFX_RX_USR_BUF_SIZE >> 5); | |
afd4aea0 BH |
419 | efx_writeo(efx, &temp, FR_AZ_RX_CFG); |
420 | ||
477e54eb BH |
421 | /* Set hash key for IPv4 */ |
422 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
423 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | |
424 | ||
d614cfbc | 425 | /* Enable IPv6 RSS */ |
5d3a6fca | 426 | BUILD_BUG_ON(sizeof(efx->rx_hash_key) < |
d614cfbc BH |
427 | 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || |
428 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); | |
5d3a6fca | 429 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); |
d614cfbc | 430 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); |
5d3a6fca | 431 | memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp)); |
d614cfbc BH |
432 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); |
433 | EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, | |
434 | FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); | |
5d3a6fca | 435 | memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp), |
d614cfbc BH |
436 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); |
437 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); | |
438 | ||
afd4aea0 BH |
439 | /* Enable event logging */ |
440 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); | |
441 | if (rc) | |
442 | return rc; | |
443 | ||
444 | /* Set destination of both TX and RX Flush events */ | |
445 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); | |
446 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); | |
447 | ||
448 | EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); | |
449 | efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); | |
450 | ||
451 | efx_nic_init_common(efx); | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static void siena_remove_nic(struct efx_nic *efx) | |
456 | { | |
55c5e0f8 BH |
457 | efx_mcdi_mon_remove(efx); |
458 | ||
afd4aea0 BH |
459 | efx_nic_free_buffer(efx, &efx->irq_status); |
460 | ||
461 | siena_reset_hw(efx, RESET_TYPE_ALL); | |
462 | ||
463 | /* Relinquish the device back to the BMC */ | |
bdca71ed | 464 | efx_mcdi_drv_attach(efx, false, NULL); |
afd4aea0 BH |
465 | |
466 | /* Tear down the private nic state */ | |
86c432ca | 467 | kfree(efx->nic_data); |
afd4aea0 BH |
468 | efx->nic_data = NULL; |
469 | } | |
470 | ||
a659b2a9 | 471 | #define STATS_GENERATION_INVALID ((__force __le64)(-1)) |
afd4aea0 BH |
472 | |
473 | static int siena_try_update_nic_stats(struct efx_nic *efx) | |
474 | { | |
a659b2a9 | 475 | __le64 *dma_stats; |
afd4aea0 | 476 | struct efx_mac_stats *mac_stats; |
a659b2a9 | 477 | __le64 generation_start, generation_end; |
afd4aea0 BH |
478 | |
479 | mac_stats = &efx->mac_stats; | |
43d620c8 | 480 | dma_stats = efx->stats_buffer.addr; |
afd4aea0 BH |
481 | |
482 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; | |
483 | if (generation_end == STATS_GENERATION_INVALID) | |
484 | return 0; | |
485 | rmb(); | |
486 | ||
487 | #define MAC_STAT(M, D) \ | |
a659b2a9 | 488 | mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D]) |
afd4aea0 BH |
489 | |
490 | MAC_STAT(tx_bytes, TX_BYTES); | |
491 | MAC_STAT(tx_bad_bytes, TX_BAD_BYTES); | |
b7f514af BH |
492 | efx_update_diff_stat(&mac_stats->tx_good_bytes, |
493 | mac_stats->tx_bytes - mac_stats->tx_bad_bytes); | |
afd4aea0 BH |
494 | MAC_STAT(tx_packets, TX_PKTS); |
495 | MAC_STAT(tx_bad, TX_BAD_FCS_PKTS); | |
496 | MAC_STAT(tx_pause, TX_PAUSE_PKTS); | |
497 | MAC_STAT(tx_control, TX_CONTROL_PKTS); | |
498 | MAC_STAT(tx_unicast, TX_UNICAST_PKTS); | |
499 | MAC_STAT(tx_multicast, TX_MULTICAST_PKTS); | |
500 | MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS); | |
501 | MAC_STAT(tx_lt64, TX_LT64_PKTS); | |
502 | MAC_STAT(tx_64, TX_64_PKTS); | |
503 | MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS); | |
504 | MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS); | |
505 | MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS); | |
506 | MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS); | |
507 | MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS); | |
508 | MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS); | |
509 | MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS); | |
510 | mac_stats->tx_collision = 0; | |
511 | MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS); | |
512 | MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS); | |
513 | MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS); | |
514 | MAC_STAT(tx_deferred, TX_DEFERRED_PKTS); | |
515 | MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS); | |
516 | mac_stats->tx_collision = (mac_stats->tx_single_collision + | |
517 | mac_stats->tx_multiple_collision + | |
518 | mac_stats->tx_excessive_collision + | |
519 | mac_stats->tx_late_collision); | |
520 | MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS); | |
521 | MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS); | |
522 | MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS); | |
523 | MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS); | |
524 | MAC_STAT(rx_bytes, RX_BYTES); | |
525 | MAC_STAT(rx_bad_bytes, RX_BAD_BYTES); | |
b7f514af BH |
526 | efx_update_diff_stat(&mac_stats->rx_good_bytes, |
527 | mac_stats->rx_bytes - mac_stats->rx_bad_bytes); | |
afd4aea0 BH |
528 | MAC_STAT(rx_packets, RX_PKTS); |
529 | MAC_STAT(rx_good, RX_GOOD_PKTS); | |
1cdc2cfc | 530 | MAC_STAT(rx_bad, RX_BAD_FCS_PKTS); |
afd4aea0 BH |
531 | MAC_STAT(rx_pause, RX_PAUSE_PKTS); |
532 | MAC_STAT(rx_control, RX_CONTROL_PKTS); | |
533 | MAC_STAT(rx_unicast, RX_UNICAST_PKTS); | |
534 | MAC_STAT(rx_multicast, RX_MULTICAST_PKTS); | |
535 | MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS); | |
536 | MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS); | |
537 | MAC_STAT(rx_64, RX_64_PKTS); | |
538 | MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS); | |
539 | MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS); | |
540 | MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS); | |
541 | MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS); | |
542 | MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS); | |
543 | MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS); | |
544 | MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS); | |
545 | mac_stats->rx_bad_lt64 = 0; | |
546 | mac_stats->rx_bad_64_to_15xx = 0; | |
547 | mac_stats->rx_bad_15xx_to_jumbo = 0; | |
548 | MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS); | |
549 | MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS); | |
550 | mac_stats->rx_missed = 0; | |
551 | MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS); | |
552 | MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS); | |
553 | MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS); | |
554 | MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS); | |
555 | MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS); | |
556 | mac_stats->rx_good_lt64 = 0; | |
557 | ||
a659b2a9 SH |
558 | efx->n_rx_nodesc_drop_cnt = |
559 | le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]); | |
afd4aea0 BH |
560 | |
561 | #undef MAC_STAT | |
562 | ||
563 | rmb(); | |
564 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; | |
565 | if (generation_end != generation_start) | |
566 | return -EAGAIN; | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | static void siena_update_nic_stats(struct efx_nic *efx) | |
572 | { | |
aabc5649 BH |
573 | int retry; |
574 | ||
575 | /* If we're unlucky enough to read statistics wduring the DMA, wait | |
576 | * up to 10ms for it to finish (typically takes <500us) */ | |
577 | for (retry = 0; retry < 100; ++retry) { | |
578 | if (siena_try_update_nic_stats(efx) == 0) | |
579 | return; | |
580 | udelay(100); | |
581 | } | |
582 | ||
583 | /* Use the old values instead */ | |
afd4aea0 BH |
584 | } |
585 | ||
586 | static void siena_start_nic_stats(struct efx_nic *efx) | |
587 | { | |
a659b2a9 | 588 | __le64 *dma_stats = efx->stats_buffer.addr; |
afd4aea0 BH |
589 | |
590 | dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID; | |
591 | ||
592 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, | |
593 | MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0); | |
594 | } | |
595 | ||
596 | static void siena_stop_nic_stats(struct efx_nic *efx) | |
597 | { | |
598 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0); | |
599 | } | |
600 | ||
afd4aea0 BH |
601 | /************************************************************************** |
602 | * | |
603 | * Wake on LAN | |
604 | * | |
605 | ************************************************************************** | |
606 | */ | |
607 | ||
608 | static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
609 | { | |
610 | struct siena_nic_data *nic_data = efx->nic_data; | |
611 | ||
612 | wol->supported = WAKE_MAGIC; | |
613 | if (nic_data->wol_filter_id != -1) | |
614 | wol->wolopts = WAKE_MAGIC; | |
615 | else | |
616 | wol->wolopts = 0; | |
617 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
618 | } | |
619 | ||
620 | ||
621 | static int siena_set_wol(struct efx_nic *efx, u32 type) | |
622 | { | |
623 | struct siena_nic_data *nic_data = efx->nic_data; | |
624 | int rc; | |
625 | ||
626 | if (type & ~WAKE_MAGIC) | |
627 | return -EINVAL; | |
628 | ||
629 | if (type & WAKE_MAGIC) { | |
630 | if (nic_data->wol_filter_id != -1) | |
631 | efx_mcdi_wol_filter_remove(efx, | |
632 | nic_data->wol_filter_id); | |
02ebc268 | 633 | rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr, |
afd4aea0 BH |
634 | &nic_data->wol_filter_id); |
635 | if (rc) | |
636 | goto fail; | |
637 | ||
638 | pci_wake_from_d3(efx->pci_dev, true); | |
639 | } else { | |
640 | rc = efx_mcdi_wol_filter_reset(efx); | |
641 | nic_data->wol_filter_id = -1; | |
642 | pci_wake_from_d3(efx->pci_dev, false); | |
643 | if (rc) | |
644 | goto fail; | |
645 | } | |
646 | ||
647 | return 0; | |
648 | fail: | |
62776d03 BH |
649 | netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n", |
650 | __func__, type, rc); | |
afd4aea0 BH |
651 | return rc; |
652 | } | |
653 | ||
654 | ||
655 | static void siena_init_wol(struct efx_nic *efx) | |
656 | { | |
657 | struct siena_nic_data *nic_data = efx->nic_data; | |
658 | int rc; | |
659 | ||
660 | rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); | |
661 | ||
662 | if (rc != 0) { | |
663 | /* If it failed, attempt to get into a synchronised | |
664 | * state with MC by resetting any set WoL filters */ | |
665 | efx_mcdi_wol_filter_reset(efx); | |
666 | nic_data->wol_filter_id = -1; | |
667 | } else if (nic_data->wol_filter_id != -1) { | |
668 | pci_wake_from_d3(efx->pci_dev, true); | |
669 | } | |
670 | } | |
671 | ||
672 | ||
673 | /************************************************************************** | |
674 | * | |
675 | * Revision-dependent attributes used by efx.c and nic.c | |
676 | * | |
677 | ************************************************************************** | |
678 | */ | |
679 | ||
6c8c2513 | 680 | const struct efx_nic_type siena_a0_nic_type = { |
afd4aea0 BH |
681 | .probe = siena_probe_nic, |
682 | .remove = siena_remove_nic, | |
683 | .init = siena_init_nic, | |
28e47c49 | 684 | .dimension_resources = siena_dimension_resources, |
afd4aea0 | 685 | .fini = efx_port_dummy_op_void, |
626950db AR |
686 | #ifdef CONFIG_EEH |
687 | .monitor = siena_monitor, | |
688 | #else | |
afd4aea0 | 689 | .monitor = NULL, |
626950db | 690 | #endif |
0e2a9c7c BH |
691 | .map_reset_reason = siena_map_reset_reason, |
692 | .map_reset_flags = siena_map_reset_flags, | |
afd4aea0 BH |
693 | .reset = siena_reset_hw, |
694 | .probe_port = siena_probe_port, | |
695 | .remove_port = siena_remove_port, | |
d5e8cc6c BH |
696 | .prepare_flush = siena_prepare_flush, |
697 | .finish_flush = siena_finish_flush, | |
afd4aea0 BH |
698 | .update_stats = siena_update_nic_stats, |
699 | .start_stats = siena_start_nic_stats, | |
700 | .stop_stats = siena_stop_nic_stats, | |
701 | .set_id_led = efx_mcdi_set_id_led, | |
702 | .push_irq_moderation = siena_push_irq_moderation, | |
710b208d BH |
703 | .reconfigure_mac = efx_mcdi_mac_reconfigure, |
704 | .check_mac_fault = efx_mcdi_mac_check_fault, | |
afd4aea0 BH |
705 | .reconfigure_port = efx_mcdi_phy_reconfigure, |
706 | .get_wol = siena_get_wol, | |
707 | .set_wol = siena_set_wol, | |
708 | .resume_wol = siena_init_wol, | |
d4f2cecc | 709 | .test_chip = siena_test_chip, |
2e803407 | 710 | .test_nvram = efx_mcdi_nvram_test_all, |
afd4aea0 BH |
711 | |
712 | .revision = EFX_REV_SIENA_A0, | |
86c432ca BH |
713 | .mem_map_size = (FR_CZ_MC_TREG_SMEM + |
714 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS), | |
afd4aea0 BH |
715 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
716 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
717 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
718 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
719 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
720 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), | |
39c9cf07 | 721 | .rx_buffer_hash_size = 0x10, |
afd4aea0 | 722 | .rx_buffer_padding = 0, |
85740cdf | 723 | .can_rx_scatter = true, |
afd4aea0 BH |
724 | .max_interrupt_mode = EFX_INT_MODE_MSIX, |
725 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
726 | * interrupt handler only supports 32 | |
727 | * channels */ | |
cc180b69 | 728 | .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH, |
39c9cf07 | 729 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
b4187e42 | 730 | NETIF_F_RXHASH | NETIF_F_NTUPLE), |
afd4aea0 | 731 | }; |