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Merge branch 'bind_unbind' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_sriov_common.c
CommitLineData
02feda17
RB		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
a930a463
HP		 8#include <linux/types.h>
9
02feda17
RB		 10#include "qlcnic_sriov.h"
11#include "qlcnic.h"
f8468331 12#include "qlcnic_83xx_hw.h"
02feda17 13
f197a7aa
RB		 14#define QLC_BC_COMMAND 0
15#define QLC_BC_RESPONSE 1
16
17#define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
18#define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
19
20#define QLC_BC_MSG 0
21#define QLC_BC_CFREE 1
97d8105c 22#define QLC_BC_FLR 2
f197a7aa
RB		 23#define QLC_BC_HDR_SZ 16
24#define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
25
7cb03b23
RB		 26#define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048
27#define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512
28
f036e4f4
RB		 29#define QLC_83XX_VF_RESET_FAIL_THRESH 8
30#define QLC_BC_CMD_MAX_RETRY_CNT 5
31
2b10d3ec 32static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work);
91b7282b
RB		 33static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *);
34static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32);
f036e4f4
RB		 35static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *);
36static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *);
97d8105c 37static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *);
e5c4e6c6 38static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *,
f197a7aa 39 struct qlcnic_cmd_args *);
21041400 40static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8);
1267ff96 41static void qlcnic_sriov_process_bc_cmd(struct work_struct *);
21041400 42static int qlcnic_sriov_vf_shutdown(struct pci_dev *);
43static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *);
74b7ba1a
RB		 44static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *,
45 struct qlcnic_cmd_args *);
f197a7aa 46
f8468331
RB		 47static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
48 .read_crb = qlcnic_83xx_read_crb,
49 .write_crb = qlcnic_83xx_write_crb,
50 .read_reg = qlcnic_83xx_rd_reg_indirect,
51 .write_reg = qlcnic_83xx_wrt_reg_indirect,
52 .get_mac_address = qlcnic_83xx_get_mac_address,
53 .setup_intr = qlcnic_83xx_setup_intr,
54 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
e5c4e6c6 55 .mbx_cmd = qlcnic_sriov_issue_cmd,
f8468331
RB		 56 .get_func_no = qlcnic_83xx_get_func_no,
57 .api_lock = qlcnic_83xx_cam_lock,
58 .api_unlock = qlcnic_83xx_cam_unlock,
59 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
60 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
61 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
7cb03b23
RB		 62 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
63 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
f8468331
RB		 64 .setup_link_event = qlcnic_83xx_setup_link_event,
65 .get_nic_info = qlcnic_83xx_get_nic_info,
66 .get_pci_info = qlcnic_83xx_get_pci_info,
67 .set_nic_info = qlcnic_83xx_set_nic_info,
68 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
69 .napi_enable = qlcnic_83xx_napi_enable,
70 .napi_disable = qlcnic_83xx_napi_disable,
71 .config_intr_coal = qlcnic_83xx_config_intr_coal,
72 .config_rss = qlcnic_83xx_config_rss,
73 .config_hw_lro = qlcnic_83xx_config_hw_lro,
74 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
75 .change_l2_filter = qlcnic_83xx_change_l2_filter,
76 .get_board_info = qlcnic_83xx_get_port_info,
91b7282b 77 .free_mac_list = qlcnic_sriov_vf_free_mac_list,
2cc5752e
M		 78 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
79 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
4bd7ef0b
CM		 80 .encap_rx_offload = qlcnic_83xx_encap_rx_offload,
81 .encap_tx_offload = qlcnic_83xx_encap_tx_offload,
f8468331
RB		 82};
83
84static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
85 .config_bridged_mode = qlcnic_config_bridged_mode,
86 .config_led = qlcnic_config_led,
f036e4f4 87 .cancel_idc_work = qlcnic_sriov_vf_cancel_fw_work,
f8468331
RB		 88 .napi_add = qlcnic_83xx_napi_add,
89 .napi_del = qlcnic_83xx_napi_del,
486a5bc7
RB		 90 .shutdown = qlcnic_sriov_vf_shutdown,
91 .resume = qlcnic_sriov_vf_resume,
f8468331
RB		 92 .config_ipaddr = qlcnic_83xx_config_ipaddr,
93 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
94};
95
f197a7aa
RB		 96static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
97 {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
98 {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
91b7282b
RB		 99 {QLCNIC_BC_CMD_GET_ACL, 3, 14},
100 {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2},
f197a7aa
RB		 101};
102
103static inline bool qlcnic_sriov_bc_msg_check(u32 val)
104{
105 return (val & (1 << QLC_BC_MSG)) ? true : false;
106}
107
108static inline bool qlcnic_sriov_channel_free_check(u32 val)
109{
110 return (val & (1 << QLC_BC_CFREE)) ? true : false;
111}
112
97d8105c
RB		 113static inline bool qlcnic_sriov_flr_check(u32 val)
114{
115 return (val & (1 << QLC_BC_FLR)) ? true : false;
116}
117
f197a7aa
RB		 118static inline u8 qlcnic_sriov_target_func_id(u32 val)
119{
120 return (val >> 4) & 0xff;
121}
122
123static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
124{
125 struct pci_dev *dev = adapter->pdev;
126 int pos;
127 u16 stride, offset;
128
129 if (qlcnic_sriov_vf_check(adapter))
130 return 0;
131
132 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
91ec701a
PB		 133 if (!pos)
134 return 0;
f197a7aa
RB		 135 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
136 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
137
138 return (dev->devfn + offset + stride * vf_id) & 0xff;
139}
140
02feda17
RB		 141int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
142{
143 struct qlcnic_sriov *sriov;
f197a7aa
RB		 144 struct qlcnic_back_channel *bc;
145 struct workqueue_struct *wq;
146 struct qlcnic_vport *vp;
147 struct qlcnic_vf_info *vf;
148 int err, i;
02feda17
RB		 149
150 if (!qlcnic_sriov_enable_check(adapter))
151 return -EIO;
152
153 sriov = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL);
154 if (!sriov)
155 return -ENOMEM;
156
157 adapter->ahw->sriov = sriov;
158 sriov->num_vfs = num_vfs;
f197a7aa
RB		 159 bc = &sriov->bc;
160 sriov->vf_info = kzalloc(sizeof(struct qlcnic_vf_info) *
161 num_vfs, GFP_KERNEL);
162 if (!sriov->vf_info) {
163 err = -ENOMEM;
164 goto qlcnic_free_sriov;
165 }
166
167 wq = create_singlethread_workqueue("bc-trans");
168 if (wq == NULL) {
169 err = -ENOMEM;
170 dev_err(&adapter->pdev->dev,
171 "Cannot create bc-trans workqueue\n");
172 goto qlcnic_free_vf_info;
173 }
174
175 bc->bc_trans_wq = wq;
176
e8b508ef
RB		 177 wq = create_singlethread_workqueue("async");
178 if (wq == NULL) {
179 err = -ENOMEM;
180 dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n");
181 goto qlcnic_destroy_trans_wq;
182 }
183
184 bc->bc_async_wq = wq;
2b10d3ec
MC		 185 INIT_LIST_HEAD(&bc->async_cmd_list);
186 INIT_WORK(&bc->vf_async_work, qlcnic_sriov_handle_async_issue_cmd);
187 spin_lock_init(&bc->queue_lock);
188 bc->adapter = adapter;
e8b508ef 189
f197a7aa
RB		 190 for (i = 0; i < num_vfs; i++) {
191 vf = &sriov->vf_info[i];
192 vf->adapter = adapter;
193 vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
194 mutex_init(&vf->send_cmd_lock);
74b7ba1a 195 spin_lock_init(&vf->vlan_list_lock);
f197a7aa
RB		 196 INIT_LIST_HEAD(&vf->rcv_act.wait_list);
197 INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
198 spin_lock_init(&vf->rcv_act.lock);
199 spin_lock_init(&vf->rcv_pend.lock);
200 init_completion(&vf->ch_free_cmpl);
201
1267ff96
SC		 202 INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd);
203
f197a7aa
RB		 204 if (qlcnic_sriov_pf_check(adapter)) {
205 vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
206 if (!vp) {
207 err = -ENOMEM;
e8b508ef 208 goto qlcnic_destroy_async_wq;
f197a7aa
RB		 209 }
210 sriov->vf_info[i].vp = vp;
d747c333 211 vp->vlan_mode = QLC_GUEST_VLAN_MODE;
4000e7a7 212 vp->max_tx_bw = MAX_BW;
ed616689 213 vp->min_tx_bw = MIN_BW;
132a3f2b 214 vp->spoofchk = false;
f197a7aa
RB		 215 random_ether_addr(vp->mac);
216 dev_info(&adapter->pdev->dev,
217 "MAC Address %pM is configured for VF %d\n",
218 vp->mac, i);
219 }
220 }
221
02feda17 222 return 0;
f197a7aa 223
e8b508ef
RB		 224qlcnic_destroy_async_wq:
225 destroy_workqueue(bc->bc_async_wq);
226
f197a7aa
RB		 227qlcnic_destroy_trans_wq:
228 destroy_workqueue(bc->bc_trans_wq);
229
230qlcnic_free_vf_info:
231 kfree(sriov->vf_info);
232
233qlcnic_free_sriov:
234 kfree(adapter->ahw->sriov);
235 return err;
02feda17
RB		 236}
237
97d8105c
RB		 238void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list)
239{
240 struct qlcnic_bc_trans *trans;
241 struct qlcnic_cmd_args cmd;
242 unsigned long flags;
243
244 spin_lock_irqsave(&t_list->lock, flags);
245
246 while (!list_empty(&t_list->wait_list)) {
247 trans = list_first_entry(&t_list->wait_list,
248 struct qlcnic_bc_trans, list);
249 list_del(&trans->list);
250 t_list->count--;
251 cmd.req.arg = (u32 *)trans->req_pay;
252 cmd.rsp.arg = (u32 *)trans->rsp_pay;
253 qlcnic_free_mbx_args(&cmd);
254 qlcnic_sriov_cleanup_transaction(trans);
255 }
256
257 spin_unlock_irqrestore(&t_list->lock, flags);
258}
259
02feda17
RB		 260void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
261{
f197a7aa
RB		 262 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
263 struct qlcnic_back_channel *bc = &sriov->bc;
97d8105c 264 struct qlcnic_vf_info *vf;
f197a7aa
RB		 265 int i;
266
02feda17
RB		 267 if (!qlcnic_sriov_enable_check(adapter))
268 return;
269
e8b508ef
RB		 270 qlcnic_sriov_cleanup_async_list(bc);
271 destroy_workqueue(bc->bc_async_wq);
97d8105c
RB		 272
273 for (i = 0; i < sriov->num_vfs; i++) {
274 vf = &sriov->vf_info[i];
275 qlcnic_sriov_cleanup_list(&vf->rcv_pend);
276 cancel_work_sync(&vf->trans_work);
277 qlcnic_sriov_cleanup_list(&vf->rcv_act);
278 }
279
f197a7aa
RB		 280 destroy_workqueue(bc->bc_trans_wq);
281
282 for (i = 0; i < sriov->num_vfs; i++)
283 kfree(sriov->vf_info[i].vp);
284
285 kfree(sriov->vf_info);
02feda17
RB		 286 kfree(adapter->ahw->sriov);
287}
288
f8468331
RB		 289static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
290{
f197a7aa
RB		 291 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
292 qlcnic_sriov_cfg_bc_intr(adapter, 0);
f8468331
RB		 293 __qlcnic_sriov_cleanup(adapter);
294}
295
02feda17
RB		 296void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
297{
6e1f586d 298 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
154d0c81
MC		 299 return;
300
301 qlcnic_sriov_free_vlans(adapter);
302
02feda17
RB		 303 if (qlcnic_sriov_pf_check(adapter))
304 qlcnic_sriov_pf_cleanup(adapter);
f8468331
RB		 305
306 if (qlcnic_sriov_vf_check(adapter))
307 qlcnic_sriov_vf_cleanup(adapter);
308}
309
f197a7aa
RB		 310static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
311 u32 *pay, u8 pci_func, u8 size)
312{
313 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19
MC		 314 struct qlcnic_mailbox *mbx = ahw->mailbox;
315 struct qlcnic_cmd_args cmd;
316 unsigned long timeout;
317 int err;
f197a7aa 318
068a8d19
MC		 319 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
320 cmd.hdr = hdr;
321 cmd.pay = pay;
322 cmd.pay_size = size;
323 cmd.func_num = pci_func;
324 cmd.op_type = QLC_83XX_MBX_POST_BC_OP;
325 cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
326
327 err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout);
328 if (err) {
329 dev_err(&adapter->pdev->dev,
330 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
331 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
332 ahw->op_mode);
333 return err;
f197a7aa 334 }
f197a7aa 335
068a8d19
MC		 336 if (!wait_for_completion_timeout(&cmd.completion, timeout)) {
337 dev_err(&adapter->pdev->dev,
338 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
339 __func__, cmd.cmd_op, cmd.type, ahw->pci_func,
340 ahw->op_mode);
341 flush_workqueue(mbx->work_q);
f197a7aa
RB		 342 }
343
068a8d19 344 return cmd.rsp_opcode;
f197a7aa
RB		 345}
346
7cb03b23
RB		 347static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter)
348{
349 adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF;
350 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
351 adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF;
352 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
353 adapter->num_txd = MAX_CMD_DESCRIPTORS;
354 adapter->max_rds_rings = MAX_RDS_RINGS;
355}
356
4000e7a7
RB		 357int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter,
358 struct qlcnic_info *npar_info, u16 vport_id)
359{
360 struct device *dev = &adapter->pdev->dev;
361 struct qlcnic_cmd_args cmd;
362 int err;
363 u32 status;
364
365 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
366 if (err)
367 return err;
368
369 cmd.req.arg[1] = vport_id << 16 | 0x1;
370 err = qlcnic_issue_cmd(adapter, &cmd);
371 if (err) {
372 dev_err(&adapter->pdev->dev,
373 "Failed to get vport info, err=%d\n", err);
374 qlcnic_free_mbx_args(&cmd);
375 return err;
376 }
377
378 status = cmd.rsp.arg[2] & 0xffff;
379 if (status & BIT_0)
380 npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]);
381 if (status & BIT_1)
382 npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]);
383 if (status & BIT_2)
384 npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]);
385 if (status & BIT_3)
386 npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]);
387 if (status & BIT_4)
388 npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]);
389 if (status & BIT_5)
390 npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]);
391 if (status & BIT_6)
392 npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]);
393 if (status & BIT_7)
394 npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]);
395 if (status & BIT_8)
396 npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]);
397 if (status & BIT_9)
398 npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]);
399
400 npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]);
401 npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]);
402 npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]);
403 npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]);
404
405 dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n"
406 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n"
407 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n"
408 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n"
409 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n"
410 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n",
411 npar_info->min_tx_bw, npar_info->max_tx_bw,
412 npar_info->max_tx_ques, npar_info->max_tx_mac_filters,
413 npar_info->max_rx_mcast_mac_filters,
414 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr,
415 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings,
416 npar_info->max_rx_buf_rings, npar_info->max_rx_ques,
417 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs,
418 npar_info->max_remote_ipv6_addrs);
419
420 qlcnic_free_mbx_args(&cmd);
421 return err;
422}
423
91b7282b 424static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter,
991ca269 425 struct qlcnic_cmd_args *cmd)
91b7282b 426{
991ca269
MC		 427 adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff;
428 adapter->flags &= ~QLCNIC_TAGGING_ENABLED;
91b7282b
RB		 429 return 0;
430}
431
432static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter,
433 struct qlcnic_cmd_args *cmd)
434{
435 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
436 int i, num_vlans;
437 u16 *vlans;
438
439 if (sriov->allowed_vlans)
440 return 0;
441
442 sriov->any_vlan = cmd->rsp.arg[2] & 0xf;
154d0c81
MC		 443 sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16;
444 dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n",
445 sriov->num_allowed_vlans);
446
447 qlcnic_sriov_alloc_vlans(adapter);
448
91b7282b
RB		 449 if (!sriov->any_vlan)
450 return 0;
451
91b7282b
RB		 452 num_vlans = sriov->num_allowed_vlans;
453 sriov->allowed_vlans = kzalloc(sizeof(u16) * num_vlans, GFP_KERNEL);
454 if (!sriov->allowed_vlans)
455 return -ENOMEM;
456
457 vlans = (u16 *)&cmd->rsp.arg[3];
458 for (i = 0; i < num_vlans; i++)
459 sriov->allowed_vlans[i] = vlans[i];
460
461 return 0;
462}
463
bcf6cb1a 464static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter)
91b7282b
RB		 465{
466 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
467 struct qlcnic_cmd_args cmd;
991ca269 468 int ret = 0;
91b7282b 469
c5316920 470 memset(&cmd, 0, sizeof(cmd));
91b7282b
RB		 471 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL);
472 if (ret)
473 return ret;
474
475 ret = qlcnic_issue_cmd(adapter, &cmd);
476 if (ret) {
477 dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n",
478 ret);
479 } else {
480 sriov->vlan_mode = cmd.rsp.arg[1] & 0x3;
481 switch (sriov->vlan_mode) {
482 case QLC_GUEST_VLAN_MODE:
483 ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd);
484 break;
485 case QLC_PVID_MODE:
991ca269 486 ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd);
91b7282b
RB		 487 break;
488 }
489 }
490
491 qlcnic_free_mbx_args(&cmd);
492 return ret;
493}
494
7cb03b23
RB		 495static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter)
496{
7cb03b23 497 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 498 struct qlcnic_info nic_info;
7cb03b23
RB		 499 int err;
500
4000e7a7
RB		 501 err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0);
502 if (err)
503 return err;
504
154d0c81
MC		 505 ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters;
506
7cb03b23
RB		 507 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
508 if (err)
509 return -EIO;
510
511 if (qlcnic_83xx_get_port_info(adapter))
512 return -EIO;
513
514 qlcnic_sriov_vf_cfg_buff_desc(adapter);
515 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
516 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
517 adapter->ahw->fw_hal_version);
518
519 ahw->physical_port = (u8) nic_info.phys_port;
520 ahw->switch_mode = nic_info.switch_mode;
521 ahw->max_mtu = nic_info.max_mtu;
522 ahw->op_mode = nic_info.op_mode;
523 ahw->capabilities = nic_info.capabilities;
524 return 0;
525}
526
f8468331
RB		 527static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
528 int pci_using_dac)
529{
530 int err;
531
d747c333
RB		 532 adapter->flags |= QLCNIC_VLAN_FILTERING;
533 adapter->ahw->total_nic_func = 1;
e8b508ef 534 INIT_LIST_HEAD(&adapter->vf_mc_list);
f8468331
RB		 535 if (!qlcnic_use_msi_x && !!qlcnic_use_msi)
536 dev_warn(&adapter->pdev->dev,
01b91f4c 537 "Device does not support MSI interrupts\n");
f8468331 538
34e8c406
HM		 539 /* compute and set default and max tx/sds rings */
540 qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING);
541 qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING);
542
543 err = qlcnic_setup_intr(adapter);
f8468331
RB		 544 if (err) {
545 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
546 goto err_out_disable_msi;
547 }
548
549 err = qlcnic_83xx_setup_mbx_intr(adapter);
550 if (err)
551 goto err_out_disable_msi;
552
553 err = qlcnic_sriov_init(adapter, 1);
554 if (err)
555 goto err_out_disable_mbx_intr;
556
f197a7aa 557 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
f8468331
RB		 558 if (err)
559 goto err_out_cleanup_sriov;
560
f197a7aa
RB		 561 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
562 if (err)
563 goto err_out_disable_bc_intr;
564
7cb03b23
RB		 565 err = qlcnic_sriov_vf_init_driver(adapter);
566 if (err)
567 goto err_out_send_channel_term;
568
bcf6cb1a
RB		 569 err = qlcnic_sriov_get_vf_acl(adapter);
570 if (err)
571 goto err_out_send_channel_term;
572
f197a7aa
RB		 573 err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
574 if (err)
575 goto err_out_send_channel_term;
576
f8468331
RB		 577 pci_set_drvdata(adapter->pdev, adapter);
578 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
579 adapter->netdev->name);
14d385b9 580
f036e4f4
RB		 581 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
582 adapter->ahw->idc.delay);
f8468331
RB		 583 return 0;
584
f197a7aa
RB		 585err_out_send_channel_term:
586 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
587
588err_out_disable_bc_intr:
589 qlcnic_sriov_cfg_bc_intr(adapter, 0);
590
f8468331
RB		 591err_out_cleanup_sriov:
592 __qlcnic_sriov_cleanup(adapter);
593
594err_out_disable_mbx_intr:
595 qlcnic_83xx_free_mbx_intr(adapter);
596
597err_out_disable_msi:
598 qlcnic_teardown_intr(adapter);
599 return err;
600}
601
f036e4f4
RB		 602static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter)
603{
604 u32 state;
605
606 do {
607 msleep(20);
608 if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT)
609 return -EIO;
610 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
611 } while (state != QLC_83XX_IDC_DEV_READY);
612
613 return 0;
614}
615
f8468331
RB		 616int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter, int pci_using_dac)
617{
618 struct qlcnic_hardware_context *ahw = adapter->ahw;
f036e4f4 619 int err;
f8468331 620
f036e4f4
RB		 621 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status);
622 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
623 ahw->reset_context = 0;
624 adapter->fw_fail_cnt = 0;
f8468331 625 ahw->msix_supported = 1;
f036e4f4 626 adapter->need_fw_reset = 0;
da6c8063 627 adapter->flags |= QLCNIC_TX_INTR_SHARED;
f8468331 628
f036e4f4
RB		 629 err = qlcnic_sriov_check_dev_ready(adapter);
630 if (err)
631 return err;
632
633 err = qlcnic_sriov_setup_vf(adapter, pci_using_dac);
634 if (err)
635 return err;
f8468331
RB		 636
637 if (qlcnic_read_mac_addr(adapter))
638 dev_warn(&adapter->pdev->dev, "failed to read mac addr\n");
639
1267ff96
SC		 640 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
641
f8468331 642 clear_bit(__QLCNIC_RESETTING, &adapter->state);
f8468331
RB		 643 return 0;
644}
645
646void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter)
647{
648 struct qlcnic_hardware_context *ahw = adapter->ahw;
649
650 ahw->op_mode = QLCNIC_SRIOV_VF_FUNC;
651 dev_info(&adapter->pdev->dev,
652 "HAL Version: %d Non Privileged SRIOV function\n",
653 ahw->fw_hal_version);
654 adapter->nic_ops = &qlcnic_sriov_vf_ops;
655 set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state);
656 return;
657}
658
659void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
660{
661 ahw->hw_ops = &qlcnic_sriov_vf_hw_ops;
662 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
663 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
02feda17 664}
f197a7aa
RB		 665
666static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
667{
668 u32 pay_size;
669
670 pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
671
672 if (pay_size)
673 pay_size = QLC_BC_PAYLOAD_SZ;
674 else
675 pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
676
677 return pay_size;
678}
679
680int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
681{
682 struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
683 u8 i;
684
685 if (qlcnic_sriov_vf_check(adapter))
686 return 0;
687
688 for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
689 if (vf_info[i].pci_func == pci_func)
690 return i;
691 }
692
693 return -EINVAL;
694}
695
696static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
697{
698 *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
699 if (!*trans)
700 return -ENOMEM;
701
702 init_completion(&(*trans)->resp_cmpl);
703 return 0;
704}
705
706static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
707 u32 size)
708{
709 *hdr = kzalloc(sizeof(struct qlcnic_bc_hdr) * size, GFP_ATOMIC);
710 if (!*hdr)
711 return -ENOMEM;
712
713 return 0;
714}
715
716static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
717{
718 const struct qlcnic_mailbox_metadata *mbx_tbl;
719 int i, size;
720
721 mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
722 size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
723
724 for (i = 0; i < size; i++) {
725 if (type == mbx_tbl[i].cmd) {
726 mbx->op_type = QLC_BC_CMD;
727 mbx->req.num = mbx_tbl[i].in_args;
728 mbx->rsp.num = mbx_tbl[i].out_args;
729 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
730 GFP_ATOMIC);
731 if (!mbx->req.arg)
732 return -ENOMEM;
733 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
734 GFP_ATOMIC);
735 if (!mbx->rsp.arg) {
736 kfree(mbx->req.arg);
737 mbx->req.arg = NULL;
738 return -ENOMEM;
739 }
f197a7aa
RB		 740 mbx->req.arg[0] = (type | (mbx->req.num << 16) |
741 (3 << 29));
6226204b 742 mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16;
f197a7aa
RB		 743 return 0;
744 }
745 }
746 return -EINVAL;
747}
748
749static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
750 struct qlcnic_cmd_args *cmd,
751 u16 seq, u8 msg_type)
752{
753 struct qlcnic_bc_hdr *hdr;
754 int i;
755 u32 num_regs, bc_pay_sz;
756 u16 remainder;
757 u8 cmd_op, num_frags, t_num_frags;
758
759 bc_pay_sz = QLC_BC_PAYLOAD_SZ;
760 if (msg_type == QLC_BC_COMMAND) {
761 trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
762 trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
763 num_regs = cmd->req.num;
764 trans->req_pay_size = (num_regs * 4);
765 num_regs = cmd->rsp.num;
766 trans->rsp_pay_size = (num_regs * 4);
767 cmd_op = cmd->req.arg[0] & 0xff;
768 remainder = (trans->req_pay_size) % (bc_pay_sz);
769 num_frags = (trans->req_pay_size) / (bc_pay_sz);
770 if (remainder)
771 num_frags++;
772 t_num_frags = num_frags;
773 if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
774 return -ENOMEM;
775 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
776 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
777 if (remainder)
778 num_frags++;
779 if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
780 return -ENOMEM;
781 num_frags = t_num_frags;
782 hdr = trans->req_hdr;
783 } else {
784 cmd->req.arg = (u32 *)trans->req_pay;
785 cmd->rsp.arg = (u32 *)trans->rsp_pay;
786 cmd_op = cmd->req.arg[0] & 0xff;
d747c333 787 cmd->cmd_op = cmd_op;
f197a7aa
RB		 788 remainder = (trans->rsp_pay_size) % (bc_pay_sz);
789 num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
790 if (remainder)
791 num_frags++;
792 cmd->req.num = trans->req_pay_size / 4;
793 cmd->rsp.num = trans->rsp_pay_size / 4;
794 hdr = trans->rsp_hdr;
6226204b 795 cmd->op_type = trans->req_hdr->op_type;
f197a7aa
RB		 796 }
797
798 trans->trans_id = seq;
799 trans->cmd_id = cmd_op;
800 for (i = 0; i < num_frags; i++) {
801 hdr[i].version = 2;
802 hdr[i].msg_type = msg_type;
803 hdr[i].op_type = cmd->op_type;
804 hdr[i].num_cmds = 1;
805 hdr[i].num_frags = num_frags;
806 hdr[i].frag_num = i + 1;
807 hdr[i].cmd_op = cmd_op;
808 hdr[i].seq_id = seq;
809 }
810 return 0;
811}
812
813static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
814{
815 if (!trans)
816 return;
817 kfree(trans->req_hdr);
818 kfree(trans->rsp_hdr);
819 kfree(trans);
820}
821
822static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
823 struct qlcnic_bc_trans *trans, u8 type)
824{
825 struct qlcnic_trans_list *t_list;
826 unsigned long flags;
827 int ret = 0;
828
829 if (type == QLC_BC_RESPONSE) {
830 t_list = &vf->rcv_act;
831 spin_lock_irqsave(&t_list->lock, flags);
832 t_list->count--;
833 list_del(&trans->list);
834 if (t_list->count > 0)
835 ret = 1;
836 spin_unlock_irqrestore(&t_list->lock, flags);
837 }
838 if (type == QLC_BC_COMMAND) {
839 while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
840 msleep(100);
841 vf->send_cmd = NULL;
842 clear_bit(QLC_BC_VF_SEND, &vf->state);
843 }
844 return ret;
845}
846
847static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
848 struct qlcnic_vf_info *vf,
849 work_func_t func)
850{
f036e4f4
RB		 851 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
852 vf->adapter->need_fw_reset)
97d8105c
RB		 853 return;
854
f197a7aa
RB		 855 queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
856}
857
858static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
859{
860 struct completion *cmpl = &trans->resp_cmpl;
861
862 if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
863 trans->trans_state = QLC_END;
864 else
865 trans->trans_state = QLC_ABORT;
866
867 return;
868}
869
870static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
871 u8 type)
872{
873 if (type == QLC_BC_RESPONSE) {
874 trans->curr_rsp_frag++;
875 if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
876 trans->trans_state = QLC_INIT;
877 else
878 trans->trans_state = QLC_END;
879 } else {
880 trans->curr_req_frag++;
881 if (trans->curr_req_frag < trans->req_hdr->num_frags)
882 trans->trans_state = QLC_INIT;
883 else
884 trans->trans_state = QLC_WAIT_FOR_RESP;
885 }
886}
887
888static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
889 u8 type)
890{
891 struct qlcnic_vf_info *vf = trans->vf;
892 struct completion *cmpl = &vf->ch_free_cmpl;
893
894 if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
895 trans->trans_state = QLC_ABORT;
896 return;
897 }
898
899 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
900 qlcnic_sriov_handle_multi_frags(trans, type);
901}
902
903static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
904 u32 *hdr, u32 *pay, u32 size)
905{
906 struct qlcnic_hardware_context *ahw = adapter->ahw;
907 u32 fw_mbx;
908 u8 i, max = 2, hdr_size, j;
909
910 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
911 max = (size / sizeof(u32)) + hdr_size;
912
913 fw_mbx = readl(QLCNIC_MBX_FW(ahw, 0));
914 for (i = 2, j = 0; j < hdr_size; i++, j++)
915 *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
916 for (; j < max; i++, j++)
917 *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
918}
919
920static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
921{
922 int ret = -EBUSY;
923 u32 timeout = 10000;
924
925 do {
926 if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
927 ret = 0;
928 break;
929 }
930 mdelay(1);
931 } while (--timeout);
932
933 return ret;
934}
935
936static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
937{
938 struct qlcnic_vf_info *vf = trans->vf;
939 u32 pay_size, hdr_size;
940 u32 *hdr, *pay;
941 int ret;
942 u8 pci_func = trans->func_id;
943
944 if (__qlcnic_sriov_issue_bc_post(vf))
945 return -EBUSY;
946
947 if (type == QLC_BC_COMMAND) {
948 hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
949 pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
950 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
951 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
952 trans->curr_req_frag);
953 pay_size = (pay_size / sizeof(u32));
954 } else {
955 hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
956 pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
957 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
958 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
959 trans->curr_rsp_frag);
960 pay_size = (pay_size / sizeof(u32));
961 }
962
963 ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
964 pci_func, pay_size);
965 return ret;
966}
967
968static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
969 struct qlcnic_vf_info *vf, u8 type)
970{
f197a7aa 971 bool flag = true;
97d8105c 972 int err = -EIO;
f197a7aa
RB		 973
974 while (flag) {
f036e4f4
RB		 975 if (test_bit(QLC_BC_VF_FLR, &vf->state) ||
976 vf->adapter->need_fw_reset)
97d8105c
RB		 977 trans->trans_state = QLC_ABORT;
978
f197a7aa
RB		 979 switch (trans->trans_state) {
980 case QLC_INIT:
981 trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
982 if (qlcnic_sriov_issue_bc_post(trans, type))
983 trans->trans_state = QLC_ABORT;
984 break;
985 case QLC_WAIT_FOR_CHANNEL_FREE:
986 qlcnic_sriov_wait_for_channel_free(trans, type);
987 break;
988 case QLC_WAIT_FOR_RESP:
989 qlcnic_sriov_wait_for_resp(trans);
990 break;
991 case QLC_END:
992 err = 0;
993 flag = false;
994 break;
995 case QLC_ABORT:
996 err = -EIO;
997 flag = false;
998 clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
999 break;
1000 default:
1001 err = -EIO;
1002 flag = false;
1003 }
1004 }
1005 return err;
1006}
1007
1008static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
1009 struct qlcnic_bc_trans *trans, int pci_func)
1010{
1011 struct qlcnic_vf_info *vf;
1012 int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
1013
1014 if (index < 0)
1015 return -EIO;
1016
1017 vf = &adapter->ahw->sriov->vf_info[index];
1018 trans->vf = vf;
1019 trans->func_id = pci_func;
1020
1021 if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
1022 if (qlcnic_sriov_pf_check(adapter))
1023 return -EIO;
1024 if (qlcnic_sriov_vf_check(adapter) &&
1025 trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
1026 return -EIO;
1027 }
1028
1029 mutex_lock(&vf->send_cmd_lock);
1030 vf->send_cmd = trans;
1031 err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
1032 qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
1033 mutex_unlock(&vf->send_cmd_lock);
1034 return err;
1035}
1036
1037static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
1038 struct qlcnic_bc_trans *trans,
1039 struct qlcnic_cmd_args *cmd)
1040{
1041#ifdef CONFIG_QLCNIC_SRIOV
1042 if (qlcnic_sriov_pf_check(adapter)) {
1043 qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
1044 return;
1045 }
1046#endif
1047 cmd->rsp.arg[0] |= (0x9 << 25);
1048 return;
1049}
1050
1051static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
1052{
1053 struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
1054 trans_work);
1055 struct qlcnic_bc_trans *trans = NULL;
1056 struct qlcnic_adapter *adapter = vf->adapter;
1057 struct qlcnic_cmd_args cmd;
1058 u8 req;
1059
f036e4f4
RB		 1060 if (adapter->need_fw_reset)
1061 return;
1062
97d8105c
RB		 1063 if (test_bit(QLC_BC_VF_FLR, &vf->state))
1064 return;
1065
e5c4e6c6 1066 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
f197a7aa
RB		 1067 trans = list_first_entry(&vf->rcv_act.wait_list,
1068 struct qlcnic_bc_trans, list);
1069 adapter = vf->adapter;
1070
1071 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
1072 QLC_BC_RESPONSE))
1073 goto cleanup_trans;
1074
1075 __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
1076 trans->trans_state = QLC_INIT;
1077 __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
1078
1079cleanup_trans:
1080 qlcnic_free_mbx_args(&cmd);
1081 req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
1082 qlcnic_sriov_cleanup_transaction(trans);
1083 if (req)
1084 qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
1085 qlcnic_sriov_process_bc_cmd);
1086}
1087
1088static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
1089 struct qlcnic_vf_info *vf)
1090{
1091 struct qlcnic_bc_trans *trans;
1092 u32 pay_size;
1093
1094 if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
1095 return;
1096
1097 trans = vf->send_cmd;
1098
1099 if (trans == NULL)
1100 goto clear_send;
1101
1102 if (trans->trans_id != hdr->seq_id)
1103 goto clear_send;
1104
1105 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
1106 trans->curr_rsp_frag);
1107 qlcnic_sriov_pull_bc_msg(vf->adapter,
1108 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
1109 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
1110 pay_size);
1111 if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
1112 goto clear_send;
1113
1114 complete(&trans->resp_cmpl);
1115
1116clear_send:
1117 clear_bit(QLC_BC_VF_SEND, &vf->state);
1118}
1119
97d8105c
RB		 1120int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1121 struct qlcnic_vf_info *vf,
1122 struct qlcnic_bc_trans *trans)
f197a7aa
RB		 1123{
1124 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1125
f197a7aa
RB		 1126 t_list->count++;
1127 list_add_tail(&trans->list, &t_list->wait_list);
1128 if (t_list->count == 1)
1129 qlcnic_sriov_schedule_bc_cmd(sriov, vf,
1130 qlcnic_sriov_process_bc_cmd);
97d8105c
RB		 1131 return 0;
1132}
1133
1134static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
1135 struct qlcnic_vf_info *vf,
1136 struct qlcnic_bc_trans *trans)
1137{
1138 struct qlcnic_trans_list *t_list = &vf->rcv_act;
1139
1140 spin_lock(&t_list->lock);
1141
1142 __qlcnic_sriov_add_act_list(sriov, vf, trans);
1143
f197a7aa
RB		 1144 spin_unlock(&t_list->lock);
1145 return 0;
1146}
1147
1148static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
1149 struct qlcnic_vf_info *vf,
1150 struct qlcnic_bc_hdr *hdr)
1151{
1152 struct qlcnic_bc_trans *trans = NULL;
1153 struct list_head *node;
1154 u32 pay_size, curr_frag;
1155 u8 found = 0, active = 0;
1156
1157 spin_lock(&vf->rcv_pend.lock);
1158 if (vf->rcv_pend.count > 0) {
1159 list_for_each(node, &vf->rcv_pend.wait_list) {
1160 trans = list_entry(node, struct qlcnic_bc_trans, list);
1161 if (trans->trans_id == hdr->seq_id) {
1162 found = 1;
1163 break;
1164 }
1165 }
1166 }
1167
1168 if (found) {
1169 curr_frag = trans->curr_req_frag;
1170 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1171 curr_frag);
1172 qlcnic_sriov_pull_bc_msg(vf->adapter,
1173 (u32 *)(trans->req_hdr + curr_frag),
1174 (u32 *)(trans->req_pay + curr_frag),
1175 pay_size);
1176 trans->curr_req_frag++;
1177 if (trans->curr_req_frag >= hdr->num_frags) {
1178 vf->rcv_pend.count--;
1179 list_del(&trans->list);
1180 active = 1;
1181 }
1182 }
1183 spin_unlock(&vf->rcv_pend.lock);
1184
1185 if (active)
1186 if (qlcnic_sriov_add_act_list(sriov, vf, trans))
1187 qlcnic_sriov_cleanup_transaction(trans);
1188
1189 return;
1190}
1191
1192static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
1193 struct qlcnic_bc_hdr *hdr,
1194 struct qlcnic_vf_info *vf)
1195{
1196 struct qlcnic_bc_trans *trans;
1197 struct qlcnic_adapter *adapter = vf->adapter;
1198 struct qlcnic_cmd_args cmd;
1199 u32 pay_size;
1200 int err;
1201 u8 cmd_op;
1202
f036e4f4
RB		 1203 if (adapter->need_fw_reset)
1204 return;
1205
f197a7aa
RB		 1206 if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
1207 hdr->op_type != QLC_BC_CMD &&
1208 hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
1209 return;
1210
1211 if (hdr->frag_num > 1) {
1212 qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
1213 return;
1214 }
1215
e5c4e6c6 1216 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args));
f197a7aa
RB		 1217 cmd_op = hdr->cmd_op;
1218 if (qlcnic_sriov_alloc_bc_trans(&trans))
1219 return;
1220
1221 if (hdr->op_type == QLC_BC_CMD)
1222 err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
1223 else
1224 err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
1225
1226 if (err) {
1227 qlcnic_sriov_cleanup_transaction(trans);
1228 return;
1229 }
1230
1231 cmd.op_type = hdr->op_type;
1232 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
1233 QLC_BC_COMMAND)) {
1234 qlcnic_free_mbx_args(&cmd);
1235 qlcnic_sriov_cleanup_transaction(trans);
1236 return;
1237 }
1238
1239 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
1240 trans->curr_req_frag);
1241 qlcnic_sriov_pull_bc_msg(vf->adapter,
1242 (u32 *)(trans->req_hdr + trans->curr_req_frag),
1243 (u32 *)(trans->req_pay + trans->curr_req_frag),
1244 pay_size);
1245 trans->func_id = vf->pci_func;
1246 trans->vf = vf;
1247 trans->trans_id = hdr->seq_id;
1248 trans->curr_req_frag++;
97d8105c
RB		 1249
1250 if (qlcnic_sriov_soft_flr_check(adapter, trans, vf))
1251 return;
1252
f197a7aa
RB		 1253 if (trans->curr_req_frag == trans->req_hdr->num_frags) {
1254 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
1255 qlcnic_free_mbx_args(&cmd);
1256 qlcnic_sriov_cleanup_transaction(trans);
1257 }
1258 } else {
1259 spin_lock(&vf->rcv_pend.lock);
1260 list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
1261 vf->rcv_pend.count++;
1262 spin_unlock(&vf->rcv_pend.lock);
1263 }
1264}
1265
1266static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
1267 struct qlcnic_vf_info *vf)
1268{
1269 struct qlcnic_bc_hdr hdr;
1270 u32 *ptr = (u32 *)&hdr;
1271 u8 msg_type, i;
1272
1273 for (i = 2; i < 6; i++)
1274 ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
1275 msg_type = hdr.msg_type;
1276
1277 switch (msg_type) {
1278 case QLC_BC_COMMAND:
1279 qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
1280 break;
1281 case QLC_BC_RESPONSE:
1282 qlcnic_sriov_handle_bc_resp(&hdr, vf);
1283 break;
1284 }
1285}
1286
97d8105c
RB		 1287static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov,
1288 struct qlcnic_vf_info *vf)
1289{
1290 struct qlcnic_adapter *adapter = vf->adapter;
1291
1292 if (qlcnic_sriov_pf_check(adapter))
1293 qlcnic_sriov_pf_handle_flr(sriov, vf);
1294 else
1295 dev_err(&adapter->pdev->dev,
1296 "Invalid event to VF. VF should not get FLR event\n");
1297}
1298
f197a7aa
RB		 1299void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
1300{
1301 struct qlcnic_vf_info *vf;
1302 struct qlcnic_sriov *sriov;
1303 int index;
1304 u8 pci_func;
1305
1306 sriov = adapter->ahw->sriov;
1307 pci_func = qlcnic_sriov_target_func_id(event);
1308 index = qlcnic_sriov_func_to_index(adapter, pci_func);
1309
1310 if (index < 0)
1311 return;
1312
1313 vf = &sriov->vf_info[index];
1314 vf->pci_func = pci_func;
1315
1316 if (qlcnic_sriov_channel_free_check(event))
1317 complete(&vf->ch_free_cmpl);
1318
97d8105c
RB		 1319 if (qlcnic_sriov_flr_check(event)) {
1320 qlcnic_sriov_handle_flr_event(sriov, vf);
1321 return;
1322 }
1323
f197a7aa
RB		 1324 if (qlcnic_sriov_bc_msg_check(event))
1325 qlcnic_sriov_handle_msg_event(sriov, vf);
1326}
1327
1328int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
1329{
1330 struct qlcnic_cmd_args cmd;
1331 int err;
1332
1333 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
1334 return 0;
1335
1336 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
1337 return -ENOMEM;
1338
1339 if (enable)
1340 cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
1341
e5c4e6c6 1342 err = qlcnic_83xx_issue_cmd(adapter, &cmd);
f197a7aa
RB		 1343
1344 if (err != QLCNIC_RCODE_SUCCESS) {
1345 dev_err(&adapter->pdev->dev,
1346 "Failed to %s bc events, err=%d\n",
1347 (enable ? "enable" : "disable"), err);
1348 }
1349
1350 qlcnic_free_mbx_args(&cmd);
1351 return err;
1352}
1353
f036e4f4
RB		 1354static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter,
1355 struct qlcnic_bc_trans *trans)
1356{
1357 u8 max = QLC_BC_CMD_MAX_RETRY_CNT;
1358 u32 state;
1359
1360 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1361 if (state == QLC_83XX_IDC_DEV_READY) {
1362 msleep(20);
1363 clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state);
1364 trans->trans_state = QLC_INIT;
1365 if (++adapter->fw_fail_cnt > max)
1366 return -EIO;
1367 else
1368 return 0;
1369 }
1370
1371 return -EIO;
1372}
1373
74b7ba1a 1374static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
f197a7aa
RB		 1375 struct qlcnic_cmd_args *cmd)
1376{
f036e4f4 1377 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 1378 struct qlcnic_mailbox *mbx = ahw->mailbox;
f036e4f4 1379 struct device *dev = &adapter->pdev->dev;
f197a7aa
RB		 1380 struct qlcnic_bc_trans *trans;
1381 int err;
1382 u32 rsp_data, opcode, mbx_err_code, rsp;
1383 u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
f036e4f4 1384 u8 func = ahw->pci_func;
f197a7aa 1385
f036e4f4
RB		 1386 rsp = qlcnic_sriov_alloc_bc_trans(&trans);
1387 if (rsp)
ab0648e8 1388 goto free_cmd;
f197a7aa 1389
f036e4f4
RB		 1390 rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND);
1391 if (rsp)
1392 goto cleanup_transaction;
f197a7aa 1393
f036e4f4 1394retry:
068a8d19 1395 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
f197a7aa
RB		 1396 rsp = -EIO;
1397 QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
f036e4f4 1398 QLCNIC_MBX_RSP(cmd->req.arg[0]), func);
f197a7aa
RB		 1399 goto err_out;
1400 }
1401
f036e4f4 1402 err = qlcnic_sriov_send_bc_cmd(adapter, trans, func);
f197a7aa 1403 if (err) {
f036e4f4
RB		 1404 dev_err(dev, "MBX command 0x%x timed out for VF %d\n",
1405 (cmd->req.arg[0] & 0xffff), func);
f197a7aa 1406 rsp = QLCNIC_RCODE_TIMEOUT;
f036e4f4
RB		 1407
1408 /* After adapter reset PF driver may take some time to
1409 * respond to VF's request. Retry request till maximum retries.
1410 */
1411 if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) &&
1412 !qlcnic_sriov_retry_bc_cmd(adapter, trans))
1413 goto retry;
1414
f197a7aa
RB		 1415 goto err_out;
1416 }
1417
1418 rsp_data = cmd->rsp.arg[0];
1419 mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
1420 opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
1421
1422 if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
1423 (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
1424 rsp = QLCNIC_RCODE_SUCCESS;
1425 } else {
d747c333
RB		 1426 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1427 rsp = QLCNIC_RCODE_SUCCESS;
1428 } else {
1429 rsp = mbx_err_code;
1430 if (!rsp)
1431 rsp = 1;
1432
1433 dev_err(dev,
1434 "MBX command 0x%x failed with err:0x%x for VF %d\n",
1435 opcode, mbx_err_code, func);
1436 }
f197a7aa
RB		 1437 }
1438
1439err_out:
f036e4f4
RB		 1440 if (rsp == QLCNIC_RCODE_TIMEOUT) {
1441 ahw->reset_context = 1;
1442 adapter->need_fw_reset = 1;
068a8d19 1443 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
f036e4f4
RB		 1444 }
1445
1446cleanup_transaction:
f197a7aa 1447 qlcnic_sriov_cleanup_transaction(trans);
ab0648e8
RB		 1448
1449free_cmd:
1450 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
1451 qlcnic_free_mbx_args(cmd);
1452 kfree(cmd);
1453 }
1454
f197a7aa
RB		 1455 return rsp;
1456}
1457
74b7ba1a
RB		 1458
1459static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter,
1460 struct qlcnic_cmd_args *cmd)
1461{
1462 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT)
1463 return qlcnic_sriov_async_issue_cmd(adapter, cmd);
1464 else
1465 return __qlcnic_sriov_issue_cmd(adapter, cmd);
1466}
1467
21041400 1468static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
f197a7aa
RB		 1469{
1470 struct qlcnic_cmd_args cmd;
1471 struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
1472 int ret;
1473
c5316920 1474 memset(&cmd, 0, sizeof(cmd));
f197a7aa
RB		 1475 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
1476 return -ENOMEM;
1477
1478 ret = qlcnic_issue_cmd(adapter, &cmd);
1479 if (ret) {
1480 dev_err(&adapter->pdev->dev,
1481 "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
1482 ret);
1483 goto out;
1484 }
1485
1486 cmd_op = (cmd.rsp.arg[0] & 0xff);
1487 if (cmd.rsp.arg[0] >> 25 == 2)
1488 return 2;
1489 if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
1490 set_bit(QLC_BC_VF_STATE, &vf->state);
1491 else
1492 clear_bit(QLC_BC_VF_STATE, &vf->state);
1493
1494out:
1495 qlcnic_free_mbx_args(&cmd);
1496 return ret;
1497}
e8b508ef 1498
fe79fabb
SS		 1499static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac,
1500 enum qlcnic_mac_type mac_type)
e8b508ef
RB		 1501{
1502 struct qlcnic_adapter *adapter = netdev_priv(netdev);
154d0c81 1503 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
154d0c81
MC		 1504 struct qlcnic_vf_info *vf;
1505 u16 vlan_id;
1506 int i;
e8b508ef 1507
154d0c81 1508 vf = &adapter->ahw->sriov->vf_info[0];
e8b508ef 1509
74b7ba1a 1510 if (!qlcnic_sriov_check_any_vlan(vf)) {
fe79fabb 1511 qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
74b7ba1a
RB		 1512 } else {
1513 spin_lock(&vf->vlan_list_lock);
1514 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1515 vlan_id = vf->sriov_vlans[i];
1516 if (vlan_id)
fe79fabb
SS		 1517 qlcnic_nic_add_mac(adapter, mac, vlan_id,
1518 mac_type);
154d0c81 1519 }
74b7ba1a
RB		 1520 spin_unlock(&vf->vlan_list_lock);
1521 if (qlcnic_84xx_check(adapter))
fe79fabb 1522 qlcnic_nic_add_mac(adapter, mac, 0, mac_type);
e8b508ef
RB		 1523 }
1524}
1525
1526void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc)
1527{
2b10d3ec
MC		 1528 struct list_head *head = &bc->async_cmd_list;
1529 struct qlcnic_async_cmd *entry;
e8b508ef 1530
74b7ba1a 1531 flush_workqueue(bc->bc_async_wq);
2b10d3ec
MC		 1532 cancel_work_sync(&bc->vf_async_work);
1533
1534 spin_lock(&bc->queue_lock);
e8b508ef 1535 while (!list_empty(head)) {
2b10d3ec 1536 entry = list_entry(head->next, struct qlcnic_async_cmd,
e8b508ef 1537 list);
e8b508ef 1538 list_del(&entry->list);
2b10d3ec 1539 kfree(entry->cmd);
e8b508ef
RB		 1540 kfree(entry);
1541 }
2b10d3ec 1542 spin_unlock(&bc->queue_lock);
e8b508ef
RB		 1543}
1544
74b7ba1a 1545void qlcnic_sriov_vf_set_multi(struct net_device *netdev)
e8b508ef
RB		 1546{
1547 struct qlcnic_adapter *adapter = netdev_priv(netdev);
154d0c81 1548 struct qlcnic_hardware_context *ahw = adapter->ahw;
74b7ba1a
RB		 1549 static const u8 bcast_addr[ETH_ALEN] = {
1550 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
1551 };
1552 struct netdev_hw_addr *ha;
154d0c81 1553 u32 mode = VPORT_MISS_MODE_DROP;
e8b508ef
RB		 1554
1555 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
1556 return;
1557
154d0c81
MC		 1558 if (netdev->flags & IFF_PROMISC) {
1559 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
1560 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1561 } else if ((netdev->flags & IFF_ALLMULTI) ||
1562 (netdev_mc_count(netdev) > ahw->max_mc_count)) {
1563 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
74b7ba1a 1564 } else {
fe79fabb 1565 qlcnic_vf_add_mc_list(netdev, bcast_addr, QLCNIC_BROADCAST_MAC);
74b7ba1a 1566 if (!netdev_mc_empty(netdev)) {
fe79fabb 1567 qlcnic_flush_mcast_mac(adapter);
74b7ba1a 1568 netdev_for_each_mc_addr(ha, netdev)
fe79fabb
SS		 1569 qlcnic_vf_add_mc_list(netdev, ha->addr,
1570 QLCNIC_MULTICAST_MAC);
74b7ba1a 1571 }
154d0c81
MC		 1572 }
1573
d747c333
RB		 1574 /* configure unicast MAC address, if there is not sufficient space
1575 * to store all the unicast addresses then enable promiscuous mode
1576 */
1577 if (netdev_uc_count(netdev) > ahw->max_uc_count) {
1578 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1579 } else if (!netdev_uc_empty(netdev)) {
1580 netdev_for_each_uc_addr(ha, netdev)
fe79fabb
SS		 1581 qlcnic_vf_add_mc_list(netdev, ha->addr,
1582 QLCNIC_UNICAST_MAC);
d747c333
RB		 1583 }
1584
1585 if (adapter->pdev->is_virtfn) {
1586 if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
1587 !adapter->fdb_mac_learn) {
1588 qlcnic_alloc_lb_filters_mem(adapter);
1589 adapter->drv_mac_learn = 1;
1590 adapter->rx_mac_learn = true;
1591 } else {
1592 adapter->drv_mac_learn = 0;
1593 adapter->rx_mac_learn = false;
1594 }
1595 }
1596
154d0c81 1597 qlcnic_nic_set_promisc(adapter, mode);
e8b508ef
RB		 1598}
1599
74b7ba1a 1600static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work)
e8b508ef 1601{
2b10d3ec
MC		 1602 struct qlcnic_async_cmd *entry, *tmp;
1603 struct qlcnic_back_channel *bc;
74b7ba1a 1604 struct qlcnic_cmd_args *cmd;
2b10d3ec
MC		 1605 struct list_head *head;
1606 LIST_HEAD(del_list);
1607
1608 bc = container_of(work, struct qlcnic_back_channel, vf_async_work);
1609 head = &bc->async_cmd_list;
1610
1611 spin_lock(&bc->queue_lock);
1612 list_splice_init(head, &del_list);
1613 spin_unlock(&bc->queue_lock);
1614
1615 list_for_each_entry_safe(entry, tmp, &del_list, list) {
1616 list_del(&entry->list);
1617 cmd = entry->cmd;
1618 __qlcnic_sriov_issue_cmd(bc->adapter, cmd);
1619 kfree(entry);
1620 }
1621
1622 if (!list_empty(head))
1623 queue_work(bc->bc_async_wq, &bc->vf_async_work);
e8b508ef 1624
e8b508ef
RB		 1625 return;
1626}
1627
2b10d3ec
MC		 1628static struct qlcnic_async_cmd *
1629qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel *bc,
1630 struct qlcnic_cmd_args *cmd)
e8b508ef 1631{
2b10d3ec 1632 struct qlcnic_async_cmd *entry = NULL;
e8b508ef 1633
2b10d3ec
MC		 1634 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
1635 if (!entry)
1636 return NULL;
e8b508ef 1637
2b10d3ec
MC		 1638 entry->cmd = cmd;
1639
1640 spin_lock(&bc->queue_lock);
1641 list_add_tail(&entry->list, &bc->async_cmd_list);
1642 spin_unlock(&bc->queue_lock);
e8b508ef
RB		 1643
1644 return entry;
1645}
1646
74b7ba1a 1647static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc,
74b7ba1a 1648 struct qlcnic_cmd_args *cmd)
e8b508ef 1649{
2b10d3ec 1650 struct qlcnic_async_cmd *entry = NULL;
e8b508ef 1651
2b10d3ec
MC		 1652 entry = qlcnic_sriov_alloc_async_cmd(bc, cmd);
1653 if (!entry) {
1654 qlcnic_free_mbx_args(cmd);
1655 kfree(cmd);
e8b508ef 1656 return;
2b10d3ec 1657 }
e8b508ef 1658
2b10d3ec 1659 queue_work(bc->bc_async_wq, &bc->vf_async_work);
e8b508ef
RB		 1660}
1661
74b7ba1a
RB		 1662static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter,
1663 struct qlcnic_cmd_args *cmd)
e8b508ef
RB		 1664{
1665
e8b508ef
RB		 1666 struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc;
1667
f036e4f4 1668 if (adapter->need_fw_reset)
74b7ba1a 1669 return -EIO;
f036e4f4 1670
2b10d3ec
MC		 1671 qlcnic_sriov_schedule_async_cmd(bc, cmd);
1672
74b7ba1a 1673 return 0;
e8b508ef 1674}
f036e4f4
RB		 1675
1676static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter)
1677{
1678 int err;
1679
5c44bbda 1680 adapter->need_fw_reset = 0;
91b86e3d 1681 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
e5c4e6c6 1682 qlcnic_83xx_enable_mbx_interrupt(adapter);
f036e4f4
RB		 1683
1684 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
1685 if (err)
1686 return err;
1687
1688 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
1689 if (err)
1690 goto err_out_cleanup_bc_intr;
1691
1692 err = qlcnic_sriov_vf_init_driver(adapter);
1693 if (err)
1694 goto err_out_term_channel;
1695
1696 return 0;
1697
1698err_out_term_channel:
1699 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
1700
1701err_out_cleanup_bc_intr:
1702 qlcnic_sriov_cfg_bc_intr(adapter, 0);
1703 return err;
1704}
1705
1706static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter)
1707{
1708 struct net_device *netdev = adapter->netdev;
1709
1710 if (netif_running(netdev)) {
1711 if (!qlcnic_up(adapter, netdev))
1712 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1713 }
1714
1715 netif_device_attach(netdev);
1716}
1717
1718static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter)
1719{
1720 struct qlcnic_hardware_context *ahw = adapter->ahw;
1721 struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl;
1722 struct net_device *netdev = adapter->netdev;
1723 u8 i, max_ints = ahw->num_msix - 1;
1724
f036e4f4 1725 netif_device_detach(netdev);
068a8d19
MC		 1726 qlcnic_83xx_detach_mailbox_work(adapter);
1727 qlcnic_83xx_disable_mbx_intr(adapter);
1728
f036e4f4
RB		 1729 if (netif_running(netdev))
1730 qlcnic_down(adapter, netdev);
1731
1732 for (i = 0; i < max_ints; i++) {
1733 intr_tbl[i].id = i;
1734 intr_tbl[i].enabled = 0;
1735 intr_tbl[i].src = 0;
1736 }
1737 ahw->reset_context = 0;
1738}
1739
1740static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter)
1741{
1742 struct qlcnic_hardware_context *ahw = adapter->ahw;
1743 struct device *dev = &adapter->pdev->dev;
1744 struct qlc_83xx_idc *idc = &ahw->idc;
1745 u8 func = ahw->pci_func;
1746 u32 state;
1747
1748 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
1749 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) {
1750 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1751 qlcnic_sriov_vf_attach(adapter);
1752 adapter->fw_fail_cnt = 0;
1753 dev_info(dev,
8b513d0c 1754 "%s: Reinitialization of VF 0x%x done after FW reset\n",
f036e4f4
RB		 1755 __func__, func);
1756 } else {
1757 dev_err(dev,
1758 "%s: Reinitialization of VF 0x%x failed after FW reset\n",
1759 __func__, func);
1760 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1761 dev_info(dev, "Current state 0x%x after FW reset\n",
1762 state);
1763 }
1764 }
1765
1766 return 0;
1767}
1768
1769static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter)
1770{
1771 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 1772 struct qlcnic_mailbox *mbx = ahw->mailbox;
f036e4f4
RB		 1773 struct device *dev = &adapter->pdev->dev;
1774 struct qlc_83xx_idc *idc = &ahw->idc;
1775 u8 func = ahw->pci_func;
1776 u32 state;
1777
1778 adapter->reset_ctx_cnt++;
1779
1780 /* Skip the context reset and check if FW is hung */
1781 if (adapter->reset_ctx_cnt < 3) {
1782 adapter->need_fw_reset = 1;
068a8d19 1783 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
f036e4f4
RB		 1784 dev_info(dev,
1785 "Resetting context, wait here to check if FW is in failed state\n");
1786 return 0;
1787 }
1788
1789 /* Check if number of resets exceed the threshold.
1790 * If it exceeds the threshold just fail the VF.
1791 */
1792 if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) {
1793 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1794 adapter->tx_timeo_cnt = 0;
1795 adapter->fw_fail_cnt = 0;
1796 adapter->reset_ctx_cnt = 0;
1797 qlcnic_sriov_vf_detach(adapter);
1798 dev_err(dev,
1799 "Device context resets have exceeded the threshold, device interface will be shutdown\n");
1800 return -EIO;
1801 }
1802
1803 dev_info(dev, "Resetting context of VF 0x%x\n", func);
1804 dev_info(dev, "%s: Context reset count %d for VF 0x%x\n",
1805 __func__, adapter->reset_ctx_cnt, func);
1806 set_bit(__QLCNIC_RESETTING, &adapter->state);
1807 adapter->need_fw_reset = 1;
068a8d19 1808 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
f036e4f4
RB		 1809 qlcnic_sriov_vf_detach(adapter);
1810 adapter->need_fw_reset = 0;
1811
1812 if (!qlcnic_sriov_vf_reinit_driver(adapter)) {
1813 qlcnic_sriov_vf_attach(adapter);
f036e4f4
RB		 1814 adapter->tx_timeo_cnt = 0;
1815 adapter->reset_ctx_cnt = 0;
1816 adapter->fw_fail_cnt = 0;
1817 dev_info(dev, "Done resetting context for VF 0x%x\n", func);
1818 } else {
1819 dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n",
1820 __func__, func);
1821 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE);
1822 dev_info(dev, "%s: Current state 0x%x\n", __func__, state);
1823 }
1824
1825 return 0;
1826}
1827
1828static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter)
1829{
1830 struct qlcnic_hardware_context *ahw = adapter->ahw;
1831 int ret = 0;
1832
1833 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY)
1834 ret = qlcnic_sriov_vf_handle_dev_ready(adapter);
1835 else if (ahw->reset_context)
1836 ret = qlcnic_sriov_vf_handle_context_reset(adapter);
1837
1838 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1839 return ret;
1840}
1841
1842static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter)
1843{
1844 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1845
1846 dev_err(&adapter->pdev->dev, "Device is in failed state\n");
1847 if (idc->prev_state == QLC_83XX_IDC_DEV_READY)
1848 qlcnic_sriov_vf_detach(adapter);
1849
1850 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status);
1851 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1852 return -EIO;
1853}
1854
1855static int
1856qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter)
1857{
068a8d19 1858 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
f036e4f4
RB		 1859 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1860
1861 dev_info(&adapter->pdev->dev, "Device is in quiescent state\n");
1862 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1863 set_bit(__QLCNIC_RESETTING, &adapter->state);
1864 adapter->tx_timeo_cnt = 0;
1865 adapter->reset_ctx_cnt = 0;
068a8d19 1866 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
f036e4f4
RB		 1867 qlcnic_sriov_vf_detach(adapter);
1868 }
1869
1870 return 0;
1871}
1872
1873static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter)
1874{
068a8d19 1875 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
f036e4f4
RB		 1876 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
1877 u8 func = adapter->ahw->pci_func;
1878
1879 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) {
1880 dev_err(&adapter->pdev->dev,
1881 "Firmware hang detected by VF 0x%x\n", func);
1882 set_bit(__QLCNIC_RESETTING, &adapter->state);
1883 adapter->tx_timeo_cnt = 0;
1884 adapter->reset_ctx_cnt = 0;
068a8d19 1885 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
f036e4f4
RB		 1886 qlcnic_sriov_vf_detach(adapter);
1887 }
1888 return 0;
1889}
1890
1891static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter)
1892{
1893 dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__);
1894 return 0;
1895}
1896
d747c333
RB		 1897static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter)
1898{
1899 if (adapter->fhash.fnum)
1900 qlcnic_prune_lb_filters(adapter);
1901}
1902
f036e4f4
RB		 1903static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work)
1904{
1905 struct qlcnic_adapter *adapter;
1906 struct qlc_83xx_idc *idc;
1907 int ret = 0;
1908
1909 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1910 idc = &adapter->ahw->idc;
1911 idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1912
1913 switch (idc->curr_state) {
1914 case QLC_83XX_IDC_DEV_READY:
1915 ret = qlcnic_sriov_vf_idc_ready_state(adapter);
1916 break;
1917 case QLC_83XX_IDC_DEV_NEED_RESET:
1918 case QLC_83XX_IDC_DEV_INIT:
1919 ret = qlcnic_sriov_vf_idc_init_reset_state(adapter);
1920 break;
1921 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1922 ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter);
1923 break;
1924 case QLC_83XX_IDC_DEV_FAILED:
1925 ret = qlcnic_sriov_vf_idc_failed_state(adapter);
1926 break;
1927 case QLC_83XX_IDC_DEV_QUISCENT:
1928 break;
1929 default:
1930 ret = qlcnic_sriov_vf_idc_unknown_state(adapter);
1931 }
1932
1933 idc->prev_state = idc->curr_state;
d747c333
RB		 1934 qlcnic_sriov_vf_periodic_tasks(adapter);
1935
f036e4f4
RB		 1936 if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status))
1937 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
1938 idc->delay);
1939}
1940
1941static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter)
1942{
1943 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1944 msleep(20);
1945
1946 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1947 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1948 cancel_delayed_work_sync(&adapter->fw_work);
1949}
91b7282b 1950
154d0c81
MC		 1951static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov,
1952 struct qlcnic_vf_info *vf, u16 vlan_id)
1953{
1954 int i, err = -EINVAL;
1955
1956 if (!vf->sriov_vlans)
1957 return err;
1958
74b7ba1a 1959 spin_lock_bh(&vf->vlan_list_lock);
154d0c81
MC		 1960
1961 for (i = 0; i < sriov->num_allowed_vlans; i++) {
1962 if (vf->sriov_vlans[i] == vlan_id) {
1963 err = 0;
1964 break;
1965 }
1966 }
1967
74b7ba1a 1968 spin_unlock_bh(&vf->vlan_list_lock);
154d0c81
MC		 1969 return err;
1970}
1971
1972static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov,
1973 struct qlcnic_vf_info *vf)
1974{
1975 int err = 0;
1976
74b7ba1a 1977 spin_lock_bh(&vf->vlan_list_lock);
154d0c81
MC		 1978
1979 if (vf->num_vlan >= sriov->num_allowed_vlans)
1980 err = -EINVAL;
1981
74b7ba1a 1982 spin_unlock_bh(&vf->vlan_list_lock);
154d0c81
MC		 1983 return err;
1984}
1985
1986static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter,
91b7282b
RB		 1987 u16 vid, u8 enable)
1988{
154d0c81
MC		 1989 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
1990 struct qlcnic_vf_info *vf;
1991 bool vlan_exist;
91b7282b
RB		 1992 u8 allowed = 0;
1993 int i;
1994
154d0c81
MC		 1995 vf = &adapter->ahw->sriov->vf_info[0];
1996 vlan_exist = qlcnic_sriov_check_any_vlan(vf);
91b7282b
RB		 1997 if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE)
1998 return -EINVAL;
1999
2000 if (enable) {
154d0c81
MC		 2001 if (qlcnic_83xx_vf_check(adapter) && vlan_exist)
2002 return -EINVAL;
2003
2004 if (qlcnic_sriov_validate_num_vlans(sriov, vf))
91b7282b
RB		 2005 return -EINVAL;
2006
2007 if (sriov->any_vlan) {
2008 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2009 if (sriov->allowed_vlans[i] == vid)
2010 allowed = 1;
2011 }
2012
2013 if (!allowed)
2014 return -EINVAL;
2015 }
2016 } else {
154d0c81 2017 if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid))
91b7282b
RB		 2018 return -EINVAL;
2019 }
2020
2021 return 0;
2022}
2023
154d0c81
MC		 2024static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id,
2025 enum qlcnic_vlan_operations opcode)
2026{
2027 struct qlcnic_adapter *adapter = vf->adapter;
2028 struct qlcnic_sriov *sriov;
2029
2030 sriov = adapter->ahw->sriov;
2031
2032 if (!vf->sriov_vlans)
2033 return;
2034
74b7ba1a 2035 spin_lock_bh(&vf->vlan_list_lock);
154d0c81
MC		 2036
2037 switch (opcode) {
2038 case QLC_VLAN_ADD:
2039 qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id);
2040 break;
2041 case QLC_VLAN_DELETE:
2042 qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id);
2043 break;
2044 default:
2045 netdev_err(adapter->netdev, "Invalid VLAN operation\n");
2046 }
2047
74b7ba1a 2048 spin_unlock_bh(&vf->vlan_list_lock);
154d0c81
MC		 2049 return;
2050}
2051
91b7282b
RB		 2052int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter,
2053 u16 vid, u8 enable)
2054{
2055 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
74b7ba1a 2056 struct net_device *netdev = adapter->netdev;
154d0c81 2057 struct qlcnic_vf_info *vf;
91b7282b
RB		 2058 struct qlcnic_cmd_args cmd;
2059 int ret;
2060
c5316920 2061 memset(&cmd, 0, sizeof(cmd));
91b7282b
RB		 2062 if (vid == 0)
2063 return 0;
2064
154d0c81
MC		 2065 vf = &adapter->ahw->sriov->vf_info[0];
2066 ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable);
91b7282b
RB		 2067 if (ret)
2068 return ret;
2069
2070 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd,
2071 QLCNIC_BC_CMD_CFG_GUEST_VLAN);
2072 if (ret)
2073 return ret;
2074
2075 cmd.req.arg[1] = (enable & 1) | vid << 16;
2076
2077 qlcnic_sriov_cleanup_async_list(&sriov->bc);
2078 ret = qlcnic_issue_cmd(adapter, &cmd);
2079 if (ret) {
2080 dev_err(&adapter->pdev->dev,
2081 "Failed to configure guest VLAN, err=%d\n", ret);
2082 } else {
74b7ba1a 2083 netif_addr_lock_bh(netdev);
91b7282b 2084 qlcnic_free_mac_list(adapter);
74b7ba1a 2085 netif_addr_unlock_bh(netdev);
91b7282b
RB		 2086
2087 if (enable)
154d0c81 2088 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD);
91b7282b 2089 else
154d0c81 2090 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE);
91b7282b 2091
74b7ba1a
RB		 2092 netif_addr_lock_bh(netdev);
2093 qlcnic_set_multi(netdev);
2094 netif_addr_unlock_bh(netdev);
91b7282b
RB		 2095 }
2096
2097 qlcnic_free_mbx_args(&cmd);
2098 return ret;
2099}
2100
2101static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter)
2102{
2103 struct list_head *head = &adapter->mac_list;
154d0c81 2104 struct qlcnic_mac_vlan_list *cur;
91b7282b
RB		 2105
2106 while (!list_empty(head)) {
154d0c81
MC		 2107 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
2108 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id,
2109 QLCNIC_MAC_DEL);
91b7282b
RB		 2110 list_del(&cur->list);
2111 kfree(cur);
2112 }
2113}
486a5bc7 2114
154d0c81 2115
21041400 2116static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev)
486a5bc7
RB		 2117{
2118 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2119 struct net_device *netdev = adapter->netdev;
2120 int retval;
2121
2122 netif_device_detach(netdev);
2123 qlcnic_cancel_idc_work(adapter);
2124
2125 if (netif_running(netdev))
2126 qlcnic_down(adapter, netdev);
2127
2128 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
2129 qlcnic_sriov_cfg_bc_intr(adapter, 0);
2130 qlcnic_83xx_disable_mbx_intr(adapter);
2131 cancel_delayed_work_sync(&adapter->idc_aen_work);
2132
2133 retval = pci_save_state(pdev);
2134 if (retval)
2135 return retval;
2136
2137 return 0;
2138}
2139
21041400 2140static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter)
486a5bc7
RB		 2141{
2142 struct qlc_83xx_idc *idc = &adapter->ahw->idc;
2143 struct net_device *netdev = adapter->netdev;
2144 int err;
2145
2146 set_bit(QLC_83XX_MODULE_LOADED, &idc->status);
e5c4e6c6 2147 qlcnic_83xx_enable_mbx_interrupt(adapter);
486a5bc7
RB		 2148 err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
2149 if (err)
2150 return err;
2151
2152 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
2153 if (!err) {
2154 if (netif_running(netdev)) {
2155 err = qlcnic_up(adapter, netdev);
2156 if (!err)
2157 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
2158 }
2159 }
2160
2161 netif_device_attach(netdev);
2162 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state,
2163 idc->delay);
2164 return err;
2165}
154d0c81
MC		 2166
2167void qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter)
2168{
2169 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2170 struct qlcnic_vf_info *vf;
2171 int i;
2172
2173 for (i = 0; i < sriov->num_vfs; i++) {
2174 vf = &sriov->vf_info[i];
2175 vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans,
2176 sizeof(*vf->sriov_vlans), GFP_KERNEL);
2177 }
2178}
2179
2180void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter)
2181{
2182 struct qlcnic_sriov *sriov = adapter->ahw->sriov;
2183 struct qlcnic_vf_info *vf;
2184 int i;
2185
2186 for (i = 0; i < sriov->num_vfs; i++) {
2187 vf = &sriov->vf_info[i];
2188 kfree(vf->sriov_vlans);
2189 vf->sriov_vlans = NULL;
2190 }
2191}
2192
2193void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov,
2194 struct qlcnic_vf_info *vf, u16 vlan_id)
2195{
2196 int i;
2197
2198 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2199 if (!vf->sriov_vlans[i]) {
2200 vf->sriov_vlans[i] = vlan_id;
2201 vf->num_vlan++;
2202 return;
2203 }
2204 }
2205}
2206
2207void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov,
2208 struct qlcnic_vf_info *vf, u16 vlan_id)
2209{
2210 int i;
2211
2212 for (i = 0; i < sriov->num_allowed_vlans; i++) {
2213 if (vf->sriov_vlans[i] == vlan_id) {
2214 vf->sriov_vlans[i] = 0;
2215 vf->num_vlan--;
2216 return;
2217 }
2218 }
2219}
2220
2221bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf)
2222{
2223 bool err = false;
2224
74b7ba1a 2225 spin_lock_bh(&vf->vlan_list_lock);
154d0c81
MC		 2226
2227 if (vf->num_vlan)
2228 err = true;
2229
74b7ba1a 2230 spin_unlock_bh(&vf->vlan_list_lock);
154d0c81
MC		 2231 return err;
2232}