Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /************************************************************************ |
776bd20f | 2 | * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC |
926bd900 | 3 | * Copyright(c) 2002-2010 Exar Corp. |
d44570e4 | 4 | * |
1da177e4 LT |
5 | * This software may be used and distributed according to the terms of |
6 | * the GNU General Public License (GPL), incorporated herein by reference. | |
7 | * Drivers based on or derived from this code fall under the GPL and must | |
8 | * retain the authorship, copyright and license notice. This file is not | |
9 | * a complete program and may only be used when the entire operating | |
10 | * system is licensed under the GPL. | |
11 | * See the file COPYING in this distribution for more information. | |
12 | * | |
13 | * Credits: | |
20346722 K |
14 | * Jeff Garzik : For pointing out the improper error condition |
15 | * check in the s2io_xmit routine and also some | |
16 | * issues in the Tx watch dog function. Also for | |
17 | * patiently answering all those innumerable | |
1da177e4 LT |
18 | * questions regaring the 2.6 porting issues. |
19 | * Stephen Hemminger : Providing proper 2.6 porting mechanism for some | |
20 | * macros available only in 2.6 Kernel. | |
20346722 | 21 | * Francois Romieu : For pointing out all code part that were |
1da177e4 | 22 | * deprecated and also styling related comments. |
20346722 | 23 | * Grant Grundler : For helping me get rid of some Architecture |
1da177e4 LT |
24 | * dependent code. |
25 | * Christopher Hellwig : Some more 2.6 specific issues in the driver. | |
20346722 | 26 | * |
1da177e4 | 27 | * The module loadable parameters that are supported by the driver and a brief |
a2a20aef | 28 | * explanation of all the variables. |
9dc737a7 | 29 | * |
20346722 K |
30 | * rx_ring_num : This can be used to program the number of receive rings used |
31 | * in the driver. | |
9dc737a7 AR |
32 | * rx_ring_sz: This defines the number of receive blocks each ring can have. |
33 | * This is also an array of size 8. | |
da6971d8 | 34 | * rx_ring_mode: This defines the operation mode of all 8 rings. The valid |
6d517a27 | 35 | * values are 1, 2. |
1da177e4 | 36 | * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. |
20346722 | 37 | * tx_fifo_len: This too is an array of 8. Each element defines the number of |
1da177e4 | 38 | * Tx descriptors that can be associated with each corresponding FIFO. |
9dc737a7 | 39 | * intr_type: This defines the type of interrupt. The values can be 0(INTA), |
8abc4d5b | 40 | * 2(MSI_X). Default value is '2(MSI_X)' |
9dc737a7 AR |
41 | * lro_max_pkts: This parameter defines maximum number of packets can be |
42 | * aggregated as a single large packet | |
926930b2 SS |
43 | * napi: This parameter used to enable/disable NAPI (polling Rx) |
44 | * Possible values '1' for enable and '0' for disable. Default is '1' | |
45 | * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO) | |
46 | * Possible values '1' for enable and '0' for disable. Default is '0' | |
47 | * vlan_tag_strip: This can be used to enable or disable vlan stripping. | |
48 | * Possible values '1' for enable , '0' for disable. | |
49 | * Default is '2' - which means disable in promisc mode | |
50 | * and enable in non-promiscuous mode. | |
3a3d5756 SH |
51 | * multiq: This parameter used to enable/disable MULTIQUEUE support. |
52 | * Possible values '1' for enable and '0' for disable. Default is '0' | |
1da177e4 LT |
53 | ************************************************************************/ |
54 | ||
6cef2b8e JP |
55 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
56 | ||
1da177e4 LT |
57 | #include <linux/module.h> |
58 | #include <linux/types.h> | |
59 | #include <linux/errno.h> | |
60 | #include <linux/ioport.h> | |
61 | #include <linux/pci.h> | |
1e7f0bd8 | 62 | #include <linux/dma-mapping.h> |
1da177e4 LT |
63 | #include <linux/kernel.h> |
64 | #include <linux/netdevice.h> | |
65 | #include <linux/etherdevice.h> | |
40239396 | 66 | #include <linux/mdio.h> |
1da177e4 LT |
67 | #include <linux/skbuff.h> |
68 | #include <linux/init.h> | |
69 | #include <linux/delay.h> | |
70 | #include <linux/stddef.h> | |
71 | #include <linux/ioctl.h> | |
72 | #include <linux/timex.h> | |
1da177e4 | 73 | #include <linux/ethtool.h> |
1da177e4 | 74 | #include <linux/workqueue.h> |
be3a6b02 | 75 | #include <linux/if_vlan.h> |
7d3d0439 RA |
76 | #include <linux/ip.h> |
77 | #include <linux/tcp.h> | |
d44570e4 JP |
78 | #include <linux/uaccess.h> |
79 | #include <linux/io.h> | |
5a0e3ad6 | 80 | #include <linux/slab.h> |
70c71606 | 81 | #include <linux/prefetch.h> |
7d3d0439 | 82 | #include <net/tcp.h> |
1da177e4 | 83 | |
fe931395 | 84 | #include <asm/div64.h> |
330ce0de | 85 | #include <asm/irq.h> |
1da177e4 LT |
86 | |
87 | /* local include */ | |
88 | #include "s2io.h" | |
89 | #include "s2io-regs.h" | |
90 | ||
11410b62 | 91 | #define DRV_VERSION "2.0.26.28" |
6c1792f4 | 92 | |
1da177e4 | 93 | /* S2io Driver name & version. */ |
c0dbf37e JM |
94 | static const char s2io_driver_name[] = "Neterion"; |
95 | static const char s2io_driver_version[] = DRV_VERSION; | |
1da177e4 | 96 | |
c0dbf37e JM |
97 | static const int rxd_size[2] = {32, 48}; |
98 | static const int rxd_count[2] = {127, 85}; | |
da6971d8 | 99 | |
1ee6dd77 | 100 | static inline int RXD_IS_UP2DT(struct RxD_t *rxdp) |
5e25b9dd K |
101 | { |
102 | int ret; | |
103 | ||
104 | ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) && | |
d44570e4 | 105 | (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK)); |
5e25b9dd K |
106 | |
107 | return ret; | |
108 | } | |
109 | ||
20346722 | 110 | /* |
1da177e4 LT |
111 | * Cards with following subsystem_id have a link state indication |
112 | * problem, 600B, 600C, 600D, 640B, 640C and 640D. | |
113 | * macro below identifies these cards given the subsystem_id. | |
114 | */ | |
d44570e4 JP |
115 | #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \ |
116 | (dev_type == XFRAME_I_DEVICE) ? \ | |
117 | ((((subid >= 0x600B) && (subid <= 0x600D)) || \ | |
118 | ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0 | |
1da177e4 LT |
119 | |
120 | #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ | |
121 | ADAPTER_STATUS_RMAC_LOCAL_FAULT))) | |
1da177e4 | 122 | |
d44570e4 | 123 | static inline int is_s2io_card_up(const struct s2io_nic *sp) |
92b84437 SS |
124 | { |
125 | return test_bit(__S2IO_STATE_CARD_UP, &sp->state); | |
126 | } | |
127 | ||
1da177e4 | 128 | /* Ethtool related variables and Macros. */ |
6fce365d | 129 | static const char s2io_gstrings[][ETH_GSTRING_LEN] = { |
1da177e4 LT |
130 | "Register test\t(offline)", |
131 | "Eeprom test\t(offline)", | |
132 | "Link test\t(online)", | |
133 | "RLDRAM test\t(offline)", | |
134 | "BIST Test\t(offline)" | |
135 | }; | |
136 | ||
6fce365d | 137 | static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = { |
1da177e4 LT |
138 | {"tmac_frms"}, |
139 | {"tmac_data_octets"}, | |
140 | {"tmac_drop_frms"}, | |
141 | {"tmac_mcst_frms"}, | |
142 | {"tmac_bcst_frms"}, | |
143 | {"tmac_pause_ctrl_frms"}, | |
bd1034f0 AR |
144 | {"tmac_ttl_octets"}, |
145 | {"tmac_ucst_frms"}, | |
146 | {"tmac_nucst_frms"}, | |
1da177e4 | 147 | {"tmac_any_err_frms"}, |
bd1034f0 | 148 | {"tmac_ttl_less_fb_octets"}, |
1da177e4 LT |
149 | {"tmac_vld_ip_octets"}, |
150 | {"tmac_vld_ip"}, | |
151 | {"tmac_drop_ip"}, | |
152 | {"tmac_icmp"}, | |
153 | {"tmac_rst_tcp"}, | |
154 | {"tmac_tcp"}, | |
155 | {"tmac_udp"}, | |
156 | {"rmac_vld_frms"}, | |
157 | {"rmac_data_octets"}, | |
158 | {"rmac_fcs_err_frms"}, | |
159 | {"rmac_drop_frms"}, | |
160 | {"rmac_vld_mcst_frms"}, | |
161 | {"rmac_vld_bcst_frms"}, | |
162 | {"rmac_in_rng_len_err_frms"}, | |
bd1034f0 | 163 | {"rmac_out_rng_len_err_frms"}, |
1da177e4 LT |
164 | {"rmac_long_frms"}, |
165 | {"rmac_pause_ctrl_frms"}, | |
bd1034f0 AR |
166 | {"rmac_unsup_ctrl_frms"}, |
167 | {"rmac_ttl_octets"}, | |
168 | {"rmac_accepted_ucst_frms"}, | |
169 | {"rmac_accepted_nucst_frms"}, | |
1da177e4 | 170 | {"rmac_discarded_frms"}, |
bd1034f0 AR |
171 | {"rmac_drop_events"}, |
172 | {"rmac_ttl_less_fb_octets"}, | |
173 | {"rmac_ttl_frms"}, | |
1da177e4 LT |
174 | {"rmac_usized_frms"}, |
175 | {"rmac_osized_frms"}, | |
176 | {"rmac_frag_frms"}, | |
177 | {"rmac_jabber_frms"}, | |
bd1034f0 AR |
178 | {"rmac_ttl_64_frms"}, |
179 | {"rmac_ttl_65_127_frms"}, | |
180 | {"rmac_ttl_128_255_frms"}, | |
181 | {"rmac_ttl_256_511_frms"}, | |
182 | {"rmac_ttl_512_1023_frms"}, | |
183 | {"rmac_ttl_1024_1518_frms"}, | |
1da177e4 LT |
184 | {"rmac_ip"}, |
185 | {"rmac_ip_octets"}, | |
186 | {"rmac_hdr_err_ip"}, | |
187 | {"rmac_drop_ip"}, | |
188 | {"rmac_icmp"}, | |
189 | {"rmac_tcp"}, | |
190 | {"rmac_udp"}, | |
191 | {"rmac_err_drp_udp"}, | |
bd1034f0 AR |
192 | {"rmac_xgmii_err_sym"}, |
193 | {"rmac_frms_q0"}, | |
194 | {"rmac_frms_q1"}, | |
195 | {"rmac_frms_q2"}, | |
196 | {"rmac_frms_q3"}, | |
197 | {"rmac_frms_q4"}, | |
198 | {"rmac_frms_q5"}, | |
199 | {"rmac_frms_q6"}, | |
200 | {"rmac_frms_q7"}, | |
201 | {"rmac_full_q0"}, | |
202 | {"rmac_full_q1"}, | |
203 | {"rmac_full_q2"}, | |
204 | {"rmac_full_q3"}, | |
205 | {"rmac_full_q4"}, | |
206 | {"rmac_full_q5"}, | |
207 | {"rmac_full_q6"}, | |
208 | {"rmac_full_q7"}, | |
1da177e4 | 209 | {"rmac_pause_cnt"}, |
bd1034f0 AR |
210 | {"rmac_xgmii_data_err_cnt"}, |
211 | {"rmac_xgmii_ctrl_err_cnt"}, | |
1da177e4 LT |
212 | {"rmac_accepted_ip"}, |
213 | {"rmac_err_tcp"}, | |
bd1034f0 AR |
214 | {"rd_req_cnt"}, |
215 | {"new_rd_req_cnt"}, | |
216 | {"new_rd_req_rtry_cnt"}, | |
217 | {"rd_rtry_cnt"}, | |
218 | {"wr_rtry_rd_ack_cnt"}, | |
219 | {"wr_req_cnt"}, | |
220 | {"new_wr_req_cnt"}, | |
221 | {"new_wr_req_rtry_cnt"}, | |
222 | {"wr_rtry_cnt"}, | |
223 | {"wr_disc_cnt"}, | |
224 | {"rd_rtry_wr_ack_cnt"}, | |
225 | {"txp_wr_cnt"}, | |
226 | {"txd_rd_cnt"}, | |
227 | {"txd_wr_cnt"}, | |
228 | {"rxd_rd_cnt"}, | |
229 | {"rxd_wr_cnt"}, | |
230 | {"txf_rd_cnt"}, | |
fa1f0cb3 SS |
231 | {"rxf_wr_cnt"} |
232 | }; | |
233 | ||
6fce365d | 234 | static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = { |
bd1034f0 AR |
235 | {"rmac_ttl_1519_4095_frms"}, |
236 | {"rmac_ttl_4096_8191_frms"}, | |
237 | {"rmac_ttl_8192_max_frms"}, | |
238 | {"rmac_ttl_gt_max_frms"}, | |
239 | {"rmac_osized_alt_frms"}, | |
240 | {"rmac_jabber_alt_frms"}, | |
241 | {"rmac_gt_max_alt_frms"}, | |
242 | {"rmac_vlan_frms"}, | |
243 | {"rmac_len_discard"}, | |
244 | {"rmac_fcs_discard"}, | |
245 | {"rmac_pf_discard"}, | |
246 | {"rmac_da_discard"}, | |
247 | {"rmac_red_discard"}, | |
248 | {"rmac_rts_discard"}, | |
249 | {"rmac_ingm_full_discard"}, | |
fa1f0cb3 SS |
250 | {"link_fault_cnt"} |
251 | }; | |
252 | ||
6fce365d | 253 | static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = { |
7ba013ac K |
254 | {"\n DRIVER STATISTICS"}, |
255 | {"single_bit_ecc_errs"}, | |
256 | {"double_bit_ecc_errs"}, | |
bd1034f0 AR |
257 | {"parity_err_cnt"}, |
258 | {"serious_err_cnt"}, | |
259 | {"soft_reset_cnt"}, | |
260 | {"fifo_full_cnt"}, | |
8116f3cf SS |
261 | {"ring_0_full_cnt"}, |
262 | {"ring_1_full_cnt"}, | |
263 | {"ring_2_full_cnt"}, | |
264 | {"ring_3_full_cnt"}, | |
265 | {"ring_4_full_cnt"}, | |
266 | {"ring_5_full_cnt"}, | |
267 | {"ring_6_full_cnt"}, | |
268 | {"ring_7_full_cnt"}, | |
43b7c451 SH |
269 | {"alarm_transceiver_temp_high"}, |
270 | {"alarm_transceiver_temp_low"}, | |
271 | {"alarm_laser_bias_current_high"}, | |
272 | {"alarm_laser_bias_current_low"}, | |
273 | {"alarm_laser_output_power_high"}, | |
274 | {"alarm_laser_output_power_low"}, | |
275 | {"warn_transceiver_temp_high"}, | |
276 | {"warn_transceiver_temp_low"}, | |
277 | {"warn_laser_bias_current_high"}, | |
278 | {"warn_laser_bias_current_low"}, | |
279 | {"warn_laser_output_power_high"}, | |
280 | {"warn_laser_output_power_low"}, | |
281 | {"lro_aggregated_pkts"}, | |
282 | {"lro_flush_both_count"}, | |
283 | {"lro_out_of_sequence_pkts"}, | |
284 | {"lro_flush_due_to_max_pkts"}, | |
285 | {"lro_avg_aggr_pkts"}, | |
286 | {"mem_alloc_fail_cnt"}, | |
287 | {"pci_map_fail_cnt"}, | |
288 | {"watchdog_timer_cnt"}, | |
289 | {"mem_allocated"}, | |
290 | {"mem_freed"}, | |
291 | {"link_up_cnt"}, | |
292 | {"link_down_cnt"}, | |
293 | {"link_up_time"}, | |
294 | {"link_down_time"}, | |
295 | {"tx_tcode_buf_abort_cnt"}, | |
296 | {"tx_tcode_desc_abort_cnt"}, | |
297 | {"tx_tcode_parity_err_cnt"}, | |
298 | {"tx_tcode_link_loss_cnt"}, | |
299 | {"tx_tcode_list_proc_err_cnt"}, | |
300 | {"rx_tcode_parity_err_cnt"}, | |
301 | {"rx_tcode_abort_cnt"}, | |
302 | {"rx_tcode_parity_abort_cnt"}, | |
303 | {"rx_tcode_rda_fail_cnt"}, | |
304 | {"rx_tcode_unkn_prot_cnt"}, | |
305 | {"rx_tcode_fcs_err_cnt"}, | |
306 | {"rx_tcode_buf_size_err_cnt"}, | |
307 | {"rx_tcode_rxd_corrupt_cnt"}, | |
308 | {"rx_tcode_unkn_err_cnt"}, | |
8116f3cf SS |
309 | {"tda_err_cnt"}, |
310 | {"pfc_err_cnt"}, | |
311 | {"pcc_err_cnt"}, | |
312 | {"tti_err_cnt"}, | |
313 | {"tpa_err_cnt"}, | |
314 | {"sm_err_cnt"}, | |
315 | {"lso_err_cnt"}, | |
316 | {"mac_tmac_err_cnt"}, | |
317 | {"mac_rmac_err_cnt"}, | |
318 | {"xgxs_txgxs_err_cnt"}, | |
319 | {"xgxs_rxgxs_err_cnt"}, | |
320 | {"rc_err_cnt"}, | |
321 | {"prc_pcix_err_cnt"}, | |
322 | {"rpa_err_cnt"}, | |
323 | {"rda_err_cnt"}, | |
324 | {"rti_err_cnt"}, | |
325 | {"mc_err_cnt"} | |
1da177e4 LT |
326 | }; |
327 | ||
4c3616cd AMR |
328 | #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys) |
329 | #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys) | |
330 | #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys) | |
fa1f0cb3 | 331 | |
d44570e4 JP |
332 | #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN) |
333 | #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN) | |
fa1f0cb3 | 334 | |
d44570e4 JP |
335 | #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN) |
336 | #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN) | |
1da177e4 | 337 | |
4c3616cd | 338 | #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings) |
d44570e4 | 339 | #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN) |
1da177e4 | 340 | |
d44570e4 JP |
341 | #define S2IO_TIMER_CONF(timer, handle, arg, exp) \ |
342 | init_timer(&timer); \ | |
343 | timer.function = handle; \ | |
344 | timer.data = (unsigned long)arg; \ | |
345 | mod_timer(&timer, (jiffies + exp)) \ | |
25fff88e | 346 | |
2fd37688 SS |
347 | /* copy mac addr to def_mac_addr array */ |
348 | static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr) | |
349 | { | |
350 | sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr); | |
351 | sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8); | |
352 | sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16); | |
353 | sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24); | |
354 | sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32); | |
355 | sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40); | |
356 | } | |
04025095 | 357 | |
20346722 | 358 | /* |
1da177e4 LT |
359 | * Constants to be programmed into the Xena's registers, to configure |
360 | * the XAUI. | |
361 | */ | |
362 | ||
1da177e4 | 363 | #define END_SIGN 0x0 |
f71e1309 | 364 | static const u64 herc_act_dtx_cfg[] = { |
541ae68f | 365 | /* Set address */ |
e960fc5c | 366 | 0x8000051536750000ULL, 0x80000515367500E0ULL, |
541ae68f | 367 | /* Write data */ |
e960fc5c | 368 | 0x8000051536750004ULL, 0x80000515367500E4ULL, |
541ae68f K |
369 | /* Set address */ |
370 | 0x80010515003F0000ULL, 0x80010515003F00E0ULL, | |
371 | /* Write data */ | |
372 | 0x80010515003F0004ULL, 0x80010515003F00E4ULL, | |
373 | /* Set address */ | |
e960fc5c | 374 | 0x801205150D440000ULL, 0x801205150D4400E0ULL, |
375 | /* Write data */ | |
376 | 0x801205150D440004ULL, 0x801205150D4400E4ULL, | |
377 | /* Set address */ | |
541ae68f K |
378 | 0x80020515F2100000ULL, 0x80020515F21000E0ULL, |
379 | /* Write data */ | |
380 | 0x80020515F2100004ULL, 0x80020515F21000E4ULL, | |
381 | /* Done */ | |
382 | END_SIGN | |
383 | }; | |
384 | ||
f71e1309 | 385 | static const u64 xena_dtx_cfg[] = { |
c92ca04b | 386 | /* Set address */ |
1da177e4 | 387 | 0x8000051500000000ULL, 0x80000515000000E0ULL, |
c92ca04b AR |
388 | /* Write data */ |
389 | 0x80000515D9350004ULL, 0x80000515D93500E4ULL, | |
390 | /* Set address */ | |
391 | 0x8001051500000000ULL, 0x80010515000000E0ULL, | |
392 | /* Write data */ | |
393 | 0x80010515001E0004ULL, 0x80010515001E00E4ULL, | |
394 | /* Set address */ | |
1da177e4 | 395 | 0x8002051500000000ULL, 0x80020515000000E0ULL, |
c92ca04b AR |
396 | /* Write data */ |
397 | 0x80020515F2100004ULL, 0x80020515F21000E4ULL, | |
1da177e4 LT |
398 | END_SIGN |
399 | }; | |
400 | ||
20346722 | 401 | /* |
1da177e4 LT |
402 | * Constants for Fixing the MacAddress problem seen mostly on |
403 | * Alpha machines. | |
404 | */ | |
f71e1309 | 405 | static const u64 fix_mac[] = { |
1da177e4 LT |
406 | 0x0060000000000000ULL, 0x0060600000000000ULL, |
407 | 0x0040600000000000ULL, 0x0000600000000000ULL, | |
408 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
409 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
410 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
411 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
412 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
413 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
414 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
415 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
416 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
417 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
418 | 0x0020600000000000ULL, 0x0000600000000000ULL, | |
419 | 0x0040600000000000ULL, 0x0060600000000000ULL, | |
420 | END_SIGN | |
421 | }; | |
422 | ||
b41477f3 AR |
423 | MODULE_LICENSE("GPL"); |
424 | MODULE_VERSION(DRV_VERSION); | |
425 | ||
426 | ||
1da177e4 | 427 | /* Module Loadable parameters. */ |
6cfc482b | 428 | S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM); |
b41477f3 | 429 | S2IO_PARM_INT(rx_ring_num, 1); |
3a3d5756 | 430 | S2IO_PARM_INT(multiq, 0); |
b41477f3 AR |
431 | S2IO_PARM_INT(rx_ring_mode, 1); |
432 | S2IO_PARM_INT(use_continuous_tx_intrs, 1); | |
433 | S2IO_PARM_INT(rmac_pause_time, 0x100); | |
434 | S2IO_PARM_INT(mc_pause_threshold_q0q3, 187); | |
435 | S2IO_PARM_INT(mc_pause_threshold_q4q7, 187); | |
436 | S2IO_PARM_INT(shared_splits, 0); | |
437 | S2IO_PARM_INT(tmac_util_period, 5); | |
438 | S2IO_PARM_INT(rmac_util_period, 5); | |
b41477f3 | 439 | S2IO_PARM_INT(l3l4hdr_size, 128); |
6cfc482b SH |
440 | /* 0 is no steering, 1 is Priority steering, 2 is Default steering */ |
441 | S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING); | |
303bcb4b | 442 | /* Frequency of Rx desc syncs expressed as power of 2 */ |
b41477f3 | 443 | S2IO_PARM_INT(rxsync_frequency, 3); |
eccb8628 | 444 | /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */ |
8abc4d5b | 445 | S2IO_PARM_INT(intr_type, 2); |
7d3d0439 | 446 | /* Large receive offload feature */ |
43b7c451 | 447 | |
7d3d0439 RA |
448 | /* Max pkts to be aggregated by LRO at one time. If not specified, |
449 | * aggregation happens until we hit max IP pkt size(64K) | |
450 | */ | |
b41477f3 | 451 | S2IO_PARM_INT(lro_max_pkts, 0xFFFF); |
b41477f3 | 452 | S2IO_PARM_INT(indicate_max_pkts, 0); |
db874e65 SS |
453 | |
454 | S2IO_PARM_INT(napi, 1); | |
455 | S2IO_PARM_INT(ufo, 0); | |
926930b2 | 456 | S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC); |
b41477f3 AR |
457 | |
458 | static unsigned int tx_fifo_len[MAX_TX_FIFOS] = | |
d44570e4 | 459 | {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN}; |
b41477f3 | 460 | static unsigned int rx_ring_sz[MAX_RX_RINGS] = |
d44570e4 | 461 | {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT}; |
b41477f3 | 462 | static unsigned int rts_frm_len[MAX_RX_RINGS] = |
d44570e4 | 463 | {[0 ...(MAX_RX_RINGS - 1)] = 0 }; |
b41477f3 AR |
464 | |
465 | module_param_array(tx_fifo_len, uint, NULL, 0); | |
466 | module_param_array(rx_ring_sz, uint, NULL, 0); | |
467 | module_param_array(rts_frm_len, uint, NULL, 0); | |
1da177e4 | 468 | |
20346722 | 469 | /* |
1da177e4 | 470 | * S2IO device table. |
20346722 | 471 | * This table lists all the devices that this driver supports. |
1da177e4 | 472 | */ |
a3aa1884 | 473 | static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = { |
1da177e4 LT |
474 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, |
475 | PCI_ANY_ID, PCI_ANY_ID}, | |
476 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, | |
477 | PCI_ANY_ID, PCI_ANY_ID}, | |
478 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, | |
d44570e4 JP |
479 | PCI_ANY_ID, PCI_ANY_ID}, |
480 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, | |
481 | PCI_ANY_ID, PCI_ANY_ID}, | |
1da177e4 LT |
482 | {0,} |
483 | }; | |
484 | ||
485 | MODULE_DEVICE_TABLE(pci, s2io_tbl); | |
486 | ||
d796fdb7 LV |
487 | static struct pci_error_handlers s2io_err_handler = { |
488 | .error_detected = s2io_io_error_detected, | |
489 | .slot_reset = s2io_io_slot_reset, | |
490 | .resume = s2io_io_resume, | |
491 | }; | |
492 | ||
1da177e4 | 493 | static struct pci_driver s2io_driver = { |
d44570e4 JP |
494 | .name = "S2IO", |
495 | .id_table = s2io_tbl, | |
496 | .probe = s2io_init_nic, | |
497 | .remove = __devexit_p(s2io_rem_nic), | |
498 | .err_handler = &s2io_err_handler, | |
1da177e4 LT |
499 | }; |
500 | ||
501 | /* A simplifier macro used both by init and free shared_mem Fns(). */ | |
502 | #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each) | |
503 | ||
3a3d5756 SH |
504 | /* netqueue manipulation helper functions */ |
505 | static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp) | |
506 | { | |
fd2ea0a7 DM |
507 | if (!sp->config.multiq) { |
508 | int i; | |
509 | ||
3a3d5756 SH |
510 | for (i = 0; i < sp->config.tx_fifo_num; i++) |
511 | sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP; | |
3a3d5756 | 512 | } |
fd2ea0a7 | 513 | netif_tx_stop_all_queues(sp->dev); |
3a3d5756 SH |
514 | } |
515 | ||
516 | static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no) | |
517 | { | |
fd2ea0a7 | 518 | if (!sp->config.multiq) |
3a3d5756 SH |
519 | sp->mac_control.fifos[fifo_no].queue_state = |
520 | FIFO_QUEUE_STOP; | |
fd2ea0a7 DM |
521 | |
522 | netif_tx_stop_all_queues(sp->dev); | |
3a3d5756 SH |
523 | } |
524 | ||
525 | static inline void s2io_start_all_tx_queue(struct s2io_nic *sp) | |
526 | { | |
fd2ea0a7 DM |
527 | if (!sp->config.multiq) { |
528 | int i; | |
529 | ||
3a3d5756 SH |
530 | for (i = 0; i < sp->config.tx_fifo_num; i++) |
531 | sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; | |
3a3d5756 | 532 | } |
fd2ea0a7 | 533 | netif_tx_start_all_queues(sp->dev); |
3a3d5756 SH |
534 | } |
535 | ||
536 | static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no) | |
537 | { | |
fd2ea0a7 | 538 | if (!sp->config.multiq) |
3a3d5756 SH |
539 | sp->mac_control.fifos[fifo_no].queue_state = |
540 | FIFO_QUEUE_START; | |
fd2ea0a7 DM |
541 | |
542 | netif_tx_start_all_queues(sp->dev); | |
3a3d5756 SH |
543 | } |
544 | ||
545 | static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp) | |
546 | { | |
fd2ea0a7 DM |
547 | if (!sp->config.multiq) { |
548 | int i; | |
549 | ||
3a3d5756 SH |
550 | for (i = 0; i < sp->config.tx_fifo_num; i++) |
551 | sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; | |
3a3d5756 | 552 | } |
fd2ea0a7 | 553 | netif_tx_wake_all_queues(sp->dev); |
3a3d5756 SH |
554 | } |
555 | ||
556 | static inline void s2io_wake_tx_queue( | |
557 | struct fifo_info *fifo, int cnt, u8 multiq) | |
558 | { | |
559 | ||
3a3d5756 SH |
560 | if (multiq) { |
561 | if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no)) | |
562 | netif_wake_subqueue(fifo->dev, fifo->fifo_no); | |
b19fa1fa | 563 | } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) { |
3a3d5756 SH |
564 | if (netif_queue_stopped(fifo->dev)) { |
565 | fifo->queue_state = FIFO_QUEUE_START; | |
566 | netif_wake_queue(fifo->dev); | |
567 | } | |
568 | } | |
569 | } | |
570 | ||
1da177e4 LT |
571 | /** |
572 | * init_shared_mem - Allocation and Initialization of Memory | |
573 | * @nic: Device private variable. | |
20346722 K |
574 | * Description: The function allocates all the memory areas shared |
575 | * between the NIC and the driver. This includes Tx descriptors, | |
1da177e4 LT |
576 | * Rx descriptors and the statistics block. |
577 | */ | |
578 | ||
579 | static int init_shared_mem(struct s2io_nic *nic) | |
580 | { | |
581 | u32 size; | |
582 | void *tmp_v_addr, *tmp_v_addr_next; | |
583 | dma_addr_t tmp_p_addr, tmp_p_addr_next; | |
1ee6dd77 | 584 | struct RxD_block *pre_rxd_blk = NULL; |
372cc597 | 585 | int i, j, blk_cnt; |
1da177e4 LT |
586 | int lst_size, lst_per_page; |
587 | struct net_device *dev = nic->dev; | |
8ae418cf | 588 | unsigned long tmp; |
1ee6dd77 | 589 | struct buffAdd *ba; |
ffb5df6c JP |
590 | struct config_param *config = &nic->config; |
591 | struct mac_info *mac_control = &nic->mac_control; | |
491976b2 | 592 | unsigned long long mem_allocated = 0; |
1da177e4 | 593 | |
13d866a9 | 594 | /* Allocation and initialization of TXDLs in FIFOs */ |
1da177e4 LT |
595 | size = 0; |
596 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
597 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
598 | ||
599 | size += tx_cfg->fifo_len; | |
1da177e4 LT |
600 | } |
601 | if (size > MAX_AVAILABLE_TXDS) { | |
9e39f7c5 JP |
602 | DBG_PRINT(ERR_DBG, |
603 | "Too many TxDs requested: %d, max supported: %d\n", | |
604 | size, MAX_AVAILABLE_TXDS); | |
b41477f3 | 605 | return -EINVAL; |
1da177e4 LT |
606 | } |
607 | ||
2fda096d SR |
608 | size = 0; |
609 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
610 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
611 | ||
612 | size = tx_cfg->fifo_len; | |
2fda096d SR |
613 | /* |
614 | * Legal values are from 2 to 8192 | |
615 | */ | |
616 | if (size < 2) { | |
9e39f7c5 JP |
617 | DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - " |
618 | "Valid lengths are 2 through 8192\n", | |
619 | i, size); | |
2fda096d SR |
620 | return -EINVAL; |
621 | } | |
622 | } | |
623 | ||
1ee6dd77 | 624 | lst_size = (sizeof(struct TxD) * config->max_txds); |
1da177e4 LT |
625 | lst_per_page = PAGE_SIZE / lst_size; |
626 | ||
627 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
628 | struct fifo_info *fifo = &mac_control->fifos[i]; |
629 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
630 | int fifo_len = tx_cfg->fifo_len; | |
1ee6dd77 | 631 | int list_holder_size = fifo_len * sizeof(struct list_info_hold); |
13d866a9 JP |
632 | |
633 | fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL); | |
634 | if (!fifo->list_info) { | |
d44570e4 | 635 | DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n"); |
1da177e4 LT |
636 | return -ENOMEM; |
637 | } | |
491976b2 | 638 | mem_allocated += list_holder_size; |
1da177e4 LT |
639 | } |
640 | for (i = 0; i < config->tx_fifo_num; i++) { | |
641 | int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, | |
642 | lst_per_page); | |
13d866a9 JP |
643 | struct fifo_info *fifo = &mac_control->fifos[i]; |
644 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
645 | ||
646 | fifo->tx_curr_put_info.offset = 0; | |
647 | fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1; | |
648 | fifo->tx_curr_get_info.offset = 0; | |
649 | fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1; | |
650 | fifo->fifo_no = i; | |
651 | fifo->nic = nic; | |
652 | fifo->max_txds = MAX_SKB_FRAGS + 2; | |
653 | fifo->dev = dev; | |
20346722 | 654 | |
1da177e4 LT |
655 | for (j = 0; j < page_num; j++) { |
656 | int k = 0; | |
657 | dma_addr_t tmp_p; | |
658 | void *tmp_v; | |
659 | tmp_v = pci_alloc_consistent(nic->pdev, | |
660 | PAGE_SIZE, &tmp_p); | |
661 | if (!tmp_v) { | |
9e39f7c5 JP |
662 | DBG_PRINT(INFO_DBG, |
663 | "pci_alloc_consistent failed for TxDL\n"); | |
1da177e4 LT |
664 | return -ENOMEM; |
665 | } | |
776bd20f | 666 | /* If we got a zero DMA address(can happen on |
667 | * certain platforms like PPC), reallocate. | |
668 | * Store virtual address of page we don't want, | |
669 | * to be freed later. | |
670 | */ | |
671 | if (!tmp_p) { | |
672 | mac_control->zerodma_virt_addr = tmp_v; | |
6aa20a22 | 673 | DBG_PRINT(INIT_DBG, |
9e39f7c5 JP |
674 | "%s: Zero DMA address for TxDL. " |
675 | "Virtual address %p\n", | |
676 | dev->name, tmp_v); | |
776bd20f | 677 | tmp_v = pci_alloc_consistent(nic->pdev, |
d44570e4 | 678 | PAGE_SIZE, &tmp_p); |
776bd20f | 679 | if (!tmp_v) { |
0c61ed5f | 680 | DBG_PRINT(INFO_DBG, |
9e39f7c5 | 681 | "pci_alloc_consistent failed for TxDL\n"); |
776bd20f | 682 | return -ENOMEM; |
683 | } | |
491976b2 | 684 | mem_allocated += PAGE_SIZE; |
776bd20f | 685 | } |
1da177e4 LT |
686 | while (k < lst_per_page) { |
687 | int l = (j * lst_per_page) + k; | |
13d866a9 | 688 | if (l == tx_cfg->fifo_len) |
20346722 | 689 | break; |
13d866a9 | 690 | fifo->list_info[l].list_virt_addr = |
d44570e4 | 691 | tmp_v + (k * lst_size); |
13d866a9 | 692 | fifo->list_info[l].list_phy_addr = |
d44570e4 | 693 | tmp_p + (k * lst_size); |
1da177e4 LT |
694 | k++; |
695 | } | |
696 | } | |
697 | } | |
1da177e4 | 698 | |
2fda096d | 699 | for (i = 0; i < config->tx_fifo_num; i++) { |
13d866a9 JP |
700 | struct fifo_info *fifo = &mac_control->fifos[i]; |
701 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
702 | ||
703 | size = tx_cfg->fifo_len; | |
704 | fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL); | |
705 | if (!fifo->ufo_in_band_v) | |
2fda096d SR |
706 | return -ENOMEM; |
707 | mem_allocated += (size * sizeof(u64)); | |
708 | } | |
fed5eccd | 709 | |
1da177e4 LT |
710 | /* Allocation and initialization of RXDs in Rings */ |
711 | size = 0; | |
712 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
713 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
714 | struct ring_info *ring = &mac_control->rings[i]; | |
715 | ||
716 | if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) { | |
9e39f7c5 JP |
717 | DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a " |
718 | "multiple of RxDs per Block\n", | |
719 | dev->name, i); | |
1da177e4 LT |
720 | return FAILURE; |
721 | } | |
13d866a9 JP |
722 | size += rx_cfg->num_rxd; |
723 | ring->block_count = rx_cfg->num_rxd / | |
d44570e4 | 724 | (rxd_count[nic->rxd_mode] + 1); |
13d866a9 | 725 | ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count; |
1da177e4 | 726 | } |
da6971d8 | 727 | if (nic->rxd_mode == RXD_MODE_1) |
1ee6dd77 | 728 | size = (size * (sizeof(struct RxD1))); |
da6971d8 | 729 | else |
1ee6dd77 | 730 | size = (size * (sizeof(struct RxD3))); |
1da177e4 LT |
731 | |
732 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
733 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
734 | struct ring_info *ring = &mac_control->rings[i]; | |
735 | ||
736 | ring->rx_curr_get_info.block_index = 0; | |
737 | ring->rx_curr_get_info.offset = 0; | |
738 | ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1; | |
739 | ring->rx_curr_put_info.block_index = 0; | |
740 | ring->rx_curr_put_info.offset = 0; | |
741 | ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1; | |
742 | ring->nic = nic; | |
743 | ring->ring_no = i; | |
13d866a9 JP |
744 | |
745 | blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1); | |
1da177e4 LT |
746 | /* Allocating all the Rx blocks */ |
747 | for (j = 0; j < blk_cnt; j++) { | |
1ee6dd77 | 748 | struct rx_block_info *rx_blocks; |
da6971d8 AR |
749 | int l; |
750 | ||
13d866a9 | 751 | rx_blocks = &ring->rx_blocks[j]; |
d44570e4 | 752 | size = SIZE_OF_BLOCK; /* size is always page size */ |
1da177e4 LT |
753 | tmp_v_addr = pci_alloc_consistent(nic->pdev, size, |
754 | &tmp_p_addr); | |
755 | if (tmp_v_addr == NULL) { | |
756 | /* | |
20346722 K |
757 | * In case of failure, free_shared_mem() |
758 | * is called, which should free any | |
759 | * memory that was alloced till the | |
1da177e4 LT |
760 | * failure happened. |
761 | */ | |
da6971d8 | 762 | rx_blocks->block_virt_addr = tmp_v_addr; |
1da177e4 LT |
763 | return -ENOMEM; |
764 | } | |
491976b2 | 765 | mem_allocated += size; |
1da177e4 | 766 | memset(tmp_v_addr, 0, size); |
4f870320 JP |
767 | |
768 | size = sizeof(struct rxd_info) * | |
769 | rxd_count[nic->rxd_mode]; | |
da6971d8 AR |
770 | rx_blocks->block_virt_addr = tmp_v_addr; |
771 | rx_blocks->block_dma_addr = tmp_p_addr; | |
4f870320 | 772 | rx_blocks->rxds = kmalloc(size, GFP_KERNEL); |
372cc597 SS |
773 | if (!rx_blocks->rxds) |
774 | return -ENOMEM; | |
4f870320 | 775 | mem_allocated += size; |
d44570e4 | 776 | for (l = 0; l < rxd_count[nic->rxd_mode]; l++) { |
da6971d8 AR |
777 | rx_blocks->rxds[l].virt_addr = |
778 | rx_blocks->block_virt_addr + | |
779 | (rxd_size[nic->rxd_mode] * l); | |
780 | rx_blocks->rxds[l].dma_addr = | |
781 | rx_blocks->block_dma_addr + | |
782 | (rxd_size[nic->rxd_mode] * l); | |
783 | } | |
1da177e4 LT |
784 | } |
785 | /* Interlinking all Rx Blocks */ | |
786 | for (j = 0; j < blk_cnt; j++) { | |
13d866a9 JP |
787 | int next = (j + 1) % blk_cnt; |
788 | tmp_v_addr = ring->rx_blocks[j].block_virt_addr; | |
789 | tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr; | |
790 | tmp_p_addr = ring->rx_blocks[j].block_dma_addr; | |
791 | tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr; | |
1da177e4 | 792 | |
43d620c8 | 793 | pre_rxd_blk = tmp_v_addr; |
1da177e4 | 794 | pre_rxd_blk->reserved_2_pNext_RxD_block = |
d44570e4 | 795 | (unsigned long)tmp_v_addr_next; |
1da177e4 | 796 | pre_rxd_blk->pNext_RxD_Blk_physical = |
d44570e4 | 797 | (u64)tmp_p_addr_next; |
1da177e4 LT |
798 | } |
799 | } | |
6d517a27 | 800 | if (nic->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
801 | /* |
802 | * Allocation of Storages for buffer addresses in 2BUFF mode | |
803 | * and the buffers as well. | |
804 | */ | |
805 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
806 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
807 | struct ring_info *ring = &mac_control->rings[i]; | |
808 | ||
809 | blk_cnt = rx_cfg->num_rxd / | |
d44570e4 | 810 | (rxd_count[nic->rxd_mode] + 1); |
4f870320 JP |
811 | size = sizeof(struct buffAdd *) * blk_cnt; |
812 | ring->ba = kmalloc(size, GFP_KERNEL); | |
13d866a9 | 813 | if (!ring->ba) |
1da177e4 | 814 | return -ENOMEM; |
4f870320 | 815 | mem_allocated += size; |
da6971d8 AR |
816 | for (j = 0; j < blk_cnt; j++) { |
817 | int k = 0; | |
4f870320 JP |
818 | |
819 | size = sizeof(struct buffAdd) * | |
820 | (rxd_count[nic->rxd_mode] + 1); | |
821 | ring->ba[j] = kmalloc(size, GFP_KERNEL); | |
13d866a9 | 822 | if (!ring->ba[j]) |
1da177e4 | 823 | return -ENOMEM; |
4f870320 | 824 | mem_allocated += size; |
da6971d8 | 825 | while (k != rxd_count[nic->rxd_mode]) { |
13d866a9 | 826 | ba = &ring->ba[j][k]; |
4f870320 JP |
827 | size = BUF0_LEN + ALIGN_SIZE; |
828 | ba->ba_0_org = kmalloc(size, GFP_KERNEL); | |
da6971d8 AR |
829 | if (!ba->ba_0_org) |
830 | return -ENOMEM; | |
4f870320 | 831 | mem_allocated += size; |
da6971d8 AR |
832 | tmp = (unsigned long)ba->ba_0_org; |
833 | tmp += ALIGN_SIZE; | |
d44570e4 JP |
834 | tmp &= ~((unsigned long)ALIGN_SIZE); |
835 | ba->ba_0 = (void *)tmp; | |
da6971d8 | 836 | |
4f870320 JP |
837 | size = BUF1_LEN + ALIGN_SIZE; |
838 | ba->ba_1_org = kmalloc(size, GFP_KERNEL); | |
da6971d8 AR |
839 | if (!ba->ba_1_org) |
840 | return -ENOMEM; | |
4f870320 | 841 | mem_allocated += size; |
d44570e4 | 842 | tmp = (unsigned long)ba->ba_1_org; |
da6971d8 | 843 | tmp += ALIGN_SIZE; |
d44570e4 JP |
844 | tmp &= ~((unsigned long)ALIGN_SIZE); |
845 | ba->ba_1 = (void *)tmp; | |
da6971d8 AR |
846 | k++; |
847 | } | |
1da177e4 LT |
848 | } |
849 | } | |
850 | } | |
1da177e4 LT |
851 | |
852 | /* Allocation and initialization of Statistics block */ | |
1ee6dd77 | 853 | size = sizeof(struct stat_block); |
d44570e4 JP |
854 | mac_control->stats_mem = |
855 | pci_alloc_consistent(nic->pdev, size, | |
856 | &mac_control->stats_mem_phy); | |
1da177e4 LT |
857 | |
858 | if (!mac_control->stats_mem) { | |
20346722 K |
859 | /* |
860 | * In case of failure, free_shared_mem() is called, which | |
861 | * should free any memory that was alloced till the | |
1da177e4 LT |
862 | * failure happened. |
863 | */ | |
864 | return -ENOMEM; | |
865 | } | |
491976b2 | 866 | mem_allocated += size; |
1da177e4 LT |
867 | mac_control->stats_mem_sz = size; |
868 | ||
869 | tmp_v_addr = mac_control->stats_mem; | |
43d620c8 | 870 | mac_control->stats_info = tmp_v_addr; |
1da177e4 | 871 | memset(tmp_v_addr, 0, size); |
3a22813a BL |
872 | DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", |
873 | dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr); | |
491976b2 | 874 | mac_control->stats_info->sw_stat.mem_allocated += mem_allocated; |
1da177e4 LT |
875 | return SUCCESS; |
876 | } | |
877 | ||
20346722 K |
878 | /** |
879 | * free_shared_mem - Free the allocated Memory | |
1da177e4 LT |
880 | * @nic: Device private variable. |
881 | * Description: This function is to free all memory locations allocated by | |
882 | * the init_shared_mem() function and return it to the kernel. | |
883 | */ | |
884 | ||
885 | static void free_shared_mem(struct s2io_nic *nic) | |
886 | { | |
887 | int i, j, blk_cnt, size; | |
888 | void *tmp_v_addr; | |
889 | dma_addr_t tmp_p_addr; | |
1da177e4 | 890 | int lst_size, lst_per_page; |
8910b49f | 891 | struct net_device *dev; |
491976b2 | 892 | int page_num = 0; |
ffb5df6c JP |
893 | struct config_param *config; |
894 | struct mac_info *mac_control; | |
895 | struct stat_block *stats; | |
896 | struct swStat *swstats; | |
1da177e4 LT |
897 | |
898 | if (!nic) | |
899 | return; | |
900 | ||
8910b49f MG |
901 | dev = nic->dev; |
902 | ||
1da177e4 | 903 | config = &nic->config; |
ffb5df6c JP |
904 | mac_control = &nic->mac_control; |
905 | stats = mac_control->stats_info; | |
906 | swstats = &stats->sw_stat; | |
1da177e4 | 907 | |
d44570e4 | 908 | lst_size = sizeof(struct TxD) * config->max_txds; |
1da177e4 LT |
909 | lst_per_page = PAGE_SIZE / lst_size; |
910 | ||
911 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
912 | struct fifo_info *fifo = &mac_control->fifos[i]; |
913 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
914 | ||
915 | page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page); | |
1da177e4 LT |
916 | for (j = 0; j < page_num; j++) { |
917 | int mem_blks = (j * lst_per_page); | |
13d866a9 JP |
918 | struct list_info_hold *fli; |
919 | ||
920 | if (!fifo->list_info) | |
6aa20a22 | 921 | return; |
13d866a9 JP |
922 | |
923 | fli = &fifo->list_info[mem_blks]; | |
924 | if (!fli->list_virt_addr) | |
1da177e4 LT |
925 | break; |
926 | pci_free_consistent(nic->pdev, PAGE_SIZE, | |
13d866a9 JP |
927 | fli->list_virt_addr, |
928 | fli->list_phy_addr); | |
ffb5df6c | 929 | swstats->mem_freed += PAGE_SIZE; |
1da177e4 | 930 | } |
776bd20f | 931 | /* If we got a zero DMA address during allocation, |
932 | * free the page now | |
933 | */ | |
934 | if (mac_control->zerodma_virt_addr) { | |
935 | pci_free_consistent(nic->pdev, PAGE_SIZE, | |
936 | mac_control->zerodma_virt_addr, | |
937 | (dma_addr_t)0); | |
6aa20a22 | 938 | DBG_PRINT(INIT_DBG, |
9e39f7c5 JP |
939 | "%s: Freeing TxDL with zero DMA address. " |
940 | "Virtual address %p\n", | |
941 | dev->name, mac_control->zerodma_virt_addr); | |
ffb5df6c | 942 | swstats->mem_freed += PAGE_SIZE; |
776bd20f | 943 | } |
13d866a9 | 944 | kfree(fifo->list_info); |
82c2d023 | 945 | swstats->mem_freed += tx_cfg->fifo_len * |
d44570e4 | 946 | sizeof(struct list_info_hold); |
1da177e4 LT |
947 | } |
948 | ||
1da177e4 | 949 | size = SIZE_OF_BLOCK; |
1da177e4 | 950 | for (i = 0; i < config->rx_ring_num; i++) { |
13d866a9 JP |
951 | struct ring_info *ring = &mac_control->rings[i]; |
952 | ||
953 | blk_cnt = ring->block_count; | |
1da177e4 | 954 | for (j = 0; j < blk_cnt; j++) { |
13d866a9 JP |
955 | tmp_v_addr = ring->rx_blocks[j].block_virt_addr; |
956 | tmp_p_addr = ring->rx_blocks[j].block_dma_addr; | |
1da177e4 LT |
957 | if (tmp_v_addr == NULL) |
958 | break; | |
959 | pci_free_consistent(nic->pdev, size, | |
960 | tmp_v_addr, tmp_p_addr); | |
ffb5df6c | 961 | swstats->mem_freed += size; |
13d866a9 | 962 | kfree(ring->rx_blocks[j].rxds); |
ffb5df6c JP |
963 | swstats->mem_freed += sizeof(struct rxd_info) * |
964 | rxd_count[nic->rxd_mode]; | |
1da177e4 LT |
965 | } |
966 | } | |
967 | ||
6d517a27 | 968 | if (nic->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
969 | /* Freeing buffer storage addresses in 2BUFF mode. */ |
970 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
971 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
972 | struct ring_info *ring = &mac_control->rings[i]; | |
973 | ||
974 | blk_cnt = rx_cfg->num_rxd / | |
975 | (rxd_count[nic->rxd_mode] + 1); | |
da6971d8 AR |
976 | for (j = 0; j < blk_cnt; j++) { |
977 | int k = 0; | |
13d866a9 | 978 | if (!ring->ba[j]) |
da6971d8 AR |
979 | continue; |
980 | while (k != rxd_count[nic->rxd_mode]) { | |
13d866a9 | 981 | struct buffAdd *ba = &ring->ba[j][k]; |
da6971d8 | 982 | kfree(ba->ba_0_org); |
ffb5df6c JP |
983 | swstats->mem_freed += |
984 | BUF0_LEN + ALIGN_SIZE; | |
da6971d8 | 985 | kfree(ba->ba_1_org); |
ffb5df6c JP |
986 | swstats->mem_freed += |
987 | BUF1_LEN + ALIGN_SIZE; | |
da6971d8 AR |
988 | k++; |
989 | } | |
13d866a9 | 990 | kfree(ring->ba[j]); |
ffb5df6c JP |
991 | swstats->mem_freed += sizeof(struct buffAdd) * |
992 | (rxd_count[nic->rxd_mode] + 1); | |
1da177e4 | 993 | } |
13d866a9 | 994 | kfree(ring->ba); |
ffb5df6c JP |
995 | swstats->mem_freed += sizeof(struct buffAdd *) * |
996 | blk_cnt; | |
1da177e4 | 997 | } |
1da177e4 | 998 | } |
1da177e4 | 999 | |
2fda096d | 1000 | for (i = 0; i < nic->config.tx_fifo_num; i++) { |
13d866a9 JP |
1001 | struct fifo_info *fifo = &mac_control->fifos[i]; |
1002 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
1003 | ||
1004 | if (fifo->ufo_in_band_v) { | |
ffb5df6c JP |
1005 | swstats->mem_freed += tx_cfg->fifo_len * |
1006 | sizeof(u64); | |
13d866a9 | 1007 | kfree(fifo->ufo_in_band_v); |
2fda096d SR |
1008 | } |
1009 | } | |
1010 | ||
1da177e4 | 1011 | if (mac_control->stats_mem) { |
ffb5df6c | 1012 | swstats->mem_freed += mac_control->stats_mem_sz; |
1da177e4 LT |
1013 | pci_free_consistent(nic->pdev, |
1014 | mac_control->stats_mem_sz, | |
1015 | mac_control->stats_mem, | |
1016 | mac_control->stats_mem_phy); | |
491976b2 | 1017 | } |
1da177e4 LT |
1018 | } |
1019 | ||
541ae68f K |
1020 | /** |
1021 | * s2io_verify_pci_mode - | |
1022 | */ | |
1023 | ||
1ee6dd77 | 1024 | static int s2io_verify_pci_mode(struct s2io_nic *nic) |
541ae68f | 1025 | { |
1ee6dd77 | 1026 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
541ae68f K |
1027 | register u64 val64 = 0; |
1028 | int mode; | |
1029 | ||
1030 | val64 = readq(&bar0->pci_mode); | |
1031 | mode = (u8)GET_PCI_MODE(val64); | |
1032 | ||
d44570e4 | 1033 | if (val64 & PCI_MODE_UNKNOWN_MODE) |
541ae68f K |
1034 | return -1; /* Unknown PCI mode */ |
1035 | return mode; | |
1036 | } | |
1037 | ||
c92ca04b AR |
1038 | #define NEC_VENID 0x1033 |
1039 | #define NEC_DEVID 0x0125 | |
1040 | static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev) | |
1041 | { | |
1042 | struct pci_dev *tdev = NULL; | |
26d36b64 AC |
1043 | while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) { |
1044 | if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) { | |
7ad62dbc | 1045 | if (tdev->bus == s2io_pdev->bus->parent) { |
26d36b64 | 1046 | pci_dev_put(tdev); |
c92ca04b | 1047 | return 1; |
7ad62dbc | 1048 | } |
c92ca04b AR |
1049 | } |
1050 | } | |
1051 | return 0; | |
1052 | } | |
541ae68f | 1053 | |
7b32a312 | 1054 | static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266}; |
541ae68f K |
1055 | /** |
1056 | * s2io_print_pci_mode - | |
1057 | */ | |
1ee6dd77 | 1058 | static int s2io_print_pci_mode(struct s2io_nic *nic) |
541ae68f | 1059 | { |
1ee6dd77 | 1060 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
541ae68f K |
1061 | register u64 val64 = 0; |
1062 | int mode; | |
1063 | struct config_param *config = &nic->config; | |
9e39f7c5 | 1064 | const char *pcimode; |
541ae68f K |
1065 | |
1066 | val64 = readq(&bar0->pci_mode); | |
1067 | mode = (u8)GET_PCI_MODE(val64); | |
1068 | ||
d44570e4 | 1069 | if (val64 & PCI_MODE_UNKNOWN_MODE) |
541ae68f K |
1070 | return -1; /* Unknown PCI mode */ |
1071 | ||
c92ca04b AR |
1072 | config->bus_speed = bus_speed[mode]; |
1073 | ||
1074 | if (s2io_on_nec_bridge(nic->pdev)) { | |
1075 | DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n", | |
d44570e4 | 1076 | nic->dev->name); |
c92ca04b AR |
1077 | return mode; |
1078 | } | |
1079 | ||
d44570e4 JP |
1080 | switch (mode) { |
1081 | case PCI_MODE_PCI_33: | |
9e39f7c5 | 1082 | pcimode = "33MHz PCI bus"; |
d44570e4 JP |
1083 | break; |
1084 | case PCI_MODE_PCI_66: | |
9e39f7c5 | 1085 | pcimode = "66MHz PCI bus"; |
d44570e4 JP |
1086 | break; |
1087 | case PCI_MODE_PCIX_M1_66: | |
9e39f7c5 | 1088 | pcimode = "66MHz PCIX(M1) bus"; |
d44570e4 JP |
1089 | break; |
1090 | case PCI_MODE_PCIX_M1_100: | |
9e39f7c5 | 1091 | pcimode = "100MHz PCIX(M1) bus"; |
d44570e4 JP |
1092 | break; |
1093 | case PCI_MODE_PCIX_M1_133: | |
9e39f7c5 | 1094 | pcimode = "133MHz PCIX(M1) bus"; |
d44570e4 JP |
1095 | break; |
1096 | case PCI_MODE_PCIX_M2_66: | |
9e39f7c5 | 1097 | pcimode = "133MHz PCIX(M2) bus"; |
d44570e4 JP |
1098 | break; |
1099 | case PCI_MODE_PCIX_M2_100: | |
9e39f7c5 | 1100 | pcimode = "200MHz PCIX(M2) bus"; |
d44570e4 JP |
1101 | break; |
1102 | case PCI_MODE_PCIX_M2_133: | |
9e39f7c5 | 1103 | pcimode = "266MHz PCIX(M2) bus"; |
d44570e4 JP |
1104 | break; |
1105 | default: | |
9e39f7c5 JP |
1106 | pcimode = "unsupported bus!"; |
1107 | mode = -1; | |
541ae68f K |
1108 | } |
1109 | ||
9e39f7c5 JP |
1110 | DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n", |
1111 | nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode); | |
1112 | ||
541ae68f K |
1113 | return mode; |
1114 | } | |
1115 | ||
b7c5678f RV |
1116 | /** |
1117 | * init_tti - Initialization transmit traffic interrupt scheme | |
1118 | * @nic: device private variable | |
1119 | * @link: link status (UP/DOWN) used to enable/disable continuous | |
1120 | * transmit interrupts | |
1121 | * Description: The function configures transmit traffic interrupts | |
1122 | * Return Value: SUCCESS on success and | |
1123 | * '-1' on failure | |
1124 | */ | |
1125 | ||
0d66afe7 | 1126 | static int init_tti(struct s2io_nic *nic, int link) |
b7c5678f RV |
1127 | { |
1128 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
1129 | register u64 val64 = 0; | |
1130 | int i; | |
ffb5df6c | 1131 | struct config_param *config = &nic->config; |
b7c5678f RV |
1132 | |
1133 | for (i = 0; i < config->tx_fifo_num; i++) { | |
1134 | /* | |
1135 | * TTI Initialization. Default Tx timer gets us about | |
1136 | * 250 interrupts per sec. Continuous interrupts are enabled | |
1137 | * by default. | |
1138 | */ | |
1139 | if (nic->device_type == XFRAME_II_DEVICE) { | |
1140 | int count = (nic->config.bus_speed * 125)/2; | |
1141 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); | |
1142 | } else | |
1143 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); | |
1144 | ||
1145 | val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | | |
d44570e4 JP |
1146 | TTI_DATA1_MEM_TX_URNG_B(0x10) | |
1147 | TTI_DATA1_MEM_TX_URNG_C(0x30) | | |
1148 | TTI_DATA1_MEM_TX_TIMER_AC_EN; | |
ac731ab6 SH |
1149 | if (i == 0) |
1150 | if (use_continuous_tx_intrs && (link == LINK_UP)) | |
1151 | val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; | |
b7c5678f RV |
1152 | writeq(val64, &bar0->tti_data1_mem); |
1153 | ||
ac731ab6 SH |
1154 | if (nic->config.intr_type == MSI_X) { |
1155 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | | |
1156 | TTI_DATA2_MEM_TX_UFC_B(0x100) | | |
1157 | TTI_DATA2_MEM_TX_UFC_C(0x200) | | |
1158 | TTI_DATA2_MEM_TX_UFC_D(0x300); | |
1159 | } else { | |
1160 | if ((nic->config.tx_steering_type == | |
d44570e4 JP |
1161 | TX_DEFAULT_STEERING) && |
1162 | (config->tx_fifo_num > 1) && | |
1163 | (i >= nic->udp_fifo_idx) && | |
1164 | (i < (nic->udp_fifo_idx + | |
1165 | nic->total_udp_fifos))) | |
ac731ab6 SH |
1166 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) | |
1167 | TTI_DATA2_MEM_TX_UFC_B(0x80) | | |
1168 | TTI_DATA2_MEM_TX_UFC_C(0x100) | | |
1169 | TTI_DATA2_MEM_TX_UFC_D(0x120); | |
1170 | else | |
1171 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | | |
1172 | TTI_DATA2_MEM_TX_UFC_B(0x20) | | |
1173 | TTI_DATA2_MEM_TX_UFC_C(0x40) | | |
1174 | TTI_DATA2_MEM_TX_UFC_D(0x80); | |
1175 | } | |
b7c5678f RV |
1176 | |
1177 | writeq(val64, &bar0->tti_data2_mem); | |
1178 | ||
d44570e4 JP |
1179 | val64 = TTI_CMD_MEM_WE | |
1180 | TTI_CMD_MEM_STROBE_NEW_CMD | | |
1181 | TTI_CMD_MEM_OFFSET(i); | |
b7c5678f RV |
1182 | writeq(val64, &bar0->tti_command_mem); |
1183 | ||
1184 | if (wait_for_cmd_complete(&bar0->tti_command_mem, | |
d44570e4 JP |
1185 | TTI_CMD_MEM_STROBE_NEW_CMD, |
1186 | S2IO_BIT_RESET) != SUCCESS) | |
b7c5678f RV |
1187 | return FAILURE; |
1188 | } | |
1189 | ||
1190 | return SUCCESS; | |
1191 | } | |
1192 | ||
20346722 K |
1193 | /** |
1194 | * init_nic - Initialization of hardware | |
b7c5678f | 1195 | * @nic: device private variable |
20346722 K |
1196 | * Description: The function sequentially configures every block |
1197 | * of the H/W from their reset values. | |
1198 | * Return Value: SUCCESS on success and | |
1da177e4 LT |
1199 | * '-1' on failure (endian settings incorrect). |
1200 | */ | |
1201 | ||
1202 | static int init_nic(struct s2io_nic *nic) | |
1203 | { | |
1ee6dd77 | 1204 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 LT |
1205 | struct net_device *dev = nic->dev; |
1206 | register u64 val64 = 0; | |
1207 | void __iomem *add; | |
1208 | u32 time; | |
1209 | int i, j; | |
c92ca04b | 1210 | int dtx_cnt = 0; |
1da177e4 | 1211 | unsigned long long mem_share; |
20346722 | 1212 | int mem_size; |
ffb5df6c JP |
1213 | struct config_param *config = &nic->config; |
1214 | struct mac_info *mac_control = &nic->mac_control; | |
1da177e4 | 1215 | |
5e25b9dd | 1216 | /* to set the swapper controle on the card */ |
d44570e4 JP |
1217 | if (s2io_set_swapper(nic)) { |
1218 | DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n"); | |
9f74ffde | 1219 | return -EIO; |
1da177e4 LT |
1220 | } |
1221 | ||
541ae68f K |
1222 | /* |
1223 | * Herc requires EOI to be removed from reset before XGXS, so.. | |
1224 | */ | |
1225 | if (nic->device_type & XFRAME_II_DEVICE) { | |
1226 | val64 = 0xA500000000ULL; | |
1227 | writeq(val64, &bar0->sw_reset); | |
1228 | msleep(500); | |
1229 | val64 = readq(&bar0->sw_reset); | |
1230 | } | |
1231 | ||
1da177e4 LT |
1232 | /* Remove XGXS from reset state */ |
1233 | val64 = 0; | |
1234 | writeq(val64, &bar0->sw_reset); | |
1da177e4 | 1235 | msleep(500); |
20346722 | 1236 | val64 = readq(&bar0->sw_reset); |
1da177e4 | 1237 | |
7962024e SH |
1238 | /* Ensure that it's safe to access registers by checking |
1239 | * RIC_RUNNING bit is reset. Check is valid only for XframeII. | |
1240 | */ | |
1241 | if (nic->device_type == XFRAME_II_DEVICE) { | |
1242 | for (i = 0; i < 50; i++) { | |
1243 | val64 = readq(&bar0->adapter_status); | |
1244 | if (!(val64 & ADAPTER_STATUS_RIC_RUNNING)) | |
1245 | break; | |
1246 | msleep(10); | |
1247 | } | |
1248 | if (i == 50) | |
1249 | return -ENODEV; | |
1250 | } | |
1251 | ||
1da177e4 LT |
1252 | /* Enable Receiving broadcasts */ |
1253 | add = &bar0->mac_cfg; | |
1254 | val64 = readq(&bar0->mac_cfg); | |
1255 | val64 |= MAC_RMAC_BCAST_ENABLE; | |
1256 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
d44570e4 | 1257 | writel((u32)val64, add); |
1da177e4 LT |
1258 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); |
1259 | writel((u32) (val64 >> 32), (add + 4)); | |
1260 | ||
1261 | /* Read registers in all blocks */ | |
1262 | val64 = readq(&bar0->mac_int_mask); | |
1263 | val64 = readq(&bar0->mc_int_mask); | |
1264 | val64 = readq(&bar0->xgxs_int_mask); | |
1265 | ||
1266 | /* Set MTU */ | |
1267 | val64 = dev->mtu; | |
1268 | writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); | |
1269 | ||
541ae68f K |
1270 | if (nic->device_type & XFRAME_II_DEVICE) { |
1271 | while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { | |
303bcb4b | 1272 | SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt], |
1da177e4 | 1273 | &bar0->dtx_control, UF); |
541ae68f K |
1274 | if (dtx_cnt & 0x1) |
1275 | msleep(1); /* Necessary!! */ | |
1da177e4 LT |
1276 | dtx_cnt++; |
1277 | } | |
541ae68f | 1278 | } else { |
c92ca04b AR |
1279 | while (xena_dtx_cfg[dtx_cnt] != END_SIGN) { |
1280 | SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], | |
1281 | &bar0->dtx_control, UF); | |
1282 | val64 = readq(&bar0->dtx_control); | |
1283 | dtx_cnt++; | |
1da177e4 LT |
1284 | } |
1285 | } | |
1286 | ||
1287 | /* Tx DMA Initialization */ | |
1288 | val64 = 0; | |
1289 | writeq(val64, &bar0->tx_fifo_partition_0); | |
1290 | writeq(val64, &bar0->tx_fifo_partition_1); | |
1291 | writeq(val64, &bar0->tx_fifo_partition_2); | |
1292 | writeq(val64, &bar0->tx_fifo_partition_3); | |
1293 | ||
1da177e4 | 1294 | for (i = 0, j = 0; i < config->tx_fifo_num; i++) { |
13d866a9 JP |
1295 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
1296 | ||
1297 | val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) | | |
1298 | vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3); | |
1da177e4 LT |
1299 | |
1300 | if (i == (config->tx_fifo_num - 1)) { | |
1301 | if (i % 2 == 0) | |
1302 | i++; | |
1303 | } | |
1304 | ||
1305 | switch (i) { | |
1306 | case 1: | |
1307 | writeq(val64, &bar0->tx_fifo_partition_0); | |
1308 | val64 = 0; | |
b7c5678f | 1309 | j = 0; |
1da177e4 LT |
1310 | break; |
1311 | case 3: | |
1312 | writeq(val64, &bar0->tx_fifo_partition_1); | |
1313 | val64 = 0; | |
b7c5678f | 1314 | j = 0; |
1da177e4 LT |
1315 | break; |
1316 | case 5: | |
1317 | writeq(val64, &bar0->tx_fifo_partition_2); | |
1318 | val64 = 0; | |
b7c5678f | 1319 | j = 0; |
1da177e4 LT |
1320 | break; |
1321 | case 7: | |
1322 | writeq(val64, &bar0->tx_fifo_partition_3); | |
b7c5678f RV |
1323 | val64 = 0; |
1324 | j = 0; | |
1325 | break; | |
1326 | default: | |
1327 | j++; | |
1da177e4 LT |
1328 | break; |
1329 | } | |
1330 | } | |
1331 | ||
5e25b9dd K |
1332 | /* |
1333 | * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug | |
1334 | * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. | |
1335 | */ | |
d44570e4 | 1336 | if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4)) |
5e25b9dd K |
1337 | writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); |
1338 | ||
1da177e4 LT |
1339 | val64 = readq(&bar0->tx_fifo_partition_0); |
1340 | DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", | |
d44570e4 | 1341 | &bar0->tx_fifo_partition_0, (unsigned long long)val64); |
1da177e4 | 1342 | |
20346722 K |
1343 | /* |
1344 | * Initialization of Tx_PA_CONFIG register to ignore packet | |
1da177e4 LT |
1345 | * integrity checking. |
1346 | */ | |
1347 | val64 = readq(&bar0->tx_pa_cfg); | |
d44570e4 JP |
1348 | val64 |= TX_PA_CFG_IGNORE_FRM_ERR | |
1349 | TX_PA_CFG_IGNORE_SNAP_OUI | | |
1350 | TX_PA_CFG_IGNORE_LLC_CTRL | | |
1351 | TX_PA_CFG_IGNORE_L2_ERR; | |
1da177e4 LT |
1352 | writeq(val64, &bar0->tx_pa_cfg); |
1353 | ||
1354 | /* Rx DMA intialization. */ | |
1355 | val64 = 0; | |
1356 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
1357 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
1358 | ||
1359 | val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3); | |
1da177e4 LT |
1360 | } |
1361 | writeq(val64, &bar0->rx_queue_priority); | |
1362 | ||
20346722 K |
1363 | /* |
1364 | * Allocating equal share of memory to all the | |
1da177e4 LT |
1365 | * configured Rings. |
1366 | */ | |
1367 | val64 = 0; | |
541ae68f K |
1368 | if (nic->device_type & XFRAME_II_DEVICE) |
1369 | mem_size = 32; | |
1370 | else | |
1371 | mem_size = 64; | |
1372 | ||
1da177e4 LT |
1373 | for (i = 0; i < config->rx_ring_num; i++) { |
1374 | switch (i) { | |
1375 | case 0: | |
20346722 K |
1376 | mem_share = (mem_size / config->rx_ring_num + |
1377 | mem_size % config->rx_ring_num); | |
1da177e4 LT |
1378 | val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); |
1379 | continue; | |
1380 | case 1: | |
20346722 | 1381 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1382 | val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); |
1383 | continue; | |
1384 | case 2: | |
20346722 | 1385 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1386 | val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); |
1387 | continue; | |
1388 | case 3: | |
20346722 | 1389 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1390 | val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); |
1391 | continue; | |
1392 | case 4: | |
20346722 | 1393 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1394 | val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); |
1395 | continue; | |
1396 | case 5: | |
20346722 | 1397 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1398 | val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); |
1399 | continue; | |
1400 | case 6: | |
20346722 | 1401 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1402 | val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); |
1403 | continue; | |
1404 | case 7: | |
20346722 | 1405 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1406 | val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); |
1407 | continue; | |
1408 | } | |
1409 | } | |
1410 | writeq(val64, &bar0->rx_queue_cfg); | |
1411 | ||
20346722 | 1412 | /* |
5e25b9dd | 1413 | * Filling Tx round robin registers |
b7c5678f | 1414 | * as per the number of FIFOs for equal scheduling priority |
1da177e4 | 1415 | */ |
5e25b9dd K |
1416 | switch (config->tx_fifo_num) { |
1417 | case 1: | |
b7c5678f | 1418 | val64 = 0x0; |
5e25b9dd K |
1419 | writeq(val64, &bar0->tx_w_round_robin_0); |
1420 | writeq(val64, &bar0->tx_w_round_robin_1); | |
1421 | writeq(val64, &bar0->tx_w_round_robin_2); | |
1422 | writeq(val64, &bar0->tx_w_round_robin_3); | |
1423 | writeq(val64, &bar0->tx_w_round_robin_4); | |
1424 | break; | |
1425 | case 2: | |
b7c5678f | 1426 | val64 = 0x0001000100010001ULL; |
5e25b9dd | 1427 | writeq(val64, &bar0->tx_w_round_robin_0); |
5e25b9dd | 1428 | writeq(val64, &bar0->tx_w_round_robin_1); |
5e25b9dd | 1429 | writeq(val64, &bar0->tx_w_round_robin_2); |
5e25b9dd | 1430 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1431 | val64 = 0x0001000100000000ULL; |
5e25b9dd K |
1432 | writeq(val64, &bar0->tx_w_round_robin_4); |
1433 | break; | |
1434 | case 3: | |
b7c5678f | 1435 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1436 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1437 | val64 = 0x0200010200010200ULL; |
5e25b9dd | 1438 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1439 | val64 = 0x0102000102000102ULL; |
5e25b9dd | 1440 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1441 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1442 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1443 | val64 = 0x0200010200000000ULL; |
5e25b9dd K |
1444 | writeq(val64, &bar0->tx_w_round_robin_4); |
1445 | break; | |
1446 | case 4: | |
b7c5678f | 1447 | val64 = 0x0001020300010203ULL; |
5e25b9dd | 1448 | writeq(val64, &bar0->tx_w_round_robin_0); |
5e25b9dd | 1449 | writeq(val64, &bar0->tx_w_round_robin_1); |
5e25b9dd | 1450 | writeq(val64, &bar0->tx_w_round_robin_2); |
5e25b9dd | 1451 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1452 | val64 = 0x0001020300000000ULL; |
5e25b9dd K |
1453 | writeq(val64, &bar0->tx_w_round_robin_4); |
1454 | break; | |
1455 | case 5: | |
b7c5678f | 1456 | val64 = 0x0001020304000102ULL; |
5e25b9dd | 1457 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1458 | val64 = 0x0304000102030400ULL; |
5e25b9dd | 1459 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1460 | val64 = 0x0102030400010203ULL; |
5e25b9dd | 1461 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1462 | val64 = 0x0400010203040001ULL; |
5e25b9dd | 1463 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1464 | val64 = 0x0203040000000000ULL; |
5e25b9dd K |
1465 | writeq(val64, &bar0->tx_w_round_robin_4); |
1466 | break; | |
1467 | case 6: | |
b7c5678f | 1468 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1469 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1470 | val64 = 0x0203040500010203ULL; |
5e25b9dd | 1471 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1472 | val64 = 0x0405000102030405ULL; |
5e25b9dd | 1473 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1474 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1475 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1476 | val64 = 0x0203040500000000ULL; |
5e25b9dd K |
1477 | writeq(val64, &bar0->tx_w_round_robin_4); |
1478 | break; | |
1479 | case 7: | |
b7c5678f | 1480 | val64 = 0x0001020304050600ULL; |
5e25b9dd | 1481 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1482 | val64 = 0x0102030405060001ULL; |
5e25b9dd | 1483 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1484 | val64 = 0x0203040506000102ULL; |
5e25b9dd | 1485 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1486 | val64 = 0x0304050600010203ULL; |
5e25b9dd | 1487 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1488 | val64 = 0x0405060000000000ULL; |
5e25b9dd K |
1489 | writeq(val64, &bar0->tx_w_round_robin_4); |
1490 | break; | |
1491 | case 8: | |
b7c5678f | 1492 | val64 = 0x0001020304050607ULL; |
5e25b9dd | 1493 | writeq(val64, &bar0->tx_w_round_robin_0); |
5e25b9dd | 1494 | writeq(val64, &bar0->tx_w_round_robin_1); |
5e25b9dd | 1495 | writeq(val64, &bar0->tx_w_round_robin_2); |
5e25b9dd | 1496 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1497 | val64 = 0x0001020300000000ULL; |
5e25b9dd K |
1498 | writeq(val64, &bar0->tx_w_round_robin_4); |
1499 | break; | |
1500 | } | |
1501 | ||
b41477f3 | 1502 | /* Enable all configured Tx FIFO partitions */ |
5d3213cc AR |
1503 | val64 = readq(&bar0->tx_fifo_partition_0); |
1504 | val64 |= (TX_FIFO_PARTITION_EN); | |
1505 | writeq(val64, &bar0->tx_fifo_partition_0); | |
1506 | ||
5e25b9dd | 1507 | /* Filling the Rx round robin registers as per the |
0425b46a SH |
1508 | * number of Rings and steering based on QoS with |
1509 | * equal priority. | |
1510 | */ | |
5e25b9dd K |
1511 | switch (config->rx_ring_num) { |
1512 | case 1: | |
0425b46a SH |
1513 | val64 = 0x0; |
1514 | writeq(val64, &bar0->rx_w_round_robin_0); | |
1515 | writeq(val64, &bar0->rx_w_round_robin_1); | |
1516 | writeq(val64, &bar0->rx_w_round_robin_2); | |
1517 | writeq(val64, &bar0->rx_w_round_robin_3); | |
1518 | writeq(val64, &bar0->rx_w_round_robin_4); | |
1519 | ||
5e25b9dd K |
1520 | val64 = 0x8080808080808080ULL; |
1521 | writeq(val64, &bar0->rts_qos_steering); | |
1522 | break; | |
1523 | case 2: | |
0425b46a | 1524 | val64 = 0x0001000100010001ULL; |
5e25b9dd | 1525 | writeq(val64, &bar0->rx_w_round_robin_0); |
5e25b9dd | 1526 | writeq(val64, &bar0->rx_w_round_robin_1); |
5e25b9dd | 1527 | writeq(val64, &bar0->rx_w_round_robin_2); |
5e25b9dd | 1528 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1529 | val64 = 0x0001000100000000ULL; |
5e25b9dd K |
1530 | writeq(val64, &bar0->rx_w_round_robin_4); |
1531 | ||
1532 | val64 = 0x8080808040404040ULL; | |
1533 | writeq(val64, &bar0->rts_qos_steering); | |
1534 | break; | |
1535 | case 3: | |
0425b46a | 1536 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1537 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1538 | val64 = 0x0200010200010200ULL; |
5e25b9dd | 1539 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1540 | val64 = 0x0102000102000102ULL; |
5e25b9dd | 1541 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1542 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1543 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1544 | val64 = 0x0200010200000000ULL; |
5e25b9dd K |
1545 | writeq(val64, &bar0->rx_w_round_robin_4); |
1546 | ||
1547 | val64 = 0x8080804040402020ULL; | |
1548 | writeq(val64, &bar0->rts_qos_steering); | |
1549 | break; | |
1550 | case 4: | |
0425b46a | 1551 | val64 = 0x0001020300010203ULL; |
5e25b9dd | 1552 | writeq(val64, &bar0->rx_w_round_robin_0); |
5e25b9dd | 1553 | writeq(val64, &bar0->rx_w_round_robin_1); |
5e25b9dd | 1554 | writeq(val64, &bar0->rx_w_round_robin_2); |
5e25b9dd | 1555 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1556 | val64 = 0x0001020300000000ULL; |
5e25b9dd K |
1557 | writeq(val64, &bar0->rx_w_round_robin_4); |
1558 | ||
1559 | val64 = 0x8080404020201010ULL; | |
1560 | writeq(val64, &bar0->rts_qos_steering); | |
1561 | break; | |
1562 | case 5: | |
0425b46a | 1563 | val64 = 0x0001020304000102ULL; |
5e25b9dd | 1564 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1565 | val64 = 0x0304000102030400ULL; |
5e25b9dd | 1566 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1567 | val64 = 0x0102030400010203ULL; |
5e25b9dd | 1568 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1569 | val64 = 0x0400010203040001ULL; |
5e25b9dd | 1570 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1571 | val64 = 0x0203040000000000ULL; |
5e25b9dd K |
1572 | writeq(val64, &bar0->rx_w_round_robin_4); |
1573 | ||
1574 | val64 = 0x8080404020201008ULL; | |
1575 | writeq(val64, &bar0->rts_qos_steering); | |
1576 | break; | |
1577 | case 6: | |
0425b46a | 1578 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1579 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1580 | val64 = 0x0203040500010203ULL; |
5e25b9dd | 1581 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1582 | val64 = 0x0405000102030405ULL; |
5e25b9dd | 1583 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1584 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1585 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1586 | val64 = 0x0203040500000000ULL; |
5e25b9dd K |
1587 | writeq(val64, &bar0->rx_w_round_robin_4); |
1588 | ||
1589 | val64 = 0x8080404020100804ULL; | |
1590 | writeq(val64, &bar0->rts_qos_steering); | |
1591 | break; | |
1592 | case 7: | |
0425b46a | 1593 | val64 = 0x0001020304050600ULL; |
5e25b9dd | 1594 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1595 | val64 = 0x0102030405060001ULL; |
5e25b9dd | 1596 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1597 | val64 = 0x0203040506000102ULL; |
5e25b9dd | 1598 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1599 | val64 = 0x0304050600010203ULL; |
5e25b9dd | 1600 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1601 | val64 = 0x0405060000000000ULL; |
5e25b9dd K |
1602 | writeq(val64, &bar0->rx_w_round_robin_4); |
1603 | ||
1604 | val64 = 0x8080402010080402ULL; | |
1605 | writeq(val64, &bar0->rts_qos_steering); | |
1606 | break; | |
1607 | case 8: | |
0425b46a | 1608 | val64 = 0x0001020304050607ULL; |
5e25b9dd | 1609 | writeq(val64, &bar0->rx_w_round_robin_0); |
5e25b9dd | 1610 | writeq(val64, &bar0->rx_w_round_robin_1); |
5e25b9dd | 1611 | writeq(val64, &bar0->rx_w_round_robin_2); |
5e25b9dd | 1612 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1613 | val64 = 0x0001020300000000ULL; |
5e25b9dd K |
1614 | writeq(val64, &bar0->rx_w_round_robin_4); |
1615 | ||
1616 | val64 = 0x8040201008040201ULL; | |
1617 | writeq(val64, &bar0->rts_qos_steering); | |
1618 | break; | |
1619 | } | |
1da177e4 LT |
1620 | |
1621 | /* UDP Fix */ | |
1622 | val64 = 0; | |
20346722 | 1623 | for (i = 0; i < 8; i++) |
1da177e4 LT |
1624 | writeq(val64, &bar0->rts_frm_len_n[i]); |
1625 | ||
5e25b9dd K |
1626 | /* Set the default rts frame length for the rings configured */ |
1627 | val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); | |
1628 | for (i = 0 ; i < config->rx_ring_num ; i++) | |
1629 | writeq(val64, &bar0->rts_frm_len_n[i]); | |
1630 | ||
1631 | /* Set the frame length for the configured rings | |
1632 | * desired by the user | |
1633 | */ | |
1634 | for (i = 0; i < config->rx_ring_num; i++) { | |
1635 | /* If rts_frm_len[i] == 0 then it is assumed that user not | |
1636 | * specified frame length steering. | |
1637 | * If the user provides the frame length then program | |
1638 | * the rts_frm_len register for those values or else | |
1639 | * leave it as it is. | |
1640 | */ | |
1641 | if (rts_frm_len[i] != 0) { | |
1642 | writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]), | |
d44570e4 | 1643 | &bar0->rts_frm_len_n[i]); |
5e25b9dd K |
1644 | } |
1645 | } | |
8a4bdbaa | 1646 | |
9fc93a41 SS |
1647 | /* Disable differentiated services steering logic */ |
1648 | for (i = 0; i < 64; i++) { | |
1649 | if (rts_ds_steer(nic, i, 0) == FAILURE) { | |
9e39f7c5 JP |
1650 | DBG_PRINT(ERR_DBG, |
1651 | "%s: rts_ds_steer failed on codepoint %d\n", | |
1652 | dev->name, i); | |
9f74ffde | 1653 | return -ENODEV; |
9fc93a41 SS |
1654 | } |
1655 | } | |
1656 | ||
20346722 | 1657 | /* Program statistics memory */ |
1da177e4 | 1658 | writeq(mac_control->stats_mem_phy, &bar0->stat_addr); |
1da177e4 | 1659 | |
541ae68f K |
1660 | if (nic->device_type == XFRAME_II_DEVICE) { |
1661 | val64 = STAT_BC(0x320); | |
1662 | writeq(val64, &bar0->stat_byte_cnt); | |
1663 | } | |
1664 | ||
20346722 | 1665 | /* |
1da177e4 LT |
1666 | * Initializing the sampling rate for the device to calculate the |
1667 | * bandwidth utilization. | |
1668 | */ | |
1669 | val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | | |
d44570e4 | 1670 | MAC_RX_LINK_UTIL_VAL(rmac_util_period); |
1da177e4 LT |
1671 | writeq(val64, &bar0->mac_link_util); |
1672 | ||
20346722 K |
1673 | /* |
1674 | * Initializing the Transmit and Receive Traffic Interrupt | |
1da177e4 LT |
1675 | * Scheme. |
1676 | */ | |
1da177e4 | 1677 | |
b7c5678f RV |
1678 | /* Initialize TTI */ |
1679 | if (SUCCESS != init_tti(nic, nic->last_link_state)) | |
1680 | return -ENODEV; | |
1da177e4 | 1681 | |
8a4bdbaa SS |
1682 | /* RTI Initialization */ |
1683 | if (nic->device_type == XFRAME_II_DEVICE) { | |
541ae68f | 1684 | /* |
8a4bdbaa SS |
1685 | * Programmed to generate Apprx 500 Intrs per |
1686 | * second | |
1687 | */ | |
1688 | int count = (nic->config.bus_speed * 125)/4; | |
1689 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); | |
1690 | } else | |
1691 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); | |
1692 | val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | | |
d44570e4 JP |
1693 | RTI_DATA1_MEM_RX_URNG_B(0x10) | |
1694 | RTI_DATA1_MEM_RX_URNG_C(0x30) | | |
1695 | RTI_DATA1_MEM_RX_TIMER_AC_EN; | |
8a4bdbaa SS |
1696 | |
1697 | writeq(val64, &bar0->rti_data1_mem); | |
1698 | ||
1699 | val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | | |
1700 | RTI_DATA2_MEM_RX_UFC_B(0x2) ; | |
1701 | if (nic->config.intr_type == MSI_X) | |
d44570e4 JP |
1702 | val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | |
1703 | RTI_DATA2_MEM_RX_UFC_D(0x40)); | |
8a4bdbaa | 1704 | else |
d44570e4 JP |
1705 | val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | |
1706 | RTI_DATA2_MEM_RX_UFC_D(0x80)); | |
8a4bdbaa | 1707 | writeq(val64, &bar0->rti_data2_mem); |
1da177e4 | 1708 | |
8a4bdbaa | 1709 | for (i = 0; i < config->rx_ring_num; i++) { |
d44570e4 JP |
1710 | val64 = RTI_CMD_MEM_WE | |
1711 | RTI_CMD_MEM_STROBE_NEW_CMD | | |
1712 | RTI_CMD_MEM_OFFSET(i); | |
8a4bdbaa | 1713 | writeq(val64, &bar0->rti_command_mem); |
1da177e4 | 1714 | |
8a4bdbaa SS |
1715 | /* |
1716 | * Once the operation completes, the Strobe bit of the | |
1717 | * command register will be reset. We poll for this | |
1718 | * particular condition. We wait for a maximum of 500ms | |
1719 | * for the operation to complete, if it's not complete | |
1720 | * by then we return error. | |
1721 | */ | |
1722 | time = 0; | |
f957bcf0 | 1723 | while (true) { |
8a4bdbaa SS |
1724 | val64 = readq(&bar0->rti_command_mem); |
1725 | if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) | |
1726 | break; | |
b6e3f982 | 1727 | |
8a4bdbaa | 1728 | if (time > 10) { |
9e39f7c5 | 1729 | DBG_PRINT(ERR_DBG, "%s: RTI init failed\n", |
8a4bdbaa | 1730 | dev->name); |
9f74ffde | 1731 | return -ENODEV; |
b6e3f982 | 1732 | } |
8a4bdbaa SS |
1733 | time++; |
1734 | msleep(50); | |
1da177e4 | 1735 | } |
1da177e4 LT |
1736 | } |
1737 | ||
20346722 K |
1738 | /* |
1739 | * Initializing proper values as Pause threshold into all | |
1da177e4 LT |
1740 | * the 8 Queues on Rx side. |
1741 | */ | |
1742 | writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); | |
1743 | writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); | |
1744 | ||
1745 | /* Disable RMAC PAD STRIPPING */ | |
509a2671 | 1746 | add = &bar0->mac_cfg; |
1da177e4 LT |
1747 | val64 = readq(&bar0->mac_cfg); |
1748 | val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); | |
1749 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1750 | writel((u32) (val64), add); | |
1751 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1752 | writel((u32) (val64 >> 32), (add + 4)); | |
1753 | val64 = readq(&bar0->mac_cfg); | |
1754 | ||
7d3d0439 RA |
1755 | /* Enable FCS stripping by adapter */ |
1756 | add = &bar0->mac_cfg; | |
1757 | val64 = readq(&bar0->mac_cfg); | |
1758 | val64 |= MAC_CFG_RMAC_STRIP_FCS; | |
1759 | if (nic->device_type == XFRAME_II_DEVICE) | |
1760 | writeq(val64, &bar0->mac_cfg); | |
1761 | else { | |
1762 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1763 | writel((u32) (val64), add); | |
1764 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1765 | writel((u32) (val64 >> 32), (add + 4)); | |
1766 | } | |
1767 | ||
20346722 K |
1768 | /* |
1769 | * Set the time value to be inserted in the pause frame | |
1da177e4 LT |
1770 | * generated by xena. |
1771 | */ | |
1772 | val64 = readq(&bar0->rmac_pause_cfg); | |
1773 | val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); | |
1774 | val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); | |
1775 | writeq(val64, &bar0->rmac_pause_cfg); | |
1776 | ||
20346722 | 1777 | /* |
1da177e4 LT |
1778 | * Set the Threshold Limit for Generating the pause frame |
1779 | * If the amount of data in any Queue exceeds ratio of | |
1780 | * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 | |
1781 | * pause frame is generated | |
1782 | */ | |
1783 | val64 = 0; | |
1784 | for (i = 0; i < 4; i++) { | |
d44570e4 JP |
1785 | val64 |= (((u64)0xFF00 | |
1786 | nic->mac_control.mc_pause_threshold_q0q3) | |
1787 | << (i * 2 * 8)); | |
1da177e4 LT |
1788 | } |
1789 | writeq(val64, &bar0->mc_pause_thresh_q0q3); | |
1790 | ||
1791 | val64 = 0; | |
1792 | for (i = 0; i < 4; i++) { | |
d44570e4 JP |
1793 | val64 |= (((u64)0xFF00 | |
1794 | nic->mac_control.mc_pause_threshold_q4q7) | |
1795 | << (i * 2 * 8)); | |
1da177e4 LT |
1796 | } |
1797 | writeq(val64, &bar0->mc_pause_thresh_q4q7); | |
1798 | ||
20346722 K |
1799 | /* |
1800 | * TxDMA will stop Read request if the number of read split has | |
1da177e4 LT |
1801 | * exceeded the limit pointed by shared_splits |
1802 | */ | |
1803 | val64 = readq(&bar0->pic_control); | |
1804 | val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); | |
1805 | writeq(val64, &bar0->pic_control); | |
1806 | ||
863c11a9 AR |
1807 | if (nic->config.bus_speed == 266) { |
1808 | writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout); | |
1809 | writeq(0x0, &bar0->read_retry_delay); | |
1810 | writeq(0x0, &bar0->write_retry_delay); | |
1811 | } | |
1812 | ||
541ae68f K |
1813 | /* |
1814 | * Programming the Herc to split every write transaction | |
1815 | * that does not start on an ADB to reduce disconnects. | |
1816 | */ | |
1817 | if (nic->device_type == XFRAME_II_DEVICE) { | |
19a60522 SS |
1818 | val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | |
1819 | MISC_LINK_STABILITY_PRD(3); | |
863c11a9 AR |
1820 | writeq(val64, &bar0->misc_control); |
1821 | val64 = readq(&bar0->pic_control2); | |
b7b5a128 | 1822 | val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15)); |
863c11a9 | 1823 | writeq(val64, &bar0->pic_control2); |
541ae68f | 1824 | } |
c92ca04b AR |
1825 | if (strstr(nic->product_name, "CX4")) { |
1826 | val64 = TMAC_AVG_IPG(0x17); | |
1827 | writeq(val64, &bar0->tmac_avg_ipg); | |
a371a07d K |
1828 | } |
1829 | ||
1da177e4 LT |
1830 | return SUCCESS; |
1831 | } | |
a371a07d K |
1832 | #define LINK_UP_DOWN_INTERRUPT 1 |
1833 | #define MAC_RMAC_ERR_TIMER 2 | |
1834 | ||
1ee6dd77 | 1835 | static int s2io_link_fault_indication(struct s2io_nic *nic) |
a371a07d K |
1836 | { |
1837 | if (nic->device_type == XFRAME_II_DEVICE) | |
1838 | return LINK_UP_DOWN_INTERRUPT; | |
1839 | else | |
1840 | return MAC_RMAC_ERR_TIMER; | |
1841 | } | |
8116f3cf | 1842 | |
9caab458 SS |
1843 | /** |
1844 | * do_s2io_write_bits - update alarm bits in alarm register | |
1845 | * @value: alarm bits | |
1846 | * @flag: interrupt status | |
1847 | * @addr: address value | |
1848 | * Description: update alarm bits in alarm register | |
1849 | * Return Value: | |
1850 | * NONE. | |
1851 | */ | |
1852 | static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr) | |
1853 | { | |
1854 | u64 temp64; | |
1855 | ||
1856 | temp64 = readq(addr); | |
1857 | ||
d44570e4 JP |
1858 | if (flag == ENABLE_INTRS) |
1859 | temp64 &= ~((u64)value); | |
9caab458 | 1860 | else |
d44570e4 | 1861 | temp64 |= ((u64)value); |
9caab458 SS |
1862 | writeq(temp64, addr); |
1863 | } | |
1da177e4 | 1864 | |
43b7c451 | 1865 | static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag) |
9caab458 SS |
1866 | { |
1867 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
1868 | register u64 gen_int_mask = 0; | |
01e16faa | 1869 | u64 interruptible; |
9caab458 | 1870 | |
01e16faa | 1871 | writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); |
9caab458 | 1872 | if (mask & TX_DMA_INTR) { |
9caab458 SS |
1873 | gen_int_mask |= TXDMA_INT_M; |
1874 | ||
1875 | do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT | | |
d44570e4 JP |
1876 | TXDMA_PCC_INT | TXDMA_TTI_INT | |
1877 | TXDMA_LSO_INT | TXDMA_TPA_INT | | |
1878 | TXDMA_SM_INT, flag, &bar0->txdma_int_mask); | |
9caab458 SS |
1879 | |
1880 | do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM | | |
d44570e4 JP |
1881 | PFC_MISC_0_ERR | PFC_MISC_1_ERR | |
1882 | PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag, | |
1883 | &bar0->pfc_err_mask); | |
9caab458 SS |
1884 | |
1885 | do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM | | |
d44570e4 JP |
1886 | TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR | |
1887 | TDA_PCIX_ERR, flag, &bar0->tda_err_mask); | |
9caab458 SS |
1888 | |
1889 | do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR | | |
d44570e4 JP |
1890 | PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM | |
1891 | PCC_N_SERR | PCC_6_COF_OV_ERR | | |
1892 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR | | |
1893 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR | | |
1894 | PCC_TXB_ECC_SG_ERR, | |
1895 | flag, &bar0->pcc_err_mask); | |
9caab458 SS |
1896 | |
1897 | do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR | | |
d44570e4 | 1898 | TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask); |
9caab458 SS |
1899 | |
1900 | do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT | | |
d44570e4 JP |
1901 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM | |
1902 | LSO6_SEND_OFLOW | LSO7_SEND_OFLOW, | |
1903 | flag, &bar0->lso_err_mask); | |
9caab458 SS |
1904 | |
1905 | do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP, | |
d44570e4 | 1906 | flag, &bar0->tpa_err_mask); |
9caab458 SS |
1907 | |
1908 | do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask); | |
9caab458 SS |
1909 | } |
1910 | ||
1911 | if (mask & TX_MAC_INTR) { | |
1912 | gen_int_mask |= TXMAC_INT_M; | |
1913 | do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag, | |
d44570e4 | 1914 | &bar0->mac_int_mask); |
9caab458 | 1915 | do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR | |
d44570e4 JP |
1916 | TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR | |
1917 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR, | |
1918 | flag, &bar0->mac_tmac_err_mask); | |
9caab458 SS |
1919 | } |
1920 | ||
1921 | if (mask & TX_XGXS_INTR) { | |
1922 | gen_int_mask |= TXXGXS_INT_M; | |
1923 | do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag, | |
d44570e4 | 1924 | &bar0->xgxs_int_mask); |
9caab458 | 1925 | do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR | |
d44570e4 JP |
1926 | TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR, |
1927 | flag, &bar0->xgxs_txgxs_err_mask); | |
9caab458 SS |
1928 | } |
1929 | ||
1930 | if (mask & RX_DMA_INTR) { | |
1931 | gen_int_mask |= RXDMA_INT_M; | |
1932 | do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M | | |
d44570e4 JP |
1933 | RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M, |
1934 | flag, &bar0->rxdma_int_mask); | |
9caab458 | 1935 | do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR | |
d44570e4 JP |
1936 | RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM | |
1937 | RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR | | |
1938 | RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask); | |
9caab458 | 1939 | do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn | |
d44570e4 JP |
1940 | PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn | |
1941 | PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag, | |
1942 | &bar0->prc_pcix_err_mask); | |
9caab458 | 1943 | do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR | |
d44570e4 JP |
1944 | RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag, |
1945 | &bar0->rpa_err_mask); | |
9caab458 | 1946 | do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR | |
d44570e4 JP |
1947 | RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM | |
1948 | RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR | | |
1949 | RDA_FRM_ECC_SG_ERR | | |
1950 | RDA_MISC_ERR|RDA_PCIX_ERR, | |
1951 | flag, &bar0->rda_err_mask); | |
9caab458 | 1952 | do_s2io_write_bits(RTI_SM_ERR_ALARM | |
d44570e4 JP |
1953 | RTI_ECC_SG_ERR | RTI_ECC_DB_ERR, |
1954 | flag, &bar0->rti_err_mask); | |
9caab458 SS |
1955 | } |
1956 | ||
1957 | if (mask & RX_MAC_INTR) { | |
1958 | gen_int_mask |= RXMAC_INT_M; | |
1959 | do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag, | |
d44570e4 JP |
1960 | &bar0->mac_int_mask); |
1961 | interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR | | |
1962 | RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR | | |
1963 | RMAC_DOUBLE_ECC_ERR); | |
01e16faa SH |
1964 | if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) |
1965 | interruptible |= RMAC_LINK_STATE_CHANGE_INT; | |
1966 | do_s2io_write_bits(interruptible, | |
d44570e4 | 1967 | flag, &bar0->mac_rmac_err_mask); |
9caab458 SS |
1968 | } |
1969 | ||
d44570e4 | 1970 | if (mask & RX_XGXS_INTR) { |
9caab458 SS |
1971 | gen_int_mask |= RXXGXS_INT_M; |
1972 | do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag, | |
d44570e4 | 1973 | &bar0->xgxs_int_mask); |
9caab458 | 1974 | do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag, |
d44570e4 | 1975 | &bar0->xgxs_rxgxs_err_mask); |
9caab458 SS |
1976 | } |
1977 | ||
1978 | if (mask & MC_INTR) { | |
1979 | gen_int_mask |= MC_INT_M; | |
d44570e4 JP |
1980 | do_s2io_write_bits(MC_INT_MASK_MC_INT, |
1981 | flag, &bar0->mc_int_mask); | |
9caab458 | 1982 | do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG | |
d44570e4 JP |
1983 | MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag, |
1984 | &bar0->mc_err_mask); | |
9caab458 SS |
1985 | } |
1986 | nic->general_int_mask = gen_int_mask; | |
1987 | ||
1988 | /* Remove this line when alarm interrupts are enabled */ | |
1989 | nic->general_int_mask = 0; | |
1990 | } | |
d44570e4 | 1991 | |
20346722 K |
1992 | /** |
1993 | * en_dis_able_nic_intrs - Enable or Disable the interrupts | |
1da177e4 LT |
1994 | * @nic: device private variable, |
1995 | * @mask: A mask indicating which Intr block must be modified and, | |
1996 | * @flag: A flag indicating whether to enable or disable the Intrs. | |
1997 | * Description: This function will either disable or enable the interrupts | |
20346722 K |
1998 | * depending on the flag argument. The mask argument can be used to |
1999 | * enable/disable any Intr block. | |
1da177e4 LT |
2000 | * Return Value: NONE. |
2001 | */ | |
2002 | ||
2003 | static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) | |
2004 | { | |
1ee6dd77 | 2005 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
9caab458 SS |
2006 | register u64 temp64 = 0, intr_mask = 0; |
2007 | ||
2008 | intr_mask = nic->general_int_mask; | |
1da177e4 LT |
2009 | |
2010 | /* Top level interrupt classification */ | |
2011 | /* PIC Interrupts */ | |
9caab458 | 2012 | if (mask & TX_PIC_INTR) { |
1da177e4 | 2013 | /* Enable PIC Intrs in the general intr mask register */ |
9caab458 | 2014 | intr_mask |= TXPIC_INT_M; |
1da177e4 | 2015 | if (flag == ENABLE_INTRS) { |
20346722 | 2016 | /* |
a371a07d | 2017 | * If Hercules adapter enable GPIO otherwise |
b41477f3 | 2018 | * disable all PCIX, Flash, MDIO, IIC and GPIO |
20346722 K |
2019 | * interrupts for now. |
2020 | * TODO | |
1da177e4 | 2021 | */ |
a371a07d | 2022 | if (s2io_link_fault_indication(nic) == |
d44570e4 | 2023 | LINK_UP_DOWN_INTERRUPT) { |
9caab458 | 2024 | do_s2io_write_bits(PIC_INT_GPIO, flag, |
d44570e4 | 2025 | &bar0->pic_int_mask); |
9caab458 | 2026 | do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag, |
d44570e4 | 2027 | &bar0->gpio_int_mask); |
9caab458 | 2028 | } else |
a371a07d | 2029 | writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); |
1da177e4 | 2030 | } else if (flag == DISABLE_INTRS) { |
20346722 K |
2031 | /* |
2032 | * Disable PIC Intrs in the general | |
2033 | * intr mask register | |
1da177e4 LT |
2034 | */ |
2035 | writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); | |
1da177e4 LT |
2036 | } |
2037 | } | |
2038 | ||
1da177e4 LT |
2039 | /* Tx traffic interrupts */ |
2040 | if (mask & TX_TRAFFIC_INTR) { | |
9caab458 | 2041 | intr_mask |= TXTRAFFIC_INT_M; |
1da177e4 | 2042 | if (flag == ENABLE_INTRS) { |
20346722 | 2043 | /* |
1da177e4 | 2044 | * Enable all the Tx side interrupts |
20346722 | 2045 | * writing 0 Enables all 64 TX interrupt levels |
1da177e4 LT |
2046 | */ |
2047 | writeq(0x0, &bar0->tx_traffic_mask); | |
2048 | } else if (flag == DISABLE_INTRS) { | |
20346722 K |
2049 | /* |
2050 | * Disable Tx Traffic Intrs in the general intr mask | |
1da177e4 LT |
2051 | * register. |
2052 | */ | |
2053 | writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); | |
1da177e4 LT |
2054 | } |
2055 | } | |
2056 | ||
2057 | /* Rx traffic interrupts */ | |
2058 | if (mask & RX_TRAFFIC_INTR) { | |
9caab458 | 2059 | intr_mask |= RXTRAFFIC_INT_M; |
1da177e4 | 2060 | if (flag == ENABLE_INTRS) { |
1da177e4 LT |
2061 | /* writing 0 Enables all 8 RX interrupt levels */ |
2062 | writeq(0x0, &bar0->rx_traffic_mask); | |
2063 | } else if (flag == DISABLE_INTRS) { | |
20346722 K |
2064 | /* |
2065 | * Disable Rx Traffic Intrs in the general intr mask | |
1da177e4 LT |
2066 | * register. |
2067 | */ | |
2068 | writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); | |
1da177e4 LT |
2069 | } |
2070 | } | |
9caab458 SS |
2071 | |
2072 | temp64 = readq(&bar0->general_int_mask); | |
2073 | if (flag == ENABLE_INTRS) | |
d44570e4 | 2074 | temp64 &= ~((u64)intr_mask); |
9caab458 SS |
2075 | else |
2076 | temp64 = DISABLE_ALL_INTRS; | |
2077 | writeq(temp64, &bar0->general_int_mask); | |
2078 | ||
2079 | nic->general_int_mask = readq(&bar0->general_int_mask); | |
1da177e4 LT |
2080 | } |
2081 | ||
19a60522 SS |
2082 | /** |
2083 | * verify_pcc_quiescent- Checks for PCC quiescent state | |
2084 | * Return: 1 If PCC is quiescence | |
2085 | * 0 If PCC is not quiescence | |
2086 | */ | |
1ee6dd77 | 2087 | static int verify_pcc_quiescent(struct s2io_nic *sp, int flag) |
20346722 | 2088 | { |
19a60522 | 2089 | int ret = 0, herc; |
1ee6dd77 | 2090 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
19a60522 | 2091 | u64 val64 = readq(&bar0->adapter_status); |
8a4bdbaa | 2092 | |
19a60522 | 2093 | herc = (sp->device_type == XFRAME_II_DEVICE); |
20346722 | 2094 | |
f957bcf0 | 2095 | if (flag == false) { |
44c10138 | 2096 | if ((!herc && (sp->pdev->revision >= 4)) || herc) { |
19a60522 | 2097 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) |
5e25b9dd | 2098 | ret = 1; |
19a60522 SS |
2099 | } else { |
2100 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) | |
5e25b9dd | 2101 | ret = 1; |
20346722 K |
2102 | } |
2103 | } else { | |
44c10138 | 2104 | if ((!herc && (sp->pdev->revision >= 4)) || herc) { |
5e25b9dd | 2105 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == |
19a60522 | 2106 | ADAPTER_STATUS_RMAC_PCC_IDLE)) |
5e25b9dd | 2107 | ret = 1; |
5e25b9dd K |
2108 | } else { |
2109 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == | |
19a60522 | 2110 | ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) |
5e25b9dd | 2111 | ret = 1; |
20346722 K |
2112 | } |
2113 | } | |
2114 | ||
2115 | return ret; | |
2116 | } | |
2117 | /** | |
2118 | * verify_xena_quiescence - Checks whether the H/W is ready | |
1da177e4 | 2119 | * Description: Returns whether the H/W is ready to go or not. Depending |
20346722 | 2120 | * on whether adapter enable bit was written or not the comparison |
1da177e4 LT |
2121 | * differs and the calling function passes the input argument flag to |
2122 | * indicate this. | |
20346722 | 2123 | * Return: 1 If xena is quiescence |
1da177e4 LT |
2124 | * 0 If Xena is not quiescence |
2125 | */ | |
2126 | ||
1ee6dd77 | 2127 | static int verify_xena_quiescence(struct s2io_nic *sp) |
1da177e4 | 2128 | { |
19a60522 | 2129 | int mode; |
1ee6dd77 | 2130 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
19a60522 SS |
2131 | u64 val64 = readq(&bar0->adapter_status); |
2132 | mode = s2io_verify_pci_mode(sp); | |
1da177e4 | 2133 | |
19a60522 | 2134 | if (!(val64 & ADAPTER_STATUS_TDMA_READY)) { |
9e39f7c5 | 2135 | DBG_PRINT(ERR_DBG, "TDMA is not ready!\n"); |
19a60522 SS |
2136 | return 0; |
2137 | } | |
2138 | if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { | |
9e39f7c5 | 2139 | DBG_PRINT(ERR_DBG, "RDMA is not ready!\n"); |
19a60522 SS |
2140 | return 0; |
2141 | } | |
2142 | if (!(val64 & ADAPTER_STATUS_PFC_READY)) { | |
9e39f7c5 | 2143 | DBG_PRINT(ERR_DBG, "PFC is not ready!\n"); |
19a60522 SS |
2144 | return 0; |
2145 | } | |
2146 | if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) { | |
9e39f7c5 | 2147 | DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n"); |
19a60522 SS |
2148 | return 0; |
2149 | } | |
2150 | if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) { | |
9e39f7c5 | 2151 | DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n"); |
19a60522 SS |
2152 | return 0; |
2153 | } | |
2154 | if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) { | |
9e39f7c5 | 2155 | DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n"); |
19a60522 SS |
2156 | return 0; |
2157 | } | |
2158 | if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) { | |
9e39f7c5 | 2159 | DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n"); |
19a60522 SS |
2160 | return 0; |
2161 | } | |
2162 | if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) { | |
9e39f7c5 | 2163 | DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n"); |
19a60522 | 2164 | return 0; |
1da177e4 LT |
2165 | } |
2166 | ||
19a60522 SS |
2167 | /* |
2168 | * In PCI 33 mode, the P_PLL is not used, and therefore, | |
2169 | * the the P_PLL_LOCK bit in the adapter_status register will | |
2170 | * not be asserted. | |
2171 | */ | |
2172 | if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && | |
d44570e4 JP |
2173 | sp->device_type == XFRAME_II_DEVICE && |
2174 | mode != PCI_MODE_PCI_33) { | |
9e39f7c5 | 2175 | DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n"); |
19a60522 SS |
2176 | return 0; |
2177 | } | |
2178 | if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | |
d44570e4 | 2179 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { |
9e39f7c5 | 2180 | DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n"); |
19a60522 SS |
2181 | return 0; |
2182 | } | |
2183 | return 1; | |
1da177e4 LT |
2184 | } |
2185 | ||
2186 | /** | |
2187 | * fix_mac_address - Fix for Mac addr problem on Alpha platforms | |
2188 | * @sp: Pointer to device specifc structure | |
20346722 | 2189 | * Description : |
1da177e4 LT |
2190 | * New procedure to clear mac address reading problems on Alpha platforms |
2191 | * | |
2192 | */ | |
2193 | ||
d44570e4 | 2194 | static void fix_mac_address(struct s2io_nic *sp) |
1da177e4 | 2195 | { |
1ee6dd77 | 2196 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
2197 | int i = 0; |
2198 | ||
2199 | while (fix_mac[i] != END_SIGN) { | |
2200 | writeq(fix_mac[i++], &bar0->gpio_control); | |
20346722 | 2201 | udelay(10); |
d83d282b | 2202 | (void) readq(&bar0->gpio_control); |
1da177e4 LT |
2203 | } |
2204 | } | |
2205 | ||
2206 | /** | |
20346722 | 2207 | * start_nic - Turns the device on |
1da177e4 | 2208 | * @nic : device private variable. |
20346722 K |
2209 | * Description: |
2210 | * This function actually turns the device on. Before this function is | |
2211 | * called,all Registers are configured from their reset states | |
2212 | * and shared memory is allocated but the NIC is still quiescent. On | |
1da177e4 LT |
2213 | * calling this function, the device interrupts are cleared and the NIC is |
2214 | * literally switched on by writing into the adapter control register. | |
20346722 | 2215 | * Return Value: |
1da177e4 LT |
2216 | * SUCCESS on success and -1 on failure. |
2217 | */ | |
2218 | ||
2219 | static int start_nic(struct s2io_nic *nic) | |
2220 | { | |
1ee6dd77 | 2221 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 LT |
2222 | struct net_device *dev = nic->dev; |
2223 | register u64 val64 = 0; | |
20346722 | 2224 | u16 subid, i; |
ffb5df6c JP |
2225 | struct config_param *config = &nic->config; |
2226 | struct mac_info *mac_control = &nic->mac_control; | |
1da177e4 LT |
2227 | |
2228 | /* PRC Initialization and configuration */ | |
2229 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
2230 | struct ring_info *ring = &mac_control->rings[i]; |
2231 | ||
d44570e4 | 2232 | writeq((u64)ring->rx_blocks[0].block_dma_addr, |
1da177e4 LT |
2233 | &bar0->prc_rxd0_n[i]); |
2234 | ||
2235 | val64 = readq(&bar0->prc_ctrl_n[i]); | |
da6971d8 AR |
2236 | if (nic->rxd_mode == RXD_MODE_1) |
2237 | val64 |= PRC_CTRL_RC_ENABLED; | |
2238 | else | |
2239 | val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; | |
863c11a9 AR |
2240 | if (nic->device_type == XFRAME_II_DEVICE) |
2241 | val64 |= PRC_CTRL_GROUP_READS; | |
2242 | val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); | |
2243 | val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000); | |
1da177e4 LT |
2244 | writeq(val64, &bar0->prc_ctrl_n[i]); |
2245 | } | |
2246 | ||
da6971d8 AR |
2247 | if (nic->rxd_mode == RXD_MODE_3B) { |
2248 | /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */ | |
2249 | val64 = readq(&bar0->rx_pa_cfg); | |
2250 | val64 |= RX_PA_CFG_IGNORE_L2_ERR; | |
2251 | writeq(val64, &bar0->rx_pa_cfg); | |
2252 | } | |
1da177e4 | 2253 | |
926930b2 SS |
2254 | if (vlan_tag_strip == 0) { |
2255 | val64 = readq(&bar0->rx_pa_cfg); | |
2256 | val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; | |
2257 | writeq(val64, &bar0->rx_pa_cfg); | |
cd0fce03 | 2258 | nic->vlan_strip_flag = 0; |
926930b2 SS |
2259 | } |
2260 | ||
20346722 | 2261 | /* |
1da177e4 LT |
2262 | * Enabling MC-RLDRAM. After enabling the device, we timeout |
2263 | * for around 100ms, which is approximately the time required | |
2264 | * for the device to be ready for operation. | |
2265 | */ | |
2266 | val64 = readq(&bar0->mc_rldram_mrs); | |
2267 | val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; | |
2268 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); | |
2269 | val64 = readq(&bar0->mc_rldram_mrs); | |
2270 | ||
20346722 | 2271 | msleep(100); /* Delay by around 100 ms. */ |
1da177e4 LT |
2272 | |
2273 | /* Enabling ECC Protection. */ | |
2274 | val64 = readq(&bar0->adapter_control); | |
2275 | val64 &= ~ADAPTER_ECC_EN; | |
2276 | writeq(val64, &bar0->adapter_control); | |
2277 | ||
20346722 K |
2278 | /* |
2279 | * Verify if the device is ready to be enabled, if so enable | |
1da177e4 LT |
2280 | * it. |
2281 | */ | |
2282 | val64 = readq(&bar0->adapter_status); | |
19a60522 | 2283 | if (!verify_xena_quiescence(nic)) { |
9e39f7c5 JP |
2284 | DBG_PRINT(ERR_DBG, "%s: device is not ready, " |
2285 | "Adapter status reads: 0x%llx\n", | |
2286 | dev->name, (unsigned long long)val64); | |
1da177e4 LT |
2287 | return FAILURE; |
2288 | } | |
2289 | ||
20346722 | 2290 | /* |
1da177e4 | 2291 | * With some switches, link might be already up at this point. |
20346722 K |
2292 | * Because of this weird behavior, when we enable laser, |
2293 | * we may not get link. We need to handle this. We cannot | |
2294 | * figure out which switch is misbehaving. So we are forced to | |
2295 | * make a global change. | |
1da177e4 LT |
2296 | */ |
2297 | ||
2298 | /* Enabling Laser. */ | |
2299 | val64 = readq(&bar0->adapter_control); | |
2300 | val64 |= ADAPTER_EOI_TX_ON; | |
2301 | writeq(val64, &bar0->adapter_control); | |
2302 | ||
c92ca04b AR |
2303 | if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { |
2304 | /* | |
25985edc | 2305 | * Dont see link state interrupts initially on some switches, |
c92ca04b AR |
2306 | * so directly scheduling the link state task here. |
2307 | */ | |
2308 | schedule_work(&nic->set_link_task); | |
2309 | } | |
1da177e4 LT |
2310 | /* SXE-002: Initialize link and activity LED */ |
2311 | subid = nic->pdev->subsystem_device; | |
541ae68f K |
2312 | if (((subid & 0xFF) >= 0x07) && |
2313 | (nic->device_type == XFRAME_I_DEVICE)) { | |
1da177e4 LT |
2314 | val64 = readq(&bar0->gpio_control); |
2315 | val64 |= 0x0000800000000000ULL; | |
2316 | writeq(val64, &bar0->gpio_control); | |
2317 | val64 = 0x0411040400000000ULL; | |
509a2671 | 2318 | writeq(val64, (void __iomem *)bar0 + 0x2700); |
1da177e4 LT |
2319 | } |
2320 | ||
1da177e4 LT |
2321 | return SUCCESS; |
2322 | } | |
fed5eccd AR |
2323 | /** |
2324 | * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb | |
2325 | */ | |
d44570e4 JP |
2326 | static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, |
2327 | struct TxD *txdlp, int get_off) | |
fed5eccd | 2328 | { |
1ee6dd77 | 2329 | struct s2io_nic *nic = fifo_data->nic; |
fed5eccd | 2330 | struct sk_buff *skb; |
1ee6dd77 | 2331 | struct TxD *txds; |
fed5eccd AR |
2332 | u16 j, frg_cnt; |
2333 | ||
2334 | txds = txdlp; | |
2fda096d | 2335 | if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) { |
d44570e4 JP |
2336 | pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer, |
2337 | sizeof(u64), PCI_DMA_TODEVICE); | |
fed5eccd AR |
2338 | txds++; |
2339 | } | |
2340 | ||
d44570e4 | 2341 | skb = (struct sk_buff *)((unsigned long)txds->Host_Control); |
fed5eccd | 2342 | if (!skb) { |
1ee6dd77 | 2343 | memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds)); |
fed5eccd AR |
2344 | return NULL; |
2345 | } | |
d44570e4 | 2346 | pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer, |
e743d313 | 2347 | skb_headlen(skb), PCI_DMA_TODEVICE); |
fed5eccd AR |
2348 | frg_cnt = skb_shinfo(skb)->nr_frags; |
2349 | if (frg_cnt) { | |
2350 | txds++; | |
2351 | for (j = 0; j < frg_cnt; j++, txds++) { | |
9e903e08 | 2352 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; |
fed5eccd AR |
2353 | if (!txds->Buffer_Pointer) |
2354 | break; | |
d44570e4 JP |
2355 | pci_unmap_page(nic->pdev, |
2356 | (dma_addr_t)txds->Buffer_Pointer, | |
9e903e08 | 2357 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
fed5eccd AR |
2358 | } |
2359 | } | |
d44570e4 JP |
2360 | memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds)); |
2361 | return skb; | |
fed5eccd | 2362 | } |
1da177e4 | 2363 | |
20346722 K |
2364 | /** |
2365 | * free_tx_buffers - Free all queued Tx buffers | |
1da177e4 | 2366 | * @nic : device private variable. |
20346722 | 2367 | * Description: |
1da177e4 | 2368 | * Free all queued Tx buffers. |
20346722 | 2369 | * Return Value: void |
d44570e4 | 2370 | */ |
1da177e4 LT |
2371 | |
2372 | static void free_tx_buffers(struct s2io_nic *nic) | |
2373 | { | |
2374 | struct net_device *dev = nic->dev; | |
2375 | struct sk_buff *skb; | |
1ee6dd77 | 2376 | struct TxD *txdp; |
1da177e4 | 2377 | int i, j; |
fed5eccd | 2378 | int cnt = 0; |
ffb5df6c JP |
2379 | struct config_param *config = &nic->config; |
2380 | struct mac_info *mac_control = &nic->mac_control; | |
2381 | struct stat_block *stats = mac_control->stats_info; | |
2382 | struct swStat *swstats = &stats->sw_stat; | |
1da177e4 LT |
2383 | |
2384 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
2385 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
2386 | struct fifo_info *fifo = &mac_control->fifos[i]; | |
2fda096d | 2387 | unsigned long flags; |
13d866a9 JP |
2388 | |
2389 | spin_lock_irqsave(&fifo->tx_lock, flags); | |
2390 | for (j = 0; j < tx_cfg->fifo_len; j++) { | |
43d620c8 | 2391 | txdp = fifo->list_info[j].list_virt_addr; |
fed5eccd AR |
2392 | skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j); |
2393 | if (skb) { | |
ffb5df6c | 2394 | swstats->mem_freed += skb->truesize; |
fed5eccd AR |
2395 | dev_kfree_skb(skb); |
2396 | cnt++; | |
1da177e4 | 2397 | } |
1da177e4 LT |
2398 | } |
2399 | DBG_PRINT(INTR_DBG, | |
9e39f7c5 | 2400 | "%s: forcibly freeing %d skbs on FIFO%d\n", |
1da177e4 | 2401 | dev->name, cnt, i); |
13d866a9 JP |
2402 | fifo->tx_curr_get_info.offset = 0; |
2403 | fifo->tx_curr_put_info.offset = 0; | |
2404 | spin_unlock_irqrestore(&fifo->tx_lock, flags); | |
1da177e4 LT |
2405 | } |
2406 | } | |
2407 | ||
20346722 K |
2408 | /** |
2409 | * stop_nic - To stop the nic | |
1da177e4 | 2410 | * @nic ; device private variable. |
20346722 K |
2411 | * Description: |
2412 | * This function does exactly the opposite of what the start_nic() | |
1da177e4 LT |
2413 | * function does. This function is called to stop the device. |
2414 | * Return Value: | |
2415 | * void. | |
2416 | */ | |
2417 | ||
2418 | static void stop_nic(struct s2io_nic *nic) | |
2419 | { | |
1ee6dd77 | 2420 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 | 2421 | register u64 val64 = 0; |
5d3213cc | 2422 | u16 interruptible; |
1da177e4 LT |
2423 | |
2424 | /* Disable all interrupts */ | |
9caab458 | 2425 | en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS); |
e960fc5c | 2426 | interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; |
9caab458 | 2427 | interruptible |= TX_PIC_INTR; |
1da177e4 LT |
2428 | en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS); |
2429 | ||
5d3213cc AR |
2430 | /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */ |
2431 | val64 = readq(&bar0->adapter_control); | |
2432 | val64 &= ~(ADAPTER_CNTL_EN); | |
2433 | writeq(val64, &bar0->adapter_control); | |
1da177e4 LT |
2434 | } |
2435 | ||
20346722 K |
2436 | /** |
2437 | * fill_rx_buffers - Allocates the Rx side skbs | |
0425b46a | 2438 | * @ring_info: per ring structure |
3f78d885 SH |
2439 | * @from_card_up: If this is true, we will map the buffer to get |
2440 | * the dma address for buf0 and buf1 to give it to the card. | |
2441 | * Else we will sync the already mapped buffer to give it to the card. | |
20346722 | 2442 | * Description: |
1da177e4 LT |
2443 | * The function allocates Rx side skbs and puts the physical |
2444 | * address of these buffers into the RxD buffer pointers, so that the NIC | |
2445 | * can DMA the received frame into these locations. | |
2446 | * The NIC supports 3 receive modes, viz | |
2447 | * 1. single buffer, | |
2448 | * 2. three buffer and | |
2449 | * 3. Five buffer modes. | |
20346722 K |
2450 | * Each mode defines how many fragments the received frame will be split |
2451 | * up into by the NIC. The frame is split into L3 header, L4 Header, | |
1da177e4 LT |
2452 | * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself |
2453 | * is split into 3 fragments. As of now only single buffer mode is | |
2454 | * supported. | |
2455 | * Return Value: | |
2456 | * SUCCESS on success or an appropriate -ve value on failure. | |
2457 | */ | |
8d8bb39b | 2458 | static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring, |
d44570e4 | 2459 | int from_card_up) |
1da177e4 | 2460 | { |
1da177e4 | 2461 | struct sk_buff *skb; |
1ee6dd77 | 2462 | struct RxD_t *rxdp; |
0425b46a | 2463 | int off, size, block_no, block_no1; |
1da177e4 | 2464 | u32 alloc_tab = 0; |
20346722 | 2465 | u32 alloc_cnt; |
20346722 | 2466 | u64 tmp; |
1ee6dd77 | 2467 | struct buffAdd *ba; |
1ee6dd77 | 2468 | struct RxD_t *first_rxdp = NULL; |
363dc367 | 2469 | u64 Buffer0_ptr = 0, Buffer1_ptr = 0; |
0425b46a | 2470 | int rxd_index = 0; |
6d517a27 VP |
2471 | struct RxD1 *rxdp1; |
2472 | struct RxD3 *rxdp3; | |
ffb5df6c | 2473 | struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat; |
1da177e4 | 2474 | |
0425b46a | 2475 | alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left; |
1da177e4 | 2476 | |
0425b46a | 2477 | block_no1 = ring->rx_curr_get_info.block_index; |
1da177e4 | 2478 | while (alloc_tab < alloc_cnt) { |
0425b46a | 2479 | block_no = ring->rx_curr_put_info.block_index; |
1da177e4 | 2480 | |
0425b46a SH |
2481 | off = ring->rx_curr_put_info.offset; |
2482 | ||
2483 | rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr; | |
2484 | ||
2485 | rxd_index = off + 1; | |
2486 | if (block_no) | |
2487 | rxd_index += (block_no * ring->rxd_count); | |
da6971d8 | 2488 | |
7d2e3cb7 | 2489 | if ((block_no == block_no1) && |
d44570e4 JP |
2490 | (off == ring->rx_curr_get_info.offset) && |
2491 | (rxdp->Host_Control)) { | |
9e39f7c5 JP |
2492 | DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n", |
2493 | ring->dev->name); | |
1da177e4 LT |
2494 | goto end; |
2495 | } | |
0425b46a SH |
2496 | if (off && (off == ring->rxd_count)) { |
2497 | ring->rx_curr_put_info.block_index++; | |
2498 | if (ring->rx_curr_put_info.block_index == | |
d44570e4 | 2499 | ring->block_count) |
0425b46a SH |
2500 | ring->rx_curr_put_info.block_index = 0; |
2501 | block_no = ring->rx_curr_put_info.block_index; | |
2502 | off = 0; | |
2503 | ring->rx_curr_put_info.offset = off; | |
2504 | rxdp = ring->rx_blocks[block_no].block_virt_addr; | |
1da177e4 | 2505 | DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", |
0425b46a SH |
2506 | ring->dev->name, rxdp); |
2507 | ||
1da177e4 | 2508 | } |
c9fcbf47 | 2509 | |
da6971d8 | 2510 | if ((rxdp->Control_1 & RXD_OWN_XENA) && |
d44570e4 JP |
2511 | ((ring->rxd_mode == RXD_MODE_3B) && |
2512 | (rxdp->Control_2 & s2BIT(0)))) { | |
0425b46a | 2513 | ring->rx_curr_put_info.offset = off; |
1da177e4 LT |
2514 | goto end; |
2515 | } | |
da6971d8 | 2516 | /* calculate size of skb based on ring mode */ |
d44570e4 JP |
2517 | size = ring->mtu + |
2518 | HEADER_ETHERNET_II_802_3_SIZE + | |
2519 | HEADER_802_2_SIZE + HEADER_SNAP_SIZE; | |
0425b46a | 2520 | if (ring->rxd_mode == RXD_MODE_1) |
da6971d8 | 2521 | size += NET_IP_ALIGN; |
da6971d8 | 2522 | else |
0425b46a | 2523 | size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4; |
1da177e4 | 2524 | |
da6971d8 | 2525 | /* allocate skb */ |
c056b734 | 2526 | skb = netdev_alloc_skb(nic->dev, size); |
d44570e4 | 2527 | if (!skb) { |
9e39f7c5 JP |
2528 | DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n", |
2529 | ring->dev->name); | |
303bcb4b K |
2530 | if (first_rxdp) { |
2531 | wmb(); | |
2532 | first_rxdp->Control_1 |= RXD_OWN_XENA; | |
2533 | } | |
ffb5df6c | 2534 | swstats->mem_alloc_fail_cnt++; |
7d2e3cb7 | 2535 | |
da6971d8 AR |
2536 | return -ENOMEM ; |
2537 | } | |
ffb5df6c | 2538 | swstats->mem_allocated += skb->truesize; |
0425b46a SH |
2539 | |
2540 | if (ring->rxd_mode == RXD_MODE_1) { | |
da6971d8 | 2541 | /* 1 buffer mode - normal operation mode */ |
d44570e4 | 2542 | rxdp1 = (struct RxD1 *)rxdp; |
1ee6dd77 | 2543 | memset(rxdp, 0, sizeof(struct RxD1)); |
da6971d8 | 2544 | skb_reserve(skb, NET_IP_ALIGN); |
d44570e4 JP |
2545 | rxdp1->Buffer0_ptr = |
2546 | pci_map_single(ring->pdev, skb->data, | |
2547 | size - NET_IP_ALIGN, | |
2548 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 2549 | if (pci_dma_mapping_error(nic->pdev, |
d44570e4 | 2550 | rxdp1->Buffer0_ptr)) |
491abf25 VP |
2551 | goto pci_map_failed; |
2552 | ||
8a4bdbaa | 2553 | rxdp->Control_2 = |
491976b2 | 2554 | SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN); |
d44570e4 | 2555 | rxdp->Host_Control = (unsigned long)skb; |
0425b46a | 2556 | } else if (ring->rxd_mode == RXD_MODE_3B) { |
da6971d8 | 2557 | /* |
6d517a27 VP |
2558 | * 2 buffer mode - |
2559 | * 2 buffer mode provides 128 | |
da6971d8 | 2560 | * byte aligned receive buffers. |
da6971d8 AR |
2561 | */ |
2562 | ||
d44570e4 | 2563 | rxdp3 = (struct RxD3 *)rxdp; |
491976b2 | 2564 | /* save buffer pointers to avoid frequent dma mapping */ |
6d517a27 VP |
2565 | Buffer0_ptr = rxdp3->Buffer0_ptr; |
2566 | Buffer1_ptr = rxdp3->Buffer1_ptr; | |
1ee6dd77 | 2567 | memset(rxdp, 0, sizeof(struct RxD3)); |
363dc367 | 2568 | /* restore the buffer pointers for dma sync*/ |
6d517a27 VP |
2569 | rxdp3->Buffer0_ptr = Buffer0_ptr; |
2570 | rxdp3->Buffer1_ptr = Buffer1_ptr; | |
363dc367 | 2571 | |
0425b46a | 2572 | ba = &ring->ba[block_no][off]; |
da6971d8 | 2573 | skb_reserve(skb, BUF0_LEN); |
d44570e4 | 2574 | tmp = (u64)(unsigned long)skb->data; |
da6971d8 AR |
2575 | tmp += ALIGN_SIZE; |
2576 | tmp &= ~ALIGN_SIZE; | |
2577 | skb->data = (void *) (unsigned long)tmp; | |
27a884dc | 2578 | skb_reset_tail_pointer(skb); |
da6971d8 | 2579 | |
3f78d885 | 2580 | if (from_card_up) { |
6d517a27 | 2581 | rxdp3->Buffer0_ptr = |
d44570e4 JP |
2582 | pci_map_single(ring->pdev, ba->ba_0, |
2583 | BUF0_LEN, | |
2584 | PCI_DMA_FROMDEVICE); | |
2585 | if (pci_dma_mapping_error(nic->pdev, | |
2586 | rxdp3->Buffer0_ptr)) | |
3f78d885 SH |
2587 | goto pci_map_failed; |
2588 | } else | |
0425b46a | 2589 | pci_dma_sync_single_for_device(ring->pdev, |
d44570e4 JP |
2590 | (dma_addr_t)rxdp3->Buffer0_ptr, |
2591 | BUF0_LEN, | |
2592 | PCI_DMA_FROMDEVICE); | |
491abf25 | 2593 | |
da6971d8 | 2594 | rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); |
0425b46a | 2595 | if (ring->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
2596 | /* Two buffer mode */ |
2597 | ||
2598 | /* | |
6aa20a22 | 2599 | * Buffer2 will have L3/L4 header plus |
da6971d8 AR |
2600 | * L4 payload |
2601 | */ | |
d44570e4 JP |
2602 | rxdp3->Buffer2_ptr = pci_map_single(ring->pdev, |
2603 | skb->data, | |
2604 | ring->mtu + 4, | |
2605 | PCI_DMA_FROMDEVICE); | |
da6971d8 | 2606 | |
8d8bb39b | 2607 | if (pci_dma_mapping_error(nic->pdev, |
d44570e4 | 2608 | rxdp3->Buffer2_ptr)) |
491abf25 VP |
2609 | goto pci_map_failed; |
2610 | ||
3f78d885 | 2611 | if (from_card_up) { |
0425b46a SH |
2612 | rxdp3->Buffer1_ptr = |
2613 | pci_map_single(ring->pdev, | |
d44570e4 JP |
2614 | ba->ba_1, |
2615 | BUF1_LEN, | |
2616 | PCI_DMA_FROMDEVICE); | |
0425b46a | 2617 | |
8d8bb39b | 2618 | if (pci_dma_mapping_error(nic->pdev, |
d44570e4 JP |
2619 | rxdp3->Buffer1_ptr)) { |
2620 | pci_unmap_single(ring->pdev, | |
2621 | (dma_addr_t)(unsigned long) | |
2622 | skb->data, | |
2623 | ring->mtu + 4, | |
2624 | PCI_DMA_FROMDEVICE); | |
3f78d885 SH |
2625 | goto pci_map_failed; |
2626 | } | |
75c30b13 | 2627 | } |
da6971d8 AR |
2628 | rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); |
2629 | rxdp->Control_2 |= SET_BUFFER2_SIZE_3 | |
d44570e4 | 2630 | (ring->mtu + 4); |
da6971d8 | 2631 | } |
b7b5a128 | 2632 | rxdp->Control_2 |= s2BIT(0); |
0425b46a | 2633 | rxdp->Host_Control = (unsigned long) (skb); |
1da177e4 | 2634 | } |
303bcb4b K |
2635 | if (alloc_tab & ((1 << rxsync_frequency) - 1)) |
2636 | rxdp->Control_1 |= RXD_OWN_XENA; | |
1da177e4 | 2637 | off++; |
0425b46a | 2638 | if (off == (ring->rxd_count + 1)) |
da6971d8 | 2639 | off = 0; |
0425b46a | 2640 | ring->rx_curr_put_info.offset = off; |
20346722 | 2641 | |
da6971d8 | 2642 | rxdp->Control_2 |= SET_RXD_MARKER; |
303bcb4b K |
2643 | if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) { |
2644 | if (first_rxdp) { | |
2645 | wmb(); | |
2646 | first_rxdp->Control_1 |= RXD_OWN_XENA; | |
2647 | } | |
2648 | first_rxdp = rxdp; | |
2649 | } | |
0425b46a | 2650 | ring->rx_bufs_left += 1; |
1da177e4 LT |
2651 | alloc_tab++; |
2652 | } | |
2653 | ||
d44570e4 | 2654 | end: |
303bcb4b K |
2655 | /* Transfer ownership of first descriptor to adapter just before |
2656 | * exiting. Before that, use memory barrier so that ownership | |
2657 | * and other fields are seen by adapter correctly. | |
2658 | */ | |
2659 | if (first_rxdp) { | |
2660 | wmb(); | |
2661 | first_rxdp->Control_1 |= RXD_OWN_XENA; | |
2662 | } | |
2663 | ||
1da177e4 | 2664 | return SUCCESS; |
d44570e4 | 2665 | |
491abf25 | 2666 | pci_map_failed: |
ffb5df6c JP |
2667 | swstats->pci_map_fail_cnt++; |
2668 | swstats->mem_freed += skb->truesize; | |
491abf25 VP |
2669 | dev_kfree_skb_irq(skb); |
2670 | return -ENOMEM; | |
1da177e4 LT |
2671 | } |
2672 | ||
da6971d8 AR |
2673 | static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk) |
2674 | { | |
2675 | struct net_device *dev = sp->dev; | |
2676 | int j; | |
2677 | struct sk_buff *skb; | |
1ee6dd77 | 2678 | struct RxD_t *rxdp; |
6d517a27 VP |
2679 | struct RxD1 *rxdp1; |
2680 | struct RxD3 *rxdp3; | |
ffb5df6c JP |
2681 | struct mac_info *mac_control = &sp->mac_control; |
2682 | struct stat_block *stats = mac_control->stats_info; | |
2683 | struct swStat *swstats = &stats->sw_stat; | |
da6971d8 | 2684 | |
da6971d8 AR |
2685 | for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) { |
2686 | rxdp = mac_control->rings[ring_no]. | |
d44570e4 JP |
2687 | rx_blocks[blk].rxds[j].virt_addr; |
2688 | skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control); | |
2689 | if (!skb) | |
da6971d8 | 2690 | continue; |
da6971d8 | 2691 | if (sp->rxd_mode == RXD_MODE_1) { |
d44570e4 JP |
2692 | rxdp1 = (struct RxD1 *)rxdp; |
2693 | pci_unmap_single(sp->pdev, | |
2694 | (dma_addr_t)rxdp1->Buffer0_ptr, | |
2695 | dev->mtu + | |
2696 | HEADER_ETHERNET_II_802_3_SIZE + | |
2697 | HEADER_802_2_SIZE + HEADER_SNAP_SIZE, | |
2698 | PCI_DMA_FROMDEVICE); | |
1ee6dd77 | 2699 | memset(rxdp, 0, sizeof(struct RxD1)); |
d44570e4 JP |
2700 | } else if (sp->rxd_mode == RXD_MODE_3B) { |
2701 | rxdp3 = (struct RxD3 *)rxdp; | |
d44570e4 JP |
2702 | pci_unmap_single(sp->pdev, |
2703 | (dma_addr_t)rxdp3->Buffer0_ptr, | |
2704 | BUF0_LEN, | |
2705 | PCI_DMA_FROMDEVICE); | |
2706 | pci_unmap_single(sp->pdev, | |
2707 | (dma_addr_t)rxdp3->Buffer1_ptr, | |
2708 | BUF1_LEN, | |
2709 | PCI_DMA_FROMDEVICE); | |
2710 | pci_unmap_single(sp->pdev, | |
2711 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
2712 | dev->mtu + 4, | |
2713 | PCI_DMA_FROMDEVICE); | |
1ee6dd77 | 2714 | memset(rxdp, 0, sizeof(struct RxD3)); |
da6971d8 | 2715 | } |
ffb5df6c | 2716 | swstats->mem_freed += skb->truesize; |
da6971d8 | 2717 | dev_kfree_skb(skb); |
0425b46a | 2718 | mac_control->rings[ring_no].rx_bufs_left -= 1; |
da6971d8 AR |
2719 | } |
2720 | } | |
2721 | ||
1da177e4 | 2722 | /** |
20346722 | 2723 | * free_rx_buffers - Frees all Rx buffers |
1da177e4 | 2724 | * @sp: device private variable. |
20346722 | 2725 | * Description: |
1da177e4 LT |
2726 | * This function will free all Rx buffers allocated by host. |
2727 | * Return Value: | |
2728 | * NONE. | |
2729 | */ | |
2730 | ||
2731 | static void free_rx_buffers(struct s2io_nic *sp) | |
2732 | { | |
2733 | struct net_device *dev = sp->dev; | |
da6971d8 | 2734 | int i, blk = 0, buf_cnt = 0; |
ffb5df6c JP |
2735 | struct config_param *config = &sp->config; |
2736 | struct mac_info *mac_control = &sp->mac_control; | |
1da177e4 LT |
2737 | |
2738 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
2739 | struct ring_info *ring = &mac_control->rings[i]; |
2740 | ||
da6971d8 | 2741 | for (blk = 0; blk < rx_ring_sz[i]; blk++) |
d44570e4 | 2742 | free_rxd_blk(sp, i, blk); |
1da177e4 | 2743 | |
13d866a9 JP |
2744 | ring->rx_curr_put_info.block_index = 0; |
2745 | ring->rx_curr_get_info.block_index = 0; | |
2746 | ring->rx_curr_put_info.offset = 0; | |
2747 | ring->rx_curr_get_info.offset = 0; | |
2748 | ring->rx_bufs_left = 0; | |
9e39f7c5 | 2749 | DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n", |
1da177e4 LT |
2750 | dev->name, buf_cnt, i); |
2751 | } | |
2752 | } | |
2753 | ||
8d8bb39b | 2754 | static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring) |
f61e0a35 | 2755 | { |
8d8bb39b | 2756 | if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) { |
9e39f7c5 JP |
2757 | DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n", |
2758 | ring->dev->name); | |
f61e0a35 SH |
2759 | } |
2760 | return 0; | |
2761 | } | |
2762 | ||
1da177e4 LT |
2763 | /** |
2764 | * s2io_poll - Rx interrupt handler for NAPI support | |
bea3348e | 2765 | * @napi : pointer to the napi structure. |
20346722 | 2766 | * @budget : The number of packets that were budgeted to be processed |
1da177e4 LT |
2767 | * during one pass through the 'Poll" function. |
2768 | * Description: | |
2769 | * Comes into picture only if NAPI support has been incorporated. It does | |
2770 | * the same thing that rx_intr_handler does, but not in a interrupt context | |
2771 | * also It will process only a given number of packets. | |
2772 | * Return value: | |
2773 | * 0 on success and 1 if there are No Rx packets to be processed. | |
2774 | */ | |
2775 | ||
f61e0a35 | 2776 | static int s2io_poll_msix(struct napi_struct *napi, int budget) |
1da177e4 | 2777 | { |
f61e0a35 SH |
2778 | struct ring_info *ring = container_of(napi, struct ring_info, napi); |
2779 | struct net_device *dev = ring->dev; | |
f61e0a35 | 2780 | int pkts_processed = 0; |
1a79d1c3 AV |
2781 | u8 __iomem *addr = NULL; |
2782 | u8 val8 = 0; | |
4cf1653a | 2783 | struct s2io_nic *nic = netdev_priv(dev); |
1ee6dd77 | 2784 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
f61e0a35 | 2785 | int budget_org = budget; |
1da177e4 | 2786 | |
f61e0a35 SH |
2787 | if (unlikely(!is_s2io_card_up(nic))) |
2788 | return 0; | |
1da177e4 | 2789 | |
f61e0a35 | 2790 | pkts_processed = rx_intr_handler(ring, budget); |
8d8bb39b | 2791 | s2io_chk_rx_buffers(nic, ring); |
1da177e4 | 2792 | |
f61e0a35 | 2793 | if (pkts_processed < budget_org) { |
288379f0 | 2794 | napi_complete(napi); |
f61e0a35 | 2795 | /*Re Enable MSI-Rx Vector*/ |
1a79d1c3 | 2796 | addr = (u8 __iomem *)&bar0->xmsi_mask_reg; |
f61e0a35 SH |
2797 | addr += 7 - ring->ring_no; |
2798 | val8 = (ring->ring_no == 0) ? 0x3f : 0xbf; | |
2799 | writeb(val8, addr); | |
2800 | val8 = readb(addr); | |
1da177e4 | 2801 | } |
f61e0a35 SH |
2802 | return pkts_processed; |
2803 | } | |
d44570e4 | 2804 | |
f61e0a35 SH |
2805 | static int s2io_poll_inta(struct napi_struct *napi, int budget) |
2806 | { | |
2807 | struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi); | |
f61e0a35 SH |
2808 | int pkts_processed = 0; |
2809 | int ring_pkts_processed, i; | |
2810 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
2811 | int budget_org = budget; | |
ffb5df6c JP |
2812 | struct config_param *config = &nic->config; |
2813 | struct mac_info *mac_control = &nic->mac_control; | |
1da177e4 | 2814 | |
f61e0a35 SH |
2815 | if (unlikely(!is_s2io_card_up(nic))) |
2816 | return 0; | |
1da177e4 | 2817 | |
1da177e4 | 2818 | for (i = 0; i < config->rx_ring_num; i++) { |
13d866a9 | 2819 | struct ring_info *ring = &mac_control->rings[i]; |
f61e0a35 | 2820 | ring_pkts_processed = rx_intr_handler(ring, budget); |
8d8bb39b | 2821 | s2io_chk_rx_buffers(nic, ring); |
f61e0a35 SH |
2822 | pkts_processed += ring_pkts_processed; |
2823 | budget -= ring_pkts_processed; | |
2824 | if (budget <= 0) | |
1da177e4 | 2825 | break; |
1da177e4 | 2826 | } |
f61e0a35 | 2827 | if (pkts_processed < budget_org) { |
288379f0 | 2828 | napi_complete(napi); |
f61e0a35 SH |
2829 | /* Re enable the Rx interrupts for the ring */ |
2830 | writeq(0, &bar0->rx_traffic_mask); | |
2831 | readl(&bar0->rx_traffic_mask); | |
2832 | } | |
2833 | return pkts_processed; | |
1da177e4 | 2834 | } |
20346722 | 2835 | |
b41477f3 | 2836 | #ifdef CONFIG_NET_POLL_CONTROLLER |
612eff0e | 2837 | /** |
b41477f3 | 2838 | * s2io_netpoll - netpoll event handler entry point |
612eff0e BH |
2839 | * @dev : pointer to the device structure. |
2840 | * Description: | |
b41477f3 AR |
2841 | * This function will be called by upper layer to check for events on the |
2842 | * interface in situations where interrupts are disabled. It is used for | |
2843 | * specific in-kernel networking tasks, such as remote consoles and kernel | |
2844 | * debugging over the network (example netdump in RedHat). | |
612eff0e | 2845 | */ |
612eff0e BH |
2846 | static void s2io_netpoll(struct net_device *dev) |
2847 | { | |
4cf1653a | 2848 | struct s2io_nic *nic = netdev_priv(dev); |
80777c54 | 2849 | const int irq = nic->pdev->irq; |
1ee6dd77 | 2850 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
b41477f3 | 2851 | u64 val64 = 0xFFFFFFFFFFFFFFFFULL; |
612eff0e | 2852 | int i; |
ffb5df6c JP |
2853 | struct config_param *config = &nic->config; |
2854 | struct mac_info *mac_control = &nic->mac_control; | |
612eff0e | 2855 | |
d796fdb7 LV |
2856 | if (pci_channel_offline(nic->pdev)) |
2857 | return; | |
2858 | ||
80777c54 | 2859 | disable_irq(irq); |
612eff0e | 2860 | |
612eff0e | 2861 | writeq(val64, &bar0->rx_traffic_int); |
b41477f3 AR |
2862 | writeq(val64, &bar0->tx_traffic_int); |
2863 | ||
6aa20a22 | 2864 | /* we need to free up the transmitted skbufs or else netpoll will |
b41477f3 AR |
2865 | * run out of skbs and will fail and eventually netpoll application such |
2866 | * as netdump will fail. | |
2867 | */ | |
2868 | for (i = 0; i < config->tx_fifo_num; i++) | |
2869 | tx_intr_handler(&mac_control->fifos[i]); | |
612eff0e | 2870 | |
b41477f3 | 2871 | /* check for received packet and indicate up to network */ |
13d866a9 JP |
2872 | for (i = 0; i < config->rx_ring_num; i++) { |
2873 | struct ring_info *ring = &mac_control->rings[i]; | |
2874 | ||
2875 | rx_intr_handler(ring, 0); | |
2876 | } | |
612eff0e BH |
2877 | |
2878 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
2879 | struct ring_info *ring = &mac_control->rings[i]; |
2880 | ||
2881 | if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) { | |
9e39f7c5 JP |
2882 | DBG_PRINT(INFO_DBG, |
2883 | "%s: Out of memory in Rx Netpoll!!\n", | |
2884 | dev->name); | |
612eff0e BH |
2885 | break; |
2886 | } | |
2887 | } | |
80777c54 | 2888 | enable_irq(irq); |
612eff0e BH |
2889 | } |
2890 | #endif | |
2891 | ||
20346722 | 2892 | /** |
1da177e4 | 2893 | * rx_intr_handler - Rx interrupt handler |
f61e0a35 SH |
2894 | * @ring_info: per ring structure. |
2895 | * @budget: budget for napi processing. | |
20346722 K |
2896 | * Description: |
2897 | * If the interrupt is because of a received frame or if the | |
1da177e4 | 2898 | * receive ring contains fresh as yet un-processed frames,this function is |
20346722 K |
2899 | * called. It picks out the RxD at which place the last Rx processing had |
2900 | * stopped and sends the skb to the OSM's Rx handler and then increments | |
1da177e4 LT |
2901 | * the offset. |
2902 | * Return Value: | |
f61e0a35 | 2903 | * No. of napi packets processed. |
1da177e4 | 2904 | */ |
f61e0a35 | 2905 | static int rx_intr_handler(struct ring_info *ring_data, int budget) |
1da177e4 | 2906 | { |
c9fcbf47 | 2907 | int get_block, put_block; |
1ee6dd77 RB |
2908 | struct rx_curr_get_info get_info, put_info; |
2909 | struct RxD_t *rxdp; | |
1da177e4 | 2910 | struct sk_buff *skb; |
f61e0a35 | 2911 | int pkt_cnt = 0, napi_pkts = 0; |
7d3d0439 | 2912 | int i; |
d44570e4 JP |
2913 | struct RxD1 *rxdp1; |
2914 | struct RxD3 *rxdp3; | |
7d3d0439 | 2915 | |
20346722 K |
2916 | get_info = ring_data->rx_curr_get_info; |
2917 | get_block = get_info.block_index; | |
1ee6dd77 | 2918 | memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info)); |
20346722 | 2919 | put_block = put_info.block_index; |
da6971d8 | 2920 | rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr; |
db874e65 | 2921 | |
da6971d8 | 2922 | while (RXD_IS_UP2DT(rxdp)) { |
db874e65 SS |
2923 | /* |
2924 | * If your are next to put index then it's | |
2925 | * FIFO full condition | |
2926 | */ | |
da6971d8 AR |
2927 | if ((get_block == put_block) && |
2928 | (get_info.offset + 1) == put_info.offset) { | |
0425b46a | 2929 | DBG_PRINT(INTR_DBG, "%s: Ring Full\n", |
d44570e4 | 2930 | ring_data->dev->name); |
da6971d8 AR |
2931 | break; |
2932 | } | |
d44570e4 | 2933 | skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control); |
20346722 | 2934 | if (skb == NULL) { |
9e39f7c5 | 2935 | DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n", |
0425b46a | 2936 | ring_data->dev->name); |
f61e0a35 | 2937 | return 0; |
1da177e4 | 2938 | } |
0425b46a | 2939 | if (ring_data->rxd_mode == RXD_MODE_1) { |
d44570e4 | 2940 | rxdp1 = (struct RxD1 *)rxdp; |
0425b46a | 2941 | pci_unmap_single(ring_data->pdev, (dma_addr_t) |
d44570e4 JP |
2942 | rxdp1->Buffer0_ptr, |
2943 | ring_data->mtu + | |
2944 | HEADER_ETHERNET_II_802_3_SIZE + | |
2945 | HEADER_802_2_SIZE + | |
2946 | HEADER_SNAP_SIZE, | |
2947 | PCI_DMA_FROMDEVICE); | |
0425b46a | 2948 | } else if (ring_data->rxd_mode == RXD_MODE_3B) { |
d44570e4 JP |
2949 | rxdp3 = (struct RxD3 *)rxdp; |
2950 | pci_dma_sync_single_for_cpu(ring_data->pdev, | |
2951 | (dma_addr_t)rxdp3->Buffer0_ptr, | |
2952 | BUF0_LEN, | |
2953 | PCI_DMA_FROMDEVICE); | |
2954 | pci_unmap_single(ring_data->pdev, | |
2955 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
2956 | ring_data->mtu + 4, | |
2957 | PCI_DMA_FROMDEVICE); | |
da6971d8 | 2958 | } |
863c11a9 | 2959 | prefetch(skb->data); |
20346722 K |
2960 | rx_osm_handler(ring_data, rxdp); |
2961 | get_info.offset++; | |
da6971d8 AR |
2962 | ring_data->rx_curr_get_info.offset = get_info.offset; |
2963 | rxdp = ring_data->rx_blocks[get_block]. | |
d44570e4 | 2964 | rxds[get_info.offset].virt_addr; |
0425b46a | 2965 | if (get_info.offset == rxd_count[ring_data->rxd_mode]) { |
20346722 | 2966 | get_info.offset = 0; |
da6971d8 | 2967 | ring_data->rx_curr_get_info.offset = get_info.offset; |
20346722 | 2968 | get_block++; |
da6971d8 AR |
2969 | if (get_block == ring_data->block_count) |
2970 | get_block = 0; | |
2971 | ring_data->rx_curr_get_info.block_index = get_block; | |
20346722 K |
2972 | rxdp = ring_data->rx_blocks[get_block].block_virt_addr; |
2973 | } | |
1da177e4 | 2974 | |
f61e0a35 SH |
2975 | if (ring_data->nic->config.napi) { |
2976 | budget--; | |
2977 | napi_pkts++; | |
2978 | if (!budget) | |
0425b46a SH |
2979 | break; |
2980 | } | |
20346722 | 2981 | pkt_cnt++; |
1da177e4 LT |
2982 | if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) |
2983 | break; | |
2984 | } | |
0425b46a | 2985 | if (ring_data->lro) { |
7d3d0439 | 2986 | /* Clear all LRO sessions before exiting */ |
d44570e4 | 2987 | for (i = 0; i < MAX_LRO_SESSIONS; i++) { |
0425b46a | 2988 | struct lro *lro = &ring_data->lro0_n[i]; |
7d3d0439 | 2989 | if (lro->in_use) { |
0425b46a | 2990 | update_L3L4_header(ring_data->nic, lro); |
cdb5bf02 | 2991 | queue_rx_frame(lro->parent, lro->vlan_tag); |
7d3d0439 RA |
2992 | clear_lro_session(lro); |
2993 | } | |
2994 | } | |
2995 | } | |
d44570e4 | 2996 | return napi_pkts; |
1da177e4 | 2997 | } |
20346722 K |
2998 | |
2999 | /** | |
1da177e4 LT |
3000 | * tx_intr_handler - Transmit interrupt handler |
3001 | * @nic : device private variable | |
20346722 K |
3002 | * Description: |
3003 | * If an interrupt was raised to indicate DMA complete of the | |
3004 | * Tx packet, this function is called. It identifies the last TxD | |
3005 | * whose buffer was freed and frees all skbs whose data have already | |
1da177e4 LT |
3006 | * DMA'ed into the NICs internal memory. |
3007 | * Return Value: | |
3008 | * NONE | |
3009 | */ | |
3010 | ||
1ee6dd77 | 3011 | static void tx_intr_handler(struct fifo_info *fifo_data) |
1da177e4 | 3012 | { |
1ee6dd77 | 3013 | struct s2io_nic *nic = fifo_data->nic; |
1ee6dd77 | 3014 | struct tx_curr_get_info get_info, put_info; |
3a3d5756 | 3015 | struct sk_buff *skb = NULL; |
1ee6dd77 | 3016 | struct TxD *txdlp; |
3a3d5756 | 3017 | int pkt_cnt = 0; |
2fda096d | 3018 | unsigned long flags = 0; |
f9046eb3 | 3019 | u8 err_mask; |
ffb5df6c JP |
3020 | struct stat_block *stats = nic->mac_control.stats_info; |
3021 | struct swStat *swstats = &stats->sw_stat; | |
1da177e4 | 3022 | |
2fda096d | 3023 | if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags)) |
d44570e4 | 3024 | return; |
2fda096d | 3025 | |
20346722 | 3026 | get_info = fifo_data->tx_curr_get_info; |
1ee6dd77 | 3027 | memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info)); |
43d620c8 | 3028 | txdlp = fifo_data->list_info[get_info.offset].list_virt_addr; |
20346722 K |
3029 | while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && |
3030 | (get_info.offset != put_info.offset) && | |
3031 | (txdlp->Host_Control)) { | |
3032 | /* Check for TxD errors */ | |
3033 | if (txdlp->Control_1 & TXD_T_CODE) { | |
3034 | unsigned long long err; | |
3035 | err = txdlp->Control_1 & TXD_T_CODE; | |
bd1034f0 | 3036 | if (err & 0x1) { |
ffb5df6c | 3037 | swstats->parity_err_cnt++; |
bd1034f0 | 3038 | } |
491976b2 SH |
3039 | |
3040 | /* update t_code statistics */ | |
f9046eb3 | 3041 | err_mask = err >> 48; |
d44570e4 JP |
3042 | switch (err_mask) { |
3043 | case 2: | |
ffb5df6c | 3044 | swstats->tx_buf_abort_cnt++; |
491976b2 SH |
3045 | break; |
3046 | ||
d44570e4 | 3047 | case 3: |
ffb5df6c | 3048 | swstats->tx_desc_abort_cnt++; |
491976b2 SH |
3049 | break; |
3050 | ||
d44570e4 | 3051 | case 7: |
ffb5df6c | 3052 | swstats->tx_parity_err_cnt++; |
491976b2 SH |
3053 | break; |
3054 | ||
d44570e4 | 3055 | case 10: |
ffb5df6c | 3056 | swstats->tx_link_loss_cnt++; |
491976b2 SH |
3057 | break; |
3058 | ||
d44570e4 | 3059 | case 15: |
ffb5df6c | 3060 | swstats->tx_list_proc_err_cnt++; |
491976b2 | 3061 | break; |
d44570e4 | 3062 | } |
20346722 | 3063 | } |
1da177e4 | 3064 | |
fed5eccd | 3065 | skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset); |
20346722 | 3066 | if (skb == NULL) { |
2fda096d | 3067 | spin_unlock_irqrestore(&fifo_data->tx_lock, flags); |
9e39f7c5 JP |
3068 | DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n", |
3069 | __func__); | |
20346722 K |
3070 | return; |
3071 | } | |
3a3d5756 | 3072 | pkt_cnt++; |
20346722 | 3073 | |
20346722 | 3074 | /* Updating the statistics block */ |
ffb5df6c | 3075 | swstats->mem_freed += skb->truesize; |
20346722 K |
3076 | dev_kfree_skb_irq(skb); |
3077 | ||
3078 | get_info.offset++; | |
863c11a9 AR |
3079 | if (get_info.offset == get_info.fifo_len + 1) |
3080 | get_info.offset = 0; | |
43d620c8 | 3081 | txdlp = fifo_data->list_info[get_info.offset].list_virt_addr; |
d44570e4 | 3082 | fifo_data->tx_curr_get_info.offset = get_info.offset; |
1da177e4 LT |
3083 | } |
3084 | ||
3a3d5756 | 3085 | s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq); |
2fda096d SR |
3086 | |
3087 | spin_unlock_irqrestore(&fifo_data->tx_lock, flags); | |
1da177e4 LT |
3088 | } |
3089 | ||
bd1034f0 AR |
3090 | /** |
3091 | * s2io_mdio_write - Function to write in to MDIO registers | |
3092 | * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS) | |
3093 | * @addr : address value | |
3094 | * @value : data value | |
3095 | * @dev : pointer to net_device structure | |
3096 | * Description: | |
3097 | * This function is used to write values to the MDIO registers | |
3098 | * NONE | |
3099 | */ | |
d44570e4 JP |
3100 | static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, |
3101 | struct net_device *dev) | |
bd1034f0 | 3102 | { |
d44570e4 | 3103 | u64 val64; |
4cf1653a | 3104 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 3105 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
bd1034f0 | 3106 | |
d44570e4 JP |
3107 | /* address transaction */ |
3108 | val64 = MDIO_MMD_INDX_ADDR(addr) | | |
3109 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3110 | MDIO_MMS_PRT_ADDR(0x0); | |
bd1034f0 AR |
3111 | writeq(val64, &bar0->mdio_control); |
3112 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3113 | writeq(val64, &bar0->mdio_control); | |
3114 | udelay(100); | |
3115 | ||
d44570e4 JP |
3116 | /* Data transaction */ |
3117 | val64 = MDIO_MMD_INDX_ADDR(addr) | | |
3118 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3119 | MDIO_MMS_PRT_ADDR(0x0) | | |
3120 | MDIO_MDIO_DATA(value) | | |
3121 | MDIO_OP(MDIO_OP_WRITE_TRANS); | |
bd1034f0 AR |
3122 | writeq(val64, &bar0->mdio_control); |
3123 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3124 | writeq(val64, &bar0->mdio_control); | |
3125 | udelay(100); | |
3126 | ||
d44570e4 JP |
3127 | val64 = MDIO_MMD_INDX_ADDR(addr) | |
3128 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3129 | MDIO_MMS_PRT_ADDR(0x0) | | |
3130 | MDIO_OP(MDIO_OP_READ_TRANS); | |
bd1034f0 AR |
3131 | writeq(val64, &bar0->mdio_control); |
3132 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3133 | writeq(val64, &bar0->mdio_control); | |
3134 | udelay(100); | |
bd1034f0 AR |
3135 | } |
3136 | ||
3137 | /** | |
3138 | * s2io_mdio_read - Function to write in to MDIO registers | |
3139 | * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS) | |
3140 | * @addr : address value | |
3141 | * @dev : pointer to net_device structure | |
3142 | * Description: | |
3143 | * This function is used to read values to the MDIO registers | |
3144 | * NONE | |
3145 | */ | |
3146 | static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev) | |
3147 | { | |
3148 | u64 val64 = 0x0; | |
3149 | u64 rval64 = 0x0; | |
4cf1653a | 3150 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 3151 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
bd1034f0 AR |
3152 | |
3153 | /* address transaction */ | |
d44570e4 JP |
3154 | val64 = val64 | (MDIO_MMD_INDX_ADDR(addr) |
3155 | | MDIO_MMD_DEV_ADDR(mmd_type) | |
3156 | | MDIO_MMS_PRT_ADDR(0x0)); | |
bd1034f0 AR |
3157 | writeq(val64, &bar0->mdio_control); |
3158 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3159 | writeq(val64, &bar0->mdio_control); | |
3160 | udelay(100); | |
3161 | ||
3162 | /* Data transaction */ | |
d44570e4 JP |
3163 | val64 = MDIO_MMD_INDX_ADDR(addr) | |
3164 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3165 | MDIO_MMS_PRT_ADDR(0x0) | | |
3166 | MDIO_OP(MDIO_OP_READ_TRANS); | |
bd1034f0 AR |
3167 | writeq(val64, &bar0->mdio_control); |
3168 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3169 | writeq(val64, &bar0->mdio_control); | |
3170 | udelay(100); | |
3171 | ||
3172 | /* Read the value from regs */ | |
3173 | rval64 = readq(&bar0->mdio_control); | |
3174 | rval64 = rval64 & 0xFFFF0000; | |
3175 | rval64 = rval64 >> 16; | |
3176 | return rval64; | |
3177 | } | |
d44570e4 | 3178 | |
bd1034f0 AR |
3179 | /** |
3180 | * s2io_chk_xpak_counter - Function to check the status of the xpak counters | |
fbfecd37 | 3181 | * @counter : counter value to be updated |
bd1034f0 AR |
3182 | * @flag : flag to indicate the status |
3183 | * @type : counter type | |
3184 | * Description: | |
3185 | * This function is to check the status of the xpak counters value | |
3186 | * NONE | |
3187 | */ | |
3188 | ||
d44570e4 JP |
3189 | static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, |
3190 | u16 flag, u16 type) | |
bd1034f0 AR |
3191 | { |
3192 | u64 mask = 0x3; | |
3193 | u64 val64; | |
3194 | int i; | |
d44570e4 | 3195 | for (i = 0; i < index; i++) |
bd1034f0 AR |
3196 | mask = mask << 0x2; |
3197 | ||
d44570e4 | 3198 | if (flag > 0) { |
bd1034f0 AR |
3199 | *counter = *counter + 1; |
3200 | val64 = *regs_stat & mask; | |
3201 | val64 = val64 >> (index * 0x2); | |
3202 | val64 = val64 + 1; | |
d44570e4 JP |
3203 | if (val64 == 3) { |
3204 | switch (type) { | |
bd1034f0 | 3205 | case 1: |
9e39f7c5 JP |
3206 | DBG_PRINT(ERR_DBG, |
3207 | "Take Xframe NIC out of service.\n"); | |
3208 | DBG_PRINT(ERR_DBG, | |
3209 | "Excessive temperatures may result in premature transceiver failure.\n"); | |
d44570e4 | 3210 | break; |
bd1034f0 | 3211 | case 2: |
9e39f7c5 JP |
3212 | DBG_PRINT(ERR_DBG, |
3213 | "Take Xframe NIC out of service.\n"); | |
3214 | DBG_PRINT(ERR_DBG, | |
3215 | "Excessive bias currents may indicate imminent laser diode failure.\n"); | |
d44570e4 | 3216 | break; |
bd1034f0 | 3217 | case 3: |
9e39f7c5 JP |
3218 | DBG_PRINT(ERR_DBG, |
3219 | "Take Xframe NIC out of service.\n"); | |
3220 | DBG_PRINT(ERR_DBG, | |
3221 | "Excessive laser output power may saturate far-end receiver.\n"); | |
d44570e4 | 3222 | break; |
bd1034f0 | 3223 | default: |
d44570e4 JP |
3224 | DBG_PRINT(ERR_DBG, |
3225 | "Incorrect XPAK Alarm type\n"); | |
bd1034f0 AR |
3226 | } |
3227 | val64 = 0x0; | |
3228 | } | |
3229 | val64 = val64 << (index * 0x2); | |
3230 | *regs_stat = (*regs_stat & (~mask)) | (val64); | |
3231 | ||
3232 | } else { | |
3233 | *regs_stat = *regs_stat & (~mask); | |
3234 | } | |
3235 | } | |
3236 | ||
3237 | /** | |
3238 | * s2io_updt_xpak_counter - Function to update the xpak counters | |
3239 | * @dev : pointer to net_device struct | |
3240 | * Description: | |
3241 | * This function is to upate the status of the xpak counters value | |
3242 | * NONE | |
3243 | */ | |
3244 | static void s2io_updt_xpak_counter(struct net_device *dev) | |
3245 | { | |
3246 | u16 flag = 0x0; | |
3247 | u16 type = 0x0; | |
3248 | u16 val16 = 0x0; | |
3249 | u64 val64 = 0x0; | |
3250 | u64 addr = 0x0; | |
3251 | ||
4cf1653a | 3252 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c JP |
3253 | struct stat_block *stats = sp->mac_control.stats_info; |
3254 | struct xpakStat *xstats = &stats->xpak_stat; | |
bd1034f0 AR |
3255 | |
3256 | /* Check the communication with the MDIO slave */ | |
40239396 | 3257 | addr = MDIO_CTRL1; |
bd1034f0 | 3258 | val64 = 0x0; |
40239396 | 3259 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); |
d44570e4 | 3260 | if ((val64 == 0xFFFF) || (val64 == 0x0000)) { |
9e39f7c5 JP |
3261 | DBG_PRINT(ERR_DBG, |
3262 | "ERR: MDIO slave access failed - Returned %llx\n", | |
3263 | (unsigned long long)val64); | |
bd1034f0 AR |
3264 | return; |
3265 | } | |
3266 | ||
40239396 | 3267 | /* Check for the expected value of control reg 1 */ |
d44570e4 | 3268 | if (val64 != MDIO_CTRL1_SPEED10G) { |
9e39f7c5 JP |
3269 | DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - " |
3270 | "Returned: %llx- Expected: 0x%x\n", | |
40239396 | 3271 | (unsigned long long)val64, MDIO_CTRL1_SPEED10G); |
bd1034f0 AR |
3272 | return; |
3273 | } | |
3274 | ||
3275 | /* Loading the DOM register to MDIO register */ | |
3276 | addr = 0xA100; | |
40239396 BH |
3277 | s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev); |
3278 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); | |
bd1034f0 AR |
3279 | |
3280 | /* Reading the Alarm flags */ | |
3281 | addr = 0xA070; | |
3282 | val64 = 0x0; | |
40239396 | 3283 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); |
bd1034f0 AR |
3284 | |
3285 | flag = CHECKBIT(val64, 0x7); | |
3286 | type = 1; | |
ffb5df6c JP |
3287 | s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high, |
3288 | &xstats->xpak_regs_stat, | |
d44570e4 | 3289 | 0x0, flag, type); |
bd1034f0 | 3290 | |
d44570e4 | 3291 | if (CHECKBIT(val64, 0x6)) |
ffb5df6c | 3292 | xstats->alarm_transceiver_temp_low++; |
bd1034f0 AR |
3293 | |
3294 | flag = CHECKBIT(val64, 0x3); | |
3295 | type = 2; | |
ffb5df6c JP |
3296 | s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high, |
3297 | &xstats->xpak_regs_stat, | |
d44570e4 | 3298 | 0x2, flag, type); |
bd1034f0 | 3299 | |
d44570e4 | 3300 | if (CHECKBIT(val64, 0x2)) |
ffb5df6c | 3301 | xstats->alarm_laser_bias_current_low++; |
bd1034f0 AR |
3302 | |
3303 | flag = CHECKBIT(val64, 0x1); | |
3304 | type = 3; | |
ffb5df6c JP |
3305 | s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high, |
3306 | &xstats->xpak_regs_stat, | |
d44570e4 | 3307 | 0x4, flag, type); |
bd1034f0 | 3308 | |
d44570e4 | 3309 | if (CHECKBIT(val64, 0x0)) |
ffb5df6c | 3310 | xstats->alarm_laser_output_power_low++; |
bd1034f0 AR |
3311 | |
3312 | /* Reading the Warning flags */ | |
3313 | addr = 0xA074; | |
3314 | val64 = 0x0; | |
40239396 | 3315 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); |
bd1034f0 | 3316 | |
d44570e4 | 3317 | if (CHECKBIT(val64, 0x7)) |
ffb5df6c | 3318 | xstats->warn_transceiver_temp_high++; |
bd1034f0 | 3319 | |
d44570e4 | 3320 | if (CHECKBIT(val64, 0x6)) |
ffb5df6c | 3321 | xstats->warn_transceiver_temp_low++; |
bd1034f0 | 3322 | |
d44570e4 | 3323 | if (CHECKBIT(val64, 0x3)) |
ffb5df6c | 3324 | xstats->warn_laser_bias_current_high++; |
bd1034f0 | 3325 | |
d44570e4 | 3326 | if (CHECKBIT(val64, 0x2)) |
ffb5df6c | 3327 | xstats->warn_laser_bias_current_low++; |
bd1034f0 | 3328 | |
d44570e4 | 3329 | if (CHECKBIT(val64, 0x1)) |
ffb5df6c | 3330 | xstats->warn_laser_output_power_high++; |
bd1034f0 | 3331 | |
d44570e4 | 3332 | if (CHECKBIT(val64, 0x0)) |
ffb5df6c | 3333 | xstats->warn_laser_output_power_low++; |
bd1034f0 AR |
3334 | } |
3335 | ||
20346722 | 3336 | /** |
1da177e4 | 3337 | * wait_for_cmd_complete - waits for a command to complete. |
20346722 | 3338 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 | 3339 | * s2io_nic structure. |
20346722 K |
3340 | * Description: Function that waits for a command to Write into RMAC |
3341 | * ADDR DATA registers to be completed and returns either success or | |
3342 | * error depending on whether the command was complete or not. | |
1da177e4 LT |
3343 | * Return value: |
3344 | * SUCCESS on success and FAILURE on failure. | |
3345 | */ | |
3346 | ||
9fc93a41 | 3347 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, |
d44570e4 | 3348 | int bit_state) |
1da177e4 | 3349 | { |
9fc93a41 | 3350 | int ret = FAILURE, cnt = 0, delay = 1; |
1da177e4 LT |
3351 | u64 val64; |
3352 | ||
9fc93a41 SS |
3353 | if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET)) |
3354 | return FAILURE; | |
3355 | ||
3356 | do { | |
c92ca04b | 3357 | val64 = readq(addr); |
9fc93a41 SS |
3358 | if (bit_state == S2IO_BIT_RESET) { |
3359 | if (!(val64 & busy_bit)) { | |
3360 | ret = SUCCESS; | |
3361 | break; | |
3362 | } | |
3363 | } else { | |
2d146eb1 | 3364 | if (val64 & busy_bit) { |
9fc93a41 SS |
3365 | ret = SUCCESS; |
3366 | break; | |
3367 | } | |
1da177e4 | 3368 | } |
c92ca04b | 3369 | |
d44570e4 | 3370 | if (in_interrupt()) |
9fc93a41 | 3371 | mdelay(delay); |
c92ca04b | 3372 | else |
9fc93a41 | 3373 | msleep(delay); |
c92ca04b | 3374 | |
9fc93a41 SS |
3375 | if (++cnt >= 10) |
3376 | delay = 50; | |
3377 | } while (cnt < 20); | |
1da177e4 LT |
3378 | return ret; |
3379 | } | |
19a60522 SS |
3380 | /* |
3381 | * check_pci_device_id - Checks if the device id is supported | |
3382 | * @id : device id | |
3383 | * Description: Function to check if the pci device id is supported by driver. | |
3384 | * Return value: Actual device id if supported else PCI_ANY_ID | |
3385 | */ | |
3386 | static u16 check_pci_device_id(u16 id) | |
3387 | { | |
3388 | switch (id) { | |
3389 | case PCI_DEVICE_ID_HERC_WIN: | |
3390 | case PCI_DEVICE_ID_HERC_UNI: | |
3391 | return XFRAME_II_DEVICE; | |
3392 | case PCI_DEVICE_ID_S2IO_UNI: | |
3393 | case PCI_DEVICE_ID_S2IO_WIN: | |
3394 | return XFRAME_I_DEVICE; | |
3395 | default: | |
3396 | return PCI_ANY_ID; | |
3397 | } | |
3398 | } | |
1da177e4 | 3399 | |
20346722 K |
3400 | /** |
3401 | * s2io_reset - Resets the card. | |
1da177e4 LT |
3402 | * @sp : private member of the device structure. |
3403 | * Description: Function to Reset the card. This function then also | |
20346722 | 3404 | * restores the previously saved PCI configuration space registers as |
1da177e4 LT |
3405 | * the card reset also resets the configuration space. |
3406 | * Return value: | |
3407 | * void. | |
3408 | */ | |
3409 | ||
d44570e4 | 3410 | static void s2io_reset(struct s2io_nic *sp) |
1da177e4 | 3411 | { |
1ee6dd77 | 3412 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 3413 | u64 val64; |
5e25b9dd | 3414 | u16 subid, pci_cmd; |
19a60522 SS |
3415 | int i; |
3416 | u16 val16; | |
491976b2 SH |
3417 | unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt; |
3418 | unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt; | |
ffb5df6c JP |
3419 | struct stat_block *stats; |
3420 | struct swStat *swstats; | |
491976b2 | 3421 | |
9e39f7c5 | 3422 | DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n", |
3a22813a | 3423 | __func__, pci_name(sp->pdev)); |
1da177e4 | 3424 | |
0b1f7ebe | 3425 | /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ |
e960fc5c | 3426 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); |
0b1f7ebe | 3427 | |
1da177e4 LT |
3428 | val64 = SW_RESET_ALL; |
3429 | writeq(val64, &bar0->sw_reset); | |
d44570e4 | 3430 | if (strstr(sp->product_name, "CX4")) |
c92ca04b | 3431 | msleep(750); |
19a60522 SS |
3432 | msleep(250); |
3433 | for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) { | |
1da177e4 | 3434 | |
19a60522 SS |
3435 | /* Restore the PCI state saved during initialization. */ |
3436 | pci_restore_state(sp->pdev); | |
b8a623bf | 3437 | pci_save_state(sp->pdev); |
19a60522 SS |
3438 | pci_read_config_word(sp->pdev, 0x2, &val16); |
3439 | if (check_pci_device_id(val16) != (u16)PCI_ANY_ID) | |
3440 | break; | |
3441 | msleep(200); | |
3442 | } | |
1da177e4 | 3443 | |
d44570e4 JP |
3444 | if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) |
3445 | DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__); | |
19a60522 SS |
3446 | |
3447 | pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd); | |
3448 | ||
3449 | s2io_init_pci(sp); | |
1da177e4 | 3450 | |
20346722 K |
3451 | /* Set swapper to enable I/O register access */ |
3452 | s2io_set_swapper(sp); | |
3453 | ||
faa4f796 SH |
3454 | /* restore mac_addr entries */ |
3455 | do_s2io_restore_unicast_mc(sp); | |
3456 | ||
cc6e7c44 RA |
3457 | /* Restore the MSIX table entries from local variables */ |
3458 | restore_xmsi_data(sp); | |
3459 | ||
5e25b9dd | 3460 | /* Clear certain PCI/PCI-X fields after reset */ |
303bcb4b | 3461 | if (sp->device_type == XFRAME_II_DEVICE) { |
b41477f3 | 3462 | /* Clear "detected parity error" bit */ |
303bcb4b | 3463 | pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000); |
5e25b9dd | 3464 | |
303bcb4b K |
3465 | /* Clearing PCIX Ecc status register */ |
3466 | pci_write_config_dword(sp->pdev, 0x68, 0x7C); | |
5e25b9dd | 3467 | |
303bcb4b | 3468 | /* Clearing PCI_STATUS error reflected here */ |
b7b5a128 | 3469 | writeq(s2BIT(62), &bar0->txpic_int_reg); |
303bcb4b | 3470 | } |
5e25b9dd | 3471 | |
20346722 | 3472 | /* Reset device statistics maintained by OS */ |
d44570e4 | 3473 | memset(&sp->stats, 0, sizeof(struct net_device_stats)); |
8a4bdbaa | 3474 | |
ffb5df6c JP |
3475 | stats = sp->mac_control.stats_info; |
3476 | swstats = &stats->sw_stat; | |
3477 | ||
491976b2 | 3478 | /* save link up/down time/cnt, reset/memory/watchdog cnt */ |
ffb5df6c JP |
3479 | up_cnt = swstats->link_up_cnt; |
3480 | down_cnt = swstats->link_down_cnt; | |
3481 | up_time = swstats->link_up_time; | |
3482 | down_time = swstats->link_down_time; | |
3483 | reset_cnt = swstats->soft_reset_cnt; | |
3484 | mem_alloc_cnt = swstats->mem_allocated; | |
3485 | mem_free_cnt = swstats->mem_freed; | |
3486 | watchdog_cnt = swstats->watchdog_timer_cnt; | |
3487 | ||
3488 | memset(stats, 0, sizeof(struct stat_block)); | |
3489 | ||
491976b2 | 3490 | /* restore link up/down time/cnt, reset/memory/watchdog cnt */ |
ffb5df6c JP |
3491 | swstats->link_up_cnt = up_cnt; |
3492 | swstats->link_down_cnt = down_cnt; | |
3493 | swstats->link_up_time = up_time; | |
3494 | swstats->link_down_time = down_time; | |
3495 | swstats->soft_reset_cnt = reset_cnt; | |
3496 | swstats->mem_allocated = mem_alloc_cnt; | |
3497 | swstats->mem_freed = mem_free_cnt; | |
3498 | swstats->watchdog_timer_cnt = watchdog_cnt; | |
20346722 | 3499 | |
1da177e4 LT |
3500 | /* SXE-002: Configure link and activity LED to turn it off */ |
3501 | subid = sp->pdev->subsystem_device; | |
541ae68f K |
3502 | if (((subid & 0xFF) >= 0x07) && |
3503 | (sp->device_type == XFRAME_I_DEVICE)) { | |
1da177e4 LT |
3504 | val64 = readq(&bar0->gpio_control); |
3505 | val64 |= 0x0000800000000000ULL; | |
3506 | writeq(val64, &bar0->gpio_control); | |
3507 | val64 = 0x0411040400000000ULL; | |
509a2671 | 3508 | writeq(val64, (void __iomem *)bar0 + 0x2700); |
1da177e4 LT |
3509 | } |
3510 | ||
541ae68f | 3511 | /* |
25985edc | 3512 | * Clear spurious ECC interrupts that would have occurred on |
541ae68f K |
3513 | * XFRAME II cards after reset. |
3514 | */ | |
3515 | if (sp->device_type == XFRAME_II_DEVICE) { | |
3516 | val64 = readq(&bar0->pcc_err_reg); | |
3517 | writeq(val64, &bar0->pcc_err_reg); | |
3518 | } | |
3519 | ||
f957bcf0 | 3520 | sp->device_enabled_once = false; |
1da177e4 LT |
3521 | } |
3522 | ||
3523 | /** | |
20346722 K |
3524 | * s2io_set_swapper - to set the swapper controle on the card |
3525 | * @sp : private member of the device structure, | |
1da177e4 | 3526 | * pointer to the s2io_nic structure. |
20346722 | 3527 | * Description: Function to set the swapper control on the card |
1da177e4 LT |
3528 | * correctly depending on the 'endianness' of the system. |
3529 | * Return value: | |
3530 | * SUCCESS on success and FAILURE on failure. | |
3531 | */ | |
3532 | ||
d44570e4 | 3533 | static int s2io_set_swapper(struct s2io_nic *sp) |
1da177e4 LT |
3534 | { |
3535 | struct net_device *dev = sp->dev; | |
1ee6dd77 | 3536 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
3537 | u64 val64, valt, valr; |
3538 | ||
20346722 | 3539 | /* |
1da177e4 LT |
3540 | * Set proper endian settings and verify the same by reading |
3541 | * the PIF Feed-back register. | |
3542 | */ | |
3543 | ||
3544 | val64 = readq(&bar0->pif_rd_swapper_fb); | |
3545 | if (val64 != 0x0123456789ABCDEFULL) { | |
3546 | int i = 0; | |
85a56498 JM |
3547 | static const u64 value[] = { |
3548 | 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */ | |
3549 | 0x8100008181000081ULL, /* FE=1, SE=0 */ | |
3550 | 0x4200004242000042ULL, /* FE=0, SE=1 */ | |
3551 | 0 /* FE=0, SE=0 */ | |
3552 | }; | |
1da177e4 | 3553 | |
d44570e4 | 3554 | while (i < 4) { |
1da177e4 LT |
3555 | writeq(value[i], &bar0->swapper_ctrl); |
3556 | val64 = readq(&bar0->pif_rd_swapper_fb); | |
3557 | if (val64 == 0x0123456789ABCDEFULL) | |
3558 | break; | |
3559 | i++; | |
3560 | } | |
3561 | if (i == 4) { | |
9e39f7c5 JP |
3562 | DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, " |
3563 | "feedback read %llx\n", | |
3564 | dev->name, (unsigned long long)val64); | |
1da177e4 LT |
3565 | return FAILURE; |
3566 | } | |
3567 | valr = value[i]; | |
3568 | } else { | |
3569 | valr = readq(&bar0->swapper_ctrl); | |
3570 | } | |
3571 | ||
3572 | valt = 0x0123456789ABCDEFULL; | |
3573 | writeq(valt, &bar0->xmsi_address); | |
3574 | val64 = readq(&bar0->xmsi_address); | |
3575 | ||
d44570e4 | 3576 | if (val64 != valt) { |
1da177e4 | 3577 | int i = 0; |
85a56498 JM |
3578 | static const u64 value[] = { |
3579 | 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */ | |
3580 | 0x0081810000818100ULL, /* FE=1, SE=0 */ | |
3581 | 0x0042420000424200ULL, /* FE=0, SE=1 */ | |
3582 | 0 /* FE=0, SE=0 */ | |
3583 | }; | |
1da177e4 | 3584 | |
d44570e4 | 3585 | while (i < 4) { |
1da177e4 LT |
3586 | writeq((value[i] | valr), &bar0->swapper_ctrl); |
3587 | writeq(valt, &bar0->xmsi_address); | |
3588 | val64 = readq(&bar0->xmsi_address); | |
d44570e4 | 3589 | if (val64 == valt) |
1da177e4 LT |
3590 | break; |
3591 | i++; | |
3592 | } | |
d44570e4 | 3593 | if (i == 4) { |
20346722 | 3594 | unsigned long long x = val64; |
9e39f7c5 JP |
3595 | DBG_PRINT(ERR_DBG, |
3596 | "Write failed, Xmsi_addr reads:0x%llx\n", x); | |
1da177e4 LT |
3597 | return FAILURE; |
3598 | } | |
3599 | } | |
3600 | val64 = readq(&bar0->swapper_ctrl); | |
3601 | val64 &= 0xFFFF000000000000ULL; | |
3602 | ||
d44570e4 | 3603 | #ifdef __BIG_ENDIAN |
20346722 K |
3604 | /* |
3605 | * The device by default set to a big endian format, so a | |
1da177e4 LT |
3606 | * big endian driver need not set anything. |
3607 | */ | |
3608 | val64 |= (SWAPPER_CTRL_TXP_FE | | |
d44570e4 JP |
3609 | SWAPPER_CTRL_TXP_SE | |
3610 | SWAPPER_CTRL_TXD_R_FE | | |
3611 | SWAPPER_CTRL_TXD_W_FE | | |
3612 | SWAPPER_CTRL_TXF_R_FE | | |
3613 | SWAPPER_CTRL_RXD_R_FE | | |
3614 | SWAPPER_CTRL_RXD_W_FE | | |
3615 | SWAPPER_CTRL_RXF_W_FE | | |
3616 | SWAPPER_CTRL_XMSI_FE | | |
3617 | SWAPPER_CTRL_STATS_FE | | |
3618 | SWAPPER_CTRL_STATS_SE); | |
eaae7f72 | 3619 | if (sp->config.intr_type == INTA) |
cc6e7c44 | 3620 | val64 |= SWAPPER_CTRL_XMSI_SE; |
1da177e4 LT |
3621 | writeq(val64, &bar0->swapper_ctrl); |
3622 | #else | |
20346722 | 3623 | /* |
1da177e4 | 3624 | * Initially we enable all bits to make it accessible by the |
20346722 | 3625 | * driver, then we selectively enable only those bits that |
1da177e4 LT |
3626 | * we want to set. |
3627 | */ | |
3628 | val64 |= (SWAPPER_CTRL_TXP_FE | | |
d44570e4 JP |
3629 | SWAPPER_CTRL_TXP_SE | |
3630 | SWAPPER_CTRL_TXD_R_FE | | |
3631 | SWAPPER_CTRL_TXD_R_SE | | |
3632 | SWAPPER_CTRL_TXD_W_FE | | |
3633 | SWAPPER_CTRL_TXD_W_SE | | |
3634 | SWAPPER_CTRL_TXF_R_FE | | |
3635 | SWAPPER_CTRL_RXD_R_FE | | |
3636 | SWAPPER_CTRL_RXD_R_SE | | |
3637 | SWAPPER_CTRL_RXD_W_FE | | |
3638 | SWAPPER_CTRL_RXD_W_SE | | |
3639 | SWAPPER_CTRL_RXF_W_FE | | |
3640 | SWAPPER_CTRL_XMSI_FE | | |
3641 | SWAPPER_CTRL_STATS_FE | | |
3642 | SWAPPER_CTRL_STATS_SE); | |
eaae7f72 | 3643 | if (sp->config.intr_type == INTA) |
cc6e7c44 | 3644 | val64 |= SWAPPER_CTRL_XMSI_SE; |
1da177e4 LT |
3645 | writeq(val64, &bar0->swapper_ctrl); |
3646 | #endif | |
3647 | val64 = readq(&bar0->swapper_ctrl); | |
3648 | ||
20346722 K |
3649 | /* |
3650 | * Verifying if endian settings are accurate by reading a | |
1da177e4 LT |
3651 | * feedback register. |
3652 | */ | |
3653 | val64 = readq(&bar0->pif_rd_swapper_fb); | |
3654 | if (val64 != 0x0123456789ABCDEFULL) { | |
3655 | /* Endian settings are incorrect, calls for another dekko. */ | |
9e39f7c5 JP |
3656 | DBG_PRINT(ERR_DBG, |
3657 | "%s: Endian settings are wrong, feedback read %llx\n", | |
3658 | dev->name, (unsigned long long)val64); | |
1da177e4 LT |
3659 | return FAILURE; |
3660 | } | |
3661 | ||
3662 | return SUCCESS; | |
3663 | } | |
3664 | ||
1ee6dd77 | 3665 | static int wait_for_msix_trans(struct s2io_nic *nic, int i) |
cc6e7c44 | 3666 | { |
1ee6dd77 | 3667 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
cc6e7c44 RA |
3668 | u64 val64; |
3669 | int ret = 0, cnt = 0; | |
3670 | ||
3671 | do { | |
3672 | val64 = readq(&bar0->xmsi_access); | |
b7b5a128 | 3673 | if (!(val64 & s2BIT(15))) |
cc6e7c44 RA |
3674 | break; |
3675 | mdelay(1); | |
3676 | cnt++; | |
d44570e4 | 3677 | } while (cnt < 5); |
cc6e7c44 RA |
3678 | if (cnt == 5) { |
3679 | DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i); | |
3680 | ret = 1; | |
3681 | } | |
3682 | ||
3683 | return ret; | |
3684 | } | |
3685 | ||
1ee6dd77 | 3686 | static void restore_xmsi_data(struct s2io_nic *nic) |
cc6e7c44 | 3687 | { |
1ee6dd77 | 3688 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
cc6e7c44 | 3689 | u64 val64; |
f61e0a35 SH |
3690 | int i, msix_index; |
3691 | ||
f61e0a35 SH |
3692 | if (nic->device_type == XFRAME_I_DEVICE) |
3693 | return; | |
cc6e7c44 | 3694 | |
d44570e4 JP |
3695 | for (i = 0; i < MAX_REQUESTED_MSI_X; i++) { |
3696 | msix_index = (i) ? ((i-1) * 8 + 1) : 0; | |
cc6e7c44 RA |
3697 | writeq(nic->msix_info[i].addr, &bar0->xmsi_address); |
3698 | writeq(nic->msix_info[i].data, &bar0->xmsi_data); | |
f61e0a35 | 3699 | val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6)); |
cc6e7c44 | 3700 | writeq(val64, &bar0->xmsi_access); |
f61e0a35 | 3701 | if (wait_for_msix_trans(nic, msix_index)) { |
9e39f7c5 JP |
3702 | DBG_PRINT(ERR_DBG, "%s: index: %d failed\n", |
3703 | __func__, msix_index); | |
cc6e7c44 RA |
3704 | continue; |
3705 | } | |
3706 | } | |
3707 | } | |
3708 | ||
1ee6dd77 | 3709 | static void store_xmsi_data(struct s2io_nic *nic) |
cc6e7c44 | 3710 | { |
1ee6dd77 | 3711 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
cc6e7c44 | 3712 | u64 val64, addr, data; |
f61e0a35 SH |
3713 | int i, msix_index; |
3714 | ||
3715 | if (nic->device_type == XFRAME_I_DEVICE) | |
3716 | return; | |
cc6e7c44 RA |
3717 | |
3718 | /* Store and display */ | |
d44570e4 JP |
3719 | for (i = 0; i < MAX_REQUESTED_MSI_X; i++) { |
3720 | msix_index = (i) ? ((i-1) * 8 + 1) : 0; | |
f61e0a35 | 3721 | val64 = (s2BIT(15) | vBIT(msix_index, 26, 6)); |
cc6e7c44 | 3722 | writeq(val64, &bar0->xmsi_access); |
f61e0a35 | 3723 | if (wait_for_msix_trans(nic, msix_index)) { |
9e39f7c5 JP |
3724 | DBG_PRINT(ERR_DBG, "%s: index: %d failed\n", |
3725 | __func__, msix_index); | |
cc6e7c44 RA |
3726 | continue; |
3727 | } | |
3728 | addr = readq(&bar0->xmsi_address); | |
3729 | data = readq(&bar0->xmsi_data); | |
3730 | if (addr && data) { | |
3731 | nic->msix_info[i].addr = addr; | |
3732 | nic->msix_info[i].data = data; | |
3733 | } | |
3734 | } | |
3735 | } | |
3736 | ||
1ee6dd77 | 3737 | static int s2io_enable_msi_x(struct s2io_nic *nic) |
cc6e7c44 | 3738 | { |
1ee6dd77 | 3739 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
ac731ab6 | 3740 | u64 rx_mat; |
cc6e7c44 RA |
3741 | u16 msi_control; /* Temp variable */ |
3742 | int ret, i, j, msix_indx = 1; | |
4f870320 | 3743 | int size; |
ffb5df6c JP |
3744 | struct stat_block *stats = nic->mac_control.stats_info; |
3745 | struct swStat *swstats = &stats->sw_stat; | |
cc6e7c44 | 3746 | |
4f870320 | 3747 | size = nic->num_entries * sizeof(struct msix_entry); |
44364a03 | 3748 | nic->entries = kzalloc(size, GFP_KERNEL); |
bd684e43 | 3749 | if (!nic->entries) { |
d44570e4 JP |
3750 | DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", |
3751 | __func__); | |
ffb5df6c | 3752 | swstats->mem_alloc_fail_cnt++; |
cc6e7c44 RA |
3753 | return -ENOMEM; |
3754 | } | |
ffb5df6c | 3755 | swstats->mem_allocated += size; |
f61e0a35 | 3756 | |
4f870320 | 3757 | size = nic->num_entries * sizeof(struct s2io_msix_entry); |
44364a03 | 3758 | nic->s2io_entries = kzalloc(size, GFP_KERNEL); |
bd684e43 | 3759 | if (!nic->s2io_entries) { |
8a4bdbaa | 3760 | DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", |
d44570e4 | 3761 | __func__); |
ffb5df6c | 3762 | swstats->mem_alloc_fail_cnt++; |
cc6e7c44 | 3763 | kfree(nic->entries); |
ffb5df6c | 3764 | swstats->mem_freed |
f61e0a35 | 3765 | += (nic->num_entries * sizeof(struct msix_entry)); |
cc6e7c44 RA |
3766 | return -ENOMEM; |
3767 | } | |
ffb5df6c | 3768 | swstats->mem_allocated += size; |
cc6e7c44 | 3769 | |
ac731ab6 SH |
3770 | nic->entries[0].entry = 0; |
3771 | nic->s2io_entries[0].entry = 0; | |
3772 | nic->s2io_entries[0].in_use = MSIX_FLG; | |
3773 | nic->s2io_entries[0].type = MSIX_ALARM_TYPE; | |
3774 | nic->s2io_entries[0].arg = &nic->mac_control.fifos; | |
3775 | ||
f61e0a35 SH |
3776 | for (i = 1; i < nic->num_entries; i++) { |
3777 | nic->entries[i].entry = ((i - 1) * 8) + 1; | |
3778 | nic->s2io_entries[i].entry = ((i - 1) * 8) + 1; | |
cc6e7c44 RA |
3779 | nic->s2io_entries[i].arg = NULL; |
3780 | nic->s2io_entries[i].in_use = 0; | |
3781 | } | |
3782 | ||
8a4bdbaa | 3783 | rx_mat = readq(&bar0->rx_mat); |
f61e0a35 | 3784 | for (j = 0; j < nic->config.rx_ring_num; j++) { |
8a4bdbaa | 3785 | rx_mat |= RX_MAT_SET(j, msix_indx); |
f61e0a35 SH |
3786 | nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j]; |
3787 | nic->s2io_entries[j+1].type = MSIX_RING_TYPE; | |
3788 | nic->s2io_entries[j+1].in_use = MSIX_FLG; | |
3789 | msix_indx += 8; | |
cc6e7c44 | 3790 | } |
8a4bdbaa | 3791 | writeq(rx_mat, &bar0->rx_mat); |
f61e0a35 | 3792 | readq(&bar0->rx_mat); |
cc6e7c44 | 3793 | |
f61e0a35 | 3794 | ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries); |
c92ca04b | 3795 | /* We fail init if error or we get less vectors than min required */ |
cc6e7c44 | 3796 | if (ret) { |
9e39f7c5 | 3797 | DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n"); |
cc6e7c44 | 3798 | kfree(nic->entries); |
ffb5df6c JP |
3799 | swstats->mem_freed += nic->num_entries * |
3800 | sizeof(struct msix_entry); | |
cc6e7c44 | 3801 | kfree(nic->s2io_entries); |
ffb5df6c JP |
3802 | swstats->mem_freed += nic->num_entries * |
3803 | sizeof(struct s2io_msix_entry); | |
cc6e7c44 RA |
3804 | nic->entries = NULL; |
3805 | nic->s2io_entries = NULL; | |
3806 | return -ENOMEM; | |
3807 | } | |
3808 | ||
3809 | /* | |
3810 | * To enable MSI-X, MSI also needs to be enabled, due to a bug | |
3811 | * in the herc NIC. (Temp change, needs to be removed later) | |
3812 | */ | |
3813 | pci_read_config_word(nic->pdev, 0x42, &msi_control); | |
3814 | msi_control |= 0x1; /* Enable MSI */ | |
3815 | pci_write_config_word(nic->pdev, 0x42, msi_control); | |
3816 | ||
3817 | return 0; | |
3818 | } | |
3819 | ||
8abc4d5b | 3820 | /* Handle software interrupt used during MSI(X) test */ |
33390a70 | 3821 | static irqreturn_t s2io_test_intr(int irq, void *dev_id) |
8abc4d5b SS |
3822 | { |
3823 | struct s2io_nic *sp = dev_id; | |
3824 | ||
3825 | sp->msi_detected = 1; | |
3826 | wake_up(&sp->msi_wait); | |
3827 | ||
3828 | return IRQ_HANDLED; | |
3829 | } | |
3830 | ||
3831 | /* Test interrupt path by forcing a a software IRQ */ | |
33390a70 | 3832 | static int s2io_test_msi(struct s2io_nic *sp) |
8abc4d5b SS |
3833 | { |
3834 | struct pci_dev *pdev = sp->pdev; | |
3835 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
3836 | int err; | |
3837 | u64 val64, saved64; | |
3838 | ||
3839 | err = request_irq(sp->entries[1].vector, s2io_test_intr, 0, | |
d44570e4 | 3840 | sp->name, sp); |
8abc4d5b SS |
3841 | if (err) { |
3842 | DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n", | |
d44570e4 | 3843 | sp->dev->name, pci_name(pdev), pdev->irq); |
8abc4d5b SS |
3844 | return err; |
3845 | } | |
3846 | ||
d44570e4 | 3847 | init_waitqueue_head(&sp->msi_wait); |
8abc4d5b SS |
3848 | sp->msi_detected = 0; |
3849 | ||
3850 | saved64 = val64 = readq(&bar0->scheduled_int_ctrl); | |
3851 | val64 |= SCHED_INT_CTRL_ONE_SHOT; | |
3852 | val64 |= SCHED_INT_CTRL_TIMER_EN; | |
3853 | val64 |= SCHED_INT_CTRL_INT2MSI(1); | |
3854 | writeq(val64, &bar0->scheduled_int_ctrl); | |
3855 | ||
3856 | wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10); | |
3857 | ||
3858 | if (!sp->msi_detected) { | |
3859 | /* MSI(X) test failed, go back to INTx mode */ | |
2450022a | 3860 | DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated " |
9e39f7c5 JP |
3861 | "using MSI(X) during test\n", |
3862 | sp->dev->name, pci_name(pdev)); | |
8abc4d5b SS |
3863 | |
3864 | err = -EOPNOTSUPP; | |
3865 | } | |
3866 | ||
3867 | free_irq(sp->entries[1].vector, sp); | |
3868 | ||
3869 | writeq(saved64, &bar0->scheduled_int_ctrl); | |
3870 | ||
3871 | return err; | |
3872 | } | |
18b2b7bd SH |
3873 | |
3874 | static void remove_msix_isr(struct s2io_nic *sp) | |
3875 | { | |
3876 | int i; | |
3877 | u16 msi_control; | |
3878 | ||
f61e0a35 | 3879 | for (i = 0; i < sp->num_entries; i++) { |
d44570e4 | 3880 | if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) { |
18b2b7bd SH |
3881 | int vector = sp->entries[i].vector; |
3882 | void *arg = sp->s2io_entries[i].arg; | |
3883 | free_irq(vector, arg); | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | kfree(sp->entries); | |
3888 | kfree(sp->s2io_entries); | |
3889 | sp->entries = NULL; | |
3890 | sp->s2io_entries = NULL; | |
3891 | ||
3892 | pci_read_config_word(sp->pdev, 0x42, &msi_control); | |
3893 | msi_control &= 0xFFFE; /* Disable MSI */ | |
3894 | pci_write_config_word(sp->pdev, 0x42, msi_control); | |
3895 | ||
3896 | pci_disable_msix(sp->pdev); | |
3897 | } | |
3898 | ||
3899 | static void remove_inta_isr(struct s2io_nic *sp) | |
3900 | { | |
80777c54 | 3901 | free_irq(sp->pdev->irq, sp->dev); |
18b2b7bd SH |
3902 | } |
3903 | ||
1da177e4 LT |
3904 | /* ********************************************************* * |
3905 | * Functions defined below concern the OS part of the driver * | |
3906 | * ********************************************************* */ | |
3907 | ||
20346722 | 3908 | /** |
1da177e4 LT |
3909 | * s2io_open - open entry point of the driver |
3910 | * @dev : pointer to the device structure. | |
3911 | * Description: | |
3912 | * This function is the open entry point of the driver. It mainly calls a | |
3913 | * function to allocate Rx buffers and inserts them into the buffer | |
20346722 | 3914 | * descriptors and then enables the Rx part of the NIC. |
1da177e4 LT |
3915 | * Return value: |
3916 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
3917 | * file on failure. | |
3918 | */ | |
3919 | ||
ac1f60db | 3920 | static int s2io_open(struct net_device *dev) |
1da177e4 | 3921 | { |
4cf1653a | 3922 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c | 3923 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
1da177e4 LT |
3924 | int err = 0; |
3925 | ||
20346722 K |
3926 | /* |
3927 | * Make sure you have link off by default every time | |
1da177e4 LT |
3928 | * Nic is initialized |
3929 | */ | |
3930 | netif_carrier_off(dev); | |
0b1f7ebe | 3931 | sp->last_link_state = 0; |
1da177e4 LT |
3932 | |
3933 | /* Initialize H/W and enable interrupts */ | |
c92ca04b AR |
3934 | err = s2io_card_up(sp); |
3935 | if (err) { | |
1da177e4 LT |
3936 | DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", |
3937 | dev->name); | |
e6a8fee2 | 3938 | goto hw_init_failed; |
1da177e4 LT |
3939 | } |
3940 | ||
2fd37688 | 3941 | if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) { |
1da177e4 | 3942 | DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); |
e6a8fee2 | 3943 | s2io_card_down(sp); |
20346722 | 3944 | err = -ENODEV; |
e6a8fee2 | 3945 | goto hw_init_failed; |
1da177e4 | 3946 | } |
3a3d5756 | 3947 | s2io_start_all_tx_queue(sp); |
1da177e4 | 3948 | return 0; |
20346722 | 3949 | |
20346722 | 3950 | hw_init_failed: |
eaae7f72 | 3951 | if (sp->config.intr_type == MSI_X) { |
491976b2 | 3952 | if (sp->entries) { |
cc6e7c44 | 3953 | kfree(sp->entries); |
ffb5df6c JP |
3954 | swstats->mem_freed += sp->num_entries * |
3955 | sizeof(struct msix_entry); | |
491976b2 SH |
3956 | } |
3957 | if (sp->s2io_entries) { | |
cc6e7c44 | 3958 | kfree(sp->s2io_entries); |
ffb5df6c JP |
3959 | swstats->mem_freed += sp->num_entries * |
3960 | sizeof(struct s2io_msix_entry); | |
491976b2 | 3961 | } |
cc6e7c44 | 3962 | } |
20346722 | 3963 | return err; |
1da177e4 LT |
3964 | } |
3965 | ||
3966 | /** | |
3967 | * s2io_close -close entry point of the driver | |
3968 | * @dev : device pointer. | |
3969 | * Description: | |
3970 | * This is the stop entry point of the driver. It needs to undo exactly | |
3971 | * whatever was done by the open entry point,thus it's usually referred to | |
3972 | * as the close function.Among other things this function mainly stops the | |
3973 | * Rx side of the NIC and frees all the Rx buffers in the Rx rings. | |
3974 | * Return value: | |
3975 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
3976 | * file on failure. | |
3977 | */ | |
3978 | ||
ac1f60db | 3979 | static int s2io_close(struct net_device *dev) |
1da177e4 | 3980 | { |
4cf1653a | 3981 | struct s2io_nic *sp = netdev_priv(dev); |
faa4f796 SH |
3982 | struct config_param *config = &sp->config; |
3983 | u64 tmp64; | |
3984 | int offset; | |
cc6e7c44 | 3985 | |
9f74ffde | 3986 | /* Return if the device is already closed * |
d44570e4 JP |
3987 | * Can happen when s2io_card_up failed in change_mtu * |
3988 | */ | |
9f74ffde SH |
3989 | if (!is_s2io_card_up(sp)) |
3990 | return 0; | |
3991 | ||
3a3d5756 | 3992 | s2io_stop_all_tx_queue(sp); |
faa4f796 SH |
3993 | /* delete all populated mac entries */ |
3994 | for (offset = 1; offset < config->max_mc_addr; offset++) { | |
3995 | tmp64 = do_s2io_read_unicast_mc(sp, offset); | |
3996 | if (tmp64 != S2IO_DISABLE_MAC_ENTRY) | |
3997 | do_s2io_delete_unicast_mc(sp, tmp64); | |
3998 | } | |
3999 | ||
e6a8fee2 | 4000 | s2io_card_down(sp); |
cc6e7c44 | 4001 | |
1da177e4 LT |
4002 | return 0; |
4003 | } | |
4004 | ||
4005 | /** | |
4006 | * s2io_xmit - Tx entry point of te driver | |
4007 | * @skb : the socket buffer containing the Tx data. | |
4008 | * @dev : device pointer. | |
4009 | * Description : | |
4010 | * This function is the Tx entry point of the driver. S2IO NIC supports | |
4011 | * certain protocol assist features on Tx side, namely CSO, S/G, LSO. | |
25985edc | 4012 | * NOTE: when device can't queue the pkt,just the trans_start variable will |
1da177e4 LT |
4013 | * not be upadted. |
4014 | * Return value: | |
4015 | * 0 on success & 1 on failure. | |
4016 | */ | |
4017 | ||
61357325 | 4018 | static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 4019 | { |
4cf1653a | 4020 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
4021 | u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; |
4022 | register u64 val64; | |
1ee6dd77 RB |
4023 | struct TxD *txdp; |
4024 | struct TxFIFO_element __iomem *tx_fifo; | |
2fda096d | 4025 | unsigned long flags = 0; |
be3a6b02 | 4026 | u16 vlan_tag = 0; |
2fda096d | 4027 | struct fifo_info *fifo = NULL; |
6cfc482b | 4028 | int do_spin_lock = 1; |
75c30b13 | 4029 | int offload_type; |
6cfc482b | 4030 | int enable_per_list_interrupt = 0; |
ffb5df6c JP |
4031 | struct config_param *config = &sp->config; |
4032 | struct mac_info *mac_control = &sp->mac_control; | |
4033 | struct stat_block *stats = mac_control->stats_info; | |
4034 | struct swStat *swstats = &stats->sw_stat; | |
1da177e4 | 4035 | |
20346722 | 4036 | DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name); |
491976b2 SH |
4037 | |
4038 | if (unlikely(skb->len <= 0)) { | |
9e39f7c5 | 4039 | DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name); |
491976b2 | 4040 | dev_kfree_skb_any(skb); |
6ed10654 | 4041 | return NETDEV_TX_OK; |
2fda096d | 4042 | } |
491976b2 | 4043 | |
92b84437 | 4044 | if (!is_s2io_card_up(sp)) { |
20346722 | 4045 | DBG_PRINT(TX_DBG, "%s: Card going down for reset\n", |
1da177e4 | 4046 | dev->name); |
20346722 | 4047 | dev_kfree_skb(skb); |
6ed10654 | 4048 | return NETDEV_TX_OK; |
1da177e4 LT |
4049 | } |
4050 | ||
4051 | queue = 0; | |
eab6d18d | 4052 | if (vlan_tx_tag_present(skb)) |
be3a6b02 | 4053 | vlan_tag = vlan_tx_tag_get(skb); |
6cfc482b SH |
4054 | if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) { |
4055 | if (skb->protocol == htons(ETH_P_IP)) { | |
4056 | struct iphdr *ip; | |
4057 | struct tcphdr *th; | |
4058 | ip = ip_hdr(skb); | |
4059 | ||
56f8a75c | 4060 | if (!ip_is_fragment(ip)) { |
6cfc482b | 4061 | th = (struct tcphdr *)(((unsigned char *)ip) + |
d44570e4 | 4062 | ip->ihl*4); |
6cfc482b SH |
4063 | |
4064 | if (ip->protocol == IPPROTO_TCP) { | |
4065 | queue_len = sp->total_tcp_fifos; | |
4066 | queue = (ntohs(th->source) + | |
d44570e4 JP |
4067 | ntohs(th->dest)) & |
4068 | sp->fifo_selector[queue_len - 1]; | |
6cfc482b SH |
4069 | if (queue >= queue_len) |
4070 | queue = queue_len - 1; | |
4071 | } else if (ip->protocol == IPPROTO_UDP) { | |
4072 | queue_len = sp->total_udp_fifos; | |
4073 | queue = (ntohs(th->source) + | |
d44570e4 JP |
4074 | ntohs(th->dest)) & |
4075 | sp->fifo_selector[queue_len - 1]; | |
6cfc482b SH |
4076 | if (queue >= queue_len) |
4077 | queue = queue_len - 1; | |
4078 | queue += sp->udp_fifo_idx; | |
4079 | if (skb->len > 1024) | |
4080 | enable_per_list_interrupt = 1; | |
4081 | do_spin_lock = 0; | |
4082 | } | |
4083 | } | |
4084 | } | |
4085 | } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING) | |
4086 | /* get fifo number based on skb->priority value */ | |
4087 | queue = config->fifo_mapping | |
d44570e4 | 4088 | [skb->priority & (MAX_TX_FIFOS - 1)]; |
6cfc482b | 4089 | fifo = &mac_control->fifos[queue]; |
3a3d5756 | 4090 | |
6cfc482b SH |
4091 | if (do_spin_lock) |
4092 | spin_lock_irqsave(&fifo->tx_lock, flags); | |
4093 | else { | |
4094 | if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags))) | |
4095 | return NETDEV_TX_LOCKED; | |
4096 | } | |
be3a6b02 | 4097 | |
3a3d5756 SH |
4098 | if (sp->config.multiq) { |
4099 | if (__netif_subqueue_stopped(dev, fifo->fifo_no)) { | |
4100 | spin_unlock_irqrestore(&fifo->tx_lock, flags); | |
4101 | return NETDEV_TX_BUSY; | |
4102 | } | |
b19fa1fa | 4103 | } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) { |
3a3d5756 SH |
4104 | if (netif_queue_stopped(dev)) { |
4105 | spin_unlock_irqrestore(&fifo->tx_lock, flags); | |
4106 | return NETDEV_TX_BUSY; | |
4107 | } | |
4108 | } | |
4109 | ||
d44570e4 JP |
4110 | put_off = (u16)fifo->tx_curr_put_info.offset; |
4111 | get_off = (u16)fifo->tx_curr_get_info.offset; | |
43d620c8 | 4112 | txdp = fifo->list_info[put_off].list_virt_addr; |
20346722 | 4113 | |
2fda096d | 4114 | queue_len = fifo->tx_curr_put_info.fifo_len + 1; |
1da177e4 | 4115 | /* Avoid "put" pointer going beyond "get" pointer */ |
863c11a9 | 4116 | if (txdp->Host_Control || |
d44570e4 | 4117 | ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) { |
776bd20f | 4118 | DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n"); |
3a3d5756 | 4119 | s2io_stop_tx_queue(sp, fifo->fifo_no); |
1da177e4 | 4120 | dev_kfree_skb(skb); |
2fda096d | 4121 | spin_unlock_irqrestore(&fifo->tx_lock, flags); |
6ed10654 | 4122 | return NETDEV_TX_OK; |
1da177e4 | 4123 | } |
0b1f7ebe | 4124 | |
75c30b13 | 4125 | offload_type = s2io_offload_type(skb); |
75c30b13 | 4126 | if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { |
1da177e4 | 4127 | txdp->Control_1 |= TXD_TCP_LSO_EN; |
75c30b13 | 4128 | txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb)); |
1da177e4 | 4129 | } |
84fa7933 | 4130 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
d44570e4 JP |
4131 | txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN | |
4132 | TXD_TX_CKO_TCP_EN | | |
4133 | TXD_TX_CKO_UDP_EN); | |
1da177e4 | 4134 | } |
fed5eccd AR |
4135 | txdp->Control_1 |= TXD_GATHER_CODE_FIRST; |
4136 | txdp->Control_1 |= TXD_LIST_OWN_XENA; | |
2fda096d | 4137 | txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no); |
6cfc482b SH |
4138 | if (enable_per_list_interrupt) |
4139 | if (put_off & (queue_len >> 5)) | |
4140 | txdp->Control_2 |= TXD_INT_TYPE_PER_LIST; | |
3a3d5756 | 4141 | if (vlan_tag) { |
be3a6b02 K |
4142 | txdp->Control_2 |= TXD_VLAN_ENABLE; |
4143 | txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag); | |
4144 | } | |
4145 | ||
e743d313 | 4146 | frg_len = skb_headlen(skb); |
75c30b13 | 4147 | if (offload_type == SKB_GSO_UDP) { |
fed5eccd AR |
4148 | int ufo_size; |
4149 | ||
75c30b13 | 4150 | ufo_size = s2io_udp_mss(skb); |
fed5eccd AR |
4151 | ufo_size &= ~7; |
4152 | txdp->Control_1 |= TXD_UFO_EN; | |
4153 | txdp->Control_1 |= TXD_UFO_MSS(ufo_size); | |
4154 | txdp->Control_1 |= TXD_BUFFER0_SIZE(8); | |
4155 | #ifdef __BIG_ENDIAN | |
3459feb8 | 4156 | /* both variants do cpu_to_be64(be32_to_cpu(...)) */ |
2fda096d | 4157 | fifo->ufo_in_band_v[put_off] = |
d44570e4 | 4158 | (__force u64)skb_shinfo(skb)->ip6_frag_id; |
fed5eccd | 4159 | #else |
2fda096d | 4160 | fifo->ufo_in_band_v[put_off] = |
d44570e4 | 4161 | (__force u64)skb_shinfo(skb)->ip6_frag_id << 32; |
fed5eccd | 4162 | #endif |
2fda096d | 4163 | txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v; |
fed5eccd | 4164 | txdp->Buffer_Pointer = pci_map_single(sp->pdev, |
d44570e4 JP |
4165 | fifo->ufo_in_band_v, |
4166 | sizeof(u64), | |
4167 | PCI_DMA_TODEVICE); | |
8d8bb39b | 4168 | if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer)) |
491abf25 | 4169 | goto pci_map_failed; |
fed5eccd | 4170 | txdp++; |
fed5eccd | 4171 | } |
1da177e4 | 4172 | |
d44570e4 JP |
4173 | txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data, |
4174 | frg_len, PCI_DMA_TODEVICE); | |
8d8bb39b | 4175 | if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer)) |
491abf25 VP |
4176 | goto pci_map_failed; |
4177 | ||
d44570e4 | 4178 | txdp->Host_Control = (unsigned long)skb; |
fed5eccd | 4179 | txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len); |
75c30b13 | 4180 | if (offload_type == SKB_GSO_UDP) |
fed5eccd AR |
4181 | txdp->Control_1 |= TXD_UFO_EN; |
4182 | ||
4183 | frg_cnt = skb_shinfo(skb)->nr_frags; | |
1da177e4 LT |
4184 | /* For fragmented SKB. */ |
4185 | for (i = 0; i < frg_cnt; i++) { | |
9e903e08 | 4186 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
0b1f7ebe | 4187 | /* A '0' length fragment will be ignored */ |
9e903e08 | 4188 | if (!skb_frag_size(frag)) |
0b1f7ebe | 4189 | continue; |
1da177e4 | 4190 | txdp++; |
f0d06d82 IC |
4191 | txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev, |
4192 | frag, 0, | |
9e903e08 | 4193 | skb_frag_size(frag), |
5d6bcdfe | 4194 | DMA_TO_DEVICE); |
9e903e08 | 4195 | txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag)); |
75c30b13 | 4196 | if (offload_type == SKB_GSO_UDP) |
fed5eccd | 4197 | txdp->Control_1 |= TXD_UFO_EN; |
1da177e4 LT |
4198 | } |
4199 | txdp->Control_1 |= TXD_GATHER_CODE_LAST; | |
4200 | ||
75c30b13 | 4201 | if (offload_type == SKB_GSO_UDP) |
fed5eccd AR |
4202 | frg_cnt++; /* as Txd0 was used for inband header */ |
4203 | ||
1da177e4 | 4204 | tx_fifo = mac_control->tx_FIFO_start[queue]; |
2fda096d | 4205 | val64 = fifo->list_info[put_off].list_phy_addr; |
1da177e4 LT |
4206 | writeq(val64, &tx_fifo->TxDL_Pointer); |
4207 | ||
4208 | val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | | |
4209 | TX_FIFO_LAST_LIST); | |
75c30b13 | 4210 | if (offload_type) |
fed5eccd | 4211 | val64 |= TX_FIFO_SPECIAL_FUNC; |
75c30b13 | 4212 | |
1da177e4 LT |
4213 | writeq(val64, &tx_fifo->List_Control); |
4214 | ||
303bcb4b K |
4215 | mmiowb(); |
4216 | ||
1da177e4 | 4217 | put_off++; |
2fda096d | 4218 | if (put_off == fifo->tx_curr_put_info.fifo_len + 1) |
863c11a9 | 4219 | put_off = 0; |
2fda096d | 4220 | fifo->tx_curr_put_info.offset = put_off; |
1da177e4 LT |
4221 | |
4222 | /* Avoid "put" pointer going beyond "get" pointer */ | |
863c11a9 | 4223 | if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) { |
ffb5df6c | 4224 | swstats->fifo_full_cnt++; |
1da177e4 LT |
4225 | DBG_PRINT(TX_DBG, |
4226 | "No free TxDs for xmit, Put: 0x%x Get:0x%x\n", | |
4227 | put_off, get_off); | |
3a3d5756 | 4228 | s2io_stop_tx_queue(sp, fifo->fifo_no); |
1da177e4 | 4229 | } |
ffb5df6c | 4230 | swstats->mem_allocated += skb->truesize; |
2fda096d | 4231 | spin_unlock_irqrestore(&fifo->tx_lock, flags); |
1da177e4 | 4232 | |
f6f4bfa3 SH |
4233 | if (sp->config.intr_type == MSI_X) |
4234 | tx_intr_handler(fifo); | |
4235 | ||
6ed10654 | 4236 | return NETDEV_TX_OK; |
ffb5df6c | 4237 | |
491abf25 | 4238 | pci_map_failed: |
ffb5df6c | 4239 | swstats->pci_map_fail_cnt++; |
3a3d5756 | 4240 | s2io_stop_tx_queue(sp, fifo->fifo_no); |
ffb5df6c | 4241 | swstats->mem_freed += skb->truesize; |
491abf25 | 4242 | dev_kfree_skb(skb); |
2fda096d | 4243 | spin_unlock_irqrestore(&fifo->tx_lock, flags); |
6ed10654 | 4244 | return NETDEV_TX_OK; |
1da177e4 LT |
4245 | } |
4246 | ||
25fff88e K |
4247 | static void |
4248 | s2io_alarm_handle(unsigned long data) | |
4249 | { | |
1ee6dd77 | 4250 | struct s2io_nic *sp = (struct s2io_nic *)data; |
8116f3cf | 4251 | struct net_device *dev = sp->dev; |
25fff88e | 4252 | |
8116f3cf | 4253 | s2io_handle_errors(dev); |
25fff88e K |
4254 | mod_timer(&sp->alarm_timer, jiffies + HZ / 2); |
4255 | } | |
4256 | ||
7d12e780 | 4257 | static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id) |
cc6e7c44 | 4258 | { |
1ee6dd77 RB |
4259 | struct ring_info *ring = (struct ring_info *)dev_id; |
4260 | struct s2io_nic *sp = ring->nic; | |
f61e0a35 | 4261 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
cc6e7c44 | 4262 | |
f61e0a35 | 4263 | if (unlikely(!is_s2io_card_up(sp))) |
92b84437 | 4264 | return IRQ_HANDLED; |
92b84437 | 4265 | |
f61e0a35 | 4266 | if (sp->config.napi) { |
1a79d1c3 AV |
4267 | u8 __iomem *addr = NULL; |
4268 | u8 val8 = 0; | |
f61e0a35 | 4269 | |
1a79d1c3 | 4270 | addr = (u8 __iomem *)&bar0->xmsi_mask_reg; |
f61e0a35 SH |
4271 | addr += (7 - ring->ring_no); |
4272 | val8 = (ring->ring_no == 0) ? 0x7f : 0xff; | |
4273 | writeb(val8, addr); | |
4274 | val8 = readb(addr); | |
288379f0 | 4275 | napi_schedule(&ring->napi); |
f61e0a35 SH |
4276 | } else { |
4277 | rx_intr_handler(ring, 0); | |
8d8bb39b | 4278 | s2io_chk_rx_buffers(sp, ring); |
f61e0a35 | 4279 | } |
7d3d0439 | 4280 | |
cc6e7c44 RA |
4281 | return IRQ_HANDLED; |
4282 | } | |
4283 | ||
7d12e780 | 4284 | static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id) |
cc6e7c44 | 4285 | { |
ac731ab6 SH |
4286 | int i; |
4287 | struct fifo_info *fifos = (struct fifo_info *)dev_id; | |
4288 | struct s2io_nic *sp = fifos->nic; | |
4289 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
4290 | struct config_param *config = &sp->config; | |
4291 | u64 reason; | |
cc6e7c44 | 4292 | |
ac731ab6 SH |
4293 | if (unlikely(!is_s2io_card_up(sp))) |
4294 | return IRQ_NONE; | |
4295 | ||
4296 | reason = readq(&bar0->general_int_status); | |
4297 | if (unlikely(reason == S2IO_MINUS_ONE)) | |
4298 | /* Nothing much can be done. Get out */ | |
92b84437 | 4299 | return IRQ_HANDLED; |
92b84437 | 4300 | |
01e16faa SH |
4301 | if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) { |
4302 | writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); | |
ac731ab6 | 4303 | |
01e16faa SH |
4304 | if (reason & GEN_INTR_TXPIC) |
4305 | s2io_txpic_intr_handle(sp); | |
ac731ab6 | 4306 | |
01e16faa SH |
4307 | if (reason & GEN_INTR_TXTRAFFIC) |
4308 | writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); | |
ac731ab6 | 4309 | |
01e16faa SH |
4310 | for (i = 0; i < config->tx_fifo_num; i++) |
4311 | tx_intr_handler(&fifos[i]); | |
ac731ab6 | 4312 | |
01e16faa SH |
4313 | writeq(sp->general_int_mask, &bar0->general_int_mask); |
4314 | readl(&bar0->general_int_status); | |
4315 | return IRQ_HANDLED; | |
4316 | } | |
4317 | /* The interrupt was not raised by us */ | |
4318 | return IRQ_NONE; | |
cc6e7c44 | 4319 | } |
ac731ab6 | 4320 | |
1ee6dd77 | 4321 | static void s2io_txpic_intr_handle(struct s2io_nic *sp) |
a371a07d | 4322 | { |
1ee6dd77 | 4323 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
a371a07d K |
4324 | u64 val64; |
4325 | ||
4326 | val64 = readq(&bar0->pic_int_status); | |
4327 | if (val64 & PIC_INT_GPIO) { | |
4328 | val64 = readq(&bar0->gpio_int_reg); | |
4329 | if ((val64 & GPIO_INT_REG_LINK_DOWN) && | |
4330 | (val64 & GPIO_INT_REG_LINK_UP)) { | |
c92ca04b AR |
4331 | /* |
4332 | * This is unstable state so clear both up/down | |
4333 | * interrupt and adapter to re-evaluate the link state. | |
4334 | */ | |
d44570e4 | 4335 | val64 |= GPIO_INT_REG_LINK_DOWN; |
a371a07d K |
4336 | val64 |= GPIO_INT_REG_LINK_UP; |
4337 | writeq(val64, &bar0->gpio_int_reg); | |
a371a07d | 4338 | val64 = readq(&bar0->gpio_int_mask); |
c92ca04b AR |
4339 | val64 &= ~(GPIO_INT_MASK_LINK_UP | |
4340 | GPIO_INT_MASK_LINK_DOWN); | |
a371a07d | 4341 | writeq(val64, &bar0->gpio_int_mask); |
d44570e4 | 4342 | } else if (val64 & GPIO_INT_REG_LINK_UP) { |
c92ca04b | 4343 | val64 = readq(&bar0->adapter_status); |
d44570e4 | 4344 | /* Enable Adapter */ |
19a60522 SS |
4345 | val64 = readq(&bar0->adapter_control); |
4346 | val64 |= ADAPTER_CNTL_EN; | |
4347 | writeq(val64, &bar0->adapter_control); | |
4348 | val64 |= ADAPTER_LED_ON; | |
4349 | writeq(val64, &bar0->adapter_control); | |
4350 | if (!sp->device_enabled_once) | |
4351 | sp->device_enabled_once = 1; | |
c92ca04b | 4352 | |
19a60522 SS |
4353 | s2io_link(sp, LINK_UP); |
4354 | /* | |
4355 | * unmask link down interrupt and mask link-up | |
4356 | * intr | |
4357 | */ | |
4358 | val64 = readq(&bar0->gpio_int_mask); | |
4359 | val64 &= ~GPIO_INT_MASK_LINK_DOWN; | |
4360 | val64 |= GPIO_INT_MASK_LINK_UP; | |
4361 | writeq(val64, &bar0->gpio_int_mask); | |
c92ca04b | 4362 | |
d44570e4 | 4363 | } else if (val64 & GPIO_INT_REG_LINK_DOWN) { |
c92ca04b | 4364 | val64 = readq(&bar0->adapter_status); |
19a60522 SS |
4365 | s2io_link(sp, LINK_DOWN); |
4366 | /* Link is down so unmaks link up interrupt */ | |
4367 | val64 = readq(&bar0->gpio_int_mask); | |
4368 | val64 &= ~GPIO_INT_MASK_LINK_UP; | |
4369 | val64 |= GPIO_INT_MASK_LINK_DOWN; | |
4370 | writeq(val64, &bar0->gpio_int_mask); | |
ac1f90d6 SS |
4371 | |
4372 | /* turn off LED */ | |
4373 | val64 = readq(&bar0->adapter_control); | |
d44570e4 | 4374 | val64 = val64 & (~ADAPTER_LED_ON); |
ac1f90d6 | 4375 | writeq(val64, &bar0->adapter_control); |
a371a07d K |
4376 | } |
4377 | } | |
c92ca04b | 4378 | val64 = readq(&bar0->gpio_int_mask); |
a371a07d K |
4379 | } |
4380 | ||
8116f3cf SS |
4381 | /** |
4382 | * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter | |
4383 | * @value: alarm bits | |
4384 | * @addr: address value | |
4385 | * @cnt: counter variable | |
4386 | * Description: Check for alarm and increment the counter | |
4387 | * Return Value: | |
4388 | * 1 - if alarm bit set | |
4389 | * 0 - if alarm bit is not set | |
4390 | */ | |
d44570e4 JP |
4391 | static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr, |
4392 | unsigned long long *cnt) | |
8116f3cf SS |
4393 | { |
4394 | u64 val64; | |
4395 | val64 = readq(addr); | |
d44570e4 | 4396 | if (val64 & value) { |
8116f3cf SS |
4397 | writeq(val64, addr); |
4398 | (*cnt)++; | |
4399 | return 1; | |
4400 | } | |
4401 | return 0; | |
4402 | ||
4403 | } | |
4404 | ||
4405 | /** | |
4406 | * s2io_handle_errors - Xframe error indication handler | |
4407 | * @nic: device private variable | |
4408 | * Description: Handle alarms such as loss of link, single or | |
4409 | * double ECC errors, critical and serious errors. | |
4410 | * Return Value: | |
4411 | * NONE | |
4412 | */ | |
d44570e4 | 4413 | static void s2io_handle_errors(void *dev_id) |
8116f3cf | 4414 | { |
d44570e4 | 4415 | struct net_device *dev = (struct net_device *)dev_id; |
4cf1653a | 4416 | struct s2io_nic *sp = netdev_priv(dev); |
8116f3cf | 4417 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
d44570e4 | 4418 | u64 temp64 = 0, val64 = 0; |
8116f3cf SS |
4419 | int i = 0; |
4420 | ||
4421 | struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat; | |
4422 | struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat; | |
4423 | ||
92b84437 | 4424 | if (!is_s2io_card_up(sp)) |
8116f3cf SS |
4425 | return; |
4426 | ||
4427 | if (pci_channel_offline(sp->pdev)) | |
4428 | return; | |
4429 | ||
4430 | memset(&sw_stat->ring_full_cnt, 0, | |
d44570e4 | 4431 | sizeof(sw_stat->ring_full_cnt)); |
8116f3cf SS |
4432 | |
4433 | /* Handling the XPAK counters update */ | |
d44570e4 | 4434 | if (stats->xpak_timer_count < 72000) { |
8116f3cf SS |
4435 | /* waiting for an hour */ |
4436 | stats->xpak_timer_count++; | |
4437 | } else { | |
4438 | s2io_updt_xpak_counter(dev); | |
4439 | /* reset the count to zero */ | |
4440 | stats->xpak_timer_count = 0; | |
4441 | } | |
4442 | ||
4443 | /* Handling link status change error Intr */ | |
4444 | if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) { | |
4445 | val64 = readq(&bar0->mac_rmac_err_reg); | |
4446 | writeq(val64, &bar0->mac_rmac_err_reg); | |
4447 | if (val64 & RMAC_LINK_STATE_CHANGE_INT) | |
4448 | schedule_work(&sp->set_link_task); | |
4449 | } | |
4450 | ||
4451 | /* In case of a serious error, the device will be Reset. */ | |
4452 | if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, | |
d44570e4 | 4453 | &sw_stat->serious_err_cnt)) |
8116f3cf SS |
4454 | goto reset; |
4455 | ||
4456 | /* Check for data parity error */ | |
4457 | if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, | |
d44570e4 | 4458 | &sw_stat->parity_err_cnt)) |
8116f3cf SS |
4459 | goto reset; |
4460 | ||
4461 | /* Check for ring full counter */ | |
4462 | if (sp->device_type == XFRAME_II_DEVICE) { | |
4463 | val64 = readq(&bar0->ring_bump_counter1); | |
d44570e4 JP |
4464 | for (i = 0; i < 4; i++) { |
4465 | temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); | |
8116f3cf SS |
4466 | temp64 >>= 64 - ((i+1)*16); |
4467 | sw_stat->ring_full_cnt[i] += temp64; | |
4468 | } | |
4469 | ||
4470 | val64 = readq(&bar0->ring_bump_counter2); | |
d44570e4 JP |
4471 | for (i = 0; i < 4; i++) { |
4472 | temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); | |
8116f3cf | 4473 | temp64 >>= 64 - ((i+1)*16); |
d44570e4 | 4474 | sw_stat->ring_full_cnt[i+4] += temp64; |
8116f3cf SS |
4475 | } |
4476 | } | |
4477 | ||
4478 | val64 = readq(&bar0->txdma_int_status); | |
4479 | /*check for pfc_err*/ | |
4480 | if (val64 & TXDMA_PFC_INT) { | |
d44570e4 JP |
4481 | if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM | |
4482 | PFC_MISC_0_ERR | PFC_MISC_1_ERR | | |
4483 | PFC_PCIX_ERR, | |
4484 | &bar0->pfc_err_reg, | |
4485 | &sw_stat->pfc_err_cnt)) | |
8116f3cf | 4486 | goto reset; |
d44570e4 JP |
4487 | do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, |
4488 | &bar0->pfc_err_reg, | |
4489 | &sw_stat->pfc_err_cnt); | |
8116f3cf SS |
4490 | } |
4491 | ||
4492 | /*check for tda_err*/ | |
4493 | if (val64 & TXDMA_TDA_INT) { | |
d44570e4 JP |
4494 | if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | |
4495 | TDA_SM0_ERR_ALARM | | |
4496 | TDA_SM1_ERR_ALARM, | |
4497 | &bar0->tda_err_reg, | |
4498 | &sw_stat->tda_err_cnt)) | |
8116f3cf SS |
4499 | goto reset; |
4500 | do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR, | |
d44570e4 JP |
4501 | &bar0->tda_err_reg, |
4502 | &sw_stat->tda_err_cnt); | |
8116f3cf SS |
4503 | } |
4504 | /*check for pcc_err*/ | |
4505 | if (val64 & TXDMA_PCC_INT) { | |
d44570e4 JP |
4506 | if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM | |
4507 | PCC_N_SERR | PCC_6_COF_OV_ERR | | |
4508 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR | | |
4509 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR | | |
4510 | PCC_TXB_ECC_DB_ERR, | |
4511 | &bar0->pcc_err_reg, | |
4512 | &sw_stat->pcc_err_cnt)) | |
8116f3cf SS |
4513 | goto reset; |
4514 | do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR, | |
d44570e4 JP |
4515 | &bar0->pcc_err_reg, |
4516 | &sw_stat->pcc_err_cnt); | |
8116f3cf SS |
4517 | } |
4518 | ||
4519 | /*check for tti_err*/ | |
4520 | if (val64 & TXDMA_TTI_INT) { | |
d44570e4 JP |
4521 | if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, |
4522 | &bar0->tti_err_reg, | |
4523 | &sw_stat->tti_err_cnt)) | |
8116f3cf SS |
4524 | goto reset; |
4525 | do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR, | |
d44570e4 JP |
4526 | &bar0->tti_err_reg, |
4527 | &sw_stat->tti_err_cnt); | |
8116f3cf SS |
4528 | } |
4529 | ||
4530 | /*check for lso_err*/ | |
4531 | if (val64 & TXDMA_LSO_INT) { | |
d44570e4 JP |
4532 | if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT | |
4533 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM, | |
4534 | &bar0->lso_err_reg, | |
4535 | &sw_stat->lso_err_cnt)) | |
8116f3cf SS |
4536 | goto reset; |
4537 | do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW, | |
d44570e4 JP |
4538 | &bar0->lso_err_reg, |
4539 | &sw_stat->lso_err_cnt); | |
8116f3cf SS |
4540 | } |
4541 | ||
4542 | /*check for tpa_err*/ | |
4543 | if (val64 & TXDMA_TPA_INT) { | |
d44570e4 JP |
4544 | if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, |
4545 | &bar0->tpa_err_reg, | |
4546 | &sw_stat->tpa_err_cnt)) | |
8116f3cf | 4547 | goto reset; |
d44570e4 JP |
4548 | do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, |
4549 | &bar0->tpa_err_reg, | |
4550 | &sw_stat->tpa_err_cnt); | |
8116f3cf SS |
4551 | } |
4552 | ||
4553 | /*check for sm_err*/ | |
4554 | if (val64 & TXDMA_SM_INT) { | |
d44570e4 JP |
4555 | if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, |
4556 | &bar0->sm_err_reg, | |
4557 | &sw_stat->sm_err_cnt)) | |
8116f3cf SS |
4558 | goto reset; |
4559 | } | |
4560 | ||
4561 | val64 = readq(&bar0->mac_int_status); | |
4562 | if (val64 & MAC_INT_STATUS_TMAC_INT) { | |
4563 | if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR, | |
d44570e4 JP |
4564 | &bar0->mac_tmac_err_reg, |
4565 | &sw_stat->mac_tmac_err_cnt)) | |
8116f3cf | 4566 | goto reset; |
d44570e4 JP |
4567 | do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR | |
4568 | TMAC_DESC_ECC_SG_ERR | | |
4569 | TMAC_DESC_ECC_DB_ERR, | |
4570 | &bar0->mac_tmac_err_reg, | |
4571 | &sw_stat->mac_tmac_err_cnt); | |
8116f3cf SS |
4572 | } |
4573 | ||
4574 | val64 = readq(&bar0->xgxs_int_status); | |
4575 | if (val64 & XGXS_INT_STATUS_TXGXS) { | |
4576 | if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR, | |
d44570e4 JP |
4577 | &bar0->xgxs_txgxs_err_reg, |
4578 | &sw_stat->xgxs_txgxs_err_cnt)) | |
8116f3cf SS |
4579 | goto reset; |
4580 | do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR, | |
d44570e4 JP |
4581 | &bar0->xgxs_txgxs_err_reg, |
4582 | &sw_stat->xgxs_txgxs_err_cnt); | |
8116f3cf SS |
4583 | } |
4584 | ||
4585 | val64 = readq(&bar0->rxdma_int_status); | |
4586 | if (val64 & RXDMA_INT_RC_INT_M) { | |
d44570e4 JP |
4587 | if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | |
4588 | RC_FTC_ECC_DB_ERR | | |
4589 | RC_PRCn_SM_ERR_ALARM | | |
4590 | RC_FTC_SM_ERR_ALARM, | |
4591 | &bar0->rc_err_reg, | |
4592 | &sw_stat->rc_err_cnt)) | |
8116f3cf | 4593 | goto reset; |
d44570e4 JP |
4594 | do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | |
4595 | RC_FTC_ECC_SG_ERR | | |
4596 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, | |
4597 | &sw_stat->rc_err_cnt); | |
4598 | if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | | |
4599 | PRC_PCI_AB_WR_Rn | | |
4600 | PRC_PCI_AB_F_WR_Rn, | |
4601 | &bar0->prc_pcix_err_reg, | |
4602 | &sw_stat->prc_pcix_err_cnt)) | |
8116f3cf | 4603 | goto reset; |
d44570e4 JP |
4604 | do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | |
4605 | PRC_PCI_DP_WR_Rn | | |
4606 | PRC_PCI_DP_F_WR_Rn, | |
4607 | &bar0->prc_pcix_err_reg, | |
4608 | &sw_stat->prc_pcix_err_cnt); | |
8116f3cf SS |
4609 | } |
4610 | ||
4611 | if (val64 & RXDMA_INT_RPA_INT_M) { | |
4612 | if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR, | |
d44570e4 JP |
4613 | &bar0->rpa_err_reg, |
4614 | &sw_stat->rpa_err_cnt)) | |
8116f3cf SS |
4615 | goto reset; |
4616 | do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, | |
d44570e4 JP |
4617 | &bar0->rpa_err_reg, |
4618 | &sw_stat->rpa_err_cnt); | |
8116f3cf SS |
4619 | } |
4620 | ||
4621 | if (val64 & RXDMA_INT_RDA_INT_M) { | |
d44570e4 JP |
4622 | if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR | |
4623 | RDA_FRM_ECC_DB_N_AERR | | |
4624 | RDA_SM1_ERR_ALARM | | |
4625 | RDA_SM0_ERR_ALARM | | |
4626 | RDA_RXD_ECC_DB_SERR, | |
4627 | &bar0->rda_err_reg, | |
4628 | &sw_stat->rda_err_cnt)) | |
8116f3cf | 4629 | goto reset; |
d44570e4 JP |
4630 | do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | |
4631 | RDA_FRM_ECC_SG_ERR | | |
4632 | RDA_MISC_ERR | | |
4633 | RDA_PCIX_ERR, | |
4634 | &bar0->rda_err_reg, | |
4635 | &sw_stat->rda_err_cnt); | |
8116f3cf SS |
4636 | } |
4637 | ||
4638 | if (val64 & RXDMA_INT_RTI_INT_M) { | |
d44570e4 JP |
4639 | if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, |
4640 | &bar0->rti_err_reg, | |
4641 | &sw_stat->rti_err_cnt)) | |
8116f3cf SS |
4642 | goto reset; |
4643 | do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR, | |
d44570e4 JP |
4644 | &bar0->rti_err_reg, |
4645 | &sw_stat->rti_err_cnt); | |
8116f3cf SS |
4646 | } |
4647 | ||
4648 | val64 = readq(&bar0->mac_int_status); | |
4649 | if (val64 & MAC_INT_STATUS_RMAC_INT) { | |
4650 | if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR, | |
d44570e4 JP |
4651 | &bar0->mac_rmac_err_reg, |
4652 | &sw_stat->mac_rmac_err_cnt)) | |
8116f3cf | 4653 | goto reset; |
d44570e4 JP |
4654 | do_s2io_chk_alarm_bit(RMAC_UNUSED_INT | |
4655 | RMAC_SINGLE_ECC_ERR | | |
4656 | RMAC_DOUBLE_ECC_ERR, | |
4657 | &bar0->mac_rmac_err_reg, | |
4658 | &sw_stat->mac_rmac_err_cnt); | |
8116f3cf SS |
4659 | } |
4660 | ||
4661 | val64 = readq(&bar0->xgxs_int_status); | |
4662 | if (val64 & XGXS_INT_STATUS_RXGXS) { | |
4663 | if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, | |
d44570e4 JP |
4664 | &bar0->xgxs_rxgxs_err_reg, |
4665 | &sw_stat->xgxs_rxgxs_err_cnt)) | |
8116f3cf SS |
4666 | goto reset; |
4667 | } | |
4668 | ||
4669 | val64 = readq(&bar0->mc_int_status); | |
d44570e4 JP |
4670 | if (val64 & MC_INT_STATUS_MC_INT) { |
4671 | if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, | |
4672 | &bar0->mc_err_reg, | |
4673 | &sw_stat->mc_err_cnt)) | |
8116f3cf SS |
4674 | goto reset; |
4675 | ||
4676 | /* Handling Ecc errors */ | |
4677 | if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { | |
4678 | writeq(val64, &bar0->mc_err_reg); | |
4679 | if (val64 & MC_ERR_REG_ECC_ALL_DBL) { | |
4680 | sw_stat->double_ecc_errs++; | |
4681 | if (sp->device_type != XFRAME_II_DEVICE) { | |
4682 | /* | |
4683 | * Reset XframeI only if critical error | |
4684 | */ | |
4685 | if (val64 & | |
d44570e4 JP |
4686 | (MC_ERR_REG_MIRI_ECC_DB_ERR_0 | |
4687 | MC_ERR_REG_MIRI_ECC_DB_ERR_1)) | |
4688 | goto reset; | |
4689 | } | |
8116f3cf SS |
4690 | } else |
4691 | sw_stat->single_ecc_errs++; | |
4692 | } | |
4693 | } | |
4694 | return; | |
4695 | ||
4696 | reset: | |
3a3d5756 | 4697 | s2io_stop_all_tx_queue(sp); |
8116f3cf SS |
4698 | schedule_work(&sp->rst_timer_task); |
4699 | sw_stat->soft_reset_cnt++; | |
8116f3cf SS |
4700 | } |
4701 | ||
1da177e4 LT |
4702 | /** |
4703 | * s2io_isr - ISR handler of the device . | |
4704 | * @irq: the irq of the device. | |
4705 | * @dev_id: a void pointer to the dev structure of the NIC. | |
20346722 K |
4706 | * Description: This function is the ISR handler of the device. It |
4707 | * identifies the reason for the interrupt and calls the relevant | |
4708 | * service routines. As a contongency measure, this ISR allocates the | |
1da177e4 LT |
4709 | * recv buffers, if their numbers are below the panic value which is |
4710 | * presently set to 25% of the original number of rcv buffers allocated. | |
4711 | * Return value: | |
20346722 | 4712 | * IRQ_HANDLED: will be returned if IRQ was handled by this routine |
1da177e4 LT |
4713 | * IRQ_NONE: will be returned if interrupt is not from our device |
4714 | */ | |
7d12e780 | 4715 | static irqreturn_t s2io_isr(int irq, void *dev_id) |
1da177e4 | 4716 | { |
d44570e4 | 4717 | struct net_device *dev = (struct net_device *)dev_id; |
4cf1653a | 4718 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 4719 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
20346722 | 4720 | int i; |
19a60522 | 4721 | u64 reason = 0; |
1ee6dd77 | 4722 | struct mac_info *mac_control; |
1da177e4 LT |
4723 | struct config_param *config; |
4724 | ||
d796fdb7 LV |
4725 | /* Pretend we handled any irq's from a disconnected card */ |
4726 | if (pci_channel_offline(sp->pdev)) | |
4727 | return IRQ_NONE; | |
4728 | ||
596c5c97 | 4729 | if (!is_s2io_card_up(sp)) |
92b84437 | 4730 | return IRQ_NONE; |
92b84437 | 4731 | |
1da177e4 | 4732 | config = &sp->config; |
ffb5df6c | 4733 | mac_control = &sp->mac_control; |
1da177e4 | 4734 | |
20346722 | 4735 | /* |
1da177e4 LT |
4736 | * Identify the cause for interrupt and call the appropriate |
4737 | * interrupt handler. Causes for the interrupt could be; | |
4738 | * 1. Rx of packet. | |
4739 | * 2. Tx complete. | |
4740 | * 3. Link down. | |
1da177e4 LT |
4741 | */ |
4742 | reason = readq(&bar0->general_int_status); | |
4743 | ||
d44570e4 JP |
4744 | if (unlikely(reason == S2IO_MINUS_ONE)) |
4745 | return IRQ_HANDLED; /* Nothing much can be done. Get out */ | |
5d3213cc | 4746 | |
d44570e4 JP |
4747 | if (reason & |
4748 | (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) { | |
596c5c97 SS |
4749 | writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); |
4750 | ||
4751 | if (config->napi) { | |
4752 | if (reason & GEN_INTR_RXTRAFFIC) { | |
288379f0 | 4753 | napi_schedule(&sp->napi); |
f61e0a35 SH |
4754 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); |
4755 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); | |
4756 | readl(&bar0->rx_traffic_int); | |
db874e65 | 4757 | } |
596c5c97 SS |
4758 | } else { |
4759 | /* | |
4760 | * rx_traffic_int reg is an R1 register, writing all 1's | |
4761 | * will ensure that the actual interrupt causing bit | |
4762 | * get's cleared and hence a read can be avoided. | |
4763 | */ | |
4764 | if (reason & GEN_INTR_RXTRAFFIC) | |
19a60522 | 4765 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); |
596c5c97 | 4766 | |
13d866a9 JP |
4767 | for (i = 0; i < config->rx_ring_num; i++) { |
4768 | struct ring_info *ring = &mac_control->rings[i]; | |
4769 | ||
4770 | rx_intr_handler(ring, 0); | |
4771 | } | |
db874e65 | 4772 | } |
596c5c97 | 4773 | |
db874e65 | 4774 | /* |
596c5c97 | 4775 | * tx_traffic_int reg is an R1 register, writing all 1's |
db874e65 SS |
4776 | * will ensure that the actual interrupt causing bit get's |
4777 | * cleared and hence a read can be avoided. | |
4778 | */ | |
596c5c97 SS |
4779 | if (reason & GEN_INTR_TXTRAFFIC) |
4780 | writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); | |
19a60522 | 4781 | |
596c5c97 SS |
4782 | for (i = 0; i < config->tx_fifo_num; i++) |
4783 | tx_intr_handler(&mac_control->fifos[i]); | |
1da177e4 | 4784 | |
596c5c97 SS |
4785 | if (reason & GEN_INTR_TXPIC) |
4786 | s2io_txpic_intr_handle(sp); | |
fe113638 | 4787 | |
596c5c97 SS |
4788 | /* |
4789 | * Reallocate the buffers from the interrupt handler itself. | |
4790 | */ | |
4791 | if (!config->napi) { | |
13d866a9 JP |
4792 | for (i = 0; i < config->rx_ring_num; i++) { |
4793 | struct ring_info *ring = &mac_control->rings[i]; | |
4794 | ||
4795 | s2io_chk_rx_buffers(sp, ring); | |
4796 | } | |
596c5c97 SS |
4797 | } |
4798 | writeq(sp->general_int_mask, &bar0->general_int_mask); | |
4799 | readl(&bar0->general_int_status); | |
20346722 | 4800 | |
596c5c97 | 4801 | return IRQ_HANDLED; |
db874e65 | 4802 | |
d44570e4 | 4803 | } else if (!reason) { |
596c5c97 SS |
4804 | /* The interrupt was not raised by us */ |
4805 | return IRQ_NONE; | |
4806 | } | |
db874e65 | 4807 | |
1da177e4 LT |
4808 | return IRQ_HANDLED; |
4809 | } | |
4810 | ||
7ba013ac K |
4811 | /** |
4812 | * s2io_updt_stats - | |
4813 | */ | |
1ee6dd77 | 4814 | static void s2io_updt_stats(struct s2io_nic *sp) |
7ba013ac | 4815 | { |
1ee6dd77 | 4816 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
7ba013ac K |
4817 | u64 val64; |
4818 | int cnt = 0; | |
4819 | ||
92b84437 | 4820 | if (is_s2io_card_up(sp)) { |
7ba013ac K |
4821 | /* Apprx 30us on a 133 MHz bus */ |
4822 | val64 = SET_UPDT_CLICKS(10) | | |
4823 | STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN; | |
4824 | writeq(val64, &bar0->stat_cfg); | |
4825 | do { | |
4826 | udelay(100); | |
4827 | val64 = readq(&bar0->stat_cfg); | |
b7b5a128 | 4828 | if (!(val64 & s2BIT(0))) |
7ba013ac K |
4829 | break; |
4830 | cnt++; | |
4831 | if (cnt == 5) | |
4832 | break; /* Updt failed */ | |
d44570e4 | 4833 | } while (1); |
8a4bdbaa | 4834 | } |
7ba013ac K |
4835 | } |
4836 | ||
1da177e4 | 4837 | /** |
20346722 | 4838 | * s2io_get_stats - Updates the device statistics structure. |
1da177e4 LT |
4839 | * @dev : pointer to the device structure. |
4840 | * Description: | |
20346722 | 4841 | * This function updates the device statistics structure in the s2io_nic |
1da177e4 LT |
4842 | * structure and returns a pointer to the same. |
4843 | * Return value: | |
4844 | * pointer to the updated net_device_stats structure. | |
4845 | */ | |
ac1f60db | 4846 | static struct net_device_stats *s2io_get_stats(struct net_device *dev) |
1da177e4 | 4847 | { |
4cf1653a | 4848 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c JP |
4849 | struct mac_info *mac_control = &sp->mac_control; |
4850 | struct stat_block *stats = mac_control->stats_info; | |
4a490432 | 4851 | u64 delta; |
1da177e4 | 4852 | |
7ba013ac K |
4853 | /* Configure Stats for immediate updt */ |
4854 | s2io_updt_stats(sp); | |
4855 | ||
4a490432 JM |
4856 | /* A device reset will cause the on-adapter statistics to be zero'ed. |
4857 | * This can be done while running by changing the MTU. To prevent the | |
4858 | * system from having the stats zero'ed, the driver keeps a copy of the | |
4859 | * last update to the system (which is also zero'ed on reset). This | |
4860 | * enables the driver to accurately know the delta between the last | |
4861 | * update and the current update. | |
4862 | */ | |
4863 | delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 | | |
4864 | le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets; | |
4865 | sp->stats.rx_packets += delta; | |
4866 | dev->stats.rx_packets += delta; | |
4867 | ||
4868 | delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 | | |
4869 | le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets; | |
4870 | sp->stats.tx_packets += delta; | |
4871 | dev->stats.tx_packets += delta; | |
4872 | ||
4873 | delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 | | |
4874 | le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes; | |
4875 | sp->stats.rx_bytes += delta; | |
4876 | dev->stats.rx_bytes += delta; | |
4877 | ||
4878 | delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 | | |
4879 | le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes; | |
4880 | sp->stats.tx_bytes += delta; | |
4881 | dev->stats.tx_bytes += delta; | |
4882 | ||
4883 | delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors; | |
4884 | sp->stats.rx_errors += delta; | |
4885 | dev->stats.rx_errors += delta; | |
4886 | ||
4887 | delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 | | |
4888 | le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors; | |
4889 | sp->stats.tx_errors += delta; | |
4890 | dev->stats.tx_errors += delta; | |
4891 | ||
4892 | delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped; | |
4893 | sp->stats.rx_dropped += delta; | |
4894 | dev->stats.rx_dropped += delta; | |
4895 | ||
4896 | delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped; | |
4897 | sp->stats.tx_dropped += delta; | |
4898 | dev->stats.tx_dropped += delta; | |
4899 | ||
4900 | /* The adapter MAC interprets pause frames as multicast packets, but | |
4901 | * does not pass them up. This erroneously increases the multicast | |
4902 | * packet count and needs to be deducted when the multicast frame count | |
4903 | * is queried. | |
4904 | */ | |
4905 | delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 | | |
4906 | le32_to_cpu(stats->rmac_vld_mcst_frms); | |
4907 | delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms); | |
4908 | delta -= sp->stats.multicast; | |
4909 | sp->stats.multicast += delta; | |
4910 | dev->stats.multicast += delta; | |
1da177e4 | 4911 | |
4a490432 JM |
4912 | delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 | |
4913 | le32_to_cpu(stats->rmac_usized_frms)) + | |
4914 | le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors; | |
4915 | sp->stats.rx_length_errors += delta; | |
4916 | dev->stats.rx_length_errors += delta; | |
13d866a9 | 4917 | |
4a490432 JM |
4918 | delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors; |
4919 | sp->stats.rx_crc_errors += delta; | |
4920 | dev->stats.rx_crc_errors += delta; | |
0425b46a | 4921 | |
d44570e4 | 4922 | return &dev->stats; |
1da177e4 LT |
4923 | } |
4924 | ||
4925 | /** | |
4926 | * s2io_set_multicast - entry point for multicast address enable/disable. | |
4927 | * @dev : pointer to the device structure | |
4928 | * Description: | |
20346722 K |
4929 | * This function is a driver entry point which gets called by the kernel |
4930 | * whenever multicast addresses must be enabled/disabled. This also gets | |
1da177e4 LT |
4931 | * called to set/reset promiscuous mode. Depending on the deivce flag, we |
4932 | * determine, if multicast address must be enabled or if promiscuous mode | |
4933 | * is to be disabled etc. | |
4934 | * Return value: | |
4935 | * void. | |
4936 | */ | |
4937 | ||
4938 | static void s2io_set_multicast(struct net_device *dev) | |
4939 | { | |
4940 | int i, j, prev_cnt; | |
22bedad3 | 4941 | struct netdev_hw_addr *ha; |
4cf1653a | 4942 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 4943 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 4944 | u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = |
d44570e4 | 4945 | 0xfeffffffffffULL; |
faa4f796 | 4946 | u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0; |
1da177e4 | 4947 | void __iomem *add; |
faa4f796 | 4948 | struct config_param *config = &sp->config; |
1da177e4 LT |
4949 | |
4950 | if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) { | |
4951 | /* Enable all Multicast addresses */ | |
4952 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac), | |
4953 | &bar0->rmac_addr_data0_mem); | |
4954 | writeq(RMAC_ADDR_DATA1_MEM_MASK(mask), | |
4955 | &bar0->rmac_addr_data1_mem); | |
4956 | val64 = RMAC_ADDR_CMD_MEM_WE | | |
d44570e4 JP |
4957 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
4958 | RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1); | |
1da177e4 LT |
4959 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
4960 | /* Wait till command completes */ | |
c92ca04b | 4961 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
4962 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
4963 | S2IO_BIT_RESET); | |
1da177e4 LT |
4964 | |
4965 | sp->m_cast_flg = 1; | |
faa4f796 | 4966 | sp->all_multi_pos = config->max_mc_addr - 1; |
1da177e4 LT |
4967 | } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) { |
4968 | /* Disable all Multicast addresses */ | |
4969 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), | |
4970 | &bar0->rmac_addr_data0_mem); | |
5e25b9dd K |
4971 | writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0), |
4972 | &bar0->rmac_addr_data1_mem); | |
1da177e4 | 4973 | val64 = RMAC_ADDR_CMD_MEM_WE | |
d44570e4 JP |
4974 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
4975 | RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); | |
1da177e4 LT |
4976 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
4977 | /* Wait till command completes */ | |
c92ca04b | 4978 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
4979 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
4980 | S2IO_BIT_RESET); | |
1da177e4 LT |
4981 | |
4982 | sp->m_cast_flg = 0; | |
4983 | sp->all_multi_pos = 0; | |
4984 | } | |
4985 | ||
4986 | if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) { | |
4987 | /* Put the NIC into promiscuous mode */ | |
4988 | add = &bar0->mac_cfg; | |
4989 | val64 = readq(&bar0->mac_cfg); | |
4990 | val64 |= MAC_CFG_RMAC_PROM_ENABLE; | |
4991 | ||
4992 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
d44570e4 | 4993 | writel((u32)val64, add); |
1da177e4 LT |
4994 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); |
4995 | writel((u32) (val64 >> 32), (add + 4)); | |
4996 | ||
926930b2 SS |
4997 | if (vlan_tag_strip != 1) { |
4998 | val64 = readq(&bar0->rx_pa_cfg); | |
4999 | val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; | |
5000 | writeq(val64, &bar0->rx_pa_cfg); | |
cd0fce03 | 5001 | sp->vlan_strip_flag = 0; |
926930b2 SS |
5002 | } |
5003 | ||
1da177e4 LT |
5004 | val64 = readq(&bar0->mac_cfg); |
5005 | sp->promisc_flg = 1; | |
776bd20f | 5006 | DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n", |
1da177e4 LT |
5007 | dev->name); |
5008 | } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) { | |
5009 | /* Remove the NIC from promiscuous mode */ | |
5010 | add = &bar0->mac_cfg; | |
5011 | val64 = readq(&bar0->mac_cfg); | |
5012 | val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; | |
5013 | ||
5014 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
d44570e4 | 5015 | writel((u32)val64, add); |
1da177e4 LT |
5016 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); |
5017 | writel((u32) (val64 >> 32), (add + 4)); | |
5018 | ||
926930b2 SS |
5019 | if (vlan_tag_strip != 0) { |
5020 | val64 = readq(&bar0->rx_pa_cfg); | |
5021 | val64 |= RX_PA_CFG_STRIP_VLAN_TAG; | |
5022 | writeq(val64, &bar0->rx_pa_cfg); | |
cd0fce03 | 5023 | sp->vlan_strip_flag = 1; |
926930b2 SS |
5024 | } |
5025 | ||
1da177e4 LT |
5026 | val64 = readq(&bar0->mac_cfg); |
5027 | sp->promisc_flg = 0; | |
9e39f7c5 | 5028 | DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name); |
1da177e4 LT |
5029 | } |
5030 | ||
5031 | /* Update individual M_CAST address list */ | |
4cd24eaf JP |
5032 | if ((!sp->m_cast_flg) && netdev_mc_count(dev)) { |
5033 | if (netdev_mc_count(dev) > | |
faa4f796 | 5034 | (config->max_mc_addr - config->max_mac_addr)) { |
9e39f7c5 JP |
5035 | DBG_PRINT(ERR_DBG, |
5036 | "%s: No more Rx filters can be added - " | |
5037 | "please enable ALL_MULTI instead\n", | |
1da177e4 | 5038 | dev->name); |
1da177e4 LT |
5039 | return; |
5040 | } | |
5041 | ||
5042 | prev_cnt = sp->mc_addr_count; | |
4cd24eaf | 5043 | sp->mc_addr_count = netdev_mc_count(dev); |
1da177e4 LT |
5044 | |
5045 | /* Clear out the previous list of Mc in the H/W. */ | |
5046 | for (i = 0; i < prev_cnt; i++) { | |
5047 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), | |
5048 | &bar0->rmac_addr_data0_mem); | |
5049 | writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), | |
d44570e4 | 5050 | &bar0->rmac_addr_data1_mem); |
1da177e4 | 5051 | val64 = RMAC_ADDR_CMD_MEM_WE | |
d44570e4 JP |
5052 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
5053 | RMAC_ADDR_CMD_MEM_OFFSET | |
5054 | (config->mc_start_offset + i); | |
1da177e4 LT |
5055 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
5056 | ||
5057 | /* Wait for command completes */ | |
c92ca04b | 5058 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
5059 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5060 | S2IO_BIT_RESET)) { | |
9e39f7c5 JP |
5061 | DBG_PRINT(ERR_DBG, |
5062 | "%s: Adding Multicasts failed\n", | |
5063 | dev->name); | |
1da177e4 LT |
5064 | return; |
5065 | } | |
5066 | } | |
5067 | ||
5068 | /* Create the new Rx filter list and update the same in H/W. */ | |
5508590c | 5069 | i = 0; |
22bedad3 | 5070 | netdev_for_each_mc_addr(ha, dev) { |
a7a80d5a | 5071 | mac_addr = 0; |
1da177e4 | 5072 | for (j = 0; j < ETH_ALEN; j++) { |
22bedad3 | 5073 | mac_addr |= ha->addr[j]; |
1da177e4 LT |
5074 | mac_addr <<= 8; |
5075 | } | |
5076 | mac_addr >>= 8; | |
5077 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), | |
5078 | &bar0->rmac_addr_data0_mem); | |
5079 | writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), | |
d44570e4 | 5080 | &bar0->rmac_addr_data1_mem); |
1da177e4 | 5081 | val64 = RMAC_ADDR_CMD_MEM_WE | |
d44570e4 JP |
5082 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
5083 | RMAC_ADDR_CMD_MEM_OFFSET | |
5084 | (i + config->mc_start_offset); | |
1da177e4 LT |
5085 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
5086 | ||
5087 | /* Wait for command completes */ | |
c92ca04b | 5088 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
5089 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5090 | S2IO_BIT_RESET)) { | |
9e39f7c5 JP |
5091 | DBG_PRINT(ERR_DBG, |
5092 | "%s: Adding Multicasts failed\n", | |
5093 | dev->name); | |
1da177e4 LT |
5094 | return; |
5095 | } | |
5508590c | 5096 | i++; |
1da177e4 LT |
5097 | } |
5098 | } | |
5099 | } | |
5100 | ||
faa4f796 SH |
5101 | /* read from CAM unicast & multicast addresses and store it in |
5102 | * def_mac_addr structure | |
5103 | */ | |
dac499f9 | 5104 | static void do_s2io_store_unicast_mc(struct s2io_nic *sp) |
faa4f796 SH |
5105 | { |
5106 | int offset; | |
5107 | u64 mac_addr = 0x0; | |
5108 | struct config_param *config = &sp->config; | |
5109 | ||
5110 | /* store unicast & multicast mac addresses */ | |
5111 | for (offset = 0; offset < config->max_mc_addr; offset++) { | |
5112 | mac_addr = do_s2io_read_unicast_mc(sp, offset); | |
5113 | /* if read fails disable the entry */ | |
5114 | if (mac_addr == FAILURE) | |
5115 | mac_addr = S2IO_DISABLE_MAC_ENTRY; | |
5116 | do_s2io_copy_mac_addr(sp, offset, mac_addr); | |
5117 | } | |
5118 | } | |
5119 | ||
5120 | /* restore unicast & multicast MAC to CAM from def_mac_addr structure */ | |
5121 | static void do_s2io_restore_unicast_mc(struct s2io_nic *sp) | |
5122 | { | |
5123 | int offset; | |
5124 | struct config_param *config = &sp->config; | |
5125 | /* restore unicast mac address */ | |
5126 | for (offset = 0; offset < config->max_mac_addr; offset++) | |
5127 | do_s2io_prog_unicast(sp->dev, | |
d44570e4 | 5128 | sp->def_mac_addr[offset].mac_addr); |
faa4f796 SH |
5129 | |
5130 | /* restore multicast mac address */ | |
5131 | for (offset = config->mc_start_offset; | |
d44570e4 | 5132 | offset < config->max_mc_addr; offset++) |
faa4f796 SH |
5133 | do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr); |
5134 | } | |
5135 | ||
5136 | /* add a multicast MAC address to CAM */ | |
5137 | static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr) | |
5138 | { | |
5139 | int i; | |
5140 | u64 mac_addr = 0; | |
5141 | struct config_param *config = &sp->config; | |
5142 | ||
5143 | for (i = 0; i < ETH_ALEN; i++) { | |
5144 | mac_addr <<= 8; | |
5145 | mac_addr |= addr[i]; | |
5146 | } | |
5147 | if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY)) | |
5148 | return SUCCESS; | |
5149 | ||
5150 | /* check if the multicast mac already preset in CAM */ | |
5151 | for (i = config->mc_start_offset; i < config->max_mc_addr; i++) { | |
5152 | u64 tmp64; | |
5153 | tmp64 = do_s2io_read_unicast_mc(sp, i); | |
5154 | if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */ | |
5155 | break; | |
5156 | ||
5157 | if (tmp64 == mac_addr) | |
5158 | return SUCCESS; | |
5159 | } | |
5160 | if (i == config->max_mc_addr) { | |
5161 | DBG_PRINT(ERR_DBG, | |
d44570e4 | 5162 | "CAM full no space left for multicast MAC\n"); |
faa4f796 SH |
5163 | return FAILURE; |
5164 | } | |
5165 | /* Update the internal structure with this new mac address */ | |
5166 | do_s2io_copy_mac_addr(sp, i, mac_addr); | |
5167 | ||
d44570e4 | 5168 | return do_s2io_add_mac(sp, mac_addr, i); |
faa4f796 SH |
5169 | } |
5170 | ||
5171 | /* add MAC address to CAM */ | |
5172 | static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off) | |
2fd37688 SS |
5173 | { |
5174 | u64 val64; | |
5175 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
5176 | ||
5177 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr), | |
d44570e4 | 5178 | &bar0->rmac_addr_data0_mem); |
2fd37688 | 5179 | |
d44570e4 | 5180 | val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
2fd37688 SS |
5181 | RMAC_ADDR_CMD_MEM_OFFSET(off); |
5182 | writeq(val64, &bar0->rmac_addr_cmd_mem); | |
5183 | ||
5184 | /* Wait till command completes */ | |
5185 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | |
d44570e4 JP |
5186 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5187 | S2IO_BIT_RESET)) { | |
faa4f796 | 5188 | DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n"); |
2fd37688 SS |
5189 | return FAILURE; |
5190 | } | |
5191 | return SUCCESS; | |
5192 | } | |
faa4f796 SH |
5193 | /* deletes a specified unicast/multicast mac entry from CAM */ |
5194 | static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr) | |
5195 | { | |
5196 | int offset; | |
5197 | u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64; | |
5198 | struct config_param *config = &sp->config; | |
5199 | ||
5200 | for (offset = 1; | |
d44570e4 | 5201 | offset < config->max_mc_addr; offset++) { |
faa4f796 SH |
5202 | tmp64 = do_s2io_read_unicast_mc(sp, offset); |
5203 | if (tmp64 == addr) { | |
5204 | /* disable the entry by writing 0xffffffffffffULL */ | |
5205 | if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE) | |
5206 | return FAILURE; | |
5207 | /* store the new mac list from CAM */ | |
5208 | do_s2io_store_unicast_mc(sp); | |
5209 | return SUCCESS; | |
5210 | } | |
5211 | } | |
5212 | DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n", | |
d44570e4 | 5213 | (unsigned long long)addr); |
faa4f796 SH |
5214 | return FAILURE; |
5215 | } | |
5216 | ||
5217 | /* read mac entries from CAM */ | |
5218 | static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset) | |
5219 | { | |
5220 | u64 tmp64 = 0xffffffffffff0000ULL, val64; | |
5221 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
5222 | ||
5223 | /* read mac addr */ | |
d44570e4 | 5224 | val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
faa4f796 SH |
5225 | RMAC_ADDR_CMD_MEM_OFFSET(offset); |
5226 | writeq(val64, &bar0->rmac_addr_cmd_mem); | |
5227 | ||
5228 | /* Wait till command completes */ | |
5229 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | |
d44570e4 JP |
5230 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5231 | S2IO_BIT_RESET)) { | |
faa4f796 SH |
5232 | DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n"); |
5233 | return FAILURE; | |
5234 | } | |
5235 | tmp64 = readq(&bar0->rmac_addr_data0_mem); | |
d44570e4 JP |
5236 | |
5237 | return tmp64 >> 16; | |
faa4f796 | 5238 | } |
2fd37688 SS |
5239 | |
5240 | /** | |
5241 | * s2io_set_mac_addr driver entry point | |
5242 | */ | |
faa4f796 | 5243 | |
2fd37688 SS |
5244 | static int s2io_set_mac_addr(struct net_device *dev, void *p) |
5245 | { | |
5246 | struct sockaddr *addr = p; | |
5247 | ||
5248 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 5249 | return -EADDRNOTAVAIL; |
2fd37688 SS |
5250 | |
5251 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
5252 | ||
5253 | /* store the MAC address in CAM */ | |
d44570e4 | 5254 | return do_s2io_prog_unicast(dev, dev->dev_addr); |
2fd37688 | 5255 | } |
1da177e4 | 5256 | /** |
2fd37688 | 5257 | * do_s2io_prog_unicast - Programs the Xframe mac address |
1da177e4 LT |
5258 | * @dev : pointer to the device structure. |
5259 | * @addr: a uchar pointer to the new mac address which is to be set. | |
20346722 | 5260 | * Description : This procedure will program the Xframe to receive |
1da177e4 | 5261 | * frames with new Mac Address |
20346722 | 5262 | * Return value: SUCCESS on success and an appropriate (-)ve integer |
1da177e4 LT |
5263 | * as defined in errno.h file on failure. |
5264 | */ | |
faa4f796 | 5265 | |
2fd37688 | 5266 | static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr) |
1da177e4 | 5267 | { |
4cf1653a | 5268 | struct s2io_nic *sp = netdev_priv(dev); |
2fd37688 | 5269 | register u64 mac_addr = 0, perm_addr = 0; |
1da177e4 | 5270 | int i; |
faa4f796 SH |
5271 | u64 tmp64; |
5272 | struct config_param *config = &sp->config; | |
1da177e4 | 5273 | |
20346722 | 5274 | /* |
d44570e4 JP |
5275 | * Set the new MAC address as the new unicast filter and reflect this |
5276 | * change on the device address registered with the OS. It will be | |
5277 | * at offset 0. | |
5278 | */ | |
1da177e4 LT |
5279 | for (i = 0; i < ETH_ALEN; i++) { |
5280 | mac_addr <<= 8; | |
5281 | mac_addr |= addr[i]; | |
2fd37688 SS |
5282 | perm_addr <<= 8; |
5283 | perm_addr |= sp->def_mac_addr[0].mac_addr[i]; | |
d8d70caf SS |
5284 | } |
5285 | ||
2fd37688 SS |
5286 | /* check if the dev_addr is different than perm_addr */ |
5287 | if (mac_addr == perm_addr) | |
d8d70caf SS |
5288 | return SUCCESS; |
5289 | ||
faa4f796 SH |
5290 | /* check if the mac already preset in CAM */ |
5291 | for (i = 1; i < config->max_mac_addr; i++) { | |
5292 | tmp64 = do_s2io_read_unicast_mc(sp, i); | |
5293 | if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */ | |
5294 | break; | |
5295 | ||
5296 | if (tmp64 == mac_addr) { | |
5297 | DBG_PRINT(INFO_DBG, | |
d44570e4 JP |
5298 | "MAC addr:0x%llx already present in CAM\n", |
5299 | (unsigned long long)mac_addr); | |
faa4f796 SH |
5300 | return SUCCESS; |
5301 | } | |
5302 | } | |
5303 | if (i == config->max_mac_addr) { | |
5304 | DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n"); | |
5305 | return FAILURE; | |
5306 | } | |
d8d70caf | 5307 | /* Update the internal structure with this new mac address */ |
faa4f796 | 5308 | do_s2io_copy_mac_addr(sp, i, mac_addr); |
d44570e4 JP |
5309 | |
5310 | return do_s2io_add_mac(sp, mac_addr, i); | |
1da177e4 LT |
5311 | } |
5312 | ||
5313 | /** | |
20346722 | 5314 | * s2io_ethtool_sset - Sets different link parameters. |
1da177e4 LT |
5315 | * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. |
5316 | * @info: pointer to the structure with parameters given by ethtool to set | |
5317 | * link information. | |
5318 | * Description: | |
20346722 | 5319 | * The function sets different link parameters provided by the user onto |
1da177e4 LT |
5320 | * the NIC. |
5321 | * Return value: | |
5322 | * 0 on success. | |
d44570e4 | 5323 | */ |
1da177e4 LT |
5324 | |
5325 | static int s2io_ethtool_sset(struct net_device *dev, | |
5326 | struct ethtool_cmd *info) | |
5327 | { | |
4cf1653a | 5328 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 | 5329 | if ((info->autoneg == AUTONEG_ENABLE) || |
25db0338 | 5330 | (ethtool_cmd_speed(info) != SPEED_10000) || |
d44570e4 | 5331 | (info->duplex != DUPLEX_FULL)) |
1da177e4 LT |
5332 | return -EINVAL; |
5333 | else { | |
5334 | s2io_close(sp->dev); | |
5335 | s2io_open(sp->dev); | |
5336 | } | |
5337 | ||
5338 | return 0; | |
5339 | } | |
5340 | ||
5341 | /** | |
20346722 | 5342 | * s2io_ethtol_gset - Return link specific information. |
1da177e4 LT |
5343 | * @sp : private member of the device structure, pointer to the |
5344 | * s2io_nic structure. | |
5345 | * @info : pointer to the structure with parameters given by ethtool | |
5346 | * to return link information. | |
5347 | * Description: | |
5348 | * Returns link specific information like speed, duplex etc.. to ethtool. | |
5349 | * Return value : | |
5350 | * return 0 on success. | |
5351 | */ | |
5352 | ||
5353 | static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) | |
5354 | { | |
4cf1653a | 5355 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5356 | info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); |
5357 | info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); | |
5358 | info->port = PORT_FIBRE; | |
1a7eb72b SS |
5359 | |
5360 | /* info->transceiver */ | |
5361 | info->transceiver = XCVR_EXTERNAL; | |
1da177e4 LT |
5362 | |
5363 | if (netif_carrier_ok(sp->dev)) { | |
70739497 | 5364 | ethtool_cmd_speed_set(info, SPEED_10000); |
1da177e4 LT |
5365 | info->duplex = DUPLEX_FULL; |
5366 | } else { | |
70739497 | 5367 | ethtool_cmd_speed_set(info, -1); |
1da177e4 LT |
5368 | info->duplex = -1; |
5369 | } | |
5370 | ||
5371 | info->autoneg = AUTONEG_DISABLE; | |
5372 | return 0; | |
5373 | } | |
5374 | ||
5375 | /** | |
20346722 K |
5376 | * s2io_ethtool_gdrvinfo - Returns driver specific information. |
5377 | * @sp : private member of the device structure, which is a pointer to the | |
1da177e4 LT |
5378 | * s2io_nic structure. |
5379 | * @info : pointer to the structure with parameters given by ethtool to | |
5380 | * return driver information. | |
5381 | * Description: | |
5382 | * Returns driver specefic information like name, version etc.. to ethtool. | |
5383 | * Return value: | |
5384 | * void | |
5385 | */ | |
5386 | ||
5387 | static void s2io_ethtool_gdrvinfo(struct net_device *dev, | |
5388 | struct ethtool_drvinfo *info) | |
5389 | { | |
4cf1653a | 5390 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 | 5391 | |
68aad78c RJ |
5392 | strlcpy(info->driver, s2io_driver_name, sizeof(info->driver)); |
5393 | strlcpy(info->version, s2io_driver_version, sizeof(info->version)); | |
68aad78c | 5394 | strlcpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info)); |
1da177e4 LT |
5395 | info->regdump_len = XENA_REG_SPACE; |
5396 | info->eedump_len = XENA_EEPROM_SPACE; | |
1da177e4 LT |
5397 | } |
5398 | ||
5399 | /** | |
5400 | * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer. | |
20346722 | 5401 | * @sp: private member of the device structure, which is a pointer to the |
1da177e4 | 5402 | * s2io_nic structure. |
20346722 | 5403 | * @regs : pointer to the structure with parameters given by ethtool for |
1da177e4 LT |
5404 | * dumping the registers. |
5405 | * @reg_space: The input argumnet into which all the registers are dumped. | |
5406 | * Description: | |
5407 | * Dumps the entire register space of xFrame NIC into the user given | |
5408 | * buffer area. | |
5409 | * Return value : | |
5410 | * void . | |
d44570e4 | 5411 | */ |
1da177e4 LT |
5412 | |
5413 | static void s2io_ethtool_gregs(struct net_device *dev, | |
5414 | struct ethtool_regs *regs, void *space) | |
5415 | { | |
5416 | int i; | |
5417 | u64 reg; | |
d44570e4 | 5418 | u8 *reg_space = (u8 *)space; |
4cf1653a | 5419 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5420 | |
5421 | regs->len = XENA_REG_SPACE; | |
5422 | regs->version = sp->pdev->subsystem_device; | |
5423 | ||
5424 | for (i = 0; i < regs->len; i += 8) { | |
5425 | reg = readq(sp->bar0 + i); | |
5426 | memcpy((reg_space + i), ®, 8); | |
5427 | } | |
5428 | } | |
5429 | ||
034e3450 | 5430 | /* |
5431 | * s2io_set_led - control NIC led | |
d44570e4 | 5432 | */ |
034e3450 | 5433 | static void s2io_set_led(struct s2io_nic *sp, bool on) |
1da177e4 | 5434 | { |
1ee6dd77 | 5435 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
034e3450 | 5436 | u16 subid = sp->pdev->subsystem_device; |
5437 | u64 val64; | |
1da177e4 | 5438 | |
541ae68f | 5439 | if ((sp->device_type == XFRAME_II_DEVICE) || |
d44570e4 | 5440 | ((subid & 0xFF) >= 0x07)) { |
1da177e4 | 5441 | val64 = readq(&bar0->gpio_control); |
034e3450 | 5442 | if (on) |
5443 | val64 |= GPIO_CTRL_GPIO_0; | |
5444 | else | |
5445 | val64 &= ~GPIO_CTRL_GPIO_0; | |
5446 | ||
1da177e4 LT |
5447 | writeq(val64, &bar0->gpio_control); |
5448 | } else { | |
5449 | val64 = readq(&bar0->adapter_control); | |
034e3450 | 5450 | if (on) |
5451 | val64 |= ADAPTER_LED_ON; | |
5452 | else | |
5453 | val64 &= ~ADAPTER_LED_ON; | |
5454 | ||
1da177e4 LT |
5455 | writeq(val64, &bar0->adapter_control); |
5456 | } | |
5457 | ||
1da177e4 LT |
5458 | } |
5459 | ||
5460 | /** | |
034e3450 | 5461 | * s2io_ethtool_set_led - To physically identify the nic on the system. |
5462 | * @dev : network device | |
5463 | * @state: led setting | |
5464 | * | |
1da177e4 | 5465 | * Description: Used to physically identify the NIC on the system. |
20346722 | 5466 | * The Link LED will blink for a time specified by the user for |
1da177e4 | 5467 | * identification. |
20346722 | 5468 | * NOTE: The Link has to be Up to be able to blink the LED. Hence |
1da177e4 | 5469 | * identification is possible only if it's link is up. |
1da177e4 LT |
5470 | */ |
5471 | ||
034e3450 | 5472 | static int s2io_ethtool_set_led(struct net_device *dev, |
5473 | enum ethtool_phys_id_state state) | |
1da177e4 | 5474 | { |
4cf1653a | 5475 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 5476 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
034e3450 | 5477 | u16 subid = sp->pdev->subsystem_device; |
1da177e4 | 5478 | |
d44570e4 | 5479 | if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) { |
034e3450 | 5480 | u64 val64 = readq(&bar0->adapter_control); |
1da177e4 | 5481 | if (!(val64 & ADAPTER_CNTL_EN)) { |
6cef2b8e | 5482 | pr_err("Adapter Link down, cannot blink LED\n"); |
034e3450 | 5483 | return -EAGAIN; |
1da177e4 LT |
5484 | } |
5485 | } | |
1da177e4 | 5486 | |
034e3450 | 5487 | switch (state) { |
5488 | case ETHTOOL_ID_ACTIVE: | |
5489 | sp->adapt_ctrl_org = readq(&bar0->gpio_control); | |
fce55922 | 5490 | return 1; /* cycle on/off once per second */ |
034e3450 | 5491 | |
5492 | case ETHTOOL_ID_ON: | |
5493 | s2io_set_led(sp, true); | |
5494 | break; | |
5495 | ||
5496 | case ETHTOOL_ID_OFF: | |
5497 | s2io_set_led(sp, false); | |
5498 | break; | |
5499 | ||
5500 | case ETHTOOL_ID_INACTIVE: | |
5501 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) | |
5502 | writeq(sp->adapt_ctrl_org, &bar0->gpio_control); | |
1da177e4 LT |
5503 | } |
5504 | ||
5505 | return 0; | |
5506 | } | |
5507 | ||
0cec35eb | 5508 | static void s2io_ethtool_gringparam(struct net_device *dev, |
d44570e4 | 5509 | struct ethtool_ringparam *ering) |
0cec35eb | 5510 | { |
4cf1653a | 5511 | struct s2io_nic *sp = netdev_priv(dev); |
d44570e4 | 5512 | int i, tx_desc_count = 0, rx_desc_count = 0; |
0cec35eb | 5513 | |
1853e2e1 | 5514 | if (sp->rxd_mode == RXD_MODE_1) { |
0cec35eb | 5515 | ering->rx_max_pending = MAX_RX_DESC_1; |
1853e2e1 JM |
5516 | ering->rx_jumbo_max_pending = MAX_RX_DESC_1; |
5517 | } else { | |
0cec35eb | 5518 | ering->rx_max_pending = MAX_RX_DESC_2; |
1853e2e1 JM |
5519 | ering->rx_jumbo_max_pending = MAX_RX_DESC_2; |
5520 | } | |
0cec35eb SH |
5521 | |
5522 | ering->tx_max_pending = MAX_TX_DESC; | |
8a4bdbaa | 5523 | |
1853e2e1 | 5524 | for (i = 0; i < sp->config.rx_ring_num; i++) |
0cec35eb | 5525 | rx_desc_count += sp->config.rx_cfg[i].num_rxd; |
0cec35eb | 5526 | ering->rx_pending = rx_desc_count; |
0cec35eb | 5527 | ering->rx_jumbo_pending = rx_desc_count; |
1853e2e1 JM |
5528 | |
5529 | for (i = 0; i < sp->config.tx_fifo_num; i++) | |
5530 | tx_desc_count += sp->config.tx_cfg[i].fifo_len; | |
5531 | ering->tx_pending = tx_desc_count; | |
5532 | DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds); | |
0cec35eb SH |
5533 | } |
5534 | ||
1da177e4 LT |
5535 | /** |
5536 | * s2io_ethtool_getpause_data -Pause frame frame generation and reception. | |
20346722 K |
5537 | * @sp : private member of the device structure, which is a pointer to the |
5538 | * s2io_nic structure. | |
1da177e4 LT |
5539 | * @ep : pointer to the structure with pause parameters given by ethtool. |
5540 | * Description: | |
5541 | * Returns the Pause frame generation and reception capability of the NIC. | |
5542 | * Return value: | |
5543 | * void | |
5544 | */ | |
5545 | static void s2io_ethtool_getpause_data(struct net_device *dev, | |
5546 | struct ethtool_pauseparam *ep) | |
5547 | { | |
5548 | u64 val64; | |
4cf1653a | 5549 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 5550 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
5551 | |
5552 | val64 = readq(&bar0->rmac_pause_cfg); | |
5553 | if (val64 & RMAC_PAUSE_GEN_ENABLE) | |
f957bcf0 | 5554 | ep->tx_pause = true; |
1da177e4 | 5555 | if (val64 & RMAC_PAUSE_RX_ENABLE) |
f957bcf0 TK |
5556 | ep->rx_pause = true; |
5557 | ep->autoneg = false; | |
1da177e4 LT |
5558 | } |
5559 | ||
5560 | /** | |
5561 | * s2io_ethtool_setpause_data - set/reset pause frame generation. | |
20346722 | 5562 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 LT |
5563 | * s2io_nic structure. |
5564 | * @ep : pointer to the structure with pause parameters given by ethtool. | |
5565 | * Description: | |
5566 | * It can be used to set or reset Pause frame generation or reception | |
5567 | * support of the NIC. | |
5568 | * Return value: | |
5569 | * int, returns 0 on Success | |
5570 | */ | |
5571 | ||
5572 | static int s2io_ethtool_setpause_data(struct net_device *dev, | |
d44570e4 | 5573 | struct ethtool_pauseparam *ep) |
1da177e4 LT |
5574 | { |
5575 | u64 val64; | |
4cf1653a | 5576 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 5577 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
5578 | |
5579 | val64 = readq(&bar0->rmac_pause_cfg); | |
5580 | if (ep->tx_pause) | |
5581 | val64 |= RMAC_PAUSE_GEN_ENABLE; | |
5582 | else | |
5583 | val64 &= ~RMAC_PAUSE_GEN_ENABLE; | |
5584 | if (ep->rx_pause) | |
5585 | val64 |= RMAC_PAUSE_RX_ENABLE; | |
5586 | else | |
5587 | val64 &= ~RMAC_PAUSE_RX_ENABLE; | |
5588 | writeq(val64, &bar0->rmac_pause_cfg); | |
5589 | return 0; | |
5590 | } | |
5591 | ||
5592 | /** | |
5593 | * read_eeprom - reads 4 bytes of data from user given offset. | |
20346722 | 5594 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 LT |
5595 | * s2io_nic structure. |
5596 | * @off : offset at which the data must be written | |
5597 | * @data : Its an output parameter where the data read at the given | |
20346722 | 5598 | * offset is stored. |
1da177e4 | 5599 | * Description: |
20346722 | 5600 | * Will read 4 bytes of data from the user given offset and return the |
1da177e4 LT |
5601 | * read data. |
5602 | * NOTE: Will allow to read only part of the EEPROM visible through the | |
5603 | * I2C bus. | |
5604 | * Return value: | |
5605 | * -1 on failure and 0 on success. | |
5606 | */ | |
5607 | ||
5608 | #define S2IO_DEV_ID 5 | |
d44570e4 | 5609 | static int read_eeprom(struct s2io_nic *sp, int off, u64 *data) |
1da177e4 LT |
5610 | { |
5611 | int ret = -1; | |
5612 | u32 exit_cnt = 0; | |
5613 | u64 val64; | |
1ee6dd77 | 5614 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 5615 | |
ad4ebed0 | 5616 | if (sp->device_type == XFRAME_I_DEVICE) { |
d44570e4 JP |
5617 | val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | |
5618 | I2C_CONTROL_ADDR(off) | | |
5619 | I2C_CONTROL_BYTE_CNT(0x3) | | |
5620 | I2C_CONTROL_READ | | |
5621 | I2C_CONTROL_CNTL_START; | |
ad4ebed0 | 5622 | SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); |
1da177e4 | 5623 | |
ad4ebed0 | 5624 | while (exit_cnt < 5) { |
5625 | val64 = readq(&bar0->i2c_control); | |
5626 | if (I2C_CONTROL_CNTL_END(val64)) { | |
5627 | *data = I2C_CONTROL_GET_DATA(val64); | |
5628 | ret = 0; | |
5629 | break; | |
5630 | } | |
5631 | msleep(50); | |
5632 | exit_cnt++; | |
1da177e4 | 5633 | } |
1da177e4 LT |
5634 | } |
5635 | ||
ad4ebed0 | 5636 | if (sp->device_type == XFRAME_II_DEVICE) { |
5637 | val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | | |
6aa20a22 | 5638 | SPI_CONTROL_BYTECNT(0x3) | |
ad4ebed0 | 5639 | SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off); |
5640 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5641 | val64 |= SPI_CONTROL_REQ; | |
5642 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5643 | while (exit_cnt < 5) { | |
5644 | val64 = readq(&bar0->spi_control); | |
5645 | if (val64 & SPI_CONTROL_NACK) { | |
5646 | ret = 1; | |
5647 | break; | |
5648 | } else if (val64 & SPI_CONTROL_DONE) { | |
5649 | *data = readq(&bar0->spi_data); | |
5650 | *data &= 0xffffff; | |
5651 | ret = 0; | |
5652 | break; | |
5653 | } | |
5654 | msleep(50); | |
5655 | exit_cnt++; | |
5656 | } | |
5657 | } | |
1da177e4 LT |
5658 | return ret; |
5659 | } | |
5660 | ||
5661 | /** | |
5662 | * write_eeprom - actually writes the relevant part of the data value. | |
5663 | * @sp : private member of the device structure, which is a pointer to the | |
5664 | * s2io_nic structure. | |
5665 | * @off : offset at which the data must be written | |
5666 | * @data : The data that is to be written | |
20346722 | 5667 | * @cnt : Number of bytes of the data that are actually to be written into |
1da177e4 LT |
5668 | * the Eeprom. (max of 3) |
5669 | * Description: | |
5670 | * Actually writes the relevant part of the data value into the Eeprom | |
5671 | * through the I2C bus. | |
5672 | * Return value: | |
5673 | * 0 on success, -1 on failure. | |
5674 | */ | |
5675 | ||
d44570e4 | 5676 | static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt) |
1da177e4 LT |
5677 | { |
5678 | int exit_cnt = 0, ret = -1; | |
5679 | u64 val64; | |
1ee6dd77 | 5680 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 5681 | |
ad4ebed0 | 5682 | if (sp->device_type == XFRAME_I_DEVICE) { |
d44570e4 JP |
5683 | val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | |
5684 | I2C_CONTROL_ADDR(off) | | |
5685 | I2C_CONTROL_BYTE_CNT(cnt) | | |
5686 | I2C_CONTROL_SET_DATA((u32)data) | | |
5687 | I2C_CONTROL_CNTL_START; | |
ad4ebed0 | 5688 | SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); |
5689 | ||
5690 | while (exit_cnt < 5) { | |
5691 | val64 = readq(&bar0->i2c_control); | |
5692 | if (I2C_CONTROL_CNTL_END(val64)) { | |
5693 | if (!(val64 & I2C_CONTROL_NACK)) | |
5694 | ret = 0; | |
5695 | break; | |
5696 | } | |
5697 | msleep(50); | |
5698 | exit_cnt++; | |
5699 | } | |
5700 | } | |
1da177e4 | 5701 | |
ad4ebed0 | 5702 | if (sp->device_type == XFRAME_II_DEVICE) { |
5703 | int write_cnt = (cnt == 8) ? 0 : cnt; | |
d44570e4 | 5704 | writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data); |
ad4ebed0 | 5705 | |
5706 | val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | | |
6aa20a22 | 5707 | SPI_CONTROL_BYTECNT(write_cnt) | |
ad4ebed0 | 5708 | SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off); |
5709 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5710 | val64 |= SPI_CONTROL_REQ; | |
5711 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5712 | while (exit_cnt < 5) { | |
5713 | val64 = readq(&bar0->spi_control); | |
5714 | if (val64 & SPI_CONTROL_NACK) { | |
5715 | ret = 1; | |
5716 | break; | |
5717 | } else if (val64 & SPI_CONTROL_DONE) { | |
1da177e4 | 5718 | ret = 0; |
ad4ebed0 | 5719 | break; |
5720 | } | |
5721 | msleep(50); | |
5722 | exit_cnt++; | |
1da177e4 | 5723 | } |
1da177e4 | 5724 | } |
1da177e4 LT |
5725 | return ret; |
5726 | } | |
1ee6dd77 | 5727 | static void s2io_vpd_read(struct s2io_nic *nic) |
9dc737a7 | 5728 | { |
b41477f3 AR |
5729 | u8 *vpd_data; |
5730 | u8 data; | |
9c179780 | 5731 | int i = 0, cnt, len, fail = 0; |
9dc737a7 | 5732 | int vpd_addr = 0x80; |
ffb5df6c | 5733 | struct swStat *swstats = &nic->mac_control.stats_info->sw_stat; |
9dc737a7 AR |
5734 | |
5735 | if (nic->device_type == XFRAME_II_DEVICE) { | |
5736 | strcpy(nic->product_name, "Xframe II 10GbE network adapter"); | |
5737 | vpd_addr = 0x80; | |
d44570e4 | 5738 | } else { |
9dc737a7 AR |
5739 | strcpy(nic->product_name, "Xframe I 10GbE network adapter"); |
5740 | vpd_addr = 0x50; | |
5741 | } | |
19a60522 | 5742 | strcpy(nic->serial_num, "NOT AVAILABLE"); |
9dc737a7 | 5743 | |
b41477f3 | 5744 | vpd_data = kmalloc(256, GFP_KERNEL); |
c53d4945 | 5745 | if (!vpd_data) { |
ffb5df6c | 5746 | swstats->mem_alloc_fail_cnt++; |
b41477f3 | 5747 | return; |
c53d4945 | 5748 | } |
ffb5df6c | 5749 | swstats->mem_allocated += 256; |
b41477f3 | 5750 | |
d44570e4 | 5751 | for (i = 0; i < 256; i += 4) { |
9dc737a7 AR |
5752 | pci_write_config_byte(nic->pdev, (vpd_addr + 2), i); |
5753 | pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data); | |
5754 | pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0); | |
d44570e4 | 5755 | for (cnt = 0; cnt < 5; cnt++) { |
9dc737a7 AR |
5756 | msleep(2); |
5757 | pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data); | |
5758 | if (data == 0x80) | |
5759 | break; | |
5760 | } | |
5761 | if (cnt >= 5) { | |
5762 | DBG_PRINT(ERR_DBG, "Read of VPD data failed\n"); | |
5763 | fail = 1; | |
5764 | break; | |
5765 | } | |
5766 | pci_read_config_dword(nic->pdev, (vpd_addr + 4), | |
5767 | (u32 *)&vpd_data[i]); | |
5768 | } | |
19a60522 | 5769 | |
d44570e4 | 5770 | if (!fail) { |
19a60522 | 5771 | /* read serial number of adapter */ |
9c179780 | 5772 | for (cnt = 0; cnt < 252; cnt++) { |
d44570e4 | 5773 | if ((vpd_data[cnt] == 'S') && |
9c179780 KV |
5774 | (vpd_data[cnt+1] == 'N')) { |
5775 | len = vpd_data[cnt+2]; | |
5776 | if (len < min(VPD_STRING_LEN, 256-cnt-2)) { | |
5777 | memcpy(nic->serial_num, | |
5778 | &vpd_data[cnt + 3], | |
5779 | len); | |
5780 | memset(nic->serial_num+len, | |
5781 | 0, | |
5782 | VPD_STRING_LEN-len); | |
5783 | break; | |
5784 | } | |
19a60522 SS |
5785 | } |
5786 | } | |
5787 | } | |
5788 | ||
9c179780 KV |
5789 | if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) { |
5790 | len = vpd_data[1]; | |
5791 | memcpy(nic->product_name, &vpd_data[3], len); | |
5792 | nic->product_name[len] = 0; | |
5793 | } | |
b41477f3 | 5794 | kfree(vpd_data); |
ffb5df6c | 5795 | swstats->mem_freed += 256; |
9dc737a7 AR |
5796 | } |
5797 | ||
1da177e4 LT |
5798 | /** |
5799 | * s2io_ethtool_geeprom - reads the value stored in the Eeprom. | |
5800 | * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. | |
20346722 | 5801 | * @eeprom : pointer to the user level structure provided by ethtool, |
1da177e4 LT |
5802 | * containing all relevant information. |
5803 | * @data_buf : user defined value to be written into Eeprom. | |
5804 | * Description: Reads the values stored in the Eeprom at given offset | |
5805 | * for a given length. Stores these values int the input argument data | |
5806 | * buffer 'data_buf' and returns these to the caller (ethtool.) | |
5807 | * Return value: | |
5808 | * int 0 on success | |
5809 | */ | |
5810 | ||
5811 | static int s2io_ethtool_geeprom(struct net_device *dev, | |
d44570e4 | 5812 | struct ethtool_eeprom *eeprom, u8 * data_buf) |
1da177e4 | 5813 | { |
ad4ebed0 | 5814 | u32 i, valid; |
5815 | u64 data; | |
4cf1653a | 5816 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5817 | |
5818 | eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); | |
5819 | ||
5820 | if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE)) | |
5821 | eeprom->len = XENA_EEPROM_SPACE - eeprom->offset; | |
5822 | ||
5823 | for (i = 0; i < eeprom->len; i += 4) { | |
5824 | if (read_eeprom(sp, (eeprom->offset + i), &data)) { | |
5825 | DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n"); | |
5826 | return -EFAULT; | |
5827 | } | |
5828 | valid = INV(data); | |
5829 | memcpy((data_buf + i), &valid, 4); | |
5830 | } | |
5831 | return 0; | |
5832 | } | |
5833 | ||
5834 | /** | |
5835 | * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom | |
5836 | * @sp : private member of the device structure, which is a pointer to the | |
5837 | * s2io_nic structure. | |
20346722 | 5838 | * @eeprom : pointer to the user level structure provided by ethtool, |
1da177e4 LT |
5839 | * containing all relevant information. |
5840 | * @data_buf ; user defined value to be written into Eeprom. | |
5841 | * Description: | |
5842 | * Tries to write the user provided value in the Eeprom, at the offset | |
5843 | * given by the user. | |
5844 | * Return value: | |
5845 | * 0 on success, -EFAULT on failure. | |
5846 | */ | |
5847 | ||
5848 | static int s2io_ethtool_seeprom(struct net_device *dev, | |
5849 | struct ethtool_eeprom *eeprom, | |
d44570e4 | 5850 | u8 *data_buf) |
1da177e4 LT |
5851 | { |
5852 | int len = eeprom->len, cnt = 0; | |
ad4ebed0 | 5853 | u64 valid = 0, data; |
4cf1653a | 5854 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5855 | |
5856 | if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { | |
5857 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 JP |
5858 | "ETHTOOL_WRITE_EEPROM Err: " |
5859 | "Magic value is wrong, it is 0x%x should be 0x%x\n", | |
5860 | (sp->pdev->vendor | (sp->pdev->device << 16)), | |
5861 | eeprom->magic); | |
1da177e4 LT |
5862 | return -EFAULT; |
5863 | } | |
5864 | ||
5865 | while (len) { | |
d44570e4 JP |
5866 | data = (u32)data_buf[cnt] & 0x000000FF; |
5867 | if (data) | |
5868 | valid = (u32)(data << 24); | |
5869 | else | |
1da177e4 LT |
5870 | valid = data; |
5871 | ||
5872 | if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) { | |
5873 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 JP |
5874 | "ETHTOOL_WRITE_EEPROM Err: " |
5875 | "Cannot write into the specified offset\n"); | |
1da177e4 LT |
5876 | return -EFAULT; |
5877 | } | |
5878 | cnt++; | |
5879 | len--; | |
5880 | } | |
5881 | ||
5882 | return 0; | |
5883 | } | |
5884 | ||
5885 | /** | |
20346722 K |
5886 | * s2io_register_test - reads and writes into all clock domains. |
5887 | * @sp : private member of the device structure, which is a pointer to the | |
1da177e4 LT |
5888 | * s2io_nic structure. |
5889 | * @data : variable that returns the result of each of the test conducted b | |
5890 | * by the driver. | |
5891 | * Description: | |
5892 | * Read and write into all clock domains. The NIC has 3 clock domains, | |
5893 | * see that registers in all the three regions are accessible. | |
5894 | * Return value: | |
5895 | * 0 on success. | |
5896 | */ | |
5897 | ||
d44570e4 | 5898 | static int s2io_register_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 | 5899 | { |
1ee6dd77 | 5900 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
ad4ebed0 | 5901 | u64 val64 = 0, exp_val; |
1da177e4 LT |
5902 | int fail = 0; |
5903 | ||
20346722 K |
5904 | val64 = readq(&bar0->pif_rd_swapper_fb); |
5905 | if (val64 != 0x123456789abcdefULL) { | |
1da177e4 | 5906 | fail = 1; |
9e39f7c5 | 5907 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1); |
1da177e4 LT |
5908 | } |
5909 | ||
5910 | val64 = readq(&bar0->rmac_pause_cfg); | |
5911 | if (val64 != 0xc000ffff00000000ULL) { | |
5912 | fail = 1; | |
9e39f7c5 | 5913 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2); |
1da177e4 LT |
5914 | } |
5915 | ||
5916 | val64 = readq(&bar0->rx_queue_cfg); | |
ad4ebed0 | 5917 | if (sp->device_type == XFRAME_II_DEVICE) |
5918 | exp_val = 0x0404040404040404ULL; | |
5919 | else | |
5920 | exp_val = 0x0808080808080808ULL; | |
5921 | if (val64 != exp_val) { | |
1da177e4 | 5922 | fail = 1; |
9e39f7c5 | 5923 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3); |
1da177e4 LT |
5924 | } |
5925 | ||
5926 | val64 = readq(&bar0->xgxs_efifo_cfg); | |
5927 | if (val64 != 0x000000001923141EULL) { | |
5928 | fail = 1; | |
9e39f7c5 | 5929 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4); |
1da177e4 LT |
5930 | } |
5931 | ||
5932 | val64 = 0x5A5A5A5A5A5A5A5AULL; | |
5933 | writeq(val64, &bar0->xmsi_data); | |
5934 | val64 = readq(&bar0->xmsi_data); | |
5935 | if (val64 != 0x5A5A5A5A5A5A5A5AULL) { | |
5936 | fail = 1; | |
9e39f7c5 | 5937 | DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1); |
1da177e4 LT |
5938 | } |
5939 | ||
5940 | val64 = 0xA5A5A5A5A5A5A5A5ULL; | |
5941 | writeq(val64, &bar0->xmsi_data); | |
5942 | val64 = readq(&bar0->xmsi_data); | |
5943 | if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { | |
5944 | fail = 1; | |
9e39f7c5 | 5945 | DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2); |
1da177e4 LT |
5946 | } |
5947 | ||
5948 | *data = fail; | |
ad4ebed0 | 5949 | return fail; |
1da177e4 LT |
5950 | } |
5951 | ||
5952 | /** | |
20346722 | 5953 | * s2io_eeprom_test - to verify that EEprom in the xena can be programmed. |
1da177e4 LT |
5954 | * @sp : private member of the device structure, which is a pointer to the |
5955 | * s2io_nic structure. | |
5956 | * @data:variable that returns the result of each of the test conducted by | |
5957 | * the driver. | |
5958 | * Description: | |
20346722 | 5959 | * Verify that EEPROM in the xena can be programmed using I2C_CONTROL |
1da177e4 LT |
5960 | * register. |
5961 | * Return value: | |
5962 | * 0 on success. | |
5963 | */ | |
5964 | ||
d44570e4 | 5965 | static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 LT |
5966 | { |
5967 | int fail = 0; | |
ad4ebed0 | 5968 | u64 ret_data, org_4F0, org_7F0; |
5969 | u8 saved_4F0 = 0, saved_7F0 = 0; | |
5970 | struct net_device *dev = sp->dev; | |
1da177e4 LT |
5971 | |
5972 | /* Test Write Error at offset 0 */ | |
ad4ebed0 | 5973 | /* Note that SPI interface allows write access to all areas |
5974 | * of EEPROM. Hence doing all negative testing only for Xframe I. | |
5975 | */ | |
5976 | if (sp->device_type == XFRAME_I_DEVICE) | |
5977 | if (!write_eeprom(sp, 0, 0, 3)) | |
5978 | fail = 1; | |
5979 | ||
5980 | /* Save current values at offsets 0x4F0 and 0x7F0 */ | |
5981 | if (!read_eeprom(sp, 0x4F0, &org_4F0)) | |
5982 | saved_4F0 = 1; | |
5983 | if (!read_eeprom(sp, 0x7F0, &org_7F0)) | |
5984 | saved_7F0 = 1; | |
1da177e4 LT |
5985 | |
5986 | /* Test Write at offset 4f0 */ | |
ad4ebed0 | 5987 | if (write_eeprom(sp, 0x4F0, 0x012345, 3)) |
1da177e4 LT |
5988 | fail = 1; |
5989 | if (read_eeprom(sp, 0x4F0, &ret_data)) | |
5990 | fail = 1; | |
5991 | ||
ad4ebed0 | 5992 | if (ret_data != 0x012345) { |
26b7625c | 5993 | DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. " |
d44570e4 JP |
5994 | "Data written %llx Data read %llx\n", |
5995 | dev->name, (unsigned long long)0x12345, | |
5996 | (unsigned long long)ret_data); | |
1da177e4 | 5997 | fail = 1; |
ad4ebed0 | 5998 | } |
1da177e4 LT |
5999 | |
6000 | /* Reset the EEPROM data go FFFF */ | |
ad4ebed0 | 6001 | write_eeprom(sp, 0x4F0, 0xFFFFFF, 3); |
1da177e4 LT |
6002 | |
6003 | /* Test Write Request Error at offset 0x7c */ | |
ad4ebed0 | 6004 | if (sp->device_type == XFRAME_I_DEVICE) |
6005 | if (!write_eeprom(sp, 0x07C, 0, 3)) | |
6006 | fail = 1; | |
1da177e4 | 6007 | |
ad4ebed0 | 6008 | /* Test Write Request at offset 0x7f0 */ |
6009 | if (write_eeprom(sp, 0x7F0, 0x012345, 3)) | |
1da177e4 | 6010 | fail = 1; |
ad4ebed0 | 6011 | if (read_eeprom(sp, 0x7F0, &ret_data)) |
1da177e4 LT |
6012 | fail = 1; |
6013 | ||
ad4ebed0 | 6014 | if (ret_data != 0x012345) { |
26b7625c | 6015 | DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. " |
d44570e4 JP |
6016 | "Data written %llx Data read %llx\n", |
6017 | dev->name, (unsigned long long)0x12345, | |
6018 | (unsigned long long)ret_data); | |
1da177e4 | 6019 | fail = 1; |
ad4ebed0 | 6020 | } |
1da177e4 LT |
6021 | |
6022 | /* Reset the EEPROM data go FFFF */ | |
ad4ebed0 | 6023 | write_eeprom(sp, 0x7F0, 0xFFFFFF, 3); |
1da177e4 | 6024 | |
ad4ebed0 | 6025 | if (sp->device_type == XFRAME_I_DEVICE) { |
6026 | /* Test Write Error at offset 0x80 */ | |
6027 | if (!write_eeprom(sp, 0x080, 0, 3)) | |
6028 | fail = 1; | |
1da177e4 | 6029 | |
ad4ebed0 | 6030 | /* Test Write Error at offset 0xfc */ |
6031 | if (!write_eeprom(sp, 0x0FC, 0, 3)) | |
6032 | fail = 1; | |
1da177e4 | 6033 | |
ad4ebed0 | 6034 | /* Test Write Error at offset 0x100 */ |
6035 | if (!write_eeprom(sp, 0x100, 0, 3)) | |
6036 | fail = 1; | |
1da177e4 | 6037 | |
ad4ebed0 | 6038 | /* Test Write Error at offset 4ec */ |
6039 | if (!write_eeprom(sp, 0x4EC, 0, 3)) | |
6040 | fail = 1; | |
6041 | } | |
6042 | ||
6043 | /* Restore values at offsets 0x4F0 and 0x7F0 */ | |
6044 | if (saved_4F0) | |
6045 | write_eeprom(sp, 0x4F0, org_4F0, 3); | |
6046 | if (saved_7F0) | |
6047 | write_eeprom(sp, 0x7F0, org_7F0, 3); | |
1da177e4 LT |
6048 | |
6049 | *data = fail; | |
ad4ebed0 | 6050 | return fail; |
1da177e4 LT |
6051 | } |
6052 | ||
6053 | /** | |
6054 | * s2io_bist_test - invokes the MemBist test of the card . | |
20346722 | 6055 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 | 6056 | * s2io_nic structure. |
20346722 | 6057 | * @data:variable that returns the result of each of the test conducted by |
1da177e4 LT |
6058 | * the driver. |
6059 | * Description: | |
6060 | * This invokes the MemBist test of the card. We give around | |
6061 | * 2 secs time for the Test to complete. If it's still not complete | |
20346722 | 6062 | * within this peiod, we consider that the test failed. |
1da177e4 LT |
6063 | * Return value: |
6064 | * 0 on success and -1 on failure. | |
6065 | */ | |
6066 | ||
d44570e4 | 6067 | static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 LT |
6068 | { |
6069 | u8 bist = 0; | |
6070 | int cnt = 0, ret = -1; | |
6071 | ||
6072 | pci_read_config_byte(sp->pdev, PCI_BIST, &bist); | |
6073 | bist |= PCI_BIST_START; | |
6074 | pci_write_config_word(sp->pdev, PCI_BIST, bist); | |
6075 | ||
6076 | while (cnt < 20) { | |
6077 | pci_read_config_byte(sp->pdev, PCI_BIST, &bist); | |
6078 | if (!(bist & PCI_BIST_START)) { | |
6079 | *data = (bist & PCI_BIST_CODE_MASK); | |
6080 | ret = 0; | |
6081 | break; | |
6082 | } | |
6083 | msleep(100); | |
6084 | cnt++; | |
6085 | } | |
6086 | ||
6087 | return ret; | |
6088 | } | |
6089 | ||
6090 | /** | |
20346722 K |
6091 | * s2io-link_test - verifies the link state of the nic |
6092 | * @sp ; private member of the device structure, which is a pointer to the | |
1da177e4 LT |
6093 | * s2io_nic structure. |
6094 | * @data: variable that returns the result of each of the test conducted by | |
6095 | * the driver. | |
6096 | * Description: | |
20346722 | 6097 | * The function verifies the link state of the NIC and updates the input |
1da177e4 LT |
6098 | * argument 'data' appropriately. |
6099 | * Return value: | |
6100 | * 0 on success. | |
6101 | */ | |
6102 | ||
d44570e4 | 6103 | static int s2io_link_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 | 6104 | { |
1ee6dd77 | 6105 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
6106 | u64 val64; |
6107 | ||
6108 | val64 = readq(&bar0->adapter_status); | |
d44570e4 | 6109 | if (!(LINK_IS_UP(val64))) |
1da177e4 | 6110 | *data = 1; |
c92ca04b AR |
6111 | else |
6112 | *data = 0; | |
1da177e4 | 6113 | |
b41477f3 | 6114 | return *data; |
1da177e4 LT |
6115 | } |
6116 | ||
6117 | /** | |
20346722 K |
6118 | * s2io_rldram_test - offline test for access to the RldRam chip on the NIC |
6119 | * @sp - private member of the device structure, which is a pointer to the | |
1da177e4 | 6120 | * s2io_nic structure. |
20346722 | 6121 | * @data - variable that returns the result of each of the test |
1da177e4 LT |
6122 | * conducted by the driver. |
6123 | * Description: | |
20346722 | 6124 | * This is one of the offline test that tests the read and write |
1da177e4 LT |
6125 | * access to the RldRam chip on the NIC. |
6126 | * Return value: | |
6127 | * 0 on success. | |
6128 | */ | |
6129 | ||
d44570e4 | 6130 | static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 | 6131 | { |
1ee6dd77 | 6132 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 6133 | u64 val64; |
ad4ebed0 | 6134 | int cnt, iteration = 0, test_fail = 0; |
1da177e4 LT |
6135 | |
6136 | val64 = readq(&bar0->adapter_control); | |
6137 | val64 &= ~ADAPTER_ECC_EN; | |
6138 | writeq(val64, &bar0->adapter_control); | |
6139 | ||
6140 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
6141 | val64 |= MC_RLDRAM_TEST_MODE; | |
ad4ebed0 | 6142 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); |
1da177e4 LT |
6143 | |
6144 | val64 = readq(&bar0->mc_rldram_mrs); | |
6145 | val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; | |
6146 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); | |
6147 | ||
6148 | val64 |= MC_RLDRAM_MRS_ENABLE; | |
6149 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); | |
6150 | ||
6151 | while (iteration < 2) { | |
6152 | val64 = 0x55555555aaaa0000ULL; | |
d44570e4 | 6153 | if (iteration == 1) |
1da177e4 | 6154 | val64 ^= 0xFFFFFFFFFFFF0000ULL; |
1da177e4 LT |
6155 | writeq(val64, &bar0->mc_rldram_test_d0); |
6156 | ||
6157 | val64 = 0xaaaa5a5555550000ULL; | |
d44570e4 | 6158 | if (iteration == 1) |
1da177e4 | 6159 | val64 ^= 0xFFFFFFFFFFFF0000ULL; |
1da177e4 LT |
6160 | writeq(val64, &bar0->mc_rldram_test_d1); |
6161 | ||
6162 | val64 = 0x55aaaaaaaa5a0000ULL; | |
d44570e4 | 6163 | if (iteration == 1) |
1da177e4 | 6164 | val64 ^= 0xFFFFFFFFFFFF0000ULL; |
1da177e4 LT |
6165 | writeq(val64, &bar0->mc_rldram_test_d2); |
6166 | ||
ad4ebed0 | 6167 | val64 = (u64) (0x0000003ffffe0100ULL); |
1da177e4 LT |
6168 | writeq(val64, &bar0->mc_rldram_test_add); |
6169 | ||
d44570e4 JP |
6170 | val64 = MC_RLDRAM_TEST_MODE | |
6171 | MC_RLDRAM_TEST_WRITE | | |
6172 | MC_RLDRAM_TEST_GO; | |
ad4ebed0 | 6173 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); |
1da177e4 LT |
6174 | |
6175 | for (cnt = 0; cnt < 5; cnt++) { | |
6176 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
6177 | if (val64 & MC_RLDRAM_TEST_DONE) | |
6178 | break; | |
6179 | msleep(200); | |
6180 | } | |
6181 | ||
6182 | if (cnt == 5) | |
6183 | break; | |
6184 | ||
ad4ebed0 | 6185 | val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; |
6186 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); | |
1da177e4 LT |
6187 | |
6188 | for (cnt = 0; cnt < 5; cnt++) { | |
6189 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
6190 | if (val64 & MC_RLDRAM_TEST_DONE) | |
6191 | break; | |
6192 | msleep(500); | |
6193 | } | |
6194 | ||
6195 | if (cnt == 5) | |
6196 | break; | |
6197 | ||
6198 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
ad4ebed0 | 6199 | if (!(val64 & MC_RLDRAM_TEST_PASS)) |
6200 | test_fail = 1; | |
1da177e4 LT |
6201 | |
6202 | iteration++; | |
6203 | } | |
6204 | ||
ad4ebed0 | 6205 | *data = test_fail; |
1da177e4 | 6206 | |
ad4ebed0 | 6207 | /* Bring the adapter out of test mode */ |
6208 | SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); | |
6209 | ||
6210 | return test_fail; | |
1da177e4 LT |
6211 | } |
6212 | ||
6213 | /** | |
6214 | * s2io_ethtool_test - conducts 6 tsets to determine the health of card. | |
6215 | * @sp : private member of the device structure, which is a pointer to the | |
6216 | * s2io_nic structure. | |
6217 | * @ethtest : pointer to a ethtool command specific structure that will be | |
6218 | * returned to the user. | |
20346722 | 6219 | * @data : variable that returns the result of each of the test |
1da177e4 LT |
6220 | * conducted by the driver. |
6221 | * Description: | |
6222 | * This function conducts 6 tests ( 4 offline and 2 online) to determine | |
6223 | * the health of the card. | |
6224 | * Return value: | |
6225 | * void | |
6226 | */ | |
6227 | ||
6228 | static void s2io_ethtool_test(struct net_device *dev, | |
6229 | struct ethtool_test *ethtest, | |
d44570e4 | 6230 | uint64_t *data) |
1da177e4 | 6231 | { |
4cf1653a | 6232 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
6233 | int orig_state = netif_running(sp->dev); |
6234 | ||
6235 | if (ethtest->flags == ETH_TEST_FL_OFFLINE) { | |
6236 | /* Offline Tests. */ | |
20346722 | 6237 | if (orig_state) |
1da177e4 | 6238 | s2io_close(sp->dev); |
1da177e4 LT |
6239 | |
6240 | if (s2io_register_test(sp, &data[0])) | |
6241 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6242 | ||
6243 | s2io_reset(sp); | |
1da177e4 LT |
6244 | |
6245 | if (s2io_rldram_test(sp, &data[3])) | |
6246 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6247 | ||
6248 | s2io_reset(sp); | |
1da177e4 LT |
6249 | |
6250 | if (s2io_eeprom_test(sp, &data[1])) | |
6251 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6252 | ||
6253 | if (s2io_bist_test(sp, &data[4])) | |
6254 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6255 | ||
6256 | if (orig_state) | |
6257 | s2io_open(sp->dev); | |
6258 | ||
6259 | data[2] = 0; | |
6260 | } else { | |
6261 | /* Online Tests. */ | |
6262 | if (!orig_state) { | |
d44570e4 | 6263 | DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n", |
1da177e4 LT |
6264 | dev->name); |
6265 | data[0] = -1; | |
6266 | data[1] = -1; | |
6267 | data[2] = -1; | |
6268 | data[3] = -1; | |
6269 | data[4] = -1; | |
6270 | } | |
6271 | ||
6272 | if (s2io_link_test(sp, &data[2])) | |
6273 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6274 | ||
6275 | data[0] = 0; | |
6276 | data[1] = 0; | |
6277 | data[3] = 0; | |
6278 | data[4] = 0; | |
6279 | } | |
6280 | } | |
6281 | ||
6282 | static void s2io_get_ethtool_stats(struct net_device *dev, | |
6283 | struct ethtool_stats *estats, | |
d44570e4 | 6284 | u64 *tmp_stats) |
1da177e4 | 6285 | { |
8116f3cf | 6286 | int i = 0, k; |
4cf1653a | 6287 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c JP |
6288 | struct stat_block *stats = sp->mac_control.stats_info; |
6289 | struct swStat *swstats = &stats->sw_stat; | |
6290 | struct xpakStat *xstats = &stats->xpak_stat; | |
1da177e4 | 6291 | |
7ba013ac | 6292 | s2io_updt_stats(sp); |
541ae68f | 6293 | tmp_stats[i++] = |
ffb5df6c JP |
6294 | (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 | |
6295 | le32_to_cpu(stats->tmac_frms); | |
541ae68f | 6296 | tmp_stats[i++] = |
ffb5df6c JP |
6297 | (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 | |
6298 | le32_to_cpu(stats->tmac_data_octets); | |
6299 | tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms); | |
541ae68f | 6300 | tmp_stats[i++] = |
ffb5df6c JP |
6301 | (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 | |
6302 | le32_to_cpu(stats->tmac_mcst_frms); | |
541ae68f | 6303 | tmp_stats[i++] = |
ffb5df6c JP |
6304 | (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 | |
6305 | le32_to_cpu(stats->tmac_bcst_frms); | |
6306 | tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms); | |
bd1034f0 | 6307 | tmp_stats[i++] = |
ffb5df6c JP |
6308 | (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 | |
6309 | le32_to_cpu(stats->tmac_ttl_octets); | |
bd1034f0 | 6310 | tmp_stats[i++] = |
ffb5df6c JP |
6311 | (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 | |
6312 | le32_to_cpu(stats->tmac_ucst_frms); | |
d44570e4 | 6313 | tmp_stats[i++] = |
ffb5df6c JP |
6314 | (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 | |
6315 | le32_to_cpu(stats->tmac_nucst_frms); | |
541ae68f | 6316 | tmp_stats[i++] = |
ffb5df6c JP |
6317 | (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 | |
6318 | le32_to_cpu(stats->tmac_any_err_frms); | |
6319 | tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets); | |
6320 | tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets); | |
541ae68f | 6321 | tmp_stats[i++] = |
ffb5df6c JP |
6322 | (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 | |
6323 | le32_to_cpu(stats->tmac_vld_ip); | |
541ae68f | 6324 | tmp_stats[i++] = |
ffb5df6c JP |
6325 | (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 | |
6326 | le32_to_cpu(stats->tmac_drop_ip); | |
541ae68f | 6327 | tmp_stats[i++] = |
ffb5df6c JP |
6328 | (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 | |
6329 | le32_to_cpu(stats->tmac_icmp); | |
541ae68f | 6330 | tmp_stats[i++] = |
ffb5df6c JP |
6331 | (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 | |
6332 | le32_to_cpu(stats->tmac_rst_tcp); | |
6333 | tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp); | |
6334 | tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 | | |
6335 | le32_to_cpu(stats->tmac_udp); | |
541ae68f | 6336 | tmp_stats[i++] = |
ffb5df6c JP |
6337 | (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 | |
6338 | le32_to_cpu(stats->rmac_vld_frms); | |
541ae68f | 6339 | tmp_stats[i++] = |
ffb5df6c JP |
6340 | (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 | |
6341 | le32_to_cpu(stats->rmac_data_octets); | |
6342 | tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms); | |
6343 | tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms); | |
541ae68f | 6344 | tmp_stats[i++] = |
ffb5df6c JP |
6345 | (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 | |
6346 | le32_to_cpu(stats->rmac_vld_mcst_frms); | |
541ae68f | 6347 | tmp_stats[i++] = |
ffb5df6c JP |
6348 | (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 | |
6349 | le32_to_cpu(stats->rmac_vld_bcst_frms); | |
6350 | tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms); | |
6351 | tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms); | |
6352 | tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms); | |
6353 | tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms); | |
6354 | tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms); | |
d44570e4 | 6355 | tmp_stats[i++] = |
ffb5df6c JP |
6356 | (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 | |
6357 | le32_to_cpu(stats->rmac_ttl_octets); | |
bd1034f0 | 6358 | tmp_stats[i++] = |
ffb5df6c JP |
6359 | (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32 |
6360 | | le32_to_cpu(stats->rmac_accepted_ucst_frms); | |
d44570e4 | 6361 | tmp_stats[i++] = |
ffb5df6c JP |
6362 | (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow) |
6363 | << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms); | |
541ae68f | 6364 | tmp_stats[i++] = |
ffb5df6c JP |
6365 | (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 | |
6366 | le32_to_cpu(stats->rmac_discarded_frms); | |
d44570e4 | 6367 | tmp_stats[i++] = |
ffb5df6c JP |
6368 | (u64)le32_to_cpu(stats->rmac_drop_events_oflow) |
6369 | << 32 | le32_to_cpu(stats->rmac_drop_events); | |
6370 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets); | |
6371 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms); | |
541ae68f | 6372 | tmp_stats[i++] = |
ffb5df6c JP |
6373 | (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 | |
6374 | le32_to_cpu(stats->rmac_usized_frms); | |
541ae68f | 6375 | tmp_stats[i++] = |
ffb5df6c JP |
6376 | (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 | |
6377 | le32_to_cpu(stats->rmac_osized_frms); | |
541ae68f | 6378 | tmp_stats[i++] = |
ffb5df6c JP |
6379 | (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 | |
6380 | le32_to_cpu(stats->rmac_frag_frms); | |
541ae68f | 6381 | tmp_stats[i++] = |
ffb5df6c JP |
6382 | (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 | |
6383 | le32_to_cpu(stats->rmac_jabber_frms); | |
6384 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms); | |
6385 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms); | |
6386 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms); | |
6387 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms); | |
6388 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms); | |
6389 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms); | |
bd1034f0 | 6390 | tmp_stats[i++] = |
ffb5df6c JP |
6391 | (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 | |
6392 | le32_to_cpu(stats->rmac_ip); | |
6393 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets); | |
6394 | tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip); | |
bd1034f0 | 6395 | tmp_stats[i++] = |
ffb5df6c JP |
6396 | (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 | |
6397 | le32_to_cpu(stats->rmac_drop_ip); | |
bd1034f0 | 6398 | tmp_stats[i++] = |
ffb5df6c JP |
6399 | (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 | |
6400 | le32_to_cpu(stats->rmac_icmp); | |
6401 | tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp); | |
bd1034f0 | 6402 | tmp_stats[i++] = |
ffb5df6c JP |
6403 | (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 | |
6404 | le32_to_cpu(stats->rmac_udp); | |
541ae68f | 6405 | tmp_stats[i++] = |
ffb5df6c JP |
6406 | (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 | |
6407 | le32_to_cpu(stats->rmac_err_drp_udp); | |
6408 | tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym); | |
6409 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0); | |
6410 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1); | |
6411 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2); | |
6412 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3); | |
6413 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4); | |
6414 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5); | |
6415 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6); | |
6416 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7); | |
6417 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0); | |
6418 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1); | |
6419 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2); | |
6420 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3); | |
6421 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4); | |
6422 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5); | |
6423 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6); | |
6424 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7); | |
541ae68f | 6425 | tmp_stats[i++] = |
ffb5df6c JP |
6426 | (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 | |
6427 | le32_to_cpu(stats->rmac_pause_cnt); | |
6428 | tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt); | |
6429 | tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt); | |
541ae68f | 6430 | tmp_stats[i++] = |
ffb5df6c JP |
6431 | (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 | |
6432 | le32_to_cpu(stats->rmac_accepted_ip); | |
6433 | tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp); | |
6434 | tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt); | |
6435 | tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt); | |
6436 | tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt); | |
6437 | tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt); | |
6438 | tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt); | |
6439 | tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt); | |
6440 | tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt); | |
6441 | tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt); | |
6442 | tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt); | |
6443 | tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt); | |
6444 | tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt); | |
6445 | tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt); | |
6446 | tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt); | |
6447 | tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt); | |
6448 | tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt); | |
6449 | tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt); | |
6450 | tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt); | |
6451 | tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt); | |
fa1f0cb3 SS |
6452 | |
6453 | /* Enhanced statistics exist only for Hercules */ | |
d44570e4 | 6454 | if (sp->device_type == XFRAME_II_DEVICE) { |
fa1f0cb3 | 6455 | tmp_stats[i++] = |
ffb5df6c | 6456 | le64_to_cpu(stats->rmac_ttl_1519_4095_frms); |
fa1f0cb3 | 6457 | tmp_stats[i++] = |
ffb5df6c | 6458 | le64_to_cpu(stats->rmac_ttl_4096_8191_frms); |
fa1f0cb3 | 6459 | tmp_stats[i++] = |
ffb5df6c JP |
6460 | le64_to_cpu(stats->rmac_ttl_8192_max_frms); |
6461 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms); | |
6462 | tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms); | |
6463 | tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms); | |
6464 | tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms); | |
6465 | tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms); | |
6466 | tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard); | |
6467 | tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard); | |
6468 | tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard); | |
6469 | tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard); | |
6470 | tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard); | |
6471 | tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard); | |
6472 | tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard); | |
6473 | tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt); | |
fa1f0cb3 SS |
6474 | } |
6475 | ||
7ba013ac | 6476 | tmp_stats[i++] = 0; |
ffb5df6c JP |
6477 | tmp_stats[i++] = swstats->single_ecc_errs; |
6478 | tmp_stats[i++] = swstats->double_ecc_errs; | |
6479 | tmp_stats[i++] = swstats->parity_err_cnt; | |
6480 | tmp_stats[i++] = swstats->serious_err_cnt; | |
6481 | tmp_stats[i++] = swstats->soft_reset_cnt; | |
6482 | tmp_stats[i++] = swstats->fifo_full_cnt; | |
8116f3cf | 6483 | for (k = 0; k < MAX_RX_RINGS; k++) |
ffb5df6c JP |
6484 | tmp_stats[i++] = swstats->ring_full_cnt[k]; |
6485 | tmp_stats[i++] = xstats->alarm_transceiver_temp_high; | |
6486 | tmp_stats[i++] = xstats->alarm_transceiver_temp_low; | |
6487 | tmp_stats[i++] = xstats->alarm_laser_bias_current_high; | |
6488 | tmp_stats[i++] = xstats->alarm_laser_bias_current_low; | |
6489 | tmp_stats[i++] = xstats->alarm_laser_output_power_high; | |
6490 | tmp_stats[i++] = xstats->alarm_laser_output_power_low; | |
6491 | tmp_stats[i++] = xstats->warn_transceiver_temp_high; | |
6492 | tmp_stats[i++] = xstats->warn_transceiver_temp_low; | |
6493 | tmp_stats[i++] = xstats->warn_laser_bias_current_high; | |
6494 | tmp_stats[i++] = xstats->warn_laser_bias_current_low; | |
6495 | tmp_stats[i++] = xstats->warn_laser_output_power_high; | |
6496 | tmp_stats[i++] = xstats->warn_laser_output_power_low; | |
6497 | tmp_stats[i++] = swstats->clubbed_frms_cnt; | |
6498 | tmp_stats[i++] = swstats->sending_both; | |
6499 | tmp_stats[i++] = swstats->outof_sequence_pkts; | |
6500 | tmp_stats[i++] = swstats->flush_max_pkts; | |
6501 | if (swstats->num_aggregations) { | |
6502 | u64 tmp = swstats->sum_avg_pkts_aggregated; | |
bd1034f0 | 6503 | int count = 0; |
6aa20a22 | 6504 | /* |
bd1034f0 AR |
6505 | * Since 64-bit divide does not work on all platforms, |
6506 | * do repeated subtraction. | |
6507 | */ | |
ffb5df6c JP |
6508 | while (tmp >= swstats->num_aggregations) { |
6509 | tmp -= swstats->num_aggregations; | |
bd1034f0 AR |
6510 | count++; |
6511 | } | |
6512 | tmp_stats[i++] = count; | |
d44570e4 | 6513 | } else |
bd1034f0 | 6514 | tmp_stats[i++] = 0; |
ffb5df6c JP |
6515 | tmp_stats[i++] = swstats->mem_alloc_fail_cnt; |
6516 | tmp_stats[i++] = swstats->pci_map_fail_cnt; | |
6517 | tmp_stats[i++] = swstats->watchdog_timer_cnt; | |
6518 | tmp_stats[i++] = swstats->mem_allocated; | |
6519 | tmp_stats[i++] = swstats->mem_freed; | |
6520 | tmp_stats[i++] = swstats->link_up_cnt; | |
6521 | tmp_stats[i++] = swstats->link_down_cnt; | |
6522 | tmp_stats[i++] = swstats->link_up_time; | |
6523 | tmp_stats[i++] = swstats->link_down_time; | |
6524 | ||
6525 | tmp_stats[i++] = swstats->tx_buf_abort_cnt; | |
6526 | tmp_stats[i++] = swstats->tx_desc_abort_cnt; | |
6527 | tmp_stats[i++] = swstats->tx_parity_err_cnt; | |
6528 | tmp_stats[i++] = swstats->tx_link_loss_cnt; | |
6529 | tmp_stats[i++] = swstats->tx_list_proc_err_cnt; | |
6530 | ||
6531 | tmp_stats[i++] = swstats->rx_parity_err_cnt; | |
6532 | tmp_stats[i++] = swstats->rx_abort_cnt; | |
6533 | tmp_stats[i++] = swstats->rx_parity_abort_cnt; | |
6534 | tmp_stats[i++] = swstats->rx_rda_fail_cnt; | |
6535 | tmp_stats[i++] = swstats->rx_unkn_prot_cnt; | |
6536 | tmp_stats[i++] = swstats->rx_fcs_err_cnt; | |
6537 | tmp_stats[i++] = swstats->rx_buf_size_err_cnt; | |
6538 | tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt; | |
6539 | tmp_stats[i++] = swstats->rx_unkn_err_cnt; | |
6540 | tmp_stats[i++] = swstats->tda_err_cnt; | |
6541 | tmp_stats[i++] = swstats->pfc_err_cnt; | |
6542 | tmp_stats[i++] = swstats->pcc_err_cnt; | |
6543 | tmp_stats[i++] = swstats->tti_err_cnt; | |
6544 | tmp_stats[i++] = swstats->tpa_err_cnt; | |
6545 | tmp_stats[i++] = swstats->sm_err_cnt; | |
6546 | tmp_stats[i++] = swstats->lso_err_cnt; | |
6547 | tmp_stats[i++] = swstats->mac_tmac_err_cnt; | |
6548 | tmp_stats[i++] = swstats->mac_rmac_err_cnt; | |
6549 | tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt; | |
6550 | tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt; | |
6551 | tmp_stats[i++] = swstats->rc_err_cnt; | |
6552 | tmp_stats[i++] = swstats->prc_pcix_err_cnt; | |
6553 | tmp_stats[i++] = swstats->rpa_err_cnt; | |
6554 | tmp_stats[i++] = swstats->rda_err_cnt; | |
6555 | tmp_stats[i++] = swstats->rti_err_cnt; | |
6556 | tmp_stats[i++] = swstats->mc_err_cnt; | |
1da177e4 LT |
6557 | } |
6558 | ||
ac1f60db | 6559 | static int s2io_ethtool_get_regs_len(struct net_device *dev) |
1da177e4 | 6560 | { |
d44570e4 | 6561 | return XENA_REG_SPACE; |
1da177e4 LT |
6562 | } |
6563 | ||
6564 | ||
ac1f60db | 6565 | static int s2io_get_eeprom_len(struct net_device *dev) |
1da177e4 | 6566 | { |
d44570e4 | 6567 | return XENA_EEPROM_SPACE; |
1da177e4 LT |
6568 | } |
6569 | ||
b9f2c044 | 6570 | static int s2io_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 6571 | { |
4cf1653a | 6572 | struct s2io_nic *sp = netdev_priv(dev); |
b9f2c044 JG |
6573 | |
6574 | switch (sset) { | |
6575 | case ETH_SS_TEST: | |
6576 | return S2IO_TEST_LEN; | |
6577 | case ETH_SS_STATS: | |
d44570e4 | 6578 | switch (sp->device_type) { |
b9f2c044 JG |
6579 | case XFRAME_I_DEVICE: |
6580 | return XFRAME_I_STAT_LEN; | |
6581 | case XFRAME_II_DEVICE: | |
6582 | return XFRAME_II_STAT_LEN; | |
6583 | default: | |
6584 | return 0; | |
6585 | } | |
6586 | default: | |
6587 | return -EOPNOTSUPP; | |
6588 | } | |
1da177e4 | 6589 | } |
ac1f60db AB |
6590 | |
6591 | static void s2io_ethtool_get_strings(struct net_device *dev, | |
d44570e4 | 6592 | u32 stringset, u8 *data) |
1da177e4 | 6593 | { |
fa1f0cb3 | 6594 | int stat_size = 0; |
4cf1653a | 6595 | struct s2io_nic *sp = netdev_priv(dev); |
fa1f0cb3 | 6596 | |
1da177e4 LT |
6597 | switch (stringset) { |
6598 | case ETH_SS_TEST: | |
6599 | memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN); | |
6600 | break; | |
6601 | case ETH_SS_STATS: | |
fa1f0cb3 | 6602 | stat_size = sizeof(ethtool_xena_stats_keys); |
d44570e4 JP |
6603 | memcpy(data, ðtool_xena_stats_keys, stat_size); |
6604 | if (sp->device_type == XFRAME_II_DEVICE) { | |
fa1f0cb3 | 6605 | memcpy(data + stat_size, |
d44570e4 JP |
6606 | ðtool_enhanced_stats_keys, |
6607 | sizeof(ethtool_enhanced_stats_keys)); | |
fa1f0cb3 SS |
6608 | stat_size += sizeof(ethtool_enhanced_stats_keys); |
6609 | } | |
6610 | ||
6611 | memcpy(data + stat_size, ðtool_driver_stats_keys, | |
d44570e4 | 6612 | sizeof(ethtool_driver_stats_keys)); |
1da177e4 LT |
6613 | } |
6614 | } | |
1da177e4 | 6615 | |
c8f44aff | 6616 | static int s2io_set_features(struct net_device *dev, netdev_features_t features) |
958de193 JM |
6617 | { |
6618 | struct s2io_nic *sp = netdev_priv(dev); | |
c8f44aff | 6619 | netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO; |
958de193 JM |
6620 | |
6621 | if (changed && netif_running(dev)) { | |
b437a8cc MM |
6622 | int rc; |
6623 | ||
958de193 JM |
6624 | s2io_stop_all_tx_queue(sp); |
6625 | s2io_card_down(sp); | |
b437a8cc | 6626 | dev->features = features; |
958de193 JM |
6627 | rc = s2io_card_up(sp); |
6628 | if (rc) | |
6629 | s2io_reset(sp); | |
6630 | else | |
6631 | s2io_start_all_tx_queue(sp); | |
b437a8cc MM |
6632 | |
6633 | return rc ? rc : 1; | |
958de193 JM |
6634 | } |
6635 | ||
b437a8cc | 6636 | return 0; |
958de193 JM |
6637 | } |
6638 | ||
7282d491 | 6639 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
6640 | .get_settings = s2io_ethtool_gset, |
6641 | .set_settings = s2io_ethtool_sset, | |
6642 | .get_drvinfo = s2io_ethtool_gdrvinfo, | |
6643 | .get_regs_len = s2io_ethtool_get_regs_len, | |
6644 | .get_regs = s2io_ethtool_gregs, | |
6645 | .get_link = ethtool_op_get_link, | |
6646 | .get_eeprom_len = s2io_get_eeprom_len, | |
6647 | .get_eeprom = s2io_ethtool_geeprom, | |
6648 | .set_eeprom = s2io_ethtool_seeprom, | |
0cec35eb | 6649 | .get_ringparam = s2io_ethtool_gringparam, |
1da177e4 LT |
6650 | .get_pauseparam = s2io_ethtool_getpause_data, |
6651 | .set_pauseparam = s2io_ethtool_setpause_data, | |
1da177e4 LT |
6652 | .self_test = s2io_ethtool_test, |
6653 | .get_strings = s2io_ethtool_get_strings, | |
034e3450 | 6654 | .set_phys_id = s2io_ethtool_set_led, |
b9f2c044 JG |
6655 | .get_ethtool_stats = s2io_get_ethtool_stats, |
6656 | .get_sset_count = s2io_get_sset_count, | |
1da177e4 LT |
6657 | }; |
6658 | ||
6659 | /** | |
20346722 | 6660 | * s2io_ioctl - Entry point for the Ioctl |
1da177e4 LT |
6661 | * @dev : Device pointer. |
6662 | * @ifr : An IOCTL specefic structure, that can contain a pointer to | |
6663 | * a proprietary structure used to pass information to the driver. | |
6664 | * @cmd : This is used to distinguish between the different commands that | |
6665 | * can be passed to the IOCTL functions. | |
6666 | * Description: | |
20346722 K |
6667 | * Currently there are no special functionality supported in IOCTL, hence |
6668 | * function always return EOPNOTSUPPORTED | |
1da177e4 LT |
6669 | */ |
6670 | ||
ac1f60db | 6671 | static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1da177e4 LT |
6672 | { |
6673 | return -EOPNOTSUPP; | |
6674 | } | |
6675 | ||
6676 | /** | |
6677 | * s2io_change_mtu - entry point to change MTU size for the device. | |
6678 | * @dev : device pointer. | |
6679 | * @new_mtu : the new MTU size for the device. | |
6680 | * Description: A driver entry point to change MTU size for the device. | |
6681 | * Before changing the MTU the device must be stopped. | |
6682 | * Return value: | |
6683 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
6684 | * file on failure. | |
6685 | */ | |
6686 | ||
ac1f60db | 6687 | static int s2io_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 6688 | { |
4cf1653a | 6689 | struct s2io_nic *sp = netdev_priv(dev); |
9f74ffde | 6690 | int ret = 0; |
1da177e4 LT |
6691 | |
6692 | if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { | |
d44570e4 | 6693 | DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name); |
1da177e4 LT |
6694 | return -EPERM; |
6695 | } | |
6696 | ||
1da177e4 | 6697 | dev->mtu = new_mtu; |
d8892c6e | 6698 | if (netif_running(dev)) { |
3a3d5756 | 6699 | s2io_stop_all_tx_queue(sp); |
e6a8fee2 | 6700 | s2io_card_down(sp); |
9f74ffde SH |
6701 | ret = s2io_card_up(sp); |
6702 | if (ret) { | |
d8892c6e | 6703 | DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", |
b39d66a8 | 6704 | __func__); |
9f74ffde | 6705 | return ret; |
d8892c6e | 6706 | } |
3a3d5756 | 6707 | s2io_wake_all_tx_queue(sp); |
d8892c6e | 6708 | } else { /* Device is down */ |
1ee6dd77 | 6709 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
d8892c6e K |
6710 | u64 val64 = new_mtu; |
6711 | ||
6712 | writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); | |
6713 | } | |
1da177e4 | 6714 | |
9f74ffde | 6715 | return ret; |
1da177e4 LT |
6716 | } |
6717 | ||
1da177e4 LT |
6718 | /** |
6719 | * s2io_set_link - Set the LInk status | |
6720 | * @data: long pointer to device private structue | |
6721 | * Description: Sets the link status for the adapter | |
6722 | */ | |
6723 | ||
c4028958 | 6724 | static void s2io_set_link(struct work_struct *work) |
1da177e4 | 6725 | { |
d44570e4 JP |
6726 | struct s2io_nic *nic = container_of(work, struct s2io_nic, |
6727 | set_link_task); | |
1da177e4 | 6728 | struct net_device *dev = nic->dev; |
1ee6dd77 | 6729 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 LT |
6730 | register u64 val64; |
6731 | u16 subid; | |
6732 | ||
22747d6b FR |
6733 | rtnl_lock(); |
6734 | ||
6735 | if (!netif_running(dev)) | |
6736 | goto out_unlock; | |
6737 | ||
92b84437 | 6738 | if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) { |
1da177e4 | 6739 | /* The card is being reset, no point doing anything */ |
22747d6b | 6740 | goto out_unlock; |
1da177e4 LT |
6741 | } |
6742 | ||
6743 | subid = nic->pdev->subsystem_device; | |
a371a07d K |
6744 | if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { |
6745 | /* | |
6746 | * Allow a small delay for the NICs self initiated | |
6747 | * cleanup to complete. | |
6748 | */ | |
6749 | msleep(100); | |
6750 | } | |
1da177e4 LT |
6751 | |
6752 | val64 = readq(&bar0->adapter_status); | |
19a60522 SS |
6753 | if (LINK_IS_UP(val64)) { |
6754 | if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { | |
6755 | if (verify_xena_quiescence(nic)) { | |
6756 | val64 = readq(&bar0->adapter_control); | |
6757 | val64 |= ADAPTER_CNTL_EN; | |
1da177e4 | 6758 | writeq(val64, &bar0->adapter_control); |
19a60522 | 6759 | if (CARDS_WITH_FAULTY_LINK_INDICATORS( |
d44570e4 | 6760 | nic->device_type, subid)) { |
19a60522 SS |
6761 | val64 = readq(&bar0->gpio_control); |
6762 | val64 |= GPIO_CTRL_GPIO_0; | |
6763 | writeq(val64, &bar0->gpio_control); | |
6764 | val64 = readq(&bar0->gpio_control); | |
6765 | } else { | |
6766 | val64 |= ADAPTER_LED_ON; | |
6767 | writeq(val64, &bar0->adapter_control); | |
a371a07d | 6768 | } |
f957bcf0 | 6769 | nic->device_enabled_once = true; |
19a60522 | 6770 | } else { |
9e39f7c5 JP |
6771 | DBG_PRINT(ERR_DBG, |
6772 | "%s: Error: device is not Quiescent\n", | |
6773 | dev->name); | |
3a3d5756 | 6774 | s2io_stop_all_tx_queue(nic); |
1da177e4 | 6775 | } |
19a60522 | 6776 | } |
92c48799 SS |
6777 | val64 = readq(&bar0->adapter_control); |
6778 | val64 |= ADAPTER_LED_ON; | |
6779 | writeq(val64, &bar0->adapter_control); | |
6780 | s2io_link(nic, LINK_UP); | |
19a60522 SS |
6781 | } else { |
6782 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, | |
6783 | subid)) { | |
6784 | val64 = readq(&bar0->gpio_control); | |
6785 | val64 &= ~GPIO_CTRL_GPIO_0; | |
6786 | writeq(val64, &bar0->gpio_control); | |
6787 | val64 = readq(&bar0->gpio_control); | |
1da177e4 | 6788 | } |
92c48799 SS |
6789 | /* turn off LED */ |
6790 | val64 = readq(&bar0->adapter_control); | |
d44570e4 | 6791 | val64 = val64 & (~ADAPTER_LED_ON); |
92c48799 | 6792 | writeq(val64, &bar0->adapter_control); |
19a60522 | 6793 | s2io_link(nic, LINK_DOWN); |
1da177e4 | 6794 | } |
92b84437 | 6795 | clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state)); |
22747d6b FR |
6796 | |
6797 | out_unlock: | |
d8d70caf | 6798 | rtnl_unlock(); |
1da177e4 LT |
6799 | } |
6800 | ||
1ee6dd77 | 6801 | static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp, |
d44570e4 JP |
6802 | struct buffAdd *ba, |
6803 | struct sk_buff **skb, u64 *temp0, u64 *temp1, | |
6804 | u64 *temp2, int size) | |
5d3213cc AR |
6805 | { |
6806 | struct net_device *dev = sp->dev; | |
491abf25 | 6807 | struct swStat *stats = &sp->mac_control.stats_info->sw_stat; |
5d3213cc AR |
6808 | |
6809 | if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) { | |
6d517a27 | 6810 | struct RxD1 *rxdp1 = (struct RxD1 *)rxdp; |
5d3213cc AR |
6811 | /* allocate skb */ |
6812 | if (*skb) { | |
6813 | DBG_PRINT(INFO_DBG, "SKB is not NULL\n"); | |
6814 | /* | |
6815 | * As Rx frame are not going to be processed, | |
6816 | * using same mapped address for the Rxd | |
6817 | * buffer pointer | |
6818 | */ | |
6d517a27 | 6819 | rxdp1->Buffer0_ptr = *temp0; |
5d3213cc | 6820 | } else { |
c056b734 | 6821 | *skb = netdev_alloc_skb(dev, size); |
5d3213cc | 6822 | if (!(*skb)) { |
9e39f7c5 JP |
6823 | DBG_PRINT(INFO_DBG, |
6824 | "%s: Out of memory to allocate %s\n", | |
6825 | dev->name, "1 buf mode SKBs"); | |
ffb5df6c | 6826 | stats->mem_alloc_fail_cnt++; |
5d3213cc AR |
6827 | return -ENOMEM ; |
6828 | } | |
ffb5df6c | 6829 | stats->mem_allocated += (*skb)->truesize; |
5d3213cc AR |
6830 | /* storing the mapped addr in a temp variable |
6831 | * such it will be used for next rxd whose | |
6832 | * Host Control is NULL | |
6833 | */ | |
6d517a27 | 6834 | rxdp1->Buffer0_ptr = *temp0 = |
d44570e4 JP |
6835 | pci_map_single(sp->pdev, (*skb)->data, |
6836 | size - NET_IP_ALIGN, | |
6837 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 6838 | if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr)) |
491abf25 | 6839 | goto memalloc_failed; |
5d3213cc AR |
6840 | rxdp->Host_Control = (unsigned long) (*skb); |
6841 | } | |
6842 | } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) { | |
6d517a27 | 6843 | struct RxD3 *rxdp3 = (struct RxD3 *)rxdp; |
5d3213cc AR |
6844 | /* Two buffer Mode */ |
6845 | if (*skb) { | |
6d517a27 VP |
6846 | rxdp3->Buffer2_ptr = *temp2; |
6847 | rxdp3->Buffer0_ptr = *temp0; | |
6848 | rxdp3->Buffer1_ptr = *temp1; | |
5d3213cc | 6849 | } else { |
c056b734 | 6850 | *skb = netdev_alloc_skb(dev, size); |
2ceaac75 | 6851 | if (!(*skb)) { |
9e39f7c5 JP |
6852 | DBG_PRINT(INFO_DBG, |
6853 | "%s: Out of memory to allocate %s\n", | |
6854 | dev->name, | |
6855 | "2 buf mode SKBs"); | |
ffb5df6c | 6856 | stats->mem_alloc_fail_cnt++; |
2ceaac75 DR |
6857 | return -ENOMEM; |
6858 | } | |
ffb5df6c | 6859 | stats->mem_allocated += (*skb)->truesize; |
6d517a27 | 6860 | rxdp3->Buffer2_ptr = *temp2 = |
5d3213cc AR |
6861 | pci_map_single(sp->pdev, (*skb)->data, |
6862 | dev->mtu + 4, | |
6863 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 6864 | if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr)) |
491abf25 | 6865 | goto memalloc_failed; |
6d517a27 | 6866 | rxdp3->Buffer0_ptr = *temp0 = |
d44570e4 JP |
6867 | pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN, |
6868 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 6869 | if (pci_dma_mapping_error(sp->pdev, |
d44570e4 JP |
6870 | rxdp3->Buffer0_ptr)) { |
6871 | pci_unmap_single(sp->pdev, | |
6872 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
6873 | dev->mtu + 4, | |
6874 | PCI_DMA_FROMDEVICE); | |
491abf25 VP |
6875 | goto memalloc_failed; |
6876 | } | |
5d3213cc AR |
6877 | rxdp->Host_Control = (unsigned long) (*skb); |
6878 | ||
6879 | /* Buffer-1 will be dummy buffer not used */ | |
6d517a27 | 6880 | rxdp3->Buffer1_ptr = *temp1 = |
5d3213cc | 6881 | pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN, |
d44570e4 | 6882 | PCI_DMA_FROMDEVICE); |
8d8bb39b | 6883 | if (pci_dma_mapping_error(sp->pdev, |
d44570e4 JP |
6884 | rxdp3->Buffer1_ptr)) { |
6885 | pci_unmap_single(sp->pdev, | |
6886 | (dma_addr_t)rxdp3->Buffer0_ptr, | |
6887 | BUF0_LEN, PCI_DMA_FROMDEVICE); | |
6888 | pci_unmap_single(sp->pdev, | |
6889 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
6890 | dev->mtu + 4, | |
6891 | PCI_DMA_FROMDEVICE); | |
491abf25 VP |
6892 | goto memalloc_failed; |
6893 | } | |
5d3213cc AR |
6894 | } |
6895 | } | |
6896 | return 0; | |
d44570e4 JP |
6897 | |
6898 | memalloc_failed: | |
6899 | stats->pci_map_fail_cnt++; | |
6900 | stats->mem_freed += (*skb)->truesize; | |
6901 | dev_kfree_skb(*skb); | |
6902 | return -ENOMEM; | |
5d3213cc | 6903 | } |
491abf25 | 6904 | |
1ee6dd77 RB |
6905 | static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp, |
6906 | int size) | |
5d3213cc AR |
6907 | { |
6908 | struct net_device *dev = sp->dev; | |
6909 | if (sp->rxd_mode == RXD_MODE_1) { | |
d44570e4 | 6910 | rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN); |
5d3213cc AR |
6911 | } else if (sp->rxd_mode == RXD_MODE_3B) { |
6912 | rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); | |
6913 | rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); | |
d44570e4 | 6914 | rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4); |
5d3213cc AR |
6915 | } |
6916 | } | |
6917 | ||
1ee6dd77 | 6918 | static int rxd_owner_bit_reset(struct s2io_nic *sp) |
5d3213cc AR |
6919 | { |
6920 | int i, j, k, blk_cnt = 0, size; | |
5d3213cc | 6921 | struct config_param *config = &sp->config; |
ffb5df6c | 6922 | struct mac_info *mac_control = &sp->mac_control; |
5d3213cc | 6923 | struct net_device *dev = sp->dev; |
1ee6dd77 | 6924 | struct RxD_t *rxdp = NULL; |
5d3213cc | 6925 | struct sk_buff *skb = NULL; |
1ee6dd77 | 6926 | struct buffAdd *ba = NULL; |
5d3213cc AR |
6927 | u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0; |
6928 | ||
6929 | /* Calculate the size based on ring mode */ | |
6930 | size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + | |
6931 | HEADER_802_2_SIZE + HEADER_SNAP_SIZE; | |
6932 | if (sp->rxd_mode == RXD_MODE_1) | |
6933 | size += NET_IP_ALIGN; | |
6934 | else if (sp->rxd_mode == RXD_MODE_3B) | |
6935 | size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4; | |
5d3213cc AR |
6936 | |
6937 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
6938 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
6939 | struct ring_info *ring = &mac_control->rings[i]; | |
6940 | ||
d44570e4 | 6941 | blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1); |
5d3213cc AR |
6942 | |
6943 | for (j = 0; j < blk_cnt; j++) { | |
6944 | for (k = 0; k < rxd_count[sp->rxd_mode]; k++) { | |
d44570e4 JP |
6945 | rxdp = ring->rx_blocks[j].rxds[k].virt_addr; |
6946 | if (sp->rxd_mode == RXD_MODE_3B) | |
13d866a9 | 6947 | ba = &ring->ba[j][k]; |
d44570e4 JP |
6948 | if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb, |
6949 | (u64 *)&temp0_64, | |
6950 | (u64 *)&temp1_64, | |
6951 | (u64 *)&temp2_64, | |
6952 | size) == -ENOMEM) { | |
ac1f90d6 SS |
6953 | return 0; |
6954 | } | |
5d3213cc AR |
6955 | |
6956 | set_rxd_buffer_size(sp, rxdp, size); | |
6957 | wmb(); | |
6958 | /* flip the Ownership bit to Hardware */ | |
6959 | rxdp->Control_1 |= RXD_OWN_XENA; | |
6960 | } | |
6961 | } | |
6962 | } | |
6963 | return 0; | |
6964 | ||
6965 | } | |
6966 | ||
d44570e4 | 6967 | static int s2io_add_isr(struct s2io_nic *sp) |
1da177e4 | 6968 | { |
e6a8fee2 | 6969 | int ret = 0; |
c92ca04b | 6970 | struct net_device *dev = sp->dev; |
e6a8fee2 | 6971 | int err = 0; |
1da177e4 | 6972 | |
eaae7f72 | 6973 | if (sp->config.intr_type == MSI_X) |
e6a8fee2 AR |
6974 | ret = s2io_enable_msi_x(sp); |
6975 | if (ret) { | |
6976 | DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name); | |
eaae7f72 | 6977 | sp->config.intr_type = INTA; |
20346722 | 6978 | } |
1da177e4 | 6979 | |
d44570e4 JP |
6980 | /* |
6981 | * Store the values of the MSIX table in | |
6982 | * the struct s2io_nic structure | |
6983 | */ | |
e6a8fee2 | 6984 | store_xmsi_data(sp); |
c92ca04b | 6985 | |
e6a8fee2 | 6986 | /* After proper initialization of H/W, register ISR */ |
eaae7f72 | 6987 | if (sp->config.intr_type == MSI_X) { |
ac731ab6 SH |
6988 | int i, msix_rx_cnt = 0; |
6989 | ||
f61e0a35 SH |
6990 | for (i = 0; i < sp->num_entries; i++) { |
6991 | if (sp->s2io_entries[i].in_use == MSIX_FLG) { | |
6992 | if (sp->s2io_entries[i].type == | |
d44570e4 | 6993 | MSIX_RING_TYPE) { |
ac731ab6 SH |
6994 | sprintf(sp->desc[i], "%s:MSI-X-%d-RX", |
6995 | dev->name, i); | |
6996 | err = request_irq(sp->entries[i].vector, | |
d44570e4 JP |
6997 | s2io_msix_ring_handle, |
6998 | 0, | |
6999 | sp->desc[i], | |
7000 | sp->s2io_entries[i].arg); | |
ac731ab6 | 7001 | } else if (sp->s2io_entries[i].type == |
d44570e4 | 7002 | MSIX_ALARM_TYPE) { |
ac731ab6 | 7003 | sprintf(sp->desc[i], "%s:MSI-X-%d-TX", |
d44570e4 | 7004 | dev->name, i); |
ac731ab6 | 7005 | err = request_irq(sp->entries[i].vector, |
d44570e4 JP |
7006 | s2io_msix_fifo_handle, |
7007 | 0, | |
7008 | sp->desc[i], | |
7009 | sp->s2io_entries[i].arg); | |
ac731ab6 | 7010 | |
fb6a825b | 7011 | } |
ac731ab6 SH |
7012 | /* if either data or addr is zero print it. */ |
7013 | if (!(sp->msix_info[i].addr && | |
d44570e4 | 7014 | sp->msix_info[i].data)) { |
ac731ab6 | 7015 | DBG_PRINT(ERR_DBG, |
d44570e4 JP |
7016 | "%s @Addr:0x%llx Data:0x%llx\n", |
7017 | sp->desc[i], | |
7018 | (unsigned long long) | |
7019 | sp->msix_info[i].addr, | |
7020 | (unsigned long long) | |
7021 | ntohl(sp->msix_info[i].data)); | |
ac731ab6 | 7022 | } else |
fb6a825b | 7023 | msix_rx_cnt++; |
ac731ab6 SH |
7024 | if (err) { |
7025 | remove_msix_isr(sp); | |
7026 | ||
7027 | DBG_PRINT(ERR_DBG, | |
d44570e4 JP |
7028 | "%s:MSI-X-%d registration " |
7029 | "failed\n", dev->name, i); | |
ac731ab6 SH |
7030 | |
7031 | DBG_PRINT(ERR_DBG, | |
d44570e4 JP |
7032 | "%s: Defaulting to INTA\n", |
7033 | dev->name); | |
ac731ab6 SH |
7034 | sp->config.intr_type = INTA; |
7035 | break; | |
fb6a825b | 7036 | } |
ac731ab6 SH |
7037 | sp->s2io_entries[i].in_use = |
7038 | MSIX_REGISTERED_SUCCESS; | |
c92ca04b | 7039 | } |
e6a8fee2 | 7040 | } |
18b2b7bd | 7041 | if (!err) { |
6cef2b8e | 7042 | pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt); |
9e39f7c5 JP |
7043 | DBG_PRINT(INFO_DBG, |
7044 | "MSI-X-TX entries enabled through alarm vector\n"); | |
18b2b7bd | 7045 | } |
e6a8fee2 | 7046 | } |
eaae7f72 | 7047 | if (sp->config.intr_type == INTA) { |
80777c54 | 7048 | err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED, |
d44570e4 | 7049 | sp->name, dev); |
e6a8fee2 AR |
7050 | if (err) { |
7051 | DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", | |
7052 | dev->name); | |
7053 | return -1; | |
7054 | } | |
7055 | } | |
7056 | return 0; | |
7057 | } | |
d44570e4 JP |
7058 | |
7059 | static void s2io_rem_isr(struct s2io_nic *sp) | |
e6a8fee2 | 7060 | { |
18b2b7bd SH |
7061 | if (sp->config.intr_type == MSI_X) |
7062 | remove_msix_isr(sp); | |
7063 | else | |
7064 | remove_inta_isr(sp); | |
e6a8fee2 AR |
7065 | } |
7066 | ||
d44570e4 | 7067 | static void do_s2io_card_down(struct s2io_nic *sp, int do_io) |
e6a8fee2 AR |
7068 | { |
7069 | int cnt = 0; | |
1ee6dd77 | 7070 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
e6a8fee2 | 7071 | register u64 val64 = 0; |
5f490c96 SH |
7072 | struct config_param *config; |
7073 | config = &sp->config; | |
e6a8fee2 | 7074 | |
9f74ffde SH |
7075 | if (!is_s2io_card_up(sp)) |
7076 | return; | |
7077 | ||
e6a8fee2 AR |
7078 | del_timer_sync(&sp->alarm_timer); |
7079 | /* If s2io_set_link task is executing, wait till it completes. */ | |
d44570e4 | 7080 | while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) |
e6a8fee2 | 7081 | msleep(50); |
92b84437 | 7082 | clear_bit(__S2IO_STATE_CARD_UP, &sp->state); |
e6a8fee2 | 7083 | |
5f490c96 | 7084 | /* Disable napi */ |
f61e0a35 SH |
7085 | if (sp->config.napi) { |
7086 | int off = 0; | |
7087 | if (config->intr_type == MSI_X) { | |
7088 | for (; off < sp->config.rx_ring_num; off++) | |
7089 | napi_disable(&sp->mac_control.rings[off].napi); | |
d44570e4 | 7090 | } |
f61e0a35 SH |
7091 | else |
7092 | napi_disable(&sp->napi); | |
7093 | } | |
5f490c96 | 7094 | |
e6a8fee2 | 7095 | /* disable Tx and Rx traffic on the NIC */ |
d796fdb7 LV |
7096 | if (do_io) |
7097 | stop_nic(sp); | |
e6a8fee2 AR |
7098 | |
7099 | s2io_rem_isr(sp); | |
1da177e4 | 7100 | |
01e16faa SH |
7101 | /* stop the tx queue, indicate link down */ |
7102 | s2io_link(sp, LINK_DOWN); | |
7103 | ||
1da177e4 | 7104 | /* Check if the device is Quiescent and then Reset the NIC */ |
d44570e4 | 7105 | while (do_io) { |
5d3213cc AR |
7106 | /* As per the HW requirement we need to replenish the |
7107 | * receive buffer to avoid the ring bump. Since there is | |
7108 | * no intention of processing the Rx frame at this pointwe are | |
70f23fd6 | 7109 | * just setting the ownership bit of rxd in Each Rx |
5d3213cc AR |
7110 | * ring to HW and set the appropriate buffer size |
7111 | * based on the ring mode | |
7112 | */ | |
7113 | rxd_owner_bit_reset(sp); | |
7114 | ||
1da177e4 | 7115 | val64 = readq(&bar0->adapter_status); |
19a60522 | 7116 | if (verify_xena_quiescence(sp)) { |
d44570e4 JP |
7117 | if (verify_pcc_quiescent(sp, sp->device_enabled_once)) |
7118 | break; | |
1da177e4 LT |
7119 | } |
7120 | ||
7121 | msleep(50); | |
7122 | cnt++; | |
7123 | if (cnt == 10) { | |
9e39f7c5 JP |
7124 | DBG_PRINT(ERR_DBG, "Device not Quiescent - " |
7125 | "adapter status reads 0x%llx\n", | |
d44570e4 | 7126 | (unsigned long long)val64); |
1da177e4 LT |
7127 | break; |
7128 | } | |
d796fdb7 LV |
7129 | } |
7130 | if (do_io) | |
7131 | s2io_reset(sp); | |
1da177e4 | 7132 | |
7ba013ac | 7133 | /* Free all Tx buffers */ |
1da177e4 | 7134 | free_tx_buffers(sp); |
7ba013ac K |
7135 | |
7136 | /* Free all Rx buffers */ | |
1da177e4 LT |
7137 | free_rx_buffers(sp); |
7138 | ||
92b84437 | 7139 | clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state)); |
1da177e4 LT |
7140 | } |
7141 | ||
d44570e4 | 7142 | static void s2io_card_down(struct s2io_nic *sp) |
d796fdb7 LV |
7143 | { |
7144 | do_s2io_card_down(sp, 1); | |
7145 | } | |
7146 | ||
d44570e4 | 7147 | static int s2io_card_up(struct s2io_nic *sp) |
1da177e4 | 7148 | { |
cc6e7c44 | 7149 | int i, ret = 0; |
1da177e4 | 7150 | struct config_param *config; |
ffb5df6c | 7151 | struct mac_info *mac_control; |
d44570e4 | 7152 | struct net_device *dev = (struct net_device *)sp->dev; |
e6a8fee2 | 7153 | u16 interruptible; |
1da177e4 LT |
7154 | |
7155 | /* Initialize the H/W I/O registers */ | |
9f74ffde SH |
7156 | ret = init_nic(sp); |
7157 | if (ret != 0) { | |
1da177e4 LT |
7158 | DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", |
7159 | dev->name); | |
9f74ffde SH |
7160 | if (ret != -EIO) |
7161 | s2io_reset(sp); | |
7162 | return ret; | |
1da177e4 LT |
7163 | } |
7164 | ||
20346722 K |
7165 | /* |
7166 | * Initializing the Rx buffers. For now we are considering only 1 | |
1da177e4 LT |
7167 | * Rx ring and initializing buffers into 30 Rx blocks |
7168 | */ | |
1da177e4 | 7169 | config = &sp->config; |
ffb5df6c | 7170 | mac_control = &sp->mac_control; |
1da177e4 LT |
7171 | |
7172 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
7173 | struct ring_info *ring = &mac_control->rings[i]; |
7174 | ||
7175 | ring->mtu = dev->mtu; | |
f0c54ace | 7176 | ring->lro = !!(dev->features & NETIF_F_LRO); |
13d866a9 | 7177 | ret = fill_rx_buffers(sp, ring, 1); |
0425b46a | 7178 | if (ret) { |
1da177e4 LT |
7179 | DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n", |
7180 | dev->name); | |
7181 | s2io_reset(sp); | |
7182 | free_rx_buffers(sp); | |
7183 | return -ENOMEM; | |
7184 | } | |
7185 | DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, | |
13d866a9 | 7186 | ring->rx_bufs_left); |
1da177e4 | 7187 | } |
5f490c96 SH |
7188 | |
7189 | /* Initialise napi */ | |
f61e0a35 | 7190 | if (config->napi) { |
f61e0a35 SH |
7191 | if (config->intr_type == MSI_X) { |
7192 | for (i = 0; i < sp->config.rx_ring_num; i++) | |
7193 | napi_enable(&sp->mac_control.rings[i].napi); | |
7194 | } else { | |
7195 | napi_enable(&sp->napi); | |
7196 | } | |
7197 | } | |
5f490c96 | 7198 | |
19a60522 SS |
7199 | /* Maintain the state prior to the open */ |
7200 | if (sp->promisc_flg) | |
7201 | sp->promisc_flg = 0; | |
7202 | if (sp->m_cast_flg) { | |
7203 | sp->m_cast_flg = 0; | |
d44570e4 | 7204 | sp->all_multi_pos = 0; |
19a60522 | 7205 | } |
1da177e4 LT |
7206 | |
7207 | /* Setting its receive mode */ | |
7208 | s2io_set_multicast(dev); | |
7209 | ||
f0c54ace | 7210 | if (dev->features & NETIF_F_LRO) { |
b41477f3 | 7211 | /* Initialize max aggregatable pkts per session based on MTU */ |
7d3d0439 | 7212 | sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu; |
d44570e4 | 7213 | /* Check if we can use (if specified) user provided value */ |
7d3d0439 RA |
7214 | if (lro_max_pkts < sp->lro_max_aggr_per_sess) |
7215 | sp->lro_max_aggr_per_sess = lro_max_pkts; | |
7216 | } | |
7217 | ||
1da177e4 LT |
7218 | /* Enable Rx Traffic and interrupts on the NIC */ |
7219 | if (start_nic(sp)) { | |
7220 | DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name); | |
1da177e4 | 7221 | s2io_reset(sp); |
e6a8fee2 AR |
7222 | free_rx_buffers(sp); |
7223 | return -ENODEV; | |
7224 | } | |
7225 | ||
7226 | /* Add interrupt service routine */ | |
7227 | if (s2io_add_isr(sp) != 0) { | |
eaae7f72 | 7228 | if (sp->config.intr_type == MSI_X) |
e6a8fee2 AR |
7229 | s2io_rem_isr(sp); |
7230 | s2io_reset(sp); | |
1da177e4 LT |
7231 | free_rx_buffers(sp); |
7232 | return -ENODEV; | |
7233 | } | |
7234 | ||
25fff88e K |
7235 | S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2)); |
7236 | ||
01e16faa SH |
7237 | set_bit(__S2IO_STATE_CARD_UP, &sp->state); |
7238 | ||
e6a8fee2 | 7239 | /* Enable select interrupts */ |
9caab458 | 7240 | en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS); |
01e16faa SH |
7241 | if (sp->config.intr_type != INTA) { |
7242 | interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR; | |
7243 | en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS); | |
7244 | } else { | |
e6a8fee2 | 7245 | interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; |
9caab458 | 7246 | interruptible |= TX_PIC_INTR; |
e6a8fee2 AR |
7247 | en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS); |
7248 | } | |
7249 | ||
1da177e4 LT |
7250 | return 0; |
7251 | } | |
7252 | ||
20346722 | 7253 | /** |
1da177e4 LT |
7254 | * s2io_restart_nic - Resets the NIC. |
7255 | * @data : long pointer to the device private structure | |
7256 | * Description: | |
7257 | * This function is scheduled to be run by the s2io_tx_watchdog | |
20346722 | 7258 | * function after 0.5 secs to reset the NIC. The idea is to reduce |
1da177e4 LT |
7259 | * the run time of the watch dog routine which is run holding a |
7260 | * spin lock. | |
7261 | */ | |
7262 | ||
c4028958 | 7263 | static void s2io_restart_nic(struct work_struct *work) |
1da177e4 | 7264 | { |
1ee6dd77 | 7265 | struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task); |
c4028958 | 7266 | struct net_device *dev = sp->dev; |
1da177e4 | 7267 | |
22747d6b FR |
7268 | rtnl_lock(); |
7269 | ||
7270 | if (!netif_running(dev)) | |
7271 | goto out_unlock; | |
7272 | ||
e6a8fee2 | 7273 | s2io_card_down(sp); |
1da177e4 | 7274 | if (s2io_card_up(sp)) { |
d44570e4 | 7275 | DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name); |
1da177e4 | 7276 | } |
3a3d5756 | 7277 | s2io_wake_all_tx_queue(sp); |
d44570e4 | 7278 | DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name); |
22747d6b FR |
7279 | out_unlock: |
7280 | rtnl_unlock(); | |
1da177e4 LT |
7281 | } |
7282 | ||
20346722 K |
7283 | /** |
7284 | * s2io_tx_watchdog - Watchdog for transmit side. | |
1da177e4 LT |
7285 | * @dev : Pointer to net device structure |
7286 | * Description: | |
7287 | * This function is triggered if the Tx Queue is stopped | |
7288 | * for a pre-defined amount of time when the Interface is still up. | |
7289 | * If the Interface is jammed in such a situation, the hardware is | |
7290 | * reset (by s2io_close) and restarted again (by s2io_open) to | |
7291 | * overcome any problem that might have been caused in the hardware. | |
7292 | * Return value: | |
7293 | * void | |
7294 | */ | |
7295 | ||
7296 | static void s2io_tx_watchdog(struct net_device *dev) | |
7297 | { | |
4cf1653a | 7298 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c | 7299 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
1da177e4 LT |
7300 | |
7301 | if (netif_carrier_ok(dev)) { | |
ffb5df6c | 7302 | swstats->watchdog_timer_cnt++; |
1da177e4 | 7303 | schedule_work(&sp->rst_timer_task); |
ffb5df6c | 7304 | swstats->soft_reset_cnt++; |
1da177e4 LT |
7305 | } |
7306 | } | |
7307 | ||
7308 | /** | |
7309 | * rx_osm_handler - To perform some OS related operations on SKB. | |
7310 | * @sp: private member of the device structure,pointer to s2io_nic structure. | |
7311 | * @skb : the socket buffer pointer. | |
7312 | * @len : length of the packet | |
7313 | * @cksum : FCS checksum of the frame. | |
7314 | * @ring_no : the ring from which this RxD was extracted. | |
20346722 | 7315 | * Description: |
b41477f3 | 7316 | * This function is called by the Rx interrupt serivce routine to perform |
1da177e4 LT |
7317 | * some OS related operations on the SKB before passing it to the upper |
7318 | * layers. It mainly checks if the checksum is OK, if so adds it to the | |
7319 | * SKBs cksum variable, increments the Rx packet count and passes the SKB | |
7320 | * to the upper layer. If the checksum is wrong, it increments the Rx | |
7321 | * packet error count, frees the SKB and returns error. | |
7322 | * Return value: | |
7323 | * SUCCESS on success and -1 on failure. | |
7324 | */ | |
1ee6dd77 | 7325 | static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp) |
1da177e4 | 7326 | { |
1ee6dd77 | 7327 | struct s2io_nic *sp = ring_data->nic; |
d44570e4 | 7328 | struct net_device *dev = (struct net_device *)ring_data->dev; |
20346722 | 7329 | struct sk_buff *skb = (struct sk_buff *) |
d44570e4 | 7330 | ((unsigned long)rxdp->Host_Control); |
20346722 | 7331 | int ring_no = ring_data->ring_no; |
1da177e4 | 7332 | u16 l3_csum, l4_csum; |
863c11a9 | 7333 | unsigned long long err = rxdp->Control_1 & RXD_T_CODE; |
2e6a684b | 7334 | struct lro *uninitialized_var(lro); |
f9046eb3 | 7335 | u8 err_mask; |
ffb5df6c | 7336 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
da6971d8 | 7337 | |
20346722 | 7338 | skb->dev = dev; |
c92ca04b | 7339 | |
863c11a9 | 7340 | if (err) { |
bd1034f0 | 7341 | /* Check for parity error */ |
d44570e4 | 7342 | if (err & 0x1) |
ffb5df6c | 7343 | swstats->parity_err_cnt++; |
d44570e4 | 7344 | |
f9046eb3 | 7345 | err_mask = err >> 48; |
d44570e4 JP |
7346 | switch (err_mask) { |
7347 | case 1: | |
ffb5df6c | 7348 | swstats->rx_parity_err_cnt++; |
491976b2 SH |
7349 | break; |
7350 | ||
d44570e4 | 7351 | case 2: |
ffb5df6c | 7352 | swstats->rx_abort_cnt++; |
491976b2 SH |
7353 | break; |
7354 | ||
d44570e4 | 7355 | case 3: |
ffb5df6c | 7356 | swstats->rx_parity_abort_cnt++; |
491976b2 SH |
7357 | break; |
7358 | ||
d44570e4 | 7359 | case 4: |
ffb5df6c | 7360 | swstats->rx_rda_fail_cnt++; |
491976b2 SH |
7361 | break; |
7362 | ||
d44570e4 | 7363 | case 5: |
ffb5df6c | 7364 | swstats->rx_unkn_prot_cnt++; |
491976b2 SH |
7365 | break; |
7366 | ||
d44570e4 | 7367 | case 6: |
ffb5df6c | 7368 | swstats->rx_fcs_err_cnt++; |
491976b2 | 7369 | break; |
bd1034f0 | 7370 | |
d44570e4 | 7371 | case 7: |
ffb5df6c | 7372 | swstats->rx_buf_size_err_cnt++; |
491976b2 SH |
7373 | break; |
7374 | ||
d44570e4 | 7375 | case 8: |
ffb5df6c | 7376 | swstats->rx_rxd_corrupt_cnt++; |
491976b2 SH |
7377 | break; |
7378 | ||
d44570e4 | 7379 | case 15: |
ffb5df6c | 7380 | swstats->rx_unkn_err_cnt++; |
491976b2 SH |
7381 | break; |
7382 | } | |
863c11a9 | 7383 | /* |
d44570e4 JP |
7384 | * Drop the packet if bad transfer code. Exception being |
7385 | * 0x5, which could be due to unsupported IPv6 extension header. | |
7386 | * In this case, we let stack handle the packet. | |
7387 | * Note that in this case, since checksum will be incorrect, | |
7388 | * stack will validate the same. | |
7389 | */ | |
f9046eb3 OH |
7390 | if (err_mask != 0x5) { |
7391 | DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n", | |
d44570e4 | 7392 | dev->name, err_mask); |
dc56e634 | 7393 | dev->stats.rx_crc_errors++; |
ffb5df6c | 7394 | swstats->mem_freed |
491976b2 | 7395 | += skb->truesize; |
863c11a9 | 7396 | dev_kfree_skb(skb); |
0425b46a | 7397 | ring_data->rx_bufs_left -= 1; |
863c11a9 AR |
7398 | rxdp->Host_Control = 0; |
7399 | return 0; | |
7400 | } | |
20346722 | 7401 | } |
1da177e4 | 7402 | |
20346722 | 7403 | rxdp->Host_Control = 0; |
da6971d8 AR |
7404 | if (sp->rxd_mode == RXD_MODE_1) { |
7405 | int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2); | |
20346722 | 7406 | |
da6971d8 | 7407 | skb_put(skb, len); |
6d517a27 | 7408 | } else if (sp->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
7409 | int get_block = ring_data->rx_curr_get_info.block_index; |
7410 | int get_off = ring_data->rx_curr_get_info.offset; | |
7411 | int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2); | |
7412 | int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2); | |
7413 | unsigned char *buff = skb_push(skb, buf0_len); | |
7414 | ||
1ee6dd77 | 7415 | struct buffAdd *ba = &ring_data->ba[get_block][get_off]; |
da6971d8 | 7416 | memcpy(buff, ba->ba_0, buf0_len); |
6d517a27 | 7417 | skb_put(skb, buf2_len); |
da6971d8 | 7418 | } |
20346722 | 7419 | |
d44570e4 JP |
7420 | if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && |
7421 | ((!ring_data->lro) || | |
7422 | (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) && | |
b437a8cc | 7423 | (dev->features & NETIF_F_RXCSUM)) { |
20346722 | 7424 | l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1); |
1da177e4 LT |
7425 | l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1); |
7426 | if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) { | |
20346722 | 7427 | /* |
1da177e4 LT |
7428 | * NIC verifies if the Checksum of the received |
7429 | * frame is Ok or not and accordingly returns | |
7430 | * a flag in the RxD. | |
7431 | */ | |
7432 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
0425b46a | 7433 | if (ring_data->lro) { |
06f0c139 | 7434 | u32 tcp_len = 0; |
7d3d0439 RA |
7435 | u8 *tcp; |
7436 | int ret = 0; | |
7437 | ||
0425b46a | 7438 | ret = s2io_club_tcp_session(ring_data, |
d44570e4 JP |
7439 | skb->data, &tcp, |
7440 | &tcp_len, &lro, | |
7441 | rxdp, sp); | |
7d3d0439 | 7442 | switch (ret) { |
d44570e4 JP |
7443 | case 3: /* Begin anew */ |
7444 | lro->parent = skb; | |
7445 | goto aggregate; | |
7446 | case 1: /* Aggregate */ | |
7447 | lro_append_pkt(sp, lro, skb, tcp_len); | |
7448 | goto aggregate; | |
7449 | case 4: /* Flush session */ | |
7450 | lro_append_pkt(sp, lro, skb, tcp_len); | |
7451 | queue_rx_frame(lro->parent, | |
7452 | lro->vlan_tag); | |
7453 | clear_lro_session(lro); | |
ffb5df6c | 7454 | swstats->flush_max_pkts++; |
d44570e4 JP |
7455 | goto aggregate; |
7456 | case 2: /* Flush both */ | |
7457 | lro->parent->data_len = lro->frags_len; | |
ffb5df6c | 7458 | swstats->sending_both++; |
d44570e4 JP |
7459 | queue_rx_frame(lro->parent, |
7460 | lro->vlan_tag); | |
7461 | clear_lro_session(lro); | |
7462 | goto send_up; | |
7463 | case 0: /* sessions exceeded */ | |
7464 | case -1: /* non-TCP or not L2 aggregatable */ | |
7465 | case 5: /* | |
7466 | * First pkt in session not | |
7467 | * L3/L4 aggregatable | |
7468 | */ | |
7469 | break; | |
7470 | default: | |
7471 | DBG_PRINT(ERR_DBG, | |
7472 | "%s: Samadhana!!\n", | |
7473 | __func__); | |
7474 | BUG(); | |
7d3d0439 RA |
7475 | } |
7476 | } | |
1da177e4 | 7477 | } else { |
20346722 K |
7478 | /* |
7479 | * Packet with erroneous checksum, let the | |
1da177e4 LT |
7480 | * upper layers deal with it. |
7481 | */ | |
bc8acf2c | 7482 | skb_checksum_none_assert(skb); |
1da177e4 | 7483 | } |
cdb5bf02 | 7484 | } else |
bc8acf2c | 7485 | skb_checksum_none_assert(skb); |
cdb5bf02 | 7486 | |
ffb5df6c | 7487 | swstats->mem_freed += skb->truesize; |
7d3d0439 | 7488 | send_up: |
0c8dfc83 | 7489 | skb_record_rx_queue(skb, ring_no); |
cdb5bf02 | 7490 | queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2)); |
7d3d0439 | 7491 | aggregate: |
0425b46a | 7492 | sp->mac_control.rings[ring_no].rx_bufs_left -= 1; |
1da177e4 LT |
7493 | return SUCCESS; |
7494 | } | |
7495 | ||
7496 | /** | |
7497 | * s2io_link - stops/starts the Tx queue. | |
7498 | * @sp : private member of the device structure, which is a pointer to the | |
7499 | * s2io_nic structure. | |
7500 | * @link : inidicates whether link is UP/DOWN. | |
7501 | * Description: | |
7502 | * This function stops/starts the Tx queue depending on whether the link | |
20346722 K |
7503 | * status of the NIC is is down or up. This is called by the Alarm |
7504 | * interrupt handler whenever a link change interrupt comes up. | |
1da177e4 LT |
7505 | * Return value: |
7506 | * void. | |
7507 | */ | |
7508 | ||
d44570e4 | 7509 | static void s2io_link(struct s2io_nic *sp, int link) |
1da177e4 | 7510 | { |
d44570e4 | 7511 | struct net_device *dev = (struct net_device *)sp->dev; |
ffb5df6c | 7512 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
1da177e4 LT |
7513 | |
7514 | if (link != sp->last_link_state) { | |
b7c5678f | 7515 | init_tti(sp, link); |
1da177e4 LT |
7516 | if (link == LINK_DOWN) { |
7517 | DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name); | |
3a3d5756 | 7518 | s2io_stop_all_tx_queue(sp); |
1da177e4 | 7519 | netif_carrier_off(dev); |
ffb5df6c JP |
7520 | if (swstats->link_up_cnt) |
7521 | swstats->link_up_time = | |
7522 | jiffies - sp->start_time; | |
7523 | swstats->link_down_cnt++; | |
1da177e4 LT |
7524 | } else { |
7525 | DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name); | |
ffb5df6c JP |
7526 | if (swstats->link_down_cnt) |
7527 | swstats->link_down_time = | |
d44570e4 | 7528 | jiffies - sp->start_time; |
ffb5df6c | 7529 | swstats->link_up_cnt++; |
1da177e4 | 7530 | netif_carrier_on(dev); |
3a3d5756 | 7531 | s2io_wake_all_tx_queue(sp); |
1da177e4 LT |
7532 | } |
7533 | } | |
7534 | sp->last_link_state = link; | |
491976b2 | 7535 | sp->start_time = jiffies; |
1da177e4 LT |
7536 | } |
7537 | ||
20346722 K |
7538 | /** |
7539 | * s2io_init_pci -Initialization of PCI and PCI-X configuration registers . | |
7540 | * @sp : private member of the device structure, which is a pointer to the | |
1da177e4 LT |
7541 | * s2io_nic structure. |
7542 | * Description: | |
7543 | * This function initializes a few of the PCI and PCI-X configuration registers | |
7544 | * with recommended values. | |
7545 | * Return value: | |
7546 | * void | |
7547 | */ | |
7548 | ||
d44570e4 | 7549 | static void s2io_init_pci(struct s2io_nic *sp) |
1da177e4 | 7550 | { |
20346722 | 7551 | u16 pci_cmd = 0, pcix_cmd = 0; |
1da177e4 LT |
7552 | |
7553 | /* Enable Data Parity Error Recovery in PCI-X command register. */ | |
7554 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, | |
20346722 | 7555 | &(pcix_cmd)); |
1da177e4 | 7556 | pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, |
20346722 | 7557 | (pcix_cmd | 1)); |
1da177e4 | 7558 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, |
20346722 | 7559 | &(pcix_cmd)); |
1da177e4 LT |
7560 | |
7561 | /* Set the PErr Response bit in PCI command register. */ | |
7562 | pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); | |
7563 | pci_write_config_word(sp->pdev, PCI_COMMAND, | |
7564 | (pci_cmd | PCI_COMMAND_PARITY)); | |
7565 | pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); | |
1da177e4 LT |
7566 | } |
7567 | ||
3a3d5756 | 7568 | static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type, |
d44570e4 | 7569 | u8 *dev_multiq) |
9dc737a7 | 7570 | { |
1853e2e1 JM |
7571 | int i; |
7572 | ||
d44570e4 | 7573 | if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) { |
9e39f7c5 | 7574 | DBG_PRINT(ERR_DBG, "Requested number of tx fifos " |
d44570e4 | 7575 | "(%d) not supported\n", tx_fifo_num); |
6cfc482b SH |
7576 | |
7577 | if (tx_fifo_num < 1) | |
7578 | tx_fifo_num = 1; | |
7579 | else | |
7580 | tx_fifo_num = MAX_TX_FIFOS; | |
7581 | ||
9e39f7c5 | 7582 | DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num); |
9dc737a7 | 7583 | } |
2fda096d | 7584 | |
6cfc482b | 7585 | if (multiq) |
3a3d5756 | 7586 | *dev_multiq = multiq; |
6cfc482b SH |
7587 | |
7588 | if (tx_steering_type && (1 == tx_fifo_num)) { | |
7589 | if (tx_steering_type != TX_DEFAULT_STEERING) | |
7590 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 | 7591 | "Tx steering is not supported with " |
d44570e4 | 7592 | "one fifo. Disabling Tx steering.\n"); |
6cfc482b SH |
7593 | tx_steering_type = NO_STEERING; |
7594 | } | |
7595 | ||
7596 | if ((tx_steering_type < NO_STEERING) || | |
d44570e4 JP |
7597 | (tx_steering_type > TX_DEFAULT_STEERING)) { |
7598 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 JP |
7599 | "Requested transmit steering not supported\n"); |
7600 | DBG_PRINT(ERR_DBG, "Disabling transmit steering\n"); | |
6cfc482b | 7601 | tx_steering_type = NO_STEERING; |
3a3d5756 SH |
7602 | } |
7603 | ||
0425b46a | 7604 | if (rx_ring_num > MAX_RX_RINGS) { |
d44570e4 | 7605 | DBG_PRINT(ERR_DBG, |
9e39f7c5 JP |
7606 | "Requested number of rx rings not supported\n"); |
7607 | DBG_PRINT(ERR_DBG, "Default to %d rx rings\n", | |
d44570e4 | 7608 | MAX_RX_RINGS); |
0425b46a | 7609 | rx_ring_num = MAX_RX_RINGS; |
9dc737a7 | 7610 | } |
0425b46a | 7611 | |
eccb8628 | 7612 | if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) { |
9e39f7c5 | 7613 | DBG_PRINT(ERR_DBG, "Wrong intr_type requested. " |
9dc737a7 AR |
7614 | "Defaulting to INTA\n"); |
7615 | *dev_intr_type = INTA; | |
7616 | } | |
596c5c97 | 7617 | |
9dc737a7 | 7618 | if ((*dev_intr_type == MSI_X) && |
d44570e4 JP |
7619 | ((pdev->device != PCI_DEVICE_ID_HERC_WIN) && |
7620 | (pdev->device != PCI_DEVICE_ID_HERC_UNI))) { | |
9e39f7c5 | 7621 | DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. " |
d44570e4 | 7622 | "Defaulting to INTA\n"); |
9dc737a7 AR |
7623 | *dev_intr_type = INTA; |
7624 | } | |
fb6a825b | 7625 | |
6d517a27 | 7626 | if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) { |
9e39f7c5 JP |
7627 | DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n"); |
7628 | DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n"); | |
6d517a27 | 7629 | rx_ring_mode = 1; |
9dc737a7 | 7630 | } |
1853e2e1 JM |
7631 | |
7632 | for (i = 0; i < MAX_RX_RINGS; i++) | |
7633 | if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) { | |
7634 | DBG_PRINT(ERR_DBG, "Requested rx ring size not " | |
7635 | "supported\nDefaulting to %d\n", | |
7636 | MAX_RX_BLOCKS_PER_RING); | |
7637 | rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING; | |
7638 | } | |
7639 | ||
9dc737a7 AR |
7640 | return SUCCESS; |
7641 | } | |
7642 | ||
9fc93a41 SS |
7643 | /** |
7644 | * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS | |
7645 | * or Traffic class respectively. | |
b7c5678f | 7646 | * @nic: device private variable |
9fc93a41 SS |
7647 | * Description: The function configures the receive steering to |
7648 | * desired receive ring. | |
7649 | * Return Value: SUCCESS on success and | |
7650 | * '-1' on failure (endian settings incorrect). | |
7651 | */ | |
7652 | static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring) | |
7653 | { | |
7654 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
7655 | register u64 val64 = 0; | |
7656 | ||
7657 | if (ds_codepoint > 63) | |
7658 | return FAILURE; | |
7659 | ||
7660 | val64 = RTS_DS_MEM_DATA(ring); | |
7661 | writeq(val64, &bar0->rts_ds_mem_data); | |
7662 | ||
7663 | val64 = RTS_DS_MEM_CTRL_WE | | |
7664 | RTS_DS_MEM_CTRL_STROBE_NEW_CMD | | |
7665 | RTS_DS_MEM_CTRL_OFFSET(ds_codepoint); | |
7666 | ||
7667 | writeq(val64, &bar0->rts_ds_mem_ctrl); | |
7668 | ||
7669 | return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, | |
d44570e4 JP |
7670 | RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, |
7671 | S2IO_BIT_RESET); | |
9fc93a41 SS |
7672 | } |
7673 | ||
04025095 SH |
7674 | static const struct net_device_ops s2io_netdev_ops = { |
7675 | .ndo_open = s2io_open, | |
7676 | .ndo_stop = s2io_close, | |
7677 | .ndo_get_stats = s2io_get_stats, | |
7678 | .ndo_start_xmit = s2io_xmit, | |
7679 | .ndo_validate_addr = eth_validate_addr, | |
afc4b13d | 7680 | .ndo_set_rx_mode = s2io_set_multicast, |
04025095 SH |
7681 | .ndo_do_ioctl = s2io_ioctl, |
7682 | .ndo_set_mac_address = s2io_set_mac_addr, | |
7683 | .ndo_change_mtu = s2io_change_mtu, | |
b437a8cc | 7684 | .ndo_set_features = s2io_set_features, |
04025095 SH |
7685 | .ndo_tx_timeout = s2io_tx_watchdog, |
7686 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7687 | .ndo_poll_controller = s2io_netpoll, | |
7688 | #endif | |
7689 | }; | |
7690 | ||
1da177e4 | 7691 | /** |
20346722 | 7692 | * s2io_init_nic - Initialization of the adapter . |
1da177e4 LT |
7693 | * @pdev : structure containing the PCI related information of the device. |
7694 | * @pre: List of PCI devices supported by the driver listed in s2io_tbl. | |
7695 | * Description: | |
7696 | * The function initializes an adapter identified by the pci_dec structure. | |
20346722 K |
7697 | * All OS related initialization including memory and device structure and |
7698 | * initlaization of the device private variable is done. Also the swapper | |
7699 | * control register is initialized to enable read and write into the I/O | |
1da177e4 LT |
7700 | * registers of the device. |
7701 | * Return value: | |
7702 | * returns 0 on success and negative on failure. | |
7703 | */ | |
7704 | ||
7705 | static int __devinit | |
7706 | s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |
7707 | { | |
1ee6dd77 | 7708 | struct s2io_nic *sp; |
1da177e4 | 7709 | struct net_device *dev; |
1da177e4 | 7710 | int i, j, ret; |
f957bcf0 | 7711 | int dma_flag = false; |
1da177e4 LT |
7712 | u32 mac_up, mac_down; |
7713 | u64 val64 = 0, tmp64 = 0; | |
1ee6dd77 | 7714 | struct XENA_dev_config __iomem *bar0 = NULL; |
1da177e4 | 7715 | u16 subid; |
1da177e4 | 7716 | struct config_param *config; |
ffb5df6c | 7717 | struct mac_info *mac_control; |
541ae68f | 7718 | int mode; |
cc6e7c44 | 7719 | u8 dev_intr_type = intr_type; |
3a3d5756 | 7720 | u8 dev_multiq = 0; |
1da177e4 | 7721 | |
3a3d5756 SH |
7722 | ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq); |
7723 | if (ret) | |
9dc737a7 | 7724 | return ret; |
1da177e4 | 7725 | |
d44570e4 JP |
7726 | ret = pci_enable_device(pdev); |
7727 | if (ret) { | |
1da177e4 | 7728 | DBG_PRINT(ERR_DBG, |
9e39f7c5 | 7729 | "%s: pci_enable_device failed\n", __func__); |
1da177e4 LT |
7730 | return ret; |
7731 | } | |
7732 | ||
6a35528a | 7733 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
9e39f7c5 | 7734 | DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__); |
f957bcf0 | 7735 | dma_flag = true; |
d44570e4 | 7736 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { |
1da177e4 | 7737 | DBG_PRINT(ERR_DBG, |
d44570e4 JP |
7738 | "Unable to obtain 64bit DMA " |
7739 | "for consistent allocations\n"); | |
1da177e4 LT |
7740 | pci_disable_device(pdev); |
7741 | return -ENOMEM; | |
7742 | } | |
284901a9 | 7743 | } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
9e39f7c5 | 7744 | DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__); |
1da177e4 LT |
7745 | } else { |
7746 | pci_disable_device(pdev); | |
7747 | return -ENOMEM; | |
7748 | } | |
d44570e4 JP |
7749 | ret = pci_request_regions(pdev, s2io_driver_name); |
7750 | if (ret) { | |
9e39f7c5 | 7751 | DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n", |
d44570e4 | 7752 | __func__, ret); |
eccb8628 VP |
7753 | pci_disable_device(pdev); |
7754 | return -ENODEV; | |
1da177e4 | 7755 | } |
3a3d5756 | 7756 | if (dev_multiq) |
6cfc482b | 7757 | dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num); |
3a3d5756 | 7758 | else |
b19fa1fa | 7759 | dev = alloc_etherdev(sizeof(struct s2io_nic)); |
1da177e4 | 7760 | if (dev == NULL) { |
1da177e4 LT |
7761 | pci_disable_device(pdev); |
7762 | pci_release_regions(pdev); | |
7763 | return -ENODEV; | |
7764 | } | |
7765 | ||
7766 | pci_set_master(pdev); | |
7767 | pci_set_drvdata(pdev, dev); | |
1da177e4 LT |
7768 | SET_NETDEV_DEV(dev, &pdev->dev); |
7769 | ||
7770 | /* Private member variable initialized to s2io NIC structure */ | |
4cf1653a | 7771 | sp = netdev_priv(dev); |
1da177e4 LT |
7772 | sp->dev = dev; |
7773 | sp->pdev = pdev; | |
1da177e4 | 7774 | sp->high_dma_flag = dma_flag; |
f957bcf0 | 7775 | sp->device_enabled_once = false; |
da6971d8 AR |
7776 | if (rx_ring_mode == 1) |
7777 | sp->rxd_mode = RXD_MODE_1; | |
7778 | if (rx_ring_mode == 2) | |
7779 | sp->rxd_mode = RXD_MODE_3B; | |
da6971d8 | 7780 | |
eaae7f72 | 7781 | sp->config.intr_type = dev_intr_type; |
1da177e4 | 7782 | |
541ae68f | 7783 | if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) || |
d44570e4 | 7784 | (pdev->device == PCI_DEVICE_ID_HERC_UNI)) |
541ae68f K |
7785 | sp->device_type = XFRAME_II_DEVICE; |
7786 | else | |
7787 | sp->device_type = XFRAME_I_DEVICE; | |
7788 | ||
6aa20a22 | 7789 | |
1da177e4 LT |
7790 | /* Initialize some PCI/PCI-X fields of the NIC. */ |
7791 | s2io_init_pci(sp); | |
7792 | ||
20346722 | 7793 | /* |
1da177e4 | 7794 | * Setting the device configuration parameters. |
20346722 K |
7795 | * Most of these parameters can be specified by the user during |
7796 | * module insertion as they are module loadable parameters. If | |
7797 | * these parameters are not not specified during load time, they | |
1da177e4 LT |
7798 | * are initialized with default values. |
7799 | */ | |
1da177e4 | 7800 | config = &sp->config; |
ffb5df6c | 7801 | mac_control = &sp->mac_control; |
1da177e4 | 7802 | |
596c5c97 | 7803 | config->napi = napi; |
6cfc482b | 7804 | config->tx_steering_type = tx_steering_type; |
596c5c97 | 7805 | |
1da177e4 | 7806 | /* Tx side parameters. */ |
6cfc482b SH |
7807 | if (config->tx_steering_type == TX_PRIORITY_STEERING) |
7808 | config->tx_fifo_num = MAX_TX_FIFOS; | |
7809 | else | |
7810 | config->tx_fifo_num = tx_fifo_num; | |
7811 | ||
7812 | /* Initialize the fifos used for tx steering */ | |
7813 | if (config->tx_fifo_num < 5) { | |
d44570e4 JP |
7814 | if (config->tx_fifo_num == 1) |
7815 | sp->total_tcp_fifos = 1; | |
7816 | else | |
7817 | sp->total_tcp_fifos = config->tx_fifo_num - 1; | |
7818 | sp->udp_fifo_idx = config->tx_fifo_num - 1; | |
7819 | sp->total_udp_fifos = 1; | |
7820 | sp->other_fifo_idx = sp->total_tcp_fifos - 1; | |
6cfc482b SH |
7821 | } else { |
7822 | sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM - | |
d44570e4 | 7823 | FIFO_OTHER_MAX_NUM); |
6cfc482b SH |
7824 | sp->udp_fifo_idx = sp->total_tcp_fifos; |
7825 | sp->total_udp_fifos = FIFO_UDP_MAX_NUM; | |
7826 | sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM; | |
7827 | } | |
7828 | ||
3a3d5756 | 7829 | config->multiq = dev_multiq; |
6cfc482b | 7830 | for (i = 0; i < config->tx_fifo_num; i++) { |
13d866a9 JP |
7831 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
7832 | ||
7833 | tx_cfg->fifo_len = tx_fifo_len[i]; | |
7834 | tx_cfg->fifo_priority = i; | |
1da177e4 LT |
7835 | } |
7836 | ||
20346722 K |
7837 | /* mapping the QoS priority to the configured fifos */ |
7838 | for (i = 0; i < MAX_TX_FIFOS; i++) | |
3a3d5756 | 7839 | config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i]; |
20346722 | 7840 | |
6cfc482b SH |
7841 | /* map the hashing selector table to the configured fifos */ |
7842 | for (i = 0; i < config->tx_fifo_num; i++) | |
7843 | sp->fifo_selector[i] = fifo_selector[i]; | |
7844 | ||
7845 | ||
1da177e4 LT |
7846 | config->tx_intr_type = TXD_INT_TYPE_UTILZ; |
7847 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
7848 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
7849 | ||
7850 | tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER); | |
7851 | if (tx_cfg->fifo_len < 65) { | |
1da177e4 LT |
7852 | config->tx_intr_type = TXD_INT_TYPE_PER_LIST; |
7853 | break; | |
7854 | } | |
7855 | } | |
fed5eccd AR |
7856 | /* + 2 because one Txd for skb->data and one Txd for UFO */ |
7857 | config->max_txds = MAX_SKB_FRAGS + 2; | |
1da177e4 LT |
7858 | |
7859 | /* Rx side parameters. */ | |
1da177e4 | 7860 | config->rx_ring_num = rx_ring_num; |
0425b46a | 7861 | for (i = 0; i < config->rx_ring_num; i++) { |
13d866a9 JP |
7862 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
7863 | struct ring_info *ring = &mac_control->rings[i]; | |
7864 | ||
7865 | rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1); | |
7866 | rx_cfg->ring_priority = i; | |
7867 | ring->rx_bufs_left = 0; | |
7868 | ring->rxd_mode = sp->rxd_mode; | |
7869 | ring->rxd_count = rxd_count[sp->rxd_mode]; | |
7870 | ring->pdev = sp->pdev; | |
7871 | ring->dev = sp->dev; | |
1da177e4 LT |
7872 | } |
7873 | ||
7874 | for (i = 0; i < rx_ring_num; i++) { | |
13d866a9 JP |
7875 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
7876 | ||
7877 | rx_cfg->ring_org = RING_ORG_BUFF1; | |
7878 | rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER); | |
1da177e4 LT |
7879 | } |
7880 | ||
7881 | /* Setting Mac Control parameters */ | |
7882 | mac_control->rmac_pause_time = rmac_pause_time; | |
7883 | mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3; | |
7884 | mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7; | |
7885 | ||
7886 | ||
1da177e4 LT |
7887 | /* initialize the shared memory used by the NIC and the host */ |
7888 | if (init_shared_mem(sp)) { | |
d44570e4 | 7889 | DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name); |
1da177e4 LT |
7890 | ret = -ENOMEM; |
7891 | goto mem_alloc_failed; | |
7892 | } | |
7893 | ||
275f165f | 7894 | sp->bar0 = pci_ioremap_bar(pdev, 0); |
1da177e4 | 7895 | if (!sp->bar0) { |
19a60522 | 7896 | DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n", |
1da177e4 LT |
7897 | dev->name); |
7898 | ret = -ENOMEM; | |
7899 | goto bar0_remap_failed; | |
7900 | } | |
7901 | ||
275f165f | 7902 | sp->bar1 = pci_ioremap_bar(pdev, 2); |
1da177e4 | 7903 | if (!sp->bar1) { |
19a60522 | 7904 | DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n", |
1da177e4 LT |
7905 | dev->name); |
7906 | ret = -ENOMEM; | |
7907 | goto bar1_remap_failed; | |
7908 | } | |
7909 | ||
1da177e4 LT |
7910 | /* Initializing the BAR1 address as the start of the FIFO pointer. */ |
7911 | for (j = 0; j < MAX_TX_FIFOS; j++) { | |
43d620c8 | 7912 | mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000); |
1da177e4 LT |
7913 | } |
7914 | ||
7915 | /* Driver entry points */ | |
04025095 | 7916 | dev->netdev_ops = &s2io_netdev_ops; |
1da177e4 | 7917 | SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); |
b437a8cc MM |
7918 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | |
7919 | NETIF_F_TSO | NETIF_F_TSO6 | | |
7920 | NETIF_F_RXCSUM | NETIF_F_LRO; | |
7921 | dev->features |= dev->hw_features | | |
7922 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
7923 | if (sp->device_type & XFRAME_II_DEVICE) { | |
7924 | dev->hw_features |= NETIF_F_UFO; | |
7925 | if (ufo) | |
7926 | dev->features |= NETIF_F_UFO; | |
7927 | } | |
f957bcf0 | 7928 | if (sp->high_dma_flag == true) |
1da177e4 | 7929 | dev->features |= NETIF_F_HIGHDMA; |
1da177e4 | 7930 | dev->watchdog_timeo = WATCH_DOG_TIMEOUT; |
c4028958 DH |
7931 | INIT_WORK(&sp->rst_timer_task, s2io_restart_nic); |
7932 | INIT_WORK(&sp->set_link_task, s2io_set_link); | |
1da177e4 | 7933 | |
e960fc5c | 7934 | pci_save_state(sp->pdev); |
1da177e4 LT |
7935 | |
7936 | /* Setting swapper control on the NIC, for proper reset operation */ | |
7937 | if (s2io_set_swapper(sp)) { | |
9e39f7c5 | 7938 | DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n", |
1da177e4 LT |
7939 | dev->name); |
7940 | ret = -EAGAIN; | |
7941 | goto set_swap_failed; | |
7942 | } | |
7943 | ||
541ae68f K |
7944 | /* Verify if the Herc works on the slot its placed into */ |
7945 | if (sp->device_type & XFRAME_II_DEVICE) { | |
7946 | mode = s2io_verify_pci_mode(sp); | |
7947 | if (mode < 0) { | |
9e39f7c5 JP |
7948 | DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n", |
7949 | __func__); | |
541ae68f K |
7950 | ret = -EBADSLT; |
7951 | goto set_swap_failed; | |
7952 | } | |
7953 | } | |
7954 | ||
f61e0a35 SH |
7955 | if (sp->config.intr_type == MSI_X) { |
7956 | sp->num_entries = config->rx_ring_num + 1; | |
7957 | ret = s2io_enable_msi_x(sp); | |
7958 | ||
7959 | if (!ret) { | |
7960 | ret = s2io_test_msi(sp); | |
7961 | /* rollback MSI-X, will re-enable during add_isr() */ | |
7962 | remove_msix_isr(sp); | |
7963 | } | |
7964 | if (ret) { | |
7965 | ||
7966 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 | 7967 | "MSI-X requested but failed to enable\n"); |
f61e0a35 SH |
7968 | sp->config.intr_type = INTA; |
7969 | } | |
7970 | } | |
7971 | ||
7972 | if (config->intr_type == MSI_X) { | |
13d866a9 JP |
7973 | for (i = 0; i < config->rx_ring_num ; i++) { |
7974 | struct ring_info *ring = &mac_control->rings[i]; | |
7975 | ||
7976 | netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64); | |
7977 | } | |
f61e0a35 SH |
7978 | } else { |
7979 | netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64); | |
7980 | } | |
7981 | ||
541ae68f K |
7982 | /* Not needed for Herc */ |
7983 | if (sp->device_type & XFRAME_I_DEVICE) { | |
7984 | /* | |
7985 | * Fix for all "FFs" MAC address problems observed on | |
7986 | * Alpha platforms | |
7987 | */ | |
7988 | fix_mac_address(sp); | |
7989 | s2io_reset(sp); | |
7990 | } | |
1da177e4 LT |
7991 | |
7992 | /* | |
1da177e4 LT |
7993 | * MAC address initialization. |
7994 | * For now only one mac address will be read and used. | |
7995 | */ | |
7996 | bar0 = sp->bar0; | |
7997 | val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | | |
d44570e4 | 7998 | RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET); |
1da177e4 | 7999 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
c92ca04b | 8000 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
8001 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
8002 | S2IO_BIT_RESET); | |
1da177e4 | 8003 | tmp64 = readq(&bar0->rmac_addr_data0_mem); |
d44570e4 | 8004 | mac_down = (u32)tmp64; |
1da177e4 LT |
8005 | mac_up = (u32) (tmp64 >> 32); |
8006 | ||
1da177e4 LT |
8007 | sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up); |
8008 | sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8); | |
8009 | sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16); | |
8010 | sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24); | |
8011 | sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16); | |
8012 | sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24); | |
8013 | ||
1da177e4 LT |
8014 | /* Set the factory defined MAC address initially */ |
8015 | dev->addr_len = ETH_ALEN; | |
8016 | memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); | |
2fd37688 | 8017 | memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN); |
1da177e4 | 8018 | |
faa4f796 SH |
8019 | /* initialize number of multicast & unicast MAC entries variables */ |
8020 | if (sp->device_type == XFRAME_I_DEVICE) { | |
8021 | config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES; | |
8022 | config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES; | |
8023 | config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET; | |
8024 | } else if (sp->device_type == XFRAME_II_DEVICE) { | |
8025 | config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES; | |
8026 | config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES; | |
8027 | config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET; | |
8028 | } | |
8029 | ||
8030 | /* store mac addresses from CAM to s2io_nic structure */ | |
8031 | do_s2io_store_unicast_mc(sp); | |
8032 | ||
f61e0a35 SH |
8033 | /* Configure MSIX vector for number of rings configured plus one */ |
8034 | if ((sp->device_type == XFRAME_II_DEVICE) && | |
d44570e4 | 8035 | (config->intr_type == MSI_X)) |
f61e0a35 SH |
8036 | sp->num_entries = config->rx_ring_num + 1; |
8037 | ||
d44570e4 | 8038 | /* Store the values of the MSIX table in the s2io_nic structure */ |
c77dd43e | 8039 | store_xmsi_data(sp); |
b41477f3 AR |
8040 | /* reset Nic and bring it to known state */ |
8041 | s2io_reset(sp); | |
8042 | ||
1da177e4 | 8043 | /* |
99993af6 | 8044 | * Initialize link state flags |
541ae68f | 8045 | * and the card state parameter |
1da177e4 | 8046 | */ |
92b84437 | 8047 | sp->state = 0; |
1da177e4 | 8048 | |
1da177e4 | 8049 | /* Initialize spinlocks */ |
13d866a9 JP |
8050 | for (i = 0; i < sp->config.tx_fifo_num; i++) { |
8051 | struct fifo_info *fifo = &mac_control->fifos[i]; | |
8052 | ||
8053 | spin_lock_init(&fifo->tx_lock); | |
8054 | } | |
db874e65 | 8055 | |
20346722 K |
8056 | /* |
8057 | * SXE-002: Configure link and activity LED to init state | |
8058 | * on driver load. | |
1da177e4 LT |
8059 | */ |
8060 | subid = sp->pdev->subsystem_device; | |
8061 | if ((subid & 0xFF) >= 0x07) { | |
8062 | val64 = readq(&bar0->gpio_control); | |
8063 | val64 |= 0x0000800000000000ULL; | |
8064 | writeq(val64, &bar0->gpio_control); | |
8065 | val64 = 0x0411040400000000ULL; | |
d44570e4 | 8066 | writeq(val64, (void __iomem *)bar0 + 0x2700); |
1da177e4 LT |
8067 | val64 = readq(&bar0->gpio_control); |
8068 | } | |
8069 | ||
8070 | sp->rx_csum = 1; /* Rx chksum verify enabled by default */ | |
8071 | ||
8072 | if (register_netdev(dev)) { | |
8073 | DBG_PRINT(ERR_DBG, "Device registration failed\n"); | |
8074 | ret = -ENODEV; | |
8075 | goto register_failed; | |
8076 | } | |
9dc737a7 | 8077 | s2io_vpd_read(sp); |
926bd900 | 8078 | DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n"); |
d44570e4 | 8079 | DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name, |
44c10138 | 8080 | sp->product_name, pdev->revision); |
b41477f3 AR |
8081 | DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name, |
8082 | s2io_driver_version); | |
9e39f7c5 JP |
8083 | DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr); |
8084 | DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num); | |
9dc737a7 | 8085 | if (sp->device_type & XFRAME_II_DEVICE) { |
0b1f7ebe | 8086 | mode = s2io_print_pci_mode(sp); |
541ae68f | 8087 | if (mode < 0) { |
541ae68f | 8088 | ret = -EBADSLT; |
9dc737a7 | 8089 | unregister_netdev(dev); |
541ae68f K |
8090 | goto set_swap_failed; |
8091 | } | |
541ae68f | 8092 | } |
d44570e4 JP |
8093 | switch (sp->rxd_mode) { |
8094 | case RXD_MODE_1: | |
8095 | DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n", | |
8096 | dev->name); | |
8097 | break; | |
8098 | case RXD_MODE_3B: | |
8099 | DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n", | |
8100 | dev->name); | |
8101 | break; | |
9dc737a7 | 8102 | } |
db874e65 | 8103 | |
f61e0a35 SH |
8104 | switch (sp->config.napi) { |
8105 | case 0: | |
8106 | DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name); | |
8107 | break; | |
8108 | case 1: | |
db874e65 | 8109 | DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name); |
f61e0a35 SH |
8110 | break; |
8111 | } | |
3a3d5756 SH |
8112 | |
8113 | DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name, | |
d44570e4 | 8114 | sp->config.tx_fifo_num); |
3a3d5756 | 8115 | |
0425b46a SH |
8116 | DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name, |
8117 | sp->config.rx_ring_num); | |
8118 | ||
d44570e4 JP |
8119 | switch (sp->config.intr_type) { |
8120 | case INTA: | |
8121 | DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name); | |
8122 | break; | |
8123 | case MSI_X: | |
8124 | DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name); | |
8125 | break; | |
9dc737a7 | 8126 | } |
3a3d5756 | 8127 | if (sp->config.multiq) { |
13d866a9 JP |
8128 | for (i = 0; i < sp->config.tx_fifo_num; i++) { |
8129 | struct fifo_info *fifo = &mac_control->fifos[i]; | |
8130 | ||
8131 | fifo->multiq = config->multiq; | |
8132 | } | |
3a3d5756 | 8133 | DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n", |
d44570e4 | 8134 | dev->name); |
3a3d5756 SH |
8135 | } else |
8136 | DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n", | |
d44570e4 | 8137 | dev->name); |
3a3d5756 | 8138 | |
6cfc482b SH |
8139 | switch (sp->config.tx_steering_type) { |
8140 | case NO_STEERING: | |
d44570e4 JP |
8141 | DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n", |
8142 | dev->name); | |
8143 | break; | |
6cfc482b | 8144 | case TX_PRIORITY_STEERING: |
d44570e4 JP |
8145 | DBG_PRINT(ERR_DBG, |
8146 | "%s: Priority steering enabled for transmit\n", | |
8147 | dev->name); | |
6cfc482b SH |
8148 | break; |
8149 | case TX_DEFAULT_STEERING: | |
d44570e4 JP |
8150 | DBG_PRINT(ERR_DBG, |
8151 | "%s: Default steering enabled for transmit\n", | |
8152 | dev->name); | |
6cfc482b SH |
8153 | } |
8154 | ||
f0c54ace AW |
8155 | DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n", |
8156 | dev->name); | |
db874e65 | 8157 | if (ufo) |
d44570e4 JP |
8158 | DBG_PRINT(ERR_DBG, |
8159 | "%s: UDP Fragmentation Offload(UFO) enabled\n", | |
8160 | dev->name); | |
7ba013ac | 8161 | /* Initialize device name */ |
9dc737a7 | 8162 | sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name); |
7ba013ac | 8163 | |
cd0fce03 BL |
8164 | if (vlan_tag_strip) |
8165 | sp->vlan_strip_flag = 1; | |
8166 | else | |
8167 | sp->vlan_strip_flag = 0; | |
8168 | ||
20346722 K |
8169 | /* |
8170 | * Make Link state as off at this point, when the Link change | |
8171 | * interrupt comes the state will be automatically changed to | |
1da177e4 LT |
8172 | * the right state. |
8173 | */ | |
8174 | netif_carrier_off(dev); | |
1da177e4 LT |
8175 | |
8176 | return 0; | |
8177 | ||
d44570e4 JP |
8178 | register_failed: |
8179 | set_swap_failed: | |
1da177e4 | 8180 | iounmap(sp->bar1); |
d44570e4 | 8181 | bar1_remap_failed: |
1da177e4 | 8182 | iounmap(sp->bar0); |
d44570e4 JP |
8183 | bar0_remap_failed: |
8184 | mem_alloc_failed: | |
1da177e4 LT |
8185 | free_shared_mem(sp); |
8186 | pci_disable_device(pdev); | |
eccb8628 | 8187 | pci_release_regions(pdev); |
1da177e4 LT |
8188 | pci_set_drvdata(pdev, NULL); |
8189 | free_netdev(dev); | |
8190 | ||
8191 | return ret; | |
8192 | } | |
8193 | ||
8194 | /** | |
20346722 | 8195 | * s2io_rem_nic - Free the PCI device |
1da177e4 | 8196 | * @pdev: structure containing the PCI related information of the device. |
20346722 | 8197 | * Description: This function is called by the Pci subsystem to release a |
1da177e4 | 8198 | * PCI device and free up all resource held up by the device. This could |
20346722 | 8199 | * be in response to a Hot plug event or when the driver is to be removed |
1da177e4 LT |
8200 | * from memory. |
8201 | */ | |
8202 | ||
8203 | static void __devexit s2io_rem_nic(struct pci_dev *pdev) | |
8204 | { | |
a31ff388 | 8205 | struct net_device *dev = pci_get_drvdata(pdev); |
1ee6dd77 | 8206 | struct s2io_nic *sp; |
1da177e4 LT |
8207 | |
8208 | if (dev == NULL) { | |
8209 | DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n"); | |
8210 | return; | |
8211 | } | |
8212 | ||
4cf1653a | 8213 | sp = netdev_priv(dev); |
23f333a2 TH |
8214 | |
8215 | cancel_work_sync(&sp->rst_timer_task); | |
8216 | cancel_work_sync(&sp->set_link_task); | |
8217 | ||
1da177e4 LT |
8218 | unregister_netdev(dev); |
8219 | ||
8220 | free_shared_mem(sp); | |
8221 | iounmap(sp->bar0); | |
8222 | iounmap(sp->bar1); | |
eccb8628 | 8223 | pci_release_regions(pdev); |
1da177e4 | 8224 | pci_set_drvdata(pdev, NULL); |
1da177e4 | 8225 | free_netdev(dev); |
19a60522 | 8226 | pci_disable_device(pdev); |
1da177e4 LT |
8227 | } |
8228 | ||
8229 | /** | |
8230 | * s2io_starter - Entry point for the driver | |
8231 | * Description: This function is the entry point for the driver. It verifies | |
8232 | * the module loadable parameters and initializes PCI configuration space. | |
8233 | */ | |
8234 | ||
43b7c451 | 8235 | static int __init s2io_starter(void) |
1da177e4 | 8236 | { |
29917620 | 8237 | return pci_register_driver(&s2io_driver); |
1da177e4 LT |
8238 | } |
8239 | ||
8240 | /** | |
20346722 | 8241 | * s2io_closer - Cleanup routine for the driver |
1da177e4 LT |
8242 | * Description: This function is the cleanup routine for the driver. It unregist * ers the driver. |
8243 | */ | |
8244 | ||
372cc597 | 8245 | static __exit void s2io_closer(void) |
1da177e4 LT |
8246 | { |
8247 | pci_unregister_driver(&s2io_driver); | |
8248 | DBG_PRINT(INIT_DBG, "cleanup done\n"); | |
8249 | } | |
8250 | ||
8251 | module_init(s2io_starter); | |
8252 | module_exit(s2io_closer); | |
7d3d0439 | 8253 | |
6aa20a22 | 8254 | static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip, |
d44570e4 JP |
8255 | struct tcphdr **tcp, struct RxD_t *rxdp, |
8256 | struct s2io_nic *sp) | |
7d3d0439 RA |
8257 | { |
8258 | int ip_off; | |
8259 | u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len; | |
8260 | ||
8261 | if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) { | |
d44570e4 JP |
8262 | DBG_PRINT(INIT_DBG, |
8263 | "%s: Non-TCP frames not supported for LRO\n", | |
b39d66a8 | 8264 | __func__); |
7d3d0439 RA |
8265 | return -1; |
8266 | } | |
8267 | ||
cdb5bf02 | 8268 | /* Checking for DIX type or DIX type with VLAN */ |
d44570e4 | 8269 | if ((l2_type == 0) || (l2_type == 4)) { |
cdb5bf02 SH |
8270 | ip_off = HEADER_ETHERNET_II_802_3_SIZE; |
8271 | /* | |
8272 | * If vlan stripping is disabled and the frame is VLAN tagged, | |
8273 | * shift the offset by the VLAN header size bytes. | |
8274 | */ | |
cd0fce03 | 8275 | if ((!sp->vlan_strip_flag) && |
d44570e4 | 8276 | (rxdp->Control_1 & RXD_FRAME_VLAN_TAG)) |
cdb5bf02 SH |
8277 | ip_off += HEADER_VLAN_SIZE; |
8278 | } else { | |
7d3d0439 | 8279 | /* LLC, SNAP etc are considered non-mergeable */ |
cdb5bf02 | 8280 | return -1; |
7d3d0439 RA |
8281 | } |
8282 | ||
8283 | *ip = (struct iphdr *)((u8 *)buffer + ip_off); | |
8284 | ip_len = (u8)((*ip)->ihl); | |
8285 | ip_len <<= 2; | |
8286 | *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len); | |
8287 | ||
8288 | return 0; | |
8289 | } | |
8290 | ||
1ee6dd77 | 8291 | static int check_for_socket_match(struct lro *lro, struct iphdr *ip, |
7d3d0439 RA |
8292 | struct tcphdr *tcp) |
8293 | { | |
d44570e4 JP |
8294 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
8295 | if ((lro->iph->saddr != ip->saddr) || | |
8296 | (lro->iph->daddr != ip->daddr) || | |
8297 | (lro->tcph->source != tcp->source) || | |
8298 | (lro->tcph->dest != tcp->dest)) | |
7d3d0439 RA |
8299 | return -1; |
8300 | return 0; | |
8301 | } | |
8302 | ||
8303 | static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp) | |
8304 | { | |
d44570e4 | 8305 | return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2); |
7d3d0439 RA |
8306 | } |
8307 | ||
1ee6dd77 | 8308 | static void initiate_new_session(struct lro *lro, u8 *l2h, |
d44570e4 JP |
8309 | struct iphdr *ip, struct tcphdr *tcp, |
8310 | u32 tcp_pyld_len, u16 vlan_tag) | |
7d3d0439 | 8311 | { |
d44570e4 | 8312 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
7d3d0439 RA |
8313 | lro->l2h = l2h; |
8314 | lro->iph = ip; | |
8315 | lro->tcph = tcp; | |
8316 | lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq); | |
c8855953 | 8317 | lro->tcp_ack = tcp->ack_seq; |
7d3d0439 RA |
8318 | lro->sg_num = 1; |
8319 | lro->total_len = ntohs(ip->tot_len); | |
8320 | lro->frags_len = 0; | |
cdb5bf02 | 8321 | lro->vlan_tag = vlan_tag; |
6aa20a22 | 8322 | /* |
d44570e4 JP |
8323 | * Check if we saw TCP timestamp. |
8324 | * Other consistency checks have already been done. | |
8325 | */ | |
7d3d0439 | 8326 | if (tcp->doff == 8) { |
c8855953 SR |
8327 | __be32 *ptr; |
8328 | ptr = (__be32 *)(tcp+1); | |
7d3d0439 | 8329 | lro->saw_ts = 1; |
c8855953 | 8330 | lro->cur_tsval = ntohl(*(ptr+1)); |
7d3d0439 RA |
8331 | lro->cur_tsecr = *(ptr+2); |
8332 | } | |
8333 | lro->in_use = 1; | |
8334 | } | |
8335 | ||
1ee6dd77 | 8336 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro) |
7d3d0439 RA |
8337 | { |
8338 | struct iphdr *ip = lro->iph; | |
8339 | struct tcphdr *tcp = lro->tcph; | |
bd4f3ae1 | 8340 | __sum16 nchk; |
ffb5df6c JP |
8341 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
8342 | ||
d44570e4 | 8343 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
7d3d0439 RA |
8344 | |
8345 | /* Update L3 header */ | |
8346 | ip->tot_len = htons(lro->total_len); | |
8347 | ip->check = 0; | |
8348 | nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl); | |
8349 | ip->check = nchk; | |
8350 | ||
8351 | /* Update L4 header */ | |
8352 | tcp->ack_seq = lro->tcp_ack; | |
8353 | tcp->window = lro->window; | |
8354 | ||
8355 | /* Update tsecr field if this session has timestamps enabled */ | |
8356 | if (lro->saw_ts) { | |
c8855953 | 8357 | __be32 *ptr = (__be32 *)(tcp + 1); |
7d3d0439 RA |
8358 | *(ptr+2) = lro->cur_tsecr; |
8359 | } | |
8360 | ||
8361 | /* Update counters required for calculation of | |
8362 | * average no. of packets aggregated. | |
8363 | */ | |
ffb5df6c JP |
8364 | swstats->sum_avg_pkts_aggregated += lro->sg_num; |
8365 | swstats->num_aggregations++; | |
7d3d0439 RA |
8366 | } |
8367 | ||
1ee6dd77 | 8368 | static void aggregate_new_rx(struct lro *lro, struct iphdr *ip, |
d44570e4 | 8369 | struct tcphdr *tcp, u32 l4_pyld) |
7d3d0439 | 8370 | { |
d44570e4 | 8371 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
7d3d0439 RA |
8372 | lro->total_len += l4_pyld; |
8373 | lro->frags_len += l4_pyld; | |
8374 | lro->tcp_next_seq += l4_pyld; | |
8375 | lro->sg_num++; | |
8376 | ||
8377 | /* Update ack seq no. and window ad(from this pkt) in LRO object */ | |
8378 | lro->tcp_ack = tcp->ack_seq; | |
8379 | lro->window = tcp->window; | |
6aa20a22 | 8380 | |
7d3d0439 | 8381 | if (lro->saw_ts) { |
c8855953 | 8382 | __be32 *ptr; |
7d3d0439 | 8383 | /* Update tsecr and tsval from this packet */ |
c8855953 SR |
8384 | ptr = (__be32 *)(tcp+1); |
8385 | lro->cur_tsval = ntohl(*(ptr+1)); | |
7d3d0439 RA |
8386 | lro->cur_tsecr = *(ptr + 2); |
8387 | } | |
8388 | } | |
8389 | ||
1ee6dd77 | 8390 | static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip, |
7d3d0439 RA |
8391 | struct tcphdr *tcp, u32 tcp_pyld_len) |
8392 | { | |
7d3d0439 RA |
8393 | u8 *ptr; |
8394 | ||
d44570e4 | 8395 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
79dc1901 | 8396 | |
7d3d0439 RA |
8397 | if (!tcp_pyld_len) { |
8398 | /* Runt frame or a pure ack */ | |
8399 | return -1; | |
8400 | } | |
8401 | ||
8402 | if (ip->ihl != 5) /* IP has options */ | |
8403 | return -1; | |
8404 | ||
75c30b13 AR |
8405 | /* If we see CE codepoint in IP header, packet is not mergeable */ |
8406 | if (INET_ECN_is_ce(ipv4_get_dsfield(ip))) | |
8407 | return -1; | |
8408 | ||
8409 | /* If we see ECE or CWR flags in TCP header, packet is not mergeable */ | |
d44570e4 JP |
8410 | if (tcp->urg || tcp->psh || tcp->rst || |
8411 | tcp->syn || tcp->fin || | |
8412 | tcp->ece || tcp->cwr || !tcp->ack) { | |
7d3d0439 RA |
8413 | /* |
8414 | * Currently recognize only the ack control word and | |
8415 | * any other control field being set would result in | |
8416 | * flushing the LRO session | |
8417 | */ | |
8418 | return -1; | |
8419 | } | |
8420 | ||
6aa20a22 | 8421 | /* |
7d3d0439 RA |
8422 | * Allow only one TCP timestamp option. Don't aggregate if |
8423 | * any other options are detected. | |
8424 | */ | |
8425 | if (tcp->doff != 5 && tcp->doff != 8) | |
8426 | return -1; | |
8427 | ||
8428 | if (tcp->doff == 8) { | |
6aa20a22 | 8429 | ptr = (u8 *)(tcp + 1); |
7d3d0439 RA |
8430 | while (*ptr == TCPOPT_NOP) |
8431 | ptr++; | |
8432 | if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP) | |
8433 | return -1; | |
8434 | ||
8435 | /* Ensure timestamp value increases monotonically */ | |
8436 | if (l_lro) | |
c8855953 | 8437 | if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2)))) |
7d3d0439 RA |
8438 | return -1; |
8439 | ||
8440 | /* timestamp echo reply should be non-zero */ | |
c8855953 | 8441 | if (*((__be32 *)(ptr+6)) == 0) |
7d3d0439 RA |
8442 | return -1; |
8443 | } | |
8444 | ||
8445 | return 0; | |
8446 | } | |
8447 | ||
d44570e4 JP |
8448 | static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, |
8449 | u8 **tcp, u32 *tcp_len, struct lro **lro, | |
8450 | struct RxD_t *rxdp, struct s2io_nic *sp) | |
7d3d0439 RA |
8451 | { |
8452 | struct iphdr *ip; | |
8453 | struct tcphdr *tcph; | |
8454 | int ret = 0, i; | |
cdb5bf02 | 8455 | u16 vlan_tag = 0; |
ffb5df6c | 8456 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
7d3d0439 | 8457 | |
d44570e4 JP |
8458 | ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp, |
8459 | rxdp, sp); | |
8460 | if (ret) | |
7d3d0439 | 8461 | return ret; |
7d3d0439 | 8462 | |
d44570e4 JP |
8463 | DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr); |
8464 | ||
cdb5bf02 | 8465 | vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2); |
7d3d0439 RA |
8466 | tcph = (struct tcphdr *)*tcp; |
8467 | *tcp_len = get_l4_pyld_length(ip, tcph); | |
d44570e4 | 8468 | for (i = 0; i < MAX_LRO_SESSIONS; i++) { |
0425b46a | 8469 | struct lro *l_lro = &ring_data->lro0_n[i]; |
7d3d0439 RA |
8470 | if (l_lro->in_use) { |
8471 | if (check_for_socket_match(l_lro, ip, tcph)) | |
8472 | continue; | |
8473 | /* Sock pair matched */ | |
8474 | *lro = l_lro; | |
8475 | ||
8476 | if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) { | |
9e39f7c5 JP |
8477 | DBG_PRINT(INFO_DBG, "%s: Out of sequence. " |
8478 | "expected 0x%x, actual 0x%x\n", | |
8479 | __func__, | |
7d3d0439 RA |
8480 | (*lro)->tcp_next_seq, |
8481 | ntohl(tcph->seq)); | |
8482 | ||
ffb5df6c | 8483 | swstats->outof_sequence_pkts++; |
7d3d0439 RA |
8484 | ret = 2; |
8485 | break; | |
8486 | } | |
8487 | ||
d44570e4 JP |
8488 | if (!verify_l3_l4_lro_capable(l_lro, ip, tcph, |
8489 | *tcp_len)) | |
7d3d0439 RA |
8490 | ret = 1; /* Aggregate */ |
8491 | else | |
8492 | ret = 2; /* Flush both */ | |
8493 | break; | |
8494 | } | |
8495 | } | |
8496 | ||
8497 | if (ret == 0) { | |
8498 | /* Before searching for available LRO objects, | |
8499 | * check if the pkt is L3/L4 aggregatable. If not | |
8500 | * don't create new LRO session. Just send this | |
8501 | * packet up. | |
8502 | */ | |
d44570e4 | 8503 | if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) |
7d3d0439 | 8504 | return 5; |
7d3d0439 | 8505 | |
d44570e4 | 8506 | for (i = 0; i < MAX_LRO_SESSIONS; i++) { |
0425b46a | 8507 | struct lro *l_lro = &ring_data->lro0_n[i]; |
7d3d0439 RA |
8508 | if (!(l_lro->in_use)) { |
8509 | *lro = l_lro; | |
8510 | ret = 3; /* Begin anew */ | |
8511 | break; | |
8512 | } | |
8513 | } | |
8514 | } | |
8515 | ||
8516 | if (ret == 0) { /* sessions exceeded */ | |
9e39f7c5 | 8517 | DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n", |
b39d66a8 | 8518 | __func__); |
7d3d0439 RA |
8519 | *lro = NULL; |
8520 | return ret; | |
8521 | } | |
8522 | ||
8523 | switch (ret) { | |
d44570e4 JP |
8524 | case 3: |
8525 | initiate_new_session(*lro, buffer, ip, tcph, *tcp_len, | |
8526 | vlan_tag); | |
8527 | break; | |
8528 | case 2: | |
8529 | update_L3L4_header(sp, *lro); | |
8530 | break; | |
8531 | case 1: | |
8532 | aggregate_new_rx(*lro, ip, tcph, *tcp_len); | |
8533 | if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) { | |
7d3d0439 | 8534 | update_L3L4_header(sp, *lro); |
d44570e4 JP |
8535 | ret = 4; /* Flush the LRO */ |
8536 | } | |
8537 | break; | |
8538 | default: | |
9e39f7c5 | 8539 | DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__); |
d44570e4 | 8540 | break; |
7d3d0439 RA |
8541 | } |
8542 | ||
8543 | return ret; | |
8544 | } | |
8545 | ||
1ee6dd77 | 8546 | static void clear_lro_session(struct lro *lro) |
7d3d0439 | 8547 | { |
1ee6dd77 | 8548 | static u16 lro_struct_size = sizeof(struct lro); |
7d3d0439 RA |
8549 | |
8550 | memset(lro, 0, lro_struct_size); | |
8551 | } | |
8552 | ||
cdb5bf02 | 8553 | static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag) |
7d3d0439 RA |
8554 | { |
8555 | struct net_device *dev = skb->dev; | |
4cf1653a | 8556 | struct s2io_nic *sp = netdev_priv(dev); |
7d3d0439 RA |
8557 | |
8558 | skb->protocol = eth_type_trans(skb, dev); | |
b85da2c0 JP |
8559 | if (vlan_tag && sp->vlan_strip_flag) |
8560 | __vlan_hwaccel_put_tag(skb, vlan_tag); | |
8561 | if (sp->config.napi) | |
8562 | netif_receive_skb(skb); | |
8563 | else | |
8564 | netif_rx(skb); | |
7d3d0439 RA |
8565 | } |
8566 | ||
1ee6dd77 | 8567 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, |
d44570e4 | 8568 | struct sk_buff *skb, u32 tcp_len) |
7d3d0439 | 8569 | { |
75c30b13 | 8570 | struct sk_buff *first = lro->parent; |
ffb5df6c | 8571 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
7d3d0439 RA |
8572 | |
8573 | first->len += tcp_len; | |
8574 | first->data_len = lro->frags_len; | |
8575 | skb_pull(skb, (skb->len - tcp_len)); | |
75c30b13 AR |
8576 | if (skb_shinfo(first)->frag_list) |
8577 | lro->last_frag->next = skb; | |
7d3d0439 RA |
8578 | else |
8579 | skb_shinfo(first)->frag_list = skb; | |
372cc597 | 8580 | first->truesize += skb->truesize; |
75c30b13 | 8581 | lro->last_frag = skb; |
ffb5df6c | 8582 | swstats->clubbed_frms_cnt++; |
7d3d0439 | 8583 | } |
d796fdb7 LV |
8584 | |
8585 | /** | |
8586 | * s2io_io_error_detected - called when PCI error is detected | |
8587 | * @pdev: Pointer to PCI device | |
8453d43f | 8588 | * @state: The current pci connection state |
d796fdb7 LV |
8589 | * |
8590 | * This function is called after a PCI bus error affecting | |
8591 | * this device has been detected. | |
8592 | */ | |
8593 | static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, | |
d44570e4 | 8594 | pci_channel_state_t state) |
d796fdb7 LV |
8595 | { |
8596 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4cf1653a | 8597 | struct s2io_nic *sp = netdev_priv(netdev); |
d796fdb7 LV |
8598 | |
8599 | netif_device_detach(netdev); | |
8600 | ||
1e3c8bd6 DN |
8601 | if (state == pci_channel_io_perm_failure) |
8602 | return PCI_ERS_RESULT_DISCONNECT; | |
8603 | ||
d796fdb7 LV |
8604 | if (netif_running(netdev)) { |
8605 | /* Bring down the card, while avoiding PCI I/O */ | |
8606 | do_s2io_card_down(sp, 0); | |
d796fdb7 LV |
8607 | } |
8608 | pci_disable_device(pdev); | |
8609 | ||
8610 | return PCI_ERS_RESULT_NEED_RESET; | |
8611 | } | |
8612 | ||
8613 | /** | |
8614 | * s2io_io_slot_reset - called after the pci bus has been reset. | |
8615 | * @pdev: Pointer to PCI device | |
8616 | * | |
8617 | * Restart the card from scratch, as if from a cold-boot. | |
8618 | * At this point, the card has exprienced a hard reset, | |
8619 | * followed by fixups by BIOS, and has its config space | |
8620 | * set up identically to what it was at cold boot. | |
8621 | */ | |
8622 | static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev) | |
8623 | { | |
8624 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4cf1653a | 8625 | struct s2io_nic *sp = netdev_priv(netdev); |
d796fdb7 LV |
8626 | |
8627 | if (pci_enable_device(pdev)) { | |
6cef2b8e | 8628 | pr_err("Cannot re-enable PCI device after reset.\n"); |
d796fdb7 LV |
8629 | return PCI_ERS_RESULT_DISCONNECT; |
8630 | } | |
8631 | ||
8632 | pci_set_master(pdev); | |
8633 | s2io_reset(sp); | |
8634 | ||
8635 | return PCI_ERS_RESULT_RECOVERED; | |
8636 | } | |
8637 | ||
8638 | /** | |
8639 | * s2io_io_resume - called when traffic can start flowing again. | |
8640 | * @pdev: Pointer to PCI device | |
8641 | * | |
8642 | * This callback is called when the error recovery driver tells | |
8643 | * us that its OK to resume normal operation. | |
8644 | */ | |
8645 | static void s2io_io_resume(struct pci_dev *pdev) | |
8646 | { | |
8647 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4cf1653a | 8648 | struct s2io_nic *sp = netdev_priv(netdev); |
d796fdb7 LV |
8649 | |
8650 | if (netif_running(netdev)) { | |
8651 | if (s2io_card_up(sp)) { | |
6cef2b8e | 8652 | pr_err("Can't bring device back up after reset.\n"); |
d796fdb7 LV |
8653 | return; |
8654 | } | |
8655 | ||
8656 | if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) { | |
8657 | s2io_card_down(sp); | |
6cef2b8e | 8658 | pr_err("Can't restore mac addr after reset.\n"); |
d796fdb7 LV |
8659 | return; |
8660 | } | |
8661 | } | |
8662 | ||
8663 | netif_device_attach(netdev); | |
fd2ea0a7 | 8664 | netif_tx_wake_all_queues(netdev); |
d796fdb7 | 8665 | } |