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1 | /* |
2 | * drivers/net/ethernet/mellanox/mlxsw/reg.h | |
3 | * Copyright (c) 2015 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> | |
5 | * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> | |
6 | * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions are met: | |
10 | * | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. Neither the names of the copyright holders nor the names of its | |
17 | * contributors may be used to endorse or promote products derived from | |
18 | * this software without specific prior written permission. | |
19 | * | |
20 | * Alternatively, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") version 2 as published by the Free | |
22 | * Software Foundation. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
28 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
29 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
32 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
34 | * POSSIBILITY OF SUCH DAMAGE. | |
35 | */ | |
36 | ||
37 | #ifndef _MLXSW_REG_H | |
38 | #define _MLXSW_REG_H | |
39 | ||
40 | #include <linux/string.h> | |
41 | #include <linux/bitops.h> | |
42 | #include <linux/if_vlan.h> | |
43 | ||
44 | #include "item.h" | |
45 | #include "port.h" | |
46 | ||
47 | struct mlxsw_reg_info { | |
48 | u16 id; | |
49 | u16 len; /* In u8 */ | |
50 | }; | |
51 | ||
52 | #define MLXSW_REG(type) (&mlxsw_reg_##type) | |
53 | #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len | |
54 | #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) | |
55 | ||
56 | /* SGCR - Switch General Configuration Register | |
57 | * -------------------------------------------- | |
58 | * This register is used for configuration of the switch capabilities. | |
59 | */ | |
60 | #define MLXSW_REG_SGCR_ID 0x2000 | |
61 | #define MLXSW_REG_SGCR_LEN 0x10 | |
62 | ||
63 | static const struct mlxsw_reg_info mlxsw_reg_sgcr = { | |
64 | .id = MLXSW_REG_SGCR_ID, | |
65 | .len = MLXSW_REG_SGCR_LEN, | |
66 | }; | |
67 | ||
68 | /* reg_sgcr_llb | |
69 | * Link Local Broadcast (Default=0) | |
70 | * When set, all Link Local packets (224.0.0.X) will be treated as broadcast | |
71 | * packets and ignore the IGMP snooping entries. | |
72 | * Access: RW | |
73 | */ | |
74 | MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); | |
75 | ||
76 | static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) | |
77 | { | |
78 | MLXSW_REG_ZERO(sgcr, payload); | |
79 | mlxsw_reg_sgcr_llb_set(payload, !!llb); | |
80 | } | |
81 | ||
82 | /* SPAD - Switch Physical Address Register | |
83 | * --------------------------------------- | |
84 | * The SPAD register configures the switch physical MAC address. | |
85 | */ | |
86 | #define MLXSW_REG_SPAD_ID 0x2002 | |
87 | #define MLXSW_REG_SPAD_LEN 0x10 | |
88 | ||
89 | static const struct mlxsw_reg_info mlxsw_reg_spad = { | |
90 | .id = MLXSW_REG_SPAD_ID, | |
91 | .len = MLXSW_REG_SPAD_LEN, | |
92 | }; | |
93 | ||
94 | /* reg_spad_base_mac | |
95 | * Base MAC address for the switch partitions. | |
96 | * Per switch partition MAC address is equal to: | |
97 | * base_mac + swid | |
98 | * Access: RW | |
99 | */ | |
100 | MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); | |
101 | ||
e61011b5 IS |
102 | /* SSPR - Switch System Port Record Register |
103 | * ----------------------------------------- | |
104 | * Configures the system port to local port mapping. | |
105 | */ | |
106 | #define MLXSW_REG_SSPR_ID 0x2008 | |
107 | #define MLXSW_REG_SSPR_LEN 0x8 | |
108 | ||
109 | static const struct mlxsw_reg_info mlxsw_reg_sspr = { | |
110 | .id = MLXSW_REG_SSPR_ID, | |
111 | .len = MLXSW_REG_SSPR_LEN, | |
112 | }; | |
113 | ||
114 | /* reg_sspr_m | |
115 | * Master - if set, then the record describes the master system port. | |
116 | * This is needed in case a local port is mapped into several system ports | |
117 | * (for multipathing). That number will be reported as the source system | |
118 | * port when packets are forwarded to the CPU. Only one master port is allowed | |
119 | * per local port. | |
120 | * | |
121 | * Note: Must be set for Spectrum. | |
122 | * Access: RW | |
123 | */ | |
124 | MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); | |
125 | ||
126 | /* reg_sspr_local_port | |
127 | * Local port number. | |
128 | * | |
129 | * Access: RW | |
130 | */ | |
131 | MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); | |
132 | ||
133 | /* reg_sspr_sub_port | |
134 | * Virtual port within the physical port. | |
135 | * Should be set to 0 when virtual ports are not enabled on the port. | |
136 | * | |
137 | * Access: RW | |
138 | */ | |
139 | MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); | |
140 | ||
141 | /* reg_sspr_system_port | |
142 | * Unique identifier within the stacking domain that represents all the ports | |
143 | * that are available in the system (external ports). | |
144 | * | |
145 | * Currently, only single-ASIC configurations are supported, so we default to | |
146 | * 1:1 mapping between system ports and local ports. | |
147 | * Access: Index | |
148 | */ | |
149 | MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); | |
150 | ||
151 | static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) | |
152 | { | |
153 | MLXSW_REG_ZERO(sspr, payload); | |
154 | mlxsw_reg_sspr_m_set(payload, 1); | |
155 | mlxsw_reg_sspr_local_port_set(payload, local_port); | |
156 | mlxsw_reg_sspr_sub_port_set(payload, 0); | |
157 | mlxsw_reg_sspr_system_port_set(payload, local_port); | |
158 | } | |
159 | ||
e534a56a JP |
160 | /* SFDAT - Switch Filtering Database Aging Time |
161 | * -------------------------------------------- | |
162 | * Controls the Switch aging time. Aging time is able to be set per Switch | |
163 | * Partition. | |
164 | */ | |
165 | #define MLXSW_REG_SFDAT_ID 0x2009 | |
166 | #define MLXSW_REG_SFDAT_LEN 0x8 | |
167 | ||
168 | static const struct mlxsw_reg_info mlxsw_reg_sfdat = { | |
169 | .id = MLXSW_REG_SFDAT_ID, | |
170 | .len = MLXSW_REG_SFDAT_LEN, | |
171 | }; | |
172 | ||
173 | /* reg_sfdat_swid | |
174 | * Switch partition ID. | |
175 | * Access: Index | |
176 | */ | |
177 | MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); | |
178 | ||
179 | /* reg_sfdat_age_time | |
180 | * Aging time in seconds | |
181 | * Min - 10 seconds | |
182 | * Max - 1,000,000 seconds | |
183 | * Default is 300 seconds. | |
184 | * Access: RW | |
185 | */ | |
186 | MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); | |
187 | ||
188 | static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) | |
189 | { | |
190 | MLXSW_REG_ZERO(sfdat, payload); | |
191 | mlxsw_reg_sfdat_swid_set(payload, 0); | |
192 | mlxsw_reg_sfdat_age_time_set(payload, age_time); | |
193 | } | |
194 | ||
236033b3 JP |
195 | /* SFD - Switch Filtering Database |
196 | * ------------------------------- | |
197 | * The following register defines the access to the filtering database. | |
198 | * The register supports querying, adding, removing and modifying the database. | |
199 | * The access is optimized for bulk updates in which case more than one | |
200 | * FDB record is present in the same command. | |
201 | */ | |
202 | #define MLXSW_REG_SFD_ID 0x200A | |
203 | #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ | |
204 | #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ | |
205 | #define MLXSW_REG_SFD_REC_MAX_COUNT 64 | |
206 | #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ | |
207 | MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) | |
208 | ||
209 | static const struct mlxsw_reg_info mlxsw_reg_sfd = { | |
210 | .id = MLXSW_REG_SFD_ID, | |
211 | .len = MLXSW_REG_SFD_LEN, | |
212 | }; | |
213 | ||
214 | /* reg_sfd_swid | |
215 | * Switch partition ID for queries. Reserved on Write. | |
216 | * Access: Index | |
217 | */ | |
218 | MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); | |
219 | ||
220 | enum mlxsw_reg_sfd_op { | |
221 | /* Dump entire FDB a (process according to record_locator) */ | |
222 | MLXSW_REG_SFD_OP_QUERY_DUMP = 0, | |
223 | /* Query records by {MAC, VID/FID} value */ | |
224 | MLXSW_REG_SFD_OP_QUERY_QUERY = 1, | |
225 | /* Query and clear activity. Query records by {MAC, VID/FID} value */ | |
226 | MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, | |
227 | /* Test. Response indicates if each of the records could be | |
228 | * added to the FDB. | |
229 | */ | |
230 | MLXSW_REG_SFD_OP_WRITE_TEST = 0, | |
231 | /* Add/modify. Aged-out records cannot be added. This command removes | |
232 | * the learning notification of the {MAC, VID/FID}. Response includes | |
233 | * the entries that were added to the FDB. | |
234 | */ | |
235 | MLXSW_REG_SFD_OP_WRITE_EDIT = 1, | |
236 | /* Remove record by {MAC, VID/FID}. This command also removes | |
237 | * the learning notification and aged-out notifications | |
238 | * of the {MAC, VID/FID}. The response provides current (pre-removal) | |
239 | * entries as non-aged-out. | |
240 | */ | |
241 | MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, | |
242 | /* Remove learned notification by {MAC, VID/FID}. The response provides | |
243 | * the removed learning notification. | |
244 | */ | |
245 | MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, | |
246 | }; | |
247 | ||
248 | /* reg_sfd_op | |
249 | * Operation. | |
250 | * Access: OP | |
251 | */ | |
252 | MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); | |
253 | ||
254 | /* reg_sfd_record_locator | |
255 | * Used for querying the FDB. Use record_locator=0 to initiate the | |
256 | * query. When a record is returned, a new record_locator is | |
257 | * returned to be used in the subsequent query. | |
258 | * Reserved for database update. | |
259 | * Access: Index | |
260 | */ | |
261 | MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); | |
262 | ||
263 | /* reg_sfd_num_rec | |
264 | * Request: Number of records to read/add/modify/remove | |
265 | * Response: Number of records read/added/replaced/removed | |
266 | * See above description for more details. | |
267 | * Ranges 0..64 | |
268 | * Access: RW | |
269 | */ | |
270 | MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); | |
271 | ||
272 | static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, | |
273 | u32 record_locator) | |
274 | { | |
275 | MLXSW_REG_ZERO(sfd, payload); | |
276 | mlxsw_reg_sfd_op_set(payload, op); | |
277 | mlxsw_reg_sfd_record_locator_set(payload, record_locator); | |
278 | } | |
279 | ||
280 | /* reg_sfd_rec_swid | |
281 | * Switch partition ID. | |
282 | * Access: Index | |
283 | */ | |
284 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, | |
285 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
286 | ||
287 | enum mlxsw_reg_sfd_rec_type { | |
288 | MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, | |
289 | }; | |
290 | ||
291 | /* reg_sfd_rec_type | |
292 | * FDB record type. | |
293 | * Access: RW | |
294 | */ | |
295 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, | |
296 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
297 | ||
298 | enum mlxsw_reg_sfd_rec_policy { | |
299 | /* Replacement disabled, aging disabled. */ | |
300 | MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, | |
301 | /* (mlag remote): Replacement enabled, aging disabled, | |
302 | * learning notification enabled on this port. | |
303 | */ | |
304 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, | |
305 | /* (ingress device): Replacement enabled, aging enabled. */ | |
306 | MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, | |
307 | }; | |
308 | ||
309 | /* reg_sfd_rec_policy | |
310 | * Policy. | |
311 | * Access: RW | |
312 | */ | |
313 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, | |
314 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
315 | ||
316 | /* reg_sfd_rec_a | |
317 | * Activity. Set for new static entries. Set for static entries if a frame SMAC | |
318 | * lookup hits on the entry. | |
319 | * To clear the a bit, use "query and clear activity" op. | |
320 | * Access: RO | |
321 | */ | |
322 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, | |
323 | MLXSW_REG_SFD_REC_LEN, 0x00, false); | |
324 | ||
325 | /* reg_sfd_rec_mac | |
326 | * MAC address. | |
327 | * Access: Index | |
328 | */ | |
329 | MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, | |
330 | MLXSW_REG_SFD_REC_LEN, 0x02); | |
331 | ||
332 | enum mlxsw_reg_sfd_rec_action { | |
333 | /* forward */ | |
334 | MLXSW_REG_SFD_REC_ACTION_NOP = 0, | |
335 | /* forward and trap, trap_id is FDB_TRAP */ | |
336 | MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, | |
337 | /* trap and do not forward, trap_id is FDB_TRAP */ | |
338 | MLXSW_REG_SFD_REC_ACTION_TRAP = 3, | |
339 | MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, | |
340 | }; | |
341 | ||
342 | /* reg_sfd_rec_action | |
343 | * Action to apply on the packet. | |
344 | * Note: Dynamic entries can only be configured with NOP action. | |
345 | * Access: RW | |
346 | */ | |
347 | MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, | |
348 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
349 | ||
350 | /* reg_sfd_uc_sub_port | |
4e9ec083 JP |
351 | * VEPA channel on local port. |
352 | * Valid only if local port is a non-stacking port. Must be 0 if multichannel | |
353 | * VEPA is not enabled. | |
236033b3 JP |
354 | * Access: RW |
355 | */ | |
356 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, | |
357 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
358 | ||
359 | /* reg_sfd_uc_fid_vid | |
360 | * Filtering ID or VLAN ID | |
361 | * For SwitchX and SwitchX-2: | |
362 | * - Dynamic entries (policy 2,3) use FID | |
363 | * - Static entries (policy 0) use VID | |
364 | * - When independent learning is configured, VID=FID | |
365 | * For Spectrum: use FID for both Dynamic and Static entries. | |
366 | * VID should not be used. | |
367 | * Access: Index | |
368 | */ | |
369 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
370 | MLXSW_REG_SFD_REC_LEN, 0x08, false); | |
371 | ||
372 | /* reg_sfd_uc_system_port | |
373 | * Unique port identifier for the final destination of the packet. | |
374 | * Access: RW | |
375 | */ | |
376 | MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, | |
377 | MLXSW_REG_SFD_REC_LEN, 0x0C, false); | |
378 | ||
379 | static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, | |
380 | enum mlxsw_reg_sfd_rec_policy policy, | |
381 | const char *mac, u16 vid, | |
382 | enum mlxsw_reg_sfd_rec_action action, | |
383 | u8 local_port) | |
384 | { | |
385 | u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); | |
386 | ||
387 | if (rec_index >= num_rec) | |
388 | mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); | |
389 | mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); | |
390 | mlxsw_reg_sfd_rec_type_set(payload, rec_index, | |
391 | MLXSW_REG_SFD_REC_TYPE_UNICAST); | |
392 | mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); | |
393 | mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); | |
394 | mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); | |
395 | mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, vid); | |
396 | mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); | |
397 | mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); | |
398 | } | |
399 | ||
75c09280 JP |
400 | static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, |
401 | char *mac, u16 *p_vid, | |
402 | u8 *p_local_port) | |
236033b3 JP |
403 | { |
404 | mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); | |
405 | *p_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); | |
406 | *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); | |
407 | } | |
408 | ||
f5d88f58 JP |
409 | /* SFN - Switch FDB Notification Register |
410 | * ------------------------------------------- | |
411 | * The switch provides notifications on newly learned FDB entries and | |
412 | * aged out entries. The notifications can be polled by software. | |
413 | */ | |
414 | #define MLXSW_REG_SFN_ID 0x200B | |
415 | #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ | |
416 | #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ | |
417 | #define MLXSW_REG_SFN_REC_MAX_COUNT 64 | |
418 | #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ | |
419 | MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) | |
420 | ||
421 | static const struct mlxsw_reg_info mlxsw_reg_sfn = { | |
422 | .id = MLXSW_REG_SFN_ID, | |
423 | .len = MLXSW_REG_SFN_LEN, | |
424 | }; | |
425 | ||
426 | /* reg_sfn_swid | |
427 | * Switch partition ID. | |
428 | * Access: Index | |
429 | */ | |
430 | MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); | |
431 | ||
432 | /* reg_sfn_num_rec | |
433 | * Request: Number of learned notifications and aged-out notification | |
434 | * records requested. | |
435 | * Response: Number of notification records returned (must be smaller | |
436 | * than or equal to the value requested) | |
437 | * Ranges 0..64 | |
438 | * Access: OP | |
439 | */ | |
440 | MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); | |
441 | ||
442 | static inline void mlxsw_reg_sfn_pack(char *payload) | |
443 | { | |
444 | MLXSW_REG_ZERO(sfn, payload); | |
445 | mlxsw_reg_sfn_swid_set(payload, 0); | |
446 | mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); | |
447 | } | |
448 | ||
449 | /* reg_sfn_rec_swid | |
450 | * Switch partition ID. | |
451 | * Access: RO | |
452 | */ | |
453 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, | |
454 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
455 | ||
456 | enum mlxsw_reg_sfn_rec_type { | |
457 | /* MAC addresses learned on a regular port. */ | |
458 | MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, | |
459 | /* Aged-out MAC address on a regular port */ | |
460 | MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, | |
461 | }; | |
462 | ||
463 | /* reg_sfn_rec_type | |
464 | * Notification record type. | |
465 | * Access: RO | |
466 | */ | |
467 | MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, | |
468 | MLXSW_REG_SFN_REC_LEN, 0x00, false); | |
469 | ||
470 | /* reg_sfn_rec_mac | |
471 | * MAC address. | |
472 | * Access: RO | |
473 | */ | |
474 | MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, | |
475 | MLXSW_REG_SFN_REC_LEN, 0x02); | |
476 | ||
8316f087 | 477 | /* reg_sfn_mac_sub_port |
f5d88f58 JP |
478 | * VEPA channel on the local port. |
479 | * 0 if multichannel VEPA is not enabled. | |
480 | * Access: RO | |
481 | */ | |
482 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, | |
483 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
484 | ||
8316f087 | 485 | /* reg_sfn_mac_fid |
f5d88f58 JP |
486 | * Filtering identifier. |
487 | * Access: RO | |
488 | */ | |
489 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
490 | MLXSW_REG_SFN_REC_LEN, 0x08, false); | |
491 | ||
8316f087 | 492 | /* reg_sfn_mac_system_port |
f5d88f58 JP |
493 | * Unique port identifier for the final destination of the packet. |
494 | * Access: RO | |
495 | */ | |
496 | MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, | |
497 | MLXSW_REG_SFN_REC_LEN, 0x0C, false); | |
498 | ||
499 | static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, | |
500 | char *mac, u16 *p_vid, | |
501 | u8 *p_local_port) | |
502 | { | |
503 | mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); | |
504 | *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); | |
505 | *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); | |
506 | } | |
507 | ||
4ec14b76 IS |
508 | /* SPMS - Switch Port MSTP/RSTP State Register |
509 | * ------------------------------------------- | |
510 | * Configures the spanning tree state of a physical port. | |
511 | */ | |
3f0effd1 | 512 | #define MLXSW_REG_SPMS_ID 0x200D |
4ec14b76 IS |
513 | #define MLXSW_REG_SPMS_LEN 0x404 |
514 | ||
515 | static const struct mlxsw_reg_info mlxsw_reg_spms = { | |
516 | .id = MLXSW_REG_SPMS_ID, | |
517 | .len = MLXSW_REG_SPMS_LEN, | |
518 | }; | |
519 | ||
520 | /* reg_spms_local_port | |
521 | * Local port number. | |
522 | * Access: Index | |
523 | */ | |
524 | MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); | |
525 | ||
526 | enum mlxsw_reg_spms_state { | |
527 | MLXSW_REG_SPMS_STATE_NO_CHANGE, | |
528 | MLXSW_REG_SPMS_STATE_DISCARDING, | |
529 | MLXSW_REG_SPMS_STATE_LEARNING, | |
530 | MLXSW_REG_SPMS_STATE_FORWARDING, | |
531 | }; | |
532 | ||
533 | /* reg_spms_state | |
534 | * Spanning tree state of each VLAN ID (VID) of the local port. | |
535 | * 0 - Do not change spanning tree state (used only when writing). | |
536 | * 1 - Discarding. No learning or forwarding to/from this port (default). | |
537 | * 2 - Learning. Port is learning, but not forwarding. | |
538 | * 3 - Forwarding. Port is learning and forwarding. | |
539 | * Access: RW | |
540 | */ | |
541 | MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); | |
542 | ||
ebb7963f | 543 | static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) |
4ec14b76 IS |
544 | { |
545 | MLXSW_REG_ZERO(spms, payload); | |
546 | mlxsw_reg_spms_local_port_set(payload, local_port); | |
ebb7963f JP |
547 | } |
548 | ||
549 | static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, | |
550 | enum mlxsw_reg_spms_state state) | |
551 | { | |
4ec14b76 IS |
552 | mlxsw_reg_spms_state_set(payload, vid, state); |
553 | } | |
554 | ||
b2e345f9 ER |
555 | /* SPVID - Switch Port VID |
556 | * ----------------------- | |
557 | * The switch port VID configures the default VID for a port. | |
558 | */ | |
559 | #define MLXSW_REG_SPVID_ID 0x200E | |
560 | #define MLXSW_REG_SPVID_LEN 0x08 | |
561 | ||
562 | static const struct mlxsw_reg_info mlxsw_reg_spvid = { | |
563 | .id = MLXSW_REG_SPVID_ID, | |
564 | .len = MLXSW_REG_SPVID_LEN, | |
565 | }; | |
566 | ||
567 | /* reg_spvid_local_port | |
568 | * Local port number. | |
569 | * Access: Index | |
570 | */ | |
571 | MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); | |
572 | ||
573 | /* reg_spvid_sub_port | |
574 | * Virtual port within the physical port. | |
575 | * Should be set to 0 when virtual ports are not enabled on the port. | |
576 | * Access: Index | |
577 | */ | |
578 | MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); | |
579 | ||
580 | /* reg_spvid_pvid | |
581 | * Port default VID | |
582 | * Access: RW | |
583 | */ | |
584 | MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); | |
585 | ||
586 | static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) | |
587 | { | |
588 | MLXSW_REG_ZERO(spvid, payload); | |
589 | mlxsw_reg_spvid_local_port_set(payload, local_port); | |
590 | mlxsw_reg_spvid_pvid_set(payload, pvid); | |
591 | } | |
592 | ||
593 | /* SPVM - Switch Port VLAN Membership | |
594 | * ---------------------------------- | |
595 | * The Switch Port VLAN Membership register configures the VLAN membership | |
596 | * of a port in a VLAN denoted by VID. VLAN membership is managed per | |
597 | * virtual port. The register can be used to add and remove VID(s) from a port. | |
598 | */ | |
599 | #define MLXSW_REG_SPVM_ID 0x200F | |
600 | #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ | |
601 | #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ | |
e934e135 | 602 | #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 |
b2e345f9 ER |
603 | #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ |
604 | MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) | |
605 | ||
606 | static const struct mlxsw_reg_info mlxsw_reg_spvm = { | |
607 | .id = MLXSW_REG_SPVM_ID, | |
608 | .len = MLXSW_REG_SPVM_LEN, | |
609 | }; | |
610 | ||
611 | /* reg_spvm_pt | |
612 | * Priority tagged. If this bit is set, packets forwarded to the port with | |
613 | * untagged VLAN membership (u bit is set) will be tagged with priority tag | |
614 | * (VID=0) | |
615 | * Access: RW | |
616 | */ | |
617 | MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); | |
618 | ||
619 | /* reg_spvm_pte | |
620 | * Priority Tagged Update Enable. On Write operations, if this bit is cleared, | |
621 | * the pt bit will NOT be updated. To update the pt bit, pte must be set. | |
622 | * Access: WO | |
623 | */ | |
624 | MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); | |
625 | ||
626 | /* reg_spvm_local_port | |
627 | * Local port number. | |
628 | * Access: Index | |
629 | */ | |
630 | MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); | |
631 | ||
632 | /* reg_spvm_sub_port | |
633 | * Virtual port within the physical port. | |
634 | * Should be set to 0 when virtual ports are not enabled on the port. | |
635 | * Access: Index | |
636 | */ | |
637 | MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); | |
638 | ||
639 | /* reg_spvm_num_rec | |
640 | * Number of records to update. Each record contains: i, e, u, vid. | |
641 | * Access: OP | |
642 | */ | |
643 | MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); | |
644 | ||
645 | /* reg_spvm_rec_i | |
646 | * Ingress membership in VLAN ID. | |
647 | * Access: Index | |
648 | */ | |
649 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, | |
650 | MLXSW_REG_SPVM_BASE_LEN, 14, 1, | |
651 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
652 | ||
653 | /* reg_spvm_rec_e | |
654 | * Egress membership in VLAN ID. | |
655 | * Access: Index | |
656 | */ | |
657 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, | |
658 | MLXSW_REG_SPVM_BASE_LEN, 13, 1, | |
659 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
660 | ||
661 | /* reg_spvm_rec_u | |
662 | * Untagged - port is an untagged member - egress transmission uses untagged | |
663 | * frames on VID<n> | |
664 | * Access: Index | |
665 | */ | |
666 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, | |
667 | MLXSW_REG_SPVM_BASE_LEN, 12, 1, | |
668 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
669 | ||
670 | /* reg_spvm_rec_vid | |
671 | * Egress membership in VLAN ID. | |
672 | * Access: Index | |
673 | */ | |
674 | MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, | |
675 | MLXSW_REG_SPVM_BASE_LEN, 0, 12, | |
676 | MLXSW_REG_SPVM_REC_LEN, 0, false); | |
677 | ||
678 | static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, | |
679 | u16 vid_begin, u16 vid_end, | |
680 | bool is_member, bool untagged) | |
681 | { | |
682 | int size = vid_end - vid_begin + 1; | |
683 | int i; | |
684 | ||
685 | MLXSW_REG_ZERO(spvm, payload); | |
686 | mlxsw_reg_spvm_local_port_set(payload, local_port); | |
687 | mlxsw_reg_spvm_num_rec_set(payload, size); | |
688 | ||
689 | for (i = 0; i < size; i++) { | |
690 | mlxsw_reg_spvm_rec_i_set(payload, i, is_member); | |
691 | mlxsw_reg_spvm_rec_e_set(payload, i, is_member); | |
692 | mlxsw_reg_spvm_rec_u_set(payload, i, untagged); | |
693 | mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); | |
694 | } | |
695 | } | |
696 | ||
4ec14b76 IS |
697 | /* SFGC - Switch Flooding Group Configuration |
698 | * ------------------------------------------ | |
699 | * The following register controls the association of flooding tables and MIDs | |
700 | * to packet types used for flooding. | |
701 | */ | |
36b78e8a | 702 | #define MLXSW_REG_SFGC_ID 0x2011 |
4ec14b76 IS |
703 | #define MLXSW_REG_SFGC_LEN 0x10 |
704 | ||
705 | static const struct mlxsw_reg_info mlxsw_reg_sfgc = { | |
706 | .id = MLXSW_REG_SFGC_ID, | |
707 | .len = MLXSW_REG_SFGC_LEN, | |
708 | }; | |
709 | ||
710 | enum mlxsw_reg_sfgc_type { | |
fa6ad058 IS |
711 | MLXSW_REG_SFGC_TYPE_BROADCAST, |
712 | MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, | |
713 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, | |
714 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, | |
715 | MLXSW_REG_SFGC_TYPE_RESERVED, | |
716 | MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, | |
717 | MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, | |
718 | MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, | |
719 | MLXSW_REG_SFGC_TYPE_MAX, | |
4ec14b76 IS |
720 | }; |
721 | ||
722 | /* reg_sfgc_type | |
723 | * The traffic type to reach the flooding table. | |
724 | * Access: Index | |
725 | */ | |
726 | MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); | |
727 | ||
728 | enum mlxsw_reg_sfgc_bridge_type { | |
729 | MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, | |
730 | MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, | |
731 | }; | |
732 | ||
733 | /* reg_sfgc_bridge_type | |
734 | * Access: Index | |
735 | * | |
736 | * Note: SwitchX-2 only supports 802.1Q mode. | |
737 | */ | |
738 | MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); | |
739 | ||
740 | enum mlxsw_flood_table_type { | |
741 | MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, | |
742 | MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, | |
743 | MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, | |
744 | MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3, | |
745 | MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, | |
746 | }; | |
747 | ||
748 | /* reg_sfgc_table_type | |
749 | * See mlxsw_flood_table_type | |
750 | * Access: RW | |
751 | * | |
752 | * Note: FID offset and FID types are not supported in SwitchX-2. | |
753 | */ | |
754 | MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); | |
755 | ||
756 | /* reg_sfgc_flood_table | |
757 | * Flooding table index to associate with the specific type on the specific | |
758 | * switch partition. | |
759 | * Access: RW | |
760 | */ | |
761 | MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); | |
762 | ||
763 | /* reg_sfgc_mid | |
764 | * The multicast ID for the swid. Not supported for Spectrum | |
765 | * Access: RW | |
766 | */ | |
767 | MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); | |
768 | ||
769 | /* reg_sfgc_counter_set_type | |
770 | * Counter Set Type for flow counters. | |
771 | * Access: RW | |
772 | */ | |
773 | MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); | |
774 | ||
775 | /* reg_sfgc_counter_index | |
776 | * Counter Index for flow counters. | |
777 | * Access: RW | |
778 | */ | |
779 | MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); | |
780 | ||
781 | static inline void | |
782 | mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, | |
783 | enum mlxsw_reg_sfgc_bridge_type bridge_type, | |
784 | enum mlxsw_flood_table_type table_type, | |
785 | unsigned int flood_table) | |
786 | { | |
787 | MLXSW_REG_ZERO(sfgc, payload); | |
788 | mlxsw_reg_sfgc_type_set(payload, type); | |
789 | mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); | |
790 | mlxsw_reg_sfgc_table_type_set(payload, table_type); | |
791 | mlxsw_reg_sfgc_flood_table_set(payload, flood_table); | |
792 | mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); | |
793 | } | |
794 | ||
795 | /* SFTR - Switch Flooding Table Register | |
796 | * ------------------------------------- | |
797 | * The switch flooding table is used for flooding packet replication. The table | |
798 | * defines a bit mask of ports for packet replication. | |
799 | */ | |
800 | #define MLXSW_REG_SFTR_ID 0x2012 | |
801 | #define MLXSW_REG_SFTR_LEN 0x420 | |
802 | ||
803 | static const struct mlxsw_reg_info mlxsw_reg_sftr = { | |
804 | .id = MLXSW_REG_SFTR_ID, | |
805 | .len = MLXSW_REG_SFTR_LEN, | |
806 | }; | |
807 | ||
808 | /* reg_sftr_swid | |
809 | * Switch partition ID with which to associate the port. | |
810 | * Access: Index | |
811 | */ | |
812 | MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); | |
813 | ||
814 | /* reg_sftr_flood_table | |
815 | * Flooding table index to associate with the specific type on the specific | |
816 | * switch partition. | |
817 | * Access: Index | |
818 | */ | |
819 | MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); | |
820 | ||
821 | /* reg_sftr_index | |
822 | * Index. Used as an index into the Flooding Table in case the table is | |
823 | * configured to use VID / FID or FID Offset. | |
824 | * Access: Index | |
825 | */ | |
826 | MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); | |
827 | ||
828 | /* reg_sftr_table_type | |
829 | * See mlxsw_flood_table_type | |
830 | * Access: RW | |
831 | */ | |
832 | MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); | |
833 | ||
834 | /* reg_sftr_range | |
835 | * Range of entries to update | |
836 | * Access: Index | |
837 | */ | |
838 | MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); | |
839 | ||
840 | /* reg_sftr_port | |
841 | * Local port membership (1 bit per port). | |
842 | * Access: RW | |
843 | */ | |
844 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); | |
845 | ||
846 | /* reg_sftr_cpu_port_mask | |
847 | * CPU port mask (1 bit per port). | |
848 | * Access: W | |
849 | */ | |
850 | MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); | |
851 | ||
852 | static inline void mlxsw_reg_sftr_pack(char *payload, | |
853 | unsigned int flood_table, | |
854 | unsigned int index, | |
855 | enum mlxsw_flood_table_type table_type, | |
bc2055f8 | 856 | unsigned int range, u8 port, bool set) |
4ec14b76 IS |
857 | { |
858 | MLXSW_REG_ZERO(sftr, payload); | |
859 | mlxsw_reg_sftr_swid_set(payload, 0); | |
860 | mlxsw_reg_sftr_flood_table_set(payload, flood_table); | |
861 | mlxsw_reg_sftr_index_set(payload, index); | |
862 | mlxsw_reg_sftr_table_type_set(payload, table_type); | |
863 | mlxsw_reg_sftr_range_set(payload, range); | |
bc2055f8 IS |
864 | mlxsw_reg_sftr_port_set(payload, port, set); |
865 | mlxsw_reg_sftr_port_mask_set(payload, port, 1); | |
4ec14b76 IS |
866 | } |
867 | ||
868 | /* SPMLR - Switch Port MAC Learning Register | |
869 | * ----------------------------------------- | |
870 | * Controls the Switch MAC learning policy per port. | |
871 | */ | |
872 | #define MLXSW_REG_SPMLR_ID 0x2018 | |
873 | #define MLXSW_REG_SPMLR_LEN 0x8 | |
874 | ||
875 | static const struct mlxsw_reg_info mlxsw_reg_spmlr = { | |
876 | .id = MLXSW_REG_SPMLR_ID, | |
877 | .len = MLXSW_REG_SPMLR_LEN, | |
878 | }; | |
879 | ||
880 | /* reg_spmlr_local_port | |
881 | * Local port number. | |
882 | * Access: Index | |
883 | */ | |
884 | MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); | |
885 | ||
886 | /* reg_spmlr_sub_port | |
887 | * Virtual port within the physical port. | |
888 | * Should be set to 0 when virtual ports are not enabled on the port. | |
889 | * Access: Index | |
890 | */ | |
891 | MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); | |
892 | ||
893 | enum mlxsw_reg_spmlr_learn_mode { | |
894 | MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, | |
895 | MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, | |
896 | MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, | |
897 | }; | |
898 | ||
899 | /* reg_spmlr_learn_mode | |
900 | * Learning mode on the port. | |
901 | * 0 - Learning disabled. | |
902 | * 2 - Learning enabled. | |
903 | * 3 - Security mode. | |
904 | * | |
905 | * In security mode the switch does not learn MACs on the port, but uses the | |
906 | * SMAC to see if it exists on another ingress port. If so, the packet is | |
907 | * classified as a bad packet and is discarded unless the software registers | |
908 | * to receive port security error packets usign HPKT. | |
909 | */ | |
910 | MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); | |
911 | ||
912 | static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, | |
913 | enum mlxsw_reg_spmlr_learn_mode mode) | |
914 | { | |
915 | MLXSW_REG_ZERO(spmlr, payload); | |
916 | mlxsw_reg_spmlr_local_port_set(payload, local_port); | |
917 | mlxsw_reg_spmlr_sub_port_set(payload, 0); | |
918 | mlxsw_reg_spmlr_learn_mode_set(payload, mode); | |
919 | } | |
920 | ||
64790239 IS |
921 | /* SVFA - Switch VID to FID Allocation Register |
922 | * -------------------------------------------- | |
923 | * Controls the VID to FID mapping and {Port, VID} to FID mapping for | |
924 | * virtualized ports. | |
925 | */ | |
926 | #define MLXSW_REG_SVFA_ID 0x201C | |
927 | #define MLXSW_REG_SVFA_LEN 0x10 | |
928 | ||
929 | static const struct mlxsw_reg_info mlxsw_reg_svfa = { | |
930 | .id = MLXSW_REG_SVFA_ID, | |
931 | .len = MLXSW_REG_SVFA_LEN, | |
932 | }; | |
933 | ||
934 | /* reg_svfa_swid | |
935 | * Switch partition ID. | |
936 | * Access: Index | |
937 | */ | |
938 | MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); | |
939 | ||
940 | /* reg_svfa_local_port | |
941 | * Local port number. | |
942 | * Access: Index | |
943 | * | |
944 | * Note: Reserved for 802.1Q FIDs. | |
945 | */ | |
946 | MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); | |
947 | ||
948 | enum mlxsw_reg_svfa_mt { | |
949 | MLXSW_REG_SVFA_MT_VID_TO_FID, | |
950 | MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, | |
951 | }; | |
952 | ||
953 | /* reg_svfa_mapping_table | |
954 | * Mapping table: | |
955 | * 0 - VID to FID | |
956 | * 1 - {Port, VID} to FID | |
957 | * Access: Index | |
958 | * | |
959 | * Note: Reserved for SwitchX-2. | |
960 | */ | |
961 | MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); | |
962 | ||
963 | /* reg_svfa_v | |
964 | * Valid. | |
965 | * Valid if set. | |
966 | * Access: RW | |
967 | * | |
968 | * Note: Reserved for SwitchX-2. | |
969 | */ | |
970 | MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); | |
971 | ||
972 | /* reg_svfa_fid | |
973 | * Filtering ID. | |
974 | * Access: RW | |
975 | */ | |
976 | MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); | |
977 | ||
978 | /* reg_svfa_vid | |
979 | * VLAN ID. | |
980 | * Access: Index | |
981 | */ | |
982 | MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); | |
983 | ||
984 | /* reg_svfa_counter_set_type | |
985 | * Counter set type for flow counters. | |
986 | * Access: RW | |
987 | * | |
988 | * Note: Reserved for SwitchX-2. | |
989 | */ | |
990 | MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); | |
991 | ||
992 | /* reg_svfa_counter_index | |
993 | * Counter index for flow counters. | |
994 | * Access: RW | |
995 | * | |
996 | * Note: Reserved for SwitchX-2. | |
997 | */ | |
998 | MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); | |
999 | ||
1000 | static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, | |
1001 | enum mlxsw_reg_svfa_mt mt, bool valid, | |
1002 | u16 fid, u16 vid) | |
1003 | { | |
1004 | MLXSW_REG_ZERO(svfa, payload); | |
1005 | local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; | |
1006 | mlxsw_reg_svfa_swid_set(payload, 0); | |
1007 | mlxsw_reg_svfa_local_port_set(payload, local_port); | |
1008 | mlxsw_reg_svfa_mapping_table_set(payload, mt); | |
1009 | mlxsw_reg_svfa_v_set(payload, valid); | |
1010 | mlxsw_reg_svfa_fid_set(payload, fid); | |
1011 | mlxsw_reg_svfa_vid_set(payload, vid); | |
1012 | } | |
1013 | ||
1f65da74 IS |
1014 | /* SVPE - Switch Virtual-Port Enabling Register |
1015 | * -------------------------------------------- | |
1016 | * Enables port virtualization. | |
1017 | */ | |
1018 | #define MLXSW_REG_SVPE_ID 0x201E | |
1019 | #define MLXSW_REG_SVPE_LEN 0x4 | |
1020 | ||
1021 | static const struct mlxsw_reg_info mlxsw_reg_svpe = { | |
1022 | .id = MLXSW_REG_SVPE_ID, | |
1023 | .len = MLXSW_REG_SVPE_LEN, | |
1024 | }; | |
1025 | ||
1026 | /* reg_svpe_local_port | |
1027 | * Local port number | |
1028 | * Access: Index | |
1029 | * | |
1030 | * Note: CPU port is not supported (uses VLAN mode only). | |
1031 | */ | |
1032 | MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); | |
1033 | ||
1034 | /* reg_svpe_vp_en | |
1035 | * Virtual port enable. | |
1036 | * 0 - Disable, VLAN mode (VID to FID). | |
1037 | * 1 - Enable, Virtual port mode ({Port, VID} to FID). | |
1038 | * Access: RW | |
1039 | */ | |
1040 | MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); | |
1041 | ||
1042 | static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, | |
1043 | bool enable) | |
1044 | { | |
1045 | MLXSW_REG_ZERO(svpe, payload); | |
1046 | mlxsw_reg_svpe_local_port_set(payload, local_port); | |
1047 | mlxsw_reg_svpe_vp_en_set(payload, enable); | |
1048 | } | |
1049 | ||
f1fb693a IS |
1050 | /* SFMR - Switch FID Management Register |
1051 | * ------------------------------------- | |
1052 | * Creates and configures FIDs. | |
1053 | */ | |
1054 | #define MLXSW_REG_SFMR_ID 0x201F | |
1055 | #define MLXSW_REG_SFMR_LEN 0x18 | |
1056 | ||
1057 | static const struct mlxsw_reg_info mlxsw_reg_sfmr = { | |
1058 | .id = MLXSW_REG_SFMR_ID, | |
1059 | .len = MLXSW_REG_SFMR_LEN, | |
1060 | }; | |
1061 | ||
1062 | enum mlxsw_reg_sfmr_op { | |
1063 | MLXSW_REG_SFMR_OP_CREATE_FID, | |
1064 | MLXSW_REG_SFMR_OP_DESTROY_FID, | |
1065 | }; | |
1066 | ||
1067 | /* reg_sfmr_op | |
1068 | * Operation. | |
1069 | * 0 - Create or edit FID. | |
1070 | * 1 - Destroy FID. | |
1071 | * Access: WO | |
1072 | */ | |
1073 | MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); | |
1074 | ||
1075 | /* reg_sfmr_fid | |
1076 | * Filtering ID. | |
1077 | * Access: Index | |
1078 | */ | |
1079 | MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); | |
1080 | ||
1081 | /* reg_sfmr_fid_offset | |
1082 | * FID offset. | |
1083 | * Used to point into the flooding table selected by SFGC register if | |
1084 | * the table is of type FID-Offset. Otherwise, this field is reserved. | |
1085 | * Access: RW | |
1086 | */ | |
1087 | MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); | |
1088 | ||
1089 | /* reg_sfmr_vtfp | |
1090 | * Valid Tunnel Flood Pointer. | |
1091 | * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. | |
1092 | * Access: RW | |
1093 | * | |
1094 | * Note: Reserved for 802.1Q FIDs. | |
1095 | */ | |
1096 | MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); | |
1097 | ||
1098 | /* reg_sfmr_nve_tunnel_flood_ptr | |
1099 | * Underlay Flooding and BC Pointer. | |
1100 | * Used as a pointer to the first entry of the group based link lists of | |
1101 | * flooding or BC entries (for NVE tunnels). | |
1102 | * Access: RW | |
1103 | */ | |
1104 | MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); | |
1105 | ||
1106 | /* reg_sfmr_vv | |
1107 | * VNI Valid. | |
1108 | * If not set, then vni is reserved. | |
1109 | * Access: RW | |
1110 | * | |
1111 | * Note: Reserved for 802.1Q FIDs. | |
1112 | */ | |
1113 | MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); | |
1114 | ||
1115 | /* reg_sfmr_vni | |
1116 | * Virtual Network Identifier. | |
1117 | * Access: RW | |
1118 | * | |
1119 | * Note: A given VNI can only be assigned to one FID. | |
1120 | */ | |
1121 | MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); | |
1122 | ||
1123 | static inline void mlxsw_reg_sfmr_pack(char *payload, | |
1124 | enum mlxsw_reg_sfmr_op op, u16 fid, | |
1125 | u16 fid_offset) | |
1126 | { | |
1127 | MLXSW_REG_ZERO(sfmr, payload); | |
1128 | mlxsw_reg_sfmr_op_set(payload, op); | |
1129 | mlxsw_reg_sfmr_fid_set(payload, fid); | |
1130 | mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); | |
1131 | mlxsw_reg_sfmr_vtfp_set(payload, false); | |
1132 | mlxsw_reg_sfmr_vv_set(payload, false); | |
1133 | } | |
1134 | ||
a4feea74 IS |
1135 | /* SPVMLR - Switch Port VLAN MAC Learning Register |
1136 | * ----------------------------------------------- | |
1137 | * Controls the switch MAC learning policy per {Port, VID}. | |
1138 | */ | |
1139 | #define MLXSW_REG_SPVMLR_ID 0x2020 | |
1140 | #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ | |
1141 | #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ | |
d270d24e | 1142 | #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 |
a4feea74 IS |
1143 | #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ |
1144 | MLXSW_REG_SPVMLR_REC_LEN * \ | |
1145 | MLXSW_REG_SPVMLR_REC_MAX_COUNT) | |
1146 | ||
1147 | static const struct mlxsw_reg_info mlxsw_reg_spvmlr = { | |
1148 | .id = MLXSW_REG_SPVMLR_ID, | |
1149 | .len = MLXSW_REG_SPVMLR_LEN, | |
1150 | }; | |
1151 | ||
1152 | /* reg_spvmlr_local_port | |
1153 | * Local ingress port. | |
1154 | * Access: Index | |
1155 | * | |
1156 | * Note: CPU port is not supported. | |
1157 | */ | |
1158 | MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); | |
1159 | ||
1160 | /* reg_spvmlr_num_rec | |
1161 | * Number of records to update. | |
1162 | * Access: OP | |
1163 | */ | |
1164 | MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); | |
1165 | ||
1166 | /* reg_spvmlr_rec_learn_enable | |
1167 | * 0 - Disable learning for {Port, VID}. | |
1168 | * 1 - Enable learning for {Port, VID}. | |
1169 | * Access: RW | |
1170 | */ | |
1171 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, | |
1172 | 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1173 | ||
1174 | /* reg_spvmlr_rec_vid | |
1175 | * VLAN ID to be added/removed from port or for querying. | |
1176 | * Access: Index | |
1177 | */ | |
1178 | MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, | |
1179 | MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); | |
1180 | ||
1181 | static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, | |
1182 | u16 vid_begin, u16 vid_end, | |
1183 | bool learn_enable) | |
1184 | { | |
1185 | int num_rec = vid_end - vid_begin + 1; | |
1186 | int i; | |
1187 | ||
1188 | WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); | |
1189 | ||
1190 | MLXSW_REG_ZERO(spvmlr, payload); | |
1191 | mlxsw_reg_spvmlr_local_port_set(payload, local_port); | |
1192 | mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); | |
1193 | ||
1194 | for (i = 0; i < num_rec; i++) { | |
1195 | mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); | |
1196 | mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); | |
1197 | } | |
1198 | } | |
1199 | ||
4ec14b76 IS |
1200 | /* PMLP - Ports Module to Local Port Register |
1201 | * ------------------------------------------ | |
1202 | * Configures the assignment of modules to local ports. | |
1203 | */ | |
1204 | #define MLXSW_REG_PMLP_ID 0x5002 | |
1205 | #define MLXSW_REG_PMLP_LEN 0x40 | |
1206 | ||
1207 | static const struct mlxsw_reg_info mlxsw_reg_pmlp = { | |
1208 | .id = MLXSW_REG_PMLP_ID, | |
1209 | .len = MLXSW_REG_PMLP_LEN, | |
1210 | }; | |
1211 | ||
1212 | /* reg_pmlp_rxtx | |
1213 | * 0 - Tx value is used for both Tx and Rx. | |
1214 | * 1 - Rx value is taken from a separte field. | |
1215 | * Access: RW | |
1216 | */ | |
1217 | MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); | |
1218 | ||
1219 | /* reg_pmlp_local_port | |
1220 | * Local port number. | |
1221 | * Access: Index | |
1222 | */ | |
1223 | MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); | |
1224 | ||
1225 | /* reg_pmlp_width | |
1226 | * 0 - Unmap local port. | |
1227 | * 1 - Lane 0 is used. | |
1228 | * 2 - Lanes 0 and 1 are used. | |
1229 | * 4 - Lanes 0, 1, 2 and 3 are used. | |
1230 | * Access: RW | |
1231 | */ | |
1232 | MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); | |
1233 | ||
1234 | /* reg_pmlp_module | |
1235 | * Module number. | |
1236 | * Access: RW | |
1237 | */ | |
1238 | MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false); | |
1239 | ||
1240 | /* reg_pmlp_tx_lane | |
1241 | * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. | |
1242 | * Access: RW | |
1243 | */ | |
1244 | MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false); | |
1245 | ||
1246 | /* reg_pmlp_rx_lane | |
1247 | * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is | |
1248 | * equal to Tx lane. | |
1249 | * Access: RW | |
1250 | */ | |
1251 | MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false); | |
1252 | ||
1253 | static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) | |
1254 | { | |
1255 | MLXSW_REG_ZERO(pmlp, payload); | |
1256 | mlxsw_reg_pmlp_local_port_set(payload, local_port); | |
1257 | } | |
1258 | ||
1259 | /* PMTU - Port MTU Register | |
1260 | * ------------------------ | |
1261 | * Configures and reports the port MTU. | |
1262 | */ | |
1263 | #define MLXSW_REG_PMTU_ID 0x5003 | |
1264 | #define MLXSW_REG_PMTU_LEN 0x10 | |
1265 | ||
1266 | static const struct mlxsw_reg_info mlxsw_reg_pmtu = { | |
1267 | .id = MLXSW_REG_PMTU_ID, | |
1268 | .len = MLXSW_REG_PMTU_LEN, | |
1269 | }; | |
1270 | ||
1271 | /* reg_pmtu_local_port | |
1272 | * Local port number. | |
1273 | * Access: Index | |
1274 | */ | |
1275 | MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); | |
1276 | ||
1277 | /* reg_pmtu_max_mtu | |
1278 | * Maximum MTU. | |
1279 | * When port type (e.g. Ethernet) is configured, the relevant MTU is | |
1280 | * reported, otherwise the minimum between the max_mtu of the different | |
1281 | * types is reported. | |
1282 | * Access: RO | |
1283 | */ | |
1284 | MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); | |
1285 | ||
1286 | /* reg_pmtu_admin_mtu | |
1287 | * MTU value to set port to. Must be smaller or equal to max_mtu. | |
1288 | * Note: If port type is Infiniband, then port must be disabled, when its | |
1289 | * MTU is set. | |
1290 | * Access: RW | |
1291 | */ | |
1292 | MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); | |
1293 | ||
1294 | /* reg_pmtu_oper_mtu | |
1295 | * The actual MTU configured on the port. Packets exceeding this size | |
1296 | * will be dropped. | |
1297 | * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband | |
1298 | * oper_mtu might be smaller than admin_mtu. | |
1299 | * Access: RO | |
1300 | */ | |
1301 | MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); | |
1302 | ||
1303 | static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, | |
1304 | u16 new_mtu) | |
1305 | { | |
1306 | MLXSW_REG_ZERO(pmtu, payload); | |
1307 | mlxsw_reg_pmtu_local_port_set(payload, local_port); | |
1308 | mlxsw_reg_pmtu_max_mtu_set(payload, 0); | |
1309 | mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); | |
1310 | mlxsw_reg_pmtu_oper_mtu_set(payload, 0); | |
1311 | } | |
1312 | ||
1313 | /* PTYS - Port Type and Speed Register | |
1314 | * ----------------------------------- | |
1315 | * Configures and reports the port speed type. | |
1316 | * | |
1317 | * Note: When set while the link is up, the changes will not take effect | |
1318 | * until the port transitions from down to up state. | |
1319 | */ | |
1320 | #define MLXSW_REG_PTYS_ID 0x5004 | |
1321 | #define MLXSW_REG_PTYS_LEN 0x40 | |
1322 | ||
1323 | static const struct mlxsw_reg_info mlxsw_reg_ptys = { | |
1324 | .id = MLXSW_REG_PTYS_ID, | |
1325 | .len = MLXSW_REG_PTYS_LEN, | |
1326 | }; | |
1327 | ||
1328 | /* reg_ptys_local_port | |
1329 | * Local port number. | |
1330 | * Access: Index | |
1331 | */ | |
1332 | MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); | |
1333 | ||
1334 | #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) | |
1335 | ||
1336 | /* reg_ptys_proto_mask | |
1337 | * Protocol mask. Indicates which protocol is used. | |
1338 | * 0 - Infiniband. | |
1339 | * 1 - Fibre Channel. | |
1340 | * 2 - Ethernet. | |
1341 | * Access: Index | |
1342 | */ | |
1343 | MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); | |
1344 | ||
1345 | #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) | |
1346 | #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) | |
1347 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) | |
1348 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) | |
1349 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) | |
1350 | #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) | |
1351 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) | |
1352 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) | |
1353 | #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) | |
1354 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) | |
1355 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) | |
1356 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) | |
1357 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) | |
1358 | #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) | |
1359 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) | |
1360 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) | |
1361 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) | |
1362 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) | |
1363 | #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) | |
1364 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) | |
1365 | #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) | |
1366 | #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) | |
1367 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) | |
1368 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) | |
1369 | #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) | |
1370 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) | |
1371 | #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) | |
1372 | ||
1373 | /* reg_ptys_eth_proto_cap | |
1374 | * Ethernet port supported speeds and protocols. | |
1375 | * Access: RO | |
1376 | */ | |
1377 | MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); | |
1378 | ||
1379 | /* reg_ptys_eth_proto_admin | |
1380 | * Speed and protocol to set port to. | |
1381 | * Access: RW | |
1382 | */ | |
1383 | MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); | |
1384 | ||
1385 | /* reg_ptys_eth_proto_oper | |
1386 | * The current speed and protocol configured for the port. | |
1387 | * Access: RO | |
1388 | */ | |
1389 | MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); | |
1390 | ||
1391 | static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port, | |
1392 | u32 proto_admin) | |
1393 | { | |
1394 | MLXSW_REG_ZERO(ptys, payload); | |
1395 | mlxsw_reg_ptys_local_port_set(payload, local_port); | |
1396 | mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); | |
1397 | mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); | |
1398 | } | |
1399 | ||
1400 | static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap, | |
1401 | u32 *p_eth_proto_adm, | |
1402 | u32 *p_eth_proto_oper) | |
1403 | { | |
1404 | if (p_eth_proto_cap) | |
1405 | *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); | |
1406 | if (p_eth_proto_adm) | |
1407 | *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); | |
1408 | if (p_eth_proto_oper) | |
1409 | *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); | |
1410 | } | |
1411 | ||
1412 | /* PPAD - Port Physical Address Register | |
1413 | * ------------------------------------- | |
1414 | * The PPAD register configures the per port physical MAC address. | |
1415 | */ | |
1416 | #define MLXSW_REG_PPAD_ID 0x5005 | |
1417 | #define MLXSW_REG_PPAD_LEN 0x10 | |
1418 | ||
1419 | static const struct mlxsw_reg_info mlxsw_reg_ppad = { | |
1420 | .id = MLXSW_REG_PPAD_ID, | |
1421 | .len = MLXSW_REG_PPAD_LEN, | |
1422 | }; | |
1423 | ||
1424 | /* reg_ppad_single_base_mac | |
1425 | * 0: base_mac, local port should be 0 and mac[7:0] is | |
1426 | * reserved. HW will set incremental | |
1427 | * 1: single_mac - mac of the local_port | |
1428 | * Access: RW | |
1429 | */ | |
1430 | MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); | |
1431 | ||
1432 | /* reg_ppad_local_port | |
1433 | * port number, if single_base_mac = 0 then local_port is reserved | |
1434 | * Access: RW | |
1435 | */ | |
1436 | MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); | |
1437 | ||
1438 | /* reg_ppad_mac | |
1439 | * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. | |
1440 | * If single_base_mac = 1 - the per port MAC address | |
1441 | * Access: RW | |
1442 | */ | |
1443 | MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); | |
1444 | ||
1445 | static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, | |
1446 | u8 local_port) | |
1447 | { | |
1448 | MLXSW_REG_ZERO(ppad, payload); | |
1449 | mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); | |
1450 | mlxsw_reg_ppad_local_port_set(payload, local_port); | |
1451 | } | |
1452 | ||
1453 | /* PAOS - Ports Administrative and Operational Status Register | |
1454 | * ----------------------------------------------------------- | |
1455 | * Configures and retrieves per port administrative and operational status. | |
1456 | */ | |
1457 | #define MLXSW_REG_PAOS_ID 0x5006 | |
1458 | #define MLXSW_REG_PAOS_LEN 0x10 | |
1459 | ||
1460 | static const struct mlxsw_reg_info mlxsw_reg_paos = { | |
1461 | .id = MLXSW_REG_PAOS_ID, | |
1462 | .len = MLXSW_REG_PAOS_LEN, | |
1463 | }; | |
1464 | ||
1465 | /* reg_paos_swid | |
1466 | * Switch partition ID with which to associate the port. | |
1467 | * Note: while external ports uses unique local port numbers (and thus swid is | |
1468 | * redundant), router ports use the same local port number where swid is the | |
1469 | * only indication for the relevant port. | |
1470 | * Access: Index | |
1471 | */ | |
1472 | MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); | |
1473 | ||
1474 | /* reg_paos_local_port | |
1475 | * Local port number. | |
1476 | * Access: Index | |
1477 | */ | |
1478 | MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); | |
1479 | ||
1480 | /* reg_paos_admin_status | |
1481 | * Port administrative state (the desired state of the port): | |
1482 | * 1 - Up. | |
1483 | * 2 - Down. | |
1484 | * 3 - Up once. This means that in case of link failure, the port won't go | |
1485 | * into polling mode, but will wait to be re-enabled by software. | |
1486 | * 4 - Disabled by system. Can only be set by hardware. | |
1487 | * Access: RW | |
1488 | */ | |
1489 | MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); | |
1490 | ||
1491 | /* reg_paos_oper_status | |
1492 | * Port operational state (the current state): | |
1493 | * 1 - Up. | |
1494 | * 2 - Down. | |
1495 | * 3 - Down by port failure. This means that the device will not let the | |
1496 | * port up again until explicitly specified by software. | |
1497 | * Access: RO | |
1498 | */ | |
1499 | MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); | |
1500 | ||
1501 | /* reg_paos_ase | |
1502 | * Admin state update enabled. | |
1503 | * Access: WO | |
1504 | */ | |
1505 | MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); | |
1506 | ||
1507 | /* reg_paos_ee | |
1508 | * Event update enable. If this bit is set, event generation will be | |
1509 | * updated based on the e field. | |
1510 | * Access: WO | |
1511 | */ | |
1512 | MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); | |
1513 | ||
1514 | /* reg_paos_e | |
1515 | * Event generation on operational state change: | |
1516 | * 0 - Do not generate event. | |
1517 | * 1 - Generate Event. | |
1518 | * 2 - Generate Single Event. | |
1519 | * Access: RW | |
1520 | */ | |
1521 | MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); | |
1522 | ||
1523 | static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, | |
1524 | enum mlxsw_port_admin_status status) | |
1525 | { | |
1526 | MLXSW_REG_ZERO(paos, payload); | |
1527 | mlxsw_reg_paos_swid_set(payload, 0); | |
1528 | mlxsw_reg_paos_local_port_set(payload, local_port); | |
1529 | mlxsw_reg_paos_admin_status_set(payload, status); | |
1530 | mlxsw_reg_paos_oper_status_set(payload, 0); | |
1531 | mlxsw_reg_paos_ase_set(payload, 1); | |
1532 | mlxsw_reg_paos_ee_set(payload, 1); | |
1533 | mlxsw_reg_paos_e_set(payload, 1); | |
1534 | } | |
1535 | ||
1536 | /* PPCNT - Ports Performance Counters Register | |
1537 | * ------------------------------------------- | |
1538 | * The PPCNT register retrieves per port performance counters. | |
1539 | */ | |
1540 | #define MLXSW_REG_PPCNT_ID 0x5008 | |
1541 | #define MLXSW_REG_PPCNT_LEN 0x100 | |
1542 | ||
1543 | static const struct mlxsw_reg_info mlxsw_reg_ppcnt = { | |
1544 | .id = MLXSW_REG_PPCNT_ID, | |
1545 | .len = MLXSW_REG_PPCNT_LEN, | |
1546 | }; | |
1547 | ||
1548 | /* reg_ppcnt_swid | |
1549 | * For HCA: must be always 0. | |
1550 | * Switch partition ID to associate port with. | |
1551 | * Switch partitions are numbered from 0 to 7 inclusively. | |
1552 | * Switch partition 254 indicates stacking ports. | |
1553 | * Switch partition 255 indicates all switch partitions. | |
1554 | * Only valid on Set() operation with local_port=255. | |
1555 | * Access: Index | |
1556 | */ | |
1557 | MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); | |
1558 | ||
1559 | /* reg_ppcnt_local_port | |
1560 | * Local port number. | |
1561 | * 255 indicates all ports on the device, and is only allowed | |
1562 | * for Set() operation. | |
1563 | * Access: Index | |
1564 | */ | |
1565 | MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); | |
1566 | ||
1567 | /* reg_ppcnt_pnat | |
1568 | * Port number access type: | |
1569 | * 0 - Local port number | |
1570 | * 1 - IB port number | |
1571 | * Access: Index | |
1572 | */ | |
1573 | MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); | |
1574 | ||
1575 | /* reg_ppcnt_grp | |
1576 | * Performance counter group. | |
1577 | * Group 63 indicates all groups. Only valid on Set() operation with | |
1578 | * clr bit set. | |
1579 | * 0x0: IEEE 802.3 Counters | |
1580 | * 0x1: RFC 2863 Counters | |
1581 | * 0x2: RFC 2819 Counters | |
1582 | * 0x3: RFC 3635 Counters | |
1583 | * 0x5: Ethernet Extended Counters | |
1584 | * 0x8: Link Level Retransmission Counters | |
1585 | * 0x10: Per Priority Counters | |
1586 | * 0x11: Per Traffic Class Counters | |
1587 | * 0x12: Physical Layer Counters | |
1588 | * Access: Index | |
1589 | */ | |
1590 | MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); | |
1591 | ||
1592 | /* reg_ppcnt_clr | |
1593 | * Clear counters. Setting the clr bit will reset the counter value | |
1594 | * for all counters in the counter group. This bit can be set | |
1595 | * for both Set() and Get() operation. | |
1596 | * Access: OP | |
1597 | */ | |
1598 | MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); | |
1599 | ||
1600 | /* reg_ppcnt_prio_tc | |
1601 | * Priority for counter set that support per priority, valid values: 0-7. | |
1602 | * Traffic class for counter set that support per traffic class, | |
1603 | * valid values: 0- cap_max_tclass-1 . | |
1604 | * For HCA: cap_max_tclass is always 8. | |
1605 | * Otherwise must be 0. | |
1606 | * Access: Index | |
1607 | */ | |
1608 | MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); | |
1609 | ||
1610 | /* reg_ppcnt_a_frames_transmitted_ok | |
1611 | * Access: RO | |
1612 | */ | |
1613 | MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, | |
1614 | 0x08 + 0x00, 0, 64); | |
1615 | ||
1616 | /* reg_ppcnt_a_frames_received_ok | |
1617 | * Access: RO | |
1618 | */ | |
1619 | MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, | |
1620 | 0x08 + 0x08, 0, 64); | |
1621 | ||
1622 | /* reg_ppcnt_a_frame_check_sequence_errors | |
1623 | * Access: RO | |
1624 | */ | |
1625 | MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, | |
1626 | 0x08 + 0x10, 0, 64); | |
1627 | ||
1628 | /* reg_ppcnt_a_alignment_errors | |
1629 | * Access: RO | |
1630 | */ | |
1631 | MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, | |
1632 | 0x08 + 0x18, 0, 64); | |
1633 | ||
1634 | /* reg_ppcnt_a_octets_transmitted_ok | |
1635 | * Access: RO | |
1636 | */ | |
1637 | MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, | |
1638 | 0x08 + 0x20, 0, 64); | |
1639 | ||
1640 | /* reg_ppcnt_a_octets_received_ok | |
1641 | * Access: RO | |
1642 | */ | |
1643 | MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, | |
1644 | 0x08 + 0x28, 0, 64); | |
1645 | ||
1646 | /* reg_ppcnt_a_multicast_frames_xmitted_ok | |
1647 | * Access: RO | |
1648 | */ | |
1649 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, | |
1650 | 0x08 + 0x30, 0, 64); | |
1651 | ||
1652 | /* reg_ppcnt_a_broadcast_frames_xmitted_ok | |
1653 | * Access: RO | |
1654 | */ | |
1655 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, | |
1656 | 0x08 + 0x38, 0, 64); | |
1657 | ||
1658 | /* reg_ppcnt_a_multicast_frames_received_ok | |
1659 | * Access: RO | |
1660 | */ | |
1661 | MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, | |
1662 | 0x08 + 0x40, 0, 64); | |
1663 | ||
1664 | /* reg_ppcnt_a_broadcast_frames_received_ok | |
1665 | * Access: RO | |
1666 | */ | |
1667 | MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, | |
1668 | 0x08 + 0x48, 0, 64); | |
1669 | ||
1670 | /* reg_ppcnt_a_in_range_length_errors | |
1671 | * Access: RO | |
1672 | */ | |
1673 | MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, | |
1674 | 0x08 + 0x50, 0, 64); | |
1675 | ||
1676 | /* reg_ppcnt_a_out_of_range_length_field | |
1677 | * Access: RO | |
1678 | */ | |
1679 | MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, | |
1680 | 0x08 + 0x58, 0, 64); | |
1681 | ||
1682 | /* reg_ppcnt_a_frame_too_long_errors | |
1683 | * Access: RO | |
1684 | */ | |
1685 | MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, | |
1686 | 0x08 + 0x60, 0, 64); | |
1687 | ||
1688 | /* reg_ppcnt_a_symbol_error_during_carrier | |
1689 | * Access: RO | |
1690 | */ | |
1691 | MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, | |
1692 | 0x08 + 0x68, 0, 64); | |
1693 | ||
1694 | /* reg_ppcnt_a_mac_control_frames_transmitted | |
1695 | * Access: RO | |
1696 | */ | |
1697 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, | |
1698 | 0x08 + 0x70, 0, 64); | |
1699 | ||
1700 | /* reg_ppcnt_a_mac_control_frames_received | |
1701 | * Access: RO | |
1702 | */ | |
1703 | MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, | |
1704 | 0x08 + 0x78, 0, 64); | |
1705 | ||
1706 | /* reg_ppcnt_a_unsupported_opcodes_received | |
1707 | * Access: RO | |
1708 | */ | |
1709 | MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, | |
1710 | 0x08 + 0x80, 0, 64); | |
1711 | ||
1712 | /* reg_ppcnt_a_pause_mac_ctrl_frames_received | |
1713 | * Access: RO | |
1714 | */ | |
1715 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, | |
1716 | 0x08 + 0x88, 0, 64); | |
1717 | ||
1718 | /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted | |
1719 | * Access: RO | |
1720 | */ | |
1721 | MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, | |
1722 | 0x08 + 0x90, 0, 64); | |
1723 | ||
1724 | static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port) | |
1725 | { | |
1726 | MLXSW_REG_ZERO(ppcnt, payload); | |
1727 | mlxsw_reg_ppcnt_swid_set(payload, 0); | |
1728 | mlxsw_reg_ppcnt_local_port_set(payload, local_port); | |
1729 | mlxsw_reg_ppcnt_pnat_set(payload, 0); | |
1730 | mlxsw_reg_ppcnt_grp_set(payload, 0); | |
1731 | mlxsw_reg_ppcnt_clr_set(payload, 0); | |
1732 | mlxsw_reg_ppcnt_prio_tc_set(payload, 0); | |
1733 | } | |
1734 | ||
e0594369 JP |
1735 | /* PBMC - Port Buffer Management Control Register |
1736 | * ---------------------------------------------- | |
1737 | * The PBMC register configures and retrieves the port packet buffer | |
1738 | * allocation for different Prios, and the Pause threshold management. | |
1739 | */ | |
1740 | #define MLXSW_REG_PBMC_ID 0x500C | |
1741 | #define MLXSW_REG_PBMC_LEN 0x68 | |
1742 | ||
1743 | static const struct mlxsw_reg_info mlxsw_reg_pbmc = { | |
1744 | .id = MLXSW_REG_PBMC_ID, | |
1745 | .len = MLXSW_REG_PBMC_LEN, | |
1746 | }; | |
1747 | ||
1748 | /* reg_pbmc_local_port | |
1749 | * Local port number. | |
1750 | * Access: Index | |
1751 | */ | |
1752 | MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); | |
1753 | ||
1754 | /* reg_pbmc_xoff_timer_value | |
1755 | * When device generates a pause frame, it uses this value as the pause | |
1756 | * timer (time for the peer port to pause in quota-512 bit time). | |
1757 | * Access: RW | |
1758 | */ | |
1759 | MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); | |
1760 | ||
1761 | /* reg_pbmc_xoff_refresh | |
1762 | * The time before a new pause frame should be sent to refresh the pause RW | |
1763 | * state. Using the same units as xoff_timer_value above (in quota-512 bit | |
1764 | * time). | |
1765 | * Access: RW | |
1766 | */ | |
1767 | MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); | |
1768 | ||
1769 | /* reg_pbmc_buf_lossy | |
1770 | * The field indicates if the buffer is lossy. | |
1771 | * 0 - Lossless | |
1772 | * 1 - Lossy | |
1773 | * Access: RW | |
1774 | */ | |
1775 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); | |
1776 | ||
1777 | /* reg_pbmc_buf_epsb | |
1778 | * Eligible for Port Shared buffer. | |
1779 | * If epsb is set, packets assigned to buffer are allowed to insert the port | |
1780 | * shared buffer. | |
1781 | * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. | |
1782 | * Access: RW | |
1783 | */ | |
1784 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); | |
1785 | ||
1786 | /* reg_pbmc_buf_size | |
1787 | * The part of the packet buffer array is allocated for the specific buffer. | |
1788 | * Units are represented in cells. | |
1789 | * Access: RW | |
1790 | */ | |
1791 | MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); | |
1792 | ||
1793 | static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, | |
1794 | u16 xoff_timer_value, u16 xoff_refresh) | |
1795 | { | |
1796 | MLXSW_REG_ZERO(pbmc, payload); | |
1797 | mlxsw_reg_pbmc_local_port_set(payload, local_port); | |
1798 | mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); | |
1799 | mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); | |
1800 | } | |
1801 | ||
1802 | static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, | |
1803 | int buf_index, | |
1804 | u16 size) | |
1805 | { | |
1806 | mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); | |
1807 | mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); | |
1808 | mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); | |
1809 | } | |
1810 | ||
4ec14b76 IS |
1811 | /* PSPA - Port Switch Partition Allocation |
1812 | * --------------------------------------- | |
1813 | * Controls the association of a port with a switch partition and enables | |
1814 | * configuring ports as stacking ports. | |
1815 | */ | |
3f0effd1 | 1816 | #define MLXSW_REG_PSPA_ID 0x500D |
4ec14b76 IS |
1817 | #define MLXSW_REG_PSPA_LEN 0x8 |
1818 | ||
1819 | static const struct mlxsw_reg_info mlxsw_reg_pspa = { | |
1820 | .id = MLXSW_REG_PSPA_ID, | |
1821 | .len = MLXSW_REG_PSPA_LEN, | |
1822 | }; | |
1823 | ||
1824 | /* reg_pspa_swid | |
1825 | * Switch partition ID. | |
1826 | * Access: RW | |
1827 | */ | |
1828 | MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); | |
1829 | ||
1830 | /* reg_pspa_local_port | |
1831 | * Local port number. | |
1832 | * Access: Index | |
1833 | */ | |
1834 | MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); | |
1835 | ||
1836 | /* reg_pspa_sub_port | |
1837 | * Virtual port within the local port. Set to 0 when virtual ports are | |
1838 | * disabled on the local port. | |
1839 | * Access: Index | |
1840 | */ | |
1841 | MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); | |
1842 | ||
1843 | static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) | |
1844 | { | |
1845 | MLXSW_REG_ZERO(pspa, payload); | |
1846 | mlxsw_reg_pspa_swid_set(payload, swid); | |
1847 | mlxsw_reg_pspa_local_port_set(payload, local_port); | |
1848 | mlxsw_reg_pspa_sub_port_set(payload, 0); | |
1849 | } | |
1850 | ||
1851 | /* HTGT - Host Trap Group Table | |
1852 | * ---------------------------- | |
1853 | * Configures the properties for forwarding to CPU. | |
1854 | */ | |
1855 | #define MLXSW_REG_HTGT_ID 0x7002 | |
1856 | #define MLXSW_REG_HTGT_LEN 0x100 | |
1857 | ||
1858 | static const struct mlxsw_reg_info mlxsw_reg_htgt = { | |
1859 | .id = MLXSW_REG_HTGT_ID, | |
1860 | .len = MLXSW_REG_HTGT_LEN, | |
1861 | }; | |
1862 | ||
1863 | /* reg_htgt_swid | |
1864 | * Switch partition ID. | |
1865 | * Access: Index | |
1866 | */ | |
1867 | MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); | |
1868 | ||
1869 | #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ | |
1870 | ||
1871 | /* reg_htgt_type | |
1872 | * CPU path type. | |
1873 | * Access: RW | |
1874 | */ | |
1875 | MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); | |
1876 | ||
801bd3de IS |
1877 | enum mlxsw_reg_htgt_trap_group { |
1878 | MLXSW_REG_HTGT_TRAP_GROUP_EMAD, | |
1879 | MLXSW_REG_HTGT_TRAP_GROUP_RX, | |
1880 | MLXSW_REG_HTGT_TRAP_GROUP_CTRL, | |
1881 | }; | |
4ec14b76 IS |
1882 | |
1883 | /* reg_htgt_trap_group | |
1884 | * Trap group number. User defined number specifying which trap groups | |
1885 | * should be forwarded to the CPU. The mapping between trap IDs and trap | |
1886 | * groups is configured using HPKT register. | |
1887 | * Access: Index | |
1888 | */ | |
1889 | MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); | |
1890 | ||
1891 | enum { | |
1892 | MLXSW_REG_HTGT_POLICER_DISABLE, | |
1893 | MLXSW_REG_HTGT_POLICER_ENABLE, | |
1894 | }; | |
1895 | ||
1896 | /* reg_htgt_pide | |
1897 | * Enable policer ID specified using 'pid' field. | |
1898 | * Access: RW | |
1899 | */ | |
1900 | MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); | |
1901 | ||
1902 | /* reg_htgt_pid | |
1903 | * Policer ID for the trap group. | |
1904 | * Access: RW | |
1905 | */ | |
1906 | MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); | |
1907 | ||
1908 | #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 | |
1909 | ||
1910 | /* reg_htgt_mirror_action | |
1911 | * Mirror action to use. | |
1912 | * 0 - Trap to CPU. | |
1913 | * 1 - Trap to CPU and mirror to a mirroring agent. | |
1914 | * 2 - Mirror to a mirroring agent and do not trap to CPU. | |
1915 | * Access: RW | |
1916 | * | |
1917 | * Note: Mirroring to a mirroring agent is only supported in Spectrum. | |
1918 | */ | |
1919 | MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); | |
1920 | ||
1921 | /* reg_htgt_mirroring_agent | |
1922 | * Mirroring agent. | |
1923 | * Access: RW | |
1924 | */ | |
1925 | MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); | |
1926 | ||
1927 | /* reg_htgt_priority | |
1928 | * Trap group priority. | |
1929 | * In case a packet matches multiple classification rules, the packet will | |
1930 | * only be trapped once, based on the trap ID associated with the group (via | |
1931 | * register HPKT) with the highest priority. | |
1932 | * Supported values are 0-7, with 7 represnting the highest priority. | |
1933 | * Access: RW | |
1934 | * | |
1935 | * Note: In SwitchX-2 this field is ignored and the priority value is replaced | |
1936 | * by the 'trap_group' field. | |
1937 | */ | |
1938 | MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); | |
1939 | ||
1940 | /* reg_htgt_local_path_cpu_tclass | |
1941 | * CPU ingress traffic class for the trap group. | |
1942 | * Access: RW | |
1943 | */ | |
1944 | MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); | |
1945 | ||
1946 | #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15 | |
1947 | #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14 | |
801bd3de | 1948 | #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13 |
4ec14b76 IS |
1949 | |
1950 | /* reg_htgt_local_path_rdq | |
1951 | * Receive descriptor queue (RDQ) to use for the trap group. | |
1952 | * Access: RW | |
1953 | */ | |
1954 | MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); | |
1955 | ||
801bd3de IS |
1956 | static inline void mlxsw_reg_htgt_pack(char *payload, |
1957 | enum mlxsw_reg_htgt_trap_group group) | |
4ec14b76 IS |
1958 | { |
1959 | u8 swid, rdq; | |
1960 | ||
1961 | MLXSW_REG_ZERO(htgt, payload); | |
801bd3de IS |
1962 | switch (group) { |
1963 | case MLXSW_REG_HTGT_TRAP_GROUP_EMAD: | |
4ec14b76 IS |
1964 | swid = MLXSW_PORT_SWID_ALL_SWIDS; |
1965 | rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD; | |
801bd3de IS |
1966 | break; |
1967 | case MLXSW_REG_HTGT_TRAP_GROUP_RX: | |
4ec14b76 IS |
1968 | swid = 0; |
1969 | rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX; | |
801bd3de IS |
1970 | break; |
1971 | case MLXSW_REG_HTGT_TRAP_GROUP_CTRL: | |
1972 | swid = 0; | |
1973 | rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL; | |
1974 | break; | |
4ec14b76 IS |
1975 | } |
1976 | mlxsw_reg_htgt_swid_set(payload, swid); | |
1977 | mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); | |
801bd3de | 1978 | mlxsw_reg_htgt_trap_group_set(payload, group); |
4ec14b76 IS |
1979 | mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE); |
1980 | mlxsw_reg_htgt_pid_set(payload, 0); | |
1981 | mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); | |
1982 | mlxsw_reg_htgt_mirroring_agent_set(payload, 0); | |
1983 | mlxsw_reg_htgt_priority_set(payload, 0); | |
1984 | mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7); | |
1985 | mlxsw_reg_htgt_local_path_rdq_set(payload, rdq); | |
1986 | } | |
1987 | ||
1988 | /* HPKT - Host Packet Trap | |
1989 | * ----------------------- | |
1990 | * Configures trap IDs inside trap groups. | |
1991 | */ | |
1992 | #define MLXSW_REG_HPKT_ID 0x7003 | |
1993 | #define MLXSW_REG_HPKT_LEN 0x10 | |
1994 | ||
1995 | static const struct mlxsw_reg_info mlxsw_reg_hpkt = { | |
1996 | .id = MLXSW_REG_HPKT_ID, | |
1997 | .len = MLXSW_REG_HPKT_LEN, | |
1998 | }; | |
1999 | ||
2000 | enum { | |
2001 | MLXSW_REG_HPKT_ACK_NOT_REQUIRED, | |
2002 | MLXSW_REG_HPKT_ACK_REQUIRED, | |
2003 | }; | |
2004 | ||
2005 | /* reg_hpkt_ack | |
2006 | * Require acknowledgements from the host for events. | |
2007 | * If set, then the device will wait for the event it sent to be acknowledged | |
2008 | * by the host. This option is only relevant for event trap IDs. | |
2009 | * Access: RW | |
2010 | * | |
2011 | * Note: Currently not supported by firmware. | |
2012 | */ | |
2013 | MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); | |
2014 | ||
2015 | enum mlxsw_reg_hpkt_action { | |
2016 | MLXSW_REG_HPKT_ACTION_FORWARD, | |
2017 | MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, | |
2018 | MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, | |
2019 | MLXSW_REG_HPKT_ACTION_DISCARD, | |
2020 | MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, | |
2021 | MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, | |
2022 | }; | |
2023 | ||
2024 | /* reg_hpkt_action | |
2025 | * Action to perform on packet when trapped. | |
2026 | * 0 - No action. Forward to CPU based on switching rules. | |
2027 | * 1 - Trap to CPU (CPU receives sole copy). | |
2028 | * 2 - Mirror to CPU (CPU receives a replica of the packet). | |
2029 | * 3 - Discard. | |
2030 | * 4 - Soft discard (allow other traps to act on the packet). | |
2031 | * 5 - Trap and soft discard (allow other traps to overwrite this trap). | |
2032 | * Access: RW | |
2033 | * | |
2034 | * Note: Must be set to 0 (forward) for event trap IDs, as they are already | |
2035 | * addressed to the CPU. | |
2036 | */ | |
2037 | MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); | |
2038 | ||
2039 | /* reg_hpkt_trap_group | |
2040 | * Trap group to associate the trap with. | |
2041 | * Access: RW | |
2042 | */ | |
2043 | MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); | |
2044 | ||
2045 | /* reg_hpkt_trap_id | |
2046 | * Trap ID. | |
2047 | * Access: Index | |
2048 | * | |
2049 | * Note: A trap ID can only be associated with a single trap group. The device | |
2050 | * will associate the trap ID with the last trap group configured. | |
2051 | */ | |
2052 | MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); | |
2053 | ||
2054 | enum { | |
2055 | MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, | |
2056 | MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, | |
2057 | MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, | |
2058 | }; | |
2059 | ||
2060 | /* reg_hpkt_ctrl | |
2061 | * Configure dedicated buffer resources for control packets. | |
2062 | * 0 - Keep factory defaults. | |
2063 | * 1 - Do not use control buffer for this trap ID. | |
2064 | * 2 - Use control buffer for this trap ID. | |
2065 | * Access: RW | |
2066 | */ | |
2067 | MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); | |
2068 | ||
f24af330 | 2069 | static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id) |
4ec14b76 | 2070 | { |
801bd3de | 2071 | enum mlxsw_reg_htgt_trap_group trap_group; |
f24af330 | 2072 | |
4ec14b76 IS |
2073 | MLXSW_REG_ZERO(hpkt, payload); |
2074 | mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); | |
2075 | mlxsw_reg_hpkt_action_set(payload, action); | |
f24af330 IS |
2076 | switch (trap_id) { |
2077 | case MLXSW_TRAP_ID_ETHEMAD: | |
2078 | case MLXSW_TRAP_ID_PUDE: | |
2079 | trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD; | |
2080 | break; | |
2081 | default: | |
2082 | trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX; | |
2083 | break; | |
2084 | } | |
4ec14b76 IS |
2085 | mlxsw_reg_hpkt_trap_group_set(payload, trap_group); |
2086 | mlxsw_reg_hpkt_trap_id_set(payload, trap_id); | |
2087 | mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT); | |
2088 | } | |
2089 | ||
e0594369 JP |
2090 | /* SBPR - Shared Buffer Pools Register |
2091 | * ----------------------------------- | |
2092 | * The SBPR configures and retrieves the shared buffer pools and configuration. | |
2093 | */ | |
2094 | #define MLXSW_REG_SBPR_ID 0xB001 | |
2095 | #define MLXSW_REG_SBPR_LEN 0x14 | |
2096 | ||
2097 | static const struct mlxsw_reg_info mlxsw_reg_sbpr = { | |
2098 | .id = MLXSW_REG_SBPR_ID, | |
2099 | .len = MLXSW_REG_SBPR_LEN, | |
2100 | }; | |
2101 | ||
2102 | enum mlxsw_reg_sbpr_dir { | |
2103 | MLXSW_REG_SBPR_DIR_INGRESS, | |
2104 | MLXSW_REG_SBPR_DIR_EGRESS, | |
2105 | }; | |
2106 | ||
2107 | /* reg_sbpr_dir | |
2108 | * Direction. | |
2109 | * Access: Index | |
2110 | */ | |
2111 | MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); | |
2112 | ||
2113 | /* reg_sbpr_pool | |
2114 | * Pool index. | |
2115 | * Access: Index | |
2116 | */ | |
2117 | MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); | |
2118 | ||
2119 | /* reg_sbpr_size | |
2120 | * Pool size in buffer cells. | |
2121 | * Access: RW | |
2122 | */ | |
2123 | MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); | |
2124 | ||
2125 | enum mlxsw_reg_sbpr_mode { | |
2126 | MLXSW_REG_SBPR_MODE_STATIC, | |
2127 | MLXSW_REG_SBPR_MODE_DYNAMIC, | |
2128 | }; | |
2129 | ||
2130 | /* reg_sbpr_mode | |
2131 | * Pool quota calculation mode. | |
2132 | * Access: RW | |
2133 | */ | |
2134 | MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); | |
2135 | ||
2136 | static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, | |
2137 | enum mlxsw_reg_sbpr_dir dir, | |
2138 | enum mlxsw_reg_sbpr_mode mode, u32 size) | |
2139 | { | |
2140 | MLXSW_REG_ZERO(sbpr, payload); | |
2141 | mlxsw_reg_sbpr_pool_set(payload, pool); | |
2142 | mlxsw_reg_sbpr_dir_set(payload, dir); | |
2143 | mlxsw_reg_sbpr_mode_set(payload, mode); | |
2144 | mlxsw_reg_sbpr_size_set(payload, size); | |
2145 | } | |
2146 | ||
2147 | /* SBCM - Shared Buffer Class Management Register | |
2148 | * ---------------------------------------------- | |
2149 | * The SBCM register configures and retrieves the shared buffer allocation | |
2150 | * and configuration according to Port-PG, including the binding to pool | |
2151 | * and definition of the associated quota. | |
2152 | */ | |
2153 | #define MLXSW_REG_SBCM_ID 0xB002 | |
2154 | #define MLXSW_REG_SBCM_LEN 0x28 | |
2155 | ||
2156 | static const struct mlxsw_reg_info mlxsw_reg_sbcm = { | |
2157 | .id = MLXSW_REG_SBCM_ID, | |
2158 | .len = MLXSW_REG_SBCM_LEN, | |
2159 | }; | |
2160 | ||
2161 | /* reg_sbcm_local_port | |
2162 | * Local port number. | |
2163 | * For Ingress: excludes CPU port and Router port | |
2164 | * For Egress: excludes IP Router | |
2165 | * Access: Index | |
2166 | */ | |
2167 | MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); | |
2168 | ||
2169 | /* reg_sbcm_pg_buff | |
2170 | * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) | |
2171 | * For PG buffer: range is 0..cap_max_pg_buffers - 1 | |
2172 | * For traffic class: range is 0..cap_max_tclass - 1 | |
2173 | * Note that when traffic class is in MC aware mode then the traffic | |
2174 | * classes which are MC aware cannot be configured. | |
2175 | * Access: Index | |
2176 | */ | |
2177 | MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); | |
2178 | ||
2179 | enum mlxsw_reg_sbcm_dir { | |
2180 | MLXSW_REG_SBCM_DIR_INGRESS, | |
2181 | MLXSW_REG_SBCM_DIR_EGRESS, | |
2182 | }; | |
2183 | ||
2184 | /* reg_sbcm_dir | |
2185 | * Direction. | |
2186 | * Access: Index | |
2187 | */ | |
2188 | MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); | |
2189 | ||
2190 | /* reg_sbcm_min_buff | |
2191 | * Minimum buffer size for the limiter, in cells. | |
2192 | * Access: RW | |
2193 | */ | |
2194 | MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); | |
2195 | ||
2196 | /* reg_sbcm_max_buff | |
2197 | * When the pool associated to the port-pg/tclass is configured to | |
2198 | * static, Maximum buffer size for the limiter configured in cells. | |
2199 | * When the pool associated to the port-pg/tclass is configured to | |
2200 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
2201 | * the following values: | |
2202 | * 0: 0 | |
2203 | * i: (1/128)*2^(i-1), for i=1..14 | |
2204 | * 0xFF: Infinity | |
2205 | * Access: RW | |
2206 | */ | |
2207 | MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); | |
2208 | ||
2209 | /* reg_sbcm_pool | |
2210 | * Association of the port-priority to a pool. | |
2211 | * Access: RW | |
2212 | */ | |
2213 | MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); | |
2214 | ||
2215 | static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, | |
2216 | enum mlxsw_reg_sbcm_dir dir, | |
2217 | u32 min_buff, u32 max_buff, u8 pool) | |
2218 | { | |
2219 | MLXSW_REG_ZERO(sbcm, payload); | |
2220 | mlxsw_reg_sbcm_local_port_set(payload, local_port); | |
2221 | mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); | |
2222 | mlxsw_reg_sbcm_dir_set(payload, dir); | |
2223 | mlxsw_reg_sbcm_min_buff_set(payload, min_buff); | |
2224 | mlxsw_reg_sbcm_max_buff_set(payload, max_buff); | |
2225 | mlxsw_reg_sbcm_pool_set(payload, pool); | |
2226 | } | |
2227 | ||
2228 | /* SBPM - Shared Buffer Class Management Register | |
2229 | * ---------------------------------------------- | |
2230 | * The SBPM register configures and retrieves the shared buffer allocation | |
2231 | * and configuration according to Port-Pool, including the definition | |
2232 | * of the associated quota. | |
2233 | */ | |
2234 | #define MLXSW_REG_SBPM_ID 0xB003 | |
2235 | #define MLXSW_REG_SBPM_LEN 0x28 | |
2236 | ||
2237 | static const struct mlxsw_reg_info mlxsw_reg_sbpm = { | |
2238 | .id = MLXSW_REG_SBPM_ID, | |
2239 | .len = MLXSW_REG_SBPM_LEN, | |
2240 | }; | |
2241 | ||
2242 | /* reg_sbpm_local_port | |
2243 | * Local port number. | |
2244 | * For Ingress: excludes CPU port and Router port | |
2245 | * For Egress: excludes IP Router | |
2246 | * Access: Index | |
2247 | */ | |
2248 | MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); | |
2249 | ||
2250 | /* reg_sbpm_pool | |
2251 | * The pool associated to quota counting on the local_port. | |
2252 | * Access: Index | |
2253 | */ | |
2254 | MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); | |
2255 | ||
2256 | enum mlxsw_reg_sbpm_dir { | |
2257 | MLXSW_REG_SBPM_DIR_INGRESS, | |
2258 | MLXSW_REG_SBPM_DIR_EGRESS, | |
2259 | }; | |
2260 | ||
2261 | /* reg_sbpm_dir | |
2262 | * Direction. | |
2263 | * Access: Index | |
2264 | */ | |
2265 | MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); | |
2266 | ||
2267 | /* reg_sbpm_min_buff | |
2268 | * Minimum buffer size for the limiter, in cells. | |
2269 | * Access: RW | |
2270 | */ | |
2271 | MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); | |
2272 | ||
2273 | /* reg_sbpm_max_buff | |
2274 | * When the pool associated to the port-pg/tclass is configured to | |
2275 | * static, Maximum buffer size for the limiter configured in cells. | |
2276 | * When the pool associated to the port-pg/tclass is configured to | |
2277 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
2278 | * the following values: | |
2279 | * 0: 0 | |
2280 | * i: (1/128)*2^(i-1), for i=1..14 | |
2281 | * 0xFF: Infinity | |
2282 | * Access: RW | |
2283 | */ | |
2284 | MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); | |
2285 | ||
2286 | static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, | |
2287 | enum mlxsw_reg_sbpm_dir dir, | |
2288 | u32 min_buff, u32 max_buff) | |
2289 | { | |
2290 | MLXSW_REG_ZERO(sbpm, payload); | |
2291 | mlxsw_reg_sbpm_local_port_set(payload, local_port); | |
2292 | mlxsw_reg_sbpm_pool_set(payload, pool); | |
2293 | mlxsw_reg_sbpm_dir_set(payload, dir); | |
2294 | mlxsw_reg_sbpm_min_buff_set(payload, min_buff); | |
2295 | mlxsw_reg_sbpm_max_buff_set(payload, max_buff); | |
2296 | } | |
2297 | ||
2298 | /* SBMM - Shared Buffer Multicast Management Register | |
2299 | * -------------------------------------------------- | |
2300 | * The SBMM register configures and retrieves the shared buffer allocation | |
2301 | * and configuration for MC packets according to Switch-Priority, including | |
2302 | * the binding to pool and definition of the associated quota. | |
2303 | */ | |
2304 | #define MLXSW_REG_SBMM_ID 0xB004 | |
2305 | #define MLXSW_REG_SBMM_LEN 0x28 | |
2306 | ||
2307 | static const struct mlxsw_reg_info mlxsw_reg_sbmm = { | |
2308 | .id = MLXSW_REG_SBMM_ID, | |
2309 | .len = MLXSW_REG_SBMM_LEN, | |
2310 | }; | |
2311 | ||
2312 | /* reg_sbmm_prio | |
2313 | * Switch Priority. | |
2314 | * Access: Index | |
2315 | */ | |
2316 | MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); | |
2317 | ||
2318 | /* reg_sbmm_min_buff | |
2319 | * Minimum buffer size for the limiter, in cells. | |
2320 | * Access: RW | |
2321 | */ | |
2322 | MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); | |
2323 | ||
2324 | /* reg_sbmm_max_buff | |
2325 | * When the pool associated to the port-pg/tclass is configured to | |
2326 | * static, Maximum buffer size for the limiter configured in cells. | |
2327 | * When the pool associated to the port-pg/tclass is configured to | |
2328 | * dynamic, the max_buff holds the "alpha" parameter, supporting | |
2329 | * the following values: | |
2330 | * 0: 0 | |
2331 | * i: (1/128)*2^(i-1), for i=1..14 | |
2332 | * 0xFF: Infinity | |
2333 | * Access: RW | |
2334 | */ | |
2335 | MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); | |
2336 | ||
2337 | /* reg_sbmm_pool | |
2338 | * Association of the port-priority to a pool. | |
2339 | * Access: RW | |
2340 | */ | |
2341 | MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); | |
2342 | ||
2343 | static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, | |
2344 | u32 max_buff, u8 pool) | |
2345 | { | |
2346 | MLXSW_REG_ZERO(sbmm, payload); | |
2347 | mlxsw_reg_sbmm_prio_set(payload, prio); | |
2348 | mlxsw_reg_sbmm_min_buff_set(payload, min_buff); | |
2349 | mlxsw_reg_sbmm_max_buff_set(payload, max_buff); | |
2350 | mlxsw_reg_sbmm_pool_set(payload, pool); | |
2351 | } | |
2352 | ||
4ec14b76 IS |
2353 | static inline const char *mlxsw_reg_id_str(u16 reg_id) |
2354 | { | |
2355 | switch (reg_id) { | |
2356 | case MLXSW_REG_SGCR_ID: | |
2357 | return "SGCR"; | |
2358 | case MLXSW_REG_SPAD_ID: | |
2359 | return "SPAD"; | |
e61011b5 IS |
2360 | case MLXSW_REG_SSPR_ID: |
2361 | return "SSPR"; | |
e534a56a JP |
2362 | case MLXSW_REG_SFDAT_ID: |
2363 | return "SFDAT"; | |
236033b3 JP |
2364 | case MLXSW_REG_SFD_ID: |
2365 | return "SFD"; | |
f5d88f58 JP |
2366 | case MLXSW_REG_SFN_ID: |
2367 | return "SFN"; | |
4ec14b76 IS |
2368 | case MLXSW_REG_SPMS_ID: |
2369 | return "SPMS"; | |
b2e345f9 ER |
2370 | case MLXSW_REG_SPVID_ID: |
2371 | return "SPVID"; | |
2372 | case MLXSW_REG_SPVM_ID: | |
2373 | return "SPVM"; | |
4ec14b76 IS |
2374 | case MLXSW_REG_SFGC_ID: |
2375 | return "SFGC"; | |
2376 | case MLXSW_REG_SFTR_ID: | |
2377 | return "SFTR"; | |
2378 | case MLXSW_REG_SPMLR_ID: | |
2379 | return "SPMLR"; | |
64790239 IS |
2380 | case MLXSW_REG_SVFA_ID: |
2381 | return "SVFA"; | |
1f65da74 IS |
2382 | case MLXSW_REG_SVPE_ID: |
2383 | return "SVPE"; | |
f1fb693a IS |
2384 | case MLXSW_REG_SFMR_ID: |
2385 | return "SFMR"; | |
a4feea74 IS |
2386 | case MLXSW_REG_SPVMLR_ID: |
2387 | return "SPVMLR"; | |
4ec14b76 IS |
2388 | case MLXSW_REG_PMLP_ID: |
2389 | return "PMLP"; | |
2390 | case MLXSW_REG_PMTU_ID: | |
2391 | return "PMTU"; | |
2392 | case MLXSW_REG_PTYS_ID: | |
2393 | return "PTYS"; | |
2394 | case MLXSW_REG_PPAD_ID: | |
2395 | return "PPAD"; | |
2396 | case MLXSW_REG_PAOS_ID: | |
2397 | return "PAOS"; | |
2398 | case MLXSW_REG_PPCNT_ID: | |
2399 | return "PPCNT"; | |
e0594369 JP |
2400 | case MLXSW_REG_PBMC_ID: |
2401 | return "PBMC"; | |
4ec14b76 IS |
2402 | case MLXSW_REG_PSPA_ID: |
2403 | return "PSPA"; | |
2404 | case MLXSW_REG_HTGT_ID: | |
2405 | return "HTGT"; | |
2406 | case MLXSW_REG_HPKT_ID: | |
2407 | return "HPKT"; | |
e0594369 JP |
2408 | case MLXSW_REG_SBPR_ID: |
2409 | return "SBPR"; | |
2410 | case MLXSW_REG_SBCM_ID: | |
2411 | return "SBCM"; | |
2412 | case MLXSW_REG_SBPM_ID: | |
2413 | return "SBPM"; | |
2414 | case MLXSW_REG_SBMM_ID: | |
2415 | return "SBMM"; | |
4ec14b76 IS |
2416 | default: |
2417 | return "*UNKNOWN*"; | |
2418 | } | |
2419 | } | |
2420 | ||
2421 | /* PUDE - Port Up / Down Event | |
2422 | * --------------------------- | |
2423 | * Reports the operational state change of a port. | |
2424 | */ | |
2425 | #define MLXSW_REG_PUDE_LEN 0x10 | |
2426 | ||
2427 | /* reg_pude_swid | |
2428 | * Switch partition ID with which to associate the port. | |
2429 | * Access: Index | |
2430 | */ | |
2431 | MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); | |
2432 | ||
2433 | /* reg_pude_local_port | |
2434 | * Local port number. | |
2435 | * Access: Index | |
2436 | */ | |
2437 | MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); | |
2438 | ||
2439 | /* reg_pude_admin_status | |
2440 | * Port administrative state (the desired state). | |
2441 | * 1 - Up. | |
2442 | * 2 - Down. | |
2443 | * 3 - Up once. This means that in case of link failure, the port won't go | |
2444 | * into polling mode, but will wait to be re-enabled by software. | |
2445 | * 4 - Disabled by system. Can only be set by hardware. | |
2446 | * Access: RO | |
2447 | */ | |
2448 | MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); | |
2449 | ||
2450 | /* reg_pude_oper_status | |
2451 | * Port operatioanl state. | |
2452 | * 1 - Up. | |
2453 | * 2 - Down. | |
2454 | * 3 - Down by port failure. This means that the device will not let the | |
2455 | * port up again until explicitly specified by software. | |
2456 | * Access: RO | |
2457 | */ | |
2458 | MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); | |
2459 | ||
2460 | #endif |