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net: use eth_hw_addr_random() and reset addr_assign_type
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / marvell / pxa168_eth.c
CommitLineData
a49f37ee
SS		 1/*
2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
4 *
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
10206601 7 * Zhangfei Gao <zgao6@marvell.com>
a49f37ee
SS		 8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/in.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/udp.h>
32#include <linux/etherdevice.h>
33#include <linux/bitops.h>
34#include <linux/delay.h>
35#include <linux/ethtool.h>
36#include <linux/platform_device.h>
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/workqueue.h>
40#include <linux/clk.h>
41#include <linux/phy.h>
42#include <linux/io.h>
b7e43381 43#include <linux/interrupt.h>
a49f37ee
SS		 44#include <linux/types.h>
45#include <asm/pgtable.h>
46#include <asm/system.h>
a49f37ee
SS		 47#include <asm/cacheflush.h>
48#include <linux/pxa168_eth.h>
49
50#define DRIVER_NAME "pxa168-eth"
51#define DRIVER_VERSION "0.3"
52
53/*
54 * Registers
55 */
56
57#define PHY_ADDRESS 0x0000
58#define SMI 0x0010
59#define PORT_CONFIG 0x0400
60#define PORT_CONFIG_EXT 0x0408
61#define PORT_COMMAND 0x0410
62#define PORT_STATUS 0x0418
63#define HTPR 0x0428
64#define SDMA_CONFIG 0x0440
65#define SDMA_CMD 0x0448
66#define INT_CAUSE 0x0450
67#define INT_W_CLEAR 0x0454
68#define INT_MASK 0x0458
69#define ETH_F_RX_DESC_0 0x0480
70#define ETH_C_RX_DESC_0 0x04A0
71#define ETH_C_TX_DESC_1 0x04E4
72
73/* smi register */
74#define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
75#define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
76#define SMI_OP_W (0 << 26) /* Write operation */
77#define SMI_OP_R (1 << 26) /* Read operation */
78
79#define PHY_WAIT_ITERATIONS 10
80
81#define PXA168_ETH_PHY_ADDR_DEFAULT 0
82/* RX & TX descriptor command */
83#define BUF_OWNED_BY_DMA (1 << 31)
84
85/* RX descriptor status */
86#define RX_EN_INT (1 << 23)
87#define RX_FIRST_DESC (1 << 17)
88#define RX_LAST_DESC (1 << 16)
89#define RX_ERROR (1 << 15)
90
91/* TX descriptor command */
92#define TX_EN_INT (1 << 23)
93#define TX_GEN_CRC (1 << 22)
94#define TX_ZERO_PADDING (1 << 18)
95#define TX_FIRST_DESC (1 << 17)
96#define TX_LAST_DESC (1 << 16)
97#define TX_ERROR (1 << 15)
98
99/* SDMA_CMD */
100#define SDMA_CMD_AT (1 << 31)
101#define SDMA_CMD_TXDL (1 << 24)
102#define SDMA_CMD_TXDH (1 << 23)
103#define SDMA_CMD_AR (1 << 15)
104#define SDMA_CMD_ERD (1 << 7)
105
106/* Bit definitions of the Port Config Reg */
107#define PCR_HS (1 << 12)
108#define PCR_EN (1 << 7)
109#define PCR_PM (1 << 0)
110
111/* Bit definitions of the Port Config Extend Reg */
112#define PCXR_2BSM (1 << 28)
113#define PCXR_DSCP_EN (1 << 21)
114#define PCXR_MFL_1518 (0 << 14)
115#define PCXR_MFL_1536 (1 << 14)
116#define PCXR_MFL_2048 (2 << 14)
117#define PCXR_MFL_64K (3 << 14)
118#define PCXR_FLP (1 << 11)
119#define PCXR_PRIO_TX_OFF 3
120#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
121
122/* Bit definitions of the SDMA Config Reg */
123#define SDCR_BSZ_OFF 12
124#define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
125#define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
126#define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
127#define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
128#define SDCR_BLMR (1 << 6)
129#define SDCR_BLMT (1 << 7)
130#define SDCR_RIFB (1 << 9)
131#define SDCR_RC_OFF 2
132#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
133
134/*
135 * Bit definitions of the Interrupt Cause Reg
136 * and Interrupt MASK Reg is the same
137 */
138#define ICR_RXBUF (1 << 0)
139#define ICR_TXBUF_H (1 << 2)
140#define ICR_TXBUF_L (1 << 3)
141#define ICR_TXEND_H (1 << 6)
142#define ICR_TXEND_L (1 << 7)
143#define ICR_RXERR (1 << 8)
144#define ICR_TXERR_H (1 << 10)
145#define ICR_TXERR_L (1 << 11)
146#define ICR_TX_UDR (1 << 13)
147#define ICR_MII_CH (1 << 28)
148
149#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
150 ICR_TXERR_H | ICR_TXERR_L |\
151 ICR_TXEND_H | ICR_TXEND_L |\
152 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
153
154#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
155
156#define NUM_RX_DESCS 64
157#define NUM_TX_DESCS 64
158
159#define HASH_ADD 0
160#define HASH_DELETE 1
161#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
162#define HOP_NUMBER 12
163
164/* Bit definitions for Port status */
165#define PORT_SPEED_100 (1 << 0)
166#define FULL_DUPLEX (1 << 1)
167#define FLOW_CONTROL_ENABLED (1 << 2)
168#define LINK_UP (1 << 3)
169
170/* Bit definitions for work to be done */
171#define WORK_LINK (1 << 0)
172#define WORK_TX_DONE (1 << 1)
173
174/*
175 * Misc definitions.
176 */
177#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
178
179struct rx_desc {
180 u32 cmd_sts; /* Descriptor command status */
181 u16 byte_cnt; /* Descriptor buffer byte count */
182 u16 buf_size; /* Buffer size */
183 u32 buf_ptr; /* Descriptor buffer pointer */
184 u32 next_desc_ptr; /* Next descriptor pointer */
185};
186
187struct tx_desc {
188 u32 cmd_sts; /* Command/status field */
189 u16 reserved;
190 u16 byte_cnt; /* buffer byte count */
191 u32 buf_ptr; /* pointer to buffer for this descriptor */
192 u32 next_desc_ptr; /* Pointer to next descriptor */
193};
194
195struct pxa168_eth_private {
196 int port_num; /* User Ethernet port number */
197
198 int rx_resource_err; /* Rx ring resource error flag */
199
200 /* Next available and first returning Rx resource */
201 int rx_curr_desc_q, rx_used_desc_q;
202
203 /* Next available and first returning Tx resource */
204 int tx_curr_desc_q, tx_used_desc_q;
205
206 struct rx_desc *p_rx_desc_area;
207 dma_addr_t rx_desc_dma;
208 int rx_desc_area_size;
209 struct sk_buff **rx_skb;
210
211 struct tx_desc *p_tx_desc_area;
212 dma_addr_t tx_desc_dma;
213 int tx_desc_area_size;
214 struct sk_buff **tx_skb;
215
216 struct work_struct tx_timeout_task;
217
218 struct net_device *dev;
219 struct napi_struct napi;
220 u8 work_todo;
221 int skb_size;
222
223 struct net_device_stats stats;
224 /* Size of Tx Ring per queue */
225 int tx_ring_size;
226 /* Number of tx descriptors in use */
227 int tx_desc_count;
228 /* Size of Rx Ring per queue */
229 int rx_ring_size;
230 /* Number of rx descriptors in use */
231 int rx_desc_count;
232
233 /*
234 * Used in case RX Ring is empty, which can occur when
235 * system does not have resources (skb's)
236 */
237 struct timer_list timeout;
238 struct mii_bus *smi_bus;
239 struct phy_device *phy;
240
241 /* clock */
242 struct clk *clk;
243 struct pxa168_eth_platform_data *pd;
244 /*
245 * Ethernet controller base address.
246 */
247 void __iomem *base;
248
249 /* Pointer to the hardware address filter table */
250 void *htpr;
251 dma_addr_t htpr_dma;
252};
253
254struct addr_table_entry {
255 __le32 lo;
256 __le32 hi;
257};
258
259/* Bit fields of a Hash Table Entry */
260enum hash_table_entry {
261 HASH_ENTRY_VALID = 1,
262 SKIP = 2,
263 HASH_ENTRY_RECEIVE_DISCARD = 4,
264 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
265};
266
267static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
268static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
269static int pxa168_init_hw(struct pxa168_eth_private *pep);
270static void eth_port_reset(struct net_device *dev);
271static void eth_port_start(struct net_device *dev);
272static int pxa168_eth_open(struct net_device *dev);
273static int pxa168_eth_stop(struct net_device *dev);
274static int ethernet_phy_setup(struct net_device *dev);
275
276static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
277{
278 return readl(pep->base + offset);
279}
280
281static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
282{
283 writel(data, pep->base + offset);
284}
285
286static void abort_dma(struct pxa168_eth_private *pep)
287{
288 int delay;
289 int max_retries = 40;
290
291 do {
292 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
293 udelay(100);
294
295 delay = 10;
296 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
297 && delay-- > 0) {
298 udelay(10);
299 }
300 } while (max_retries-- > 0 && delay <= 0);
301
302 if (max_retries <= 0)
303 printk(KERN_ERR "%s : DMA Stuck\n", __func__);
304}
305
306static int ethernet_phy_get(struct pxa168_eth_private *pep)
307{
308 unsigned int reg_data;
309
310 reg_data = rdl(pep, PHY_ADDRESS);
311
312 return (reg_data >> (5 * pep->port_num)) & 0x1f;
313}
314
315static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
316{
317 u32 reg_data;
318 int addr_shift = 5 * pep->port_num;
319
320 reg_data = rdl(pep, PHY_ADDRESS);
321 reg_data &= ~(0x1f << addr_shift);
322 reg_data |= (phy_addr & 0x1f) << addr_shift;
323 wrl(pep, PHY_ADDRESS, reg_data);
324}
325
326static void ethernet_phy_reset(struct pxa168_eth_private *pep)
327{
328 int data;
329
330 data = phy_read(pep->phy, MII_BMCR);
331 if (data < 0)
332 return;
333
334 data |= BMCR_RESET;
335 if (phy_write(pep->phy, MII_BMCR, data) < 0)
336 return;
337
338 do {
339 data = phy_read(pep->phy, MII_BMCR);
340 } while (data >= 0 && data & BMCR_RESET);
341}
342
343static void rxq_refill(struct net_device *dev)
344{
345 struct pxa168_eth_private *pep = netdev_priv(dev);
346 struct sk_buff *skb;
347 struct rx_desc *p_used_rx_desc;
348 int used_rx_desc;
349
350 while (pep->rx_desc_count < pep->rx_ring_size) {
351 int size;
352
c056b734 353 skb = netdev_alloc_skb(dev, pep->skb_size);
a49f37ee
SS		 354 if (!skb)
355 break;
356 if (SKB_DMA_REALIGN)
357 skb_reserve(skb, SKB_DMA_REALIGN);
358 pep->rx_desc_count++;
359 /* Get 'used' Rx descriptor */
360 used_rx_desc = pep->rx_used_desc_q;
361 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
362 size = skb->end - skb->data;
363 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
364 skb->data,
365 size,
366 DMA_FROM_DEVICE);
367 p_used_rx_desc->buf_size = size;
368 pep->rx_skb[used_rx_desc] = skb;
369
370 /* Return the descriptor to DMA ownership */
371 wmb();
372 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
373 wmb();
374
375 /* Move the used descriptor pointer to the next descriptor */
376 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
377
378 /* Any Rx return cancels the Rx resource error status */
379 pep->rx_resource_err = 0;
380
381 skb_reserve(skb, ETH_HW_IP_ALIGN);
382 }
383
384 /*
385 * If RX ring is empty of SKB, set a timer to try allocating
386 * again at a later time.
387 */
388 if (pep->rx_desc_count == 0) {
389 pep->timeout.expires = jiffies + (HZ / 10);
390 add_timer(&pep->timeout);
391 }
392}
393
394static inline void rxq_refill_timer_wrapper(unsigned long data)
395{
396 struct pxa168_eth_private *pep = (void *)data;
397 napi_schedule(&pep->napi);
398}
399
400static inline u8 flip_8_bits(u8 x)
401{
402 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
403 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
404 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
405 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
406}
407
408static void nibble_swap_every_byte(unsigned char *mac_addr)
409{
410 int i;
411 for (i = 0; i < ETH_ALEN; i++) {
412 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
413 ((mac_addr[i] & 0xf0) >> 4);
414 }
415}
416
417static void inverse_every_nibble(unsigned char *mac_addr)
418{
419 int i;
420 for (i = 0; i < ETH_ALEN; i++)
421 mac_addr[i] = flip_8_bits(mac_addr[i]);
422}
423
424/*
425 * ----------------------------------------------------------------------------
426 * This function will calculate the hash function of the address.
427 * Inputs
428 * mac_addr_orig - MAC address.
429 * Outputs
430 * return the calculated entry.
431 */
432static u32 hash_function(unsigned char *mac_addr_orig)
433{
434 u32 hash_result;
435 u32 addr0;
436 u32 addr1;
437 u32 addr2;
438 u32 addr3;
439 unsigned char mac_addr[ETH_ALEN];
440
441 /* Make a copy of MAC address since we are going to performe bit
442 * operations on it
443 */
444 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
445
446 nibble_swap_every_byte(mac_addr);
447 inverse_every_nibble(mac_addr);
448
449 addr0 = (mac_addr[5] >> 2) & 0x3f;
450 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
451 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
452 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
453
454 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
455 hash_result = hash_result & 0x07ff;
456 return hash_result;
457}
458
459/*
460 * ----------------------------------------------------------------------------
461 * This function will add/del an entry to the address table.
462 * Inputs
463 * pep - ETHERNET .
464 * mac_addr - MAC address.
465 * skip - if 1, skip this address.Used in case of deleting an entry which is a
25985edc 466 * part of chain in the hash table.We can't just delete the entry since
a49f37ee
SS		 467 * that will break the chain.We need to defragment the tables time to
468 * time.
469 * rd - 0 Discard packet upon match.
470 * - 1 Receive packet upon match.
471 * Outputs
472 * address table entry is added/deleted.
473 * 0 if success.
474 * -ENOSPC if table full
475 */
476static int add_del_hash_entry(struct pxa168_eth_private *pep,
477 unsigned char *mac_addr,
478 u32 rd, u32 skip, int del)
479{
480 struct addr_table_entry *entry, *start;
481 u32 new_high;
482 u32 new_low;
483 u32 i;
484
485 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
486 | (((mac_addr[1] >> 0) & 0xf) << 11)
487 | (((mac_addr[0] >> 4) & 0xf) << 7)
488 | (((mac_addr[0] >> 0) & 0xf) << 3)
489 | (((mac_addr[3] >> 4) & 0x1) << 31)
490 | (((mac_addr[3] >> 0) & 0xf) << 27)
491 | (((mac_addr[2] >> 4) & 0xf) << 23)
492 | (((mac_addr[2] >> 0) & 0xf) << 19)
493 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
494 | HASH_ENTRY_VALID;
495
496 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
497 | (((mac_addr[5] >> 0) & 0xf) << 11)
498 | (((mac_addr[4] >> 4) & 0xf) << 7)
499 | (((mac_addr[4] >> 0) & 0xf) << 3)
500 | (((mac_addr[3] >> 5) & 0x7) << 0);
501
502 /*
503 * Pick the appropriate table, start scanning for free/reusable
504 * entries at the index obtained by hashing the specified MAC address
505 */
43d620c8 506 start = pep->htpr;
a49f37ee
SS		 507 entry = start + hash_function(mac_addr);
508 for (i = 0; i < HOP_NUMBER; i++) {
509 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
510 break;
511 } else {
512 /* if same address put in same position */
513 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
514 (new_low & 0xfffffff8)) &&
515 (le32_to_cpu(entry->hi) == new_high)) {
516 break;
517 }
518 }
519 if (entry == start + 0x7ff)
520 entry = start;
521 else
522 entry++;
523 }
524
525 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
526 (le32_to_cpu(entry->hi) != new_high) && del)
527 return 0;
528
529 if (i == HOP_NUMBER) {
530 if (!del) {
531 printk(KERN_INFO "%s: table section is full, need to "
532 "move to 16kB implementation?\n",
533 __FILE__);
534 return -ENOSPC;
535 } else
536 return 0;
537 }
538
539 /*
540 * Update the selected entry
541 */
542 if (del) {
543 entry->hi = 0;
544 entry->lo = 0;
545 } else {
546 entry->hi = cpu_to_le32(new_high);
547 entry->lo = cpu_to_le32(new_low);
548 }
549
550 return 0;
551}
552
553/*
554 * ----------------------------------------------------------------------------
555 * Create an addressTable entry from MAC address info
556 * found in the specifed net_device struct
557 *
558 * Input : pointer to ethernet interface network device structure
559 * Output : N/A
560 */
561static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
562 unsigned char *oaddr,
563 unsigned char *addr)
564{
565 /* Delete old entry */
566 if (oaddr)
567 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
568 /* Add new entry */
569 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
570}
571
572static int init_hash_table(struct pxa168_eth_private *pep)
573{
574 /*
575 * Hardware expects CPU to build a hash table based on a predefined
576 * hash function and populate it based on hardware address. The
577 * location of the hash table is identified by 32-bit pointer stored
578 * in HTPR internal register. Two possible sizes exists for the hash
579 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
580 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
581 * 1/2kB.
582 */
583 /* TODO: Add support for 8kB hash table and alternative hash
584 * function.Driver can dynamically switch to them if the 1/2kB hash
585 * table is full.
586 */
587 if (pep->htpr == NULL) {
588 pep->htpr = dma_alloc_coherent(pep->dev->dev.parent,
589 HASH_ADDR_TABLE_SIZE,
590 &pep->htpr_dma, GFP_KERNEL);
591 if (pep->htpr == NULL)
592 return -ENOMEM;
593 }
594 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
595 wrl(pep, HTPR, pep->htpr_dma);
596 return 0;
597}
598
599static void pxa168_eth_set_rx_mode(struct net_device *dev)
600{
601 struct pxa168_eth_private *pep = netdev_priv(dev);
602 struct netdev_hw_addr *ha;
603 u32 val;
604
605 val = rdl(pep, PORT_CONFIG);
606 if (dev->flags & IFF_PROMISC)
607 val |= PCR_PM;
608 else
609 val &= ~PCR_PM;
610 wrl(pep, PORT_CONFIG, val);
611
612 /*
613 * Remove the old list of MAC address and add dev->addr
614 * and multicast address.
615 */
616 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
617 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
618
619 netdev_for_each_mc_addr(ha, dev)
620 update_hash_table_mac_address(pep, NULL, ha->addr);
621}
622
623static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
624{
625 struct sockaddr *sa = addr;
626 struct pxa168_eth_private *pep = netdev_priv(dev);
627 unsigned char oldMac[ETH_ALEN];
628
629 if (!is_valid_ether_addr(sa->sa_data))
630 return -EINVAL;
631 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
7ce5d222 632 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
a49f37ee
SS		 633 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
634 netif_addr_lock_bh(dev);
635 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
636 netif_addr_unlock_bh(dev);
637 return 0;
638}
639
640static void eth_port_start(struct net_device *dev)
641{
642 unsigned int val = 0;
643 struct pxa168_eth_private *pep = netdev_priv(dev);
644 int tx_curr_desc, rx_curr_desc;
645
646 /* Perform PHY reset, if there is a PHY. */
647 if (pep->phy != NULL) {
648 struct ethtool_cmd cmd;
649
650 pxa168_get_settings(pep->dev, &cmd);
651 ethernet_phy_reset(pep);
652 pxa168_set_settings(pep->dev, &cmd);
653 }
654
655 /* Assignment of Tx CTRP of given queue */
656 tx_curr_desc = pep->tx_curr_desc_q;
657 wrl(pep, ETH_C_TX_DESC_1,
b2bc8563 658 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
a49f37ee
SS		 659
660 /* Assignment of Rx CRDP of given queue */
661 rx_curr_desc = pep->rx_curr_desc_q;
662 wrl(pep, ETH_C_RX_DESC_0,
b2bc8563 663 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 664
665 wrl(pep, ETH_F_RX_DESC_0,
b2bc8563 666 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 667
668 /* Clear all interrupts */
669 wrl(pep, INT_CAUSE, 0);
670
671 /* Enable all interrupts for receive, transmit and error. */
672 wrl(pep, INT_MASK, ALL_INTS);
673
674 val = rdl(pep, PORT_CONFIG);
675 val |= PCR_EN;
676 wrl(pep, PORT_CONFIG, val);
677
678 /* Start RX DMA engine */
679 val = rdl(pep, SDMA_CMD);
680 val |= SDMA_CMD_ERD;
681 wrl(pep, SDMA_CMD, val);
682}
683
684static void eth_port_reset(struct net_device *dev)
685{
686 struct pxa168_eth_private *pep = netdev_priv(dev);
687 unsigned int val = 0;
688
689 /* Stop all interrupts for receive, transmit and error. */
690 wrl(pep, INT_MASK, 0);
691
692 /* Clear all interrupts */
693 wrl(pep, INT_CAUSE, 0);
694
695 /* Stop RX DMA */
696 val = rdl(pep, SDMA_CMD);
697 val &= ~SDMA_CMD_ERD; /* abort dma command */
698
699 /* Abort any transmit and receive operations and put DMA
700 * in idle state.
701 */
702 abort_dma(pep);
703
704 /* Disable port */
705 val = rdl(pep, PORT_CONFIG);
706 val &= ~PCR_EN;
707 wrl(pep, PORT_CONFIG, val);
708}
709
710/*
711 * txq_reclaim - Free the tx desc data for completed descriptors
712 * If force is non-zero, frees uncompleted descriptors as well
713 */
714static int txq_reclaim(struct net_device *dev, int force)
715{
716 struct pxa168_eth_private *pep = netdev_priv(dev);
717 struct tx_desc *desc;
718 u32 cmd_sts;
719 struct sk_buff *skb;
720 int tx_index;
721 dma_addr_t addr;
722 int count;
723 int released = 0;
724
725 netif_tx_lock(dev);
726
727 pep->work_todo &= ~WORK_TX_DONE;
728 while (pep->tx_desc_count > 0) {
729 tx_index = pep->tx_used_desc_q;
730 desc = &pep->p_tx_desc_area[tx_index];
731 cmd_sts = desc->cmd_sts;
732 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
733 if (released > 0) {
734 goto txq_reclaim_end;
735 } else {
736 released = -1;
737 goto txq_reclaim_end;
738 }
739 }
740 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
741 pep->tx_desc_count--;
742 addr = desc->buf_ptr;
743 count = desc->byte_cnt;
744 skb = pep->tx_skb[tx_index];
745 if (skb)
746 pep->tx_skb[tx_index] = NULL;
747
748 if (cmd_sts & TX_ERROR) {
749 if (net_ratelimit())
750 printk(KERN_ERR "%s: Error in TX\n", dev->name);
751 dev->stats.tx_errors++;
752 }
753 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
754 if (skb)
755 dev_kfree_skb_irq(skb);
756 released++;
757 }
758txq_reclaim_end:
759 netif_tx_unlock(dev);
760 return released;
761}
762
763static void pxa168_eth_tx_timeout(struct net_device *dev)
764{
765 struct pxa168_eth_private *pep = netdev_priv(dev);
766
767 printk(KERN_INFO "%s: TX timeout desc_count %d\n",
768 dev->name, pep->tx_desc_count);
769
770 schedule_work(&pep->tx_timeout_task);
771}
772
773static void pxa168_eth_tx_timeout_task(struct work_struct *work)
774{
775 struct pxa168_eth_private *pep = container_of(work,
776 struct pxa168_eth_private,
777 tx_timeout_task);
778 struct net_device *dev = pep->dev;
779 pxa168_eth_stop(dev);
780 pxa168_eth_open(dev);
781}
782
783static int rxq_process(struct net_device *dev, int budget)
784{
785 struct pxa168_eth_private *pep = netdev_priv(dev);
786 struct net_device_stats *stats = &dev->stats;
787 unsigned int received_packets = 0;
788 struct sk_buff *skb;
789
790 while (budget-- > 0) {
791 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
792 struct rx_desc *rx_desc;
793 unsigned int cmd_sts;
794
795 /* Do not process Rx ring in case of Rx ring resource error */
796 if (pep->rx_resource_err)
797 break;
798 rx_curr_desc = pep->rx_curr_desc_q;
799 rx_used_desc = pep->rx_used_desc_q;
800 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
801 cmd_sts = rx_desc->cmd_sts;
802 rmb();
803 if (cmd_sts & (BUF_OWNED_BY_DMA))
804 break;
805 skb = pep->rx_skb[rx_curr_desc];
806 pep->rx_skb[rx_curr_desc] = NULL;
807
808 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
809 pep->rx_curr_desc_q = rx_next_curr_desc;
810
811 /* Rx descriptors exhausted. */
812 /* Set the Rx ring resource error flag */
813 if (rx_next_curr_desc == rx_used_desc)
814 pep->rx_resource_err = 1;
815 pep->rx_desc_count--;
816 dma_unmap_single(NULL, rx_desc->buf_ptr,
817 rx_desc->buf_size,
818 DMA_FROM_DEVICE);
819 received_packets++;
820 /*
821 * Update statistics.
822 * Note byte count includes 4 byte CRC count
823 */
824 stats->rx_packets++;
825 stats->rx_bytes += rx_desc->byte_cnt;
826 /*
827 * In case received a packet without first / last bits on OR
828 * the error summary bit is on, the packets needs to be droped.
829 */
830 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
831 (RX_FIRST_DESC | RX_LAST_DESC))
832 || (cmd_sts & RX_ERROR)) {
833
834 stats->rx_dropped++;
835 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
836 (RX_FIRST_DESC | RX_LAST_DESC)) {
837 if (net_ratelimit())
838 printk(KERN_ERR
839 "%s: Rx pkt on multiple desc\n",
840 dev->name);
841 }
842 if (cmd_sts & RX_ERROR)
843 stats->rx_errors++;
844 dev_kfree_skb_irq(skb);
845 } else {
846 /*
847 * The -4 is for the CRC in the trailer of the
848 * received packet
849 */
850 skb_put(skb, rx_desc->byte_cnt - 4);
851 skb->protocol = eth_type_trans(skb, dev);
852 netif_receive_skb(skb);
853 }
a49f37ee
SS		 854 }
855 /* Fill RX ring with skb's */
856 rxq_refill(dev);
857 return received_packets;
858}
859
860static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
861 struct net_device *dev)
862{
863 u32 icr;
864 int ret = 0;
865
866 icr = rdl(pep, INT_CAUSE);
867 if (icr == 0)
868 return IRQ_NONE;
869
870 wrl(pep, INT_CAUSE, ~icr);
871 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
872 pep->work_todo |= WORK_TX_DONE;
873 ret = 1;
874 }
875 if (icr & ICR_RXBUF)
876 ret = 1;
877 if (icr & ICR_MII_CH) {
878 pep->work_todo |= WORK_LINK;
879 ret = 1;
880 }
881 return ret;
882}
883
884static void handle_link_event(struct pxa168_eth_private *pep)
885{
886 struct net_device *dev = pep->dev;
887 u32 port_status;
888 int speed;
889 int duplex;
890 int fc;
891
892 port_status = rdl(pep, PORT_STATUS);
893 if (!(port_status & LINK_UP)) {
894 if (netif_carrier_ok(dev)) {
895 printk(KERN_INFO "%s: link down\n", dev->name);
896 netif_carrier_off(dev);
897 txq_reclaim(dev, 1);
898 }
899 return;
900 }
901 if (port_status & PORT_SPEED_100)
902 speed = 100;
903 else
904 speed = 10;
905
906 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
907 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
908 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
909 "flow control %sabled\n", dev->name,
910 speed, duplex ? "full" : "half", fc ? "en" : "dis");
911 if (!netif_carrier_ok(dev))
912 netif_carrier_on(dev);
913}
914
915static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
916{
917 struct net_device *dev = (struct net_device *)dev_id;
918 struct pxa168_eth_private *pep = netdev_priv(dev);
919
920 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
921 return IRQ_NONE;
922 /* Disable interrupts */
923 wrl(pep, INT_MASK, 0);
924 napi_schedule(&pep->napi);
925 return IRQ_HANDLED;
926}
927
928static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
929{
930 int skb_size;
931
932 /*
933 * Reserve 2+14 bytes for an ethernet header (the hardware
934 * automatically prepends 2 bytes of dummy data to each
935 * received packet), 16 bytes for up to four VLAN tags, and
936 * 4 bytes for the trailing FCS -- 36 bytes total.
937 */
938 skb_size = pep->dev->mtu + 36;
939
940 /*
941 * Make sure that the skb size is a multiple of 8 bytes, as
942 * the lower three bits of the receive descriptor's buffer
943 * size field are ignored by the hardware.
944 */
945 pep->skb_size = (skb_size + 7) & ~7;
946
947 /*
948 * If NET_SKB_PAD is smaller than a cache line,
949 * netdev_alloc_skb() will cause skb->data to be misaligned
950 * to a cache line boundary. If this is the case, include
951 * some extra space to allow re-aligning the data area.
952 */
953 pep->skb_size += SKB_DMA_REALIGN;
954
955}
956
957static int set_port_config_ext(struct pxa168_eth_private *pep)
958{
959 int skb_size;
960
961 pxa168_eth_recalc_skb_size(pep);
962 if (pep->skb_size <= 1518)
963 skb_size = PCXR_MFL_1518;
964 else if (pep->skb_size <= 1536)
965 skb_size = PCXR_MFL_1536;
966 else if (pep->skb_size <= 2048)
967 skb_size = PCXR_MFL_2048;
968 else
969 skb_size = PCXR_MFL_64K;
970
971 /* Extended Port Configuration */
972 wrl(pep,
973 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
974 PCXR_DSCP_EN | /* Enable DSCP in IP */
975 skb_size | PCXR_FLP | /* do not force link pass */
976 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
977
978 return 0;
979}
980
981static int pxa168_init_hw(struct pxa168_eth_private *pep)
982{
983 int err = 0;
984
985 /* Disable interrupts */
986 wrl(pep, INT_MASK, 0);
987 wrl(pep, INT_CAUSE, 0);
988 /* Write to ICR to clear interrupts. */
989 wrl(pep, INT_W_CLEAR, 0);
990 /* Abort any transmit and receive operations and put DMA
991 * in idle state.
992 */
993 abort_dma(pep);
994 /* Initialize address hash table */
995 err = init_hash_table(pep);
996 if (err)
997 return err;
998 /* SDMA configuration */
999 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
1000 SDCR_RIFB | /* Rx interrupt on frame */
1001 SDCR_BLMT | /* Little endian transmit */
1002 SDCR_BLMR | /* Little endian receive */
1003 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
1004 /* Port Configuration */
1005 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
1006 set_port_config_ext(pep);
1007
1008 return err;
1009}
1010
1011static int rxq_init(struct net_device *dev)
1012{
1013 struct pxa168_eth_private *pep = netdev_priv(dev);
1014 struct rx_desc *p_rx_desc;
1015 int size = 0, i = 0;
1016 int rx_desc_num = pep->rx_ring_size;
1017
1018 /* Allocate RX skb rings */
1019 pep->rx_skb = kmalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
1020 GFP_KERNEL);
e404decb 1021 if (!pep->rx_skb)
a49f37ee 1022 return -ENOMEM;
e404decb 1023
a49f37ee
SS		 1024 /* Allocate RX ring */
1025 pep->rx_desc_count = 0;
1026 size = pep->rx_ring_size * sizeof(struct rx_desc);
1027 pep->rx_desc_area_size = size;
1028 pep->p_rx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size,
1029 &pep->rx_desc_dma, GFP_KERNEL);
1030 if (!pep->p_rx_desc_area) {
1031 printk(KERN_ERR "%s: Cannot alloc RX ring (size %d bytes)\n",
1032 dev->name, size);
1033 goto out;
1034 }
1035 memset((void *)pep->p_rx_desc_area, 0, size);
1036 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1037 p_rx_desc = (struct rx_desc *)pep->p_rx_desc_area;
1038 for (i = 0; i < rx_desc_num; i++) {
1039 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1040 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1041 }
1042 /* Save Rx desc pointer to driver struct. */
1043 pep->rx_curr_desc_q = 0;
1044 pep->rx_used_desc_q = 0;
1045 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1046 return 0;
1047out:
1048 kfree(pep->rx_skb);
1049 return -ENOMEM;
1050}
1051
1052static void rxq_deinit(struct net_device *dev)
1053{
1054 struct pxa168_eth_private *pep = netdev_priv(dev);
1055 int curr;
1056
1057 /* Free preallocated skb's on RX rings */
1058 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1059 if (pep->rx_skb[curr]) {
1060 dev_kfree_skb(pep->rx_skb[curr]);
1061 pep->rx_desc_count--;
1062 }
1063 }
1064 if (pep->rx_desc_count)
1065 printk(KERN_ERR
1066 "Error in freeing Rx Ring. %d skb's still\n",
1067 pep->rx_desc_count);
1068 /* Free RX ring */
1069 if (pep->p_rx_desc_area)
1070 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1071 pep->p_rx_desc_area, pep->rx_desc_dma);
1072 kfree(pep->rx_skb);
1073}
1074
1075static int txq_init(struct net_device *dev)
1076{
1077 struct pxa168_eth_private *pep = netdev_priv(dev);
1078 struct tx_desc *p_tx_desc;
1079 int size = 0, i = 0;
1080 int tx_desc_num = pep->tx_ring_size;
1081
1082 pep->tx_skb = kmalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
1083 GFP_KERNEL);
e404decb 1084 if (!pep->tx_skb)
a49f37ee 1085 return -ENOMEM;
e404decb 1086
a49f37ee
SS		 1087 /* Allocate TX ring */
1088 pep->tx_desc_count = 0;
1089 size = pep->tx_ring_size * sizeof(struct tx_desc);
1090 pep->tx_desc_area_size = size;
1091 pep->p_tx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size,
1092 &pep->tx_desc_dma, GFP_KERNEL);
1093 if (!pep->p_tx_desc_area) {
1094 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1095 dev->name, size);
1096 goto out;
1097 }
1098 memset((void *)pep->p_tx_desc_area, 0, pep->tx_desc_area_size);
1099 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1100 p_tx_desc = (struct tx_desc *)pep->p_tx_desc_area;
1101 for (i = 0; i < tx_desc_num; i++) {
1102 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1103 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1104 }
1105 pep->tx_curr_desc_q = 0;
1106 pep->tx_used_desc_q = 0;
1107 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1108 return 0;
1109out:
1110 kfree(pep->tx_skb);
1111 return -ENOMEM;
1112}
1113
1114static void txq_deinit(struct net_device *dev)
1115{
1116 struct pxa168_eth_private *pep = netdev_priv(dev);
1117
1118 /* Free outstanding skb's on TX ring */
1119 txq_reclaim(dev, 1);
1120 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1121 /* Free TX ring */
1122 if (pep->p_tx_desc_area)
1123 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1124 pep->p_tx_desc_area, pep->tx_desc_dma);
1125 kfree(pep->tx_skb);
1126}
1127
1128static int pxa168_eth_open(struct net_device *dev)
1129{
1130 struct pxa168_eth_private *pep = netdev_priv(dev);
1131 int err;
1132
1133 err = request_irq(dev->irq, pxa168_eth_int_handler,
1134 IRQF_DISABLED, dev->name, dev);
1135 if (err) {
1136 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1137 return -EAGAIN;
1138 }
1139 pep->rx_resource_err = 0;
1140 err = rxq_init(dev);
1141 if (err != 0)
1142 goto out_free_irq;
1143 err = txq_init(dev);
1144 if (err != 0)
1145 goto out_free_rx_skb;
1146 pep->rx_used_desc_q = 0;
1147 pep->rx_curr_desc_q = 0;
1148
1149 /* Fill RX ring with skb's */
1150 rxq_refill(dev);
1151 pep->rx_used_desc_q = 0;
1152 pep->rx_curr_desc_q = 0;
1153 netif_carrier_off(dev);
1154 eth_port_start(dev);
1155 napi_enable(&pep->napi);
1156 return 0;
1157out_free_rx_skb:
1158 rxq_deinit(dev);
1159out_free_irq:
1160 free_irq(dev->irq, dev);
1161 return err;
1162}
1163
1164static int pxa168_eth_stop(struct net_device *dev)
1165{
1166 struct pxa168_eth_private *pep = netdev_priv(dev);
1167 eth_port_reset(dev);
1168
1169 /* Disable interrupts */
1170 wrl(pep, INT_MASK, 0);
1171 wrl(pep, INT_CAUSE, 0);
1172 /* Write to ICR to clear interrupts. */
1173 wrl(pep, INT_W_CLEAR, 0);
1174 napi_disable(&pep->napi);
1175 del_timer_sync(&pep->timeout);
1176 netif_carrier_off(dev);
1177 free_irq(dev->irq, dev);
1178 rxq_deinit(dev);
1179 txq_deinit(dev);
1180
1181 return 0;
1182}
1183
1184static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1185{
1186 int retval;
1187 struct pxa168_eth_private *pep = netdev_priv(dev);
1188
1189 if ((mtu > 9500) || (mtu < 68))
1190 return -EINVAL;
1191
1192 dev->mtu = mtu;
1193 retval = set_port_config_ext(pep);
1194
1195 if (!netif_running(dev))
1196 return 0;
1197
1198 /*
1199 * Stop and then re-open the interface. This will allocate RX
1200 * skbs of the new MTU.
1201 * There is a possible danger that the open will not succeed,
1202 * due to memory being full.
1203 */
1204 pxa168_eth_stop(dev);
1205 if (pxa168_eth_open(dev)) {
1206 dev_printk(KERN_ERR, &dev->dev,
1207 "fatal error on re-opening device after "
1208 "MTU change\n");
1209 }
1210
1211 return 0;
1212}
1213
1214static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1215{
1216 int tx_desc_curr;
1217
1218 tx_desc_curr = pep->tx_curr_desc_q;
1219 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1220 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1221 pep->tx_desc_count++;
1222
1223 return tx_desc_curr;
1224}
1225
1226static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1227{
1228 struct pxa168_eth_private *pep =
1229 container_of(napi, struct pxa168_eth_private, napi);
1230 struct net_device *dev = pep->dev;
1231 int work_done = 0;
1232
1233 if (unlikely(pep->work_todo & WORK_LINK)) {
1234 pep->work_todo &= ~(WORK_LINK);
1235 handle_link_event(pep);
1236 }
1237 /*
1238 * We call txq_reclaim every time since in NAPI interupts are disabled
1239 * and due to this we miss the TX_DONE interrupt,which is not updated in
1240 * interrupt status register.
1241 */
1242 txq_reclaim(dev, 0);
1243 if (netif_queue_stopped(dev)
1244 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1245 netif_wake_queue(dev);
1246 }
1247 work_done = rxq_process(dev, budget);
1248 if (work_done < budget) {
1249 napi_complete(napi);
1250 wrl(pep, INT_MASK, ALL_INTS);
1251 }
1252
1253 return work_done;
1254}
1255
1256static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1257{
1258 struct pxa168_eth_private *pep = netdev_priv(dev);
1259 struct net_device_stats *stats = &dev->stats;
1260 struct tx_desc *desc;
1261 int tx_index;
1262 int length;
1263
1264 tx_index = eth_alloc_tx_desc_index(pep);
1265 desc = &pep->p_tx_desc_area[tx_index];
1266 length = skb->len;
1267 pep->tx_skb[tx_index] = skb;
1268 desc->byte_cnt = length;
1269 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1f6e44a6
RC		 1270
1271 skb_tx_timestamp(skb);
1272
a49f37ee
SS		 1273 wmb();
1274 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1275 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1276 wmb();
1277 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1278
38442040 1279 stats->tx_bytes += length;
a49f37ee
SS		 1280 stats->tx_packets++;
1281 dev->trans_start = jiffies;
1282 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1283 /* We handled the current skb, but now we are out of space.*/
1284 netif_stop_queue(dev);
1285 }
1286
1287 return NETDEV_TX_OK;
1288}
1289
1290static int smi_wait_ready(struct pxa168_eth_private *pep)
1291{
1292 int i = 0;
1293
1294 /* wait for the SMI register to become available */
1295 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1296 if (i == PHY_WAIT_ITERATIONS)
1297 return -ETIMEDOUT;
1298 msleep(10);
1299 }
1300
1301 return 0;
1302}
1303
1304static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1305{
1306 struct pxa168_eth_private *pep = bus->priv;
1307 int i = 0;
1308 int val;
1309
1310 if (smi_wait_ready(pep)) {
1311 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1312 return -ETIMEDOUT;
1313 }
1314 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1315 /* now wait for the data to be valid */
1316 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1317 if (i == PHY_WAIT_ITERATIONS) {
1318 printk(KERN_WARNING
1319 "pxa168_eth: SMI bus read not valid\n");
1320 return -ENODEV;
1321 }
1322 msleep(10);
1323 }
1324
1325 return val & 0xffff;
1326}
1327
1328static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1329 u16 value)
1330{
1331 struct pxa168_eth_private *pep = bus->priv;
1332
1333 if (smi_wait_ready(pep)) {
1334 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1335 return -ETIMEDOUT;
1336 }
1337
1338 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1339 SMI_OP_W | (value & 0xffff));
1340
1341 if (smi_wait_ready(pep)) {
1342 printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n");
1343 return -ETIMEDOUT;
1344 }
1345
1346 return 0;
1347}
1348
1349static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1350 int cmd)
1351{
1352 struct pxa168_eth_private *pep = netdev_priv(dev);
1353 if (pep->phy != NULL)
4f2c8510 1354 return phy_mii_ioctl(pep->phy, ifr, cmd);
a49f37ee
SS		 1355
1356 return -EOPNOTSUPP;
1357}
1358
1359static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1360{
1361 struct mii_bus *bus = pep->smi_bus;
1362 struct phy_device *phydev;
1363 int start;
1364 int num;
1365 int i;
1366
1367 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1368 /* Scan entire range */
1369 start = ethernet_phy_get(pep);
1370 num = 32;
1371 } else {
1372 /* Use phy addr specific to platform */
1373 start = phy_addr & 0x1f;
1374 num = 1;
1375 }
1376 phydev = NULL;
1377 for (i = 0; i < num; i++) {
1378 int addr = (start + i) & 0x1f;
1379 if (bus->phy_map[addr] == NULL)
1380 mdiobus_scan(bus, addr);
1381
1382 if (phydev == NULL) {
1383 phydev = bus->phy_map[addr];
1384 if (phydev != NULL)
1385 ethernet_phy_set_addr(pep, addr);
1386 }
1387 }
1388
1389 return phydev;
1390}
1391
1392static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex)
1393{
1394 struct phy_device *phy = pep->phy;
1395 ethernet_phy_reset(pep);
1396
1397 phy_attach(pep->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_MII);
1398
1399 if (speed == 0) {
1400 phy->autoneg = AUTONEG_ENABLE;
1401 phy->speed = 0;
1402 phy->duplex = 0;
1403 phy->supported &= PHY_BASIC_FEATURES;
1404 phy->advertising = phy->supported | ADVERTISED_Autoneg;
1405 } else {
1406 phy->autoneg = AUTONEG_DISABLE;
1407 phy->advertising = 0;
1408 phy->speed = speed;
1409 phy->duplex = duplex;
1410 }
1411 phy_start_aneg(phy);
1412}
1413
1414static int ethernet_phy_setup(struct net_device *dev)
1415{
1416 struct pxa168_eth_private *pep = netdev_priv(dev);
1417
4169591f
DC		 1418 if (pep->pd->init)
1419 pep->pd->init();
a49f37ee
SS		 1420 pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f);
1421 if (pep->phy != NULL)
1422 phy_init(pep, pep->pd->speed, pep->pd->duplex);
1423 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1424
1425 return 0;
1426}
1427
1428static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1429{
1430 struct pxa168_eth_private *pep = netdev_priv(dev);
1431 int err;
1432
1433 err = phy_read_status(pep->phy);
1434 if (err == 0)
1435 err = phy_ethtool_gset(pep->phy, cmd);
1436
1437 return err;
1438}
1439
1440static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1441{
1442 struct pxa168_eth_private *pep = netdev_priv(dev);
1443
1444 return phy_ethtool_sset(pep->phy, cmd);
1445}
1446
1447static void pxa168_get_drvinfo(struct net_device *dev,
1448 struct ethtool_drvinfo *info)
1449{
1450 strncpy(info->driver, DRIVER_NAME, 32);
1451 strncpy(info->version, DRIVER_VERSION, 32);
1452 strncpy(info->fw_version, "N/A", 32);
1453 strncpy(info->bus_info, "N/A", 32);
1454}
1455
a49f37ee
SS		 1456static const struct ethtool_ops pxa168_ethtool_ops = {
1457 .get_settings = pxa168_get_settings,
1458 .set_settings = pxa168_set_settings,
1459 .get_drvinfo = pxa168_get_drvinfo,
ed4ba4b5 1460 .get_link = ethtool_op_get_link,
a49f37ee
SS		 1461};
1462
1463static const struct net_device_ops pxa168_eth_netdev_ops = {
1464 .ndo_open = pxa168_eth_open,
1465 .ndo_stop = pxa168_eth_stop,
1466 .ndo_start_xmit = pxa168_eth_start_xmit,
1467 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1468 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1469 .ndo_validate_addr = eth_validate_addr,
1470 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1471 .ndo_change_mtu = pxa168_eth_change_mtu,
1472 .ndo_tx_timeout = pxa168_eth_tx_timeout,
1473};
1474
1475static int pxa168_eth_probe(struct platform_device *pdev)
1476{
1477 struct pxa168_eth_private *pep = NULL;
1478 struct net_device *dev = NULL;
1479 struct resource *res;
1480 struct clk *clk;
1481 int err;
1482
1483 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1484
1485 clk = clk_get(&pdev->dev, "MFUCLK");
1486 if (IS_ERR(clk)) {
1487 printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n",
1488 DRIVER_NAME);
1489 return -ENODEV;
1490 }
1491 clk_enable(clk);
1492
1493 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1494 if (!dev) {
1495 err = -ENOMEM;
945c7c73 1496 goto err_clk;
a49f37ee
SS		 1497 }
1498
1499 platform_set_drvdata(pdev, dev);
1500 pep = netdev_priv(dev);
1501 pep->dev = dev;
1502 pep->clk = clk;
1503 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1504 if (res == NULL) {
1505 err = -ENODEV;
945c7c73 1506 goto err_netdev;
a49f37ee 1507 }
28f65c11 1508 pep->base = ioremap(res->start, resource_size(res));
a49f37ee
SS		 1509 if (pep->base == NULL) {
1510 err = -ENOMEM;
945c7c73 1511 goto err_netdev;
a49f37ee
SS		 1512 }
1513 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1514 BUG_ON(!res);
1515 dev->irq = res->start;
1516 dev->netdev_ops = &pxa168_eth_netdev_ops;
1517 dev->watchdog_timeo = 2 * HZ;
1518 dev->base_addr = 0;
1519 SET_ETHTOOL_OPS(dev, &pxa168_ethtool_ops);
1520
1521 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1522
1523 printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME);
7ce5d222 1524 eth_hw_addr_random(dev);
a49f37ee
SS		 1525
1526 pep->pd = pdev->dev.platform_data;
1527 pep->rx_ring_size = NUM_RX_DESCS;
1528 if (pep->pd->rx_queue_size)
1529 pep->rx_ring_size = pep->pd->rx_queue_size;
1530
1531 pep->tx_ring_size = NUM_TX_DESCS;
1532 if (pep->pd->tx_queue_size)
1533 pep->tx_ring_size = pep->pd->tx_queue_size;
1534
1535 pep->port_num = pep->pd->port_number;
1536 /* Hardware supports only 3 ports */
1537 BUG_ON(pep->port_num > 2);
1538 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1539
1540 memset(&pep->timeout, 0, sizeof(struct timer_list));
1541 init_timer(&pep->timeout);
1542 pep->timeout.function = rxq_refill_timer_wrapper;
1543 pep->timeout.data = (unsigned long)pep;
1544
1545 pep->smi_bus = mdiobus_alloc();
1546 if (pep->smi_bus == NULL) {
1547 err = -ENOMEM;
945c7c73 1548 goto err_base;
a49f37ee
SS		 1549 }
1550 pep->smi_bus->priv = pep;
1551 pep->smi_bus->name = "pxa168_eth smi";
1552 pep->smi_bus->read = pxa168_smi_read;
1553 pep->smi_bus->write = pxa168_smi_write;
d073a102
FF		 1554 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1555 pdev->name, pdev->id);
a49f37ee
SS		 1556 pep->smi_bus->parent = &pdev->dev;
1557 pep->smi_bus->phy_mask = 0xffffffff;
945c7c73
DC		 1558 err = mdiobus_register(pep->smi_bus);
1559 if (err)
1560 goto err_free_mdio;
1561
a49f37ee
SS		 1562 pxa168_init_hw(pep);
1563 err = ethernet_phy_setup(dev);
1564 if (err)
945c7c73 1565 goto err_mdiobus;
a49f37ee
SS		 1566 SET_NETDEV_DEV(dev, &pdev->dev);
1567 err = register_netdev(dev);
1568 if (err)
945c7c73 1569 goto err_mdiobus;
a49f37ee 1570 return 0;
945c7c73
DC		 1571
1572err_mdiobus:
1573 mdiobus_unregister(pep->smi_bus);
1574err_free_mdio:
1575 mdiobus_free(pep->smi_bus);
1576err_base:
1577 iounmap(pep->base);
1578err_netdev:
1579 free_netdev(dev);
1580err_clk:
1581 clk_disable(clk);
1582 clk_put(clk);
a49f37ee
SS		 1583 return err;
1584}
1585
1586static int pxa168_eth_remove(struct platform_device *pdev)
1587{
1588 struct net_device *dev = platform_get_drvdata(pdev);
1589 struct pxa168_eth_private *pep = netdev_priv(dev);
1590
1591 if (pep->htpr) {
1592 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1593 pep->htpr, pep->htpr_dma);
1594 pep->htpr = NULL;
1595 }
1596 if (pep->clk) {
1597 clk_disable(pep->clk);
1598 clk_put(pep->clk);
1599 pep->clk = NULL;
1600 }
1601 if (pep->phy != NULL)
1602 phy_detach(pep->phy);
1603
1604 iounmap(pep->base);
1605 pep->base = NULL;
9c01ae58
DK		 1606 mdiobus_unregister(pep->smi_bus);
1607 mdiobus_free(pep->smi_bus);
a49f37ee 1608 unregister_netdev(dev);
23f333a2 1609 cancel_work_sync(&pep->tx_timeout_task);
a49f37ee
SS		 1610 free_netdev(dev);
1611 platform_set_drvdata(pdev, NULL);
1612 return 0;
1613}
1614
1615static void pxa168_eth_shutdown(struct platform_device *pdev)
1616{
1617 struct net_device *dev = platform_get_drvdata(pdev);
1618 eth_port_reset(dev);
1619}
1620
1621#ifdef CONFIG_PM
1622static int pxa168_eth_resume(struct platform_device *pdev)
1623{
1624 return -ENOSYS;
1625}
1626
1627static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1628{
1629 return -ENOSYS;
1630}
1631
1632#else
1633#define pxa168_eth_resume NULL
1634#define pxa168_eth_suspend NULL
1635#endif
1636
1637static struct platform_driver pxa168_eth_driver = {
1638 .probe = pxa168_eth_probe,
1639 .remove = pxa168_eth_remove,
1640 .shutdown = pxa168_eth_shutdown,
1641 .resume = pxa168_eth_resume,
1642 .suspend = pxa168_eth_suspend,
1643 .driver = {
1644 .name = DRIVER_NAME,
1645 },
1646};
1647
db62f684 1648module_platform_driver(pxa168_eth_driver);
a49f37ee
SS		 1649
1650MODULE_LICENSE("GPL");
1651MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1652MODULE_ALIAS("platform:pxa168_eth");
kernel source for telekom puls (alcatel/mediatek)