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Merge tag 'for-linus-v3.10-rc3' of git://oss.sgi.com/xfs/xfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
3871c387
MS		 23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
24 *
1da177e4
LT		 25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 */
a779d38c 39
7542db8b
JP		 40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
1da177e4
LT		 42#include <linux/init.h>
43#include <linux/dma-mapping.h>
b6298c22 44#include <linux/in.h>
c3efab8e 45#include <linux/ip.h>
1da177e4
LT		 46#include <linux/tcp.h>
47#include <linux/udp.h>
48#include <linux/etherdevice.h>
1da177e4
LT		 49#include <linux/delay.h>
50#include <linux/ethtool.h>
d052d1be 51#include <linux/platform_device.h>
fbd6a754
LB		 52#include <linux/module.h>
53#include <linux/kernel.h>
54#include <linux/spinlock.h>
55#include <linux/workqueue.h>
ed94493f 56#include <linux/phy.h>
fbd6a754 57#include <linux/mv643xx_eth.h>
10a9948d 58#include <linux/io.h>
3619eb85 59#include <linux/interrupt.h>
10a9948d 60#include <linux/types.h>
5a0e3ad6 61#include <linux/slab.h>
452503eb 62#include <linux/clk.h>
fbd6a754 63
e5371493 64static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 65static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 66
fbd6a754 67
fbd6a754
LB		 68/*
69 * Registers shared between all ports.
70 */
3cb4667c 71#define PHY_ADDR 0x0000
3cb4667c
LB		 72#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
73#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
74#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
75#define WINDOW_BAR_ENABLE 0x0290
76#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 77
78/*
37a6084f
LB		 79 * Main per-port registers. These live at offset 0x0400 for
80 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 81 */
37a6084f 82#define PORT_CONFIG 0x0000
d9a073ea 83#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 84#define PORT_CONFIG_EXT 0x0004
85#define MAC_ADDR_LOW 0x0014
86#define MAC_ADDR_HIGH 0x0018
87#define SDMA_CONFIG 0x001c
becfad97
LB		 88#define TX_BURST_SIZE_16_64BIT 0x01000000
89#define TX_BURST_SIZE_4_64BIT 0x00800000
90#define BLM_TX_NO_SWAP 0x00000020
91#define BLM_RX_NO_SWAP 0x00000010
92#define RX_BURST_SIZE_16_64BIT 0x00000008
93#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 94#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 95#define SET_MII_SPEED_TO_100 0x01000000
96#define SET_GMII_SPEED_TO_1000 0x00800000
97#define SET_FULL_DUPLEX_MODE 0x00200000
98#define MAX_RX_PACKET_9700BYTE 0x000a0000
99#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
100#define DO_NOT_FORCE_LINK_FAIL 0x00000400
101#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
102#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
103#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
104#define FORCE_LINK_PASS 0x00000002
105#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 106#define PORT_STATUS 0x0044
a2a41689 107#define TX_FIFO_EMPTY 0x00000400
ae9ae064 108#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 109#define PORT_SPEED_MASK 0x00000030
110#define PORT_SPEED_1000 0x00000010
111#define PORT_SPEED_100 0x00000020
112#define PORT_SPEED_10 0x00000000
113#define FLOW_CONTROL_ENABLED 0x00000008
114#define FULL_DUPLEX 0x00000004
81600eea 115#define LINK_UP 0x00000002
37a6084f
LB		 116#define TXQ_COMMAND 0x0048
117#define TXQ_FIX_PRIO_CONF 0x004c
118#define TX_BW_RATE 0x0050
119#define TX_BW_MTU 0x0058
120#define TX_BW_BURST 0x005c
121#define INT_CAUSE 0x0060
226bb6b7 122#define INT_TX_END 0x07f80000
e0ca8410 123#define INT_TX_END_0 0x00080000
befefe21 124#define INT_RX 0x000003fc
e0ca8410 125#define INT_RX_0 0x00000004
073a345c 126#define INT_EXT 0x00000002
37a6084f 127#define INT_CAUSE_EXT 0x0064
befefe21
LB		 128#define INT_EXT_LINK_PHY 0x00110000
129#define INT_EXT_TX 0x000000ff
37a6084f
LB		 130#define INT_MASK 0x0068
131#define INT_MASK_EXT 0x006c
132#define TX_FIFO_URGENT_THRESHOLD 0x0074
302476c9
PZ		 133#define RX_DISCARD_FRAME_CNT 0x0084
134#define RX_OVERRUN_FRAME_CNT 0x0088
37a6084f
LB		 135#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
136#define TX_BW_RATE_MOVED 0x00e0
137#define TX_BW_MTU_MOVED 0x00e8
138#define TX_BW_BURST_MOVED 0x00ec
139#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
140#define RXQ_COMMAND 0x0280
141#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
142#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
143#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
144#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
145
146/*
147 * Misc per-port registers.
148 */
3cb4667c
LB		 149#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
150#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
151#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
152#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 153
2679a550
LB		 154
155/*
becfad97 156 * SDMA configuration register default value.
2679a550 157 */
fbd6a754
LB		 158#if defined(__BIG_ENDIAN)
159#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 160 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 162#elif defined(__LITTLE_ENDIAN)
163#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 164 (RX_BURST_SIZE_4_64BIT | \
165 BLM_RX_NO_SWAP | \
166 BLM_TX_NO_SWAP | \
167 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 168#else
169#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
170#endif
171
2beff77b
LB		 172
173/*
becfad97 174 * Misc definitions.
2beff77b 175 */
becfad97
LB		 176#define DEFAULT_RX_QUEUE_SIZE 128
177#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 178#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 179
fbd6a754 180
7ca72a3b
LB		 181/*
182 * RX/TX descriptors.
fbd6a754
LB		 183 */
184#if defined(__BIG_ENDIAN)
cc9754b3 185struct rx_desc {
fbd6a754
LB		 186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191};
192
cc9754b3 193struct tx_desc {
fbd6a754
LB		 194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199};
200#elif defined(__LITTLE_ENDIAN)
cc9754b3 201struct rx_desc {
fbd6a754
LB		 202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
207};
208
cc9754b3 209struct tx_desc {
fbd6a754
LB		 210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
215};
216#else
217#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218#endif
219
7ca72a3b 220/* RX & TX descriptor command */
cc9754b3 221#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 222
223/* RX & TX descriptor status */
cc9754b3 224#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 225
226/* RX descriptor status */
cc9754b3
LB		 227#define LAYER_4_CHECKSUM_OK 0x40000000
228#define RX_ENABLE_INTERRUPT 0x20000000
229#define RX_FIRST_DESC 0x08000000
230#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 231#define RX_IP_HDR_OK 0x02000000
232#define RX_PKT_IS_IPV4 0x01000000
233#define RX_PKT_IS_ETHERNETV2 0x00800000
234#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 237
238/* TX descriptor command */
cc9754b3
LB		 239#define TX_ENABLE_INTERRUPT 0x00800000
240#define GEN_CRC 0x00400000
241#define TX_FIRST_DESC 0x00200000
242#define TX_LAST_DESC 0x00100000
243#define ZERO_PADDING 0x00080000
244#define GEN_IP_V4_CHECKSUM 0x00040000
245#define GEN_TCP_UDP_CHECKSUM 0x00020000
246#define UDP_FRAME 0x00010000
e32b6617
LB		 247#define MAC_HDR_EXTRA_4_BYTES 0x00008000
248#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 249
cc9754b3 250#define TX_IHL_SHIFT 11
7ca72a3b
LB		 251
252
c9df406f 253/* global *******************************************************************/
e5371493 254struct mv643xx_eth_shared_private {
fc32b0e2
LB		 255 /*
256 * Ethernet controller base address.
257 */
cc9754b3 258 void __iomem *base;
c9df406f 259
fc32b0e2
LB		 260 /*
261 * Per-port MBUS window access register value.
262 */
c9df406f
LB		 263 u32 win_protect;
264
fc32b0e2
LB		 265 /*
266 * Hardware-specific parameters.
267 */
773fc3ee 268 int extended_rx_coal_limit;
457b1d5a 269 int tx_bw_control;
9b2c2ff7 270 int tx_csum_limit;
20922486 271 struct clk *clk;
c9df406f
LB		 272};
273
457b1d5a
LB		 274#define TX_BW_CONTROL_ABSENT 0
275#define TX_BW_CONTROL_OLD_LAYOUT 1
276#define TX_BW_CONTROL_NEW_LAYOUT 2
277
e7d2f4db
LB		 278static int mv643xx_eth_open(struct net_device *dev);
279static int mv643xx_eth_stop(struct net_device *dev);
280
c9df406f
LB		 281
282/* per-port *****************************************************************/
e5371493 283struct mib_counters {
fbd6a754
LB		 284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
303 u32 fc_sent;
304 u32 good_fc_received;
305 u32 bad_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
309 u32 jabber_received;
310 u32 mac_receive_error;
311 u32 bad_crc_event;
312 u32 collision;
313 u32 late_collision;
302476c9
PZ		 314 /* Non MIB hardware counters */
315 u32 rx_discard;
316 u32 rx_overrun;
fbd6a754
LB		 317};
318
8a578111 319struct rx_queue {
64da80a2
LB		 320 int index;
321
8a578111
LB		 322 int rx_ring_size;
323
324 int rx_desc_count;
325 int rx_curr_desc;
326 int rx_used_desc;
327
328 struct rx_desc *rx_desc_area;
329 dma_addr_t rx_desc_dma;
330 int rx_desc_area_size;
331 struct sk_buff **rx_skb;
8a578111
LB		 332};
333
13d64285 334struct tx_queue {
3d6b35bc
LB		 335 int index;
336
13d64285 337 int tx_ring_size;
fbd6a754 338
13d64285
LB		 339 int tx_desc_count;
340 int tx_curr_desc;
341 int tx_used_desc;
fbd6a754 342
5daffe94 343 struct tx_desc *tx_desc_area;
fbd6a754
LB		 344 dma_addr_t tx_desc_dma;
345 int tx_desc_area_size;
99ab08e0
LB		 346
347 struct sk_buff_head tx_skb;
8fd89211
LB		 348
349 unsigned long tx_packets;
350 unsigned long tx_bytes;
351 unsigned long tx_dropped;
13d64285
LB		 352};
353
354struct mv643xx_eth_private {
355 struct mv643xx_eth_shared_private *shared;
37a6084f 356 void __iomem *base;
fc32b0e2 357 int port_num;
13d64285 358
fc32b0e2 359 struct net_device *dev;
fbd6a754 360
ed94493f 361 struct phy_device *phy;
fbd6a754 362
4ff3495a
LB		 363 struct timer_list mib_counters_timer;
364 spinlock_t mib_counters_lock;
fc32b0e2 365 struct mib_counters mib_counters;
4ff3495a 366
fc32b0e2 367 struct work_struct tx_timeout_task;
8a578111 368
1fa38c58 369 struct napi_struct napi;
e0ca8410 370 u32 int_mask;
1319ebad 371 u8 oom;
1fa38c58
LB		 372 u8 work_link;
373 u8 work_tx;
374 u8 work_tx_end;
375 u8 work_rx;
376 u8 work_rx_refill;
1fa38c58 377
2bcb4b0f 378 int skb_size;
2bcb4b0f 379
8a578111
LB		 380 /*
381 * RX state.
382 */
e7d2f4db 383 int rx_ring_size;
8a578111
LB		 384 unsigned long rx_desc_sram_addr;
385 int rx_desc_sram_size;
f7981c1c 386 int rxq_count;
2257e05c 387 struct timer_list rx_oom;
64da80a2 388 struct rx_queue rxq[8];
13d64285
LB		 389
390 /*
391 * TX state.
392 */
e7d2f4db 393 int tx_ring_size;
13d64285
LB		 394 unsigned long tx_desc_sram_addr;
395 int tx_desc_sram_size;
f7981c1c 396 int txq_count;
3d6b35bc 397 struct tx_queue txq[8];
452503eb
AL		 398
399 /*
400 * Hardware-specific parameters.
401 */
402 struct clk *clk;
403 unsigned int t_clk;
fbd6a754 404};
1da177e4 405
fbd6a754 406
c9df406f 407/* port register accessors **************************************************/
e5371493 408static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 409{
cc9754b3 410 return readl(mp->shared->base + offset);
c9df406f 411}
fbd6a754 412
37a6084f
LB		 413static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
414{
415 return readl(mp->base + offset);
416}
417
e5371493 418static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 419{
cc9754b3 420 writel(data, mp->shared->base + offset);
c9df406f 421}
fbd6a754 422
37a6084f
LB		 423static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
424{
425 writel(data, mp->base + offset);
426}
427
fbd6a754 428
c9df406f 429/* rxq/txq helper functions *************************************************/
8a578111 430static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 431{
64da80a2 432 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 433}
fbd6a754 434
13d64285
LB		 435static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
436{
3d6b35bc 437 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 438}
439
8a578111 440static void rxq_enable(struct rx_queue *rxq)
c9df406f 441{
8a578111 442 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 443 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 444}
1da177e4 445
8a578111
LB		 446static void rxq_disable(struct rx_queue *rxq)
447{
448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 449 u8 mask = 1 << rxq->index;
1da177e4 450
37a6084f
LB		 451 wrlp(mp, RXQ_COMMAND, mask << 8);
452 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 453 udelay(10);
c9df406f
LB		 454}
455
6b368f68
LB		 456static void txq_reset_hw_ptr(struct tx_queue *txq)
457{
458 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 459 u32 addr;
460
461 addr = (u32)txq->tx_desc_dma;
462 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 463 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 464}
465
13d64285 466static void txq_enable(struct tx_queue *txq)
1da177e4 467{
13d64285 468 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 469 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 470}
471
13d64285 472static void txq_disable(struct tx_queue *txq)
1da177e4 473{
13d64285 474 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 475 u8 mask = 1 << txq->index;
c9df406f 476
37a6084f
LB		 477 wrlp(mp, TXQ_COMMAND, mask << 8);
478 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 479 udelay(10);
480}
481
1fa38c58 482static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 483{
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 485 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 486
8fd89211
LB		 487 if (netif_tx_queue_stopped(nq)) {
488 __netif_tx_lock(nq, smp_processor_id());
489 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
490 netif_tx_wake_queue(nq);
491 __netif_tx_unlock(nq);
492 }
1da177e4
LT		 493}
494
8a578111 495static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 496{
8a578111
LB		 497 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
498 struct net_device_stats *stats = &mp->dev->stats;
499 int rx;
1da177e4 500
8a578111 501 rx = 0;
9e1f3772 502 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 503 struct rx_desc *rx_desc;
96587661 504 unsigned int cmd_sts;
fc32b0e2 505 struct sk_buff *skb;
6b8f90c2 506 u16 byte_cnt;
ff561eef 507
8a578111 508 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 509
96587661 510 cmd_sts = rx_desc->cmd_sts;
2257e05c 511 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 512 break;
96587661 513 rmb();
1da177e4 514
8a578111
LB		 515 skb = rxq->rx_skb[rxq->rx_curr_desc];
516 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 517
9da78745
LB		 518 rxq->rx_curr_desc++;
519 if (rxq->rx_curr_desc == rxq->rx_ring_size)
520 rxq->rx_curr_desc = 0;
ff561eef 521
eb0519b5 522 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 523 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 524 rxq->rx_desc_count--;
525 rx++;
b1dd9ca1 526
1fa38c58
LB		 527 mp->work_rx_refill |= 1 << rxq->index;
528
6b8f90c2
LB		 529 byte_cnt = rx_desc->byte_cnt;
530
468d09f8
DF		 531 /*
532 * Update statistics.
fc32b0e2
LB		 533 *
534 * Note that the descriptor byte count includes 2 dummy
535 * bytes automatically inserted by the hardware at the
536 * start of the packet (which we don't count), and a 4
537 * byte CRC at the end of the packet (which we do count).
468d09f8 538 */
1da177e4 539 stats->rx_packets++;
6b8f90c2 540 stats->rx_bytes += byte_cnt - 2;
96587661 541
1da177e4 542 /*
fc32b0e2
LB		 543 * In case we received a packet without first / last bits
544 * on, or the error summary bit is set, the packet needs
545 * to be dropped.
1da177e4 546 */
f61e5547
LB		 547 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
548 != (RX_FIRST_DESC | RX_LAST_DESC))
549 goto err;
550
551 /*
552 * The -4 is for the CRC in the trailer of the
553 * received packet
554 */
555 skb_put(skb, byte_cnt - 2 - 4);
556
557 if (cmd_sts & LAYER_4_CHECKSUM_OK)
558 skb->ip_summed = CHECKSUM_UNNECESSARY;
559 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 560
3619eb85 561 napi_gro_receive(&mp->napi, skb);
f61e5547
LB		 562
563 continue;
564
565err:
566 stats->rx_dropped++;
567
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC)) {
570 if (net_ratelimit())
7542db8b
JP		 571 netdev_err(mp->dev,
572 "received packet spanning multiple descriptors\n");
1da177e4 573 }
f61e5547
LB		 574
575 if (cmd_sts & ERROR_SUMMARY)
576 stats->rx_errors++;
577
578 dev_kfree_skb(skb);
1da177e4 579 }
fc32b0e2 580
1fa38c58
LB		 581 if (rx < budget)
582 mp->work_rx &= ~(1 << rxq->index);
583
8a578111 584 return rx;
1da177e4
LT		 585}
586
1fa38c58 587static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 588{
1fa38c58 589 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 590 int refilled;
8a578111 591
1fa38c58
LB		 592 refilled = 0;
593 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
594 struct sk_buff *skb;
1fa38c58 595 int rx;
53771522 596 struct rx_desc *rx_desc;
530e557a 597 int size;
d0412d96 598
acb600de 599 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
2bcb4b0f 600
1fa38c58 601 if (skb == NULL) {
1319ebad 602 mp->oom = 1;
1fa38c58
LB		 603 goto oom;
604 }
d0412d96 605
7fd96ce4
LB		 606 if (SKB_DMA_REALIGN)
607 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 608
1fa38c58
LB		 609 refilled++;
610 rxq->rx_desc_count++;
c9df406f 611
1fa38c58
LB		 612 rx = rxq->rx_used_desc++;
613 if (rxq->rx_used_desc == rxq->rx_ring_size)
614 rxq->rx_used_desc = 0;
2257e05c 615
53771522
LB		 616 rx_desc = rxq->rx_desc_area + rx;
617
530e557a 618 size = skb->end - skb->data;
eb0519b5 619 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 620 skb->data, size,
eb0519b5 621 DMA_FROM_DEVICE);
530e557a 622 rx_desc->buf_size = size;
1fa38c58
LB		 623 rxq->rx_skb[rx] = skb;
624 wmb();
53771522 625 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 626 wmb();
2257e05c 627
1fa38c58
LB		 628 /*
629 * The hardware automatically prepends 2 bytes of
630 * dummy data to each received packet, so that the
631 * IP header ends up 16-byte aligned.
632 */
633 skb_reserve(skb, 2);
634 }
635
636 if (refilled < budget)
637 mp->work_rx_refill &= ~(1 << rxq->index);
638
639oom:
640 return refilled;
d0412d96
JC		 641}
642
c9df406f
LB		 643
644/* tx ***********************************************************************/
c9df406f 645static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 646{
13d64285 647 int frag;
1da177e4 648
c9df406f 649 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
9e903e08
ED		 650 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
651
652 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
c9df406f 653 return 1;
1da177e4 654 }
13d64285 655
c9df406f
LB		 656 return 0;
657}
7303fde8 658
13d64285 659static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 660{
eb0519b5 661 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 662 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 663 int frag;
1da177e4 664
13d64285
LB		 665 for (frag = 0; frag < nr_frags; frag++) {
666 skb_frag_t *this_frag;
667 int tx_index;
668 struct tx_desc *desc;
669
670 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 671 tx_index = txq->tx_curr_desc++;
672 if (txq->tx_curr_desc == txq->tx_ring_size)
673 txq->tx_curr_desc = 0;
13d64285
LB		 674 desc = &txq->tx_desc_area[tx_index];
675
676 /*
677 * The last fragment will generate an interrupt
678 * which will free the skb on TX completion.
679 */
680 if (frag == nr_frags - 1) {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
682 ZERO_PADDING | TX_LAST_DESC |
683 TX_ENABLE_INTERRUPT;
13d64285
LB		 684 } else {
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 686 }
687
c9df406f 688 desc->l4i_chk = 0;
9e903e08 689 desc->byte_cnt = skb_frag_size(this_frag);
f106358b
IC		 690 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
691 this_frag, 0,
9e903e08 692 skb_frag_size(this_frag),
f106358b 693 DMA_TO_DEVICE);
c9df406f 694 }
1da177e4
LT		 695}
696
c9df406f
LB		 697static inline __be16 sum16_as_be(__sum16 sum)
698{
699 return (__force __be16)sum;
700}
1da177e4 701
4df89bd5 702static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 703{
8fa89bf5 704 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 705 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 706 int tx_index;
cc9754b3 707 struct tx_desc *desc;
c9df406f 708 u32 cmd_sts;
4df89bd5 709 u16 l4i_chk;
c9df406f 710 int length;
1da177e4 711
cc9754b3 712 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 713 l4i_chk = 0;
c9df406f
LB		 714
715 if (skb->ip_summed == CHECKSUM_PARTIAL) {
9b2c2ff7 716 int hdr_len;
4df89bd5 717 int tag_bytes;
e32b6617
LB		 718
719 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
720 skb->protocol != htons(ETH_P_8021Q));
c9df406f 721
9b2c2ff7
SB		 722 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
723 tag_bytes = hdr_len - ETH_HLEN;
724 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
725 unlikely(tag_bytes & ~12)) {
4df89bd5
LB		 726 if (skb_checksum_help(skb) == 0)
727 goto no_csum;
728 kfree_skb(skb);
729 return 1;
730 }
c9df406f 731
4df89bd5 732 if (tag_bytes & 4)
e32b6617 733 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 734 if (tag_bytes & 8)
e32b6617 735 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 736
737 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
738 GEN_IP_V4_CHECKSUM |
739 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 740
c9df406f
LB		 741 switch (ip_hdr(skb)->protocol) {
742 case IPPROTO_UDP:
cc9754b3 743 cmd_sts |= UDP_FRAME;
4df89bd5 744 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 745 break;
746 case IPPROTO_TCP:
4df89bd5 747 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 748 break;
749 default:
750 BUG();
751 }
752 } else {
4df89bd5 753no_csum:
c9df406f 754 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 755 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 756 }
757
66823b92
LB		 758 tx_index = txq->tx_curr_desc++;
759 if (txq->tx_curr_desc == txq->tx_ring_size)
760 txq->tx_curr_desc = 0;
4df89bd5
LB		 761 desc = &txq->tx_desc_area[tx_index];
762
763 if (nr_frags) {
764 txq_submit_frag_skb(txq, skb);
765 length = skb_headlen(skb);
766 } else {
767 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
768 length = skb->len;
769 }
770
771 desc->l4i_chk = l4i_chk;
772 desc->byte_cnt = length;
eb0519b5
GP		 773 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
774 length, DMA_TO_DEVICE);
4df89bd5 775
99ab08e0
LB		 776 __skb_queue_tail(&txq->tx_skb, skb);
777
3b182d7d
RC		 778 skb_tx_timestamp(skb);
779
c9df406f
LB		 780 /* ensure all other descriptors are written before first cmd_sts */
781 wmb();
782 desc->cmd_sts = cmd_sts;
783
1fa38c58
LB		 784 /* clear TX_END status */
785 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 786
c9df406f
LB		 787 /* ensure all descriptors are written before poking hardware */
788 wmb();
13d64285 789 txq_enable(txq);
c9df406f 790
13d64285 791 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 792
793 return 0;
1da177e4 794}
1da177e4 795
0ccfe64d 796static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 797{
e5371493 798 struct mv643xx_eth_private *mp = netdev_priv(dev);
73151ce3 799 int length, queue;
13d64285 800 struct tx_queue *txq;
e5ef1de1 801 struct netdev_queue *nq;
afdb57a2 802
8fd89211
LB		 803 queue = skb_get_queue_mapping(skb);
804 txq = mp->txq + queue;
805 nq = netdev_get_tx_queue(dev, queue);
806
c9df406f 807 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 808 txq->tx_dropped++;
7542db8b
JP		 809 netdev_printk(KERN_DEBUG, dev,
810 "failed to linearize skb with tiny unaligned fragment\n");
c9df406f
LB		 811 return NETDEV_TX_BUSY;
812 }
813
17cd0a59 814 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1 815 if (net_ratelimit())
7542db8b 816 netdev_err(dev, "tx queue full?!\n");
3d6b35bc
LB		 817 kfree_skb(skb);
818 return NETDEV_TX_OK;
c9df406f
LB		 819 }
820
73151ce3
RC		 821 length = skb->len;
822
4df89bd5
LB		 823 if (!txq_submit_skb(txq, skb)) {
824 int entries_left;
825
73151ce3 826 txq->tx_bytes += length;
4df89bd5 827 txq->tx_packets++;
c9df406f 828
4df89bd5
LB		 829 entries_left = txq->tx_ring_size - txq->tx_desc_count;
830 if (entries_left < MAX_SKB_FRAGS + 1)
831 netif_tx_stop_queue(nq);
832 }
c9df406f 833
c9df406f 834 return NETDEV_TX_OK;
1da177e4
LT		 835}
836
c9df406f 837
1fa38c58
LB		 838/* tx napi ******************************************************************/
839static void txq_kick(struct tx_queue *txq)
840{
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 842 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 843 u32 hw_desc_ptr;
844 u32 expected_ptr;
845
8fd89211 846 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 847
37a6084f 848 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 849 goto out;
850
37a6084f 851 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 852 expected_ptr = (u32)txq->tx_desc_dma +
853 txq->tx_curr_desc * sizeof(struct tx_desc);
854
855 if (hw_desc_ptr != expected_ptr)
856 txq_enable(txq);
857
858out:
8fd89211 859 __netif_tx_unlock(nq);
1fa38c58
LB		 860
861 mp->work_tx_end &= ~(1 << txq->index);
862}
863
864static int txq_reclaim(struct tx_queue *txq, int budget, int force)
865{
866 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 867 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 868 int reclaimed;
869
3aefe2b4 870 __netif_tx_lock_bh(nq);
1fa38c58
LB		 871
872 reclaimed = 0;
873 while (reclaimed < budget && txq->tx_desc_count > 0) {
874 int tx_index;
875 struct tx_desc *desc;
876 u32 cmd_sts;
877 struct sk_buff *skb;
1fa38c58
LB		 878
879 tx_index = txq->tx_used_desc;
880 desc = &txq->tx_desc_area[tx_index];
881 cmd_sts = desc->cmd_sts;
882
883 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
884 if (!force)
885 break;
886 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
887 }
888
889 txq->tx_used_desc = tx_index + 1;
890 if (txq->tx_used_desc == txq->tx_ring_size)
891 txq->tx_used_desc = 0;
892
893 reclaimed++;
894 txq->tx_desc_count--;
895
99ab08e0
LB		 896 skb = NULL;
897 if (cmd_sts & TX_LAST_DESC)
898 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 899
900 if (cmd_sts & ERROR_SUMMARY) {
7542db8b 901 netdev_info(mp->dev, "tx error\n");
1fa38c58
LB		 902 mp->dev->stats.tx_errors++;
903 }
904
a418950c 905 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 906 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 907 desc->byte_cnt, DMA_TO_DEVICE);
908 } else {
eb0519b5 909 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 910 desc->byte_cnt, DMA_TO_DEVICE);
911 }
1fa38c58 912
acb600de 913 dev_kfree_skb(skb);
1fa38c58
LB		 914 }
915
3aefe2b4 916 __netif_tx_unlock_bh(nq);
8fd89211 917
1fa38c58
LB		 918 if (reclaimed < budget)
919 mp->work_tx &= ~(1 << txq->index);
920
1fa38c58
LB		 921 return reclaimed;
922}
923
924
89df5fdc
LB		 925/* tx rate control **********************************************************/
926/*
927 * Set total maximum TX rate (shared by all TX queues for this port)
928 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
929 */
930static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
931{
932 int token_rate;
933 int mtu;
934 int bucket_size;
935
452503eb 936 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 937 if (token_rate > 1023)
938 token_rate = 1023;
939
940 mtu = (mp->dev->mtu + 255) >> 8;
941 if (mtu > 63)
942 mtu = 63;
943
944 bucket_size = (burst + 255) >> 8;
945 if (bucket_size > 65535)
946 bucket_size = 65535;
947
457b1d5a
LB		 948 switch (mp->shared->tx_bw_control) {
949 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 950 wrlp(mp, TX_BW_RATE, token_rate);
951 wrlp(mp, TX_BW_MTU, mtu);
952 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 953 break;
954 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 955 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
956 wrlp(mp, TX_BW_MTU_MOVED, mtu);
957 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 958 break;
1e881592 959 }
89df5fdc
LB		 960}
961
962static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
963{
964 struct mv643xx_eth_private *mp = txq_to_mp(txq);
965 int token_rate;
966 int bucket_size;
967
452503eb 968 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 969 if (token_rate > 1023)
970 token_rate = 1023;
971
972 bucket_size = (burst + 255) >> 8;
973 if (bucket_size > 65535)
974 bucket_size = 65535;
975
37a6084f
LB		 976 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
977 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 978}
979
980static void txq_set_fixed_prio_mode(struct tx_queue *txq)
981{
982 struct mv643xx_eth_private *mp = txq_to_mp(txq);
983 int off;
984 u32 val;
985
986 /*
987 * Turn on fixed priority mode.
988 */
457b1d5a
LB		 989 off = 0;
990 switch (mp->shared->tx_bw_control) {
991 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 992 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 993 break;
994 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 995 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 996 break;
997 }
89df5fdc 998
457b1d5a 999 if (off) {
37a6084f 1000 val = rdlp(mp, off);
457b1d5a 1001 val |= 1 << txq->index;
37a6084f 1002 wrlp(mp, off, val);
457b1d5a 1003 }
89df5fdc
LB		 1004}
1005
89df5fdc 1006
c9df406f 1007/* mii management interface *************************************************/
260055bb
PS		 1008static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1009{
1010 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1011 u32 autoneg_disable = FORCE_LINK_PASS |
1012 DISABLE_AUTO_NEG_SPEED_GMII |
1013 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1014 DISABLE_AUTO_NEG_FOR_DUPLEX;
1015
1016 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1017 /* enable auto negotiation */
1018 pscr &= ~autoneg_disable;
1019 goto out_write;
1020 }
1021
1022 pscr |= autoneg_disable;
1023
1024 if (mp->phy->speed == SPEED_1000) {
1025 /* force gigabit, half duplex not supported */
1026 pscr |= SET_GMII_SPEED_TO_1000;
1027 pscr |= SET_FULL_DUPLEX_MODE;
1028 goto out_write;
1029 }
1030
1031 pscr &= ~SET_GMII_SPEED_TO_1000;
1032
1033 if (mp->phy->speed == SPEED_100)
1034 pscr |= SET_MII_SPEED_TO_100;
1035 else
1036 pscr &= ~SET_MII_SPEED_TO_100;
1037
1038 if (mp->phy->duplex == DUPLEX_FULL)
1039 pscr |= SET_FULL_DUPLEX_MODE;
1040 else
1041 pscr &= ~SET_FULL_DUPLEX_MODE;
1042
1043out_write:
1044 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1045}
1046
8fd89211
LB		 1047/* statistics ***************************************************************/
1048static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1049{
1050 struct mv643xx_eth_private *mp = netdev_priv(dev);
1051 struct net_device_stats *stats = &dev->stats;
1052 unsigned long tx_packets = 0;
1053 unsigned long tx_bytes = 0;
1054 unsigned long tx_dropped = 0;
1055 int i;
1056
1057 for (i = 0; i < mp->txq_count; i++) {
1058 struct tx_queue *txq = mp->txq + i;
1059
1060 tx_packets += txq->tx_packets;
1061 tx_bytes += txq->tx_bytes;
1062 tx_dropped += txq->tx_dropped;
1063 }
1064
1065 stats->tx_packets = tx_packets;
1066 stats->tx_bytes = tx_bytes;
1067 stats->tx_dropped = tx_dropped;
1068
1069 return stats;
1070}
1071
fc32b0e2 1072static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1073{
fc32b0e2 1074 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1075}
1076
fc32b0e2 1077static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1078{
fc32b0e2
LB		 1079 int i;
1080
1081 for (i = 0; i < 0x80; i += 4)
1082 mib_read(mp, i);
302476c9
PZ		 1083
1084 /* Clear non MIB hw counters also */
1085 rdlp(mp, RX_DISCARD_FRAME_CNT);
1086 rdlp(mp, RX_OVERRUN_FRAME_CNT);
c9df406f 1087}
d0412d96 1088
fc32b0e2 1089static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1090{
e5371493 1091 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1092
57e8f26a 1093 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1094 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1095 p->bad_octets_received += mib_read(mp, 0x08);
1096 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1097 p->good_frames_received += mib_read(mp, 0x10);
1098 p->bad_frames_received += mib_read(mp, 0x14);
1099 p->broadcast_frames_received += mib_read(mp, 0x18);
1100 p->multicast_frames_received += mib_read(mp, 0x1c);
1101 p->frames_64_octets += mib_read(mp, 0x20);
1102 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1103 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1104 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1105 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1106 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1107 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1108 p->good_frames_sent += mib_read(mp, 0x40);
1109 p->excessive_collision += mib_read(mp, 0x44);
1110 p->multicast_frames_sent += mib_read(mp, 0x48);
1111 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1112 p->unrec_mac_control_received += mib_read(mp, 0x50);
1113 p->fc_sent += mib_read(mp, 0x54);
1114 p->good_fc_received += mib_read(mp, 0x58);
1115 p->bad_fc_received += mib_read(mp, 0x5c);
1116 p->undersize_received += mib_read(mp, 0x60);
1117 p->fragments_received += mib_read(mp, 0x64);
1118 p->oversize_received += mib_read(mp, 0x68);
1119 p->jabber_received += mib_read(mp, 0x6c);
1120 p->mac_receive_error += mib_read(mp, 0x70);
1121 p->bad_crc_event += mib_read(mp, 0x74);
1122 p->collision += mib_read(mp, 0x78);
1123 p->late_collision += mib_read(mp, 0x7c);
302476c9
PZ		 1124 /* Non MIB hardware counters */
1125 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1126 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
57e8f26a 1127 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1128
1129 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1130}
1131
1132static void mib_counters_timer_wrapper(unsigned long _mp)
1133{
1134 struct mv643xx_eth_private *mp = (void *)_mp;
1135
1136 mib_counters_update(mp);
d0412d96
JC		 1137}
1138
c9df406f 1139
3e508034
LB		 1140/* interrupt coalescing *****************************************************/
1141/*
1142 * Hardware coalescing parameters are set in units of 64 t_clk
1143 * cycles. I.e.:
1144 *
1145 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1146 *
1147 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1148 *
1149 * In the ->set*() methods, we round the computed register value
1150 * to the nearest integer.
1151 */
1152static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1153{
1154 u32 val = rdlp(mp, SDMA_CONFIG);
1155 u64 temp;
1156
1157 if (mp->shared->extended_rx_coal_limit)
1158 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1159 else
1160 temp = (val & 0x003fff00) >> 8;
1161
1162 temp *= 64000000;
452503eb 1163 do_div(temp, mp->t_clk);
3e508034
LB		 1164
1165 return (unsigned int)temp;
1166}
1167
1168static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1169{
1170 u64 temp;
1171 u32 val;
1172
452503eb 1173 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1174 temp += 31999999;
1175 do_div(temp, 64000000);
1176
1177 val = rdlp(mp, SDMA_CONFIG);
1178 if (mp->shared->extended_rx_coal_limit) {
1179 if (temp > 0xffff)
1180 temp = 0xffff;
1181 val &= ~0x023fff80;
1182 val |= (temp & 0x8000) << 10;
1183 val |= (temp & 0x7fff) << 7;
1184 } else {
1185 if (temp > 0x3fff)
1186 temp = 0x3fff;
1187 val &= ~0x003fff00;
1188 val |= (temp & 0x3fff) << 8;
1189 }
1190 wrlp(mp, SDMA_CONFIG, val);
1191}
1192
1193static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1194{
1195 u64 temp;
1196
1197 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1198 temp *= 64000000;
452503eb 1199 do_div(temp, mp->t_clk);
3e508034
LB		 1200
1201 return (unsigned int)temp;
1202}
1203
1204static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1205{
1206 u64 temp;
1207
452503eb 1208 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1209 temp += 31999999;
1210 do_div(temp, 64000000);
1211
1212 if (temp > 0x3fff)
1213 temp = 0x3fff;
1214
1215 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1216}
1217
1218
c9df406f 1219/* ethtool ******************************************************************/
e5371493 1220struct mv643xx_eth_stats {
c9df406f
LB		 1221 char stat_string[ETH_GSTRING_LEN];
1222 int sizeof_stat;
16820054
LB		 1223 int netdev_off;
1224 int mp_off;
c9df406f
LB		 1225};
1226
16820054
LB		 1227#define SSTAT(m) \
1228 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1229 offsetof(struct net_device, stats.m), -1 }
1230
1231#define MIBSTAT(m) \
1232 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1233 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1234
1235static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1236 SSTAT(rx_packets),
1237 SSTAT(tx_packets),
1238 SSTAT(rx_bytes),
1239 SSTAT(tx_bytes),
1240 SSTAT(rx_errors),
1241 SSTAT(tx_errors),
1242 SSTAT(rx_dropped),
1243 SSTAT(tx_dropped),
1244 MIBSTAT(good_octets_received),
1245 MIBSTAT(bad_octets_received),
1246 MIBSTAT(internal_mac_transmit_err),
1247 MIBSTAT(good_frames_received),
1248 MIBSTAT(bad_frames_received),
1249 MIBSTAT(broadcast_frames_received),
1250 MIBSTAT(multicast_frames_received),
1251 MIBSTAT(frames_64_octets),
1252 MIBSTAT(frames_65_to_127_octets),
1253 MIBSTAT(frames_128_to_255_octets),
1254 MIBSTAT(frames_256_to_511_octets),
1255 MIBSTAT(frames_512_to_1023_octets),
1256 MIBSTAT(frames_1024_to_max_octets),
1257 MIBSTAT(good_octets_sent),
1258 MIBSTAT(good_frames_sent),
1259 MIBSTAT(excessive_collision),
1260 MIBSTAT(multicast_frames_sent),
1261 MIBSTAT(broadcast_frames_sent),
1262 MIBSTAT(unrec_mac_control_received),
1263 MIBSTAT(fc_sent),
1264 MIBSTAT(good_fc_received),
1265 MIBSTAT(bad_fc_received),
1266 MIBSTAT(undersize_received),
1267 MIBSTAT(fragments_received),
1268 MIBSTAT(oversize_received),
1269 MIBSTAT(jabber_received),
1270 MIBSTAT(mac_receive_error),
1271 MIBSTAT(bad_crc_event),
1272 MIBSTAT(collision),
1273 MIBSTAT(late_collision),
302476c9
PZ		 1274 MIBSTAT(rx_discard),
1275 MIBSTAT(rx_overrun),
c9df406f
LB		 1276};
1277
10a9948d 1278static int
6bdf576e
LB		 1279mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1280 struct ethtool_cmd *cmd)
d0412d96 1281{
d0412d96
JC		 1282 int err;
1283
ed94493f
LB		 1284 err = phy_read_status(mp->phy);
1285 if (err == 0)
1286 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1287
fc32b0e2
LB		 1288 /*
1289 * The MAC does not support 1000baseT_Half.
1290 */
d0412d96
JC		 1291 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1292 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1293
1294 return err;
1295}
1296
10a9948d 1297static int
6bdf576e 1298mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1299 struct ethtool_cmd *cmd)
bedfe324 1300{
81600eea
LB		 1301 u32 port_status;
1302
37a6084f 1303 port_status = rdlp(mp, PORT_STATUS);
81600eea 1304
bedfe324
LB		 1305 cmd->supported = SUPPORTED_MII;
1306 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1307 switch (port_status & PORT_SPEED_MASK) {
1308 case PORT_SPEED_10:
70739497 1309 ethtool_cmd_speed_set(cmd, SPEED_10);
81600eea
LB		 1310 break;
1311 case PORT_SPEED_100:
70739497 1312 ethtool_cmd_speed_set(cmd, SPEED_100);
81600eea
LB		 1313 break;
1314 case PORT_SPEED_1000:
70739497 1315 ethtool_cmd_speed_set(cmd, SPEED_1000);
81600eea
LB		 1316 break;
1317 default:
1318 cmd->speed = -1;
1319 break;
1320 }
1321 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1322 cmd->port = PORT_MII;
1323 cmd->phy_address = 0;
1324 cmd->transceiver = XCVR_INTERNAL;
1325 cmd->autoneg = AUTONEG_DISABLE;
1326 cmd->maxtxpkt = 1;
1327 cmd->maxrxpkt = 1;
1328
1329 return 0;
1330}
1331
3871c387
MS		 1332static void
1333mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1334{
1335 struct mv643xx_eth_private *mp = netdev_priv(dev);
1336 wol->supported = 0;
1337 wol->wolopts = 0;
1338 if (mp->phy)
1339 phy_ethtool_get_wol(mp->phy, wol);
1340}
1341
1342static int
1343mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1344{
1345 struct mv643xx_eth_private *mp = netdev_priv(dev);
1346 int err;
1347
1348 if (mp->phy == NULL)
1349 return -EOPNOTSUPP;
1350
1351 err = phy_ethtool_set_wol(mp->phy, wol);
1352 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1353 * this debugging hint is useful to have.
1354 */
1355 if (err == -EOPNOTSUPP)
1356 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1357 return err;
1358}
1359
6bdf576e
LB		 1360static int
1361mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1362{
1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1364
1365 if (mp->phy != NULL)
1366 return mv643xx_eth_get_settings_phy(mp, cmd);
1367 else
1368 return mv643xx_eth_get_settings_phyless(mp, cmd);
1369}
1370
10a9948d
LB		 1371static int
1372mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1373{
e5371493 1374 struct mv643xx_eth_private *mp = netdev_priv(dev);
260055bb 1375 int ret;
ab4384a6 1376
6bdf576e
LB		 1377 if (mp->phy == NULL)
1378 return -EINVAL;
1379
fc32b0e2
LB		 1380 /*
1381 * The MAC does not support 1000baseT_Half.
1382 */
1383 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1384
260055bb
PS		 1385 ret = phy_ethtool_sset(mp->phy, cmd);
1386 if (!ret)
1387 mv643xx_adjust_pscr(mp);
1388 return ret;
c9df406f 1389}
1da177e4 1390
fc32b0e2
LB		 1391static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1392 struct ethtool_drvinfo *drvinfo)
c9df406f 1393{
6f39da2c
AL		 1394 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1395 sizeof(drvinfo->driver));
68aad78c 1396 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
6f39da2c
AL		 1397 sizeof(drvinfo->version));
1398 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1399 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
16820054 1400 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1401}
1da177e4 1402
fc32b0e2 1403static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1404{
e5371493 1405 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1406
6bdf576e
LB		 1407 if (mp->phy == NULL)
1408 return -EINVAL;
1da177e4 1409
6bdf576e 1410 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1411}
1412
3e508034
LB		 1413static int
1414mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1415{
1416 struct mv643xx_eth_private *mp = netdev_priv(dev);
1417
1418 ec->rx_coalesce_usecs = get_rx_coal(mp);
1419 ec->tx_coalesce_usecs = get_tx_coal(mp);
1420
1421 return 0;
1422}
1423
1424static int
1425mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1426{
1427 struct mv643xx_eth_private *mp = netdev_priv(dev);
1428
1429 set_rx_coal(mp, ec->rx_coalesce_usecs);
1430 set_tx_coal(mp, ec->tx_coalesce_usecs);
1431
1432 return 0;
1433}
1434
e7d2f4db
LB		 1435static void
1436mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1437{
1438 struct mv643xx_eth_private *mp = netdev_priv(dev);
1439
1440 er->rx_max_pending = 4096;
1441 er->tx_max_pending = 4096;
e7d2f4db
LB		 1442
1443 er->rx_pending = mp->rx_ring_size;
1444 er->tx_pending = mp->tx_ring_size;
e7d2f4db
LB		 1445}
1446
1447static int
1448mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1449{
1450 struct mv643xx_eth_private *mp = netdev_priv(dev);
1451
1452 if (er->rx_mini_pending || er->rx_jumbo_pending)
1453 return -EINVAL;
1454
1455 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1456 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1457
1458 if (netif_running(dev)) {
1459 mv643xx_eth_stop(dev);
1460 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 1461 netdev_err(dev,
1462 "fatal error on re-opening device after ring param change\n");
e7d2f4db
LB		 1463 return -ENOMEM;
1464 }
1465 }
1466
1467 return 0;
1468}
1469
d888b373
LB		 1470
1471static int
c8f44aff 1472mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
d888b373
LB		 1473{
1474 struct mv643xx_eth_private *mp = netdev_priv(dev);
3ad9b358 1475 bool rx_csum = features & NETIF_F_RXCSUM;
d888b373
LB		 1476
1477 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1478
1479 return 0;
1480}
1481
fc32b0e2
LB		 1482static void mv643xx_eth_get_strings(struct net_device *dev,
1483 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1484{
1485 int i;
1da177e4 1486
fc32b0e2
LB		 1487 if (stringset == ETH_SS_STATS) {
1488 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1489 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1490 mv643xx_eth_stats[i].stat_string,
e5371493 1491 ETH_GSTRING_LEN);
c9df406f 1492 }
c9df406f
LB		 1493 }
1494}
1da177e4 1495
fc32b0e2
LB		 1496static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1497 struct ethtool_stats *stats,
1498 uint64_t *data)
c9df406f 1499{
b9873841 1500 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1501 int i;
1da177e4 1502
8fd89211 1503 mv643xx_eth_get_stats(dev);
fc32b0e2 1504 mib_counters_update(mp);
1da177e4 1505
16820054
LB		 1506 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1507 const struct mv643xx_eth_stats *stat;
1508 void *p;
1509
1510 stat = mv643xx_eth_stats + i;
1511
1512 if (stat->netdev_off >= 0)
1513 p = ((void *)mp->dev) + stat->netdev_off;
1514 else
1515 p = ((void *)mp) + stat->mp_off;
1516
1517 data[i] = (stat->sizeof_stat == 8) ?
1518 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1519 }
c9df406f 1520}
1da177e4 1521
fc32b0e2 1522static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1523{
fc32b0e2 1524 if (sset == ETH_SS_STATS)
16820054 1525 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1526
1527 return -EOPNOTSUPP;
c9df406f 1528}
1da177e4 1529
e5371493 1530static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1531 .get_settings = mv643xx_eth_get_settings,
1532 .set_settings = mv643xx_eth_set_settings,
1533 .get_drvinfo = mv643xx_eth_get_drvinfo,
1534 .nway_reset = mv643xx_eth_nway_reset,
ed4ba4b5 1535 .get_link = ethtool_op_get_link,
3e508034
LB		 1536 .get_coalesce = mv643xx_eth_get_coalesce,
1537 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1538 .get_ringparam = mv643xx_eth_get_ringparam,
1539 .set_ringparam = mv643xx_eth_set_ringparam,
fc32b0e2
LB		 1540 .get_strings = mv643xx_eth_get_strings,
1541 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1542 .get_sset_count = mv643xx_eth_get_sset_count,
ebad0a8d 1543 .get_ts_info = ethtool_op_get_ts_info,
3871c387
MS		 1544 .get_wol = mv643xx_eth_get_wol,
1545 .set_wol = mv643xx_eth_set_wol,
c9df406f 1546};
1da177e4 1547
bea3348e 1548
c9df406f 1549/* address handling *********************************************************/
5daffe94 1550static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1551{
66e63ffb
LB		 1552 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1553 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1554
5daffe94
LB		 1555 addr[0] = (mac_h >> 24) & 0xff;
1556 addr[1] = (mac_h >> 16) & 0xff;
1557 addr[2] = (mac_h >> 8) & 0xff;
1558 addr[3] = mac_h & 0xff;
1559 addr[4] = (mac_l >> 8) & 0xff;
1560 addr[5] = mac_l & 0xff;
c9df406f 1561}
1da177e4 1562
66e63ffb 1563static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1564{
66e63ffb
LB		 1565 wrlp(mp, MAC_ADDR_HIGH,
1566 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1567 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1568}
d0412d96 1569
66e63ffb 1570static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1571{
ccffad25 1572 struct netdev_hw_addr *ha;
66e63ffb 1573 u32 nibbles;
1da177e4 1574
66e63ffb
LB		 1575 if (dev->flags & IFF_PROMISC)
1576 return 0;
1da177e4 1577
66e63ffb 1578 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1579 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1580 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1581 return 0;
ccffad25 1582 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1583 return 0;
ff561eef 1584
ccffad25 1585 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1586 }
1da177e4 1587
66e63ffb 1588 return nibbles;
1da177e4
LT		 1589}
1590
66e63ffb 1591static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1592{
e5371493 1593 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1594 u32 port_config;
1595 u32 nibbles;
1596 int i;
1da177e4 1597
cc9754b3 1598 uc_addr_set(mp, dev->dev_addr);
1da177e4 1599
6877f54e
PS		 1600 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1601
66e63ffb
LB		 1602 nibbles = uc_addr_filter_mask(dev);
1603 if (!nibbles) {
1604 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1605 nibbles = 0xffff;
66e63ffb
LB		 1606 }
1607
1608 for (i = 0; i < 16; i += 4) {
1609 int off = UNICAST_TABLE(mp->port_num) + i;
1610 u32 v;
1611
1612 v = 0;
1613 if (nibbles & 1)
1614 v |= 0x00000001;
1615 if (nibbles & 2)
1616 v |= 0x00000100;
1617 if (nibbles & 4)
1618 v |= 0x00010000;
1619 if (nibbles & 8)
1620 v |= 0x01000000;
1621 nibbles >>= 4;
1622
1623 wrl(mp, off, v);
1624 }
1625
66e63ffb 1626 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1627}
1628
69876569
LB		 1629static int addr_crc(unsigned char *addr)
1630{
1631 int crc = 0;
1632 int i;
1633
1634 for (i = 0; i < 6; i++) {
1635 int j;
1636
1637 crc = (crc ^ addr[i]) << 8;
1638 for (j = 7; j >= 0; j--) {
1639 if (crc & (0x100 << j))
1640 crc ^= 0x107 << j;
1641 }
1642 }
1643
1644 return crc;
1645}
1646
66e63ffb 1647static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1648{
fc32b0e2 1649 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1650 u32 *mc_spec;
1651 u32 *mc_other;
22bedad3 1652 struct netdev_hw_addr *ha;
fc32b0e2 1653 int i;
c8aaea25 1654
fc32b0e2 1655 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1656 int port_num;
1657 u32 accept;
c8aaea25 1658
66e63ffb
LB		 1659oom:
1660 port_num = mp->port_num;
1661 accept = 0x01010101;
fc32b0e2
LB		 1662 for (i = 0; i < 0x100; i += 4) {
1663 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1664 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1665 }
1666 return;
1667 }
c8aaea25 1668
82a5bd6a 1669 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1670 if (mc_spec == NULL)
1671 goto oom;
1672 mc_other = mc_spec + (0x100 >> 2);
1673
1674 memset(mc_spec, 0, 0x100);
1675 memset(mc_other, 0, 0x100);
1da177e4 1676
22bedad3
JP		 1677 netdev_for_each_mc_addr(ha, dev) {
1678 u8 *a = ha->addr;
66e63ffb
LB		 1679 u32 *table;
1680 int entry;
1da177e4 1681
fc32b0e2 1682 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1683 table = mc_spec;
1684 entry = a[5];
fc32b0e2 1685 } else {
66e63ffb
LB		 1686 table = mc_other;
1687 entry = addr_crc(a);
fc32b0e2 1688 }
66e63ffb 1689
2b448334 1690 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1691 }
66e63ffb
LB		 1692
1693 for (i = 0; i < 0x100; i += 4) {
1694 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1695 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1696 }
1697
1698 kfree(mc_spec);
1699}
1700
1701static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1702{
1703 mv643xx_eth_program_unicast_filter(dev);
1704 mv643xx_eth_program_multicast_filter(dev);
1705}
1706
1707static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1708{
1709 struct sockaddr *sa = addr;
1710
a29ec08a 1711 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 1712 return -EADDRNOTAVAIL;
a29ec08a 1713
66e63ffb
LB		 1714 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1715
1716 netif_addr_lock_bh(dev);
1717 mv643xx_eth_program_unicast_filter(dev);
1718 netif_addr_unlock_bh(dev);
1719
1720 return 0;
c9df406f 1721}
c8aaea25 1722
c8aaea25 1723
c9df406f 1724/* rx/tx queue initialisation ***********************************************/
64da80a2 1725static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1726{
64da80a2 1727 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1728 struct rx_desc *rx_desc;
1729 int size;
c9df406f
LB		 1730 int i;
1731
64da80a2
LB		 1732 rxq->index = index;
1733
e7d2f4db 1734 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1735
1736 rxq->rx_desc_count = 0;
1737 rxq->rx_curr_desc = 0;
1738 rxq->rx_used_desc = 0;
1739
1740 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1741
f7981c1c 1742 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1743 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1744 mp->rx_desc_sram_size);
1745 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1746 } else {
eb0519b5
GP		 1747 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1748 size, &rxq->rx_desc_dma,
1749 GFP_KERNEL);
f7ea3337
PJ		 1750 }
1751
8a578111 1752 if (rxq->rx_desc_area == NULL) {
7542db8b 1753 netdev_err(mp->dev,
8a578111
LB		 1754 "can't allocate rx ring (%d bytes)\n", size);
1755 goto out;
1756 }
1757 memset(rxq->rx_desc_area, 0, size);
1da177e4 1758
8a578111 1759 rxq->rx_desc_area_size = size;
b2adaca9
JP		 1760 rxq->rx_skb = kmalloc_array(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1761 GFP_KERNEL);
1762 if (rxq->rx_skb == NULL)
8a578111 1763 goto out_free;
8a578111 1764
64699336 1765 rx_desc = rxq->rx_desc_area;
8a578111 1766 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1767 int nexti;
1768
1769 nexti = i + 1;
1770 if (nexti == rxq->rx_ring_size)
1771 nexti = 0;
1772
8a578111
LB		 1773 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1774 nexti * sizeof(struct rx_desc);
1775 }
1776
8a578111
LB		 1777 return 0;
1778
1779
1780out_free:
f7981c1c 1781 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1782 iounmap(rxq->rx_desc_area);
1783 else
eb0519b5 1784 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1785 rxq->rx_desc_area,
1786 rxq->rx_desc_dma);
1787
1788out:
1789 return -ENOMEM;
c9df406f 1790}
c8aaea25 1791
8a578111 1792static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1793{
8a578111
LB		 1794 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1795 int i;
1796
1797 rxq_disable(rxq);
c8aaea25 1798
8a578111
LB		 1799 for (i = 0; i < rxq->rx_ring_size; i++) {
1800 if (rxq->rx_skb[i]) {
1801 dev_kfree_skb(rxq->rx_skb[i]);
1802 rxq->rx_desc_count--;
1da177e4 1803 }
c8aaea25 1804 }
1da177e4 1805
8a578111 1806 if (rxq->rx_desc_count) {
7542db8b 1807 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
8a578111
LB		 1808 rxq->rx_desc_count);
1809 }
1810
f7981c1c 1811 if (rxq->index == 0 &&
64da80a2 1812 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1813 iounmap(rxq->rx_desc_area);
c9df406f 1814 else
eb0519b5 1815 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1816 rxq->rx_desc_area, rxq->rx_desc_dma);
1817
1818 kfree(rxq->rx_skb);
c9df406f 1819}
1da177e4 1820
3d6b35bc 1821static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1822{
3d6b35bc 1823 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1824 struct tx_desc *tx_desc;
1825 int size;
c9df406f 1826 int i;
1da177e4 1827
3d6b35bc
LB		 1828 txq->index = index;
1829
e7d2f4db 1830 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1831
1832 txq->tx_desc_count = 0;
1833 txq->tx_curr_desc = 0;
1834 txq->tx_used_desc = 0;
1835
1836 size = txq->tx_ring_size * sizeof(struct tx_desc);
1837
f7981c1c 1838 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1839 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1840 mp->tx_desc_sram_size);
1841 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1842 } else {
eb0519b5
GP		 1843 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1844 size, &txq->tx_desc_dma,
1845 GFP_KERNEL);
13d64285
LB		 1846 }
1847
1848 if (txq->tx_desc_area == NULL) {
7542db8b 1849 netdev_err(mp->dev,
13d64285 1850 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1851 return -ENOMEM;
c9df406f 1852 }
13d64285
LB		 1853 memset(txq->tx_desc_area, 0, size);
1854
1855 txq->tx_desc_area_size = size;
13d64285 1856
64699336 1857 tx_desc = txq->tx_desc_area;
13d64285 1858 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1859 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1860 int nexti;
1861
1862 nexti = i + 1;
1863 if (nexti == txq->tx_ring_size)
1864 nexti = 0;
6b368f68
LB		 1865
1866 txd->cmd_sts = 0;
1867 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1868 nexti * sizeof(struct tx_desc);
1869 }
1870
99ab08e0 1871 skb_queue_head_init(&txq->tx_skb);
c9df406f 1872
99ab08e0 1873 return 0;
c8aaea25 1874}
1da177e4 1875
13d64285 1876static void txq_deinit(struct tx_queue *txq)
c9df406f 1877{
13d64285 1878 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1879
13d64285 1880 txq_disable(txq);
1fa38c58 1881 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1882
13d64285 1883 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1884
f7981c1c 1885 if (txq->index == 0 &&
3d6b35bc 1886 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1887 iounmap(txq->tx_desc_area);
c9df406f 1888 else
eb0519b5 1889 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 1890 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1891}
1da177e4 1892
1da177e4 1893
c9df406f 1894/* netdev ops and related ***************************************************/
1fa38c58
LB		 1895static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1896{
1897 u32 int_cause;
1898 u32 int_cause_ext;
1899
e0ca8410 1900 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 1901 if (int_cause == 0)
1902 return 0;
1903
1904 int_cause_ext = 0;
e0ca8410
SB		 1905 if (int_cause & INT_EXT) {
1906 int_cause &= ~INT_EXT;
37a6084f 1907 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 1908 }
1fa38c58 1909
1fa38c58 1910 if (int_cause) {
37a6084f 1911 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 1912 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 1913 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 1914 mp->work_rx |= (int_cause & INT_RX) >> 2;
1915 }
1916
1917 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1918 if (int_cause_ext) {
37a6084f 1919 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 1920 if (int_cause_ext & INT_EXT_LINK_PHY)
1921 mp->work_link = 1;
1922 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1923 }
1924
1925 return 1;
1926}
1927
1928static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1929{
1930 struct net_device *dev = (struct net_device *)dev_id;
1931 struct mv643xx_eth_private *mp = netdev_priv(dev);
1932
1933 if (unlikely(!mv643xx_eth_collect_events(mp)))
1934 return IRQ_NONE;
1935
37a6084f 1936 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 1937 napi_schedule(&mp->napi);
1938
1939 return IRQ_HANDLED;
1940}
1941
2f7eb47a
LB		 1942static void handle_link_event(struct mv643xx_eth_private *mp)
1943{
1944 struct net_device *dev = mp->dev;
1945 u32 port_status;
1946 int speed;
1947 int duplex;
1948 int fc;
1949
37a6084f 1950 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 1951 if (!(port_status & LINK_UP)) {
1952 if (netif_carrier_ok(dev)) {
1953 int i;
1954
7542db8b 1955 netdev_info(dev, "link down\n");
2f7eb47a
LB		 1956
1957 netif_carrier_off(dev);
2f7eb47a 1958
f7981c1c 1959 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1960 struct tx_queue *txq = mp->txq + i;
1961
1fa38c58 1962 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1963 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1964 }
1965 }
1966 return;
1967 }
1968
1969 switch (port_status & PORT_SPEED_MASK) {
1970 case PORT_SPEED_10:
1971 speed = 10;
1972 break;
1973 case PORT_SPEED_100:
1974 speed = 100;
1975 break;
1976 case PORT_SPEED_1000:
1977 speed = 1000;
1978 break;
1979 default:
1980 speed = -1;
1981 break;
1982 }
1983 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1984 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1985
7542db8b
JP		 1986 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
1987 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2f7eb47a 1988
4fdeca3f 1989 if (!netif_carrier_ok(dev))
2f7eb47a 1990 netif_carrier_on(dev);
2f7eb47a
LB		 1991}
1992
1fa38c58 1993static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1994{
1fa38c58
LB		 1995 struct mv643xx_eth_private *mp;
1996 int work_done;
ce4e2e45 1997
1fa38c58 1998 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1999
1319ebad
LB		 2000 if (unlikely(mp->oom)) {
2001 mp->oom = 0;
2002 del_timer(&mp->rx_oom);
2003 }
1da177e4 2004
1fa38c58
LB		 2005 work_done = 0;
2006 while (work_done < budget) {
2007 u8 queue_mask;
2008 int queue;
2009 int work_tbd;
2010
2011 if (mp->work_link) {
2012 mp->work_link = 0;
2013 handle_link_event(mp);
26ef1f17 2014 work_done++;
1fa38c58
LB		 2015 continue;
2016 }
1da177e4 2017
1319ebad
LB		 2018 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2019 if (likely(!mp->oom))
2020 queue_mask |= mp->work_rx_refill;
2021
1fa38c58
LB		 2022 if (!queue_mask) {
2023 if (mv643xx_eth_collect_events(mp))
2024 continue;
2025 break;
2026 }
1da177e4 2027
1fa38c58
LB		 2028 queue = fls(queue_mask) - 1;
2029 queue_mask = 1 << queue;
2030
2031 work_tbd = budget - work_done;
2032 if (work_tbd > 16)
2033 work_tbd = 16;
2034
2035 if (mp->work_tx_end & queue_mask) {
2036 txq_kick(mp->txq + queue);
2037 } else if (mp->work_tx & queue_mask) {
2038 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2039 txq_maybe_wake(mp->txq + queue);
2040 } else if (mp->work_rx & queue_mask) {
2041 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2042 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2043 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2044 } else {
2045 BUG();
2046 }
84dd619e 2047 }
fc32b0e2 2048
1fa38c58 2049 if (work_done < budget) {
1319ebad 2050 if (mp->oom)
1fa38c58
LB		 2051 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2052 napi_complete(napi);
e0ca8410 2053 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2054 }
3d6b35bc 2055
1fa38c58
LB		 2056 return work_done;
2057}
8fa89bf5 2058
1fa38c58
LB		 2059static inline void oom_timer_wrapper(unsigned long data)
2060{
2061 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2062
1fa38c58 2063 napi_schedule(&mp->napi);
1da177e4
LT		 2064}
2065
e5371493 2066static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2067{
45c5d3bc
LB		 2068 int data;
2069
ed94493f 2070 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2071 if (data < 0)
2072 return;
1da177e4 2073
7f106c1d 2074 data |= BMCR_RESET;
ed94493f 2075 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2076 return;
1da177e4 2077
c9df406f 2078 do {
ed94493f 2079 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2080 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2081}
2082
fc32b0e2 2083static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2084{
d0412d96 2085 u32 pscr;
8a578111 2086 int i;
1da177e4 2087
bedfe324
LB		 2088 /*
2089 * Perform PHY reset, if there is a PHY.
2090 */
ed94493f 2091 if (mp->phy != NULL) {
bedfe324
LB		 2092 struct ethtool_cmd cmd;
2093
2094 mv643xx_eth_get_settings(mp->dev, &cmd);
2095 phy_reset(mp);
2096 mv643xx_eth_set_settings(mp->dev, &cmd);
2097 }
1da177e4 2098
81600eea
LB		 2099 /*
2100 * Configure basic link parameters.
2101 */
37a6084f 2102 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2103
2104 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2105 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2106
2107 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2108 if (mp->phy == NULL)
81600eea 2109 pscr |= FORCE_LINK_PASS;
37a6084f 2110 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2111
13d64285
LB		 2112 /*
2113 * Configure TX path and queues.
2114 */
89df5fdc 2115 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2116 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2117 struct tx_queue *txq = mp->txq + i;
13d64285 2118
6b368f68 2119 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2120 txq_set_rate(txq, 1000000000, 16777216);
2121 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2122 }
2123
d9a073ea
LB		 2124 /*
2125 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2126 * frames to RX queue #0, and include the pseudo-header when
2127 * calculating receive checksums.
d9a073ea 2128 */
e138f96b 2129 mv643xx_eth_set_features(mp->dev, mp->dev->features);
01999873 2130
376489a2
LB		 2131 /*
2132 * Treat BPDUs as normal multicasts, and disable partition mode.
2133 */
37a6084f 2134 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2135
5a893922
LB		 2136 /*
2137 * Add configured unicast addresses to address filter table.
2138 */
2139 mv643xx_eth_program_unicast_filter(mp->dev);
2140
8a578111 2141 /*
64da80a2 2142 * Enable the receive queues.
8a578111 2143 */
f7981c1c 2144 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2145 struct rx_queue *rxq = mp->rxq + i;
8a578111 2146 u32 addr;
1da177e4 2147
8a578111
LB		 2148 addr = (u32)rxq->rx_desc_dma;
2149 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2150 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2151
8a578111
LB		 2152 rxq_enable(rxq);
2153 }
1da177e4
LT		 2154}
2155
2bcb4b0f
LB		 2156static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2157{
2158 int skb_size;
2159
2160 /*
2161 * Reserve 2+14 bytes for an ethernet header (the hardware
2162 * automatically prepends 2 bytes of dummy data to each
2163 * received packet), 16 bytes for up to four VLAN tags, and
2164 * 4 bytes for the trailing FCS -- 36 bytes total.
2165 */
2166 skb_size = mp->dev->mtu + 36;
2167
2168 /*
2169 * Make sure that the skb size is a multiple of 8 bytes, as
2170 * the lower three bits of the receive descriptor's buffer
2171 * size field are ignored by the hardware.
2172 */
2173 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2174
2175 /*
2176 * If NET_SKB_PAD is smaller than a cache line,
2177 * netdev_alloc_skb() will cause skb->data to be misaligned
2178 * to a cache line boundary. If this is the case, include
2179 * some extra space to allow re-aligning the data area.
2180 */
2181 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2182}
2183
c9df406f 2184static int mv643xx_eth_open(struct net_device *dev)
16e03018 2185{
e5371493 2186 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2187 int err;
64da80a2 2188 int i;
16e03018 2189
37a6084f
LB		 2190 wrlp(mp, INT_CAUSE, 0);
2191 wrlp(mp, INT_CAUSE_EXT, 0);
2192 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2193
fc32b0e2 2194 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2195 IRQF_SHARED, dev->name, dev);
c9df406f 2196 if (err) {
7542db8b 2197 netdev_err(dev, "can't assign irq\n");
c9df406f 2198 return -EAGAIN;
16e03018
DF		 2199 }
2200
2bcb4b0f
LB		 2201 mv643xx_eth_recalc_skb_size(mp);
2202
2257e05c
LB		 2203 napi_enable(&mp->napi);
2204
e0ca8410
SB		 2205 mp->int_mask = INT_EXT;
2206
f7981c1c 2207 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2208 err = rxq_init(mp, i);
2209 if (err) {
2210 while (--i >= 0)
f7981c1c 2211 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2212 goto out;
2213 }
2214
1fa38c58 2215 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2216 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2217 }
2218
1319ebad 2219 if (mp->oom) {
2257e05c
LB		 2220 mp->rx_oom.expires = jiffies + (HZ / 10);
2221 add_timer(&mp->rx_oom);
64da80a2 2222 }
8a578111 2223
f7981c1c 2224 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2225 err = txq_init(mp, i);
2226 if (err) {
2227 while (--i >= 0)
f7981c1c 2228 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2229 goto out_free;
2230 }
e0ca8410 2231 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2232 }
16e03018 2233
fc32b0e2 2234 port_start(mp);
16e03018 2235
37a6084f 2236 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2237 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2238
c9df406f
LB		 2239 return 0;
2240
13d64285 2241
fc32b0e2 2242out_free:
f7981c1c
LB		 2243 for (i = 0; i < mp->rxq_count; i++)
2244 rxq_deinit(mp->rxq + i);
fc32b0e2 2245out:
c9df406f
LB		 2246 free_irq(dev->irq, dev);
2247
2248 return err;
16e03018
DF		 2249}
2250
e5371493 2251static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2252{
fc32b0e2 2253 unsigned int data;
64da80a2 2254 int i;
1da177e4 2255
f7981c1c
LB		 2256 for (i = 0; i < mp->rxq_count; i++)
2257 rxq_disable(mp->rxq + i);
2258 for (i = 0; i < mp->txq_count; i++)
2259 txq_disable(mp->txq + i);
ae9ae064
LB		 2260
2261 while (1) {
37a6084f 2262 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2263
2264 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2265 break;
13d64285 2266 udelay(10);
ae9ae064 2267 }
1da177e4 2268
c9df406f 2269 /* Reset the Enable bit in the Configuration Register */
37a6084f 2270 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2271 data &= ~(SERIAL_PORT_ENABLE |
2272 DO_NOT_FORCE_LINK_FAIL |
2273 FORCE_LINK_PASS);
37a6084f 2274 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2275}
2276
c9df406f 2277static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2278{
e5371493 2279 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2280 int i;
1da177e4 2281
fe65e704 2282 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2283 wrlp(mp, INT_MASK, 0x00000000);
2284 rdlp(mp, INT_MASK);
1da177e4 2285
c9df406f 2286 napi_disable(&mp->napi);
78fff83b 2287
2257e05c
LB		 2288 del_timer_sync(&mp->rx_oom);
2289
c9df406f 2290 netif_carrier_off(dev);
1da177e4 2291
fc32b0e2
LB		 2292 free_irq(dev->irq, dev);
2293
cc9754b3 2294 port_reset(mp);
8fd89211 2295 mv643xx_eth_get_stats(dev);
fc32b0e2 2296 mib_counters_update(mp);
57e8f26a 2297 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2298
f7981c1c
LB		 2299 for (i = 0; i < mp->rxq_count; i++)
2300 rxq_deinit(mp->rxq + i);
2301 for (i = 0; i < mp->txq_count; i++)
2302 txq_deinit(mp->txq + i);
1da177e4 2303
c9df406f 2304 return 0;
1da177e4
LT		 2305}
2306
fc32b0e2 2307static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2308{
e5371493 2309 struct mv643xx_eth_private *mp = netdev_priv(dev);
260055bb 2310 int ret;
1da177e4 2311
260055bb
PS		 2312 if (mp->phy == NULL)
2313 return -ENOTSUPP;
bedfe324 2314
260055bb
PS		 2315 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2316 if (!ret)
2317 mv643xx_adjust_pscr(mp);
2318 return ret;
1da177e4
LT		 2319}
2320
c9df406f 2321static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2322{
89df5fdc
LB		 2323 struct mv643xx_eth_private *mp = netdev_priv(dev);
2324
fc32b0e2 2325 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2326 return -EINVAL;
1da177e4 2327
c9df406f 2328 dev->mtu = new_mtu;
2bcb4b0f 2329 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2330 tx_set_rate(mp, 1000000000, 16777216);
2331
c9df406f
LB		 2332 if (!netif_running(dev))
2333 return 0;
1da177e4 2334
c9df406f
LB		 2335 /*
2336 * Stop and then re-open the interface. This will allocate RX
2337 * skbs of the new MTU.
2338 * There is a possible danger that the open will not succeed,
fc32b0e2 2339 * due to memory being full.
c9df406f
LB		 2340 */
2341 mv643xx_eth_stop(dev);
2342 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 2343 netdev_err(dev,
2344 "fatal error on re-opening device after MTU change\n");
c9df406f
LB		 2345 }
2346
2347 return 0;
1da177e4
LT		 2348}
2349
fc32b0e2 2350static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2351{
fc32b0e2 2352 struct mv643xx_eth_private *mp;
1da177e4 2353
fc32b0e2
LB		 2354 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2355 if (netif_running(mp->dev)) {
e5ef1de1 2356 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2357 port_reset(mp);
2358 port_start(mp);
e5ef1de1 2359 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2360 }
c9df406f
LB		 2361}
2362
c9df406f 2363static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2364{
e5371493 2365 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2366
7542db8b 2367 netdev_info(dev, "tx timeout\n");
d0412d96 2368
c9df406f 2369 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2370}
2371
c9df406f 2372#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2373static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2374{
fc32b0e2 2375 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2376
37a6084f
LB		 2377 wrlp(mp, INT_MASK, 0x00000000);
2378 rdlp(mp, INT_MASK);
c9df406f 2379
fc32b0e2 2380 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2381
e0ca8410 2382 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2383}
c9df406f 2384#endif
9f8dd319 2385
9f8dd319 2386
c9df406f 2387/* platform glue ************************************************************/
e5371493
LB		 2388static void
2389mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
63a9332b 2390 const struct mbus_dram_target_info *dram)
c9df406f 2391{
cc9754b3 2392 void __iomem *base = msp->base;
c9df406f
LB		 2393 u32 win_enable;
2394 u32 win_protect;
2395 int i;
9f8dd319 2396
c9df406f
LB		 2397 for (i = 0; i < 6; i++) {
2398 writel(0, base + WINDOW_BASE(i));
2399 writel(0, base + WINDOW_SIZE(i));
2400 if (i < 4)
2401 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2402 }
2403
c9df406f
LB		 2404 win_enable = 0x3f;
2405 win_protect = 0;
2406
2407 for (i = 0; i < dram->num_cs; i++) {
63a9332b 2408 const struct mbus_dram_window *cs = dram->cs + i;
c9df406f
LB		 2409
2410 writel((cs->base & 0xffff0000) |
2411 (cs->mbus_attr << 8) |
2412 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2413 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2414
2415 win_enable &= ~(1 << i);
2416 win_protect |= 3 << (2 * i);
2417 }
2418
2419 writel(win_enable, base + WINDOW_BAR_ENABLE);
2420 msp->win_protect = win_protect;
9f8dd319
DF		 2421}
2422
773fc3ee
LB		 2423static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2424{
2425 /*
2426 * Check whether we have a 14-bit coal limit field in bits
2427 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2428 * SDMA config register.
2429 */
37a6084f
LB		 2430 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2431 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2432 msp->extended_rx_coal_limit = 1;
2433 else
2434 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2435
2436 /*
457b1d5a
LB		 2437 * Check whether the MAC supports TX rate control, and if
2438 * yes, whether its associated registers are in the old or
2439 * the new place.
1e881592 2440 */
37a6084f
LB		 2441 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2442 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2443 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2444 } else {
37a6084f
LB		 2445 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2446 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2447 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2448 else
2449 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2450 }
773fc3ee
LB		 2451}
2452
c9df406f 2453static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2454{
10a9948d 2455 static int mv643xx_eth_version_printed;
c9df406f 2456 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2457 struct mv643xx_eth_shared_private *msp;
63a9332b 2458 const struct mbus_dram_target_info *dram;
c9df406f 2459 struct resource *res;
9f8dd319 2460
e5371493 2461 if (!mv643xx_eth_version_printed++)
7542db8b
JP		 2462 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2463 mv643xx_eth_driver_version);
9f8dd319 2464
c9df406f
LB		 2465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2466 if (res == NULL)
727f957a 2467 return -EINVAL;
9f8dd319 2468
727f957a 2469 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
c9df406f 2470 if (msp == NULL)
727f957a 2471 return -ENOMEM;
c9df406f 2472
28f65c11 2473 msp->base = ioremap(res->start, resource_size(res));
cc9754b3 2474 if (msp->base == NULL)
727f957a 2475 return -ENOMEM;
c9df406f 2476
20922486
SH		 2477 msp->clk = devm_clk_get(&pdev->dev, NULL);
2478 if (!IS_ERR(msp->clk))
2479 clk_prepare_enable(msp->clk);
2480
c9df406f
LB		 2481 /*
2482 * (Re-)program MBUS remapping windows if we are asked to.
2483 */
63a9332b
AL		 2484 dram = mv_mbus_dram_info();
2485 if (dram)
2486 mv643xx_eth_conf_mbus_windows(msp, dram);
c9df406f 2487
50a749c1
DC		 2488 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2489 pd->tx_csum_limit : 9 * 1024;
773fc3ee 2490 infer_hw_params(msp);
fc32b0e2
LB		 2491
2492 platform_set_drvdata(pdev, msp);
2493
c9df406f 2494 return 0;
c9df406f
LB		 2495}
2496
2497static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2498{
e5371493 2499 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2500
cc9754b3 2501 iounmap(msp->base);
20922486
SH		 2502 if (!IS_ERR(msp->clk))
2503 clk_disable_unprepare(msp->clk);
c9df406f
LB		 2504
2505 return 0;
9f8dd319
DF		 2506}
2507
c9df406f 2508static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2509 .probe = mv643xx_eth_shared_probe,
2510 .remove = mv643xx_eth_shared_remove,
c9df406f 2511 .driver = {
fc32b0e2 2512 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2513 .owner = THIS_MODULE,
2514 },
2515};
2516
e5371493 2517static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2518{
c9df406f 2519 int addr_shift = 5 * mp->port_num;
fc32b0e2 2520 u32 data;
1da177e4 2521
fc32b0e2
LB		 2522 data = rdl(mp, PHY_ADDR);
2523 data &= ~(0x1f << addr_shift);
2524 data |= (phy_addr & 0x1f) << addr_shift;
2525 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2526}
2527
e5371493 2528static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2529{
fc32b0e2
LB		 2530 unsigned int data;
2531
2532 data = rdl(mp, PHY_ADDR);
2533
2534 return (data >> (5 * mp->port_num)) & 0x1f;
2535}
2536
2537static void set_params(struct mv643xx_eth_private *mp,
2538 struct mv643xx_eth_platform_data *pd)
2539{
2540 struct net_device *dev = mp->dev;
2541
2542 if (is_valid_ether_addr(pd->mac_addr))
2543 memcpy(dev->dev_addr, pd->mac_addr, 6);
2544 else
2545 uc_addr_get(mp, dev->dev_addr);
2546
e7d2f4db 2547 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2548 if (pd->rx_queue_size)
e7d2f4db 2549 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2550 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2551 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2552
f7981c1c 2553 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2554
e7d2f4db 2555 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2556 if (pd->tx_queue_size)
e7d2f4db 2557 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2558 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2559 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2560
f7981c1c 2561 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2562}
2563
c3a07134
FF		 2564static void mv643xx_eth_adjust_link(struct net_device *dev)
2565{
2566 struct mv643xx_eth_private *mp = netdev_priv(dev);
2567
2568 mv643xx_adjust_pscr(mp);
2569}
2570
ed94493f
LB		 2571static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2572 int phy_addr)
1da177e4 2573{
ed94493f
LB		 2574 struct phy_device *phydev;
2575 int start;
2576 int num;
2577 int i;
c3a07134 2578 char phy_id[MII_BUS_ID_SIZE + 3];
45c5d3bc 2579
ed94493f
LB		 2580 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2581 start = phy_addr_get(mp) & 0x1f;
2582 num = 32;
2583 } else {
2584 start = phy_addr & 0x1f;
2585 num = 1;
2586 }
45c5d3bc 2587
c3a07134 2588 /* Attempt to connect to the PHY using orion-mdio */
976c90b9 2589 phydev = ERR_PTR(-ENODEV);
ed94493f
LB		 2590 for (i = 0; i < num; i++) {
2591 int addr = (start + i) & 0x1f;
fc32b0e2 2592
c3a07134
FF		 2593 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2594 "orion-mdio-mii", addr);
1da177e4 2595
c3a07134
FF		 2596 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2597 PHY_INTERFACE_MODE_GMII);
2598 if (!IS_ERR(phydev)) {
2599 phy_addr_set(mp, addr);
2600 break;
ed94493f
LB		 2601 }
2602 }
1da177e4 2603
ed94493f 2604 return phydev;
1da177e4
LT		 2605}
2606
ed94493f 2607static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2608{
ed94493f 2609 struct phy_device *phy = mp->phy;
c28a4f89 2610
fc32b0e2
LB		 2611 phy_reset(mp);
2612
ed94493f
LB		 2613 if (speed == 0) {
2614 phy->autoneg = AUTONEG_ENABLE;
2615 phy->speed = 0;
2616 phy->duplex = 0;
2617 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2618 } else {
ed94493f
LB		 2619 phy->autoneg = AUTONEG_DISABLE;
2620 phy->advertising = 0;
2621 phy->speed = speed;
2622 phy->duplex = duplex;
c9df406f 2623 }
ed94493f 2624 phy_start_aneg(phy);
c28a4f89
JC		 2625}
2626
81600eea
LB		 2627static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2628{
2629 u32 pscr;
2630
37a6084f 2631 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2632 if (pscr & SERIAL_PORT_ENABLE) {
2633 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2634 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2635 }
2636
2637 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2638 if (mp->phy == NULL) {
81600eea
LB		 2639 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2640 if (speed == SPEED_1000)
2641 pscr |= SET_GMII_SPEED_TO_1000;
2642 else if (speed == SPEED_100)
2643 pscr |= SET_MII_SPEED_TO_100;
2644
2645 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2646
2647 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2648 if (duplex == DUPLEX_FULL)
2649 pscr |= SET_FULL_DUPLEX_MODE;
2650 }
2651
37a6084f 2652 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2653}
2654
ea8a8642
LB		 2655static const struct net_device_ops mv643xx_eth_netdev_ops = {
2656 .ndo_open = mv643xx_eth_open,
2657 .ndo_stop = mv643xx_eth_stop,
2658 .ndo_start_xmit = mv643xx_eth_xmit,
2659 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2660 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 2661 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 2662 .ndo_do_ioctl = mv643xx_eth_ioctl,
2663 .ndo_change_mtu = mv643xx_eth_change_mtu,
aad59c43 2664 .ndo_set_features = mv643xx_eth_set_features,
ea8a8642
LB		 2665 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2666 .ndo_get_stats = mv643xx_eth_get_stats,
2667#ifdef CONFIG_NET_POLL_CONTROLLER
2668 .ndo_poll_controller = mv643xx_eth_netpoll,
2669#endif
2670};
2671
c9df406f 2672static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2673{
c9df406f 2674 struct mv643xx_eth_platform_data *pd;
e5371493 2675 struct mv643xx_eth_private *mp;
c9df406f 2676 struct net_device *dev;
c9df406f 2677 struct resource *res;
fc32b0e2 2678 int err;
1da177e4 2679
c9df406f
LB		 2680 pd = pdev->dev.platform_data;
2681 if (pd == NULL) {
7542db8b 2682 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2683 return -ENODEV;
2684 }
1da177e4 2685
c9df406f 2686 if (pd->shared == NULL) {
7542db8b 2687 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2688 return -ENODEV;
2689 }
8f518703 2690
e5ef1de1 2691 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2692 if (!dev)
2693 return -ENOMEM;
1da177e4 2694
c9df406f 2695 mp = netdev_priv(dev);
fc32b0e2
LB		 2696 platform_set_drvdata(pdev, mp);
2697
2698 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2699 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2700 mp->port_num = pd->port_number;
2701
c9df406f 2702 mp->dev = dev;
78fff83b 2703
452503eb 2704 /*
9a43a026
AL		 2705 * Start with a default rate, and if there is a clock, allow
2706 * it to override the default.
452503eb 2707 */
9a43a026 2708 mp->t_clk = 133000000;
20922486 2709 mp->clk = devm_clk_get(&pdev->dev, NULL);
452503eb
AL		 2710 if (!IS_ERR(mp->clk)) {
2711 clk_prepare_enable(mp->clk);
2712 mp->t_clk = clk_get_rate(mp->clk);
452503eb 2713 }
20922486 2714
fc32b0e2 2715 set_params(mp, pd);
206d6b32
BH		 2716 netif_set_real_num_tx_queues(dev, mp->txq_count);
2717 netif_set_real_num_rx_queues(dev, mp->rxq_count);
fc32b0e2 2718
976c90b9 2719 if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
ed94493f 2720 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2721
976c90b9
SB		 2722 if (IS_ERR(mp->phy)) {
2723 err = PTR_ERR(mp->phy);
2724 if (err == -ENODEV)
2725 err = -EPROBE_DEFER;
2726 goto out;
2727 }
ed94493f 2728 phy_init(mp, pd->speed, pd->duplex);
976c90b9 2729 }
6bdf576e
LB		 2730
2731 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2732
81600eea 2733 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2734
4ff3495a
LB		 2735
2736 mib_counters_clear(mp);
2737
2738 init_timer(&mp->mib_counters_timer);
2739 mp->mib_counters_timer.data = (unsigned long)mp;
2740 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2741 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2742 add_timer(&mp->mib_counters_timer);
2743
2744 spin_lock_init(&mp->mib_counters_lock);
2745
2746 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2747
a3659aa0 2748 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
2257e05c
LB		 2749
2750 init_timer(&mp->rx_oom);
2751 mp->rx_oom.data = (unsigned long)mp;
2752 mp->rx_oom.function = oom_timer_wrapper;
2753
fc32b0e2 2754
c9df406f
LB		 2755 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2756 BUG_ON(!res);
2757 dev->irq = res->start;
1da177e4 2758
ea8a8642
LB		 2759 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2760
c9df406f
LB		 2761 dev->watchdog_timeo = 2 * HZ;
2762 dev->base_addr = 0;
1da177e4 2763
3619eb85 2764 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
aad59c43 2765 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
e32b6617 2766 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2767
01789349
JP		 2768 dev->priv_flags |= IFF_UNICAST_FLT;
2769
fc32b0e2 2770 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2771
c9df406f 2772 if (mp->shared->win_protect)
fc32b0e2 2773 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2774
a5fe3616
LB		 2775 netif_carrier_off(dev);
2776
b5e86db4
LB		 2777 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2778
4fb0a54a 2779 set_rx_coal(mp, 250);
a5fe3616
LB		 2780 set_tx_coal(mp, 0);
2781
c9df406f
LB		 2782 err = register_netdev(dev);
2783 if (err)
2784 goto out;
1da177e4 2785
7542db8b
JP		 2786 netdev_notice(dev, "port %d with MAC address %pM\n",
2787 mp->port_num, dev->dev_addr);
1da177e4 2788
13d64285 2789 if (mp->tx_desc_sram_size > 0)
7542db8b 2790 netdev_notice(dev, "configured with sram\n");
1da177e4 2791
c9df406f 2792 return 0;
1da177e4 2793
c9df406f 2794out:
20922486 2795 if (!IS_ERR(mp->clk))
baffab28 2796 clk_disable_unprepare(mp->clk);
c9df406f 2797 free_netdev(dev);
1da177e4 2798
c9df406f 2799 return err;
1da177e4
LT		 2800}
2801
c9df406f 2802static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2803{
fc32b0e2 2804 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2805
fc32b0e2 2806 unregister_netdev(mp->dev);
ed94493f
LB		 2807 if (mp->phy != NULL)
2808 phy_detach(mp->phy);
23f333a2 2809 cancel_work_sync(&mp->tx_timeout_task);
452503eb 2810
20922486 2811 if (!IS_ERR(mp->clk))
452503eb 2812 clk_disable_unprepare(mp->clk);
9a43a026 2813
fc32b0e2 2814 free_netdev(mp->dev);
c9df406f 2815
c9df406f 2816 platform_set_drvdata(pdev, NULL);
fc32b0e2 2817
c9df406f 2818 return 0;
1da177e4
LT		 2819}
2820
c9df406f 2821static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2822{
fc32b0e2 2823 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2824
c9df406f 2825 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2826 wrlp(mp, INT_MASK, 0);
2827 rdlp(mp, INT_MASK);
c9df406f 2828
fc32b0e2
LB		 2829 if (netif_running(mp->dev))
2830 port_reset(mp);
d0412d96
JC		 2831}
2832
c9df406f 2833static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2834 .probe = mv643xx_eth_probe,
2835 .remove = mv643xx_eth_remove,
2836 .shutdown = mv643xx_eth_shutdown,
c9df406f 2837 .driver = {
fc32b0e2 2838 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2839 .owner = THIS_MODULE,
2840 },
2841};
2842
e5371493 2843static int __init mv643xx_eth_init_module(void)
d0412d96 2844{
c9df406f 2845 int rc;
d0412d96 2846
c9df406f
LB		 2847 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2848 if (!rc) {
2849 rc = platform_driver_register(&mv643xx_eth_driver);
2850 if (rc)
2851 platform_driver_unregister(&mv643xx_eth_shared_driver);
2852 }
fc32b0e2 2853
c9df406f 2854 return rc;
d0412d96 2855}
fc32b0e2 2856module_init(mv643xx_eth_init_module);
d0412d96 2857
e5371493 2858static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2859{
c9df406f
LB		 2860 platform_driver_unregister(&mv643xx_eth_driver);
2861 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2862}
e5371493 2863module_exit(mv643xx_eth_cleanup_module);
1da177e4 2864
45675bc6
LB		 2865MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2866 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2867MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2868MODULE_LICENSE("GPL");
c9df406f 2869MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2870MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
kernel source for telekom puls (alcatel/mediatek)