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92915f71 GR |
1 | /******************************************************************************* |
2 | ||
3 | Intel 82599 Virtual Function driver | |
5c47a2b6 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
92915f71 GR |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | ||
29 | /****************************************************************************** | |
30 | Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code | |
31 | ******************************************************************************/ | |
dbd9636e JK |
32 | |
33 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
34 | ||
92915f71 | 35 | #include <linux/types.h> |
dadcd65f | 36 | #include <linux/bitops.h> |
92915f71 GR |
37 | #include <linux/module.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/vmalloc.h> | |
41 | #include <linux/string.h> | |
42 | #include <linux/in.h> | |
43 | #include <linux/ip.h> | |
44 | #include <linux/tcp.h> | |
70a10e25 | 45 | #include <linux/sctp.h> |
92915f71 | 46 | #include <linux/ipv6.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
92915f71 GR |
48 | #include <net/checksum.h> |
49 | #include <net/ip6_checksum.h> | |
50 | #include <linux/ethtool.h> | |
01789349 | 51 | #include <linux/if.h> |
92915f71 | 52 | #include <linux/if_vlan.h> |
70c71606 | 53 | #include <linux/prefetch.h> |
92915f71 GR |
54 | |
55 | #include "ixgbevf.h" | |
56 | ||
3d8fe98f | 57 | const char ixgbevf_driver_name[] = "ixgbevf"; |
92915f71 | 58 | static const char ixgbevf_driver_string[] = |
422e05d1 | 59 | "Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver"; |
92915f71 | 60 | |
1b3d2d77 | 61 | #define DRV_VERSION "2.7.12-k" |
92915f71 | 62 | const char ixgbevf_driver_version[] = DRV_VERSION; |
66c87bd5 | 63 | static char ixgbevf_copyright[] = |
5c47a2b6 | 64 | "Copyright (c) 2009 - 2012 Intel Corporation."; |
92915f71 GR |
65 | |
66 | static const struct ixgbevf_info *ixgbevf_info_tbl[] = { | |
2316aa2a GR |
67 | [board_82599_vf] = &ixgbevf_82599_vf_info, |
68 | [board_X540_vf] = &ixgbevf_X540_vf_info, | |
92915f71 GR |
69 | }; |
70 | ||
71 | /* ixgbevf_pci_tbl - PCI Device ID Table | |
72 | * | |
73 | * Wildcard entries (PCI_ANY_ID) should come last | |
74 | * Last entry must be all 0s | |
75 | * | |
76 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
77 | * Class, Class Mask, private data (not used) } | |
78 | */ | |
79 | static struct pci_device_id ixgbevf_pci_tbl[] = { | |
80 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF), | |
81 | board_82599_vf}, | |
2316aa2a GR |
82 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF), |
83 | board_X540_vf}, | |
92915f71 GR |
84 | |
85 | /* required last entry */ | |
86 | {0, } | |
87 | }; | |
88 | MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl); | |
89 | ||
90 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); | |
91 | MODULE_DESCRIPTION("Intel(R) 82599 Virtual Function Driver"); | |
92 | MODULE_LICENSE("GPL"); | |
93 | MODULE_VERSION(DRV_VERSION); | |
94 | ||
b3f4d599 | 95 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
96 | static int debug = -1; | |
97 | module_param(debug, int, 0); | |
98 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
92915f71 GR |
99 | |
100 | /* forward decls */ | |
fa71ae27 | 101 | static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector); |
56e94095 | 102 | static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter); |
92915f71 GR |
103 | |
104 | static inline void ixgbevf_release_rx_desc(struct ixgbe_hw *hw, | |
105 | struct ixgbevf_ring *rx_ring, | |
106 | u32 val) | |
107 | { | |
108 | /* | |
109 | * Force memory writes to complete before letting h/w | |
110 | * know there are new descriptors to fetch. (Only | |
111 | * applicable for weak-ordered memory model archs, | |
112 | * such as IA-64). | |
113 | */ | |
114 | wmb(); | |
115 | IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rx_ring->reg_idx), val); | |
116 | } | |
117 | ||
49ce9c2c | 118 | /** |
65d676c8 | 119 | * ixgbevf_set_ivar - set IVAR registers - maps interrupt causes to vectors |
92915f71 GR |
120 | * @adapter: pointer to adapter struct |
121 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
122 | * @queue: queue to map the corresponding interrupt to | |
123 | * @msix_vector: the vector to map to the corresponding queue | |
124 | * | |
125 | */ | |
126 | static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction, | |
127 | u8 queue, u8 msix_vector) | |
128 | { | |
129 | u32 ivar, index; | |
130 | struct ixgbe_hw *hw = &adapter->hw; | |
131 | if (direction == -1) { | |
132 | /* other causes */ | |
133 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
134 | ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); | |
135 | ivar &= ~0xFF; | |
136 | ivar |= msix_vector; | |
137 | IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar); | |
138 | } else { | |
139 | /* tx or rx causes */ | |
140 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
141 | index = ((16 * (queue & 1)) + (8 * direction)); | |
142 | ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); | |
143 | ivar &= ~(0xFF << index); | |
144 | ivar |= (msix_vector << index); | |
145 | IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar); | |
146 | } | |
147 | } | |
148 | ||
70a10e25 | 149 | static void ixgbevf_unmap_and_free_tx_resource(struct ixgbevf_ring *tx_ring, |
92915f71 GR |
150 | struct ixgbevf_tx_buffer |
151 | *tx_buffer_info) | |
152 | { | |
153 | if (tx_buffer_info->dma) { | |
154 | if (tx_buffer_info->mapped_as_page) | |
70a10e25 | 155 | dma_unmap_page(tx_ring->dev, |
92915f71 GR |
156 | tx_buffer_info->dma, |
157 | tx_buffer_info->length, | |
2a1f8794 | 158 | DMA_TO_DEVICE); |
92915f71 | 159 | else |
70a10e25 | 160 | dma_unmap_single(tx_ring->dev, |
92915f71 GR |
161 | tx_buffer_info->dma, |
162 | tx_buffer_info->length, | |
2a1f8794 | 163 | DMA_TO_DEVICE); |
92915f71 GR |
164 | tx_buffer_info->dma = 0; |
165 | } | |
166 | if (tx_buffer_info->skb) { | |
167 | dev_kfree_skb_any(tx_buffer_info->skb); | |
168 | tx_buffer_info->skb = NULL; | |
169 | } | |
170 | tx_buffer_info->time_stamp = 0; | |
171 | /* tx_buffer_info must be completely set up in the transmit path */ | |
172 | } | |
173 | ||
92915f71 GR |
174 | #define IXGBE_MAX_TXD_PWR 14 |
175 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
176 | ||
177 | /* Tx Descriptors needed, worst case */ | |
3595990a AD |
178 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) |
179 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) | |
92915f71 GR |
180 | |
181 | static void ixgbevf_tx_timeout(struct net_device *netdev); | |
182 | ||
183 | /** | |
184 | * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes | |
fa71ae27 | 185 | * @q_vector: board private structure |
92915f71 GR |
186 | * @tx_ring: tx ring to clean |
187 | **/ | |
fa71ae27 | 188 | static bool ixgbevf_clean_tx_irq(struct ixgbevf_q_vector *q_vector, |
92915f71 GR |
189 | struct ixgbevf_ring *tx_ring) |
190 | { | |
fa71ae27 | 191 | struct ixgbevf_adapter *adapter = q_vector->adapter; |
92915f71 GR |
192 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
193 | struct ixgbevf_tx_buffer *tx_buffer_info; | |
194 | unsigned int i, eop, count = 0; | |
195 | unsigned int total_bytes = 0, total_packets = 0; | |
196 | ||
10cc1bdd AD |
197 | if (test_bit(__IXGBEVF_DOWN, &adapter->state)) |
198 | return true; | |
199 | ||
92915f71 GR |
200 | i = tx_ring->next_to_clean; |
201 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
908421f6 | 202 | eop_desc = IXGBEVF_TX_DESC(tx_ring, eop); |
92915f71 GR |
203 | |
204 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
fa71ae27 | 205 | (count < tx_ring->count)) { |
92915f71 | 206 | bool cleaned = false; |
2d0bb1c1 | 207 | rmb(); /* read buffer_info after eop_desc */ |
98b9e48f GR |
208 | /* eop could change between read and DD-check */ |
209 | if (unlikely(eop != tx_ring->tx_buffer_info[i].next_to_watch)) | |
210 | goto cont_loop; | |
92915f71 GR |
211 | for ( ; !cleaned; count++) { |
212 | struct sk_buff *skb; | |
908421f6 | 213 | tx_desc = IXGBEVF_TX_DESC(tx_ring, i); |
92915f71 GR |
214 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
215 | cleaned = (i == eop); | |
216 | skb = tx_buffer_info->skb; | |
217 | ||
218 | if (cleaned && skb) { | |
219 | unsigned int segs, bytecount; | |
220 | ||
221 | /* gso_segs is currently only valid for tcp */ | |
222 | segs = skb_shinfo(skb)->gso_segs ?: 1; | |
223 | /* multiply data chunks by size of headers */ | |
224 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
225 | skb->len; | |
226 | total_packets += segs; | |
227 | total_bytes += bytecount; | |
228 | } | |
229 | ||
70a10e25 | 230 | ixgbevf_unmap_and_free_tx_resource(tx_ring, |
92915f71 GR |
231 | tx_buffer_info); |
232 | ||
233 | tx_desc->wb.status = 0; | |
234 | ||
235 | i++; | |
236 | if (i == tx_ring->count) | |
237 | i = 0; | |
238 | } | |
239 | ||
98b9e48f | 240 | cont_loop: |
92915f71 | 241 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
908421f6 | 242 | eop_desc = IXGBEVF_TX_DESC(tx_ring, eop); |
92915f71 GR |
243 | } |
244 | ||
245 | tx_ring->next_to_clean = i; | |
246 | ||
247 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) | |
fb40195c | 248 | if (unlikely(count && netif_carrier_ok(tx_ring->netdev) && |
92915f71 GR |
249 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { |
250 | /* Make sure that anybody stopping the queue after this | |
251 | * sees the new next_to_clean. | |
252 | */ | |
253 | smp_mb(); | |
fb40195c AD |
254 | if (__netif_subqueue_stopped(tx_ring->netdev, |
255 | tx_ring->queue_index) && | |
92915f71 | 256 | !test_bit(__IXGBEVF_DOWN, &adapter->state)) { |
fb40195c AD |
257 | netif_wake_subqueue(tx_ring->netdev, |
258 | tx_ring->queue_index); | |
92915f71 GR |
259 | ++adapter->restart_queue; |
260 | } | |
92915f71 GR |
261 | } |
262 | ||
4197aa7b | 263 | u64_stats_update_begin(&tx_ring->syncp); |
92915f71 GR |
264 | tx_ring->total_bytes += total_bytes; |
265 | tx_ring->total_packets += total_packets; | |
4197aa7b | 266 | u64_stats_update_end(&tx_ring->syncp); |
ac6ed8f0 GR |
267 | q_vector->tx.total_bytes += total_bytes; |
268 | q_vector->tx.total_packets += total_packets; | |
92915f71 | 269 | |
fa71ae27 | 270 | return count < tx_ring->count; |
92915f71 GR |
271 | } |
272 | ||
273 | /** | |
274 | * ixgbevf_receive_skb - Send a completed packet up the stack | |
275 | * @q_vector: structure containing interrupt and ring information | |
276 | * @skb: packet to send up | |
277 | * @status: hardware indication of status of receive | |
92915f71 GR |
278 | * @rx_desc: rx descriptor |
279 | **/ | |
280 | static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector, | |
281 | struct sk_buff *skb, u8 status, | |
92915f71 GR |
282 | union ixgbe_adv_rx_desc *rx_desc) |
283 | { | |
284 | struct ixgbevf_adapter *adapter = q_vector->adapter; | |
285 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); | |
dd1ed3b7 | 286 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); |
92915f71 | 287 | |
5d9a533b | 288 | if (is_vlan && test_bit(tag & VLAN_VID_MASK, adapter->active_vlans)) |
dadcd65f | 289 | __vlan_hwaccel_put_tag(skb, tag); |
dadcd65f | 290 | |
366c1099 GR |
291 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) |
292 | napi_gro_receive(&q_vector->napi, skb); | |
293 | else | |
294 | netif_rx(skb); | |
92915f71 GR |
295 | } |
296 | ||
297 | /** | |
298 | * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum | |
299 | * @adapter: address of board private structure | |
300 | * @status_err: hardware indication of status of receive | |
301 | * @skb: skb currently being received and modified | |
302 | **/ | |
303 | static inline void ixgbevf_rx_checksum(struct ixgbevf_adapter *adapter, | |
fb40195c | 304 | struct ixgbevf_ring *ring, |
92915f71 GR |
305 | u32 status_err, struct sk_buff *skb) |
306 | { | |
bc8acf2c | 307 | skb_checksum_none_assert(skb); |
92915f71 GR |
308 | |
309 | /* Rx csum disabled */ | |
fb40195c | 310 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
92915f71 GR |
311 | return; |
312 | ||
313 | /* if IP and error */ | |
314 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
315 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
316 | adapter->hw_csum_rx_error++; | |
317 | return; | |
318 | } | |
319 | ||
320 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
321 | return; | |
322 | ||
323 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
324 | adapter->hw_csum_rx_error++; | |
325 | return; | |
326 | } | |
327 | ||
328 | /* It must be a TCP or UDP packet with a valid checksum */ | |
329 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
330 | adapter->hw_csum_rx_good++; | |
331 | } | |
332 | ||
333 | /** | |
334 | * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split | |
335 | * @adapter: address of board private structure | |
336 | **/ | |
337 | static void ixgbevf_alloc_rx_buffers(struct ixgbevf_adapter *adapter, | |
338 | struct ixgbevf_ring *rx_ring, | |
339 | int cleaned_count) | |
340 | { | |
341 | struct pci_dev *pdev = adapter->pdev; | |
342 | union ixgbe_adv_rx_desc *rx_desc; | |
343 | struct ixgbevf_rx_buffer *bi; | |
344 | struct sk_buff *skb; | |
fb40195c | 345 | unsigned int i = rx_ring->next_to_use; |
92915f71 | 346 | |
92915f71 GR |
347 | bi = &rx_ring->rx_buffer_info[i]; |
348 | ||
349 | while (cleaned_count--) { | |
908421f6 | 350 | rx_desc = IXGBEVF_RX_DESC(rx_ring, i); |
92915f71 GR |
351 | skb = bi->skb; |
352 | if (!skb) { | |
fb40195c AD |
353 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, |
354 | rx_ring->rx_buf_len); | |
92915f71 GR |
355 | if (!skb) { |
356 | adapter->alloc_rx_buff_failed++; | |
357 | goto no_buffers; | |
358 | } | |
92915f71 GR |
359 | bi->skb = skb; |
360 | } | |
361 | if (!bi->dma) { | |
2a1f8794 | 362 | bi->dma = dma_map_single(&pdev->dev, skb->data, |
92915f71 | 363 | rx_ring->rx_buf_len, |
2a1f8794 | 364 | DMA_FROM_DEVICE); |
6132ee8a GR |
365 | if (dma_mapping_error(&pdev->dev, bi->dma)) { |
366 | dev_kfree_skb(skb); | |
367 | bi->skb = NULL; | |
368 | dev_err(&pdev->dev, "RX DMA map failed\n"); | |
369 | break; | |
370 | } | |
92915f71 | 371 | } |
77d5dfca | 372 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
92915f71 GR |
373 | |
374 | i++; | |
375 | if (i == rx_ring->count) | |
376 | i = 0; | |
377 | bi = &rx_ring->rx_buffer_info[i]; | |
378 | } | |
379 | ||
380 | no_buffers: | |
381 | if (rx_ring->next_to_use != i) { | |
382 | rx_ring->next_to_use = i; | |
92915f71 GR |
383 | |
384 | ixgbevf_release_rx_desc(&adapter->hw, rx_ring, i); | |
385 | } | |
386 | } | |
387 | ||
388 | static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter, | |
5f3600eb | 389 | u32 qmask) |
92915f71 | 390 | { |
92915f71 GR |
391 | struct ixgbe_hw *hw = &adapter->hw; |
392 | ||
5f3600eb | 393 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, qmask); |
92915f71 GR |
394 | } |
395 | ||
92915f71 GR |
396 | static bool ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector, |
397 | struct ixgbevf_ring *rx_ring, | |
fa71ae27 | 398 | int budget) |
92915f71 GR |
399 | { |
400 | struct ixgbevf_adapter *adapter = q_vector->adapter; | |
401 | struct pci_dev *pdev = adapter->pdev; | |
402 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
403 | struct ixgbevf_rx_buffer *rx_buffer_info, *next_buffer; | |
404 | struct sk_buff *skb; | |
405 | unsigned int i; | |
406 | u32 len, staterr; | |
92915f71 GR |
407 | int cleaned_count = 0; |
408 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
409 | ||
410 | i = rx_ring->next_to_clean; | |
908421f6 | 411 | rx_desc = IXGBEVF_RX_DESC(rx_ring, i); |
92915f71 GR |
412 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
413 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
414 | ||
415 | while (staterr & IXGBE_RXD_STAT_DD) { | |
fa71ae27 | 416 | if (!budget) |
92915f71 | 417 | break; |
fa71ae27 | 418 | budget--; |
92915f71 | 419 | |
2d0bb1c1 | 420 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
77d5dfca | 421 | len = le16_to_cpu(rx_desc->wb.upper.length); |
92915f71 GR |
422 | skb = rx_buffer_info->skb; |
423 | prefetch(skb->data - NET_IP_ALIGN); | |
424 | rx_buffer_info->skb = NULL; | |
425 | ||
426 | if (rx_buffer_info->dma) { | |
2a1f8794 | 427 | dma_unmap_single(&pdev->dev, rx_buffer_info->dma, |
92915f71 | 428 | rx_ring->rx_buf_len, |
2a1f8794 | 429 | DMA_FROM_DEVICE); |
92915f71 GR |
430 | rx_buffer_info->dma = 0; |
431 | skb_put(skb, len); | |
432 | } | |
433 | ||
92915f71 GR |
434 | i++; |
435 | if (i == rx_ring->count) | |
436 | i = 0; | |
437 | ||
908421f6 | 438 | next_rxd = IXGBEVF_RX_DESC(rx_ring, i); |
92915f71 GR |
439 | prefetch(next_rxd); |
440 | cleaned_count++; | |
441 | ||
442 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
443 | ||
444 | if (!(staterr & IXGBE_RXD_STAT_EOP)) { | |
77d5dfca | 445 | skb->next = next_buffer->skb; |
5c60f81a | 446 | IXGBE_CB(skb->next)->prev = skb; |
92915f71 GR |
447 | adapter->non_eop_descs++; |
448 | goto next_desc; | |
449 | } | |
450 | ||
5c60f81a AD |
451 | /* we should not be chaining buffers, if we did drop the skb */ |
452 | if (IXGBE_CB(skb)->prev) { | |
453 | do { | |
454 | struct sk_buff *this = skb; | |
455 | skb = IXGBE_CB(skb)->prev; | |
456 | dev_kfree_skb(this); | |
457 | } while (skb); | |
458 | goto next_desc; | |
459 | } | |
460 | ||
92915f71 GR |
461 | /* ERR_MASK will only have valid bits if EOP set */ |
462 | if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) { | |
463 | dev_kfree_skb_irq(skb); | |
464 | goto next_desc; | |
465 | } | |
466 | ||
fb40195c | 467 | ixgbevf_rx_checksum(adapter, rx_ring, staterr, skb); |
92915f71 GR |
468 | |
469 | /* probably a little skewed due to removing CRC */ | |
470 | total_rx_bytes += skb->len; | |
471 | total_rx_packets++; | |
472 | ||
473 | /* | |
474 | * Work around issue of some types of VM to VM loop back | |
475 | * packets not getting split correctly | |
476 | */ | |
477 | if (staterr & IXGBE_RXD_STAT_LB) { | |
e743d313 | 478 | u32 header_fixup_len = skb_headlen(skb); |
92915f71 GR |
479 | if (header_fixup_len < 14) |
480 | skb_push(skb, header_fixup_len); | |
481 | } | |
fb40195c | 482 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
92915f71 | 483 | |
815cccbf JF |
484 | /* Workaround hardware that can't do proper VEPA multicast |
485 | * source pruning. | |
486 | */ | |
487 | if ((skb->pkt_type & (PACKET_BROADCAST | PACKET_MULTICAST)) && | |
488 | !(compare_ether_addr(adapter->netdev->dev_addr, | |
489 | eth_hdr(skb)->h_source))) { | |
490 | dev_kfree_skb_irq(skb); | |
491 | goto next_desc; | |
492 | } | |
493 | ||
b3d58a8f | 494 | ixgbevf_receive_skb(q_vector, skb, staterr, rx_desc); |
92915f71 GR |
495 | |
496 | next_desc: | |
497 | rx_desc->wb.upper.status_error = 0; | |
498 | ||
499 | /* return some buffers to hardware, one at a time is too slow */ | |
500 | if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) { | |
501 | ixgbevf_alloc_rx_buffers(adapter, rx_ring, | |
502 | cleaned_count); | |
503 | cleaned_count = 0; | |
504 | } | |
505 | ||
506 | /* use prefetched values */ | |
507 | rx_desc = next_rxd; | |
508 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
509 | ||
510 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
511 | } | |
512 | ||
513 | rx_ring->next_to_clean = i; | |
514 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
515 | ||
516 | if (cleaned_count) | |
517 | ixgbevf_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
518 | ||
4197aa7b | 519 | u64_stats_update_begin(&rx_ring->syncp); |
92915f71 GR |
520 | rx_ring->total_packets += total_rx_packets; |
521 | rx_ring->total_bytes += total_rx_bytes; | |
4197aa7b | 522 | u64_stats_update_end(&rx_ring->syncp); |
ac6ed8f0 GR |
523 | q_vector->rx.total_packets += total_rx_packets; |
524 | q_vector->rx.total_bytes += total_rx_bytes; | |
92915f71 | 525 | |
fa71ae27 | 526 | return !!budget; |
92915f71 GR |
527 | } |
528 | ||
529 | /** | |
fa71ae27 | 530 | * ixgbevf_poll - NAPI polling calback |
92915f71 GR |
531 | * @napi: napi struct with our devices info in it |
532 | * @budget: amount of work driver is allowed to do this pass, in packets | |
533 | * | |
fa71ae27 | 534 | * This function will clean more than one or more rings associated with a |
92915f71 GR |
535 | * q_vector. |
536 | **/ | |
fa71ae27 | 537 | static int ixgbevf_poll(struct napi_struct *napi, int budget) |
92915f71 GR |
538 | { |
539 | struct ixgbevf_q_vector *q_vector = | |
540 | container_of(napi, struct ixgbevf_q_vector, napi); | |
541 | struct ixgbevf_adapter *adapter = q_vector->adapter; | |
fa71ae27 AD |
542 | struct ixgbevf_ring *ring; |
543 | int per_ring_budget; | |
544 | bool clean_complete = true; | |
545 | ||
546 | ixgbevf_for_each_ring(ring, q_vector->tx) | |
547 | clean_complete &= ixgbevf_clean_tx_irq(q_vector, ring); | |
92915f71 GR |
548 | |
549 | /* attempt to distribute budget to each queue fairly, but don't allow | |
550 | * the budget to go below 1 because we'll exit polling */ | |
fa71ae27 AD |
551 | if (q_vector->rx.count > 1) |
552 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
553 | else | |
554 | per_ring_budget = budget; | |
555 | ||
366c1099 | 556 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
fa71ae27 AD |
557 | ixgbevf_for_each_ring(ring, q_vector->rx) |
558 | clean_complete &= ixgbevf_clean_rx_irq(q_vector, ring, | |
559 | per_ring_budget); | |
366c1099 | 560 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
fa71ae27 AD |
561 | |
562 | /* If all work not completed, return budget and keep polling */ | |
563 | if (!clean_complete) | |
564 | return budget; | |
565 | /* all work done, exit the polling mode */ | |
566 | napi_complete(napi); | |
567 | if (adapter->rx_itr_setting & 1) | |
568 | ixgbevf_set_itr(q_vector); | |
569 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state)) | |
570 | ixgbevf_irq_enable_queues(adapter, | |
571 | 1 << q_vector->v_idx); | |
92915f71 | 572 | |
fa71ae27 | 573 | return 0; |
92915f71 GR |
574 | } |
575 | ||
ce422606 GR |
576 | /** |
577 | * ixgbevf_write_eitr - write VTEITR register in hardware specific way | |
578 | * @q_vector: structure containing interrupt and ring information | |
579 | */ | |
580 | static void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector) | |
581 | { | |
582 | struct ixgbevf_adapter *adapter = q_vector->adapter; | |
583 | struct ixgbe_hw *hw = &adapter->hw; | |
584 | int v_idx = q_vector->v_idx; | |
585 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; | |
586 | ||
587 | /* | |
588 | * set the WDIS bit to not clear the timer bits and cause an | |
589 | * immediate assertion of the interrupt | |
590 | */ | |
591 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
592 | ||
593 | IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg); | |
594 | } | |
92915f71 GR |
595 | |
596 | /** | |
597 | * ixgbevf_configure_msix - Configure MSI-X hardware | |
598 | * @adapter: board private structure | |
599 | * | |
600 | * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X | |
601 | * interrupts. | |
602 | **/ | |
603 | static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter) | |
604 | { | |
605 | struct ixgbevf_q_vector *q_vector; | |
6b43c446 | 606 | int q_vectors, v_idx; |
92915f71 GR |
607 | |
608 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
5f3600eb | 609 | adapter->eims_enable_mask = 0; |
92915f71 GR |
610 | |
611 | /* | |
612 | * Populate the IVAR table and set the ITR values to the | |
613 | * corresponding register. | |
614 | */ | |
615 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
6b43c446 | 616 | struct ixgbevf_ring *ring; |
92915f71 | 617 | q_vector = adapter->q_vector[v_idx]; |
6b43c446 AD |
618 | |
619 | ixgbevf_for_each_ring(ring, q_vector->rx) | |
620 | ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); | |
621 | ||
622 | ixgbevf_for_each_ring(ring, q_vector->tx) | |
623 | ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); | |
92915f71 | 624 | |
5f3600eb AD |
625 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
626 | /* tx only vector */ | |
627 | if (adapter->tx_itr_setting == 1) | |
628 | q_vector->itr = IXGBE_10K_ITR; | |
629 | else | |
630 | q_vector->itr = adapter->tx_itr_setting; | |
631 | } else { | |
632 | /* rx or rx/tx vector */ | |
633 | if (adapter->rx_itr_setting == 1) | |
634 | q_vector->itr = IXGBE_20K_ITR; | |
635 | else | |
636 | q_vector->itr = adapter->rx_itr_setting; | |
637 | } | |
638 | ||
639 | /* add q_vector eims value to global eims_enable_mask */ | |
640 | adapter->eims_enable_mask |= 1 << v_idx; | |
92915f71 | 641 | |
5f3600eb | 642 | ixgbevf_write_eitr(q_vector); |
92915f71 GR |
643 | } |
644 | ||
645 | ixgbevf_set_ivar(adapter, -1, 1, v_idx); | |
5f3600eb AD |
646 | /* setup eims_other and add value to global eims_enable_mask */ |
647 | adapter->eims_other = 1 << v_idx; | |
648 | adapter->eims_enable_mask |= adapter->eims_other; | |
92915f71 GR |
649 | } |
650 | ||
651 | enum latency_range { | |
652 | lowest_latency = 0, | |
653 | low_latency = 1, | |
654 | bulk_latency = 2, | |
655 | latency_invalid = 255 | |
656 | }; | |
657 | ||
658 | /** | |
659 | * ixgbevf_update_itr - update the dynamic ITR value based on statistics | |
5f3600eb AD |
660 | * @q_vector: structure containing interrupt and ring information |
661 | * @ring_container: structure containing ring performance data | |
92915f71 GR |
662 | * |
663 | * Stores a new ITR value based on packets and byte | |
664 | * counts during the last interrupt. The advantage of per interrupt | |
665 | * computation is faster updates and more accurate ITR for the current | |
666 | * traffic pattern. Constants in this function were computed | |
667 | * based on theoretical maximum wire speed and thresholds were set based | |
668 | * on testing data as well as attempting to minimize response time | |
669 | * while increasing bulk throughput. | |
670 | **/ | |
5f3600eb AD |
671 | static void ixgbevf_update_itr(struct ixgbevf_q_vector *q_vector, |
672 | struct ixgbevf_ring_container *ring_container) | |
92915f71 | 673 | { |
5f3600eb AD |
674 | int bytes = ring_container->total_bytes; |
675 | int packets = ring_container->total_packets; | |
92915f71 GR |
676 | u32 timepassed_us; |
677 | u64 bytes_perint; | |
5f3600eb | 678 | u8 itr_setting = ring_container->itr; |
92915f71 GR |
679 | |
680 | if (packets == 0) | |
5f3600eb | 681 | return; |
92915f71 GR |
682 | |
683 | /* simple throttlerate management | |
684 | * 0-20MB/s lowest (100000 ints/s) | |
685 | * 20-100MB/s low (20000 ints/s) | |
686 | * 100-1249MB/s bulk (8000 ints/s) | |
687 | */ | |
688 | /* what was last interrupt timeslice? */ | |
5f3600eb | 689 | timepassed_us = q_vector->itr >> 2; |
92915f71 GR |
690 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
691 | ||
692 | switch (itr_setting) { | |
693 | case lowest_latency: | |
e2c28ce7 | 694 | if (bytes_perint > 10) |
5f3600eb | 695 | itr_setting = low_latency; |
92915f71 GR |
696 | break; |
697 | case low_latency: | |
e2c28ce7 | 698 | if (bytes_perint > 20) |
5f3600eb | 699 | itr_setting = bulk_latency; |
e2c28ce7 | 700 | else if (bytes_perint <= 10) |
5f3600eb | 701 | itr_setting = lowest_latency; |
92915f71 GR |
702 | break; |
703 | case bulk_latency: | |
e2c28ce7 | 704 | if (bytes_perint <= 20) |
5f3600eb | 705 | itr_setting = low_latency; |
92915f71 GR |
706 | break; |
707 | } | |
708 | ||
5f3600eb AD |
709 | /* clear work counters since we have the values we need */ |
710 | ring_container->total_bytes = 0; | |
711 | ring_container->total_packets = 0; | |
712 | ||
713 | /* write updated itr to ring container */ | |
714 | ring_container->itr = itr_setting; | |
92915f71 GR |
715 | } |
716 | ||
fa71ae27 | 717 | static void ixgbevf_set_itr(struct ixgbevf_q_vector *q_vector) |
92915f71 | 718 | { |
5f3600eb AD |
719 | u32 new_itr = q_vector->itr; |
720 | u8 current_itr; | |
92915f71 | 721 | |
5f3600eb AD |
722 | ixgbevf_update_itr(q_vector, &q_vector->tx); |
723 | ixgbevf_update_itr(q_vector, &q_vector->rx); | |
92915f71 | 724 | |
6b43c446 | 725 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
92915f71 GR |
726 | |
727 | switch (current_itr) { | |
728 | /* counts and packets in update_itr are dependent on these numbers */ | |
729 | case lowest_latency: | |
5f3600eb | 730 | new_itr = IXGBE_100K_ITR; |
92915f71 GR |
731 | break; |
732 | case low_latency: | |
5f3600eb | 733 | new_itr = IXGBE_20K_ITR; |
92915f71 GR |
734 | break; |
735 | case bulk_latency: | |
736 | default: | |
5f3600eb | 737 | new_itr = IXGBE_8K_ITR; |
92915f71 GR |
738 | break; |
739 | } | |
740 | ||
5f3600eb | 741 | if (new_itr != q_vector->itr) { |
92915f71 | 742 | /* do an exponential smoothing */ |
5f3600eb AD |
743 | new_itr = (10 * new_itr * q_vector->itr) / |
744 | ((9 * new_itr) + q_vector->itr); | |
745 | ||
746 | /* save the algorithm value here */ | |
747 | q_vector->itr = new_itr; | |
748 | ||
749 | ixgbevf_write_eitr(q_vector); | |
92915f71 | 750 | } |
92915f71 GR |
751 | } |
752 | ||
4b2cd27f | 753 | static irqreturn_t ixgbevf_msix_other(int irq, void *data) |
92915f71 | 754 | { |
fa71ae27 | 755 | struct ixgbevf_adapter *adapter = data; |
92915f71 | 756 | struct ixgbe_hw *hw = &adapter->hw; |
08259594 | 757 | |
4b2cd27f | 758 | hw->mac.get_link_status = 1; |
a9ee25a2 | 759 | |
4b2cd27f AD |
760 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state)) |
761 | mod_timer(&adapter->watchdog_timer, jiffies); | |
3a2c4033 | 762 | |
5f3600eb AD |
763 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_other); |
764 | ||
92915f71 GR |
765 | return IRQ_HANDLED; |
766 | } | |
767 | ||
92915f71 GR |
768 | |
769 | /** | |
fa71ae27 | 770 | * ixgbevf_msix_clean_rings - single unshared vector rx clean (all queues) |
92915f71 GR |
771 | * @irq: unused |
772 | * @data: pointer to our q_vector struct for this interrupt vector | |
773 | **/ | |
fa71ae27 | 774 | static irqreturn_t ixgbevf_msix_clean_rings(int irq, void *data) |
92915f71 GR |
775 | { |
776 | struct ixgbevf_q_vector *q_vector = data; | |
92915f71 | 777 | |
5f3600eb | 778 | /* EIAM disabled interrupts (on this vector) for us */ |
fa71ae27 AD |
779 | if (q_vector->rx.ring || q_vector->tx.ring) |
780 | napi_schedule(&q_vector->napi); | |
92915f71 GR |
781 | |
782 | return IRQ_HANDLED; | |
783 | } | |
784 | ||
785 | static inline void map_vector_to_rxq(struct ixgbevf_adapter *a, int v_idx, | |
786 | int r_idx) | |
787 | { | |
788 | struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx]; | |
789 | ||
6b43c446 AD |
790 | a->rx_ring[r_idx].next = q_vector->rx.ring; |
791 | q_vector->rx.ring = &a->rx_ring[r_idx]; | |
792 | q_vector->rx.count++; | |
92915f71 GR |
793 | } |
794 | ||
795 | static inline void map_vector_to_txq(struct ixgbevf_adapter *a, int v_idx, | |
796 | int t_idx) | |
797 | { | |
798 | struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx]; | |
799 | ||
6b43c446 AD |
800 | a->tx_ring[t_idx].next = q_vector->tx.ring; |
801 | q_vector->tx.ring = &a->tx_ring[t_idx]; | |
802 | q_vector->tx.count++; | |
92915f71 GR |
803 | } |
804 | ||
805 | /** | |
806 | * ixgbevf_map_rings_to_vectors - Maps descriptor rings to vectors | |
807 | * @adapter: board private structure to initialize | |
808 | * | |
809 | * This function maps descriptor rings to the queue-specific vectors | |
810 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
811 | * one vector per ring/queue, but on a constrained vector budget, we | |
812 | * group the rings as "efficiently" as possible. You would add new | |
813 | * mapping configurations in here. | |
814 | **/ | |
815 | static int ixgbevf_map_rings_to_vectors(struct ixgbevf_adapter *adapter) | |
816 | { | |
817 | int q_vectors; | |
818 | int v_start = 0; | |
819 | int rxr_idx = 0, txr_idx = 0; | |
820 | int rxr_remaining = adapter->num_rx_queues; | |
821 | int txr_remaining = adapter->num_tx_queues; | |
822 | int i, j; | |
823 | int rqpv, tqpv; | |
824 | int err = 0; | |
825 | ||
826 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
827 | ||
828 | /* | |
829 | * The ideal configuration... | |
830 | * We have enough vectors to map one per queue. | |
831 | */ | |
832 | if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
833 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
834 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
835 | ||
836 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) | |
837 | map_vector_to_txq(adapter, v_start, txr_idx); | |
838 | goto out; | |
839 | } | |
840 | ||
841 | /* | |
842 | * If we don't have enough vectors for a 1-to-1 | |
843 | * mapping, we'll have to group them so there are | |
844 | * multiple queues per vector. | |
845 | */ | |
846 | /* Re-adjusting *qpv takes care of the remainder. */ | |
847 | for (i = v_start; i < q_vectors; i++) { | |
848 | rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i); | |
849 | for (j = 0; j < rqpv; j++) { | |
850 | map_vector_to_rxq(adapter, i, rxr_idx); | |
851 | rxr_idx++; | |
852 | rxr_remaining--; | |
853 | } | |
854 | } | |
855 | for (i = v_start; i < q_vectors; i++) { | |
856 | tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i); | |
857 | for (j = 0; j < tqpv; j++) { | |
858 | map_vector_to_txq(adapter, i, txr_idx); | |
859 | txr_idx++; | |
860 | txr_remaining--; | |
861 | } | |
862 | } | |
863 | ||
864 | out: | |
865 | return err; | |
866 | } | |
867 | ||
868 | /** | |
869 | * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts | |
870 | * @adapter: board private structure | |
871 | * | |
872 | * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests | |
873 | * interrupts from the kernel. | |
874 | **/ | |
875 | static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter) | |
876 | { | |
877 | struct net_device *netdev = adapter->netdev; | |
fa71ae27 AD |
878 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
879 | int vector, err; | |
92915f71 GR |
880 | int ri = 0, ti = 0; |
881 | ||
92915f71 | 882 | for (vector = 0; vector < q_vectors; vector++) { |
fa71ae27 AD |
883 | struct ixgbevf_q_vector *q_vector = adapter->q_vector[vector]; |
884 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
885 | ||
886 | if (q_vector->tx.ring && q_vector->rx.ring) { | |
887 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, | |
888 | "%s-%s-%d", netdev->name, "TxRx", ri++); | |
889 | ti++; | |
890 | } else if (q_vector->rx.ring) { | |
891 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, | |
892 | "%s-%s-%d", netdev->name, "rx", ri++); | |
893 | } else if (q_vector->tx.ring) { | |
894 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, | |
895 | "%s-%s-%d", netdev->name, "tx", ti++); | |
92915f71 GR |
896 | } else { |
897 | /* skip this unused q_vector */ | |
898 | continue; | |
899 | } | |
fa71ae27 AD |
900 | err = request_irq(entry->vector, &ixgbevf_msix_clean_rings, 0, |
901 | q_vector->name, q_vector); | |
92915f71 GR |
902 | if (err) { |
903 | hw_dbg(&adapter->hw, | |
904 | "request_irq failed for MSIX interrupt " | |
905 | "Error: %d\n", err); | |
906 | goto free_queue_irqs; | |
907 | } | |
908 | } | |
909 | ||
92915f71 | 910 | err = request_irq(adapter->msix_entries[vector].vector, |
4b2cd27f | 911 | &ixgbevf_msix_other, 0, netdev->name, adapter); |
92915f71 GR |
912 | if (err) { |
913 | hw_dbg(&adapter->hw, | |
4b2cd27f | 914 | "request_irq for msix_other failed: %d\n", err); |
92915f71 GR |
915 | goto free_queue_irqs; |
916 | } | |
917 | ||
918 | return 0; | |
919 | ||
920 | free_queue_irqs: | |
fa71ae27 AD |
921 | while (vector) { |
922 | vector--; | |
923 | free_irq(adapter->msix_entries[vector].vector, | |
924 | adapter->q_vector[vector]); | |
925 | } | |
92915f71 GR |
926 | pci_disable_msix(adapter->pdev); |
927 | kfree(adapter->msix_entries); | |
928 | adapter->msix_entries = NULL; | |
929 | return err; | |
930 | } | |
931 | ||
932 | static inline void ixgbevf_reset_q_vectors(struct ixgbevf_adapter *adapter) | |
933 | { | |
934 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
935 | ||
936 | for (i = 0; i < q_vectors; i++) { | |
937 | struct ixgbevf_q_vector *q_vector = adapter->q_vector[i]; | |
6b43c446 AD |
938 | q_vector->rx.ring = NULL; |
939 | q_vector->tx.ring = NULL; | |
940 | q_vector->rx.count = 0; | |
941 | q_vector->tx.count = 0; | |
92915f71 GR |
942 | } |
943 | } | |
944 | ||
945 | /** | |
946 | * ixgbevf_request_irq - initialize interrupts | |
947 | * @adapter: board private structure | |
948 | * | |
949 | * Attempts to configure interrupts using the best available | |
950 | * capabilities of the hardware and kernel. | |
951 | **/ | |
952 | static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter) | |
953 | { | |
954 | int err = 0; | |
955 | ||
956 | err = ixgbevf_request_msix_irqs(adapter); | |
957 | ||
958 | if (err) | |
959 | hw_dbg(&adapter->hw, | |
960 | "request_irq failed, Error %d\n", err); | |
961 | ||
962 | return err; | |
963 | } | |
964 | ||
965 | static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter) | |
966 | { | |
92915f71 GR |
967 | int i, q_vectors; |
968 | ||
969 | q_vectors = adapter->num_msix_vectors; | |
92915f71 GR |
970 | i = q_vectors - 1; |
971 | ||
fa71ae27 | 972 | free_irq(adapter->msix_entries[i].vector, adapter); |
92915f71 GR |
973 | i--; |
974 | ||
975 | for (; i >= 0; i--) { | |
fa71ae27 AD |
976 | /* free only the irqs that were actually requested */ |
977 | if (!adapter->q_vector[i]->rx.ring && | |
978 | !adapter->q_vector[i]->tx.ring) | |
979 | continue; | |
980 | ||
92915f71 GR |
981 | free_irq(adapter->msix_entries[i].vector, |
982 | adapter->q_vector[i]); | |
983 | } | |
984 | ||
985 | ixgbevf_reset_q_vectors(adapter); | |
986 | } | |
987 | ||
988 | /** | |
989 | * ixgbevf_irq_disable - Mask off interrupt generation on the NIC | |
990 | * @adapter: board private structure | |
991 | **/ | |
992 | static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter) | |
993 | { | |
92915f71 | 994 | struct ixgbe_hw *hw = &adapter->hw; |
5f3600eb | 995 | int i; |
92915f71 | 996 | |
5f3600eb | 997 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, 0); |
92915f71 | 998 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0); |
5f3600eb | 999 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, 0); |
92915f71 GR |
1000 | |
1001 | IXGBE_WRITE_FLUSH(hw); | |
1002 | ||
1003 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1004 | synchronize_irq(adapter->msix_entries[i].vector); | |
1005 | } | |
1006 | ||
1007 | /** | |
1008 | * ixgbevf_irq_enable - Enable default interrupt generation settings | |
1009 | * @adapter: board private structure | |
1010 | **/ | |
5f3600eb | 1011 | static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter) |
92915f71 GR |
1012 | { |
1013 | struct ixgbe_hw *hw = &adapter->hw; | |
92915f71 | 1014 | |
5f3600eb AD |
1015 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, adapter->eims_enable_mask); |
1016 | IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, adapter->eims_enable_mask); | |
1017 | IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, adapter->eims_enable_mask); | |
92915f71 GR |
1018 | } |
1019 | ||
1020 | /** | |
1021 | * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset | |
1022 | * @adapter: board private structure | |
1023 | * | |
1024 | * Configure the Tx unit of the MAC after a reset. | |
1025 | **/ | |
1026 | static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter) | |
1027 | { | |
1028 | u64 tdba; | |
1029 | struct ixgbe_hw *hw = &adapter->hw; | |
1030 | u32 i, j, tdlen, txctrl; | |
1031 | ||
1032 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1033 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1034 | struct ixgbevf_ring *ring = &adapter->tx_ring[i]; | |
1035 | j = ring->reg_idx; | |
1036 | tdba = ring->dma; | |
1037 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
1038 | IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j), | |
1039 | (tdba & DMA_BIT_MASK(32))); | |
1040 | IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32)); | |
1041 | IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j), tdlen); | |
1042 | IXGBE_WRITE_REG(hw, IXGBE_VFTDH(j), 0); | |
1043 | IXGBE_WRITE_REG(hw, IXGBE_VFTDT(j), 0); | |
1044 | adapter->tx_ring[i].head = IXGBE_VFTDH(j); | |
1045 | adapter->tx_ring[i].tail = IXGBE_VFTDT(j); | |
1046 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1047 | * bookkeeping if things aren't delivered in order. | |
1048 | */ | |
1049 | txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(j)); | |
1050 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; | |
1051 | IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(j), txctrl); | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 | |
1056 | ||
1057 | static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, int index) | |
1058 | { | |
1059 | struct ixgbevf_ring *rx_ring; | |
1060 | struct ixgbe_hw *hw = &adapter->hw; | |
1061 | u32 srrctl; | |
1062 | ||
1063 | rx_ring = &adapter->rx_ring[index]; | |
1064 | ||
1065 | srrctl = IXGBE_SRRCTL_DROP_EN; | |
1066 | ||
77d5dfca | 1067 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
92915f71 | 1068 | |
dd1fe113 AD |
1069 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
1070 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1071 | ||
92915f71 GR |
1072 | IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl); |
1073 | } | |
1074 | ||
dd1fe113 AD |
1075 | static void ixgbevf_set_rx_buffer_len(struct ixgbevf_adapter *adapter) |
1076 | { | |
1077 | struct ixgbe_hw *hw = &adapter->hw; | |
1078 | struct net_device *netdev = adapter->netdev; | |
1079 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
1080 | int i; | |
1081 | u16 rx_buf_len; | |
1082 | ||
1083 | /* notify the PF of our intent to use this size of frame */ | |
1084 | ixgbevf_rlpml_set_vf(hw, max_frame); | |
1085 | ||
1086 | /* PF will allow an extra 4 bytes past for vlan tagged frames */ | |
1087 | max_frame += VLAN_HLEN; | |
1088 | ||
1089 | /* | |
85624caf GR |
1090 | * Allocate buffer sizes that fit well into 32K and |
1091 | * take into account max frame size of 9.5K | |
dd1fe113 AD |
1092 | */ |
1093 | if ((hw->mac.type == ixgbe_mac_X540_vf) && | |
1094 | (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE)) | |
1095 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
85624caf GR |
1096 | else if (max_frame <= IXGBEVF_RXBUFFER_2K) |
1097 | rx_buf_len = IXGBEVF_RXBUFFER_2K; | |
1098 | else if (max_frame <= IXGBEVF_RXBUFFER_4K) | |
1099 | rx_buf_len = IXGBEVF_RXBUFFER_4K; | |
1100 | else if (max_frame <= IXGBEVF_RXBUFFER_8K) | |
1101 | rx_buf_len = IXGBEVF_RXBUFFER_8K; | |
dd1fe113 | 1102 | else |
85624caf | 1103 | rx_buf_len = IXGBEVF_RXBUFFER_10K; |
dd1fe113 AD |
1104 | |
1105 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1106 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
1107 | } | |
1108 | ||
92915f71 GR |
1109 | /** |
1110 | * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset | |
1111 | * @adapter: board private structure | |
1112 | * | |
1113 | * Configure the Rx unit of the MAC after a reset. | |
1114 | **/ | |
1115 | static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter) | |
1116 | { | |
1117 | u64 rdba; | |
1118 | struct ixgbe_hw *hw = &adapter->hw; | |
92915f71 GR |
1119 | int i, j; |
1120 | u32 rdlen; | |
92915f71 | 1121 | |
77d5dfca AD |
1122 | /* PSRTYPE must be initialized in 82599 */ |
1123 | IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); | |
dd1fe113 AD |
1124 | |
1125 | /* set_rx_buffer_len must be called before ring initialization */ | |
1126 | ixgbevf_set_rx_buffer_len(adapter); | |
92915f71 GR |
1127 | |
1128 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); | |
1129 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1130 | * the Base and Length of the Rx Descriptor Ring */ | |
1131 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1132 | rdba = adapter->rx_ring[i].dma; | |
1133 | j = adapter->rx_ring[i].reg_idx; | |
1134 | IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(j), | |
1135 | (rdba & DMA_BIT_MASK(32))); | |
1136 | IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(j), (rdba >> 32)); | |
1137 | IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(j), rdlen); | |
1138 | IXGBE_WRITE_REG(hw, IXGBE_VFRDH(j), 0); | |
1139 | IXGBE_WRITE_REG(hw, IXGBE_VFRDT(j), 0); | |
1140 | adapter->rx_ring[i].head = IXGBE_VFRDH(j); | |
1141 | adapter->rx_ring[i].tail = IXGBE_VFRDT(j); | |
92915f71 GR |
1142 | |
1143 | ixgbevf_configure_srrctl(adapter, j); | |
1144 | } | |
1145 | } | |
1146 | ||
8e586137 | 1147 | static int ixgbevf_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
92915f71 GR |
1148 | { |
1149 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
1150 | struct ixgbe_hw *hw = &adapter->hw; | |
2ddc7fe1 AD |
1151 | int err; |
1152 | ||
1153 | if (!hw->mac.ops.set_vfta) | |
1154 | return -EOPNOTSUPP; | |
92915f71 | 1155 | |
55fdd45b | 1156 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 1157 | |
92915f71 | 1158 | /* add VID to filter table */ |
2ddc7fe1 | 1159 | err = hw->mac.ops.set_vfta(hw, vid, 0, true); |
1c55ed76 | 1160 | |
55fdd45b | 1161 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 1162 | |
2ddc7fe1 AD |
1163 | /* translate error return types so error makes sense */ |
1164 | if (err == IXGBE_ERR_MBX) | |
1165 | return -EIO; | |
1166 | ||
1167 | if (err == IXGBE_ERR_INVALID_ARGUMENT) | |
1168 | return -EACCES; | |
1169 | ||
dadcd65f | 1170 | set_bit(vid, adapter->active_vlans); |
8e586137 | 1171 | |
2ddc7fe1 | 1172 | return err; |
92915f71 GR |
1173 | } |
1174 | ||
8e586137 | 1175 | static int ixgbevf_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
92915f71 GR |
1176 | { |
1177 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
1178 | struct ixgbe_hw *hw = &adapter->hw; | |
2ddc7fe1 | 1179 | int err = -EOPNOTSUPP; |
92915f71 | 1180 | |
55fdd45b | 1181 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 1182 | |
92915f71 GR |
1183 | /* remove VID from filter table */ |
1184 | if (hw->mac.ops.set_vfta) | |
2ddc7fe1 | 1185 | err = hw->mac.ops.set_vfta(hw, vid, 0, false); |
1c55ed76 | 1186 | |
55fdd45b | 1187 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 1188 | |
dadcd65f | 1189 | clear_bit(vid, adapter->active_vlans); |
8e586137 | 1190 | |
2ddc7fe1 | 1191 | return err; |
92915f71 GR |
1192 | } |
1193 | ||
1194 | static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter) | |
1195 | { | |
dadcd65f | 1196 | u16 vid; |
92915f71 | 1197 | |
dadcd65f JP |
1198 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
1199 | ixgbevf_vlan_rx_add_vid(adapter->netdev, vid); | |
92915f71 GR |
1200 | } |
1201 | ||
46ec20ff GR |
1202 | static int ixgbevf_write_uc_addr_list(struct net_device *netdev) |
1203 | { | |
1204 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
1205 | struct ixgbe_hw *hw = &adapter->hw; | |
1206 | int count = 0; | |
1207 | ||
1208 | if ((netdev_uc_count(netdev)) > 10) { | |
dbd9636e | 1209 | pr_err("Too many unicast filters - No Space\n"); |
46ec20ff GR |
1210 | return -ENOSPC; |
1211 | } | |
1212 | ||
1213 | if (!netdev_uc_empty(netdev)) { | |
1214 | struct netdev_hw_addr *ha; | |
1215 | netdev_for_each_uc_addr(ha, netdev) { | |
1216 | hw->mac.ops.set_uc_addr(hw, ++count, ha->addr); | |
1217 | udelay(200); | |
1218 | } | |
1219 | } else { | |
1220 | /* | |
1221 | * If the list is empty then send message to PF driver to | |
1222 | * clear all macvlans on this VF. | |
1223 | */ | |
1224 | hw->mac.ops.set_uc_addr(hw, 0, NULL); | |
1225 | } | |
1226 | ||
1227 | return count; | |
1228 | } | |
1229 | ||
92915f71 GR |
1230 | /** |
1231 | * ixgbevf_set_rx_mode - Multicast set | |
1232 | * @netdev: network interface device structure | |
1233 | * | |
1234 | * The set_rx_method entry point is called whenever the multicast address | |
1235 | * list or the network interface flags are updated. This routine is | |
1236 | * responsible for configuring the hardware for proper multicast mode. | |
1237 | **/ | |
1238 | static void ixgbevf_set_rx_mode(struct net_device *netdev) | |
1239 | { | |
1240 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
1241 | struct ixgbe_hw *hw = &adapter->hw; | |
92915f71 | 1242 | |
55fdd45b | 1243 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 1244 | |
92915f71 | 1245 | /* reprogram multicast list */ |
92915f71 | 1246 | if (hw->mac.ops.update_mc_addr_list) |
5c58c47a | 1247 | hw->mac.ops.update_mc_addr_list(hw, netdev); |
46ec20ff GR |
1248 | |
1249 | ixgbevf_write_uc_addr_list(netdev); | |
1c55ed76 | 1250 | |
55fdd45b | 1251 | spin_unlock_bh(&adapter->mbx_lock); |
92915f71 GR |
1252 | } |
1253 | ||
1254 | static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter) | |
1255 | { | |
1256 | int q_idx; | |
1257 | struct ixgbevf_q_vector *q_vector; | |
1258 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1259 | ||
1260 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
92915f71 | 1261 | q_vector = adapter->q_vector[q_idx]; |
fa71ae27 | 1262 | napi_enable(&q_vector->napi); |
92915f71 GR |
1263 | } |
1264 | } | |
1265 | ||
1266 | static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter) | |
1267 | { | |
1268 | int q_idx; | |
1269 | struct ixgbevf_q_vector *q_vector; | |
1270 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1271 | ||
1272 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
1273 | q_vector = adapter->q_vector[q_idx]; | |
92915f71 GR |
1274 | napi_disable(&q_vector->napi); |
1275 | } | |
1276 | } | |
1277 | ||
1278 | static void ixgbevf_configure(struct ixgbevf_adapter *adapter) | |
1279 | { | |
1280 | struct net_device *netdev = adapter->netdev; | |
1281 | int i; | |
1282 | ||
1283 | ixgbevf_set_rx_mode(netdev); | |
1284 | ||
1285 | ixgbevf_restore_vlan(adapter); | |
1286 | ||
1287 | ixgbevf_configure_tx(adapter); | |
1288 | ixgbevf_configure_rx(adapter); | |
1289 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1290 | struct ixgbevf_ring *ring = &adapter->rx_ring[i]; | |
18c63089 AD |
1291 | ixgbevf_alloc_rx_buffers(adapter, ring, |
1292 | IXGBE_DESC_UNUSED(ring)); | |
92915f71 GR |
1293 | } |
1294 | } | |
1295 | ||
1296 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
1297 | static inline void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter, | |
1298 | int rxr) | |
1299 | { | |
1300 | struct ixgbe_hw *hw = &adapter->hw; | |
1301 | int j = adapter->rx_ring[rxr].reg_idx; | |
1302 | int k; | |
1303 | ||
1304 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
1305 | if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
1306 | break; | |
1307 | else | |
1308 | msleep(1); | |
1309 | } | |
1310 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
1311 | hw_dbg(hw, "RXDCTL.ENABLE on Rx queue %d " | |
1312 | "not set within the polling period\n", rxr); | |
1313 | } | |
1314 | ||
1315 | ixgbevf_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
1316 | (adapter->rx_ring[rxr].count - 1)); | |
1317 | } | |
1318 | ||
33bd9f60 GR |
1319 | static void ixgbevf_save_reset_stats(struct ixgbevf_adapter *adapter) |
1320 | { | |
1321 | /* Only save pre-reset stats if there are some */ | |
1322 | if (adapter->stats.vfgprc || adapter->stats.vfgptc) { | |
1323 | adapter->stats.saved_reset_vfgprc += adapter->stats.vfgprc - | |
1324 | adapter->stats.base_vfgprc; | |
1325 | adapter->stats.saved_reset_vfgptc += adapter->stats.vfgptc - | |
1326 | adapter->stats.base_vfgptc; | |
1327 | adapter->stats.saved_reset_vfgorc += adapter->stats.vfgorc - | |
1328 | adapter->stats.base_vfgorc; | |
1329 | adapter->stats.saved_reset_vfgotc += adapter->stats.vfgotc - | |
1330 | adapter->stats.base_vfgotc; | |
1331 | adapter->stats.saved_reset_vfmprc += adapter->stats.vfmprc - | |
1332 | adapter->stats.base_vfmprc; | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter) | |
1337 | { | |
1338 | struct ixgbe_hw *hw = &adapter->hw; | |
1339 | ||
1340 | adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC); | |
1341 | adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB); | |
1342 | adapter->stats.last_vfgorc |= | |
1343 | (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32); | |
1344 | adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC); | |
1345 | adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB); | |
1346 | adapter->stats.last_vfgotc |= | |
1347 | (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32); | |
1348 | adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC); | |
1349 | ||
1350 | adapter->stats.base_vfgprc = adapter->stats.last_vfgprc; | |
1351 | adapter->stats.base_vfgorc = adapter->stats.last_vfgorc; | |
1352 | adapter->stats.base_vfgptc = adapter->stats.last_vfgptc; | |
1353 | adapter->stats.base_vfgotc = adapter->stats.last_vfgotc; | |
1354 | adapter->stats.base_vfmprc = adapter->stats.last_vfmprc; | |
1355 | } | |
1356 | ||
31186785 AD |
1357 | static void ixgbevf_negotiate_api(struct ixgbevf_adapter *adapter) |
1358 | { | |
1359 | struct ixgbe_hw *hw = &adapter->hw; | |
56e94095 AD |
1360 | int api[] = { ixgbe_mbox_api_11, |
1361 | ixgbe_mbox_api_10, | |
31186785 AD |
1362 | ixgbe_mbox_api_unknown }; |
1363 | int err = 0, idx = 0; | |
1364 | ||
55fdd45b | 1365 | spin_lock_bh(&adapter->mbx_lock); |
31186785 AD |
1366 | |
1367 | while (api[idx] != ixgbe_mbox_api_unknown) { | |
1368 | err = ixgbevf_negotiate_api_version(hw, api[idx]); | |
1369 | if (!err) | |
1370 | break; | |
1371 | idx++; | |
1372 | } | |
1373 | ||
55fdd45b | 1374 | spin_unlock_bh(&adapter->mbx_lock); |
31186785 AD |
1375 | } |
1376 | ||
795180d8 | 1377 | static void ixgbevf_up_complete(struct ixgbevf_adapter *adapter) |
92915f71 GR |
1378 | { |
1379 | struct net_device *netdev = adapter->netdev; | |
1380 | struct ixgbe_hw *hw = &adapter->hw; | |
1381 | int i, j = 0; | |
1382 | int num_rx_rings = adapter->num_rx_queues; | |
1383 | u32 txdctl, rxdctl; | |
1384 | ||
1385 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1386 | j = adapter->tx_ring[i].reg_idx; | |
1387 | txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j)); | |
1388 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ | |
1389 | txdctl |= (8 << 16); | |
1390 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl); | |
1391 | } | |
1392 | ||
1393 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1394 | j = adapter->tx_ring[i].reg_idx; | |
1395 | txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j)); | |
1396 | txdctl |= IXGBE_TXDCTL_ENABLE; | |
1397 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl); | |
1398 | } | |
1399 | ||
1400 | for (i = 0; i < num_rx_rings; i++) { | |
1401 | j = adapter->rx_ring[i].reg_idx; | |
1402 | rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j)); | |
dadcd65f | 1403 | rxdctl |= IXGBE_RXDCTL_ENABLE | IXGBE_RXDCTL_VME; |
69bfbec4 GR |
1404 | if (hw->mac.type == ixgbe_mac_X540_vf) { |
1405 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
1406 | rxdctl |= ((netdev->mtu + ETH_HLEN + ETH_FCS_LEN) | | |
1407 | IXGBE_RXDCTL_RLPML_EN); | |
1408 | } | |
92915f71 GR |
1409 | IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(j), rxdctl); |
1410 | ixgbevf_rx_desc_queue_enable(adapter, i); | |
1411 | } | |
1412 | ||
1413 | ixgbevf_configure_msix(adapter); | |
1414 | ||
55fdd45b | 1415 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 1416 | |
92915f71 GR |
1417 | if (hw->mac.ops.set_rar) { |
1418 | if (is_valid_ether_addr(hw->mac.addr)) | |
1419 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0); | |
1420 | else | |
1421 | hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0); | |
1422 | } | |
1423 | ||
55fdd45b | 1424 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 1425 | |
92915f71 GR |
1426 | clear_bit(__IXGBEVF_DOWN, &adapter->state); |
1427 | ixgbevf_napi_enable_all(adapter); | |
1428 | ||
1429 | /* enable transmits */ | |
1430 | netif_tx_start_all_queues(netdev); | |
1431 | ||
33bd9f60 GR |
1432 | ixgbevf_save_reset_stats(adapter); |
1433 | ixgbevf_init_last_counter_stats(adapter); | |
1434 | ||
4b2cd27f | 1435 | hw->mac.get_link_status = 1; |
92915f71 | 1436 | mod_timer(&adapter->watchdog_timer, jiffies); |
92915f71 GR |
1437 | } |
1438 | ||
56e94095 AD |
1439 | static int ixgbevf_reset_queues(struct ixgbevf_adapter *adapter) |
1440 | { | |
1441 | struct ixgbe_hw *hw = &adapter->hw; | |
1442 | struct ixgbevf_ring *rx_ring; | |
1443 | unsigned int def_q = 0; | |
1444 | unsigned int num_tcs = 0; | |
1445 | unsigned int num_rx_queues = 1; | |
1446 | int err, i; | |
1447 | ||
55fdd45b | 1448 | spin_lock_bh(&adapter->mbx_lock); |
56e94095 AD |
1449 | |
1450 | /* fetch queue configuration from the PF */ | |
1451 | err = ixgbevf_get_queues(hw, &num_tcs, &def_q); | |
1452 | ||
55fdd45b | 1453 | spin_unlock_bh(&adapter->mbx_lock); |
56e94095 AD |
1454 | |
1455 | if (err) | |
1456 | return err; | |
1457 | ||
1458 | if (num_tcs > 1) { | |
1459 | /* update default Tx ring register index */ | |
1460 | adapter->tx_ring[0].reg_idx = def_q; | |
1461 | ||
1462 | /* we need as many queues as traffic classes */ | |
1463 | num_rx_queues = num_tcs; | |
1464 | } | |
1465 | ||
1466 | /* nothing to do if we have the correct number of queues */ | |
1467 | if (adapter->num_rx_queues == num_rx_queues) | |
1468 | return 0; | |
1469 | ||
1470 | /* allocate new rings */ | |
1471 | rx_ring = kcalloc(num_rx_queues, | |
1472 | sizeof(struct ixgbevf_ring), GFP_KERNEL); | |
1473 | if (!rx_ring) | |
1474 | return -ENOMEM; | |
1475 | ||
1476 | /* setup ring fields */ | |
1477 | for (i = 0; i < num_rx_queues; i++) { | |
1478 | rx_ring[i].count = adapter->rx_ring_count; | |
1479 | rx_ring[i].queue_index = i; | |
1480 | rx_ring[i].reg_idx = i; | |
1481 | rx_ring[i].dev = &adapter->pdev->dev; | |
1482 | rx_ring[i].netdev = adapter->netdev; | |
1483 | ||
1484 | /* allocate resources on the ring */ | |
1485 | err = ixgbevf_setup_rx_resources(adapter, &rx_ring[i]); | |
1486 | if (err) { | |
1487 | while (i) { | |
1488 | i--; | |
1489 | ixgbevf_free_rx_resources(adapter, &rx_ring[i]); | |
1490 | } | |
1491 | kfree(rx_ring); | |
1492 | return err; | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | /* free the existing rings and queues */ | |
1497 | ixgbevf_free_all_rx_resources(adapter); | |
1498 | adapter->num_rx_queues = 0; | |
1499 | kfree(adapter->rx_ring); | |
1500 | ||
1501 | /* move new rings into position on the adapter struct */ | |
1502 | adapter->rx_ring = rx_ring; | |
1503 | adapter->num_rx_queues = num_rx_queues; | |
1504 | ||
1505 | /* reset ring to vector mapping */ | |
1506 | ixgbevf_reset_q_vectors(adapter); | |
1507 | ixgbevf_map_rings_to_vectors(adapter); | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
795180d8 | 1512 | void ixgbevf_up(struct ixgbevf_adapter *adapter) |
92915f71 | 1513 | { |
92915f71 GR |
1514 | struct ixgbe_hw *hw = &adapter->hw; |
1515 | ||
31186785 AD |
1516 | ixgbevf_negotiate_api(adapter); |
1517 | ||
56e94095 AD |
1518 | ixgbevf_reset_queues(adapter); |
1519 | ||
92915f71 GR |
1520 | ixgbevf_configure(adapter); |
1521 | ||
795180d8 | 1522 | ixgbevf_up_complete(adapter); |
92915f71 GR |
1523 | |
1524 | /* clear any pending interrupts, may auto mask */ | |
1525 | IXGBE_READ_REG(hw, IXGBE_VTEICR); | |
1526 | ||
5f3600eb | 1527 | ixgbevf_irq_enable(adapter); |
92915f71 GR |
1528 | } |
1529 | ||
1530 | /** | |
1531 | * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue | |
1532 | * @adapter: board private structure | |
1533 | * @rx_ring: ring to free buffers from | |
1534 | **/ | |
1535 | static void ixgbevf_clean_rx_ring(struct ixgbevf_adapter *adapter, | |
1536 | struct ixgbevf_ring *rx_ring) | |
1537 | { | |
1538 | struct pci_dev *pdev = adapter->pdev; | |
1539 | unsigned long size; | |
1540 | unsigned int i; | |
1541 | ||
c0456c23 GR |
1542 | if (!rx_ring->rx_buffer_info) |
1543 | return; | |
92915f71 | 1544 | |
c0456c23 | 1545 | /* Free all the Rx ring sk_buffs */ |
92915f71 GR |
1546 | for (i = 0; i < rx_ring->count; i++) { |
1547 | struct ixgbevf_rx_buffer *rx_buffer_info; | |
1548 | ||
1549 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
1550 | if (rx_buffer_info->dma) { | |
2a1f8794 | 1551 | dma_unmap_single(&pdev->dev, rx_buffer_info->dma, |
92915f71 | 1552 | rx_ring->rx_buf_len, |
2a1f8794 | 1553 | DMA_FROM_DEVICE); |
92915f71 GR |
1554 | rx_buffer_info->dma = 0; |
1555 | } | |
1556 | if (rx_buffer_info->skb) { | |
1557 | struct sk_buff *skb = rx_buffer_info->skb; | |
1558 | rx_buffer_info->skb = NULL; | |
1559 | do { | |
1560 | struct sk_buff *this = skb; | |
5c60f81a | 1561 | skb = IXGBE_CB(skb)->prev; |
92915f71 GR |
1562 | dev_kfree_skb(this); |
1563 | } while (skb); | |
1564 | } | |
92915f71 GR |
1565 | } |
1566 | ||
1567 | size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count; | |
1568 | memset(rx_ring->rx_buffer_info, 0, size); | |
1569 | ||
1570 | /* Zero out the descriptor ring */ | |
1571 | memset(rx_ring->desc, 0, rx_ring->size); | |
1572 | ||
1573 | rx_ring->next_to_clean = 0; | |
1574 | rx_ring->next_to_use = 0; | |
1575 | ||
1576 | if (rx_ring->head) | |
1577 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
1578 | if (rx_ring->tail) | |
1579 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
1580 | } | |
1581 | ||
1582 | /** | |
1583 | * ixgbevf_clean_tx_ring - Free Tx Buffers | |
1584 | * @adapter: board private structure | |
1585 | * @tx_ring: ring to be cleaned | |
1586 | **/ | |
1587 | static void ixgbevf_clean_tx_ring(struct ixgbevf_adapter *adapter, | |
1588 | struct ixgbevf_ring *tx_ring) | |
1589 | { | |
1590 | struct ixgbevf_tx_buffer *tx_buffer_info; | |
1591 | unsigned long size; | |
1592 | unsigned int i; | |
1593 | ||
c0456c23 GR |
1594 | if (!tx_ring->tx_buffer_info) |
1595 | return; | |
1596 | ||
92915f71 GR |
1597 | /* Free all the Tx ring sk_buffs */ |
1598 | ||
1599 | for (i = 0; i < tx_ring->count; i++) { | |
1600 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
70a10e25 | 1601 | ixgbevf_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
92915f71 GR |
1602 | } |
1603 | ||
1604 | size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count; | |
1605 | memset(tx_ring->tx_buffer_info, 0, size); | |
1606 | ||
1607 | memset(tx_ring->desc, 0, tx_ring->size); | |
1608 | ||
1609 | tx_ring->next_to_use = 0; | |
1610 | tx_ring->next_to_clean = 0; | |
1611 | ||
1612 | if (tx_ring->head) | |
1613 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
1614 | if (tx_ring->tail) | |
1615 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
1616 | } | |
1617 | ||
1618 | /** | |
1619 | * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues | |
1620 | * @adapter: board private structure | |
1621 | **/ | |
1622 | static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter) | |
1623 | { | |
1624 | int i; | |
1625 | ||
1626 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1627 | ixgbevf_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
1628 | } | |
1629 | ||
1630 | /** | |
1631 | * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues | |
1632 | * @adapter: board private structure | |
1633 | **/ | |
1634 | static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter) | |
1635 | { | |
1636 | int i; | |
1637 | ||
1638 | for (i = 0; i < adapter->num_tx_queues; i++) | |
1639 | ixgbevf_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
1640 | } | |
1641 | ||
1642 | void ixgbevf_down(struct ixgbevf_adapter *adapter) | |
1643 | { | |
1644 | struct net_device *netdev = adapter->netdev; | |
1645 | struct ixgbe_hw *hw = &adapter->hw; | |
1646 | u32 txdctl; | |
1647 | int i, j; | |
1648 | ||
1649 | /* signal that we are down to the interrupt handler */ | |
1650 | set_bit(__IXGBEVF_DOWN, &adapter->state); | |
1651 | /* disable receives */ | |
1652 | ||
1653 | netif_tx_disable(netdev); | |
1654 | ||
1655 | msleep(10); | |
1656 | ||
1657 | netif_tx_stop_all_queues(netdev); | |
1658 | ||
1659 | ixgbevf_irq_disable(adapter); | |
1660 | ||
1661 | ixgbevf_napi_disable_all(adapter); | |
1662 | ||
1663 | del_timer_sync(&adapter->watchdog_timer); | |
1664 | /* can't call flush scheduled work here because it can deadlock | |
1665 | * if linkwatch_event tries to acquire the rtnl_lock which we are | |
1666 | * holding */ | |
1667 | while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK) | |
1668 | msleep(1); | |
1669 | ||
1670 | /* disable transmits in the hardware now that interrupts are off */ | |
1671 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1672 | j = adapter->tx_ring[i].reg_idx; | |
1673 | txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j)); | |
1674 | IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), | |
1675 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
1676 | } | |
1677 | ||
1678 | netif_carrier_off(netdev); | |
1679 | ||
1680 | if (!pci_channel_offline(adapter->pdev)) | |
1681 | ixgbevf_reset(adapter); | |
1682 | ||
1683 | ixgbevf_clean_all_tx_rings(adapter); | |
1684 | ixgbevf_clean_all_rx_rings(adapter); | |
1685 | } | |
1686 | ||
1687 | void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter) | |
1688 | { | |
1689 | WARN_ON(in_interrupt()); | |
c0456c23 | 1690 | |
92915f71 GR |
1691 | while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state)) |
1692 | msleep(1); | |
1693 | ||
c0456c23 GR |
1694 | /* |
1695 | * Check if PF is up before re-init. If not then skip until | |
1696 | * later when the PF is up and ready to service requests from | |
1697 | * the VF via mailbox. If the VF is up and running then the | |
1698 | * watchdog task will continue to schedule reset tasks until | |
1699 | * the PF is up and running. | |
1700 | */ | |
4b2cd27f AD |
1701 | ixgbevf_down(adapter); |
1702 | ixgbevf_up(adapter); | |
92915f71 GR |
1703 | |
1704 | clear_bit(__IXGBEVF_RESETTING, &adapter->state); | |
1705 | } | |
1706 | ||
1707 | void ixgbevf_reset(struct ixgbevf_adapter *adapter) | |
1708 | { | |
1709 | struct ixgbe_hw *hw = &adapter->hw; | |
1710 | struct net_device *netdev = adapter->netdev; | |
1711 | ||
55fdd45b | 1712 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 1713 | |
92915f71 GR |
1714 | if (hw->mac.ops.reset_hw(hw)) |
1715 | hw_dbg(hw, "PF still resetting\n"); | |
1716 | else | |
1717 | hw->mac.ops.init_hw(hw); | |
1718 | ||
55fdd45b | 1719 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 1720 | |
92915f71 GR |
1721 | if (is_valid_ether_addr(adapter->hw.mac.addr)) { |
1722 | memcpy(netdev->dev_addr, adapter->hw.mac.addr, | |
1723 | netdev->addr_len); | |
1724 | memcpy(netdev->perm_addr, adapter->hw.mac.addr, | |
1725 | netdev->addr_len); | |
1726 | } | |
1727 | } | |
1728 | ||
e45dd5fe JK |
1729 | static int ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter, |
1730 | int vectors) | |
92915f71 | 1731 | { |
a5f9337b ET |
1732 | int err = 0; |
1733 | int vector_threshold; | |
92915f71 | 1734 | |
fa71ae27 AD |
1735 | /* We'll want at least 2 (vector_threshold): |
1736 | * 1) TxQ[0] + RxQ[0] handler | |
1737 | * 2) Other (Link Status Change, etc.) | |
92915f71 GR |
1738 | */ |
1739 | vector_threshold = MIN_MSIX_COUNT; | |
1740 | ||
1741 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
1742 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
1743 | * Right now, we simply care about how many we'll get; we'll | |
1744 | * set them up later while requesting irq's. | |
1745 | */ | |
1746 | while (vectors >= vector_threshold) { | |
1747 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
1748 | vectors); | |
e45dd5fe | 1749 | if (!err || err < 0) /* Success or a nasty failure. */ |
92915f71 | 1750 | break; |
92915f71 GR |
1751 | else /* err == number of vectors we should try again with */ |
1752 | vectors = err; | |
1753 | } | |
1754 | ||
e45dd5fe JK |
1755 | if (vectors < vector_threshold) |
1756 | err = -ENOMEM; | |
1757 | ||
1758 | if (err) { | |
1759 | dev_err(&adapter->pdev->dev, | |
1760 | "Unable to allocate MSI-X interrupts\n"); | |
92915f71 GR |
1761 | kfree(adapter->msix_entries); |
1762 | adapter->msix_entries = NULL; | |
1763 | } else { | |
1764 | /* | |
1765 | * Adjust for only the vectors we'll use, which is minimum | |
1766 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
1767 | * vectors we were allocated. | |
1768 | */ | |
1769 | adapter->num_msix_vectors = vectors; | |
1770 | } | |
e45dd5fe | 1771 | return err; |
92915f71 GR |
1772 | } |
1773 | ||
49ce9c2c BH |
1774 | /** |
1775 | * ixgbevf_set_num_queues - Allocate queues for device, feature dependent | |
92915f71 GR |
1776 | * @adapter: board private structure to initialize |
1777 | * | |
1778 | * This is the top level queue allocation routine. The order here is very | |
1779 | * important, starting with the "most" number of features turned on at once, | |
1780 | * and ending with the smallest set of features. This way large combinations | |
1781 | * can be allocated if they're turned on, and smaller combinations are the | |
1782 | * fallthrough conditions. | |
1783 | * | |
1784 | **/ | |
1785 | static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter) | |
1786 | { | |
1787 | /* Start with base case */ | |
1788 | adapter->num_rx_queues = 1; | |
1789 | adapter->num_tx_queues = 1; | |
92915f71 GR |
1790 | } |
1791 | ||
1792 | /** | |
1793 | * ixgbevf_alloc_queues - Allocate memory for all rings | |
1794 | * @adapter: board private structure to initialize | |
1795 | * | |
1796 | * We allocate one ring per queue at run-time since we don't know the | |
1797 | * number of queues at compile-time. The polling_netdev array is | |
1798 | * intended for Multiqueue, but should work fine with a single queue. | |
1799 | **/ | |
1800 | static int ixgbevf_alloc_queues(struct ixgbevf_adapter *adapter) | |
1801 | { | |
1802 | int i; | |
1803 | ||
1804 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
1805 | sizeof(struct ixgbevf_ring), GFP_KERNEL); | |
1806 | if (!adapter->tx_ring) | |
1807 | goto err_tx_ring_allocation; | |
1808 | ||
1809 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
1810 | sizeof(struct ixgbevf_ring), GFP_KERNEL); | |
1811 | if (!adapter->rx_ring) | |
1812 | goto err_rx_ring_allocation; | |
1813 | ||
1814 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1815 | adapter->tx_ring[i].count = adapter->tx_ring_count; | |
1816 | adapter->tx_ring[i].queue_index = i; | |
56e94095 | 1817 | /* reg_idx may be remapped later by DCB config */ |
92915f71 | 1818 | adapter->tx_ring[i].reg_idx = i; |
fb40195c AD |
1819 | adapter->tx_ring[i].dev = &adapter->pdev->dev; |
1820 | adapter->tx_ring[i].netdev = adapter->netdev; | |
92915f71 GR |
1821 | } |
1822 | ||
1823 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1824 | adapter->rx_ring[i].count = adapter->rx_ring_count; | |
1825 | adapter->rx_ring[i].queue_index = i; | |
1826 | adapter->rx_ring[i].reg_idx = i; | |
fb40195c AD |
1827 | adapter->rx_ring[i].dev = &adapter->pdev->dev; |
1828 | adapter->rx_ring[i].netdev = adapter->netdev; | |
92915f71 GR |
1829 | } |
1830 | ||
1831 | return 0; | |
1832 | ||
1833 | err_rx_ring_allocation: | |
1834 | kfree(adapter->tx_ring); | |
1835 | err_tx_ring_allocation: | |
1836 | return -ENOMEM; | |
1837 | } | |
1838 | ||
1839 | /** | |
1840 | * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported | |
1841 | * @adapter: board private structure to initialize | |
1842 | * | |
1843 | * Attempt to configure the interrupts using the best available | |
1844 | * capabilities of the hardware and the kernel. | |
1845 | **/ | |
1846 | static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter) | |
1847 | { | |
91e2b89b | 1848 | struct net_device *netdev = adapter->netdev; |
92915f71 GR |
1849 | int err = 0; |
1850 | int vector, v_budget; | |
1851 | ||
1852 | /* | |
1853 | * It's easy to be greedy for MSI-X vectors, but it really | |
1854 | * doesn't do us much good if we have a lot more vectors | |
1855 | * than CPU's. So let's be conservative and only ask for | |
fa71ae27 AD |
1856 | * (roughly) the same number of vectors as there are CPU's. |
1857 | * The default is to use pairs of vectors. | |
92915f71 | 1858 | */ |
fa71ae27 AD |
1859 | v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); |
1860 | v_budget = min_t(int, v_budget, num_online_cpus()); | |
1861 | v_budget += NON_Q_VECTORS; | |
92915f71 GR |
1862 | |
1863 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
1864 | * mean we disable MSI-X capabilities of the adapter. */ | |
1865 | adapter->msix_entries = kcalloc(v_budget, | |
1866 | sizeof(struct msix_entry), GFP_KERNEL); | |
1867 | if (!adapter->msix_entries) { | |
1868 | err = -ENOMEM; | |
1869 | goto out; | |
1870 | } | |
1871 | ||
1872 | for (vector = 0; vector < v_budget; vector++) | |
1873 | adapter->msix_entries[vector].entry = vector; | |
1874 | ||
e45dd5fe JK |
1875 | err = ixgbevf_acquire_msix_vectors(adapter, v_budget); |
1876 | if (err) | |
1877 | goto out; | |
92915f71 | 1878 | |
91e2b89b GR |
1879 | err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); |
1880 | if (err) | |
1881 | goto out; | |
1882 | ||
1883 | err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); | |
1884 | ||
92915f71 GR |
1885 | out: |
1886 | return err; | |
1887 | } | |
1888 | ||
1889 | /** | |
1890 | * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors | |
1891 | * @adapter: board private structure to initialize | |
1892 | * | |
1893 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
1894 | * return -ENOMEM. | |
1895 | **/ | |
1896 | static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter) | |
1897 | { | |
1898 | int q_idx, num_q_vectors; | |
1899 | struct ixgbevf_q_vector *q_vector; | |
92915f71 GR |
1900 | |
1901 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
92915f71 GR |
1902 | |
1903 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1904 | q_vector = kzalloc(sizeof(struct ixgbevf_q_vector), GFP_KERNEL); | |
1905 | if (!q_vector) | |
1906 | goto err_out; | |
1907 | q_vector->adapter = adapter; | |
1908 | q_vector->v_idx = q_idx; | |
fa71ae27 AD |
1909 | netif_napi_add(adapter->netdev, &q_vector->napi, |
1910 | ixgbevf_poll, 64); | |
92915f71 GR |
1911 | adapter->q_vector[q_idx] = q_vector; |
1912 | } | |
1913 | ||
1914 | return 0; | |
1915 | ||
1916 | err_out: | |
1917 | while (q_idx) { | |
1918 | q_idx--; | |
1919 | q_vector = adapter->q_vector[q_idx]; | |
1920 | netif_napi_del(&q_vector->napi); | |
1921 | kfree(q_vector); | |
1922 | adapter->q_vector[q_idx] = NULL; | |
1923 | } | |
1924 | return -ENOMEM; | |
1925 | } | |
1926 | ||
1927 | /** | |
1928 | * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors | |
1929 | * @adapter: board private structure to initialize | |
1930 | * | |
1931 | * This function frees the memory allocated to the q_vectors. In addition if | |
1932 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1933 | * to freeing the q_vector. | |
1934 | **/ | |
1935 | static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter) | |
1936 | { | |
f4477702 | 1937 | int q_idx, num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
92915f71 GR |
1938 | |
1939 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
1940 | struct ixgbevf_q_vector *q_vector = adapter->q_vector[q_idx]; | |
1941 | ||
1942 | adapter->q_vector[q_idx] = NULL; | |
f4477702 | 1943 | netif_napi_del(&q_vector->napi); |
92915f71 GR |
1944 | kfree(q_vector); |
1945 | } | |
1946 | } | |
1947 | ||
1948 | /** | |
1949 | * ixgbevf_reset_interrupt_capability - Reset MSIX setup | |
1950 | * @adapter: board private structure | |
1951 | * | |
1952 | **/ | |
1953 | static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter) | |
1954 | { | |
1955 | pci_disable_msix(adapter->pdev); | |
1956 | kfree(adapter->msix_entries); | |
1957 | adapter->msix_entries = NULL; | |
92915f71 GR |
1958 | } |
1959 | ||
1960 | /** | |
1961 | * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init | |
1962 | * @adapter: board private structure to initialize | |
1963 | * | |
1964 | **/ | |
1965 | static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter) | |
1966 | { | |
1967 | int err; | |
1968 | ||
1969 | /* Number of supported queues */ | |
1970 | ixgbevf_set_num_queues(adapter); | |
1971 | ||
1972 | err = ixgbevf_set_interrupt_capability(adapter); | |
1973 | if (err) { | |
1974 | hw_dbg(&adapter->hw, | |
1975 | "Unable to setup interrupt capabilities\n"); | |
1976 | goto err_set_interrupt; | |
1977 | } | |
1978 | ||
1979 | err = ixgbevf_alloc_q_vectors(adapter); | |
1980 | if (err) { | |
1981 | hw_dbg(&adapter->hw, "Unable to allocate memory for queue " | |
1982 | "vectors\n"); | |
1983 | goto err_alloc_q_vectors; | |
1984 | } | |
1985 | ||
1986 | err = ixgbevf_alloc_queues(adapter); | |
1987 | if (err) { | |
dbd9636e | 1988 | pr_err("Unable to allocate memory for queues\n"); |
92915f71 GR |
1989 | goto err_alloc_queues; |
1990 | } | |
1991 | ||
1992 | hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, " | |
1993 | "Tx Queue count = %u\n", | |
1994 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
1995 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
1996 | ||
1997 | set_bit(__IXGBEVF_DOWN, &adapter->state); | |
1998 | ||
1999 | return 0; | |
2000 | err_alloc_queues: | |
2001 | ixgbevf_free_q_vectors(adapter); | |
2002 | err_alloc_q_vectors: | |
2003 | ixgbevf_reset_interrupt_capability(adapter); | |
2004 | err_set_interrupt: | |
2005 | return err; | |
2006 | } | |
2007 | ||
0ac1e8ce AD |
2008 | /** |
2009 | * ixgbevf_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
2010 | * @adapter: board private structure to clear interrupt scheme on | |
2011 | * | |
2012 | * We go through and clear interrupt specific resources and reset the structure | |
2013 | * to pre-load conditions | |
2014 | **/ | |
2015 | static void ixgbevf_clear_interrupt_scheme(struct ixgbevf_adapter *adapter) | |
2016 | { | |
2017 | adapter->num_tx_queues = 0; | |
2018 | adapter->num_rx_queues = 0; | |
2019 | ||
2020 | ixgbevf_free_q_vectors(adapter); | |
2021 | ixgbevf_reset_interrupt_capability(adapter); | |
2022 | } | |
2023 | ||
92915f71 GR |
2024 | /** |
2025 | * ixgbevf_sw_init - Initialize general software structures | |
2026 | * (struct ixgbevf_adapter) | |
2027 | * @adapter: board private structure to initialize | |
2028 | * | |
2029 | * ixgbevf_sw_init initializes the Adapter private data structure. | |
2030 | * Fields are initialized based on PCI device information and | |
2031 | * OS network device settings (MTU size). | |
2032 | **/ | |
2033 | static int __devinit ixgbevf_sw_init(struct ixgbevf_adapter *adapter) | |
2034 | { | |
2035 | struct ixgbe_hw *hw = &adapter->hw; | |
2036 | struct pci_dev *pdev = adapter->pdev; | |
2037 | int err; | |
2038 | ||
2039 | /* PCI config space info */ | |
2040 | ||
2041 | hw->vendor_id = pdev->vendor; | |
2042 | hw->device_id = pdev->device; | |
ff938e43 | 2043 | hw->revision_id = pdev->revision; |
92915f71 GR |
2044 | hw->subsystem_vendor_id = pdev->subsystem_vendor; |
2045 | hw->subsystem_device_id = pdev->subsystem_device; | |
2046 | ||
2047 | hw->mbx.ops.init_params(hw); | |
56e94095 AD |
2048 | |
2049 | /* assume legacy case in which PF would only give VF 2 queues */ | |
2050 | hw->mac.max_tx_queues = 2; | |
2051 | hw->mac.max_rx_queues = 2; | |
2052 | ||
92915f71 GR |
2053 | err = hw->mac.ops.reset_hw(hw); |
2054 | if (err) { | |
2055 | dev_info(&pdev->dev, | |
2056 | "PF still in reset state, assigning new address\n"); | |
1a0d6ae5 DK |
2057 | eth_hw_addr_random(adapter->netdev); |
2058 | memcpy(adapter->hw.mac.addr, adapter->netdev->dev_addr, | |
2059 | adapter->netdev->addr_len); | |
92915f71 GR |
2060 | } else { |
2061 | err = hw->mac.ops.init_hw(hw); | |
2062 | if (err) { | |
dbd9636e | 2063 | pr_err("init_shared_code failed: %d\n", err); |
92915f71 GR |
2064 | goto out; |
2065 | } | |
1a0d6ae5 DK |
2066 | memcpy(adapter->netdev->dev_addr, adapter->hw.mac.addr, |
2067 | adapter->netdev->addr_len); | |
92915f71 GR |
2068 | } |
2069 | ||
1c55ed76 AD |
2070 | /* lock to protect mailbox accesses */ |
2071 | spin_lock_init(&adapter->mbx_lock); | |
2072 | ||
92915f71 | 2073 | /* Enable dynamic interrupt throttling rates */ |
5f3600eb AD |
2074 | adapter->rx_itr_setting = 1; |
2075 | adapter->tx_itr_setting = 1; | |
92915f71 | 2076 | |
92915f71 GR |
2077 | /* set default ring sizes */ |
2078 | adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD; | |
2079 | adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD; | |
2080 | ||
92915f71 | 2081 | set_bit(__IXGBEVF_DOWN, &adapter->state); |
1a0d6ae5 | 2082 | return 0; |
92915f71 GR |
2083 | |
2084 | out: | |
2085 | return err; | |
2086 | } | |
2087 | ||
92915f71 GR |
2088 | #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \ |
2089 | { \ | |
2090 | u32 current_counter = IXGBE_READ_REG(hw, reg); \ | |
2091 | if (current_counter < last_counter) \ | |
2092 | counter += 0x100000000LL; \ | |
2093 | last_counter = current_counter; \ | |
2094 | counter &= 0xFFFFFFFF00000000LL; \ | |
2095 | counter |= current_counter; \ | |
2096 | } | |
2097 | ||
2098 | #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ | |
2099 | { \ | |
2100 | u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \ | |
2101 | u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \ | |
2102 | u64 current_counter = (current_counter_msb << 32) | \ | |
2103 | current_counter_lsb; \ | |
2104 | if (current_counter < last_counter) \ | |
2105 | counter += 0x1000000000LL; \ | |
2106 | last_counter = current_counter; \ | |
2107 | counter &= 0xFFFFFFF000000000LL; \ | |
2108 | counter |= current_counter; \ | |
2109 | } | |
2110 | /** | |
2111 | * ixgbevf_update_stats - Update the board statistics counters. | |
2112 | * @adapter: board private structure | |
2113 | **/ | |
2114 | void ixgbevf_update_stats(struct ixgbevf_adapter *adapter) | |
2115 | { | |
2116 | struct ixgbe_hw *hw = &adapter->hw; | |
2117 | ||
2118 | UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc, | |
2119 | adapter->stats.vfgprc); | |
2120 | UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc, | |
2121 | adapter->stats.vfgptc); | |
2122 | UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, | |
2123 | adapter->stats.last_vfgorc, | |
2124 | adapter->stats.vfgorc); | |
2125 | UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, | |
2126 | adapter->stats.last_vfgotc, | |
2127 | adapter->stats.vfgotc); | |
2128 | UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc, | |
2129 | adapter->stats.vfmprc); | |
92915f71 GR |
2130 | } |
2131 | ||
2132 | /** | |
2133 | * ixgbevf_watchdog - Timer Call-back | |
2134 | * @data: pointer to adapter cast into an unsigned long | |
2135 | **/ | |
2136 | static void ixgbevf_watchdog(unsigned long data) | |
2137 | { | |
2138 | struct ixgbevf_adapter *adapter = (struct ixgbevf_adapter *)data; | |
2139 | struct ixgbe_hw *hw = &adapter->hw; | |
5f3600eb | 2140 | u32 eics = 0; |
92915f71 GR |
2141 | int i; |
2142 | ||
2143 | /* | |
2144 | * Do the watchdog outside of interrupt context due to the lovely | |
2145 | * delays that some of the newer hardware requires | |
2146 | */ | |
2147 | ||
2148 | if (test_bit(__IXGBEVF_DOWN, &adapter->state)) | |
2149 | goto watchdog_short_circuit; | |
2150 | ||
2151 | /* get one bit for every active tx/rx interrupt vector */ | |
2152 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
2153 | struct ixgbevf_q_vector *qv = adapter->q_vector[i]; | |
6b43c446 | 2154 | if (qv->rx.ring || qv->tx.ring) |
5f3600eb | 2155 | eics |= 1 << i; |
92915f71 GR |
2156 | } |
2157 | ||
5f3600eb | 2158 | IXGBE_WRITE_REG(hw, IXGBE_VTEICS, eics); |
92915f71 GR |
2159 | |
2160 | watchdog_short_circuit: | |
2161 | schedule_work(&adapter->watchdog_task); | |
2162 | } | |
2163 | ||
2164 | /** | |
2165 | * ixgbevf_tx_timeout - Respond to a Tx Hang | |
2166 | * @netdev: network interface device structure | |
2167 | **/ | |
2168 | static void ixgbevf_tx_timeout(struct net_device *netdev) | |
2169 | { | |
2170 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2171 | ||
2172 | /* Do the reset outside of interrupt context */ | |
2173 | schedule_work(&adapter->reset_task); | |
2174 | } | |
2175 | ||
2176 | static void ixgbevf_reset_task(struct work_struct *work) | |
2177 | { | |
2178 | struct ixgbevf_adapter *adapter; | |
2179 | adapter = container_of(work, struct ixgbevf_adapter, reset_task); | |
2180 | ||
2181 | /* If we're already down or resetting, just bail */ | |
2182 | if (test_bit(__IXGBEVF_DOWN, &adapter->state) || | |
2183 | test_bit(__IXGBEVF_RESETTING, &adapter->state)) | |
2184 | return; | |
2185 | ||
2186 | adapter->tx_timeout_count++; | |
2187 | ||
2188 | ixgbevf_reinit_locked(adapter); | |
2189 | } | |
2190 | ||
2191 | /** | |
2192 | * ixgbevf_watchdog_task - worker thread to bring link up | |
2193 | * @work: pointer to work_struct containing our data | |
2194 | **/ | |
2195 | static void ixgbevf_watchdog_task(struct work_struct *work) | |
2196 | { | |
2197 | struct ixgbevf_adapter *adapter = container_of(work, | |
2198 | struct ixgbevf_adapter, | |
2199 | watchdog_task); | |
2200 | struct net_device *netdev = adapter->netdev; | |
2201 | struct ixgbe_hw *hw = &adapter->hw; | |
2202 | u32 link_speed = adapter->link_speed; | |
2203 | bool link_up = adapter->link_up; | |
2204 | ||
2205 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
2206 | ||
2207 | /* | |
2208 | * Always check the link on the watchdog because we have | |
2209 | * no LSC interrupt | |
2210 | */ | |
2211 | if (hw->mac.ops.check_link) { | |
1c55ed76 AD |
2212 | s32 need_reset; |
2213 | ||
55fdd45b | 2214 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 AD |
2215 | |
2216 | need_reset = hw->mac.ops.check_link(hw, &link_speed, | |
2217 | &link_up, false); | |
2218 | ||
55fdd45b | 2219 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 AD |
2220 | |
2221 | if (need_reset) { | |
92915f71 GR |
2222 | adapter->link_up = link_up; |
2223 | adapter->link_speed = link_speed; | |
da6b3330 GR |
2224 | netif_carrier_off(netdev); |
2225 | netif_tx_stop_all_queues(netdev); | |
92915f71 GR |
2226 | schedule_work(&adapter->reset_task); |
2227 | goto pf_has_reset; | |
2228 | } | |
2229 | } else { | |
2230 | /* always assume link is up, if no check link | |
2231 | * function */ | |
2232 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
2233 | link_up = true; | |
2234 | } | |
2235 | adapter->link_up = link_up; | |
2236 | adapter->link_speed = link_speed; | |
2237 | ||
2238 | if (link_up) { | |
2239 | if (!netif_carrier_ok(netdev)) { | |
300bc060 JP |
2240 | hw_dbg(&adapter->hw, "NIC Link is Up, %u Gbps\n", |
2241 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ? | |
2242 | 10 : 1); | |
92915f71 GR |
2243 | netif_carrier_on(netdev); |
2244 | netif_tx_wake_all_queues(netdev); | |
92915f71 GR |
2245 | } |
2246 | } else { | |
2247 | adapter->link_up = false; | |
2248 | adapter->link_speed = 0; | |
2249 | if (netif_carrier_ok(netdev)) { | |
2250 | hw_dbg(&adapter->hw, "NIC Link is Down\n"); | |
2251 | netif_carrier_off(netdev); | |
2252 | netif_tx_stop_all_queues(netdev); | |
2253 | } | |
2254 | } | |
2255 | ||
92915f71 GR |
2256 | ixgbevf_update_stats(adapter); |
2257 | ||
33bd9f60 | 2258 | pf_has_reset: |
92915f71 GR |
2259 | /* Reset the timer */ |
2260 | if (!test_bit(__IXGBEVF_DOWN, &adapter->state)) | |
2261 | mod_timer(&adapter->watchdog_timer, | |
2262 | round_jiffies(jiffies + (2 * HZ))); | |
2263 | ||
2264 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; | |
2265 | } | |
2266 | ||
2267 | /** | |
2268 | * ixgbevf_free_tx_resources - Free Tx Resources per Queue | |
2269 | * @adapter: board private structure | |
2270 | * @tx_ring: Tx descriptor ring for a specific queue | |
2271 | * | |
2272 | * Free all transmit software resources | |
2273 | **/ | |
2274 | void ixgbevf_free_tx_resources(struct ixgbevf_adapter *adapter, | |
2275 | struct ixgbevf_ring *tx_ring) | |
2276 | { | |
2277 | struct pci_dev *pdev = adapter->pdev; | |
2278 | ||
92915f71 GR |
2279 | ixgbevf_clean_tx_ring(adapter, tx_ring); |
2280 | ||
2281 | vfree(tx_ring->tx_buffer_info); | |
2282 | tx_ring->tx_buffer_info = NULL; | |
2283 | ||
2a1f8794 NN |
2284 | dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, |
2285 | tx_ring->dma); | |
92915f71 GR |
2286 | |
2287 | tx_ring->desc = NULL; | |
2288 | } | |
2289 | ||
2290 | /** | |
2291 | * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues | |
2292 | * @adapter: board private structure | |
2293 | * | |
2294 | * Free all transmit software resources | |
2295 | **/ | |
2296 | static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter) | |
2297 | { | |
2298 | int i; | |
2299 | ||
2300 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2301 | if (adapter->tx_ring[i].desc) | |
2302 | ixgbevf_free_tx_resources(adapter, | |
2303 | &adapter->tx_ring[i]); | |
2304 | ||
2305 | } | |
2306 | ||
2307 | /** | |
2308 | * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors) | |
2309 | * @adapter: board private structure | |
2310 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
2311 | * | |
2312 | * Return 0 on success, negative on failure | |
2313 | **/ | |
2314 | int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *adapter, | |
2315 | struct ixgbevf_ring *tx_ring) | |
2316 | { | |
2317 | struct pci_dev *pdev = adapter->pdev; | |
2318 | int size; | |
2319 | ||
2320 | size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count; | |
89bf67f1 | 2321 | tx_ring->tx_buffer_info = vzalloc(size); |
92915f71 GR |
2322 | if (!tx_ring->tx_buffer_info) |
2323 | goto err; | |
92915f71 GR |
2324 | |
2325 | /* round up to nearest 4K */ | |
2326 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); | |
2327 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
2328 | ||
2a1f8794 NN |
2329 | tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, |
2330 | &tx_ring->dma, GFP_KERNEL); | |
92915f71 GR |
2331 | if (!tx_ring->desc) |
2332 | goto err; | |
2333 | ||
2334 | tx_ring->next_to_use = 0; | |
2335 | tx_ring->next_to_clean = 0; | |
92915f71 GR |
2336 | return 0; |
2337 | ||
2338 | err: | |
2339 | vfree(tx_ring->tx_buffer_info); | |
2340 | tx_ring->tx_buffer_info = NULL; | |
2341 | hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit " | |
2342 | "descriptor ring\n"); | |
2343 | return -ENOMEM; | |
2344 | } | |
2345 | ||
2346 | /** | |
2347 | * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources | |
2348 | * @adapter: board private structure | |
2349 | * | |
2350 | * If this function returns with an error, then it's possible one or | |
2351 | * more of the rings is populated (while the rest are not). It is the | |
2352 | * callers duty to clean those orphaned rings. | |
2353 | * | |
2354 | * Return 0 on success, negative on failure | |
2355 | **/ | |
2356 | static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter) | |
2357 | { | |
2358 | int i, err = 0; | |
2359 | ||
2360 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2361 | err = ixgbevf_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
2362 | if (!err) | |
2363 | continue; | |
2364 | hw_dbg(&adapter->hw, | |
2365 | "Allocation for Tx Queue %u failed\n", i); | |
2366 | break; | |
2367 | } | |
2368 | ||
2369 | return err; | |
2370 | } | |
2371 | ||
2372 | /** | |
2373 | * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors) | |
2374 | * @adapter: board private structure | |
2375 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
2376 | * | |
2377 | * Returns 0 on success, negative on failure | |
2378 | **/ | |
2379 | int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter, | |
2380 | struct ixgbevf_ring *rx_ring) | |
2381 | { | |
2382 | struct pci_dev *pdev = adapter->pdev; | |
2383 | int size; | |
2384 | ||
2385 | size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count; | |
89bf67f1 | 2386 | rx_ring->rx_buffer_info = vzalloc(size); |
e404decb | 2387 | if (!rx_ring->rx_buffer_info) |
92915f71 | 2388 | goto alloc_failed; |
92915f71 GR |
2389 | |
2390 | /* Round up to nearest 4K */ | |
2391 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); | |
2392 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
2393 | ||
2a1f8794 NN |
2394 | rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, |
2395 | &rx_ring->dma, GFP_KERNEL); | |
92915f71 GR |
2396 | |
2397 | if (!rx_ring->desc) { | |
2398 | hw_dbg(&adapter->hw, | |
2399 | "Unable to allocate memory for " | |
2400 | "the receive descriptor ring\n"); | |
2401 | vfree(rx_ring->rx_buffer_info); | |
2402 | rx_ring->rx_buffer_info = NULL; | |
2403 | goto alloc_failed; | |
2404 | } | |
2405 | ||
2406 | rx_ring->next_to_clean = 0; | |
2407 | rx_ring->next_to_use = 0; | |
2408 | ||
2409 | return 0; | |
2410 | alloc_failed: | |
2411 | return -ENOMEM; | |
2412 | } | |
2413 | ||
2414 | /** | |
2415 | * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources | |
2416 | * @adapter: board private structure | |
2417 | * | |
2418 | * If this function returns with an error, then it's possible one or | |
2419 | * more of the rings is populated (while the rest are not). It is the | |
2420 | * callers duty to clean those orphaned rings. | |
2421 | * | |
2422 | * Return 0 on success, negative on failure | |
2423 | **/ | |
2424 | static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter) | |
2425 | { | |
2426 | int i, err = 0; | |
2427 | ||
2428 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2429 | err = ixgbevf_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
2430 | if (!err) | |
2431 | continue; | |
2432 | hw_dbg(&adapter->hw, | |
2433 | "Allocation for Rx Queue %u failed\n", i); | |
2434 | break; | |
2435 | } | |
2436 | return err; | |
2437 | } | |
2438 | ||
2439 | /** | |
2440 | * ixgbevf_free_rx_resources - Free Rx Resources | |
2441 | * @adapter: board private structure | |
2442 | * @rx_ring: ring to clean the resources from | |
2443 | * | |
2444 | * Free all receive software resources | |
2445 | **/ | |
2446 | void ixgbevf_free_rx_resources(struct ixgbevf_adapter *adapter, | |
2447 | struct ixgbevf_ring *rx_ring) | |
2448 | { | |
2449 | struct pci_dev *pdev = adapter->pdev; | |
2450 | ||
2451 | ixgbevf_clean_rx_ring(adapter, rx_ring); | |
2452 | ||
2453 | vfree(rx_ring->rx_buffer_info); | |
2454 | rx_ring->rx_buffer_info = NULL; | |
2455 | ||
2a1f8794 NN |
2456 | dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, |
2457 | rx_ring->dma); | |
92915f71 GR |
2458 | |
2459 | rx_ring->desc = NULL; | |
2460 | } | |
2461 | ||
2462 | /** | |
2463 | * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues | |
2464 | * @adapter: board private structure | |
2465 | * | |
2466 | * Free all receive software resources | |
2467 | **/ | |
2468 | static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter) | |
2469 | { | |
2470 | int i; | |
2471 | ||
2472 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2473 | if (adapter->rx_ring[i].desc) | |
2474 | ixgbevf_free_rx_resources(adapter, | |
2475 | &adapter->rx_ring[i]); | |
2476 | } | |
2477 | ||
56e94095 AD |
2478 | static int ixgbevf_setup_queues(struct ixgbevf_adapter *adapter) |
2479 | { | |
2480 | struct ixgbe_hw *hw = &adapter->hw; | |
2481 | struct ixgbevf_ring *rx_ring; | |
2482 | unsigned int def_q = 0; | |
2483 | unsigned int num_tcs = 0; | |
2484 | unsigned int num_rx_queues = 1; | |
2485 | int err, i; | |
2486 | ||
55fdd45b | 2487 | spin_lock_bh(&adapter->mbx_lock); |
56e94095 AD |
2488 | |
2489 | /* fetch queue configuration from the PF */ | |
2490 | err = ixgbevf_get_queues(hw, &num_tcs, &def_q); | |
2491 | ||
55fdd45b | 2492 | spin_unlock_bh(&adapter->mbx_lock); |
56e94095 AD |
2493 | |
2494 | if (err) | |
2495 | return err; | |
2496 | ||
2497 | if (num_tcs > 1) { | |
2498 | /* update default Tx ring register index */ | |
2499 | adapter->tx_ring[0].reg_idx = def_q; | |
2500 | ||
2501 | /* we need as many queues as traffic classes */ | |
2502 | num_rx_queues = num_tcs; | |
2503 | } | |
2504 | ||
2505 | /* nothing to do if we have the correct number of queues */ | |
2506 | if (adapter->num_rx_queues == num_rx_queues) | |
2507 | return 0; | |
2508 | ||
2509 | /* allocate new rings */ | |
2510 | rx_ring = kcalloc(num_rx_queues, | |
2511 | sizeof(struct ixgbevf_ring), GFP_KERNEL); | |
2512 | if (!rx_ring) | |
2513 | return -ENOMEM; | |
2514 | ||
2515 | /* setup ring fields */ | |
2516 | for (i = 0; i < num_rx_queues; i++) { | |
2517 | rx_ring[i].count = adapter->rx_ring_count; | |
2518 | rx_ring[i].queue_index = i; | |
2519 | rx_ring[i].reg_idx = i; | |
2520 | rx_ring[i].dev = &adapter->pdev->dev; | |
2521 | rx_ring[i].netdev = adapter->netdev; | |
2522 | } | |
2523 | ||
2524 | /* free the existing ring and queues */ | |
2525 | adapter->num_rx_queues = 0; | |
2526 | kfree(adapter->rx_ring); | |
2527 | ||
2528 | /* move new rings into position on the adapter struct */ | |
2529 | adapter->rx_ring = rx_ring; | |
2530 | adapter->num_rx_queues = num_rx_queues; | |
2531 | ||
2532 | return 0; | |
2533 | } | |
2534 | ||
92915f71 GR |
2535 | /** |
2536 | * ixgbevf_open - Called when a network interface is made active | |
2537 | * @netdev: network interface device structure | |
2538 | * | |
2539 | * Returns 0 on success, negative value on failure | |
2540 | * | |
2541 | * The open entry point is called when a network interface is made | |
2542 | * active by the system (IFF_UP). At this point all resources needed | |
2543 | * for transmit and receive operations are allocated, the interrupt | |
2544 | * handler is registered with the OS, the watchdog timer is started, | |
2545 | * and the stack is notified that the interface is ready. | |
2546 | **/ | |
2547 | static int ixgbevf_open(struct net_device *netdev) | |
2548 | { | |
2549 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2550 | struct ixgbe_hw *hw = &adapter->hw; | |
2551 | int err; | |
2552 | ||
2553 | /* disallow open during test */ | |
2554 | if (test_bit(__IXGBEVF_TESTING, &adapter->state)) | |
2555 | return -EBUSY; | |
2556 | ||
2557 | if (hw->adapter_stopped) { | |
2558 | ixgbevf_reset(adapter); | |
2559 | /* if adapter is still stopped then PF isn't up and | |
2560 | * the vf can't start. */ | |
2561 | if (hw->adapter_stopped) { | |
2562 | err = IXGBE_ERR_MBX; | |
dbd9636e JK |
2563 | pr_err("Unable to start - perhaps the PF Driver isn't " |
2564 | "up yet\n"); | |
92915f71 GR |
2565 | goto err_setup_reset; |
2566 | } | |
2567 | } | |
2568 | ||
31186785 AD |
2569 | ixgbevf_negotiate_api(adapter); |
2570 | ||
56e94095 AD |
2571 | /* setup queue reg_idx and Rx queue count */ |
2572 | err = ixgbevf_setup_queues(adapter); | |
2573 | if (err) | |
2574 | goto err_setup_queues; | |
2575 | ||
92915f71 GR |
2576 | /* allocate transmit descriptors */ |
2577 | err = ixgbevf_setup_all_tx_resources(adapter); | |
2578 | if (err) | |
2579 | goto err_setup_tx; | |
2580 | ||
2581 | /* allocate receive descriptors */ | |
2582 | err = ixgbevf_setup_all_rx_resources(adapter); | |
2583 | if (err) | |
2584 | goto err_setup_rx; | |
2585 | ||
2586 | ixgbevf_configure(adapter); | |
2587 | ||
2588 | /* | |
2589 | * Map the Tx/Rx rings to the vectors we were allotted. | |
2590 | * if request_irq will be called in this function map_rings | |
2591 | * must be called *before* up_complete | |
2592 | */ | |
2593 | ixgbevf_map_rings_to_vectors(adapter); | |
2594 | ||
795180d8 | 2595 | ixgbevf_up_complete(adapter); |
92915f71 GR |
2596 | |
2597 | /* clear any pending interrupts, may auto mask */ | |
2598 | IXGBE_READ_REG(hw, IXGBE_VTEICR); | |
2599 | err = ixgbevf_request_irq(adapter); | |
2600 | if (err) | |
2601 | goto err_req_irq; | |
2602 | ||
5f3600eb | 2603 | ixgbevf_irq_enable(adapter); |
92915f71 GR |
2604 | |
2605 | return 0; | |
2606 | ||
2607 | err_req_irq: | |
2608 | ixgbevf_down(adapter); | |
92915f71 GR |
2609 | ixgbevf_free_irq(adapter); |
2610 | err_setup_rx: | |
2611 | ixgbevf_free_all_rx_resources(adapter); | |
2612 | err_setup_tx: | |
2613 | ixgbevf_free_all_tx_resources(adapter); | |
56e94095 | 2614 | err_setup_queues: |
92915f71 GR |
2615 | ixgbevf_reset(adapter); |
2616 | ||
2617 | err_setup_reset: | |
2618 | ||
2619 | return err; | |
2620 | } | |
2621 | ||
2622 | /** | |
2623 | * ixgbevf_close - Disables a network interface | |
2624 | * @netdev: network interface device structure | |
2625 | * | |
2626 | * Returns 0, this is not allowed to fail | |
2627 | * | |
2628 | * The close entry point is called when an interface is de-activated | |
2629 | * by the OS. The hardware is still under the drivers control, but | |
2630 | * needs to be disabled. A global MAC reset is issued to stop the | |
2631 | * hardware, and all transmit and receive resources are freed. | |
2632 | **/ | |
2633 | static int ixgbevf_close(struct net_device *netdev) | |
2634 | { | |
2635 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2636 | ||
2637 | ixgbevf_down(adapter); | |
2638 | ixgbevf_free_irq(adapter); | |
2639 | ||
2640 | ixgbevf_free_all_tx_resources(adapter); | |
2641 | ixgbevf_free_all_rx_resources(adapter); | |
2642 | ||
2643 | return 0; | |
2644 | } | |
2645 | ||
70a10e25 AD |
2646 | static void ixgbevf_tx_ctxtdesc(struct ixgbevf_ring *tx_ring, |
2647 | u32 vlan_macip_lens, u32 type_tucmd, | |
2648 | u32 mss_l4len_idx) | |
92915f71 GR |
2649 | { |
2650 | struct ixgbe_adv_tx_context_desc *context_desc; | |
70a10e25 | 2651 | u16 i = tx_ring->next_to_use; |
92915f71 | 2652 | |
70a10e25 | 2653 | context_desc = IXGBEVF_TX_CTXTDESC(tx_ring, i); |
92915f71 | 2654 | |
70a10e25 AD |
2655 | i++; |
2656 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
92915f71 | 2657 | |
70a10e25 AD |
2658 | /* set bits to identify this as an advanced context descriptor */ |
2659 | type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; | |
92915f71 | 2660 | |
70a10e25 AD |
2661 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); |
2662 | context_desc->seqnum_seed = 0; | |
2663 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
2664 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
2665 | } | |
2666 | ||
2667 | static int ixgbevf_tso(struct ixgbevf_ring *tx_ring, | |
2668 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) | |
2669 | { | |
2670 | u32 vlan_macip_lens, type_tucmd; | |
2671 | u32 mss_l4len_idx, l4len; | |
2672 | ||
2673 | if (!skb_is_gso(skb)) | |
2674 | return 0; | |
92915f71 | 2675 | |
70a10e25 AD |
2676 | if (skb_header_cloned(skb)) { |
2677 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2678 | if (err) | |
2679 | return err; | |
92915f71 GR |
2680 | } |
2681 | ||
70a10e25 AD |
2682 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
2683 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
2684 | ||
2685 | if (skb->protocol == htons(ETH_P_IP)) { | |
2686 | struct iphdr *iph = ip_hdr(skb); | |
2687 | iph->tot_len = 0; | |
2688 | iph->check = 0; | |
2689 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
2690 | iph->daddr, 0, | |
2691 | IPPROTO_TCP, | |
2692 | 0); | |
2693 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
2694 | } else if (skb_is_gso_v6(skb)) { | |
2695 | ipv6_hdr(skb)->payload_len = 0; | |
2696 | tcp_hdr(skb)->check = | |
2697 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
2698 | &ipv6_hdr(skb)->daddr, | |
2699 | 0, IPPROTO_TCP, 0); | |
2700 | } | |
2701 | ||
2702 | /* compute header lengths */ | |
2703 | l4len = tcp_hdrlen(skb); | |
2704 | *hdr_len += l4len; | |
2705 | *hdr_len = skb_transport_offset(skb) + l4len; | |
2706 | ||
2707 | /* mss_l4len_id: use 1 as index for TSO */ | |
2708 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
2709 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
2710 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
2711 | ||
2712 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
2713 | vlan_macip_lens = skb_network_header_len(skb); | |
2714 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
2715 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
2716 | ||
2717 | ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens, | |
2718 | type_tucmd, mss_l4len_idx); | |
2719 | ||
2720 | return 1; | |
92915f71 GR |
2721 | } |
2722 | ||
70a10e25 | 2723 | static bool ixgbevf_tx_csum(struct ixgbevf_ring *tx_ring, |
92915f71 GR |
2724 | struct sk_buff *skb, u32 tx_flags) |
2725 | { | |
92915f71 | 2726 | |
92915f71 | 2727 | |
92915f71 | 2728 | |
70a10e25 AD |
2729 | u32 vlan_macip_lens = 0; |
2730 | u32 mss_l4len_idx = 0; | |
2731 | u32 type_tucmd = 0; | |
92915f71 | 2732 | |
70a10e25 AD |
2733 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
2734 | u8 l4_hdr = 0; | |
2735 | switch (skb->protocol) { | |
2736 | case __constant_htons(ETH_P_IP): | |
2737 | vlan_macip_lens |= skb_network_header_len(skb); | |
2738 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
2739 | l4_hdr = ip_hdr(skb)->protocol; | |
2740 | break; | |
2741 | case __constant_htons(ETH_P_IPV6): | |
2742 | vlan_macip_lens |= skb_network_header_len(skb); | |
2743 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
2744 | break; | |
2745 | default: | |
2746 | if (unlikely(net_ratelimit())) { | |
2747 | dev_warn(tx_ring->dev, | |
2748 | "partial checksum but proto=%x!\n", | |
2749 | skb->protocol); | |
2750 | } | |
2751 | break; | |
2752 | } | |
92915f71 | 2753 | |
70a10e25 AD |
2754 | switch (l4_hdr) { |
2755 | case IPPROTO_TCP: | |
2756 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
2757 | mss_l4len_idx = tcp_hdrlen(skb) << | |
2758 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
2759 | break; | |
2760 | case IPPROTO_SCTP: | |
2761 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
2762 | mss_l4len_idx = sizeof(struct sctphdr) << | |
2763 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
2764 | break; | |
2765 | case IPPROTO_UDP: | |
2766 | mss_l4len_idx = sizeof(struct udphdr) << | |
2767 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
2768 | break; | |
2769 | default: | |
2770 | if (unlikely(net_ratelimit())) { | |
2771 | dev_warn(tx_ring->dev, | |
2772 | "partial checksum but l4 proto=%x!\n", | |
2773 | l4_hdr); | |
2774 | } | |
2775 | break; | |
2776 | } | |
92915f71 GR |
2777 | } |
2778 | ||
70a10e25 AD |
2779 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
2780 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
2781 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
2782 | ||
2783 | ixgbevf_tx_ctxtdesc(tx_ring, vlan_macip_lens, | |
2784 | type_tucmd, mss_l4len_idx); | |
2785 | ||
2786 | return (skb->ip_summed == CHECKSUM_PARTIAL); | |
92915f71 GR |
2787 | } |
2788 | ||
70a10e25 | 2789 | static int ixgbevf_tx_map(struct ixgbevf_ring *tx_ring, |
92915f71 GR |
2790 | struct sk_buff *skb, u32 tx_flags, |
2791 | unsigned int first) | |
2792 | { | |
92915f71 GR |
2793 | struct ixgbevf_tx_buffer *tx_buffer_info; |
2794 | unsigned int len; | |
2795 | unsigned int total = skb->len; | |
2540ddb5 KV |
2796 | unsigned int offset = 0, size; |
2797 | int count = 0; | |
92915f71 GR |
2798 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; |
2799 | unsigned int f; | |
65deeed7 | 2800 | int i; |
92915f71 GR |
2801 | |
2802 | i = tx_ring->next_to_use; | |
2803 | ||
2804 | len = min(skb_headlen(skb), total); | |
2805 | while (len) { | |
2806 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2807 | size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD); | |
2808 | ||
2809 | tx_buffer_info->length = size; | |
2810 | tx_buffer_info->mapped_as_page = false; | |
70a10e25 | 2811 | tx_buffer_info->dma = dma_map_single(tx_ring->dev, |
92915f71 | 2812 | skb->data + offset, |
2a1f8794 | 2813 | size, DMA_TO_DEVICE); |
70a10e25 | 2814 | if (dma_mapping_error(tx_ring->dev, tx_buffer_info->dma)) |
92915f71 | 2815 | goto dma_error; |
92915f71 GR |
2816 | tx_buffer_info->next_to_watch = i; |
2817 | ||
2818 | len -= size; | |
2819 | total -= size; | |
2820 | offset += size; | |
2821 | count++; | |
2822 | i++; | |
2823 | if (i == tx_ring->count) | |
2824 | i = 0; | |
2825 | } | |
2826 | ||
2827 | for (f = 0; f < nr_frags; f++) { | |
9e903e08 | 2828 | const struct skb_frag_struct *frag; |
92915f71 GR |
2829 | |
2830 | frag = &skb_shinfo(skb)->frags[f]; | |
9e903e08 | 2831 | len = min((unsigned int)skb_frag_size(frag), total); |
877749bf | 2832 | offset = 0; |
92915f71 GR |
2833 | |
2834 | while (len) { | |
2835 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2836 | size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD); | |
2837 | ||
2838 | tx_buffer_info->length = size; | |
877749bf | 2839 | tx_buffer_info->dma = |
70a10e25 | 2840 | skb_frag_dma_map(tx_ring->dev, frag, |
877749bf | 2841 | offset, size, DMA_TO_DEVICE); |
70a10e25 AD |
2842 | if (dma_mapping_error(tx_ring->dev, |
2843 | tx_buffer_info->dma)) | |
92915f71 | 2844 | goto dma_error; |
6132ee8a | 2845 | tx_buffer_info->mapped_as_page = true; |
92915f71 GR |
2846 | tx_buffer_info->next_to_watch = i; |
2847 | ||
2848 | len -= size; | |
2849 | total -= size; | |
2850 | offset += size; | |
2851 | count++; | |
2852 | i++; | |
2853 | if (i == tx_ring->count) | |
2854 | i = 0; | |
2855 | } | |
2856 | if (total == 0) | |
2857 | break; | |
2858 | } | |
2859 | ||
2860 | if (i == 0) | |
2861 | i = tx_ring->count - 1; | |
2862 | else | |
2863 | i = i - 1; | |
2864 | tx_ring->tx_buffer_info[i].skb = skb; | |
2865 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
70a10e25 | 2866 | tx_ring->tx_buffer_info[first].time_stamp = jiffies; |
92915f71 GR |
2867 | |
2868 | return count; | |
2869 | ||
2870 | dma_error: | |
70a10e25 | 2871 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
92915f71 GR |
2872 | |
2873 | /* clear timestamp and dma mappings for failed tx_buffer_info map */ | |
2874 | tx_buffer_info->dma = 0; | |
92915f71 GR |
2875 | tx_buffer_info->next_to_watch = 0; |
2876 | count--; | |
2877 | ||
2878 | /* clear timestamp and dma mappings for remaining portion of packet */ | |
2879 | while (count >= 0) { | |
2880 | count--; | |
2881 | i--; | |
2882 | if (i < 0) | |
2883 | i += tx_ring->count; | |
2884 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
70a10e25 | 2885 | ixgbevf_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
92915f71 GR |
2886 | } |
2887 | ||
2888 | return count; | |
2889 | } | |
2890 | ||
70a10e25 | 2891 | static void ixgbevf_tx_queue(struct ixgbevf_ring *tx_ring, int tx_flags, |
92915f71 GR |
2892 | int count, u32 paylen, u8 hdr_len) |
2893 | { | |
2894 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
2895 | struct ixgbevf_tx_buffer *tx_buffer_info; | |
2896 | u32 olinfo_status = 0, cmd_type_len = 0; | |
2897 | unsigned int i; | |
2898 | ||
2899 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
2900 | ||
2901 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
2902 | ||
2903 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
2904 | ||
2905 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
2906 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
2907 | ||
70a10e25 AD |
2908 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) |
2909 | olinfo_status |= IXGBE_ADVTXD_POPTS_TXSM; | |
2910 | ||
92915f71 GR |
2911 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { |
2912 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
2913 | ||
92915f71 GR |
2914 | /* use index 1 context for tso */ |
2915 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
2916 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
70a10e25 AD |
2917 | olinfo_status |= IXGBE_ADVTXD_POPTS_IXSM; |
2918 | ||
2919 | } | |
92915f71 | 2920 | |
70a10e25 AD |
2921 | /* |
2922 | * Check Context must be set if Tx switch is enabled, which it | |
2923 | * always is for case where virtual functions are running | |
2924 | */ | |
2925 | olinfo_status |= IXGBE_ADVTXD_CC; | |
92915f71 GR |
2926 | |
2927 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
2928 | ||
2929 | i = tx_ring->next_to_use; | |
2930 | while (count--) { | |
2931 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
908421f6 | 2932 | tx_desc = IXGBEVF_TX_DESC(tx_ring, i); |
92915f71 GR |
2933 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); |
2934 | tx_desc->read.cmd_type_len = | |
2935 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); | |
2936 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
2937 | i++; | |
2938 | if (i == tx_ring->count) | |
2939 | i = 0; | |
2940 | } | |
2941 | ||
2942 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
2943 | ||
92915f71 | 2944 | tx_ring->next_to_use = i; |
92915f71 GR |
2945 | } |
2946 | ||
fb40195c | 2947 | static int __ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size) |
92915f71 | 2948 | { |
fb40195c | 2949 | struct ixgbevf_adapter *adapter = netdev_priv(tx_ring->netdev); |
92915f71 | 2950 | |
fb40195c | 2951 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
92915f71 GR |
2952 | /* Herbert's original patch had: |
2953 | * smp_mb__after_netif_stop_queue(); | |
2954 | * but since that doesn't exist yet, just open code it. */ | |
2955 | smp_mb(); | |
2956 | ||
2957 | /* We need to check again in a case another CPU has just | |
2958 | * made room available. */ | |
2959 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
2960 | return -EBUSY; | |
2961 | ||
2962 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fb40195c | 2963 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
92915f71 GR |
2964 | ++adapter->restart_queue; |
2965 | return 0; | |
2966 | } | |
2967 | ||
fb40195c | 2968 | static int ixgbevf_maybe_stop_tx(struct ixgbevf_ring *tx_ring, int size) |
92915f71 GR |
2969 | { |
2970 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
2971 | return 0; | |
fb40195c | 2972 | return __ixgbevf_maybe_stop_tx(tx_ring, size); |
92915f71 GR |
2973 | } |
2974 | ||
2975 | static int ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2976 | { | |
2977 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
2978 | struct ixgbevf_ring *tx_ring; | |
2979 | unsigned int first; | |
2980 | unsigned int tx_flags = 0; | |
2981 | u8 hdr_len = 0; | |
2982 | int r_idx = 0, tso; | |
3595990a AD |
2983 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
2984 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
2985 | unsigned short f; | |
2986 | #endif | |
f9d08f16 | 2987 | u8 *dst_mac = skb_header_pointer(skb, 0, 0, NULL); |
46acc460 | 2988 | if (!dst_mac || is_link_local_ether_addr(dst_mac)) { |
f9d08f16 GR |
2989 | dev_kfree_skb(skb); |
2990 | return NETDEV_TX_OK; | |
2991 | } | |
92915f71 GR |
2992 | |
2993 | tx_ring = &adapter->tx_ring[r_idx]; | |
2994 | ||
3595990a AD |
2995 | /* |
2996 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
2997 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, | |
2998 | * + 2 desc gap to keep tail from touching head, | |
2999 | * + 1 desc for context descriptor, | |
3000 | * otherwise try next time | |
3001 | */ | |
3002 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
3003 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
3004 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
3005 | #else | |
3006 | count += skb_shinfo(skb)->nr_frags; | |
3007 | #endif | |
fb40195c | 3008 | if (ixgbevf_maybe_stop_tx(tx_ring, count + 3)) { |
3595990a AD |
3009 | adapter->tx_busy++; |
3010 | return NETDEV_TX_BUSY; | |
3011 | } | |
3012 | ||
eab6d18d | 3013 | if (vlan_tx_tag_present(skb)) { |
92915f71 GR |
3014 | tx_flags |= vlan_tx_tag_get(skb); |
3015 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
3016 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
3017 | } | |
3018 | ||
92915f71 GR |
3019 | first = tx_ring->next_to_use; |
3020 | ||
3021 | if (skb->protocol == htons(ETH_P_IP)) | |
3022 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
70a10e25 | 3023 | tso = ixgbevf_tso(tx_ring, skb, tx_flags, &hdr_len); |
92915f71 GR |
3024 | if (tso < 0) { |
3025 | dev_kfree_skb_any(skb); | |
3026 | return NETDEV_TX_OK; | |
3027 | } | |
3028 | ||
3029 | if (tso) | |
70a10e25 AD |
3030 | tx_flags |= IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_CSUM; |
3031 | else if (ixgbevf_tx_csum(tx_ring, skb, tx_flags)) | |
92915f71 GR |
3032 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
3033 | ||
70a10e25 AD |
3034 | ixgbevf_tx_queue(tx_ring, tx_flags, |
3035 | ixgbevf_tx_map(tx_ring, skb, tx_flags, first), | |
92915f71 | 3036 | skb->len, hdr_len); |
70a10e25 AD |
3037 | /* |
3038 | * Force memory writes to complete before letting h/w | |
3039 | * know there are new descriptors to fetch. (Only | |
3040 | * applicable for weak-ordered memory model archs, | |
3041 | * such as IA-64). | |
3042 | */ | |
3043 | wmb(); | |
3044 | ||
3045 | writel(tx_ring->next_to_use, adapter->hw.hw_addr + tx_ring->tail); | |
92915f71 | 3046 | |
fb40195c | 3047 | ixgbevf_maybe_stop_tx(tx_ring, DESC_NEEDED); |
92915f71 GR |
3048 | |
3049 | return NETDEV_TX_OK; | |
3050 | } | |
3051 | ||
92915f71 GR |
3052 | /** |
3053 | * ixgbevf_set_mac - Change the Ethernet Address of the NIC | |
3054 | * @netdev: network interface device structure | |
3055 | * @p: pointer to an address structure | |
3056 | * | |
3057 | * Returns 0 on success, negative on failure | |
3058 | **/ | |
3059 | static int ixgbevf_set_mac(struct net_device *netdev, void *p) | |
3060 | { | |
3061 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3062 | struct ixgbe_hw *hw = &adapter->hw; | |
3063 | struct sockaddr *addr = p; | |
3064 | ||
3065 | if (!is_valid_ether_addr(addr->sa_data)) | |
3066 | return -EADDRNOTAVAIL; | |
3067 | ||
3068 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
3069 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); | |
3070 | ||
55fdd45b | 3071 | spin_lock_bh(&adapter->mbx_lock); |
1c55ed76 | 3072 | |
92915f71 GR |
3073 | if (hw->mac.ops.set_rar) |
3074 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0); | |
3075 | ||
55fdd45b | 3076 | spin_unlock_bh(&adapter->mbx_lock); |
1c55ed76 | 3077 | |
92915f71 GR |
3078 | return 0; |
3079 | } | |
3080 | ||
3081 | /** | |
3082 | * ixgbevf_change_mtu - Change the Maximum Transfer Unit | |
3083 | * @netdev: network interface device structure | |
3084 | * @new_mtu: new value for maximum frame size | |
3085 | * | |
3086 | * Returns 0 on success, negative on failure | |
3087 | **/ | |
3088 | static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu) | |
3089 | { | |
3090 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3091 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
69bfbec4 | 3092 | int max_possible_frame = MAXIMUM_ETHERNET_VLAN_SIZE; |
69bfbec4 | 3093 | |
56e94095 AD |
3094 | switch (adapter->hw.api_version) { |
3095 | case ixgbe_mbox_api_11: | |
69bfbec4 | 3096 | max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE; |
56e94095 AD |
3097 | break; |
3098 | default: | |
3099 | if (adapter->hw.mac.type == ixgbe_mac_X540_vf) | |
3100 | max_possible_frame = IXGBE_MAX_JUMBO_FRAME_SIZE; | |
3101 | break; | |
3102 | } | |
92915f71 GR |
3103 | |
3104 | /* MTU < 68 is an error and causes problems on some kernels */ | |
69bfbec4 | 3105 | if ((new_mtu < 68) || (max_frame > max_possible_frame)) |
92915f71 GR |
3106 | return -EINVAL; |
3107 | ||
3108 | hw_dbg(&adapter->hw, "changing MTU from %d to %d\n", | |
3109 | netdev->mtu, new_mtu); | |
3110 | /* must set new MTU before calling down or up */ | |
3111 | netdev->mtu = new_mtu; | |
3112 | ||
3113 | if (netif_running(netdev)) | |
3114 | ixgbevf_reinit_locked(adapter); | |
3115 | ||
3116 | return 0; | |
3117 | } | |
3118 | ||
0ac1e8ce | 3119 | static int ixgbevf_suspend(struct pci_dev *pdev, pm_message_t state) |
92915f71 GR |
3120 | { |
3121 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3122 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
0ac1e8ce AD |
3123 | #ifdef CONFIG_PM |
3124 | int retval = 0; | |
3125 | #endif | |
92915f71 GR |
3126 | |
3127 | netif_device_detach(netdev); | |
3128 | ||
3129 | if (netif_running(netdev)) { | |
0ac1e8ce | 3130 | rtnl_lock(); |
92915f71 GR |
3131 | ixgbevf_down(adapter); |
3132 | ixgbevf_free_irq(adapter); | |
3133 | ixgbevf_free_all_tx_resources(adapter); | |
3134 | ixgbevf_free_all_rx_resources(adapter); | |
0ac1e8ce | 3135 | rtnl_unlock(); |
92915f71 GR |
3136 | } |
3137 | ||
0ac1e8ce | 3138 | ixgbevf_clear_interrupt_scheme(adapter); |
92915f71 | 3139 | |
0ac1e8ce AD |
3140 | #ifdef CONFIG_PM |
3141 | retval = pci_save_state(pdev); | |
3142 | if (retval) | |
3143 | return retval; | |
92915f71 | 3144 | |
0ac1e8ce | 3145 | #endif |
92915f71 | 3146 | pci_disable_device(pdev); |
0ac1e8ce AD |
3147 | |
3148 | return 0; | |
3149 | } | |
3150 | ||
3151 | #ifdef CONFIG_PM | |
3152 | static int ixgbevf_resume(struct pci_dev *pdev) | |
3153 | { | |
3154 | struct ixgbevf_adapter *adapter = pci_get_drvdata(pdev); | |
3155 | struct net_device *netdev = adapter->netdev; | |
3156 | u32 err; | |
3157 | ||
3158 | pci_set_power_state(pdev, PCI_D0); | |
3159 | pci_restore_state(pdev); | |
3160 | /* | |
3161 | * pci_restore_state clears dev->state_saved so call | |
3162 | * pci_save_state to restore it. | |
3163 | */ | |
3164 | pci_save_state(pdev); | |
3165 | ||
3166 | err = pci_enable_device_mem(pdev); | |
3167 | if (err) { | |
3168 | dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n"); | |
3169 | return err; | |
3170 | } | |
3171 | pci_set_master(pdev); | |
3172 | ||
3173 | rtnl_lock(); | |
3174 | err = ixgbevf_init_interrupt_scheme(adapter); | |
3175 | rtnl_unlock(); | |
3176 | if (err) { | |
3177 | dev_err(&pdev->dev, "Cannot initialize interrupts\n"); | |
3178 | return err; | |
3179 | } | |
3180 | ||
3181 | ixgbevf_reset(adapter); | |
3182 | ||
3183 | if (netif_running(netdev)) { | |
3184 | err = ixgbevf_open(netdev); | |
3185 | if (err) | |
3186 | return err; | |
3187 | } | |
3188 | ||
3189 | netif_device_attach(netdev); | |
3190 | ||
3191 | return err; | |
3192 | } | |
3193 | ||
3194 | #endif /* CONFIG_PM */ | |
3195 | static void ixgbevf_shutdown(struct pci_dev *pdev) | |
3196 | { | |
3197 | ixgbevf_suspend(pdev, PMSG_SUSPEND); | |
92915f71 GR |
3198 | } |
3199 | ||
4197aa7b ED |
3200 | static struct rtnl_link_stats64 *ixgbevf_get_stats(struct net_device *netdev, |
3201 | struct rtnl_link_stats64 *stats) | |
3202 | { | |
3203 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3204 | unsigned int start; | |
3205 | u64 bytes, packets; | |
3206 | const struct ixgbevf_ring *ring; | |
3207 | int i; | |
3208 | ||
3209 | ixgbevf_update_stats(adapter); | |
3210 | ||
3211 | stats->multicast = adapter->stats.vfmprc - adapter->stats.base_vfmprc; | |
3212 | ||
3213 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3214 | ring = &adapter->rx_ring[i]; | |
3215 | do { | |
3216 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
3217 | bytes = ring->total_bytes; | |
3218 | packets = ring->total_packets; | |
3219 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
3220 | stats->rx_bytes += bytes; | |
3221 | stats->rx_packets += packets; | |
3222 | } | |
3223 | ||
3224 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3225 | ring = &adapter->tx_ring[i]; | |
3226 | do { | |
3227 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
3228 | bytes = ring->total_bytes; | |
3229 | packets = ring->total_packets; | |
3230 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
3231 | stats->tx_bytes += bytes; | |
3232 | stats->tx_packets += packets; | |
3233 | } | |
3234 | ||
3235 | return stats; | |
3236 | } | |
3237 | ||
0ac1e8ce | 3238 | static const struct net_device_ops ixgbevf_netdev_ops = { |
c12db769 SH |
3239 | .ndo_open = ixgbevf_open, |
3240 | .ndo_stop = ixgbevf_close, | |
3241 | .ndo_start_xmit = ixgbevf_xmit_frame, | |
3242 | .ndo_set_rx_mode = ixgbevf_set_rx_mode, | |
4197aa7b | 3243 | .ndo_get_stats64 = ixgbevf_get_stats, |
92915f71 | 3244 | .ndo_validate_addr = eth_validate_addr, |
c12db769 SH |
3245 | .ndo_set_mac_address = ixgbevf_set_mac, |
3246 | .ndo_change_mtu = ixgbevf_change_mtu, | |
3247 | .ndo_tx_timeout = ixgbevf_tx_timeout, | |
c12db769 SH |
3248 | .ndo_vlan_rx_add_vid = ixgbevf_vlan_rx_add_vid, |
3249 | .ndo_vlan_rx_kill_vid = ixgbevf_vlan_rx_kill_vid, | |
92915f71 | 3250 | }; |
92915f71 GR |
3251 | |
3252 | static void ixgbevf_assign_netdev_ops(struct net_device *dev) | |
3253 | { | |
0ac1e8ce | 3254 | dev->netdev_ops = &ixgbevf_netdev_ops; |
92915f71 GR |
3255 | ixgbevf_set_ethtool_ops(dev); |
3256 | dev->watchdog_timeo = 5 * HZ; | |
3257 | } | |
3258 | ||
3259 | /** | |
3260 | * ixgbevf_probe - Device Initialization Routine | |
3261 | * @pdev: PCI device information struct | |
3262 | * @ent: entry in ixgbevf_pci_tbl | |
3263 | * | |
3264 | * Returns 0 on success, negative on failure | |
3265 | * | |
3266 | * ixgbevf_probe initializes an adapter identified by a pci_dev structure. | |
3267 | * The OS initialization, configuring of the adapter private structure, | |
3268 | * and a hardware reset occur. | |
3269 | **/ | |
3270 | static int __devinit ixgbevf_probe(struct pci_dev *pdev, | |
3271 | const struct pci_device_id *ent) | |
3272 | { | |
3273 | struct net_device *netdev; | |
3274 | struct ixgbevf_adapter *adapter = NULL; | |
3275 | struct ixgbe_hw *hw = NULL; | |
3276 | const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data]; | |
3277 | static int cards_found; | |
3278 | int err, pci_using_dac; | |
3279 | ||
3280 | err = pci_enable_device(pdev); | |
3281 | if (err) | |
3282 | return err; | |
3283 | ||
2a1f8794 NN |
3284 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
3285 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
92915f71 GR |
3286 | pci_using_dac = 1; |
3287 | } else { | |
2a1f8794 | 3288 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
92915f71 | 3289 | if (err) { |
2a1f8794 NN |
3290 | err = dma_set_coherent_mask(&pdev->dev, |
3291 | DMA_BIT_MASK(32)); | |
92915f71 GR |
3292 | if (err) { |
3293 | dev_err(&pdev->dev, "No usable DMA " | |
3294 | "configuration, aborting\n"); | |
3295 | goto err_dma; | |
3296 | } | |
3297 | } | |
3298 | pci_using_dac = 0; | |
3299 | } | |
3300 | ||
3301 | err = pci_request_regions(pdev, ixgbevf_driver_name); | |
3302 | if (err) { | |
3303 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
3304 | goto err_pci_reg; | |
3305 | } | |
3306 | ||
3307 | pci_set_master(pdev); | |
3308 | ||
92915f71 GR |
3309 | netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter), |
3310 | MAX_TX_QUEUES); | |
92915f71 GR |
3311 | if (!netdev) { |
3312 | err = -ENOMEM; | |
3313 | goto err_alloc_etherdev; | |
3314 | } | |
3315 | ||
3316 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
3317 | ||
3318 | pci_set_drvdata(pdev, netdev); | |
3319 | adapter = netdev_priv(netdev); | |
3320 | ||
3321 | adapter->netdev = netdev; | |
3322 | adapter->pdev = pdev; | |
3323 | hw = &adapter->hw; | |
3324 | hw->back = adapter; | |
b3f4d599 | 3325 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
92915f71 GR |
3326 | |
3327 | /* | |
3328 | * call save state here in standalone driver because it relies on | |
3329 | * adapter struct to exist, and needs to call netdev_priv | |
3330 | */ | |
3331 | pci_save_state(pdev); | |
3332 | ||
3333 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), | |
3334 | pci_resource_len(pdev, 0)); | |
3335 | if (!hw->hw_addr) { | |
3336 | err = -EIO; | |
3337 | goto err_ioremap; | |
3338 | } | |
3339 | ||
3340 | ixgbevf_assign_netdev_ops(netdev); | |
3341 | ||
3342 | adapter->bd_number = cards_found; | |
3343 | ||
3344 | /* Setup hw api */ | |
3345 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
3346 | hw->mac.type = ii->mac; | |
3347 | ||
3348 | memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops, | |
f416dfc0 | 3349 | sizeof(struct ixgbe_mbx_operations)); |
92915f71 | 3350 | |
92915f71 GR |
3351 | /* setup the private structure */ |
3352 | err = ixgbevf_sw_init(adapter); | |
1a0d6ae5 DK |
3353 | if (err) |
3354 | goto err_sw_init; | |
3355 | ||
3356 | /* The HW MAC address was set and/or determined in sw_init */ | |
3357 | memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len); | |
3358 | ||
3359 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
3360 | pr_err("invalid MAC address\n"); | |
3361 | err = -EIO; | |
3362 | goto err_sw_init; | |
3363 | } | |
92915f71 | 3364 | |
471a76de | 3365 | netdev->hw_features = NETIF_F_SG | |
92915f71 | 3366 | NETIF_F_IP_CSUM | |
471a76de MM |
3367 | NETIF_F_IPV6_CSUM | |
3368 | NETIF_F_TSO | | |
3369 | NETIF_F_TSO6 | | |
3370 | NETIF_F_RXCSUM; | |
3371 | ||
3372 | netdev->features = netdev->hw_features | | |
92915f71 GR |
3373 | NETIF_F_HW_VLAN_TX | |
3374 | NETIF_F_HW_VLAN_RX | | |
3375 | NETIF_F_HW_VLAN_FILTER; | |
3376 | ||
92915f71 GR |
3377 | netdev->vlan_features |= NETIF_F_TSO; |
3378 | netdev->vlan_features |= NETIF_F_TSO6; | |
3379 | netdev->vlan_features |= NETIF_F_IP_CSUM; | |
3bfacf96 | 3380 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
92915f71 GR |
3381 | netdev->vlan_features |= NETIF_F_SG; |
3382 | ||
3383 | if (pci_using_dac) | |
3384 | netdev->features |= NETIF_F_HIGHDMA; | |
3385 | ||
01789349 JP |
3386 | netdev->priv_flags |= IFF_UNICAST_FLT; |
3387 | ||
92915f71 | 3388 | init_timer(&adapter->watchdog_timer); |
c061b18d | 3389 | adapter->watchdog_timer.function = ixgbevf_watchdog; |
92915f71 GR |
3390 | adapter->watchdog_timer.data = (unsigned long)adapter; |
3391 | ||
3392 | INIT_WORK(&adapter->reset_task, ixgbevf_reset_task); | |
3393 | INIT_WORK(&adapter->watchdog_task, ixgbevf_watchdog_task); | |
3394 | ||
3395 | err = ixgbevf_init_interrupt_scheme(adapter); | |
3396 | if (err) | |
3397 | goto err_sw_init; | |
3398 | ||
3399 | /* pick up the PCI bus settings for reporting later */ | |
3400 | if (hw->mac.ops.get_bus_info) | |
3401 | hw->mac.ops.get_bus_info(hw); | |
3402 | ||
92915f71 GR |
3403 | strcpy(netdev->name, "eth%d"); |
3404 | ||
3405 | err = register_netdev(netdev); | |
3406 | if (err) | |
3407 | goto err_register; | |
3408 | ||
5d426ad1 GR |
3409 | netif_carrier_off(netdev); |
3410 | ||
33bd9f60 GR |
3411 | ixgbevf_init_last_counter_stats(adapter); |
3412 | ||
92915f71 | 3413 | /* print the MAC address */ |
f794e7ef | 3414 | hw_dbg(hw, "%pM\n", netdev->dev_addr); |
92915f71 GR |
3415 | |
3416 | hw_dbg(hw, "MAC: %d\n", hw->mac.type); | |
3417 | ||
92915f71 GR |
3418 | hw_dbg(hw, "Intel(R) 82599 Virtual Function\n"); |
3419 | cards_found++; | |
3420 | return 0; | |
3421 | ||
3422 | err_register: | |
0ac1e8ce | 3423 | ixgbevf_clear_interrupt_scheme(adapter); |
92915f71 GR |
3424 | err_sw_init: |
3425 | ixgbevf_reset_interrupt_capability(adapter); | |
3426 | iounmap(hw->hw_addr); | |
3427 | err_ioremap: | |
3428 | free_netdev(netdev); | |
3429 | err_alloc_etherdev: | |
3430 | pci_release_regions(pdev); | |
3431 | err_pci_reg: | |
3432 | err_dma: | |
3433 | pci_disable_device(pdev); | |
3434 | return err; | |
3435 | } | |
3436 | ||
3437 | /** | |
3438 | * ixgbevf_remove - Device Removal Routine | |
3439 | * @pdev: PCI device information struct | |
3440 | * | |
3441 | * ixgbevf_remove is called by the PCI subsystem to alert the driver | |
3442 | * that it should release a PCI device. The could be caused by a | |
3443 | * Hot-Plug event, or because the driver is going to be removed from | |
3444 | * memory. | |
3445 | **/ | |
3446 | static void __devexit ixgbevf_remove(struct pci_dev *pdev) | |
3447 | { | |
3448 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3449 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3450 | ||
3451 | set_bit(__IXGBEVF_DOWN, &adapter->state); | |
3452 | ||
3453 | del_timer_sync(&adapter->watchdog_timer); | |
3454 | ||
23f333a2 | 3455 | cancel_work_sync(&adapter->reset_task); |
92915f71 GR |
3456 | cancel_work_sync(&adapter->watchdog_task); |
3457 | ||
fd13a9ab | 3458 | if (netdev->reg_state == NETREG_REGISTERED) |
92915f71 | 3459 | unregister_netdev(netdev); |
92915f71 | 3460 | |
0ac1e8ce | 3461 | ixgbevf_clear_interrupt_scheme(adapter); |
92915f71 GR |
3462 | ixgbevf_reset_interrupt_capability(adapter); |
3463 | ||
3464 | iounmap(adapter->hw.hw_addr); | |
3465 | pci_release_regions(pdev); | |
3466 | ||
3467 | hw_dbg(&adapter->hw, "Remove complete\n"); | |
3468 | ||
3469 | kfree(adapter->tx_ring); | |
3470 | kfree(adapter->rx_ring); | |
3471 | ||
3472 | free_netdev(netdev); | |
3473 | ||
3474 | pci_disable_device(pdev); | |
3475 | } | |
3476 | ||
9f19f31d AD |
3477 | /** |
3478 | * ixgbevf_io_error_detected - called when PCI error is detected | |
3479 | * @pdev: Pointer to PCI device | |
3480 | * @state: The current pci connection state | |
3481 | * | |
3482 | * This function is called after a PCI bus error affecting | |
3483 | * this device has been detected. | |
3484 | */ | |
3485 | static pci_ers_result_t ixgbevf_io_error_detected(struct pci_dev *pdev, | |
3486 | pci_channel_state_t state) | |
3487 | { | |
3488 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3489 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3490 | ||
3491 | netif_device_detach(netdev); | |
3492 | ||
3493 | if (state == pci_channel_io_perm_failure) | |
3494 | return PCI_ERS_RESULT_DISCONNECT; | |
3495 | ||
3496 | if (netif_running(netdev)) | |
3497 | ixgbevf_down(adapter); | |
3498 | ||
3499 | pci_disable_device(pdev); | |
3500 | ||
3501 | /* Request a slot slot reset. */ | |
3502 | return PCI_ERS_RESULT_NEED_RESET; | |
3503 | } | |
3504 | ||
3505 | /** | |
3506 | * ixgbevf_io_slot_reset - called after the pci bus has been reset. | |
3507 | * @pdev: Pointer to PCI device | |
3508 | * | |
3509 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
3510 | * resembles the first-half of the ixgbevf_resume routine. | |
3511 | */ | |
3512 | static pci_ers_result_t ixgbevf_io_slot_reset(struct pci_dev *pdev) | |
3513 | { | |
3514 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3515 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3516 | ||
3517 | if (pci_enable_device_mem(pdev)) { | |
3518 | dev_err(&pdev->dev, | |
3519 | "Cannot re-enable PCI device after reset.\n"); | |
3520 | return PCI_ERS_RESULT_DISCONNECT; | |
3521 | } | |
3522 | ||
3523 | pci_set_master(pdev); | |
3524 | ||
3525 | ixgbevf_reset(adapter); | |
3526 | ||
3527 | return PCI_ERS_RESULT_RECOVERED; | |
3528 | } | |
3529 | ||
3530 | /** | |
3531 | * ixgbevf_io_resume - called when traffic can start flowing again. | |
3532 | * @pdev: Pointer to PCI device | |
3533 | * | |
3534 | * This callback is called when the error recovery driver tells us that | |
3535 | * its OK to resume normal operation. Implementation resembles the | |
3536 | * second-half of the ixgbevf_resume routine. | |
3537 | */ | |
3538 | static void ixgbevf_io_resume(struct pci_dev *pdev) | |
3539 | { | |
3540 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3541 | struct ixgbevf_adapter *adapter = netdev_priv(netdev); | |
3542 | ||
3543 | if (netif_running(netdev)) | |
3544 | ixgbevf_up(adapter); | |
3545 | ||
3546 | netif_device_attach(netdev); | |
3547 | } | |
3548 | ||
3549 | /* PCI Error Recovery (ERS) */ | |
3646f0e5 | 3550 | static const struct pci_error_handlers ixgbevf_err_handler = { |
9f19f31d AD |
3551 | .error_detected = ixgbevf_io_error_detected, |
3552 | .slot_reset = ixgbevf_io_slot_reset, | |
3553 | .resume = ixgbevf_io_resume, | |
3554 | }; | |
3555 | ||
92915f71 GR |
3556 | static struct pci_driver ixgbevf_driver = { |
3557 | .name = ixgbevf_driver_name, | |
3558 | .id_table = ixgbevf_pci_tbl, | |
3559 | .probe = ixgbevf_probe, | |
3560 | .remove = __devexit_p(ixgbevf_remove), | |
0ac1e8ce AD |
3561 | #ifdef CONFIG_PM |
3562 | /* Power Management Hooks */ | |
3563 | .suspend = ixgbevf_suspend, | |
3564 | .resume = ixgbevf_resume, | |
3565 | #endif | |
92915f71 | 3566 | .shutdown = ixgbevf_shutdown, |
9f19f31d | 3567 | .err_handler = &ixgbevf_err_handler |
92915f71 GR |
3568 | }; |
3569 | ||
3570 | /** | |
65d676c8 | 3571 | * ixgbevf_init_module - Driver Registration Routine |
92915f71 | 3572 | * |
65d676c8 | 3573 | * ixgbevf_init_module is the first routine called when the driver is |
92915f71 GR |
3574 | * loaded. All it does is register with the PCI subsystem. |
3575 | **/ | |
3576 | static int __init ixgbevf_init_module(void) | |
3577 | { | |
3578 | int ret; | |
dbd9636e JK |
3579 | pr_info("%s - version %s\n", ixgbevf_driver_string, |
3580 | ixgbevf_driver_version); | |
92915f71 | 3581 | |
dbd9636e | 3582 | pr_info("%s\n", ixgbevf_copyright); |
92915f71 GR |
3583 | |
3584 | ret = pci_register_driver(&ixgbevf_driver); | |
3585 | return ret; | |
3586 | } | |
3587 | ||
3588 | module_init(ixgbevf_init_module); | |
3589 | ||
3590 | /** | |
65d676c8 | 3591 | * ixgbevf_exit_module - Driver Exit Cleanup Routine |
92915f71 | 3592 | * |
65d676c8 | 3593 | * ixgbevf_exit_module is called just before the driver is removed |
92915f71 GR |
3594 | * from memory. |
3595 | **/ | |
3596 | static void __exit ixgbevf_exit_module(void) | |
3597 | { | |
3598 | pci_unregister_driver(&ixgbevf_driver); | |
3599 | } | |
3600 | ||
3601 | #ifdef DEBUG | |
3602 | /** | |
65d676c8 | 3603 | * ixgbevf_get_hw_dev_name - return device name string |
92915f71 GR |
3604 | * used by hardware layer to print debugging information |
3605 | **/ | |
3606 | char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw) | |
3607 | { | |
3608 | struct ixgbevf_adapter *adapter = hw->back; | |
3609 | return adapter->netdev->name; | |
3610 | } | |
3611 | ||
3612 | #endif | |
3613 | module_exit(ixgbevf_exit_module); | |
3614 | ||
3615 | /* ixgbevf_main.c */ |