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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
e1befd77 42static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
11afc1b1
PW		 43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
037c6d0a 60 u16 ext_ability = 0;
9a799d71 61
c44ade9e
JB		 62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 64 hw->phy.mdio.prtad = phy_addr;
6b73e10d 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 66 ixgbe_get_phy_id(hw);
67 hw->phy.type =
68 ixgbe_get_phy_type_from_id(hw->phy.id);
037c6d0a
ET		 69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
c44ade9e
JB		 85 status = 0;
86 break;
87 }
9a799d71 88 }
63d6e1d8 89 /* clear value if nothing found */
037c6d0a
ET		 90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 92 } else {
93 status = 0;
9a799d71 94 }
c44ade9e 95
9a799d71
AK		 96 return status;
97}
98
9a799d71
AK		 99/**
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
102 *
103 **/
104static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
105{
106 u32 status;
107 u16 phy_id_high = 0;
108 u16 phy_id_low = 0;
109
6b73e10d 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 111 &phy_id_high);
9a799d71
AK		 112
113 if (status == 0) {
114 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 116 &phy_id_low);
9a799d71
AK		 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
119 }
9a799d71
AK		 120 return status;
121}
122
123/**
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
126 *
127 **/
128static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
129{
130 enum ixgbe_phy_type phy_type;
131
132 switch (phy_id) {
0befdb3e
JB		 133 case TN1010_PHY_ID:
134 phy_type = ixgbe_phy_tn;
135 break;
2b264909 136 case X540_PHY_ID:
fe15e8e1
DS		 137 phy_type = ixgbe_phy_aq;
138 break;
9a799d71
AK		 139 case QT2022_PHY_ID:
140 phy_type = ixgbe_phy_qt;
141 break;
c4900be0
DS		 142 case ATH_PHY_ID:
143 phy_type = ixgbe_phy_nl;
144 break;
9a799d71
AK		 145 default:
146 phy_type = ixgbe_phy_unknown;
147 break;
148 }
149
150 return phy_type;
151}
152
153/**
c44ade9e 154 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 155 * @hw: pointer to hardware structure
156 **/
c44ade9e 157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 158{
1783575c
ET		 159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
119fc60a
MC		 169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
1783575c 172 goto out;
119fc60a 173
9a799d71
AK		 174 /*
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
177 */
1783575c
ET		 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
9a799d71
AK		 204}
205
206/**
c44ade9e 207 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 208 * @hw: pointer to hardware structure
209 * @reg_addr: 32 bit address of PHY register to read
210 * @phy_data: Pointer to read data from PHY register
211 **/
c44ade9e
JB		 212s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
213 u32 device_type, u16 *phy_data)
9a799d71
AK		 214{
215 u32 command;
216 u32 i;
9a799d71
AK		 217 u32 data;
218 s32 status = 0;
219 u16 gssr;
220
221 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
222 gssr = IXGBE_GSSR_PHY1_SM;
223 else
224 gssr = IXGBE_GSSR_PHY0_SM;
225
5e655105 226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
9a799d71
AK		 227 status = IXGBE_ERR_SWFW_SYNC;
228
229 if (status == 0) {
230 /* Setup and write the address cycle command */
231 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 232 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 233 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 234 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 235
236 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
237
238 /*
239 * Check every 10 usec to see if the address cycle completed.
240 * The MDI Command bit will clear when the operation is
241 * complete
242 */
c44ade9e 243 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 244 udelay(10);
245
246 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
247
248 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
249 break;
250 }
251
252 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
253 hw_dbg(hw, "PHY address command did not complete.\n");
254 status = IXGBE_ERR_PHY;
255 }
256
257 if (status == 0) {
258 /*
259 * Address cycle complete, setup and write the read
260 * command
261 */
262 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 263 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 264 (hw->phy.mdio.prtad <<
265 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 266 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 267
268 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
269
270 /*
271 * Check every 10 usec to see if the address cycle
272 * completed. The MDI Command bit will clear when the
273 * operation is complete
274 */
c44ade9e 275 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 276 udelay(10);
277
278 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
279
280 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
281 break;
282 }
283
284 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 285 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 286 status = IXGBE_ERR_PHY;
287 } else {
288 /*
289 * Read operation is complete. Get the data
290 * from MSRWD
291 */
292 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
293 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
294 *phy_data = (u16)(data);
295 }
296 }
297
5e655105 298 hw->mac.ops.release_swfw_sync(hw, gssr);
9a799d71 299 }
c44ade9e 300
9a799d71
AK		 301 return status;
302}
303
304/**
c44ade9e 305 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit PHY register to write
308 * @device_type: 5 bit device type
309 * @phy_data: Data to write to the PHY register
310 **/
c44ade9e
JB		 311s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
312 u32 device_type, u16 phy_data)
9a799d71
AK		 313{
314 u32 command;
315 u32 i;
9a799d71
AK		 316 s32 status = 0;
317 u16 gssr;
318
319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
320 gssr = IXGBE_GSSR_PHY1_SM;
321 else
322 gssr = IXGBE_GSSR_PHY0_SM;
323
5e655105 324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
9a799d71
AK		 325 status = IXGBE_ERR_SWFW_SYNC;
326
327 if (status == 0) {
328 /* Put the data in the MDI single read and write data register*/
329 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
330
331 /* Setup and write the address cycle command */
332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 334 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 335 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 336
337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
338
339 /*
340 * Check every 10 usec to see if the address cycle completed.
341 * The MDI Command bit will clear when the operation is
342 * complete
343 */
c44ade9e 344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 345 udelay(10);
346
347 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
348
c44ade9e 349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 350 break;
9a799d71
AK		 351 }
352
c44ade9e
JB		 353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
354 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 355 status = IXGBE_ERR_PHY;
c44ade9e 356 }
9a799d71
AK		 357
358 if (status == 0) {
359 /*
360 * Address cycle complete, setup and write the write
361 * command
362 */
363 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 364 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 365 (hw->phy.mdio.prtad <<
366 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 367 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 368
369 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
370
371 /*
372 * Check every 10 usec to see if the address cycle
373 * completed. The MDI Command bit will clear when the
374 * operation is complete
375 */
c44ade9e 376 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 377 udelay(10);
378
379 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
380
c44ade9e 381 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 382 break;
9a799d71
AK		 383 }
384
c44ade9e
JB		 385 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
386 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 387 status = IXGBE_ERR_PHY;
c44ade9e 388 }
9a799d71
AK		 389 }
390
5e655105 391 hw->mac.ops.release_swfw_sync(hw, gssr);
9a799d71
AK		 392 }
393
394 return status;
395}
396
397/**
c44ade9e 398 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 399 * @hw: pointer to hardware structure
400 *
401 * Restart autonegotiation and PHY and waits for completion.
402 **/
c44ade9e 403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 404{
9dda1736 405 s32 status = 0;
9a799d71
AK		 406 u32 time_out;
407 u32 max_time_out = 10;
9dda1736
ET		 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
409 bool autoneg = false;
410 ixgbe_link_speed speed;
9a799d71 411
9dda1736
ET		 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
413
414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
415 /* Set or unset auto-negotiation 10G advertisement */
416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
417 MDIO_MMD_AN,
418 &autoneg_reg);
9a799d71 419
6b73e10d 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9dda1736
ET		 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 423
9dda1736
ET		 424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
425 MDIO_MMD_AN,
426 autoneg_reg);
427 }
428
429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
430 /* Set or unset auto-negotiation 1G advertisement */
431 hw->phy.ops.read_reg(hw,
432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
433 MDIO_MMD_AN,
434 &autoneg_reg);
435
436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
439
440 hw->phy.ops.write_reg(hw,
441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
442 MDIO_MMD_AN,
443 autoneg_reg);
444 }
445
446 if (speed & IXGBE_LINK_SPEED_100_FULL) {
447 /* Set or unset auto-negotiation 100M advertisement */
448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
a59e8a1a
ET		 452 autoneg_reg &= ~(ADVERTISE_100FULL |
453 ADVERTISE_100HALF);
9dda1736
ET		 454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
455 autoneg_reg |= ADVERTISE_100FULL;
456
457 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
458 MDIO_MMD_AN,
459 autoneg_reg);
460 }
9a799d71
AK		 461
462 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 463 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
464 MDIO_MMD_AN, &autoneg_reg);
9a799d71 465
6b73e10d 466 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 467
9dda1736
ET		 468 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
469 MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 470
471 /* Wait for autonegotiation to finish */
472 for (time_out = 0; time_out < max_time_out; time_out++) {
473 udelay(10);
474 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 475 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
476 MDIO_MMD_AN,
477 &autoneg_reg);
9a799d71 478
6b73e10d
BH		 479 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
480 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 481 break;
482 }
483 }
484
9dda1736 485 if (time_out == max_time_out) {
9a799d71 486 status = IXGBE_ERR_LINK_SETUP;
9dda1736
ET		 487 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
488 }
9a799d71
AK		 489
490 return status;
491}
492
493/**
c44ade9e 494 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 495 * @hw: pointer to hardware structure
496 * @speed: new link speed
497 * @autoneg: true if autonegotiation enabled
498 **/
c44ade9e
JB		 499s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
500 ixgbe_link_speed speed,
501 bool autoneg,
502 bool autoneg_wait_to_complete)
9a799d71 503{
c44ade9e 504
9a799d71
AK		 505 /*
506 * Clear autoneg_advertised and set new values based on input link
507 * speed.
508 */
509 hw->phy.autoneg_advertised = 0;
510
511 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
512 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 513
9a799d71
AK		 514 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
515 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
516
9dda1736
ET		 517 if (speed & IXGBE_LINK_SPEED_100_FULL)
518 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
519
9a799d71 520 /* Setup link based on the new speed settings */
c44ade9e 521 hw->phy.ops.setup_link(hw);
9a799d71
AK		 522
523 return 0;
524}
c44ade9e 525
a391f1d5
DS		 526/**
527 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
528 * @hw: pointer to hardware structure
529 * @speed: pointer to link speed
530 * @autoneg: boolean auto-negotiation value
531 *
532 * Determines the link capabilities by reading the AUTOC register.
533 */
534s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 535 ixgbe_link_speed *speed,
536 bool *autoneg)
a391f1d5
DS		 537{
538 s32 status = IXGBE_ERR_LINK_SETUP;
539 u16 speed_ability;
540
541 *speed = 0;
542 *autoneg = true;
543
544 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
545 &speed_ability);
546
547 if (status == 0) {
548 if (speed_ability & MDIO_SPEED_10G)
549 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
550 if (speed_ability & MDIO_PMA_SPEED_1000)
551 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
552 if (speed_ability & MDIO_PMA_SPEED_100)
553 *speed |= IXGBE_LINK_SPEED_100_FULL;
554 }
555
556 return status;
557}
558
9dda1736
ET		 559/**
560 * ixgbe_check_phy_link_tnx - Determine link and speed status
561 * @hw: pointer to hardware structure
562 *
563 * Reads the VS1 register to determine if link is up and the current speed for
564 * the PHY.
565 **/
566s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
567 bool *link_up)
568{
569 s32 status = 0;
570 u32 time_out;
571 u32 max_time_out = 10;
572 u16 phy_link = 0;
573 u16 phy_speed = 0;
574 u16 phy_data = 0;
575
576 /* Initialize speed and link to default case */
577 *link_up = false;
578 *speed = IXGBE_LINK_SPEED_10GB_FULL;
579
580 /*
581 * Check current speed and link status of the PHY register.
582 * This is a vendor specific register and may have to
583 * be changed for other copper PHYs.
584 */
585 for (time_out = 0; time_out < max_time_out; time_out++) {
586 udelay(10);
587 status = hw->phy.ops.read_reg(hw,
588 MDIO_STAT1,
589 MDIO_MMD_VEND1,
590 &phy_data);
591 phy_link = phy_data &
592 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
593 phy_speed = phy_data &
594 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
595 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
596 *link_up = true;
597 if (phy_speed ==
598 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
599 *speed = IXGBE_LINK_SPEED_1GB_FULL;
600 break;
601 }
602 }
603
604 return status;
605}
606
607/**
608 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
609 * @hw: pointer to hardware structure
610 *
611 * Restart autonegotiation and PHY and waits for completion.
612 **/
613s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
614{
615 s32 status = 0;
616 u32 time_out;
617 u32 max_time_out = 10;
618 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
619 bool autoneg = false;
620 ixgbe_link_speed speed;
621
622 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
623
624 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
625 /* Set or unset auto-negotiation 10G advertisement */
626 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
627 MDIO_MMD_AN,
628 &autoneg_reg);
629
630 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
631 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
632 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
633
634 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
635 MDIO_MMD_AN,
636 autoneg_reg);
637 }
638
639 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
640 /* Set or unset auto-negotiation 1G advertisement */
641 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
642 MDIO_MMD_AN,
643 &autoneg_reg);
644
645 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
646 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
647 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
648
649 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
650 MDIO_MMD_AN,
651 autoneg_reg);
652 }
653
654 if (speed & IXGBE_LINK_SPEED_100_FULL) {
655 /* Set or unset auto-negotiation 100M advertisement */
656 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
657 MDIO_MMD_AN,
658 &autoneg_reg);
659
50c022e7
ET		 660 autoneg_reg &= ~(ADVERTISE_100FULL |
661 ADVERTISE_100HALF);
9dda1736
ET		 662 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
663 autoneg_reg |= ADVERTISE_100FULL;
664
665 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
666 MDIO_MMD_AN,
667 autoneg_reg);
668 }
669
670 /* Restart PHY autonegotiation and wait for completion */
671 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
672 MDIO_MMD_AN, &autoneg_reg);
673
674 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
675
676 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
677 MDIO_MMD_AN, autoneg_reg);
678
679 /* Wait for autonegotiation to finish */
680 for (time_out = 0; time_out < max_time_out; time_out++) {
681 udelay(10);
682 /* Restart PHY autonegotiation and wait for completion */
683 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
684 MDIO_MMD_AN,
685 &autoneg_reg);
686
687 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
688 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
689 break;
690 }
691
692 if (time_out == max_time_out) {
693 status = IXGBE_ERR_LINK_SETUP;
694 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
695 }
696
697 return status;
698}
699
700/**
701 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
702 * @hw: pointer to hardware structure
703 * @firmware_version: pointer to the PHY Firmware Version
704 **/
705s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
706 u16 *firmware_version)
707{
708 s32 status = 0;
709
710 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
711 MDIO_MMD_VEND1,
712 firmware_version);
713
714 return status;
715}
716
717/**
718 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
719 * @hw: pointer to hardware structure
720 * @firmware_version: pointer to the PHY Firmware Version
721 **/
722s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
723 u16 *firmware_version)
724{
725 s32 status = 0;
726
727 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
728 MDIO_MMD_VEND1,
729 firmware_version);
730
731 return status;
732}
733
c4900be0
DS		 734/**
735 * ixgbe_reset_phy_nl - Performs a PHY reset
736 * @hw: pointer to hardware structure
737 **/
738s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
739{
740 u16 phy_offset, control, eword, edata, block_crc;
741 bool end_data = false;
742 u16 list_offset, data_offset;
743 u16 phy_data = 0;
744 s32 ret_val = 0;
745 u32 i;
746
6b73e10d 747 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 748
749 /* reset the PHY and poll for completion */
6b73e10d
BH		 750 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
751 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 752
753 for (i = 0; i < 100; i++) {
6b73e10d
BH		 754 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
755 &phy_data);
756 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0 757 break;
032b4325 758 usleep_range(10000, 20000);
c4900be0
DS		 759 }
760
6b73e10d 761 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 762 hw_dbg(hw, "PHY reset did not complete.\n");
763 ret_val = IXGBE_ERR_PHY;
764 goto out;
765 }
766
767 /* Get init offsets */
768 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
769 &data_offset);
770 if (ret_val != 0)
771 goto out;
772
773 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
774 data_offset++;
775 while (!end_data) {
776 /*
777 * Read control word from PHY init contents offset
778 */
779 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
780 control = (eword & IXGBE_CONTROL_MASK_NL) >>
781 IXGBE_CONTROL_SHIFT_NL;
782 edata = eword & IXGBE_DATA_MASK_NL;
783 switch (control) {
784 case IXGBE_DELAY_NL:
785 data_offset++;
786 hw_dbg(hw, "DELAY: %d MS\n", edata);
032b4325 787 usleep_range(edata * 1000, edata * 2000);
c4900be0
DS		 788 break;
789 case IXGBE_DATA_NL:
d6dbee86 790 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 791 data_offset++;
792 hw->eeprom.ops.read(hw, data_offset++,
793 &phy_offset);
794 for (i = 0; i < edata; i++) {
795 hw->eeprom.ops.read(hw, data_offset, &eword);
796 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 797 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 798 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
799 phy_offset);
800 data_offset++;
801 phy_offset++;
802 }
803 break;
804 case IXGBE_CONTROL_NL:
805 data_offset++;
d6dbee86 806 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 807 if (edata == IXGBE_CONTROL_EOL_NL) {
808 hw_dbg(hw, "EOL\n");
809 end_data = true;
810 } else if (edata == IXGBE_CONTROL_SOL_NL) {
811 hw_dbg(hw, "SOL\n");
812 } else {
813 hw_dbg(hw, "Bad control value\n");
814 ret_val = IXGBE_ERR_PHY;
815 goto out;
816 }
817 break;
818 default:
819 hw_dbg(hw, "Bad control type\n");
820 ret_val = IXGBE_ERR_PHY;
821 goto out;
822 }
823 }
824
825out:
826 return ret_val;
827}
828
829/**
76d97dd4 830 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
c4900be0
DS		 831 * @hw: pointer to hardware structure
832 *
76d97dd4 833 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 834 **/
835s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
836{
8ef78adc 837 struct ixgbe_adapter *adapter = hw->back;
c4900be0
DS		 838 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
839 u32 vendor_oui = 0;
553b4497 840 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 841 u8 identifier = 0;
842 u8 comp_codes_1g = 0;
843 u8 comp_codes_10g = 0;
11afc1b1 844 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 845 u8 cable_tech = 0;
ea0a04df 846 u8 cable_spec = 0;
11afc1b1 847 u16 enforce_sfp = 0;
c4900be0 848
8ca783ab
DS		 849 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
850 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
851 status = IXGBE_ERR_SFP_NOT_PRESENT;
852 goto out;
853 }
854
76d97dd4
ET		 855 status = hw->phy.ops.read_i2c_eeprom(hw,
856 IXGBE_SFF_IDENTIFIER,
c4900be0
DS		 857 &identifier);
858
76d97dd4
ET		 859 if (status == IXGBE_ERR_SWFW_SYNC ||
860 status == IXGBE_ERR_I2C ||
861 status == IXGBE_ERR_SFP_NOT_PRESENT)
862 goto err_read_i2c_eeprom;
c4900be0 863
76d97dd4
ET		 864 /* LAN ID is needed for sfp_type determination */
865 hw->mac.ops.set_lan_id(hw);
866
867 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
868 hw->phy.type = ixgbe_phy_sfp_unsupported;
869 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
870 } else {
871 status = hw->phy.ops.read_i2c_eeprom(hw,
872 IXGBE_SFF_1GBE_COMP_CODES,
873 &comp_codes_1g);
874
875 if (status == IXGBE_ERR_SWFW_SYNC ||
876 status == IXGBE_ERR_I2C ||
877 status == IXGBE_ERR_SFP_NOT_PRESENT)
878 goto err_read_i2c_eeprom;
879
880 status = hw->phy.ops.read_i2c_eeprom(hw,
881 IXGBE_SFF_10GBE_COMP_CODES,
882 &comp_codes_10g);
883
884 if (status == IXGBE_ERR_SWFW_SYNC ||
885 status == IXGBE_ERR_I2C ||
886 status == IXGBE_ERR_SFP_NOT_PRESENT)
887 goto err_read_i2c_eeprom;
888 status = hw->phy.ops.read_i2c_eeprom(hw,
889 IXGBE_SFF_CABLE_TECHNOLOGY,
890 &cable_tech);
891
892 if (status == IXGBE_ERR_SWFW_SYNC ||
893 status == IXGBE_ERR_I2C ||
894 status == IXGBE_ERR_SFP_NOT_PRESENT)
895 goto err_read_i2c_eeprom;
896
897 /* ID Module
898 * =========
899 * 0 SFP_DA_CU
900 * 1 SFP_SR
901 * 2 SFP_LR
902 * 3 SFP_DA_CORE0 - 82599-specific
903 * 4 SFP_DA_CORE1 - 82599-specific
904 * 5 SFP_SR/LR_CORE0 - 82599-specific
905 * 6 SFP_SR/LR_CORE1 - 82599-specific
906 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
907 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
908 * 9 SFP_1g_cu_CORE0 - 82599-specific
909 * 10 SFP_1g_cu_CORE1 - 82599-specific
910 */
11afc1b1 911 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 912 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 913 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
914 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
915 hw->phy.sfp_type = ixgbe_sfp_type_sr;
916 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
917 hw->phy.sfp_type = ixgbe_sfp_type_lr;
918 else
919 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
920 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 921 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 922 if (hw->bus.lan_id == 0)
923 hw->phy.sfp_type =
924 ixgbe_sfp_type_da_cu_core0;
925 else
926 hw->phy.sfp_type =
927 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 928 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
929 hw->phy.ops.read_i2c_eeprom(
930 hw, IXGBE_SFF_CABLE_SPEC_COMP,
931 &cable_spec);
932 if (cable_spec &
933 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
934 if (hw->bus.lan_id == 0)
935 hw->phy.sfp_type =
936 ixgbe_sfp_type_da_act_lmt_core0;
937 else
938 hw->phy.sfp_type =
939 ixgbe_sfp_type_da_act_lmt_core1;
940 } else {
941 hw->phy.sfp_type =
76d97dd4 942 ixgbe_sfp_type_unknown;
ea0a04df 943 }
76d97dd4
ET		 944 } else if (comp_codes_10g &
945 (IXGBE_SFF_10GBASESR_CAPABLE |
946 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 947 if (hw->bus.lan_id == 0)
948 hw->phy.sfp_type =
949 ixgbe_sfp_type_srlr_core0;
950 else
951 hw->phy.sfp_type =
952 ixgbe_sfp_type_srlr_core1;
76d97dd4 953 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 954 if (hw->bus.lan_id == 0)
955 hw->phy.sfp_type =
956 ixgbe_sfp_type_1g_cu_core0;
957 else
958 hw->phy.sfp_type =
959 ixgbe_sfp_type_1g_cu_core1;
76d97dd4 960 } else {
11afc1b1 961 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 962 }
11afc1b1 963 }
c4900be0 964
553b4497
PW		 965 if (hw->phy.sfp_type != stored_sfp_type)
966 hw->phy.sfp_setup_needed = true;
967
968 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 969 hw->phy.multispeed_fiber = false;
553b4497
PW		 970 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
971 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
972 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
973 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
974 hw->phy.multispeed_fiber = true;
975
c4900be0 976 /* Determine PHY vendor */
04193058 977 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 978 hw->phy.id = identifier;
76d97dd4 979 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 980 IXGBE_SFF_VENDOR_OUI_BYTE0,
981 &oui_bytes[0]);
76d97dd4
ET		 982
983 if (status == IXGBE_ERR_SWFW_SYNC ||
984 status == IXGBE_ERR_I2C ||
985 status == IXGBE_ERR_SFP_NOT_PRESENT)
986 goto err_read_i2c_eeprom;
987
988 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 989 IXGBE_SFF_VENDOR_OUI_BYTE1,
990 &oui_bytes[1]);
76d97dd4
ET		 991
992 if (status == IXGBE_ERR_SWFW_SYNC ||
993 status == IXGBE_ERR_I2C ||
994 status == IXGBE_ERR_SFP_NOT_PRESENT)
995 goto err_read_i2c_eeprom;
996
997 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 998 IXGBE_SFF_VENDOR_OUI_BYTE2,
999 &oui_bytes[2]);
1000
76d97dd4
ET		 1001 if (status == IXGBE_ERR_SWFW_SYNC ||
1002 status == IXGBE_ERR_I2C ||
1003 status == IXGBE_ERR_SFP_NOT_PRESENT)
1004 goto err_read_i2c_eeprom;
1005
c4900be0
DS		 1006 vendor_oui =
1007 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1008 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1009 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1010
1011 switch (vendor_oui) {
1012 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 1013 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1014 hw->phy.type =
76d97dd4 1015 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 1016 break;
1017 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 1018 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1019 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1020 else
1021 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 1022 break;
1023 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1024 hw->phy.type = ixgbe_phy_sfp_avago;
1025 break;
11afc1b1
PW		 1026 case IXGBE_SFF_VENDOR_OUI_INTEL:
1027 hw->phy.type = ixgbe_phy_sfp_intel;
1028 break;
c4900be0 1029 default:
537d58a0 1030 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1031 hw->phy.type =
76d97dd4 1032 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 1033 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1034 hw->phy.type =
1035 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 1036 else
1037 hw->phy.type = ixgbe_phy_sfp_unknown;
1038 break;
1039 }
1040 }
fa466e91 1041
76d97dd4 1042 /* Allow any DA cable vendor */
ea0a04df
DS		 1043 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1044 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 1045 status = 0;
1046 goto out;
1047 }
1048
cb836a97
DS		 1049 /* Verify supported 1G SFP modules */
1050 if (comp_codes_10g == 0 &&
1051 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1052 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
fa466e91
WJP		 1053 hw->phy.type = ixgbe_phy_sfp_unsupported;
1054 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1055 goto out;
1056 }
1057
1058 /* Anything else 82598-based is supported */
1059 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 1060 status = 0;
1061 goto out;
1062 }
1063
04193058 1064 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97
DS		 1065 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1066 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1067 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
11afc1b1
PW		 1068 /* Make sure we're a supported PHY type */
1069 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1070 status = 0;
1071 } else {
8ef78adc
PWJ		 1072 if (hw->allow_unsupported_sfp) {
1073 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1074 status = 0;
1075 } else {
1076 hw_dbg(hw,
1077 "SFP+ module not supported\n");
1078 hw->phy.type =
1079 ixgbe_phy_sfp_unsupported;
1080 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1081 }
11afc1b1
PW		 1082 }
1083 } else {
1084 status = 0;
1085 }
c4900be0
DS		 1086 }
1087
1088out:
1089 return status;
76d97dd4
ET		 1090
1091err_read_i2c_eeprom:
1092 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1093 if (hw->phy.type != ixgbe_phy_nl) {
1094 hw->phy.id = 0;
1095 hw->phy.type = ixgbe_phy_unknown;
1096 }
1097 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 1098}
1099
1100/**
76d97dd4 1101 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 1102 * @hw: pointer to hardware structure
1103 * @list_offset: offset to the SFP ID list
1104 * @data_offset: offset to the SFP data block
75f19c3c
ET		 1105 *
1106 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1107 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 1108 **/
1109s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1110 u16 *list_offset,
1111 u16 *data_offset)
1112{
1113 u16 sfp_id;
cb836a97 1114 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 1115
1116 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1117 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1118
1119 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1120 return IXGBE_ERR_SFP_NOT_PRESENT;
1121
1122 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1123 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1124 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1125
cb836a97
DS		 1126 /*
1127 * Limiting active cables and 1G Phys must be initialized as
1128 * SR modules
1129 */
1130 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1131 sfp_type == ixgbe_sfp_type_1g_cu_core0)
1132 sfp_type = ixgbe_sfp_type_srlr_core0;
1133 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1134 sfp_type == ixgbe_sfp_type_1g_cu_core1)
1135 sfp_type = ixgbe_sfp_type_srlr_core1;
1136
c4900be0
DS		 1137 /* Read offset to PHY init contents */
1138 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1139
1140 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 1141 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 1142
1143 /* Shift offset to first ID word */
1144 (*list_offset)++;
1145
1146 /*
1147 * Find the matching SFP ID in the EEPROM
1148 * and program the init sequence
1149 */
1150 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1151
1152 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 1153 if (sfp_id == sfp_type) {
c4900be0
DS		 1154 (*list_offset)++;
1155 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1156 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1157 hw_dbg(hw, "SFP+ module not supported\n");
1158 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1159 } else {
1160 break;
1161 }
1162 } else {
1163 (*list_offset) += 2;
1164 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1165 return IXGBE_ERR_PHY;
1166 }
1167 }
1168
1169 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1170 hw_dbg(hw, "No matching SFP+ module found\n");
1171 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1172 }
1173
1174 return 0;
1175}
1176
11afc1b1
PW		 1177/**
1178 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1179 * @hw: pointer to hardware structure
1180 * @byte_offset: EEPROM byte offset to read
1181 * @eeprom_data: value read
1182 *
1183 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1184 **/
1185s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1186 u8 *eeprom_data)
1187{
1188 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1189 IXGBE_I2C_EEPROM_DEV_ADDR,
1190 eeprom_data);
1191}
1192
1193/**
1194 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1195 * @hw: pointer to hardware structure
1196 * @byte_offset: EEPROM byte offset to write
1197 * @eeprom_data: value to write
1198 *
1199 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1200 **/
1201s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1202 u8 eeprom_data)
1203{
1204 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1205 IXGBE_I2C_EEPROM_DEV_ADDR,
1206 eeprom_data);
1207}
1208
1209/**
1210 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1211 * @hw: pointer to hardware structure
1212 * @byte_offset: byte offset to read
1213 * @data: value read
1214 *
1215 * Performs byte read operation to SFP module's EEPROM over I2C interface at
3fbaa3ac 1216 * a specified device address.
11afc1b1
PW		 1217 **/
1218s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1219 u8 dev_addr, u8 *data)
1220{
1221 s32 status = 0;
75f19c3c 1222 u32 max_retry = 10;
11afc1b1 1223 u32 retry = 0;
75f19c3c 1224 u16 swfw_mask = 0;
3db1cd5c 1225 bool nack = true;
3fbaa3ac 1226 *data = 0;
11afc1b1 1227
75f19c3c
ET		 1228 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1229 swfw_mask = IXGBE_GSSR_PHY1_SM;
1230 else
1231 swfw_mask = IXGBE_GSSR_PHY0_SM;
1232
11afc1b1 1233 do {
6d980c3e 1234 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1235 status = IXGBE_ERR_SWFW_SYNC;
1236 goto read_byte_out;
1237 }
1238
11afc1b1
PW		 1239 ixgbe_i2c_start(hw);
1240
1241 /* Device Address and write indication */
1242 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1243 if (status != 0)
1244 goto fail;
1245
1246 status = ixgbe_get_i2c_ack(hw);
1247 if (status != 0)
1248 goto fail;
1249
1250 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1251 if (status != 0)
1252 goto fail;
1253
1254 status = ixgbe_get_i2c_ack(hw);
1255 if (status != 0)
1256 goto fail;
1257
1258 ixgbe_i2c_start(hw);
1259
1260 /* Device Address and read indication */
1261 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1262 if (status != 0)
1263 goto fail;
1264
1265 status = ixgbe_get_i2c_ack(hw);
1266 if (status != 0)
1267 goto fail;
1268
1269 status = ixgbe_clock_in_i2c_byte(hw, data);
1270 if (status != 0)
1271 goto fail;
1272
1273 status = ixgbe_clock_out_i2c_bit(hw, nack);
1274 if (status != 0)
1275 goto fail;
1276
1277 ixgbe_i2c_stop(hw);
1278 break;
1279
1280fail:
6d980c3e 1281 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1282 msleep(100);
11afc1b1
PW		 1283 ixgbe_i2c_bus_clear(hw);
1284 retry++;
1285 if (retry < max_retry)
1286 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1287 else
1288 hw_dbg(hw, "I2C byte read error.\n");
1289
1290 } while (retry < max_retry);
1291
6d980c3e 1292 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1293
1294read_byte_out:
11afc1b1
PW		 1295 return status;
1296}
1297
1298/**
1299 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1300 * @hw: pointer to hardware structure
1301 * @byte_offset: byte offset to write
1302 * @data: value to write
1303 *
1304 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1305 * a specified device address.
1306 **/
1307s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1308 u8 dev_addr, u8 data)
1309{
1310 s32 status = 0;
1311 u32 max_retry = 1;
1312 u32 retry = 0;
75f19c3c
ET		 1313 u16 swfw_mask = 0;
1314
1315 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1316 swfw_mask = IXGBE_GSSR_PHY1_SM;
1317 else
1318 swfw_mask = IXGBE_GSSR_PHY0_SM;
1319
6d980c3e 1320 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1321 status = IXGBE_ERR_SWFW_SYNC;
1322 goto write_byte_out;
1323 }
11afc1b1
PW		 1324
1325 do {
1326 ixgbe_i2c_start(hw);
1327
1328 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1329 if (status != 0)
1330 goto fail;
1331
1332 status = ixgbe_get_i2c_ack(hw);
1333 if (status != 0)
1334 goto fail;
1335
1336 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1337 if (status != 0)
1338 goto fail;
1339
1340 status = ixgbe_get_i2c_ack(hw);
1341 if (status != 0)
1342 goto fail;
1343
1344 status = ixgbe_clock_out_i2c_byte(hw, data);
1345 if (status != 0)
1346 goto fail;
1347
1348 status = ixgbe_get_i2c_ack(hw);
1349 if (status != 0)
1350 goto fail;
1351
1352 ixgbe_i2c_stop(hw);
1353 break;
1354
1355fail:
1356 ixgbe_i2c_bus_clear(hw);
1357 retry++;
1358 if (retry < max_retry)
1359 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1360 else
1361 hw_dbg(hw, "I2C byte write error.\n");
1362 } while (retry < max_retry);
1363
6d980c3e 1364 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1365
1366write_byte_out:
11afc1b1
PW		 1367 return status;
1368}
1369
1370/**
1371 * ixgbe_i2c_start - Sets I2C start condition
1372 * @hw: pointer to hardware structure
1373 *
1374 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1375 **/
1376static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1377{
1378 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1379
1380 /* Start condition must begin with data and clock high */
1381 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1382 ixgbe_raise_i2c_clk(hw, &i2cctl);
1383
1384 /* Setup time for start condition (4.7us) */
1385 udelay(IXGBE_I2C_T_SU_STA);
1386
1387 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1388
1389 /* Hold time for start condition (4us) */
1390 udelay(IXGBE_I2C_T_HD_STA);
1391
1392 ixgbe_lower_i2c_clk(hw, &i2cctl);
1393
1394 /* Minimum low period of clock is 4.7 us */
1395 udelay(IXGBE_I2C_T_LOW);
1396
1397}
1398
1399/**
1400 * ixgbe_i2c_stop - Sets I2C stop condition
1401 * @hw: pointer to hardware structure
1402 *
1403 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1404 **/
1405static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1406{
1407 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1408
1409 /* Stop condition must begin with data low and clock high */
1410 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1411 ixgbe_raise_i2c_clk(hw, &i2cctl);
1412
1413 /* Setup time for stop condition (4us) */
1414 udelay(IXGBE_I2C_T_SU_STO);
1415
1416 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1417
1418 /* bus free time between stop and start (4.7us)*/
1419 udelay(IXGBE_I2C_T_BUF);
1420}
1421
1422/**
1423 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1424 * @hw: pointer to hardware structure
1425 * @data: data byte to clock in
1426 *
1427 * Clocks in one byte data via I2C data/clock
1428 **/
1429static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1430{
11afc1b1 1431 s32 i;
3db1cd5c 1432 bool bit = false;
11afc1b1
PW		 1433
1434 for (i = 7; i >= 0; i--) {
e1befd77 1435 ixgbe_clock_in_i2c_bit(hw, &bit);
11afc1b1 1436 *data |= bit << i;
11afc1b1
PW		 1437 }
1438
e1befd77 1439 return 0;
11afc1b1
PW		 1440}
1441
1442/**
1443 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1444 * @hw: pointer to hardware structure
1445 * @data: data byte clocked out
1446 *
1447 * Clocks out one byte data via I2C data/clock
1448 **/
1449static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1450{
1451 s32 status = 0;
1452 s32 i;
1453 u32 i2cctl;
3db1cd5c 1454 bool bit = false;
11afc1b1
PW		 1455
1456 for (i = 7; i >= 0; i--) {
1457 bit = (data >> i) & 0x1;
1458 status = ixgbe_clock_out_i2c_bit(hw, bit);
1459
1460 if (status != 0)
1461 break;
1462 }
1463
1464 /* Release SDA line (set high) */
1465 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1466 i2cctl |= IXGBE_I2C_DATA_OUT;
1467 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
176f950d 1468 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1469
1470 return status;
1471}
1472
1473/**
1474 * ixgbe_get_i2c_ack - Polls for I2C ACK
1475 * @hw: pointer to hardware structure
1476 *
1477 * Clocks in/out one bit via I2C data/clock
1478 **/
1479static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1480{
e1befd77 1481 s32 status = 0;
11afc1b1
PW		 1482 u32 i = 0;
1483 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1484 u32 timeout = 10;
3db1cd5c 1485 bool ack = true;
11afc1b1 1486
e1befd77 1487 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1 1488
11afc1b1
PW		 1489
1490 /* Minimum high period of clock is 4us */
1491 udelay(IXGBE_I2C_T_HIGH);
1492
1493 /* Poll for ACK. Note that ACK in I2C spec is
1494 * transition from 1 to 0 */
1495 for (i = 0; i < timeout; i++) {
1496 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1497 ack = ixgbe_get_i2c_data(&i2cctl);
1498
1499 udelay(1);
1500 if (ack == 0)
1501 break;
1502 }
1503
1504 if (ack == 1) {
1505 hw_dbg(hw, "I2C ack was not received.\n");
1506 status = IXGBE_ERR_I2C;
1507 }
1508
1509 ixgbe_lower_i2c_clk(hw, &i2cctl);
1510
1511 /* Minimum low period of clock is 4.7 us */
1512 udelay(IXGBE_I2C_T_LOW);
1513
11afc1b1
PW		 1514 return status;
1515}
1516
1517/**
1518 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1519 * @hw: pointer to hardware structure
1520 * @data: read data value
1521 *
1522 * Clocks in one bit via I2C data/clock
1523 **/
1524static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1525{
11afc1b1
PW		 1526 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1527
e1befd77 1528 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1529
1530 /* Minimum high period of clock is 4us */
1531 udelay(IXGBE_I2C_T_HIGH);
1532
1533 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1534 *data = ixgbe_get_i2c_data(&i2cctl);
1535
1536 ixgbe_lower_i2c_clk(hw, &i2cctl);
1537
1538 /* Minimum low period of clock is 4.7 us */
1539 udelay(IXGBE_I2C_T_LOW);
1540
e1befd77 1541 return 0;
11afc1b1
PW		 1542}
1543
1544/**
1545 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1546 * @hw: pointer to hardware structure
1547 * @data: data value to write
1548 *
1549 * Clocks out one bit via I2C data/clock
1550 **/
1551static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1552{
1553 s32 status;
1554 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1555
1556 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1557 if (status == 0) {
e1befd77 1558 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1559
1560 /* Minimum high period of clock is 4us */
1561 udelay(IXGBE_I2C_T_HIGH);
1562
1563 ixgbe_lower_i2c_clk(hw, &i2cctl);
1564
1565 /* Minimum low period of clock is 4.7 us.
1566 * This also takes care of the data hold time.
1567 */
1568 udelay(IXGBE_I2C_T_LOW);
1569 } else {
1570 status = IXGBE_ERR_I2C;
1571 hw_dbg(hw, "I2C data was not set to %X\n", data);
1572 }
1573
1574 return status;
1575}
1576/**
1577 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1578 * @hw: pointer to hardware structure
1579 * @i2cctl: Current value of I2CCTL register
1580 *
1581 * Raises the I2C clock line '0'->'1'
1582 **/
e1befd77 1583static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
11afc1b1 1584{
8f56e4b9
DS		 1585 u32 i = 0;
1586 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1587 u32 i2cctl_r = 0;
11afc1b1 1588
8f56e4b9
DS		 1589 for (i = 0; i < timeout; i++) {
1590 *i2cctl |= IXGBE_I2C_CLK_OUT;
1591 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1592 IXGBE_WRITE_FLUSH(hw);
1593 /* SCL rise time (1000ns) */
1594 udelay(IXGBE_I2C_T_RISE);
1595
1596 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1597 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1598 break;
1599 }
11afc1b1
PW		 1600}
1601
1602/**
1603 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1604 * @hw: pointer to hardware structure
1605 * @i2cctl: Current value of I2CCTL register
1606 *
1607 * Lowers the I2C clock line '1'->'0'
1608 **/
1609static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1610{
1611
1612 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1613
1614 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1615 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1616
1617 /* SCL fall time (300ns) */
1618 udelay(IXGBE_I2C_T_FALL);
1619}
1620
1621/**
1622 * ixgbe_set_i2c_data - Sets the I2C data bit
1623 * @hw: pointer to hardware structure
1624 * @i2cctl: Current value of I2CCTL register
1625 * @data: I2C data value (0 or 1) to set
1626 *
1627 * Sets the I2C data bit
1628 **/
1629static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1630{
1631 s32 status = 0;
1632
1633 if (data)
1634 *i2cctl |= IXGBE_I2C_DATA_OUT;
1635 else
1636 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1637
1638 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1639 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1640
1641 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1642 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1643
1644 /* Verify data was set correctly */
1645 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1646 if (data != ixgbe_get_i2c_data(i2cctl)) {
1647 status = IXGBE_ERR_I2C;
1648 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1649 }
1650
1651 return status;
1652}
1653
1654/**
1655 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1656 * @hw: pointer to hardware structure
1657 * @i2cctl: Current value of I2CCTL register
1658 *
1659 * Returns the I2C data bit value
1660 **/
1661static bool ixgbe_get_i2c_data(u32 *i2cctl)
1662{
1663 bool data;
1664
1665 if (*i2cctl & IXGBE_I2C_DATA_IN)
3db1cd5c 1666 data = true;
11afc1b1 1667 else
3db1cd5c 1668 data = false;
11afc1b1
PW		 1669
1670 return data;
1671}
1672
1673/**
1674 * ixgbe_i2c_bus_clear - Clears the I2C bus
1675 * @hw: pointer to hardware structure
1676 *
1677 * Clears the I2C bus by sending nine clock pulses.
1678 * Used when data line is stuck low.
1679 **/
1680static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1681{
1682 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1683 u32 i;
1684
75f19c3c
ET		 1685 ixgbe_i2c_start(hw);
1686
11afc1b1
PW		 1687 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1688
1689 for (i = 0; i < 9; i++) {
1690 ixgbe_raise_i2c_clk(hw, &i2cctl);
1691
1692 /* Min high period of clock is 4us */
1693 udelay(IXGBE_I2C_T_HIGH);
1694
1695 ixgbe_lower_i2c_clk(hw, &i2cctl);
1696
1697 /* Min low period of clock is 4.7us*/
1698 udelay(IXGBE_I2C_T_LOW);
1699 }
1700
75f19c3c
ET		 1701 ixgbe_i2c_start(hw);
1702
11afc1b1
PW		 1703 /* Put the i2c bus back to default state */
1704 ixgbe_i2c_stop(hw);
1705}
1706
119fc60a 1707/**
25985edc 1708 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
119fc60a
MC		 1709 * @hw: pointer to hardware structure
1710 *
1711 * Checks if the LASI temp alarm status was triggered due to overtemp
1712 **/
1713s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1714{
1715 s32 status = 0;
1716 u16 phy_data = 0;
1717
1718 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1719 goto out;
1720
1721 /* Check that the LASI temp alarm status was triggered */
1722 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1723 MDIO_MMD_PMAPMD, &phy_data);
1724
1725 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1726 goto out;
1727
1728 status = IXGBE_ERR_OVERTEMP;
1729out:
1730 return status;
1731}
kernel source for telekom puls (alcatel/mediatek)