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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
8c5afd6d 66#define DRV_VERSION "3.13.10-k"
9c8eb720 67const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 68static const char ixgbe_copyright[] =
434c5e39 69 "Copyright (c) 1999-2013 Intel Corporation.";
9a799d71
AK		 70
71static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 72 [board_82598] = &ixgbe_82598_info,
e8e26350 73 [board_82599] = &ixgbe_82599_info,
fe15e8e1 74 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 75};
76
77/* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 115 /* required last entry */
116 {0, }
117};
118MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
5dd2d332 120#ifdef CONFIG_IXGBE_DCA
bd0362dd 121static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 122 void *p);
bd0362dd
JC		 123static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127};
128#endif
129
1cdd1ec8
GR		 130#ifdef CONFIG_PCI_IOV
131static unsigned int max_vfs;
132module_param(max_vfs, uint, 0);
e8e9f696 133MODULE_PARM_DESC(max_vfs,
6b42a9c5 134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 135#endif /* CONFIG_PCI_IOV */
136
8ef78adc
PWJ		 137static unsigned int allow_unsupported_sfp;
138module_param(allow_unsupported_sfp, uint, 0);
139MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
b3f4d599 142#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143static int debug = -1;
144module_param(debug, int, 0);
145MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
9a799d71
AK		 147MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
b8e82001
JK		 152static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
153 u32 reg, u16 *value)
154{
155 int pos = 0;
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
168 if (!pos)
169 return -1;
170
171 pci_read_config_word(parent_dev, pos + reg, value);
172 return 0;
173}
174
175static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176{
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196}
197
7086400d
AD		 198static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199{
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203}
204
205static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206{
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
52f33af8 209 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212}
213
dcd79aeb
TI		 214struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217};
218
219static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249};
250
251
252/*
253 * ixgbe_regdump - register printout routine
254 */
255static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256{
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
c7689578 319 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 326 pr_err("%-15s", rname);
dcd79aeb 327 for (j = 0; j < 8; j++)
c7689578
JP		 328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
dcd79aeb
TI		 330 }
331
332}
333
334/*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337static void ixgbe_dump(struct ixgbe_adapter *adapter)
338{
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
729739b7 344 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 359 pr_info("Device Name state "
dcd79aeb 360 "trans_start last_rx\n");
c7689578
JP		 361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
dcd79aeb
TI		 366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 370 pr_info(" Register Name Value\n");
dcd79aeb
TI		 371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 381 pr_info(" %s %s %s %s\n",
382 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
383 "leng", "ntw", "timestamp");
dcd79aeb
TI		 384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
729739b7 386 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 387 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 388 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 389 (u64)dma_unmap_addr(tx_buffer, dma),
390 dma_unmap_len(tx_buffer, len),
391 tx_buffer->next_to_watch,
392 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 393 }
394
395 /* Print TX Rings */
396 if (!netif_msg_tx_done(adapter))
397 goto rx_ring_summary;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
400
401 /* Transmit Descriptor Formats
402 *
39ac868a 403 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 404 * +--------------------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +--------------------------------------------------------------+
39ac868a 407 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 408 * +--------------------------------------------------------------+
409 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 410 *
411 * 82598 Advanced Transmit Descriptor (Write-Back Format)
412 * +--------------------------------------------------------------+
413 * 0 | RSV [63:0] |
414 * +--------------------------------------------------------------+
415 * 8 | RSV | STA | NXTSEQ |
416 * +--------------------------------------------------------------+
417 * 63 36 35 32 31 0
418 *
419 * 82599+ Advanced Transmit Descriptor
420 * +--------------------------------------------------------------+
421 * 0 | Buffer Address [63:0] |
422 * +--------------------------------------------------------------+
423 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
424 * +--------------------------------------------------------------+
425 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
426 *
427 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
428 * +--------------------------------------------------------------+
429 * 0 | RSV [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | RSV | STA | RSV |
432 * +--------------------------------------------------------------+
433 * 63 36 35 32 31 0
dcd79aeb
TI		 434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
8ad88e37
JH		 441 pr_info("%s%s %s %s %s %s\n",
442 "T [desc] [address 63:0 ] ",
443 "[PlPOIdStDDt Ln] [bi->dma ] ",
444 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 447 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 448 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 449 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 450 if (dma_unmap_len(tx_buffer, len) > 0) {
451 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
452 i,
453 le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 456 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 457 tx_buffer->next_to_watch,
458 (u64)tx_buffer->time_stamp,
459 tx_buffer->skb);
460 if (i == tx_ring->next_to_use &&
461 i == tx_ring->next_to_clean)
462 pr_cont(" NTC/U\n");
463 else if (i == tx_ring->next_to_use)
464 pr_cont(" NTU\n");
465 else if (i == tx_ring->next_to_clean)
466 pr_cont(" NTC\n");
467 else
468 pr_cont("\n");
469
470 if (netif_msg_pktdata(adapter) &&
471 tx_buffer->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS, 16, 1,
474 tx_buffer->skb->data,
475 dma_unmap_len(tx_buffer, len),
476 true);
477 }
dcd79aeb
TI		 478 }
479 }
480
481 /* Print RX Rings Summary */
482rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 484 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
c7689578
JP		 487 pr_info("%5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
39ac868a
JH		 497 /* Receive Descriptor Formats
498 *
499 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 500 * 63 1 0
501 * +-----------------------------------------------------+
502 * 0 | Packet Buffer Address [63:1] |A0/NSE|
503 * +----------------------------------------------+------+
504 * 8 | Header Buffer Address [63:1] | DD |
505 * +-----------------------------------------------------+
506 *
507 *
39ac868a 508 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 509 *
510 * 63 48 47 32 31 30 21 20 16 15 4 3 0
511 * +------------------------------------------------------+
39ac868a
JH		 512 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
513 * | Packet | IP | | | | Type | Type |
514 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 515 * +------------------------------------------------------+
516 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
517 * +------------------------------------------------------+
518 * 63 48 47 32 31 20 19 0
39ac868a
JH		 519 *
520 * 82599+ Advanced Receive Descriptor (Read) Format
521 * 63 1 0
522 * +-----------------------------------------------------+
523 * 0 | Packet Buffer Address [63:1] |A0/NSE|
524 * +----------------------------------------------+------+
525 * 8 | Header Buffer Address [63:1] | DD |
526 * +-----------------------------------------------------+
527 *
528 *
529 * 82599+ Advanced Receive Descriptor (Write-Back) Format
530 *
531 * 63 48 47 32 31 30 21 20 17 16 4 3 0
532 * +------------------------------------------------------+
533 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
534 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
535 * |/ Flow Dir Flt ID | | | | | |
536 * +------------------------------------------------------+
537 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
538 * +------------------------------------------------------+
539 * 63 48 47 32 31 20 19 0
dcd79aeb 540 */
39ac868a 541
dcd79aeb
TI		 542 for (n = 0; n < adapter->num_rx_queues; n++) {
543 rx_ring = adapter->rx_ring[n];
c7689578
JP		 544 pr_info("------------------------------------\n");
545 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
546 pr_info("------------------------------------\n");
8ad88e37
JH		 547 pr_info("%s%s%s",
548 "R [desc] [ PktBuf A0] ",
549 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 550 "<-- Adv Rx Read format\n");
8ad88e37
JH		 551 pr_info("%s%s%s",
552 "RWB[desc] [PcsmIpSHl PtRs] ",
553 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 554 "<-- Adv Rx Write-Back format\n");
555
556 for (i = 0; i < rx_ring->count; i++) {
557 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 558 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 559 u0 = (struct my_u0 *)rx_desc;
560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
561 if (staterr & IXGBE_RXD_STAT_DD) {
562 /* Descriptor Done */
c7689578 563 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 564 "%016llX ---------------- %p", i,
565 le64_to_cpu(u0->a),
566 le64_to_cpu(u0->b),
567 rx_buffer_info->skb);
568 } else {
c7689578 569 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 570 "%016llX %016llX %p", i,
571 le64_to_cpu(u0->a),
572 le64_to_cpu(u0->b),
573 (u64)rx_buffer_info->dma,
574 rx_buffer_info->skb);
575
9c50c035
ET		 576 if (netif_msg_pktdata(adapter) &&
577 rx_buffer_info->dma) {
dcd79aeb
TI		 578 print_hex_dump(KERN_INFO, "",
579 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 580 page_address(rx_buffer_info->page) +
581 rx_buffer_info->page_offset,
f800326d 582 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 583 }
584 }
585
586 if (i == rx_ring->next_to_use)
c7689578 587 pr_cont(" NTU\n");
dcd79aeb 588 else if (i == rx_ring->next_to_clean)
c7689578 589 pr_cont(" NTC\n");
dcd79aeb 590 else
c7689578 591 pr_cont("\n");
dcd79aeb
TI		 592
593 }
594 }
595
596exit:
597 return;
598}
599
5eba3699
AV		 600static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
601{
602 u32 ctrl_ext;
603
604 /* Let firmware take over control of h/w */
605 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 607 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 608}
609
610static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
611{
612 u32 ctrl_ext;
613
614 /* Let firmware know the driver has taken over */
615 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 617 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 618}
9a799d71 619
49ce9c2c 620/**
e8e26350
PW		 621 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
622 * @adapter: pointer to adapter struct
623 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
624 * @queue: queue to map the corresponding interrupt to
625 * @msix_vector: the vector to map to the corresponding queue
626 *
627 */
628static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 629 u8 queue, u8 msix_vector)
9a799d71
AK		 630{
631 u32 ivar, index;
e8e26350
PW		 632 struct ixgbe_hw *hw = &adapter->hw;
633 switch (hw->mac.type) {
634 case ixgbe_mac_82598EB:
635 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
636 if (direction == -1)
637 direction = 0;
638 index = (((direction * 64) + queue) >> 2) & 0x1F;
639 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
640 ivar &= ~(0xFF << (8 * (queue & 0x3)));
641 ivar |= (msix_vector << (8 * (queue & 0x3)));
642 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
643 break;
644 case ixgbe_mac_82599EB:
b93a2226 645 case ixgbe_mac_X540:
e8e26350
PW		 646 if (direction == -1) {
647 /* other causes */
648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
649 index = ((queue & 1) * 8);
650 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
651 ivar &= ~(0xFF << index);
652 ivar |= (msix_vector << index);
653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
654 break;
655 } else {
656 /* tx or rx causes */
657 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
658 index = ((16 * (queue & 1)) + (8 * direction));
659 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
660 ivar &= ~(0xFF << index);
661 ivar |= (msix_vector << index);
662 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
663 break;
664 }
665 default:
666 break;
667 }
9a799d71
AK		 668}
669
fe49f04a 670static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 671 u64 qmask)
fe49f04a
AD		 672{
673 u32 mask;
674
bd508178
AD		 675 switch (adapter->hw.mac.type) {
676 case ixgbe_mac_82598EB:
fe49f04a
AD		 677 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 679 break;
680 case ixgbe_mac_82599EB:
b93a2226 681 case ixgbe_mac_X540:
fe49f04a
AD		 682 mask = (qmask & 0xFFFFFFFF);
683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
684 mask = (qmask >> 32);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 686 break;
687 default:
688 break;
fe49f04a
AD		 689 }
690}
691
729739b7
AD		 692void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
693 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 694{
729739b7
AD		 695 if (tx_buffer->skb) {
696 dev_kfree_skb_any(tx_buffer->skb);
697 if (dma_unmap_len(tx_buffer, len))
d3d00239 698 dma_unmap_single(ring->dev,
729739b7
AD		 699 dma_unmap_addr(tx_buffer, dma),
700 dma_unmap_len(tx_buffer, len),
701 DMA_TO_DEVICE);
702 } else if (dma_unmap_len(tx_buffer, len)) {
703 dma_unmap_page(ring->dev,
704 dma_unmap_addr(tx_buffer, dma),
705 dma_unmap_len(tx_buffer, len),
706 DMA_TO_DEVICE);
e5a43549 707 }
729739b7
AD		 708 tx_buffer->next_to_watch = NULL;
709 tx_buffer->skb = NULL;
710 dma_unmap_len_set(tx_buffer, len, 0);
711 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 712}
713
943561d3 714static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 715{
716 struct ixgbe_hw *hw = &adapter->hw;
717 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 718 int i;
943561d3 719 u32 data;
c84d324c 720
943561d3
AD		 721 if ((hw->fc.current_mode != ixgbe_fc_full) &&
722 (hw->fc.current_mode != ixgbe_fc_rx_pause))
723 return;
c84d324c 724
943561d3
AD		 725 switch (hw->mac.type) {
726 case ixgbe_mac_82598EB:
727 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
728 break;
729 default:
730 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
731 }
732 hwstats->lxoffrxc += data;
c84d324c 733
943561d3
AD		 734 /* refill credits (no tx hang) if we received xoff */
735 if (!data)
c84d324c 736 return;
943561d3
AD		 737
738 for (i = 0; i < adapter->num_tx_queues; i++)
739 clear_bit(__IXGBE_HANG_CHECK_ARMED,
740 &adapter->tx_ring[i]->state);
741}
742
743static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
744{
745 struct ixgbe_hw *hw = &adapter->hw;
746 struct ixgbe_hw_stats *hwstats = &adapter->stats;
747 u32 xoff[8] = {0};
2afaa00d 748 u8 tc;
943561d3
AD		 749 int i;
750 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
751
752 if (adapter->ixgbe_ieee_pfc)
753 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
754
755 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
756 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 757 return;
943561d3 758 }
c84d324c
JF		 759
760 /* update stats for each tc, only valid with PFC enabled */
761 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 762 u32 pxoffrxc;
763
c84d324c
JF		 764 switch (hw->mac.type) {
765 case ixgbe_mac_82598EB:
2afaa00d 766 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 767 break;
c84d324c 768 default:
2afaa00d 769 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 770 }
2afaa00d
PN		 771 hwstats->pxoffrxc[i] += pxoffrxc;
772 /* Get the TC for given UP */
773 tc = netdev_get_prio_tc_map(adapter->netdev, i);
774 xoff[tc] += pxoffrxc;
c84d324c
JF		 775 }
776
777 /* disarm tx queues that have received xoff frames */
778 for (i = 0; i < adapter->num_tx_queues; i++) {
779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 780
2afaa00d 781 tc = tx_ring->dcb_tc;
c84d324c
JF		 782 if (xoff[tc])
783 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 784 }
26f23d82
YZ		 785}
786
c84d324c 787static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 788{
7d7ce682 789 return ring->stats.packets;
c84d324c
JF		 790}
791
792static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
793{
794 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 795 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 796
c84d324c
JF		 797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
799
800 if (head != tail)
801 return (head < tail) ?
802 tail - head : (tail + ring->count - head);
803
804 return 0;
805}
806
807static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
808{
809 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
810 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
811 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
812 bool ret = false;
813
7d637bcc 814 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 815
816 /*
817 * Check for a hung queue, but be thorough. This verifies
818 * that a transmit has been completed since the previous
819 * check AND there is at least one packet pending. The
820 * ARMED bit is set to indicate a potential hang. The
821 * bit is cleared if a pause frame is received to remove
822 * false hang detection due to PFC or 802.3x frames. By
823 * requiring this to fail twice we avoid races with
824 * pfc clearing the ARMED bit and conditions where we
825 * run the check_tx_hang logic with a transmit completion
826 * pending but without time to complete it yet.
827 */
828 if ((tx_done_old == tx_done) && tx_pending) {
829 /* make sure it is true for two checks in a row */
830 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
831 &tx_ring->state);
832 } else {
833 /* update completed stats and continue */
834 tx_ring->tx_stats.tx_done_old = tx_done;
835 /* reset the countdown */
836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 837 }
838
c84d324c 839 return ret;
9a799d71
AK		 840}
841
c83c6cbd
AD		 842/**
843 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
844 * @adapter: driver private struct
845 **/
846static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
847{
848
849 /* Do the reset outside of interrupt context */
850 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
851 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 852 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 853 ixgbe_service_event_schedule(adapter);
854 }
855}
e01c31a5 856
9a799d71
AK		 857/**
858 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 859 * @q_vector: structure containing interrupt and ring information
e01c31a5 860 * @tx_ring: tx ring to clean
9a799d71 861 **/
fe49f04a 862static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 863 struct ixgbe_ring *tx_ring)
9a799d71 864{
fe49f04a 865 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 866 struct ixgbe_tx_buffer *tx_buffer;
867 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 868 unsigned int total_bytes = 0, total_packets = 0;
59224555 869 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 870 unsigned int i = tx_ring->next_to_clean;
871
872 if (test_bit(__IXGBE_DOWN, &adapter->state))
873 return true;
9a799d71 874
d3d00239 875 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 876 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 877 i -= tx_ring->count;
12207e49 878
729739b7 879 do {
d3d00239
AD		 880 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
881
882 /* if next_to_watch is not set then there is no work pending */
883 if (!eop_desc)
884 break;
885
7f83a9e6 886 /* prevent any other reads prior to eop_desc */
7e63bf49 887 read_barrier_depends();
7f83a9e6 888
d3d00239
AD		 889 /* if DD is not set pending work has not been completed */
890 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
891 break;
8ad494b0 892
d3d00239
AD		 893 /* clear next_to_watch to prevent false hangs */
894 tx_buffer->next_to_watch = NULL;
8ad494b0 895
091a6246
AD		 896 /* update the statistics for this packet */
897 total_bytes += tx_buffer->bytecount;
898 total_packets += tx_buffer->gso_segs;
899
fd0db0ed
AD		 900 /* free the skb */
901 dev_kfree_skb_any(tx_buffer->skb);
902
729739b7
AD		 903 /* unmap skb header data */
904 dma_unmap_single(tx_ring->dev,
905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
907 DMA_TO_DEVICE);
908
fd0db0ed
AD		 909 /* clear tx_buffer data */
910 tx_buffer->skb = NULL;
729739b7 911 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 912
729739b7
AD		 913 /* unmap remaining buffers */
914 while (tx_desc != eop_desc) {
d3d00239
AD		 915 tx_buffer++;
916 tx_desc++;
8ad494b0 917 i++;
729739b7
AD		 918 if (unlikely(!i)) {
919 i -= tx_ring->count;
d3d00239 920 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 921 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 922 }
e01c31a5 923
729739b7
AD		 924 /* unmap any remaining paged data */
925 if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(tx_ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 dma_unmap_len_set(tx_buffer, len, 0);
931 }
932 }
933
934 /* move us one more past the eop_desc for start of next pkt */
935 tx_buffer++;
936 tx_desc++;
937 i++;
938 if (unlikely(!i)) {
939 i -= tx_ring->count;
940 tx_buffer = tx_ring->tx_buffer_info;
941 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
942 }
943
944 /* issue prefetch for next Tx descriptor */
945 prefetch(tx_desc);
12207e49 946
729739b7
AD		 947 /* update budget accounting */
948 budget--;
949 } while (likely(budget));
950
951 i += tx_ring->count;
9a799d71 952 tx_ring->next_to_clean = i;
d3d00239 953 u64_stats_update_begin(&tx_ring->syncp);
b953799e 954 tx_ring->stats.bytes += total_bytes;
bd198058 955 tx_ring->stats.packets += total_packets;
d3d00239 956 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 957 q_vector->tx.total_bytes += total_bytes;
958 q_vector->tx.total_packets += total_packets;
b953799e 959
c84d324c
JF		 960 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
961 /* schedule immediate reset if we believe we hung */
962 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 963 e_err(drv, "Detected Tx Unit Hang\n"
964 " Tx Queue <%d>\n"
965 " TDH, TDT <%x>, <%x>\n"
966 " next_to_use <%x>\n"
967 " next_to_clean <%x>\n"
968 "tx_buffer_info[next_to_clean]\n"
969 " time_stamp <%lx>\n"
970 " jiffies <%lx>\n",
971 tx_ring->queue_index,
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 974 tx_ring->next_to_use, i,
975 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 976
977 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
978
979 e_info(probe,
980 "tx hang %d detected on queue %d, resetting adapter\n",
981 adapter->tx_timeout_count + 1, tx_ring->queue_index);
982
b953799e 983 /* schedule immediate reset if we believe we hung */
c83c6cbd 984 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 985
986 /* the adapter is about to reset, no point in enabling stuff */
59224555 987 return true;
b953799e 988 }
9a799d71 989
b2d96e0a
AD		 990 netdev_tx_completed_queue(txring_txq(tx_ring),
991 total_packets, total_bytes);
992
e092be60 993#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 994 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 995 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 996 /* Make sure that anybody stopping the queue after this
997 * sees the new next_to_clean.
998 */
999 smp_mb();
729739b7
AD		 1000 if (__netif_subqueue_stopped(tx_ring->netdev,
1001 tx_ring->queue_index)
1002 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1003 netif_wake_subqueue(tx_ring->netdev,
1004 tx_ring->queue_index);
5b7da515 1005 ++tx_ring->tx_stats.restart_queue;
30eba97a 1006 }
e092be60 1007 }
9a799d71 1008
59224555 1009 return !!budget;
9a799d71
AK		 1010}
1011
5dd2d332 1012#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1013static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1014 struct ixgbe_ring *tx_ring,
33cf09c9 1015 int cpu)
bd0362dd 1016{
33cf09c9 1017 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1018 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1019 u16 reg_offset;
33cf09c9 1020
33cf09c9
AD		 1021 switch (hw->mac.type) {
1022 case ixgbe_mac_82598EB:
bdda1a61 1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1024 break;
1025 case ixgbe_mac_82599EB:
b93a2226 1026 case ixgbe_mac_X540:
bdda1a61
AD		 1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1028 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1029 break;
1030 default:
bdda1a61
AD		 1031 /* for unknown hardware do not write register */
1032 return;
bd0362dd 1033 }
bdda1a61
AD		 1034
1035 /*
1036 * We can enable relaxed ordering for reads, but not writes when
1037 * DCA is enabled. This is due to a known issue in some chipsets
1038 * which will cause the DCA tag to be cleared.
1039 */
1040 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1041 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1042 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1043
1044 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1045}
1046
bdda1a61
AD		 1047static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1048 struct ixgbe_ring *rx_ring,
33cf09c9 1049 int cpu)
bd0362dd 1050{
33cf09c9 1051 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1052 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1053 u8 reg_idx = rx_ring->reg_idx;
1054
33cf09c9
AD		 1055
1056 switch (hw->mac.type) {
33cf09c9 1057 case ixgbe_mac_82599EB:
b93a2226 1058 case ixgbe_mac_X540:
bdda1a61 1059 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1060 break;
1061 default:
1062 break;
1063 }
bdda1a61
AD		 1064
1065 /*
1066 * We can enable relaxed ordering for reads, but not writes when
1067 * DCA is enabled. This is due to a known issue in some chipsets
1068 * which will cause the DCA tag to be cleared.
1069 */
1070 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1071 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1072
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1074}
1075
1076static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1077{
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1079 struct ixgbe_ring *ring;
bd0362dd 1080 int cpu = get_cpu();
bd0362dd 1081
33cf09c9
AD		 1082 if (q_vector->cpu == cpu)
1083 goto out_no_update;
1084
a557928e 1085 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1086 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1087
a557928e 1088 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1089 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1090
1091 q_vector->cpu = cpu;
1092out_no_update:
bd0362dd
JC		 1093 put_cpu();
1094}
1095
1096static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1097{
1098 int i;
1099
1100 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1101 return;
1102
e35ec126
AD		 1103 /* always use CB2 mode, difference is masked in the CB driver */
1104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1105
49c7ffbe 1106 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1107 adapter->q_vector[i]->cpu = -1;
1108 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1109 }
1110}
1111
1112static int __ixgbe_notify_dca(struct device *dev, void *data)
1113{
c60fbb00 1114 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1115 unsigned long event = *(unsigned long *)data;
1116
2a72c31e 1117 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1118 return 0;
1119
bd0362dd
JC		 1120 switch (event) {
1121 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1122 /* if we're already enabled, don't do it again */
1123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1124 break;
652f093f 1125 if (dca_add_requester(dev) == 0) {
96b0e0f6 1126 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1127 ixgbe_setup_dca(adapter);
1128 break;
1129 }
1130 /* Fall Through since DCA is disabled. */
1131 case DCA_PROVIDER_REMOVE:
1132 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1133 dca_remove_requester(dev);
1134 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1136 }
1137 break;
1138 }
1139
652f093f 1140 return 0;
bd0362dd 1141}
67a74ee2 1142
bdda1a61 1143#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1144static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1145 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1146 struct sk_buff *skb)
1147{
8a0da21b
AD		 1148 if (ring->netdev->features & NETIF_F_RXHASH)
1149 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1150}
1151
f800326d 1152#ifdef IXGBE_FCOE
ff886dfc
AD		 1153/**
1154 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1155 * @ring: structure containing ring specific data
ff886dfc
AD		 1156 * @rx_desc: advanced rx descriptor
1157 *
1158 * Returns : true if it is FCoE pkt
1159 */
57efd44c 1160static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1161 union ixgbe_adv_rx_desc *rx_desc)
1162{
1163 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1164
57efd44c 1165 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1166 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1167 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1168 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1169}
1170
f800326d 1171#endif /* IXGBE_FCOE */
e59bd25d
AV		 1172/**
1173 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1174 * @ring: structure containing ring specific data
1175 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1176 * @skb: skb currently being received and modified
1177 **/
8a0da21b 1178static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1179 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1180 struct sk_buff *skb)
9a799d71 1181{
8a0da21b 1182 skb_checksum_none_assert(skb);
9a799d71 1183
712744be 1184 /* Rx csum disabled */
8a0da21b 1185 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1186 return;
e59bd25d
AV		 1187
1188 /* if IP and error */
f56e0cb1
AD		 1189 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1190 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1191 ring->rx_stats.csum_err++;
9a799d71
AK		 1192 return;
1193 }
e59bd25d 1194
f56e0cb1 1195 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1196 return;
1197
f56e0cb1 1198 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1199 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1200
1201 /*
1202 * 82599 errata, UDP frames with a 0 checksum can be marked as
1203 * checksum errors.
1204 */
8a0da21b
AD		 1205 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1206 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1207 return;
1208
8a0da21b 1209 ring->rx_stats.csum_err++;
e59bd25d
AV		 1210 return;
1211 }
1212
9a799d71 1213 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1215}
1216
84ea2591 1217static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1218{
f56e0cb1 1219 rx_ring->next_to_use = val;
f800326d
AD		 1220
1221 /* update next to alloc since we have filled the ring */
1222 rx_ring->next_to_alloc = val;
e8e26350
PW		 1223 /*
1224 * Force memory writes to complete before letting h/w
1225 * know there are new descriptors to fetch. (Only
1226 * applicable for weak-ordered memory model archs,
1227 * such as IA-64).
1228 */
1229 wmb();
84ea2591 1230 writel(val, rx_ring->tail);
e8e26350
PW		 1231}
1232
f990b79b
AD		 1233static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1234 struct ixgbe_rx_buffer *bi)
1235{
1236 struct page *page = bi->page;
f800326d 1237 dma_addr_t dma = bi->dma;
f990b79b 1238
f800326d
AD		 1239 /* since we are recycling buffers we should seldom need to alloc */
1240 if (likely(dma))
f990b79b
AD		 1241 return true;
1242
f800326d
AD		 1243 /* alloc new page for storage */
1244 if (likely(!page)) {
0614002b
MG		 1245 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1246 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1247 if (unlikely(!page)) {
1248 rx_ring->rx_stats.alloc_rx_page_failed++;
1249 return false;
1250 }
f800326d 1251 bi->page = page;
f990b79b
AD		 1252 }
1253
f800326d
AD		 1254 /* map page for use */
1255 dma = dma_map_page(rx_ring->dev, page, 0,
1256 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1257
1258 /*
1259 * if mapping failed free memory back to system since
1260 * there isn't much point in holding memory we can't use
1261 */
1262 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1263 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1264 bi->page = NULL;
f990b79b 1265
f990b79b
AD		 1266 rx_ring->rx_stats.alloc_rx_page_failed++;
1267 return false;
1268 }
1269
f800326d 1270 bi->dma = dma;
afaa9459 1271 bi->page_offset = 0;
f800326d 1272
f990b79b
AD		 1273 return true;
1274}
1275
9a799d71 1276/**
f990b79b 1277 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1278 * @rx_ring: ring to place buffers on
1279 * @cleaned_count: number of buffers to replace
9a799d71 1280 **/
fc77dc3c 1281void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1282{
9a799d71 1283 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1284 struct ixgbe_rx_buffer *bi;
d5f398ed 1285 u16 i = rx_ring->next_to_use;
9a799d71 1286
f800326d
AD		 1287 /* nothing to do */
1288 if (!cleaned_count)
fc77dc3c
AD		 1289 return;
1290
e4f74028 1291 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1292 bi = &rx_ring->rx_buffer_info[i];
1293 i -= rx_ring->count;
9a799d71 1294
f800326d
AD		 1295 do {
1296 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1297 break;
d5f398ed 1298
f800326d
AD		 1299 /*
1300 * Refresh the desc even if buffer_addrs didn't change
1301 * because each write-back erases this info.
1302 */
1303 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1304
f990b79b
AD		 1305 rx_desc++;
1306 bi++;
9a799d71 1307 i++;
f990b79b 1308 if (unlikely(!i)) {
e4f74028 1309 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1310 bi = rx_ring->rx_buffer_info;
1311 i -= rx_ring->count;
1312 }
1313
1314 /* clear the hdr_addr for the next_to_use descriptor */
1315 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1316
1317 cleaned_count--;
1318 } while (cleaned_count);
7c6e0a43 1319
f990b79b
AD		 1320 i += rx_ring->count;
1321
f56e0cb1 1322 if (rx_ring->next_to_use != i)
84ea2591 1323 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1324}
1325
1d2024f6
AD		 1326/**
1327 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1328 * @data: pointer to the start of the headers
1329 * @max_len: total length of section to find headers in
1330 *
1331 * This function is meant to determine the length of headers that will
1332 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1333 * motivation of doing this is to only perform one pull for IPv4 TCP
1334 * packets so that we can do basic things like calculating the gso_size
1335 * based on the average data per packet.
1336 **/
1337static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 unsigned int max_len)
1339{
1340 union {
1341 unsigned char *network;
1342 /* l2 headers */
1343 struct ethhdr *eth;
1344 struct vlan_hdr *vlan;
1345 /* l3 headers */
1346 struct iphdr *ipv4;
a048b40e 1347 struct ipv6hdr *ipv6;
1d2024f6
AD		 1348 } hdr;
1349 __be16 protocol;
1350 u8 nexthdr = 0; /* default to not TCP */
1351 u8 hlen;
1352
1353 /* this should never happen, but better safe than sorry */
1354 if (max_len < ETH_HLEN)
1355 return max_len;
1356
1357 /* initialize network frame pointer */
1358 hdr.network = data;
1359
1360 /* set first protocol and move network header forward */
1361 protocol = hdr.eth->h_proto;
1362 hdr.network += ETH_HLEN;
1363
1364 /* handle any vlan tag if present */
1365 if (protocol == __constant_htons(ETH_P_8021Q)) {
1366 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1367 return max_len;
1368
1369 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1370 hdr.network += VLAN_HLEN;
1371 }
1372
1373 /* handle L3 protocols */
1374 if (protocol == __constant_htons(ETH_P_IP)) {
1375 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1376 return max_len;
1377
1378 /* access ihl as a u8 to avoid unaligned access on ia64 */
1379 hlen = (hdr.network[0] & 0x0F) << 2;
1380
1381 /* verify hlen meets minimum size requirements */
1382 if (hlen < sizeof(struct iphdr))
1383 return hdr.network - data;
1384
ed83da12 1385 /* record next protocol if header is present */
20967f42 1386 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1387 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1388 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1389 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1390 return max_len;
1391
1392 /* record next protocol */
1393 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1394 hlen = sizeof(struct ipv6hdr);
f800326d 1395#ifdef IXGBE_FCOE
1d2024f6
AD		 1396 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1397 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1398 return max_len;
ed83da12 1399 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1400#endif
1401 } else {
1402 return hdr.network - data;
1403 }
1404
ed83da12
AD		 1405 /* relocate pointer to start of L4 header */
1406 hdr.network += hlen;
1407
a048b40e 1408 /* finally sort out TCP/UDP */
1d2024f6
AD		 1409 if (nexthdr == IPPROTO_TCP) {
1410 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1411 return max_len;
1412
1413 /* access doff as a u8 to avoid unaligned access on ia64 */
1414 hlen = (hdr.network[12] & 0xF0) >> 2;
1415
1416 /* verify hlen meets minimum size requirements */
1417 if (hlen < sizeof(struct tcphdr))
1418 return hdr.network - data;
1419
1420 hdr.network += hlen;
a048b40e
AD		 1421 } else if (nexthdr == IPPROTO_UDP) {
1422 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1423 return max_len;
1424
1425 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1426 }
1427
1428 /*
1429 * If everything has gone correctly hdr.network should be the
1430 * data section of the packet and will be the end of the header.
1431 * If not then it probably represents the end of the last recognized
1432 * header.
1433 */
1434 if ((hdr.network - data) < max_len)
1435 return hdr.network - data;
1436 else
1437 return max_len;
1438}
1439
1d2024f6
AD		 1440static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1441 struct sk_buff *skb)
1442{
f800326d 1443 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1444
1445 /* set gso_size to avoid messing up TCP MSS */
1446 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1447 IXGBE_CB(skb)->append_cnt);
96be80ab 1448 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1449}
1450
1451static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1452 struct sk_buff *skb)
1453{
1454 /* if append_cnt is 0 then frame is not RSC */
1455 if (!IXGBE_CB(skb)->append_cnt)
1456 return;
1457
1458 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1459 rx_ring->rx_stats.rsc_flush++;
1460
1461 ixgbe_set_rsc_gso_size(rx_ring, skb);
1462
1463 /* gso_size is computed using append_cnt so always clear it last */
1464 IXGBE_CB(skb)->append_cnt = 0;
1465}
1466
8a0da21b
AD		 1467/**
1468 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1469 * @rx_ring: rx descriptor ring packet is being transacted on
1470 * @rx_desc: pointer to the EOP Rx descriptor
1471 * @skb: pointer to current skb being populated
f8212f97 1472 *
8a0da21b
AD		 1473 * This function checks the ring, descriptor, and packet information in
1474 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1475 * other fields within the skb.
f8212f97 1476 **/
8a0da21b
AD		 1477static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
f8212f97 1480{
43e95f11
JF		 1481 struct net_device *dev = rx_ring->netdev;
1482
8a0da21b
AD		 1483 ixgbe_update_rsc_stats(rx_ring, skb);
1484
1485 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1486
8a0da21b
AD		 1487 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1488
6cb562d6 1489 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1490
f646968f 1491 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1492 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1493 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1494 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1495 }
1496
8a0da21b 1497 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1498
43e95f11 1499 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1500}
1501
8a0da21b
AD		 1502static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1503 struct sk_buff *skb)
aa80175a 1504{
8a0da21b
AD		 1505 struct ixgbe_adapter *adapter = q_vector->adapter;
1506
1507 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1508 napi_gro_receive(&q_vector->napi, skb);
1509 else
1510 netif_rx(skb);
aa80175a 1511}
43634e82 1512
f800326d
AD		 1513/**
1514 * ixgbe_is_non_eop - process handling of non-EOP buffers
1515 * @rx_ring: Rx ring being processed
1516 * @rx_desc: Rx descriptor for current buffer
1517 * @skb: Current socket buffer containing buffer in progress
1518 *
1519 * This function updates next to clean. If the buffer is an EOP buffer
1520 * this function exits returning false, otherwise it will place the
1521 * sk_buff in the next buffer to be chained and return true indicating
1522 * that this is in fact a non-EOP buffer.
1523 **/
1524static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1525 union ixgbe_adv_rx_desc *rx_desc,
1526 struct sk_buff *skb)
1527{
1528 u32 ntc = rx_ring->next_to_clean + 1;
1529
1530 /* fetch, update, and store next to clean */
1531 ntc = (ntc < rx_ring->count) ? ntc : 0;
1532 rx_ring->next_to_clean = ntc;
1533
1534 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1535
5a02cbd1
AD		 1536 /* update RSC append count if present */
1537 if (ring_is_rsc_enabled(rx_ring)) {
1538 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1539 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1540
1541 if (unlikely(rsc_enabled)) {
1542 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1543
1544 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1545 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1546
5a02cbd1
AD		 1547 /* update ntc based on RSC value */
1548 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1549 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1550 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1551 }
f800326d
AD		 1552 }
1553
5a02cbd1
AD		 1554 /* if we are the last buffer then there is nothing else to do */
1555 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1556 return false;
1557
f800326d
AD		 1558 /* place skb in next buffer to be received */
1559 rx_ring->rx_buffer_info[ntc].skb = skb;
1560 rx_ring->rx_stats.non_eop_descs++;
1561
1562 return true;
1563}
1564
19861ce2
AD		 1565/**
1566 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1567 * @rx_ring: rx descriptor ring packet is being transacted on
1568 * @skb: pointer to current skb being adjusted
1569 *
1570 * This function is an ixgbe specific version of __pskb_pull_tail. The
1571 * main difference between this version and the original function is that
1572 * this function can make several assumptions about the state of things
1573 * that allow for significant optimizations versus the standard function.
1574 * As a result we can do things like drop a frag and maintain an accurate
1575 * truesize for the skb.
1576 */
1577static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1578 struct sk_buff *skb)
1579{
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1581 unsigned char *va;
1582 unsigned int pull_len;
1583
1584 /*
1585 * it is valid to use page_address instead of kmap since we are
1586 * working with pages allocated out of the lomem pool per
1587 * alloc_page(GFP_ATOMIC)
1588 */
1589 va = skb_frag_address(frag);
1590
1591 /*
1592 * we need the header to contain the greater of either ETH_HLEN or
1593 * 60 bytes if the skb->len is less than 60 for skb_pad.
1594 */
cf3fe7ac 1595 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1596
1597 /* align pull length to size of long to optimize memcpy performance */
1598 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1599
1600 /* update all of the pointers */
1601 skb_frag_size_sub(frag, pull_len);
1602 frag->page_offset += pull_len;
1603 skb->data_len -= pull_len;
1604 skb->tail += pull_len;
19861ce2
AD		 1605}
1606
42073d91
AD		 1607/**
1608 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1609 * @rx_ring: rx descriptor ring packet is being transacted on
1610 * @skb: pointer to current skb being updated
1611 *
1612 * This function provides a basic DMA sync up for the first fragment of an
1613 * skb. The reason for doing this is that the first fragment cannot be
1614 * unmapped until we have reached the end of packet descriptor for a buffer
1615 * chain.
1616 */
1617static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1618 struct sk_buff *skb)
1619{
1620 /* if the page was released unmap it, else just sync our portion */
1621 if (unlikely(IXGBE_CB(skb)->page_released)) {
1622 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1623 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1624 IXGBE_CB(skb)->page_released = false;
1625 } else {
1626 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1627
1628 dma_sync_single_range_for_cpu(rx_ring->dev,
1629 IXGBE_CB(skb)->dma,
1630 frag->page_offset,
1631 ixgbe_rx_bufsz(rx_ring),
1632 DMA_FROM_DEVICE);
1633 }
1634 IXGBE_CB(skb)->dma = 0;
1635}
1636
f800326d
AD		 1637/**
1638 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1639 * @rx_ring: rx descriptor ring packet is being transacted on
1640 * @rx_desc: pointer to the EOP Rx descriptor
1641 * @skb: pointer to current skb being fixed
1642 *
1643 * Check for corrupted packet headers caused by senders on the local L2
1644 * embedded NIC switch not setting up their Tx Descriptors right. These
1645 * should be very rare.
1646 *
1647 * Also address the case where we are pulling data in on pages only
1648 * and as such no data is present in the skb header.
1649 *
1650 * In addition if skb is not at least 60 bytes we need to pad it so that
1651 * it is large enough to qualify as a valid Ethernet frame.
1652 *
1653 * Returns true if an error was encountered and skb was freed.
1654 **/
1655static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1656 union ixgbe_adv_rx_desc *rx_desc,
1657 struct sk_buff *skb)
1658{
f800326d 1659 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1660
1661 /* verify that the packet does not have any known errors */
1662 if (unlikely(ixgbe_test_staterr(rx_desc,
1663 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1664 !(netdev->features & NETIF_F_RXALL))) {
1665 dev_kfree_skb_any(skb);
1666 return true;
1667 }
1668
19861ce2 1669 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1670 if (skb_is_nonlinear(skb))
1671 ixgbe_pull_tail(rx_ring, skb);
f800326d 1672
57efd44c
AD		 1673#ifdef IXGBE_FCOE
1674 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1675 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1676 return false;
1677
1678#endif
f800326d
AD		 1679 /* if skb_pad returns an error the skb was freed */
1680 if (unlikely(skb->len < 60)) {
1681 int pad_len = 60 - skb->len;
1682
1683 if (skb_pad(skb, pad_len))
1684 return true;
1685 __skb_put(skb, pad_len);
1686 }
1687
1688 return false;
1689}
1690
f800326d
AD		 1691/**
1692 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1693 * @rx_ring: rx descriptor ring to store buffers on
1694 * @old_buff: donor buffer to have page reused
1695 *
0549ae20 1696 * Synchronizes page for reuse by the adapter
f800326d
AD		 1697 **/
1698static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1699 struct ixgbe_rx_buffer *old_buff)
1700{
1701 struct ixgbe_rx_buffer *new_buff;
1702 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1703
1704 new_buff = &rx_ring->rx_buffer_info[nta];
1705
1706 /* update, and store next to alloc */
1707 nta++;
1708 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1709
1710 /* transfer page from old buffer to new buffer */
1711 new_buff->page = old_buff->page;
1712 new_buff->dma = old_buff->dma;
0549ae20 1713 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1714
1715 /* sync the buffer for use by the device */
1716 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1717 new_buff->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
f800326d 1719 DMA_FROM_DEVICE);
f800326d
AD		 1720}
1721
1722/**
1723 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1724 * @rx_ring: rx descriptor ring to transact packets on
1725 * @rx_buffer: buffer containing page to add
1726 * @rx_desc: descriptor containing length of buffer written by hardware
1727 * @skb: sk_buff to place the data into
1728 *
0549ae20
AD		 1729 * This function will add the data contained in rx_buffer->page to the skb.
1730 * This is done either through a direct copy if the data in the buffer is
1731 * less than the skb header size, otherwise it will just attach the page as
1732 * a frag to the skb.
1733 *
1734 * The function will then update the page offset if necessary and return
1735 * true if the buffer can be reused by the adapter.
f800326d 1736 **/
0549ae20 1737static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1738 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1739 union ixgbe_adv_rx_desc *rx_desc,
1740 struct sk_buff *skb)
f800326d 1741{
0549ae20
AD		 1742 struct page *page = rx_buffer->page;
1743 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1744#if (PAGE_SIZE < 8192)
0549ae20 1745 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1746#else
1747 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1748 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1749 ixgbe_rx_bufsz(rx_ring);
1750#endif
0549ae20 1751
cf3fe7ac
AD		 1752 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1753 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1754
1755 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1756
1757 /* we can reuse buffer as-is, just make sure it is local */
1758 if (likely(page_to_nid(page) == numa_node_id()))
1759 return true;
1760
1761 /* this page cannot be reused so discard it */
1762 put_page(page);
1763 return false;
1764 }
1765
0549ae20
AD		 1766 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1767 rx_buffer->page_offset, size, truesize);
1768
09816fbe
AD		 1769 /* avoid re-using remote pages */
1770 if (unlikely(page_to_nid(page) != numa_node_id()))
1771 return false;
1772
1773#if (PAGE_SIZE < 8192)
1774 /* if we are only owner of page we can reuse it */
1775 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1776 return false;
1777
1778 /* flip page offset to other buffer */
1779 rx_buffer->page_offset ^= truesize;
1780
09816fbe
AD		 1781 /*
1782 * since we are the only owner of the page and we need to
1783 * increment it, just set the value to 2 in order to avoid
1784 * an unecessary locked operation
1785 */
1786 atomic_set(&page->_count, 2);
1787#else
1788 /* move offset up to the next cache line */
1789 rx_buffer->page_offset += truesize;
1790
1791 if (rx_buffer->page_offset > last_offset)
1792 return false;
1793
0549ae20
AD		 1794 /* bump ref count on page before it is given to the stack */
1795 get_page(page);
09816fbe 1796#endif
0549ae20
AD		 1797
1798 return true;
f800326d
AD		 1799}
1800
18806c9e
AD		 1801static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1802 union ixgbe_adv_rx_desc *rx_desc)
1803{
1804 struct ixgbe_rx_buffer *rx_buffer;
1805 struct sk_buff *skb;
1806 struct page *page;
1807
1808 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1809 page = rx_buffer->page;
1810 prefetchw(page);
1811
1812 skb = rx_buffer->skb;
1813
1814 if (likely(!skb)) {
1815 void *page_addr = page_address(page) +
1816 rx_buffer->page_offset;
1817
1818 /* prefetch first cache line of first page */
1819 prefetch(page_addr);
1820#if L1_CACHE_BYTES < 128
1821 prefetch(page_addr + L1_CACHE_BYTES);
1822#endif
1823
1824 /* allocate a skb to store the frags */
1825 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1826 IXGBE_RX_HDR_SIZE);
1827 if (unlikely(!skb)) {
1828 rx_ring->rx_stats.alloc_rx_buff_failed++;
1829 return NULL;
1830 }
1831
1832 /*
1833 * we will be copying header into skb->data in
1834 * pskb_may_pull so it is in our interest to prefetch
1835 * it now to avoid a possible cache miss
1836 */
1837 prefetchw(skb->data);
1838
1839 /*
1840 * Delay unmapping of the first packet. It carries the
1841 * header information, HW may still access the header
1842 * after the writeback. Only unmap it when EOP is
1843 * reached
1844 */
1845 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1846 goto dma_sync;
1847
1848 IXGBE_CB(skb)->dma = rx_buffer->dma;
1849 } else {
1850 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1851 ixgbe_dma_sync_frag(rx_ring, skb);
1852
1853dma_sync:
1854 /* we are reusing so sync this buffer for CPU use */
1855 dma_sync_single_range_for_cpu(rx_ring->dev,
1856 rx_buffer->dma,
1857 rx_buffer->page_offset,
1858 ixgbe_rx_bufsz(rx_ring),
1859 DMA_FROM_DEVICE);
1860 }
1861
1862 /* pull page into skb */
1863 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1864 /* hand second half of page back to the ring */
1865 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1866 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1867 /* the page has been released from the ring */
1868 IXGBE_CB(skb)->page_released = true;
1869 } else {
1870 /* we are not reusing the buffer so unmap it */
1871 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1872 ixgbe_rx_pg_size(rx_ring),
1873 DMA_FROM_DEVICE);
1874 }
1875
1876 /* clear contents of buffer_info */
1877 rx_buffer->skb = NULL;
1878 rx_buffer->dma = 0;
1879 rx_buffer->page = NULL;
1880
1881 return skb;
f800326d
AD		 1882}
1883
1884/**
1885 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1886 * @q_vector: structure containing interrupt and ring information
1887 * @rx_ring: rx descriptor ring to transact packets on
1888 * @budget: Total limit on number of packets to process
1889 *
1890 * This function provides a "bounce buffer" approach to Rx interrupt
1891 * processing. The advantage to this is that on systems that have
1892 * expensive overhead for IOMMU access this provides a means of avoiding
1893 * it by maintaining the mapping of the page to the syste.
1894 *
1895 * Returns true if all work is completed without reaching budget
1896 **/
4ff7fb12 1897static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1898 struct ixgbe_ring *rx_ring,
f4de00ed 1899 const int budget)
9a799d71 1900{
d2f4fbe2 1901 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1902#ifdef IXGBE_FCOE
f800326d 1903 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1904 int ddp_bytes;
1905 unsigned int mss = 0;
3d8fd385 1906#endif /* IXGBE_FCOE */
f800326d 1907 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1908
f800326d 1909 do {
f800326d
AD		 1910 union ixgbe_adv_rx_desc *rx_desc;
1911 struct sk_buff *skb;
f800326d
AD		 1912
1913 /* return some buffers to hardware, one at a time is too slow */
1914 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1915 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1916 cleaned_count = 0;
1917 }
1918
18806c9e 1919 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1920
1921 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1922 break;
9a799d71 1923
f800326d
AD		 1924 /*
1925 * This memory barrier is needed to keep us from reading
1926 * any other fields out of the rx_desc until we know the
1927 * RXD_STAT_DD bit is set
1928 */
1929 rmb();
9a799d71 1930
18806c9e
AD		 1931 /* retrieve a buffer from the ring */
1932 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1933
18806c9e
AD		 1934 /* exit if we failed to retrieve a buffer */
1935 if (!skb)
1936 break;
9a799d71 1937
9a799d71 1938 cleaned_count++;
f8212f97 1939
f800326d
AD		 1940 /* place incomplete frames back on ring for completion */
1941 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1942 continue;
c267fc16 1943
f800326d
AD		 1944 /* verify the packet layout is correct */
1945 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1946 continue;
9a799d71 1947
d2f4fbe2
AV		 1948 /* probably a little skewed due to removing CRC */
1949 total_rx_bytes += skb->len;
d2f4fbe2 1950
8a0da21b
AD		 1951 /* populate checksum, timestamp, VLAN, and protocol */
1952 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1953
332d4a7d
YZ		 1954#ifdef IXGBE_FCOE
1955 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1956 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1957 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1958 /* include DDPed FCoE data */
1959 if (ddp_bytes > 0) {
1960 if (!mss) {
1961 mss = rx_ring->netdev->mtu -
1962 sizeof(struct fcoe_hdr) -
1963 sizeof(struct fc_frame_header) -
1964 sizeof(struct fcoe_crc_eof);
1965 if (mss > 512)
1966 mss &= ~511;
1967 }
1968 total_rx_bytes += ddp_bytes;
1969 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1970 mss);
1971 }
63d635b2
AD		 1972 if (!ddp_bytes) {
1973 dev_kfree_skb_any(skb);
f800326d 1974 continue;
63d635b2 1975 }
3d8fd385 1976 }
f800326d 1977
332d4a7d 1978#endif /* IXGBE_FCOE */
8a0da21b 1979 ixgbe_rx_skb(q_vector, skb);
9a799d71 1980
f800326d 1981 /* update budget accounting */
f4de00ed
AD		 1982 total_rx_packets++;
1983 } while (likely(total_rx_packets < budget));
9a799d71 1984
c267fc16
AD		 1985 u64_stats_update_begin(&rx_ring->syncp);
1986 rx_ring->stats.packets += total_rx_packets;
1987 rx_ring->stats.bytes += total_rx_bytes;
1988 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1989 q_vector->rx.total_packets += total_rx_packets;
1990 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1991
f800326d
AD		 1992 if (cleaned_count)
1993 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1994
f4de00ed 1995 return (total_rx_packets < budget);
9a799d71
AK		 1996}
1997
9a799d71
AK		 1998/**
1999 * ixgbe_configure_msix - Configure MSI-X hardware
2000 * @adapter: board private structure
2001 *
2002 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2003 * interrupts.
2004 **/
2005static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2006{
021230d4 2007 struct ixgbe_q_vector *q_vector;
49c7ffbe 2008 int v_idx;
021230d4 2009 u32 mask;
9a799d71 2010
8e34d1aa
AD		 2011 /* Populate MSIX to EITR Select */
2012 if (adapter->num_vfs > 32) {
2013 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2015 }
2016
4df10466
JB		 2017 /*
2018 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2019 * corresponding register.
2020 */
49c7ffbe 2021 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2022 struct ixgbe_ring *ring;
7a921c93 2023 q_vector = adapter->q_vector[v_idx];
021230d4 2024
a557928e 2025 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2026 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2027
a557928e 2028 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2029 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2030
fe49f04a 2031 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2032 }
2033
bd508178
AD		 2034 switch (adapter->hw.mac.type) {
2035 case ixgbe_mac_82598EB:
e8e26350 2036 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2037 v_idx);
bd508178
AD		 2038 break;
2039 case ixgbe_mac_82599EB:
b93a2226 2040 case ixgbe_mac_X540:
e8e26350 2041 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2042 break;
bd508178
AD		 2043 default:
2044 break;
2045 }
021230d4
AV		 2046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2047
41fb9248 2048 /* set up to autoclear timer, and the vectors */
021230d4 2049 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2050 mask &= ~(IXGBE_EIMS_OTHER |
2051 IXGBE_EIMS_MAILBOX |
2052 IXGBE_EIMS_LSC);
2053
021230d4 2054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2055}
2056
f494e8fa
AV		 2057enum latency_range {
2058 lowest_latency = 0,
2059 low_latency = 1,
2060 bulk_latency = 2,
2061 latency_invalid = 255
2062};
2063
2064/**
2065 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2066 * @q_vector: structure containing interrupt and ring information
2067 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2068 *
2069 * Stores a new ITR value based on packets and byte
2070 * counts during the last interrupt. The advantage of per interrupt
2071 * computation is faster updates and more accurate ITR for the current
2072 * traffic pattern. Constants in this function were computed
2073 * based on theoretical maximum wire speed and thresholds were set based
2074 * on testing data as well as attempting to minimize response time
2075 * while increasing bulk throughput.
2076 * this functionality is controlled by the InterruptThrottleRate module
2077 * parameter (see ixgbe_param.c)
2078 **/
bd198058
AD		 2079static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2080 struct ixgbe_ring_container *ring_container)
f494e8fa 2081{
bd198058
AD		 2082 int bytes = ring_container->total_bytes;
2083 int packets = ring_container->total_packets;
2084 u32 timepassed_us;
621bd70e 2085 u64 bytes_perint;
bd198058 2086 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2087
2088 if (packets == 0)
bd198058 2089 return;
f494e8fa
AV		 2090
2091 /* simple throttlerate management
621bd70e
AD		 2092 * 0-10MB/s lowest (100000 ints/s)
2093 * 10-20MB/s low (20000 ints/s)
2094 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2095 */
2096 /* what was last interrupt timeslice? */
d5bf4f67 2097 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2098 if (timepassed_us == 0)
2099 return;
2100
f494e8fa
AV		 2101 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2102
2103 switch (itr_setting) {
2104 case lowest_latency:
621bd70e 2105 if (bytes_perint > 10)
bd198058 2106 itr_setting = low_latency;
f494e8fa
AV		 2107 break;
2108 case low_latency:
621bd70e 2109 if (bytes_perint > 20)
bd198058 2110 itr_setting = bulk_latency;
621bd70e 2111 else if (bytes_perint <= 10)
bd198058 2112 itr_setting = lowest_latency;
f494e8fa
AV		 2113 break;
2114 case bulk_latency:
621bd70e 2115 if (bytes_perint <= 20)
bd198058 2116 itr_setting = low_latency;
f494e8fa
AV		 2117 break;
2118 }
2119
bd198058
AD		 2120 /* clear work counters since we have the values we need */
2121 ring_container->total_bytes = 0;
2122 ring_container->total_packets = 0;
2123
2124 /* write updated itr to ring container */
2125 ring_container->itr = itr_setting;
f494e8fa
AV		 2126}
2127
509ee935
JB		 2128/**
2129 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2130 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2131 *
2132 * This function is made to be called by ethtool and by the driver
2133 * when it needs to update EITR registers at runtime. Hardware
2134 * specific quirks/differences are taken care of here.
2135 */
fe49f04a 2136void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2137{
fe49f04a 2138 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2139 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2140 int v_idx = q_vector->v_idx;
5d967eb7 2141 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2142
bd508178
AD		 2143 switch (adapter->hw.mac.type) {
2144 case ixgbe_mac_82598EB:
509ee935
JB		 2145 /* must write high and low 16 bits to reset counter */
2146 itr_reg |= (itr_reg << 16);
bd508178
AD		 2147 break;
2148 case ixgbe_mac_82599EB:
b93a2226 2149 case ixgbe_mac_X540:
509ee935
JB		 2150 /*
2151 * set the WDIS bit to not clear the timer bits and cause an
2152 * immediate assertion of the interrupt
2153 */
2154 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2155 break;
2156 default:
2157 break;
509ee935
JB		 2158 }
2159 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2160}
2161
bd198058 2162static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2163{
d5bf4f67 2164 u32 new_itr = q_vector->itr;
bd198058 2165 u8 current_itr;
f494e8fa 2166
bd198058
AD		 2167 ixgbe_update_itr(q_vector, &q_vector->tx);
2168 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2169
08c8833b 2170 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2171
2172 switch (current_itr) {
2173 /* counts and packets in update_itr are dependent on these numbers */
2174 case lowest_latency:
d5bf4f67 2175 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2176 break;
2177 case low_latency:
d5bf4f67 2178 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2179 break;
2180 case bulk_latency:
d5bf4f67 2181 new_itr = IXGBE_8K_ITR;
f494e8fa 2182 break;
bd198058
AD		 2183 default:
2184 break;
f494e8fa
AV		 2185 }
2186
d5bf4f67 2187 if (new_itr != q_vector->itr) {
fe49f04a 2188 /* do an exponential smoothing */
d5bf4f67
ET		 2189 new_itr = (10 * new_itr * q_vector->itr) /
2190 ((9 * new_itr) + q_vector->itr);
509ee935 2191
bd198058 2192 /* save the algorithm value here */
5d967eb7 2193 q_vector->itr = new_itr;
fe49f04a
AD		 2194
2195 ixgbe_write_eitr(q_vector);
f494e8fa 2196 }
f494e8fa
AV		 2197}
2198
119fc60a 2199/**
de88eeeb 2200 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2201 * @adapter: pointer to adapter
119fc60a 2202 **/
f0f9778d 2203static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2204{
119fc60a
MC		 2205 struct ixgbe_hw *hw = &adapter->hw;
2206 u32 eicr = adapter->interrupt_event;
2207
f0f9778d 2208 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2209 return;
2210
f0f9778d
AD		 2211 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2212 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2213 return;
2214
2215 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2216
7ca647bd 2217 switch (hw->device_id) {
f0f9778d
AD		 2218 case IXGBE_DEV_ID_82599_T3_LOM:
2219 /*
2220 * Since the warning interrupt is for both ports
2221 * we don't have to check if:
2222 * - This interrupt wasn't for our port.
2223 * - We may have missed the interrupt so always have to
2224 * check if we got a LSC
2225 */
2226 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2227 !(eicr & IXGBE_EICR_LSC))
2228 return;
2229
2230 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2231 u32 speed;
f0f9778d 2232 bool link_up = false;
7ca647bd 2233
3d292265 2234 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2235
f0f9778d
AD		 2236 if (link_up)
2237 return;
2238 }
2239
2240 /* Check if this is not due to overtemp */
2241 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2242 return;
2243
2244 break;
7ca647bd
JP		 2245 default:
2246 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2247 return;
7ca647bd 2248 break;
119fc60a 2249 }
7ca647bd
JP		 2250 e_crit(drv,
2251 "Network adapter has been stopped because it has over heated. "
2252 "Restart the computer. If the problem persists, "
2253 "power off the system and replace the adapter\n");
f0f9778d
AD		 2254
2255 adapter->interrupt_event = 0;
119fc60a
MC		 2256}
2257
0befdb3e
JB		 2258static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2259{
2260 struct ixgbe_hw *hw = &adapter->hw;
2261
2262 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2263 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2264 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2265 /* write to clear the interrupt */
2266 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2267 }
2268}
cf8280ee 2269
4f51bf70
JK		 2270static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2271{
2272 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2273 return;
2274
2275 switch (adapter->hw.mac.type) {
2276 case ixgbe_mac_82599EB:
2277 /*
2278 * Need to check link state so complete overtemp check
2279 * on service task
2280 */
2281 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2282 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2283 adapter->interrupt_event = eicr;
2284 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2285 ixgbe_service_event_schedule(adapter);
2286 return;
2287 }
2288 return;
2289 case ixgbe_mac_X540:
2290 if (!(eicr & IXGBE_EICR_TS))
2291 return;
2292 break;
2293 default:
2294 return;
2295 }
2296
2297 e_crit(drv,
2298 "Network adapter has been stopped because it has over heated. "
2299 "Restart the computer. If the problem persists, "
2300 "power off the system and replace the adapter\n");
2301}
2302
e8e26350
PW		 2303static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2304{
2305 struct ixgbe_hw *hw = &adapter->hw;
2306
73c4b7cd
AD		 2307 if (eicr & IXGBE_EICR_GPI_SDP2) {
2308 /* Clear the interrupt */
2309 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2310 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2311 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2312 ixgbe_service_event_schedule(adapter);
2313 }
73c4b7cd
AD		 2314 }
2315
e8e26350
PW		 2316 if (eicr & IXGBE_EICR_GPI_SDP1) {
2317 /* Clear the interrupt */
2318 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2319 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2320 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2321 ixgbe_service_event_schedule(adapter);
2322 }
e8e26350
PW		 2323 }
2324}
2325
cf8280ee
JB		 2326static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2327{
2328 struct ixgbe_hw *hw = &adapter->hw;
2329
2330 adapter->lsc_int++;
2331 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2332 adapter->link_check_timeout = jiffies;
2333 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2334 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2335 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2336 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2337 }
2338}
2339
fe49f04a
AD		 2340static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2341 u64 qmask)
2342{
2343 u32 mask;
bd508178 2344 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2345
bd508178
AD		 2346 switch (hw->mac.type) {
2347 case ixgbe_mac_82598EB:
fe49f04a 2348 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2349 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2350 break;
2351 case ixgbe_mac_82599EB:
b93a2226 2352 case ixgbe_mac_X540:
fe49f04a 2353 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2354 if (mask)
2355 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2356 mask = (qmask >> 32);
bd508178
AD		 2357 if (mask)
2358 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2359 break;
2360 default:
2361 break;
fe49f04a
AD		 2362 }
2363 /* skip the flush */
2364}
2365
2366static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2367 u64 qmask)
fe49f04a
AD		 2368{
2369 u32 mask;
bd508178 2370 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2371
bd508178
AD		 2372 switch (hw->mac.type) {
2373 case ixgbe_mac_82598EB:
fe49f04a 2374 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2375 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2376 break;
2377 case ixgbe_mac_82599EB:
b93a2226 2378 case ixgbe_mac_X540:
fe49f04a 2379 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2380 if (mask)
2381 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2382 mask = (qmask >> 32);
bd508178
AD		 2383 if (mask)
2384 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2385 break;
2386 default:
2387 break;
fe49f04a
AD		 2388 }
2389 /* skip the flush */
2390}
2391
021230d4 2392/**
2c4af694
AD		 2393 * ixgbe_irq_enable - Enable default interrupt generation settings
2394 * @adapter: board private structure
021230d4 2395 **/
2c4af694
AD		 2396static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2397 bool flush)
9a799d71 2398{
2c4af694 2399 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2400
2c4af694
AD		 2401 /* don't reenable LSC while waiting for link */
2402 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2403 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2404
2c4af694 2405 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2406 switch (adapter->hw.mac.type) {
2407 case ixgbe_mac_82599EB:
2408 mask |= IXGBE_EIMS_GPI_SDP0;
2409 break;
2410 case ixgbe_mac_X540:
2411 mask |= IXGBE_EIMS_TS;
2412 break;
2413 default:
2414 break;
2415 }
2c4af694
AD		 2416 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2417 mask |= IXGBE_EIMS_GPI_SDP1;
2418 switch (adapter->hw.mac.type) {
2419 case ixgbe_mac_82599EB:
2c4af694
AD		 2420 mask |= IXGBE_EIMS_GPI_SDP1;
2421 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2422 case ixgbe_mac_X540:
2423 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2424 mask |= IXGBE_EIMS_MAILBOX;
2425 break;
2426 default:
2427 break;
9a799d71 2428 }
db0677fa 2429
db0677fa
JK		 2430 if (adapter->hw.mac.type == ixgbe_mac_X540)
2431 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2432
2c4af694
AD		 2433 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2434 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2435 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2436
2c4af694
AD		 2437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2438 if (queues)
2439 ixgbe_irq_enable_queues(adapter, ~0);
2440 if (flush)
2441 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2442}
2443
2c4af694 2444static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2445{
a65151ba 2446 struct ixgbe_adapter *adapter = data;
9a799d71 2447 struct ixgbe_hw *hw = &adapter->hw;
54037505 2448 u32 eicr;
91281fd3 2449
54037505
DS		 2450 /*
2451 * Workaround for Silicon errata. Use clear-by-write instead
2452 * of clear-by-read. Reading with EICS will return the
2453 * interrupt causes without clearing, which later be done
2454 * with the write to EICR.
2455 */
2456 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2457
2458 /* The lower 16bits of the EICR register are for the queue interrupts
2459 * which should be masked here in order to not accidently clear them if
2460 * the bits are high when ixgbe_msix_other is called. There is a race
2461 * condition otherwise which results in possible performance loss
2462 * especially if the ixgbe_msix_other interrupt is triggering
2463 * consistently (as it would when PPS is turned on for the X540 device)
2464 */
2465 eicr &= 0xFFFF0000;
2466
54037505 2467 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2468
cf8280ee
JB		 2469 if (eicr & IXGBE_EICR_LSC)
2470 ixgbe_check_lsc(adapter);
f0848276 2471
1cdd1ec8
GR		 2472 if (eicr & IXGBE_EICR_MAILBOX)
2473 ixgbe_msg_task(adapter);
efe3d3c8 2474
bd508178
AD		 2475 switch (hw->mac.type) {
2476 case ixgbe_mac_82599EB:
b93a2226 2477 case ixgbe_mac_X540:
2c4af694
AD		 2478 if (eicr & IXGBE_EICR_ECC)
2479 e_info(link, "Received unrecoverable ECC Err, please "
2480 "reboot\n");
c4cf55e5
PWJ		 2481 /* Handle Flow Director Full threshold interrupt */
2482 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2483 int reinit_count = 0;
c4cf55e5 2484 int i;
c4cf55e5 2485 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2486 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2487 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2488 &ring->state))
2489 reinit_count++;
2490 }
2491 if (reinit_count) {
2492 /* no more flow director interrupts until after init */
2493 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2494 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2495 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2496 }
2497 }
f0f9778d 2498 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2499 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2500 break;
2501 default:
2502 break;
c4cf55e5 2503 }
f0848276 2504
bd508178 2505 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2506
db0677fa
JK		 2507 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2508 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2509
7086400d 2510 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2511 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2512 ixgbe_irq_enable(adapter, false, false);
f0848276 2513
9a799d71 2514 return IRQ_HANDLED;
f0848276 2515}
91281fd3 2516
4ff7fb12 2517static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2518{
021230d4 2519 struct ixgbe_q_vector *q_vector = data;
91281fd3 2520
9b471446 2521 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2522
4ff7fb12
AD		 2523 if (q_vector->rx.ring || q_vector->tx.ring)
2524 napi_schedule(&q_vector->napi);
91281fd3 2525
9a799d71 2526 return IRQ_HANDLED;
91281fd3
AD		 2527}
2528
eb01b975
AD		 2529/**
2530 * ixgbe_poll - NAPI Rx polling callback
2531 * @napi: structure for representing this polling device
2532 * @budget: how many packets driver is allowed to clean
2533 *
2534 * This function is used for legacy and MSI, NAPI mode
2535 **/
8af3c33f 2536int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2537{
2538 struct ixgbe_q_vector *q_vector =
2539 container_of(napi, struct ixgbe_q_vector, napi);
2540 struct ixgbe_adapter *adapter = q_vector->adapter;
2541 struct ixgbe_ring *ring;
2542 int per_ring_budget;
2543 bool clean_complete = true;
2544
2545#ifdef CONFIG_IXGBE_DCA
2546 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2547 ixgbe_update_dca(q_vector);
2548#endif
2549
2550 ixgbe_for_each_ring(ring, q_vector->tx)
2551 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2552
2553 /* attempt to distribute budget to each queue fairly, but don't allow
2554 * the budget to go below 1 because we'll exit polling */
2555 if (q_vector->rx.count > 1)
2556 per_ring_budget = max(budget/q_vector->rx.count, 1);
2557 else
2558 per_ring_budget = budget;
2559
2560 ixgbe_for_each_ring(ring, q_vector->rx)
2561 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2562 per_ring_budget);
2563
2564 /* If all work not completed, return budget and keep polling */
2565 if (!clean_complete)
2566 return budget;
2567
2568 /* all work done, exit the polling mode */
2569 napi_complete(napi);
2570 if (adapter->rx_itr_setting & 1)
2571 ixgbe_set_itr(q_vector);
2572 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2573 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2574
2575 return 0;
2576}
2577
021230d4
AV		 2578/**
2579 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2580 * @adapter: board private structure
2581 *
2582 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2583 * interrupts from the kernel.
2584 **/
2585static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2586{
2587 struct net_device *netdev = adapter->netdev;
207867f5 2588 int vector, err;
e8e9f696 2589 int ri = 0, ti = 0;
021230d4 2590
49c7ffbe 2591 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2592 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2593 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2594
4ff7fb12 2595 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2596 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2597 "%s-%s-%d", netdev->name, "TxRx", ri++);
2598 ti++;
2599 } else if (q_vector->rx.ring) {
9fe93afd 2600 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2601 "%s-%s-%d", netdev->name, "rx", ri++);
2602 } else if (q_vector->tx.ring) {
9fe93afd 2603 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2604 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2605 } else {
2606 /* skip this unused q_vector */
2607 continue;
32aa77a4 2608 }
207867f5
AD		 2609 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2610 q_vector->name, q_vector);
9a799d71 2611 if (err) {
396e799c 2612 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2613 "Error: %d\n", err);
021230d4 2614 goto free_queue_irqs;
9a799d71 2615 }
207867f5
AD		 2616 /* If Flow Director is enabled, set interrupt affinity */
2617 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2618 /* assign the mask for this irq */
2619 irq_set_affinity_hint(entry->vector,
de88eeeb 2620 &q_vector->affinity_mask);
207867f5 2621 }
9a799d71
AK		 2622 }
2623
021230d4 2624 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2625 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2626 if (err) {
de88eeeb 2627 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2628 goto free_queue_irqs;
9a799d71
AK		 2629 }
2630
9a799d71
AK		 2631 return 0;
2632
021230d4 2633free_queue_irqs:
207867f5
AD		 2634 while (vector) {
2635 vector--;
2636 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2637 NULL);
2638 free_irq(adapter->msix_entries[vector].vector,
2639 adapter->q_vector[vector]);
2640 }
021230d4
AV		 2641 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2642 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2643 kfree(adapter->msix_entries);
2644 adapter->msix_entries = NULL;
9a799d71
AK		 2645 return err;
2646}
2647
2648/**
021230d4 2649 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2650 * @irq: interrupt number
2651 * @data: pointer to a network interface device structure
9a799d71
AK		 2652 **/
2653static irqreturn_t ixgbe_intr(int irq, void *data)
2654{
a65151ba 2655 struct ixgbe_adapter *adapter = data;
9a799d71 2656 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2657 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2658 u32 eicr;
2659
54037505 2660 /*
24ddd967 2661 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2662 * before the read of EICR.
2663 */
2664 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2665
021230d4 2666 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2667 * therefore no explicit interrupt disable is necessary */
021230d4 2668 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2669 if (!eicr) {
6af3b9eb
ET		 2670 /*
2671 * shared interrupt alert!
f47cf66e 2672 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2673 * have disabled interrupts due to EIAM
2674 * finish the workaround of silicon errata on 82598. Unmask
2675 * the interrupt that we masked before the EICR read.
2676 */
2677 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2678 ixgbe_irq_enable(adapter, true, true);
9a799d71 2679 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2680 }
9a799d71 2681
cf8280ee
JB		 2682 if (eicr & IXGBE_EICR_LSC)
2683 ixgbe_check_lsc(adapter);
021230d4 2684
bd508178
AD		 2685 switch (hw->mac.type) {
2686 case ixgbe_mac_82599EB:
e8e26350 2687 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2688 /* Fall through */
2689 case ixgbe_mac_X540:
2690 if (eicr & IXGBE_EICR_ECC)
2691 e_info(link, "Received unrecoverable ECC err, please "
2692 "reboot\n");
4f51bf70 2693 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2694 break;
2695 default:
2696 break;
2697 }
e8e26350 2698
0befdb3e 2699 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2700 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2701 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2702
b9f6ed2b
AD		 2703 /* would disable interrupts here but EIAM disabled it */
2704 napi_schedule(&q_vector->napi);
9a799d71 2705
6af3b9eb
ET		 2706 /*
2707 * re-enable link(maybe) and non-queue interrupts, no flush.
2708 * ixgbe_poll will re-enable the queue interrupts
2709 */
6af3b9eb
ET		 2710 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2711 ixgbe_irq_enable(adapter, false, false);
2712
9a799d71
AK		 2713 return IRQ_HANDLED;
2714}
2715
2716/**
2717 * ixgbe_request_irq - initialize interrupts
2718 * @adapter: board private structure
2719 *
2720 * Attempts to configure interrupts using the best available
2721 * capabilities of the hardware and kernel.
2722 **/
021230d4 2723static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2724{
2725 struct net_device *netdev = adapter->netdev;
021230d4 2726 int err;
9a799d71 2727
4cc6df29 2728 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2729 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2730 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2731 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2732 netdev->name, adapter);
4cc6df29 2733 else
a0607fd3 2734 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2735 netdev->name, adapter);
9a799d71 2736
de88eeeb 2737 if (err)
396e799c 2738 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2739
9a799d71
AK		 2740 return err;
2741}
2742
2743static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2744{
49c7ffbe 2745 int vector;
9a799d71 2746
49c7ffbe
AD		 2747 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2748 free_irq(adapter->pdev->irq, adapter);
2749 return;
2750 }
4cc6df29 2751
49c7ffbe
AD		 2752 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2753 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2754 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2755
49c7ffbe
AD		 2756 /* free only the irqs that were actually requested */
2757 if (!q_vector->rx.ring && !q_vector->tx.ring)
2758 continue;
207867f5 2759
49c7ffbe
AD		 2760 /* clear the affinity_mask in the IRQ descriptor */
2761 irq_set_affinity_hint(entry->vector, NULL);
2762
2763 free_irq(entry->vector, q_vector);
9a799d71 2764 }
49c7ffbe
AD		 2765
2766 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2767}
2768
22d5a71b
JB		 2769/**
2770 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2771 * @adapter: board private structure
2772 **/
2773static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2774{
bd508178
AD		 2775 switch (adapter->hw.mac.type) {
2776 case ixgbe_mac_82598EB:
835462fc 2777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2778 break;
2779 case ixgbe_mac_82599EB:
b93a2226 2780 case ixgbe_mac_X540:
835462fc
NS		 2781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2782 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2783 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2784 break;
2785 default:
2786 break;
22d5a71b
JB		 2787 }
2788 IXGBE_WRITE_FLUSH(&adapter->hw);
2789 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2790 int vector;
2791
2792 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2793 synchronize_irq(adapter->msix_entries[vector].vector);
2794
2795 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2796 } else {
2797 synchronize_irq(adapter->pdev->irq);
2798 }
2799}
2800
9a799d71
AK		 2801/**
2802 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2803 *
2804 **/
2805static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2806{
d5bf4f67 2807 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2808
d5bf4f67 2809 ixgbe_write_eitr(q_vector);
9a799d71 2810
e8e26350
PW		 2811 ixgbe_set_ivar(adapter, 0, 0, 0);
2812 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2813
396e799c 2814 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2815}
2816
43e69bf0
AD		 2817/**
2818 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2819 * @adapter: board private structure
2820 * @ring: structure containing ring specific data
2821 *
2822 * Configure the Tx descriptor ring after a reset.
2823 **/
84418e3b
AD		 2824void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2825 struct ixgbe_ring *ring)
43e69bf0
AD		 2826{
2827 struct ixgbe_hw *hw = &adapter->hw;
2828 u64 tdba = ring->dma;
2f1860b8 2829 int wait_loop = 10;
b88c6de2 2830 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2831 u8 reg_idx = ring->reg_idx;
43e69bf0 2832
2f1860b8 2833 /* disable queue to avoid issues while updating state */
b88c6de2 2834 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2835 IXGBE_WRITE_FLUSH(hw);
2836
43e69bf0 2837 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2838 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2839 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2840 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2841 ring->count * sizeof(union ixgbe_adv_tx_desc));
2842 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2843 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2844 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2845
b88c6de2
AD		 2846 /*
2847 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 2848 * higher than 1 when:
2849 * - ITR is 0 as it could cause false TX hangs
2850 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 2851 *
2852 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2853 * to or less than the number of on chip descriptors, which is
2854 * currently 40.
2855 */
67da097e
ET		 2856#if IS_ENABLED(CONFIG_BQL)
2857 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2858#else
e954b374 2859 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 2860#endif
b88c6de2
AD		 2861 txdctl |= (1 << 16); /* WTHRESH = 1 */
2862 else
2863 txdctl |= (8 << 16); /* WTHRESH = 8 */
2864
e954b374
AD		 2865 /*
2866 * Setting PTHRESH to 32 both improves performance
2867 * and avoids a TX hang with DFP enabled
2868 */
b88c6de2
AD		 2869 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2870 32; /* PTHRESH = 32 */
2f1860b8
AD		 2871
2872 /* reinitialize flowdirector state */
39cb681b 2873 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2874 ring->atr_sample_rate = adapter->atr_sample_rate;
2875 ring->atr_count = 0;
2876 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2877 } else {
2878 ring->atr_sample_rate = 0;
2879 }
2f1860b8 2880
fd786b7b
AD		 2881 /* initialize XPS */
2882 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2883 struct ixgbe_q_vector *q_vector = ring->q_vector;
2884
2885 if (q_vector)
2886 netif_set_xps_queue(adapter->netdev,
2887 &q_vector->affinity_mask,
2888 ring->queue_index);
2889 }
2890
c84d324c
JF		 2891 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2892
2f1860b8 2893 /* enable queue */
2f1860b8
AD		 2894 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2895
2896 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2897 if (hw->mac.type == ixgbe_mac_82598EB &&
2898 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2899 return;
2900
2901 /* poll to verify queue is enabled */
2902 do {
032b4325 2903 usleep_range(1000, 2000);
2f1860b8
AD		 2904 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2905 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2906 if (!wait_loop)
2907 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2908}
2909
120ff942
AD		 2910static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2911{
2912 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2913 u32 rttdcs, mtqc;
8b1c0b24 2914 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2915
2916 if (hw->mac.type == ixgbe_mac_82598EB)
2917 return;
2918
2919 /* disable the arbiter while setting MTQC */
2920 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2921 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2922 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2923
2924 /* set transmit pool layout */
671c0adb
AD		 2925 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2926 mtqc = IXGBE_MTQC_VT_ENA;
2927 if (tcs > 4)
2928 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2929 else if (tcs > 1)
2930 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2931 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2932 mtqc |= IXGBE_MTQC_32VF;
2933 else
2934 mtqc |= IXGBE_MTQC_64VF;
2935 } else {
2936 if (tcs > 4)
2937 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2938 else if (tcs > 1)
2939 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2940 else
671c0adb
AD		 2941 mtqc = IXGBE_MTQC_64Q_1PB;
2942 }
120ff942 2943
671c0adb 2944 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2945
671c0adb
AD		 2946 /* Enable Security TX Buffer IFG for multiple pb */
2947 if (tcs) {
2948 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2949 sectx |= IXGBE_SECTX_DCB;
2950 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2951 }
2952
2953 /* re-enable the arbiter */
2954 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2955 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2956}
2957
9a799d71 2958/**
3a581073 2959 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2960 * @adapter: board private structure
2961 *
2962 * Configure the Tx unit of the MAC after a reset.
2963 **/
2964static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2965{
2f1860b8
AD		 2966 struct ixgbe_hw *hw = &adapter->hw;
2967 u32 dmatxctl;
43e69bf0 2968 u32 i;
9a799d71 2969
2f1860b8
AD		 2970 ixgbe_setup_mtqc(adapter);
2971
2972 if (hw->mac.type != ixgbe_mac_82598EB) {
2973 /* DMATXCTL.EN must be before Tx queues are enabled */
2974 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2975 dmatxctl |= IXGBE_DMATXCTL_TE;
2976 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2977 }
2978
9a799d71 2979 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2980 for (i = 0; i < adapter->num_tx_queues; i++)
2981 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2982}
2983
3ebe8fde
AD		 2984static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2985 struct ixgbe_ring *ring)
2986{
2987 struct ixgbe_hw *hw = &adapter->hw;
2988 u8 reg_idx = ring->reg_idx;
2989 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2990
2991 srrctl |= IXGBE_SRRCTL_DROP_EN;
2992
2993 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2994}
2995
2996static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2997 struct ixgbe_ring *ring)
2998{
2999 struct ixgbe_hw *hw = &adapter->hw;
3000 u8 reg_idx = ring->reg_idx;
3001 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3002
3003 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3004
3005 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3006}
3007
3008#ifdef CONFIG_IXGBE_DCB
3009void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3010#else
3011static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3012#endif
3013{
3014 int i;
3015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3016
3017 if (adapter->ixgbe_ieee_pfc)
3018 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3019
3020 /*
3021 * We should set the drop enable bit if:
3022 * SR-IOV is enabled
3023 * or
3024 * Number of Rx queues > 1 and flow control is disabled
3025 *
3026 * This allows us to avoid head of line blocking for security
3027 * and performance reasons.
3028 */
3029 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3030 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3031 for (i = 0; i < adapter->num_rx_queues; i++)
3032 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3033 } else {
3034 for (i = 0; i < adapter->num_rx_queues; i++)
3035 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3036 }
3037}
3038
e8e26350 3039#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3040
a6616b42 3041static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3042 struct ixgbe_ring *rx_ring)
cc41ac7c 3043{
45e9baa5 3044 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3045 u32 srrctl;
bf29ee6c 3046 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3047
45e9baa5
AD		 3048 if (hw->mac.type == ixgbe_mac_82598EB) {
3049 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3050
45e9baa5
AD		 3051 /*
3052 * if VMDq is not active we must program one srrctl register
3053 * per RSS queue since we have enabled RDRXCTL.MVMEN
3054 */
3055 reg_idx &= mask;
3056 }
cc41ac7c 3057
45e9baa5
AD		 3058 /* configure header buffer length, needed for RSC */
3059 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3060
45e9baa5 3061 /* configure the packet buffer length */
f800326d 3062 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3063
3064 /* configure descriptor type */
f800326d 3065 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3066
45e9baa5 3067 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3068}
9a799d71 3069
05abb126 3070static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3071{
05abb126
AD		 3072 struct ixgbe_hw *hw = &adapter->hw;
3073 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3074 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3075 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3076 u32 mrqc = 0, reta = 0;
3077 u32 rxcsum;
3078 int i, j;
671c0adb
AD		 3079 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3080
671c0adb
AD		 3081 /*
3082 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3083 * make full use of any rings they may have. We will use the
3084 * PSRTYPE register to control how many rings we use within the PF.
3085 */
3086 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3087 rss_i = 2;
0cefafad 3088
05abb126
AD		 3089 /* Fill out hash function seeds */
3090 for (i = 0; i < 10; i++)
3091 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3092
3093 /* Fill out redirection table */
3094 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3095 if (j == rss_i)
05abb126
AD		 3096 j = 0;
3097 /* reta = 4-byte sliding window of
3098 * 0x00..(indices-1)(indices-1)00..etc. */
3099 reta = (reta << 8) | (j * 0x11);
3100 if ((i & 3) == 3)
3101 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3102 }
0cefafad 3103
05abb126
AD		 3104 /* Disable indicating checksum in descriptor, enables RSS hash */
3105 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3106 rxcsum |= IXGBE_RXCSUM_PCSD;
3107 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3108
671c0adb 3109 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3110 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3111 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3112 } else {
671c0adb
AD		 3113 u8 tcs = netdev_get_num_tc(adapter->netdev);
3114
3115 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3116 if (tcs > 4)
3117 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3118 else if (tcs > 1)
3119 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3120 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3121 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3122 else
671c0adb
AD		 3123 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3124 } else {
3125 if (tcs > 4)
8b1c0b24 3126 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3127 else if (tcs > 1)
3128 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3129 else
3130 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3131 }
0cefafad
JB		 3132 }
3133
05abb126 3134 /* Perform hash on these packet types */
671c0adb
AD		 3135 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3136 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3137 IXGBE_MRQC_RSS_FIELD_IPV6 |
3138 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3139
ef6afc0c
AD		 3140 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3141 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3142 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3143 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3144
05abb126 3145 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3146}
3147
bb5a9ad2
NS		 3148/**
3149 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3150 * @adapter: address of board private structure
3151 * @index: index of ring to set
bb5a9ad2 3152 **/
082757af 3153static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3154 struct ixgbe_ring *ring)
bb5a9ad2 3155{
bb5a9ad2 3156 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3157 u32 rscctrl;
bf29ee6c 3158 u8 reg_idx = ring->reg_idx;
7367096a 3159
7d637bcc 3160 if (!ring_is_rsc_enabled(ring))
7367096a 3161 return;
bb5a9ad2 3162
7367096a 3163 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3164 rscctrl |= IXGBE_RSCCTL_RSCEN;
3165 /*
3166 * we must limit the number of descriptors so that the
3167 * total size of max desc * buf_len is not greater
642c680e 3168 * than 65536
bb5a9ad2 3169 */
f800326d 3170 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3171 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3172}
3173
9e10e045
AD		 3174#define IXGBE_MAX_RX_DESC_POLL 10
3175static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3176 struct ixgbe_ring *ring)
3177{
3178 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3179 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3180 u32 rxdctl;
bf29ee6c 3181 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3182
3183 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3184 if (hw->mac.type == ixgbe_mac_82598EB &&
3185 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3186 return;
3187
3188 do {
032b4325 3189 usleep_range(1000, 2000);
9e10e045
AD		 3190 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3191 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3192
3193 if (!wait_loop) {
3194 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3195 "the polling period\n", reg_idx);
3196 }
3197}
3198
2d39d576
YZ		 3199void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3200 struct ixgbe_ring *ring)
3201{
3202 struct ixgbe_hw *hw = &adapter->hw;
3203 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3204 u32 rxdctl;
3205 u8 reg_idx = ring->reg_idx;
3206
3207 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3208 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3209
3210 /* write value back with RXDCTL.ENABLE bit cleared */
3211 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3212
3213 if (hw->mac.type == ixgbe_mac_82598EB &&
3214 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3215 return;
3216
3217 /* the hardware may take up to 100us to really disable the rx queue */
3218 do {
3219 udelay(10);
3220 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3221 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3222
3223 if (!wait_loop) {
3224 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3225 "the polling period\n", reg_idx);
3226 }
3227}
3228
84418e3b
AD		 3229void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3230 struct ixgbe_ring *ring)
acd37177
AD		 3231{
3232 struct ixgbe_hw *hw = &adapter->hw;
3233 u64 rdba = ring->dma;
9e10e045 3234 u32 rxdctl;
bf29ee6c 3235 u8 reg_idx = ring->reg_idx;
acd37177 3236
9e10e045
AD		 3237 /* disable queue to avoid issues while updating state */
3238 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3239 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3240
acd37177
AD		 3241 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3242 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3243 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3244 ring->count * sizeof(union ixgbe_adv_rx_desc));
3245 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3246 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3247 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3248
3249 ixgbe_configure_srrctl(adapter, ring);
3250 ixgbe_configure_rscctl(adapter, ring);
3251
3252 if (hw->mac.type == ixgbe_mac_82598EB) {
3253 /*
3254 * enable cache line friendly hardware writes:
3255 * PTHRESH=32 descriptors (half the internal cache),
3256 * this also removes ugly rx_no_buffer_count increment
3257 * HTHRESH=4 descriptors (to minimize latency on fetch)
3258 * WTHRESH=8 burst writeback up to two cache lines
3259 */
3260 rxdctl &= ~0x3FFFFF;
3261 rxdctl |= 0x080420;
3262 }
3263
3264 /* enable receive descriptor ring */
3265 rxdctl |= IXGBE_RXDCTL_ENABLE;
3266 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3267
3268 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3269 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3270}
3271
48654521
AD		 3272static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3273{
3274 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3275 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3276 int p;
3277
3278 /* PSRTYPE must be initialized in non 82598 adapters */
3279 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3280 IXGBE_PSRTYPE_UDPHDR |
3281 IXGBE_PSRTYPE_IPV4HDR |
48654521 3282 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3283 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3284
3285 if (hw->mac.type == ixgbe_mac_82598EB)
3286 return;
3287
fbe7ca7f
AD		 3288 if (rss_i > 3)
3289 psrtype |= 2 << 29;
3290 else if (rss_i > 1)
3291 psrtype |= 1 << 29;
48654521
AD		 3292
3293 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3294 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3295 psrtype);
3296}
3297
f5b4a52e
AD		 3298static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3299{
3300 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3301 u32 reg_offset, vf_shift;
435b19f6 3302 u32 gcr_ext, vmdctl;
de4c7f65 3303 int i;
f5b4a52e
AD		 3304
3305 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3306 return;
3307
3308 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3309 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3310 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3311 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3312 vmdctl |= IXGBE_VT_CTL_REPLEN;
3313 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3314
1d9c0bfd
AD		 3315 vf_shift = VMDQ_P(0) % 32;
3316 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3317
3318 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3319 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3320 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3321 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3322 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3323 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3324 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3325
3326 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3327 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3328
3329 /*
3330 * Set up VF register offsets for selected VT Mode,
3331 * i.e. 32 or 64 VFs for SR-IOV
3332 */
73079ea0
AD		 3333 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3334 case IXGBE_82599_VMDQ_8Q_MASK:
3335 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3336 break;
3337 case IXGBE_82599_VMDQ_4Q_MASK:
3338 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3339 break;
3340 default:
3341 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3342 break;
3343 }
3344
f5b4a52e
AD		 3345 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3346
435b19f6 3347
a985b6c3 3348 /* Enable MAC Anti-Spoofing */
435b19f6 3349 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3350 adapter->num_vfs);
de4c7f65
GR		 3351 /* For VFs that have spoof checking turned off */
3352 for (i = 0; i < adapter->num_vfs; i++) {
3353 if (!adapter->vfinfo[i].spoofchk_enabled)
3354 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3355 }
f5b4a52e
AD		 3356}
3357
477de6ed 3358static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3359{
9a799d71
AK		 3360 struct ixgbe_hw *hw = &adapter->hw;
3361 struct net_device *netdev = adapter->netdev;
3362 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3363 struct ixgbe_ring *rx_ring;
3364 int i;
3365 u32 mhadd, hlreg0;
48654521 3366
63f39bd1 3367#ifdef IXGBE_FCOE
477de6ed
AD		 3368 /* adjust max frame to be able to do baby jumbo for FCoE */
3369 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3370 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3371 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3372
477de6ed 3373#endif /* IXGBE_FCOE */
872844dd
AD		 3374
3375 /* adjust max frame to be at least the size of a standard frame */
3376 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3377 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3378
477de6ed
AD		 3379 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3380 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3381 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3382 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3383
3384 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3385 }
3386
3387 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3388 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3389 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3390 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3391
0cefafad
JB		 3392 /*
3393 * Setup the HW Rx Head and Tail Descriptor Pointers and
3394 * the Base and Length of the Rx Descriptor Ring
3395 */
9a799d71 3396 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3397 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3398 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3399 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3400 else
7d637bcc 3401 clear_ring_rsc_enabled(rx_ring);
477de6ed 3402 }
477de6ed
AD		 3403}
3404
7367096a
AD		 3405static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3406{
3407 struct ixgbe_hw *hw = &adapter->hw;
3408 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3409
3410 switch (hw->mac.type) {
3411 case ixgbe_mac_82598EB:
3412 /*
3413 * For VMDq support of different descriptor types or
3414 * buffer sizes through the use of multiple SRRCTL
3415 * registers, RDRXCTL.MVMEN must be set to 1
3416 *
3417 * also, the manual doesn't mention it clearly but DCA hints
3418 * will only use queue 0's tags unless this bit is set. Side
3419 * effects of setting this bit are only that SRRCTL must be
3420 * fully programmed [0..15]
3421 */
3422 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3423 break;
3424 case ixgbe_mac_82599EB:
b93a2226 3425 case ixgbe_mac_X540:
7367096a
AD		 3426 /* Disable RSC for ACK packets */
3427 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3428 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3429 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3430 /* hardware requires some bits to be set by default */
3431 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3432 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3433 break;
3434 default:
3435 /* We should do nothing since we don't know this hardware */
3436 return;
3437 }
3438
3439 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3440}
3441
477de6ed
AD		 3442/**
3443 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3444 * @adapter: board private structure
3445 *
3446 * Configure the Rx unit of the MAC after a reset.
3447 **/
3448static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3449{
3450 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3451 int i;
3452 u32 rxctrl;
477de6ed
AD		 3453
3454 /* disable receives while setting up the descriptors */
3455 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3456 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3457
3458 ixgbe_setup_psrtype(adapter);
7367096a 3459 ixgbe_setup_rdrxctl(adapter);
477de6ed 3460
9e10e045 3461 /* Program registers for the distribution of queues */
f5b4a52e 3462 ixgbe_setup_mrqc(adapter);
f5b4a52e 3463
477de6ed
AD		 3464 /* set_rx_buffer_len must be called before ring initialization */
3465 ixgbe_set_rx_buffer_len(adapter);
3466
3467 /*
3468 * Setup the HW Rx Head and Tail Descriptor Pointers and
3469 * the Base and Length of the Rx Descriptor Ring
3470 */
9e10e045
AD		 3471 for (i = 0; i < adapter->num_rx_queues; i++)
3472 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3473
9e10e045
AD		 3474 /* disable drop enable for 82598 parts */
3475 if (hw->mac.type == ixgbe_mac_82598EB)
3476 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3477
3478 /* enable all receives */
3479 rxctrl |= IXGBE_RXCTRL_RXEN;
3480 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3481}
3482
80d5c368
PM		 3483static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3484 __be16 proto, u16 vid)
068c89b0
DS		 3485{
3486 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3487 struct ixgbe_hw *hw = &adapter->hw;
3488
3489 /* add VID to filter table */
1d9c0bfd 3490 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3491 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3492
3493 return 0;
068c89b0
DS		 3494}
3495
80d5c368
PM		 3496static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3497 __be16 proto, u16 vid)
068c89b0
DS		 3498{
3499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3500 struct ixgbe_hw *hw = &adapter->hw;
3501
068c89b0 3502 /* remove VID from filter table */
1d9c0bfd 3503 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3504 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3505
3506 return 0;
068c89b0
DS		 3507}
3508
5f6c0181
JB		 3509/**
3510 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3511 * @adapter: driver data
3512 */
3513static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3514{
3515 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3516 u32 vlnctrl;
3517
3518 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3519 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3520 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3521}
3522
3523/**
3524 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3525 * @adapter: driver data
3526 */
3527static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3528{
3529 struct ixgbe_hw *hw = &adapter->hw;
3530 u32 vlnctrl;
3531
3532 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3533 vlnctrl |= IXGBE_VLNCTRL_VFE;
3534 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3535 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3536}
3537
3538/**
3539 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3540 * @adapter: driver data
3541 */
3542static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3543{
3544 struct ixgbe_hw *hw = &adapter->hw;
3545 u32 vlnctrl;
5f6c0181
JB		 3546 int i, j;
3547
3548 switch (hw->mac.type) {
3549 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3551 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3552 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3553 break;
3554 case ixgbe_mac_82599EB:
b93a2226 3555 case ixgbe_mac_X540:
5f6c0181
JB		 3556 for (i = 0; i < adapter->num_rx_queues; i++) {
3557 j = adapter->rx_ring[i]->reg_idx;
3558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3559 vlnctrl &= ~IXGBE_RXDCTL_VME;
3560 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3561 }
3562 break;
3563 default:
3564 break;
3565 }
3566}
3567
3568/**
f62bbb5e 3569 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3570 * @adapter: driver data
3571 */
f62bbb5e 3572static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3573{
3574 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3575 u32 vlnctrl;
5f6c0181
JB		 3576 int i, j;
3577
3578 switch (hw->mac.type) {
3579 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3580 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3581 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3582 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3583 break;
3584 case ixgbe_mac_82599EB:
b93a2226 3585 case ixgbe_mac_X540:
5f6c0181
JB		 3586 for (i = 0; i < adapter->num_rx_queues; i++) {
3587 j = adapter->rx_ring[i]->reg_idx;
3588 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3589 vlnctrl |= IXGBE_RXDCTL_VME;
3590 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3591 }
3592 break;
3593 default:
3594 break;
3595 }
3596}
3597
9a799d71
AK		 3598static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3599{
f62bbb5e 3600 u16 vid;
9a799d71 3601
80d5c368 3602 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3603
3604 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3605 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3606}
3607
2850062a
AD		 3608/**
3609 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3610 * @netdev: network interface device structure
3611 *
3612 * Writes unicast address list to the RAR table.
3613 * Returns: -ENOMEM on failure/insufficient address space
3614 * 0 on no addresses written
3615 * X on writing X addresses to the RAR table
3616 **/
3617static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3618{
3619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3620 struct ixgbe_hw *hw = &adapter->hw;
95447461 3621 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3622 int count = 0;
3623
95447461
JF		 3624 /* In SR-IOV mode significantly less RAR entries are available */
3625 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3626 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3627
2850062a
AD		 3628 /* return ENOMEM indicating insufficient memory for addresses */
3629 if (netdev_uc_count(netdev) > rar_entries)
3630 return -ENOMEM;
3631
95447461 3632 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3633 struct netdev_hw_addr *ha;
3634 /* return error if we do not support writing to RAR table */
3635 if (!hw->mac.ops.set_rar)
3636 return -ENOMEM;
3637
3638 netdev_for_each_uc_addr(ha, netdev) {
3639 if (!rar_entries)
3640 break;
3641 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3642 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3643 count++;
3644 }
3645 }
3646 /* write the addresses in reverse order to avoid write combining */
3647 for (; rar_entries > 0 ; rar_entries--)
3648 hw->mac.ops.clear_rar(hw, rar_entries);
3649
3650 return count;
3651}
3652
9a799d71 3653/**
2c5645cf 3654 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3655 * @netdev: network interface device structure
3656 *
2c5645cf
CL		 3657 * The set_rx_method entry point is called whenever the unicast/multicast
3658 * address list or the network interface flags are updated. This routine is
3659 * responsible for configuring the hardware for proper unicast, multicast and
3660 * promiscuous mode.
9a799d71 3661 **/
7f870475 3662void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3663{
3664 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3665 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3666 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3667 int count;
9a799d71
AK		 3668
3669 /* Check for Promiscuous and All Multicast modes */
3670
3671 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3672
f5dc442b 3673 /* set all bits that we expect to always be set */
3f2d1c0f 3674 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3675 fctrl |= IXGBE_FCTRL_BAM;
3676 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3677 fctrl |= IXGBE_FCTRL_PMCF;
3678
2850062a
AD		 3679 /* clear the bits we are changing the status of */
3680 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3681
9a799d71 3682 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3683 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3684 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3685 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3686 /* don't hardware filter vlans in promisc mode */
3687 ixgbe_vlan_filter_disable(adapter);
9a799d71 3688 } else {
746b9f02
PM		 3689 if (netdev->flags & IFF_ALLMULTI) {
3690 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3691 vmolr |= IXGBE_VMOLR_MPE;
3692 } else {
3693 /*
3694 * Write addresses to the MTA, if the attempt fails
25985edc 3695 * then we should just turn on promiscuous mode so
2850062a
AD		 3696 * that we can at least receive multicast traffic
3697 */
3698 hw->mac.ops.update_mc_addr_list(hw, netdev);
3699 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3700 }
5f6c0181 3701 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3702 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3703 }
3704
3705 /*
3706 * Write addresses to available RAR registers, if there is not
3707 * sufficient space to store all the addresses then enable
3708 * unicast promiscuous mode
3709 */
3710 count = ixgbe_write_uc_addr_list(netdev);
3711 if (count < 0) {
3712 fctrl |= IXGBE_FCTRL_UPE;
3713 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3714 }
3715
1d9c0bfd 3716 if (adapter->num_vfs)
1cdd1ec8 3717 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3718
3719 if (hw->mac.type != ixgbe_mac_82598EB) {
3720 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3721 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3722 IXGBE_VMOLR_ROPE);
1d9c0bfd 3723 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3724 }
3725
3f2d1c0f
BG		 3726 /* This is useful for sniffing bad packets. */
3727 if (adapter->netdev->features & NETIF_F_RXALL) {
3728 /* UPE and MPE will be handled by normal PROMISC logic
3729 * in e1000e_set_rx_mode */
3730 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3731 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3732 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3733
3734 fctrl &= ~(IXGBE_FCTRL_DPF);
3735 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3736 }
3737
2850062a 3738 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3739
f646968f 3740 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3741 ixgbe_vlan_strip_enable(adapter);
3742 else
3743 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3744}
3745
021230d4
AV		 3746static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3747{
3748 int q_idx;
021230d4 3749
49c7ffbe
AD		 3750 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3751 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3752}
3753
3754static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3755{
3756 int q_idx;
021230d4 3757
49c7ffbe
AD		 3758 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3759 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3760}
3761
7a6b6f51 3762#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3763/**
2f90b865
AD		 3764 * ixgbe_configure_dcb - Configure DCB hardware
3765 * @adapter: ixgbe adapter struct
3766 *
3767 * This is called by the driver on open to configure the DCB hardware.
3768 * This is also called by the gennetlink interface when reconfiguring
3769 * the DCB state.
3770 */
3771static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3772{
3773 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3774 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3775
67ebd791
AD		 3776 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3777 if (hw->mac.type == ixgbe_mac_82598EB)
3778 netif_set_gso_max_size(adapter->netdev, 65536);
3779 return;
3780 }
3781
3782 if (hw->mac.type == ixgbe_mac_82598EB)
3783 netif_set_gso_max_size(adapter->netdev, 32768);
3784
971060b1 3785#ifdef IXGBE_FCOE
b120818e
JF		 3786 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3787 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3788#endif
b120818e
JF		 3789
3790 /* reconfigure the hardware */
3791 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3792 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3793 DCB_TX_CONFIG);
3794 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3795 DCB_RX_CONFIG);
3796 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3797 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3798 ixgbe_dcb_hw_ets(&adapter->hw,
3799 adapter->ixgbe_ieee_ets,
3800 max_frame);
3801 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3802 adapter->ixgbe_ieee_pfc->pfc_en,
3803 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3804 }
8187cd48
JF		 3805
3806 /* Enable RSS Hash per TC */
3807 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3808 u32 msb = 0;
3809 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3810
d411a936
AD		 3811 while (rss_i) {
3812 msb++;
3813 rss_i >>= 1;
3814 }
8187cd48 3815
4ae63730
AD		 3816 /* write msb to all 8 TCs in one write */
3817 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3818 }
2f90b865 3819}
9da712d2
JF		 3820#endif
3821
3822/* Additional bittime to account for IXGBE framing */
3823#define IXGBE_ETH_FRAMING 20
3824
49ce9c2c 3825/**
9da712d2
JF		 3826 * ixgbe_hpbthresh - calculate high water mark for flow control
3827 *
3828 * @adapter: board private structure to calculate for
49ce9c2c 3829 * @pb: packet buffer to calculate
9da712d2
JF		 3830 */
3831static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3832{
3833 struct ixgbe_hw *hw = &adapter->hw;
3834 struct net_device *dev = adapter->netdev;
3835 int link, tc, kb, marker;
3836 u32 dv_id, rx_pba;
3837
3838 /* Calculate max LAN frame size */
3839 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3840
3841#ifdef IXGBE_FCOE
3842 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3843 if ((dev->features & NETIF_F_FCOE_MTU) &&
3844 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3845 (pb == ixgbe_fcoe_get_tc(adapter)))
3846 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3847
3848#endif
9da712d2
JF		 3849 /* Calculate delay value for device */
3850 switch (hw->mac.type) {
3851 case ixgbe_mac_X540:
3852 dv_id = IXGBE_DV_X540(link, tc);
3853 break;
3854 default:
3855 dv_id = IXGBE_DV(link, tc);
3856 break;
3857 }
3858
3859 /* Loopback switch introduces additional latency */
3860 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3861 dv_id += IXGBE_B2BT(tc);
3862
3863 /* Delay value is calculated in bit times convert to KB */
3864 kb = IXGBE_BT2KB(dv_id);
3865 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3866
3867 marker = rx_pba - kb;
3868
3869 /* It is possible that the packet buffer is not large enough
3870 * to provide required headroom. In this case throw an error
3871 * to user and a do the best we can.
3872 */
3873 if (marker < 0) {
3874 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3875 "headroom to support flow control."
3876 "Decrease MTU or number of traffic classes\n", pb);
3877 marker = tc + 1;
3878 }
3879
3880 return marker;
3881}
3882
49ce9c2c 3883/**
9da712d2
JF		 3884 * ixgbe_lpbthresh - calculate low water mark for for flow control
3885 *
3886 * @adapter: board private structure to calculate for
49ce9c2c 3887 * @pb: packet buffer to calculate
9da712d2
JF		 3888 */
3889static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3890{
3891 struct ixgbe_hw *hw = &adapter->hw;
3892 struct net_device *dev = adapter->netdev;
3893 int tc;
3894 u32 dv_id;
3895
3896 /* Calculate max LAN frame size */
3897 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3898
3899 /* Calculate delay value for device */
3900 switch (hw->mac.type) {
3901 case ixgbe_mac_X540:
3902 dv_id = IXGBE_LOW_DV_X540(tc);
3903 break;
3904 default:
3905 dv_id = IXGBE_LOW_DV(tc);
3906 break;
3907 }
3908
3909 /* Delay value is calculated in bit times convert to KB */
3910 return IXGBE_BT2KB(dv_id);
3911}
3912
3913/*
3914 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3915 */
3916static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3917{
3918 struct ixgbe_hw *hw = &adapter->hw;
3919 int num_tc = netdev_get_num_tc(adapter->netdev);
3920 int i;
3921
3922 if (!num_tc)
3923 num_tc = 1;
3924
3925 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3926
3927 for (i = 0; i < num_tc; i++) {
3928 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3929
3930 /* Low water marks must not be larger than high water marks */
3931 if (hw->fc.low_water > hw->fc.high_water[i])
3932 hw->fc.low_water = 0;
3933 }
3934}
3935
80605c65
JF		 3936static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3937{
80605c65 3938 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3939 int hdrm;
3940 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3941
3942 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3943 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3944 hdrm = 32 << adapter->fdir_pballoc;
3945 else
3946 hdrm = 0;
80605c65 3947
f7e1027f 3948 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3949 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3950}
3951
e4911d57
AD		 3952static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3953{
3954 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 3955 struct hlist_node *node2;
e4911d57
AD		 3956 struct ixgbe_fdir_filter *filter;
3957
3958 spin_lock(&adapter->fdir_perfect_lock);
3959
3960 if (!hlist_empty(&adapter->fdir_filter_list))
3961 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3962
b67bfe0d 3963 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 3964 &adapter->fdir_filter_list, fdir_node) {
3965 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3966 &filter->filter,
3967 filter->sw_idx,
3968 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3969 IXGBE_FDIR_DROP_QUEUE :
3970 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3971 }
3972
3973 spin_unlock(&adapter->fdir_perfect_lock);
3974}
3975
9a799d71
AK		 3976static void ixgbe_configure(struct ixgbe_adapter *adapter)
3977{
d2f5e7f3
AS		 3978 struct ixgbe_hw *hw = &adapter->hw;
3979
80605c65 3980 ixgbe_configure_pb(adapter);
7a6b6f51 3981#ifdef CONFIG_IXGBE_DCB
67ebd791 3982 ixgbe_configure_dcb(adapter);
2f90b865 3983#endif
b35d4d42
AD		 3984 /*
3985 * We must restore virtualization before VLANs or else
3986 * the VLVF registers will not be populated
3987 */
3988 ixgbe_configure_virtualization(adapter);
9a799d71 3989
4c1d7b4b 3990 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3991 ixgbe_restore_vlan(adapter);
3992
d2f5e7f3
AS		 3993 switch (hw->mac.type) {
3994 case ixgbe_mac_82599EB:
3995 case ixgbe_mac_X540:
3996 hw->mac.ops.disable_rx_buff(hw);
3997 break;
3998 default:
3999 break;
4000 }
4001
c4cf55e5 4002 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4003 ixgbe_init_fdir_signature_82599(&adapter->hw,
4004 adapter->fdir_pballoc);
e4911d57
AD		 4005 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4006 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4007 adapter->fdir_pballoc);
4008 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4009 }
4c1d7b4b 4010
d2f5e7f3
AS		 4011 switch (hw->mac.type) {
4012 case ixgbe_mac_82599EB:
4013 case ixgbe_mac_X540:
4014 hw->mac.ops.enable_rx_buff(hw);
4015 break;
4016 default:
4017 break;
4018 }
4019
7c8ae65a
AD		 4020#ifdef IXGBE_FCOE
4021 /* configure FCoE L2 filters, redirection table, and Rx control */
4022 ixgbe_configure_fcoe(adapter);
4023
4024#endif /* IXGBE_FCOE */
9a799d71
AK		 4025 ixgbe_configure_tx(adapter);
4026 ixgbe_configure_rx(adapter);
9a799d71
AK		 4027}
4028
e8e26350
PW		 4029static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4030{
4031 switch (hw->phy.type) {
4032 case ixgbe_phy_sfp_avago:
4033 case ixgbe_phy_sfp_ftl:
4034 case ixgbe_phy_sfp_intel:
4035 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4036 case ixgbe_phy_sfp_passive_tyco:
4037 case ixgbe_phy_sfp_passive_unknown:
4038 case ixgbe_phy_sfp_active_unknown:
4039 case ixgbe_phy_sfp_ftl_active:
e8e26350 4040 return true;
8917b447
AD		 4041 case ixgbe_phy_nl:
4042 if (hw->mac.type == ixgbe_mac_82598EB)
4043 return true;
e8e26350
PW		 4044 default:
4045 return false;
4046 }
4047}
4048
0ecc061d 4049/**
e8e26350
PW		 4050 * ixgbe_sfp_link_config - set up SFP+ link
4051 * @adapter: pointer to private adapter struct
4052 **/
4053static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4054{
7086400d 4055 /*
52f33af8 4056 * We are assuming the worst case scenario here, and that
7086400d
AD		 4057 * is that an SFP was inserted/removed after the reset
4058 * but before SFP detection was enabled. As such the best
4059 * solution is to just start searching as soon as we start
4060 */
4061 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4062 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4063
7086400d 4064 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4065}
4066
4067/**
4068 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4069 * @hw: pointer to private hardware struct
4070 *
4071 * Returns 0 on success, negative on failure
4072 **/
e8e26350 4073static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4074{
3d292265
JH		 4075 u32 speed;
4076 bool autoneg, link_up = false;
0ecc061d
PWJ		 4077 u32 ret = IXGBE_ERR_LINK_SETUP;
4078
4079 if (hw->mac.ops.check_link)
3d292265 4080 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4081
4082 if (ret)
4083 goto link_cfg_out;
4084
3d292265
JH		 4085 speed = hw->phy.autoneg_advertised;
4086 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4087 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4088 &autoneg);
0ecc061d
PWJ		 4089 if (ret)
4090 goto link_cfg_out;
4091
8620a103 4092 if (hw->mac.ops.setup_link)
fd0326f2 4093 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4094link_cfg_out:
4095 return ret;
4096}
4097
a34bcfff 4098static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4099{
9a799d71 4100 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4101 u32 gpie = 0;
9a799d71 4102
9b471446 4103 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4104 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4105 IXGBE_GPIE_OCD;
4106 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4107 /*
4108 * use EIAM to auto-mask when MSI-X interrupt is asserted
4109 * this saves a register write for every interrupt
4110 */
4111 switch (hw->mac.type) {
4112 case ixgbe_mac_82598EB:
4113 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4114 break;
9b471446 4115 case ixgbe_mac_82599EB:
b93a2226
DS		 4116 case ixgbe_mac_X540:
4117 default:
9b471446
JB		 4118 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4119 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4120 break;
4121 }
4122 } else {
021230d4
AV		 4123 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4124 * specifically only auto mask tx and rx interrupts */
4125 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4126 }
9a799d71 4127
a34bcfff
AD		 4128 /* XXX: to interrupt immediately for EICS writes, enable this */
4129 /* gpie |= IXGBE_GPIE_EIMEN; */
4130
4131 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4132 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4133
4134 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4135 case IXGBE_82599_VMDQ_8Q_MASK:
4136 gpie |= IXGBE_GPIE_VTMODE_16;
4137 break;
4138 case IXGBE_82599_VMDQ_4Q_MASK:
4139 gpie |= IXGBE_GPIE_VTMODE_32;
4140 break;
4141 default:
4142 gpie |= IXGBE_GPIE_VTMODE_64;
4143 break;
4144 }
119fc60a
MC		 4145 }
4146
5fdd31f9 4147 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4148 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4149 switch (adapter->hw.mac.type) {
4150 case ixgbe_mac_82599EB:
4151 gpie |= IXGBE_SDP0_GPIEN;
4152 break;
4153 case ixgbe_mac_X540:
4154 gpie |= IXGBE_EIMS_TS;
4155 break;
4156 default:
4157 break;
4158 }
4159 }
5fdd31f9 4160
a34bcfff
AD		 4161 /* Enable fan failure interrupt */
4162 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4163 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4164
2698b208 4165 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4166 gpie |= IXGBE_SDP1_GPIEN;
4167 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4168 }
a34bcfff
AD		 4169
4170 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4171}
4172
c7ccde0f 4173static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4174{
4175 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4176 int err;
a34bcfff
AD		 4177 u32 ctrl_ext;
4178
4179 ixgbe_get_hw_control(adapter);
4180 ixgbe_setup_gpie(adapter);
e8e26350 4181
9a799d71
AK		 4182 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4183 ixgbe_configure_msix(adapter);
4184 else
4185 ixgbe_configure_msi_and_legacy(adapter);
4186
ec74a471
ET		 4187 /* enable the optics for 82599 SFP+ fiber */
4188 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4189 hw->mac.ops.enable_tx_laser(hw);
4190
9a799d71 4191 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4192 ixgbe_napi_enable_all(adapter);
4193
73c4b7cd
AD		 4194 if (ixgbe_is_sfp(hw)) {
4195 ixgbe_sfp_link_config(adapter);
4196 } else {
4197 err = ixgbe_non_sfp_link_config(hw);
4198 if (err)
4199 e_err(probe, "link_config FAILED %d\n", err);
4200 }
4201
021230d4
AV		 4202 /* clear any pending interrupts, may auto mask */
4203 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4204 ixgbe_irq_enable(adapter, true, true);
9a799d71 4205
bf069c97
DS		 4206 /*
4207 * If this adapter has a fan, check to see if we had a failure
4208 * before we enabled the interrupt.
4209 */
4210 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4211 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4212 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4213 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4214 }
4215
1da100bb 4216 /* enable transmits */
477de6ed 4217 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4218
9a799d71
AK		 4219 /* bring the link up in the watchdog, this could race with our first
4220 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4221 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4222 adapter->link_check_timeout = jiffies;
7086400d 4223 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4224
4225 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4226 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4227 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4228 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4229}
4230
d4f80882
AV		 4231void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4232{
4233 WARN_ON(in_interrupt());
7086400d
AD		 4234 /* put off any impending NetWatchDogTimeout */
4235 adapter->netdev->trans_start = jiffies;
4236
d4f80882 4237 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4238 usleep_range(1000, 2000);
d4f80882 4239 ixgbe_down(adapter);
5809a1ae
GR		 4240 /*
4241 * If SR-IOV enabled then wait a bit before bringing the adapter
4242 * back up to give the VFs time to respond to the reset. The
4243 * two second wait is based upon the watchdog timer cycle in
4244 * the VF driver.
4245 */
4246 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4247 msleep(2000);
d4f80882
AV		 4248 ixgbe_up(adapter);
4249 clear_bit(__IXGBE_RESETTING, &adapter->state);
4250}
4251
c7ccde0f 4252void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4253{
4254 /* hardware has been reset, we need to reload some things */
4255 ixgbe_configure(adapter);
4256
c7ccde0f 4257 ixgbe_up_complete(adapter);
9a799d71
AK		 4258}
4259
4260void ixgbe_reset(struct ixgbe_adapter *adapter)
4261{
c44ade9e 4262 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4263 int err;
4264
7086400d
AD		 4265 /* lock SFP init bit to prevent race conditions with the watchdog */
4266 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4267 usleep_range(1000, 2000);
4268
4269 /* clear all SFP and link config related flags while holding SFP_INIT */
4270 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4271 IXGBE_FLAG2_SFP_NEEDS_RESET);
4272 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4273
8ca783ab 4274 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4275 switch (err) {
4276 case 0:
4277 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4278 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4279 break;
4280 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4281 e_dev_err("master disable timed out\n");
da4dd0f7 4282 break;
794caeb2
PWJ		 4283 case IXGBE_ERR_EEPROM_VERSION:
4284 /* We are running on a pre-production device, log a warning */
849c4542 4285 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4286 "Please be aware there may be issues associated with "
849c4542
ET		 4287 "your hardware. If you are experiencing problems "
4288 "please contact your Intel or hardware "
4289 "representative who provided you with this "
4290 "hardware.\n");
794caeb2 4291 break;
da4dd0f7 4292 default:
849c4542 4293 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4294 }
9a799d71 4295
7086400d
AD		 4296 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4297
9a799d71 4298 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4299 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4300
4301 /* update SAN MAC vmdq pool selection */
4302 if (hw->mac.san_mac_rar_index)
4303 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4304
1a71ab24
JK		 4305 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4306 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4307}
4308
9a799d71
AK		 4309/**
4310 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4311 * @rx_ring: ring to free buffers from
4312 **/
b6ec895e 4313static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4314{
b6ec895e 4315 struct device *dev = rx_ring->dev;
9a799d71 4316 unsigned long size;
b6ec895e 4317 u16 i;
9a799d71 4318
84418e3b
AD		 4319 /* ring already cleared, nothing to do */
4320 if (!rx_ring->rx_buffer_info)
4321 return;
9a799d71 4322
84418e3b 4323 /* Free all the Rx ring sk_buffs */
9a799d71 4324 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4325 struct ixgbe_rx_buffer *rx_buffer;
4326
4327 rx_buffer = &rx_ring->rx_buffer_info[i];
4328 if (rx_buffer->skb) {
4329 struct sk_buff *skb = rx_buffer->skb;
4330 if (IXGBE_CB(skb)->page_released) {
4331 dma_unmap_page(dev,
4332 IXGBE_CB(skb)->dma,
4333 ixgbe_rx_bufsz(rx_ring),
4334 DMA_FROM_DEVICE);
4335 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4336 }
4337 dev_kfree_skb(skb);
9a799d71 4338 }
f800326d
AD		 4339 rx_buffer->skb = NULL;
4340 if (rx_buffer->dma)
4341 dma_unmap_page(dev, rx_buffer->dma,
4342 ixgbe_rx_pg_size(rx_ring),
4343 DMA_FROM_DEVICE);
4344 rx_buffer->dma = 0;
4345 if (rx_buffer->page)
dd411ec4
AD		 4346 __free_pages(rx_buffer->page,
4347 ixgbe_rx_pg_order(rx_ring));
f800326d 4348 rx_buffer->page = NULL;
9a799d71
AK		 4349 }
4350
4351 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4352 memset(rx_ring->rx_buffer_info, 0, size);
4353
4354 /* Zero out the descriptor ring */
4355 memset(rx_ring->desc, 0, rx_ring->size);
4356
f800326d 4357 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4358 rx_ring->next_to_clean = 0;
4359 rx_ring->next_to_use = 0;
9a799d71
AK		 4360}
4361
4362/**
4363 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4364 * @tx_ring: ring to be cleaned
4365 **/
b6ec895e 4366static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4367{
4368 struct ixgbe_tx_buffer *tx_buffer_info;
4369 unsigned long size;
b6ec895e 4370 u16 i;
9a799d71 4371
84418e3b
AD		 4372 /* ring already cleared, nothing to do */
4373 if (!tx_ring->tx_buffer_info)
4374 return;
9a799d71 4375
84418e3b 4376 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4377 for (i = 0; i < tx_ring->count; i++) {
4378 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4379 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4380 }
4381
dad8a3b3
JF		 4382 netdev_tx_reset_queue(txring_txq(tx_ring));
4383
9a799d71
AK		 4384 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4385 memset(tx_ring->tx_buffer_info, 0, size);
4386
4387 /* Zero out the descriptor ring */
4388 memset(tx_ring->desc, 0, tx_ring->size);
4389
4390 tx_ring->next_to_use = 0;
4391 tx_ring->next_to_clean = 0;
9a799d71
AK		 4392}
4393
4394/**
021230d4 4395 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4396 * @adapter: board private structure
4397 **/
021230d4 4398static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4399{
4400 int i;
4401
021230d4 4402 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4403 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4404}
4405
4406/**
021230d4 4407 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4408 * @adapter: board private structure
4409 **/
021230d4 4410static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4411{
4412 int i;
4413
021230d4 4414 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4415 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4416}
4417
e4911d57
AD		 4418static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4419{
b67bfe0d 4420 struct hlist_node *node2;
e4911d57
AD		 4421 struct ixgbe_fdir_filter *filter;
4422
4423 spin_lock(&adapter->fdir_perfect_lock);
4424
b67bfe0d 4425 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4426 &adapter->fdir_filter_list, fdir_node) {
4427 hlist_del(&filter->fdir_node);
4428 kfree(filter);
4429 }
4430 adapter->fdir_filter_count = 0;
4431
4432 spin_unlock(&adapter->fdir_perfect_lock);
4433}
4434
9a799d71
AK		 4435void ixgbe_down(struct ixgbe_adapter *adapter)
4436{
4437 struct net_device *netdev = adapter->netdev;
7f821875 4438 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4439 u32 rxctrl;
bf29ee6c 4440 int i;
9a799d71
AK		 4441
4442 /* signal that we are down to the interrupt handler */
4443 set_bit(__IXGBE_DOWN, &adapter->state);
4444
4445 /* disable receives */
7f821875
JB		 4446 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4447 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4448
2d39d576
YZ		 4449 /* disable all enabled rx queues */
4450 for (i = 0; i < adapter->num_rx_queues; i++)
4451 /* this call also flushes the previous write */
4452 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4453
032b4325 4454 usleep_range(10000, 20000);
9a799d71 4455
7f821875
JB		 4456 netif_tx_stop_all_queues(netdev);
4457
7086400d 4458 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4459 netif_carrier_off(netdev);
4460 netif_tx_disable(netdev);
4461
4462 ixgbe_irq_disable(adapter);
4463
4464 ixgbe_napi_disable_all(adapter);
4465
d034acf1
AD		 4466 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4467 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4468 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4469
4470 del_timer_sync(&adapter->service_timer);
4471
34cecbbf 4472 if (adapter->num_vfs) {
8e34d1aa
AD		 4473 /* Clear EITR Select mapping */
4474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4475
4476 /* Mark all the VFs as inactive */
4477 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4478 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4479
34cecbbf
AD		 4480 /* ping all the active vfs to let them know we are going down */
4481 ixgbe_ping_all_vfs(adapter);
4482
4483 /* Disable all VFTE/VFRE TX/RX */
4484 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4485 }
4486
7f821875
JB		 4487 /* disable transmits in the hardware now that interrupts are off */
4488 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4489 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4490 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4491 }
34cecbbf
AD		 4492
4493 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4494 switch (hw->mac.type) {
4495 case ixgbe_mac_82599EB:
b93a2226 4496 case ixgbe_mac_X540:
88512539 4497 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4498 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4499 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4500 break;
4501 default:
4502 break;
4503 }
7f821875 4504
6f4a0e45
PL		 4505 if (!pci_channel_offline(adapter->pdev))
4506 ixgbe_reset(adapter);
c6ecf39a 4507
ec74a471
ET		 4508 /* power down the optics for 82599 SFP+ fiber */
4509 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4510 hw->mac.ops.disable_tx_laser(hw);
4511
9a799d71
AK		 4512 ixgbe_clean_all_tx_rings(adapter);
4513 ixgbe_clean_all_rx_rings(adapter);
4514
5dd2d332 4515#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4516 /* since we reset the hardware DCA settings were cleared */
e35ec126 4517 ixgbe_setup_dca(adapter);
96b0e0f6 4518#endif
9a799d71
AK		 4519}
4520
9a799d71
AK		 4521/**
4522 * ixgbe_tx_timeout - Respond to a Tx Hang
4523 * @netdev: network interface device structure
4524 **/
4525static void ixgbe_tx_timeout(struct net_device *netdev)
4526{
4527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4528
4529 /* Do the reset outside of interrupt context */
c83c6cbd 4530 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4531}
4532
9a799d71
AK		 4533/**
4534 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4535 * @adapter: board private structure to initialize
4536 *
4537 * ixgbe_sw_init initializes the Adapter private data structure.
4538 * Fields are initialized based on PCI device information and
4539 * OS network device settings (MTU size).
4540 **/
9f9a12f8 4541static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4542{
4543 struct ixgbe_hw *hw = &adapter->hw;
4544 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4545 unsigned int rss, fdir;
cb6d0f5e 4546 u32 fwsm;
7a6b6f51 4547#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4548 int j;
4549 struct tc_configuration *tc;
4550#endif
021230d4 4551
c44ade9e
JB		 4552 /* PCI config space info */
4553
4554 hw->vendor_id = pdev->vendor;
4555 hw->device_id = pdev->device;
4556 hw->revision_id = pdev->revision;
4557 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4558 hw->subsystem_device_id = pdev->subsystem_device;
4559
8fc3bb6d 4560 /* Set common capability flags and settings */
3ed69d7e 4561 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4562 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 4563 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4564 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 4565 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4566 adapter->atr_sample_rate = 20;
d3cb9869
AD		 4567 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4568 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 4569 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4570#ifdef CONFIG_IXGBE_DCA
4571 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4572#endif
4573#ifdef IXGBE_FCOE
4574 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4575 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4576#ifdef CONFIG_IXGBE_DCB
4577 /* Default traffic class to use for FCoE */
4578 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4579#endif /* CONFIG_IXGBE_DCB */
4580#endif /* IXGBE_FCOE */
4581
4582 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 4583 switch (hw->mac.type) {
4584 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 4585 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4586 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4587
bf069c97
DS		 4588 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4589 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 4590
49c7ffbe 4591 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 4592 adapter->ring_feature[RING_F_FDIR].limit = 0;
4593 adapter->atr_sample_rate = 0;
4594 adapter->fdir_pballoc = 0;
4595#ifdef IXGBE_FCOE
4596 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4597 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4598#ifdef CONFIG_IXGBE_DCB
4599 adapter->fcoe.up = 0;
4600#endif /* IXGBE_DCB */
4601#endif /* IXGBE_FCOE */
4602 break;
4603 case ixgbe_mac_82599EB:
4604 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4605 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 4606 break;
b93a2226 4607 case ixgbe_mac_X540:
cb6d0f5e
JK		 4608 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4609 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4610 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 4611 break;
4612 default:
4613 break;
f8212f97 4614 }
2f90b865 4615
7c8ae65a
AD		 4616#ifdef IXGBE_FCOE
4617 /* FCoE support exists, always init the FCoE lock */
4618 spin_lock_init(&adapter->fcoe.lock);
4619
4620#endif
1fc5f038
AD		 4621 /* n-tuple support exists, always init our spinlock */
4622 spin_lock_init(&adapter->fdir_perfect_lock);
4623
7a6b6f51 4624#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4625 switch (hw->mac.type) {
4626 case ixgbe_mac_X540:
4627 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4628 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4629 break;
4630 default:
4631 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4632 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4633 break;
4634 }
4635
2f90b865
AD		 4636 /* Configure DCB traffic classes */
4637 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4638 tc = &adapter->dcb_cfg.tc_config[j];
4639 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4640 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4641 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4642 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4643 tc->dcb_pfc = pfc_disabled;
4644 }
4de2a022
JF		 4645
4646 /* Initialize default user to priority mapping, UPx->TC0 */
4647 tc = &adapter->dcb_cfg.tc_config[0];
4648 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4649 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4650
2f90b865
AD		 4651 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4652 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4653 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4654 adapter->dcb_set_bitmap = 0x00;
3032309b 4655 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4656 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4657 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4658
4659#endif
9a799d71
AK		 4660
4661 /* default flow control settings */
cd7664f6 4662 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4663 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4664 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4665 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4666 hw->fc.send_xon = true;
db2adc2d
JK		 4667 hw->fc.disable_fc_autoneg =
4668 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
9a799d71 4669
99d74487
AD		 4670#ifdef CONFIG_PCI_IOV
4671 /* assign number of SR-IOV VFs */
4672 if (hw->mac.type != ixgbe_mac_82598EB)
4673 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4674
4675#endif
30efa5a3 4676 /* enable itr by default in dynamic mode */
f7554a2b 4677 adapter->rx_itr_setting = 1;
f7554a2b 4678 adapter->tx_itr_setting = 1;
30efa5a3 4679
30efa5a3
JB		 4680 /* set default ring sizes */
4681 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4682 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4683
bd198058 4684 /* set default work limits */
59224555 4685 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4686
9a799d71 4687 /* initialize eeprom parameters */
c44ade9e 4688 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4689 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4690 return -EIO;
4691 }
4692
9a799d71
AK		 4693 set_bit(__IXGBE_DOWN, &adapter->state);
4694
4695 return 0;
4696}
4697
4698/**
4699 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4700 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4701 *
4702 * Return 0 on success, negative on failure
4703 **/
b6ec895e 4704int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4705{
b6ec895e 4706 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4707 int orig_node = dev_to_node(dev);
4708 int numa_node = -1;
9a799d71
AK		 4709 int size;
4710
3a581073 4711 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4712
4713 if (tx_ring->q_vector)
4714 numa_node = tx_ring->q_vector->numa_node;
4715
4716 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4717 if (!tx_ring->tx_buffer_info)
89bf67f1 4718 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4719 if (!tx_ring->tx_buffer_info)
4720 goto err;
9a799d71
AK		 4721
4722 /* round up to nearest 4K */
12207e49 4723 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4724 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4725
de88eeeb
AD		 4726 set_dev_node(dev, numa_node);
4727 tx_ring->desc = dma_alloc_coherent(dev,
4728 tx_ring->size,
4729 &tx_ring->dma,
4730 GFP_KERNEL);
4731 set_dev_node(dev, orig_node);
4732 if (!tx_ring->desc)
4733 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4734 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4735 if (!tx_ring->desc)
4736 goto err;
9a799d71 4737
3a581073
JB		 4738 tx_ring->next_to_use = 0;
4739 tx_ring->next_to_clean = 0;
9a799d71 4740 return 0;
e01c31a5
JB		 4741
4742err:
4743 vfree(tx_ring->tx_buffer_info);
4744 tx_ring->tx_buffer_info = NULL;
b6ec895e 4745 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4746 return -ENOMEM;
9a799d71
AK		 4747}
4748
69888674
AD		 4749/**
4750 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4751 * @adapter: board private structure
4752 *
4753 * If this function returns with an error, then it's possible one or
4754 * more of the rings is populated (while the rest are not). It is the
4755 * callers duty to clean those orphaned rings.
4756 *
4757 * Return 0 on success, negative on failure
4758 **/
4759static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4760{
4761 int i, err = 0;
4762
4763 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4764 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4765 if (!err)
4766 continue;
de3d5b94 4767
396e799c 4768 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4769 goto err_setup_tx;
69888674
AD		 4770 }
4771
de3d5b94
AD		 4772 return 0;
4773err_setup_tx:
4774 /* rewind the index freeing the rings as we go */
4775 while (i--)
4776 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4777 return err;
4778}
4779
9a799d71
AK		 4780/**
4781 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4782 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4783 *
4784 * Returns 0 on success, negative on failure
4785 **/
b6ec895e 4786int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4787{
b6ec895e 4788 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4789 int orig_node = dev_to_node(dev);
4790 int numa_node = -1;
021230d4 4791 int size;
9a799d71 4792
3a581073 4793 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4794
4795 if (rx_ring->q_vector)
4796 numa_node = rx_ring->q_vector->numa_node;
4797
4798 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4799 if (!rx_ring->rx_buffer_info)
89bf67f1 4800 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4801 if (!rx_ring->rx_buffer_info)
4802 goto err;
9a799d71 4803
9a799d71 4804 /* Round up to nearest 4K */
3a581073
JB		 4805 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4806 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4807
de88eeeb
AD		 4808 set_dev_node(dev, numa_node);
4809 rx_ring->desc = dma_alloc_coherent(dev,
4810 rx_ring->size,
4811 &rx_ring->dma,
4812 GFP_KERNEL);
4813 set_dev_node(dev, orig_node);
4814 if (!rx_ring->desc)
4815 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4816 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4817 if (!rx_ring->desc)
4818 goto err;
9a799d71 4819
3a581073
JB		 4820 rx_ring->next_to_clean = 0;
4821 rx_ring->next_to_use = 0;
9a799d71
AK		 4822
4823 return 0;
b6ec895e
AD		 4824err:
4825 vfree(rx_ring->rx_buffer_info);
4826 rx_ring->rx_buffer_info = NULL;
4827 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4828 return -ENOMEM;
9a799d71
AK		 4829}
4830
69888674
AD		 4831/**
4832 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4833 * @adapter: board private structure
4834 *
4835 * If this function returns with an error, then it's possible one or
4836 * more of the rings is populated (while the rest are not). It is the
4837 * callers duty to clean those orphaned rings.
4838 *
4839 * Return 0 on success, negative on failure
4840 **/
69888674
AD		 4841static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4842{
4843 int i, err = 0;
4844
4845 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4846 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4847 if (!err)
4848 continue;
de3d5b94 4849
396e799c 4850 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4851 goto err_setup_rx;
69888674
AD		 4852 }
4853
7c8ae65a
AD		 4854#ifdef IXGBE_FCOE
4855 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4856 if (!err)
4857#endif
4858 return 0;
de3d5b94
AD		 4859err_setup_rx:
4860 /* rewind the index freeing the rings as we go */
4861 while (i--)
4862 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4863 return err;
4864}
4865
9a799d71
AK		 4866/**
4867 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4868 * @tx_ring: Tx descriptor ring for a specific queue
4869 *
4870 * Free all transmit software resources
4871 **/
b6ec895e 4872void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4873{
b6ec895e 4874 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4875
4876 vfree(tx_ring->tx_buffer_info);
4877 tx_ring->tx_buffer_info = NULL;
4878
b6ec895e
AD		 4879 /* if not set, then don't free */
4880 if (!tx_ring->desc)
4881 return;
4882
4883 dma_free_coherent(tx_ring->dev, tx_ring->size,
4884 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4885
4886 tx_ring->desc = NULL;
4887}
4888
4889/**
4890 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4891 * @adapter: board private structure
4892 *
4893 * Free all transmit software resources
4894 **/
4895static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4896{
4897 int i;
4898
4899 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4900 if (adapter->tx_ring[i]->desc)
b6ec895e 4901 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4902}
4903
4904/**
b4617240 4905 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4906 * @rx_ring: ring to clean the resources from
4907 *
4908 * Free all receive software resources
4909 **/
b6ec895e 4910void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4911{
b6ec895e 4912 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4913
4914 vfree(rx_ring->rx_buffer_info);
4915 rx_ring->rx_buffer_info = NULL;
4916
b6ec895e
AD		 4917 /* if not set, then don't free */
4918 if (!rx_ring->desc)
4919 return;
4920
4921 dma_free_coherent(rx_ring->dev, rx_ring->size,
4922 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4923
4924 rx_ring->desc = NULL;
4925}
4926
4927/**
4928 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4929 * @adapter: board private structure
4930 *
4931 * Free all receive software resources
4932 **/
4933static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4934{
4935 int i;
4936
7c8ae65a
AD		 4937#ifdef IXGBE_FCOE
4938 ixgbe_free_fcoe_ddp_resources(adapter);
4939
4940#endif
9a799d71 4941 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4942 if (adapter->rx_ring[i]->desc)
b6ec895e 4943 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4944}
4945
9a799d71
AK		 4946/**
4947 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4948 * @netdev: network interface device structure
4949 * @new_mtu: new value for maximum frame size
4950 *
4951 * Returns 0 on success, negative on failure
4952 **/
4953static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4954{
4955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4956 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4957
42c783c5 4958 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4959 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4960 return -EINVAL;
4961
4962 /*
872844dd
AD		 4963 * For 82599EB we cannot allow legacy VFs to enable their receive
4964 * paths when MTU greater than 1500 is configured. So display a
4965 * warning that legacy VFs will be disabled.
655309e9
AD		 4966 */
4967 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4968 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 4969 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 4970 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 4971
396e799c 4972 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4973
021230d4 4974 /* must set new MTU before calling down or up */
9a799d71
AK		 4975 netdev->mtu = new_mtu;
4976
d4f80882
AV		 4977 if (netif_running(netdev))
4978 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4979
4980 return 0;
4981}
4982
4983/**
4984 * ixgbe_open - Called when a network interface is made active
4985 * @netdev: network interface device structure
4986 *
4987 * Returns 0 on success, negative value on failure
4988 *
4989 * The open entry point is called when a network interface is made
4990 * active by the system (IFF_UP). At this point all resources needed
4991 * for transmit and receive operations are allocated, the interrupt
4992 * handler is registered with the OS, the watchdog timer is started,
4993 * and the stack is notified that the interface is ready.
4994 **/
4995static int ixgbe_open(struct net_device *netdev)
4996{
4997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4998 int err;
4bebfaa5
AK		 4999
5000 /* disallow open during test */
5001 if (test_bit(__IXGBE_TESTING, &adapter->state))
5002 return -EBUSY;
9a799d71 5003
54386467
JB		 5004 netif_carrier_off(netdev);
5005
9a799d71
AK		 5006 /* allocate transmit descriptors */
5007 err = ixgbe_setup_all_tx_resources(adapter);
5008 if (err)
5009 goto err_setup_tx;
5010
9a799d71
AK		 5011 /* allocate receive descriptors */
5012 err = ixgbe_setup_all_rx_resources(adapter);
5013 if (err)
5014 goto err_setup_rx;
5015
5016 ixgbe_configure(adapter);
5017
021230d4 5018 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5019 if (err)
5020 goto err_req_irq;
5021
ac802f5d
AD		 5022 /* Notify the stack of the actual queue counts. */
5023 err = netif_set_real_num_tx_queues(netdev,
5024 adapter->num_rx_pools > 1 ? 1 :
5025 adapter->num_tx_queues);
5026 if (err)
5027 goto err_set_queues;
5028
5029
5030 err = netif_set_real_num_rx_queues(netdev,
5031 adapter->num_rx_pools > 1 ? 1 :
5032 adapter->num_rx_queues);
5033 if (err)
5034 goto err_set_queues;
5035
1a71ab24 5036 ixgbe_ptp_init(adapter);
1a71ab24 5037
c7ccde0f 5038 ixgbe_up_complete(adapter);
9a799d71
AK		 5039
5040 return 0;
5041
ac802f5d
AD		 5042err_set_queues:
5043 ixgbe_free_irq(adapter);
9a799d71 5044err_req_irq:
a20a1199 5045 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5046err_setup_rx:
a20a1199 5047 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5048err_setup_tx:
9a799d71
AK		 5049 ixgbe_reset(adapter);
5050
5051 return err;
5052}
5053
5054/**
5055 * ixgbe_close - Disables a network interface
5056 * @netdev: network interface device structure
5057 *
5058 * Returns 0, this is not allowed to fail
5059 *
5060 * The close entry point is called when an interface is de-activated
5061 * by the OS. The hardware is still under the drivers control, but
5062 * needs to be disabled. A global MAC reset is issued to stop the
5063 * hardware, and all transmit and receive resources are freed.
5064 **/
5065static int ixgbe_close(struct net_device *netdev)
5066{
5067 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5068
1a71ab24 5069 ixgbe_ptp_stop(adapter);
1a71ab24 5070
9a799d71
AK		 5071 ixgbe_down(adapter);
5072 ixgbe_free_irq(adapter);
5073
e4911d57
AD		 5074 ixgbe_fdir_filter_exit(adapter);
5075
9a799d71
AK		 5076 ixgbe_free_all_tx_resources(adapter);
5077 ixgbe_free_all_rx_resources(adapter);
5078
5eba3699 5079 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5080
5081 return 0;
5082}
5083
b3c8b4ba
AD		 5084#ifdef CONFIG_PM
5085static int ixgbe_resume(struct pci_dev *pdev)
5086{
c60fbb00
AD		 5087 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5088 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5089 u32 err;
5090
5091 pci_set_power_state(pdev, PCI_D0);
5092 pci_restore_state(pdev);
656ab817
DS		 5093 /*
5094 * pci_restore_state clears dev->state_saved so call
5095 * pci_save_state to restore it.
5096 */
5097 pci_save_state(pdev);
9ce77666 5098
5099 err = pci_enable_device_mem(pdev);
b3c8b4ba 5100 if (err) {
849c4542 5101 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5102 return err;
5103 }
5104 pci_set_master(pdev);
5105
dd4d8ca6 5106 pci_wake_from_d3(pdev, false);
b3c8b4ba 5107
b3c8b4ba
AD		 5108 ixgbe_reset(adapter);
5109
495dce12
WJP		 5110 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5111
ac802f5d
AD		 5112 rtnl_lock();
5113 err = ixgbe_init_interrupt_scheme(adapter);
5114 if (!err && netif_running(netdev))
c60fbb00 5115 err = ixgbe_open(netdev);
ac802f5d
AD		 5116
5117 rtnl_unlock();
5118
5119 if (err)
5120 return err;
b3c8b4ba
AD		 5121
5122 netif_device_attach(netdev);
5123
5124 return 0;
5125}
b3c8b4ba 5126#endif /* CONFIG_PM */
9d8d05ae
RW		 5127
5128static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5129{
c60fbb00
AD		 5130 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5131 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5132 struct ixgbe_hw *hw = &adapter->hw;
5133 u32 ctrl, fctrl;
5134 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5135#ifdef CONFIG_PM
5136 int retval = 0;
5137#endif
5138
5139 netif_device_detach(netdev);
5140
499ab5cc 5141 rtnl_lock();
b3c8b4ba
AD		 5142 if (netif_running(netdev)) {
5143 ixgbe_down(adapter);
5144 ixgbe_free_irq(adapter);
5145 ixgbe_free_all_tx_resources(adapter);
5146 ixgbe_free_all_rx_resources(adapter);
5147 }
499ab5cc 5148 rtnl_unlock();
b3c8b4ba 5149
5f5ae6fc
AD		 5150 ixgbe_clear_interrupt_scheme(adapter);
5151
b3c8b4ba
AD		 5152#ifdef CONFIG_PM
5153 retval = pci_save_state(pdev);
5154 if (retval)
5155 return retval;
4df10466 5156
b3c8b4ba 5157#endif
e8e26350
PW		 5158 if (wufc) {
5159 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5160
ec74a471
ET		 5161 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5162 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5163 hw->mac.ops.enable_tx_laser(hw);
5164
e8e26350
PW		 5165 /* turn on all-multi mode if wake on multicast is enabled */
5166 if (wufc & IXGBE_WUFC_MC) {
5167 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5168 fctrl |= IXGBE_FCTRL_MPE;
5169 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5170 }
5171
5172 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5173 ctrl |= IXGBE_CTRL_GIO_DIS;
5174 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5175
5176 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5177 } else {
5178 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5179 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5180 }
5181
bd508178
AD		 5182 switch (hw->mac.type) {
5183 case ixgbe_mac_82598EB:
dd4d8ca6 5184 pci_wake_from_d3(pdev, false);
bd508178
AD		 5185 break;
5186 case ixgbe_mac_82599EB:
b93a2226 5187 case ixgbe_mac_X540:
bd508178
AD		 5188 pci_wake_from_d3(pdev, !!wufc);
5189 break;
5190 default:
5191 break;
5192 }
b3c8b4ba 5193
9d8d05ae
RW		 5194 *enable_wake = !!wufc;
5195
b3c8b4ba
AD		 5196 ixgbe_release_hw_control(adapter);
5197
5198 pci_disable_device(pdev);
5199
9d8d05ae
RW		 5200 return 0;
5201}
5202
5203#ifdef CONFIG_PM
5204static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5205{
5206 int retval;
5207 bool wake;
5208
5209 retval = __ixgbe_shutdown(pdev, &wake);
5210 if (retval)
5211 return retval;
5212
5213 if (wake) {
5214 pci_prepare_to_sleep(pdev);
5215 } else {
5216 pci_wake_from_d3(pdev, false);
5217 pci_set_power_state(pdev, PCI_D3hot);
5218 }
b3c8b4ba
AD		 5219
5220 return 0;
5221}
9d8d05ae 5222#endif /* CONFIG_PM */
b3c8b4ba
AD		 5223
5224static void ixgbe_shutdown(struct pci_dev *pdev)
5225{
9d8d05ae
RW		 5226 bool wake;
5227
5228 __ixgbe_shutdown(pdev, &wake);
5229
5230 if (system_state == SYSTEM_POWER_OFF) {
5231 pci_wake_from_d3(pdev, wake);
5232 pci_set_power_state(pdev, PCI_D3hot);
5233 }
b3c8b4ba
AD		 5234}
5235
9a799d71
AK		 5236/**
5237 * ixgbe_update_stats - Update the board statistics counters.
5238 * @adapter: board private structure
5239 **/
5240void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5241{
2d86f139 5242 struct net_device *netdev = adapter->netdev;
9a799d71 5243 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5244 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5245 u64 total_mpc = 0;
5246 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5247 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5248 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5249 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5250
d08935c2
DS		 5251 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5252 test_bit(__IXGBE_RESETTING, &adapter->state))
5253 return;
5254
94b982b2 5255 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5256 u64 rsc_count = 0;
94b982b2 5257 u64 rsc_flush = 0;
94b982b2 5258 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5259 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5260 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5261 }
5262 adapter->rsc_total_count = rsc_count;
5263 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5264 }
5265
5b7da515
AD		 5266 for (i = 0; i < adapter->num_rx_queues; i++) {
5267 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5268 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5269 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5270 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5271 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5272 bytes += rx_ring->stats.bytes;
5273 packets += rx_ring->stats.packets;
5274 }
5275 adapter->non_eop_descs = non_eop_descs;
5276 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5277 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5278 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5279 netdev->stats.rx_bytes = bytes;
5280 netdev->stats.rx_packets = packets;
5281
5282 bytes = 0;
5283 packets = 0;
7ca3bc58 5284 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5285 for (i = 0; i < adapter->num_tx_queues; i++) {
5286 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5287 restart_queue += tx_ring->tx_stats.restart_queue;
5288 tx_busy += tx_ring->tx_stats.tx_busy;
5289 bytes += tx_ring->stats.bytes;
5290 packets += tx_ring->stats.packets;
5291 }
eb985f09 5292 adapter->restart_queue = restart_queue;
5b7da515
AD		 5293 adapter->tx_busy = tx_busy;
5294 netdev->stats.tx_bytes = bytes;
5295 netdev->stats.tx_packets = packets;
7ca3bc58 5296
7ca647bd 5297 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5298
5299 /* 8 register reads */
6f11eef7
AV		 5300 for (i = 0; i < 8; i++) {
5301 /* for packet buffers not used, the register should read 0 */
5302 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5303 missed_rx += mpc;
7ca647bd
JP		 5304 hwstats->mpc[i] += mpc;
5305 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5306 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5307 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5308 switch (hw->mac.type) {
5309 case ixgbe_mac_82598EB:
1a70db4b
ET		 5310 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5311 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5312 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5313 hwstats->pxonrxc[i] +=
5314 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5315 break;
5316 case ixgbe_mac_82599EB:
b93a2226 5317 case ixgbe_mac_X540:
bd508178
AD		 5318 hwstats->pxonrxc[i] +=
5319 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5320 break;
5321 default:
5322 break;
e8e26350 5323 }
6f11eef7 5324 }
1a70db4b
ET		 5325
5326 /*16 register reads */
5327 for (i = 0; i < 16; i++) {
5328 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5329 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5330 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5331 (hw->mac.type == ixgbe_mac_X540)) {
5332 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5333 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5334 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5335 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5336 }
5337 }
5338
7ca647bd 5339 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5340 /* work around hardware counting issue */
7ca647bd 5341 hwstats->gprc -= missed_rx;
6f11eef7 5342
c84d324c
JF		 5343 ixgbe_update_xoff_received(adapter);
5344
6f11eef7 5345 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5346 switch (hw->mac.type) {
5347 case ixgbe_mac_82598EB:
5348 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5349 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5350 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5351 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5352 break;
b93a2226 5353 case ixgbe_mac_X540:
58f6bcf9
ET		 5354 /* OS2BMC stats are X540 only*/
5355 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5356 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5357 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5358 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5359 case ixgbe_mac_82599EB:
a4d4f629
AD		 5360 for (i = 0; i < 16; i++)
5361 adapter->hw_rx_no_dma_resources +=
5362 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5363 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5364 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5365 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5366 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5367 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5368 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5369 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5370 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5371 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5372#ifdef IXGBE_FCOE
7ca647bd
JP		 5373 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5374 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5375 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5376 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5377 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5378 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5379 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5380 if (adapter->fcoe.ddp_pool) {
5381 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5382 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5383 unsigned int cpu;
5384 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5385 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5386 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5387 noddp += ddp_pool->noddp;
5388 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5389 }
5a1ee270
AD		 5390 hwstats->fcoe_noddp = noddp;
5391 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5392 }
6d45522c 5393#endif /* IXGBE_FCOE */
bd508178
AD		 5394 break;
5395 default:
5396 break;
e8e26350 5397 }
9a799d71 5398 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5399 hwstats->bprc += bprc;
5400 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5401 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5402 hwstats->mprc -= bprc;
5403 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5404 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5405 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5406 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5407 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5408 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5409 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5410 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5411 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5412 hwstats->lxontxc += lxon;
6f11eef7 5413 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5414 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5415 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5416 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5417 /*
5418 * 82598 errata - tx of flow control packets is included in tx counters
5419 */
5420 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5421 hwstats->gptc -= xon_off_tot;
5422 hwstats->mptc -= xon_off_tot;
5423 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5424 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5425 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5426 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5427 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5428 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5429 hwstats->ptc64 -= xon_off_tot;
5430 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5431 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5432 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5433 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5434 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5435 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5436
5437 /* Fill out the OS statistics structure */
7ca647bd 5438 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5439
5440 /* Rx Errors */
7ca647bd 5441 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5442 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5443 netdev->stats.rx_length_errors = hwstats->rlec;
5444 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5445 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5446}
5447
5448/**
d034acf1 5449 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5450 * @adapter: pointer to the device adapter structure
9a799d71 5451 **/
d034acf1 5452static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5453{
cf8280ee 5454 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5455 int i;
cf8280ee 5456
d034acf1
AD		 5457 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5458 return;
5459
5460 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5461
d034acf1 5462 /* if interface is down do nothing */
fe49f04a 5463 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5464 return;
5465
5466 /* do nothing if we are not using signature filters */
5467 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5468 return;
5469
5470 adapter->fdir_overflow++;
5471
93c52dd0
AD		 5472 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5473 for (i = 0; i < adapter->num_tx_queues; i++)
5474 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5475 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5476 /* re-enable flow director interrupts */
5477 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5478 } else {
5479 e_err(probe, "failed to finish FDIR re-initialization, "
5480 "ignored adding FDIR ATR filters\n");
5481 }
93c52dd0
AD		 5482}
5483
5484/**
5485 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5486 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5487 *
5488 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5489 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5490 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5491 * determine if a hang has occurred.
93c52dd0
AD		 5492 */
5493static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5494{
cf8280ee 5495 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5496 u64 eics = 0;
5497 int i;
cf8280ee 5498
93c52dd0
AD		 5499 /* If we're down or resetting, just bail */
5500 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5501 test_bit(__IXGBE_RESETTING, &adapter->state))
5502 return;
22d5a71b 5503
93c52dd0
AD		 5504 /* Force detection of hung controller */
5505 if (netif_carrier_ok(adapter->netdev)) {
5506 for (i = 0; i < adapter->num_tx_queues; i++)
5507 set_check_for_tx_hang(adapter->tx_ring[i]);
5508 }
22d5a71b 5509
fe49f04a
AD		 5510 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5511 /*
5512 * for legacy and MSI interrupts don't set any bits
5513 * that are enabled for EIAM, because this operation
5514 * would set *both* EIMS and EICS for any bit in EIAM
5515 */
5516 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5517 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5518 } else {
5519 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5520 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5521 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5522 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5523 eics |= ((u64)1 << i);
5524 }
cf8280ee 5525 }
9a799d71 5526
93c52dd0 5527 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5528 ixgbe_irq_rearm_queues(adapter, eics);
5529
cf8280ee
JB		 5530}
5531
e8e26350 5532/**
93c52dd0 5533 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5534 * @adapter: pointer to the device adapter structure
5535 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5536 **/
93c52dd0 5537static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5538{
e8e26350 5539 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5540 u32 link_speed = adapter->link_speed;
5541 bool link_up = adapter->link_up;
041441d0 5542 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5543
93c52dd0
AD		 5544 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5545 return;
5546
5547 if (hw->mac.ops.check_link) {
5548 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5549 } else {
93c52dd0
AD		 5550 /* always assume link is up, if no check link function */
5551 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5552 link_up = true;
c4cf55e5 5553 }
041441d0
AD		 5554
5555 if (adapter->ixgbe_ieee_pfc)
5556 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5557
3ebe8fde 5558 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5559 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5560 ixgbe_set_rx_drop_en(adapter);
5561 }
93c52dd0
AD		 5562
5563 if (link_up ||
5564 time_after(jiffies, (adapter->link_check_timeout +
5565 IXGBE_TRY_LINK_TIMEOUT))) {
5566 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5567 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5568 IXGBE_WRITE_FLUSH(hw);
5569 }
5570
5571 adapter->link_up = link_up;
5572 adapter->link_speed = link_speed;
e8e26350
PW		 5573}
5574
107d3018
AD		 5575static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5576{
5577#ifdef CONFIG_IXGBE_DCB
5578 struct net_device *netdev = adapter->netdev;
5579 struct dcb_app app = {
5580 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5581 .protocol = 0,
5582 };
5583 u8 up = 0;
5584
5585 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5586 up = dcb_ieee_getapp_mask(netdev, &app);
5587
5588 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5589#endif
5590}
5591
e8e26350 5592/**
93c52dd0
AD		 5593 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5594 * print link up message
49ce9c2c 5595 * @adapter: pointer to the device adapter structure
e8e26350 5596 **/
93c52dd0 5597static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5598{
93c52dd0 5599 struct net_device *netdev = adapter->netdev;
e8e26350 5600 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5601 u32 link_speed = adapter->link_speed;
5602 bool flow_rx, flow_tx;
e8e26350 5603
93c52dd0
AD		 5604 /* only continue if link was previously down */
5605 if (netif_carrier_ok(netdev))
a985b6c3 5606 return;
63d6e1d8 5607
93c52dd0 5608 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5609
93c52dd0
AD		 5610 switch (hw->mac.type) {
5611 case ixgbe_mac_82598EB: {
5612 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5613 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5614 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5615 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5616 }
5617 break;
5618 case ixgbe_mac_X540:
5619 case ixgbe_mac_82599EB: {
5620 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5621 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5622 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5623 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5624 }
5625 break;
5626 default:
5627 flow_tx = false;
5628 flow_rx = false;
5629 break;
e8e26350 5630 }
3a6a4eda 5631
6cb562d6
JK		 5632 adapter->last_rx_ptp_check = jiffies;
5633
1a71ab24
JK		 5634 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5635 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5636
93c52dd0
AD		 5637 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5638 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5639 "10 Gbps" :
5640 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5641 "1 Gbps" :
5642 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5643 "100 Mbps" :
5644 "unknown speed"))),
5645 ((flow_rx && flow_tx) ? "RX/TX" :
5646 (flow_rx ? "RX" :
5647 (flow_tx ? "TX" : "None"))));
e8e26350 5648
93c52dd0 5649 netif_carrier_on(netdev);
93c52dd0 5650 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5651
107d3018
AD		 5652 /* update the default user priority for VFs */
5653 ixgbe_update_default_up(adapter);
5654
befa2af7
AD		 5655 /* ping all the active vfs to let them know link has changed */
5656 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5657}
5658
c4cf55e5 5659/**
93c52dd0
AD		 5660 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5661 * print link down message
49ce9c2c 5662 * @adapter: pointer to the adapter structure
c4cf55e5 5663 **/
581330ba 5664static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5665{
cf8280ee 5666 struct net_device *netdev = adapter->netdev;
c4cf55e5 5667 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5668
93c52dd0
AD		 5669 adapter->link_up = false;
5670 adapter->link_speed = 0;
cf8280ee 5671
93c52dd0
AD		 5672 /* only continue if link was up previously */
5673 if (!netif_carrier_ok(netdev))
5674 return;
264857b8 5675
93c52dd0
AD		 5676 /* poll for SFP+ cable when link is down */
5677 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5678 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5679
1a71ab24
JK		 5680 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5681 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5682
93c52dd0
AD		 5683 e_info(drv, "NIC Link is Down\n");
5684 netif_carrier_off(netdev);
befa2af7
AD		 5685
5686 /* ping all the active vfs to let them know link has changed */
5687 ixgbe_ping_all_vfs(adapter);
93c52dd0 5688}
e8e26350 5689
93c52dd0
AD		 5690/**
5691 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5692 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5693 **/
5694static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5695{
c4cf55e5 5696 int i;
93c52dd0 5697 int some_tx_pending = 0;
c4cf55e5 5698
93c52dd0 5699 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5700 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5701 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5702 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5703 some_tx_pending = 1;
5704 break;
5705 }
5706 }
5707
5708 if (some_tx_pending) {
5709 /* We've lost link, so the controller stops DMA,
5710 * but we've got queued Tx work that's never going
5711 * to get done, so reset controller to flush Tx.
5712 * (Do the reset outside of interrupt context).
5713 */
12ff3f3b 5714 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 5715 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5716 }
c4cf55e5 5717 }
c4cf55e5
PWJ		 5718}
5719
a985b6c3
GR		 5720static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5721{
5722 u32 ssvpc;
5723
0584d999
GR		 5724 /* Do not perform spoof check for 82598 or if not in IOV mode */
5725 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5726 adapter->num_vfs == 0)
a985b6c3
GR		 5727 return;
5728
5729 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5730
5731 /*
5732 * ssvpc register is cleared on read, if zero then no
5733 * spoofed packets in the last interval.
5734 */
5735 if (!ssvpc)
5736 return;
5737
d6ea0754 5738 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5739}
5740
93c52dd0
AD		 5741/**
5742 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5743 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5744 **/
5745static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5746{
5747 /* if interface is down do nothing */
7edebf9a
ET		 5748 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5749 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5750 return;
5751
5752 ixgbe_watchdog_update_link(adapter);
5753
5754 if (adapter->link_up)
5755 ixgbe_watchdog_link_is_up(adapter);
5756 else
5757 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5758
a985b6c3 5759 ixgbe_spoof_check(adapter);
9a799d71 5760 ixgbe_update_stats(adapter);
93c52dd0
AD		 5761
5762 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5763}
10eec955 5764
cf8280ee 5765/**
7086400d 5766 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5767 * @adapter: the ixgbe adapter structure
cf8280ee 5768 **/
7086400d 5769static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5770{
cf8280ee 5771 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5772 s32 err;
cf8280ee 5773
7086400d
AD		 5774 /* not searching for SFP so there is nothing to do here */
5775 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5776 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5777 return;
10eec955 5778
71858acb
AG		 5779 /* concurent i2c reads are not supported */
5780 if (test_bit(__IXGBE_READ_I2C, &adapter->state))
5781 return;
5782
7086400d
AD		 5783 /* someone else is in init, wait until next service event */
5784 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5785 return;
cf8280ee 5786
7086400d
AD		 5787 err = hw->phy.ops.identify_sfp(hw);
5788 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5789 goto sfp_out;
264857b8 5790
7086400d
AD		 5791 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5792 /* If no cable is present, then we need to reset
5793 * the next time we find a good cable. */
5794 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5795 }
9a799d71 5796
7086400d
AD		 5797 /* exit on error */
5798 if (err)
5799 goto sfp_out;
e8e26350 5800
7086400d
AD		 5801 /* exit if reset not needed */
5802 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5803 goto sfp_out;
9a799d71 5804
7086400d 5805 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5806
7086400d
AD		 5807 /*
5808 * A module may be identified correctly, but the EEPROM may not have
5809 * support for that module. setup_sfp() will fail in that case, so
5810 * we should not allow that module to load.
5811 */
5812 if (hw->mac.type == ixgbe_mac_82598EB)
5813 err = hw->phy.ops.reset(hw);
5814 else
5815 err = hw->mac.ops.setup_sfp(hw);
5816
5817 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5818 goto sfp_out;
5819
5820 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5821 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5822
5823sfp_out:
5824 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5825
5826 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5827 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5828 e_dev_err("failed to initialize because an unsupported "
5829 "SFP+ module type was detected.\n");
5830 e_dev_err("Reload the driver after installing a "
5831 "supported module.\n");
5832 unregister_netdev(adapter->netdev);
bc59fcda 5833 }
7086400d 5834}
bc59fcda 5835
7086400d
AD		 5836/**
5837 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5838 * @adapter: the ixgbe adapter structure
7086400d
AD		 5839 **/
5840static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5841{
5842 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 5843 u32 speed;
5844 bool autoneg = false;
7086400d
AD		 5845
5846 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5847 return;
5848
5849 /* someone else is in init, wait until next service event */
5850 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5851 return;
5852
5853 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5854
3d292265
JH		 5855 speed = hw->phy.autoneg_advertised;
5856 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5857 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7086400d 5858 if (hw->mac.ops.setup_link)
fd0326f2 5859 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 5860
5861 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5862 adapter->link_check_timeout = jiffies;
5863 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5864}
5865
83c61fa9
GR		 5866#ifdef CONFIG_PCI_IOV
5867static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5868{
5869 int vf;
5870 struct ixgbe_hw *hw = &adapter->hw;
5871 struct net_device *netdev = adapter->netdev;
5872 u32 gpc;
5873 u32 ciaa, ciad;
5874
5875 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5876 if (gpc) /* If incrementing then no need for the check below */
5877 return;
5878 /*
5879 * Check to see if a bad DMA write target from an errant or
5880 * malicious VF has caused a PCIe error. If so then we can
5881 * issue a VFLR to the offending VF(s) and then resume without
5882 * requesting a full slot reset.
5883 */
5884
5885 for (vf = 0; vf < adapter->num_vfs; vf++) {
5886 ciaa = (vf << 16) | 0x80000000;
5887 /* 32 bit read so align, we really want status at offset 6 */
5888 ciaa |= PCI_COMMAND;
5889 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5890 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5891 ciaa &= 0x7FFFFFFF;
5892 /* disable debug mode asap after reading data */
5893 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5894 /* Get the upper 16 bits which will be the PCI status reg */
5895 ciad >>= 16;
5896 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5897 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5898 /* Issue VFLR */
5899 ciaa = (vf << 16) | 0x80000000;
5900 ciaa |= 0xA8;
5901 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5902 ciad = 0x00008000; /* VFLR */
5903 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5904 ciaa &= 0x7FFFFFFF;
5905 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5906 }
5907 }
5908}
5909
5910#endif
7086400d
AD		 5911/**
5912 * ixgbe_service_timer - Timer Call-back
5913 * @data: pointer to adapter cast into an unsigned long
5914 **/
5915static void ixgbe_service_timer(unsigned long data)
5916{
5917 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5918 unsigned long next_event_offset;
83c61fa9 5919 bool ready = true;
7086400d 5920
6bb78cfb
AD		 5921 /* poll faster when waiting for link */
5922 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5923 next_event_offset = HZ / 10;
5924 else
5925 next_event_offset = HZ * 2;
83c61fa9 5926
6bb78cfb 5927#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5928 /*
5929 * don't bother with SR-IOV VF DMA hang check if there are
5930 * no VFs or the link is down
5931 */
5932 if (!adapter->num_vfs ||
6bb78cfb 5933 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5934 goto normal_timer_service;
83c61fa9
GR		 5935
5936 /* If we have VFs allocated then we must check for DMA hangs */
5937 ixgbe_check_for_bad_vf(adapter);
5938 next_event_offset = HZ / 50;
5939 adapter->timer_event_accumulator++;
5940
6bb78cfb 5941 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5942 adapter->timer_event_accumulator = 0;
7086400d 5943 else
6bb78cfb 5944 ready = false;
7086400d 5945
6bb78cfb 5946normal_timer_service:
83c61fa9 5947#endif
7086400d
AD		 5948 /* Reset the timer */
5949 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5950
83c61fa9
GR		 5951 if (ready)
5952 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5953}
5954
c83c6cbd
AD		 5955static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5956{
5957 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5958 return;
5959
5960 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5961
5962 /* If we're already down or resetting, just bail */
5963 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5964 test_bit(__IXGBE_RESETTING, &adapter->state))
5965 return;
5966
5967 ixgbe_dump(adapter);
5968 netdev_err(adapter->netdev, "Reset adapter\n");
5969 adapter->tx_timeout_count++;
5970
5971 ixgbe_reinit_locked(adapter);
5972}
5973
7086400d
AD		 5974/**
5975 * ixgbe_service_task - manages and runs subtasks
5976 * @work: pointer to work_struct containing our data
5977 **/
5978static void ixgbe_service_task(struct work_struct *work)
5979{
5980 struct ixgbe_adapter *adapter = container_of(work,
5981 struct ixgbe_adapter,
5982 service_task);
c83c6cbd 5983 ixgbe_reset_subtask(adapter);
7086400d
AD		 5984 ixgbe_sfp_detection_subtask(adapter);
5985 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5986 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5987 ixgbe_watchdog_subtask(adapter);
d034acf1 5988 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5989 ixgbe_check_hang_subtask(adapter);
891dc082
JK		 5990
5991 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5992 ixgbe_ptp_overflow_check(adapter);
5993 ixgbe_ptp_rx_hang(adapter);
5994 }
7086400d
AD		 5995
5996 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5997}
5998
fd0db0ed
AD		 5999static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6000 struct ixgbe_tx_buffer *first,
244e27ad 6001 u8 *hdr_len)
897ab156 6002{
fd0db0ed 6003 struct sk_buff *skb = first->skb;
897ab156
AD		 6004 u32 vlan_macip_lens, type_tucmd;
6005 u32 mss_l4len_idx, l4len;
9a799d71 6006
8f4fbb9b
AD		 6007 if (skb->ip_summed != CHECKSUM_PARTIAL)
6008 return 0;
6009
897ab156
AD		 6010 if (!skb_is_gso(skb))
6011 return 0;
9a799d71 6012
897ab156 6013 if (skb_header_cloned(skb)) {
244e27ad 6014 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6015 if (err)
6016 return err;
9a799d71 6017 }
9a799d71 6018
897ab156
AD		 6019 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6020 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6021
244e27ad 6022 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6023 struct iphdr *iph = ip_hdr(skb);
6024 iph->tot_len = 0;
6025 iph->check = 0;
6026 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6027 iph->daddr, 0,
6028 IPPROTO_TCP,
6029 0);
6030 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6031 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6032 IXGBE_TX_FLAGS_CSUM |
6033 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6034 } else if (skb_is_gso_v6(skb)) {
6035 ipv6_hdr(skb)->payload_len = 0;
6036 tcp_hdr(skb)->check =
6037 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6038 &ipv6_hdr(skb)->daddr,
6039 0, IPPROTO_TCP, 0);
244e27ad
AD		 6040 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6041 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6042 }
6043
091a6246 6044 /* compute header lengths */
897ab156
AD		 6045 l4len = tcp_hdrlen(skb);
6046 *hdr_len = skb_transport_offset(skb) + l4len;
6047
091a6246
AD		 6048 /* update gso size and bytecount with header size */
6049 first->gso_segs = skb_shinfo(skb)->gso_segs;
6050 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6051
c44f5f51 6052 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6053 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6054 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6055
6056 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6057 vlan_macip_lens = skb_network_header_len(skb);
6058 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6059 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6060
6061 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6062 mss_l4len_idx);
897ab156
AD		 6063
6064 return 1;
6065}
6066
244e27ad
AD		 6067static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6068 struct ixgbe_tx_buffer *first)
7ca647bd 6069{
fd0db0ed 6070 struct sk_buff *skb = first->skb;
897ab156
AD		 6071 u32 vlan_macip_lens = 0;
6072 u32 mss_l4len_idx = 0;
6073 u32 type_tucmd = 0;
7ca647bd 6074
897ab156 6075 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6076 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6077 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6078 return;
897ab156
AD		 6079 } else {
6080 u8 l4_hdr = 0;
244e27ad 6081 switch (first->protocol) {
897ab156
AD		 6082 case __constant_htons(ETH_P_IP):
6083 vlan_macip_lens |= skb_network_header_len(skb);
6084 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6085 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6086 break;
897ab156
AD		 6087 case __constant_htons(ETH_P_IPV6):
6088 vlan_macip_lens |= skb_network_header_len(skb);
6089 l4_hdr = ipv6_hdr(skb)->nexthdr;
6090 break;
6091 default:
6092 if (unlikely(net_ratelimit())) {
6093 dev_warn(tx_ring->dev,
6094 "partial checksum but proto=%x!\n",
244e27ad 6095 first->protocol);
897ab156 6096 }
7ca647bd
JP		 6097 break;
6098 }
897ab156
AD		 6099
6100 switch (l4_hdr) {
7ca647bd 6101 case IPPROTO_TCP:
897ab156
AD		 6102 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6103 mss_l4len_idx = tcp_hdrlen(skb) <<
6104 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6105 break;
6106 case IPPROTO_SCTP:
897ab156
AD		 6107 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6108 mss_l4len_idx = sizeof(struct sctphdr) <<
6109 IXGBE_ADVTXD_L4LEN_SHIFT;
6110 break;
6111 case IPPROTO_UDP:
6112 mss_l4len_idx = sizeof(struct udphdr) <<
6113 IXGBE_ADVTXD_L4LEN_SHIFT;
6114 break;
6115 default:
6116 if (unlikely(net_ratelimit())) {
6117 dev_warn(tx_ring->dev,
6118 "partial checksum but l4 proto=%x!\n",
244e27ad 6119 l4_hdr);
897ab156 6120 }
7ca647bd
JP		 6121 break;
6122 }
244e27ad
AD		 6123
6124 /* update TX checksum flag */
6125 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6126 }
6127
244e27ad 6128 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6129 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6130 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6131
897ab156
AD		 6132 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6133 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6134}
6135
472148c3
AD		 6136#define IXGBE_SET_FLAG(_input, _flag, _result) \
6137 ((_flag <= _result) ? \
6138 ((u32)(_input & _flag) * (_result / _flag)) : \
6139 ((u32)(_input & _flag) / (_flag / _result)))
6140
6141static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6142{
d3d00239 6143 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6144 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6145 IXGBE_ADVTXD_DCMD_DEXT |
6146 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6147
d3d00239 6148 /* set HW vlan bit if vlan is present */
472148c3
AD		 6149 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6150 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6151
d3d00239 6152 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6153 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6154 IXGBE_ADVTXD_DCMD_TSE);
6155
6156 /* set timestamp bit if present */
6157 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6158 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6159
62748b7b 6160 /* insert frame checksum */
472148c3 6161 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6162
d3d00239
AD		 6163 return cmd_type;
6164}
9a799d71 6165
729739b7
AD		 6166static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6167 u32 tx_flags, unsigned int paylen)
d3d00239 6168{
472148c3 6169 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6170
d3d00239 6171 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6172 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6173 IXGBE_TX_FLAGS_CSUM,
6174 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6175
93f5b3c1 6176 /* enble IPv4 checksum for TSO */
472148c3
AD		 6177 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6178 IXGBE_TX_FLAGS_IPV4,
6179 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6180
7f9643fd
AD		 6181 /*
6182 * Check Context must be set if Tx switch is enabled, which it
6183 * always is for case where virtual functions are running
6184 */
472148c3
AD		 6185 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6186 IXGBE_TX_FLAGS_CC,
6187 IXGBE_ADVTXD_CC);
7f9643fd 6188
472148c3 6189 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6190}
44df32c5 6191
d3d00239
AD		 6192#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6193 IXGBE_TXD_CMD_RS)
6194
6195static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6196 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6197 const u8 hdr_len)
6198{
fd0db0ed 6199 struct sk_buff *skb = first->skb;
729739b7 6200 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6201 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6202 struct skb_frag_struct *frag;
6203 dma_addr_t dma;
6204 unsigned int data_len, size;
244e27ad 6205 u32 tx_flags = first->tx_flags;
472148c3 6206 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6207 u16 i = tx_ring->next_to_use;
d3d00239 6208
729739b7
AD		 6209 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6210
ec718254
AD		 6211 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6212
6213 size = skb_headlen(skb);
6214 data_len = skb->data_len;
729739b7 6215
d3d00239
AD		 6216#ifdef IXGBE_FCOE
6217 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6218 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6219 size -= sizeof(struct fcoe_crc_eof) - data_len;
6220 data_len = 0;
729739b7
AD		 6221 } else {
6222 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6223 }
6224 }
44df32c5 6225
d3d00239 6226#endif
729739b7 6227 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6228
ec718254 6229 tx_buffer = first;
9a799d71 6230
ec718254
AD		 6231 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6232 if (dma_mapping_error(tx_ring->dev, dma))
6233 goto dma_error;
6234
6235 /* record length, and DMA address */
6236 dma_unmap_len_set(tx_buffer, len, size);
6237 dma_unmap_addr_set(tx_buffer, dma, dma);
6238
6239 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6240
729739b7 6241 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6242 tx_desc->read.cmd_type_len =
472148c3 6243 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6244
d3d00239 6245 i++;
729739b7 6246 tx_desc++;
d3d00239 6247 if (i == tx_ring->count) {
e4f74028 6248 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6249 i = 0;
6250 }
ec718254 6251 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6252
6253 dma += IXGBE_MAX_DATA_PER_TXD;
6254 size -= IXGBE_MAX_DATA_PER_TXD;
6255
6256 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6257 }
e5a43549 6258
729739b7
AD		 6259 if (likely(!data_len))
6260 break;
9a799d71 6261
472148c3 6262 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6263
729739b7
AD		 6264 i++;
6265 tx_desc++;
6266 if (i == tx_ring->count) {
6267 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6268 i = 0;
6269 }
ec718254 6270 tx_desc->read.olinfo_status = 0;
9a799d71 6271
d3d00239 6272#ifdef IXGBE_FCOE
9e903e08 6273 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6274#else
9e903e08 6275 size = skb_frag_size(frag);
d3d00239
AD		 6276#endif
6277 data_len -= size;
9a799d71 6278
729739b7
AD		 6279 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6280 DMA_TO_DEVICE);
9a799d71 6281
729739b7 6282 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6283 }
9a799d71 6284
729739b7 6285 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6286 cmd_type |= size | IXGBE_TXD_CMD;
6287 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6288
091a6246 6289 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6290
d3d00239
AD		 6291 /* set the timestamp */
6292 first->time_stamp = jiffies;
9a799d71
AK		 6293
6294 /*
729739b7
AD		 6295 * Force memory writes to complete before letting h/w know there
6296 * are new descriptors to fetch. (Only applicable for weak-ordered
6297 * memory model archs, such as IA-64).
6298 *
6299 * We also need this memory barrier to make certain all of the
6300 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6301 */
6302 wmb();
6303
d3d00239
AD		 6304 /* set next_to_watch value indicating a packet is present */
6305 first->next_to_watch = tx_desc;
6306
729739b7
AD		 6307 i++;
6308 if (i == tx_ring->count)
6309 i = 0;
6310
6311 tx_ring->next_to_use = i;
6312
d3d00239 6313 /* notify HW of packet */
84ea2591 6314 writel(i, tx_ring->tail);
d3d00239
AD		 6315
6316 return;
6317dma_error:
729739b7 6318 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6319
6320 /* clear dma mappings for failed tx_buffer_info map */
6321 for (;;) {
729739b7
AD		 6322 tx_buffer = &tx_ring->tx_buffer_info[i];
6323 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6324 if (tx_buffer == first)
d3d00239
AD		 6325 break;
6326 if (i == 0)
6327 i = tx_ring->count;
6328 i--;
6329 }
6330
d3d00239 6331 tx_ring->next_to_use = i;
9a799d71
AK		 6332}
6333
fd0db0ed 6334static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6335 struct ixgbe_tx_buffer *first)
69830529
AD		 6336{
6337 struct ixgbe_q_vector *q_vector = ring->q_vector;
6338 union ixgbe_atr_hash_dword input = { .dword = 0 };
6339 union ixgbe_atr_hash_dword common = { .dword = 0 };
6340 union {
6341 unsigned char *network;
6342 struct iphdr *ipv4;
6343 struct ipv6hdr *ipv6;
6344 } hdr;
ee9e0f0b 6345 struct tcphdr *th;
905e4a41 6346 __be16 vlan_id;
c4cf55e5 6347
69830529
AD		 6348 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6349 if (!q_vector)
6350 return;
6351
6352 /* do nothing if sampling is disabled */
6353 if (!ring->atr_sample_rate)
d3ead241 6354 return;
c4cf55e5 6355
69830529 6356 ring->atr_count++;
c4cf55e5 6357
69830529 6358 /* snag network header to get L4 type and address */
fd0db0ed 6359 hdr.network = skb_network_header(first->skb);
69830529
AD		 6360
6361 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6362 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6363 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6364 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6365 hdr.ipv4->protocol != IPPROTO_TCP))
6366 return;
ee9e0f0b 6367
fd0db0ed 6368 th = tcp_hdr(first->skb);
c4cf55e5 6369
66f32a8b
AD		 6370 /* skip this packet since it is invalid or the socket is closing */
6371 if (!th || th->fin)
69830529
AD		 6372 return;
6373
6374 /* sample on all syn packets or once every atr sample count */
6375 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6376 return;
6377
6378 /* reset sample count */
6379 ring->atr_count = 0;
6380
244e27ad 6381 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6382
6383 /*
6384 * src and dst are inverted, think how the receiver sees them
6385 *
6386 * The input is broken into two sections, a non-compressed section
6387 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6388 * is XORed together and stored in the compressed dword.
6389 */
6390 input.formatted.vlan_id = vlan_id;
6391
6392 /*
6393 * since src port and flex bytes occupy the same word XOR them together
6394 * and write the value to source port portion of compressed dword
6395 */
244e27ad 6396 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6397 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6398 else
244e27ad 6399 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6400 common.port.dst ^= th->source;
6401
244e27ad 6402 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6403 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6404 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6405 } else {
6406 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6407 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6408 hdr.ipv6->saddr.s6_addr32[1] ^
6409 hdr.ipv6->saddr.s6_addr32[2] ^
6410 hdr.ipv6->saddr.s6_addr32[3] ^
6411 hdr.ipv6->daddr.s6_addr32[0] ^
6412 hdr.ipv6->daddr.s6_addr32[1] ^
6413 hdr.ipv6->daddr.s6_addr32[2] ^
6414 hdr.ipv6->daddr.s6_addr32[3];
6415 }
c4cf55e5
PWJ		 6416
6417 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6418 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6419 input, common, ring->queue_index);
c4cf55e5
PWJ		 6420}
6421
63544e9c 6422static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6423{
fc77dc3c 6424 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6425 /* Herbert's original patch had:
6426 * smp_mb__after_netif_stop_queue();
6427 * but since that doesn't exist yet, just open code it. */
6428 smp_mb();
6429
6430 /* We need to check again in a case another CPU has just
6431 * made room available. */
7d4987de 6432 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6433 return -EBUSY;
6434
6435 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6436 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6437 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6438 return 0;
6439}
6440
82d4e46e 6441static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6442{
7d4987de 6443 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6444 return 0;
fc77dc3c 6445 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6446}
6447
97488bd1 6448#ifdef IXGBE_FCOE
09a3b1f8
SH		 6449static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6450{
97488bd1
AD		 6451 struct ixgbe_adapter *adapter;
6452 struct ixgbe_ring_feature *f;
6453 int txq;
5e09a105 6454
97488bd1
AD		 6455 /*
6456 * only execute the code below if protocol is FCoE
6457 * or FIP and we have FCoE enabled on the adapter
6458 */
6459 switch (vlan_get_protocol(skb)) {
6460 case __constant_htons(ETH_P_FCOE):
6461 case __constant_htons(ETH_P_FIP):
6462 adapter = netdev_priv(dev);
c087663e 6463
97488bd1
AD		 6464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6465 break;
6466 default:
6467 return __netdev_pick_tx(dev, skb);
6468 }
c087663e 6469
97488bd1 6470 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6471
97488bd1
AD		 6472 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6473 smp_processor_id();
56075a98 6474
97488bd1
AD		 6475 while (txq >= f->indices)
6476 txq -= f->indices;
c4cf55e5 6477
97488bd1 6478 return txq + f->offset;
09a3b1f8
SH		 6479}
6480
97488bd1 6481#endif
fc77dc3c 6482netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6483 struct ixgbe_adapter *adapter,
6484 struct ixgbe_ring *tx_ring)
9a799d71 6485{
d3d00239 6486 struct ixgbe_tx_buffer *first;
5f715823 6487 int tso;
d3d00239 6488 u32 tx_flags = 0;
a535c30e 6489 unsigned short f;
a535c30e 6490 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6491 __be16 protocol = skb->protocol;
63544e9c 6492 u8 hdr_len = 0;
5e09a105 6493
a535c30e
AD		 6494 /*
6495 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6496 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6497 * + 2 desc gap to keep tail from touching head,
6498 * + 1 desc for context descriptor,
6499 * otherwise try next time
6500 */
a535c30e
AD		 6501 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6502 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 6503
a535c30e
AD		 6504 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6505 tx_ring->tx_stats.tx_busy++;
6506 return NETDEV_TX_BUSY;
6507 }
6508
fd0db0ed
AD		 6509 /* record the location of the first descriptor for this packet */
6510 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6511 first->skb = skb;
091a6246
AD		 6512 first->bytecount = skb->len;
6513 first->gso_segs = 1;
fd0db0ed 6514
66f32a8b 6515 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6516 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6517 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6518 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6519 /* else if it is a SW VLAN check the next protocol and store the tag */
6520 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6521 struct vlan_hdr *vhdr, _vhdr;
6522 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6523 if (!vhdr)
6524 goto out_drop;
6525
6526 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6527 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6528 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6529 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6530 }
6531
aa7bd467
JK		 6532 skb_tx_timestamp(skb);
6533
3a6a4eda
JK		 6534 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6535 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6536 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 6537
6538 /* schedule check for Tx timestamp */
6539 adapter->ptp_tx_skb = skb_get(skb);
6540 adapter->ptp_tx_start = jiffies;
6541 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 6542 }
3a6a4eda 6543
9e0c5648
AD		 6544#ifdef CONFIG_PCI_IOV
6545 /*
6546 * Use the l2switch_enable flag - would be false if the DMA
6547 * Tx switch had been disabled.
6548 */
6549 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 6550 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 6551
6552#endif
32701dc2 6553 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6554 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6555 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6556 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6557 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6558 tx_flags |= (skb->priority & 0x7) <<
6559 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6560 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6561 struct vlan_ethhdr *vhdr;
6562 if (skb_header_cloned(skb) &&
6563 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6564 goto out_drop;
6565 vhdr = (struct vlan_ethhdr *)skb->data;
6566 vhdr->h_vlan_TCI = htons(tx_flags >>
6567 IXGBE_TX_FLAGS_VLAN_SHIFT);
6568 } else {
6569 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6570 }
9a799d71 6571 }
eacd73f7 6572
244e27ad
AD		 6573 /* record initial flags and protocol */
6574 first->tx_flags = tx_flags;
6575 first->protocol = protocol;
6576
eacd73f7 6577#ifdef IXGBE_FCOE
66f32a8b
AD		 6578 /* setup tx offload for FCoE */
6579 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6580 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6581 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6582 if (tso < 0)
6583 goto out_drop;
9a799d71 6584
66f32a8b 6585 goto xmit_fcoe;
eacd73f7 6586 }
9a799d71 6587
66f32a8b 6588#endif /* IXGBE_FCOE */
244e27ad 6589 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6590 if (tso < 0)
897ab156 6591 goto out_drop;
244e27ad
AD		 6592 else if (!tso)
6593 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6594
6595 /* add the ATR filter if ATR is on */
6596 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6597 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6598
6599#ifdef IXGBE_FCOE
6600xmit_fcoe:
6601#endif /* IXGBE_FCOE */
244e27ad 6602 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6603
6604 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6605
6606 return NETDEV_TX_OK;
897ab156
AD		 6607
6608out_drop:
fd0db0ed
AD		 6609 dev_kfree_skb_any(first->skb);
6610 first->skb = NULL;
6611
897ab156 6612 return NETDEV_TX_OK;
9a799d71
AK		 6613}
6614
a50c29dd
AD		 6615static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6616 struct net_device *netdev)
84418e3b
AD		 6617{
6618 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6619 struct ixgbe_ring *tx_ring;
6620
a50c29dd
AD		 6621 /*
6622 * The minimum packet size for olinfo paylen is 17 so pad the skb
6623 * in order to meet this minimum size requirement.
6624 */
f73332fc
SH		 6625 if (unlikely(skb->len < 17)) {
6626 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6627 return NETDEV_TX_OK;
6628 skb->len = 17;
71a49f77 6629 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6630 }
6631
84418e3b 6632 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6633 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6634}
6635
9a799d71
AK		 6636/**
6637 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6638 * @netdev: network interface device structure
6639 * @p: pointer to an address structure
6640 *
6641 * Returns 0 on success, negative on failure
6642 **/
6643static int ixgbe_set_mac(struct net_device *netdev, void *p)
6644{
6645 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6646 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6647 struct sockaddr *addr = p;
6648
6649 if (!is_valid_ether_addr(addr->sa_data))
6650 return -EADDRNOTAVAIL;
6651
6652 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6653 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6654
1d9c0bfd 6655 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6656
6657 return 0;
6658}
6659
6b73e10d
BH		 6660static int
6661ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6662{
6663 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6664 struct ixgbe_hw *hw = &adapter->hw;
6665 u16 value;
6666 int rc;
6667
6668 if (prtad != hw->phy.mdio.prtad)
6669 return -EINVAL;
6670 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6671 if (!rc)
6672 rc = value;
6673 return rc;
6674}
6675
6676static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6677 u16 addr, u16 value)
6678{
6679 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6680 struct ixgbe_hw *hw = &adapter->hw;
6681
6682 if (prtad != hw->phy.mdio.prtad)
6683 return -EINVAL;
6684 return hw->phy.ops.write_reg(hw, addr, devad, value);
6685}
6686
6687static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6688{
6689 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6690
3a6a4eda 6691 switch (cmd) {
3a6a4eda
JK		 6692 case SIOCSHWTSTAMP:
6693 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6694 default:
6695 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6696 }
6b73e10d
BH		 6697}
6698
0365e6e4
PW		 6699/**
6700 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6701 * netdev->dev_addrs
0365e6e4
PW		 6702 * @netdev: network interface device structure
6703 *
6704 * Returns non-zero on failure
6705 **/
6706static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6707{
6708 int err = 0;
6709 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6710 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6711
7fa7c9dc 6712 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6713 rtnl_lock();
7fa7c9dc 6714 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6715 rtnl_unlock();
7fa7c9dc
AD		 6716
6717 /* update SAN MAC vmdq pool selection */
6718 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6719 }
6720 return err;
6721}
6722
6723/**
6724 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6725 * netdev->dev_addrs
0365e6e4
PW		 6726 * @netdev: network interface device structure
6727 *
6728 * Returns non-zero on failure
6729 **/
6730static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6731{
6732 int err = 0;
6733 struct ixgbe_adapter *adapter = netdev_priv(dev);
6734 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6735
6736 if (is_valid_ether_addr(mac->san_addr)) {
6737 rtnl_lock();
6738 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6739 rtnl_unlock();
6740 }
6741 return err;
6742}
6743
9a799d71
AK		 6744#ifdef CONFIG_NET_POLL_CONTROLLER
6745/*
6746 * Polling 'interrupt' - used by things like netconsole to send skbs
6747 * without having to re-enable interrupts. It's not called while
6748 * the interrupt routine is executing.
6749 */
6750static void ixgbe_netpoll(struct net_device *netdev)
6751{
6752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6753 int i;
9a799d71 6754
1a647bd2
AD		 6755 /* if interface is down do nothing */
6756 if (test_bit(__IXGBE_DOWN, &adapter->state))
6757 return;
6758
9a799d71 6759 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6760 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6761 for (i = 0; i < adapter->num_q_vectors; i++)
6762 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6763 } else {
6764 ixgbe_intr(adapter->pdev->irq, netdev);
6765 }
9a799d71 6766 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6767}
9a799d71 6768
581330ba 6769#endif
de1036b1
ED		 6770static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6771 struct rtnl_link_stats64 *stats)
6772{
6773 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6774 int i;
6775
1a51502b 6776 rcu_read_lock();
de1036b1 6777 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6778 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6779 u64 bytes, packets;
6780 unsigned int start;
6781
1a51502b
ED		 6782 if (ring) {
6783 do {
6784 start = u64_stats_fetch_begin_bh(&ring->syncp);
6785 packets = ring->stats.packets;
6786 bytes = ring->stats.bytes;
6787 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6788 stats->rx_packets += packets;
6789 stats->rx_bytes += bytes;
6790 }
de1036b1 6791 }
1ac9ad13
ED		 6792
6793 for (i = 0; i < adapter->num_tx_queues; i++) {
6794 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6795 u64 bytes, packets;
6796 unsigned int start;
6797
6798 if (ring) {
6799 do {
6800 start = u64_stats_fetch_begin_bh(&ring->syncp);
6801 packets = ring->stats.packets;
6802 bytes = ring->stats.bytes;
6803 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6804 stats->tx_packets += packets;
6805 stats->tx_bytes += bytes;
6806 }
6807 }
1a51502b 6808 rcu_read_unlock();
de1036b1
ED		 6809 /* following stats updated by ixgbe_watchdog_task() */
6810 stats->multicast = netdev->stats.multicast;
6811 stats->rx_errors = netdev->stats.rx_errors;
6812 stats->rx_length_errors = netdev->stats.rx_length_errors;
6813 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6814 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6815 return stats;
6816}
6817
8af3c33f 6818#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6819/**
6820 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6821 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6822 * @tc: number of traffic classes currently enabled
6823 *
6824 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6825 * 802.1Q priority maps to a packet buffer that exists.
6826 */
6827static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6828{
6829 struct ixgbe_hw *hw = &adapter->hw;
6830 u32 reg, rsave;
6831 int i;
6832
6833 /* 82598 have a static priority to TC mapping that can not
6834 * be changed so no validation is needed.
6835 */
6836 if (hw->mac.type == ixgbe_mac_82598EB)
6837 return;
6838
6839 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6840 rsave = reg;
6841
6842 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6843 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6844
6845 /* If up2tc is out of bounds default to zero */
6846 if (up2tc > tc)
6847 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6848 }
6849
6850 if (reg != rsave)
6851 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6852
6853 return;
6854}
6855
02debdc9
AD		 6856/**
6857 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6858 * @adapter: Pointer to adapter struct
6859 *
6860 * Populate the netdev user priority to tc map
6861 */
6862static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6863{
6864 struct net_device *dev = adapter->netdev;
6865 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6866 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6867 u8 prio;
6868
6869 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6870 u8 tc = 0;
6871
6872 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6873 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6874 else if (ets)
6875 tc = ets->prio_tc[prio];
6876
6877 netdev_set_prio_tc_map(dev, prio, tc);
6878 }
6879}
6880
cca73c59 6881#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 6882/**
6883 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6884 *
6885 * @netdev: net device to configure
6886 * @tc: number of traffic classes to enable
6887 */
6888int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6889{
8b1c0b24
JF		 6890 struct ixgbe_adapter *adapter = netdev_priv(dev);
6891 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6892
8b1c0b24 6893 /* Hardware supports up to 8 traffic classes */
4de2a022 6894 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6895 (hw->mac.type == ixgbe_mac_82598EB &&
6896 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6897 return -EINVAL;
6898
6899 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6900 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6901 * hardware is not flexible enough to do this dynamically.
6902 */
6903 if (netif_running(dev))
6904 ixgbe_close(dev);
6905 ixgbe_clear_interrupt_scheme(adapter);
6906
cca73c59 6907#ifdef CONFIG_IXGBE_DCB
e7589eab 6908 if (tc) {
8b1c0b24 6909 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6910 ixgbe_set_prio_tc_map(adapter);
6911
e7589eab 6912 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6913
943561d3
AD		 6914 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6915 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6916 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6917 }
e7589eab 6918 } else {
8b1c0b24 6919 netdev_reset_tc(dev);
02debdc9 6920
943561d3
AD		 6921 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6922 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6923
6924 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6925
6926 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6927 adapter->dcb_cfg.pfc_mode_enable = false;
6928 }
6929
8b1c0b24 6930 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 6931
6932#endif /* CONFIG_IXGBE_DCB */
6933 ixgbe_init_interrupt_scheme(adapter);
6934
8b1c0b24 6935 if (netif_running(dev))
cca73c59 6936 return ixgbe_open(dev);
8b1c0b24
JF		 6937
6938 return 0;
6939}
de1036b1 6940
da36b647
GR		 6941#ifdef CONFIG_PCI_IOV
6942void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6943{
6944 struct net_device *netdev = adapter->netdev;
6945
6946 rtnl_lock();
da36b647 6947 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 6948 rtnl_unlock();
6949}
6950
6951#endif
082757af
DS		 6952void ixgbe_do_reset(struct net_device *netdev)
6953{
6954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6955
6956 if (netif_running(netdev))
6957 ixgbe_reinit_locked(adapter);
6958 else
6959 ixgbe_reset(adapter);
6960}
6961
c8f44aff 6962static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6963 netdev_features_t features)
082757af
DS		 6964{
6965 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6966
082757af 6967 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6968 if (!(features & NETIF_F_RXCSUM))
6969 features &= ~NETIF_F_LRO;
082757af 6970
567d2de2
AD		 6971 /* Turn off LRO if not RSC capable */
6972 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6973 features &= ~NETIF_F_LRO;
8e2813f5 6974
567d2de2 6975 return features;
082757af
DS		 6976}
6977
c8f44aff 6978static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6979 netdev_features_t features)
082757af
DS		 6980{
6981 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6982 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6983 bool need_reset = false;
6984
082757af 6985 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6986 if (!(features & NETIF_F_LRO)) {
6987 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6988 need_reset = true;
567d2de2
AD		 6989 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6990 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6991 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6992 if (adapter->rx_itr_setting == 1 ||
6993 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6994 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6995 need_reset = true;
6996 } else if ((changed ^ features) & NETIF_F_LRO) {
6997 e_info(probe, "rx-usecs set too low, "
6998 "disabling RSC\n");
082757af
DS		 6999 }
7000 }
7001
7002 /*
7003 * Check if Flow Director n-tuple support was enabled or disabled. If
7004 * the state changed, we need to reset.
7005 */
39cb681b
AD		 7006 switch (features & NETIF_F_NTUPLE) {
7007 case NETIF_F_NTUPLE:
567d2de2 7008 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7009 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7010 need_reset = true;
7011
567d2de2
AD		 7012 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7013 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7014 break;
7015 default:
7016 /* turn off perfect filters, enable ATR and reset */
7017 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7018 need_reset = true;
7019
7020 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7021
7022 /* We cannot enable ATR if SR-IOV is enabled */
7023 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7024 break;
7025
7026 /* We cannot enable ATR if we have 2 or more traffic classes */
7027 if (netdev_get_num_tc(netdev) > 1)
7028 break;
7029
7030 /* We cannot enable ATR if RSS is disabled */
7031 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7032 break;
7033
7034 /* A sample rate of 0 indicates ATR disabled */
7035 if (!adapter->atr_sample_rate)
7036 break;
7037
7038 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7039 break;
082757af
DS		 7040 }
7041
f646968f 7042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7043 ixgbe_vlan_strip_enable(adapter);
7044 else
7045 ixgbe_vlan_strip_disable(adapter);
7046
3f2d1c0f
BG		 7047 if (changed & NETIF_F_RXALL)
7048 need_reset = true;
7049
567d2de2 7050 netdev->features = features;
082757af
DS		 7051 if (need_reset)
7052 ixgbe_do_reset(netdev);
7053
7054 return 0;
082757af
DS		 7055}
7056
edc7d573 7057static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7058 struct net_device *dev,
6b6e2725 7059 const unsigned char *addr,
0f4b0add
JF		 7060 u16 flags)
7061{
7062 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7063 int err;
7064
7065 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7066 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7067
b1ac1ef7
JF		 7068 /* Hardware does not support aging addresses so if a
7069 * ndm_state is given only allow permanent addresses
7070 */
7071 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7072 pr_info("%s: FDB only supports static addresses\n",
7073 ixgbe_driver_name);
7074 return -EINVAL;
7075 }
7076
46acc460 7077 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7078 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7079
7080 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7081 err = dev_uc_add_excl(dev, addr);
0f4b0add 7082 else
95447461
JF		 7083 err = -ENOMEM;
7084 } else if (is_multicast_ether_addr(addr)) {
7085 err = dev_mc_add_excl(dev, addr);
7086 } else {
7087 err = -EINVAL;
0f4b0add
JF		 7088 }
7089
7090 /* Only return duplicate errors if NLM_F_EXCL is set */
7091 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7092 err = 0;
7093
7094 return err;
7095}
7096
815cccbf
JF		 7097static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7098 struct nlmsghdr *nlh)
7099{
7100 struct ixgbe_adapter *adapter = netdev_priv(dev);
7101 struct nlattr *attr, *br_spec;
7102 int rem;
7103
7104 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7105 return -EOPNOTSUPP;
7106
7107 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7108
7109 nla_for_each_nested(attr, br_spec, rem) {
7110 __u16 mode;
7111 u32 reg = 0;
7112
7113 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7114 continue;
7115
7116 mode = nla_get_u16(attr);
9b735984 7117 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7118 reg = 0;
9b735984
GR		 7119 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7120 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7121 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7122 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7123 } else
815cccbf
JF		 7124 return -EINVAL;
7125
7126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7127
7128 e_info(drv, "enabling bridge mode: %s\n",
7129 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7130 }
7131
7132 return 0;
7133}
7134
7135static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7136 struct net_device *dev,
7137 u32 filter_mask)
815cccbf
JF		 7138{
7139 struct ixgbe_adapter *adapter = netdev_priv(dev);
7140 u16 mode;
7141
7142 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7143 return 0;
7144
9b735984 7145 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7146 mode = BRIDGE_MODE_VEB;
7147 else
7148 mode = BRIDGE_MODE_VEPA;
7149
7150 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7151}
7152
0edc3527 7153static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7154 .ndo_open = ixgbe_open,
0edc3527 7155 .ndo_stop = ixgbe_close,
00829823 7156 .ndo_start_xmit = ixgbe_xmit_frame,
97488bd1 7157#ifdef IXGBE_FCOE
09a3b1f8 7158 .ndo_select_queue = ixgbe_select_queue,
97488bd1 7159#endif
581330ba 7160 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7161 .ndo_validate_addr = eth_validate_addr,
7162 .ndo_set_mac_address = ixgbe_set_mac,
7163 .ndo_change_mtu = ixgbe_change_mtu,
7164 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7165 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7166 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7167 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7168 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7169 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7170 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7171 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7172 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7173 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7174#ifdef CONFIG_IXGBE_DCB
24095aa3 7175 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7176#endif
0edc3527
SH		 7177#ifdef CONFIG_NET_POLL_CONTROLLER
7178 .ndo_poll_controller = ixgbe_netpoll,
7179#endif
332d4a7d
YZ		 7180#ifdef IXGBE_FCOE
7181 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7182 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7183 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7184 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7185 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7186 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7187 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7188#endif /* IXGBE_FCOE */
082757af
DS		 7189 .ndo_set_features = ixgbe_set_features,
7190 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7191 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7192 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7193 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7194};
7195
8e2813f5
JK		 7196/**
7197 * ixgbe_wol_supported - Check whether device supports WoL
7198 * @hw: hw specific details
7199 * @device_id: the device ID
7200 * @subdev_id: the subsystem device ID
7201 *
7202 * This function is used by probe and ethtool to determine
7203 * which devices have WoL support
7204 *
7205 **/
7206int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7207 u16 subdevice_id)
7208{
7209 struct ixgbe_hw *hw = &adapter->hw;
7210 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7211 int is_wol_supported = 0;
7212
7213 switch (device_id) {
7214 case IXGBE_DEV_ID_82599_SFP:
7215 /* Only these subdevices could supports WOL */
7216 switch (subdevice_id) {
7217 case IXGBE_SUBDEV_ID_82599_560FLR:
7218 /* only support first port */
7219 if (hw->bus.func != 0)
7220 break;
5700ff26 7221 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7222 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7223 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7224 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7225 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7226 is_wol_supported = 1;
7227 break;
7228 }
7229 break;
5daebbb0
DS		 7230 case IXGBE_DEV_ID_82599EN_SFP:
7231 /* Only this subdevice supports WOL */
7232 switch (subdevice_id) {
7233 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7234 is_wol_supported = 1;
7235 break;
7236 }
7237 break;
8e2813f5
JK		 7238 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7239 /* All except this subdevice support WOL */
7240 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7241 is_wol_supported = 1;
7242 break;
7243 case IXGBE_DEV_ID_82599_KX4:
7244 is_wol_supported = 1;
7245 break;
7246 case IXGBE_DEV_ID_X540T:
df376f0d 7247 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7248 /* check eeprom to see if enabled wol */
7249 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7250 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7251 (hw->bus.func == 0))) {
7252 is_wol_supported = 1;
7253 }
7254 break;
7255 }
7256
7257 return is_wol_supported;
7258}
7259
9a799d71
AK		 7260/**
7261 * ixgbe_probe - Device Initialization Routine
7262 * @pdev: PCI device information struct
7263 * @ent: entry in ixgbe_pci_tbl
7264 *
7265 * Returns 0 on success, negative on failure
7266 *
7267 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7268 * The OS initialization, configuring of the adapter private structure,
7269 * and a hardware reset occur.
7270 **/
1dd06ae8 7271static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7272{
7273 struct net_device *netdev;
7274 struct ixgbe_adapter *adapter = NULL;
7275 struct ixgbe_hw *hw;
7276 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7277 static int cards_found;
7278 int i, err, pci_using_dac;
d3cb9869 7279 unsigned int indices = MAX_TX_QUEUES;
289700db 7280 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7281#ifdef IXGBE_FCOE
7282 u16 device_caps;
7283#endif
289700db 7284 u32 eec;
9a799d71 7285
bded64a7
AG		 7286 /* Catch broken hardware that put the wrong VF device ID in
7287 * the PCIe SR-IOV capability.
7288 */
7289 if (pdev->is_virtfn) {
7290 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7291 pci_name(pdev), pdev->vendor, pdev->device);
7292 return -EINVAL;
7293 }
7294
9ce77666 7295 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7296 if (err)
7297 return err;
7298
1b507730
NN		 7299 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7300 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7301 pci_using_dac = 1;
7302 } else {
1b507730 7303 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7304 if (err) {
1b507730
NN		 7305 err = dma_set_coherent_mask(&pdev->dev,
7306 DMA_BIT_MASK(32));
9a799d71 7307 if (err) {
b8bc0421
DC		 7308 dev_err(&pdev->dev,
7309 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7310 goto err_dma;
7311 }
7312 }
7313 pci_using_dac = 0;
7314 }
7315
9ce77666 7316 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7317 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7318 if (err) {
b8bc0421
DC		 7319 dev_err(&pdev->dev,
7320 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7321 goto err_pci_reg;
7322 }
7323
19d5afd4 7324 pci_enable_pcie_error_reporting(pdev);
6fabd715 7325
9a799d71 7326 pci_set_master(pdev);
fb3b27bc 7327 pci_save_state(pdev);
9a799d71 7328
d3cb9869 7329 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7330#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7331 /* 8 TC w/ 4 queues per TC */
7332 indices = 4 * MAX_TRAFFIC_CLASS;
7333#else
7334 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7335#endif
d3cb9869 7336 }
e901acd6 7337
c85a2618 7338 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7339 if (!netdev) {
7340 err = -ENOMEM;
7341 goto err_alloc_etherdev;
7342 }
7343
9a799d71
AK		 7344 SET_NETDEV_DEV(netdev, &pdev->dev);
7345
9a799d71 7346 adapter = netdev_priv(netdev);
c60fbb00 7347 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7348
7349 adapter->netdev = netdev;
7350 adapter->pdev = pdev;
7351 hw = &adapter->hw;
7352 hw->back = adapter;
b3f4d599 7353 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7354
05857980 7355 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7356 pci_resource_len(pdev, 0));
9a799d71
AK		 7357 if (!hw->hw_addr) {
7358 err = -EIO;
7359 goto err_ioremap;
7360 }
7361
0edc3527 7362 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7363 ixgbe_set_ethtool_ops(netdev);
9a799d71 7364 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7365 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7366
9a799d71
AK		 7367 adapter->bd_number = cards_found;
7368
9a799d71
AK		 7369 /* Setup hw api */
7370 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7371 hw->mac.type = ii->mac;
9a799d71 7372
c44ade9e
JB		 7373 /* EEPROM */
7374 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7375 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7376 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7377 if (!(eec & (1 << 8)))
7378 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7379
7380 /* PHY */
7381 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7382 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7383 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7384 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7385 hw->phy.mdio.mmds = 0;
7386 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7387 hw->phy.mdio.dev = netdev;
7388 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7389 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7390
8ca783ab 7391 ii->get_invariants(hw);
9a799d71
AK		 7392
7393 /* setup the private structure */
7394 err = ixgbe_sw_init(adapter);
7395 if (err)
7396 goto err_sw_init;
7397
0b2679d6
DS		 7398 /* Cache if MNG FW is up so we don't have to read the REG later */
7399 if (hw->mac.ops.mng_fw_enabled)
7400 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7401
e86bff0e 7402 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7403 switch (adapter->hw.mac.type) {
7404 case ixgbe_mac_82599EB:
7405 case ixgbe_mac_X540:
e86bff0e 7406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7407 break;
7408 default:
7409 break;
7410 }
e86bff0e 7411
bf069c97
DS		 7412 /*
7413 * If there is a fan on this device and it has failed log the
7414 * failure.
7415 */
7416 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7417 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7418 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7419 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7420 }
7421
8ef78adc
PWJ		 7422 if (allow_unsupported_sfp)
7423 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7424
c44ade9e 7425 /* reset_hw fills in the perm_addr as well */
119fc60a 7426 hw->phy.reset_if_overtemp = true;
c44ade9e 7427 err = hw->mac.ops.reset_hw(hw);
119fc60a 7428 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7429 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7430 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7431 err = 0;
7432 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7433 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7434 "module type was detected.\n");
7435 e_dev_err("Reload the driver after installing a supported "
7436 "module.\n");
04f165ef
PW		 7437 goto err_sw_init;
7438 } else if (err) {
849c4542 7439 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7440 goto err_sw_init;
7441 }
7442
99d74487 7443#ifdef CONFIG_PCI_IOV
60a1a680
GR		 7444 /* SR-IOV not supported on the 82598 */
7445 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7446 goto skip_sriov;
7447 /* Mailbox */
7448 ixgbe_init_mbx_params_pf(hw);
7449 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7450 ixgbe_enable_sriov(adapter);
43dc4e01 7451 pci_sriov_set_totalvfs(pdev, 63);
60a1a680 7452skip_sriov:
1cdd1ec8 7453
99d74487 7454#endif
396e799c 7455 netdev->features = NETIF_F_SG |
e8e9f696 7456 NETIF_F_IP_CSUM |
082757af 7457 NETIF_F_IPV6_CSUM |
f646968f
PM		 7458 NETIF_F_HW_VLAN_CTAG_TX |
7459 NETIF_F_HW_VLAN_CTAG_RX |
7460 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 7461 NETIF_F_TSO |
7462 NETIF_F_TSO6 |
082757af
DS		 7463 NETIF_F_RXHASH |
7464 NETIF_F_RXCSUM;
9a799d71 7465
082757af 7466 netdev->hw_features = netdev->features;
ad31c402 7467
58be7666
DS		 7468 switch (adapter->hw.mac.type) {
7469 case ixgbe_mac_82599EB:
7470 case ixgbe_mac_X540:
45a5ead0 7471 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7472 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7473 NETIF_F_NTUPLE;
58be7666
DS		 7474 break;
7475 default:
7476 break;
7477 }
45a5ead0 7478
3f2d1c0f
BG		 7479 netdev->hw_features |= NETIF_F_RXALL;
7480
ad31c402
JK		 7481 netdev->vlan_features |= NETIF_F_TSO;
7482 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7483 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7484 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7485 netdev->vlan_features |= NETIF_F_SG;
7486
01789349 7487 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7488 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7489
7a6b6f51 7490#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7491 netdev->dcbnl_ops = &dcbnl_ops;
7492#endif
7493
eacd73f7 7494#ifdef IXGBE_FCOE
0d551589 7495 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 7496 unsigned int fcoe_l;
7497
eacd73f7
YZ		 7498 if (hw->mac.ops.get_device_caps) {
7499 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7500 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7501 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7502 }
7c8ae65a 7503
d3cb9869
AD		 7504
7505 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7506 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 7507
a58915c7
AD		 7508 netdev->features |= NETIF_F_FSO |
7509 NETIF_F_FCOE_CRC;
7510
7c8ae65a
AD		 7511 netdev->vlan_features |= NETIF_F_FSO |
7512 NETIF_F_FCOE_CRC |
7513 NETIF_F_FCOE_MTU;
5e09d7f6 7514 }
eacd73f7 7515#endif /* IXGBE_FCOE */
7b872a55 7516 if (pci_using_dac) {
9a799d71 7517 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7518 netdev->vlan_features |= NETIF_F_HIGHDMA;
7519 }
9a799d71 7520
082757af
DS		 7521 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7522 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7523 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7524 netdev->features |= NETIF_F_LRO;
7525
9a799d71 7526 /* make sure the EEPROM is good */
c44ade9e 7527 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7528 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7529 err = -EIO;
35937c05 7530 goto err_sw_init;
9a799d71
AK		 7531 }
7532
7533 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 7534
aaeb6cdf 7535 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 7536 e_dev_err("invalid MAC address\n");
9a799d71 7537 err = -EIO;
35937c05 7538 goto err_sw_init;
9a799d71
AK		 7539 }
7540
7086400d 7541 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7542 (unsigned long) adapter);
9a799d71 7543
7086400d
AD		 7544 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7545 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7546
021230d4
AV		 7547 err = ixgbe_init_interrupt_scheme(adapter);
7548 if (err)
7549 goto err_sw_init;
9a799d71 7550
8e2813f5 7551 /* WOL not supported for all devices */
c23f5b6b 7552 adapter->wol = 0;
8e2813f5 7553 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 7554 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 7555 pdev->subsystem_device);
6b92b0ba 7556 if (hw->wol_enabled)
9417c464 7557 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7558
e8e26350
PW		 7559 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7560
15e5209f
ET		 7561 /* save off EEPROM version number */
7562 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7563 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7564
04f165ef
PW		 7565 /* pick up the PCI bus settings for reporting later */
7566 hw->mac.ops.get_bus_info(hw);
b8e82001
JK		 7567 if (hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP)
7568 ixgbe_get_parent_bus_info(adapter);
04f165ef 7569
9a799d71 7570 /* print bus type/speed/width info */
849c4542 7571 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8710a5f
JK		 7572 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7573 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
6716344c 7574 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7575 "Unknown"),
7576 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7577 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7578 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7579 "Unknown"),
7580 netdev->dev_addr);
289700db
DS		 7581
7582 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7583 if (err)
9fe93afd 7584 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7585 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7586 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7587 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7588 part_str);
e8e26350 7589 else
289700db
DS		 7590 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7591 hw->mac.type, hw->phy.type, part_str);
9a799d71 7592
e8e26350 7593 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7594 e_dev_warn("PCI-Express bandwidth available for this card is "
7595 "not sufficient for optimal performance.\n");
7596 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7597 "is required.\n");
0c254d86
AK		 7598 }
7599
9a799d71 7600 /* reset the hardware with the new settings */
794caeb2 7601 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7602 if (err == IXGBE_ERR_EEPROM_VERSION) {
7603 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7604 e_dev_warn("This device is a pre-production adapter/LOM. "
7605 "Please be aware there may be issues associated "
7606 "with your hardware. If you are experiencing "
7607 "problems please contact your Intel or hardware "
7608 "representative who provided you with this "
7609 "hardware.\n");
794caeb2 7610 }
9a799d71
AK		 7611 strcpy(netdev->name, "eth%d");
7612 err = register_netdev(netdev);
7613 if (err)
7614 goto err_register;
7615
ec74a471
ET		 7616 /* power down the optics for 82599 SFP+ fiber */
7617 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7618 hw->mac.ops.disable_tx_laser(hw);
7619
54386467
JB		 7620 /* carrier off reporting is important to ethtool even BEFORE open */
7621 netif_carrier_off(netdev);
7622
5dd2d332 7623#ifdef CONFIG_IXGBE_DCA
652f093f 7624 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7625 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7626 ixgbe_setup_dca(adapter);
7627 }
7628#endif
1cdd1ec8 7629 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7630 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7631 for (i = 0; i < adapter->num_vfs; i++)
7632 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7633 }
7634
2466dd9c
JK		 7635 /* firmware requires driver version to be 0xFFFFFFFF
7636 * since os does not support feature
7637 */
9612de92 7638 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7639 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7640 0xFF);
9612de92 7641
0365e6e4
PW		 7642 /* add san mac addr to netdev */
7643 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7644
ea81875a 7645 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7646 cards_found++;
3ca8bc6d 7647
1210982b 7648#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7649 if (ixgbe_sysfs_init(adapter))
7650 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7651#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7652
00949167 7653 ixgbe_dbg_adapter_init(adapter);
00949167 7654
0b2679d6
DS		 7655 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7656 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7657 hw->mac.ops.setup_link(hw,
7658 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7659 true);
7660
9a799d71
AK		 7661 return 0;
7662
7663err_register:
5eba3699 7664 ixgbe_release_hw_control(adapter);
7a921c93 7665 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7666err_sw_init:
99d74487 7667 ixgbe_disable_sriov(adapter);
7086400d 7668 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7669 iounmap(hw->hw_addr);
7670err_ioremap:
7671 free_netdev(netdev);
7672err_alloc_etherdev:
e8e9f696
JP		 7673 pci_release_selected_regions(pdev,
7674 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7675err_pci_reg:
7676err_dma:
7677 pci_disable_device(pdev);
7678 return err;
7679}
7680
7681/**
7682 * ixgbe_remove - Device Removal Routine
7683 * @pdev: PCI device information struct
7684 *
7685 * ixgbe_remove is called by the PCI subsystem to alert the driver
7686 * that it should release a PCI device. The could be caused by a
7687 * Hot-Plug event, or because the driver is going to be removed from
7688 * memory.
7689 **/
9f9a12f8 7690static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 7691{
c60fbb00
AD		 7692 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7693 struct net_device *netdev = adapter->netdev;
9a799d71 7694
00949167 7695 ixgbe_dbg_adapter_exit(adapter);
00949167 7696
9a799d71 7697 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7698 cancel_work_sync(&adapter->service_task);
9a799d71 7699
3a6a4eda 7700
5dd2d332 7701#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7702 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7703 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7704 dca_remove_requester(&pdev->dev);
7705 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7706 }
7707
7708#endif
1210982b 7709#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7710 ixgbe_sysfs_exit(adapter);
1210982b 7711#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7712
0365e6e4
PW		 7713 /* remove the added san mac */
7714 ixgbe_del_sanmac_netdev(netdev);
7715
c4900be0
DS		 7716 if (netdev->reg_state == NETREG_REGISTERED)
7717 unregister_netdev(netdev);
9a799d71 7718
da36b647
GR		 7719#ifdef CONFIG_PCI_IOV
7720 /*
7721 * Only disable SR-IOV on unload if the user specified the now
7722 * deprecated max_vfs module parameter.
7723 */
7724 if (max_vfs)
7725 ixgbe_disable_sriov(adapter);
7726#endif
7a921c93 7727 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7728
021230d4 7729 ixgbe_release_hw_control(adapter);
9a799d71 7730
2b1588c3
AD		 7731#ifdef CONFIG_DCB
7732 kfree(adapter->ixgbe_ieee_pfc);
7733 kfree(adapter->ixgbe_ieee_ets);
7734
7735#endif
9a799d71 7736 iounmap(adapter->hw.hw_addr);
9ce77666 7737 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7738 IORESOURCE_MEM));
9a799d71 7739
849c4542 7740 e_dev_info("complete\n");
021230d4 7741
9a799d71
AK		 7742 free_netdev(netdev);
7743
19d5afd4 7744 pci_disable_pcie_error_reporting(pdev);
6fabd715 7745
9a799d71
AK		 7746 pci_disable_device(pdev);
7747}
7748
7749/**
7750 * ixgbe_io_error_detected - called when PCI error is detected
7751 * @pdev: Pointer to PCI device
7752 * @state: The current pci connection state
7753 *
7754 * This function is called after a PCI bus error affecting
7755 * this device has been detected.
7756 */
7757static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7758 pci_channel_state_t state)
9a799d71 7759{
c60fbb00
AD		 7760 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7761 struct net_device *netdev = adapter->netdev;
9a799d71 7762
83c61fa9
GR		 7763#ifdef CONFIG_PCI_IOV
7764 struct pci_dev *bdev, *vfdev;
7765 u32 dw0, dw1, dw2, dw3;
7766 int vf, pos;
7767 u16 req_id, pf_func;
7768
7769 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7770 adapter->num_vfs == 0)
7771 goto skip_bad_vf_detection;
7772
7773 bdev = pdev->bus->self;
62f87c0e 7774 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7775 bdev = bdev->bus->self;
7776
7777 if (!bdev)
7778 goto skip_bad_vf_detection;
7779
7780 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7781 if (!pos)
7782 goto skip_bad_vf_detection;
7783
7784 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7785 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7786 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7787 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7788
7789 req_id = dw1 >> 16;
7790 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7791 if (!(req_id & 0x0080))
7792 goto skip_bad_vf_detection;
7793
7794 pf_func = req_id & 0x01;
7795 if ((pf_func & 1) == (pdev->devfn & 1)) {
7796 unsigned int device_id;
7797
7798 vf = (req_id & 0x7F) >> 1;
7799 e_dev_err("VF %d has caused a PCIe error\n", vf);
7800 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7801 "%8.8x\tdw3: %8.8x\n",
7802 dw0, dw1, dw2, dw3);
7803 switch (adapter->hw.mac.type) {
7804 case ixgbe_mac_82599EB:
7805 device_id = IXGBE_82599_VF_DEVICE_ID;
7806 break;
7807 case ixgbe_mac_X540:
7808 device_id = IXGBE_X540_VF_DEVICE_ID;
7809 break;
7810 default:
7811 device_id = 0;
7812 break;
7813 }
7814
7815 /* Find the pci device of the offending VF */
36e90319 7816 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7817 while (vfdev) {
7818 if (vfdev->devfn == (req_id & 0xFF))
7819 break;
36e90319 7820 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7821 device_id, vfdev);
7822 }
7823 /*
7824 * There's a slim chance the VF could have been hot plugged,
7825 * so if it is no longer present we don't need to issue the
7826 * VFLR. Just clean up the AER in that case.
7827 */
7828 if (vfdev) {
7829 e_dev_err("Issuing VFLR to VF %d\n", vf);
7830 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 7831 /* Free device reference count */
7832 pci_dev_put(vfdev);
83c61fa9
GR		 7833 }
7834
7835 pci_cleanup_aer_uncorrect_error_status(pdev);
7836 }
7837
7838 /*
7839 * Even though the error may have occurred on the other port
7840 * we still need to increment the vf error reference count for
7841 * both ports because the I/O resume function will be called
7842 * for both of them.
7843 */
7844 adapter->vferr_refcount++;
7845
7846 return PCI_ERS_RESULT_RECOVERED;
7847
7848skip_bad_vf_detection:
7849#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7850 netif_device_detach(netdev);
7851
3044b8d1
BL		 7852 if (state == pci_channel_io_perm_failure)
7853 return PCI_ERS_RESULT_DISCONNECT;
7854
9a799d71
AK		 7855 if (netif_running(netdev))
7856 ixgbe_down(adapter);
7857 pci_disable_device(pdev);
7858
b4617240 7859 /* Request a slot reset. */
9a799d71
AK		 7860 return PCI_ERS_RESULT_NEED_RESET;
7861}
7862
7863/**
7864 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7865 * @pdev: Pointer to PCI device
7866 *
7867 * Restart the card from scratch, as if from a cold-boot.
7868 */
7869static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7870{
c60fbb00 7871 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7872 pci_ers_result_t result;
7873 int err;
9a799d71 7874
9ce77666 7875 if (pci_enable_device_mem(pdev)) {
396e799c 7876 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7877 result = PCI_ERS_RESULT_DISCONNECT;
7878 } else {
7879 pci_set_master(pdev);
7880 pci_restore_state(pdev);
c0e1f68b 7881 pci_save_state(pdev);
9a799d71 7882
dd4d8ca6 7883 pci_wake_from_d3(pdev, false);
9a799d71 7884
6fabd715 7885 ixgbe_reset(adapter);
88512539 7886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7887 result = PCI_ERS_RESULT_RECOVERED;
7888 }
7889
7890 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7891 if (err) {
849c4542
ET		 7892 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7893 "failed 0x%0x\n", err);
6fabd715
PWJ		 7894 /* non-fatal, continue */
7895 }
9a799d71 7896
6fabd715 7897 return result;
9a799d71
AK		 7898}
7899
7900/**
7901 * ixgbe_io_resume - called when traffic can start flowing again.
7902 * @pdev: Pointer to PCI device
7903 *
7904 * This callback is called when the error recovery driver tells us that
7905 * its OK to resume normal operation.
7906 */
7907static void ixgbe_io_resume(struct pci_dev *pdev)
7908{
c60fbb00
AD		 7909 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7910 struct net_device *netdev = adapter->netdev;
9a799d71 7911
83c61fa9
GR		 7912#ifdef CONFIG_PCI_IOV
7913 if (adapter->vferr_refcount) {
7914 e_info(drv, "Resuming after VF err\n");
7915 adapter->vferr_refcount--;
7916 return;
7917 }
7918
7919#endif
c7ccde0f
AD		 7920 if (netif_running(netdev))
7921 ixgbe_up(adapter);
9a799d71
AK		 7922
7923 netif_device_attach(netdev);
9a799d71
AK		 7924}
7925
3646f0e5 7926static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7927 .error_detected = ixgbe_io_error_detected,
7928 .slot_reset = ixgbe_io_slot_reset,
7929 .resume = ixgbe_io_resume,
7930};
7931
7932static struct pci_driver ixgbe_driver = {
7933 .name = ixgbe_driver_name,
7934 .id_table = ixgbe_pci_tbl,
7935 .probe = ixgbe_probe,
9f9a12f8 7936 .remove = ixgbe_remove,
9a799d71
AK		 7937#ifdef CONFIG_PM
7938 .suspend = ixgbe_suspend,
7939 .resume = ixgbe_resume,
7940#endif
7941 .shutdown = ixgbe_shutdown,
da36b647 7942 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 7943 .err_handler = &ixgbe_err_handler
7944};
7945
7946/**
7947 * ixgbe_init_module - Driver Registration Routine
7948 *
7949 * ixgbe_init_module is the first routine called when the driver is
7950 * loaded. All it does is register with the PCI subsystem.
7951 **/
7952static int __init ixgbe_init_module(void)
7953{
7954 int ret;
c7689578 7955 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7956 pr_info("%s\n", ixgbe_copyright);
9a799d71 7957
00949167 7958 ixgbe_dbg_init();
00949167 7959
f01fc1a8
JK		 7960 ret = pci_register_driver(&ixgbe_driver);
7961 if (ret) {
f01fc1a8 7962 ixgbe_dbg_exit();
f01fc1a8
JK		 7963 return ret;
7964 }
7965
5dd2d332 7966#ifdef CONFIG_IXGBE_DCA
bd0362dd 7967 dca_register_notify(&dca_notifier);
bd0362dd 7968#endif
5dd2d332 7969
f01fc1a8 7970 return 0;
9a799d71 7971}
b4617240 7972
9a799d71
AK		 7973module_init(ixgbe_init_module);
7974
7975/**
7976 * ixgbe_exit_module - Driver Exit Cleanup Routine
7977 *
7978 * ixgbe_exit_module is called just before the driver is removed
7979 * from memory.
7980 **/
7981static void __exit ixgbe_exit_module(void)
7982{
5dd2d332 7983#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7984 dca_unregister_notify(&dca_notifier);
7985#endif
9a799d71 7986 pci_unregister_driver(&ixgbe_driver);
00949167 7987
00949167 7988 ixgbe_dbg_exit();
00949167 7989
1a51502b 7990 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7991}
bd0362dd 7992
5dd2d332 7993#ifdef CONFIG_IXGBE_DCA
bd0362dd 7994static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7995 void *p)
bd0362dd
JC		 7996{
7997 int ret_val;
7998
7999 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8000 __ixgbe_notify_dca);
bd0362dd
JC		 8001
8002 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8003}
b453368d 8004
5dd2d332 8005#endif /* CONFIG_IXGBE_DCA */
849c4542 8006
9a799d71
AK		 8007module_exit(ixgbe_exit_module);
8008
8009/* ixgbe_main.c */
kernel source for telekom puls (alcatel/mediatek)