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igb: Enable SR-IOV configuration via PCI sysfs interface
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
9d5c8243
AK		 60#include "igb.h"
61
200e5fd5 62#define MAJ 4
6699938b
CW		 63#define MIN 1
64#define BUILD 2
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 72
9d5c8243
AK		 73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
a3aa1884 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 119static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 121static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
53c7d064 125static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 126static void igb_configure_tx(struct igb_adapter *);
127static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 128static void igb_clean_all_tx_rings(struct igb_adapter *);
129static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 130static void igb_clean_tx_ring(struct igb_ring *);
131static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 132static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 133static void igb_update_phy_info(unsigned long);
134static void igb_watchdog(unsigned long);
135static void igb_watchdog_task(struct work_struct *);
cd392f5c 136static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
138 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 139static int igb_change_mtu(struct net_device *, int);
140static int igb_set_mac(struct net_device *, void *);
68d480c4 141static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 142static irqreturn_t igb_intr(int irq, void *);
143static irqreturn_t igb_intr_msi(int irq, void *);
144static irqreturn_t igb_msix_other(int irq, void *);
047e0030 145static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 146#ifdef CONFIG_IGB_DCA
047e0030 147static void igb_update_dca(struct igb_q_vector *);
fe4506b6 148static void igb_setup_dca(struct igb_adapter *);
421e02f0 149#endif /* CONFIG_IGB_DCA */
661086df 150static int igb_poll(struct napi_struct *, int);
13fde97a 151static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 152static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 153static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
154static void igb_tx_timeout(struct net_device *);
155static void igb_reset_task(struct work_struct *);
c8f44aff 156static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 157static int igb_vlan_rx_add_vid(struct net_device *, u16);
158static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 159static void igb_restore_vlan(struct igb_adapter *);
26ad9178 160static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 161static void igb_ping_all_vfs(struct igb_adapter *);
162static void igb_msg_task(struct igb_adapter *);
4ae196df 163static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 164static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 165static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 166static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
167static int igb_ndo_set_vf_vlan(struct net_device *netdev,
168 int vf, u16 vlan, u8 qos);
169static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
17dc566c 172static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 173
174#ifdef CONFIG_PCI_IOV
0224d663 175static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 176static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 177#endif
9d5c8243 178
9d5c8243 179#ifdef CONFIG_PM
d9dd966d 180#ifdef CONFIG_PM_SLEEP
749ab2cd 181static int igb_suspend(struct device *);
d9dd966d 182#endif
749ab2cd
YZ		 183static int igb_resume(struct device *);
184#ifdef CONFIG_PM_RUNTIME
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188#endif
189static const struct dev_pm_ops igb_pm_ops = {
190 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
191 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
192 igb_runtime_idle)
193};
9d5c8243
AK		 194#endif
195static void igb_shutdown(struct pci_dev *);
fa44f2f1 196static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 197#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 198static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
199static struct notifier_block dca_notifier = {
200 .notifier_call = igb_notify_dca,
201 .next = NULL,
202 .priority = 0
203};
204#endif
9d5c8243
AK		 205#ifdef CONFIG_NET_POLL_CONTROLLER
206/* for netdump / net console */
207static void igb_netpoll(struct net_device *);
208#endif
37680117 209#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 210static unsigned int max_vfs = 0;
211module_param(max_vfs, uint, 0);
212MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
213 "per physical function");
214#endif /* CONFIG_PCI_IOV */
215
9d5c8243
AK		 216static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
217 pci_channel_state_t);
218static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
219static void igb_io_resume(struct pci_dev *);
220
3646f0e5 221static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 222 .error_detected = igb_io_error_detected,
223 .slot_reset = igb_io_slot_reset,
224 .resume = igb_io_resume,
225};
226
b6e0c419 227static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 228
229static struct pci_driver igb_driver = {
230 .name = igb_driver_name,
231 .id_table = igb_pci_tbl,
232 .probe = igb_probe,
9f9a12f8 233 .remove = igb_remove,
9d5c8243 234#ifdef CONFIG_PM
749ab2cd 235 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 236#endif
237 .shutdown = igb_shutdown,
fa44f2f1 238 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 239 .err_handler = &igb_err_handler
240};
241
242MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
243MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
244MODULE_LICENSE("GPL");
245MODULE_VERSION(DRV_VERSION);
246
b3f4d599 247#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
248static int debug = -1;
249module_param(debug, int, 0);
250MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
251
c97ec42a
TI		 252struct igb_reg_info {
253 u32 ofs;
254 char *name;
255};
256
257static const struct igb_reg_info igb_reg_info_tbl[] = {
258
259 /* General Registers */
260 {E1000_CTRL, "CTRL"},
261 {E1000_STATUS, "STATUS"},
262 {E1000_CTRL_EXT, "CTRL_EXT"},
263
264 /* Interrupt Registers */
265 {E1000_ICR, "ICR"},
266
267 /* RX Registers */
268 {E1000_RCTL, "RCTL"},
269 {E1000_RDLEN(0), "RDLEN"},
270 {E1000_RDH(0), "RDH"},
271 {E1000_RDT(0), "RDT"},
272 {E1000_RXDCTL(0), "RXDCTL"},
273 {E1000_RDBAL(0), "RDBAL"},
274 {E1000_RDBAH(0), "RDBAH"},
275
276 /* TX Registers */
277 {E1000_TCTL, "TCTL"},
278 {E1000_TDBAL(0), "TDBAL"},
279 {E1000_TDBAH(0), "TDBAH"},
280 {E1000_TDLEN(0), "TDLEN"},
281 {E1000_TDH(0), "TDH"},
282 {E1000_TDT(0), "TDT"},
283 {E1000_TXDCTL(0), "TXDCTL"},
284 {E1000_TDFH, "TDFH"},
285 {E1000_TDFT, "TDFT"},
286 {E1000_TDFHS, "TDFHS"},
287 {E1000_TDFPC, "TDFPC"},
288
289 /* List Terminator */
290 {}
291};
292
293/*
294 * igb_regdump - register printout routine
295 */
296static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297{
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
876d2d6f 352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
c97ec42a
TI		 359}
360
361/*
362 * igb_dump - Print registers, tx-rings and rx-rings
363 */
364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 383 pr_info("Device Name state trans_start "
384 "last_rx\n");
385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
386 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 387 }
388
389 /* Print Registers */
390 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 391 pr_info(" Register Name Value\n");
c97ec42a
TI		 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
393 reginfo->name; reginfo++) {
394 igb_regdump(hw, reginfo);
395 }
396
397 /* Print TX Ring Summary */
398 if (!netdev || !netif_running(netdev))
399 goto exit;
400
401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 403 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 404 struct igb_tx_buffer *buffer_info;
c97ec42a 405 tx_ring = adapter->tx_ring[n];
06034649 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
408 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 409 (u64)dma_unmap_addr(buffer_info, dma),
410 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp);
c97ec42a
TI		 413 }
414
415 /* Print TX Rings */
416 if (!netif_msg_tx_done(adapter))
417 goto rx_ring_summary;
418
419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420
421 /* Transmit Descriptor Formats
422 *
423 * Advanced Transmit Descriptor
424 * +--------------------------------------------------------------+
425 * 0 | Buffer Address [63:0] |
426 * +--------------------------------------------------------------+
427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
428 * +--------------------------------------------------------------+
429 * 63 46 45 40 39 38 36 35 32 31 24 15 0
430 */
431
432 for (n = 0; n < adapter->num_tx_queues; n++) {
433 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 434 pr_info("------------------------------------\n");
435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
436 pr_info("------------------------------------\n");
437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
438 "[bi->dma ] leng ntw timestamp "
439 "bi->skb\n");
c97ec42a
TI		 440
441 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 442 const char *next_desc;
06034649 443 struct igb_tx_buffer *buffer_info;
60136906 444 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 445 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 446 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 447 if (i == tx_ring->next_to_use &&
448 i == tx_ring->next_to_clean)
449 next_desc = " NTC/U";
450 else if (i == tx_ring->next_to_use)
451 next_desc = " NTU";
452 else if (i == tx_ring->next_to_clean)
453 next_desc = " NTC";
454 else
455 next_desc = "";
456
457 pr_info("T [0x%03X] %016llX %016llX %016llX"
458 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 459 le64_to_cpu(u0->a),
460 le64_to_cpu(u0->b),
c9f14bf3
AD		 461 (u64)dma_unmap_addr(buffer_info, dma),
462 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 463 buffer_info->next_to_watch,
464 (u64)buffer_info->time_stamp,
876d2d6f 465 buffer_info->skb, next_desc);
c97ec42a 466
b669588a 467 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS,
b669588a 470 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 471 dma_unmap_len(buffer_info, len),
472 true);
c97ec42a
TI		 473 }
474 }
475
476 /* Print RX Rings Summary */
477rx_ring_summary:
478 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 479 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 480 for (n = 0; n < adapter->num_rx_queues; n++) {
481 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 482 pr_info(" %5d %5X %5X\n",
483 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 484 }
485
486 /* Print RX Rings */
487 if (!netif_msg_rx_status(adapter))
488 goto exit;
489
490 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
491
492 /* Advanced Receive Descriptor (Read) Format
493 * 63 1 0
494 * +-----------------------------------------------------+
495 * 0 | Packet Buffer Address [63:1] |A0/NSE|
496 * +----------------------------------------------+------+
497 * 8 | Header Buffer Address [63:1] | DD |
498 * +-----------------------------------------------------+
499 *
500 *
501 * Advanced Receive Descriptor (Write-Back) Format
502 *
503 * 63 48 47 32 31 30 21 20 17 16 4 3 0
504 * +------------------------------------------------------+
505 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
506 * | Checksum Ident | | | | Type | Type |
507 * +------------------------------------------------------+
508 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
509 * +------------------------------------------------------+
510 * 63 48 47 32 31 20 19 0
511 */
512
513 for (n = 0; n < adapter->num_rx_queues; n++) {
514 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 515 pr_info("------------------------------------\n");
516 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
517 pr_info("------------------------------------\n");
518 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
519 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
520 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
521 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 522
523 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 524 const char *next_desc;
06034649
AD		 525 struct igb_rx_buffer *buffer_info;
526 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 527 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 528 u0 = (struct my_u0 *)rx_desc;
529 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 530
531 if (i == rx_ring->next_to_use)
532 next_desc = " NTU";
533 else if (i == rx_ring->next_to_clean)
534 next_desc = " NTC";
535 else
536 next_desc = "";
537
c97ec42a
TI		 538 if (staterr & E1000_RXD_STAT_DD) {
539 /* Descriptor Done */
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
541 "RWB", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
1a1c225b 544 next_desc);
c97ec42a 545 } else {
1a1c225b
AD		 546 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
547 "R ", i,
c97ec42a
TI		 548 le64_to_cpu(u0->a),
549 le64_to_cpu(u0->b),
550 (u64)buffer_info->dma,
1a1c225b 551 next_desc);
c97ec42a 552
b669588a 553 if (netif_msg_pktdata(adapter) &&
1a1c225b 554 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 555 print_hex_dump(KERN_INFO, "",
556 DUMP_PREFIX_ADDRESS,
557 16, 1,
b669588a
ET		 558 page_address(buffer_info->page) +
559 buffer_info->page_offset,
de78d1f9 560 IGB_RX_BUFSZ, true);
c97ec42a
TI		 561 }
562 }
c97ec42a
TI		 563 }
564 }
565
566exit:
567 return;
568}
569
9d5c8243 570/**
c041076a 571 * igb_get_hw_dev - return device
9d5c8243
AK		 572 * used by hardware layer to print debugging information
573 **/
c041076a 574struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 575{
576 struct igb_adapter *adapter = hw->back;
c041076a 577 return adapter->netdev;
9d5c8243 578}
38c845c7 579
9d5c8243
AK		 580/**
581 * igb_init_module - Driver Registration Routine
582 *
583 * igb_init_module is the first routine called when the driver is
584 * loaded. All it does is register with the PCI subsystem.
585 **/
586static int __init igb_init_module(void)
587{
588 int ret;
876d2d6f 589 pr_info("%s - version %s\n",
9d5c8243
AK		 590 igb_driver_string, igb_driver_version);
591
876d2d6f 592 pr_info("%s\n", igb_copyright);
9d5c8243 593
421e02f0 594#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 595 dca_register_notify(&dca_notifier);
596#endif
bbd98fe4 597 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 598 return ret;
599}
600
601module_init(igb_init_module);
602
603/**
604 * igb_exit_module - Driver Exit Cleanup Routine
605 *
606 * igb_exit_module is called just before the driver is removed
607 * from memory.
608 **/
609static void __exit igb_exit_module(void)
610{
421e02f0 611#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 612 dca_unregister_notify(&dca_notifier);
613#endif
9d5c8243
AK		 614 pci_unregister_driver(&igb_driver);
615}
616
617module_exit(igb_exit_module);
618
26bc19ec
AD		 619#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
620/**
621 * igb_cache_ring_register - Descriptor ring to register mapping
622 * @adapter: board private structure to initialize
623 *
624 * Once we know the feature-set enabled for the device, we'll cache
625 * the register offset the descriptor ring is assigned to.
626 **/
627static void igb_cache_ring_register(struct igb_adapter *adapter)
628{
ee1b9f06 629 int i = 0, j = 0;
047e0030 630 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 631
632 switch (adapter->hw.mac.type) {
633 case e1000_82576:
634 /* The queues are allocated for virtualization such that VF 0
635 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
636 * In order to avoid collision we start at the first free queue
637 * and continue consuming queues in the same sequence
638 */
ee1b9f06 639 if (adapter->vfs_allocated_count) {
a99955fc 640 for (; i < adapter->rss_queues; i++)
3025a446
AD		 641 adapter->rx_ring[i]->reg_idx = rbase_offset +
642 Q_IDX_82576(i);
ee1b9f06 643 }
26bc19ec 644 case e1000_82575:
55cac248 645 case e1000_82580:
d2ba2ed8 646 case e1000_i350:
f96a8a0b
CW		 647 case e1000_i210:
648 case e1000_i211:
26bc19ec 649 default:
ee1b9f06 650 for (; i < adapter->num_rx_queues; i++)
3025a446 651 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 652 for (; j < adapter->num_tx_queues; j++)
3025a446 653 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 654 break;
655 }
656}
657
4be000c8
AD		 658/**
659 * igb_write_ivar - configure ivar for given MSI-X vector
660 * @hw: pointer to the HW structure
661 * @msix_vector: vector number we are allocating to a given ring
662 * @index: row index of IVAR register to write within IVAR table
663 * @offset: column offset of in IVAR, should be multiple of 8
664 *
665 * This function is intended to handle the writing of the IVAR register
666 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
667 * each containing an cause allocation for an Rx and Tx ring, and a
668 * variable number of rows depending on the number of queues supported.
669 **/
670static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
671 int index, int offset)
672{
673 u32 ivar = array_rd32(E1000_IVAR0, index);
674
675 /* clear any bits that are currently set */
676 ivar &= ~((u32)0xFF << offset);
677
678 /* write vector and valid bit */
679 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
680
681 array_wr32(E1000_IVAR0, index, ivar);
682}
683
9d5c8243 684#define IGB_N0_QUEUE -1
047e0030 685static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 686{
047e0030 687 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 688 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 689 int rx_queue = IGB_N0_QUEUE;
690 int tx_queue = IGB_N0_QUEUE;
4be000c8 691 u32 msixbm = 0;
047e0030 692
0ba82994
AD		 693 if (q_vector->rx.ring)
694 rx_queue = q_vector->rx.ring->reg_idx;
695 if (q_vector->tx.ring)
696 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 697
698 switch (hw->mac.type) {
699 case e1000_82575:
9d5c8243
AK		 700 /* The 82575 assigns vectors using a bitmask, which matches the
701 bitmask for the EICR/EIMS/EIMC registers. To assign one
702 or more queues to a vector, we write the appropriate bits
703 into the MSIXBM register for that vector. */
047e0030 704 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 705 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 706 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 707 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 708 if (!adapter->msix_entries && msix_vector == 0)
709 msixbm |= E1000_EIMS_OTHER;
9d5c8243 710 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 711 q_vector->eims_value = msixbm;
2d064c06
AD		 712 break;
713 case e1000_82576:
4be000c8
AD		 714 /*
715 * 82576 uses a table that essentially consists of 2 columns
716 * with 8 rows. The ordering is column-major so we use the
717 * lower 3 bits as the row index, and the 4th bit as the
718 * column offset.
719 */
720 if (rx_queue > IGB_N0_QUEUE)
721 igb_write_ivar(hw, msix_vector,
722 rx_queue & 0x7,
723 (rx_queue & 0x8) << 1);
724 if (tx_queue > IGB_N0_QUEUE)
725 igb_write_ivar(hw, msix_vector,
726 tx_queue & 0x7,
727 ((tx_queue & 0x8) << 1) + 8);
047e0030 728 q_vector->eims_value = 1 << msix_vector;
2d064c06 729 break;
55cac248 730 case e1000_82580:
d2ba2ed8 731 case e1000_i350:
f96a8a0b
CW		 732 case e1000_i210:
733 case e1000_i211:
4be000c8
AD		 734 /*
735 * On 82580 and newer adapters the scheme is similar to 82576
736 * however instead of ordering column-major we have things
737 * ordered row-major. So we traverse the table by using
738 * bit 0 as the column offset, and the remaining bits as the
739 * row index.
740 */
741 if (rx_queue > IGB_N0_QUEUE)
742 igb_write_ivar(hw, msix_vector,
743 rx_queue >> 1,
744 (rx_queue & 0x1) << 4);
745 if (tx_queue > IGB_N0_QUEUE)
746 igb_write_ivar(hw, msix_vector,
747 tx_queue >> 1,
748 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 749 q_vector->eims_value = 1 << msix_vector;
750 break;
2d064c06
AD		 751 default:
752 BUG();
753 break;
754 }
26b39276
AD		 755
756 /* add q_vector eims value to global eims_enable_mask */
757 adapter->eims_enable_mask |= q_vector->eims_value;
758
759 /* configure q_vector to set itr on first interrupt */
760 q_vector->set_itr = 1;
9d5c8243
AK		 761}
762
763/**
764 * igb_configure_msix - Configure MSI-X hardware
765 *
766 * igb_configure_msix sets up the hardware to properly
767 * generate MSI-X interrupts.
768 **/
769static void igb_configure_msix(struct igb_adapter *adapter)
770{
771 u32 tmp;
772 int i, vector = 0;
773 struct e1000_hw *hw = &adapter->hw;
774
775 adapter->eims_enable_mask = 0;
9d5c8243
AK		 776
777 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 778 switch (hw->mac.type) {
779 case e1000_82575:
9d5c8243
AK		 780 tmp = rd32(E1000_CTRL_EXT);
781 /* enable MSI-X PBA support*/
782 tmp |= E1000_CTRL_EXT_PBA_CLR;
783
784 /* Auto-Mask interrupts upon ICR read. */
785 tmp |= E1000_CTRL_EXT_EIAME;
786 tmp |= E1000_CTRL_EXT_IRCA;
787
788 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 789
790 /* enable msix_other interrupt */
791 array_wr32(E1000_MSIXBM(0), vector++,
792 E1000_EIMS_OTHER);
844290e5 793 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 794
2d064c06
AD		 795 break;
796
797 case e1000_82576:
55cac248 798 case e1000_82580:
d2ba2ed8 799 case e1000_i350:
f96a8a0b
CW		 800 case e1000_i210:
801 case e1000_i211:
047e0030
AD		 802 /* Turn on MSI-X capability first, or our settings
803 * won't stick. And it will take days to debug. */
804 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
805 E1000_GPIE_PBA | E1000_GPIE_EIAME |
806 E1000_GPIE_NSICR);
807
808 /* enable msix_other interrupt */
809 adapter->eims_other = 1 << vector;
2d064c06 810 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 811
047e0030 812 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 813 break;
814 default:
815 /* do nothing, since nothing else supports MSI-X */
816 break;
817 } /* switch (hw->mac.type) */
047e0030
AD		 818
819 adapter->eims_enable_mask |= adapter->eims_other;
820
26b39276
AD		 821 for (i = 0; i < adapter->num_q_vectors; i++)
822 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 823
9d5c8243
AK		 824 wrfl();
825}
826
827/**
828 * igb_request_msix - Initialize MSI-X interrupts
829 *
830 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
831 * kernel.
832 **/
833static int igb_request_msix(struct igb_adapter *adapter)
834{
835 struct net_device *netdev = adapter->netdev;
047e0030 836 struct e1000_hw *hw = &adapter->hw;
52285b76 837 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 838
047e0030 839 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 840 igb_msix_other, 0, netdev->name, adapter);
047e0030 841 if (err)
52285b76 842 goto err_out;
047e0030
AD		 843
844 for (i = 0; i < adapter->num_q_vectors; i++) {
845 struct igb_q_vector *q_vector = adapter->q_vector[i];
846
52285b76
SA		 847 vector++;
848
047e0030
AD		 849 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
850
0ba82994 851 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 852 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 853 q_vector->rx.ring->queue_index);
854 else if (q_vector->tx.ring)
047e0030 855 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 856 q_vector->tx.ring->queue_index);
857 else if (q_vector->rx.ring)
047e0030 858 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 859 q_vector->rx.ring->queue_index);
9d5c8243 860 else
047e0030
AD		 861 sprintf(q_vector->name, "%s-unused", netdev->name);
862
9d5c8243 863 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 864 igb_msix_ring, 0, q_vector->name,
047e0030 865 q_vector);
9d5c8243 866 if (err)
52285b76 867 goto err_free;
9d5c8243
AK		 868 }
869
9d5c8243
AK		 870 igb_configure_msix(adapter);
871 return 0;
52285b76
SA		 872
873err_free:
874 /* free already assigned IRQs */
875 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
876
877 vector--;
878 for (i = 0; i < vector; i++) {
879 free_irq(adapter->msix_entries[free_vector++].vector,
880 adapter->q_vector[i]);
881 }
882err_out:
9d5c8243
AK		 883 return err;
884}
885
886static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
887{
888 if (adapter->msix_entries) {
889 pci_disable_msix(adapter->pdev);
890 kfree(adapter->msix_entries);
891 adapter->msix_entries = NULL;
047e0030 892 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 893 pci_disable_msi(adapter->pdev);
047e0030 894 }
9d5c8243
AK		 895}
896
5536d210
AD		 897/**
898 * igb_free_q_vector - Free memory allocated for specific interrupt vector
899 * @adapter: board private structure to initialize
900 * @v_idx: Index of vector to be freed
901 *
902 * This function frees the memory allocated to the q_vector. In addition if
903 * NAPI is enabled it will delete any references to the NAPI struct prior
904 * to freeing the q_vector.
905 **/
906static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
907{
908 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
909
910 if (q_vector->tx.ring)
911 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
912
913 if (q_vector->rx.ring)
914 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
915
916 adapter->q_vector[v_idx] = NULL;
917 netif_napi_del(&q_vector->napi);
918
919 /*
920 * ixgbe_get_stats64() might access the rings on this vector,
921 * we must wait a grace period before freeing it.
922 */
923 kfree_rcu(q_vector, rcu);
924}
925
047e0030
AD		 926/**
927 * igb_free_q_vectors - Free memory allocated for interrupt vectors
928 * @adapter: board private structure to initialize
929 *
930 * This function frees the memory allocated to the q_vectors. In addition if
931 * NAPI is enabled it will delete any references to the NAPI struct prior
932 * to freeing the q_vector.
933 **/
934static void igb_free_q_vectors(struct igb_adapter *adapter)
935{
5536d210
AD		 936 int v_idx = adapter->num_q_vectors;
937
938 adapter->num_tx_queues = 0;
939 adapter->num_rx_queues = 0;
047e0030 940 adapter->num_q_vectors = 0;
5536d210
AD		 941
942 while (v_idx--)
943 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 944}
945
946/**
947 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
948 *
949 * This function resets the device so that it has 0 rx queues, tx queues, and
950 * MSI-X interrupts allocated.
951 */
952static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
953{
047e0030
AD		 954 igb_free_q_vectors(adapter);
955 igb_reset_interrupt_capability(adapter);
956}
9d5c8243
AK		 957
958/**
959 * igb_set_interrupt_capability - set MSI or MSI-X if supported
960 *
961 * Attempt to configure interrupts using the best available
962 * capabilities of the hardware and kernel.
963 **/
53c7d064 964static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 965{
966 int err;
967 int numvecs, i;
968
53c7d064
SA		 969 if (!msix)
970 goto msi_only;
971
83b7180d 972 /* Number of supported queues. */
a99955fc 973 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 974 if (adapter->vfs_allocated_count)
975 adapter->num_tx_queues = 1;
976 else
977 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 978
047e0030
AD		 979 /* start with one vector for every rx queue */
980 numvecs = adapter->num_rx_queues;
981
3ad2f3fb 982 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 983 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
984 numvecs += adapter->num_tx_queues;
047e0030
AD		 985
986 /* store the number of vectors reserved for queues */
987 adapter->num_q_vectors = numvecs;
988
989 /* add 1 vector for link status interrupts */
990 numvecs++;
9d5c8243
AK		 991 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
992 GFP_KERNEL);
f96a8a0b 993
9d5c8243
AK		 994 if (!adapter->msix_entries)
995 goto msi_only;
996
997 for (i = 0; i < numvecs; i++)
998 adapter->msix_entries[i].entry = i;
999
1000 err = pci_enable_msix(adapter->pdev,
1001 adapter->msix_entries,
1002 numvecs);
1003 if (err == 0)
0c2cc02e 1004 return;
9d5c8243
AK		 1005
1006 igb_reset_interrupt_capability(adapter);
1007
1008 /* If we can't do MSI-X, try MSI */
1009msi_only:
2a3abf6d
AD		 1010#ifdef CONFIG_PCI_IOV
1011 /* disable SR-IOV for non MSI-X configurations */
1012 if (adapter->vf_data) {
1013 struct e1000_hw *hw = &adapter->hw;
1014 /* disable iov and allow time for transactions to clear */
1015 pci_disable_sriov(adapter->pdev);
1016 msleep(500);
1017
1018 kfree(adapter->vf_data);
1019 adapter->vf_data = NULL;
1020 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1021 wrfl();
2a3abf6d
AD		 1022 msleep(100);
1023 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1024 }
1025#endif
4fc82adf 1026 adapter->vfs_allocated_count = 0;
a99955fc 1027 adapter->rss_queues = 1;
4fc82adf 1028 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1029 adapter->num_rx_queues = 1;
661086df 1030 adapter->num_tx_queues = 1;
047e0030 1031 adapter->num_q_vectors = 1;
9d5c8243 1032 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1033 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1034}
1035
5536d210
AD		 1036static void igb_add_ring(struct igb_ring *ring,
1037 struct igb_ring_container *head)
1038{
1039 head->ring = ring;
1040 head->count++;
1041}
1042
047e0030 1043/**
5536d210 1044 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1045 * @adapter: board private structure to initialize
5536d210
AD		 1046 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1047 * @v_idx: index of vector in adapter struct
1048 * @txr_count: total number of Tx rings to allocate
1049 * @txr_idx: index of first Tx ring to allocate
1050 * @rxr_count: total number of Rx rings to allocate
1051 * @rxr_idx: index of first Rx ring to allocate
047e0030 1052 *
5536d210 1053 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1054 **/
5536d210
AD		 1055static int igb_alloc_q_vector(struct igb_adapter *adapter,
1056 int v_count, int v_idx,
1057 int txr_count, int txr_idx,
1058 int rxr_count, int rxr_idx)
047e0030
AD		 1059{
1060 struct igb_q_vector *q_vector;
5536d210
AD		 1061 struct igb_ring *ring;
1062 int ring_count, size;
047e0030 1063
5536d210
AD		 1064 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1065 if (txr_count > 1 || rxr_count > 1)
1066 return -ENOMEM;
1067
1068 ring_count = txr_count + rxr_count;
1069 size = sizeof(struct igb_q_vector) +
1070 (sizeof(struct igb_ring) * ring_count);
1071
1072 /* allocate q_vector and rings */
1073 q_vector = kzalloc(size, GFP_KERNEL);
1074 if (!q_vector)
1075 return -ENOMEM;
1076
1077 /* initialize NAPI */
1078 netif_napi_add(adapter->netdev, &q_vector->napi,
1079 igb_poll, 64);
1080
1081 /* tie q_vector and adapter together */
1082 adapter->q_vector[v_idx] = q_vector;
1083 q_vector->adapter = adapter;
1084
1085 /* initialize work limits */
1086 q_vector->tx.work_limit = adapter->tx_work_limit;
1087
1088 /* initialize ITR configuration */
1089 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1090 q_vector->itr_val = IGB_START_ITR;
1091
1092 /* initialize pointer to rings */
1093 ring = q_vector->ring;
1094
1095 if (txr_count) {
1096 /* assign generic ring traits */
1097 ring->dev = &adapter->pdev->dev;
1098 ring->netdev = adapter->netdev;
1099
1100 /* configure backlink on ring */
1101 ring->q_vector = q_vector;
1102
1103 /* update q_vector Tx values */
1104 igb_add_ring(ring, &q_vector->tx);
1105
1106 /* For 82575, context index must be unique per ring. */
1107 if (adapter->hw.mac.type == e1000_82575)
1108 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1109
1110 /* apply Tx specific ring traits */
1111 ring->count = adapter->tx_ring_count;
1112 ring->queue_index = txr_idx;
1113
1114 /* assign ring to adapter */
1115 adapter->tx_ring[txr_idx] = ring;
1116
1117 /* push pointer to next ring */
1118 ring++;
047e0030 1119 }
81c2fc22 1120
5536d210
AD		 1121 if (rxr_count) {
1122 /* assign generic ring traits */
1123 ring->dev = &adapter->pdev->dev;
1124 ring->netdev = adapter->netdev;
047e0030 1125
5536d210
AD		 1126 /* configure backlink on ring */
1127 ring->q_vector = q_vector;
047e0030 1128
5536d210
AD		 1129 /* update q_vector Rx values */
1130 igb_add_ring(ring, &q_vector->rx);
047e0030 1131
5536d210
AD		 1132 /* set flag indicating ring supports SCTP checksum offload */
1133 if (adapter->hw.mac.type >= e1000_82576)
1134 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1135
5536d210
AD		 1136 /*
1137 * On i350, i210, and i211, loopback VLAN packets
1138 * have the tag byte-swapped.
1139 * */
1140 if (adapter->hw.mac.type >= e1000_i350)
1141 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1142
5536d210
AD		 1143 /* apply Rx specific ring traits */
1144 ring->count = adapter->rx_ring_count;
1145 ring->queue_index = rxr_idx;
1146
1147 /* assign ring to adapter */
1148 adapter->rx_ring[rxr_idx] = ring;
1149 }
1150
1151 return 0;
047e0030
AD		 1152}
1153
5536d210 1154
047e0030 1155/**
5536d210
AD		 1156 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1157 * @adapter: board private structure to initialize
047e0030 1158 *
5536d210
AD		 1159 * We allocate one q_vector per queue interrupt. If allocation fails we
1160 * return -ENOMEM.
047e0030 1161 **/
5536d210 1162static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1163{
5536d210
AD		 1164 int q_vectors = adapter->num_q_vectors;
1165 int rxr_remaining = adapter->num_rx_queues;
1166 int txr_remaining = adapter->num_tx_queues;
1167 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1168 int err;
047e0030 1169
5536d210
AD		 1170 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1171 for (; rxr_remaining; v_idx++) {
1172 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1173 0, 0, 1, rxr_idx);
047e0030 1174
5536d210
AD		 1175 if (err)
1176 goto err_out;
1177
1178 /* update counts and index */
1179 rxr_remaining--;
1180 rxr_idx++;
047e0030 1181 }
047e0030 1182 }
5536d210
AD		 1183
1184 for (; v_idx < q_vectors; v_idx++) {
1185 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1186 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1187 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1188 tqpv, txr_idx, rqpv, rxr_idx);
1189
1190 if (err)
1191 goto err_out;
1192
1193 /* update counts and index */
1194 rxr_remaining -= rqpv;
1195 txr_remaining -= tqpv;
1196 rxr_idx++;
1197 txr_idx++;
1198 }
1199
047e0030 1200 return 0;
5536d210
AD		 1201
1202err_out:
1203 adapter->num_tx_queues = 0;
1204 adapter->num_rx_queues = 0;
1205 adapter->num_q_vectors = 0;
1206
1207 while (v_idx--)
1208 igb_free_q_vector(adapter, v_idx);
1209
1210 return -ENOMEM;
047e0030
AD		 1211}
1212
1213/**
1214 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1215 *
1216 * This function initializes the interrupts and allocates all of the queues.
1217 **/
53c7d064 1218static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1219{
1220 struct pci_dev *pdev = adapter->pdev;
1221 int err;
1222
53c7d064 1223 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1224
1225 err = igb_alloc_q_vectors(adapter);
1226 if (err) {
1227 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1228 goto err_alloc_q_vectors;
1229 }
1230
5536d210 1231 igb_cache_ring_register(adapter);
047e0030
AD		 1232
1233 return 0;
5536d210 1234
047e0030
AD		 1235err_alloc_q_vectors:
1236 igb_reset_interrupt_capability(adapter);
1237 return err;
1238}
1239
9d5c8243
AK		 1240/**
1241 * igb_request_irq - initialize interrupts
1242 *
1243 * Attempts to configure interrupts using the best available
1244 * capabilities of the hardware and kernel.
1245 **/
1246static int igb_request_irq(struct igb_adapter *adapter)
1247{
1248 struct net_device *netdev = adapter->netdev;
047e0030 1249 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1250 int err = 0;
1251
1252 if (adapter->msix_entries) {
1253 err = igb_request_msix(adapter);
844290e5 1254 if (!err)
9d5c8243 1255 goto request_done;
9d5c8243 1256 /* fall back to MSI */
5536d210
AD		 1257 igb_free_all_tx_resources(adapter);
1258 igb_free_all_rx_resources(adapter);
53c7d064 1259
047e0030 1260 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1261 err = igb_init_interrupt_scheme(adapter, false);
1262 if (err)
047e0030 1263 goto request_done;
53c7d064 1264
047e0030
AD		 1265 igb_setup_all_tx_resources(adapter);
1266 igb_setup_all_rx_resources(adapter);
53c7d064 1267 igb_configure(adapter);
9d5c8243 1268 }
844290e5 1269
c74d588e
AD		 1270 igb_assign_vector(adapter->q_vector[0], 0);
1271
7dfc16fa 1272 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1273 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1274 netdev->name, adapter);
9d5c8243
AK		 1275 if (!err)
1276 goto request_done;
047e0030 1277
9d5c8243
AK		 1278 /* fall back to legacy interrupts */
1279 igb_reset_interrupt_capability(adapter);
7dfc16fa 1280 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1281 }
1282
c74d588e 1283 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1284 netdev->name, adapter);
9d5c8243 1285
6cb5e577 1286 if (err)
c74d588e 1287 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1288 err);
9d5c8243
AK		 1289
1290request_done:
1291 return err;
1292}
1293
1294static void igb_free_irq(struct igb_adapter *adapter)
1295{
9d5c8243
AK		 1296 if (adapter->msix_entries) {
1297 int vector = 0, i;
1298
047e0030 1299 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1300
0d1ae7f4 1301 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1302 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1303 adapter->q_vector[i]);
047e0030
AD		 1304 } else {
1305 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1306 }
9d5c8243
AK		 1307}
1308
1309/**
1310 * igb_irq_disable - Mask off interrupt generation on the NIC
1311 * @adapter: board private structure
1312 **/
1313static void igb_irq_disable(struct igb_adapter *adapter)
1314{
1315 struct e1000_hw *hw = &adapter->hw;
1316
25568a53
AD		 1317 /*
1318 * we need to be careful when disabling interrupts. The VFs are also
1319 * mapped into these registers and so clearing the bits can cause
1320 * issues on the VF drivers so we only need to clear what we set
1321 */
9d5c8243 1322 if (adapter->msix_entries) {
2dfd1212
AD		 1323 u32 regval = rd32(E1000_EIAM);
1324 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1325 wr32(E1000_EIMC, adapter->eims_enable_mask);
1326 regval = rd32(E1000_EIAC);
1327 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1328 }
844290e5
PW		 1329
1330 wr32(E1000_IAM, 0);
9d5c8243
AK		 1331 wr32(E1000_IMC, ~0);
1332 wrfl();
81a61859
ET		 1333 if (adapter->msix_entries) {
1334 int i;
1335 for (i = 0; i < adapter->num_q_vectors; i++)
1336 synchronize_irq(adapter->msix_entries[i].vector);
1337 } else {
1338 synchronize_irq(adapter->pdev->irq);
1339 }
9d5c8243
AK		 1340}
1341
1342/**
1343 * igb_irq_enable - Enable default interrupt generation settings
1344 * @adapter: board private structure
1345 **/
1346static void igb_irq_enable(struct igb_adapter *adapter)
1347{
1348 struct e1000_hw *hw = &adapter->hw;
1349
1350 if (adapter->msix_entries) {
06218a8d 1351 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1352 u32 regval = rd32(E1000_EIAC);
1353 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1354 regval = rd32(E1000_EIAM);
1355 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1356 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1357 if (adapter->vfs_allocated_count) {
4ae196df 1358 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1359 ims |= E1000_IMS_VMMB;
1360 }
1361 wr32(E1000_IMS, ims);
844290e5 1362 } else {
55cac248
AD		 1363 wr32(E1000_IMS, IMS_ENABLE_MASK |
1364 E1000_IMS_DRSTA);
1365 wr32(E1000_IAM, IMS_ENABLE_MASK |
1366 E1000_IMS_DRSTA);
844290e5 1367 }
9d5c8243
AK		 1368}
1369
1370static void igb_update_mng_vlan(struct igb_adapter *adapter)
1371{
51466239 1372 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1373 u16 vid = adapter->hw.mng_cookie.vlan_id;
1374 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1375
1376 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1377 /* add VID to filter table */
1378 igb_vfta_set(hw, vid, true);
1379 adapter->mng_vlan_id = vid;
1380 } else {
1381 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1382 }
1383
1384 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1385 (vid != old_vid) &&
b2cb09b1 1386 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1387 /* remove VID from filter table */
1388 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1389 }
1390}
1391
1392/**
1393 * igb_release_hw_control - release control of the h/w to f/w
1394 * @adapter: address of board private structure
1395 *
1396 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1397 * For ASF and Pass Through versions of f/w this means that the
1398 * driver is no longer loaded.
1399 *
1400 **/
1401static void igb_release_hw_control(struct igb_adapter *adapter)
1402{
1403 struct e1000_hw *hw = &adapter->hw;
1404 u32 ctrl_ext;
1405
1406 /* Let firmware take over control of h/w */
1407 ctrl_ext = rd32(E1000_CTRL_EXT);
1408 wr32(E1000_CTRL_EXT,
1409 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1410}
1411
9d5c8243
AK		 1412/**
1413 * igb_get_hw_control - get control of the h/w from f/w
1414 * @adapter: address of board private structure
1415 *
1416 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1417 * For ASF and Pass Through versions of f/w this means that
1418 * the driver is loaded.
1419 *
1420 **/
1421static void igb_get_hw_control(struct igb_adapter *adapter)
1422{
1423 struct e1000_hw *hw = &adapter->hw;
1424 u32 ctrl_ext;
1425
1426 /* Let firmware know the driver has taken over */
1427 ctrl_ext = rd32(E1000_CTRL_EXT);
1428 wr32(E1000_CTRL_EXT,
1429 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1430}
1431
9d5c8243
AK		 1432/**
1433 * igb_configure - configure the hardware for RX and TX
1434 * @adapter: private board structure
1435 **/
1436static void igb_configure(struct igb_adapter *adapter)
1437{
1438 struct net_device *netdev = adapter->netdev;
1439 int i;
1440
1441 igb_get_hw_control(adapter);
ff41f8dc 1442 igb_set_rx_mode(netdev);
9d5c8243
AK		 1443
1444 igb_restore_vlan(adapter);
9d5c8243 1445
85b430b4 1446 igb_setup_tctl(adapter);
06cf2666 1447 igb_setup_mrqc(adapter);
9d5c8243 1448 igb_setup_rctl(adapter);
85b430b4
AD		 1449
1450 igb_configure_tx(adapter);
9d5c8243 1451 igb_configure_rx(adapter);
662d7205
AD		 1452
1453 igb_rx_fifo_flush_82575(&adapter->hw);
1454
c493ea45 1455 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1456 * at least 1 descriptor unused to make sure
1457 * next_to_use != next_to_clean */
1458 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1459 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1460 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1461 }
9d5c8243
AK		 1462}
1463
88a268c1
NN		 1464/**
1465 * igb_power_up_link - Power up the phy/serdes link
1466 * @adapter: address of board private structure
1467 **/
1468void igb_power_up_link(struct igb_adapter *adapter)
1469{
76886596
AA		 1470 igb_reset_phy(&adapter->hw);
1471
88a268c1
NN		 1472 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1473 igb_power_up_phy_copper(&adapter->hw);
1474 else
1475 igb_power_up_serdes_link_82575(&adapter->hw);
1476}
1477
1478/**
1479 * igb_power_down_link - Power down the phy/serdes link
1480 * @adapter: address of board private structure
1481 */
1482static void igb_power_down_link(struct igb_adapter *adapter)
1483{
1484 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1485 igb_power_down_phy_copper_82575(&adapter->hw);
1486 else
1487 igb_shutdown_serdes_link_82575(&adapter->hw);
1488}
9d5c8243
AK		 1489
1490/**
1491 * igb_up - Open the interface and prepare it to handle traffic
1492 * @adapter: board private structure
1493 **/
9d5c8243
AK		 1494int igb_up(struct igb_adapter *adapter)
1495{
1496 struct e1000_hw *hw = &adapter->hw;
1497 int i;
1498
1499 /* hardware has been reset, we need to reload some things */
1500 igb_configure(adapter);
1501
1502 clear_bit(__IGB_DOWN, &adapter->state);
1503
0d1ae7f4
AD		 1504 for (i = 0; i < adapter->num_q_vectors; i++)
1505 napi_enable(&(adapter->q_vector[i]->napi));
1506
844290e5 1507 if (adapter->msix_entries)
9d5c8243 1508 igb_configure_msix(adapter);
feeb2721
AD		 1509 else
1510 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1511
1512 /* Clear any pending interrupts. */
1513 rd32(E1000_ICR);
1514 igb_irq_enable(adapter);
1515
d4960307
AD		 1516 /* notify VFs that reset has been completed */
1517 if (adapter->vfs_allocated_count) {
1518 u32 reg_data = rd32(E1000_CTRL_EXT);
1519 reg_data |= E1000_CTRL_EXT_PFRSTD;
1520 wr32(E1000_CTRL_EXT, reg_data);
1521 }
1522
4cb9be7a
JB		 1523 netif_tx_start_all_queues(adapter->netdev);
1524
25568a53
AD		 1525 /* start the watchdog. */
1526 hw->mac.get_link_status = 1;
1527 schedule_work(&adapter->watchdog_task);
1528
9d5c8243
AK		 1529 return 0;
1530}
1531
1532void igb_down(struct igb_adapter *adapter)
1533{
9d5c8243 1534 struct net_device *netdev = adapter->netdev;
330a6d6a 1535 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1536 u32 tctl, rctl;
1537 int i;
1538
1539 /* signal that we're down so the interrupt handler does not
1540 * reschedule our watchdog timer */
1541 set_bit(__IGB_DOWN, &adapter->state);
1542
1543 /* disable receives in the hardware */
1544 rctl = rd32(E1000_RCTL);
1545 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1546 /* flush and sleep below */
1547
fd2ea0a7 1548 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1549
1550 /* disable transmits in the hardware */
1551 tctl = rd32(E1000_TCTL);
1552 tctl &= ~E1000_TCTL_EN;
1553 wr32(E1000_TCTL, tctl);
1554 /* flush both disables and wait for them to finish */
1555 wrfl();
1556 msleep(10);
1557
0d1ae7f4
AD		 1558 for (i = 0; i < adapter->num_q_vectors; i++)
1559 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1560
9d5c8243
AK		 1561 igb_irq_disable(adapter);
1562
1563 del_timer_sync(&adapter->watchdog_timer);
1564 del_timer_sync(&adapter->phy_info_timer);
1565
9d5c8243 1566 netif_carrier_off(netdev);
04fe6358
AD		 1567
1568 /* record the stats before reset*/
12dcd86b
ED		 1569 spin_lock(&adapter->stats64_lock);
1570 igb_update_stats(adapter, &adapter->stats64);
1571 spin_unlock(&adapter->stats64_lock);
04fe6358 1572
9d5c8243
AK		 1573 adapter->link_speed = 0;
1574 adapter->link_duplex = 0;
1575
3023682e
JK		 1576 if (!pci_channel_offline(adapter->pdev))
1577 igb_reset(adapter);
9d5c8243
AK		 1578 igb_clean_all_tx_rings(adapter);
1579 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1580#ifdef CONFIG_IGB_DCA
1581
1582 /* since we reset the hardware DCA settings were cleared */
1583 igb_setup_dca(adapter);
1584#endif
9d5c8243
AK		 1585}
1586
1587void igb_reinit_locked(struct igb_adapter *adapter)
1588{
1589 WARN_ON(in_interrupt());
1590 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1591 msleep(1);
1592 igb_down(adapter);
1593 igb_up(adapter);
1594 clear_bit(__IGB_RESETTING, &adapter->state);
1595}
1596
1597void igb_reset(struct igb_adapter *adapter)
1598{
090b1795 1599 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1600 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1601 struct e1000_mac_info *mac = &hw->mac;
1602 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1603 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1604
1605 /* Repartition Pba for greater than 9k mtu
1606 * To take effect CTRL.RST is required.
1607 */
fa4dfae0 1608 switch (mac->type) {
d2ba2ed8 1609 case e1000_i350:
55cac248
AD		 1610 case e1000_82580:
1611 pba = rd32(E1000_RXPBS);
1612 pba = igb_rxpbs_adjust_82580(pba);
1613 break;
fa4dfae0 1614 case e1000_82576:
d249be54
AD		 1615 pba = rd32(E1000_RXPBS);
1616 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1617 break;
1618 case e1000_82575:
f96a8a0b
CW		 1619 case e1000_i210:
1620 case e1000_i211:
fa4dfae0
AD		 1621 default:
1622 pba = E1000_PBA_34K;
1623 break;
2d064c06 1624 }
9d5c8243 1625
2d064c06
AD		 1626 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1627 (mac->type < e1000_82576)) {
9d5c8243
AK		 1628 /* adjust PBA for jumbo frames */
1629 wr32(E1000_PBA, pba);
1630
1631 /* To maintain wire speed transmits, the Tx FIFO should be
1632 * large enough to accommodate two full transmit packets,
1633 * rounded up to the next 1KB and expressed in KB. Likewise,
1634 * the Rx FIFO should be large enough to accommodate at least
1635 * one full receive packet and is similarly rounded up and
1636 * expressed in KB. */
1637 pba = rd32(E1000_PBA);
1638 /* upper 16 bits has Tx packet buffer allocation size in KB */
1639 tx_space = pba >> 16;
1640 /* lower 16 bits has Rx packet buffer allocation size in KB */
1641 pba &= 0xffff;
1642 /* the tx fifo also stores 16 bytes of information about the tx
1643 * but don't include ethernet FCS because hardware appends it */
1644 min_tx_space = (adapter->max_frame_size +
85e8d004 1645 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1646 ETH_FCS_LEN) * 2;
1647 min_tx_space = ALIGN(min_tx_space, 1024);
1648 min_tx_space >>= 10;
1649 /* software strips receive CRC, so leave room for it */
1650 min_rx_space = adapter->max_frame_size;
1651 min_rx_space = ALIGN(min_rx_space, 1024);
1652 min_rx_space >>= 10;
1653
1654 /* If current Tx allocation is less than the min Tx FIFO size,
1655 * and the min Tx FIFO size is less than the current Rx FIFO
1656 * allocation, take space away from current Rx allocation */
1657 if (tx_space < min_tx_space &&
1658 ((min_tx_space - tx_space) < pba)) {
1659 pba = pba - (min_tx_space - tx_space);
1660
1661 /* if short on rx space, rx wins and must trump tx
1662 * adjustment */
1663 if (pba < min_rx_space)
1664 pba = min_rx_space;
1665 }
2d064c06 1666 wr32(E1000_PBA, pba);
9d5c8243 1667 }
9d5c8243
AK		 1668
1669 /* flow control settings */
1670 /* The high water mark must be low enough to fit one full frame
1671 * (or the size used for early receive) above it in the Rx FIFO.
1672 * Set it to the lower of:
1673 * - 90% of the Rx FIFO size, or
1674 * - the full Rx FIFO size minus one full frame */
1675 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1676 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1677
d48507fe 1678 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1679 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1680 fc->pause_time = 0xFFFF;
1681 fc->send_xon = 1;
0cce119a 1682 fc->current_mode = fc->requested_mode;
9d5c8243 1683
4ae196df
AD		 1684 /* disable receive for all VFs and wait one second */
1685 if (adapter->vfs_allocated_count) {
1686 int i;
1687 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1688 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1689
1690 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1691 igb_ping_all_vfs(adapter);
4ae196df
AD		 1692
1693 /* disable transmits and receives */
1694 wr32(E1000_VFRE, 0);
1695 wr32(E1000_VFTE, 0);
1696 }
1697
9d5c8243 1698 /* Allow time for pending master requests to run */
330a6d6a 1699 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1700 wr32(E1000_WUC, 0);
1701
330a6d6a 1702 if (hw->mac.ops.init_hw(hw))
090b1795 1703 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1704
a27416bb
MV		 1705 /*
1706 * Flow control settings reset on hardware reset, so guarantee flow
1707 * control is off when forcing speed.
1708 */
1709 if (!hw->mac.autoneg)
1710 igb_force_mac_fc(hw);
1711
b6e0c419 1712 igb_init_dmac(adapter, pba);
88a268c1
NN		 1713 if (!netif_running(adapter->netdev))
1714 igb_power_down_link(adapter);
1715
9d5c8243
AK		 1716 igb_update_mng_vlan(adapter);
1717
1718 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1719 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1720
1f6e8178
MV		 1721 /* Re-enable PTP, where applicable. */
1722 igb_ptp_reset(adapter);
1f6e8178 1723
330a6d6a 1724 igb_get_phy_info(hw);
9d5c8243
AK		 1725}
1726
c8f44aff
MM		 1727static netdev_features_t igb_fix_features(struct net_device *netdev,
1728 netdev_features_t features)
b2cb09b1
JP		 1729{
1730 /*
1731 * Since there is no support for separate rx/tx vlan accel
1732 * enable/disable make sure tx flag is always in same state as rx.
1733 */
1734 if (features & NETIF_F_HW_VLAN_RX)
1735 features |= NETIF_F_HW_VLAN_TX;
1736 else
1737 features &= ~NETIF_F_HW_VLAN_TX;
1738
1739 return features;
1740}
1741
c8f44aff
MM		 1742static int igb_set_features(struct net_device *netdev,
1743 netdev_features_t features)
ac52caa3 1744{
c8f44aff 1745 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1746 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1747
b2cb09b1
JP		 1748 if (changed & NETIF_F_HW_VLAN_RX)
1749 igb_vlan_mode(netdev, features);
1750
89eaefb6
BG		 1751 if (!(changed & NETIF_F_RXALL))
1752 return 0;
1753
1754 netdev->features = features;
1755
1756 if (netif_running(netdev))
1757 igb_reinit_locked(adapter);
1758 else
1759 igb_reset(adapter);
1760
ac52caa3
MM		 1761 return 0;
1762}
1763
2e5c6922 1764static const struct net_device_ops igb_netdev_ops = {
559e9c49 1765 .ndo_open = igb_open,
2e5c6922 1766 .ndo_stop = igb_close,
cd392f5c 1767 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1768 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1769 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1770 .ndo_set_mac_address = igb_set_mac,
1771 .ndo_change_mtu = igb_change_mtu,
1772 .ndo_do_ioctl = igb_ioctl,
1773 .ndo_tx_timeout = igb_tx_timeout,
1774 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1775 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1776 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1777 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1778 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1779 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1780 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1781#ifdef CONFIG_NET_POLL_CONTROLLER
1782 .ndo_poll_controller = igb_netpoll,
1783#endif
b2cb09b1
JP		 1784 .ndo_fix_features = igb_fix_features,
1785 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1786};
1787
d67974f0
CW		 1788/**
1789 * igb_set_fw_version - Configure version string for ethtool
1790 * @adapter: adapter struct
1791 *
1792 **/
1793void igb_set_fw_version(struct igb_adapter *adapter)
1794{
1795 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1796 struct e1000_fw_version fw;
1797
1798 igb_get_fw_version(hw, &fw);
1799
1800 switch (hw->mac.type) {
1801 case e1000_i211:
d67974f0 1802 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1803 "%2d.%2d-%d",
1804 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1805 break;
1806
1807 default:
1808 /* if option is rom valid, display its version too */
1809 if (fw.or_valid) {
1810 snprintf(adapter->fw_version,
1811 sizeof(adapter->fw_version),
1812 "%d.%d, 0x%08x, %d.%d.%d",
1813 fw.eep_major, fw.eep_minor, fw.etrack_id,
1814 fw.or_major, fw.or_build, fw.or_patch);
1815 /* no option rom */
1816 } else {
1817 snprintf(adapter->fw_version,
1818 sizeof(adapter->fw_version),
1819 "%d.%d, 0x%08x",
1820 fw.eep_major, fw.eep_minor, fw.etrack_id);
1821 }
1822 break;
d67974f0 1823 }
d67974f0
CW		 1824 return;
1825}
1826
9d5c8243
AK		 1827/**
1828 * igb_probe - Device Initialization Routine
1829 * @pdev: PCI device information struct
1830 * @ent: entry in igb_pci_tbl
1831 *
1832 * Returns 0 on success, negative on failure
1833 *
1834 * igb_probe initializes an adapter identified by a pci_dev structure.
1835 * The OS initialization, configuring of the adapter private structure,
1836 * and a hardware reset occur.
1837 **/
1dd06ae8 1838static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1839{
1840 struct net_device *netdev;
1841 struct igb_adapter *adapter;
1842 struct e1000_hw *hw;
4337e993 1843 u16 eeprom_data = 0;
9835fd73 1844 s32 ret_val;
4337e993 1845 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1846 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1847 unsigned long mmio_start, mmio_len;
2d6a5e95 1848 int err, pci_using_dac;
9835fd73 1849 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1850
bded64a7
AG		 1851 /* Catch broken hardware that put the wrong VF device ID in
1852 * the PCIe SR-IOV capability.
1853 */
1854 if (pdev->is_virtfn) {
1855 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1856 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1857 return -EINVAL;
1858 }
1859
aed5dec3 1860 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1861 if (err)
1862 return err;
1863
1864 pci_using_dac = 0;
59d71989 1865 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1866 if (!err) {
59d71989 1867 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1868 if (!err)
1869 pci_using_dac = 1;
1870 } else {
59d71989 1871 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1872 if (err) {
59d71989 1873 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1874 if (err) {
1875 dev_err(&pdev->dev, "No usable DMA "
1876 "configuration, aborting\n");
1877 goto err_dma;
1878 }
1879 }
1880 }
1881
aed5dec3
AD		 1882 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1883 IORESOURCE_MEM),
1884 igb_driver_name);
9d5c8243
AK		 1885 if (err)
1886 goto err_pci_reg;
1887
19d5afd4 1888 pci_enable_pcie_error_reporting(pdev);
40a914fa 1889
9d5c8243 1890 pci_set_master(pdev);
c682fc23 1891 pci_save_state(pdev);
9d5c8243
AK		 1892
1893 err = -ENOMEM;
1bfaf07b 1894 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1895 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1896 if (!netdev)
1897 goto err_alloc_etherdev;
1898
1899 SET_NETDEV_DEV(netdev, &pdev->dev);
1900
1901 pci_set_drvdata(pdev, netdev);
1902 adapter = netdev_priv(netdev);
1903 adapter->netdev = netdev;
1904 adapter->pdev = pdev;
1905 hw = &adapter->hw;
1906 hw->back = adapter;
b3f4d599 1907 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 1908
1909 mmio_start = pci_resource_start(pdev, 0);
1910 mmio_len = pci_resource_len(pdev, 0);
1911
1912 err = -EIO;
28b0759c
AD		 1913 hw->hw_addr = ioremap(mmio_start, mmio_len);
1914 if (!hw->hw_addr)
9d5c8243
AK		 1915 goto err_ioremap;
1916
2e5c6922 1917 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1918 igb_set_ethtool_ops(netdev);
9d5c8243 1919 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1920
1921 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1922
1923 netdev->mem_start = mmio_start;
1924 netdev->mem_end = mmio_start + mmio_len;
1925
9d5c8243
AK		 1926 /* PCI config space info */
1927 hw->vendor_id = pdev->vendor;
1928 hw->device_id = pdev->device;
1929 hw->revision_id = pdev->revision;
1930 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1931 hw->subsystem_device_id = pdev->subsystem_device;
1932
9d5c8243
AK		 1933 /* Copy the default MAC, PHY and NVM function pointers */
1934 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1935 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1936 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1937 /* Initialize skew-specific constants */
1938 err = ei->get_invariants(hw);
1939 if (err)
450c87c8 1940 goto err_sw_init;
9d5c8243 1941
450c87c8 1942 /* setup the private structure */
9d5c8243
AK		 1943 err = igb_sw_init(adapter);
1944 if (err)
1945 goto err_sw_init;
1946
1947 igb_get_bus_info_pcie(hw);
1948
1949 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1950
1951 /* Copper options */
1952 if (hw->phy.media_type == e1000_media_type_copper) {
1953 hw->phy.mdix = AUTO_ALL_MODES;
1954 hw->phy.disable_polarity_correction = false;
1955 hw->phy.ms_type = e1000_ms_hw_default;
1956 }
1957
1958 if (igb_check_reset_block(hw))
1959 dev_info(&pdev->dev,
1960 "PHY reset is blocked due to SOL/IDER session.\n");
1961
077887c3
AD		 1962 /*
1963 * features is initialized to 0 in allocation, it might have bits
1964 * set by igb_sw_init so we should use an or instead of an
1965 * assignment.
1966 */
1967 netdev->features |= NETIF_F_SG |
1968 NETIF_F_IP_CSUM |
1969 NETIF_F_IPV6_CSUM |
1970 NETIF_F_TSO |
1971 NETIF_F_TSO6 |
1972 NETIF_F_RXHASH |
1973 NETIF_F_RXCSUM |
1974 NETIF_F_HW_VLAN_RX |
1975 NETIF_F_HW_VLAN_TX;
1976
1977 /* copy netdev features into list of user selectable features */
1978 netdev->hw_features |= netdev->features;
89eaefb6 1979 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 1980
1981 /* set this bit last since it cannot be part of hw_features */
1982 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1983
1984 netdev->vlan_features |= NETIF_F_TSO |
1985 NETIF_F_TSO6 |
1986 NETIF_F_IP_CSUM |
1987 NETIF_F_IPV6_CSUM |
1988 NETIF_F_SG;
48f29ffc 1989
6b8f0922
BG		 1990 netdev->priv_flags |= IFF_SUPP_NOFCS;
1991
7b872a55 1992 if (pci_using_dac) {
9d5c8243 1993 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1994 netdev->vlan_features |= NETIF_F_HIGHDMA;
1995 }
9d5c8243 1996
ac52caa3
MM		 1997 if (hw->mac.type >= e1000_82576) {
1998 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1999 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2000 }
b9473560 2001
01789349
JP		 2002 netdev->priv_flags |= IFF_UNICAST_FLT;
2003
330a6d6a 2004 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2005
2006 /* before reading the NVM, reset the controller to put the device in a
2007 * known good starting state */
2008 hw->mac.ops.reset_hw(hw);
2009
f96a8a0b
CW		 2010 /*
2011 * make sure the NVM is good , i211 parts have special NVM that
2012 * doesn't contain a checksum
2013 */
2014 if (hw->mac.type != e1000_i211) {
2015 if (hw->nvm.ops.validate(hw) < 0) {
2016 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2017 err = -EIO;
2018 goto err_eeprom;
2019 }
9d5c8243
AK		 2020 }
2021
2022 /* copy the MAC address out of the NVM */
2023 if (hw->mac.ops.read_mac_addr(hw))
2024 dev_err(&pdev->dev, "NVM Read Error\n");
2025
2026 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2027
aaeb6cdf 2028 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2029 dev_err(&pdev->dev, "Invalid MAC Address\n");
2030 err = -EIO;
2031 goto err_eeprom;
2032 }
2033
d67974f0
CW		 2034 /* get firmware version for ethtool -i */
2035 igb_set_fw_version(adapter);
2036
c061b18d 2037 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2038 (unsigned long) adapter);
c061b18d 2039 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2040 (unsigned long) adapter);
9d5c8243
AK		 2041
2042 INIT_WORK(&adapter->reset_task, igb_reset_task);
2043 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2044
450c87c8 2045 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2046 adapter->fc_autoneg = true;
2047 hw->mac.autoneg = true;
2048 hw->phy.autoneg_advertised = 0x2f;
2049
0cce119a
AD		 2050 hw->fc.requested_mode = e1000_fc_default;
2051 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2052
9d5c8243
AK		 2053 igb_validate_mdi_setting(hw);
2054
63d4a8f9 2055 /* By default, support wake on port A */
a2cf8b6c 2056 if (hw->bus.func == 0)
63d4a8f9
MV		 2057 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2058
2059 /* Check the NVM for wake support on non-port A ports */
2060 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2061 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2062 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2063 &eeprom_data);
a2cf8b6c
AD		 2064 else if (hw->bus.func == 1)
2065 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2066
63d4a8f9
MV		 2067 if (eeprom_data & IGB_EEPROM_APME)
2068 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2069
2070 /* now that we have the eeprom settings, apply the special cases where
2071 * the eeprom may be wrong or the board simply won't support wake on
2072 * lan on a particular port */
2073 switch (pdev->device) {
2074 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2075 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2076 break;
2077 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2078 case E1000_DEV_ID_82576_FIBER:
2079 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2080 /* Wake events only supported on port A for dual fiber
2081 * regardless of eeprom setting */
2082 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2083 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2084 break;
c8ea5ea9 2085 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2086 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2087 /* if quad port adapter, disable WoL on all but port A */
2088 if (global_quad_port_a != 0)
63d4a8f9 2089 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2090 else
2091 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2092 /* Reset for multiple quad port adapters */
2093 if (++global_quad_port_a == 4)
2094 global_quad_port_a = 0;
2095 break;
63d4a8f9
MV		 2096 default:
2097 /* If the device can't wake, don't set software support */
2098 if (!device_can_wakeup(&adapter->pdev->dev))
2099 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2100 }
2101
2102 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2103 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2104 adapter->wol |= E1000_WUFC_MAG;
2105
2106 /* Some vendors want WoL disabled by default, but still supported */
2107 if ((hw->mac.type == e1000_i350) &&
2108 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2109 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2110 adapter->wol = 0;
2111 }
2112
2113 device_set_wakeup_enable(&adapter->pdev->dev,
2114 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2115
2116 /* reset the hardware with the new settings */
2117 igb_reset(adapter);
2118
2119 /* let the f/w know that the h/w is now under the control of the
2120 * driver. */
2121 igb_get_hw_control(adapter);
2122
9d5c8243
AK		 2123 strcpy(netdev->name, "eth%d");
2124 err = register_netdev(netdev);
2125 if (err)
2126 goto err_register;
2127
b168dfc5
JB		 2128 /* carrier off reporting is important to ethtool even BEFORE open */
2129 netif_carrier_off(netdev);
2130
421e02f0 2131#ifdef CONFIG_IGB_DCA
bbd98fe4 2132 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2133 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2134 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2135 igb_setup_dca(adapter);
2136 }
fe4506b6 2137
38c845c7 2138#endif
3c89f6d0 2139
673b8b70 2140 /* do hw tstamp init after resetting */
7ebae817 2141 igb_ptp_init(adapter);
673b8b70 2142
9d5c8243
AK		 2143 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2144 /* print bus type/speed/width info */
7c510e4b 2145 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2146 netdev->name,
559e9c49 2147 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2148 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2149 "unknown"),
59c3de89
AD		 2150 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2151 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2152 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2153 "unknown"),
7c510e4b 2154 netdev->dev_addr);
9d5c8243 2155
9835fd73
CW		 2156 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2157 if (ret_val)
2158 strcpy(part_str, "Unknown");
2159 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2160 dev_info(&pdev->dev,
2161 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2162 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2163 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2164 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2165 switch (hw->mac.type) {
2166 case e1000_i350:
f96a8a0b
CW		 2167 case e1000_i210:
2168 case e1000_i211:
09b068d4
CW		 2169 igb_set_eee_i350(hw);
2170 break;
2171 default:
2172 break;
2173 }
749ab2cd
YZ		 2174
2175 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2176 return 0;
2177
2178err_register:
2179 igb_release_hw_control(adapter);
2180err_eeprom:
2181 if (!igb_check_reset_block(hw))
f5f4cf08 2182 igb_reset_phy(hw);
9d5c8243
AK		 2183
2184 if (hw->flash_address)
2185 iounmap(hw->flash_address);
9d5c8243 2186err_sw_init:
047e0030 2187 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2188 iounmap(hw->hw_addr);
2189err_ioremap:
2190 free_netdev(netdev);
2191err_alloc_etherdev:
559e9c49
AD		 2192 pci_release_selected_regions(pdev,
2193 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2194err_pci_reg:
2195err_dma:
2196 pci_disable_device(pdev);
2197 return err;
2198}
2199
fa44f2f1
GR		 2200#ifdef CONFIG_PCI_IOV
2201static int igb_disable_sriov(struct pci_dev *pdev)
2202{
2203 struct net_device *netdev = pci_get_drvdata(pdev);
2204 struct igb_adapter *adapter = netdev_priv(netdev);
2205 struct e1000_hw *hw = &adapter->hw;
2206
2207 /* reclaim resources allocated to VFs */
2208 if (adapter->vf_data) {
2209 /* disable iov and allow time for transactions to clear */
2210 if (igb_vfs_are_assigned(adapter)) {
2211 dev_warn(&pdev->dev,
2212 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2213 return -EPERM;
2214 } else {
2215 pci_disable_sriov(pdev);
2216 msleep(500);
2217 }
2218
2219 kfree(adapter->vf_data);
2220 adapter->vf_data = NULL;
2221 adapter->vfs_allocated_count = 0;
2222 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2223 wrfl();
2224 msleep(100);
2225 dev_info(&pdev->dev, "IOV Disabled\n");
2226
2227 /* Re-enable DMA Coalescing flag since IOV is turned off */
2228 adapter->flags |= IGB_FLAG_DMAC;
2229 }
2230
2231 return 0;
2232}
2233
2234static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2235{
2236 struct net_device *netdev = pci_get_drvdata(pdev);
2237 struct igb_adapter *adapter = netdev_priv(netdev);
2238 int old_vfs = pci_num_vf(pdev);
2239 int err = 0;
2240 int i;
2241
2242 if (!num_vfs)
2243 goto out;
2244 else if (old_vfs && old_vfs == num_vfs)
2245 goto out;
2246 else if (old_vfs && old_vfs != num_vfs)
2247 err = igb_disable_sriov(pdev);
2248
2249 if (err)
2250 goto out;
2251
2252 if (num_vfs > 7) {
2253 err = -EPERM;
2254 goto out;
2255 }
2256
2257 adapter->vfs_allocated_count = num_vfs;
2258
2259 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2260 sizeof(struct vf_data_storage), GFP_KERNEL);
2261
2262 /* if allocation failed then we do not support SR-IOV */
2263 if (!adapter->vf_data) {
2264 adapter->vfs_allocated_count = 0;
2265 dev_err(&pdev->dev,
2266 "Unable to allocate memory for VF Data Storage\n");
2267 err = -ENOMEM;
2268 goto out;
2269 }
2270
2271 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2272 if (err)
2273 goto err_out;
2274
2275 dev_info(&pdev->dev, "%d VFs allocated\n",
2276 adapter->vfs_allocated_count);
2277 for (i = 0; i < adapter->vfs_allocated_count; i++)
2278 igb_vf_configure(adapter, i);
2279
2280 /* DMA Coalescing is not supported in IOV mode. */
2281 adapter->flags &= ~IGB_FLAG_DMAC;
2282 goto out;
2283
2284err_out:
2285 kfree(adapter->vf_data);
2286 adapter->vf_data = NULL;
2287 adapter->vfs_allocated_count = 0;
2288out:
2289 return err;
2290}
2291
2292#endif
9d5c8243
AK		 2293/**
2294 * igb_remove - Device Removal Routine
2295 * @pdev: PCI device information struct
2296 *
2297 * igb_remove is called by the PCI subsystem to alert the driver
2298 * that it should release a PCI device. The could be caused by a
2299 * Hot-Plug event, or because the driver is going to be removed from
2300 * memory.
2301 **/
9f9a12f8 2302static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2303{
2304 struct net_device *netdev = pci_get_drvdata(pdev);
2305 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2306 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2307
749ab2cd 2308 pm_runtime_get_noresume(&pdev->dev);
a79f4f88 2309 igb_ptp_stop(adapter);
749ab2cd 2310
760141a5
TH		 2311 /*
2312 * The watchdog timer may be rescheduled, so explicitly
2313 * disable watchdog from being rescheduled.
2314 */
9d5c8243
AK		 2315 set_bit(__IGB_DOWN, &adapter->state);
2316 del_timer_sync(&adapter->watchdog_timer);
2317 del_timer_sync(&adapter->phy_info_timer);
2318
760141a5
TH		 2319 cancel_work_sync(&adapter->reset_task);
2320 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2321
421e02f0 2322#ifdef CONFIG_IGB_DCA
7dfc16fa 2323 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2324 dev_info(&pdev->dev, "DCA disabled\n");
2325 dca_remove_requester(&pdev->dev);
7dfc16fa 2326 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2327 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2328 }
2329#endif
2330
9d5c8243
AK		 2331 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2332 * would have already happened in close and is redundant. */
2333 igb_release_hw_control(adapter);
2334
2335 unregister_netdev(netdev);
2336
047e0030 2337 igb_clear_interrupt_scheme(adapter);
9d5c8243 2338
37680117 2339#ifdef CONFIG_PCI_IOV
fa44f2f1 2340 igb_disable_sriov(pdev);
37680117 2341#endif
559e9c49 2342
28b0759c
AD		 2343 iounmap(hw->hw_addr);
2344 if (hw->flash_address)
2345 iounmap(hw->flash_address);
559e9c49
AD		 2346 pci_release_selected_regions(pdev,
2347 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2348
1128c756 2349 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2350 free_netdev(netdev);
2351
19d5afd4 2352 pci_disable_pcie_error_reporting(pdev);
40a914fa 2353
9d5c8243
AK		 2354 pci_disable_device(pdev);
2355}
2356
a6b623e0
AD		 2357/**
2358 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2359 * @adapter: board private structure to initialize
2360 *
2361 * This function initializes the vf specific data storage and then attempts to
2362 * allocate the VFs. The reason for ordering it this way is because it is much
2363 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2364 * the memory for the VFs.
2365 **/
9f9a12f8 2366static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2367{
2368#ifdef CONFIG_PCI_IOV
2369 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2370 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2371
f96a8a0b
CW		 2372 /* Virtualization features not supported on i210 family. */
2373 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2374 return;
2375
fa44f2f1
GR		 2376 igb_enable_sriov(pdev, max_vfs);
2377 pci_sriov_set_totalvfs(pdev, 7);
0224d663 2378
a6b623e0
AD		 2379#endif /* CONFIG_PCI_IOV */
2380}
2381
fa44f2f1 2382static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2383{
2384 struct e1000_hw *hw = &adapter->hw;
374a542d 2385 u32 max_rss_queues;
9d5c8243 2386
374a542d 2387 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2388 switch (hw->mac.type) {
374a542d
MV		 2389 case e1000_i211:
2390 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2391 break;
2392 case e1000_82575:
f96a8a0b 2393 case e1000_i210:
374a542d
MV		 2394 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2395 break;
2396 case e1000_i350:
2397 /* I350 cannot do RSS and SR-IOV at the same time */
2398 if (!!adapter->vfs_allocated_count) {
2399 max_rss_queues = 1;
2400 break;
2401 }
2402 /* fall through */
2403 case e1000_82576:
2404 if (!!adapter->vfs_allocated_count) {
2405 max_rss_queues = 2;
2406 break;
2407 }
2408 /* fall through */
2409 case e1000_82580:
2410 default:
2411 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2412 break;
374a542d
MV		 2413 }
2414
2415 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2416
2417 /* Determine if we need to pair queues. */
2418 switch (hw->mac.type) {
2419 case e1000_82575:
f96a8a0b 2420 case e1000_i211:
374a542d 2421 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2422 break;
374a542d
MV		 2423 case e1000_82576:
2424 /*
2425 * If VFs are going to be allocated with RSS queues then we
2426 * should pair the queues in order to conserve interrupts due
2427 * to limited supply.
2428 */
2429 if ((adapter->rss_queues > 1) &&
2430 (adapter->vfs_allocated_count > 6))
2431 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2432 /* fall through */
2433 case e1000_82580:
2434 case e1000_i350:
2435 case e1000_i210:
f96a8a0b 2436 default:
374a542d
MV		 2437 /*
2438 * If rss_queues > half of max_rss_queues, pair the queues in
2439 * order to conserve interrupts due to limited supply.
2440 */
2441 if (adapter->rss_queues > (max_rss_queues / 2))
2442 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2443 break;
2444 }
fa44f2f1
GR		 2445}
2446
2447/**
2448 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2449 * @adapter: board private structure to initialize
2450 *
2451 * igb_sw_init initializes the Adapter private data structure.
2452 * Fields are initialized based on PCI device information and
2453 * OS network device settings (MTU size).
2454 **/
2455static int igb_sw_init(struct igb_adapter *adapter)
2456{
2457 struct e1000_hw *hw = &adapter->hw;
2458 struct net_device *netdev = adapter->netdev;
2459 struct pci_dev *pdev = adapter->pdev;
2460
2461 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2462
2463 /* set default ring sizes */
2464 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2465 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2466
2467 /* set default ITR values */
2468 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2469 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2470
2471 /* set default work limits */
2472 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2473
2474 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2475 VLAN_HLEN;
2476 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2477
2478 spin_lock_init(&adapter->stats64_lock);
2479#ifdef CONFIG_PCI_IOV
2480 switch (hw->mac.type) {
2481 case e1000_82576:
2482 case e1000_i350:
2483 if (max_vfs > 7) {
2484 dev_warn(&pdev->dev,
2485 "Maximum of 7 VFs per PF, using max\n");
2486 adapter->vfs_allocated_count = 7;
2487 } else
2488 adapter->vfs_allocated_count = max_vfs;
2489 if (adapter->vfs_allocated_count)
2490 dev_warn(&pdev->dev,
2491 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2492 break;
2493 default:
2494 break;
2495 }
2496#endif /* CONFIG_PCI_IOV */
2497
2498 igb_init_queue_configuration(adapter);
a99955fc 2499
1128c756
CW		 2500 /* Setup and initialize a copy of the hw vlan table array */
2501 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2502 E1000_VLAN_FILTER_TBL_SIZE,
2503 GFP_ATOMIC);
2504
a6b623e0 2505 /* This call may decrease the number of queues */
53c7d064 2506 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2507 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2508 return -ENOMEM;
2509 }
2510
a6b623e0
AD		 2511 igb_probe_vfs(adapter);
2512
9d5c8243
AK		 2513 /* Explicitly disable IRQ since the NIC can be in any state. */
2514 igb_irq_disable(adapter);
2515
f96a8a0b 2516 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2517 adapter->flags &= ~IGB_FLAG_DMAC;
2518
9d5c8243
AK		 2519 set_bit(__IGB_DOWN, &adapter->state);
2520 return 0;
2521}
2522
2523/**
2524 * igb_open - Called when a network interface is made active
2525 * @netdev: network interface device structure
2526 *
2527 * Returns 0 on success, negative value on failure
2528 *
2529 * The open entry point is called when a network interface is made
2530 * active by the system (IFF_UP). At this point all resources needed
2531 * for transmit and receive operations are allocated, the interrupt
2532 * handler is registered with the OS, the watchdog timer is started,
2533 * and the stack is notified that the interface is ready.
2534 **/
749ab2cd 2535static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2536{
2537 struct igb_adapter *adapter = netdev_priv(netdev);
2538 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2539 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2540 int err;
2541 int i;
2542
2543 /* disallow open during test */
749ab2cd
YZ		 2544 if (test_bit(__IGB_TESTING, &adapter->state)) {
2545 WARN_ON(resuming);
9d5c8243 2546 return -EBUSY;
749ab2cd
YZ		 2547 }
2548
2549 if (!resuming)
2550 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2551
b168dfc5
JB		 2552 netif_carrier_off(netdev);
2553
9d5c8243
AK		 2554 /* allocate transmit descriptors */
2555 err = igb_setup_all_tx_resources(adapter);
2556 if (err)
2557 goto err_setup_tx;
2558
2559 /* allocate receive descriptors */
2560 err = igb_setup_all_rx_resources(adapter);
2561 if (err)
2562 goto err_setup_rx;
2563
88a268c1 2564 igb_power_up_link(adapter);
9d5c8243 2565
9d5c8243
AK		 2566 /* before we allocate an interrupt, we must be ready to handle it.
2567 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2568 * as soon as we call pci_request_irq, so we have to setup our
2569 * clean_rx handler before we do so. */
2570 igb_configure(adapter);
2571
2572 err = igb_request_irq(adapter);
2573 if (err)
2574 goto err_req_irq;
2575
0c2cc02e
AD		 2576 /* Notify the stack of the actual queue counts. */
2577 err = netif_set_real_num_tx_queues(adapter->netdev,
2578 adapter->num_tx_queues);
2579 if (err)
2580 goto err_set_queues;
2581
2582 err = netif_set_real_num_rx_queues(adapter->netdev,
2583 adapter->num_rx_queues);
2584 if (err)
2585 goto err_set_queues;
2586
9d5c8243
AK		 2587 /* From here on the code is the same as igb_up() */
2588 clear_bit(__IGB_DOWN, &adapter->state);
2589
0d1ae7f4
AD		 2590 for (i = 0; i < adapter->num_q_vectors; i++)
2591 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2592
2593 /* Clear any pending interrupts. */
2594 rd32(E1000_ICR);
844290e5
PW		 2595
2596 igb_irq_enable(adapter);
2597
d4960307
AD		 2598 /* notify VFs that reset has been completed */
2599 if (adapter->vfs_allocated_count) {
2600 u32 reg_data = rd32(E1000_CTRL_EXT);
2601 reg_data |= E1000_CTRL_EXT_PFRSTD;
2602 wr32(E1000_CTRL_EXT, reg_data);
2603 }
2604
d55b53ff
JK		 2605 netif_tx_start_all_queues(netdev);
2606
749ab2cd
YZ		 2607 if (!resuming)
2608 pm_runtime_put(&pdev->dev);
2609
25568a53
AD		 2610 /* start the watchdog. */
2611 hw->mac.get_link_status = 1;
2612 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2613
2614 return 0;
2615
0c2cc02e
AD		 2616err_set_queues:
2617 igb_free_irq(adapter);
9d5c8243
AK		 2618err_req_irq:
2619 igb_release_hw_control(adapter);
88a268c1 2620 igb_power_down_link(adapter);
9d5c8243
AK		 2621 igb_free_all_rx_resources(adapter);
2622err_setup_rx:
2623 igb_free_all_tx_resources(adapter);
2624err_setup_tx:
2625 igb_reset(adapter);
749ab2cd
YZ		 2626 if (!resuming)
2627 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2628
2629 return err;
2630}
2631
749ab2cd
YZ		 2632static int igb_open(struct net_device *netdev)
2633{
2634 return __igb_open(netdev, false);
2635}
2636
9d5c8243
AK		 2637/**
2638 * igb_close - Disables a network interface
2639 * @netdev: network interface device structure
2640 *
2641 * Returns 0, this is not allowed to fail
2642 *
2643 * The close entry point is called when an interface is de-activated
2644 * by the OS. The hardware is still under the driver's control, but
2645 * needs to be disabled. A global MAC reset is issued to stop the
2646 * hardware, and all transmit and receive resources are freed.
2647 **/
749ab2cd 2648static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2649{
2650 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2651 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2652
2653 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2654
749ab2cd
YZ		 2655 if (!suspending)
2656 pm_runtime_get_sync(&pdev->dev);
2657
2658 igb_down(adapter);
9d5c8243
AK		 2659 igb_free_irq(adapter);
2660
2661 igb_free_all_tx_resources(adapter);
2662 igb_free_all_rx_resources(adapter);
2663
749ab2cd
YZ		 2664 if (!suspending)
2665 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2666 return 0;
2667}
2668
749ab2cd
YZ		 2669static int igb_close(struct net_device *netdev)
2670{
2671 return __igb_close(netdev, false);
2672}
2673
9d5c8243
AK		 2674/**
2675 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2676 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2677 *
2678 * Return 0 on success, negative on failure
2679 **/
80785298 2680int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2681{
59d71989 2682 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2683 int size;
2684
06034649 2685 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2686
2687 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2688 if (!tx_ring->tx_buffer_info)
9d5c8243 2689 goto err;
9d5c8243
AK		 2690
2691 /* round up to nearest 4K */
85e8d004 2692 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2693 tx_ring->size = ALIGN(tx_ring->size, 4096);
2694
5536d210
AD		 2695 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2696 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2697 if (!tx_ring->desc)
2698 goto err;
2699
9d5c8243
AK		 2700 tx_ring->next_to_use = 0;
2701 tx_ring->next_to_clean = 0;
81c2fc22 2702
9d5c8243
AK		 2703 return 0;
2704
2705err:
06034649 2706 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2707 tx_ring->tx_buffer_info = NULL;
2708 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2709 return -ENOMEM;
2710}
2711
2712/**
2713 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2714 * (Descriptors) for all queues
2715 * @adapter: board private structure
2716 *
2717 * Return 0 on success, negative on failure
2718 **/
2719static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2720{
439705e1 2721 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2722 int i, err = 0;
2723
2724 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2725 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2726 if (err) {
439705e1 2727 dev_err(&pdev->dev,
9d5c8243
AK		 2728 "Allocation for Tx Queue %u failed\n", i);
2729 for (i--; i >= 0; i--)
3025a446 2730 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2731 break;
2732 }
2733 }
2734
2735 return err;
2736}
2737
2738/**
85b430b4
AD		 2739 * igb_setup_tctl - configure the transmit control registers
2740 * @adapter: Board private structure
9d5c8243 2741 **/
d7ee5b3a 2742void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2743{
9d5c8243
AK		 2744 struct e1000_hw *hw = &adapter->hw;
2745 u32 tctl;
9d5c8243 2746
85b430b4
AD		 2747 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2748 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2749
2750 /* Program the Transmit Control Register */
9d5c8243
AK		 2751 tctl = rd32(E1000_TCTL);
2752 tctl &= ~E1000_TCTL_CT;
2753 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2754 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2755
2756 igb_config_collision_dist(hw);
2757
9d5c8243
AK		 2758 /* Enable transmits */
2759 tctl |= E1000_TCTL_EN;
2760
2761 wr32(E1000_TCTL, tctl);
2762}
2763
85b430b4
AD		 2764/**
2765 * igb_configure_tx_ring - Configure transmit ring after Reset
2766 * @adapter: board private structure
2767 * @ring: tx ring to configure
2768 *
2769 * Configure a transmit ring after a reset.
2770 **/
d7ee5b3a
AD		 2771void igb_configure_tx_ring(struct igb_adapter *adapter,
2772 struct igb_ring *ring)
85b430b4
AD		 2773{
2774 struct e1000_hw *hw = &adapter->hw;
a74420e0 2775 u32 txdctl = 0;
85b430b4
AD		 2776 u64 tdba = ring->dma;
2777 int reg_idx = ring->reg_idx;
2778
2779 /* disable the queue */
a74420e0 2780 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2781 wrfl();
2782 mdelay(10);
2783
2784 wr32(E1000_TDLEN(reg_idx),
2785 ring->count * sizeof(union e1000_adv_tx_desc));
2786 wr32(E1000_TDBAL(reg_idx),
2787 tdba & 0x00000000ffffffffULL);
2788 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2789
fce99e34 2790 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2791 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2792 writel(0, ring->tail);
85b430b4
AD		 2793
2794 txdctl |= IGB_TX_PTHRESH;
2795 txdctl |= IGB_TX_HTHRESH << 8;
2796 txdctl |= IGB_TX_WTHRESH << 16;
2797
2798 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2799 wr32(E1000_TXDCTL(reg_idx), txdctl);
2800}
2801
2802/**
2803 * igb_configure_tx - Configure transmit Unit after Reset
2804 * @adapter: board private structure
2805 *
2806 * Configure the Tx unit of the MAC after a reset.
2807 **/
2808static void igb_configure_tx(struct igb_adapter *adapter)
2809{
2810 int i;
2811
2812 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2813 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2814}
2815
9d5c8243
AK		 2816/**
2817 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2818 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2819 *
2820 * Returns 0 on success, negative on failure
2821 **/
80785298 2822int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2823{
59d71989 2824 struct device *dev = rx_ring->dev;
f33005a6 2825 int size;
9d5c8243 2826
06034649 2827 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2828
2829 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2830 if (!rx_ring->rx_buffer_info)
9d5c8243 2831 goto err;
9d5c8243 2832
9d5c8243 2833 /* Round up to nearest 4K */
f33005a6 2834 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2835 rx_ring->size = ALIGN(rx_ring->size, 4096);
2836
5536d210
AD		 2837 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2838 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2839 if (!rx_ring->desc)
2840 goto err;
2841
cbc8e55f 2842 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 2843 rx_ring->next_to_clean = 0;
2844 rx_ring->next_to_use = 0;
9d5c8243 2845
9d5c8243
AK		 2846 return 0;
2847
2848err:
06034649
AD		 2849 vfree(rx_ring->rx_buffer_info);
2850 rx_ring->rx_buffer_info = NULL;
f33005a6 2851 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2852 return -ENOMEM;
2853}
2854
2855/**
2856 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2857 * (Descriptors) for all queues
2858 * @adapter: board private structure
2859 *
2860 * Return 0 on success, negative on failure
2861 **/
2862static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2863{
439705e1 2864 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2865 int i, err = 0;
2866
2867 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2868 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2869 if (err) {
439705e1 2870 dev_err(&pdev->dev,
9d5c8243
AK		 2871 "Allocation for Rx Queue %u failed\n", i);
2872 for (i--; i >= 0; i--)
3025a446 2873 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2874 break;
2875 }
2876 }
2877
2878 return err;
2879}
2880
06cf2666
AD		 2881/**
2882 * igb_setup_mrqc - configure the multiple receive queue control registers
2883 * @adapter: Board private structure
2884 **/
2885static void igb_setup_mrqc(struct igb_adapter *adapter)
2886{
2887 struct e1000_hw *hw = &adapter->hw;
2888 u32 mrqc, rxcsum;
797fd4be 2889 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 2890 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2891 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2892 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2893 0xFA01ACBE };
06cf2666
AD		 2894
2895 /* Fill out hash function seeds */
a57fe23e
AD		 2896 for (j = 0; j < 10; j++)
2897 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 2898
a99955fc 2899 num_rx_queues = adapter->rss_queues;
06cf2666 2900
797fd4be
AD		 2901 switch (hw->mac.type) {
2902 case e1000_82575:
2903 shift = 6;
2904 break;
2905 case e1000_82576:
2906 /* 82576 supports 2 RSS queues for SR-IOV */
2907 if (adapter->vfs_allocated_count) {
06cf2666
AD		 2908 shift = 3;
2909 num_rx_queues = 2;
06cf2666 2910 }
797fd4be
AD		 2911 break;
2912 default:
2913 break;
06cf2666
AD		 2914 }
2915
797fd4be
AD		 2916 /*
2917 * Populate the indirection table 4 entries at a time. To do this
2918 * we are generating the results for n and n+2 and then interleaving
2919 * those with the results with n+1 and n+3.
2920 */
2921 for (j = 0; j < 32; j++) {
2922 /* first pass generates n and n+2 */
2923 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2924 u32 reta = (base & 0x07800780) >> (7 - shift);
2925
2926 /* second pass generates n+1 and n+3 */
2927 base += 0x00010001 * num_rx_queues;
2928 reta |= (base & 0x07800780) << (1 + shift);
2929
2930 wr32(E1000_RETA(j), reta);
06cf2666
AD		 2931 }
2932
2933 /*
2934 * Disable raw packet checksumming so that RSS hash is placed in
2935 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2936 * offloads as they are enabled by default
2937 */
2938 rxcsum = rd32(E1000_RXCSUM);
2939 rxcsum |= E1000_RXCSUM_PCSD;
2940
2941 if (adapter->hw.mac.type >= e1000_82576)
2942 /* Enable Receive Checksum Offload for SCTP */
2943 rxcsum |= E1000_RXCSUM_CRCOFL;
2944
2945 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2946 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 2947
039454a8
AA		 2948 /* Generate RSS hash based on packet types, TCP/UDP
2949 * port numbers and/or IPv4/v6 src and dst addresses
2950 */
f96a8a0b
CW		 2951 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2952 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2953 E1000_MRQC_RSS_FIELD_IPV6 |
2954 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2955 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 2956
039454a8
AA		 2957 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2958 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2959 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2960 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2961
06cf2666
AD		 2962 /* If VMDq is enabled then we set the appropriate mode for that, else
2963 * we default to RSS so that an RSS hash is calculated per packet even
2964 * if we are only using one queue */
2965 if (adapter->vfs_allocated_count) {
2966 if (hw->mac.type > e1000_82575) {
2967 /* Set the default pool for the PF's first queue */
2968 u32 vtctl = rd32(E1000_VT_CTL);
2969 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2970 E1000_VT_CTL_DISABLE_DEF_POOL);
2971 vtctl |= adapter->vfs_allocated_count <<
2972 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2973 wr32(E1000_VT_CTL, vtctl);
2974 }
a99955fc 2975 if (adapter->rss_queues > 1)
f96a8a0b 2976 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 2977 else
f96a8a0b 2978 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 2979 } else {
f96a8a0b
CW		 2980 if (hw->mac.type != e1000_i211)
2981 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 2982 }
2983 igb_vmm_control(adapter);
2984
06cf2666
AD		 2985 wr32(E1000_MRQC, mrqc);
2986}
2987
9d5c8243
AK		 2988/**
2989 * igb_setup_rctl - configure the receive control registers
2990 * @adapter: Board private structure
2991 **/
d7ee5b3a 2992void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2993{
2994 struct e1000_hw *hw = &adapter->hw;
2995 u32 rctl;
9d5c8243
AK		 2996
2997 rctl = rd32(E1000_RCTL);
2998
2999 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3000 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3001
69d728ba 3002 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3003 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3004
87cb7e8c
AK		 3005 /*
3006 * enable stripping of CRC. It's unlikely this will break BMC
3007 * redirection as it did with e1000. Newer features require
3008 * that the HW strips the CRC.
73cd78f1 3009 */
87cb7e8c 3010 rctl |= E1000_RCTL_SECRC;
9d5c8243 3011
559e9c49 3012 /* disable store bad packets and clear size bits. */
ec54d7d6 3013 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3014
6ec43fe6
AD		 3015 /* enable LPE to prevent packets larger than max_frame_size */
3016 rctl |= E1000_RCTL_LPE;
9d5c8243 3017
952f72a8
AD		 3018 /* disable queue 0 to prevent tail write w/o re-config */
3019 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3020
e1739522
AD		 3021 /* Attention!!! For SR-IOV PF driver operations you must enable
3022 * queue drop for all VF and PF queues to prevent head of line blocking
3023 * if an un-trusted VF does not provide descriptors to hardware.
3024 */
3025 if (adapter->vfs_allocated_count) {
e1739522
AD		 3026 /* set all queue drop enable bits */
3027 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3028 }
3029
89eaefb6
BG		 3030 /* This is useful for sniffing bad packets. */
3031 if (adapter->netdev->features & NETIF_F_RXALL) {
3032 /* UPE and MPE will be handled by normal PROMISC logic
3033 * in e1000e_set_rx_mode */
3034 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3035 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3036 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3037
3038 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3039 E1000_RCTL_DPF | /* Allow filtered pause */
3040 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3041 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3042 * and that breaks VLANs.
3043 */
3044 }
3045
9d5c8243
AK		 3046 wr32(E1000_RCTL, rctl);
3047}
3048
7d5753f0
AD		 3049static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3050 int vfn)
3051{
3052 struct e1000_hw *hw = &adapter->hw;
3053 u32 vmolr;
3054
3055 /* if it isn't the PF check to see if VFs are enabled and
3056 * increase the size to support vlan tags */
3057 if (vfn < adapter->vfs_allocated_count &&
3058 adapter->vf_data[vfn].vlans_enabled)
3059 size += VLAN_TAG_SIZE;
3060
3061 vmolr = rd32(E1000_VMOLR(vfn));
3062 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3063 vmolr |= size | E1000_VMOLR_LPE;
3064 wr32(E1000_VMOLR(vfn), vmolr);
3065
3066 return 0;
3067}
3068
e1739522
AD		 3069/**
3070 * igb_rlpml_set - set maximum receive packet size
3071 * @adapter: board private structure
3072 *
3073 * Configure maximum receivable packet size.
3074 **/
3075static void igb_rlpml_set(struct igb_adapter *adapter)
3076{
153285f9 3077 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3078 struct e1000_hw *hw = &adapter->hw;
3079 u16 pf_id = adapter->vfs_allocated_count;
3080
e1739522
AD		 3081 if (pf_id) {
3082 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3083 /*
3084 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3085 * to our max jumbo frame size, in case we need to enable
3086 * jumbo frames on one of the rings later.
3087 * This will not pass over-length frames into the default
3088 * queue because it's gated by the VMOLR.RLPML.
3089 */
7d5753f0 3090 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3091 }
3092
3093 wr32(E1000_RLPML, max_frame_size);
3094}
3095
8151d294
WM		 3096static inline void igb_set_vmolr(struct igb_adapter *adapter,
3097 int vfn, bool aupe)
7d5753f0
AD		 3098{
3099 struct e1000_hw *hw = &adapter->hw;
3100 u32 vmolr;
3101
3102 /*
3103 * This register exists only on 82576 and newer so if we are older then
3104 * we should exit and do nothing
3105 */
3106 if (hw->mac.type < e1000_82576)
3107 return;
3108
3109 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3110 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3111 if (aupe)
3112 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3113 else
3114 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3115
3116 /* clear all bits that might not be set */
3117 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3118
a99955fc 3119 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3120 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3121 /*
3122 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3123 * multicast packets
3124 */
3125 if (vfn <= adapter->vfs_allocated_count)
3126 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3127
3128 wr32(E1000_VMOLR(vfn), vmolr);
3129}
3130
85b430b4
AD		 3131/**
3132 * igb_configure_rx_ring - Configure a receive ring after Reset
3133 * @adapter: board private structure
3134 * @ring: receive ring to be configured
3135 *
3136 * Configure the Rx unit of the MAC after a reset.
3137 **/
d7ee5b3a
AD		 3138void igb_configure_rx_ring(struct igb_adapter *adapter,
3139 struct igb_ring *ring)
85b430b4
AD		 3140{
3141 struct e1000_hw *hw = &adapter->hw;
3142 u64 rdba = ring->dma;
3143 int reg_idx = ring->reg_idx;
a74420e0 3144 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3145
3146 /* disable the queue */
a74420e0 3147 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3148
3149 /* Set DMA base address registers */
3150 wr32(E1000_RDBAL(reg_idx),
3151 rdba & 0x00000000ffffffffULL);
3152 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3153 wr32(E1000_RDLEN(reg_idx),
3154 ring->count * sizeof(union e1000_adv_rx_desc));
3155
3156 /* initialize head and tail */
fce99e34 3157 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3158 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3159 writel(0, ring->tail);
85b430b4 3160
952f72a8 3161 /* set descriptor configuration */
44390ca6 3162 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3163 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3164 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3165 if (hw->mac.type >= e1000_82580)
757b77e2 3166 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3167 /* Only set Drop Enable if we are supporting multiple queues */
3168 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3169 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3170
3171 wr32(E1000_SRRCTL(reg_idx), srrctl);
3172
7d5753f0 3173 /* set filtering for VMDQ pools */
8151d294 3174 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3175
85b430b4
AD		 3176 rxdctl |= IGB_RX_PTHRESH;
3177 rxdctl |= IGB_RX_HTHRESH << 8;
3178 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3179
3180 /* enable receive descriptor fetching */
3181 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3182 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3183}
3184
9d5c8243
AK		 3185/**
3186 * igb_configure_rx - Configure receive Unit after Reset
3187 * @adapter: board private structure
3188 *
3189 * Configure the Rx unit of the MAC after a reset.
3190 **/
3191static void igb_configure_rx(struct igb_adapter *adapter)
3192{
9107584e 3193 int i;
9d5c8243 3194
68d480c4
AD		 3195 /* set UTA to appropriate mode */
3196 igb_set_uta(adapter);
3197
26ad9178
AD		 3198 /* set the correct pool for the PF default MAC address in entry 0 */
3199 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3200 adapter->vfs_allocated_count);
3201
06cf2666
AD		 3202 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3203 * the Base and Length of the Rx Descriptor Ring */
3204 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3205 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3206}
3207
3208/**
3209 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3210 * @tx_ring: Tx descriptor ring for a specific queue
3211 *
3212 * Free all transmit software resources
3213 **/
68fd9910 3214void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3215{
3b644cf6 3216 igb_clean_tx_ring(tx_ring);
9d5c8243 3217
06034649
AD		 3218 vfree(tx_ring->tx_buffer_info);
3219 tx_ring->tx_buffer_info = NULL;
9d5c8243 3220
439705e1
AD		 3221 /* if not set, then don't free */
3222 if (!tx_ring->desc)
3223 return;
3224
59d71989
AD		 3225 dma_free_coherent(tx_ring->dev, tx_ring->size,
3226 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3227
3228 tx_ring->desc = NULL;
3229}
3230
3231/**
3232 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3233 * @adapter: board private structure
3234 *
3235 * Free all transmit software resources
3236 **/
3237static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3238{
3239 int i;
3240
3241 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3242 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3243}
3244
ebe42d16
AD		 3245void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3246 struct igb_tx_buffer *tx_buffer)
3247{
3248 if (tx_buffer->skb) {
3249 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3250 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3251 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3252 dma_unmap_addr(tx_buffer, dma),
3253 dma_unmap_len(tx_buffer, len),
ebe42d16 3254 DMA_TO_DEVICE);
c9f14bf3 3255 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3256 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3257 dma_unmap_addr(tx_buffer, dma),
3258 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3259 DMA_TO_DEVICE);
3260 }
3261 tx_buffer->next_to_watch = NULL;
3262 tx_buffer->skb = NULL;
c9f14bf3 3263 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3264 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3265}
3266
3267/**
3268 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3269 * @tx_ring: ring to be cleaned
3270 **/
3b644cf6 3271static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3272{
06034649 3273 struct igb_tx_buffer *buffer_info;
9d5c8243 3274 unsigned long size;
6ad4edfc 3275 u16 i;
9d5c8243 3276
06034649 3277 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3278 return;
3279 /* Free all the Tx ring sk_buffs */
3280
3281 for (i = 0; i < tx_ring->count; i++) {
06034649 3282 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3283 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3284 }
3285
dad8a3b3
JF		 3286 netdev_tx_reset_queue(txring_txq(tx_ring));
3287
06034649
AD		 3288 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3289 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3290
3291 /* Zero out the descriptor ring */
9d5c8243
AK		 3292 memset(tx_ring->desc, 0, tx_ring->size);
3293
3294 tx_ring->next_to_use = 0;
3295 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3296}
3297
3298/**
3299 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3300 * @adapter: board private structure
3301 **/
3302static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3303{
3304 int i;
3305
3306 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3307 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3308}
3309
3310/**
3311 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3312 * @rx_ring: ring to clean the resources from
3313 *
3314 * Free all receive software resources
3315 **/
68fd9910 3316void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3317{
3b644cf6 3318 igb_clean_rx_ring(rx_ring);
9d5c8243 3319
06034649
AD		 3320 vfree(rx_ring->rx_buffer_info);
3321 rx_ring->rx_buffer_info = NULL;
9d5c8243 3322
439705e1
AD		 3323 /* if not set, then don't free */
3324 if (!rx_ring->desc)
3325 return;
3326
59d71989
AD		 3327 dma_free_coherent(rx_ring->dev, rx_ring->size,
3328 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3329
3330 rx_ring->desc = NULL;
3331}
3332
3333/**
3334 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3335 * @adapter: board private structure
3336 *
3337 * Free all receive software resources
3338 **/
3339static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3340{
3341 int i;
3342
3343 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3344 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3345}
3346
3347/**
3348 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3349 * @rx_ring: ring to free buffers from
3350 **/
3b644cf6 3351static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3352{
9d5c8243 3353 unsigned long size;
c023cd88 3354 u16 i;
9d5c8243 3355
1a1c225b
AD		 3356 if (rx_ring->skb)
3357 dev_kfree_skb(rx_ring->skb);
3358 rx_ring->skb = NULL;
3359
06034649 3360 if (!rx_ring->rx_buffer_info)
9d5c8243 3361 return;
439705e1 3362
9d5c8243
AK		 3363 /* Free all the Rx ring sk_buffs */
3364 for (i = 0; i < rx_ring->count; i++) {
06034649 3365 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3366
cbc8e55f
AD		 3367 if (!buffer_info->page)
3368 continue;
3369
3370 dma_unmap_page(rx_ring->dev,
3371 buffer_info->dma,
3372 PAGE_SIZE,
3373 DMA_FROM_DEVICE);
3374 __free_page(buffer_info->page);
3375
1a1c225b 3376 buffer_info->page = NULL;
9d5c8243
AK		 3377 }
3378
06034649
AD		 3379 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3380 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3381
3382 /* Zero out the descriptor ring */
3383 memset(rx_ring->desc, 0, rx_ring->size);
3384
cbc8e55f 3385 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3386 rx_ring->next_to_clean = 0;
3387 rx_ring->next_to_use = 0;
9d5c8243
AK		 3388}
3389
3390/**
3391 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3392 * @adapter: board private structure
3393 **/
3394static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3395{
3396 int i;
3397
3398 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3399 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3400}
3401
3402/**
3403 * igb_set_mac - Change the Ethernet Address of the NIC
3404 * @netdev: network interface device structure
3405 * @p: pointer to an address structure
3406 *
3407 * Returns 0 on success, negative on failure
3408 **/
3409static int igb_set_mac(struct net_device *netdev, void *p)
3410{
3411 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3412 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3413 struct sockaddr *addr = p;
3414
3415 if (!is_valid_ether_addr(addr->sa_data))
3416 return -EADDRNOTAVAIL;
3417
3418 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3419 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3420
26ad9178
AD		 3421 /* set the correct pool for the new PF MAC address in entry 0 */
3422 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3423 adapter->vfs_allocated_count);
e1739522 3424
9d5c8243
AK		 3425 return 0;
3426}
3427
3428/**
68d480c4 3429 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3430 * @netdev: network interface device structure
3431 *
68d480c4
AD		 3432 * Writes multicast address list to the MTA hash table.
3433 * Returns: -ENOMEM on failure
3434 * 0 on no addresses written
3435 * X on writing X addresses to MTA
9d5c8243 3436 **/
68d480c4 3437static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3438{
3439 struct igb_adapter *adapter = netdev_priv(netdev);
3440 struct e1000_hw *hw = &adapter->hw;
22bedad3 3441 struct netdev_hw_addr *ha;
68d480c4 3442 u8 *mta_list;
9d5c8243
AK		 3443 int i;
3444
4cd24eaf 3445 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3446 /* nothing to program, so clear mc list */
3447 igb_update_mc_addr_list(hw, NULL, 0);
3448 igb_restore_vf_multicasts(adapter);
3449 return 0;
3450 }
9d5c8243 3451
4cd24eaf 3452 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3453 if (!mta_list)
3454 return -ENOMEM;
ff41f8dc 3455
68d480c4 3456 /* The shared function expects a packed array of only addresses. */
48e2f183 3457 i = 0;
22bedad3
JP		 3458 netdev_for_each_mc_addr(ha, netdev)
3459 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3460
68d480c4
AD		 3461 igb_update_mc_addr_list(hw, mta_list, i);
3462 kfree(mta_list);
3463
4cd24eaf 3464 return netdev_mc_count(netdev);
68d480c4
AD		 3465}
3466
3467/**
3468 * igb_write_uc_addr_list - write unicast addresses to RAR table
3469 * @netdev: network interface device structure
3470 *
3471 * Writes unicast address list to the RAR table.
3472 * Returns: -ENOMEM on failure/insufficient address space
3473 * 0 on no addresses written
3474 * X on writing X addresses to the RAR table
3475 **/
3476static int igb_write_uc_addr_list(struct net_device *netdev)
3477{
3478 struct igb_adapter *adapter = netdev_priv(netdev);
3479 struct e1000_hw *hw = &adapter->hw;
3480 unsigned int vfn = adapter->vfs_allocated_count;
3481 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3482 int count = 0;
3483
3484 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3485 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3486 return -ENOMEM;
9d5c8243 3487
32e7bfc4 3488 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3489 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3490
3491 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3492 if (!rar_entries)
3493 break;
26ad9178
AD		 3494 igb_rar_set_qsel(adapter, ha->addr,
3495 rar_entries--,
68d480c4
AD		 3496 vfn);
3497 count++;
ff41f8dc
AD		 3498 }
3499 }
3500 /* write the addresses in reverse order to avoid write combining */
3501 for (; rar_entries > 0 ; rar_entries--) {
3502 wr32(E1000_RAH(rar_entries), 0);
3503 wr32(E1000_RAL(rar_entries), 0);
3504 }
3505 wrfl();
3506
68d480c4
AD		 3507 return count;
3508}
3509
3510/**
3511 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3512 * @netdev: network interface device structure
3513 *
3514 * The set_rx_mode entry point is called whenever the unicast or multicast
3515 * address lists or the network interface flags are updated. This routine is
3516 * responsible for configuring the hardware for proper unicast, multicast,
3517 * promiscuous mode, and all-multi behavior.
3518 **/
3519static void igb_set_rx_mode(struct net_device *netdev)
3520{
3521 struct igb_adapter *adapter = netdev_priv(netdev);
3522 struct e1000_hw *hw = &adapter->hw;
3523 unsigned int vfn = adapter->vfs_allocated_count;
3524 u32 rctl, vmolr = 0;
3525 int count;
3526
3527 /* Check for Promiscuous and All Multicast modes */
3528 rctl = rd32(E1000_RCTL);
3529
3530 /* clear the effected bits */
3531 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3532
3533 if (netdev->flags & IFF_PROMISC) {
3534 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3535 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3536 } else {
3537 if (netdev->flags & IFF_ALLMULTI) {
3538 rctl |= E1000_RCTL_MPE;
3539 vmolr |= E1000_VMOLR_MPME;
3540 } else {
3541 /*
3542 * Write addresses to the MTA, if the attempt fails
25985edc 3543 * then we should just turn on promiscuous mode so
68d480c4
AD		 3544 * that we can at least receive multicast traffic
3545 */
3546 count = igb_write_mc_addr_list(netdev);
3547 if (count < 0) {
3548 rctl |= E1000_RCTL_MPE;
3549 vmolr |= E1000_VMOLR_MPME;
3550 } else if (count) {
3551 vmolr |= E1000_VMOLR_ROMPE;
3552 }
3553 }
3554 /*
3555 * Write addresses to available RAR registers, if there is not
3556 * sufficient space to store all the addresses then enable
25985edc 3557 * unicast promiscuous mode
68d480c4
AD		 3558 */
3559 count = igb_write_uc_addr_list(netdev);
3560 if (count < 0) {
3561 rctl |= E1000_RCTL_UPE;
3562 vmolr |= E1000_VMOLR_ROPE;
3563 }
3564 rctl |= E1000_RCTL_VFE;
28fc06f5 3565 }
68d480c4 3566 wr32(E1000_RCTL, rctl);
28fc06f5 3567
68d480c4
AD		 3568 /*
3569 * In order to support SR-IOV and eventually VMDq it is necessary to set
3570 * the VMOLR to enable the appropriate modes. Without this workaround
3571 * we will have issues with VLAN tag stripping not being done for frames
3572 * that are only arriving because we are the default pool
3573 */
f96a8a0b 3574 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3575 return;
9d5c8243 3576
68d480c4
AD		 3577 vmolr |= rd32(E1000_VMOLR(vfn)) &
3578 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3579 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3580 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3581}
3582
13800469
GR		 3583static void igb_check_wvbr(struct igb_adapter *adapter)
3584{
3585 struct e1000_hw *hw = &adapter->hw;
3586 u32 wvbr = 0;
3587
3588 switch (hw->mac.type) {
3589 case e1000_82576:
3590 case e1000_i350:
3591 if (!(wvbr = rd32(E1000_WVBR)))
3592 return;
3593 break;
3594 default:
3595 break;
3596 }
3597
3598 adapter->wvbr |= wvbr;
3599}
3600
3601#define IGB_STAGGERED_QUEUE_OFFSET 8
3602
3603static void igb_spoof_check(struct igb_adapter *adapter)
3604{
3605 int j;
3606
3607 if (!adapter->wvbr)
3608 return;
3609
3610 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3611 if (adapter->wvbr & (1 << j) ||
3612 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3613 dev_warn(&adapter->pdev->dev,
3614 "Spoof event(s) detected on VF %d\n", j);
3615 adapter->wvbr &=
3616 ~((1 << j) |
3617 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3618 }
3619 }
3620}
3621
9d5c8243
AK		 3622/* Need to wait a few seconds after link up to get diagnostic information from
3623 * the phy */
3624static void igb_update_phy_info(unsigned long data)
3625{
3626 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3627 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3628}
3629
4d6b725e
AD		 3630/**
3631 * igb_has_link - check shared code for link and determine up/down
3632 * @adapter: pointer to driver private info
3633 **/
3145535a 3634bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3635{
3636 struct e1000_hw *hw = &adapter->hw;
3637 bool link_active = false;
3638 s32 ret_val = 0;
3639
3640 /* get_link_status is set on LSC (link status) interrupt or
3641 * rx sequence error interrupt. get_link_status will stay
3642 * false until the e1000_check_for_link establishes link
3643 * for copper adapters ONLY
3644 */
3645 switch (hw->phy.media_type) {
3646 case e1000_media_type_copper:
3647 if (hw->mac.get_link_status) {
3648 ret_val = hw->mac.ops.check_for_link(hw);
3649 link_active = !hw->mac.get_link_status;
3650 } else {
3651 link_active = true;
3652 }
3653 break;
4d6b725e
AD		 3654 case e1000_media_type_internal_serdes:
3655 ret_val = hw->mac.ops.check_for_link(hw);
3656 link_active = hw->mac.serdes_has_link;
3657 break;
3658 default:
3659 case e1000_media_type_unknown:
3660 break;
3661 }
3662
3663 return link_active;
3664}
3665
563988dc
SA		 3666static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3667{
3668 bool ret = false;
3669 u32 ctrl_ext, thstat;
3670
f96a8a0b 3671 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3672 if (hw->mac.type == e1000_i350) {
3673 thstat = rd32(E1000_THSTAT);
3674 ctrl_ext = rd32(E1000_CTRL_EXT);
3675
3676 if ((hw->phy.media_type == e1000_media_type_copper) &&
3677 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3678 ret = !!(thstat & event);
3679 }
3680 }
3681
3682 return ret;
3683}
3684
9d5c8243
AK		 3685/**
3686 * igb_watchdog - Timer Call-back
3687 * @data: pointer to adapter cast into an unsigned long
3688 **/
3689static void igb_watchdog(unsigned long data)
3690{
3691 struct igb_adapter *adapter = (struct igb_adapter *)data;
3692 /* Do the rest outside of interrupt context */
3693 schedule_work(&adapter->watchdog_task);
3694}
3695
3696static void igb_watchdog_task(struct work_struct *work)
3697{
3698 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3699 struct igb_adapter,
3700 watchdog_task);
9d5c8243 3701 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3702 struct net_device *netdev = adapter->netdev;
563988dc 3703 u32 link;
7a6ea550 3704 int i;
9d5c8243 3705
4d6b725e 3706 link = igb_has_link(adapter);
9d5c8243 3707 if (link) {
749ab2cd
YZ		 3708 /* Cancel scheduled suspend requests. */
3709 pm_runtime_resume(netdev->dev.parent);
3710
9d5c8243
AK		 3711 if (!netif_carrier_ok(netdev)) {
3712 u32 ctrl;
330a6d6a
AD		 3713 hw->mac.ops.get_speed_and_duplex(hw,
3714 &adapter->link_speed,
3715 &adapter->link_duplex);
9d5c8243
AK		 3716
3717 ctrl = rd32(E1000_CTRL);
527d47c1 3718 /* Links status message must follow this format */
876d2d6f
JK		 3719 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3720 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3721 netdev->name,
3722 adapter->link_speed,
3723 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3724 "Full" : "Half",
3725 (ctrl & E1000_CTRL_TFCE) &&
3726 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3727 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3728 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3729
563988dc 3730 /* check for thermal sensor event */
876d2d6f
JK		 3731 if (igb_thermal_sensor_event(hw,
3732 E1000_THSTAT_LINK_THROTTLE)) {
3733 netdev_info(netdev, "The network adapter link "
3734 "speed was downshifted because it "
3735 "overheated\n");
7ef5ed1c 3736 }
563988dc 3737
d07f3e37 3738 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3739 adapter->tx_timeout_factor = 1;
3740 switch (adapter->link_speed) {
3741 case SPEED_10:
9d5c8243
AK		 3742 adapter->tx_timeout_factor = 14;
3743 break;
3744 case SPEED_100:
9d5c8243
AK		 3745 /* maybe add some timeout factor ? */
3746 break;
3747 }
3748
3749 netif_carrier_on(netdev);
9d5c8243 3750
4ae196df 3751 igb_ping_all_vfs(adapter);
17dc566c 3752 igb_check_vf_rate_limit(adapter);
4ae196df 3753
4b1a9877 3754 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3755 if (!test_bit(__IGB_DOWN, &adapter->state))
3756 mod_timer(&adapter->phy_info_timer,
3757 round_jiffies(jiffies + 2 * HZ));
3758 }
3759 } else {
3760 if (netif_carrier_ok(netdev)) {
3761 adapter->link_speed = 0;
3762 adapter->link_duplex = 0;
563988dc
SA		 3763
3764 /* check for thermal sensor event */
876d2d6f
JK		 3765 if (igb_thermal_sensor_event(hw,
3766 E1000_THSTAT_PWR_DOWN)) {
3767 netdev_err(netdev, "The network adapter was "
3768 "stopped because it overheated\n");
7ef5ed1c 3769 }
563988dc 3770
527d47c1
AD		 3771 /* Links status message must follow this format */
3772 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3773 netdev->name);
9d5c8243 3774 netif_carrier_off(netdev);
4b1a9877 3775
4ae196df
AD		 3776 igb_ping_all_vfs(adapter);
3777
4b1a9877 3778 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3779 if (!test_bit(__IGB_DOWN, &adapter->state))
3780 mod_timer(&adapter->phy_info_timer,
3781 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3782
3783 pm_schedule_suspend(netdev->dev.parent,
3784 MSEC_PER_SEC * 5);
9d5c8243
AK		 3785 }
3786 }
3787
12dcd86b
ED		 3788 spin_lock(&adapter->stats64_lock);
3789 igb_update_stats(adapter, &adapter->stats64);
3790 spin_unlock(&adapter->stats64_lock);
9d5c8243 3791
dbabb065 3792 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3793 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3794 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3795 /* We've lost link, so the controller stops DMA,
3796 * but we've got queued Tx work that's never going
3797 * to get done, so reset controller to flush Tx.
3798 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3799 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3800 adapter->tx_timeout_count++;
3801 schedule_work(&adapter->reset_task);
3802 /* return immediately since reset is imminent */
3803 return;
3804 }
9d5c8243 3805 }
9d5c8243 3806
dbabb065 3807 /* Force detection of hung controller every watchdog period */
6d095fa8 3808 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3809 }
f7ba205e 3810
9d5c8243 3811 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3812 if (adapter->msix_entries) {
047e0030 3813 u32 eics = 0;
0d1ae7f4
AD		 3814 for (i = 0; i < adapter->num_q_vectors; i++)
3815 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3816 wr32(E1000_EICS, eics);
3817 } else {
3818 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3819 }
9d5c8243 3820
13800469
GR		 3821 igb_spoof_check(adapter);
3822
9d5c8243
AK		 3823 /* Reset the timer */
3824 if (!test_bit(__IGB_DOWN, &adapter->state))
3825 mod_timer(&adapter->watchdog_timer,
3826 round_jiffies(jiffies + 2 * HZ));
3827}
3828
3829enum latency_range {
3830 lowest_latency = 0,
3831 low_latency = 1,
3832 bulk_latency = 2,
3833 latency_invalid = 255
3834};
3835
6eb5a7f1
AD		 3836/**
3837 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3838 *
3839 * Stores a new ITR value based on strictly on packet size. This
3840 * algorithm is less sophisticated than that used in igb_update_itr,
3841 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3842 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3843 * were determined based on theoretical maximum wire speed and testing
3844 * data, in order to minimize response time while increasing bulk
3845 * throughput.
3846 * This functionality is controlled by the InterruptThrottleRate module
3847 * parameter (see igb_param.c)
3848 * NOTE: This function is called only when operating in a multiqueue
3849 * receive environment.
047e0030 3850 * @q_vector: pointer to q_vector
6eb5a7f1 3851 **/
047e0030 3852static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3853{
047e0030 3854 int new_val = q_vector->itr_val;
6eb5a7f1 3855 int avg_wire_size = 0;
047e0030 3856 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3857 unsigned int packets;
9d5c8243 3858
6eb5a7f1
AD		 3859 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3860 * ints/sec - ITR timer value of 120 ticks.
3861 */
3862 if (adapter->link_speed != SPEED_1000) {
0ba82994 3863 new_val = IGB_4K_ITR;
6eb5a7f1 3864 goto set_itr_val;
9d5c8243 3865 }
047e0030 3866
0ba82994
AD		 3867 packets = q_vector->rx.total_packets;
3868 if (packets)
3869 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3870
0ba82994
AD		 3871 packets = q_vector->tx.total_packets;
3872 if (packets)
3873 avg_wire_size = max_t(u32, avg_wire_size,
3874 q_vector->tx.total_bytes / packets);
047e0030
AD		 3875
3876 /* if avg_wire_size isn't set no work was done */
3877 if (!avg_wire_size)
3878 goto clear_counts;
9d5c8243 3879
6eb5a7f1
AD		 3880 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3881 avg_wire_size += 24;
3882
3883 /* Don't starve jumbo frames */
3884 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3885
6eb5a7f1
AD		 3886 /* Give a little boost to mid-size frames */
3887 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3888 new_val = avg_wire_size / 3;
3889 else
3890 new_val = avg_wire_size / 2;
9d5c8243 3891
0ba82994
AD		 3892 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3893 if (new_val < IGB_20K_ITR &&
3894 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3895 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3896 new_val = IGB_20K_ITR;
abe1c363 3897
6eb5a7f1 3898set_itr_val:
047e0030
AD		 3899 if (new_val != q_vector->itr_val) {
3900 q_vector->itr_val = new_val;
3901 q_vector->set_itr = 1;
9d5c8243 3902 }
6eb5a7f1 3903clear_counts:
0ba82994
AD		 3904 q_vector->rx.total_bytes = 0;
3905 q_vector->rx.total_packets = 0;
3906 q_vector->tx.total_bytes = 0;
3907 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3908}
3909
3910/**
3911 * igb_update_itr - update the dynamic ITR value based on statistics
3912 * Stores a new ITR value based on packets and byte
3913 * counts during the last interrupt. The advantage of per interrupt
3914 * computation is faster updates and more accurate ITR for the current
3915 * traffic pattern. Constants in this function were computed
3916 * based on theoretical maximum wire speed and thresholds were set based
3917 * on testing data as well as attempting to minimize response time
3918 * while increasing bulk throughput.
3919 * this functionality is controlled by the InterruptThrottleRate module
3920 * parameter (see igb_param.c)
3921 * NOTE: These calculations are only valid when operating in a single-
3922 * queue environment.
0ba82994
AD		 3923 * @q_vector: pointer to q_vector
3924 * @ring_container: ring info to update the itr for
9d5c8243 3925 **/
0ba82994
AD		 3926static void igb_update_itr(struct igb_q_vector *q_vector,
3927 struct igb_ring_container *ring_container)
9d5c8243 3928{
0ba82994
AD		 3929 unsigned int packets = ring_container->total_packets;
3930 unsigned int bytes = ring_container->total_bytes;
3931 u8 itrval = ring_container->itr;
9d5c8243 3932
0ba82994 3933 /* no packets, exit with status unchanged */
9d5c8243 3934 if (packets == 0)
0ba82994 3935 return;
9d5c8243 3936
0ba82994 3937 switch (itrval) {
9d5c8243
AK		 3938 case lowest_latency:
3939 /* handle TSO and jumbo frames */
3940 if (bytes/packets > 8000)
0ba82994 3941 itrval = bulk_latency;
9d5c8243 3942 else if ((packets < 5) && (bytes > 512))
0ba82994 3943 itrval = low_latency;
9d5c8243
AK		 3944 break;
3945 case low_latency: /* 50 usec aka 20000 ints/s */
3946 if (bytes > 10000) {
3947 /* this if handles the TSO accounting */
3948 if (bytes/packets > 8000) {
0ba82994 3949 itrval = bulk_latency;
9d5c8243 3950 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3951 itrval = bulk_latency;
9d5c8243 3952 } else if ((packets > 35)) {
0ba82994 3953 itrval = lowest_latency;
9d5c8243
AK		 3954 }
3955 } else if (bytes/packets > 2000) {
0ba82994 3956 itrval = bulk_latency;
9d5c8243 3957 } else if (packets <= 2 && bytes < 512) {
0ba82994 3958 itrval = lowest_latency;
9d5c8243
AK		 3959 }
3960 break;
3961 case bulk_latency: /* 250 usec aka 4000 ints/s */
3962 if (bytes > 25000) {
3963 if (packets > 35)
0ba82994 3964 itrval = low_latency;
1e5c3d21 3965 } else if (bytes < 1500) {
0ba82994 3966 itrval = low_latency;
9d5c8243
AK		 3967 }
3968 break;
3969 }
3970
0ba82994
AD		 3971 /* clear work counters since we have the values we need */
3972 ring_container->total_bytes = 0;
3973 ring_container->total_packets = 0;
3974
3975 /* write updated itr to ring container */
3976 ring_container->itr = itrval;
9d5c8243
AK		 3977}
3978
0ba82994 3979static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3980{
0ba82994 3981 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3982 u32 new_itr = q_vector->itr_val;
0ba82994 3983 u8 current_itr = 0;
9d5c8243
AK		 3984
3985 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3986 if (adapter->link_speed != SPEED_1000) {
3987 current_itr = 0;
0ba82994 3988 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3989 goto set_itr_now;
3990 }
3991
0ba82994
AD		 3992 igb_update_itr(q_vector, &q_vector->tx);
3993 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3994
0ba82994 3995 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3996
6eb5a7f1 3997 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3998 if (current_itr == lowest_latency &&
3999 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4000 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4001 current_itr = low_latency;
4002
9d5c8243
AK		 4003 switch (current_itr) {
4004 /* counts and packets in update_itr are dependent on these numbers */
4005 case lowest_latency:
0ba82994 4006 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4007 break;
4008 case low_latency:
0ba82994 4009 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4010 break;
4011 case bulk_latency:
0ba82994 4012 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4013 break;
4014 default:
4015 break;
4016 }
4017
4018set_itr_now:
047e0030 4019 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4020 /* this attempts to bias the interrupt rate towards Bulk
4021 * by adding intermediate steps when interrupt rate is
4022 * increasing */
047e0030
AD		 4023 new_itr = new_itr > q_vector->itr_val ?
4024 max((new_itr * q_vector->itr_val) /
4025 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 4026 new_itr) :
9d5c8243
AK		 4027 new_itr;
4028 /* Don't write the value here; it resets the adapter's
4029 * internal timer, and causes us to delay far longer than
4030 * we should between interrupts. Instead, we write the ITR
4031 * value at the beginning of the next interrupt so the timing
4032 * ends up being correct.
4033 */
047e0030
AD		 4034 q_vector->itr_val = new_itr;
4035 q_vector->set_itr = 1;
9d5c8243 4036 }
9d5c8243
AK		 4037}
4038
c50b52a0
SH		 4039static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4040 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4041{
4042 struct e1000_adv_tx_context_desc *context_desc;
4043 u16 i = tx_ring->next_to_use;
4044
4045 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4046
4047 i++;
4048 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4049
4050 /* set bits to identify this as an advanced context descriptor */
4051 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4052
4053 /* For 82575, context index must be unique per ring. */
866cff06 4054 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4055 mss_l4len_idx |= tx_ring->reg_idx << 4;
4056
4057 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4058 context_desc->seqnum_seed = 0;
4059 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4060 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4061}
4062
7af40ad9
AD		 4063static int igb_tso(struct igb_ring *tx_ring,
4064 struct igb_tx_buffer *first,
4065 u8 *hdr_len)
9d5c8243 4066{
7af40ad9 4067 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4068 u32 vlan_macip_lens, type_tucmd;
4069 u32 mss_l4len_idx, l4len;
4070
ed6aa105
AD		 4071 if (skb->ip_summed != CHECKSUM_PARTIAL)
4072 return 0;
4073
7d13a7d0
AD		 4074 if (!skb_is_gso(skb))
4075 return 0;
9d5c8243
AK		 4076
4077 if (skb_header_cloned(skb)) {
7af40ad9 4078 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4079 if (err)
4080 return err;
4081 }
4082
7d13a7d0
AD		 4083 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4084 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4085
7af40ad9 4086 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4087 struct iphdr *iph = ip_hdr(skb);
4088 iph->tot_len = 0;
4089 iph->check = 0;
4090 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4091 iph->daddr, 0,
4092 IPPROTO_TCP,
4093 0);
7d13a7d0 4094 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4095 first->tx_flags |= IGB_TX_FLAGS_TSO |
4096 IGB_TX_FLAGS_CSUM |
4097 IGB_TX_FLAGS_IPV4;
8e1e8a47 4098 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4099 ipv6_hdr(skb)->payload_len = 0;
4100 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4101 &ipv6_hdr(skb)->daddr,
4102 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4103 first->tx_flags |= IGB_TX_FLAGS_TSO |
4104 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4105 }
4106
7af40ad9 4107 /* compute header lengths */
7d13a7d0
AD		 4108 l4len = tcp_hdrlen(skb);
4109 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4110
7af40ad9
AD		 4111 /* update gso size and bytecount with header size */
4112 first->gso_segs = skb_shinfo(skb)->gso_segs;
4113 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4114
9d5c8243 4115 /* MSS L4LEN IDX */
7d13a7d0
AD		 4116 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4117 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4118
7d13a7d0
AD		 4119 /* VLAN MACLEN IPLEN */
4120 vlan_macip_lens = skb_network_header_len(skb);
4121 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4122 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4123
7d13a7d0 4124 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4125
7d13a7d0 4126 return 1;
9d5c8243
AK		 4127}
4128
7af40ad9 4129static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4130{
7af40ad9 4131 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4132 u32 vlan_macip_lens = 0;
4133 u32 mss_l4len_idx = 0;
4134 u32 type_tucmd = 0;
9d5c8243 4135
7d13a7d0 4136 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4137 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4138 return;
7d13a7d0
AD		 4139 } else {
4140 u8 l4_hdr = 0;
7af40ad9 4141 switch (first->protocol) {
7d13a7d0
AD		 4142 case __constant_htons(ETH_P_IP):
4143 vlan_macip_lens |= skb_network_header_len(skb);
4144 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4145 l4_hdr = ip_hdr(skb)->protocol;
4146 break;
4147 case __constant_htons(ETH_P_IPV6):
4148 vlan_macip_lens |= skb_network_header_len(skb);
4149 l4_hdr = ipv6_hdr(skb)->nexthdr;
4150 break;
4151 default:
4152 if (unlikely(net_ratelimit())) {
4153 dev_warn(tx_ring->dev,
4154 "partial checksum but proto=%x!\n",
7af40ad9 4155 first->protocol);
fa4a7ef3 4156 }
7d13a7d0
AD		 4157 break;
4158 }
fa4a7ef3 4159
7d13a7d0
AD		 4160 switch (l4_hdr) {
4161 case IPPROTO_TCP:
4162 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4163 mss_l4len_idx = tcp_hdrlen(skb) <<
4164 E1000_ADVTXD_L4LEN_SHIFT;
4165 break;
4166 case IPPROTO_SCTP:
4167 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4168 mss_l4len_idx = sizeof(struct sctphdr) <<
4169 E1000_ADVTXD_L4LEN_SHIFT;
4170 break;
4171 case IPPROTO_UDP:
4172 mss_l4len_idx = sizeof(struct udphdr) <<
4173 E1000_ADVTXD_L4LEN_SHIFT;
4174 break;
4175 default:
4176 if (unlikely(net_ratelimit())) {
4177 dev_warn(tx_ring->dev,
4178 "partial checksum but l4 proto=%x!\n",
4179 l4_hdr);
44b0cda3 4180 }
7d13a7d0 4181 break;
9d5c8243 4182 }
7af40ad9
AD		 4183
4184 /* update TX checksum flag */
4185 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4186 }
9d5c8243 4187
7d13a7d0 4188 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4189 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4190
7d13a7d0 4191 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4192}
4193
1d9daf45
AD		 4194#define IGB_SET_FLAG(_input, _flag, _result) \
4195 ((_flag <= _result) ? \
4196 ((u32)(_input & _flag) * (_result / _flag)) : \
4197 ((u32)(_input & _flag) / (_flag / _result)))
4198
4199static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4200{
4201 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4202 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4203 E1000_ADVTXD_DCMD_DEXT |
4204 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4205
4206 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4207 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4208 (E1000_ADVTXD_DCMD_VLE));
4209
4210 /* set segmentation bits for TSO */
4211 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4212 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4213
4214 /* set timestamp bit if present */
1d9daf45
AD		 4215 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4216 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4217
1d9daf45
AD		 4218 /* insert frame checksum */
4219 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4220
4221 return cmd_type;
4222}
4223
7af40ad9
AD		 4224static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4225 union e1000_adv_tx_desc *tx_desc,
4226 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4227{
4228 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4229
1d9daf45
AD		 4230 /* 82575 requires a unique index per ring */
4231 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4232 olinfo_status |= tx_ring->reg_idx << 4;
4233
4234 /* insert L4 checksum */
1d9daf45
AD		 4235 olinfo_status |= IGB_SET_FLAG(tx_flags,
4236 IGB_TX_FLAGS_CSUM,
4237 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4238
1d9daf45
AD		 4239 /* insert IPv4 checksum */
4240 olinfo_status |= IGB_SET_FLAG(tx_flags,
4241 IGB_TX_FLAGS_IPV4,
4242 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4243
7af40ad9 4244 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4245}
4246
ebe42d16
AD		 4247/*
4248 * The largest size we can write to the descriptor is 65535. In order to
4249 * maintain a power of two alignment we have to limit ourselves to 32K.
4250 */
4251#define IGB_MAX_TXD_PWR 15
7af40ad9 4252#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4253
7af40ad9
AD		 4254static void igb_tx_map(struct igb_ring *tx_ring,
4255 struct igb_tx_buffer *first,
ebe42d16 4256 const u8 hdr_len)
9d5c8243 4257{
7af40ad9 4258 struct sk_buff *skb = first->skb;
c9f14bf3 4259 struct igb_tx_buffer *tx_buffer;
ebe42d16 4260 union e1000_adv_tx_desc *tx_desc;
80d0759e 4261 struct skb_frag_struct *frag;
ebe42d16 4262 dma_addr_t dma;
80d0759e 4263 unsigned int data_len, size;
7af40ad9 4264 u32 tx_flags = first->tx_flags;
1d9daf45 4265 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4266 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4267
4268 tx_desc = IGB_TX_DESC(tx_ring, i);
4269
80d0759e
AD		 4270 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4271
4272 size = skb_headlen(skb);
4273 data_len = skb->data_len;
ebe42d16
AD		 4274
4275 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4276
80d0759e
AD		 4277 tx_buffer = first;
4278
4279 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4280 if (dma_mapping_error(tx_ring->dev, dma))
4281 goto dma_error;
4282
4283 /* record length, and DMA address */
4284 dma_unmap_len_set(tx_buffer, len, size);
4285 dma_unmap_addr_set(tx_buffer, dma, dma);
4286
4287 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4288
ebe42d16
AD		 4289 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4290 tx_desc->read.cmd_type_len =
1d9daf45 4291 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4292
4293 i++;
4294 tx_desc++;
4295 if (i == tx_ring->count) {
4296 tx_desc = IGB_TX_DESC(tx_ring, 0);
4297 i = 0;
4298 }
80d0759e 4299 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4300
4301 dma += IGB_MAX_DATA_PER_TXD;
4302 size -= IGB_MAX_DATA_PER_TXD;
4303
ebe42d16
AD		 4304 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4305 }
4306
4307 if (likely(!data_len))
4308 break;
2bbfebe2 4309
1d9daf45 4310 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4311
65689fef 4312 i++;
ebe42d16
AD		 4313 tx_desc++;
4314 if (i == tx_ring->count) {
4315 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4316 i = 0;
ebe42d16 4317 }
80d0759e 4318 tx_desc->read.olinfo_status = 0;
65689fef 4319
9e903e08 4320 size = skb_frag_size(frag);
ebe42d16
AD		 4321 data_len -= size;
4322
4323 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4324 size, DMA_TO_DEVICE);
6366ad33 4325
c9f14bf3 4326 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4327 }
4328
ebe42d16 4329 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4330 cmd_type |= size | IGB_TXD_DCMD;
4331 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4332
80d0759e
AD		 4333 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4334
8542db05
AD		 4335 /* set the timestamp */
4336 first->time_stamp = jiffies;
4337
ebe42d16
AD		 4338 /*
4339 * Force memory writes to complete before letting h/w know there
4340 * are new descriptors to fetch. (Only applicable for weak-ordered
4341 * memory model archs, such as IA-64).
4342 *
4343 * We also need this memory barrier to make certain all of the
4344 * status bits have been updated before next_to_watch is written.
4345 */
4346 wmb();
4347
8542db05 4348 /* set next_to_watch value indicating a packet is present */
ebe42d16 4349 first->next_to_watch = tx_desc;
9d5c8243 4350
ebe42d16
AD		 4351 i++;
4352 if (i == tx_ring->count)
4353 i = 0;
6366ad33 4354
ebe42d16 4355 tx_ring->next_to_use = i;
6366ad33 4356
ebe42d16 4357 writel(i, tx_ring->tail);
6366ad33 4358
ebe42d16
AD		 4359 /* we need this if more than one processor can write to our tail
4360 * at a time, it syncronizes IO on IA64/Altix systems */
4361 mmiowb();
4362
4363 return;
4364
4365dma_error:
4366 dev_err(tx_ring->dev, "TX DMA map failed\n");
4367
4368 /* clear dma mappings for failed tx_buffer_info map */
4369 for (;;) {
c9f14bf3
AD		 4370 tx_buffer = &tx_ring->tx_buffer_info[i];
4371 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4372 if (tx_buffer == first)
ebe42d16 4373 break;
a77ff709
NN		 4374 if (i == 0)
4375 i = tx_ring->count;
6366ad33 4376 i--;
6366ad33
AD		 4377 }
4378
9d5c8243 4379 tx_ring->next_to_use = i;
9d5c8243
AK		 4380}
4381
6ad4edfc 4382static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4383{
e694e964
AD		 4384 struct net_device *netdev = tx_ring->netdev;
4385
661086df 4386 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4387
9d5c8243
AK		 4388 /* Herbert's original patch had:
4389 * smp_mb__after_netif_stop_queue();
4390 * but since that doesn't exist yet, just open code it. */
4391 smp_mb();
4392
4393 /* We need to check again in a case another CPU has just
4394 * made room available. */
c493ea45 4395 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4396 return -EBUSY;
4397
4398 /* A reprieve! */
661086df 4399 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4400
4401 u64_stats_update_begin(&tx_ring->tx_syncp2);
4402 tx_ring->tx_stats.restart_queue2++;
4403 u64_stats_update_end(&tx_ring->tx_syncp2);
4404
9d5c8243
AK		 4405 return 0;
4406}
4407
6ad4edfc 4408static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4409{
c493ea45 4410 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4411 return 0;
e694e964 4412 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4413}
4414
cd392f5c
AD		 4415netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4416 struct igb_ring *tx_ring)
9d5c8243 4417{
1f6e8178 4418 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4419 struct igb_tx_buffer *first;
ebe42d16 4420 int tso;
91d4ee33 4421 u32 tx_flags = 0;
31f6adbb 4422 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4423 u8 hdr_len = 0;
9d5c8243 4424
9d5c8243
AK		 4425 /* need: 1 descriptor per page,
4426 * + 2 desc gap to keep tail from touching head,
4427 * + 1 desc for skb->data,
4428 * + 1 desc for context descriptor,
4429 * otherwise try next time */
e694e964 4430 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4431 /* this is a hard error */
9d5c8243
AK		 4432 return NETDEV_TX_BUSY;
4433 }
33af6bcc 4434
7af40ad9
AD		 4435 /* record the location of the first descriptor for this packet */
4436 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4437 first->skb = skb;
4438 first->bytecount = skb->len;
4439 first->gso_segs = 1;
4440
1f6e8178
MV		 4441 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4442 !(adapter->ptp_tx_skb))) {
2244d07b 4443 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4444 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4445
4446 adapter->ptp_tx_skb = skb_get(skb);
4447 if (adapter->hw.mac.type == e1000_82576)
4448 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4449 }
9d5c8243 4450
eab6d18d 4451 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4452 tx_flags |= IGB_TX_FLAGS_VLAN;
4453 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4454 }
4455
7af40ad9
AD		 4456 /* record initial flags and protocol */
4457 first->tx_flags = tx_flags;
4458 first->protocol = protocol;
cdfd01fc 4459
7af40ad9
AD		 4460 tso = igb_tso(tx_ring, first, &hdr_len);
4461 if (tso < 0)
7d13a7d0 4462 goto out_drop;
7af40ad9
AD		 4463 else if (!tso)
4464 igb_tx_csum(tx_ring, first);
9d5c8243 4465
7af40ad9 4466 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4467
4468 /* Make sure there is space in the ring for the next send. */
e694e964 4469 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4470
9d5c8243 4471 return NETDEV_TX_OK;
7d13a7d0
AD		 4472
4473out_drop:
7af40ad9
AD		 4474 igb_unmap_and_free_tx_resource(tx_ring, first);
4475
7d13a7d0 4476 return NETDEV_TX_OK;
9d5c8243
AK		 4477}
4478
1cc3bd87
AD		 4479static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4480 struct sk_buff *skb)
4481{
4482 unsigned int r_idx = skb->queue_mapping;
4483
4484 if (r_idx >= adapter->num_tx_queues)
4485 r_idx = r_idx % adapter->num_tx_queues;
4486
4487 return adapter->tx_ring[r_idx];
4488}
4489
cd392f5c
AD		 4490static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4491 struct net_device *netdev)
9d5c8243
AK		 4492{
4493 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4494
4495 if (test_bit(__IGB_DOWN, &adapter->state)) {
4496 dev_kfree_skb_any(skb);
4497 return NETDEV_TX_OK;
4498 }
4499
4500 if (skb->len <= 0) {
4501 dev_kfree_skb_any(skb);
4502 return NETDEV_TX_OK;
4503 }
4504
1cc3bd87
AD		 4505 /*
4506 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4507 * in order to meet this minimum size requirement.
4508 */
ea5ceeab
TD		 4509 if (unlikely(skb->len < 17)) {
4510 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4511 return NETDEV_TX_OK;
4512 skb->len = 17;
ea5ceeab 4513 skb_set_tail_pointer(skb, 17);
1cc3bd87 4514 }
9d5c8243 4515
1cc3bd87 4516 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4517}
4518
4519/**
4520 * igb_tx_timeout - Respond to a Tx Hang
4521 * @netdev: network interface device structure
4522 **/
4523static void igb_tx_timeout(struct net_device *netdev)
4524{
4525 struct igb_adapter *adapter = netdev_priv(netdev);
4526 struct e1000_hw *hw = &adapter->hw;
4527
4528 /* Do the reset outside of interrupt context */
4529 adapter->tx_timeout_count++;
f7ba205e 4530
06218a8d 4531 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4532 hw->dev_spec._82575.global_device_reset = true;
4533
9d5c8243 4534 schedule_work(&adapter->reset_task);
265de409
AD		 4535 wr32(E1000_EICS,
4536 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4537}
4538
4539static void igb_reset_task(struct work_struct *work)
4540{
4541 struct igb_adapter *adapter;
4542 adapter = container_of(work, struct igb_adapter, reset_task);
4543
c97ec42a
TI		 4544 igb_dump(adapter);
4545 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4546 igb_reinit_locked(adapter);
4547}
4548
4549/**
12dcd86b 4550 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4551 * @netdev: network interface device structure
12dcd86b 4552 * @stats: rtnl_link_stats64 pointer
9d5c8243 4553 *
9d5c8243 4554 **/
12dcd86b
ED		 4555static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4556 struct rtnl_link_stats64 *stats)
9d5c8243 4557{
12dcd86b
ED		 4558 struct igb_adapter *adapter = netdev_priv(netdev);
4559
4560 spin_lock(&adapter->stats64_lock);
4561 igb_update_stats(adapter, &adapter->stats64);
4562 memcpy(stats, &adapter->stats64, sizeof(*stats));
4563 spin_unlock(&adapter->stats64_lock);
4564
4565 return stats;
9d5c8243
AK		 4566}
4567
4568/**
4569 * igb_change_mtu - Change the Maximum Transfer Unit
4570 * @netdev: network interface device structure
4571 * @new_mtu: new value for maximum frame size
4572 *
4573 * Returns 0 on success, negative on failure
4574 **/
4575static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4576{
4577 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4578 struct pci_dev *pdev = adapter->pdev;
153285f9 4579 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4580
c809d227 4581 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4582 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4583 return -EINVAL;
4584 }
4585
153285f9 4586#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4587 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4588 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4589 return -EINVAL;
4590 }
4591
4592 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4593 msleep(1);
73cd78f1 4594
9d5c8243
AK		 4595 /* igb_down has a dependency on max_frame_size */
4596 adapter->max_frame_size = max_frame;
559e9c49 4597
4c844851
AD		 4598 if (netif_running(netdev))
4599 igb_down(adapter);
9d5c8243 4600
090b1795 4601 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4602 netdev->mtu, new_mtu);
4603 netdev->mtu = new_mtu;
4604
4605 if (netif_running(netdev))
4606 igb_up(adapter);
4607 else
4608 igb_reset(adapter);
4609
4610 clear_bit(__IGB_RESETTING, &adapter->state);
4611
4612 return 0;
4613}
4614
4615/**
4616 * igb_update_stats - Update the board statistics counters
4617 * @adapter: board private structure
4618 **/
4619
12dcd86b
ED		 4620void igb_update_stats(struct igb_adapter *adapter,
4621 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4622{
4623 struct e1000_hw *hw = &adapter->hw;
4624 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4625 u32 reg, mpc;
9d5c8243 4626 u16 phy_tmp;
3f9c0164
AD		 4627 int i;
4628 u64 bytes, packets;
12dcd86b
ED		 4629 unsigned int start;
4630 u64 _bytes, _packets;
9d5c8243
AK		 4631
4632#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4633
4634 /*
4635 * Prevent stats update while adapter is being reset, or if the pci
4636 * connection is down.
4637 */
4638 if (adapter->link_speed == 0)
4639 return;
4640 if (pci_channel_offline(pdev))
4641 return;
4642
3f9c0164
AD		 4643 bytes = 0;
4644 packets = 0;
4645 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4646 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4647 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4648
ae1c07a6
AD		 4649 if (rqdpc) {
4650 ring->rx_stats.drops += rqdpc;
4651 net_stats->rx_fifo_errors += rqdpc;
4652 }
12dcd86b
ED		 4653
4654 do {
4655 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4656 _bytes = ring->rx_stats.bytes;
4657 _packets = ring->rx_stats.packets;
4658 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4659 bytes += _bytes;
4660 packets += _packets;
3f9c0164
AD		 4661 }
4662
128e45eb
AD		 4663 net_stats->rx_bytes = bytes;
4664 net_stats->rx_packets = packets;
3f9c0164
AD		 4665
4666 bytes = 0;
4667 packets = 0;
4668 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4669 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4670 do {
4671 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4672 _bytes = ring->tx_stats.bytes;
4673 _packets = ring->tx_stats.packets;
4674 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4675 bytes += _bytes;
4676 packets += _packets;
3f9c0164 4677 }
128e45eb
AD		 4678 net_stats->tx_bytes = bytes;
4679 net_stats->tx_packets = packets;
3f9c0164
AD		 4680
4681 /* read stats registers */
9d5c8243
AK		 4682 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4683 adapter->stats.gprc += rd32(E1000_GPRC);
4684 adapter->stats.gorc += rd32(E1000_GORCL);
4685 rd32(E1000_GORCH); /* clear GORCL */
4686 adapter->stats.bprc += rd32(E1000_BPRC);
4687 adapter->stats.mprc += rd32(E1000_MPRC);
4688 adapter->stats.roc += rd32(E1000_ROC);
4689
4690 adapter->stats.prc64 += rd32(E1000_PRC64);
4691 adapter->stats.prc127 += rd32(E1000_PRC127);
4692 adapter->stats.prc255 += rd32(E1000_PRC255);
4693 adapter->stats.prc511 += rd32(E1000_PRC511);
4694 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4695 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4696 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4697 adapter->stats.sec += rd32(E1000_SEC);
4698
fa3d9a6d
MW		 4699 mpc = rd32(E1000_MPC);
4700 adapter->stats.mpc += mpc;
4701 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4702 adapter->stats.scc += rd32(E1000_SCC);
4703 adapter->stats.ecol += rd32(E1000_ECOL);
4704 adapter->stats.mcc += rd32(E1000_MCC);
4705 adapter->stats.latecol += rd32(E1000_LATECOL);
4706 adapter->stats.dc += rd32(E1000_DC);
4707 adapter->stats.rlec += rd32(E1000_RLEC);
4708 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4709 adapter->stats.xontxc += rd32(E1000_XONTXC);
4710 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4711 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4712 adapter->stats.fcruc += rd32(E1000_FCRUC);
4713 adapter->stats.gptc += rd32(E1000_GPTC);
4714 adapter->stats.gotc += rd32(E1000_GOTCL);
4715 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4716 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4717 adapter->stats.ruc += rd32(E1000_RUC);
4718 adapter->stats.rfc += rd32(E1000_RFC);
4719 adapter->stats.rjc += rd32(E1000_RJC);
4720 adapter->stats.tor += rd32(E1000_TORH);
4721 adapter->stats.tot += rd32(E1000_TOTH);
4722 adapter->stats.tpr += rd32(E1000_TPR);
4723
4724 adapter->stats.ptc64 += rd32(E1000_PTC64);
4725 adapter->stats.ptc127 += rd32(E1000_PTC127);
4726 adapter->stats.ptc255 += rd32(E1000_PTC255);
4727 adapter->stats.ptc511 += rd32(E1000_PTC511);
4728 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4729 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4730
4731 adapter->stats.mptc += rd32(E1000_MPTC);
4732 adapter->stats.bptc += rd32(E1000_BPTC);
4733
2d0b0f69
NN		 4734 adapter->stats.tpt += rd32(E1000_TPT);
4735 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4736
4737 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4738 /* read internal phy specific stats */
4739 reg = rd32(E1000_CTRL_EXT);
4740 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4741 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4742
4743 /* this stat has invalid values on i210/i211 */
4744 if ((hw->mac.type != e1000_i210) &&
4745 (hw->mac.type != e1000_i211))
4746 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4747 }
4748
9d5c8243
AK		 4749 adapter->stats.tsctc += rd32(E1000_TSCTC);
4750 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4751
4752 adapter->stats.iac += rd32(E1000_IAC);
4753 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4754 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4755 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4756 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4757 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4758 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4759 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4760 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4761
4762 /* Fill out the OS statistics structure */
128e45eb
AD		 4763 net_stats->multicast = adapter->stats.mprc;
4764 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4765
4766 /* Rx Errors */
4767
4768 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4769 * our own version based on RUC and ROC */
128e45eb 4770 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4771 adapter->stats.crcerrs + adapter->stats.algnerrc +
4772 adapter->stats.ruc + adapter->stats.roc +
4773 adapter->stats.cexterr;
128e45eb
AD		 4774 net_stats->rx_length_errors = adapter->stats.ruc +
4775 adapter->stats.roc;
4776 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4777 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4778 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4779
4780 /* Tx Errors */
128e45eb
AD		 4781 net_stats->tx_errors = adapter->stats.ecol +
4782 adapter->stats.latecol;
4783 net_stats->tx_aborted_errors = adapter->stats.ecol;
4784 net_stats->tx_window_errors = adapter->stats.latecol;
4785 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4786
4787 /* Tx Dropped needs to be maintained elsewhere */
4788
4789 /* Phy Stats */
4790 if (hw->phy.media_type == e1000_media_type_copper) {
4791 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4792 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4793 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4794 adapter->phy_stats.idle_errors += phy_tmp;
4795 }
4796 }
4797
4798 /* Management Stats */
4799 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4800 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4801 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4802
4803 /* OS2BMC Stats */
4804 reg = rd32(E1000_MANC);
4805 if (reg & E1000_MANC_EN_BMC2OS) {
4806 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4807 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4808 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4809 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4810 }
9d5c8243
AK		 4811}
4812
9d5c8243
AK		 4813static irqreturn_t igb_msix_other(int irq, void *data)
4814{
047e0030 4815 struct igb_adapter *adapter = data;
9d5c8243 4816 struct e1000_hw *hw = &adapter->hw;
844290e5 4817 u32 icr = rd32(E1000_ICR);
844290e5 4818 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4819
7f081d40
AD		 4820 if (icr & E1000_ICR_DRSTA)
4821 schedule_work(&adapter->reset_task);
4822
047e0030 4823 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4824 /* HW is reporting DMA is out of sync */
4825 adapter->stats.doosync++;
13800469
GR		 4826 /* The DMA Out of Sync is also indication of a spoof event
4827 * in IOV mode. Check the Wrong VM Behavior register to
4828 * see if it is really a spoof event. */
4829 igb_check_wvbr(adapter);
dda0e083 4830 }
eebbbdba 4831
4ae196df
AD		 4832 /* Check for a mailbox event */
4833 if (icr & E1000_ICR_VMMB)
4834 igb_msg_task(adapter);
4835
4836 if (icr & E1000_ICR_LSC) {
4837 hw->mac.get_link_status = 1;
4838 /* guard against interrupt when we're going down */
4839 if (!test_bit(__IGB_DOWN, &adapter->state))
4840 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4841 }
4842
1f6e8178
MV		 4843 if (icr & E1000_ICR_TS) {
4844 u32 tsicr = rd32(E1000_TSICR);
4845
4846 if (tsicr & E1000_TSICR_TXTS) {
4847 /* acknowledge the interrupt */
4848 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4849 /* retrieve hardware timestamp */
4850 schedule_work(&adapter->ptp_tx_work);
4851 }
4852 }
1f6e8178 4853
844290e5 4854 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4855
4856 return IRQ_HANDLED;
4857}
4858
047e0030 4859static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4860{
26b39276 4861 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4862 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4863
047e0030
AD		 4864 if (!q_vector->set_itr)
4865 return;
73cd78f1 4866
047e0030
AD		 4867 if (!itr_val)
4868 itr_val = 0x4;
661086df 4869
26b39276
AD		 4870 if (adapter->hw.mac.type == e1000_82575)
4871 itr_val |= itr_val << 16;
661086df 4872 else
0ba82994 4873 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4874
047e0030
AD		 4875 writel(itr_val, q_vector->itr_register);
4876 q_vector->set_itr = 0;
6eb5a7f1
AD		 4877}
4878
047e0030 4879static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4880{
047e0030 4881 struct igb_q_vector *q_vector = data;
9d5c8243 4882
047e0030
AD		 4883 /* Write the ITR value calculated from the previous interrupt. */
4884 igb_write_itr(q_vector);
9d5c8243 4885
047e0030 4886 napi_schedule(&q_vector->napi);
844290e5 4887
047e0030 4888 return IRQ_HANDLED;
fe4506b6
JC		 4889}
4890
421e02f0 4891#ifdef CONFIG_IGB_DCA
6a05004a
AD		 4892static void igb_update_tx_dca(struct igb_adapter *adapter,
4893 struct igb_ring *tx_ring,
4894 int cpu)
4895{
4896 struct e1000_hw *hw = &adapter->hw;
4897 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4898
4899 if (hw->mac.type != e1000_82575)
4900 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4901
4902 /*
4903 * We can enable relaxed ordering for reads, but not writes when
4904 * DCA is enabled. This is due to a known issue in some chipsets
4905 * which will cause the DCA tag to be cleared.
4906 */
4907 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4908 E1000_DCA_TXCTRL_DATA_RRO_EN |
4909 E1000_DCA_TXCTRL_DESC_DCA_EN;
4910
4911 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4912}
4913
4914static void igb_update_rx_dca(struct igb_adapter *adapter,
4915 struct igb_ring *rx_ring,
4916 int cpu)
4917{
4918 struct e1000_hw *hw = &adapter->hw;
4919 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4920
4921 if (hw->mac.type != e1000_82575)
4922 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4923
4924 /*
4925 * We can enable relaxed ordering for reads, but not writes when
4926 * DCA is enabled. This is due to a known issue in some chipsets
4927 * which will cause the DCA tag to be cleared.
4928 */
4929 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4930 E1000_DCA_RXCTRL_DESC_DCA_EN;
4931
4932 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4933}
4934
047e0030 4935static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4936{
047e0030 4937 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 4938 int cpu = get_cpu();
fe4506b6 4939
047e0030
AD		 4940 if (q_vector->cpu == cpu)
4941 goto out_no_update;
4942
6a05004a
AD		 4943 if (q_vector->tx.ring)
4944 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4945
4946 if (q_vector->rx.ring)
4947 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4948
047e0030
AD		 4949 q_vector->cpu = cpu;
4950out_no_update:
fe4506b6
JC		 4951 put_cpu();
4952}
4953
4954static void igb_setup_dca(struct igb_adapter *adapter)
4955{
7e0e99ef 4956 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4957 int i;
4958
7dfc16fa 4959 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4960 return;
4961
7e0e99ef
AD		 4962 /* Always use CB2 mode, difference is masked in the CB driver. */
4963 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4964
047e0030 4965 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4966 adapter->q_vector[i]->cpu = -1;
4967 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4968 }
4969}
4970
4971static int __igb_notify_dca(struct device *dev, void *data)
4972{
4973 struct net_device *netdev = dev_get_drvdata(dev);
4974 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4975 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4976 struct e1000_hw *hw = &adapter->hw;
4977 unsigned long event = *(unsigned long *)data;
4978
4979 switch (event) {
4980 case DCA_PROVIDER_ADD:
4981 /* if already enabled, don't do it again */
7dfc16fa 4982 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4983 break;
fe4506b6 4984 if (dca_add_requester(dev) == 0) {
bbd98fe4 4985 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4986 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4987 igb_setup_dca(adapter);
4988 break;
4989 }
4990 /* Fall Through since DCA is disabled. */
4991 case DCA_PROVIDER_REMOVE:
7dfc16fa 4992 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4993 /* without this a class_device is left
047e0030 4994 * hanging around in the sysfs model */
fe4506b6 4995 dca_remove_requester(dev);
090b1795 4996 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4997 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4998 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4999 }
5000 break;
5001 }
bbd98fe4 5002
fe4506b6 5003 return 0;
9d5c8243
AK		 5004}
5005
fe4506b6
JC		 5006static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5007 void *p)
5008{
5009 int ret_val;
5010
5011 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5012 __igb_notify_dca);
5013
5014 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5015}
421e02f0 5016#endif /* CONFIG_IGB_DCA */
9d5c8243 5017
0224d663
GR		 5018#ifdef CONFIG_PCI_IOV
5019static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5020{
5021 unsigned char mac_addr[ETH_ALEN];
0224d663 5022
7efd26d0 5023 eth_random_addr(mac_addr);
0224d663
GR		 5024 igb_set_vf_mac(adapter, vf, mac_addr);
5025
f557147c 5026 return 0;
0224d663
GR		 5027}
5028
f557147c 5029static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 5030{
0224d663 5031 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 5032 struct pci_dev *vfdev;
5033 int dev_id;
0224d663
GR		 5034
5035 switch (adapter->hw.mac.type) {
5036 case e1000_82576:
f557147c 5037 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 5038 break;
5039 case e1000_i350:
f557147c 5040 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 5041 break;
5042 default:
f557147c 5043 return false;
0224d663
GR		 5044 }
5045
f557147c
SA		 5046 /* loop through all the VFs to see if we own any that are assigned */
5047 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5048 while (vfdev) {
5049 /* if we don't own it we don't care */
5050 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5051 /* if it is assigned we cannot release it */
5052 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5053 return true;
5054 }
f557147c
SA		 5055
5056 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5057 }
f557147c 5058
0224d663
GR		 5059 return false;
5060}
5061
5062#endif
4ae196df
AD		 5063static void igb_ping_all_vfs(struct igb_adapter *adapter)
5064{
5065 struct e1000_hw *hw = &adapter->hw;
5066 u32 ping;
5067 int i;
5068
5069 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5070 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5071 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5072 ping |= E1000_VT_MSGTYPE_CTS;
5073 igb_write_mbx(hw, &ping, 1, i);
5074 }
5075}
5076
7d5753f0
AD		 5077static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5078{
5079 struct e1000_hw *hw = &adapter->hw;
5080 u32 vmolr = rd32(E1000_VMOLR(vf));
5081 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5082
d85b9004 5083 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5084 IGB_VF_FLAG_MULTI_PROMISC);
5085 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5086
5087 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5088 vmolr |= E1000_VMOLR_MPME;
d85b9004 5089 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5090 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5091 } else {
5092 /*
5093 * if we have hashes and we are clearing a multicast promisc
5094 * flag we need to write the hashes to the MTA as this step
5095 * was previously skipped
5096 */
5097 if (vf_data->num_vf_mc_hashes > 30) {
5098 vmolr |= E1000_VMOLR_MPME;
5099 } else if (vf_data->num_vf_mc_hashes) {
5100 int j;
5101 vmolr |= E1000_VMOLR_ROMPE;
5102 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5103 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5104 }
5105 }
5106
5107 wr32(E1000_VMOLR(vf), vmolr);
5108
5109 /* there are flags left unprocessed, likely not supported */
5110 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5111 return -EINVAL;
5112
5113 return 0;
5114
5115}
5116
4ae196df
AD		 5117static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5118 u32 *msgbuf, u32 vf)
5119{
5120 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5121 u16 *hash_list = (u16 *)&msgbuf[1];
5122 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5123 int i;
5124
7d5753f0 5125 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5126 * to this VF for later use to restore when the PF multi cast
5127 * list changes
5128 */
5129 vf_data->num_vf_mc_hashes = n;
5130
7d5753f0
AD		 5131 /* only up to 30 hash values supported */
5132 if (n > 30)
5133 n = 30;
5134
5135 /* store the hashes for later use */
4ae196df 5136 for (i = 0; i < n; i++)
a419aef8 5137 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5138
5139 /* Flush and reset the mta with the new values */
ff41f8dc 5140 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5141
5142 return 0;
5143}
5144
5145static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5146{
5147 struct e1000_hw *hw = &adapter->hw;
5148 struct vf_data_storage *vf_data;
5149 int i, j;
5150
5151 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5152 u32 vmolr = rd32(E1000_VMOLR(i));
5153 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5154
4ae196df 5155 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5156
5157 if ((vf_data->num_vf_mc_hashes > 30) ||
5158 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5159 vmolr |= E1000_VMOLR_MPME;
5160 } else if (vf_data->num_vf_mc_hashes) {
5161 vmolr |= E1000_VMOLR_ROMPE;
5162 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5163 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5164 }
5165 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5166 }
5167}
5168
5169static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5170{
5171 struct e1000_hw *hw = &adapter->hw;
5172 u32 pool_mask, reg, vid;
5173 int i;
5174
5175 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5176
5177 /* Find the vlan filter for this id */
5178 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5179 reg = rd32(E1000_VLVF(i));
5180
5181 /* remove the vf from the pool */
5182 reg &= ~pool_mask;
5183
5184 /* if pool is empty then remove entry from vfta */
5185 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5186 (reg & E1000_VLVF_VLANID_ENABLE)) {
5187 reg = 0;
5188 vid = reg & E1000_VLVF_VLANID_MASK;
5189 igb_vfta_set(hw, vid, false);
5190 }
5191
5192 wr32(E1000_VLVF(i), reg);
5193 }
ae641bdc
AD		 5194
5195 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5196}
5197
5198static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5199{
5200 struct e1000_hw *hw = &adapter->hw;
5201 u32 reg, i;
5202
51466239
AD		 5203 /* The vlvf table only exists on 82576 hardware and newer */
5204 if (hw->mac.type < e1000_82576)
5205 return -1;
5206
5207 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5208 if (!adapter->vfs_allocated_count)
5209 return -1;
5210
5211 /* Find the vlan filter for this id */
5212 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5213 reg = rd32(E1000_VLVF(i));
5214 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5215 vid == (reg & E1000_VLVF_VLANID_MASK))
5216 break;
5217 }
5218
5219 if (add) {
5220 if (i == E1000_VLVF_ARRAY_SIZE) {
5221 /* Did not find a matching VLAN ID entry that was
5222 * enabled. Search for a free filter entry, i.e.
5223 * one without the enable bit set
5224 */
5225 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5226 reg = rd32(E1000_VLVF(i));
5227 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5228 break;
5229 }
5230 }
5231 if (i < E1000_VLVF_ARRAY_SIZE) {
5232 /* Found an enabled/available entry */
5233 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5234
5235 /* if !enabled we need to set this up in vfta */
5236 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5237 /* add VID to filter table */
5238 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5239 reg |= E1000_VLVF_VLANID_ENABLE;
5240 }
cad6d05f
AD		 5241 reg &= ~E1000_VLVF_VLANID_MASK;
5242 reg |= vid;
4ae196df 5243 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5244
5245 /* do not modify RLPML for PF devices */
5246 if (vf >= adapter->vfs_allocated_count)
5247 return 0;
5248
5249 if (!adapter->vf_data[vf].vlans_enabled) {
5250 u32 size;
5251 reg = rd32(E1000_VMOLR(vf));
5252 size = reg & E1000_VMOLR_RLPML_MASK;
5253 size += 4;
5254 reg &= ~E1000_VMOLR_RLPML_MASK;
5255 reg |= size;
5256 wr32(E1000_VMOLR(vf), reg);
5257 }
ae641bdc 5258
51466239 5259 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5260 }
5261 } else {
5262 if (i < E1000_VLVF_ARRAY_SIZE) {
5263 /* remove vf from the pool */
5264 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5265 /* if pool is empty then remove entry from vfta */
5266 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5267 reg = 0;
5268 igb_vfta_set(hw, vid, false);
5269 }
5270 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5271
5272 /* do not modify RLPML for PF devices */
5273 if (vf >= adapter->vfs_allocated_count)
5274 return 0;
5275
5276 adapter->vf_data[vf].vlans_enabled--;
5277 if (!adapter->vf_data[vf].vlans_enabled) {
5278 u32 size;
5279 reg = rd32(E1000_VMOLR(vf));
5280 size = reg & E1000_VMOLR_RLPML_MASK;
5281 size -= 4;
5282 reg &= ~E1000_VMOLR_RLPML_MASK;
5283 reg |= size;
5284 wr32(E1000_VMOLR(vf), reg);
5285 }
4ae196df
AD		 5286 }
5287 }
8151d294
WM		 5288 return 0;
5289}
5290
5291static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5292{
5293 struct e1000_hw *hw = &adapter->hw;
5294
5295 if (vid)
5296 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5297 else
5298 wr32(E1000_VMVIR(vf), 0);
5299}
5300
5301static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5302 int vf, u16 vlan, u8 qos)
5303{
5304 int err = 0;
5305 struct igb_adapter *adapter = netdev_priv(netdev);
5306
5307 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5308 return -EINVAL;
5309 if (vlan || qos) {
5310 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5311 if (err)
5312 goto out;
5313 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5314 igb_set_vmolr(adapter, vf, !vlan);
5315 adapter->vf_data[vf].pf_vlan = vlan;
5316 adapter->vf_data[vf].pf_qos = qos;
5317 dev_info(&adapter->pdev->dev,
5318 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5319 if (test_bit(__IGB_DOWN, &adapter->state)) {
5320 dev_warn(&adapter->pdev->dev,
5321 "The VF VLAN has been set,"
5322 " but the PF device is not up.\n");
5323 dev_warn(&adapter->pdev->dev,
5324 "Bring the PF device up before"
5325 " attempting to use the VF device.\n");
5326 }
5327 } else {
5328 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5329 false, vf);
5330 igb_set_vmvir(adapter, vlan, vf);
5331 igb_set_vmolr(adapter, vf, true);
5332 adapter->vf_data[vf].pf_vlan = 0;
5333 adapter->vf_data[vf].pf_qos = 0;
5334 }
5335out:
5336 return err;
4ae196df
AD		 5337}
5338
5339static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5340{
5341 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5342 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5343
5344 return igb_vlvf_set(adapter, vid, add, vf);
5345}
5346
f2ca0dbe 5347static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5348{
8fa7e0f7
GR		 5349 /* clear flags - except flag that indicates PF has set the MAC */
5350 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5351 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5352
5353 /* reset offloads to defaults */
8151d294 5354 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5355
5356 /* reset vlans for device */
5357 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5358 if (adapter->vf_data[vf].pf_vlan)
5359 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5360 adapter->vf_data[vf].pf_vlan,
5361 adapter->vf_data[vf].pf_qos);
5362 else
5363 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5364
5365 /* reset multicast table array for vf */
5366 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5367
5368 /* Flush and reset the mta with the new values */
ff41f8dc 5369 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5370}
5371
f2ca0dbe
AD		 5372static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5373{
5374 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5375
5376 /* generate a new mac address as we were hotplug removed/added */
8151d294 5377 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5378 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5379
5380 /* process remaining reset events */
5381 igb_vf_reset(adapter, vf);
5382}
5383
5384static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5385{
5386 struct e1000_hw *hw = &adapter->hw;
5387 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5388 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5389 u32 reg, msgbuf[3];
5390 u8 *addr = (u8 *)(&msgbuf[1]);
5391
5392 /* process all the same items cleared in a function level reset */
f2ca0dbe 5393 igb_vf_reset(adapter, vf);
4ae196df
AD		 5394
5395 /* set vf mac address */
26ad9178 5396 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5397
5398 /* enable transmit and receive for vf */
5399 reg = rd32(E1000_VFTE);
5400 wr32(E1000_VFTE, reg | (1 << vf));
5401 reg = rd32(E1000_VFRE);
5402 wr32(E1000_VFRE, reg | (1 << vf));
5403
8fa7e0f7 5404 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5405
5406 /* reply to reset with ack and vf mac address */
5407 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5408 memcpy(addr, vf_mac, 6);
5409 igb_write_mbx(hw, msgbuf, 3, vf);
5410}
5411
5412static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5413{
de42edde
GR		 5414 /*
5415 * The VF MAC Address is stored in a packed array of bytes
5416 * starting at the second 32 bit word of the msg array
5417 */
f2ca0dbe
AD		 5418 unsigned char *addr = (char *)&msg[1];
5419 int err = -1;
4ae196df 5420
f2ca0dbe
AD		 5421 if (is_valid_ether_addr(addr))
5422 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5423
f2ca0dbe 5424 return err;
4ae196df
AD		 5425}
5426
5427static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5428{
5429 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5430 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5431 u32 msg = E1000_VT_MSGTYPE_NACK;
5432
5433 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5434 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5435 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5436 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5437 vf_data->last_nack = jiffies;
4ae196df
AD		 5438 }
5439}
5440
f2ca0dbe 5441static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5442{
f2ca0dbe
AD		 5443 struct pci_dev *pdev = adapter->pdev;
5444 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5445 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5446 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5447 s32 retval;
5448
f2ca0dbe 5449 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5450
fef45f4c
AD		 5451 if (retval) {
5452 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5453 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5454 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5455 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5456 return;
5457 goto out;
5458 }
4ae196df
AD		 5459
5460 /* this is a message we already processed, do nothing */
5461 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5462 return;
4ae196df
AD		 5463
5464 /*
5465 * until the vf completes a reset it should not be
5466 * allowed to start any configuration.
5467 */
5468
5469 if (msgbuf[0] == E1000_VF_RESET) {
5470 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5471 return;
4ae196df
AD		 5472 }
5473
f2ca0dbe 5474 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5475 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5476 return;
5477 retval = -1;
5478 goto out;
4ae196df
AD		 5479 }
5480
5481 switch ((msgbuf[0] & 0xFFFF)) {
5482 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5483 retval = -EINVAL;
5484 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5485 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5486 else
5487 dev_warn(&pdev->dev,
5488 "VF %d attempted to override administratively "
5489 "set MAC address\nReload the VF driver to "
5490 "resume operations\n", vf);
4ae196df 5491 break;
7d5753f0
AD		 5492 case E1000_VF_SET_PROMISC:
5493 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5494 break;
4ae196df
AD		 5495 case E1000_VF_SET_MULTICAST:
5496 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5497 break;
5498 case E1000_VF_SET_LPE:
5499 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5500 break;
5501 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5502 retval = -1;
5503 if (vf_data->pf_vlan)
5504 dev_warn(&pdev->dev,
5505 "VF %d attempted to override administratively "
5506 "set VLAN tag\nReload the VF driver to "
5507 "resume operations\n", vf);
8151d294
WM		 5508 else
5509 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5510 break;
5511 default:
090b1795 5512 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5513 retval = -1;
5514 break;
5515 }
5516
fef45f4c
AD		 5517 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5518out:
4ae196df
AD		 5519 /* notify the VF of the results of what it sent us */
5520 if (retval)
5521 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5522 else
5523 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5524
4ae196df 5525 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5526}
4ae196df 5527
f2ca0dbe
AD		 5528static void igb_msg_task(struct igb_adapter *adapter)
5529{
5530 struct e1000_hw *hw = &adapter->hw;
5531 u32 vf;
5532
5533 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5534 /* process any reset requests */
5535 if (!igb_check_for_rst(hw, vf))
5536 igb_vf_reset_event(adapter, vf);
5537
5538 /* process any messages pending */
5539 if (!igb_check_for_msg(hw, vf))
5540 igb_rcv_msg_from_vf(adapter, vf);
5541
5542 /* process any acks */
5543 if (!igb_check_for_ack(hw, vf))
5544 igb_rcv_ack_from_vf(adapter, vf);
5545 }
4ae196df
AD		 5546}
5547
68d480c4
AD		 5548/**
5549 * igb_set_uta - Set unicast filter table address
5550 * @adapter: board private structure
5551 *
5552 * The unicast table address is a register array of 32-bit registers.
5553 * The table is meant to be used in a way similar to how the MTA is used
5554 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5555 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5556 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5557 **/
5558static void igb_set_uta(struct igb_adapter *adapter)
5559{
5560 struct e1000_hw *hw = &adapter->hw;
5561 int i;
5562
5563 /* The UTA table only exists on 82576 hardware and newer */
5564 if (hw->mac.type < e1000_82576)
5565 return;
5566
5567 /* we only need to do this if VMDq is enabled */
5568 if (!adapter->vfs_allocated_count)
5569 return;
5570
5571 for (i = 0; i < hw->mac.uta_reg_count; i++)
5572 array_wr32(E1000_UTA, i, ~0);
5573}
5574
9d5c8243
AK		 5575/**
5576 * igb_intr_msi - Interrupt Handler
5577 * @irq: interrupt number
5578 * @data: pointer to a network interface device structure
5579 **/
5580static irqreturn_t igb_intr_msi(int irq, void *data)
5581{
047e0030
AD		 5582 struct igb_adapter *adapter = data;
5583 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5584 struct e1000_hw *hw = &adapter->hw;
5585 /* read ICR disables interrupts using IAM */
5586 u32 icr = rd32(E1000_ICR);
5587
047e0030 5588 igb_write_itr(q_vector);
9d5c8243 5589
7f081d40
AD		 5590 if (icr & E1000_ICR_DRSTA)
5591 schedule_work(&adapter->reset_task);
5592
047e0030 5593 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5594 /* HW is reporting DMA is out of sync */
5595 adapter->stats.doosync++;
5596 }
5597
9d5c8243
AK		 5598 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5599 hw->mac.get_link_status = 1;
5600 if (!test_bit(__IGB_DOWN, &adapter->state))
5601 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5602 }
5603
1f6e8178
MV		 5604 if (icr & E1000_ICR_TS) {
5605 u32 tsicr = rd32(E1000_TSICR);
5606
5607 if (tsicr & E1000_TSICR_TXTS) {
5608 /* acknowledge the interrupt */
5609 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5610 /* retrieve hardware timestamp */
5611 schedule_work(&adapter->ptp_tx_work);
5612 }
5613 }
1f6e8178 5614
047e0030 5615 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5616
5617 return IRQ_HANDLED;
5618}
5619
5620/**
4a3c6433 5621 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5622 * @irq: interrupt number
5623 * @data: pointer to a network interface device structure
5624 **/
5625static irqreturn_t igb_intr(int irq, void *data)
5626{
047e0030
AD		 5627 struct igb_adapter *adapter = data;
5628 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5629 struct e1000_hw *hw = &adapter->hw;
5630 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5631 * need for the IMC write */
5632 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5633
5634 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5635 * not set, then the adapter didn't send an interrupt */
5636 if (!(icr & E1000_ICR_INT_ASSERTED))
5637 return IRQ_NONE;
5638
0ba82994
AD		 5639 igb_write_itr(q_vector);
5640
7f081d40
AD		 5641 if (icr & E1000_ICR_DRSTA)
5642 schedule_work(&adapter->reset_task);
5643
047e0030 5644 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5645 /* HW is reporting DMA is out of sync */
5646 adapter->stats.doosync++;
5647 }
5648
9d5c8243
AK		 5649 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5650 hw->mac.get_link_status = 1;
5651 /* guard against interrupt when we're going down */
5652 if (!test_bit(__IGB_DOWN, &adapter->state))
5653 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5654 }
5655
1f6e8178
MV		 5656 if (icr & E1000_ICR_TS) {
5657 u32 tsicr = rd32(E1000_TSICR);
5658
5659 if (tsicr & E1000_TSICR_TXTS) {
5660 /* acknowledge the interrupt */
5661 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5662 /* retrieve hardware timestamp */
5663 schedule_work(&adapter->ptp_tx_work);
5664 }
5665 }
1f6e8178 5666
047e0030 5667 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5668
5669 return IRQ_HANDLED;
5670}
5671
c50b52a0 5672static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5673{
047e0030 5674 struct igb_adapter *adapter = q_vector->adapter;
46544258 5675 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5676
0ba82994
AD		 5677 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5678 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5679 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5680 igb_set_itr(q_vector);
46544258 5681 else
047e0030 5682 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5683 }
5684
46544258
AD		 5685 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5686 if (adapter->msix_entries)
047e0030 5687 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5688 else
5689 igb_irq_enable(adapter);
5690 }
9d5c8243
AK		 5691}
5692
46544258
AD		 5693/**
5694 * igb_poll - NAPI Rx polling callback
5695 * @napi: napi polling structure
5696 * @budget: count of how many packets we should handle
5697 **/
5698static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5699{
047e0030
AD		 5700 struct igb_q_vector *q_vector = container_of(napi,
5701 struct igb_q_vector,
5702 napi);
16eb8815 5703 bool clean_complete = true;
9d5c8243 5704
421e02f0 5705#ifdef CONFIG_IGB_DCA
047e0030
AD		 5706 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5707 igb_update_dca(q_vector);
fe4506b6 5708#endif
0ba82994 5709 if (q_vector->tx.ring)
13fde97a 5710 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5711
0ba82994 5712 if (q_vector->rx.ring)
cd392f5c 5713 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5714
16eb8815
AD		 5715 /* If all work not completed, return budget and keep polling */
5716 if (!clean_complete)
5717 return budget;
46544258 5718
9d5c8243 5719 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5720 napi_complete(napi);
5721 igb_ring_irq_enable(q_vector);
9d5c8243 5722
16eb8815 5723 return 0;
9d5c8243 5724}
6d8126f9 5725
9d5c8243
AK		 5726/**
5727 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5728 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5729 *
9d5c8243
AK		 5730 * returns true if ring is completely cleaned
5731 **/
047e0030 5732static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5733{
047e0030 5734 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5735 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5736 struct igb_tx_buffer *tx_buffer;
f4128785 5737 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5738 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5739 unsigned int budget = q_vector->tx.work_limit;
8542db05 5740 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5741
13fde97a
AD		 5742 if (test_bit(__IGB_DOWN, &adapter->state))
5743 return true;
0e014cb1 5744
06034649 5745 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5746 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5747 i -= tx_ring->count;
9d5c8243 5748
f4128785
AD		 5749 do {
5750 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5751
5752 /* if next_to_watch is not set then there is no work pending */
5753 if (!eop_desc)
5754 break;
13fde97a 5755
f4128785
AD		 5756 /* prevent any other reads prior to eop_desc */
5757 rmb();
5758
13fde97a
AD		 5759 /* if DD is not set pending work has not been completed */
5760 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5761 break;
5762
8542db05
AD		 5763 /* clear next_to_watch to prevent false hangs */
5764 tx_buffer->next_to_watch = NULL;
9d5c8243 5765
ebe42d16
AD		 5766 /* update the statistics for this packet */
5767 total_bytes += tx_buffer->bytecount;
5768 total_packets += tx_buffer->gso_segs;
13fde97a 5769
ebe42d16
AD		 5770 /* free the skb */
5771 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5772
ebe42d16
AD		 5773 /* unmap skb header data */
5774 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5775 dma_unmap_addr(tx_buffer, dma),
5776 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5777 DMA_TO_DEVICE);
5778
c9f14bf3
AD		 5779 /* clear tx_buffer data */
5780 tx_buffer->skb = NULL;
5781 dma_unmap_len_set(tx_buffer, len, 0);
5782
ebe42d16
AD		 5783 /* clear last DMA location and unmap remaining buffers */
5784 while (tx_desc != eop_desc) {
13fde97a
AD		 5785 tx_buffer++;
5786 tx_desc++;
9d5c8243 5787 i++;
8542db05
AD		 5788 if (unlikely(!i)) {
5789 i -= tx_ring->count;
06034649 5790 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5791 tx_desc = IGB_TX_DESC(tx_ring, 0);
5792 }
ebe42d16
AD		 5793
5794 /* unmap any remaining paged data */
c9f14bf3 5795 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5796 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5797 dma_unmap_addr(tx_buffer, dma),
5798 dma_unmap_len(tx_buffer, len),
ebe42d16 5799 DMA_TO_DEVICE);
c9f14bf3 5800 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5801 }
5802 }
5803
ebe42d16
AD		 5804 /* move us one more past the eop_desc for start of next pkt */
5805 tx_buffer++;
5806 tx_desc++;
5807 i++;
5808 if (unlikely(!i)) {
5809 i -= tx_ring->count;
5810 tx_buffer = tx_ring->tx_buffer_info;
5811 tx_desc = IGB_TX_DESC(tx_ring, 0);
5812 }
f4128785
AD		 5813
5814 /* issue prefetch for next Tx descriptor */
5815 prefetch(tx_desc);
5816
5817 /* update budget accounting */
5818 budget--;
5819 } while (likely(budget));
0e014cb1 5820
bdbc0631
ED		 5821 netdev_tx_completed_queue(txring_txq(tx_ring),
5822 total_packets, total_bytes);
8542db05 5823 i += tx_ring->count;
9d5c8243 5824 tx_ring->next_to_clean = i;
13fde97a
AD		 5825 u64_stats_update_begin(&tx_ring->tx_syncp);
5826 tx_ring->tx_stats.bytes += total_bytes;
5827 tx_ring->tx_stats.packets += total_packets;
5828 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5829 q_vector->tx.total_bytes += total_bytes;
5830 q_vector->tx.total_packets += total_packets;
9d5c8243 5831
6d095fa8 5832 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5833 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5834
9d5c8243
AK		 5835 /* Detect a transmit hang in hardware, this serializes the
5836 * check with the clearing of time_stamp and movement of i */
6d095fa8 5837 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5838 if (tx_buffer->next_to_watch &&
8542db05 5839 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5840 (adapter->tx_timeout_factor * HZ)) &&
5841 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5842
9d5c8243 5843 /* detected Tx unit hang */
59d71989 5844 dev_err(tx_ring->dev,
9d5c8243 5845 "Detected Tx Unit Hang\n"
2d064c06 5846 " Tx Queue <%d>\n"
9d5c8243
AK		 5847 " TDH <%x>\n"
5848 " TDT <%x>\n"
5849 " next_to_use <%x>\n"
5850 " next_to_clean <%x>\n"
9d5c8243
AK		 5851 "buffer_info[next_to_clean]\n"
5852 " time_stamp <%lx>\n"
8542db05 5853 " next_to_watch <%p>\n"
9d5c8243
AK		 5854 " jiffies <%lx>\n"
5855 " desc.status <%x>\n",
2d064c06 5856 tx_ring->queue_index,
238ac817 5857 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5858 readl(tx_ring->tail),
9d5c8243
AK		 5859 tx_ring->next_to_use,
5860 tx_ring->next_to_clean,
8542db05 5861 tx_buffer->time_stamp,
f4128785 5862 tx_buffer->next_to_watch,
9d5c8243 5863 jiffies,
f4128785 5864 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 5865 netif_stop_subqueue(tx_ring->netdev,
5866 tx_ring->queue_index);
5867
5868 /* we are about to reset, no point in enabling stuff */
5869 return true;
9d5c8243
AK		 5870 }
5871 }
13fde97a
AD		 5872
5873 if (unlikely(total_packets &&
5874 netif_carrier_ok(tx_ring->netdev) &&
5875 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5876 /* Make sure that anybody stopping the queue after this
5877 * sees the new next_to_clean.
5878 */
5879 smp_mb();
5880 if (__netif_subqueue_stopped(tx_ring->netdev,
5881 tx_ring->queue_index) &&
5882 !(test_bit(__IGB_DOWN, &adapter->state))) {
5883 netif_wake_subqueue(tx_ring->netdev,
5884 tx_ring->queue_index);
5885
5886 u64_stats_update_begin(&tx_ring->tx_syncp);
5887 tx_ring->tx_stats.restart_queue++;
5888 u64_stats_update_end(&tx_ring->tx_syncp);
5889 }
5890 }
5891
5892 return !!budget;
9d5c8243
AK		 5893}
5894
cbc8e55f
AD		 5895/**
5896 * igb_reuse_rx_page - page flip buffer and store it back on the ring
5897 * @rx_ring: rx descriptor ring to store buffers on
5898 * @old_buff: donor buffer to have page reused
5899 *
5900 * Synchronizes page for reuse by the adapter
5901 **/
5902static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5903 struct igb_rx_buffer *old_buff)
5904{
5905 struct igb_rx_buffer *new_buff;
5906 u16 nta = rx_ring->next_to_alloc;
5907
5908 new_buff = &rx_ring->rx_buffer_info[nta];
5909
5910 /* update, and store next to alloc */
5911 nta++;
5912 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5913
5914 /* transfer page from old buffer to new buffer */
5915 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5916
5917 /* sync the buffer for use by the device */
5918 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5919 old_buff->page_offset,
de78d1f9 5920 IGB_RX_BUFSZ,
cbc8e55f
AD		 5921 DMA_FROM_DEVICE);
5922}
5923
5924/**
5925 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5926 * @rx_ring: rx descriptor ring to transact packets on
5927 * @rx_buffer: buffer containing page to add
5928 * @rx_desc: descriptor containing length of buffer written by hardware
5929 * @skb: sk_buff to place the data into
5930 *
5931 * This function will add the data contained in rx_buffer->page to the skb.
5932 * This is done either through a direct copy if the data in the buffer is
5933 * less than the skb header size, otherwise it will just attach the page as
5934 * a frag to the skb.
5935 *
5936 * The function will then update the page offset if necessary and return
5937 * true if the buffer can be reused by the adapter.
5938 **/
5939static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5940 struct igb_rx_buffer *rx_buffer,
5941 union e1000_adv_rx_desc *rx_desc,
5942 struct sk_buff *skb)
5943{
5944 struct page *page = rx_buffer->page;
5945 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5946
5947 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5948 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5949
cbc8e55f
AD		 5950 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5951 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5952 va += IGB_TS_HDR_LEN;
5953 size -= IGB_TS_HDR_LEN;
5954 }
5955
cbc8e55f
AD		 5956 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5957
5958 /* we can reuse buffer as-is, just make sure it is local */
5959 if (likely(page_to_nid(page) == numa_node_id()))
5960 return true;
5961
5962 /* this page cannot be reused so discard it */
5963 put_page(page);
5964 return false;
5965 }
5966
5967 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 5968 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 5969
5970 /* avoid re-using remote pages */
5971 if (unlikely(page_to_nid(page) != numa_node_id()))
5972 return false;
5973
de78d1f9 5974#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 5975 /* if we are only owner of page we can reuse it */
5976 if (unlikely(page_count(page) != 1))
5977 return false;
5978
5979 /* flip page offset to other buffer */
de78d1f9 5980 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 5981
5982 /*
5983 * since we are the only owner of the page and we need to
5984 * increment it, just set the value to 2 in order to avoid
5985 * an unnecessary locked operation
5986 */
5987 atomic_set(&page->_count, 2);
de78d1f9
AD		 5988#else
5989 /* move offset up to the next cache line */
5990 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5991
5992 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5993 return false;
5994
5995 /* bump ref count on page before it is given to the stack */
5996 get_page(page);
5997#endif
cbc8e55f
AD		 5998
5999 return true;
6000}
6001
2e334eee
AD		 6002static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6003 union e1000_adv_rx_desc *rx_desc,
6004 struct sk_buff *skb)
6005{
6006 struct igb_rx_buffer *rx_buffer;
6007 struct page *page;
6008
6009 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6010
6011 /*
6012 * This memory barrier is needed to keep us from reading
6013 * any other fields out of the rx_desc until we know the
6014 * RXD_STAT_DD bit is set
6015 */
6016 rmb();
6017
6018 page = rx_buffer->page;
6019 prefetchw(page);
6020
6021 if (likely(!skb)) {
6022 void *page_addr = page_address(page) +
6023 rx_buffer->page_offset;
6024
6025 /* prefetch first cache line of first page */
6026 prefetch(page_addr);
6027#if L1_CACHE_BYTES < 128
6028 prefetch(page_addr + L1_CACHE_BYTES);
6029#endif
6030
6031 /* allocate a skb to store the frags */
6032 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6033 IGB_RX_HDR_LEN);
6034 if (unlikely(!skb)) {
6035 rx_ring->rx_stats.alloc_failed++;
6036 return NULL;
6037 }
6038
6039 /*
6040 * we will be copying header into skb->data in
6041 * pskb_may_pull so it is in our interest to prefetch
6042 * it now to avoid a possible cache miss
6043 */
6044 prefetchw(skb->data);
6045 }
6046
6047 /* we are reusing so sync this buffer for CPU use */
6048 dma_sync_single_range_for_cpu(rx_ring->dev,
6049 rx_buffer->dma,
6050 rx_buffer->page_offset,
de78d1f9 6051 IGB_RX_BUFSZ,
2e334eee
AD		 6052 DMA_FROM_DEVICE);
6053
6054 /* pull page into skb */
6055 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6056 /* hand second half of page back to the ring */
6057 igb_reuse_rx_page(rx_ring, rx_buffer);
6058 } else {
6059 /* we are not reusing the buffer so unmap it */
6060 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6061 PAGE_SIZE, DMA_FROM_DEVICE);
6062 }
6063
6064 /* clear contents of rx_buffer */
6065 rx_buffer->page = NULL;
6066
6067 return skb;
6068}
6069
cd392f5c 6070static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6071 union e1000_adv_rx_desc *rx_desc,
6072 struct sk_buff *skb)
9d5c8243 6073{
bc8acf2c 6074 skb_checksum_none_assert(skb);
9d5c8243 6075
294e7d78 6076 /* Ignore Checksum bit is set */
3ceb90fd 6077 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6078 return;
6079
6080 /* Rx checksum disabled via ethtool */
6081 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6082 return;
85ad76b2 6083
9d5c8243 6084 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6085 if (igb_test_staterr(rx_desc,
6086 E1000_RXDEXT_STATERR_TCPE |
6087 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6088 /*
6089 * work around errata with sctp packets where the TCPE aka
6090 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6091 * packets, (aka let the stack check the crc32c)
6092 */
866cff06
AD		 6093 if (!((skb->len == 60) &&
6094 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6095 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6096 ring->rx_stats.csum_err++;
12dcd86b
ED		 6097 u64_stats_update_end(&ring->rx_syncp);
6098 }
9d5c8243 6099 /* let the stack verify checksum errors */
9d5c8243
AK		 6100 return;
6101 }
6102 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6103 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6104 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6105 skb->ip_summed = CHECKSUM_UNNECESSARY;
6106
3ceb90fd
AD		 6107 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6108 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6109}
6110
077887c3
AD		 6111static inline void igb_rx_hash(struct igb_ring *ring,
6112 union e1000_adv_rx_desc *rx_desc,
6113 struct sk_buff *skb)
6114{
6115 if (ring->netdev->features & NETIF_F_RXHASH)
6116 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6117}
6118
2e334eee
AD		 6119/**
6120 * igb_is_non_eop - process handling of non-EOP buffers
6121 * @rx_ring: Rx ring being processed
6122 * @rx_desc: Rx descriptor for current buffer
6123 * @skb: current socket buffer containing buffer in progress
6124 *
6125 * This function updates next to clean. If the buffer is an EOP buffer
6126 * this function exits returning false, otherwise it will place the
6127 * sk_buff in the next buffer to be chained and return true indicating
6128 * that this is in fact a non-EOP buffer.
6129 **/
6130static bool igb_is_non_eop(struct igb_ring *rx_ring,
6131 union e1000_adv_rx_desc *rx_desc)
6132{
6133 u32 ntc = rx_ring->next_to_clean + 1;
6134
6135 /* fetch, update, and store next to clean */
6136 ntc = (ntc < rx_ring->count) ? ntc : 0;
6137 rx_ring->next_to_clean = ntc;
6138
6139 prefetch(IGB_RX_DESC(rx_ring, ntc));
6140
6141 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6142 return false;
6143
6144 return true;
6145}
6146
1a1c225b
AD		 6147/**
6148 * igb_get_headlen - determine size of header for LRO/GRO
6149 * @data: pointer to the start of the headers
6150 * @max_len: total length of section to find headers in
6151 *
6152 * This function is meant to determine the length of headers that will
6153 * be recognized by hardware for LRO, and GRO offloads. The main
6154 * motivation of doing this is to only perform one pull for IPv4 TCP
6155 * packets so that we can do basic things like calculating the gso_size
6156 * based on the average data per packet.
6157 **/
6158static unsigned int igb_get_headlen(unsigned char *data,
6159 unsigned int max_len)
6160{
6161 union {
6162 unsigned char *network;
6163 /* l2 headers */
6164 struct ethhdr *eth;
6165 struct vlan_hdr *vlan;
6166 /* l3 headers */
6167 struct iphdr *ipv4;
6168 struct ipv6hdr *ipv6;
6169 } hdr;
6170 __be16 protocol;
6171 u8 nexthdr = 0; /* default to not TCP */
6172 u8 hlen;
6173
6174 /* this should never happen, but better safe than sorry */
6175 if (max_len < ETH_HLEN)
6176 return max_len;
6177
6178 /* initialize network frame pointer */
6179 hdr.network = data;
6180
6181 /* set first protocol and move network header forward */
6182 protocol = hdr.eth->h_proto;
6183 hdr.network += ETH_HLEN;
6184
6185 /* handle any vlan tag if present */
6186 if (protocol == __constant_htons(ETH_P_8021Q)) {
6187 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6188 return max_len;
6189
6190 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6191 hdr.network += VLAN_HLEN;
6192 }
6193
6194 /* handle L3 protocols */
6195 if (protocol == __constant_htons(ETH_P_IP)) {
6196 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6197 return max_len;
6198
6199 /* access ihl as a u8 to avoid unaligned access on ia64 */
6200 hlen = (hdr.network[0] & 0x0F) << 2;
6201
6202 /* verify hlen meets minimum size requirements */
6203 if (hlen < sizeof(struct iphdr))
6204 return hdr.network - data;
6205
f2fb4ab2
AD		 6206 /* record next protocol if header is present */
6207 if (!hdr.ipv4->frag_off)
6208 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6209 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6210 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6211 return max_len;
6212
6213 /* record next protocol */
6214 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6215 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6216 } else {
6217 return hdr.network - data;
6218 }
6219
f2fb4ab2
AD		 6220 /* relocate pointer to start of L4 header */
6221 hdr.network += hlen;
6222
1a1c225b
AD		 6223 /* finally sort out TCP */
6224 if (nexthdr == IPPROTO_TCP) {
6225 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6226 return max_len;
6227
6228 /* access doff as a u8 to avoid unaligned access on ia64 */
6229 hlen = (hdr.network[12] & 0xF0) >> 2;
6230
6231 /* verify hlen meets minimum size requirements */
6232 if (hlen < sizeof(struct tcphdr))
6233 return hdr.network - data;
6234
6235 hdr.network += hlen;
6236 } else if (nexthdr == IPPROTO_UDP) {
6237 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6238 return max_len;
6239
6240 hdr.network += sizeof(struct udphdr);
6241 }
6242
6243 /*
6244 * If everything has gone correctly hdr.network should be the
6245 * data section of the packet and will be the end of the header.
6246 * If not then it probably represents the end of the last recognized
6247 * header.
6248 */
6249 if ((hdr.network - data) < max_len)
6250 return hdr.network - data;
6251 else
6252 return max_len;
6253}
6254
6255/**
6256 * igb_pull_tail - igb specific version of skb_pull_tail
6257 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6258 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6259 * @skb: pointer to current skb being adjusted
6260 *
6261 * This function is an igb specific version of __pskb_pull_tail. The
6262 * main difference between this version and the original function is that
6263 * this function can make several assumptions about the state of things
6264 * that allow for significant optimizations versus the standard function.
6265 * As a result we can do things like drop a frag and maintain an accurate
6266 * truesize for the skb.
6267 */
6268static void igb_pull_tail(struct igb_ring *rx_ring,
6269 union e1000_adv_rx_desc *rx_desc,
6270 struct sk_buff *skb)
2d94d8ab 6271{
1a1c225b
AD		 6272 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6273 unsigned char *va;
6274 unsigned int pull_len;
6275
6276 /*
6277 * it is valid to use page_address instead of kmap since we are
6278 * working with pages allocated out of the lomem pool per
6279 * alloc_page(GFP_ATOMIC)
2d94d8ab 6280 */
1a1c225b
AD		 6281 va = skb_frag_address(frag);
6282
1a1c225b
AD		 6283 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6284 /* retrieve timestamp from buffer */
6285 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6286
6287 /* update pointers to remove timestamp header */
6288 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6289 frag->page_offset += IGB_TS_HDR_LEN;
6290 skb->data_len -= IGB_TS_HDR_LEN;
6291 skb->len -= IGB_TS_HDR_LEN;
6292
6293 /* move va to start of packet data */
6294 va += IGB_TS_HDR_LEN;
6295 }
6296
1a1c225b
AD		 6297 /*
6298 * we need the header to contain the greater of either ETH_HLEN or
6299 * 60 bytes if the skb->len is less than 60 for skb_pad.
6300 */
6301 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6302
6303 /* align pull length to size of long to optimize memcpy performance */
6304 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6305
6306 /* update all of the pointers */
6307 skb_frag_size_sub(frag, pull_len);
6308 frag->page_offset += pull_len;
6309 skb->data_len -= pull_len;
6310 skb->tail += pull_len;
6311}
6312
6313/**
6314 * igb_cleanup_headers - Correct corrupted or empty headers
6315 * @rx_ring: rx descriptor ring packet is being transacted on
6316 * @rx_desc: pointer to the EOP Rx descriptor
6317 * @skb: pointer to current skb being fixed
6318 *
6319 * Address the case where we are pulling data in on pages only
6320 * and as such no data is present in the skb header.
6321 *
6322 * In addition if skb is not at least 60 bytes we need to pad it so that
6323 * it is large enough to qualify as a valid Ethernet frame.
6324 *
6325 * Returns true if an error was encountered and skb was freed.
6326 **/
6327static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6328 union e1000_adv_rx_desc *rx_desc,
6329 struct sk_buff *skb)
6330{
6331
6332 if (unlikely((igb_test_staterr(rx_desc,
6333 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6334 struct net_device *netdev = rx_ring->netdev;
6335 if (!(netdev->features & NETIF_F_RXALL)) {
6336 dev_kfree_skb_any(skb);
6337 return true;
6338 }
6339 }
6340
6341 /* place header in linear portion of buffer */
6342 if (skb_is_nonlinear(skb))
6343 igb_pull_tail(rx_ring, rx_desc, skb);
6344
6345 /* if skb_pad returns an error the skb was freed */
6346 if (unlikely(skb->len < 60)) {
6347 int pad_len = 60 - skb->len;
6348
6349 if (skb_pad(skb, pad_len))
6350 return true;
6351 __skb_put(skb, pad_len);
6352 }
6353
6354 return false;
2d94d8ab
AD		 6355}
6356
db2ee5bd
AD		 6357/**
6358 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6359 * @rx_ring: rx descriptor ring packet is being transacted on
6360 * @rx_desc: pointer to the EOP Rx descriptor
6361 * @skb: pointer to current skb being populated
6362 *
6363 * This function checks the ring, descriptor, and packet information in
6364 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6365 * other fields within the skb.
6366 **/
6367static void igb_process_skb_fields(struct igb_ring *rx_ring,
6368 union e1000_adv_rx_desc *rx_desc,
6369 struct sk_buff *skb)
6370{
6371 struct net_device *dev = rx_ring->netdev;
6372
6373 igb_rx_hash(rx_ring, rx_desc, skb);
6374
6375 igb_rx_checksum(rx_ring, rx_desc, skb);
6376
db2ee5bd 6377 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6378
6379 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6380 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6381 u16 vid;
6382 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6383 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6384 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6385 else
6386 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6387
6388 __vlan_hwaccel_put_tag(skb, vid);
6389 }
6390
6391 skb_record_rx_queue(skb, rx_ring->queue_index);
6392
6393 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6394}
6395
2e334eee 6396static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6397{
0ba82994 6398 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6399 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6400 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6401 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6402
2e334eee
AD		 6403 do {
6404 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6405
2e334eee
AD		 6406 /* return some buffers to hardware, one at a time is too slow */
6407 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6408 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6409 cleaned_count = 0;
6410 }
bf36c1a0 6411
2e334eee 6412 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6413
2e334eee
AD		 6414 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6415 break;
9d5c8243 6416
2e334eee
AD		 6417 /* retrieve a buffer from the ring */
6418 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6419
2e334eee
AD		 6420 /* exit if we failed to retrieve a buffer */
6421 if (!skb)
6422 break;
1a1c225b 6423
2e334eee 6424 cleaned_count++;
1a1c225b 6425
2e334eee
AD		 6426 /* fetch next buffer in frame if non-eop */
6427 if (igb_is_non_eop(rx_ring, rx_desc))
6428 continue;
1a1c225b
AD		 6429
6430 /* verify the packet layout is correct */
6431 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6432 skb = NULL;
6433 continue;
9d5c8243 6434 }
9d5c8243 6435
db2ee5bd 6436 /* probably a little skewed due to removing CRC */
3ceb90fd 6437 total_bytes += skb->len;
3ceb90fd 6438
db2ee5bd
AD		 6439 /* populate checksum, timestamp, VLAN, and protocol */
6440 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6441
b2cb09b1 6442 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6443
1a1c225b
AD		 6444 /* reset skb pointer */
6445 skb = NULL;
6446
2e334eee
AD		 6447 /* update budget accounting */
6448 total_packets++;
6449 } while (likely(total_packets < budget));
bf36c1a0 6450
1a1c225b
AD		 6451 /* place incomplete frames back on ring for completion */
6452 rx_ring->skb = skb;
6453
12dcd86b 6454 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6455 rx_ring->rx_stats.packets += total_packets;
6456 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6457 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6458 q_vector->rx.total_packets += total_packets;
6459 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6460
6461 if (cleaned_count)
cd392f5c 6462 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6463
2e334eee 6464 return (total_packets < budget);
9d5c8243
AK		 6465}
6466
c023cd88 6467static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6468 struct igb_rx_buffer *bi)
c023cd88
AD		 6469{
6470 struct page *page = bi->page;
cbc8e55f 6471 dma_addr_t dma;
c023cd88 6472
cbc8e55f
AD		 6473 /* since we are recycling buffers we should seldom need to alloc */
6474 if (likely(page))
c023cd88
AD		 6475 return true;
6476
cbc8e55f
AD		 6477 /* alloc new page for storage */
6478 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6479 if (unlikely(!page)) {
6480 rx_ring->rx_stats.alloc_failed++;
6481 return false;
c023cd88
AD		 6482 }
6483
cbc8e55f
AD		 6484 /* map page for use */
6485 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6486
cbc8e55f
AD		 6487 /*
6488 * if mapping failed free memory back to system since
6489 * there isn't much point in holding memory we can't use
6490 */
1a1c225b 6491 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6492 __free_page(page);
6493
c023cd88
AD		 6494 rx_ring->rx_stats.alloc_failed++;
6495 return false;
6496 }
6497
1a1c225b 6498 bi->dma = dma;
cbc8e55f
AD		 6499 bi->page = page;
6500 bi->page_offset = 0;
1a1c225b 6501
c023cd88
AD		 6502 return true;
6503}
6504
9d5c8243 6505/**
cd392f5c 6506 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6507 * @adapter: address of board private structure
6508 **/
cd392f5c 6509void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6510{
9d5c8243 6511 union e1000_adv_rx_desc *rx_desc;
06034649 6512 struct igb_rx_buffer *bi;
c023cd88 6513 u16 i = rx_ring->next_to_use;
9d5c8243 6514
cbc8e55f
AD		 6515 /* nothing to do */
6516 if (!cleaned_count)
6517 return;
6518
60136906 6519 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6520 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6521 i -= rx_ring->count;
9d5c8243 6522
cbc8e55f 6523 do {
1a1c225b 6524 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6525 break;
9d5c8243 6526
cbc8e55f
AD		 6527 /*
6528 * Refresh the desc even if buffer_addrs didn't change
6529 * because each write-back erases this info.
6530 */
6531 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6532
c023cd88
AD		 6533 rx_desc++;
6534 bi++;
9d5c8243 6535 i++;
c023cd88 6536 if (unlikely(!i)) {
60136906 6537 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6538 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6539 i -= rx_ring->count;
6540 }
6541
6542 /* clear the hdr_addr for the next_to_use descriptor */
6543 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6544
6545 cleaned_count--;
6546 } while (cleaned_count);
9d5c8243 6547
c023cd88
AD		 6548 i += rx_ring->count;
6549
9d5c8243 6550 if (rx_ring->next_to_use != i) {
cbc8e55f 6551 /* record the next descriptor to use */
9d5c8243 6552 rx_ring->next_to_use = i;
9d5c8243 6553
cbc8e55f
AD		 6554 /* update next to alloc since we have filled the ring */
6555 rx_ring->next_to_alloc = i;
6556
6557 /*
6558 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6559 * know there are new descriptors to fetch. (Only
6560 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6561 * such as IA-64).
6562 */
9d5c8243 6563 wmb();
fce99e34 6564 writel(i, rx_ring->tail);
9d5c8243
AK		 6565 }
6566}
6567
6568/**
6569 * igb_mii_ioctl -
6570 * @netdev:
6571 * @ifreq:
6572 * @cmd:
6573 **/
6574static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6575{
6576 struct igb_adapter *adapter = netdev_priv(netdev);
6577 struct mii_ioctl_data *data = if_mii(ifr);
6578
6579 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6580 return -EOPNOTSUPP;
6581
6582 switch (cmd) {
6583 case SIOCGMIIPHY:
6584 data->phy_id = adapter->hw.phy.addr;
6585 break;
6586 case SIOCGMIIREG:
f5f4cf08
AD		 6587 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6588 &data->val_out))
9d5c8243
AK		 6589 return -EIO;
6590 break;
6591 case SIOCSMIIREG:
6592 default:
6593 return -EOPNOTSUPP;
6594 }
6595 return 0;
6596}
6597
6598/**
6599 * igb_ioctl -
6600 * @netdev:
6601 * @ifreq:
6602 * @cmd:
6603 **/
6604static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6605{
6606 switch (cmd) {
6607 case SIOCGMIIPHY:
6608 case SIOCGMIIREG:
6609 case SIOCSMIIREG:
6610 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6611 case SIOCSHWTSTAMP:
a79f4f88 6612 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6613 default:
6614 return -EOPNOTSUPP;
6615 }
6616}
6617
009bc06e
AD		 6618s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6619{
6620 struct igb_adapter *adapter = hw->back;
009bc06e 6621
23d028cc 6622 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6623 return -E1000_ERR_CONFIG;
6624
009bc06e
AD		 6625 return 0;
6626}
6627
6628s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6629{
6630 struct igb_adapter *adapter = hw->back;
009bc06e 6631
23d028cc 6632 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6633 return -E1000_ERR_CONFIG;
6634
009bc06e
AD		 6635 return 0;
6636}
6637
c8f44aff 6638static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6639{
6640 struct igb_adapter *adapter = netdev_priv(netdev);
6641 struct e1000_hw *hw = &adapter->hw;
6642 u32 ctrl, rctl;
5faf030c 6643 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6644
5faf030c 6645 if (enable) {
9d5c8243
AK		 6646 /* enable VLAN tag insert/strip */
6647 ctrl = rd32(E1000_CTRL);
6648 ctrl |= E1000_CTRL_VME;
6649 wr32(E1000_CTRL, ctrl);
6650
51466239 6651 /* Disable CFI check */
9d5c8243 6652 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6653 rctl &= ~E1000_RCTL_CFIEN;
6654 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6655 } else {
6656 /* disable VLAN tag insert/strip */
6657 ctrl = rd32(E1000_CTRL);
6658 ctrl &= ~E1000_CTRL_VME;
6659 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6660 }
6661
e1739522 6662 igb_rlpml_set(adapter);
9d5c8243
AK		 6663}
6664
8e586137 6665static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6666{
6667 struct igb_adapter *adapter = netdev_priv(netdev);
6668 struct e1000_hw *hw = &adapter->hw;
4ae196df 6669 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6670
51466239
AD		 6671 /* attempt to add filter to vlvf array */
6672 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6673
51466239
AD		 6674 /* add the filter since PF can receive vlans w/o entry in vlvf */
6675 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6676
6677 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6678
6679 return 0;
9d5c8243
AK		 6680}
6681
8e586137 6682static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6683{
6684 struct igb_adapter *adapter = netdev_priv(netdev);
6685 struct e1000_hw *hw = &adapter->hw;
4ae196df 6686 int pf_id = adapter->vfs_allocated_count;
51466239 6687 s32 err;
9d5c8243 6688
51466239
AD		 6689 /* remove vlan from VLVF table array */
6690 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6691
51466239
AD		 6692 /* if vid was not present in VLVF just remove it from table */
6693 if (err)
4ae196df 6694 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6695
6696 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6697
6698 return 0;
9d5c8243
AK		 6699}
6700
6701static void igb_restore_vlan(struct igb_adapter *adapter)
6702{
b2cb09b1 6703 u16 vid;
9d5c8243 6704
5faf030c
AD		 6705 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6706
b2cb09b1
JP		 6707 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6708 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6709}
6710
14ad2513 6711int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6712{
090b1795 6713 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6714 struct e1000_mac_info *mac = &adapter->hw.mac;
6715
6716 mac->autoneg = 0;
6717
14ad2513
DD		 6718 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6719 * for the switch() below to work */
6720 if ((spd & 1) || (dplx & ~1))
6721 goto err_inval;
6722
cd2638a8
CW		 6723 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6724 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6725 spd != SPEED_1000 &&
6726 dplx != DUPLEX_FULL)
6727 goto err_inval;
cd2638a8 6728
14ad2513 6729 switch (spd + dplx) {
9d5c8243
AK		 6730 case SPEED_10 + DUPLEX_HALF:
6731 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6732 break;
6733 case SPEED_10 + DUPLEX_FULL:
6734 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6735 break;
6736 case SPEED_100 + DUPLEX_HALF:
6737 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6738 break;
6739 case SPEED_100 + DUPLEX_FULL:
6740 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6741 break;
6742 case SPEED_1000 + DUPLEX_FULL:
6743 mac->autoneg = 1;
6744 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6745 break;
6746 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6747 default:
14ad2513 6748 goto err_inval;
9d5c8243 6749 }
8376dad0
JB		 6750
6751 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6752 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6753
9d5c8243 6754 return 0;
14ad2513
DD		 6755
6756err_inval:
6757 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6758 return -EINVAL;
9d5c8243
AK		 6759}
6760
749ab2cd
YZ		 6761static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6762 bool runtime)
9d5c8243
AK		 6763{
6764 struct net_device *netdev = pci_get_drvdata(pdev);
6765 struct igb_adapter *adapter = netdev_priv(netdev);
6766 struct e1000_hw *hw = &adapter->hw;
2d064c06 6767 u32 ctrl, rctl, status;
749ab2cd 6768 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6769#ifdef CONFIG_PM
6770 int retval = 0;
6771#endif
6772
6773 netif_device_detach(netdev);
6774
a88f10ec 6775 if (netif_running(netdev))
749ab2cd 6776 __igb_close(netdev, true);
a88f10ec 6777
047e0030 6778 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6779
6780#ifdef CONFIG_PM
6781 retval = pci_save_state(pdev);
6782 if (retval)
6783 return retval;
6784#endif
6785
6786 status = rd32(E1000_STATUS);
6787 if (status & E1000_STATUS_LU)
6788 wufc &= ~E1000_WUFC_LNKC;
6789
6790 if (wufc) {
6791 igb_setup_rctl(adapter);
ff41f8dc 6792 igb_set_rx_mode(netdev);
9d5c8243
AK		 6793
6794 /* turn on all-multi mode if wake on multicast is enabled */
6795 if (wufc & E1000_WUFC_MC) {
6796 rctl = rd32(E1000_RCTL);
6797 rctl |= E1000_RCTL_MPE;
6798 wr32(E1000_RCTL, rctl);
6799 }
6800
6801 ctrl = rd32(E1000_CTRL);
6802 /* advertise wake from D3Cold */
6803 #define E1000_CTRL_ADVD3WUC 0x00100000
6804 /* phy power management enable */
6805 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6806 ctrl |= E1000_CTRL_ADVD3WUC;
6807 wr32(E1000_CTRL, ctrl);
6808
9d5c8243 6809 /* Allow time for pending master requests to run */
330a6d6a 6810 igb_disable_pcie_master(hw);
9d5c8243
AK		 6811
6812 wr32(E1000_WUC, E1000_WUC_PME_EN);
6813 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6814 } else {
6815 wr32(E1000_WUC, 0);
6816 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6817 }
6818
3fe7c4c9
RW		 6819 *enable_wake = wufc || adapter->en_mng_pt;
6820 if (!*enable_wake)
88a268c1
NN		 6821 igb_power_down_link(adapter);
6822 else
6823 igb_power_up_link(adapter);
9d5c8243
AK		 6824
6825 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6826 * would have already happened in close and is redundant. */
6827 igb_release_hw_control(adapter);
6828
6829 pci_disable_device(pdev);
6830
9d5c8243
AK		 6831 return 0;
6832}
6833
6834#ifdef CONFIG_PM
d9dd966d 6835#ifdef CONFIG_PM_SLEEP
749ab2cd 6836static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6837{
6838 int retval;
6839 bool wake;
749ab2cd 6840 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6841
749ab2cd 6842 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6843 if (retval)
6844 return retval;
6845
6846 if (wake) {
6847 pci_prepare_to_sleep(pdev);
6848 } else {
6849 pci_wake_from_d3(pdev, false);
6850 pci_set_power_state(pdev, PCI_D3hot);
6851 }
6852
6853 return 0;
6854}
d9dd966d 6855#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6856
749ab2cd 6857static int igb_resume(struct device *dev)
9d5c8243 6858{
749ab2cd 6859 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6860 struct net_device *netdev = pci_get_drvdata(pdev);
6861 struct igb_adapter *adapter = netdev_priv(netdev);
6862 struct e1000_hw *hw = &adapter->hw;
6863 u32 err;
6864
6865 pci_set_power_state(pdev, PCI_D0);
6866 pci_restore_state(pdev);
b94f2d77 6867 pci_save_state(pdev);
42bfd33a 6868
aed5dec3 6869 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6870 if (err) {
6871 dev_err(&pdev->dev,
6872 "igb: Cannot enable PCI device from suspend\n");
6873 return err;
6874 }
6875 pci_set_master(pdev);
6876
6877 pci_enable_wake(pdev, PCI_D3hot, 0);
6878 pci_enable_wake(pdev, PCI_D3cold, 0);
6879
53c7d064 6880 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 6881 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6882 return -ENOMEM;
9d5c8243
AK		 6883 }
6884
9d5c8243 6885 igb_reset(adapter);
a8564f03
AD		 6886
6887 /* let the f/w know that the h/w is now under the control of the
6888 * driver. */
6889 igb_get_hw_control(adapter);
6890
9d5c8243
AK		 6891 wr32(E1000_WUS, ~0);
6892
749ab2cd 6893 if (netdev->flags & IFF_UP) {
0c2cc02e 6894 rtnl_lock();
749ab2cd 6895 err = __igb_open(netdev, true);
0c2cc02e 6896 rtnl_unlock();
a88f10ec
AD		 6897 if (err)
6898 return err;
6899 }
9d5c8243
AK		 6900
6901 netif_device_attach(netdev);
749ab2cd
YZ		 6902 return 0;
6903}
6904
6905#ifdef CONFIG_PM_RUNTIME
6906static int igb_runtime_idle(struct device *dev)
6907{
6908 struct pci_dev *pdev = to_pci_dev(dev);
6909 struct net_device *netdev = pci_get_drvdata(pdev);
6910 struct igb_adapter *adapter = netdev_priv(netdev);
6911
6912 if (!igb_has_link(adapter))
6913 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6914
6915 return -EBUSY;
6916}
6917
6918static int igb_runtime_suspend(struct device *dev)
6919{
6920 struct pci_dev *pdev = to_pci_dev(dev);
6921 int retval;
6922 bool wake;
6923
6924 retval = __igb_shutdown(pdev, &wake, 1);
6925 if (retval)
6926 return retval;
6927
6928 if (wake) {
6929 pci_prepare_to_sleep(pdev);
6930 } else {
6931 pci_wake_from_d3(pdev, false);
6932 pci_set_power_state(pdev, PCI_D3hot);
6933 }
9d5c8243 6934
9d5c8243
AK		 6935 return 0;
6936}
749ab2cd
YZ		 6937
6938static int igb_runtime_resume(struct device *dev)
6939{
6940 return igb_resume(dev);
6941}
6942#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 6943#endif
6944
6945static void igb_shutdown(struct pci_dev *pdev)
6946{
3fe7c4c9
RW		 6947 bool wake;
6948
749ab2cd 6949 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6950
6951 if (system_state == SYSTEM_POWER_OFF) {
6952 pci_wake_from_d3(pdev, wake);
6953 pci_set_power_state(pdev, PCI_D3hot);
6954 }
9d5c8243
AK		 6955}
6956
fa44f2f1
GR		 6957#ifdef CONFIG_PCI_IOV
6958static int igb_sriov_reinit(struct pci_dev *dev)
6959{
6960 struct net_device *netdev = pci_get_drvdata(dev);
6961 struct igb_adapter *adapter = netdev_priv(netdev);
6962 struct pci_dev *pdev = adapter->pdev;
6963
6964 rtnl_lock();
6965
6966 if (netif_running(netdev))
6967 igb_close(netdev);
6968
6969 igb_clear_interrupt_scheme(adapter);
6970
6971 igb_init_queue_configuration(adapter);
6972
6973 if (igb_init_interrupt_scheme(adapter, true)) {
6974 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6975 return -ENOMEM;
6976 }
6977
6978 if (netif_running(netdev))
6979 igb_open(netdev);
6980
6981 rtnl_unlock();
6982
6983 return 0;
6984}
6985
6986static int igb_pci_disable_sriov(struct pci_dev *dev)
6987{
6988 int err = igb_disable_sriov(dev);
6989
6990 if (!err)
6991 err = igb_sriov_reinit(dev);
6992
6993 return err;
6994}
6995
6996static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
6997{
6998 int err = igb_enable_sriov(dev, num_vfs);
6999
7000 if (err)
7001 goto out;
7002
7003 err = igb_sriov_reinit(dev);
7004 if (!err)
7005 return num_vfs;
7006
7007out:
7008 return err;
7009}
7010
7011#endif
7012static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7013{
7014#ifdef CONFIG_PCI_IOV
7015 if (num_vfs == 0)
7016 return igb_pci_disable_sriov(dev);
7017 else
7018 return igb_pci_enable_sriov(dev, num_vfs);
7019#endif
7020 return 0;
7021}
7022
9d5c8243
AK		 7023#ifdef CONFIG_NET_POLL_CONTROLLER
7024/*
7025 * Polling 'interrupt' - used by things like netconsole to send skbs
7026 * without having to re-enable interrupts. It's not called while
7027 * the interrupt routine is executing.
7028 */
7029static void igb_netpoll(struct net_device *netdev)
7030{
7031 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7032 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7033 struct igb_q_vector *q_vector;
9d5c8243 7034 int i;
9d5c8243 7035
047e0030 7036 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7037 q_vector = adapter->q_vector[i];
7038 if (adapter->msix_entries)
7039 wr32(E1000_EIMC, q_vector->eims_value);
7040 else
7041 igb_irq_disable(adapter);
047e0030 7042 napi_schedule(&q_vector->napi);
eebbbdba 7043 }
9d5c8243
AK		 7044}
7045#endif /* CONFIG_NET_POLL_CONTROLLER */
7046
7047/**
7048 * igb_io_error_detected - called when PCI error is detected
7049 * @pdev: Pointer to PCI device
7050 * @state: The current pci connection state
7051 *
7052 * This function is called after a PCI bus error affecting
7053 * this device has been detected.
7054 */
7055static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7056 pci_channel_state_t state)
7057{
7058 struct net_device *netdev = pci_get_drvdata(pdev);
7059 struct igb_adapter *adapter = netdev_priv(netdev);
7060
7061 netif_device_detach(netdev);
7062
59ed6eec
AD		 7063 if (state == pci_channel_io_perm_failure)
7064 return PCI_ERS_RESULT_DISCONNECT;
7065
9d5c8243
AK		 7066 if (netif_running(netdev))
7067 igb_down(adapter);
7068 pci_disable_device(pdev);
7069
7070 /* Request a slot slot reset. */
7071 return PCI_ERS_RESULT_NEED_RESET;
7072}
7073
7074/**
7075 * igb_io_slot_reset - called after the pci bus has been reset.
7076 * @pdev: Pointer to PCI device
7077 *
7078 * Restart the card from scratch, as if from a cold-boot. Implementation
7079 * resembles the first-half of the igb_resume routine.
7080 */
7081static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7082{
7083 struct net_device *netdev = pci_get_drvdata(pdev);
7084 struct igb_adapter *adapter = netdev_priv(netdev);
7085 struct e1000_hw *hw = &adapter->hw;
40a914fa 7086 pci_ers_result_t result;
42bfd33a 7087 int err;
9d5c8243 7088
aed5dec3 7089 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7090 dev_err(&pdev->dev,
7091 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7092 result = PCI_ERS_RESULT_DISCONNECT;
7093 } else {
7094 pci_set_master(pdev);
7095 pci_restore_state(pdev);
b94f2d77 7096 pci_save_state(pdev);
9d5c8243 7097
40a914fa
AD		 7098 pci_enable_wake(pdev, PCI_D3hot, 0);
7099 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7100
40a914fa
AD		 7101 igb_reset(adapter);
7102 wr32(E1000_WUS, ~0);
7103 result = PCI_ERS_RESULT_RECOVERED;
7104 }
9d5c8243 7105
ea943d41
JK		 7106 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7107 if (err) {
7108 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7109 "failed 0x%0x\n", err);
7110 /* non-fatal, continue */
7111 }
40a914fa
AD		 7112
7113 return result;
9d5c8243
AK		 7114}
7115
7116/**
7117 * igb_io_resume - called when traffic can start flowing again.
7118 * @pdev: Pointer to PCI device
7119 *
7120 * This callback is called when the error recovery driver tells us that
7121 * its OK to resume normal operation. Implementation resembles the
7122 * second-half of the igb_resume routine.
7123 */
7124static void igb_io_resume(struct pci_dev *pdev)
7125{
7126 struct net_device *netdev = pci_get_drvdata(pdev);
7127 struct igb_adapter *adapter = netdev_priv(netdev);
7128
9d5c8243
AK		 7129 if (netif_running(netdev)) {
7130 if (igb_up(adapter)) {
7131 dev_err(&pdev->dev, "igb_up failed after reset\n");
7132 return;
7133 }
7134 }
7135
7136 netif_device_attach(netdev);
7137
7138 /* let the f/w know that the h/w is now under the control of the
7139 * driver. */
7140 igb_get_hw_control(adapter);
9d5c8243
AK		 7141}
7142
26ad9178
AD		 7143static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7144 u8 qsel)
7145{
7146 u32 rar_low, rar_high;
7147 struct e1000_hw *hw = &adapter->hw;
7148
7149 /* HW expects these in little endian so we reverse the byte order
7150 * from network order (big endian) to little endian
7151 */
7152 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7153 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7154 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7155
7156 /* Indicate to hardware the Address is Valid. */
7157 rar_high |= E1000_RAH_AV;
7158
7159 if (hw->mac.type == e1000_82575)
7160 rar_high |= E1000_RAH_POOL_1 * qsel;
7161 else
7162 rar_high |= E1000_RAH_POOL_1 << qsel;
7163
7164 wr32(E1000_RAL(index), rar_low);
7165 wrfl();
7166 wr32(E1000_RAH(index), rar_high);
7167 wrfl();
7168}
7169
4ae196df
AD		 7170static int igb_set_vf_mac(struct igb_adapter *adapter,
7171 int vf, unsigned char *mac_addr)
7172{
7173 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7174 /* VF MAC addresses start at end of receive addresses and moves
7175 * torwards the first, as a result a collision should not be possible */
7176 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7177
37680117 7178 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7179
26ad9178 7180 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7181
7182 return 0;
7183}
7184
8151d294
WM		 7185static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7186{
7187 struct igb_adapter *adapter = netdev_priv(netdev);
7188 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7189 return -EINVAL;
7190 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7191 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7192 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7193 " change effective.");
7194 if (test_bit(__IGB_DOWN, &adapter->state)) {
7195 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7196 " but the PF device is not up.\n");
7197 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7198 " attempting to use the VF device.\n");
7199 }
7200 return igb_set_vf_mac(adapter, vf, mac);
7201}
7202
17dc566c
LL		 7203static int igb_link_mbps(int internal_link_speed)
7204{
7205 switch (internal_link_speed) {
7206 case SPEED_100:
7207 return 100;
7208 case SPEED_1000:
7209 return 1000;
7210 default:
7211 return 0;
7212 }
7213}
7214
7215static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7216 int link_speed)
7217{
7218 int rf_dec, rf_int;
7219 u32 bcnrc_val;
7220
7221 if (tx_rate != 0) {
7222 /* Calculate the rate factor values to set */
7223 rf_int = link_speed / tx_rate;
7224 rf_dec = (link_speed - (rf_int * tx_rate));
7225 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7226
7227 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7228 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7229 E1000_RTTBCNRC_RF_INT_MASK);
7230 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7231 } else {
7232 bcnrc_val = 0;
7233 }
7234
7235 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7236 /*
7237 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7238 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7239 */
7240 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7241 wr32(E1000_RTTBCNRC, bcnrc_val);
7242}
7243
7244static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7245{
7246 int actual_link_speed, i;
7247 bool reset_rate = false;
7248
7249 /* VF TX rate limit was not set or not supported */
7250 if ((adapter->vf_rate_link_speed == 0) ||
7251 (adapter->hw.mac.type != e1000_82576))
7252 return;
7253
7254 actual_link_speed = igb_link_mbps(adapter->link_speed);
7255 if (actual_link_speed != adapter->vf_rate_link_speed) {
7256 reset_rate = true;
7257 adapter->vf_rate_link_speed = 0;
7258 dev_info(&adapter->pdev->dev,
7259 "Link speed has been changed. VF Transmit "
7260 "rate is disabled\n");
7261 }
7262
7263 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7264 if (reset_rate)
7265 adapter->vf_data[i].tx_rate = 0;
7266
7267 igb_set_vf_rate_limit(&adapter->hw, i,
7268 adapter->vf_data[i].tx_rate,
7269 actual_link_speed);
7270 }
7271}
7272
8151d294
WM		 7273static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7274{
17dc566c
LL		 7275 struct igb_adapter *adapter = netdev_priv(netdev);
7276 struct e1000_hw *hw = &adapter->hw;
7277 int actual_link_speed;
7278
7279 if (hw->mac.type != e1000_82576)
7280 return -EOPNOTSUPP;
7281
7282 actual_link_speed = igb_link_mbps(adapter->link_speed);
7283 if ((vf >= adapter->vfs_allocated_count) ||
7284 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7285 (tx_rate < 0) || (tx_rate > actual_link_speed))
7286 return -EINVAL;
7287
7288 adapter->vf_rate_link_speed = actual_link_speed;
7289 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7290 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7291
7292 return 0;
8151d294
WM		 7293}
7294
7295static int igb_ndo_get_vf_config(struct net_device *netdev,
7296 int vf, struct ifla_vf_info *ivi)
7297{
7298 struct igb_adapter *adapter = netdev_priv(netdev);
7299 if (vf >= adapter->vfs_allocated_count)
7300 return -EINVAL;
7301 ivi->vf = vf;
7302 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7303 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7304 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7305 ivi->qos = adapter->vf_data[vf].pf_qos;
7306 return 0;
7307}
7308
4ae196df
AD		 7309static void igb_vmm_control(struct igb_adapter *adapter)
7310{
7311 struct e1000_hw *hw = &adapter->hw;
10d8e907 7312 u32 reg;
4ae196df 7313
52a1dd4d
AD		 7314 switch (hw->mac.type) {
7315 case e1000_82575:
f96a8a0b
CW		 7316 case e1000_i210:
7317 case e1000_i211:
52a1dd4d
AD		 7318 default:
7319 /* replication is not supported for 82575 */
4ae196df 7320 return;
52a1dd4d
AD		 7321 case e1000_82576:
7322 /* notify HW that the MAC is adding vlan tags */
7323 reg = rd32(E1000_DTXCTL);
7324 reg |= E1000_DTXCTL_VLAN_ADDED;
7325 wr32(E1000_DTXCTL, reg);
7326 case e1000_82580:
7327 /* enable replication vlan tag stripping */
7328 reg = rd32(E1000_RPLOLR);
7329 reg |= E1000_RPLOLR_STRVLAN;
7330 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7331 case e1000_i350:
7332 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7333 break;
7334 }
10d8e907 7335
d4960307
AD		 7336 if (adapter->vfs_allocated_count) {
7337 igb_vmdq_set_loopback_pf(hw, true);
7338 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7339 igb_vmdq_set_anti_spoofing_pf(hw, true,
7340 adapter->vfs_allocated_count);
d4960307
AD		 7341 } else {
7342 igb_vmdq_set_loopback_pf(hw, false);
7343 igb_vmdq_set_replication_pf(hw, false);
7344 }
4ae196df
AD		 7345}
7346
b6e0c419
CW		 7347static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7348{
7349 struct e1000_hw *hw = &adapter->hw;
7350 u32 dmac_thr;
7351 u16 hwm;
7352
7353 if (hw->mac.type > e1000_82580) {
7354 if (adapter->flags & IGB_FLAG_DMAC) {
7355 u32 reg;
7356
7357 /* force threshold to 0. */
7358 wr32(E1000_DMCTXTH, 0);
7359
7360 /*
e8c626e9
MV		 7361 * DMA Coalescing high water mark needs to be greater
7362 * than the Rx threshold. Set hwm to PBA - max frame
7363 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7364 */
e8c626e9
MV		 7365 hwm = 64 * pba - adapter->max_frame_size / 16;
7366 if (hwm < 64 * (pba - 6))
7367 hwm = 64 * (pba - 6);
7368 reg = rd32(E1000_FCRTC);
7369 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7370 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7371 & E1000_FCRTC_RTH_COAL_MASK);
7372 wr32(E1000_FCRTC, reg);
7373
7374 /*
7375 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7376 * frame size, capping it at PBA - 10KB.
7377 */
7378 dmac_thr = pba - adapter->max_frame_size / 512;
7379 if (dmac_thr < pba - 10)
7380 dmac_thr = pba - 10;
b6e0c419
CW		 7381 reg = rd32(E1000_DMACR);
7382 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7383 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7384 & E1000_DMACR_DMACTHR_MASK);
7385
7386 /* transition to L0x or L1 if available..*/
7387 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7388
7389 /* watchdog timer= +-1000 usec in 32usec intervals */
7390 reg |= (1000 >> 5);
0c02dd98
MV		 7391
7392 /* Disable BMC-to-OS Watchdog Enable */
7393 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7394 wr32(E1000_DMACR, reg);
7395
7396 /*
7397 * no lower threshold to disable
7398 * coalescing(smart fifb)-UTRESH=0
7399 */
7400 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7401
7402 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7403
7404 wr32(E1000_DMCTLX, reg);
7405
7406 /*
7407 * free space in tx packet buffer to wake from
7408 * DMA coal
7409 */
7410 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7411 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7412
7413 /*
7414 * make low power state decision controlled
7415 * by DMA coal
7416 */
7417 reg = rd32(E1000_PCIEMISC);
7418 reg &= ~E1000_PCIEMISC_LX_DECISION;
7419 wr32(E1000_PCIEMISC, reg);
7420 } /* endif adapter->dmac is not disabled */
7421 } else if (hw->mac.type == e1000_82580) {
7422 u32 reg = rd32(E1000_PCIEMISC);
7423 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7424 wr32(E1000_DMACR, 0);
7425 }
7426}
7427
9d5c8243 7428/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)