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igb: Add support for byte queue limits.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4297f99b 4 Copyright(c) 2007-2011 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
421e02f0 56#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 57#include <linux/dca.h>
58#endif
9d5c8243
AK		 59#include "igb.h"
60
0d1fe82d 61#define MAJ 3
a28dc43f
CW		 62#define MIN 2
63#define BUILD 10
0d1fe82d 64#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 65__stringify(BUILD) "-k"
9d5c8243
AK		 66char igb_driver_name[] = "igb";
67char igb_driver_version[] = DRV_VERSION;
68static const char igb_driver_string[] =
69 "Intel(R) Gigabit Ethernet Network Driver";
4c4b42cb 70static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
9d5c8243 71
9d5c8243
AK		 72static const struct e1000_info *igb_info_tbl[] = {
73 [board_82575] = &e1000_82575_info,
74};
75
a3aa1884 76static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
d2ba2ed8
AD		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
102 /* required last entry */
103 {0, }
104};
105
106MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
107
108void igb_reset(struct igb_adapter *);
109static int igb_setup_all_tx_resources(struct igb_adapter *);
110static int igb_setup_all_rx_resources(struct igb_adapter *);
111static void igb_free_all_tx_resources(struct igb_adapter *);
112static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 113static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 114static int igb_probe(struct pci_dev *, const struct pci_device_id *);
115static void __devexit igb_remove(struct pci_dev *pdev);
673b8b70 116static void igb_init_hw_timer(struct igb_adapter *adapter);
9d5c8243
AK		 117static int igb_sw_init(struct igb_adapter *);
118static int igb_open(struct net_device *);
119static int igb_close(struct net_device *);
120static void igb_configure_tx(struct igb_adapter *);
121static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 122static void igb_clean_all_tx_rings(struct igb_adapter *);
123static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 124static void igb_clean_tx_ring(struct igb_ring *);
125static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 126static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 127static void igb_update_phy_info(unsigned long);
128static void igb_watchdog(unsigned long);
129static void igb_watchdog_task(struct work_struct *);
cd392f5c 130static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 131static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
132 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 133static int igb_change_mtu(struct net_device *, int);
134static int igb_set_mac(struct net_device *, void *);
68d480c4 135static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 136static irqreturn_t igb_intr(int irq, void *);
137static irqreturn_t igb_intr_msi(int irq, void *);
138static irqreturn_t igb_msix_other(int irq, void *);
047e0030 139static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 140#ifdef CONFIG_IGB_DCA
047e0030 141static void igb_update_dca(struct igb_q_vector *);
fe4506b6 142static void igb_setup_dca(struct igb_adapter *);
421e02f0 143#endif /* CONFIG_IGB_DCA */
661086df 144static int igb_poll(struct napi_struct *, int);
13fde97a 145static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 146static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 147static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
148static void igb_tx_timeout(struct net_device *);
149static void igb_reset_task(struct work_struct *);
c8f44aff 150static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 151static int igb_vlan_rx_add_vid(struct net_device *, u16);
152static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 153static void igb_restore_vlan(struct igb_adapter *);
26ad9178 154static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 155static void igb_ping_all_vfs(struct igb_adapter *);
156static void igb_msg_task(struct igb_adapter *);
4ae196df 157static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 158static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 159static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 160static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
161static int igb_ndo_set_vf_vlan(struct net_device *netdev,
162 int vf, u16 vlan, u8 qos);
163static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
164static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
165 struct ifla_vf_info *ivi);
17dc566c 166static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 167
168#ifdef CONFIG_PCI_IOV
0224d663
GR		 169static int igb_vf_configure(struct igb_adapter *adapter, int vf);
170static int igb_find_enabled_vfs(struct igb_adapter *adapter);
171static int igb_check_vf_assignment(struct igb_adapter *adapter);
46a01698 172#endif
9d5c8243 173
9d5c8243 174#ifdef CONFIG_PM
3fe7c4c9 175static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 176static int igb_resume(struct pci_dev *);
177#endif
178static void igb_shutdown(struct pci_dev *);
421e02f0 179#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 180static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
181static struct notifier_block dca_notifier = {
182 .notifier_call = igb_notify_dca,
183 .next = NULL,
184 .priority = 0
185};
186#endif
9d5c8243
AK		 187#ifdef CONFIG_NET_POLL_CONTROLLER
188/* for netdump / net console */
189static void igb_netpoll(struct net_device *);
190#endif
37680117 191#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 192static unsigned int max_vfs = 0;
193module_param(max_vfs, uint, 0);
194MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
195 "per physical function");
196#endif /* CONFIG_PCI_IOV */
197
9d5c8243
AK		 198static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
199 pci_channel_state_t);
200static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
201static void igb_io_resume(struct pci_dev *);
202
203static struct pci_error_handlers igb_err_handler = {
204 .error_detected = igb_io_error_detected,
205 .slot_reset = igb_io_slot_reset,
206 .resume = igb_io_resume,
207};
208
b6e0c419 209static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 210
211static struct pci_driver igb_driver = {
212 .name = igb_driver_name,
213 .id_table = igb_pci_tbl,
214 .probe = igb_probe,
215 .remove = __devexit_p(igb_remove),
216#ifdef CONFIG_PM
25985edc 217 /* Power Management Hooks */
9d5c8243
AK		 218 .suspend = igb_suspend,
219 .resume = igb_resume,
220#endif
221 .shutdown = igb_shutdown,
222 .err_handler = &igb_err_handler
223};
224
225MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
226MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_VERSION);
229
c97ec42a
TI		 230struct igb_reg_info {
231 u32 ofs;
232 char *name;
233};
234
235static const struct igb_reg_info igb_reg_info_tbl[] = {
236
237 /* General Registers */
238 {E1000_CTRL, "CTRL"},
239 {E1000_STATUS, "STATUS"},
240 {E1000_CTRL_EXT, "CTRL_EXT"},
241
242 /* Interrupt Registers */
243 {E1000_ICR, "ICR"},
244
245 /* RX Registers */
246 {E1000_RCTL, "RCTL"},
247 {E1000_RDLEN(0), "RDLEN"},
248 {E1000_RDH(0), "RDH"},
249 {E1000_RDT(0), "RDT"},
250 {E1000_RXDCTL(0), "RXDCTL"},
251 {E1000_RDBAL(0), "RDBAL"},
252 {E1000_RDBAH(0), "RDBAH"},
253
254 /* TX Registers */
255 {E1000_TCTL, "TCTL"},
256 {E1000_TDBAL(0), "TDBAL"},
257 {E1000_TDBAH(0), "TDBAH"},
258 {E1000_TDLEN(0), "TDLEN"},
259 {E1000_TDH(0), "TDH"},
260 {E1000_TDT(0), "TDT"},
261 {E1000_TXDCTL(0), "TXDCTL"},
262 {E1000_TDFH, "TDFH"},
263 {E1000_TDFT, "TDFT"},
264 {E1000_TDFHS, "TDFHS"},
265 {E1000_TDFPC, "TDFPC"},
266
267 /* List Terminator */
268 {}
269};
270
271/*
272 * igb_regdump - register printout routine
273 */
274static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
275{
276 int n = 0;
277 char rname[16];
278 u32 regs[8];
279
280 switch (reginfo->ofs) {
281 case E1000_RDLEN(0):
282 for (n = 0; n < 4; n++)
283 regs[n] = rd32(E1000_RDLEN(n));
284 break;
285 case E1000_RDH(0):
286 for (n = 0; n < 4; n++)
287 regs[n] = rd32(E1000_RDH(n));
288 break;
289 case E1000_RDT(0):
290 for (n = 0; n < 4; n++)
291 regs[n] = rd32(E1000_RDT(n));
292 break;
293 case E1000_RXDCTL(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RXDCTL(n));
296 break;
297 case E1000_RDBAL(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_RDBAL(n));
300 break;
301 case E1000_RDBAH(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDBAH(n));
304 break;
305 case E1000_TDBAL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDBAL(n));
308 break;
309 case E1000_TDBAH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_TDBAH(n));
312 break;
313 case E1000_TDLEN(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_TDLEN(n));
316 break;
317 case E1000_TDH(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_TDH(n));
320 break;
321 case E1000_TDT(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_TDT(n));
324 break;
325 case E1000_TXDCTL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_TXDCTL(n));
328 break;
329 default:
876d2d6f 330 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 331 return;
332 }
333
334 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 335 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
336 regs[2], regs[3]);
c97ec42a
TI		 337}
338
339/*
340 * igb_dump - Print registers, tx-rings and rx-rings
341 */
342static void igb_dump(struct igb_adapter *adapter)
343{
344 struct net_device *netdev = adapter->netdev;
345 struct e1000_hw *hw = &adapter->hw;
346 struct igb_reg_info *reginfo;
c97ec42a
TI		 347 struct igb_ring *tx_ring;
348 union e1000_adv_tx_desc *tx_desc;
349 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 350 struct igb_ring *rx_ring;
351 union e1000_adv_rx_desc *rx_desc;
352 u32 staterr;
6ad4edfc 353 u16 i, n;
c97ec42a
TI		 354
355 if (!netif_msg_hw(adapter))
356 return;
357
358 /* Print netdevice Info */
359 if (netdev) {
360 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 361 pr_info("Device Name state trans_start "
362 "last_rx\n");
363 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
364 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 365 }
366
367 /* Print Registers */
368 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 369 pr_info(" Register Name Value\n");
c97ec42a
TI		 370 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
371 reginfo->name; reginfo++) {
372 igb_regdump(hw, reginfo);
373 }
374
375 /* Print TX Ring Summary */
376 if (!netdev || !netif_running(netdev))
377 goto exit;
378
379 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 380 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 381 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 382 struct igb_tx_buffer *buffer_info;
c97ec42a 383 tx_ring = adapter->tx_ring[n];
06034649 384 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 385 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
386 n, tx_ring->next_to_use, tx_ring->next_to_clean,
387 (u64)buffer_info->dma,
388 buffer_info->length,
389 buffer_info->next_to_watch,
390 (u64)buffer_info->time_stamp);
c97ec42a
TI		 391 }
392
393 /* Print TX Rings */
394 if (!netif_msg_tx_done(adapter))
395 goto rx_ring_summary;
396
397 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
398
399 /* Transmit Descriptor Formats
400 *
401 * Advanced Transmit Descriptor
402 * +--------------------------------------------------------------+
403 * 0 | Buffer Address [63:0] |
404 * +--------------------------------------------------------------+
405 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
406 * +--------------------------------------------------------------+
407 * 63 46 45 40 39 38 36 35 32 31 24 15 0
408 */
409
410 for (n = 0; n < adapter->num_tx_queues; n++) {
411 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 412 pr_info("------------------------------------\n");
413 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
414 pr_info("------------------------------------\n");
415 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
416 "[bi->dma ] leng ntw timestamp "
417 "bi->skb\n");
c97ec42a
TI		 418
419 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 420 const char *next_desc;
06034649 421 struct igb_tx_buffer *buffer_info;
60136906 422 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 423 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 424 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 425 if (i == tx_ring->next_to_use &&
426 i == tx_ring->next_to_clean)
427 next_desc = " NTC/U";
428 else if (i == tx_ring->next_to_use)
429 next_desc = " NTU";
430 else if (i == tx_ring->next_to_clean)
431 next_desc = " NTC";
432 else
433 next_desc = "";
434
435 pr_info("T [0x%03X] %016llX %016llX %016llX"
436 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 437 le64_to_cpu(u0->a),
438 le64_to_cpu(u0->b),
439 (u64)buffer_info->dma,
440 buffer_info->length,
441 buffer_info->next_to_watch,
442 (u64)buffer_info->time_stamp,
876d2d6f 443 buffer_info->skb, next_desc);
c97ec42a
TI		 444
445 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
446 print_hex_dump(KERN_INFO, "",
447 DUMP_PREFIX_ADDRESS,
448 16, 1, phys_to_virt(buffer_info->dma),
449 buffer_info->length, true);
450 }
451 }
452
453 /* Print RX Rings Summary */
454rx_ring_summary:
455 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 456 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 457 for (n = 0; n < adapter->num_rx_queues; n++) {
458 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 459 pr_info(" %5d %5X %5X\n",
460 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 461 }
462
463 /* Print RX Rings */
464 if (!netif_msg_rx_status(adapter))
465 goto exit;
466
467 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
468
469 /* Advanced Receive Descriptor (Read) Format
470 * 63 1 0
471 * +-----------------------------------------------------+
472 * 0 | Packet Buffer Address [63:1] |A0/NSE|
473 * +----------------------------------------------+------+
474 * 8 | Header Buffer Address [63:1] | DD |
475 * +-----------------------------------------------------+
476 *
477 *
478 * Advanced Receive Descriptor (Write-Back) Format
479 *
480 * 63 48 47 32 31 30 21 20 17 16 4 3 0
481 * +------------------------------------------------------+
482 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
483 * | Checksum Ident | | | | Type | Type |
484 * +------------------------------------------------------+
485 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
486 * +------------------------------------------------------+
487 * 63 48 47 32 31 20 19 0
488 */
489
490 for (n = 0; n < adapter->num_rx_queues; n++) {
491 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 492 pr_info("------------------------------------\n");
493 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
494 pr_info("------------------------------------\n");
495 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
496 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
497 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
498 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 499
500 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 501 const char *next_desc;
06034649
AD		 502 struct igb_rx_buffer *buffer_info;
503 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 504 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 505 u0 = (struct my_u0 *)rx_desc;
506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 507
508 if (i == rx_ring->next_to_use)
509 next_desc = " NTU";
510 else if (i == rx_ring->next_to_clean)
511 next_desc = " NTC";
512 else
513 next_desc = "";
514
c97ec42a
TI		 515 if (staterr & E1000_RXD_STAT_DD) {
516 /* Descriptor Done */
876d2d6f
JK		 517 pr_info("%s[0x%03X] %016llX %016llX -------"
518 "--------- %p%s\n", "RWB", i,
c97ec42a
TI		 519 le64_to_cpu(u0->a),
520 le64_to_cpu(u0->b),
876d2d6f 521 buffer_info->skb, next_desc);
c97ec42a 522 } else {
876d2d6f
JK		 523 pr_info("%s[0x%03X] %016llX %016llX %016llX"
524 " %p%s\n", "R ", i,
c97ec42a
TI		 525 le64_to_cpu(u0->a),
526 le64_to_cpu(u0->b),
527 (u64)buffer_info->dma,
876d2d6f 528 buffer_info->skb, next_desc);
c97ec42a
TI		 529
530 if (netif_msg_pktdata(adapter)) {
531 print_hex_dump(KERN_INFO, "",
532 DUMP_PREFIX_ADDRESS,
533 16, 1,
534 phys_to_virt(buffer_info->dma),
44390ca6
AD		 535 IGB_RX_HDR_LEN, true);
536 print_hex_dump(KERN_INFO, "",
537 DUMP_PREFIX_ADDRESS,
538 16, 1,
539 phys_to_virt(
540 buffer_info->page_dma +
541 buffer_info->page_offset),
542 PAGE_SIZE/2, true);
c97ec42a
TI		 543 }
544 }
c97ec42a
TI		 545 }
546 }
547
548exit:
549 return;
550}
551
552
38c845c7
PO		 553/**
554 * igb_read_clock - read raw cycle counter (to be used by time counter)
555 */
556static cycle_t igb_read_clock(const struct cyclecounter *tc)
557{
558 struct igb_adapter *adapter =
559 container_of(tc, struct igb_adapter, cycles);
560 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 561 u64 stamp = 0;
562 int shift = 0;
38c845c7 563
55cac248
AD		 564 /*
565 * The timestamp latches on lowest register read. For the 82580
566 * the lowest register is SYSTIMR instead of SYSTIML. However we never
567 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
568 */
06218a8d 569 if (hw->mac.type >= e1000_82580) {
55cac248
AD		 570 stamp = rd32(E1000_SYSTIMR) >> 8;
571 shift = IGB_82580_TSYNC_SHIFT;
572 }
573
c5b9bd5e
AD		 574 stamp |= (u64)rd32(E1000_SYSTIML) << shift;
575 stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
38c845c7
PO		 576 return stamp;
577}
578
9d5c8243 579/**
c041076a 580 * igb_get_hw_dev - return device
9d5c8243
AK		 581 * used by hardware layer to print debugging information
582 **/
c041076a 583struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 584{
585 struct igb_adapter *adapter = hw->back;
c041076a 586 return adapter->netdev;
9d5c8243 587}
38c845c7 588
9d5c8243
AK		 589/**
590 * igb_init_module - Driver Registration Routine
591 *
592 * igb_init_module is the first routine called when the driver is
593 * loaded. All it does is register with the PCI subsystem.
594 **/
595static int __init igb_init_module(void)
596{
597 int ret;
876d2d6f 598 pr_info("%s - version %s\n",
9d5c8243
AK		 599 igb_driver_string, igb_driver_version);
600
876d2d6f 601 pr_info("%s\n", igb_copyright);
9d5c8243 602
421e02f0 603#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 604 dca_register_notify(&dca_notifier);
605#endif
bbd98fe4 606 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 607 return ret;
608}
609
610module_init(igb_init_module);
611
612/**
613 * igb_exit_module - Driver Exit Cleanup Routine
614 *
615 * igb_exit_module is called just before the driver is removed
616 * from memory.
617 **/
618static void __exit igb_exit_module(void)
619{
421e02f0 620#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 621 dca_unregister_notify(&dca_notifier);
622#endif
9d5c8243
AK		 623 pci_unregister_driver(&igb_driver);
624}
625
626module_exit(igb_exit_module);
627
26bc19ec
AD		 628#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
629/**
630 * igb_cache_ring_register - Descriptor ring to register mapping
631 * @adapter: board private structure to initialize
632 *
633 * Once we know the feature-set enabled for the device, we'll cache
634 * the register offset the descriptor ring is assigned to.
635 **/
636static void igb_cache_ring_register(struct igb_adapter *adapter)
637{
ee1b9f06 638 int i = 0, j = 0;
047e0030 639 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 640
641 switch (adapter->hw.mac.type) {
642 case e1000_82576:
643 /* The queues are allocated for virtualization such that VF 0
644 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
645 * In order to avoid collision we start at the first free queue
646 * and continue consuming queues in the same sequence
647 */
ee1b9f06 648 if (adapter->vfs_allocated_count) {
a99955fc 649 for (; i < adapter->rss_queues; i++)
3025a446
AD		 650 adapter->rx_ring[i]->reg_idx = rbase_offset +
651 Q_IDX_82576(i);
ee1b9f06 652 }
26bc19ec 653 case e1000_82575:
55cac248 654 case e1000_82580:
d2ba2ed8 655 case e1000_i350:
26bc19ec 656 default:
ee1b9f06 657 for (; i < adapter->num_rx_queues; i++)
3025a446 658 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 659 for (; j < adapter->num_tx_queues; j++)
3025a446 660 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 661 break;
662 }
663}
664
047e0030
AD		 665static void igb_free_queues(struct igb_adapter *adapter)
666{
3025a446 667 int i;
047e0030 668
3025a446
AD		 669 for (i = 0; i < adapter->num_tx_queues; i++) {
670 kfree(adapter->tx_ring[i]);
671 adapter->tx_ring[i] = NULL;
672 }
673 for (i = 0; i < adapter->num_rx_queues; i++) {
674 kfree(adapter->rx_ring[i]);
675 adapter->rx_ring[i] = NULL;
676 }
047e0030
AD		 677 adapter->num_rx_queues = 0;
678 adapter->num_tx_queues = 0;
679}
680
9d5c8243
AK		 681/**
682 * igb_alloc_queues - Allocate memory for all rings
683 * @adapter: board private structure to initialize
684 *
685 * We allocate one ring per queue at run-time since we don't know the
686 * number of queues at compile-time.
687 **/
688static int igb_alloc_queues(struct igb_adapter *adapter)
689{
3025a446 690 struct igb_ring *ring;
9d5c8243 691 int i;
81c2fc22 692 int orig_node = adapter->node;
9d5c8243 693
661086df 694 for (i = 0; i < adapter->num_tx_queues; i++) {
81c2fc22
AD		 695 if (orig_node == -1) {
696 int cur_node = next_online_node(adapter->node);
697 if (cur_node == MAX_NUMNODES)
698 cur_node = first_online_node;
699 adapter->node = cur_node;
700 }
701 ring = kzalloc_node(sizeof(struct igb_ring), GFP_KERNEL,
702 adapter->node);
703 if (!ring)
704 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
3025a446
AD		 705 if (!ring)
706 goto err;
68fd9910 707 ring->count = adapter->tx_ring_count;
661086df 708 ring->queue_index = i;
59d71989 709 ring->dev = &adapter->pdev->dev;
e694e964 710 ring->netdev = adapter->netdev;
81c2fc22 711 ring->numa_node = adapter->node;
85ad76b2
AD		 712 /* For 82575, context index must be unique per ring. */
713 if (adapter->hw.mac.type == e1000_82575)
866cff06 714 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
3025a446 715 adapter->tx_ring[i] = ring;
661086df 716 }
81c2fc22
AD		 717 /* Restore the adapter's original node */
718 adapter->node = orig_node;
85ad76b2 719
9d5c8243 720 for (i = 0; i < adapter->num_rx_queues; i++) {
81c2fc22
AD		 721 if (orig_node == -1) {
722 int cur_node = next_online_node(adapter->node);
723 if (cur_node == MAX_NUMNODES)
724 cur_node = first_online_node;
725 adapter->node = cur_node;
726 }
727 ring = kzalloc_node(sizeof(struct igb_ring), GFP_KERNEL,
728 adapter->node);
729 if (!ring)
730 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
3025a446
AD		 731 if (!ring)
732 goto err;
68fd9910 733 ring->count = adapter->rx_ring_count;
844290e5 734 ring->queue_index = i;
59d71989 735 ring->dev = &adapter->pdev->dev;
e694e964 736 ring->netdev = adapter->netdev;
81c2fc22 737 ring->numa_node = adapter->node;
85ad76b2
AD		 738 /* set flag indicating ring supports SCTP checksum offload */
739 if (adapter->hw.mac.type >= e1000_82576)
866cff06 740 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
8be10e91
AD		 741
742 /* On i350, loopback VLAN packets have the tag byte-swapped. */
743 if (adapter->hw.mac.type == e1000_i350)
744 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
745
3025a446 746 adapter->rx_ring[i] = ring;
9d5c8243 747 }
81c2fc22
AD		 748 /* Restore the adapter's original node */
749 adapter->node = orig_node;
26bc19ec
AD		 750
751 igb_cache_ring_register(adapter);
9d5c8243 752
047e0030 753 return 0;
a88f10ec 754
047e0030 755err:
81c2fc22
AD		 756 /* Restore the adapter's original node */
757 adapter->node = orig_node;
047e0030 758 igb_free_queues(adapter);
d1a8c9e1 759
047e0030 760 return -ENOMEM;
a88f10ec
AD		 761}
762
4be000c8
AD		 763/**
764 * igb_write_ivar - configure ivar for given MSI-X vector
765 * @hw: pointer to the HW structure
766 * @msix_vector: vector number we are allocating to a given ring
767 * @index: row index of IVAR register to write within IVAR table
768 * @offset: column offset of in IVAR, should be multiple of 8
769 *
770 * This function is intended to handle the writing of the IVAR register
771 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
772 * each containing an cause allocation for an Rx and Tx ring, and a
773 * variable number of rows depending on the number of queues supported.
774 **/
775static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
776 int index, int offset)
777{
778 u32 ivar = array_rd32(E1000_IVAR0, index);
779
780 /* clear any bits that are currently set */
781 ivar &= ~((u32)0xFF << offset);
782
783 /* write vector and valid bit */
784 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
785
786 array_wr32(E1000_IVAR0, index, ivar);
787}
788
9d5c8243 789#define IGB_N0_QUEUE -1
047e0030 790static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 791{
047e0030 792 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 793 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 794 int rx_queue = IGB_N0_QUEUE;
795 int tx_queue = IGB_N0_QUEUE;
4be000c8 796 u32 msixbm = 0;
047e0030 797
0ba82994
AD		 798 if (q_vector->rx.ring)
799 rx_queue = q_vector->rx.ring->reg_idx;
800 if (q_vector->tx.ring)
801 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 802
803 switch (hw->mac.type) {
804 case e1000_82575:
9d5c8243
AK		 805 /* The 82575 assigns vectors using a bitmask, which matches the
806 bitmask for the EICR/EIMS/EIMC registers. To assign one
807 or more queues to a vector, we write the appropriate bits
808 into the MSIXBM register for that vector. */
047e0030 809 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 810 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 811 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 812 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 813 if (!adapter->msix_entries && msix_vector == 0)
814 msixbm |= E1000_EIMS_OTHER;
9d5c8243 815 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 816 q_vector->eims_value = msixbm;
2d064c06
AD		 817 break;
818 case e1000_82576:
4be000c8
AD		 819 /*
820 * 82576 uses a table that essentially consists of 2 columns
821 * with 8 rows. The ordering is column-major so we use the
822 * lower 3 bits as the row index, and the 4th bit as the
823 * column offset.
824 */
825 if (rx_queue > IGB_N0_QUEUE)
826 igb_write_ivar(hw, msix_vector,
827 rx_queue & 0x7,
828 (rx_queue & 0x8) << 1);
829 if (tx_queue > IGB_N0_QUEUE)
830 igb_write_ivar(hw, msix_vector,
831 tx_queue & 0x7,
832 ((tx_queue & 0x8) << 1) + 8);
047e0030 833 q_vector->eims_value = 1 << msix_vector;
2d064c06 834 break;
55cac248 835 case e1000_82580:
d2ba2ed8 836 case e1000_i350:
4be000c8
AD		 837 /*
838 * On 82580 and newer adapters the scheme is similar to 82576
839 * however instead of ordering column-major we have things
840 * ordered row-major. So we traverse the table by using
841 * bit 0 as the column offset, and the remaining bits as the
842 * row index.
843 */
844 if (rx_queue > IGB_N0_QUEUE)
845 igb_write_ivar(hw, msix_vector,
846 rx_queue >> 1,
847 (rx_queue & 0x1) << 4);
848 if (tx_queue > IGB_N0_QUEUE)
849 igb_write_ivar(hw, msix_vector,
850 tx_queue >> 1,
851 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 852 q_vector->eims_value = 1 << msix_vector;
853 break;
2d064c06
AD		 854 default:
855 BUG();
856 break;
857 }
26b39276
AD		 858
859 /* add q_vector eims value to global eims_enable_mask */
860 adapter->eims_enable_mask |= q_vector->eims_value;
861
862 /* configure q_vector to set itr on first interrupt */
863 q_vector->set_itr = 1;
9d5c8243
AK		 864}
865
866/**
867 * igb_configure_msix - Configure MSI-X hardware
868 *
869 * igb_configure_msix sets up the hardware to properly
870 * generate MSI-X interrupts.
871 **/
872static void igb_configure_msix(struct igb_adapter *adapter)
873{
874 u32 tmp;
875 int i, vector = 0;
876 struct e1000_hw *hw = &adapter->hw;
877
878 adapter->eims_enable_mask = 0;
9d5c8243
AK		 879
880 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 881 switch (hw->mac.type) {
882 case e1000_82575:
9d5c8243
AK		 883 tmp = rd32(E1000_CTRL_EXT);
884 /* enable MSI-X PBA support*/
885 tmp |= E1000_CTRL_EXT_PBA_CLR;
886
887 /* Auto-Mask interrupts upon ICR read. */
888 tmp |= E1000_CTRL_EXT_EIAME;
889 tmp |= E1000_CTRL_EXT_IRCA;
890
891 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 892
893 /* enable msix_other interrupt */
894 array_wr32(E1000_MSIXBM(0), vector++,
895 E1000_EIMS_OTHER);
844290e5 896 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 897
2d064c06
AD		 898 break;
899
900 case e1000_82576:
55cac248 901 case e1000_82580:
d2ba2ed8 902 case e1000_i350:
047e0030
AD		 903 /* Turn on MSI-X capability first, or our settings
904 * won't stick. And it will take days to debug. */
905 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
906 E1000_GPIE_PBA | E1000_GPIE_EIAME |
907 E1000_GPIE_NSICR);
908
909 /* enable msix_other interrupt */
910 adapter->eims_other = 1 << vector;
2d064c06 911 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 912
047e0030 913 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 914 break;
915 default:
916 /* do nothing, since nothing else supports MSI-X */
917 break;
918 } /* switch (hw->mac.type) */
047e0030
AD		 919
920 adapter->eims_enable_mask |= adapter->eims_other;
921
26b39276
AD		 922 for (i = 0; i < adapter->num_q_vectors; i++)
923 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 924
9d5c8243
AK		 925 wrfl();
926}
927
928/**
929 * igb_request_msix - Initialize MSI-X interrupts
930 *
931 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
932 * kernel.
933 **/
934static int igb_request_msix(struct igb_adapter *adapter)
935{
936 struct net_device *netdev = adapter->netdev;
047e0030 937 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 938 int i, err = 0, vector = 0;
939
047e0030 940 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 941 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 942 if (err)
943 goto out;
944 vector++;
945
946 for (i = 0; i < adapter->num_q_vectors; i++) {
947 struct igb_q_vector *q_vector = adapter->q_vector[i];
948
949 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
950
0ba82994 951 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 953 q_vector->rx.ring->queue_index);
954 else if (q_vector->tx.ring)
047e0030 955 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 956 q_vector->tx.ring->queue_index);
957 else if (q_vector->rx.ring)
047e0030 958 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 959 q_vector->rx.ring->queue_index);
9d5c8243 960 else
047e0030
AD		 961 sprintf(q_vector->name, "%s-unused", netdev->name);
962
9d5c8243 963 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 964 igb_msix_ring, 0, q_vector->name,
047e0030 965 q_vector);
9d5c8243
AK		 966 if (err)
967 goto out;
9d5c8243
AK		 968 vector++;
969 }
970
9d5c8243
AK		 971 igb_configure_msix(adapter);
972 return 0;
973out:
974 return err;
975}
976
977static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
978{
979 if (adapter->msix_entries) {
980 pci_disable_msix(adapter->pdev);
981 kfree(adapter->msix_entries);
982 adapter->msix_entries = NULL;
047e0030 983 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 984 pci_disable_msi(adapter->pdev);
047e0030 985 }
9d5c8243
AK		 986}
987
047e0030
AD		 988/**
989 * igb_free_q_vectors - Free memory allocated for interrupt vectors
990 * @adapter: board private structure to initialize
991 *
992 * This function frees the memory allocated to the q_vectors. In addition if
993 * NAPI is enabled it will delete any references to the NAPI struct prior
994 * to freeing the q_vector.
995 **/
996static void igb_free_q_vectors(struct igb_adapter *adapter)
997{
998 int v_idx;
999
1000 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1001 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1002 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 1003 if (!q_vector)
1004 continue;
047e0030
AD		 1005 netif_napi_del(&q_vector->napi);
1006 kfree(q_vector);
1007 }
1008 adapter->num_q_vectors = 0;
1009}
1010
1011/**
1012 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1013 *
1014 * This function resets the device so that it has 0 rx queues, tx queues, and
1015 * MSI-X interrupts allocated.
1016 */
1017static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1018{
1019 igb_free_queues(adapter);
1020 igb_free_q_vectors(adapter);
1021 igb_reset_interrupt_capability(adapter);
1022}
9d5c8243
AK		 1023
1024/**
1025 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1026 *
1027 * Attempt to configure interrupts using the best available
1028 * capabilities of the hardware and kernel.
1029 **/
21adef3e 1030static int igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 1031{
1032 int err;
1033 int numvecs, i;
1034
83b7180d 1035 /* Number of supported queues. */
a99955fc 1036 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1037 if (adapter->vfs_allocated_count)
1038 adapter->num_tx_queues = 1;
1039 else
1040 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1041
047e0030
AD		 1042 /* start with one vector for every rx queue */
1043 numvecs = adapter->num_rx_queues;
1044
3ad2f3fb 1045 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1046 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1047 numvecs += adapter->num_tx_queues;
047e0030
AD		 1048
1049 /* store the number of vectors reserved for queues */
1050 adapter->num_q_vectors = numvecs;
1051
1052 /* add 1 vector for link status interrupts */
1053 numvecs++;
9d5c8243
AK		 1054 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1055 GFP_KERNEL);
1056 if (!adapter->msix_entries)
1057 goto msi_only;
1058
1059 for (i = 0; i < numvecs; i++)
1060 adapter->msix_entries[i].entry = i;
1061
1062 err = pci_enable_msix(adapter->pdev,
1063 adapter->msix_entries,
1064 numvecs);
1065 if (err == 0)
34a20e89 1066 goto out;
9d5c8243
AK		 1067
1068 igb_reset_interrupt_capability(adapter);
1069
1070 /* If we can't do MSI-X, try MSI */
1071msi_only:
2a3abf6d
AD		 1072#ifdef CONFIG_PCI_IOV
1073 /* disable SR-IOV for non MSI-X configurations */
1074 if (adapter->vf_data) {
1075 struct e1000_hw *hw = &adapter->hw;
1076 /* disable iov and allow time for transactions to clear */
1077 pci_disable_sriov(adapter->pdev);
1078 msleep(500);
1079
1080 kfree(adapter->vf_data);
1081 adapter->vf_data = NULL;
1082 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1083 wrfl();
2a3abf6d
AD		 1084 msleep(100);
1085 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1086 }
1087#endif
4fc82adf 1088 adapter->vfs_allocated_count = 0;
a99955fc 1089 adapter->rss_queues = 1;
4fc82adf 1090 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1091 adapter->num_rx_queues = 1;
661086df 1092 adapter->num_tx_queues = 1;
047e0030 1093 adapter->num_q_vectors = 1;
9d5c8243 1094 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1095 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1096out:
21adef3e
BH		 1097 /* Notify the stack of the (possibly) reduced queue counts. */
1098 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1099 return netif_set_real_num_rx_queues(adapter->netdev,
1100 adapter->num_rx_queues);
9d5c8243
AK		 1101}
1102
047e0030
AD		 1103/**
1104 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1105 * @adapter: board private structure to initialize
1106 *
1107 * We allocate one q_vector per queue interrupt. If allocation fails we
1108 * return -ENOMEM.
1109 **/
1110static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1111{
1112 struct igb_q_vector *q_vector;
1113 struct e1000_hw *hw = &adapter->hw;
1114 int v_idx;
81c2fc22 1115 int orig_node = adapter->node;
047e0030
AD		 1116
1117 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
81c2fc22
AD		 1118 if ((adapter->num_q_vectors == (adapter->num_rx_queues +
1119 adapter->num_tx_queues)) &&
1120 (adapter->num_rx_queues == v_idx))
1121 adapter->node = orig_node;
1122 if (orig_node == -1) {
1123 int cur_node = next_online_node(adapter->node);
1124 if (cur_node == MAX_NUMNODES)
1125 cur_node = first_online_node;
1126 adapter->node = cur_node;
1127 }
1128 q_vector = kzalloc_node(sizeof(struct igb_q_vector), GFP_KERNEL,
1129 adapter->node);
1130 if (!q_vector)
1131 q_vector = kzalloc(sizeof(struct igb_q_vector),
1132 GFP_KERNEL);
047e0030
AD		 1133 if (!q_vector)
1134 goto err_out;
1135 q_vector->adapter = adapter;
047e0030
AD		 1136 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1137 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1138 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1139 adapter->q_vector[v_idx] = q_vector;
1140 }
81c2fc22
AD		 1141 /* Restore the adapter's original node */
1142 adapter->node = orig_node;
1143
047e0030
AD		 1144 return 0;
1145
1146err_out:
81c2fc22
AD		 1147 /* Restore the adapter's original node */
1148 adapter->node = orig_node;
fe0592b4 1149 igb_free_q_vectors(adapter);
047e0030
AD		 1150 return -ENOMEM;
1151}
1152
1153static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1154 int ring_idx, int v_idx)
1155{
3025a446 1156 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1157
0ba82994
AD		 1158 q_vector->rx.ring = adapter->rx_ring[ring_idx];
1159 q_vector->rx.ring->q_vector = q_vector;
1160 q_vector->rx.count++;
4fc82adf
AD		 1161 q_vector->itr_val = adapter->rx_itr_setting;
1162 if (q_vector->itr_val && q_vector->itr_val <= 3)
1163 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1164}
1165
1166static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1167 int ring_idx, int v_idx)
1168{
3025a446 1169 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1170
0ba82994
AD		 1171 q_vector->tx.ring = adapter->tx_ring[ring_idx];
1172 q_vector->tx.ring->q_vector = q_vector;
1173 q_vector->tx.count++;
4fc82adf 1174 q_vector->itr_val = adapter->tx_itr_setting;
0ba82994 1175 q_vector->tx.work_limit = adapter->tx_work_limit;
4fc82adf
AD		 1176 if (q_vector->itr_val && q_vector->itr_val <= 3)
1177 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1178}
1179
1180/**
1181 * igb_map_ring_to_vector - maps allocated queues to vectors
1182 *
1183 * This function maps the recently allocated queues to vectors.
1184 **/
1185static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1186{
1187 int i;
1188 int v_idx = 0;
1189
1190 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1191 (adapter->num_q_vectors < adapter->num_tx_queues))
1192 return -ENOMEM;
1193
1194 if (adapter->num_q_vectors >=
1195 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1196 for (i = 0; i < adapter->num_rx_queues; i++)
1197 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1198 for (i = 0; i < adapter->num_tx_queues; i++)
1199 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1200 } else {
1201 for (i = 0; i < adapter->num_rx_queues; i++) {
1202 if (i < adapter->num_tx_queues)
1203 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1204 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1205 }
1206 for (; i < adapter->num_tx_queues; i++)
1207 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1208 }
1209 return 0;
1210}
1211
1212/**
1213 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1214 *
1215 * This function initializes the interrupts and allocates all of the queues.
1216 **/
1217static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1218{
1219 struct pci_dev *pdev = adapter->pdev;
1220 int err;
1221
21adef3e
BH		 1222 err = igb_set_interrupt_capability(adapter);
1223 if (err)
1224 return err;
047e0030
AD		 1225
1226 err = igb_alloc_q_vectors(adapter);
1227 if (err) {
1228 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1229 goto err_alloc_q_vectors;
1230 }
1231
1232 err = igb_alloc_queues(adapter);
1233 if (err) {
1234 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1235 goto err_alloc_queues;
1236 }
1237
1238 err = igb_map_ring_to_vector(adapter);
1239 if (err) {
1240 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1241 goto err_map_queues;
1242 }
1243
1244
1245 return 0;
1246err_map_queues:
1247 igb_free_queues(adapter);
1248err_alloc_queues:
1249 igb_free_q_vectors(adapter);
1250err_alloc_q_vectors:
1251 igb_reset_interrupt_capability(adapter);
1252 return err;
1253}
1254
9d5c8243
AK		 1255/**
1256 * igb_request_irq - initialize interrupts
1257 *
1258 * Attempts to configure interrupts using the best available
1259 * capabilities of the hardware and kernel.
1260 **/
1261static int igb_request_irq(struct igb_adapter *adapter)
1262{
1263 struct net_device *netdev = adapter->netdev;
047e0030 1264 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1265 int err = 0;
1266
1267 if (adapter->msix_entries) {
1268 err = igb_request_msix(adapter);
844290e5 1269 if (!err)
9d5c8243 1270 goto request_done;
9d5c8243 1271 /* fall back to MSI */
047e0030 1272 igb_clear_interrupt_scheme(adapter);
c74d588e 1273 if (!pci_enable_msi(pdev))
7dfc16fa 1274 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1275 igb_free_all_tx_resources(adapter);
1276 igb_free_all_rx_resources(adapter);
047e0030 1277 adapter->num_tx_queues = 1;
9d5c8243 1278 adapter->num_rx_queues = 1;
047e0030
AD		 1279 adapter->num_q_vectors = 1;
1280 err = igb_alloc_q_vectors(adapter);
1281 if (err) {
1282 dev_err(&pdev->dev,
1283 "Unable to allocate memory for vectors\n");
1284 goto request_done;
1285 }
1286 err = igb_alloc_queues(adapter);
1287 if (err) {
1288 dev_err(&pdev->dev,
1289 "Unable to allocate memory for queues\n");
1290 igb_free_q_vectors(adapter);
1291 goto request_done;
1292 }
1293 igb_setup_all_tx_resources(adapter);
1294 igb_setup_all_rx_resources(adapter);
9d5c8243 1295 }
844290e5 1296
c74d588e
AD		 1297 igb_assign_vector(adapter->q_vector[0], 0);
1298
7dfc16fa 1299 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1300 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1301 netdev->name, adapter);
9d5c8243
AK		 1302 if (!err)
1303 goto request_done;
047e0030 1304
9d5c8243
AK		 1305 /* fall back to legacy interrupts */
1306 igb_reset_interrupt_capability(adapter);
7dfc16fa 1307 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1308 }
1309
c74d588e 1310 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1311 netdev->name, adapter);
9d5c8243 1312
6cb5e577 1313 if (err)
c74d588e 1314 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1315 err);
9d5c8243
AK		 1316
1317request_done:
1318 return err;
1319}
1320
1321static void igb_free_irq(struct igb_adapter *adapter)
1322{
9d5c8243
AK		 1323 if (adapter->msix_entries) {
1324 int vector = 0, i;
1325
047e0030 1326 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1327
0d1ae7f4 1328 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1329 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1330 adapter->q_vector[i]);
047e0030
AD		 1331 } else {
1332 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1333 }
9d5c8243
AK		 1334}
1335
1336/**
1337 * igb_irq_disable - Mask off interrupt generation on the NIC
1338 * @adapter: board private structure
1339 **/
1340static void igb_irq_disable(struct igb_adapter *adapter)
1341{
1342 struct e1000_hw *hw = &adapter->hw;
1343
25568a53
AD		 1344 /*
1345 * we need to be careful when disabling interrupts. The VFs are also
1346 * mapped into these registers and so clearing the bits can cause
1347 * issues on the VF drivers so we only need to clear what we set
1348 */
9d5c8243 1349 if (adapter->msix_entries) {
2dfd1212
AD		 1350 u32 regval = rd32(E1000_EIAM);
1351 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1352 wr32(E1000_EIMC, adapter->eims_enable_mask);
1353 regval = rd32(E1000_EIAC);
1354 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1355 }
844290e5
PW		 1356
1357 wr32(E1000_IAM, 0);
9d5c8243
AK		 1358 wr32(E1000_IMC, ~0);
1359 wrfl();
81a61859
ET		 1360 if (adapter->msix_entries) {
1361 int i;
1362 for (i = 0; i < adapter->num_q_vectors; i++)
1363 synchronize_irq(adapter->msix_entries[i].vector);
1364 } else {
1365 synchronize_irq(adapter->pdev->irq);
1366 }
9d5c8243
AK		 1367}
1368
1369/**
1370 * igb_irq_enable - Enable default interrupt generation settings
1371 * @adapter: board private structure
1372 **/
1373static void igb_irq_enable(struct igb_adapter *adapter)
1374{
1375 struct e1000_hw *hw = &adapter->hw;
1376
1377 if (adapter->msix_entries) {
06218a8d 1378 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1379 u32 regval = rd32(E1000_EIAC);
1380 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1381 regval = rd32(E1000_EIAM);
1382 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1383 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1384 if (adapter->vfs_allocated_count) {
4ae196df 1385 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1386 ims |= E1000_IMS_VMMB;
1387 }
1388 wr32(E1000_IMS, ims);
844290e5 1389 } else {
55cac248
AD		 1390 wr32(E1000_IMS, IMS_ENABLE_MASK |
1391 E1000_IMS_DRSTA);
1392 wr32(E1000_IAM, IMS_ENABLE_MASK |
1393 E1000_IMS_DRSTA);
844290e5 1394 }
9d5c8243
AK		 1395}
1396
1397static void igb_update_mng_vlan(struct igb_adapter *adapter)
1398{
51466239 1399 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1400 u16 vid = adapter->hw.mng_cookie.vlan_id;
1401 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1402
1403 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1404 /* add VID to filter table */
1405 igb_vfta_set(hw, vid, true);
1406 adapter->mng_vlan_id = vid;
1407 } else {
1408 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1409 }
1410
1411 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1412 (vid != old_vid) &&
b2cb09b1 1413 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1414 /* remove VID from filter table */
1415 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1416 }
1417}
1418
1419/**
1420 * igb_release_hw_control - release control of the h/w to f/w
1421 * @adapter: address of board private structure
1422 *
1423 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1424 * For ASF and Pass Through versions of f/w this means that the
1425 * driver is no longer loaded.
1426 *
1427 **/
1428static void igb_release_hw_control(struct igb_adapter *adapter)
1429{
1430 struct e1000_hw *hw = &adapter->hw;
1431 u32 ctrl_ext;
1432
1433 /* Let firmware take over control of h/w */
1434 ctrl_ext = rd32(E1000_CTRL_EXT);
1435 wr32(E1000_CTRL_EXT,
1436 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1437}
1438
9d5c8243
AK		 1439/**
1440 * igb_get_hw_control - get control of the h/w from f/w
1441 * @adapter: address of board private structure
1442 *
1443 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1444 * For ASF and Pass Through versions of f/w this means that
1445 * the driver is loaded.
1446 *
1447 **/
1448static void igb_get_hw_control(struct igb_adapter *adapter)
1449{
1450 struct e1000_hw *hw = &adapter->hw;
1451 u32 ctrl_ext;
1452
1453 /* Let firmware know the driver has taken over */
1454 ctrl_ext = rd32(E1000_CTRL_EXT);
1455 wr32(E1000_CTRL_EXT,
1456 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1457}
1458
9d5c8243
AK		 1459/**
1460 * igb_configure - configure the hardware for RX and TX
1461 * @adapter: private board structure
1462 **/
1463static void igb_configure(struct igb_adapter *adapter)
1464{
1465 struct net_device *netdev = adapter->netdev;
1466 int i;
1467
1468 igb_get_hw_control(adapter);
ff41f8dc 1469 igb_set_rx_mode(netdev);
9d5c8243
AK		 1470
1471 igb_restore_vlan(adapter);
9d5c8243 1472
85b430b4 1473 igb_setup_tctl(adapter);
06cf2666 1474 igb_setup_mrqc(adapter);
9d5c8243 1475 igb_setup_rctl(adapter);
85b430b4
AD		 1476
1477 igb_configure_tx(adapter);
9d5c8243 1478 igb_configure_rx(adapter);
662d7205
AD		 1479
1480 igb_rx_fifo_flush_82575(&adapter->hw);
1481
c493ea45 1482 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1483 * at least 1 descriptor unused to make sure
1484 * next_to_use != next_to_clean */
1485 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1486 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1487 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1488 }
9d5c8243
AK		 1489}
1490
88a268c1
NN		 1491/**
1492 * igb_power_up_link - Power up the phy/serdes link
1493 * @adapter: address of board private structure
1494 **/
1495void igb_power_up_link(struct igb_adapter *adapter)
1496{
1497 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1498 igb_power_up_phy_copper(&adapter->hw);
1499 else
1500 igb_power_up_serdes_link_82575(&adapter->hw);
1501}
1502
1503/**
1504 * igb_power_down_link - Power down the phy/serdes link
1505 * @adapter: address of board private structure
1506 */
1507static void igb_power_down_link(struct igb_adapter *adapter)
1508{
1509 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1510 igb_power_down_phy_copper_82575(&adapter->hw);
1511 else
1512 igb_shutdown_serdes_link_82575(&adapter->hw);
1513}
9d5c8243
AK		 1514
1515/**
1516 * igb_up - Open the interface and prepare it to handle traffic
1517 * @adapter: board private structure
1518 **/
9d5c8243
AK		 1519int igb_up(struct igb_adapter *adapter)
1520{
1521 struct e1000_hw *hw = &adapter->hw;
1522 int i;
1523
1524 /* hardware has been reset, we need to reload some things */
1525 igb_configure(adapter);
1526
1527 clear_bit(__IGB_DOWN, &adapter->state);
1528
0d1ae7f4
AD		 1529 for (i = 0; i < adapter->num_q_vectors; i++)
1530 napi_enable(&(adapter->q_vector[i]->napi));
1531
844290e5 1532 if (adapter->msix_entries)
9d5c8243 1533 igb_configure_msix(adapter);
feeb2721
AD		 1534 else
1535 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1536
1537 /* Clear any pending interrupts. */
1538 rd32(E1000_ICR);
1539 igb_irq_enable(adapter);
1540
d4960307
AD		 1541 /* notify VFs that reset has been completed */
1542 if (adapter->vfs_allocated_count) {
1543 u32 reg_data = rd32(E1000_CTRL_EXT);
1544 reg_data |= E1000_CTRL_EXT_PFRSTD;
1545 wr32(E1000_CTRL_EXT, reg_data);
1546 }
1547
4cb9be7a
JB		 1548 netif_tx_start_all_queues(adapter->netdev);
1549
25568a53
AD		 1550 /* start the watchdog. */
1551 hw->mac.get_link_status = 1;
1552 schedule_work(&adapter->watchdog_task);
1553
9d5c8243
AK		 1554 return 0;
1555}
1556
1557void igb_down(struct igb_adapter *adapter)
1558{
9d5c8243 1559 struct net_device *netdev = adapter->netdev;
330a6d6a 1560 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1561 u32 tctl, rctl;
1562 int i;
1563
1564 /* signal that we're down so the interrupt handler does not
1565 * reschedule our watchdog timer */
1566 set_bit(__IGB_DOWN, &adapter->state);
1567
1568 /* disable receives in the hardware */
1569 rctl = rd32(E1000_RCTL);
1570 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1571 /* flush and sleep below */
1572
fd2ea0a7 1573 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1574
1575 /* disable transmits in the hardware */
1576 tctl = rd32(E1000_TCTL);
1577 tctl &= ~E1000_TCTL_EN;
1578 wr32(E1000_TCTL, tctl);
1579 /* flush both disables and wait for them to finish */
1580 wrfl();
1581 msleep(10);
1582
0d1ae7f4
AD		 1583 for (i = 0; i < adapter->num_q_vectors; i++)
1584 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1585
9d5c8243
AK		 1586 igb_irq_disable(adapter);
1587
1588 del_timer_sync(&adapter->watchdog_timer);
1589 del_timer_sync(&adapter->phy_info_timer);
1590
9d5c8243 1591 netif_carrier_off(netdev);
04fe6358
AD		 1592
1593 /* record the stats before reset*/
12dcd86b
ED		 1594 spin_lock(&adapter->stats64_lock);
1595 igb_update_stats(adapter, &adapter->stats64);
1596 spin_unlock(&adapter->stats64_lock);
04fe6358 1597
9d5c8243
AK		 1598 adapter->link_speed = 0;
1599 adapter->link_duplex = 0;
1600
3023682e
JK		 1601 if (!pci_channel_offline(adapter->pdev))
1602 igb_reset(adapter);
9d5c8243
AK		 1603 igb_clean_all_tx_rings(adapter);
1604 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1605#ifdef CONFIG_IGB_DCA
1606
1607 /* since we reset the hardware DCA settings were cleared */
1608 igb_setup_dca(adapter);
1609#endif
9d5c8243
AK		 1610}
1611
1612void igb_reinit_locked(struct igb_adapter *adapter)
1613{
1614 WARN_ON(in_interrupt());
1615 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1616 msleep(1);
1617 igb_down(adapter);
1618 igb_up(adapter);
1619 clear_bit(__IGB_RESETTING, &adapter->state);
1620}
1621
1622void igb_reset(struct igb_adapter *adapter)
1623{
090b1795 1624 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1625 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1626 struct e1000_mac_info *mac = &hw->mac;
1627 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1628 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1629 u16 hwm;
1630
1631 /* Repartition Pba for greater than 9k mtu
1632 * To take effect CTRL.RST is required.
1633 */
fa4dfae0 1634 switch (mac->type) {
d2ba2ed8 1635 case e1000_i350:
55cac248
AD		 1636 case e1000_82580:
1637 pba = rd32(E1000_RXPBS);
1638 pba = igb_rxpbs_adjust_82580(pba);
1639 break;
fa4dfae0 1640 case e1000_82576:
d249be54
AD		 1641 pba = rd32(E1000_RXPBS);
1642 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1643 break;
1644 case e1000_82575:
1645 default:
1646 pba = E1000_PBA_34K;
1647 break;
2d064c06 1648 }
9d5c8243 1649
2d064c06
AD		 1650 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1651 (mac->type < e1000_82576)) {
9d5c8243
AK		 1652 /* adjust PBA for jumbo frames */
1653 wr32(E1000_PBA, pba);
1654
1655 /* To maintain wire speed transmits, the Tx FIFO should be
1656 * large enough to accommodate two full transmit packets,
1657 * rounded up to the next 1KB and expressed in KB. Likewise,
1658 * the Rx FIFO should be large enough to accommodate at least
1659 * one full receive packet and is similarly rounded up and
1660 * expressed in KB. */
1661 pba = rd32(E1000_PBA);
1662 /* upper 16 bits has Tx packet buffer allocation size in KB */
1663 tx_space = pba >> 16;
1664 /* lower 16 bits has Rx packet buffer allocation size in KB */
1665 pba &= 0xffff;
1666 /* the tx fifo also stores 16 bytes of information about the tx
1667 * but don't include ethernet FCS because hardware appends it */
1668 min_tx_space = (adapter->max_frame_size +
85e8d004 1669 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1670 ETH_FCS_LEN) * 2;
1671 min_tx_space = ALIGN(min_tx_space, 1024);
1672 min_tx_space >>= 10;
1673 /* software strips receive CRC, so leave room for it */
1674 min_rx_space = adapter->max_frame_size;
1675 min_rx_space = ALIGN(min_rx_space, 1024);
1676 min_rx_space >>= 10;
1677
1678 /* If current Tx allocation is less than the min Tx FIFO size,
1679 * and the min Tx FIFO size is less than the current Rx FIFO
1680 * allocation, take space away from current Rx allocation */
1681 if (tx_space < min_tx_space &&
1682 ((min_tx_space - tx_space) < pba)) {
1683 pba = pba - (min_tx_space - tx_space);
1684
1685 /* if short on rx space, rx wins and must trump tx
1686 * adjustment */
1687 if (pba < min_rx_space)
1688 pba = min_rx_space;
1689 }
2d064c06 1690 wr32(E1000_PBA, pba);
9d5c8243 1691 }
9d5c8243
AK		 1692
1693 /* flow control settings */
1694 /* The high water mark must be low enough to fit one full frame
1695 * (or the size used for early receive) above it in the Rx FIFO.
1696 * Set it to the lower of:
1697 * - 90% of the Rx FIFO size, or
1698 * - the full Rx FIFO size minus one full frame */
1699 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1700 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1701
d405ea3e
AD		 1702 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1703 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1704 fc->pause_time = 0xFFFF;
1705 fc->send_xon = 1;
0cce119a 1706 fc->current_mode = fc->requested_mode;
9d5c8243 1707
4ae196df
AD		 1708 /* disable receive for all VFs and wait one second */
1709 if (adapter->vfs_allocated_count) {
1710 int i;
1711 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1712 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1713
1714 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1715 igb_ping_all_vfs(adapter);
4ae196df
AD		 1716
1717 /* disable transmits and receives */
1718 wr32(E1000_VFRE, 0);
1719 wr32(E1000_VFTE, 0);
1720 }
1721
9d5c8243 1722 /* Allow time for pending master requests to run */
330a6d6a 1723 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1724 wr32(E1000_WUC, 0);
1725
330a6d6a 1726 if (hw->mac.ops.init_hw(hw))
090b1795 1727 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1728
b6e0c419 1729 igb_init_dmac(adapter, pba);
88a268c1
NN		 1730 if (!netif_running(adapter->netdev))
1731 igb_power_down_link(adapter);
1732
9d5c8243
AK		 1733 igb_update_mng_vlan(adapter);
1734
1735 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1736 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1737
330a6d6a 1738 igb_get_phy_info(hw);
9d5c8243
AK		 1739}
1740
c8f44aff
MM		 1741static netdev_features_t igb_fix_features(struct net_device *netdev,
1742 netdev_features_t features)
b2cb09b1
JP		 1743{
1744 /*
1745 * Since there is no support for separate rx/tx vlan accel
1746 * enable/disable make sure tx flag is always in same state as rx.
1747 */
1748 if (features & NETIF_F_HW_VLAN_RX)
1749 features |= NETIF_F_HW_VLAN_TX;
1750 else
1751 features &= ~NETIF_F_HW_VLAN_TX;
1752
1753 return features;
1754}
1755
c8f44aff
MM		 1756static int igb_set_features(struct net_device *netdev,
1757 netdev_features_t features)
ac52caa3 1758{
c8f44aff 1759 netdev_features_t changed = netdev->features ^ features;
ac52caa3 1760
b2cb09b1
JP		 1761 if (changed & NETIF_F_HW_VLAN_RX)
1762 igb_vlan_mode(netdev, features);
1763
ac52caa3
MM		 1764 return 0;
1765}
1766
2e5c6922 1767static const struct net_device_ops igb_netdev_ops = {
559e9c49 1768 .ndo_open = igb_open,
2e5c6922 1769 .ndo_stop = igb_close,
cd392f5c 1770 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1771 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1772 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1773 .ndo_set_mac_address = igb_set_mac,
1774 .ndo_change_mtu = igb_change_mtu,
1775 .ndo_do_ioctl = igb_ioctl,
1776 .ndo_tx_timeout = igb_tx_timeout,
1777 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1778 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1779 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1780 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1781 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1782 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1783 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1784#ifdef CONFIG_NET_POLL_CONTROLLER
1785 .ndo_poll_controller = igb_netpoll,
1786#endif
b2cb09b1
JP		 1787 .ndo_fix_features = igb_fix_features,
1788 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1789};
1790
9d5c8243
AK		 1791/**
1792 * igb_probe - Device Initialization Routine
1793 * @pdev: PCI device information struct
1794 * @ent: entry in igb_pci_tbl
1795 *
1796 * Returns 0 on success, negative on failure
1797 *
1798 * igb_probe initializes an adapter identified by a pci_dev structure.
1799 * The OS initialization, configuring of the adapter private structure,
1800 * and a hardware reset occur.
1801 **/
1802static int __devinit igb_probe(struct pci_dev *pdev,
1803 const struct pci_device_id *ent)
1804{
1805 struct net_device *netdev;
1806 struct igb_adapter *adapter;
1807 struct e1000_hw *hw;
4337e993 1808 u16 eeprom_data = 0;
9835fd73 1809 s32 ret_val;
4337e993 1810 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1811 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1812 unsigned long mmio_start, mmio_len;
2d6a5e95 1813 int err, pci_using_dac;
9d5c8243 1814 u16 eeprom_apme_mask = IGB_EEPROM_APME;
9835fd73 1815 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1816
bded64a7
AG		 1817 /* Catch broken hardware that put the wrong VF device ID in
1818 * the PCIe SR-IOV capability.
1819 */
1820 if (pdev->is_virtfn) {
1821 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1822 pci_name(pdev), pdev->vendor, pdev->device);
1823 return -EINVAL;
1824 }
1825
aed5dec3 1826 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1827 if (err)
1828 return err;
1829
1830 pci_using_dac = 0;
59d71989 1831 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1832 if (!err) {
59d71989 1833 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1834 if (!err)
1835 pci_using_dac = 1;
1836 } else {
59d71989 1837 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1838 if (err) {
59d71989 1839 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1840 if (err) {
1841 dev_err(&pdev->dev, "No usable DMA "
1842 "configuration, aborting\n");
1843 goto err_dma;
1844 }
1845 }
1846 }
1847
aed5dec3
AD		 1848 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1849 IORESOURCE_MEM),
1850 igb_driver_name);
9d5c8243
AK		 1851 if (err)
1852 goto err_pci_reg;
1853
19d5afd4 1854 pci_enable_pcie_error_reporting(pdev);
40a914fa 1855
9d5c8243 1856 pci_set_master(pdev);
c682fc23 1857 pci_save_state(pdev);
9d5c8243
AK		 1858
1859 err = -ENOMEM;
1bfaf07b 1860 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1861 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1862 if (!netdev)
1863 goto err_alloc_etherdev;
1864
1865 SET_NETDEV_DEV(netdev, &pdev->dev);
1866
1867 pci_set_drvdata(pdev, netdev);
1868 adapter = netdev_priv(netdev);
1869 adapter->netdev = netdev;
1870 adapter->pdev = pdev;
1871 hw = &adapter->hw;
1872 hw->back = adapter;
1873 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1874
1875 mmio_start = pci_resource_start(pdev, 0);
1876 mmio_len = pci_resource_len(pdev, 0);
1877
1878 err = -EIO;
28b0759c
AD		 1879 hw->hw_addr = ioremap(mmio_start, mmio_len);
1880 if (!hw->hw_addr)
9d5c8243
AK		 1881 goto err_ioremap;
1882
2e5c6922 1883 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1884 igb_set_ethtool_ops(netdev);
9d5c8243 1885 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1886
1887 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1888
1889 netdev->mem_start = mmio_start;
1890 netdev->mem_end = mmio_start + mmio_len;
1891
9d5c8243
AK		 1892 /* PCI config space info */
1893 hw->vendor_id = pdev->vendor;
1894 hw->device_id = pdev->device;
1895 hw->revision_id = pdev->revision;
1896 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1897 hw->subsystem_device_id = pdev->subsystem_device;
1898
9d5c8243
AK		 1899 /* Copy the default MAC, PHY and NVM function pointers */
1900 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1901 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1902 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1903 /* Initialize skew-specific constants */
1904 err = ei->get_invariants(hw);
1905 if (err)
450c87c8 1906 goto err_sw_init;
9d5c8243 1907
450c87c8 1908 /* setup the private structure */
9d5c8243
AK		 1909 err = igb_sw_init(adapter);
1910 if (err)
1911 goto err_sw_init;
1912
1913 igb_get_bus_info_pcie(hw);
1914
1915 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1916
1917 /* Copper options */
1918 if (hw->phy.media_type == e1000_media_type_copper) {
1919 hw->phy.mdix = AUTO_ALL_MODES;
1920 hw->phy.disable_polarity_correction = false;
1921 hw->phy.ms_type = e1000_ms_hw_default;
1922 }
1923
1924 if (igb_check_reset_block(hw))
1925 dev_info(&pdev->dev,
1926 "PHY reset is blocked due to SOL/IDER session.\n");
1927
077887c3
AD		 1928 /*
1929 * features is initialized to 0 in allocation, it might have bits
1930 * set by igb_sw_init so we should use an or instead of an
1931 * assignment.
1932 */
1933 netdev->features |= NETIF_F_SG |
1934 NETIF_F_IP_CSUM |
1935 NETIF_F_IPV6_CSUM |
1936 NETIF_F_TSO |
1937 NETIF_F_TSO6 |
1938 NETIF_F_RXHASH |
1939 NETIF_F_RXCSUM |
1940 NETIF_F_HW_VLAN_RX |
1941 NETIF_F_HW_VLAN_TX;
1942
1943 /* copy netdev features into list of user selectable features */
1944 netdev->hw_features |= netdev->features;
1945
1946 /* set this bit last since it cannot be part of hw_features */
1947 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1948
1949 netdev->vlan_features |= NETIF_F_TSO |
1950 NETIF_F_TSO6 |
1951 NETIF_F_IP_CSUM |
1952 NETIF_F_IPV6_CSUM |
1953 NETIF_F_SG;
48f29ffc 1954
7b872a55 1955 if (pci_using_dac) {
9d5c8243 1956 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1957 netdev->vlan_features |= NETIF_F_HIGHDMA;
1958 }
9d5c8243 1959
ac52caa3
MM		 1960 if (hw->mac.type >= e1000_82576) {
1961 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1962 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1963 }
b9473560 1964
01789349
JP		 1965 netdev->priv_flags |= IFF_UNICAST_FLT;
1966
330a6d6a 1967 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1968
1969 /* before reading the NVM, reset the controller to put the device in a
1970 * known good starting state */
1971 hw->mac.ops.reset_hw(hw);
1972
1973 /* make sure the NVM is good */
4322e561 1974 if (hw->nvm.ops.validate(hw) < 0) {
9d5c8243
AK		 1975 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1976 err = -EIO;
1977 goto err_eeprom;
1978 }
1979
1980 /* copy the MAC address out of the NVM */
1981 if (hw->mac.ops.read_mac_addr(hw))
1982 dev_err(&pdev->dev, "NVM Read Error\n");
1983
1984 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1985 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1986
1987 if (!is_valid_ether_addr(netdev->perm_addr)) {
1988 dev_err(&pdev->dev, "Invalid MAC Address\n");
1989 err = -EIO;
1990 goto err_eeprom;
1991 }
1992
c061b18d 1993 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 1994 (unsigned long) adapter);
c061b18d 1995 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 1996 (unsigned long) adapter);
9d5c8243
AK		 1997
1998 INIT_WORK(&adapter->reset_task, igb_reset_task);
1999 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2000
450c87c8 2001 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2002 adapter->fc_autoneg = true;
2003 hw->mac.autoneg = true;
2004 hw->phy.autoneg_advertised = 0x2f;
2005
0cce119a
AD		 2006 hw->fc.requested_mode = e1000_fc_default;
2007 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2008
9d5c8243
AK		 2009 igb_validate_mdi_setting(hw);
2010
9d5c8243
AK		 2011 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2012 * enable the ACPI Magic Packet filter
2013 */
2014
a2cf8b6c 2015 if (hw->bus.func == 0)
312c75ae 2016 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6d337dce 2017 else if (hw->mac.type >= e1000_82580)
55cac248
AD		 2018 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2019 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2020 &eeprom_data);
a2cf8b6c
AD		 2021 else if (hw->bus.func == 1)
2022 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 2023
2024 if (eeprom_data & eeprom_apme_mask)
2025 adapter->eeprom_wol |= E1000_WUFC_MAG;
2026
2027 /* now that we have the eeprom settings, apply the special cases where
2028 * the eeprom may be wrong or the board simply won't support wake on
2029 * lan on a particular port */
2030 switch (pdev->device) {
2031 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2032 adapter->eeprom_wol = 0;
2033 break;
2034 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2035 case E1000_DEV_ID_82576_FIBER:
2036 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2037 /* Wake events only supported on port A for dual fiber
2038 * regardless of eeprom setting */
2039 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2040 adapter->eeprom_wol = 0;
2041 break;
c8ea5ea9 2042 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2043 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2044 /* if quad port adapter, disable WoL on all but port A */
2045 if (global_quad_port_a != 0)
2046 adapter->eeprom_wol = 0;
2047 else
2048 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2049 /* Reset for multiple quad port adapters */
2050 if (++global_quad_port_a == 4)
2051 global_quad_port_a = 0;
2052 break;
9d5c8243
AK		 2053 }
2054
2055 /* initialize the wol settings based on the eeprom settings */
2056 adapter->wol = adapter->eeprom_wol;
e1b86d84 2057 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 2058
2059 /* reset the hardware with the new settings */
2060 igb_reset(adapter);
2061
2062 /* let the f/w know that the h/w is now under the control of the
2063 * driver. */
2064 igb_get_hw_control(adapter);
2065
9d5c8243
AK		 2066 strcpy(netdev->name, "eth%d");
2067 err = register_netdev(netdev);
2068 if (err)
2069 goto err_register;
2070
b168dfc5
JB		 2071 /* carrier off reporting is important to ethtool even BEFORE open */
2072 netif_carrier_off(netdev);
2073
421e02f0 2074#ifdef CONFIG_IGB_DCA
bbd98fe4 2075 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2076 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2077 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2078 igb_setup_dca(adapter);
2079 }
fe4506b6 2080
38c845c7 2081#endif
673b8b70
AB		 2082 /* do hw tstamp init after resetting */
2083 igb_init_hw_timer(adapter);
2084
9d5c8243
AK		 2085 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2086 /* print bus type/speed/width info */
7c510e4b 2087 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2088 netdev->name,
559e9c49 2089 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2090 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2091 "unknown"),
59c3de89
AD		 2092 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2093 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2094 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2095 "unknown"),
7c510e4b 2096 netdev->dev_addr);
9d5c8243 2097
9835fd73
CW		 2098 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2099 if (ret_val)
2100 strcpy(part_str, "Unknown");
2101 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2102 dev_info(&pdev->dev,
2103 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2104 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2105 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2106 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2107 switch (hw->mac.type) {
2108 case e1000_i350:
2109 igb_set_eee_i350(hw);
2110 break;
2111 default:
2112 break;
2113 }
9d5c8243
AK		 2114 return 0;
2115
2116err_register:
2117 igb_release_hw_control(adapter);
2118err_eeprom:
2119 if (!igb_check_reset_block(hw))
f5f4cf08 2120 igb_reset_phy(hw);
9d5c8243
AK		 2121
2122 if (hw->flash_address)
2123 iounmap(hw->flash_address);
9d5c8243 2124err_sw_init:
047e0030 2125 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2126 iounmap(hw->hw_addr);
2127err_ioremap:
2128 free_netdev(netdev);
2129err_alloc_etherdev:
559e9c49
AD		 2130 pci_release_selected_regions(pdev,
2131 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2132err_pci_reg:
2133err_dma:
2134 pci_disable_device(pdev);
2135 return err;
2136}
2137
2138/**
2139 * igb_remove - Device Removal Routine
2140 * @pdev: PCI device information struct
2141 *
2142 * igb_remove is called by the PCI subsystem to alert the driver
2143 * that it should release a PCI device. The could be caused by a
2144 * Hot-Plug event, or because the driver is going to be removed from
2145 * memory.
2146 **/
2147static void __devexit igb_remove(struct pci_dev *pdev)
2148{
2149 struct net_device *netdev = pci_get_drvdata(pdev);
2150 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2151 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2152
760141a5
TH		 2153 /*
2154 * The watchdog timer may be rescheduled, so explicitly
2155 * disable watchdog from being rescheduled.
2156 */
9d5c8243
AK		 2157 set_bit(__IGB_DOWN, &adapter->state);
2158 del_timer_sync(&adapter->watchdog_timer);
2159 del_timer_sync(&adapter->phy_info_timer);
2160
760141a5
TH		 2161 cancel_work_sync(&adapter->reset_task);
2162 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2163
421e02f0 2164#ifdef CONFIG_IGB_DCA
7dfc16fa 2165 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2166 dev_info(&pdev->dev, "DCA disabled\n");
2167 dca_remove_requester(&pdev->dev);
7dfc16fa 2168 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2169 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2170 }
2171#endif
2172
9d5c8243
AK		 2173 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2174 * would have already happened in close and is redundant. */
2175 igb_release_hw_control(adapter);
2176
2177 unregister_netdev(netdev);
2178
047e0030 2179 igb_clear_interrupt_scheme(adapter);
9d5c8243 2180
37680117
AD		 2181#ifdef CONFIG_PCI_IOV
2182 /* reclaim resources allocated to VFs */
2183 if (adapter->vf_data) {
2184 /* disable iov and allow time for transactions to clear */
0224d663
GR		 2185 if (!igb_check_vf_assignment(adapter)) {
2186 pci_disable_sriov(pdev);
2187 msleep(500);
2188 } else {
2189 dev_info(&pdev->dev, "VF(s) assigned to guests!\n");
2190 }
37680117
AD		 2191
2192 kfree(adapter->vf_data);
2193 adapter->vf_data = NULL;
2194 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2195 wrfl();
37680117
AD		 2196 msleep(100);
2197 dev_info(&pdev->dev, "IOV Disabled\n");
2198 }
2199#endif
559e9c49 2200
28b0759c
AD		 2201 iounmap(hw->hw_addr);
2202 if (hw->flash_address)
2203 iounmap(hw->flash_address);
559e9c49
AD		 2204 pci_release_selected_regions(pdev,
2205 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2206
1128c756 2207 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2208 free_netdev(netdev);
2209
19d5afd4 2210 pci_disable_pcie_error_reporting(pdev);
40a914fa 2211
9d5c8243
AK		 2212 pci_disable_device(pdev);
2213}
2214
a6b623e0
AD		 2215/**
2216 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2217 * @adapter: board private structure to initialize
2218 *
2219 * This function initializes the vf specific data storage and then attempts to
2220 * allocate the VFs. The reason for ordering it this way is because it is much
2221 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2222 * the memory for the VFs.
2223 **/
2224static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2225{
2226#ifdef CONFIG_PCI_IOV
2227 struct pci_dev *pdev = adapter->pdev;
0224d663
GR		 2228 int old_vfs = igb_find_enabled_vfs(adapter);
2229 int i;
a6b623e0 2230
0224d663
GR		 2231 if (old_vfs) {
2232 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2233 "max_vfs setting of %d\n", old_vfs, max_vfs);
2234 adapter->vfs_allocated_count = old_vfs;
a6b623e0
AD		 2235 }
2236
0224d663
GR		 2237 if (!adapter->vfs_allocated_count)
2238 return;
2239
2240 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2241 sizeof(struct vf_data_storage), GFP_KERNEL);
2242 /* if allocation failed then we do not support SR-IOV */
2243 if (!adapter->vf_data) {
a6b623e0 2244 adapter->vfs_allocated_count = 0;
0224d663
GR		 2245 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2246 "Data Storage\n");
2247 goto out;
a6b623e0 2248 }
0224d663
GR		 2249
2250 if (!old_vfs) {
2251 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2252 goto err_out;
2253 }
2254 dev_info(&pdev->dev, "%d VFs allocated\n",
2255 adapter->vfs_allocated_count);
2256 for (i = 0; i < adapter->vfs_allocated_count; i++)
2257 igb_vf_configure(adapter, i);
2258
2259 /* DMA Coalescing is not supported in IOV mode. */
2260 adapter->flags &= ~IGB_FLAG_DMAC;
2261 goto out;
2262err_out:
2263 kfree(adapter->vf_data);
2264 adapter->vf_data = NULL;
2265 adapter->vfs_allocated_count = 0;
2266out:
2267 return;
a6b623e0
AD		 2268#endif /* CONFIG_PCI_IOV */
2269}
2270
115f459a
AD		 2271/**
2272 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
2273 * @adapter: board private structure to initialize
2274 *
2275 * igb_init_hw_timer initializes the function pointer and values for the hw
2276 * timer found in hardware.
2277 **/
2278static void igb_init_hw_timer(struct igb_adapter *adapter)
2279{
2280 struct e1000_hw *hw = &adapter->hw;
2281
2282 switch (hw->mac.type) {
d2ba2ed8 2283 case e1000_i350:
55cac248
AD		 2284 case e1000_82580:
2285 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2286 adapter->cycles.read = igb_read_clock;
2287 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2288 adapter->cycles.mult = 1;
2289 /*
2290 * The 82580 timesync updates the system timer every 8ns by 8ns
2291 * and the value cannot be shifted. Instead we need to shift
2292 * the registers to generate a 64bit timer value. As a result
2293 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
2294 * 24 in order to generate a larger value for synchronization.
2295 */
2296 adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
2297 /* disable system timer temporarily by setting bit 31 */
2298 wr32(E1000_TSAUXC, 0x80000000);
2299 wrfl();
2300
2301 /* Set registers so that rollover occurs soon to test this. */
2302 wr32(E1000_SYSTIMR, 0x00000000);
2303 wr32(E1000_SYSTIML, 0x80000000);
2304 wr32(E1000_SYSTIMH, 0x000000FF);
2305 wrfl();
2306
2307 /* enable system timer by clearing bit 31 */
2308 wr32(E1000_TSAUXC, 0x0);
2309 wrfl();
2310
2311 timecounter_init(&adapter->clock,
2312 &adapter->cycles,
2313 ktime_to_ns(ktime_get_real()));
2314 /*
2315 * Synchronize our NIC clock against system wall clock. NIC
2316 * time stamp reading requires ~3us per sample, each sample
2317 * was pretty stable even under load => only require 10
2318 * samples for each offset comparison.
2319 */
2320 memset(&adapter->compare, 0, sizeof(adapter->compare));
2321 adapter->compare.source = &adapter->clock;
2322 adapter->compare.target = ktime_get_real;
2323 adapter->compare.num_samples = 10;
2324 timecompare_update(&adapter->compare, 0);
2325 break;
115f459a
AD		 2326 case e1000_82576:
2327 /*
2328 * Initialize hardware timer: we keep it running just in case
2329 * that some program needs it later on.
2330 */
2331 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
2332 adapter->cycles.read = igb_read_clock;
2333 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
2334 adapter->cycles.mult = 1;
2335 /**
2336 * Scale the NIC clock cycle by a large factor so that
2337 * relatively small clock corrections can be added or
25985edc 2338 * subtracted at each clock tick. The drawbacks of a large
115f459a
AD		 2339 * factor are a) that the clock register overflows more quickly
2340 * (not such a big deal) and b) that the increment per tick has
2341 * to fit into 24 bits. As a result we need to use a shift of
2342 * 19 so we can fit a value of 16 into the TIMINCA register.
2343 */
2344 adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
2345 wr32(E1000_TIMINCA,
2346 (1 << E1000_TIMINCA_16NS_SHIFT) |
2347 (16 << IGB_82576_TSYNC_SHIFT));
2348
2349 /* Set registers so that rollover occurs soon to test this. */
2350 wr32(E1000_SYSTIML, 0x00000000);
2351 wr32(E1000_SYSTIMH, 0xFF800000);
2352 wrfl();
2353
2354 timecounter_init(&adapter->clock,
2355 &adapter->cycles,
2356 ktime_to_ns(ktime_get_real()));
2357 /*
2358 * Synchronize our NIC clock against system wall clock. NIC
2359 * time stamp reading requires ~3us per sample, each sample
2360 * was pretty stable even under load => only require 10
2361 * samples for each offset comparison.
2362 */
2363 memset(&adapter->compare, 0, sizeof(adapter->compare));
2364 adapter->compare.source = &adapter->clock;
2365 adapter->compare.target = ktime_get_real;
2366 adapter->compare.num_samples = 10;
2367 timecompare_update(&adapter->compare, 0);
2368 break;
2369 case e1000_82575:
2370 /* 82575 does not support timesync */
2371 default:
2372 break;
2373 }
2374
2375}
2376
9d5c8243
AK		 2377/**
2378 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2379 * @adapter: board private structure to initialize
2380 *
2381 * igb_sw_init initializes the Adapter private data structure.
2382 * Fields are initialized based on PCI device information and
2383 * OS network device settings (MTU size).
2384 **/
2385static int __devinit igb_sw_init(struct igb_adapter *adapter)
2386{
2387 struct e1000_hw *hw = &adapter->hw;
2388 struct net_device *netdev = adapter->netdev;
2389 struct pci_dev *pdev = adapter->pdev;
2390
2391 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2392
13fde97a 2393 /* set default ring sizes */
68fd9910
AD		 2394 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2395 adapter->rx_ring_count = IGB_DEFAULT_RXD;
13fde97a
AD		 2396
2397 /* set default ITR values */
4fc82adf
AD		 2398 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2399 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2400
13fde97a
AD		 2401 /* set default work limits */
2402 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2403
153285f9
AD		 2404 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2405 VLAN_HLEN;
9d5c8243
AK		 2406 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2407
81c2fc22
AD		 2408 adapter->node = -1;
2409
12dcd86b 2410 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2411#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2412 switch (hw->mac.type) {
2413 case e1000_82576:
2414 case e1000_i350:
9b082d73
SA		 2415 if (max_vfs > 7) {
2416 dev_warn(&pdev->dev,
2417 "Maximum of 7 VFs per PF, using max\n");
2418 adapter->vfs_allocated_count = 7;
2419 } else
2420 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2421 break;
2422 default:
2423 break;
2424 }
a6b623e0 2425#endif /* CONFIG_PCI_IOV */
a99955fc 2426 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
665c8c8e
WM		 2427 /* i350 cannot do RSS and SR-IOV at the same time */
2428 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
2429 adapter->rss_queues = 1;
a99955fc
AD		 2430
2431 /*
2432 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2433 * then we should combine the queues into a queue pair in order to
2434 * conserve interrupts due to limited supply
2435 */
2436 if ((adapter->rss_queues > 4) ||
2437 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2438 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2439
1128c756
CW		 2440 /* Setup and initialize a copy of the hw vlan table array */
2441 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2442 E1000_VLAN_FILTER_TBL_SIZE,
2443 GFP_ATOMIC);
2444
a6b623e0 2445 /* This call may decrease the number of queues */
047e0030 2446 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2447 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2448 return -ENOMEM;
2449 }
2450
a6b623e0
AD		 2451 igb_probe_vfs(adapter);
2452
9d5c8243
AK		 2453 /* Explicitly disable IRQ since the NIC can be in any state. */
2454 igb_irq_disable(adapter);
2455
831ec0b4
CW		 2456 if (hw->mac.type == e1000_i350)
2457 adapter->flags &= ~IGB_FLAG_DMAC;
2458
9d5c8243
AK		 2459 set_bit(__IGB_DOWN, &adapter->state);
2460 return 0;
2461}
2462
2463/**
2464 * igb_open - Called when a network interface is made active
2465 * @netdev: network interface device structure
2466 *
2467 * Returns 0 on success, negative value on failure
2468 *
2469 * The open entry point is called when a network interface is made
2470 * active by the system (IFF_UP). At this point all resources needed
2471 * for transmit and receive operations are allocated, the interrupt
2472 * handler is registered with the OS, the watchdog timer is started,
2473 * and the stack is notified that the interface is ready.
2474 **/
2475static int igb_open(struct net_device *netdev)
2476{
2477 struct igb_adapter *adapter = netdev_priv(netdev);
2478 struct e1000_hw *hw = &adapter->hw;
2479 int err;
2480 int i;
2481
2482 /* disallow open during test */
2483 if (test_bit(__IGB_TESTING, &adapter->state))
2484 return -EBUSY;
2485
b168dfc5
JB		 2486 netif_carrier_off(netdev);
2487
9d5c8243
AK		 2488 /* allocate transmit descriptors */
2489 err = igb_setup_all_tx_resources(adapter);
2490 if (err)
2491 goto err_setup_tx;
2492
2493 /* allocate receive descriptors */
2494 err = igb_setup_all_rx_resources(adapter);
2495 if (err)
2496 goto err_setup_rx;
2497
88a268c1 2498 igb_power_up_link(adapter);
9d5c8243 2499
9d5c8243
AK		 2500 /* before we allocate an interrupt, we must be ready to handle it.
2501 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2502 * as soon as we call pci_request_irq, so we have to setup our
2503 * clean_rx handler before we do so. */
2504 igb_configure(adapter);
2505
2506 err = igb_request_irq(adapter);
2507 if (err)
2508 goto err_req_irq;
2509
2510 /* From here on the code is the same as igb_up() */
2511 clear_bit(__IGB_DOWN, &adapter->state);
2512
0d1ae7f4
AD		 2513 for (i = 0; i < adapter->num_q_vectors; i++)
2514 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2515
2516 /* Clear any pending interrupts. */
2517 rd32(E1000_ICR);
844290e5
PW		 2518
2519 igb_irq_enable(adapter);
2520
d4960307
AD		 2521 /* notify VFs that reset has been completed */
2522 if (adapter->vfs_allocated_count) {
2523 u32 reg_data = rd32(E1000_CTRL_EXT);
2524 reg_data |= E1000_CTRL_EXT_PFRSTD;
2525 wr32(E1000_CTRL_EXT, reg_data);
2526 }
2527
d55b53ff
JK		 2528 netif_tx_start_all_queues(netdev);
2529
25568a53
AD		 2530 /* start the watchdog. */
2531 hw->mac.get_link_status = 1;
2532 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2533
2534 return 0;
2535
2536err_req_irq:
2537 igb_release_hw_control(adapter);
88a268c1 2538 igb_power_down_link(adapter);
9d5c8243
AK		 2539 igb_free_all_rx_resources(adapter);
2540err_setup_rx:
2541 igb_free_all_tx_resources(adapter);
2542err_setup_tx:
2543 igb_reset(adapter);
2544
2545 return err;
2546}
2547
2548/**
2549 * igb_close - Disables a network interface
2550 * @netdev: network interface device structure
2551 *
2552 * Returns 0, this is not allowed to fail
2553 *
2554 * The close entry point is called when an interface is de-activated
2555 * by the OS. The hardware is still under the driver's control, but
2556 * needs to be disabled. A global MAC reset is issued to stop the
2557 * hardware, and all transmit and receive resources are freed.
2558 **/
2559static int igb_close(struct net_device *netdev)
2560{
2561 struct igb_adapter *adapter = netdev_priv(netdev);
2562
2563 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2564 igb_down(adapter);
2565
2566 igb_free_irq(adapter);
2567
2568 igb_free_all_tx_resources(adapter);
2569 igb_free_all_rx_resources(adapter);
2570
9d5c8243
AK		 2571 return 0;
2572}
2573
2574/**
2575 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2576 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2577 *
2578 * Return 0 on success, negative on failure
2579 **/
80785298 2580int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2581{
59d71989 2582 struct device *dev = tx_ring->dev;
81c2fc22 2583 int orig_node = dev_to_node(dev);
9d5c8243
AK		 2584 int size;
2585
06034649 2586 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
81c2fc22
AD		 2587 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
2588 if (!tx_ring->tx_buffer_info)
2589 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2590 if (!tx_ring->tx_buffer_info)
9d5c8243 2591 goto err;
9d5c8243
AK		 2592
2593 /* round up to nearest 4K */
85e8d004 2594 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2595 tx_ring->size = ALIGN(tx_ring->size, 4096);
2596
81c2fc22 2597 set_dev_node(dev, tx_ring->numa_node);
59d71989
AD		 2598 tx_ring->desc = dma_alloc_coherent(dev,
2599 tx_ring->size,
2600 &tx_ring->dma,
2601 GFP_KERNEL);
81c2fc22
AD		 2602 set_dev_node(dev, orig_node);
2603 if (!tx_ring->desc)
2604 tx_ring->desc = dma_alloc_coherent(dev,
2605 tx_ring->size,
2606 &tx_ring->dma,
2607 GFP_KERNEL);
9d5c8243
AK		 2608
2609 if (!tx_ring->desc)
2610 goto err;
2611
9d5c8243
AK		 2612 tx_ring->next_to_use = 0;
2613 tx_ring->next_to_clean = 0;
81c2fc22 2614
9d5c8243
AK		 2615 return 0;
2616
2617err:
06034649 2618 vfree(tx_ring->tx_buffer_info);
59d71989 2619 dev_err(dev,
9d5c8243
AK		 2620 "Unable to allocate memory for the transmit descriptor ring\n");
2621 return -ENOMEM;
2622}
2623
2624/**
2625 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2626 * (Descriptors) for all queues
2627 * @adapter: board private structure
2628 *
2629 * Return 0 on success, negative on failure
2630 **/
2631static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2632{
439705e1 2633 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2634 int i, err = 0;
2635
2636 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2637 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2638 if (err) {
439705e1 2639 dev_err(&pdev->dev,
9d5c8243
AK		 2640 "Allocation for Tx Queue %u failed\n", i);
2641 for (i--; i >= 0; i--)
3025a446 2642 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2643 break;
2644 }
2645 }
2646
2647 return err;
2648}
2649
2650/**
85b430b4
AD		 2651 * igb_setup_tctl - configure the transmit control registers
2652 * @adapter: Board private structure
9d5c8243 2653 **/
d7ee5b3a 2654void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2655{
9d5c8243
AK		 2656 struct e1000_hw *hw = &adapter->hw;
2657 u32 tctl;
9d5c8243 2658
85b430b4
AD		 2659 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2660 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2661
2662 /* Program the Transmit Control Register */
9d5c8243
AK		 2663 tctl = rd32(E1000_TCTL);
2664 tctl &= ~E1000_TCTL_CT;
2665 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2666 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2667
2668 igb_config_collision_dist(hw);
2669
9d5c8243
AK		 2670 /* Enable transmits */
2671 tctl |= E1000_TCTL_EN;
2672
2673 wr32(E1000_TCTL, tctl);
2674}
2675
85b430b4
AD		 2676/**
2677 * igb_configure_tx_ring - Configure transmit ring after Reset
2678 * @adapter: board private structure
2679 * @ring: tx ring to configure
2680 *
2681 * Configure a transmit ring after a reset.
2682 **/
d7ee5b3a
AD		 2683void igb_configure_tx_ring(struct igb_adapter *adapter,
2684 struct igb_ring *ring)
85b430b4
AD		 2685{
2686 struct e1000_hw *hw = &adapter->hw;
a74420e0 2687 u32 txdctl = 0;
85b430b4
AD		 2688 u64 tdba = ring->dma;
2689 int reg_idx = ring->reg_idx;
2690
2691 /* disable the queue */
a74420e0 2692 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2693 wrfl();
2694 mdelay(10);
2695
2696 wr32(E1000_TDLEN(reg_idx),
2697 ring->count * sizeof(union e1000_adv_tx_desc));
2698 wr32(E1000_TDBAL(reg_idx),
2699 tdba & 0x00000000ffffffffULL);
2700 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2701
fce99e34 2702 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2703 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2704 writel(0, ring->tail);
85b430b4
AD		 2705
2706 txdctl |= IGB_TX_PTHRESH;
2707 txdctl |= IGB_TX_HTHRESH << 8;
2708 txdctl |= IGB_TX_WTHRESH << 16;
2709
2710 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2711 wr32(E1000_TXDCTL(reg_idx), txdctl);
2712}
2713
2714/**
2715 * igb_configure_tx - Configure transmit Unit after Reset
2716 * @adapter: board private structure
2717 *
2718 * Configure the Tx unit of the MAC after a reset.
2719 **/
2720static void igb_configure_tx(struct igb_adapter *adapter)
2721{
2722 int i;
2723
2724 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2725 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2726}
2727
9d5c8243
AK		 2728/**
2729 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2730 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2731 *
2732 * Returns 0 on success, negative on failure
2733 **/
80785298 2734int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2735{
59d71989 2736 struct device *dev = rx_ring->dev;
81c2fc22 2737 int orig_node = dev_to_node(dev);
9d5c8243
AK		 2738 int size, desc_len;
2739
06034649 2740 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
81c2fc22
AD		 2741 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
2742 if (!rx_ring->rx_buffer_info)
2743 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2744 if (!rx_ring->rx_buffer_info)
9d5c8243 2745 goto err;
9d5c8243
AK		 2746
2747 desc_len = sizeof(union e1000_adv_rx_desc);
2748
2749 /* Round up to nearest 4K */
2750 rx_ring->size = rx_ring->count * desc_len;
2751 rx_ring->size = ALIGN(rx_ring->size, 4096);
2752
81c2fc22 2753 set_dev_node(dev, rx_ring->numa_node);
59d71989
AD		 2754 rx_ring->desc = dma_alloc_coherent(dev,
2755 rx_ring->size,
2756 &rx_ring->dma,
2757 GFP_KERNEL);
81c2fc22
AD		 2758 set_dev_node(dev, orig_node);
2759 if (!rx_ring->desc)
2760 rx_ring->desc = dma_alloc_coherent(dev,
2761 rx_ring->size,
2762 &rx_ring->dma,
2763 GFP_KERNEL);
9d5c8243
AK		 2764
2765 if (!rx_ring->desc)
2766 goto err;
2767
2768 rx_ring->next_to_clean = 0;
2769 rx_ring->next_to_use = 0;
9d5c8243 2770
9d5c8243
AK		 2771 return 0;
2772
2773err:
06034649
AD		 2774 vfree(rx_ring->rx_buffer_info);
2775 rx_ring->rx_buffer_info = NULL;
59d71989
AD		 2776 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2777 " ring\n");
9d5c8243
AK		 2778 return -ENOMEM;
2779}
2780
2781/**
2782 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2783 * (Descriptors) for all queues
2784 * @adapter: board private structure
2785 *
2786 * Return 0 on success, negative on failure
2787 **/
2788static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2789{
439705e1 2790 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2791 int i, err = 0;
2792
2793 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2794 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2795 if (err) {
439705e1 2796 dev_err(&pdev->dev,
9d5c8243
AK		 2797 "Allocation for Rx Queue %u failed\n", i);
2798 for (i--; i >= 0; i--)
3025a446 2799 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2800 break;
2801 }
2802 }
2803
2804 return err;
2805}
2806
06cf2666
AD		 2807/**
2808 * igb_setup_mrqc - configure the multiple receive queue control registers
2809 * @adapter: Board private structure
2810 **/
2811static void igb_setup_mrqc(struct igb_adapter *adapter)
2812{
2813 struct e1000_hw *hw = &adapter->hw;
2814 u32 mrqc, rxcsum;
2815 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2816 union e1000_reta {
2817 u32 dword;
2818 u8 bytes[4];
2819 } reta;
2820 static const u8 rsshash[40] = {
2821 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2822 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2823 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2824 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2825
2826 /* Fill out hash function seeds */
2827 for (j = 0; j < 10; j++) {
2828 u32 rsskey = rsshash[(j * 4)];
2829 rsskey |= rsshash[(j * 4) + 1] << 8;
2830 rsskey |= rsshash[(j * 4) + 2] << 16;
2831 rsskey |= rsshash[(j * 4) + 3] << 24;
2832 array_wr32(E1000_RSSRK(0), j, rsskey);
2833 }
2834
a99955fc 2835 num_rx_queues = adapter->rss_queues;
06cf2666
AD		 2836
2837 if (adapter->vfs_allocated_count) {
2838 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2839 switch (hw->mac.type) {
d2ba2ed8 2840 case e1000_i350:
55cac248
AD		 2841 case e1000_82580:
2842 num_rx_queues = 1;
2843 shift = 0;
2844 break;
06cf2666
AD		 2845 case e1000_82576:
2846 shift = 3;
2847 num_rx_queues = 2;
2848 break;
2849 case e1000_82575:
2850 shift = 2;
2851 shift2 = 6;
2852 default:
2853 break;
2854 }
2855 } else {
2856 if (hw->mac.type == e1000_82575)
2857 shift = 6;
2858 }
2859
2860 for (j = 0; j < (32 * 4); j++) {
2861 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2862 if (shift2)
2863 reta.bytes[j & 3] |= num_rx_queues << shift2;
2864 if ((j & 3) == 3)
2865 wr32(E1000_RETA(j >> 2), reta.dword);
2866 }
2867
2868 /*
2869 * Disable raw packet checksumming so that RSS hash is placed in
2870 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2871 * offloads as they are enabled by default
2872 */
2873 rxcsum = rd32(E1000_RXCSUM);
2874 rxcsum |= E1000_RXCSUM_PCSD;
2875
2876 if (adapter->hw.mac.type >= e1000_82576)
2877 /* Enable Receive Checksum Offload for SCTP */
2878 rxcsum |= E1000_RXCSUM_CRCOFL;
2879
2880 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2881 wr32(E1000_RXCSUM, rxcsum);
2882
2883 /* If VMDq is enabled then we set the appropriate mode for that, else
2884 * we default to RSS so that an RSS hash is calculated per packet even
2885 * if we are only using one queue */
2886 if (adapter->vfs_allocated_count) {
2887 if (hw->mac.type > e1000_82575) {
2888 /* Set the default pool for the PF's first queue */
2889 u32 vtctl = rd32(E1000_VT_CTL);
2890 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2891 E1000_VT_CTL_DISABLE_DEF_POOL);
2892 vtctl |= adapter->vfs_allocated_count <<
2893 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2894 wr32(E1000_VT_CTL, vtctl);
2895 }
a99955fc 2896 if (adapter->rss_queues > 1)
06cf2666
AD		 2897 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2898 else
2899 mrqc = E1000_MRQC_ENABLE_VMDQ;
2900 } else {
2901 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2902 }
2903 igb_vmm_control(adapter);
2904
4478a9cd
AD		 2905 /*
2906 * Generate RSS hash based on TCP port numbers and/or
2907 * IPv4/v6 src and dst addresses since UDP cannot be
2908 * hashed reliably due to IP fragmentation
2909 */
2910 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2911 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2912 E1000_MRQC_RSS_FIELD_IPV6 |
2913 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2914 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2915
2916 wr32(E1000_MRQC, mrqc);
2917}
2918
9d5c8243
AK		 2919/**
2920 * igb_setup_rctl - configure the receive control registers
2921 * @adapter: Board private structure
2922 **/
d7ee5b3a 2923void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2924{
2925 struct e1000_hw *hw = &adapter->hw;
2926 u32 rctl;
9d5c8243
AK		 2927
2928 rctl = rd32(E1000_RCTL);
2929
2930 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2931 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2932
69d728ba 2933 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2934 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2935
87cb7e8c
AK		 2936 /*
2937 * enable stripping of CRC. It's unlikely this will break BMC
2938 * redirection as it did with e1000. Newer features require
2939 * that the HW strips the CRC.
73cd78f1 2940 */
87cb7e8c 2941 rctl |= E1000_RCTL_SECRC;
9d5c8243 2942
559e9c49 2943 /* disable store bad packets and clear size bits. */
ec54d7d6 2944 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2945
6ec43fe6
AD		 2946 /* enable LPE to prevent packets larger than max_frame_size */
2947 rctl |= E1000_RCTL_LPE;
9d5c8243 2948
952f72a8
AD		 2949 /* disable queue 0 to prevent tail write w/o re-config */
2950 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2951
e1739522
AD		 2952 /* Attention!!! For SR-IOV PF driver operations you must enable
2953 * queue drop for all VF and PF queues to prevent head of line blocking
2954 * if an un-trusted VF does not provide descriptors to hardware.
2955 */
2956 if (adapter->vfs_allocated_count) {
e1739522
AD		 2957 /* set all queue drop enable bits */
2958 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2959 }
2960
9d5c8243
AK		 2961 wr32(E1000_RCTL, rctl);
2962}
2963
7d5753f0
AD		 2964static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2965 int vfn)
2966{
2967 struct e1000_hw *hw = &adapter->hw;
2968 u32 vmolr;
2969
2970 /* if it isn't the PF check to see if VFs are enabled and
2971 * increase the size to support vlan tags */
2972 if (vfn < adapter->vfs_allocated_count &&
2973 adapter->vf_data[vfn].vlans_enabled)
2974 size += VLAN_TAG_SIZE;
2975
2976 vmolr = rd32(E1000_VMOLR(vfn));
2977 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2978 vmolr |= size | E1000_VMOLR_LPE;
2979 wr32(E1000_VMOLR(vfn), vmolr);
2980
2981 return 0;
2982}
2983
e1739522
AD		 2984/**
2985 * igb_rlpml_set - set maximum receive packet size
2986 * @adapter: board private structure
2987 *
2988 * Configure maximum receivable packet size.
2989 **/
2990static void igb_rlpml_set(struct igb_adapter *adapter)
2991{
153285f9 2992 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 2993 struct e1000_hw *hw = &adapter->hw;
2994 u16 pf_id = adapter->vfs_allocated_count;
2995
e1739522
AD		 2996 if (pf_id) {
2997 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 2998 /*
2999 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3000 * to our max jumbo frame size, in case we need to enable
3001 * jumbo frames on one of the rings later.
3002 * This will not pass over-length frames into the default
3003 * queue because it's gated by the VMOLR.RLPML.
3004 */
7d5753f0 3005 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3006 }
3007
3008 wr32(E1000_RLPML, max_frame_size);
3009}
3010
8151d294
WM		 3011static inline void igb_set_vmolr(struct igb_adapter *adapter,
3012 int vfn, bool aupe)
7d5753f0
AD		 3013{
3014 struct e1000_hw *hw = &adapter->hw;
3015 u32 vmolr;
3016
3017 /*
3018 * This register exists only on 82576 and newer so if we are older then
3019 * we should exit and do nothing
3020 */
3021 if (hw->mac.type < e1000_82576)
3022 return;
3023
3024 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3025 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3026 if (aupe)
3027 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3028 else
3029 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3030
3031 /* clear all bits that might not be set */
3032 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3033
a99955fc 3034 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3035 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3036 /*
3037 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3038 * multicast packets
3039 */
3040 if (vfn <= adapter->vfs_allocated_count)
3041 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3042
3043 wr32(E1000_VMOLR(vfn), vmolr);
3044}
3045
85b430b4
AD		 3046/**
3047 * igb_configure_rx_ring - Configure a receive ring after Reset
3048 * @adapter: board private structure
3049 * @ring: receive ring to be configured
3050 *
3051 * Configure the Rx unit of the MAC after a reset.
3052 **/
d7ee5b3a
AD		 3053void igb_configure_rx_ring(struct igb_adapter *adapter,
3054 struct igb_ring *ring)
85b430b4
AD		 3055{
3056 struct e1000_hw *hw = &adapter->hw;
3057 u64 rdba = ring->dma;
3058 int reg_idx = ring->reg_idx;
a74420e0 3059 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3060
3061 /* disable the queue */
a74420e0 3062 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3063
3064 /* Set DMA base address registers */
3065 wr32(E1000_RDBAL(reg_idx),
3066 rdba & 0x00000000ffffffffULL);
3067 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3068 wr32(E1000_RDLEN(reg_idx),
3069 ring->count * sizeof(union e1000_adv_rx_desc));
3070
3071 /* initialize head and tail */
fce99e34 3072 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3073 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3074 writel(0, ring->tail);
85b430b4 3075
952f72a8 3076 /* set descriptor configuration */
44390ca6 3077 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
952f72a8 3078#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
44390ca6 3079 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3080#else
44390ca6 3081 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3082#endif
44390ca6 3083 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
06218a8d 3084 if (hw->mac.type >= e1000_82580)
757b77e2 3085 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3086 /* Only set Drop Enable if we are supporting multiple queues */
3087 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3088 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3089
3090 wr32(E1000_SRRCTL(reg_idx), srrctl);
3091
7d5753f0 3092 /* set filtering for VMDQ pools */
8151d294 3093 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3094
85b430b4
AD		 3095 rxdctl |= IGB_RX_PTHRESH;
3096 rxdctl |= IGB_RX_HTHRESH << 8;
3097 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3098
3099 /* enable receive descriptor fetching */
3100 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3101 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3102}
3103
9d5c8243
AK		 3104/**
3105 * igb_configure_rx - Configure receive Unit after Reset
3106 * @adapter: board private structure
3107 *
3108 * Configure the Rx unit of the MAC after a reset.
3109 **/
3110static void igb_configure_rx(struct igb_adapter *adapter)
3111{
9107584e 3112 int i;
9d5c8243 3113
68d480c4
AD		 3114 /* set UTA to appropriate mode */
3115 igb_set_uta(adapter);
3116
26ad9178
AD		 3117 /* set the correct pool for the PF default MAC address in entry 0 */
3118 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3119 adapter->vfs_allocated_count);
3120
06cf2666
AD		 3121 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3122 * the Base and Length of the Rx Descriptor Ring */
3123 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3124 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3125}
3126
3127/**
3128 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3129 * @tx_ring: Tx descriptor ring for a specific queue
3130 *
3131 * Free all transmit software resources
3132 **/
68fd9910 3133void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3134{
3b644cf6 3135 igb_clean_tx_ring(tx_ring);
9d5c8243 3136
06034649
AD		 3137 vfree(tx_ring->tx_buffer_info);
3138 tx_ring->tx_buffer_info = NULL;
9d5c8243 3139
439705e1
AD		 3140 /* if not set, then don't free */
3141 if (!tx_ring->desc)
3142 return;
3143
59d71989
AD		 3144 dma_free_coherent(tx_ring->dev, tx_ring->size,
3145 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3146
3147 tx_ring->desc = NULL;
3148}
3149
3150/**
3151 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3152 * @adapter: board private structure
3153 *
3154 * Free all transmit software resources
3155 **/
3156static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3157{
3158 int i;
3159
3160 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3161 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3162}
3163
ebe42d16
AD		 3164void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3165 struct igb_tx_buffer *tx_buffer)
3166{
3167 if (tx_buffer->skb) {
3168 dev_kfree_skb_any(tx_buffer->skb);
3169 if (tx_buffer->dma)
3170 dma_unmap_single(ring->dev,
3171 tx_buffer->dma,
3172 tx_buffer->length,
3173 DMA_TO_DEVICE);
3174 } else if (tx_buffer->dma) {
3175 dma_unmap_page(ring->dev,
3176 tx_buffer->dma,
3177 tx_buffer->length,
3178 DMA_TO_DEVICE);
3179 }
3180 tx_buffer->next_to_watch = NULL;
3181 tx_buffer->skb = NULL;
3182 tx_buffer->dma = 0;
3183 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3184}
3185
3186/**
3187 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3188 * @tx_ring: ring to be cleaned
3189 **/
3b644cf6 3190static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3191{
06034649 3192 struct igb_tx_buffer *buffer_info;
9d5c8243 3193 unsigned long size;
6ad4edfc 3194 u16 i;
9d5c8243 3195
06034649 3196 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3197 return;
3198 /* Free all the Tx ring sk_buffs */
3199
3200 for (i = 0; i < tx_ring->count; i++) {
06034649 3201 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3202 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243 3203 }
bdbc0631 3204 netdev_tx_reset_queue(txring_txq(tx_ring));
9d5c8243 3205
06034649
AD		 3206 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3207 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3208
3209 /* Zero out the descriptor ring */
9d5c8243
AK		 3210 memset(tx_ring->desc, 0, tx_ring->size);
3211
3212 tx_ring->next_to_use = 0;
3213 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3214}
3215
3216/**
3217 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3218 * @adapter: board private structure
3219 **/
3220static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3221{
3222 int i;
3223
3224 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3225 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3226}
3227
3228/**
3229 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3230 * @rx_ring: ring to clean the resources from
3231 *
3232 * Free all receive software resources
3233 **/
68fd9910 3234void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3235{
3b644cf6 3236 igb_clean_rx_ring(rx_ring);
9d5c8243 3237
06034649
AD		 3238 vfree(rx_ring->rx_buffer_info);
3239 rx_ring->rx_buffer_info = NULL;
9d5c8243 3240
439705e1
AD		 3241 /* if not set, then don't free */
3242 if (!rx_ring->desc)
3243 return;
3244
59d71989
AD		 3245 dma_free_coherent(rx_ring->dev, rx_ring->size,
3246 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3247
3248 rx_ring->desc = NULL;
3249}
3250
3251/**
3252 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3253 * @adapter: board private structure
3254 *
3255 * Free all receive software resources
3256 **/
3257static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3258{
3259 int i;
3260
3261 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3262 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3263}
3264
3265/**
3266 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3267 * @rx_ring: ring to free buffers from
3268 **/
3b644cf6 3269static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3270{
9d5c8243 3271 unsigned long size;
c023cd88 3272 u16 i;
9d5c8243 3273
06034649 3274 if (!rx_ring->rx_buffer_info)
9d5c8243 3275 return;
439705e1 3276
9d5c8243
AK		 3277 /* Free all the Rx ring sk_buffs */
3278 for (i = 0; i < rx_ring->count; i++) {
06034649 3279 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3280 if (buffer_info->dma) {
59d71989 3281 dma_unmap_single(rx_ring->dev,
80785298 3282 buffer_info->dma,
44390ca6 3283 IGB_RX_HDR_LEN,
59d71989 3284 DMA_FROM_DEVICE);
9d5c8243
AK		 3285 buffer_info->dma = 0;
3286 }
3287
3288 if (buffer_info->skb) {
3289 dev_kfree_skb(buffer_info->skb);
3290 buffer_info->skb = NULL;
3291 }
6ec43fe6 3292 if (buffer_info->page_dma) {
59d71989 3293 dma_unmap_page(rx_ring->dev,
80785298 3294 buffer_info->page_dma,
6ec43fe6 3295 PAGE_SIZE / 2,
59d71989 3296 DMA_FROM_DEVICE);
6ec43fe6
AD		 3297 buffer_info->page_dma = 0;
3298 }
9d5c8243 3299 if (buffer_info->page) {
9d5c8243
AK		 3300 put_page(buffer_info->page);
3301 buffer_info->page = NULL;
bf36c1a0 3302 buffer_info->page_offset = 0;
9d5c8243
AK		 3303 }
3304 }
3305
06034649
AD		 3306 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3307 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3308
3309 /* Zero out the descriptor ring */
3310 memset(rx_ring->desc, 0, rx_ring->size);
3311
3312 rx_ring->next_to_clean = 0;
3313 rx_ring->next_to_use = 0;
9d5c8243
AK		 3314}
3315
3316/**
3317 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3318 * @adapter: board private structure
3319 **/
3320static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3321{
3322 int i;
3323
3324 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3325 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3326}
3327
3328/**
3329 * igb_set_mac - Change the Ethernet Address of the NIC
3330 * @netdev: network interface device structure
3331 * @p: pointer to an address structure
3332 *
3333 * Returns 0 on success, negative on failure
3334 **/
3335static int igb_set_mac(struct net_device *netdev, void *p)
3336{
3337 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3338 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3339 struct sockaddr *addr = p;
3340
3341 if (!is_valid_ether_addr(addr->sa_data))
3342 return -EADDRNOTAVAIL;
3343
3344 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3345 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3346
26ad9178
AD		 3347 /* set the correct pool for the new PF MAC address in entry 0 */
3348 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3349 adapter->vfs_allocated_count);
e1739522 3350
9d5c8243
AK		 3351 return 0;
3352}
3353
3354/**
68d480c4 3355 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3356 * @netdev: network interface device structure
3357 *
68d480c4
AD		 3358 * Writes multicast address list to the MTA hash table.
3359 * Returns: -ENOMEM on failure
3360 * 0 on no addresses written
3361 * X on writing X addresses to MTA
9d5c8243 3362 **/
68d480c4 3363static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3364{
3365 struct igb_adapter *adapter = netdev_priv(netdev);
3366 struct e1000_hw *hw = &adapter->hw;
22bedad3 3367 struct netdev_hw_addr *ha;
68d480c4 3368 u8 *mta_list;
9d5c8243
AK		 3369 int i;
3370
4cd24eaf 3371 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3372 /* nothing to program, so clear mc list */
3373 igb_update_mc_addr_list(hw, NULL, 0);
3374 igb_restore_vf_multicasts(adapter);
3375 return 0;
3376 }
9d5c8243 3377
4cd24eaf 3378 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3379 if (!mta_list)
3380 return -ENOMEM;
ff41f8dc 3381
68d480c4 3382 /* The shared function expects a packed array of only addresses. */
48e2f183 3383 i = 0;
22bedad3
JP		 3384 netdev_for_each_mc_addr(ha, netdev)
3385 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3386
68d480c4
AD		 3387 igb_update_mc_addr_list(hw, mta_list, i);
3388 kfree(mta_list);
3389
4cd24eaf 3390 return netdev_mc_count(netdev);
68d480c4
AD		 3391}
3392
3393/**
3394 * igb_write_uc_addr_list - write unicast addresses to RAR table
3395 * @netdev: network interface device structure
3396 *
3397 * Writes unicast address list to the RAR table.
3398 * Returns: -ENOMEM on failure/insufficient address space
3399 * 0 on no addresses written
3400 * X on writing X addresses to the RAR table
3401 **/
3402static int igb_write_uc_addr_list(struct net_device *netdev)
3403{
3404 struct igb_adapter *adapter = netdev_priv(netdev);
3405 struct e1000_hw *hw = &adapter->hw;
3406 unsigned int vfn = adapter->vfs_allocated_count;
3407 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3408 int count = 0;
3409
3410 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3411 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3412 return -ENOMEM;
9d5c8243 3413
32e7bfc4 3414 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3415 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3416
3417 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3418 if (!rar_entries)
3419 break;
26ad9178
AD		 3420 igb_rar_set_qsel(adapter, ha->addr,
3421 rar_entries--,
68d480c4
AD		 3422 vfn);
3423 count++;
ff41f8dc
AD		 3424 }
3425 }
3426 /* write the addresses in reverse order to avoid write combining */
3427 for (; rar_entries > 0 ; rar_entries--) {
3428 wr32(E1000_RAH(rar_entries), 0);
3429 wr32(E1000_RAL(rar_entries), 0);
3430 }
3431 wrfl();
3432
68d480c4
AD		 3433 return count;
3434}
3435
3436/**
3437 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3438 * @netdev: network interface device structure
3439 *
3440 * The set_rx_mode entry point is called whenever the unicast or multicast
3441 * address lists or the network interface flags are updated. This routine is
3442 * responsible for configuring the hardware for proper unicast, multicast,
3443 * promiscuous mode, and all-multi behavior.
3444 **/
3445static void igb_set_rx_mode(struct net_device *netdev)
3446{
3447 struct igb_adapter *adapter = netdev_priv(netdev);
3448 struct e1000_hw *hw = &adapter->hw;
3449 unsigned int vfn = adapter->vfs_allocated_count;
3450 u32 rctl, vmolr = 0;
3451 int count;
3452
3453 /* Check for Promiscuous and All Multicast modes */
3454 rctl = rd32(E1000_RCTL);
3455
3456 /* clear the effected bits */
3457 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3458
3459 if (netdev->flags & IFF_PROMISC) {
3460 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3461 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3462 } else {
3463 if (netdev->flags & IFF_ALLMULTI) {
3464 rctl |= E1000_RCTL_MPE;
3465 vmolr |= E1000_VMOLR_MPME;
3466 } else {
3467 /*
3468 * Write addresses to the MTA, if the attempt fails
25985edc 3469 * then we should just turn on promiscuous mode so
68d480c4
AD		 3470 * that we can at least receive multicast traffic
3471 */
3472 count = igb_write_mc_addr_list(netdev);
3473 if (count < 0) {
3474 rctl |= E1000_RCTL_MPE;
3475 vmolr |= E1000_VMOLR_MPME;
3476 } else if (count) {
3477 vmolr |= E1000_VMOLR_ROMPE;
3478 }
3479 }
3480 /*
3481 * Write addresses to available RAR registers, if there is not
3482 * sufficient space to store all the addresses then enable
25985edc 3483 * unicast promiscuous mode
68d480c4
AD		 3484 */
3485 count = igb_write_uc_addr_list(netdev);
3486 if (count < 0) {
3487 rctl |= E1000_RCTL_UPE;
3488 vmolr |= E1000_VMOLR_ROPE;
3489 }
3490 rctl |= E1000_RCTL_VFE;
28fc06f5 3491 }
68d480c4 3492 wr32(E1000_RCTL, rctl);
28fc06f5 3493
68d480c4
AD		 3494 /*
3495 * In order to support SR-IOV and eventually VMDq it is necessary to set
3496 * the VMOLR to enable the appropriate modes. Without this workaround
3497 * we will have issues with VLAN tag stripping not being done for frames
3498 * that are only arriving because we are the default pool
3499 */
3500 if (hw->mac.type < e1000_82576)
28fc06f5 3501 return;
9d5c8243 3502
68d480c4
AD		 3503 vmolr |= rd32(E1000_VMOLR(vfn)) &
3504 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3505 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3506 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3507}
3508
13800469
GR		 3509static void igb_check_wvbr(struct igb_adapter *adapter)
3510{
3511 struct e1000_hw *hw = &adapter->hw;
3512 u32 wvbr = 0;
3513
3514 switch (hw->mac.type) {
3515 case e1000_82576:
3516 case e1000_i350:
3517 if (!(wvbr = rd32(E1000_WVBR)))
3518 return;
3519 break;
3520 default:
3521 break;
3522 }
3523
3524 adapter->wvbr |= wvbr;
3525}
3526
3527#define IGB_STAGGERED_QUEUE_OFFSET 8
3528
3529static void igb_spoof_check(struct igb_adapter *adapter)
3530{
3531 int j;
3532
3533 if (!adapter->wvbr)
3534 return;
3535
3536 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3537 if (adapter->wvbr & (1 << j) ||
3538 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3539 dev_warn(&adapter->pdev->dev,
3540 "Spoof event(s) detected on VF %d\n", j);
3541 adapter->wvbr &=
3542 ~((1 << j) |
3543 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3544 }
3545 }
3546}
3547
9d5c8243
AK		 3548/* Need to wait a few seconds after link up to get diagnostic information from
3549 * the phy */
3550static void igb_update_phy_info(unsigned long data)
3551{
3552 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3553 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3554}
3555
4d6b725e
AD		 3556/**
3557 * igb_has_link - check shared code for link and determine up/down
3558 * @adapter: pointer to driver private info
3559 **/
3145535a 3560bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3561{
3562 struct e1000_hw *hw = &adapter->hw;
3563 bool link_active = false;
3564 s32 ret_val = 0;
3565
3566 /* get_link_status is set on LSC (link status) interrupt or
3567 * rx sequence error interrupt. get_link_status will stay
3568 * false until the e1000_check_for_link establishes link
3569 * for copper adapters ONLY
3570 */
3571 switch (hw->phy.media_type) {
3572 case e1000_media_type_copper:
3573 if (hw->mac.get_link_status) {
3574 ret_val = hw->mac.ops.check_for_link(hw);
3575 link_active = !hw->mac.get_link_status;
3576 } else {
3577 link_active = true;
3578 }
3579 break;
4d6b725e
AD		 3580 case e1000_media_type_internal_serdes:
3581 ret_val = hw->mac.ops.check_for_link(hw);
3582 link_active = hw->mac.serdes_has_link;
3583 break;
3584 default:
3585 case e1000_media_type_unknown:
3586 break;
3587 }
3588
3589 return link_active;
3590}
3591
563988dc
SA		 3592static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3593{
3594 bool ret = false;
3595 u32 ctrl_ext, thstat;
3596
3597 /* check for thermal sensor event on i350, copper only */
3598 if (hw->mac.type == e1000_i350) {
3599 thstat = rd32(E1000_THSTAT);
3600 ctrl_ext = rd32(E1000_CTRL_EXT);
3601
3602 if ((hw->phy.media_type == e1000_media_type_copper) &&
3603 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3604 ret = !!(thstat & event);
3605 }
3606 }
3607
3608 return ret;
3609}
3610
9d5c8243
AK		 3611/**
3612 * igb_watchdog - Timer Call-back
3613 * @data: pointer to adapter cast into an unsigned long
3614 **/
3615static void igb_watchdog(unsigned long data)
3616{
3617 struct igb_adapter *adapter = (struct igb_adapter *)data;
3618 /* Do the rest outside of interrupt context */
3619 schedule_work(&adapter->watchdog_task);
3620}
3621
3622static void igb_watchdog_task(struct work_struct *work)
3623{
3624 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3625 struct igb_adapter,
3626 watchdog_task);
9d5c8243 3627 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3628 struct net_device *netdev = adapter->netdev;
563988dc 3629 u32 link;
7a6ea550 3630 int i;
9d5c8243 3631
4d6b725e 3632 link = igb_has_link(adapter);
9d5c8243
AK		 3633 if (link) {
3634 if (!netif_carrier_ok(netdev)) {
3635 u32 ctrl;
330a6d6a
AD		 3636 hw->mac.ops.get_speed_and_duplex(hw,
3637 &adapter->link_speed,
3638 &adapter->link_duplex);
9d5c8243
AK		 3639
3640 ctrl = rd32(E1000_CTRL);
527d47c1 3641 /* Links status message must follow this format */
876d2d6f
JK		 3642 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3643 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3644 netdev->name,
3645 adapter->link_speed,
3646 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3647 "Full" : "Half",
3648 (ctrl & E1000_CTRL_TFCE) &&
3649 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3650 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3651 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3652
563988dc 3653 /* check for thermal sensor event */
876d2d6f
JK		 3654 if (igb_thermal_sensor_event(hw,
3655 E1000_THSTAT_LINK_THROTTLE)) {
3656 netdev_info(netdev, "The network adapter link "
3657 "speed was downshifted because it "
3658 "overheated\n");
7ef5ed1c 3659 }
563988dc 3660
d07f3e37 3661 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3662 adapter->tx_timeout_factor = 1;
3663 switch (adapter->link_speed) {
3664 case SPEED_10:
9d5c8243
AK		 3665 adapter->tx_timeout_factor = 14;
3666 break;
3667 case SPEED_100:
9d5c8243
AK		 3668 /* maybe add some timeout factor ? */
3669 break;
3670 }
3671
3672 netif_carrier_on(netdev);
9d5c8243 3673
4ae196df 3674 igb_ping_all_vfs(adapter);
17dc566c 3675 igb_check_vf_rate_limit(adapter);
4ae196df 3676
4b1a9877 3677 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3678 if (!test_bit(__IGB_DOWN, &adapter->state))
3679 mod_timer(&adapter->phy_info_timer,
3680 round_jiffies(jiffies + 2 * HZ));
3681 }
3682 } else {
3683 if (netif_carrier_ok(netdev)) {
3684 adapter->link_speed = 0;
3685 adapter->link_duplex = 0;
563988dc
SA		 3686
3687 /* check for thermal sensor event */
876d2d6f
JK		 3688 if (igb_thermal_sensor_event(hw,
3689 E1000_THSTAT_PWR_DOWN)) {
3690 netdev_err(netdev, "The network adapter was "
3691 "stopped because it overheated\n");
7ef5ed1c 3692 }
563988dc 3693
527d47c1
AD		 3694 /* Links status message must follow this format */
3695 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3696 netdev->name);
9d5c8243 3697 netif_carrier_off(netdev);
4b1a9877 3698
4ae196df
AD		 3699 igb_ping_all_vfs(adapter);
3700
4b1a9877 3701 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3702 if (!test_bit(__IGB_DOWN, &adapter->state))
3703 mod_timer(&adapter->phy_info_timer,
3704 round_jiffies(jiffies + 2 * HZ));
3705 }
3706 }
3707
12dcd86b
ED		 3708 spin_lock(&adapter->stats64_lock);
3709 igb_update_stats(adapter, &adapter->stats64);
3710 spin_unlock(&adapter->stats64_lock);
9d5c8243 3711
dbabb065 3712 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3713 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3714 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3715 /* We've lost link, so the controller stops DMA,
3716 * but we've got queued Tx work that's never going
3717 * to get done, so reset controller to flush Tx.
3718 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3719 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3720 adapter->tx_timeout_count++;
3721 schedule_work(&adapter->reset_task);
3722 /* return immediately since reset is imminent */
3723 return;
3724 }
9d5c8243 3725 }
9d5c8243 3726
dbabb065 3727 /* Force detection of hung controller every watchdog period */
6d095fa8 3728 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3729 }
f7ba205e 3730
9d5c8243 3731 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3732 if (adapter->msix_entries) {
047e0030 3733 u32 eics = 0;
0d1ae7f4
AD		 3734 for (i = 0; i < adapter->num_q_vectors; i++)
3735 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3736 wr32(E1000_EICS, eics);
3737 } else {
3738 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3739 }
9d5c8243 3740
13800469
GR		 3741 igb_spoof_check(adapter);
3742
9d5c8243
AK		 3743 /* Reset the timer */
3744 if (!test_bit(__IGB_DOWN, &adapter->state))
3745 mod_timer(&adapter->watchdog_timer,
3746 round_jiffies(jiffies + 2 * HZ));
3747}
3748
3749enum latency_range {
3750 lowest_latency = 0,
3751 low_latency = 1,
3752 bulk_latency = 2,
3753 latency_invalid = 255
3754};
3755
6eb5a7f1
AD		 3756/**
3757 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3758 *
3759 * Stores a new ITR value based on strictly on packet size. This
3760 * algorithm is less sophisticated than that used in igb_update_itr,
3761 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3762 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3763 * were determined based on theoretical maximum wire speed and testing
3764 * data, in order to minimize response time while increasing bulk
3765 * throughput.
3766 * This functionality is controlled by the InterruptThrottleRate module
3767 * parameter (see igb_param.c)
3768 * NOTE: This function is called only when operating in a multiqueue
3769 * receive environment.
047e0030 3770 * @q_vector: pointer to q_vector
6eb5a7f1 3771 **/
047e0030 3772static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3773{
047e0030 3774 int new_val = q_vector->itr_val;
6eb5a7f1 3775 int avg_wire_size = 0;
047e0030 3776 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3777 unsigned int packets;
9d5c8243 3778
6eb5a7f1
AD		 3779 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3780 * ints/sec - ITR timer value of 120 ticks.
3781 */
3782 if (adapter->link_speed != SPEED_1000) {
0ba82994 3783 new_val = IGB_4K_ITR;
6eb5a7f1 3784 goto set_itr_val;
9d5c8243 3785 }
047e0030 3786
0ba82994
AD		 3787 packets = q_vector->rx.total_packets;
3788 if (packets)
3789 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3790
0ba82994
AD		 3791 packets = q_vector->tx.total_packets;
3792 if (packets)
3793 avg_wire_size = max_t(u32, avg_wire_size,
3794 q_vector->tx.total_bytes / packets);
047e0030
AD		 3795
3796 /* if avg_wire_size isn't set no work was done */
3797 if (!avg_wire_size)
3798 goto clear_counts;
9d5c8243 3799
6eb5a7f1
AD		 3800 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3801 avg_wire_size += 24;
3802
3803 /* Don't starve jumbo frames */
3804 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3805
6eb5a7f1
AD		 3806 /* Give a little boost to mid-size frames */
3807 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3808 new_val = avg_wire_size / 3;
3809 else
3810 new_val = avg_wire_size / 2;
9d5c8243 3811
0ba82994
AD		 3812 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3813 if (new_val < IGB_20K_ITR &&
3814 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3815 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3816 new_val = IGB_20K_ITR;
abe1c363 3817
6eb5a7f1 3818set_itr_val:
047e0030
AD		 3819 if (new_val != q_vector->itr_val) {
3820 q_vector->itr_val = new_val;
3821 q_vector->set_itr = 1;
9d5c8243 3822 }
6eb5a7f1 3823clear_counts:
0ba82994
AD		 3824 q_vector->rx.total_bytes = 0;
3825 q_vector->rx.total_packets = 0;
3826 q_vector->tx.total_bytes = 0;
3827 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3828}
3829
3830/**
3831 * igb_update_itr - update the dynamic ITR value based on statistics
3832 * Stores a new ITR value based on packets and byte
3833 * counts during the last interrupt. The advantage of per interrupt
3834 * computation is faster updates and more accurate ITR for the current
3835 * traffic pattern. Constants in this function were computed
3836 * based on theoretical maximum wire speed and thresholds were set based
3837 * on testing data as well as attempting to minimize response time
3838 * while increasing bulk throughput.
3839 * this functionality is controlled by the InterruptThrottleRate module
3840 * parameter (see igb_param.c)
3841 * NOTE: These calculations are only valid when operating in a single-
3842 * queue environment.
0ba82994
AD		 3843 * @q_vector: pointer to q_vector
3844 * @ring_container: ring info to update the itr for
9d5c8243 3845 **/
0ba82994
AD		 3846static void igb_update_itr(struct igb_q_vector *q_vector,
3847 struct igb_ring_container *ring_container)
9d5c8243 3848{
0ba82994
AD		 3849 unsigned int packets = ring_container->total_packets;
3850 unsigned int bytes = ring_container->total_bytes;
3851 u8 itrval = ring_container->itr;
9d5c8243 3852
0ba82994 3853 /* no packets, exit with status unchanged */
9d5c8243 3854 if (packets == 0)
0ba82994 3855 return;
9d5c8243 3856
0ba82994 3857 switch (itrval) {
9d5c8243
AK		 3858 case lowest_latency:
3859 /* handle TSO and jumbo frames */
3860 if (bytes/packets > 8000)
0ba82994 3861 itrval = bulk_latency;
9d5c8243 3862 else if ((packets < 5) && (bytes > 512))
0ba82994 3863 itrval = low_latency;
9d5c8243
AK		 3864 break;
3865 case low_latency: /* 50 usec aka 20000 ints/s */
3866 if (bytes > 10000) {
3867 /* this if handles the TSO accounting */
3868 if (bytes/packets > 8000) {
0ba82994 3869 itrval = bulk_latency;
9d5c8243 3870 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3871 itrval = bulk_latency;
9d5c8243 3872 } else if ((packets > 35)) {
0ba82994 3873 itrval = lowest_latency;
9d5c8243
AK		 3874 }
3875 } else if (bytes/packets > 2000) {
0ba82994 3876 itrval = bulk_latency;
9d5c8243 3877 } else if (packets <= 2 && bytes < 512) {
0ba82994 3878 itrval = lowest_latency;
9d5c8243
AK		 3879 }
3880 break;
3881 case bulk_latency: /* 250 usec aka 4000 ints/s */
3882 if (bytes > 25000) {
3883 if (packets > 35)
0ba82994 3884 itrval = low_latency;
1e5c3d21 3885 } else if (bytes < 1500) {
0ba82994 3886 itrval = low_latency;
9d5c8243
AK		 3887 }
3888 break;
3889 }
3890
0ba82994
AD		 3891 /* clear work counters since we have the values we need */
3892 ring_container->total_bytes = 0;
3893 ring_container->total_packets = 0;
3894
3895 /* write updated itr to ring container */
3896 ring_container->itr = itrval;
9d5c8243
AK		 3897}
3898
0ba82994 3899static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3900{
0ba82994 3901 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3902 u32 new_itr = q_vector->itr_val;
0ba82994 3903 u8 current_itr = 0;
9d5c8243
AK		 3904
3905 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3906 if (adapter->link_speed != SPEED_1000) {
3907 current_itr = 0;
0ba82994 3908 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3909 goto set_itr_now;
3910 }
3911
0ba82994
AD		 3912 igb_update_itr(q_vector, &q_vector->tx);
3913 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3914
0ba82994 3915 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3916
6eb5a7f1 3917 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3918 if (current_itr == lowest_latency &&
3919 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3920 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 3921 current_itr = low_latency;
3922
9d5c8243
AK		 3923 switch (current_itr) {
3924 /* counts and packets in update_itr are dependent on these numbers */
3925 case lowest_latency:
0ba82994 3926 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 3927 break;
3928 case low_latency:
0ba82994 3929 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 3930 break;
3931 case bulk_latency:
0ba82994 3932 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 3933 break;
3934 default:
3935 break;
3936 }
3937
3938set_itr_now:
047e0030 3939 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3940 /* this attempts to bias the interrupt rate towards Bulk
3941 * by adding intermediate steps when interrupt rate is
3942 * increasing */
047e0030
AD		 3943 new_itr = new_itr > q_vector->itr_val ?
3944 max((new_itr * q_vector->itr_val) /
3945 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 3946 new_itr) :
9d5c8243
AK		 3947 new_itr;
3948 /* Don't write the value here; it resets the adapter's
3949 * internal timer, and causes us to delay far longer than
3950 * we should between interrupts. Instead, we write the ITR
3951 * value at the beginning of the next interrupt so the timing
3952 * ends up being correct.
3953 */
047e0030
AD		 3954 q_vector->itr_val = new_itr;
3955 q_vector->set_itr = 1;
9d5c8243 3956 }
9d5c8243
AK		 3957}
3958
7d13a7d0
AD		 3959void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3960 u32 type_tucmd, u32 mss_l4len_idx)
3961{
3962 struct e1000_adv_tx_context_desc *context_desc;
3963 u16 i = tx_ring->next_to_use;
3964
3965 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3966
3967 i++;
3968 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3969
3970 /* set bits to identify this as an advanced context descriptor */
3971 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3972
3973 /* For 82575, context index must be unique per ring. */
866cff06 3974 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 3975 mss_l4len_idx |= tx_ring->reg_idx << 4;
3976
3977 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3978 context_desc->seqnum_seed = 0;
3979 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
3980 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3981}
3982
7af40ad9
AD		 3983static int igb_tso(struct igb_ring *tx_ring,
3984 struct igb_tx_buffer *first,
3985 u8 *hdr_len)
9d5c8243 3986{
7af40ad9 3987 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 3988 u32 vlan_macip_lens, type_tucmd;
3989 u32 mss_l4len_idx, l4len;
3990
3991 if (!skb_is_gso(skb))
3992 return 0;
9d5c8243
AK		 3993
3994 if (skb_header_cloned(skb)) {
7af40ad9 3995 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 3996 if (err)
3997 return err;
3998 }
3999
7d13a7d0
AD		 4000 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4001 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4002
7af40ad9 4003 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4004 struct iphdr *iph = ip_hdr(skb);
4005 iph->tot_len = 0;
4006 iph->check = 0;
4007 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4008 iph->daddr, 0,
4009 IPPROTO_TCP,
4010 0);
7d13a7d0 4011 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4012 first->tx_flags |= IGB_TX_FLAGS_TSO |
4013 IGB_TX_FLAGS_CSUM |
4014 IGB_TX_FLAGS_IPV4;
8e1e8a47 4015 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4016 ipv6_hdr(skb)->payload_len = 0;
4017 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4018 &ipv6_hdr(skb)->daddr,
4019 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4020 first->tx_flags |= IGB_TX_FLAGS_TSO |
4021 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4022 }
4023
7af40ad9 4024 /* compute header lengths */
7d13a7d0
AD		 4025 l4len = tcp_hdrlen(skb);
4026 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4027
7af40ad9
AD		 4028 /* update gso size and bytecount with header size */
4029 first->gso_segs = skb_shinfo(skb)->gso_segs;
4030 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4031
9d5c8243 4032 /* MSS L4LEN IDX */
7d13a7d0
AD		 4033 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4034 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4035
7d13a7d0
AD		 4036 /* VLAN MACLEN IPLEN */
4037 vlan_macip_lens = skb_network_header_len(skb);
4038 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4039 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4040
7d13a7d0 4041 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4042
7d13a7d0 4043 return 1;
9d5c8243
AK		 4044}
4045
7af40ad9 4046static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4047{
7af40ad9 4048 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4049 u32 vlan_macip_lens = 0;
4050 u32 mss_l4len_idx = 0;
4051 u32 type_tucmd = 0;
9d5c8243 4052
7d13a7d0 4053 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4054 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4055 return;
7d13a7d0
AD		 4056 } else {
4057 u8 l4_hdr = 0;
7af40ad9 4058 switch (first->protocol) {
7d13a7d0
AD		 4059 case __constant_htons(ETH_P_IP):
4060 vlan_macip_lens |= skb_network_header_len(skb);
4061 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4062 l4_hdr = ip_hdr(skb)->protocol;
4063 break;
4064 case __constant_htons(ETH_P_IPV6):
4065 vlan_macip_lens |= skb_network_header_len(skb);
4066 l4_hdr = ipv6_hdr(skb)->nexthdr;
4067 break;
4068 default:
4069 if (unlikely(net_ratelimit())) {
4070 dev_warn(tx_ring->dev,
4071 "partial checksum but proto=%x!\n",
7af40ad9 4072 first->protocol);
fa4a7ef3 4073 }
7d13a7d0
AD		 4074 break;
4075 }
fa4a7ef3 4076
7d13a7d0
AD		 4077 switch (l4_hdr) {
4078 case IPPROTO_TCP:
4079 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4080 mss_l4len_idx = tcp_hdrlen(skb) <<
4081 E1000_ADVTXD_L4LEN_SHIFT;
4082 break;
4083 case IPPROTO_SCTP:
4084 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4085 mss_l4len_idx = sizeof(struct sctphdr) <<
4086 E1000_ADVTXD_L4LEN_SHIFT;
4087 break;
4088 case IPPROTO_UDP:
4089 mss_l4len_idx = sizeof(struct udphdr) <<
4090 E1000_ADVTXD_L4LEN_SHIFT;
4091 break;
4092 default:
4093 if (unlikely(net_ratelimit())) {
4094 dev_warn(tx_ring->dev,
4095 "partial checksum but l4 proto=%x!\n",
4096 l4_hdr);
44b0cda3 4097 }
7d13a7d0 4098 break;
9d5c8243 4099 }
7af40ad9
AD		 4100
4101 /* update TX checksum flag */
4102 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4103 }
9d5c8243 4104
7d13a7d0 4105 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4106 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4107
7d13a7d0 4108 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4109}
4110
e032afc8
AD		 4111static __le32 igb_tx_cmd_type(u32 tx_flags)
4112{
4113 /* set type for advanced descriptor with frame checksum insertion */
4114 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA |
4115 E1000_ADVTXD_DCMD_IFCS |
4116 E1000_ADVTXD_DCMD_DEXT);
4117
4118 /* set HW vlan bit if vlan is present */
4119 if (tx_flags & IGB_TX_FLAGS_VLAN)
4120 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE);
4121
4122 /* set timestamp bit if present */
4123 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4124 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP);
4125
4126 /* set segmentation bits for TSO */
4127 if (tx_flags & IGB_TX_FLAGS_TSO)
4128 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE);
4129
4130 return cmd_type;
4131}
4132
7af40ad9
AD		 4133static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4134 union e1000_adv_tx_desc *tx_desc,
4135 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4136{
4137 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4138
4139 /* 82575 requires a unique index per ring if any offload is enabled */
4140 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) &&
866cff06 4141 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4142 olinfo_status |= tx_ring->reg_idx << 4;
4143
4144 /* insert L4 checksum */
4145 if (tx_flags & IGB_TX_FLAGS_CSUM) {
4146 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4147
4148 /* insert IPv4 checksum */
4149 if (tx_flags & IGB_TX_FLAGS_IPV4)
4150 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4151 }
4152
7af40ad9 4153 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4154}
4155
ebe42d16
AD		 4156/*
4157 * The largest size we can write to the descriptor is 65535. In order to
4158 * maintain a power of two alignment we have to limit ourselves to 32K.
4159 */
4160#define IGB_MAX_TXD_PWR 15
7af40ad9 4161#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4162
7af40ad9
AD		 4163static void igb_tx_map(struct igb_ring *tx_ring,
4164 struct igb_tx_buffer *first,
ebe42d16 4165 const u8 hdr_len)
9d5c8243 4166{
7af40ad9 4167 struct sk_buff *skb = first->skb;
ebe42d16
AD		 4168 struct igb_tx_buffer *tx_buffer_info;
4169 union e1000_adv_tx_desc *tx_desc;
4170 dma_addr_t dma;
4171 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
4172 unsigned int data_len = skb->data_len;
4173 unsigned int size = skb_headlen(skb);
4174 unsigned int paylen = skb->len - hdr_len;
4175 __le32 cmd_type;
7af40ad9 4176 u32 tx_flags = first->tx_flags;
ebe42d16 4177 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4178
4179 tx_desc = IGB_TX_DESC(tx_ring, i);
4180
7af40ad9 4181 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen);
ebe42d16
AD		 4182 cmd_type = igb_tx_cmd_type(tx_flags);
4183
4184 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4185 if (dma_mapping_error(tx_ring->dev, dma))
6366ad33 4186 goto dma_error;
9d5c8243 4187
ebe42d16
AD		 4188 /* record length, and DMA address */
4189 first->length = size;
4190 first->dma = dma;
ebe42d16
AD		 4191 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4192
4193 for (;;) {
4194 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4195 tx_desc->read.cmd_type_len =
4196 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD);
4197
4198 i++;
4199 tx_desc++;
4200 if (i == tx_ring->count) {
4201 tx_desc = IGB_TX_DESC(tx_ring, 0);
4202 i = 0;
4203 }
4204
4205 dma += IGB_MAX_DATA_PER_TXD;
4206 size -= IGB_MAX_DATA_PER_TXD;
4207
4208 tx_desc->read.olinfo_status = 0;
4209 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4210 }
4211
4212 if (likely(!data_len))
4213 break;
2bbfebe2 4214
ebe42d16 4215 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9d5c8243 4216
65689fef 4217 i++;
ebe42d16
AD		 4218 tx_desc++;
4219 if (i == tx_ring->count) {
4220 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4221 i = 0;
ebe42d16 4222 }
65689fef 4223
9e903e08 4224 size = skb_frag_size(frag);
ebe42d16
AD		 4225 data_len -= size;
4226
4227 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4228 size, DMA_TO_DEVICE);
4229 if (dma_mapping_error(tx_ring->dev, dma))
6366ad33
AD		 4230 goto dma_error;
4231
ebe42d16
AD		 4232 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4233 tx_buffer_info->length = size;
4234 tx_buffer_info->dma = dma;
4235
4236 tx_desc->read.olinfo_status = 0;
4237 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4238
4239 frag++;
9d5c8243
AK		 4240 }
4241
bdbc0631
ED		 4242 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4243
ebe42d16
AD		 4244 /* write last descriptor with RS and EOP bits */
4245 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD);
4246 tx_desc->read.cmd_type_len = cmd_type;
8542db05
AD		 4247
4248 /* set the timestamp */
4249 first->time_stamp = jiffies;
4250
ebe42d16
AD		 4251 /*
4252 * Force memory writes to complete before letting h/w know there
4253 * are new descriptors to fetch. (Only applicable for weak-ordered
4254 * memory model archs, such as IA-64).
4255 *
4256 * We also need this memory barrier to make certain all of the
4257 * status bits have been updated before next_to_watch is written.
4258 */
4259 wmb();
4260
8542db05 4261 /* set next_to_watch value indicating a packet is present */
ebe42d16 4262 first->next_to_watch = tx_desc;
9d5c8243 4263
ebe42d16
AD		 4264 i++;
4265 if (i == tx_ring->count)
4266 i = 0;
6366ad33 4267
ebe42d16 4268 tx_ring->next_to_use = i;
6366ad33 4269
ebe42d16 4270 writel(i, tx_ring->tail);
6366ad33 4271
ebe42d16
AD		 4272 /* we need this if more than one processor can write to our tail
4273 * at a time, it syncronizes IO on IA64/Altix systems */
4274 mmiowb();
4275
4276 return;
4277
4278dma_error:
4279 dev_err(tx_ring->dev, "TX DMA map failed\n");
4280
4281 /* clear dma mappings for failed tx_buffer_info map */
4282 for (;;) {
4283 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4284 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4285 if (tx_buffer_info == first)
4286 break;
a77ff709
NN		 4287 if (i == 0)
4288 i = tx_ring->count;
6366ad33 4289 i--;
6366ad33
AD		 4290 }
4291
9d5c8243 4292 tx_ring->next_to_use = i;
9d5c8243
AK		 4293}
4294
6ad4edfc 4295static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4296{
e694e964
AD		 4297 struct net_device *netdev = tx_ring->netdev;
4298
661086df 4299 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4300
9d5c8243
AK		 4301 /* Herbert's original patch had:
4302 * smp_mb__after_netif_stop_queue();
4303 * but since that doesn't exist yet, just open code it. */
4304 smp_mb();
4305
4306 /* We need to check again in a case another CPU has just
4307 * made room available. */
c493ea45 4308 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4309 return -EBUSY;
4310
4311 /* A reprieve! */
661086df 4312 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4313
4314 u64_stats_update_begin(&tx_ring->tx_syncp2);
4315 tx_ring->tx_stats.restart_queue2++;
4316 u64_stats_update_end(&tx_ring->tx_syncp2);
4317
9d5c8243
AK		 4318 return 0;
4319}
4320
6ad4edfc 4321static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4322{
c493ea45 4323 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4324 return 0;
e694e964 4325 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4326}
4327
cd392f5c
AD		 4328netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4329 struct igb_ring *tx_ring)
9d5c8243 4330{
8542db05 4331 struct igb_tx_buffer *first;
ebe42d16 4332 int tso;
91d4ee33 4333 u32 tx_flags = 0;
31f6adbb 4334 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4335 u8 hdr_len = 0;
9d5c8243 4336
9d5c8243
AK		 4337 /* need: 1 descriptor per page,
4338 * + 2 desc gap to keep tail from touching head,
4339 * + 1 desc for skb->data,
4340 * + 1 desc for context descriptor,
4341 * otherwise try next time */
e694e964 4342 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4343 /* this is a hard error */
9d5c8243
AK		 4344 return NETDEV_TX_BUSY;
4345 }
33af6bcc 4346
7af40ad9
AD		 4347 /* record the location of the first descriptor for this packet */
4348 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4349 first->skb = skb;
4350 first->bytecount = skb->len;
4351 first->gso_segs = 1;
4352
2244d07b
OH		 4353 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4354 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4355 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 4356 }
9d5c8243 4357
eab6d18d 4358 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4359 tx_flags |= IGB_TX_FLAGS_VLAN;
4360 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4361 }
4362
7af40ad9
AD		 4363 /* record initial flags and protocol */
4364 first->tx_flags = tx_flags;
4365 first->protocol = protocol;
cdfd01fc 4366
7af40ad9
AD		 4367 tso = igb_tso(tx_ring, first, &hdr_len);
4368 if (tso < 0)
7d13a7d0 4369 goto out_drop;
7af40ad9
AD		 4370 else if (!tso)
4371 igb_tx_csum(tx_ring, first);
9d5c8243 4372
7af40ad9 4373 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4374
4375 /* Make sure there is space in the ring for the next send. */
e694e964 4376 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4377
9d5c8243 4378 return NETDEV_TX_OK;
7d13a7d0
AD		 4379
4380out_drop:
7af40ad9
AD		 4381 igb_unmap_and_free_tx_resource(tx_ring, first);
4382
7d13a7d0 4383 return NETDEV_TX_OK;
9d5c8243
AK		 4384}
4385
1cc3bd87
AD		 4386static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4387 struct sk_buff *skb)
4388{
4389 unsigned int r_idx = skb->queue_mapping;
4390
4391 if (r_idx >= adapter->num_tx_queues)
4392 r_idx = r_idx % adapter->num_tx_queues;
4393
4394 return adapter->tx_ring[r_idx];
4395}
4396
cd392f5c
AD		 4397static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4398 struct net_device *netdev)
9d5c8243
AK		 4399{
4400 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4401
4402 if (test_bit(__IGB_DOWN, &adapter->state)) {
4403 dev_kfree_skb_any(skb);
4404 return NETDEV_TX_OK;
4405 }
4406
4407 if (skb->len <= 0) {
4408 dev_kfree_skb_any(skb);
4409 return NETDEV_TX_OK;
4410 }
4411
1cc3bd87
AD		 4412 /*
4413 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4414 * in order to meet this minimum size requirement.
4415 */
4416 if (skb->len < 17) {
4417 if (skb_padto(skb, 17))
4418 return NETDEV_TX_OK;
4419 skb->len = 17;
4420 }
9d5c8243 4421
1cc3bd87 4422 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4423}
4424
4425/**
4426 * igb_tx_timeout - Respond to a Tx Hang
4427 * @netdev: network interface device structure
4428 **/
4429static void igb_tx_timeout(struct net_device *netdev)
4430{
4431 struct igb_adapter *adapter = netdev_priv(netdev);
4432 struct e1000_hw *hw = &adapter->hw;
4433
4434 /* Do the reset outside of interrupt context */
4435 adapter->tx_timeout_count++;
f7ba205e 4436
06218a8d 4437 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4438 hw->dev_spec._82575.global_device_reset = true;
4439
9d5c8243 4440 schedule_work(&adapter->reset_task);
265de409
AD		 4441 wr32(E1000_EICS,
4442 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4443}
4444
4445static void igb_reset_task(struct work_struct *work)
4446{
4447 struct igb_adapter *adapter;
4448 adapter = container_of(work, struct igb_adapter, reset_task);
4449
c97ec42a
TI		 4450 igb_dump(adapter);
4451 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4452 igb_reinit_locked(adapter);
4453}
4454
4455/**
12dcd86b 4456 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4457 * @netdev: network interface device structure
12dcd86b 4458 * @stats: rtnl_link_stats64 pointer
9d5c8243 4459 *
9d5c8243 4460 **/
12dcd86b
ED		 4461static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4462 struct rtnl_link_stats64 *stats)
9d5c8243 4463{
12dcd86b
ED		 4464 struct igb_adapter *adapter = netdev_priv(netdev);
4465
4466 spin_lock(&adapter->stats64_lock);
4467 igb_update_stats(adapter, &adapter->stats64);
4468 memcpy(stats, &adapter->stats64, sizeof(*stats));
4469 spin_unlock(&adapter->stats64_lock);
4470
4471 return stats;
9d5c8243
AK		 4472}
4473
4474/**
4475 * igb_change_mtu - Change the Maximum Transfer Unit
4476 * @netdev: network interface device structure
4477 * @new_mtu: new value for maximum frame size
4478 *
4479 * Returns 0 on success, negative on failure
4480 **/
4481static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4482{
4483 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4484 struct pci_dev *pdev = adapter->pdev;
153285f9 4485 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4486
c809d227 4487 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4488 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4489 return -EINVAL;
4490 }
4491
153285f9 4492#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4493 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4494 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4495 return -EINVAL;
4496 }
4497
4498 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4499 msleep(1);
73cd78f1 4500
9d5c8243
AK		 4501 /* igb_down has a dependency on max_frame_size */
4502 adapter->max_frame_size = max_frame;
559e9c49 4503
4c844851
AD		 4504 if (netif_running(netdev))
4505 igb_down(adapter);
9d5c8243 4506
090b1795 4507 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4508 netdev->mtu, new_mtu);
4509 netdev->mtu = new_mtu;
4510
4511 if (netif_running(netdev))
4512 igb_up(adapter);
4513 else
4514 igb_reset(adapter);
4515
4516 clear_bit(__IGB_RESETTING, &adapter->state);
4517
4518 return 0;
4519}
4520
4521/**
4522 * igb_update_stats - Update the board statistics counters
4523 * @adapter: board private structure
4524 **/
4525
12dcd86b
ED		 4526void igb_update_stats(struct igb_adapter *adapter,
4527 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4528{
4529 struct e1000_hw *hw = &adapter->hw;
4530 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4531 u32 reg, mpc;
9d5c8243 4532 u16 phy_tmp;
3f9c0164
AD		 4533 int i;
4534 u64 bytes, packets;
12dcd86b
ED		 4535 unsigned int start;
4536 u64 _bytes, _packets;
9d5c8243
AK		 4537
4538#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4539
4540 /*
4541 * Prevent stats update while adapter is being reset, or if the pci
4542 * connection is down.
4543 */
4544 if (adapter->link_speed == 0)
4545 return;
4546 if (pci_channel_offline(pdev))
4547 return;
4548
3f9c0164
AD		 4549 bytes = 0;
4550 packets = 0;
4551 for (i = 0; i < adapter->num_rx_queues; i++) {
4552 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
3025a446 4553 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4554
3025a446 4555 ring->rx_stats.drops += rqdpc_tmp;
128e45eb 4556 net_stats->rx_fifo_errors += rqdpc_tmp;
12dcd86b
ED		 4557
4558 do {
4559 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4560 _bytes = ring->rx_stats.bytes;
4561 _packets = ring->rx_stats.packets;
4562 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4563 bytes += _bytes;
4564 packets += _packets;
3f9c0164
AD		 4565 }
4566
128e45eb
AD		 4567 net_stats->rx_bytes = bytes;
4568 net_stats->rx_packets = packets;
3f9c0164
AD		 4569
4570 bytes = 0;
4571 packets = 0;
4572 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4573 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4574 do {
4575 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4576 _bytes = ring->tx_stats.bytes;
4577 _packets = ring->tx_stats.packets;
4578 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4579 bytes += _bytes;
4580 packets += _packets;
3f9c0164 4581 }
128e45eb
AD		 4582 net_stats->tx_bytes = bytes;
4583 net_stats->tx_packets = packets;
3f9c0164
AD		 4584
4585 /* read stats registers */
9d5c8243
AK		 4586 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4587 adapter->stats.gprc += rd32(E1000_GPRC);
4588 adapter->stats.gorc += rd32(E1000_GORCL);
4589 rd32(E1000_GORCH); /* clear GORCL */
4590 adapter->stats.bprc += rd32(E1000_BPRC);
4591 adapter->stats.mprc += rd32(E1000_MPRC);
4592 adapter->stats.roc += rd32(E1000_ROC);
4593
4594 adapter->stats.prc64 += rd32(E1000_PRC64);
4595 adapter->stats.prc127 += rd32(E1000_PRC127);
4596 adapter->stats.prc255 += rd32(E1000_PRC255);
4597 adapter->stats.prc511 += rd32(E1000_PRC511);
4598 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4599 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4600 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4601 adapter->stats.sec += rd32(E1000_SEC);
4602
fa3d9a6d
MW		 4603 mpc = rd32(E1000_MPC);
4604 adapter->stats.mpc += mpc;
4605 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4606 adapter->stats.scc += rd32(E1000_SCC);
4607 adapter->stats.ecol += rd32(E1000_ECOL);
4608 adapter->stats.mcc += rd32(E1000_MCC);
4609 adapter->stats.latecol += rd32(E1000_LATECOL);
4610 adapter->stats.dc += rd32(E1000_DC);
4611 adapter->stats.rlec += rd32(E1000_RLEC);
4612 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4613 adapter->stats.xontxc += rd32(E1000_XONTXC);
4614 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4615 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4616 adapter->stats.fcruc += rd32(E1000_FCRUC);
4617 adapter->stats.gptc += rd32(E1000_GPTC);
4618 adapter->stats.gotc += rd32(E1000_GOTCL);
4619 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4620 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4621 adapter->stats.ruc += rd32(E1000_RUC);
4622 adapter->stats.rfc += rd32(E1000_RFC);
4623 adapter->stats.rjc += rd32(E1000_RJC);
4624 adapter->stats.tor += rd32(E1000_TORH);
4625 adapter->stats.tot += rd32(E1000_TOTH);
4626 adapter->stats.tpr += rd32(E1000_TPR);
4627
4628 adapter->stats.ptc64 += rd32(E1000_PTC64);
4629 adapter->stats.ptc127 += rd32(E1000_PTC127);
4630 adapter->stats.ptc255 += rd32(E1000_PTC255);
4631 adapter->stats.ptc511 += rd32(E1000_PTC511);
4632 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4633 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4634
4635 adapter->stats.mptc += rd32(E1000_MPTC);
4636 adapter->stats.bptc += rd32(E1000_BPTC);
4637
2d0b0f69
NN		 4638 adapter->stats.tpt += rd32(E1000_TPT);
4639 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4640
4641 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4642 /* read internal phy specific stats */
4643 reg = rd32(E1000_CTRL_EXT);
4644 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4645 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4646 adapter->stats.tncrs += rd32(E1000_TNCRS);
4647 }
4648
9d5c8243
AK		 4649 adapter->stats.tsctc += rd32(E1000_TSCTC);
4650 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4651
4652 adapter->stats.iac += rd32(E1000_IAC);
4653 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4654 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4655 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4656 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4657 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4658 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4659 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4660 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4661
4662 /* Fill out the OS statistics structure */
128e45eb
AD		 4663 net_stats->multicast = adapter->stats.mprc;
4664 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4665
4666 /* Rx Errors */
4667
4668 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4669 * our own version based on RUC and ROC */
128e45eb 4670 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4671 adapter->stats.crcerrs + adapter->stats.algnerrc +
4672 adapter->stats.ruc + adapter->stats.roc +
4673 adapter->stats.cexterr;
128e45eb
AD		 4674 net_stats->rx_length_errors = adapter->stats.ruc +
4675 adapter->stats.roc;
4676 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4677 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4678 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4679
4680 /* Tx Errors */
128e45eb
AD		 4681 net_stats->tx_errors = adapter->stats.ecol +
4682 adapter->stats.latecol;
4683 net_stats->tx_aborted_errors = adapter->stats.ecol;
4684 net_stats->tx_window_errors = adapter->stats.latecol;
4685 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4686
4687 /* Tx Dropped needs to be maintained elsewhere */
4688
4689 /* Phy Stats */
4690 if (hw->phy.media_type == e1000_media_type_copper) {
4691 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4692 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4693 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4694 adapter->phy_stats.idle_errors += phy_tmp;
4695 }
4696 }
4697
4698 /* Management Stats */
4699 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4700 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4701 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4702
4703 /* OS2BMC Stats */
4704 reg = rd32(E1000_MANC);
4705 if (reg & E1000_MANC_EN_BMC2OS) {
4706 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4707 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4708 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4709 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4710 }
9d5c8243
AK		 4711}
4712
9d5c8243
AK		 4713static irqreturn_t igb_msix_other(int irq, void *data)
4714{
047e0030 4715 struct igb_adapter *adapter = data;
9d5c8243 4716 struct e1000_hw *hw = &adapter->hw;
844290e5 4717 u32 icr = rd32(E1000_ICR);
844290e5 4718 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4719
7f081d40
AD		 4720 if (icr & E1000_ICR_DRSTA)
4721 schedule_work(&adapter->reset_task);
4722
047e0030 4723 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4724 /* HW is reporting DMA is out of sync */
4725 adapter->stats.doosync++;
13800469
GR		 4726 /* The DMA Out of Sync is also indication of a spoof event
4727 * in IOV mode. Check the Wrong VM Behavior register to
4728 * see if it is really a spoof event. */
4729 igb_check_wvbr(adapter);
dda0e083 4730 }
eebbbdba 4731
4ae196df
AD		 4732 /* Check for a mailbox event */
4733 if (icr & E1000_ICR_VMMB)
4734 igb_msg_task(adapter);
4735
4736 if (icr & E1000_ICR_LSC) {
4737 hw->mac.get_link_status = 1;
4738 /* guard against interrupt when we're going down */
4739 if (!test_bit(__IGB_DOWN, &adapter->state))
4740 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4741 }
4742
844290e5 4743 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4744
4745 return IRQ_HANDLED;
4746}
4747
047e0030 4748static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4749{
26b39276 4750 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4751 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4752
047e0030
AD		 4753 if (!q_vector->set_itr)
4754 return;
73cd78f1 4755
047e0030
AD		 4756 if (!itr_val)
4757 itr_val = 0x4;
661086df 4758
26b39276
AD		 4759 if (adapter->hw.mac.type == e1000_82575)
4760 itr_val |= itr_val << 16;
661086df 4761 else
0ba82994 4762 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4763
047e0030
AD		 4764 writel(itr_val, q_vector->itr_register);
4765 q_vector->set_itr = 0;
6eb5a7f1
AD		 4766}
4767
047e0030 4768static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4769{
047e0030 4770 struct igb_q_vector *q_vector = data;
9d5c8243 4771
047e0030
AD		 4772 /* Write the ITR value calculated from the previous interrupt. */
4773 igb_write_itr(q_vector);
9d5c8243 4774
047e0030 4775 napi_schedule(&q_vector->napi);
844290e5 4776
047e0030 4777 return IRQ_HANDLED;
fe4506b6
JC		 4778}
4779
421e02f0 4780#ifdef CONFIG_IGB_DCA
047e0030 4781static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4782{
047e0030 4783 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4784 struct e1000_hw *hw = &adapter->hw;
4785 int cpu = get_cpu();
fe4506b6 4786
047e0030
AD		 4787 if (q_vector->cpu == cpu)
4788 goto out_no_update;
4789
0ba82994
AD		 4790 if (q_vector->tx.ring) {
4791 int q = q_vector->tx.ring->reg_idx;
047e0030
AD		 4792 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4793 if (hw->mac.type == e1000_82575) {
4794 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4795 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4796 } else {
047e0030
AD		 4797 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4798 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4799 E1000_DCA_TXCTRL_CPUID_SHIFT;
4800 }
4801 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4802 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4803 }
0ba82994
AD		 4804 if (q_vector->rx.ring) {
4805 int q = q_vector->rx.ring->reg_idx;
047e0030
AD		 4806 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4807 if (hw->mac.type == e1000_82575) {
2d064c06 4808 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4809 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4810 } else {
4811 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4812 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4813 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4814 }
fe4506b6
JC		 4815 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4816 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4817 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4818 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4819 }
047e0030
AD		 4820 q_vector->cpu = cpu;
4821out_no_update:
fe4506b6
JC		 4822 put_cpu();
4823}
4824
4825static void igb_setup_dca(struct igb_adapter *adapter)
4826{
7e0e99ef 4827 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4828 int i;
4829
7dfc16fa 4830 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4831 return;
4832
7e0e99ef
AD		 4833 /* Always use CB2 mode, difference is masked in the CB driver. */
4834 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4835
047e0030 4836 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4837 adapter->q_vector[i]->cpu = -1;
4838 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4839 }
4840}
4841
4842static int __igb_notify_dca(struct device *dev, void *data)
4843{
4844 struct net_device *netdev = dev_get_drvdata(dev);
4845 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4846 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4847 struct e1000_hw *hw = &adapter->hw;
4848 unsigned long event = *(unsigned long *)data;
4849
4850 switch (event) {
4851 case DCA_PROVIDER_ADD:
4852 /* if already enabled, don't do it again */
7dfc16fa 4853 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4854 break;
fe4506b6 4855 if (dca_add_requester(dev) == 0) {
bbd98fe4 4856 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4857 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4858 igb_setup_dca(adapter);
4859 break;
4860 }
4861 /* Fall Through since DCA is disabled. */
4862 case DCA_PROVIDER_REMOVE:
7dfc16fa 4863 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4864 /* without this a class_device is left
047e0030 4865 * hanging around in the sysfs model */
fe4506b6 4866 dca_remove_requester(dev);
090b1795 4867 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4868 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4869 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4870 }
4871 break;
4872 }
bbd98fe4 4873
fe4506b6 4874 return 0;
9d5c8243
AK		 4875}
4876
fe4506b6
JC		 4877static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4878 void *p)
4879{
4880 int ret_val;
4881
4882 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4883 __igb_notify_dca);
4884
4885 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4886}
421e02f0 4887#endif /* CONFIG_IGB_DCA */
9d5c8243 4888
0224d663
GR		 4889#ifdef CONFIG_PCI_IOV
4890static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4891{
4892 unsigned char mac_addr[ETH_ALEN];
4893 struct pci_dev *pdev = adapter->pdev;
4894 struct e1000_hw *hw = &adapter->hw;
4895 struct pci_dev *pvfdev;
4896 unsigned int device_id;
4897 u16 thisvf_devfn;
4898
4899 random_ether_addr(mac_addr);
4900 igb_set_vf_mac(adapter, vf, mac_addr);
4901
4902 switch (adapter->hw.mac.type) {
4903 case e1000_82576:
4904 device_id = IGB_82576_VF_DEV_ID;
4905 /* VF Stride for 82576 is 2 */
4906 thisvf_devfn = (pdev->devfn + 0x80 + (vf << 1)) |
4907 (pdev->devfn & 1);
4908 break;
4909 case e1000_i350:
4910 device_id = IGB_I350_VF_DEV_ID;
4911 /* VF Stride for I350 is 4 */
4912 thisvf_devfn = (pdev->devfn + 0x80 + (vf << 2)) |
4913 (pdev->devfn & 3);
4914 break;
4915 default:
4916 device_id = 0;
4917 thisvf_devfn = 0;
4918 break;
4919 }
4920
4921 pvfdev = pci_get_device(hw->vendor_id, device_id, NULL);
4922 while (pvfdev) {
4923 if (pvfdev->devfn == thisvf_devfn)
4924 break;
4925 pvfdev = pci_get_device(hw->vendor_id,
4926 device_id, pvfdev);
4927 }
4928
4929 if (pvfdev)
4930 adapter->vf_data[vf].vfdev = pvfdev;
4931 else
4932 dev_err(&pdev->dev,
4933 "Couldn't find pci dev ptr for VF %4.4x\n",
4934 thisvf_devfn);
4935 return pvfdev != NULL;
4936}
4937
4938static int igb_find_enabled_vfs(struct igb_adapter *adapter)
4939{
4940 struct e1000_hw *hw = &adapter->hw;
4941 struct pci_dev *pdev = adapter->pdev;
4942 struct pci_dev *pvfdev;
4943 u16 vf_devfn = 0;
4944 u16 vf_stride;
4945 unsigned int device_id;
4946 int vfs_found = 0;
4947
4948 switch (adapter->hw.mac.type) {
4949 case e1000_82576:
4950 device_id = IGB_82576_VF_DEV_ID;
4951 /* VF Stride for 82576 is 2 */
4952 vf_stride = 2;
4953 break;
4954 case e1000_i350:
4955 device_id = IGB_I350_VF_DEV_ID;
4956 /* VF Stride for I350 is 4 */
4957 vf_stride = 4;
4958 break;
4959 default:
4960 device_id = 0;
4961 vf_stride = 0;
4962 break;
4963 }
4964
4965 vf_devfn = pdev->devfn + 0x80;
4966 pvfdev = pci_get_device(hw->vendor_id, device_id, NULL);
4967 while (pvfdev) {
4968 if (pvfdev->devfn == vf_devfn)
4969 vfs_found++;
4970 vf_devfn += vf_stride;
4971 pvfdev = pci_get_device(hw->vendor_id,
4972 device_id, pvfdev);
4973 }
4974
4975 return vfs_found;
4976}
4977
4978static int igb_check_vf_assignment(struct igb_adapter *adapter)
4979{
4980 int i;
4981 for (i = 0; i < adapter->vfs_allocated_count; i++) {
4982 if (adapter->vf_data[i].vfdev) {
4983 if (adapter->vf_data[i].vfdev->dev_flags &
4984 PCI_DEV_FLAGS_ASSIGNED)
4985 return true;
4986 }
4987 }
4988 return false;
4989}
4990
4991#endif
4ae196df
AD		 4992static void igb_ping_all_vfs(struct igb_adapter *adapter)
4993{
4994 struct e1000_hw *hw = &adapter->hw;
4995 u32 ping;
4996 int i;
4997
4998 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
4999 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5000 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5001 ping |= E1000_VT_MSGTYPE_CTS;
5002 igb_write_mbx(hw, &ping, 1, i);
5003 }
5004}
5005
7d5753f0
AD		 5006static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5007{
5008 struct e1000_hw *hw = &adapter->hw;
5009 u32 vmolr = rd32(E1000_VMOLR(vf));
5010 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5011
d85b9004 5012 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5013 IGB_VF_FLAG_MULTI_PROMISC);
5014 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5015
5016 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5017 vmolr |= E1000_VMOLR_MPME;
d85b9004 5018 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5019 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5020 } else {
5021 /*
5022 * if we have hashes and we are clearing a multicast promisc
5023 * flag we need to write the hashes to the MTA as this step
5024 * was previously skipped
5025 */
5026 if (vf_data->num_vf_mc_hashes > 30) {
5027 vmolr |= E1000_VMOLR_MPME;
5028 } else if (vf_data->num_vf_mc_hashes) {
5029 int j;
5030 vmolr |= E1000_VMOLR_ROMPE;
5031 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5032 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5033 }
5034 }
5035
5036 wr32(E1000_VMOLR(vf), vmolr);
5037
5038 /* there are flags left unprocessed, likely not supported */
5039 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5040 return -EINVAL;
5041
5042 return 0;
5043
5044}
5045
4ae196df
AD		 5046static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5047 u32 *msgbuf, u32 vf)
5048{
5049 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5050 u16 *hash_list = (u16 *)&msgbuf[1];
5051 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5052 int i;
5053
7d5753f0 5054 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5055 * to this VF for later use to restore when the PF multi cast
5056 * list changes
5057 */
5058 vf_data->num_vf_mc_hashes = n;
5059
7d5753f0
AD		 5060 /* only up to 30 hash values supported */
5061 if (n > 30)
5062 n = 30;
5063
5064 /* store the hashes for later use */
4ae196df 5065 for (i = 0; i < n; i++)
a419aef8 5066 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5067
5068 /* Flush and reset the mta with the new values */
ff41f8dc 5069 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5070
5071 return 0;
5072}
5073
5074static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5075{
5076 struct e1000_hw *hw = &adapter->hw;
5077 struct vf_data_storage *vf_data;
5078 int i, j;
5079
5080 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5081 u32 vmolr = rd32(E1000_VMOLR(i));
5082 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5083
4ae196df 5084 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5085
5086 if ((vf_data->num_vf_mc_hashes > 30) ||
5087 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5088 vmolr |= E1000_VMOLR_MPME;
5089 } else if (vf_data->num_vf_mc_hashes) {
5090 vmolr |= E1000_VMOLR_ROMPE;
5091 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5092 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5093 }
5094 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5095 }
5096}
5097
5098static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5099{
5100 struct e1000_hw *hw = &adapter->hw;
5101 u32 pool_mask, reg, vid;
5102 int i;
5103
5104 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5105
5106 /* Find the vlan filter for this id */
5107 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5108 reg = rd32(E1000_VLVF(i));
5109
5110 /* remove the vf from the pool */
5111 reg &= ~pool_mask;
5112
5113 /* if pool is empty then remove entry from vfta */
5114 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5115 (reg & E1000_VLVF_VLANID_ENABLE)) {
5116 reg = 0;
5117 vid = reg & E1000_VLVF_VLANID_MASK;
5118 igb_vfta_set(hw, vid, false);
5119 }
5120
5121 wr32(E1000_VLVF(i), reg);
5122 }
ae641bdc
AD		 5123
5124 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5125}
5126
5127static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5128{
5129 struct e1000_hw *hw = &adapter->hw;
5130 u32 reg, i;
5131
51466239
AD		 5132 /* The vlvf table only exists on 82576 hardware and newer */
5133 if (hw->mac.type < e1000_82576)
5134 return -1;
5135
5136 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5137 if (!adapter->vfs_allocated_count)
5138 return -1;
5139
5140 /* Find the vlan filter for this id */
5141 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5142 reg = rd32(E1000_VLVF(i));
5143 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5144 vid == (reg & E1000_VLVF_VLANID_MASK))
5145 break;
5146 }
5147
5148 if (add) {
5149 if (i == E1000_VLVF_ARRAY_SIZE) {
5150 /* Did not find a matching VLAN ID entry that was
5151 * enabled. Search for a free filter entry, i.e.
5152 * one without the enable bit set
5153 */
5154 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5155 reg = rd32(E1000_VLVF(i));
5156 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5157 break;
5158 }
5159 }
5160 if (i < E1000_VLVF_ARRAY_SIZE) {
5161 /* Found an enabled/available entry */
5162 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5163
5164 /* if !enabled we need to set this up in vfta */
5165 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5166 /* add VID to filter table */
5167 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5168 reg |= E1000_VLVF_VLANID_ENABLE;
5169 }
cad6d05f
AD		 5170 reg &= ~E1000_VLVF_VLANID_MASK;
5171 reg |= vid;
4ae196df 5172 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5173
5174 /* do not modify RLPML for PF devices */
5175 if (vf >= adapter->vfs_allocated_count)
5176 return 0;
5177
5178 if (!adapter->vf_data[vf].vlans_enabled) {
5179 u32 size;
5180 reg = rd32(E1000_VMOLR(vf));
5181 size = reg & E1000_VMOLR_RLPML_MASK;
5182 size += 4;
5183 reg &= ~E1000_VMOLR_RLPML_MASK;
5184 reg |= size;
5185 wr32(E1000_VMOLR(vf), reg);
5186 }
ae641bdc 5187
51466239 5188 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5189 }
5190 } else {
5191 if (i < E1000_VLVF_ARRAY_SIZE) {
5192 /* remove vf from the pool */
5193 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5194 /* if pool is empty then remove entry from vfta */
5195 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5196 reg = 0;
5197 igb_vfta_set(hw, vid, false);
5198 }
5199 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5200
5201 /* do not modify RLPML for PF devices */
5202 if (vf >= adapter->vfs_allocated_count)
5203 return 0;
5204
5205 adapter->vf_data[vf].vlans_enabled--;
5206 if (!adapter->vf_data[vf].vlans_enabled) {
5207 u32 size;
5208 reg = rd32(E1000_VMOLR(vf));
5209 size = reg & E1000_VMOLR_RLPML_MASK;
5210 size -= 4;
5211 reg &= ~E1000_VMOLR_RLPML_MASK;
5212 reg |= size;
5213 wr32(E1000_VMOLR(vf), reg);
5214 }
4ae196df
AD		 5215 }
5216 }
8151d294
WM		 5217 return 0;
5218}
5219
5220static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5221{
5222 struct e1000_hw *hw = &adapter->hw;
5223
5224 if (vid)
5225 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5226 else
5227 wr32(E1000_VMVIR(vf), 0);
5228}
5229
5230static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5231 int vf, u16 vlan, u8 qos)
5232{
5233 int err = 0;
5234 struct igb_adapter *adapter = netdev_priv(netdev);
5235
5236 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5237 return -EINVAL;
5238 if (vlan || qos) {
5239 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5240 if (err)
5241 goto out;
5242 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5243 igb_set_vmolr(adapter, vf, !vlan);
5244 adapter->vf_data[vf].pf_vlan = vlan;
5245 adapter->vf_data[vf].pf_qos = qos;
5246 dev_info(&adapter->pdev->dev,
5247 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5248 if (test_bit(__IGB_DOWN, &adapter->state)) {
5249 dev_warn(&adapter->pdev->dev,
5250 "The VF VLAN has been set,"
5251 " but the PF device is not up.\n");
5252 dev_warn(&adapter->pdev->dev,
5253 "Bring the PF device up before"
5254 " attempting to use the VF device.\n");
5255 }
5256 } else {
5257 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5258 false, vf);
5259 igb_set_vmvir(adapter, vlan, vf);
5260 igb_set_vmolr(adapter, vf, true);
5261 adapter->vf_data[vf].pf_vlan = 0;
5262 adapter->vf_data[vf].pf_qos = 0;
5263 }
5264out:
5265 return err;
4ae196df
AD		 5266}
5267
5268static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5269{
5270 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5271 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5272
5273 return igb_vlvf_set(adapter, vid, add, vf);
5274}
5275
f2ca0dbe 5276static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5277{
8fa7e0f7
GR		 5278 /* clear flags - except flag that indicates PF has set the MAC */
5279 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5280 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5281
5282 /* reset offloads to defaults */
8151d294 5283 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5284
5285 /* reset vlans for device */
5286 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5287 if (adapter->vf_data[vf].pf_vlan)
5288 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5289 adapter->vf_data[vf].pf_vlan,
5290 adapter->vf_data[vf].pf_qos);
5291 else
5292 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5293
5294 /* reset multicast table array for vf */
5295 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5296
5297 /* Flush and reset the mta with the new values */
ff41f8dc 5298 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5299}
5300
f2ca0dbe
AD		 5301static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5302{
5303 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5304
5305 /* generate a new mac address as we were hotplug removed/added */
8151d294
WM		 5306 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5307 random_ether_addr(vf_mac);
f2ca0dbe
AD		 5308
5309 /* process remaining reset events */
5310 igb_vf_reset(adapter, vf);
5311}
5312
5313static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5314{
5315 struct e1000_hw *hw = &adapter->hw;
5316 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5317 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5318 u32 reg, msgbuf[3];
5319 u8 *addr = (u8 *)(&msgbuf[1]);
5320
5321 /* process all the same items cleared in a function level reset */
f2ca0dbe 5322 igb_vf_reset(adapter, vf);
4ae196df
AD		 5323
5324 /* set vf mac address */
26ad9178 5325 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5326
5327 /* enable transmit and receive for vf */
5328 reg = rd32(E1000_VFTE);
5329 wr32(E1000_VFTE, reg | (1 << vf));
5330 reg = rd32(E1000_VFRE);
5331 wr32(E1000_VFRE, reg | (1 << vf));
5332
8fa7e0f7 5333 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5334
5335 /* reply to reset with ack and vf mac address */
5336 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5337 memcpy(addr, vf_mac, 6);
5338 igb_write_mbx(hw, msgbuf, 3, vf);
5339}
5340
5341static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5342{
de42edde
GR		 5343 /*
5344 * The VF MAC Address is stored in a packed array of bytes
5345 * starting at the second 32 bit word of the msg array
5346 */
f2ca0dbe
AD		 5347 unsigned char *addr = (char *)&msg[1];
5348 int err = -1;
4ae196df 5349
f2ca0dbe
AD		 5350 if (is_valid_ether_addr(addr))
5351 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5352
f2ca0dbe 5353 return err;
4ae196df
AD		 5354}
5355
5356static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5357{
5358 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5359 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5360 u32 msg = E1000_VT_MSGTYPE_NACK;
5361
5362 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5363 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5364 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5365 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5366 vf_data->last_nack = jiffies;
4ae196df
AD		 5367 }
5368}
5369
f2ca0dbe 5370static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5371{
f2ca0dbe
AD		 5372 struct pci_dev *pdev = adapter->pdev;
5373 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5374 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5375 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5376 s32 retval;
5377
f2ca0dbe 5378 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5379
fef45f4c
AD		 5380 if (retval) {
5381 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5382 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5383 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5384 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5385 return;
5386 goto out;
5387 }
4ae196df
AD		 5388
5389 /* this is a message we already processed, do nothing */
5390 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5391 return;
4ae196df
AD		 5392
5393 /*
5394 * until the vf completes a reset it should not be
5395 * allowed to start any configuration.
5396 */
5397
5398 if (msgbuf[0] == E1000_VF_RESET) {
5399 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5400 return;
4ae196df
AD		 5401 }
5402
f2ca0dbe 5403 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5404 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5405 return;
5406 retval = -1;
5407 goto out;
4ae196df
AD		 5408 }
5409
5410 switch ((msgbuf[0] & 0xFFFF)) {
5411 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5412 retval = -EINVAL;
5413 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5414 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5415 else
5416 dev_warn(&pdev->dev,
5417 "VF %d attempted to override administratively "
5418 "set MAC address\nReload the VF driver to "
5419 "resume operations\n", vf);
4ae196df 5420 break;
7d5753f0
AD		 5421 case E1000_VF_SET_PROMISC:
5422 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5423 break;
4ae196df
AD		 5424 case E1000_VF_SET_MULTICAST:
5425 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5426 break;
5427 case E1000_VF_SET_LPE:
5428 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5429 break;
5430 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5431 retval = -1;
5432 if (vf_data->pf_vlan)
5433 dev_warn(&pdev->dev,
5434 "VF %d attempted to override administratively "
5435 "set VLAN tag\nReload the VF driver to "
5436 "resume operations\n", vf);
8151d294
WM		 5437 else
5438 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5439 break;
5440 default:
090b1795 5441 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5442 retval = -1;
5443 break;
5444 }
5445
fef45f4c
AD		 5446 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5447out:
4ae196df
AD		 5448 /* notify the VF of the results of what it sent us */
5449 if (retval)
5450 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5451 else
5452 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5453
4ae196df 5454 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5455}
4ae196df 5456
f2ca0dbe
AD		 5457static void igb_msg_task(struct igb_adapter *adapter)
5458{
5459 struct e1000_hw *hw = &adapter->hw;
5460 u32 vf;
5461
5462 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5463 /* process any reset requests */
5464 if (!igb_check_for_rst(hw, vf))
5465 igb_vf_reset_event(adapter, vf);
5466
5467 /* process any messages pending */
5468 if (!igb_check_for_msg(hw, vf))
5469 igb_rcv_msg_from_vf(adapter, vf);
5470
5471 /* process any acks */
5472 if (!igb_check_for_ack(hw, vf))
5473 igb_rcv_ack_from_vf(adapter, vf);
5474 }
4ae196df
AD		 5475}
5476
68d480c4
AD		 5477/**
5478 * igb_set_uta - Set unicast filter table address
5479 * @adapter: board private structure
5480 *
5481 * The unicast table address is a register array of 32-bit registers.
5482 * The table is meant to be used in a way similar to how the MTA is used
5483 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5484 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5485 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5486 **/
5487static void igb_set_uta(struct igb_adapter *adapter)
5488{
5489 struct e1000_hw *hw = &adapter->hw;
5490 int i;
5491
5492 /* The UTA table only exists on 82576 hardware and newer */
5493 if (hw->mac.type < e1000_82576)
5494 return;
5495
5496 /* we only need to do this if VMDq is enabled */
5497 if (!adapter->vfs_allocated_count)
5498 return;
5499
5500 for (i = 0; i < hw->mac.uta_reg_count; i++)
5501 array_wr32(E1000_UTA, i, ~0);
5502}
5503
9d5c8243
AK		 5504/**
5505 * igb_intr_msi - Interrupt Handler
5506 * @irq: interrupt number
5507 * @data: pointer to a network interface device structure
5508 **/
5509static irqreturn_t igb_intr_msi(int irq, void *data)
5510{
047e0030
AD		 5511 struct igb_adapter *adapter = data;
5512 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5513 struct e1000_hw *hw = &adapter->hw;
5514 /* read ICR disables interrupts using IAM */
5515 u32 icr = rd32(E1000_ICR);
5516
047e0030 5517 igb_write_itr(q_vector);
9d5c8243 5518
7f081d40
AD		 5519 if (icr & E1000_ICR_DRSTA)
5520 schedule_work(&adapter->reset_task);
5521
047e0030 5522 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5523 /* HW is reporting DMA is out of sync */
5524 adapter->stats.doosync++;
5525 }
5526
9d5c8243
AK		 5527 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5528 hw->mac.get_link_status = 1;
5529 if (!test_bit(__IGB_DOWN, &adapter->state))
5530 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5531 }
5532
047e0030 5533 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5534
5535 return IRQ_HANDLED;
5536}
5537
5538/**
4a3c6433 5539 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5540 * @irq: interrupt number
5541 * @data: pointer to a network interface device structure
5542 **/
5543static irqreturn_t igb_intr(int irq, void *data)
5544{
047e0030
AD		 5545 struct igb_adapter *adapter = data;
5546 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5547 struct e1000_hw *hw = &adapter->hw;
5548 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5549 * need for the IMC write */
5550 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5551
5552 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5553 * not set, then the adapter didn't send an interrupt */
5554 if (!(icr & E1000_ICR_INT_ASSERTED))
5555 return IRQ_NONE;
5556
0ba82994
AD		 5557 igb_write_itr(q_vector);
5558
7f081d40
AD		 5559 if (icr & E1000_ICR_DRSTA)
5560 schedule_work(&adapter->reset_task);
5561
047e0030 5562 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5563 /* HW is reporting DMA is out of sync */
5564 adapter->stats.doosync++;
5565 }
5566
9d5c8243
AK		 5567 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5568 hw->mac.get_link_status = 1;
5569 /* guard against interrupt when we're going down */
5570 if (!test_bit(__IGB_DOWN, &adapter->state))
5571 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5572 }
5573
047e0030 5574 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5575
5576 return IRQ_HANDLED;
5577}
5578
0ba82994 5579void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5580{
047e0030 5581 struct igb_adapter *adapter = q_vector->adapter;
46544258 5582 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5583
0ba82994
AD		 5584 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5585 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5586 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5587 igb_set_itr(q_vector);
46544258 5588 else
047e0030 5589 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5590 }
5591
46544258
AD		 5592 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5593 if (adapter->msix_entries)
047e0030 5594 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5595 else
5596 igb_irq_enable(adapter);
5597 }
9d5c8243
AK		 5598}
5599
46544258
AD		 5600/**
5601 * igb_poll - NAPI Rx polling callback
5602 * @napi: napi polling structure
5603 * @budget: count of how many packets we should handle
5604 **/
5605static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5606{
047e0030
AD		 5607 struct igb_q_vector *q_vector = container_of(napi,
5608 struct igb_q_vector,
5609 napi);
16eb8815 5610 bool clean_complete = true;
9d5c8243 5611
421e02f0 5612#ifdef CONFIG_IGB_DCA
047e0030
AD		 5613 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5614 igb_update_dca(q_vector);
fe4506b6 5615#endif
0ba82994 5616 if (q_vector->tx.ring)
13fde97a 5617 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5618
0ba82994 5619 if (q_vector->rx.ring)
cd392f5c 5620 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5621
16eb8815
AD		 5622 /* If all work not completed, return budget and keep polling */
5623 if (!clean_complete)
5624 return budget;
46544258 5625
9d5c8243 5626 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5627 napi_complete(napi);
5628 igb_ring_irq_enable(q_vector);
9d5c8243 5629
16eb8815 5630 return 0;
9d5c8243 5631}
6d8126f9 5632
33af6bcc 5633/**
c5b9bd5e 5634 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
33af6bcc 5635 * @adapter: board private structure
c5b9bd5e
AD		 5636 * @shhwtstamps: timestamp structure to update
5637 * @regval: unsigned 64bit system time value.
5638 *
5639 * We need to convert the system time value stored in the RX/TXSTMP registers
5640 * into a hwtstamp which can be used by the upper level timestamping functions
5641 */
5642static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
5643 struct skb_shared_hwtstamps *shhwtstamps,
5644 u64 regval)
5645{
5646 u64 ns;
5647
55cac248
AD		 5648 /*
5649 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
5650 * 24 to match clock shift we setup earlier.
5651 */
06218a8d 5652 if (adapter->hw.mac.type >= e1000_82580)
55cac248
AD		 5653 regval <<= IGB_82580_TSYNC_SHIFT;
5654
c5b9bd5e
AD		 5655 ns = timecounter_cyc2time(&adapter->clock, regval);
5656 timecompare_update(&adapter->compare, ns);
5657 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
5658 shhwtstamps->hwtstamp = ns_to_ktime(ns);
5659 shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
5660}
5661
5662/**
5663 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5664 * @q_vector: pointer to q_vector containing needed info
06034649 5665 * @buffer: pointer to igb_tx_buffer structure
33af6bcc
PO		 5666 *
5667 * If we were asked to do hardware stamping and such a time stamp is
5668 * available, then it must have been for this skb here because we only
5669 * allow only one such packet into the queue.
5670 */
06034649
AD		 5671static void igb_tx_hwtstamp(struct igb_q_vector *q_vector,
5672 struct igb_tx_buffer *buffer_info)
33af6bcc 5673{
c5b9bd5e 5674 struct igb_adapter *adapter = q_vector->adapter;
33af6bcc 5675 struct e1000_hw *hw = &adapter->hw;
c5b9bd5e
AD		 5676 struct skb_shared_hwtstamps shhwtstamps;
5677 u64 regval;
33af6bcc 5678
c5b9bd5e 5679 /* if skb does not support hw timestamp or TX stamp not valid exit */
2bbfebe2 5680 if (likely(!(buffer_info->tx_flags & IGB_TX_FLAGS_TSTAMP)) ||
c5b9bd5e
AD		 5681 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5682 return;
5683
5684 regval = rd32(E1000_TXSTMPL);
5685 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5686
5687 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
2873957d 5688 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
33af6bcc
PO		 5689}
5690
9d5c8243
AK		 5691/**
5692 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5693 * @q_vector: pointer to q_vector containing needed info
9d5c8243
AK		 5694 * returns true if ring is completely cleaned
5695 **/
047e0030 5696static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5697{
047e0030 5698 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5699 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5700 struct igb_tx_buffer *tx_buffer;
8542db05 5701 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 5702 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5703 unsigned int budget = q_vector->tx.work_limit;
8542db05 5704 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5705
13fde97a
AD		 5706 if (test_bit(__IGB_DOWN, &adapter->state))
5707 return true;
0e014cb1 5708
06034649 5709 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5710 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5711 i -= tx_ring->count;
9d5c8243 5712
13fde97a 5713 for (; budget; budget--) {
8542db05 5714 eop_desc = tx_buffer->next_to_watch;
13fde97a 5715
8542db05
AD		 5716 /* prevent any other reads prior to eop_desc */
5717 rmb();
5718
5719 /* if next_to_watch is not set then there is no work pending */
5720 if (!eop_desc)
5721 break;
13fde97a
AD		 5722
5723 /* if DD is not set pending work has not been completed */
5724 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5725 break;
5726
8542db05
AD		 5727 /* clear next_to_watch to prevent false hangs */
5728 tx_buffer->next_to_watch = NULL;
9d5c8243 5729
ebe42d16
AD		 5730 /* update the statistics for this packet */
5731 total_bytes += tx_buffer->bytecount;
5732 total_packets += tx_buffer->gso_segs;
13fde97a 5733
ebe42d16
AD		 5734 /* retrieve hardware timestamp */
5735 igb_tx_hwtstamp(q_vector, tx_buffer);
5736
5737 /* free the skb */
5738 dev_kfree_skb_any(tx_buffer->skb);
5739 tx_buffer->skb = NULL;
13fde97a 5740
ebe42d16
AD		 5741 /* unmap skb header data */
5742 dma_unmap_single(tx_ring->dev,
5743 tx_buffer->dma,
5744 tx_buffer->length,
5745 DMA_TO_DEVICE);
5746
5747 /* clear last DMA location and unmap remaining buffers */
5748 while (tx_desc != eop_desc) {
5749 tx_buffer->dma = 0;
9d5c8243 5750
13fde97a
AD		 5751 tx_buffer++;
5752 tx_desc++;
9d5c8243 5753 i++;
8542db05
AD		 5754 if (unlikely(!i)) {
5755 i -= tx_ring->count;
06034649 5756 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5757 tx_desc = IGB_TX_DESC(tx_ring, 0);
5758 }
ebe42d16
AD		 5759
5760 /* unmap any remaining paged data */
5761 if (tx_buffer->dma) {
5762 dma_unmap_page(tx_ring->dev,
5763 tx_buffer->dma,
5764 tx_buffer->length,
5765 DMA_TO_DEVICE);
5766 }
5767 }
5768
5769 /* clear last DMA location */
5770 tx_buffer->dma = 0;
5771
5772 /* move us one more past the eop_desc for start of next pkt */
5773 tx_buffer++;
5774 tx_desc++;
5775 i++;
5776 if (unlikely(!i)) {
5777 i -= tx_ring->count;
5778 tx_buffer = tx_ring->tx_buffer_info;
5779 tx_desc = IGB_TX_DESC(tx_ring, 0);
5780 }
0e014cb1
AD		 5781 }
5782
bdbc0631
ED		 5783 netdev_tx_completed_queue(txring_txq(tx_ring),
5784 total_packets, total_bytes);
8542db05 5785 i += tx_ring->count;
9d5c8243 5786 tx_ring->next_to_clean = i;
13fde97a
AD		 5787 u64_stats_update_begin(&tx_ring->tx_syncp);
5788 tx_ring->tx_stats.bytes += total_bytes;
5789 tx_ring->tx_stats.packets += total_packets;
5790 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5791 q_vector->tx.total_bytes += total_bytes;
5792 q_vector->tx.total_packets += total_packets;
9d5c8243 5793
6d095fa8 5794 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5795 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5796
8542db05 5797 eop_desc = tx_buffer->next_to_watch;
9d5c8243 5798
9d5c8243
AK		 5799 /* Detect a transmit hang in hardware, this serializes the
5800 * check with the clearing of time_stamp and movement of i */
6d095fa8 5801 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8542db05
AD		 5802 if (eop_desc &&
5803 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5804 (adapter->tx_timeout_factor * HZ)) &&
5805 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5806
9d5c8243 5807 /* detected Tx unit hang */
59d71989 5808 dev_err(tx_ring->dev,
9d5c8243 5809 "Detected Tx Unit Hang\n"
2d064c06 5810 " Tx Queue <%d>\n"
9d5c8243
AK		 5811 " TDH <%x>\n"
5812 " TDT <%x>\n"
5813 " next_to_use <%x>\n"
5814 " next_to_clean <%x>\n"
9d5c8243
AK		 5815 "buffer_info[next_to_clean]\n"
5816 " time_stamp <%lx>\n"
8542db05 5817 " next_to_watch <%p>\n"
9d5c8243
AK		 5818 " jiffies <%lx>\n"
5819 " desc.status <%x>\n",
2d064c06 5820 tx_ring->queue_index,
238ac817 5821 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5822 readl(tx_ring->tail),
9d5c8243
AK		 5823 tx_ring->next_to_use,
5824 tx_ring->next_to_clean,
8542db05
AD		 5825 tx_buffer->time_stamp,
5826 eop_desc,
9d5c8243 5827 jiffies,
0e014cb1 5828 eop_desc->wb.status);
13fde97a
AD		 5829 netif_stop_subqueue(tx_ring->netdev,
5830 tx_ring->queue_index);
5831
5832 /* we are about to reset, no point in enabling stuff */
5833 return true;
9d5c8243
AK		 5834 }
5835 }
13fde97a
AD		 5836
5837 if (unlikely(total_packets &&
5838 netif_carrier_ok(tx_ring->netdev) &&
5839 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5840 /* Make sure that anybody stopping the queue after this
5841 * sees the new next_to_clean.
5842 */
5843 smp_mb();
5844 if (__netif_subqueue_stopped(tx_ring->netdev,
5845 tx_ring->queue_index) &&
5846 !(test_bit(__IGB_DOWN, &adapter->state))) {
5847 netif_wake_subqueue(tx_ring->netdev,
5848 tx_ring->queue_index);
5849
5850 u64_stats_update_begin(&tx_ring->tx_syncp);
5851 tx_ring->tx_stats.restart_queue++;
5852 u64_stats_update_end(&tx_ring->tx_syncp);
5853 }
5854 }
5855
5856 return !!budget;
9d5c8243
AK		 5857}
5858
cd392f5c 5859static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 5860 union e1000_adv_rx_desc *rx_desc,
5861 struct sk_buff *skb)
9d5c8243 5862{
bc8acf2c 5863 skb_checksum_none_assert(skb);
9d5c8243 5864
294e7d78 5865 /* Ignore Checksum bit is set */
3ceb90fd 5866 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 5867 return;
5868
5869 /* Rx checksum disabled via ethtool */
5870 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 5871 return;
85ad76b2 5872
9d5c8243 5873 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 5874 if (igb_test_staterr(rx_desc,
5875 E1000_RXDEXT_STATERR_TCPE |
5876 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5877 /*
5878 * work around errata with sctp packets where the TCPE aka
5879 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5880 * packets, (aka let the stack check the crc32c)
5881 */
866cff06
AD		 5882 if (!((skb->len == 60) &&
5883 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 5884 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 5885 ring->rx_stats.csum_err++;
12dcd86b
ED		 5886 u64_stats_update_end(&ring->rx_syncp);
5887 }
9d5c8243 5888 /* let the stack verify checksum errors */
9d5c8243
AK		 5889 return;
5890 }
5891 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 5892 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
5893 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 5894 skb->ip_summed = CHECKSUM_UNNECESSARY;
5895
3ceb90fd
AD		 5896 dev_dbg(ring->dev, "cksum success: bits %08X\n",
5897 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 5898}
5899
077887c3
AD		 5900static inline void igb_rx_hash(struct igb_ring *ring,
5901 union e1000_adv_rx_desc *rx_desc,
5902 struct sk_buff *skb)
5903{
5904 if (ring->netdev->features & NETIF_F_RXHASH)
5905 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
5906}
5907
3ceb90fd
AD		 5908static void igb_rx_hwtstamp(struct igb_q_vector *q_vector,
5909 union e1000_adv_rx_desc *rx_desc,
5910 struct sk_buff *skb)
c5b9bd5e
AD		 5911{
5912 struct igb_adapter *adapter = q_vector->adapter;
5913 struct e1000_hw *hw = &adapter->hw;
5914 u64 regval;
5915
3ceb90fd
AD		 5916 if (!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP |
5917 E1000_RXDADV_STAT_TS))
5918 return;
5919
c5b9bd5e
AD		 5920 /*
5921 * If this bit is set, then the RX registers contain the time stamp. No
5922 * other packet will be time stamped until we read these registers, so
5923 * read the registers to make them available again. Because only one
5924 * packet can be time stamped at a time, we know that the register
5925 * values must belong to this one here and therefore we don't need to
5926 * compare any of the additional attributes stored for it.
5927 *
2244d07b 5928 * If nothing went wrong, then it should have a shared tx_flags that we
c5b9bd5e
AD		 5929 * can turn into a skb_shared_hwtstamps.
5930 */
3ceb90fd 5931 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
757b77e2
NN		 5932 u32 *stamp = (u32 *)skb->data;
5933 regval = le32_to_cpu(*(stamp + 2));
5934 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5935 skb_pull(skb, IGB_TS_HDR_LEN);
5936 } else {
5937 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5938 return;
c5b9bd5e 5939
757b77e2
NN		 5940 regval = rd32(E1000_RXSTMPL);
5941 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5942 }
c5b9bd5e
AD		 5943
5944 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5945}
8be10e91
AD		 5946
5947static void igb_rx_vlan(struct igb_ring *ring,
5948 union e1000_adv_rx_desc *rx_desc,
5949 struct sk_buff *skb)
5950{
5951 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
5952 u16 vid;
5953 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
5954 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags))
5955 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
5956 else
5957 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
5958
5959 __vlan_hwaccel_put_tag(skb, vid);
5960 }
5961}
5962
44390ca6 5963static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc)
2d94d8ab
AD		 5964{
5965 /* HW will not DMA in data larger than the given buffer, even if it
5966 * parses the (NFS, of course) header to be larger. In that case, it
5967 * fills the header buffer and spills the rest into the page.
5968 */
5969 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5970 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
44390ca6
AD		 5971 if (hlen > IGB_RX_HDR_LEN)
5972 hlen = IGB_RX_HDR_LEN;
2d94d8ab
AD		 5973 return hlen;
5974}
5975
cd392f5c 5976static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)
9d5c8243 5977{
0ba82994 5978 struct igb_ring *rx_ring = q_vector->rx.ring;
16eb8815
AD		 5979 union e1000_adv_rx_desc *rx_desc;
5980 const int current_node = numa_node_id();
9d5c8243 5981 unsigned int total_bytes = 0, total_packets = 0;
16eb8815
AD		 5982 u16 cleaned_count = igb_desc_unused(rx_ring);
5983 u16 i = rx_ring->next_to_clean;
9d5c8243 5984
60136906 5985 rx_desc = IGB_RX_DESC(rx_ring, i);
9d5c8243 5986
3ceb90fd 5987 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
06034649 5988 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
16eb8815
AD		 5989 struct sk_buff *skb = buffer_info->skb;
5990 union e1000_adv_rx_desc *next_rxd;
9d5c8243 5991
69d3ca53 5992 buffer_info->skb = NULL;
16eb8815 5993 prefetch(skb->data);
69d3ca53
AD		 5994
5995 i++;
5996 if (i == rx_ring->count)
5997 i = 0;
42d0781a 5998
60136906 5999 next_rxd = IGB_RX_DESC(rx_ring, i);
69d3ca53 6000 prefetch(next_rxd);
9d5c8243 6001
16eb8815
AD		 6002 /*
6003 * This memory barrier is needed to keep us from reading
6004 * any other fields out of the rx_desc until we know the
6005 * RXD_STAT_DD bit is set
6006 */
6007 rmb();
9d5c8243 6008
16eb8815
AD		 6009 if (!skb_is_nonlinear(skb)) {
6010 __skb_put(skb, igb_get_hlen(rx_desc));
6011 dma_unmap_single(rx_ring->dev, buffer_info->dma,
44390ca6 6012 IGB_RX_HDR_LEN,
59d71989 6013 DMA_FROM_DEVICE);
91615f76 6014 buffer_info->dma = 0;
bf36c1a0
AD		 6015 }
6016
16eb8815
AD		 6017 if (rx_desc->wb.upper.length) {
6018 u16 length = le16_to_cpu(rx_desc->wb.upper.length);
bf36c1a0 6019
aa913403 6020 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
bf36c1a0
AD		 6021 buffer_info->page,
6022 buffer_info->page_offset,
6023 length);
6024
16eb8815
AD		 6025 skb->len += length;
6026 skb->data_len += length;
95b9c1df 6027 skb->truesize += PAGE_SIZE / 2;
16eb8815 6028
d1eff350
AD		 6029 if ((page_count(buffer_info->page) != 1) ||
6030 (page_to_nid(buffer_info->page) != current_node))
bf36c1a0
AD		 6031 buffer_info->page = NULL;
6032 else
6033 get_page(buffer_info->page);
9d5c8243 6034
16eb8815
AD		 6035 dma_unmap_page(rx_ring->dev, buffer_info->page_dma,
6036 PAGE_SIZE / 2, DMA_FROM_DEVICE);
6037 buffer_info->page_dma = 0;
9d5c8243 6038 }
9d5c8243 6039
3ceb90fd 6040 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)) {
06034649
AD		 6041 struct igb_rx_buffer *next_buffer;
6042 next_buffer = &rx_ring->rx_buffer_info[i];
b2d56536
AD		 6043 buffer_info->skb = next_buffer->skb;
6044 buffer_info->dma = next_buffer->dma;
6045 next_buffer->skb = skb;
6046 next_buffer->dma = 0;
bf36c1a0
AD		 6047 goto next_desc;
6048 }
44390ca6 6049
3ceb90fd
AD		 6050 if (igb_test_staterr(rx_desc,
6051 E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
16eb8815 6052 dev_kfree_skb_any(skb);
9d5c8243
AK		 6053 goto next_desc;
6054 }
9d5c8243 6055
3ceb90fd 6056 igb_rx_hwtstamp(q_vector, rx_desc, skb);
077887c3 6057 igb_rx_hash(rx_ring, rx_desc, skb);
3ceb90fd 6058 igb_rx_checksum(rx_ring, rx_desc, skb);
8be10e91 6059 igb_rx_vlan(rx_ring, rx_desc, skb);
3ceb90fd
AD		 6060
6061 total_bytes += skb->len;
6062 total_packets++;
6063
6064 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6065
b2cb09b1 6066 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6067
16eb8815 6068 budget--;
9d5c8243 6069next_desc:
16eb8815
AD		 6070 if (!budget)
6071 break;
6072
6073 cleaned_count++;
9d5c8243
AK		 6074 /* return some buffers to hardware, one at a time is too slow */
6075 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
cd392f5c 6076 igb_alloc_rx_buffers(rx_ring, cleaned_count);
9d5c8243
AK		 6077 cleaned_count = 0;
6078 }
6079
6080 /* use prefetched values */
6081 rx_desc = next_rxd;
9d5c8243 6082 }
bf36c1a0 6083
9d5c8243 6084 rx_ring->next_to_clean = i;
12dcd86b 6085 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6086 rx_ring->rx_stats.packets += total_packets;
6087 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6088 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6089 q_vector->rx.total_packets += total_packets;
6090 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6091
6092 if (cleaned_count)
cd392f5c 6093 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6094
16eb8815 6095 return !!budget;
9d5c8243
AK		 6096}
6097
c023cd88 6098static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring,
06034649 6099 struct igb_rx_buffer *bi)
c023cd88
AD		 6100{
6101 struct sk_buff *skb = bi->skb;
6102 dma_addr_t dma = bi->dma;
6103
6104 if (dma)
6105 return true;
6106
6107 if (likely(!skb)) {
6108 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6109 IGB_RX_HDR_LEN);
6110 bi->skb = skb;
6111 if (!skb) {
6112 rx_ring->rx_stats.alloc_failed++;
6113 return false;
6114 }
6115
6116 /* initialize skb for ring */
6117 skb_record_rx_queue(skb, rx_ring->queue_index);
6118 }
6119
6120 dma = dma_map_single(rx_ring->dev, skb->data,
6121 IGB_RX_HDR_LEN, DMA_FROM_DEVICE);
6122
6123 if (dma_mapping_error(rx_ring->dev, dma)) {
6124 rx_ring->rx_stats.alloc_failed++;
6125 return false;
6126 }
6127
6128 bi->dma = dma;
6129 return true;
6130}
6131
6132static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6133 struct igb_rx_buffer *bi)
c023cd88
AD		 6134{
6135 struct page *page = bi->page;
6136 dma_addr_t page_dma = bi->page_dma;
6137 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
6138
6139 if (page_dma)
6140 return true;
6141
6142 if (!page) {
1f2149c1 6143 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
c023cd88
AD		 6144 bi->page = page;
6145 if (unlikely(!page)) {
6146 rx_ring->rx_stats.alloc_failed++;
6147 return false;
6148 }
6149 }
6150
6151 page_dma = dma_map_page(rx_ring->dev, page,
6152 page_offset, PAGE_SIZE / 2,
6153 DMA_FROM_DEVICE);
6154
6155 if (dma_mapping_error(rx_ring->dev, page_dma)) {
6156 rx_ring->rx_stats.alloc_failed++;
6157 return false;
6158 }
6159
6160 bi->page_dma = page_dma;
6161 bi->page_offset = page_offset;
6162 return true;
6163}
6164
9d5c8243 6165/**
cd392f5c 6166 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6167 * @adapter: address of board private structure
6168 **/
cd392f5c 6169void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6170{
9d5c8243 6171 union e1000_adv_rx_desc *rx_desc;
06034649 6172 struct igb_rx_buffer *bi;
c023cd88 6173 u16 i = rx_ring->next_to_use;
9d5c8243 6174
60136906 6175 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6176 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6177 i -= rx_ring->count;
9d5c8243
AK		 6178
6179 while (cleaned_count--) {
c023cd88
AD		 6180 if (!igb_alloc_mapped_skb(rx_ring, bi))
6181 break;
9d5c8243 6182
c023cd88
AD		 6183 /* Refresh the desc even if buffer_addrs didn't change
6184 * because each write-back erases this info. */
6185 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9d5c8243 6186
c023cd88
AD		 6187 if (!igb_alloc_mapped_page(rx_ring, bi))
6188 break;
6189
6190 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9d5c8243 6191
c023cd88
AD		 6192 rx_desc++;
6193 bi++;
9d5c8243 6194 i++;
c023cd88 6195 if (unlikely(!i)) {
60136906 6196 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6197 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6198 i -= rx_ring->count;
6199 }
6200
6201 /* clear the hdr_addr for the next_to_use descriptor */
6202 rx_desc->read.hdr_addr = 0;
9d5c8243
AK		 6203 }
6204
c023cd88
AD		 6205 i += rx_ring->count;
6206
9d5c8243
AK		 6207 if (rx_ring->next_to_use != i) {
6208 rx_ring->next_to_use = i;
9d5c8243
AK		 6209
6210 /* Force memory writes to complete before letting h/w
6211 * know there are new descriptors to fetch. (Only
6212 * applicable for weak-ordered memory model archs,
6213 * such as IA-64). */
6214 wmb();
fce99e34 6215 writel(i, rx_ring->tail);
9d5c8243
AK		 6216 }
6217}
6218
6219/**
6220 * igb_mii_ioctl -
6221 * @netdev:
6222 * @ifreq:
6223 * @cmd:
6224 **/
6225static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6226{
6227 struct igb_adapter *adapter = netdev_priv(netdev);
6228 struct mii_ioctl_data *data = if_mii(ifr);
6229
6230 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6231 return -EOPNOTSUPP;
6232
6233 switch (cmd) {
6234 case SIOCGMIIPHY:
6235 data->phy_id = adapter->hw.phy.addr;
6236 break;
6237 case SIOCGMIIREG:
f5f4cf08
AD		 6238 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6239 &data->val_out))
9d5c8243
AK		 6240 return -EIO;
6241 break;
6242 case SIOCSMIIREG:
6243 default:
6244 return -EOPNOTSUPP;
6245 }
6246 return 0;
6247}
6248
c6cb090b
PO		 6249/**
6250 * igb_hwtstamp_ioctl - control hardware time stamping
6251 * @netdev:
6252 * @ifreq:
6253 * @cmd:
6254 *
33af6bcc
PO		 6255 * Outgoing time stamping can be enabled and disabled. Play nice and
6256 * disable it when requested, although it shouldn't case any overhead
6257 * when no packet needs it. At most one packet in the queue may be
6258 * marked for time stamping, otherwise it would be impossible to tell
6259 * for sure to which packet the hardware time stamp belongs.
6260 *
6261 * Incoming time stamping has to be configured via the hardware
6262 * filters. Not all combinations are supported, in particular event
6263 * type has to be specified. Matching the kind of event packet is
6264 * not supported, with the exception of "all V2 events regardless of
6265 * level 2 or 4".
6266 *
c6cb090b
PO		 6267 **/
6268static int igb_hwtstamp_ioctl(struct net_device *netdev,
6269 struct ifreq *ifr, int cmd)
6270{
33af6bcc
PO		 6271 struct igb_adapter *adapter = netdev_priv(netdev);
6272 struct e1000_hw *hw = &adapter->hw;
c6cb090b 6273 struct hwtstamp_config config;
c5b9bd5e
AD		 6274 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
6275 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
33af6bcc 6276 u32 tsync_rx_cfg = 0;
c5b9bd5e
AD		 6277 bool is_l4 = false;
6278 bool is_l2 = false;
33af6bcc 6279 u32 regval;
c6cb090b
PO		 6280
6281 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6282 return -EFAULT;
6283
6284 /* reserved for future extensions */
6285 if (config.flags)
6286 return -EINVAL;
6287
33af6bcc
PO		 6288 switch (config.tx_type) {
6289 case HWTSTAMP_TX_OFF:
c5b9bd5e 6290 tsync_tx_ctl = 0;
33af6bcc 6291 case HWTSTAMP_TX_ON:
33af6bcc
PO		 6292 break;
6293 default:
6294 return -ERANGE;
6295 }
6296
6297 switch (config.rx_filter) {
6298 case HWTSTAMP_FILTER_NONE:
c5b9bd5e 6299 tsync_rx_ctl = 0;
33af6bcc
PO		 6300 break;
6301 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6302 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6303 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6304 case HWTSTAMP_FILTER_ALL:
6305 /*
6306 * register TSYNCRXCFG must be set, therefore it is not
6307 * possible to time stamp both Sync and Delay_Req messages
6308 * => fall back to time stamping all packets
6309 */
c5b9bd5e 6310 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
33af6bcc
PO		 6311 config.rx_filter = HWTSTAMP_FILTER_ALL;
6312 break;
6313 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
c5b9bd5e 6314 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6315 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
c5b9bd5e 6316 is_l4 = true;
33af6bcc
PO		 6317 break;
6318 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
c5b9bd5e 6319 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
33af6bcc 6320 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
c5b9bd5e 6321 is_l4 = true;
33af6bcc
PO		 6322 break;
6323 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6324 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
c5b9bd5e 6325 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6326 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
c5b9bd5e
AD		 6327 is_l2 = true;
6328 is_l4 = true;
33af6bcc
PO		 6329 config.rx_filter = HWTSTAMP_FILTER_SOME;
6330 break;
6331 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6332 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
c5b9bd5e 6333 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
33af6bcc 6334 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
c5b9bd5e
AD		 6335 is_l2 = true;
6336 is_l4 = true;
33af6bcc
PO		 6337 config.rx_filter = HWTSTAMP_FILTER_SOME;
6338 break;
6339 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6340 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6341 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
c5b9bd5e 6342 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
33af6bcc 6343 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
c5b9bd5e 6344 is_l2 = true;
11ba69e8 6345 is_l4 = true;
33af6bcc
PO		 6346 break;
6347 default:
6348 return -ERANGE;
6349 }
6350
c5b9bd5e
AD		 6351 if (hw->mac.type == e1000_82575) {
6352 if (tsync_rx_ctl | tsync_tx_ctl)
6353 return -EINVAL;
6354 return 0;
6355 }
6356
757b77e2
NN		 6357 /*
6358 * Per-packet timestamping only works if all packets are
6359 * timestamped, so enable timestamping in all packets as
6360 * long as one rx filter was configured.
6361 */
06218a8d 6362 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
757b77e2
NN		 6363 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6364 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6365 }
6366
33af6bcc
PO		 6367 /* enable/disable TX */
6368 regval = rd32(E1000_TSYNCTXCTL);
c5b9bd5e
AD		 6369 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6370 regval |= tsync_tx_ctl;
33af6bcc
PO		 6371 wr32(E1000_TSYNCTXCTL, regval);
6372
c5b9bd5e 6373 /* enable/disable RX */
33af6bcc 6374 regval = rd32(E1000_TSYNCRXCTL);
c5b9bd5e
AD		 6375 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6376 regval |= tsync_rx_ctl;
33af6bcc 6377 wr32(E1000_TSYNCRXCTL, regval);
33af6bcc 6378
c5b9bd5e
AD		 6379 /* define which PTP packets are time stamped */
6380 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
33af6bcc 6381
c5b9bd5e
AD		 6382 /* define ethertype filter for timestamped packets */
6383 if (is_l2)
6384 wr32(E1000_ETQF(3),
6385 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6386 E1000_ETQF_1588 | /* enable timestamping */
6387 ETH_P_1588)); /* 1588 eth protocol type */
6388 else
6389 wr32(E1000_ETQF(3), 0);
6390
6391#define PTP_PORT 319
6392 /* L4 Queue Filter[3]: filter by destination port and protocol */
6393 if (is_l4) {
6394 u32 ftqf = (IPPROTO_UDP /* UDP */
6395 | E1000_FTQF_VF_BP /* VF not compared */
6396 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6397 | E1000_FTQF_MASK); /* mask all inputs */
6398 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6399
6400 wr32(E1000_IMIR(3), htons(PTP_PORT));
6401 wr32(E1000_IMIREXT(3),
6402 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6403 if (hw->mac.type == e1000_82576) {
6404 /* enable source port check */
6405 wr32(E1000_SPQF(3), htons(PTP_PORT));
6406 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6407 }
6408 wr32(E1000_FTQF(3), ftqf);
6409 } else {
6410 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6411 }
33af6bcc
PO		 6412 wrfl();
6413
6414 adapter->hwtstamp_config = config;
6415
6416 /* clear TX/RX time stamp registers, just to be sure */
6417 regval = rd32(E1000_TXSTMPH);
6418 regval = rd32(E1000_RXSTMPH);
c6cb090b 6419
33af6bcc
PO		 6420 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6421 -EFAULT : 0;
c6cb090b
PO		 6422}
6423
9d5c8243
AK		 6424/**
6425 * igb_ioctl -
6426 * @netdev:
6427 * @ifreq:
6428 * @cmd:
6429 **/
6430static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6431{
6432 switch (cmd) {
6433 case SIOCGMIIPHY:
6434 case SIOCGMIIREG:
6435 case SIOCSMIIREG:
6436 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 6437 case SIOCSHWTSTAMP:
6438 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6439 default:
6440 return -EOPNOTSUPP;
6441 }
6442}
6443
009bc06e
AD		 6444s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6445{
6446 struct igb_adapter *adapter = hw->back;
6447 u16 cap_offset;
6448
bdaae04c 6449 cap_offset = adapter->pdev->pcie_cap;
009bc06e
AD		 6450 if (!cap_offset)
6451 return -E1000_ERR_CONFIG;
6452
6453 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6454
6455 return 0;
6456}
6457
6458s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6459{
6460 struct igb_adapter *adapter = hw->back;
6461 u16 cap_offset;
6462
bdaae04c 6463 cap_offset = adapter->pdev->pcie_cap;
009bc06e
AD		 6464 if (!cap_offset)
6465 return -E1000_ERR_CONFIG;
6466
6467 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6468
6469 return 0;
6470}
6471
c8f44aff 6472static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6473{
6474 struct igb_adapter *adapter = netdev_priv(netdev);
6475 struct e1000_hw *hw = &adapter->hw;
6476 u32 ctrl, rctl;
5faf030c 6477 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6478
5faf030c 6479 if (enable) {
9d5c8243
AK		 6480 /* enable VLAN tag insert/strip */
6481 ctrl = rd32(E1000_CTRL);
6482 ctrl |= E1000_CTRL_VME;
6483 wr32(E1000_CTRL, ctrl);
6484
51466239 6485 /* Disable CFI check */
9d5c8243 6486 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6487 rctl &= ~E1000_RCTL_CFIEN;
6488 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6489 } else {
6490 /* disable VLAN tag insert/strip */
6491 ctrl = rd32(E1000_CTRL);
6492 ctrl &= ~E1000_CTRL_VME;
6493 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6494 }
6495
e1739522 6496 igb_rlpml_set(adapter);
9d5c8243
AK		 6497}
6498
8e586137 6499static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6500{
6501 struct igb_adapter *adapter = netdev_priv(netdev);
6502 struct e1000_hw *hw = &adapter->hw;
4ae196df 6503 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6504
51466239
AD		 6505 /* attempt to add filter to vlvf array */
6506 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6507
51466239
AD		 6508 /* add the filter since PF can receive vlans w/o entry in vlvf */
6509 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6510
6511 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6512
6513 return 0;
9d5c8243
AK		 6514}
6515
8e586137 6516static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6517{
6518 struct igb_adapter *adapter = netdev_priv(netdev);
6519 struct e1000_hw *hw = &adapter->hw;
4ae196df 6520 int pf_id = adapter->vfs_allocated_count;
51466239 6521 s32 err;
9d5c8243 6522
51466239
AD		 6523 /* remove vlan from VLVF table array */
6524 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6525
51466239
AD		 6526 /* if vid was not present in VLVF just remove it from table */
6527 if (err)
4ae196df 6528 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6529
6530 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6531
6532 return 0;
9d5c8243
AK		 6533}
6534
6535static void igb_restore_vlan(struct igb_adapter *adapter)
6536{
b2cb09b1 6537 u16 vid;
9d5c8243 6538
5faf030c
AD		 6539 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6540
b2cb09b1
JP		 6541 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6542 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6543}
6544
14ad2513 6545int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6546{
090b1795 6547 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6548 struct e1000_mac_info *mac = &adapter->hw.mac;
6549
6550 mac->autoneg = 0;
6551
14ad2513
DD		 6552 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6553 * for the switch() below to work */
6554 if ((spd & 1) || (dplx & ~1))
6555 goto err_inval;
6556
cd2638a8
CW		 6557 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6558 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6559 spd != SPEED_1000 &&
6560 dplx != DUPLEX_FULL)
6561 goto err_inval;
cd2638a8 6562
14ad2513 6563 switch (spd + dplx) {
9d5c8243
AK		 6564 case SPEED_10 + DUPLEX_HALF:
6565 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6566 break;
6567 case SPEED_10 + DUPLEX_FULL:
6568 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6569 break;
6570 case SPEED_100 + DUPLEX_HALF:
6571 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6572 break;
6573 case SPEED_100 + DUPLEX_FULL:
6574 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6575 break;
6576 case SPEED_1000 + DUPLEX_FULL:
6577 mac->autoneg = 1;
6578 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6579 break;
6580 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6581 default:
14ad2513 6582 goto err_inval;
9d5c8243
AK		 6583 }
6584 return 0;
14ad2513
DD		 6585
6586err_inval:
6587 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6588 return -EINVAL;
9d5c8243
AK		 6589}
6590
3fe7c4c9 6591static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 6592{
6593 struct net_device *netdev = pci_get_drvdata(pdev);
6594 struct igb_adapter *adapter = netdev_priv(netdev);
6595 struct e1000_hw *hw = &adapter->hw;
2d064c06 6596 u32 ctrl, rctl, status;
9d5c8243
AK		 6597 u32 wufc = adapter->wol;
6598#ifdef CONFIG_PM
6599 int retval = 0;
6600#endif
6601
6602 netif_device_detach(netdev);
6603
a88f10ec
AD		 6604 if (netif_running(netdev))
6605 igb_close(netdev);
6606
047e0030 6607 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6608
6609#ifdef CONFIG_PM
6610 retval = pci_save_state(pdev);
6611 if (retval)
6612 return retval;
6613#endif
6614
6615 status = rd32(E1000_STATUS);
6616 if (status & E1000_STATUS_LU)
6617 wufc &= ~E1000_WUFC_LNKC;
6618
6619 if (wufc) {
6620 igb_setup_rctl(adapter);
ff41f8dc 6621 igb_set_rx_mode(netdev);
9d5c8243
AK		 6622
6623 /* turn on all-multi mode if wake on multicast is enabled */
6624 if (wufc & E1000_WUFC_MC) {
6625 rctl = rd32(E1000_RCTL);
6626 rctl |= E1000_RCTL_MPE;
6627 wr32(E1000_RCTL, rctl);
6628 }
6629
6630 ctrl = rd32(E1000_CTRL);
6631 /* advertise wake from D3Cold */
6632 #define E1000_CTRL_ADVD3WUC 0x00100000
6633 /* phy power management enable */
6634 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6635 ctrl |= E1000_CTRL_ADVD3WUC;
6636 wr32(E1000_CTRL, ctrl);
6637
9d5c8243 6638 /* Allow time for pending master requests to run */
330a6d6a 6639 igb_disable_pcie_master(hw);
9d5c8243
AK		 6640
6641 wr32(E1000_WUC, E1000_WUC_PME_EN);
6642 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6643 } else {
6644 wr32(E1000_WUC, 0);
6645 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6646 }
6647
3fe7c4c9
RW		 6648 *enable_wake = wufc || adapter->en_mng_pt;
6649 if (!*enable_wake)
88a268c1
NN		 6650 igb_power_down_link(adapter);
6651 else
6652 igb_power_up_link(adapter);
9d5c8243
AK		 6653
6654 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6655 * would have already happened in close and is redundant. */
6656 igb_release_hw_control(adapter);
6657
6658 pci_disable_device(pdev);
6659
9d5c8243
AK		 6660 return 0;
6661}
6662
6663#ifdef CONFIG_PM
3fe7c4c9
RW		 6664static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
6665{
6666 int retval;
6667 bool wake;
6668
6669 retval = __igb_shutdown(pdev, &wake);
6670 if (retval)
6671 return retval;
6672
6673 if (wake) {
6674 pci_prepare_to_sleep(pdev);
6675 } else {
6676 pci_wake_from_d3(pdev, false);
6677 pci_set_power_state(pdev, PCI_D3hot);
6678 }
6679
6680 return 0;
6681}
6682
9d5c8243
AK		 6683static int igb_resume(struct pci_dev *pdev)
6684{
6685 struct net_device *netdev = pci_get_drvdata(pdev);
6686 struct igb_adapter *adapter = netdev_priv(netdev);
6687 struct e1000_hw *hw = &adapter->hw;
6688 u32 err;
6689
6690 pci_set_power_state(pdev, PCI_D0);
6691 pci_restore_state(pdev);
b94f2d77 6692 pci_save_state(pdev);
42bfd33a 6693
aed5dec3 6694 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6695 if (err) {
6696 dev_err(&pdev->dev,
6697 "igb: Cannot enable PCI device from suspend\n");
6698 return err;
6699 }
6700 pci_set_master(pdev);
6701
6702 pci_enable_wake(pdev, PCI_D3hot, 0);
6703 pci_enable_wake(pdev, PCI_D3cold, 0);
6704
047e0030 6705 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6706 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6707 return -ENOMEM;
9d5c8243
AK		 6708 }
6709
9d5c8243 6710 igb_reset(adapter);
a8564f03
AD		 6711
6712 /* let the f/w know that the h/w is now under the control of the
6713 * driver. */
6714 igb_get_hw_control(adapter);
6715
9d5c8243
AK		 6716 wr32(E1000_WUS, ~0);
6717
a88f10ec
AD		 6718 if (netif_running(netdev)) {
6719 err = igb_open(netdev);
6720 if (err)
6721 return err;
6722 }
9d5c8243
AK		 6723
6724 netif_device_attach(netdev);
6725
9d5c8243
AK		 6726 return 0;
6727}
6728#endif
6729
6730static void igb_shutdown(struct pci_dev *pdev)
6731{
3fe7c4c9
RW		 6732 bool wake;
6733
6734 __igb_shutdown(pdev, &wake);
6735
6736 if (system_state == SYSTEM_POWER_OFF) {
6737 pci_wake_from_d3(pdev, wake);
6738 pci_set_power_state(pdev, PCI_D3hot);
6739 }
9d5c8243
AK		 6740}
6741
6742#ifdef CONFIG_NET_POLL_CONTROLLER
6743/*
6744 * Polling 'interrupt' - used by things like netconsole to send skbs
6745 * without having to re-enable interrupts. It's not called while
6746 * the interrupt routine is executing.
6747 */
6748static void igb_netpoll(struct net_device *netdev)
6749{
6750 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6751 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 6752 struct igb_q_vector *q_vector;
9d5c8243 6753 int i;
9d5c8243 6754
047e0030 6755 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 6756 q_vector = adapter->q_vector[i];
6757 if (adapter->msix_entries)
6758 wr32(E1000_EIMC, q_vector->eims_value);
6759 else
6760 igb_irq_disable(adapter);
047e0030 6761 napi_schedule(&q_vector->napi);
eebbbdba 6762 }
9d5c8243
AK		 6763}
6764#endif /* CONFIG_NET_POLL_CONTROLLER */
6765
6766/**
6767 * igb_io_error_detected - called when PCI error is detected
6768 * @pdev: Pointer to PCI device
6769 * @state: The current pci connection state
6770 *
6771 * This function is called after a PCI bus error affecting
6772 * this device has been detected.
6773 */
6774static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6775 pci_channel_state_t state)
6776{
6777 struct net_device *netdev = pci_get_drvdata(pdev);
6778 struct igb_adapter *adapter = netdev_priv(netdev);
6779
6780 netif_device_detach(netdev);
6781
59ed6eec
AD		 6782 if (state == pci_channel_io_perm_failure)
6783 return PCI_ERS_RESULT_DISCONNECT;
6784
9d5c8243
AK		 6785 if (netif_running(netdev))
6786 igb_down(adapter);
6787 pci_disable_device(pdev);
6788
6789 /* Request a slot slot reset. */
6790 return PCI_ERS_RESULT_NEED_RESET;
6791}
6792
6793/**
6794 * igb_io_slot_reset - called after the pci bus has been reset.
6795 * @pdev: Pointer to PCI device
6796 *
6797 * Restart the card from scratch, as if from a cold-boot. Implementation
6798 * resembles the first-half of the igb_resume routine.
6799 */
6800static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6801{
6802 struct net_device *netdev = pci_get_drvdata(pdev);
6803 struct igb_adapter *adapter = netdev_priv(netdev);
6804 struct e1000_hw *hw = &adapter->hw;
40a914fa 6805 pci_ers_result_t result;
42bfd33a 6806 int err;
9d5c8243 6807
aed5dec3 6808 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6809 dev_err(&pdev->dev,
6810 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6811 result = PCI_ERS_RESULT_DISCONNECT;
6812 } else {
6813 pci_set_master(pdev);
6814 pci_restore_state(pdev);
b94f2d77 6815 pci_save_state(pdev);
9d5c8243 6816
40a914fa
AD		 6817 pci_enable_wake(pdev, PCI_D3hot, 0);
6818 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6819
40a914fa
AD		 6820 igb_reset(adapter);
6821 wr32(E1000_WUS, ~0);
6822 result = PCI_ERS_RESULT_RECOVERED;
6823 }
9d5c8243 6824
ea943d41
JK		 6825 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6826 if (err) {
6827 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6828 "failed 0x%0x\n", err);
6829 /* non-fatal, continue */
6830 }
40a914fa
AD		 6831
6832 return result;
9d5c8243
AK		 6833}
6834
6835/**
6836 * igb_io_resume - called when traffic can start flowing again.
6837 * @pdev: Pointer to PCI device
6838 *
6839 * This callback is called when the error recovery driver tells us that
6840 * its OK to resume normal operation. Implementation resembles the
6841 * second-half of the igb_resume routine.
6842 */
6843static void igb_io_resume(struct pci_dev *pdev)
6844{
6845 struct net_device *netdev = pci_get_drvdata(pdev);
6846 struct igb_adapter *adapter = netdev_priv(netdev);
6847
9d5c8243
AK		 6848 if (netif_running(netdev)) {
6849 if (igb_up(adapter)) {
6850 dev_err(&pdev->dev, "igb_up failed after reset\n");
6851 return;
6852 }
6853 }
6854
6855 netif_device_attach(netdev);
6856
6857 /* let the f/w know that the h/w is now under the control of the
6858 * driver. */
6859 igb_get_hw_control(adapter);
9d5c8243
AK		 6860}
6861
26ad9178
AD		 6862static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6863 u8 qsel)
6864{
6865 u32 rar_low, rar_high;
6866 struct e1000_hw *hw = &adapter->hw;
6867
6868 /* HW expects these in little endian so we reverse the byte order
6869 * from network order (big endian) to little endian
6870 */
6871 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6872 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6873 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6874
6875 /* Indicate to hardware the Address is Valid. */
6876 rar_high |= E1000_RAH_AV;
6877
6878 if (hw->mac.type == e1000_82575)
6879 rar_high |= E1000_RAH_POOL_1 * qsel;
6880 else
6881 rar_high |= E1000_RAH_POOL_1 << qsel;
6882
6883 wr32(E1000_RAL(index), rar_low);
6884 wrfl();
6885 wr32(E1000_RAH(index), rar_high);
6886 wrfl();
6887}
6888
4ae196df
AD		 6889static int igb_set_vf_mac(struct igb_adapter *adapter,
6890 int vf, unsigned char *mac_addr)
6891{
6892 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6893 /* VF MAC addresses start at end of receive addresses and moves
6894 * torwards the first, as a result a collision should not be possible */
6895 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6896
37680117 6897 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6898
26ad9178 6899 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6900
6901 return 0;
6902}
6903
8151d294
WM		 6904static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6905{
6906 struct igb_adapter *adapter = netdev_priv(netdev);
6907 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6908 return -EINVAL;
6909 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6910 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6911 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6912 " change effective.");
6913 if (test_bit(__IGB_DOWN, &adapter->state)) {
6914 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6915 " but the PF device is not up.\n");
6916 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6917 " attempting to use the VF device.\n");
6918 }
6919 return igb_set_vf_mac(adapter, vf, mac);
6920}
6921
17dc566c
LL		 6922static int igb_link_mbps(int internal_link_speed)
6923{
6924 switch (internal_link_speed) {
6925 case SPEED_100:
6926 return 100;
6927 case SPEED_1000:
6928 return 1000;
6929 default:
6930 return 0;
6931 }
6932}
6933
6934static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6935 int link_speed)
6936{
6937 int rf_dec, rf_int;
6938 u32 bcnrc_val;
6939
6940 if (tx_rate != 0) {
6941 /* Calculate the rate factor values to set */
6942 rf_int = link_speed / tx_rate;
6943 rf_dec = (link_speed - (rf_int * tx_rate));
6944 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6945
6946 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6947 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6948 E1000_RTTBCNRC_RF_INT_MASK);
6949 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6950 } else {
6951 bcnrc_val = 0;
6952 }
6953
6954 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
6955 wr32(E1000_RTTBCNRC, bcnrc_val);
6956}
6957
6958static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6959{
6960 int actual_link_speed, i;
6961 bool reset_rate = false;
6962
6963 /* VF TX rate limit was not set or not supported */
6964 if ((adapter->vf_rate_link_speed == 0) ||
6965 (adapter->hw.mac.type != e1000_82576))
6966 return;
6967
6968 actual_link_speed = igb_link_mbps(adapter->link_speed);
6969 if (actual_link_speed != adapter->vf_rate_link_speed) {
6970 reset_rate = true;
6971 adapter->vf_rate_link_speed = 0;
6972 dev_info(&adapter->pdev->dev,
6973 "Link speed has been changed. VF Transmit "
6974 "rate is disabled\n");
6975 }
6976
6977 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6978 if (reset_rate)
6979 adapter->vf_data[i].tx_rate = 0;
6980
6981 igb_set_vf_rate_limit(&adapter->hw, i,
6982 adapter->vf_data[i].tx_rate,
6983 actual_link_speed);
6984 }
6985}
6986
8151d294
WM		 6987static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6988{
17dc566c
LL		 6989 struct igb_adapter *adapter = netdev_priv(netdev);
6990 struct e1000_hw *hw = &adapter->hw;
6991 int actual_link_speed;
6992
6993 if (hw->mac.type != e1000_82576)
6994 return -EOPNOTSUPP;
6995
6996 actual_link_speed = igb_link_mbps(adapter->link_speed);
6997 if ((vf >= adapter->vfs_allocated_count) ||
6998 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6999 (tx_rate < 0) || (tx_rate > actual_link_speed))
7000 return -EINVAL;
7001
7002 adapter->vf_rate_link_speed = actual_link_speed;
7003 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7004 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7005
7006 return 0;
8151d294
WM		 7007}
7008
7009static int igb_ndo_get_vf_config(struct net_device *netdev,
7010 int vf, struct ifla_vf_info *ivi)
7011{
7012 struct igb_adapter *adapter = netdev_priv(netdev);
7013 if (vf >= adapter->vfs_allocated_count)
7014 return -EINVAL;
7015 ivi->vf = vf;
7016 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7017 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7018 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7019 ivi->qos = adapter->vf_data[vf].pf_qos;
7020 return 0;
7021}
7022
4ae196df
AD		 7023static void igb_vmm_control(struct igb_adapter *adapter)
7024{
7025 struct e1000_hw *hw = &adapter->hw;
10d8e907 7026 u32 reg;
4ae196df 7027
52a1dd4d
AD		 7028 switch (hw->mac.type) {
7029 case e1000_82575:
7030 default:
7031 /* replication is not supported for 82575 */
4ae196df 7032 return;
52a1dd4d
AD		 7033 case e1000_82576:
7034 /* notify HW that the MAC is adding vlan tags */
7035 reg = rd32(E1000_DTXCTL);
7036 reg |= E1000_DTXCTL_VLAN_ADDED;
7037 wr32(E1000_DTXCTL, reg);
7038 case e1000_82580:
7039 /* enable replication vlan tag stripping */
7040 reg = rd32(E1000_RPLOLR);
7041 reg |= E1000_RPLOLR_STRVLAN;
7042 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7043 case e1000_i350:
7044 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7045 break;
7046 }
10d8e907 7047
d4960307
AD		 7048 if (adapter->vfs_allocated_count) {
7049 igb_vmdq_set_loopback_pf(hw, true);
7050 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7051 igb_vmdq_set_anti_spoofing_pf(hw, true,
7052 adapter->vfs_allocated_count);
d4960307
AD		 7053 } else {
7054 igb_vmdq_set_loopback_pf(hw, false);
7055 igb_vmdq_set_replication_pf(hw, false);
7056 }
4ae196df
AD		 7057}
7058
b6e0c419
CW		 7059static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7060{
7061 struct e1000_hw *hw = &adapter->hw;
7062 u32 dmac_thr;
7063 u16 hwm;
7064
7065 if (hw->mac.type > e1000_82580) {
7066 if (adapter->flags & IGB_FLAG_DMAC) {
7067 u32 reg;
7068
7069 /* force threshold to 0. */
7070 wr32(E1000_DMCTXTH, 0);
7071
7072 /*
e8c626e9
MV		 7073 * DMA Coalescing high water mark needs to be greater
7074 * than the Rx threshold. Set hwm to PBA - max frame
7075 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7076 */
e8c626e9
MV		 7077 hwm = 64 * pba - adapter->max_frame_size / 16;
7078 if (hwm < 64 * (pba - 6))
7079 hwm = 64 * (pba - 6);
7080 reg = rd32(E1000_FCRTC);
7081 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7082 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7083 & E1000_FCRTC_RTH_COAL_MASK);
7084 wr32(E1000_FCRTC, reg);
7085
7086 /*
7087 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7088 * frame size, capping it at PBA - 10KB.
7089 */
7090 dmac_thr = pba - adapter->max_frame_size / 512;
7091 if (dmac_thr < pba - 10)
7092 dmac_thr = pba - 10;
b6e0c419
CW		 7093 reg = rd32(E1000_DMACR);
7094 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7095 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7096 & E1000_DMACR_DMACTHR_MASK);
7097
7098 /* transition to L0x or L1 if available..*/
7099 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7100
7101 /* watchdog timer= +-1000 usec in 32usec intervals */
7102 reg |= (1000 >> 5);
7103 wr32(E1000_DMACR, reg);
7104
7105 /*
7106 * no lower threshold to disable
7107 * coalescing(smart fifb)-UTRESH=0
7108 */
7109 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7110
7111 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7112
7113 wr32(E1000_DMCTLX, reg);
7114
7115 /*
7116 * free space in tx packet buffer to wake from
7117 * DMA coal
7118 */
7119 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7120 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7121
7122 /*
7123 * make low power state decision controlled
7124 * by DMA coal
7125 */
7126 reg = rd32(E1000_PCIEMISC);
7127 reg &= ~E1000_PCIEMISC_LX_DECISION;
7128 wr32(E1000_PCIEMISC, reg);
7129 } /* endif adapter->dmac is not disabled */
7130 } else if (hw->mac.type == e1000_82580) {
7131 u32 reg = rd32(E1000_PCIEMISC);
7132 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7133 wr32(E1000_DMACR, 0);
7134 }
7135}
7136
9d5c8243 7137/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)