Commit | Line | Data |
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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
6e861326 | 4 | Copyright(c) 2007-2012 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
876d2d6f JK |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
9d5c8243 AK |
30 | #include <linux/module.h> |
31 | #include <linux/types.h> | |
32 | #include <linux/init.h> | |
b2cb09b1 | 33 | #include <linux/bitops.h> |
9d5c8243 AK |
34 | #include <linux/vmalloc.h> |
35 | #include <linux/pagemap.h> | |
36 | #include <linux/netdevice.h> | |
9d5c8243 | 37 | #include <linux/ipv6.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
9d5c8243 AK |
39 | #include <net/checksum.h> |
40 | #include <net/ip6_checksum.h> | |
c6cb090b | 41 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
42 | #include <linux/mii.h> |
43 | #include <linux/ethtool.h> | |
01789349 | 44 | #include <linux/if.h> |
9d5c8243 AK |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/pci.h> | |
c54106bb | 47 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
48 | #include <linux/delay.h> |
49 | #include <linux/interrupt.h> | |
7d13a7d0 AD |
50 | #include <linux/ip.h> |
51 | #include <linux/tcp.h> | |
52 | #include <linux/sctp.h> | |
9d5c8243 | 53 | #include <linux/if_ether.h> |
40a914fa | 54 | #include <linux/aer.h> |
70c71606 | 55 | #include <linux/prefetch.h> |
749ab2cd | 56 | #include <linux/pm_runtime.h> |
421e02f0 | 57 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
58 | #include <linux/dca.h> |
59 | #endif | |
441fc6fd | 60 | #include <linux/i2c.h> |
9d5c8243 AK |
61 | #include "igb.h" |
62 | ||
200e5fd5 | 63 | #define MAJ 4 |
6699938b CW |
64 | #define MIN 1 |
65 | #define BUILD 2 | |
0d1fe82d | 66 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
929dd047 | 67 | __stringify(BUILD) "-k" |
9d5c8243 AK |
68 | char igb_driver_name[] = "igb"; |
69 | char igb_driver_version[] = DRV_VERSION; | |
70 | static const char igb_driver_string[] = | |
71 | "Intel(R) Gigabit Ethernet Network Driver"; | |
6e861326 | 72 | static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; |
9d5c8243 | 73 | |
9d5c8243 AK |
74 | static const struct e1000_info *igb_info_tbl[] = { |
75 | [board_82575] = &e1000_82575_info, | |
76 | }; | |
77 | ||
a3aa1884 | 78 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
f96a8a0b CW |
79 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, |
80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, | |
81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, | |
82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, | |
83 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, | |
d2ba2ed8 AD |
84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
85 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, | |
86 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, | |
87 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, | |
55cac248 AD |
88 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
89 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
6493d24f | 90 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, |
55cac248 AD |
91 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, |
92 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
93 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
308fb39a JG |
94 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, |
95 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, | |
1b5dda33 GJ |
96 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, |
97 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, | |
2d064c06 | 98 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 99 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 100 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
101 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
102 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 103 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
b894fa26 | 104 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
c8ea5ea9 | 105 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
106 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
107 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
108 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
109 | /* required last entry */ | |
110 | {0, } | |
111 | }; | |
112 | ||
113 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
114 | ||
115 | void igb_reset(struct igb_adapter *); | |
116 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
117 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
118 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
119 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 120 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 | 121 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
9f9a12f8 | 122 | static void igb_remove(struct pci_dev *pdev); |
9d5c8243 AK |
123 | static int igb_sw_init(struct igb_adapter *); |
124 | static int igb_open(struct net_device *); | |
125 | static int igb_close(struct net_device *); | |
53c7d064 | 126 | static void igb_configure(struct igb_adapter *); |
9d5c8243 AK |
127 | static void igb_configure_tx(struct igb_adapter *); |
128 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
129 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
130 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
131 | static void igb_clean_tx_ring(struct igb_ring *); |
132 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 133 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
134 | static void igb_update_phy_info(unsigned long); |
135 | static void igb_watchdog(unsigned long); | |
136 | static void igb_watchdog_task(struct work_struct *); | |
cd392f5c | 137 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); |
12dcd86b ED |
138 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, |
139 | struct rtnl_link_stats64 *stats); | |
9d5c8243 AK |
140 | static int igb_change_mtu(struct net_device *, int); |
141 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 142 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
143 | static irqreturn_t igb_intr(int irq, void *); |
144 | static irqreturn_t igb_intr_msi(int irq, void *); | |
145 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 146 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 147 | #ifdef CONFIG_IGB_DCA |
047e0030 | 148 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 149 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 150 | #endif /* CONFIG_IGB_DCA */ |
661086df | 151 | static int igb_poll(struct napi_struct *, int); |
13fde97a | 152 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
cd392f5c | 153 | static bool igb_clean_rx_irq(struct igb_q_vector *, int); |
9d5c8243 AK |
154 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
155 | static void igb_tx_timeout(struct net_device *); | |
156 | static void igb_reset_task(struct work_struct *); | |
c8f44aff | 157 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); |
8e586137 JP |
158 | static int igb_vlan_rx_add_vid(struct net_device *, u16); |
159 | static int igb_vlan_rx_kill_vid(struct net_device *, u16); | |
9d5c8243 | 160 | static void igb_restore_vlan(struct igb_adapter *); |
26ad9178 | 161 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
162 | static void igb_ping_all_vfs(struct igb_adapter *); |
163 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 164 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 165 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 166 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
8151d294 WM |
167 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
168 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
169 | int vf, u16 vlan, u8 qos); | |
170 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); | |
171 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, | |
172 | struct ifla_vf_info *ivi); | |
17dc566c | 173 | static void igb_check_vf_rate_limit(struct igb_adapter *); |
46a01698 RL |
174 | |
175 | #ifdef CONFIG_PCI_IOV | |
0224d663 | 176 | static int igb_vf_configure(struct igb_adapter *adapter, int vf); |
f557147c | 177 | static bool igb_vfs_are_assigned(struct igb_adapter *adapter); |
46a01698 | 178 | #endif |
9d5c8243 | 179 | |
9d5c8243 | 180 | #ifdef CONFIG_PM |
d9dd966d | 181 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 182 | static int igb_suspend(struct device *); |
d9dd966d | 183 | #endif |
749ab2cd YZ |
184 | static int igb_resume(struct device *); |
185 | #ifdef CONFIG_PM_RUNTIME | |
186 | static int igb_runtime_suspend(struct device *dev); | |
187 | static int igb_runtime_resume(struct device *dev); | |
188 | static int igb_runtime_idle(struct device *dev); | |
189 | #endif | |
190 | static const struct dev_pm_ops igb_pm_ops = { | |
191 | SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) | |
192 | SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, | |
193 | igb_runtime_idle) | |
194 | }; | |
9d5c8243 AK |
195 | #endif |
196 | static void igb_shutdown(struct pci_dev *); | |
fa44f2f1 | 197 | static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); |
421e02f0 | 198 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
199 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
200 | static struct notifier_block dca_notifier = { | |
201 | .notifier_call = igb_notify_dca, | |
202 | .next = NULL, | |
203 | .priority = 0 | |
204 | }; | |
205 | #endif | |
9d5c8243 AK |
206 | #ifdef CONFIG_NET_POLL_CONTROLLER |
207 | /* for netdump / net console */ | |
208 | static void igb_netpoll(struct net_device *); | |
209 | #endif | |
37680117 | 210 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
211 | static unsigned int max_vfs = 0; |
212 | module_param(max_vfs, uint, 0); | |
213 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
214 | "per physical function"); | |
215 | #endif /* CONFIG_PCI_IOV */ | |
216 | ||
9d5c8243 AK |
217 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
218 | pci_channel_state_t); | |
219 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
220 | static void igb_io_resume(struct pci_dev *); | |
221 | ||
3646f0e5 | 222 | static const struct pci_error_handlers igb_err_handler = { |
9d5c8243 AK |
223 | .error_detected = igb_io_error_detected, |
224 | .slot_reset = igb_io_slot_reset, | |
225 | .resume = igb_io_resume, | |
226 | }; | |
227 | ||
b6e0c419 | 228 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); |
9d5c8243 AK |
229 | |
230 | static struct pci_driver igb_driver = { | |
231 | .name = igb_driver_name, | |
232 | .id_table = igb_pci_tbl, | |
233 | .probe = igb_probe, | |
9f9a12f8 | 234 | .remove = igb_remove, |
9d5c8243 | 235 | #ifdef CONFIG_PM |
749ab2cd | 236 | .driver.pm = &igb_pm_ops, |
9d5c8243 AK |
237 | #endif |
238 | .shutdown = igb_shutdown, | |
fa44f2f1 | 239 | .sriov_configure = igb_pci_sriov_configure, |
9d5c8243 AK |
240 | .err_handler = &igb_err_handler |
241 | }; | |
242 | ||
243 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
244 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
245 | MODULE_LICENSE("GPL"); | |
246 | MODULE_VERSION(DRV_VERSION); | |
247 | ||
b3f4d599 | 248 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
249 | static int debug = -1; | |
250 | module_param(debug, int, 0); | |
251 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
252 | ||
c97ec42a TI |
253 | struct igb_reg_info { |
254 | u32 ofs; | |
255 | char *name; | |
256 | }; | |
257 | ||
258 | static const struct igb_reg_info igb_reg_info_tbl[] = { | |
259 | ||
260 | /* General Registers */ | |
261 | {E1000_CTRL, "CTRL"}, | |
262 | {E1000_STATUS, "STATUS"}, | |
263 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
264 | ||
265 | /* Interrupt Registers */ | |
266 | {E1000_ICR, "ICR"}, | |
267 | ||
268 | /* RX Registers */ | |
269 | {E1000_RCTL, "RCTL"}, | |
270 | {E1000_RDLEN(0), "RDLEN"}, | |
271 | {E1000_RDH(0), "RDH"}, | |
272 | {E1000_RDT(0), "RDT"}, | |
273 | {E1000_RXDCTL(0), "RXDCTL"}, | |
274 | {E1000_RDBAL(0), "RDBAL"}, | |
275 | {E1000_RDBAH(0), "RDBAH"}, | |
276 | ||
277 | /* TX Registers */ | |
278 | {E1000_TCTL, "TCTL"}, | |
279 | {E1000_TDBAL(0), "TDBAL"}, | |
280 | {E1000_TDBAH(0), "TDBAH"}, | |
281 | {E1000_TDLEN(0), "TDLEN"}, | |
282 | {E1000_TDH(0), "TDH"}, | |
283 | {E1000_TDT(0), "TDT"}, | |
284 | {E1000_TXDCTL(0), "TXDCTL"}, | |
285 | {E1000_TDFH, "TDFH"}, | |
286 | {E1000_TDFT, "TDFT"}, | |
287 | {E1000_TDFHS, "TDFHS"}, | |
288 | {E1000_TDFPC, "TDFPC"}, | |
289 | ||
290 | /* List Terminator */ | |
291 | {} | |
292 | }; | |
293 | ||
294 | /* | |
295 | * igb_regdump - register printout routine | |
296 | */ | |
297 | static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) | |
298 | { | |
299 | int n = 0; | |
300 | char rname[16]; | |
301 | u32 regs[8]; | |
302 | ||
303 | switch (reginfo->ofs) { | |
304 | case E1000_RDLEN(0): | |
305 | for (n = 0; n < 4; n++) | |
306 | regs[n] = rd32(E1000_RDLEN(n)); | |
307 | break; | |
308 | case E1000_RDH(0): | |
309 | for (n = 0; n < 4; n++) | |
310 | regs[n] = rd32(E1000_RDH(n)); | |
311 | break; | |
312 | case E1000_RDT(0): | |
313 | for (n = 0; n < 4; n++) | |
314 | regs[n] = rd32(E1000_RDT(n)); | |
315 | break; | |
316 | case E1000_RXDCTL(0): | |
317 | for (n = 0; n < 4; n++) | |
318 | regs[n] = rd32(E1000_RXDCTL(n)); | |
319 | break; | |
320 | case E1000_RDBAL(0): | |
321 | for (n = 0; n < 4; n++) | |
322 | regs[n] = rd32(E1000_RDBAL(n)); | |
323 | break; | |
324 | case E1000_RDBAH(0): | |
325 | for (n = 0; n < 4; n++) | |
326 | regs[n] = rd32(E1000_RDBAH(n)); | |
327 | break; | |
328 | case E1000_TDBAL(0): | |
329 | for (n = 0; n < 4; n++) | |
330 | regs[n] = rd32(E1000_RDBAL(n)); | |
331 | break; | |
332 | case E1000_TDBAH(0): | |
333 | for (n = 0; n < 4; n++) | |
334 | regs[n] = rd32(E1000_TDBAH(n)); | |
335 | break; | |
336 | case E1000_TDLEN(0): | |
337 | for (n = 0; n < 4; n++) | |
338 | regs[n] = rd32(E1000_TDLEN(n)); | |
339 | break; | |
340 | case E1000_TDH(0): | |
341 | for (n = 0; n < 4; n++) | |
342 | regs[n] = rd32(E1000_TDH(n)); | |
343 | break; | |
344 | case E1000_TDT(0): | |
345 | for (n = 0; n < 4; n++) | |
346 | regs[n] = rd32(E1000_TDT(n)); | |
347 | break; | |
348 | case E1000_TXDCTL(0): | |
349 | for (n = 0; n < 4; n++) | |
350 | regs[n] = rd32(E1000_TXDCTL(n)); | |
351 | break; | |
352 | default: | |
876d2d6f | 353 | pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); |
c97ec42a TI |
354 | return; |
355 | } | |
356 | ||
357 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); | |
876d2d6f JK |
358 | pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], |
359 | regs[2], regs[3]); | |
c97ec42a TI |
360 | } |
361 | ||
362 | /* | |
363 | * igb_dump - Print registers, tx-rings and rx-rings | |
364 | */ | |
365 | static void igb_dump(struct igb_adapter *adapter) | |
366 | { | |
367 | struct net_device *netdev = adapter->netdev; | |
368 | struct e1000_hw *hw = &adapter->hw; | |
369 | struct igb_reg_info *reginfo; | |
c97ec42a TI |
370 | struct igb_ring *tx_ring; |
371 | union e1000_adv_tx_desc *tx_desc; | |
372 | struct my_u0 { u64 a; u64 b; } *u0; | |
c97ec42a TI |
373 | struct igb_ring *rx_ring; |
374 | union e1000_adv_rx_desc *rx_desc; | |
375 | u32 staterr; | |
6ad4edfc | 376 | u16 i, n; |
c97ec42a TI |
377 | |
378 | if (!netif_msg_hw(adapter)) | |
379 | return; | |
380 | ||
381 | /* Print netdevice Info */ | |
382 | if (netdev) { | |
383 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
876d2d6f JK |
384 | pr_info("Device Name state trans_start " |
385 | "last_rx\n"); | |
386 | pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, | |
387 | netdev->state, netdev->trans_start, netdev->last_rx); | |
c97ec42a TI |
388 | } |
389 | ||
390 | /* Print Registers */ | |
391 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
876d2d6f | 392 | pr_info(" Register Name Value\n"); |
c97ec42a TI |
393 | for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; |
394 | reginfo->name; reginfo++) { | |
395 | igb_regdump(hw, reginfo); | |
396 | } | |
397 | ||
398 | /* Print TX Ring Summary */ | |
399 | if (!netdev || !netif_running(netdev)) | |
400 | goto exit; | |
401 | ||
402 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
876d2d6f | 403 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
c97ec42a | 404 | for (n = 0; n < adapter->num_tx_queues; n++) { |
06034649 | 405 | struct igb_tx_buffer *buffer_info; |
c97ec42a | 406 | tx_ring = adapter->tx_ring[n]; |
06034649 | 407 | buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
876d2d6f JK |
408 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
409 | n, tx_ring->next_to_use, tx_ring->next_to_clean, | |
c9f14bf3 AD |
410 | (u64)dma_unmap_addr(buffer_info, dma), |
411 | dma_unmap_len(buffer_info, len), | |
876d2d6f JK |
412 | buffer_info->next_to_watch, |
413 | (u64)buffer_info->time_stamp); | |
c97ec42a TI |
414 | } |
415 | ||
416 | /* Print TX Rings */ | |
417 | if (!netif_msg_tx_done(adapter)) | |
418 | goto rx_ring_summary; | |
419 | ||
420 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
421 | ||
422 | /* Transmit Descriptor Formats | |
423 | * | |
424 | * Advanced Transmit Descriptor | |
425 | * +--------------------------------------------------------------+ | |
426 | * 0 | Buffer Address [63:0] | | |
427 | * +--------------------------------------------------------------+ | |
428 | * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | | |
429 | * +--------------------------------------------------------------+ | |
430 | * 63 46 45 40 39 38 36 35 32 31 24 15 0 | |
431 | */ | |
432 | ||
433 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
434 | tx_ring = adapter->tx_ring[n]; | |
876d2d6f JK |
435 | pr_info("------------------------------------\n"); |
436 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
437 | pr_info("------------------------------------\n"); | |
438 | pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " | |
439 | "[bi->dma ] leng ntw timestamp " | |
440 | "bi->skb\n"); | |
c97ec42a TI |
441 | |
442 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
876d2d6f | 443 | const char *next_desc; |
06034649 | 444 | struct igb_tx_buffer *buffer_info; |
60136906 | 445 | tx_desc = IGB_TX_DESC(tx_ring, i); |
06034649 | 446 | buffer_info = &tx_ring->tx_buffer_info[i]; |
c97ec42a | 447 | u0 = (struct my_u0 *)tx_desc; |
876d2d6f JK |
448 | if (i == tx_ring->next_to_use && |
449 | i == tx_ring->next_to_clean) | |
450 | next_desc = " NTC/U"; | |
451 | else if (i == tx_ring->next_to_use) | |
452 | next_desc = " NTU"; | |
453 | else if (i == tx_ring->next_to_clean) | |
454 | next_desc = " NTC"; | |
455 | else | |
456 | next_desc = ""; | |
457 | ||
458 | pr_info("T [0x%03X] %016llX %016llX %016llX" | |
459 | " %04X %p %016llX %p%s\n", i, | |
c97ec42a TI |
460 | le64_to_cpu(u0->a), |
461 | le64_to_cpu(u0->b), | |
c9f14bf3 AD |
462 | (u64)dma_unmap_addr(buffer_info, dma), |
463 | dma_unmap_len(buffer_info, len), | |
c97ec42a TI |
464 | buffer_info->next_to_watch, |
465 | (u64)buffer_info->time_stamp, | |
876d2d6f | 466 | buffer_info->skb, next_desc); |
c97ec42a | 467 | |
b669588a | 468 | if (netif_msg_pktdata(adapter) && buffer_info->skb) |
c97ec42a TI |
469 | print_hex_dump(KERN_INFO, "", |
470 | DUMP_PREFIX_ADDRESS, | |
b669588a | 471 | 16, 1, buffer_info->skb->data, |
c9f14bf3 AD |
472 | dma_unmap_len(buffer_info, len), |
473 | true); | |
c97ec42a TI |
474 | } |
475 | } | |
476 | ||
477 | /* Print RX Rings Summary */ | |
478 | rx_ring_summary: | |
479 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
876d2d6f | 480 | pr_info("Queue [NTU] [NTC]\n"); |
c97ec42a TI |
481 | for (n = 0; n < adapter->num_rx_queues; n++) { |
482 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
483 | pr_info(" %5d %5X %5X\n", |
484 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
c97ec42a TI |
485 | } |
486 | ||
487 | /* Print RX Rings */ | |
488 | if (!netif_msg_rx_status(adapter)) | |
489 | goto exit; | |
490 | ||
491 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
492 | ||
493 | /* Advanced Receive Descriptor (Read) Format | |
494 | * 63 1 0 | |
495 | * +-----------------------------------------------------+ | |
496 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
497 | * +----------------------------------------------+------+ | |
498 | * 8 | Header Buffer Address [63:1] | DD | | |
499 | * +-----------------------------------------------------+ | |
500 | * | |
501 | * | |
502 | * Advanced Receive Descriptor (Write-Back) Format | |
503 | * | |
504 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
505 | * +------------------------------------------------------+ | |
506 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
507 | * | Checksum Ident | | | | Type | Type | | |
508 | * +------------------------------------------------------+ | |
509 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
510 | * +------------------------------------------------------+ | |
511 | * 63 48 47 32 31 20 19 0 | |
512 | */ | |
513 | ||
514 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
515 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
516 | pr_info("------------------------------------\n"); |
517 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
518 | pr_info("------------------------------------\n"); | |
519 | pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " | |
520 | "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); | |
521 | pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" | |
522 | "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); | |
c97ec42a TI |
523 | |
524 | for (i = 0; i < rx_ring->count; i++) { | |
876d2d6f | 525 | const char *next_desc; |
06034649 AD |
526 | struct igb_rx_buffer *buffer_info; |
527 | buffer_info = &rx_ring->rx_buffer_info[i]; | |
60136906 | 528 | rx_desc = IGB_RX_DESC(rx_ring, i); |
c97ec42a TI |
529 | u0 = (struct my_u0 *)rx_desc; |
530 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
876d2d6f JK |
531 | |
532 | if (i == rx_ring->next_to_use) | |
533 | next_desc = " NTU"; | |
534 | else if (i == rx_ring->next_to_clean) | |
535 | next_desc = " NTC"; | |
536 | else | |
537 | next_desc = ""; | |
538 | ||
c97ec42a TI |
539 | if (staterr & E1000_RXD_STAT_DD) { |
540 | /* Descriptor Done */ | |
1a1c225b AD |
541 | pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", |
542 | "RWB", i, | |
c97ec42a TI |
543 | le64_to_cpu(u0->a), |
544 | le64_to_cpu(u0->b), | |
1a1c225b | 545 | next_desc); |
c97ec42a | 546 | } else { |
1a1c225b AD |
547 | pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", |
548 | "R ", i, | |
c97ec42a TI |
549 | le64_to_cpu(u0->a), |
550 | le64_to_cpu(u0->b), | |
551 | (u64)buffer_info->dma, | |
1a1c225b | 552 | next_desc); |
c97ec42a | 553 | |
b669588a | 554 | if (netif_msg_pktdata(adapter) && |
1a1c225b | 555 | buffer_info->dma && buffer_info->page) { |
44390ca6 AD |
556 | print_hex_dump(KERN_INFO, "", |
557 | DUMP_PREFIX_ADDRESS, | |
558 | 16, 1, | |
b669588a ET |
559 | page_address(buffer_info->page) + |
560 | buffer_info->page_offset, | |
de78d1f9 | 561 | IGB_RX_BUFSZ, true); |
c97ec42a TI |
562 | } |
563 | } | |
c97ec42a TI |
564 | } |
565 | } | |
566 | ||
567 | exit: | |
568 | return; | |
569 | } | |
570 | ||
441fc6fd CW |
571 | /* igb_get_i2c_data - Reads the I2C SDA data bit |
572 | * @hw: pointer to hardware structure | |
573 | * @i2cctl: Current value of I2CCTL register | |
574 | * | |
575 | * Returns the I2C data bit value | |
576 | */ | |
577 | static int igb_get_i2c_data(void *data) | |
578 | { | |
579 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
580 | struct e1000_hw *hw = &adapter->hw; | |
581 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
582 | ||
583 | return ((i2cctl & E1000_I2C_DATA_IN) != 0); | |
584 | } | |
585 | ||
586 | /* igb_set_i2c_data - Sets the I2C data bit | |
587 | * @data: pointer to hardware structure | |
588 | * @state: I2C data value (0 or 1) to set | |
589 | * | |
590 | * Sets the I2C data bit | |
591 | */ | |
592 | static void igb_set_i2c_data(void *data, int state) | |
593 | { | |
594 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
595 | struct e1000_hw *hw = &adapter->hw; | |
596 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
597 | ||
598 | if (state) | |
599 | i2cctl |= E1000_I2C_DATA_OUT; | |
600 | else | |
601 | i2cctl &= ~E1000_I2C_DATA_OUT; | |
602 | ||
603 | i2cctl &= ~E1000_I2C_DATA_OE_N; | |
604 | i2cctl |= E1000_I2C_CLK_OE_N; | |
605 | wr32(E1000_I2CPARAMS, i2cctl); | |
606 | wrfl(); | |
607 | ||
608 | } | |
609 | ||
610 | /* igb_set_i2c_clk - Sets the I2C SCL clock | |
611 | * @data: pointer to hardware structure | |
612 | * @state: state to set clock | |
613 | * | |
614 | * Sets the I2C clock line to state | |
615 | */ | |
616 | static void igb_set_i2c_clk(void *data, int state) | |
617 | { | |
618 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
619 | struct e1000_hw *hw = &adapter->hw; | |
620 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
621 | ||
622 | if (state) { | |
623 | i2cctl |= E1000_I2C_CLK_OUT; | |
624 | i2cctl &= ~E1000_I2C_CLK_OE_N; | |
625 | } else { | |
626 | i2cctl &= ~E1000_I2C_CLK_OUT; | |
627 | i2cctl &= ~E1000_I2C_CLK_OE_N; | |
628 | } | |
629 | wr32(E1000_I2CPARAMS, i2cctl); | |
630 | wrfl(); | |
631 | } | |
632 | ||
633 | /* igb_get_i2c_clk - Gets the I2C SCL clock state | |
634 | * @data: pointer to hardware structure | |
635 | * | |
636 | * Gets the I2C clock state | |
637 | */ | |
638 | static int igb_get_i2c_clk(void *data) | |
639 | { | |
640 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
641 | struct e1000_hw *hw = &adapter->hw; | |
642 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
643 | ||
644 | return ((i2cctl & E1000_I2C_CLK_IN) != 0); | |
645 | } | |
646 | ||
647 | static const struct i2c_algo_bit_data igb_i2c_algo = { | |
648 | .setsda = igb_set_i2c_data, | |
649 | .setscl = igb_set_i2c_clk, | |
650 | .getsda = igb_get_i2c_data, | |
651 | .getscl = igb_get_i2c_clk, | |
652 | .udelay = 5, | |
653 | .timeout = 20, | |
654 | }; | |
655 | ||
9d5c8243 | 656 | /** |
c041076a | 657 | * igb_get_hw_dev - return device |
9d5c8243 AK |
658 | * used by hardware layer to print debugging information |
659 | **/ | |
c041076a | 660 | struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
9d5c8243 AK |
661 | { |
662 | struct igb_adapter *adapter = hw->back; | |
c041076a | 663 | return adapter->netdev; |
9d5c8243 | 664 | } |
38c845c7 | 665 | |
9d5c8243 AK |
666 | /** |
667 | * igb_init_module - Driver Registration Routine | |
668 | * | |
669 | * igb_init_module is the first routine called when the driver is | |
670 | * loaded. All it does is register with the PCI subsystem. | |
671 | **/ | |
672 | static int __init igb_init_module(void) | |
673 | { | |
674 | int ret; | |
876d2d6f | 675 | pr_info("%s - version %s\n", |
9d5c8243 AK |
676 | igb_driver_string, igb_driver_version); |
677 | ||
876d2d6f | 678 | pr_info("%s\n", igb_copyright); |
9d5c8243 | 679 | |
421e02f0 | 680 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
681 | dca_register_notify(&dca_notifier); |
682 | #endif | |
bbd98fe4 | 683 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
684 | return ret; |
685 | } | |
686 | ||
687 | module_init(igb_init_module); | |
688 | ||
689 | /** | |
690 | * igb_exit_module - Driver Exit Cleanup Routine | |
691 | * | |
692 | * igb_exit_module is called just before the driver is removed | |
693 | * from memory. | |
694 | **/ | |
695 | static void __exit igb_exit_module(void) | |
696 | { | |
421e02f0 | 697 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
698 | dca_unregister_notify(&dca_notifier); |
699 | #endif | |
9d5c8243 AK |
700 | pci_unregister_driver(&igb_driver); |
701 | } | |
702 | ||
703 | module_exit(igb_exit_module); | |
704 | ||
26bc19ec AD |
705 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
706 | /** | |
707 | * igb_cache_ring_register - Descriptor ring to register mapping | |
708 | * @adapter: board private structure to initialize | |
709 | * | |
710 | * Once we know the feature-set enabled for the device, we'll cache | |
711 | * the register offset the descriptor ring is assigned to. | |
712 | **/ | |
713 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
714 | { | |
ee1b9f06 | 715 | int i = 0, j = 0; |
047e0030 | 716 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
717 | |
718 | switch (adapter->hw.mac.type) { | |
719 | case e1000_82576: | |
720 | /* The queues are allocated for virtualization such that VF 0 | |
721 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
722 | * In order to avoid collision we start at the first free queue | |
723 | * and continue consuming queues in the same sequence | |
724 | */ | |
ee1b9f06 | 725 | if (adapter->vfs_allocated_count) { |
a99955fc | 726 | for (; i < adapter->rss_queues; i++) |
3025a446 AD |
727 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
728 | Q_IDX_82576(i); | |
ee1b9f06 | 729 | } |
26bc19ec | 730 | case e1000_82575: |
55cac248 | 731 | case e1000_82580: |
d2ba2ed8 | 732 | case e1000_i350: |
f96a8a0b CW |
733 | case e1000_i210: |
734 | case e1000_i211: | |
26bc19ec | 735 | default: |
ee1b9f06 | 736 | for (; i < adapter->num_rx_queues; i++) |
3025a446 | 737 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
ee1b9f06 | 738 | for (; j < adapter->num_tx_queues; j++) |
3025a446 | 739 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
26bc19ec AD |
740 | break; |
741 | } | |
742 | } | |
743 | ||
4be000c8 AD |
744 | /** |
745 | * igb_write_ivar - configure ivar for given MSI-X vector | |
746 | * @hw: pointer to the HW structure | |
747 | * @msix_vector: vector number we are allocating to a given ring | |
748 | * @index: row index of IVAR register to write within IVAR table | |
749 | * @offset: column offset of in IVAR, should be multiple of 8 | |
750 | * | |
751 | * This function is intended to handle the writing of the IVAR register | |
752 | * for adapters 82576 and newer. The IVAR table consists of 2 columns, | |
753 | * each containing an cause allocation for an Rx and Tx ring, and a | |
754 | * variable number of rows depending on the number of queues supported. | |
755 | **/ | |
756 | static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, | |
757 | int index, int offset) | |
758 | { | |
759 | u32 ivar = array_rd32(E1000_IVAR0, index); | |
760 | ||
761 | /* clear any bits that are currently set */ | |
762 | ivar &= ~((u32)0xFF << offset); | |
763 | ||
764 | /* write vector and valid bit */ | |
765 | ivar |= (msix_vector | E1000_IVAR_VALID) << offset; | |
766 | ||
767 | array_wr32(E1000_IVAR0, index, ivar); | |
768 | } | |
769 | ||
9d5c8243 | 770 | #define IGB_N0_QUEUE -1 |
047e0030 | 771 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 | 772 | { |
047e0030 | 773 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 774 | struct e1000_hw *hw = &adapter->hw; |
047e0030 AD |
775 | int rx_queue = IGB_N0_QUEUE; |
776 | int tx_queue = IGB_N0_QUEUE; | |
4be000c8 | 777 | u32 msixbm = 0; |
047e0030 | 778 | |
0ba82994 AD |
779 | if (q_vector->rx.ring) |
780 | rx_queue = q_vector->rx.ring->reg_idx; | |
781 | if (q_vector->tx.ring) | |
782 | tx_queue = q_vector->tx.ring->reg_idx; | |
2d064c06 AD |
783 | |
784 | switch (hw->mac.type) { | |
785 | case e1000_82575: | |
9d5c8243 AK |
786 | /* The 82575 assigns vectors using a bitmask, which matches the |
787 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
788 | or more queues to a vector, we write the appropriate bits | |
789 | into the MSIXBM register for that vector. */ | |
047e0030 | 790 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 791 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 792 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 793 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
feeb2721 AD |
794 | if (!adapter->msix_entries && msix_vector == 0) |
795 | msixbm |= E1000_EIMS_OTHER; | |
9d5c8243 | 796 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 797 | q_vector->eims_value = msixbm; |
2d064c06 AD |
798 | break; |
799 | case e1000_82576: | |
4be000c8 AD |
800 | /* |
801 | * 82576 uses a table that essentially consists of 2 columns | |
802 | * with 8 rows. The ordering is column-major so we use the | |
803 | * lower 3 bits as the row index, and the 4th bit as the | |
804 | * column offset. | |
805 | */ | |
806 | if (rx_queue > IGB_N0_QUEUE) | |
807 | igb_write_ivar(hw, msix_vector, | |
808 | rx_queue & 0x7, | |
809 | (rx_queue & 0x8) << 1); | |
810 | if (tx_queue > IGB_N0_QUEUE) | |
811 | igb_write_ivar(hw, msix_vector, | |
812 | tx_queue & 0x7, | |
813 | ((tx_queue & 0x8) << 1) + 8); | |
047e0030 | 814 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 815 | break; |
55cac248 | 816 | case e1000_82580: |
d2ba2ed8 | 817 | case e1000_i350: |
f96a8a0b CW |
818 | case e1000_i210: |
819 | case e1000_i211: | |
4be000c8 AD |
820 | /* |
821 | * On 82580 and newer adapters the scheme is similar to 82576 | |
822 | * however instead of ordering column-major we have things | |
823 | * ordered row-major. So we traverse the table by using | |
824 | * bit 0 as the column offset, and the remaining bits as the | |
825 | * row index. | |
826 | */ | |
827 | if (rx_queue > IGB_N0_QUEUE) | |
828 | igb_write_ivar(hw, msix_vector, | |
829 | rx_queue >> 1, | |
830 | (rx_queue & 0x1) << 4); | |
831 | if (tx_queue > IGB_N0_QUEUE) | |
832 | igb_write_ivar(hw, msix_vector, | |
833 | tx_queue >> 1, | |
834 | ((tx_queue & 0x1) << 4) + 8); | |
55cac248 AD |
835 | q_vector->eims_value = 1 << msix_vector; |
836 | break; | |
2d064c06 AD |
837 | default: |
838 | BUG(); | |
839 | break; | |
840 | } | |
26b39276 AD |
841 | |
842 | /* add q_vector eims value to global eims_enable_mask */ | |
843 | adapter->eims_enable_mask |= q_vector->eims_value; | |
844 | ||
845 | /* configure q_vector to set itr on first interrupt */ | |
846 | q_vector->set_itr = 1; | |
9d5c8243 AK |
847 | } |
848 | ||
849 | /** | |
850 | * igb_configure_msix - Configure MSI-X hardware | |
851 | * | |
852 | * igb_configure_msix sets up the hardware to properly | |
853 | * generate MSI-X interrupts. | |
854 | **/ | |
855 | static void igb_configure_msix(struct igb_adapter *adapter) | |
856 | { | |
857 | u32 tmp; | |
858 | int i, vector = 0; | |
859 | struct e1000_hw *hw = &adapter->hw; | |
860 | ||
861 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
862 | |
863 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
864 | switch (hw->mac.type) { |
865 | case e1000_82575: | |
9d5c8243 AK |
866 | tmp = rd32(E1000_CTRL_EXT); |
867 | /* enable MSI-X PBA support*/ | |
868 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
869 | ||
870 | /* Auto-Mask interrupts upon ICR read. */ | |
871 | tmp |= E1000_CTRL_EXT_EIAME; | |
872 | tmp |= E1000_CTRL_EXT_IRCA; | |
873 | ||
874 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
875 | |
876 | /* enable msix_other interrupt */ | |
877 | array_wr32(E1000_MSIXBM(0), vector++, | |
878 | E1000_EIMS_OTHER); | |
844290e5 | 879 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 880 | |
2d064c06 AD |
881 | break; |
882 | ||
883 | case e1000_82576: | |
55cac248 | 884 | case e1000_82580: |
d2ba2ed8 | 885 | case e1000_i350: |
f96a8a0b CW |
886 | case e1000_i210: |
887 | case e1000_i211: | |
047e0030 AD |
888 | /* Turn on MSI-X capability first, or our settings |
889 | * won't stick. And it will take days to debug. */ | |
890 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
891 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | |
892 | E1000_GPIE_NSICR); | |
893 | ||
894 | /* enable msix_other interrupt */ | |
895 | adapter->eims_other = 1 << vector; | |
2d064c06 | 896 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 897 | |
047e0030 | 898 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
899 | break; |
900 | default: | |
901 | /* do nothing, since nothing else supports MSI-X */ | |
902 | break; | |
903 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
904 | |
905 | adapter->eims_enable_mask |= adapter->eims_other; | |
906 | ||
26b39276 AD |
907 | for (i = 0; i < adapter->num_q_vectors; i++) |
908 | igb_assign_vector(adapter->q_vector[i], vector++); | |
047e0030 | 909 | |
9d5c8243 AK |
910 | wrfl(); |
911 | } | |
912 | ||
913 | /** | |
914 | * igb_request_msix - Initialize MSI-X interrupts | |
915 | * | |
916 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
917 | * kernel. | |
918 | **/ | |
919 | static int igb_request_msix(struct igb_adapter *adapter) | |
920 | { | |
921 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 922 | struct e1000_hw *hw = &adapter->hw; |
52285b76 | 923 | int i, err = 0, vector = 0, free_vector = 0; |
9d5c8243 | 924 | |
047e0030 | 925 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 926 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 | 927 | if (err) |
52285b76 | 928 | goto err_out; |
047e0030 AD |
929 | |
930 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
931 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
932 | ||
52285b76 SA |
933 | vector++; |
934 | ||
047e0030 AD |
935 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); |
936 | ||
0ba82994 | 937 | if (q_vector->rx.ring && q_vector->tx.ring) |
047e0030 | 938 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, |
0ba82994 AD |
939 | q_vector->rx.ring->queue_index); |
940 | else if (q_vector->tx.ring) | |
047e0030 | 941 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, |
0ba82994 AD |
942 | q_vector->tx.ring->queue_index); |
943 | else if (q_vector->rx.ring) | |
047e0030 | 944 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, |
0ba82994 | 945 | q_vector->rx.ring->queue_index); |
9d5c8243 | 946 | else |
047e0030 AD |
947 | sprintf(q_vector->name, "%s-unused", netdev->name); |
948 | ||
9d5c8243 | 949 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 950 | igb_msix_ring, 0, q_vector->name, |
047e0030 | 951 | q_vector); |
9d5c8243 | 952 | if (err) |
52285b76 | 953 | goto err_free; |
9d5c8243 AK |
954 | } |
955 | ||
9d5c8243 AK |
956 | igb_configure_msix(adapter); |
957 | return 0; | |
52285b76 SA |
958 | |
959 | err_free: | |
960 | /* free already assigned IRQs */ | |
961 | free_irq(adapter->msix_entries[free_vector++].vector, adapter); | |
962 | ||
963 | vector--; | |
964 | for (i = 0; i < vector; i++) { | |
965 | free_irq(adapter->msix_entries[free_vector++].vector, | |
966 | adapter->q_vector[i]); | |
967 | } | |
968 | err_out: | |
9d5c8243 AK |
969 | return err; |
970 | } | |
971 | ||
972 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
973 | { | |
974 | if (adapter->msix_entries) { | |
975 | pci_disable_msix(adapter->pdev); | |
976 | kfree(adapter->msix_entries); | |
977 | adapter->msix_entries = NULL; | |
047e0030 | 978 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 979 | pci_disable_msi(adapter->pdev); |
047e0030 | 980 | } |
9d5c8243 AK |
981 | } |
982 | ||
5536d210 AD |
983 | /** |
984 | * igb_free_q_vector - Free memory allocated for specific interrupt vector | |
985 | * @adapter: board private structure to initialize | |
986 | * @v_idx: Index of vector to be freed | |
987 | * | |
988 | * This function frees the memory allocated to the q_vector. In addition if | |
989 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
990 | * to freeing the q_vector. | |
991 | **/ | |
992 | static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) | |
993 | { | |
994 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
995 | ||
996 | if (q_vector->tx.ring) | |
997 | adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; | |
998 | ||
999 | if (q_vector->rx.ring) | |
1000 | adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; | |
1001 | ||
1002 | adapter->q_vector[v_idx] = NULL; | |
1003 | netif_napi_del(&q_vector->napi); | |
1004 | ||
1005 | /* | |
1006 | * ixgbe_get_stats64() might access the rings on this vector, | |
1007 | * we must wait a grace period before freeing it. | |
1008 | */ | |
1009 | kfree_rcu(q_vector, rcu); | |
1010 | } | |
1011 | ||
047e0030 AD |
1012 | /** |
1013 | * igb_free_q_vectors - Free memory allocated for interrupt vectors | |
1014 | * @adapter: board private structure to initialize | |
1015 | * | |
1016 | * This function frees the memory allocated to the q_vectors. In addition if | |
1017 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1018 | * to freeing the q_vector. | |
1019 | **/ | |
1020 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
1021 | { | |
5536d210 AD |
1022 | int v_idx = adapter->num_q_vectors; |
1023 | ||
1024 | adapter->num_tx_queues = 0; | |
1025 | adapter->num_rx_queues = 0; | |
047e0030 | 1026 | adapter->num_q_vectors = 0; |
5536d210 AD |
1027 | |
1028 | while (v_idx--) | |
1029 | igb_free_q_vector(adapter, v_idx); | |
047e0030 AD |
1030 | } |
1031 | ||
1032 | /** | |
1033 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts | |
1034 | * | |
1035 | * This function resets the device so that it has 0 rx queues, tx queues, and | |
1036 | * MSI-X interrupts allocated. | |
1037 | */ | |
1038 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
1039 | { | |
047e0030 AD |
1040 | igb_free_q_vectors(adapter); |
1041 | igb_reset_interrupt_capability(adapter); | |
1042 | } | |
9d5c8243 AK |
1043 | |
1044 | /** | |
1045 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
1046 | * | |
1047 | * Attempt to configure interrupts using the best available | |
1048 | * capabilities of the hardware and kernel. | |
1049 | **/ | |
53c7d064 | 1050 | static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) |
9d5c8243 AK |
1051 | { |
1052 | int err; | |
1053 | int numvecs, i; | |
1054 | ||
53c7d064 SA |
1055 | if (!msix) |
1056 | goto msi_only; | |
1057 | ||
83b7180d | 1058 | /* Number of supported queues. */ |
a99955fc | 1059 | adapter->num_rx_queues = adapter->rss_queues; |
5fa8517f GR |
1060 | if (adapter->vfs_allocated_count) |
1061 | adapter->num_tx_queues = 1; | |
1062 | else | |
1063 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 1064 | |
047e0030 AD |
1065 | /* start with one vector for every rx queue */ |
1066 | numvecs = adapter->num_rx_queues; | |
1067 | ||
3ad2f3fb | 1068 | /* if tx handler is separate add 1 for every tx queue */ |
a99955fc AD |
1069 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
1070 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
1071 | |
1072 | /* store the number of vectors reserved for queues */ | |
1073 | adapter->num_q_vectors = numvecs; | |
1074 | ||
1075 | /* add 1 vector for link status interrupts */ | |
1076 | numvecs++; | |
9d5c8243 AK |
1077 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
1078 | GFP_KERNEL); | |
f96a8a0b | 1079 | |
9d5c8243 AK |
1080 | if (!adapter->msix_entries) |
1081 | goto msi_only; | |
1082 | ||
1083 | for (i = 0; i < numvecs; i++) | |
1084 | adapter->msix_entries[i].entry = i; | |
1085 | ||
1086 | err = pci_enable_msix(adapter->pdev, | |
1087 | adapter->msix_entries, | |
1088 | numvecs); | |
1089 | if (err == 0) | |
0c2cc02e | 1090 | return; |
9d5c8243 AK |
1091 | |
1092 | igb_reset_interrupt_capability(adapter); | |
1093 | ||
1094 | /* If we can't do MSI-X, try MSI */ | |
1095 | msi_only: | |
2a3abf6d AD |
1096 | #ifdef CONFIG_PCI_IOV |
1097 | /* disable SR-IOV for non MSI-X configurations */ | |
1098 | if (adapter->vf_data) { | |
1099 | struct e1000_hw *hw = &adapter->hw; | |
1100 | /* disable iov and allow time for transactions to clear */ | |
1101 | pci_disable_sriov(adapter->pdev); | |
1102 | msleep(500); | |
1103 | ||
1104 | kfree(adapter->vf_data); | |
1105 | adapter->vf_data = NULL; | |
1106 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 1107 | wrfl(); |
2a3abf6d AD |
1108 | msleep(100); |
1109 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
1110 | } | |
1111 | #endif | |
4fc82adf | 1112 | adapter->vfs_allocated_count = 0; |
a99955fc | 1113 | adapter->rss_queues = 1; |
4fc82adf | 1114 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 1115 | adapter->num_rx_queues = 1; |
661086df | 1116 | adapter->num_tx_queues = 1; |
047e0030 | 1117 | adapter->num_q_vectors = 1; |
9d5c8243 | 1118 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1119 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1120 | } |
1121 | ||
5536d210 AD |
1122 | static void igb_add_ring(struct igb_ring *ring, |
1123 | struct igb_ring_container *head) | |
1124 | { | |
1125 | head->ring = ring; | |
1126 | head->count++; | |
1127 | } | |
1128 | ||
047e0030 | 1129 | /** |
5536d210 | 1130 | * igb_alloc_q_vector - Allocate memory for a single interrupt vector |
047e0030 | 1131 | * @adapter: board private structure to initialize |
5536d210 AD |
1132 | * @v_count: q_vectors allocated on adapter, used for ring interleaving |
1133 | * @v_idx: index of vector in adapter struct | |
1134 | * @txr_count: total number of Tx rings to allocate | |
1135 | * @txr_idx: index of first Tx ring to allocate | |
1136 | * @rxr_count: total number of Rx rings to allocate | |
1137 | * @rxr_idx: index of first Rx ring to allocate | |
047e0030 | 1138 | * |
5536d210 | 1139 | * We allocate one q_vector. If allocation fails we return -ENOMEM. |
047e0030 | 1140 | **/ |
5536d210 AD |
1141 | static int igb_alloc_q_vector(struct igb_adapter *adapter, |
1142 | int v_count, int v_idx, | |
1143 | int txr_count, int txr_idx, | |
1144 | int rxr_count, int rxr_idx) | |
047e0030 AD |
1145 | { |
1146 | struct igb_q_vector *q_vector; | |
5536d210 AD |
1147 | struct igb_ring *ring; |
1148 | int ring_count, size; | |
047e0030 | 1149 | |
5536d210 AD |
1150 | /* igb only supports 1 Tx and/or 1 Rx queue per vector */ |
1151 | if (txr_count > 1 || rxr_count > 1) | |
1152 | return -ENOMEM; | |
1153 | ||
1154 | ring_count = txr_count + rxr_count; | |
1155 | size = sizeof(struct igb_q_vector) + | |
1156 | (sizeof(struct igb_ring) * ring_count); | |
1157 | ||
1158 | /* allocate q_vector and rings */ | |
1159 | q_vector = kzalloc(size, GFP_KERNEL); | |
1160 | if (!q_vector) | |
1161 | return -ENOMEM; | |
1162 | ||
1163 | /* initialize NAPI */ | |
1164 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
1165 | igb_poll, 64); | |
1166 | ||
1167 | /* tie q_vector and adapter together */ | |
1168 | adapter->q_vector[v_idx] = q_vector; | |
1169 | q_vector->adapter = adapter; | |
1170 | ||
1171 | /* initialize work limits */ | |
1172 | q_vector->tx.work_limit = adapter->tx_work_limit; | |
1173 | ||
1174 | /* initialize ITR configuration */ | |
1175 | q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); | |
1176 | q_vector->itr_val = IGB_START_ITR; | |
1177 | ||
1178 | /* initialize pointer to rings */ | |
1179 | ring = q_vector->ring; | |
1180 | ||
1181 | if (txr_count) { | |
1182 | /* assign generic ring traits */ | |
1183 | ring->dev = &adapter->pdev->dev; | |
1184 | ring->netdev = adapter->netdev; | |
1185 | ||
1186 | /* configure backlink on ring */ | |
1187 | ring->q_vector = q_vector; | |
1188 | ||
1189 | /* update q_vector Tx values */ | |
1190 | igb_add_ring(ring, &q_vector->tx); | |
1191 | ||
1192 | /* For 82575, context index must be unique per ring. */ | |
1193 | if (adapter->hw.mac.type == e1000_82575) | |
1194 | set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); | |
1195 | ||
1196 | /* apply Tx specific ring traits */ | |
1197 | ring->count = adapter->tx_ring_count; | |
1198 | ring->queue_index = txr_idx; | |
1199 | ||
1200 | /* assign ring to adapter */ | |
1201 | adapter->tx_ring[txr_idx] = ring; | |
1202 | ||
1203 | /* push pointer to next ring */ | |
1204 | ring++; | |
047e0030 | 1205 | } |
81c2fc22 | 1206 | |
5536d210 AD |
1207 | if (rxr_count) { |
1208 | /* assign generic ring traits */ | |
1209 | ring->dev = &adapter->pdev->dev; | |
1210 | ring->netdev = adapter->netdev; | |
047e0030 | 1211 | |
5536d210 AD |
1212 | /* configure backlink on ring */ |
1213 | ring->q_vector = q_vector; | |
047e0030 | 1214 | |
5536d210 AD |
1215 | /* update q_vector Rx values */ |
1216 | igb_add_ring(ring, &q_vector->rx); | |
047e0030 | 1217 | |
5536d210 AD |
1218 | /* set flag indicating ring supports SCTP checksum offload */ |
1219 | if (adapter->hw.mac.type >= e1000_82576) | |
1220 | set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); | |
047e0030 | 1221 | |
5536d210 AD |
1222 | /* |
1223 | * On i350, i210, and i211, loopback VLAN packets | |
1224 | * have the tag byte-swapped. | |
1225 | * */ | |
1226 | if (adapter->hw.mac.type >= e1000_i350) | |
1227 | set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); | |
047e0030 | 1228 | |
5536d210 AD |
1229 | /* apply Rx specific ring traits */ |
1230 | ring->count = adapter->rx_ring_count; | |
1231 | ring->queue_index = rxr_idx; | |
1232 | ||
1233 | /* assign ring to adapter */ | |
1234 | adapter->rx_ring[rxr_idx] = ring; | |
1235 | } | |
1236 | ||
1237 | return 0; | |
047e0030 AD |
1238 | } |
1239 | ||
5536d210 | 1240 | |
047e0030 | 1241 | /** |
5536d210 AD |
1242 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors |
1243 | * @adapter: board private structure to initialize | |
047e0030 | 1244 | * |
5536d210 AD |
1245 | * We allocate one q_vector per queue interrupt. If allocation fails we |
1246 | * return -ENOMEM. | |
047e0030 | 1247 | **/ |
5536d210 | 1248 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) |
047e0030 | 1249 | { |
5536d210 AD |
1250 | int q_vectors = adapter->num_q_vectors; |
1251 | int rxr_remaining = adapter->num_rx_queues; | |
1252 | int txr_remaining = adapter->num_tx_queues; | |
1253 | int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
1254 | int err; | |
047e0030 | 1255 | |
5536d210 AD |
1256 | if (q_vectors >= (rxr_remaining + txr_remaining)) { |
1257 | for (; rxr_remaining; v_idx++) { | |
1258 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1259 | 0, 0, 1, rxr_idx); | |
047e0030 | 1260 | |
5536d210 AD |
1261 | if (err) |
1262 | goto err_out; | |
1263 | ||
1264 | /* update counts and index */ | |
1265 | rxr_remaining--; | |
1266 | rxr_idx++; | |
047e0030 | 1267 | } |
047e0030 | 1268 | } |
5536d210 AD |
1269 | |
1270 | for (; v_idx < q_vectors; v_idx++) { | |
1271 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); | |
1272 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); | |
1273 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1274 | tqpv, txr_idx, rqpv, rxr_idx); | |
1275 | ||
1276 | if (err) | |
1277 | goto err_out; | |
1278 | ||
1279 | /* update counts and index */ | |
1280 | rxr_remaining -= rqpv; | |
1281 | txr_remaining -= tqpv; | |
1282 | rxr_idx++; | |
1283 | txr_idx++; | |
1284 | } | |
1285 | ||
047e0030 | 1286 | return 0; |
5536d210 AD |
1287 | |
1288 | err_out: | |
1289 | adapter->num_tx_queues = 0; | |
1290 | adapter->num_rx_queues = 0; | |
1291 | adapter->num_q_vectors = 0; | |
1292 | ||
1293 | while (v_idx--) | |
1294 | igb_free_q_vector(adapter, v_idx); | |
1295 | ||
1296 | return -ENOMEM; | |
047e0030 AD |
1297 | } |
1298 | ||
1299 | /** | |
1300 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors | |
1301 | * | |
1302 | * This function initializes the interrupts and allocates all of the queues. | |
1303 | **/ | |
53c7d064 | 1304 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) |
047e0030 AD |
1305 | { |
1306 | struct pci_dev *pdev = adapter->pdev; | |
1307 | int err; | |
1308 | ||
53c7d064 | 1309 | igb_set_interrupt_capability(adapter, msix); |
047e0030 AD |
1310 | |
1311 | err = igb_alloc_q_vectors(adapter); | |
1312 | if (err) { | |
1313 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
1314 | goto err_alloc_q_vectors; | |
1315 | } | |
1316 | ||
5536d210 | 1317 | igb_cache_ring_register(adapter); |
047e0030 AD |
1318 | |
1319 | return 0; | |
5536d210 | 1320 | |
047e0030 AD |
1321 | err_alloc_q_vectors: |
1322 | igb_reset_interrupt_capability(adapter); | |
1323 | return err; | |
1324 | } | |
1325 | ||
9d5c8243 AK |
1326 | /** |
1327 | * igb_request_irq - initialize interrupts | |
1328 | * | |
1329 | * Attempts to configure interrupts using the best available | |
1330 | * capabilities of the hardware and kernel. | |
1331 | **/ | |
1332 | static int igb_request_irq(struct igb_adapter *adapter) | |
1333 | { | |
1334 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 1335 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
1336 | int err = 0; |
1337 | ||
1338 | if (adapter->msix_entries) { | |
1339 | err = igb_request_msix(adapter); | |
844290e5 | 1340 | if (!err) |
9d5c8243 | 1341 | goto request_done; |
9d5c8243 | 1342 | /* fall back to MSI */ |
5536d210 AD |
1343 | igb_free_all_tx_resources(adapter); |
1344 | igb_free_all_rx_resources(adapter); | |
53c7d064 | 1345 | |
047e0030 | 1346 | igb_clear_interrupt_scheme(adapter); |
53c7d064 SA |
1347 | err = igb_init_interrupt_scheme(adapter, false); |
1348 | if (err) | |
047e0030 | 1349 | goto request_done; |
53c7d064 | 1350 | |
047e0030 AD |
1351 | igb_setup_all_tx_resources(adapter); |
1352 | igb_setup_all_rx_resources(adapter); | |
53c7d064 | 1353 | igb_configure(adapter); |
9d5c8243 | 1354 | } |
844290e5 | 1355 | |
c74d588e AD |
1356 | igb_assign_vector(adapter->q_vector[0], 0); |
1357 | ||
7dfc16fa | 1358 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
c74d588e | 1359 | err = request_irq(pdev->irq, igb_intr_msi, 0, |
047e0030 | 1360 | netdev->name, adapter); |
9d5c8243 AK |
1361 | if (!err) |
1362 | goto request_done; | |
047e0030 | 1363 | |
9d5c8243 AK |
1364 | /* fall back to legacy interrupts */ |
1365 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 1366 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1367 | } |
1368 | ||
c74d588e | 1369 | err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 1370 | netdev->name, adapter); |
9d5c8243 | 1371 | |
6cb5e577 | 1372 | if (err) |
c74d588e | 1373 | dev_err(&pdev->dev, "Error %d getting interrupt\n", |
9d5c8243 | 1374 | err); |
9d5c8243 AK |
1375 | |
1376 | request_done: | |
1377 | return err; | |
1378 | } | |
1379 | ||
1380 | static void igb_free_irq(struct igb_adapter *adapter) | |
1381 | { | |
9d5c8243 AK |
1382 | if (adapter->msix_entries) { |
1383 | int vector = 0, i; | |
1384 | ||
047e0030 | 1385 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 1386 | |
0d1ae7f4 | 1387 | for (i = 0; i < adapter->num_q_vectors; i++) |
047e0030 | 1388 | free_irq(adapter->msix_entries[vector++].vector, |
0d1ae7f4 | 1389 | adapter->q_vector[i]); |
047e0030 AD |
1390 | } else { |
1391 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 1392 | } |
9d5c8243 AK |
1393 | } |
1394 | ||
1395 | /** | |
1396 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
1397 | * @adapter: board private structure | |
1398 | **/ | |
1399 | static void igb_irq_disable(struct igb_adapter *adapter) | |
1400 | { | |
1401 | struct e1000_hw *hw = &adapter->hw; | |
1402 | ||
25568a53 AD |
1403 | /* |
1404 | * we need to be careful when disabling interrupts. The VFs are also | |
1405 | * mapped into these registers and so clearing the bits can cause | |
1406 | * issues on the VF drivers so we only need to clear what we set | |
1407 | */ | |
9d5c8243 | 1408 | if (adapter->msix_entries) { |
2dfd1212 AD |
1409 | u32 regval = rd32(E1000_EIAM); |
1410 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
1411 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
1412 | regval = rd32(E1000_EIAC); | |
1413 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 1414 | } |
844290e5 PW |
1415 | |
1416 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
1417 | wr32(E1000_IMC, ~0); |
1418 | wrfl(); | |
81a61859 ET |
1419 | if (adapter->msix_entries) { |
1420 | int i; | |
1421 | for (i = 0; i < adapter->num_q_vectors; i++) | |
1422 | synchronize_irq(adapter->msix_entries[i].vector); | |
1423 | } else { | |
1424 | synchronize_irq(adapter->pdev->irq); | |
1425 | } | |
9d5c8243 AK |
1426 | } |
1427 | ||
1428 | /** | |
1429 | * igb_irq_enable - Enable default interrupt generation settings | |
1430 | * @adapter: board private structure | |
1431 | **/ | |
1432 | static void igb_irq_enable(struct igb_adapter *adapter) | |
1433 | { | |
1434 | struct e1000_hw *hw = &adapter->hw; | |
1435 | ||
1436 | if (adapter->msix_entries) { | |
06218a8d | 1437 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; |
2dfd1212 AD |
1438 | u32 regval = rd32(E1000_EIAC); |
1439 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1440 | regval = rd32(E1000_EIAM); | |
1441 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1442 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1443 | if (adapter->vfs_allocated_count) { |
4ae196df | 1444 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1445 | ims |= E1000_IMS_VMMB; |
1446 | } | |
1447 | wr32(E1000_IMS, ims); | |
844290e5 | 1448 | } else { |
55cac248 AD |
1449 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1450 | E1000_IMS_DRSTA); | |
1451 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1452 | E1000_IMS_DRSTA); | |
844290e5 | 1453 | } |
9d5c8243 AK |
1454 | } |
1455 | ||
1456 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1457 | { | |
51466239 | 1458 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1459 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1460 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1461 | |
1462 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1463 | /* add VID to filter table */ | |
1464 | igb_vfta_set(hw, vid, true); | |
1465 | adapter->mng_vlan_id = vid; | |
1466 | } else { | |
1467 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1468 | } | |
1469 | ||
1470 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1471 | (vid != old_vid) && | |
b2cb09b1 | 1472 | !test_bit(old_vid, adapter->active_vlans)) { |
51466239 AD |
1473 | /* remove VID from filter table */ |
1474 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1475 | } |
1476 | } | |
1477 | ||
1478 | /** | |
1479 | * igb_release_hw_control - release control of the h/w to f/w | |
1480 | * @adapter: address of board private structure | |
1481 | * | |
1482 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
1483 | * For ASF and Pass Through versions of f/w this means that the | |
1484 | * driver is no longer loaded. | |
1485 | * | |
1486 | **/ | |
1487 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1488 | { | |
1489 | struct e1000_hw *hw = &adapter->hw; | |
1490 | u32 ctrl_ext; | |
1491 | ||
1492 | /* Let firmware take over control of h/w */ | |
1493 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1494 | wr32(E1000_CTRL_EXT, | |
1495 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1496 | } | |
1497 | ||
9d5c8243 AK |
1498 | /** |
1499 | * igb_get_hw_control - get control of the h/w from f/w | |
1500 | * @adapter: address of board private structure | |
1501 | * | |
1502 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
1503 | * For ASF and Pass Through versions of f/w this means that | |
1504 | * the driver is loaded. | |
1505 | * | |
1506 | **/ | |
1507 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1508 | { | |
1509 | struct e1000_hw *hw = &adapter->hw; | |
1510 | u32 ctrl_ext; | |
1511 | ||
1512 | /* Let firmware know the driver has taken over */ | |
1513 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1514 | wr32(E1000_CTRL_EXT, | |
1515 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1516 | } | |
1517 | ||
9d5c8243 AK |
1518 | /** |
1519 | * igb_configure - configure the hardware for RX and TX | |
1520 | * @adapter: private board structure | |
1521 | **/ | |
1522 | static void igb_configure(struct igb_adapter *adapter) | |
1523 | { | |
1524 | struct net_device *netdev = adapter->netdev; | |
1525 | int i; | |
1526 | ||
1527 | igb_get_hw_control(adapter); | |
ff41f8dc | 1528 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1529 | |
1530 | igb_restore_vlan(adapter); | |
9d5c8243 | 1531 | |
85b430b4 | 1532 | igb_setup_tctl(adapter); |
06cf2666 | 1533 | igb_setup_mrqc(adapter); |
9d5c8243 | 1534 | igb_setup_rctl(adapter); |
85b430b4 AD |
1535 | |
1536 | igb_configure_tx(adapter); | |
9d5c8243 | 1537 | igb_configure_rx(adapter); |
662d7205 AD |
1538 | |
1539 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1540 | ||
c493ea45 | 1541 | /* call igb_desc_unused which always leaves |
9d5c8243 AK |
1542 | * at least 1 descriptor unused to make sure |
1543 | * next_to_use != next_to_clean */ | |
1544 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 1545 | struct igb_ring *ring = adapter->rx_ring[i]; |
cd392f5c | 1546 | igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); |
9d5c8243 | 1547 | } |
9d5c8243 AK |
1548 | } |
1549 | ||
88a268c1 NN |
1550 | /** |
1551 | * igb_power_up_link - Power up the phy/serdes link | |
1552 | * @adapter: address of board private structure | |
1553 | **/ | |
1554 | void igb_power_up_link(struct igb_adapter *adapter) | |
1555 | { | |
76886596 AA |
1556 | igb_reset_phy(&adapter->hw); |
1557 | ||
88a268c1 NN |
1558 | if (adapter->hw.phy.media_type == e1000_media_type_copper) |
1559 | igb_power_up_phy_copper(&adapter->hw); | |
1560 | else | |
1561 | igb_power_up_serdes_link_82575(&adapter->hw); | |
1562 | } | |
1563 | ||
1564 | /** | |
1565 | * igb_power_down_link - Power down the phy/serdes link | |
1566 | * @adapter: address of board private structure | |
1567 | */ | |
1568 | static void igb_power_down_link(struct igb_adapter *adapter) | |
1569 | { | |
1570 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1571 | igb_power_down_phy_copper_82575(&adapter->hw); | |
1572 | else | |
1573 | igb_shutdown_serdes_link_82575(&adapter->hw); | |
1574 | } | |
9d5c8243 AK |
1575 | |
1576 | /** | |
1577 | * igb_up - Open the interface and prepare it to handle traffic | |
1578 | * @adapter: board private structure | |
1579 | **/ | |
9d5c8243 AK |
1580 | int igb_up(struct igb_adapter *adapter) |
1581 | { | |
1582 | struct e1000_hw *hw = &adapter->hw; | |
1583 | int i; | |
1584 | ||
1585 | /* hardware has been reset, we need to reload some things */ | |
1586 | igb_configure(adapter); | |
1587 | ||
1588 | clear_bit(__IGB_DOWN, &adapter->state); | |
1589 | ||
0d1ae7f4 AD |
1590 | for (i = 0; i < adapter->num_q_vectors; i++) |
1591 | napi_enable(&(adapter->q_vector[i]->napi)); | |
1592 | ||
844290e5 | 1593 | if (adapter->msix_entries) |
9d5c8243 | 1594 | igb_configure_msix(adapter); |
feeb2721 AD |
1595 | else |
1596 | igb_assign_vector(adapter->q_vector[0], 0); | |
9d5c8243 AK |
1597 | |
1598 | /* Clear any pending interrupts. */ | |
1599 | rd32(E1000_ICR); | |
1600 | igb_irq_enable(adapter); | |
1601 | ||
d4960307 AD |
1602 | /* notify VFs that reset has been completed */ |
1603 | if (adapter->vfs_allocated_count) { | |
1604 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1605 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1606 | wr32(E1000_CTRL_EXT, reg_data); | |
1607 | } | |
1608 | ||
4cb9be7a JB |
1609 | netif_tx_start_all_queues(adapter->netdev); |
1610 | ||
25568a53 AD |
1611 | /* start the watchdog. */ |
1612 | hw->mac.get_link_status = 1; | |
1613 | schedule_work(&adapter->watchdog_task); | |
1614 | ||
9d5c8243 AK |
1615 | return 0; |
1616 | } | |
1617 | ||
1618 | void igb_down(struct igb_adapter *adapter) | |
1619 | { | |
9d5c8243 | 1620 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1621 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1622 | u32 tctl, rctl; |
1623 | int i; | |
1624 | ||
1625 | /* signal that we're down so the interrupt handler does not | |
1626 | * reschedule our watchdog timer */ | |
1627 | set_bit(__IGB_DOWN, &adapter->state); | |
1628 | ||
1629 | /* disable receives in the hardware */ | |
1630 | rctl = rd32(E1000_RCTL); | |
1631 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1632 | /* flush and sleep below */ | |
1633 | ||
fd2ea0a7 | 1634 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1635 | |
1636 | /* disable transmits in the hardware */ | |
1637 | tctl = rd32(E1000_TCTL); | |
1638 | tctl &= ~E1000_TCTL_EN; | |
1639 | wr32(E1000_TCTL, tctl); | |
1640 | /* flush both disables and wait for them to finish */ | |
1641 | wrfl(); | |
1642 | msleep(10); | |
1643 | ||
0d1ae7f4 AD |
1644 | for (i = 0; i < adapter->num_q_vectors; i++) |
1645 | napi_disable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 | 1646 | |
9d5c8243 AK |
1647 | igb_irq_disable(adapter); |
1648 | ||
1649 | del_timer_sync(&adapter->watchdog_timer); | |
1650 | del_timer_sync(&adapter->phy_info_timer); | |
1651 | ||
9d5c8243 | 1652 | netif_carrier_off(netdev); |
04fe6358 AD |
1653 | |
1654 | /* record the stats before reset*/ | |
12dcd86b ED |
1655 | spin_lock(&adapter->stats64_lock); |
1656 | igb_update_stats(adapter, &adapter->stats64); | |
1657 | spin_unlock(&adapter->stats64_lock); | |
04fe6358 | 1658 | |
9d5c8243 AK |
1659 | adapter->link_speed = 0; |
1660 | adapter->link_duplex = 0; | |
1661 | ||
3023682e JK |
1662 | if (!pci_channel_offline(adapter->pdev)) |
1663 | igb_reset(adapter); | |
9d5c8243 AK |
1664 | igb_clean_all_tx_rings(adapter); |
1665 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1666 | #ifdef CONFIG_IGB_DCA |
1667 | ||
1668 | /* since we reset the hardware DCA settings were cleared */ | |
1669 | igb_setup_dca(adapter); | |
1670 | #endif | |
9d5c8243 AK |
1671 | } |
1672 | ||
1673 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1674 | { | |
1675 | WARN_ON(in_interrupt()); | |
1676 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1677 | msleep(1); | |
1678 | igb_down(adapter); | |
1679 | igb_up(adapter); | |
1680 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1681 | } | |
1682 | ||
1683 | void igb_reset(struct igb_adapter *adapter) | |
1684 | { | |
090b1795 | 1685 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1686 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1687 | struct e1000_mac_info *mac = &hw->mac; |
1688 | struct e1000_fc_info *fc = &hw->fc; | |
d48507fe | 1689 | u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; |
9d5c8243 AK |
1690 | |
1691 | /* Repartition Pba for greater than 9k mtu | |
1692 | * To take effect CTRL.RST is required. | |
1693 | */ | |
fa4dfae0 | 1694 | switch (mac->type) { |
d2ba2ed8 | 1695 | case e1000_i350: |
55cac248 AD |
1696 | case e1000_82580: |
1697 | pba = rd32(E1000_RXPBS); | |
1698 | pba = igb_rxpbs_adjust_82580(pba); | |
1699 | break; | |
fa4dfae0 | 1700 | case e1000_82576: |
d249be54 AD |
1701 | pba = rd32(E1000_RXPBS); |
1702 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1703 | break; |
1704 | case e1000_82575: | |
f96a8a0b CW |
1705 | case e1000_i210: |
1706 | case e1000_i211: | |
fa4dfae0 AD |
1707 | default: |
1708 | pba = E1000_PBA_34K; | |
1709 | break; | |
2d064c06 | 1710 | } |
9d5c8243 | 1711 | |
2d064c06 AD |
1712 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1713 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1714 | /* adjust PBA for jumbo frames */ |
1715 | wr32(E1000_PBA, pba); | |
1716 | ||
1717 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1718 | * large enough to accommodate two full transmit packets, | |
1719 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1720 | * the Rx FIFO should be large enough to accommodate at least | |
1721 | * one full receive packet and is similarly rounded up and | |
1722 | * expressed in KB. */ | |
1723 | pba = rd32(E1000_PBA); | |
1724 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1725 | tx_space = pba >> 16; | |
1726 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1727 | pba &= 0xffff; | |
1728 | /* the tx fifo also stores 16 bytes of information about the tx | |
1729 | * but don't include ethernet FCS because hardware appends it */ | |
1730 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 1731 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1732 | ETH_FCS_LEN) * 2; |
1733 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1734 | min_tx_space >>= 10; | |
1735 | /* software strips receive CRC, so leave room for it */ | |
1736 | min_rx_space = adapter->max_frame_size; | |
1737 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1738 | min_rx_space >>= 10; | |
1739 | ||
1740 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1741 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1742 | * allocation, take space away from current Rx allocation */ | |
1743 | if (tx_space < min_tx_space && | |
1744 | ((min_tx_space - tx_space) < pba)) { | |
1745 | pba = pba - (min_tx_space - tx_space); | |
1746 | ||
1747 | /* if short on rx space, rx wins and must trump tx | |
1748 | * adjustment */ | |
1749 | if (pba < min_rx_space) | |
1750 | pba = min_rx_space; | |
1751 | } | |
2d064c06 | 1752 | wr32(E1000_PBA, pba); |
9d5c8243 | 1753 | } |
9d5c8243 AK |
1754 | |
1755 | /* flow control settings */ | |
1756 | /* The high water mark must be low enough to fit one full frame | |
1757 | * (or the size used for early receive) above it in the Rx FIFO. | |
1758 | * Set it to the lower of: | |
1759 | * - 90% of the Rx FIFO size, or | |
1760 | * - the full Rx FIFO size minus one full frame */ | |
1761 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1762 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1763 | |
d48507fe | 1764 | fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ |
d405ea3e | 1765 | fc->low_water = fc->high_water - 16; |
9d5c8243 AK |
1766 | fc->pause_time = 0xFFFF; |
1767 | fc->send_xon = 1; | |
0cce119a | 1768 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1769 | |
4ae196df AD |
1770 | /* disable receive for all VFs and wait one second */ |
1771 | if (adapter->vfs_allocated_count) { | |
1772 | int i; | |
1773 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
8fa7e0f7 | 1774 | adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; |
4ae196df AD |
1775 | |
1776 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1777 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1778 | |
1779 | /* disable transmits and receives */ | |
1780 | wr32(E1000_VFRE, 0); | |
1781 | wr32(E1000_VFTE, 0); | |
1782 | } | |
1783 | ||
9d5c8243 | 1784 | /* Allow time for pending master requests to run */ |
330a6d6a | 1785 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1786 | wr32(E1000_WUC, 0); |
1787 | ||
330a6d6a | 1788 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1789 | dev_err(&pdev->dev, "Hardware Error\n"); |
831ec0b4 | 1790 | |
a27416bb MV |
1791 | /* |
1792 | * Flow control settings reset on hardware reset, so guarantee flow | |
1793 | * control is off when forcing speed. | |
1794 | */ | |
1795 | if (!hw->mac.autoneg) | |
1796 | igb_force_mac_fc(hw); | |
1797 | ||
b6e0c419 | 1798 | igb_init_dmac(adapter, pba); |
e428893b CW |
1799 | #ifdef CONFIG_IGB_HWMON |
1800 | /* Re-initialize the thermal sensor on i350 devices. */ | |
1801 | if (!test_bit(__IGB_DOWN, &adapter->state)) { | |
1802 | if (mac->type == e1000_i350 && hw->bus.func == 0) { | |
1803 | /* If present, re-initialize the external thermal sensor | |
1804 | * interface. | |
1805 | */ | |
1806 | if (adapter->ets) | |
1807 | mac->ops.init_thermal_sensor_thresh(hw); | |
1808 | } | |
1809 | } | |
1810 | #endif | |
88a268c1 NN |
1811 | if (!netif_running(adapter->netdev)) |
1812 | igb_power_down_link(adapter); | |
1813 | ||
9d5c8243 AK |
1814 | igb_update_mng_vlan(adapter); |
1815 | ||
1816 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1817 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1818 | ||
1f6e8178 MV |
1819 | /* Re-enable PTP, where applicable. */ |
1820 | igb_ptp_reset(adapter); | |
1f6e8178 | 1821 | |
330a6d6a | 1822 | igb_get_phy_info(hw); |
9d5c8243 AK |
1823 | } |
1824 | ||
c8f44aff MM |
1825 | static netdev_features_t igb_fix_features(struct net_device *netdev, |
1826 | netdev_features_t features) | |
b2cb09b1 JP |
1827 | { |
1828 | /* | |
1829 | * Since there is no support for separate rx/tx vlan accel | |
1830 | * enable/disable make sure tx flag is always in same state as rx. | |
1831 | */ | |
1832 | if (features & NETIF_F_HW_VLAN_RX) | |
1833 | features |= NETIF_F_HW_VLAN_TX; | |
1834 | else | |
1835 | features &= ~NETIF_F_HW_VLAN_TX; | |
1836 | ||
1837 | return features; | |
1838 | } | |
1839 | ||
c8f44aff MM |
1840 | static int igb_set_features(struct net_device *netdev, |
1841 | netdev_features_t features) | |
ac52caa3 | 1842 | { |
c8f44aff | 1843 | netdev_features_t changed = netdev->features ^ features; |
89eaefb6 | 1844 | struct igb_adapter *adapter = netdev_priv(netdev); |
ac52caa3 | 1845 | |
b2cb09b1 JP |
1846 | if (changed & NETIF_F_HW_VLAN_RX) |
1847 | igb_vlan_mode(netdev, features); | |
1848 | ||
89eaefb6 BG |
1849 | if (!(changed & NETIF_F_RXALL)) |
1850 | return 0; | |
1851 | ||
1852 | netdev->features = features; | |
1853 | ||
1854 | if (netif_running(netdev)) | |
1855 | igb_reinit_locked(adapter); | |
1856 | else | |
1857 | igb_reset(adapter); | |
1858 | ||
ac52caa3 MM |
1859 | return 0; |
1860 | } | |
1861 | ||
2e5c6922 | 1862 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1863 | .ndo_open = igb_open, |
2e5c6922 | 1864 | .ndo_stop = igb_close, |
cd392f5c | 1865 | .ndo_start_xmit = igb_xmit_frame, |
12dcd86b | 1866 | .ndo_get_stats64 = igb_get_stats64, |
ff41f8dc | 1867 | .ndo_set_rx_mode = igb_set_rx_mode, |
2e5c6922 SH |
1868 | .ndo_set_mac_address = igb_set_mac, |
1869 | .ndo_change_mtu = igb_change_mtu, | |
1870 | .ndo_do_ioctl = igb_ioctl, | |
1871 | .ndo_tx_timeout = igb_tx_timeout, | |
1872 | .ndo_validate_addr = eth_validate_addr, | |
2e5c6922 SH |
1873 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
1874 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
8151d294 WM |
1875 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
1876 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | |
1877 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | |
1878 | .ndo_get_vf_config = igb_ndo_get_vf_config, | |
2e5c6922 SH |
1879 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1880 | .ndo_poll_controller = igb_netpoll, | |
1881 | #endif | |
b2cb09b1 JP |
1882 | .ndo_fix_features = igb_fix_features, |
1883 | .ndo_set_features = igb_set_features, | |
2e5c6922 SH |
1884 | }; |
1885 | ||
d67974f0 CW |
1886 | /** |
1887 | * igb_set_fw_version - Configure version string for ethtool | |
1888 | * @adapter: adapter struct | |
1889 | * | |
1890 | **/ | |
1891 | void igb_set_fw_version(struct igb_adapter *adapter) | |
1892 | { | |
1893 | struct e1000_hw *hw = &adapter->hw; | |
0b1a6f2e CW |
1894 | struct e1000_fw_version fw; |
1895 | ||
1896 | igb_get_fw_version(hw, &fw); | |
1897 | ||
1898 | switch (hw->mac.type) { | |
1899 | case e1000_i211: | |
d67974f0 | 1900 | snprintf(adapter->fw_version, sizeof(adapter->fw_version), |
0b1a6f2e CW |
1901 | "%2d.%2d-%d", |
1902 | fw.invm_major, fw.invm_minor, fw.invm_img_type); | |
1903 | break; | |
1904 | ||
1905 | default: | |
1906 | /* if option is rom valid, display its version too */ | |
1907 | if (fw.or_valid) { | |
1908 | snprintf(adapter->fw_version, | |
1909 | sizeof(adapter->fw_version), | |
1910 | "%d.%d, 0x%08x, %d.%d.%d", | |
1911 | fw.eep_major, fw.eep_minor, fw.etrack_id, | |
1912 | fw.or_major, fw.or_build, fw.or_patch); | |
1913 | /* no option rom */ | |
1914 | } else { | |
1915 | snprintf(adapter->fw_version, | |
1916 | sizeof(adapter->fw_version), | |
1917 | "%d.%d, 0x%08x", | |
1918 | fw.eep_major, fw.eep_minor, fw.etrack_id); | |
1919 | } | |
1920 | break; | |
d67974f0 | 1921 | } |
d67974f0 CW |
1922 | return; |
1923 | } | |
1924 | ||
441fc6fd CW |
1925 | static const struct i2c_board_info i350_sensor_info = { |
1926 | I2C_BOARD_INFO("i350bb", 0Xf8), | |
1927 | }; | |
1928 | ||
1929 | /* igb_init_i2c - Init I2C interface | |
1930 | * @adapter: pointer to adapter structure | |
1931 | * | |
1932 | */ | |
1933 | static s32 igb_init_i2c(struct igb_adapter *adapter) | |
1934 | { | |
1935 | s32 status = E1000_SUCCESS; | |
1936 | ||
1937 | /* I2C interface supported on i350 devices */ | |
1938 | if (adapter->hw.mac.type != e1000_i350) | |
1939 | return E1000_SUCCESS; | |
1940 | ||
1941 | /* Initialize the i2c bus which is controlled by the registers. | |
1942 | * This bus will use the i2c_algo_bit structue that implements | |
1943 | * the protocol through toggling of the 4 bits in the register. | |
1944 | */ | |
1945 | adapter->i2c_adap.owner = THIS_MODULE; | |
1946 | adapter->i2c_algo = igb_i2c_algo; | |
1947 | adapter->i2c_algo.data = adapter; | |
1948 | adapter->i2c_adap.algo_data = &adapter->i2c_algo; | |
1949 | adapter->i2c_adap.dev.parent = &adapter->pdev->dev; | |
1950 | strlcpy(adapter->i2c_adap.name, "igb BB", | |
1951 | sizeof(adapter->i2c_adap.name)); | |
1952 | status = i2c_bit_add_bus(&adapter->i2c_adap); | |
1953 | return status; | |
1954 | } | |
1955 | ||
9d5c8243 AK |
1956 | /** |
1957 | * igb_probe - Device Initialization Routine | |
1958 | * @pdev: PCI device information struct | |
1959 | * @ent: entry in igb_pci_tbl | |
1960 | * | |
1961 | * Returns 0 on success, negative on failure | |
1962 | * | |
1963 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1964 | * The OS initialization, configuring of the adapter private structure, | |
1965 | * and a hardware reset occur. | |
1966 | **/ | |
1dd06ae8 | 1967 | static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
9d5c8243 AK |
1968 | { |
1969 | struct net_device *netdev; | |
1970 | struct igb_adapter *adapter; | |
1971 | struct e1000_hw *hw; | |
4337e993 | 1972 | u16 eeprom_data = 0; |
9835fd73 | 1973 | s32 ret_val; |
4337e993 | 1974 | static int global_quad_port_a; /* global quad port a indication */ |
9d5c8243 AK |
1975 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1976 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 1977 | int err, pci_using_dac; |
9835fd73 | 1978 | u8 part_str[E1000_PBANUM_LENGTH]; |
9d5c8243 | 1979 | |
bded64a7 AG |
1980 | /* Catch broken hardware that put the wrong VF device ID in |
1981 | * the PCIe SR-IOV capability. | |
1982 | */ | |
1983 | if (pdev->is_virtfn) { | |
1984 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
f96a8a0b | 1985 | pci_name(pdev), pdev->vendor, pdev->device); |
bded64a7 AG |
1986 | return -EINVAL; |
1987 | } | |
1988 | ||
aed5dec3 | 1989 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1990 | if (err) |
1991 | return err; | |
1992 | ||
1993 | pci_using_dac = 0; | |
59d71989 | 1994 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 | 1995 | if (!err) { |
59d71989 | 1996 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
1997 | if (!err) |
1998 | pci_using_dac = 1; | |
1999 | } else { | |
59d71989 | 2000 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 | 2001 | if (err) { |
59d71989 | 2002 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 AK |
2003 | if (err) { |
2004 | dev_err(&pdev->dev, "No usable DMA " | |
2005 | "configuration, aborting\n"); | |
2006 | goto err_dma; | |
2007 | } | |
2008 | } | |
2009 | } | |
2010 | ||
aed5dec3 AD |
2011 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
2012 | IORESOURCE_MEM), | |
2013 | igb_driver_name); | |
9d5c8243 AK |
2014 | if (err) |
2015 | goto err_pci_reg; | |
2016 | ||
19d5afd4 | 2017 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 2018 | |
9d5c8243 | 2019 | pci_set_master(pdev); |
c682fc23 | 2020 | pci_save_state(pdev); |
9d5c8243 AK |
2021 | |
2022 | err = -ENOMEM; | |
1bfaf07b | 2023 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1cc3bd87 | 2024 | IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
2025 | if (!netdev) |
2026 | goto err_alloc_etherdev; | |
2027 | ||
2028 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2029 | ||
2030 | pci_set_drvdata(pdev, netdev); | |
2031 | adapter = netdev_priv(netdev); | |
2032 | adapter->netdev = netdev; | |
2033 | adapter->pdev = pdev; | |
2034 | hw = &adapter->hw; | |
2035 | hw->back = adapter; | |
b3f4d599 | 2036 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9d5c8243 AK |
2037 | |
2038 | mmio_start = pci_resource_start(pdev, 0); | |
2039 | mmio_len = pci_resource_len(pdev, 0); | |
2040 | ||
2041 | err = -EIO; | |
28b0759c AD |
2042 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
2043 | if (!hw->hw_addr) | |
9d5c8243 AK |
2044 | goto err_ioremap; |
2045 | ||
2e5c6922 | 2046 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 2047 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 2048 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
2049 | |
2050 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
2051 | ||
2052 | netdev->mem_start = mmio_start; | |
2053 | netdev->mem_end = mmio_start + mmio_len; | |
2054 | ||
9d5c8243 AK |
2055 | /* PCI config space info */ |
2056 | hw->vendor_id = pdev->vendor; | |
2057 | hw->device_id = pdev->device; | |
2058 | hw->revision_id = pdev->revision; | |
2059 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
2060 | hw->subsystem_device_id = pdev->subsystem_device; | |
2061 | ||
9d5c8243 AK |
2062 | /* Copy the default MAC, PHY and NVM function pointers */ |
2063 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
2064 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
2065 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
2066 | /* Initialize skew-specific constants */ | |
2067 | err = ei->get_invariants(hw); | |
2068 | if (err) | |
450c87c8 | 2069 | goto err_sw_init; |
9d5c8243 | 2070 | |
450c87c8 | 2071 | /* setup the private structure */ |
9d5c8243 AK |
2072 | err = igb_sw_init(adapter); |
2073 | if (err) | |
2074 | goto err_sw_init; | |
2075 | ||
2076 | igb_get_bus_info_pcie(hw); | |
2077 | ||
2078 | hw->phy.autoneg_wait_to_complete = false; | |
9d5c8243 AK |
2079 | |
2080 | /* Copper options */ | |
2081 | if (hw->phy.media_type == e1000_media_type_copper) { | |
2082 | hw->phy.mdix = AUTO_ALL_MODES; | |
2083 | hw->phy.disable_polarity_correction = false; | |
2084 | hw->phy.ms_type = e1000_ms_hw_default; | |
2085 | } | |
2086 | ||
2087 | if (igb_check_reset_block(hw)) | |
2088 | dev_info(&pdev->dev, | |
2089 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
2090 | ||
077887c3 AD |
2091 | /* |
2092 | * features is initialized to 0 in allocation, it might have bits | |
2093 | * set by igb_sw_init so we should use an or instead of an | |
2094 | * assignment. | |
2095 | */ | |
2096 | netdev->features |= NETIF_F_SG | | |
2097 | NETIF_F_IP_CSUM | | |
2098 | NETIF_F_IPV6_CSUM | | |
2099 | NETIF_F_TSO | | |
2100 | NETIF_F_TSO6 | | |
2101 | NETIF_F_RXHASH | | |
2102 | NETIF_F_RXCSUM | | |
2103 | NETIF_F_HW_VLAN_RX | | |
2104 | NETIF_F_HW_VLAN_TX; | |
2105 | ||
2106 | /* copy netdev features into list of user selectable features */ | |
2107 | netdev->hw_features |= netdev->features; | |
89eaefb6 | 2108 | netdev->hw_features |= NETIF_F_RXALL; |
077887c3 AD |
2109 | |
2110 | /* set this bit last since it cannot be part of hw_features */ | |
2111 | netdev->features |= NETIF_F_HW_VLAN_FILTER; | |
2112 | ||
2113 | netdev->vlan_features |= NETIF_F_TSO | | |
2114 | NETIF_F_TSO6 | | |
2115 | NETIF_F_IP_CSUM | | |
2116 | NETIF_F_IPV6_CSUM | | |
2117 | NETIF_F_SG; | |
48f29ffc | 2118 | |
6b8f0922 BG |
2119 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
2120 | ||
7b872a55 | 2121 | if (pci_using_dac) { |
9d5c8243 | 2122 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
2123 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
2124 | } | |
9d5c8243 | 2125 | |
ac52caa3 MM |
2126 | if (hw->mac.type >= e1000_82576) { |
2127 | netdev->hw_features |= NETIF_F_SCTP_CSUM; | |
b9473560 | 2128 | netdev->features |= NETIF_F_SCTP_CSUM; |
ac52caa3 | 2129 | } |
b9473560 | 2130 | |
01789349 JP |
2131 | netdev->priv_flags |= IFF_UNICAST_FLT; |
2132 | ||
330a6d6a | 2133 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
2134 | |
2135 | /* before reading the NVM, reset the controller to put the device in a | |
2136 | * known good starting state */ | |
2137 | hw->mac.ops.reset_hw(hw); | |
2138 | ||
f96a8a0b CW |
2139 | /* |
2140 | * make sure the NVM is good , i211 parts have special NVM that | |
2141 | * doesn't contain a checksum | |
2142 | */ | |
2143 | if (hw->mac.type != e1000_i211) { | |
2144 | if (hw->nvm.ops.validate(hw) < 0) { | |
2145 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
2146 | err = -EIO; | |
2147 | goto err_eeprom; | |
2148 | } | |
9d5c8243 AK |
2149 | } |
2150 | ||
2151 | /* copy the MAC address out of the NVM */ | |
2152 | if (hw->mac.ops.read_mac_addr(hw)) | |
2153 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
2154 | ||
2155 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
9d5c8243 | 2156 | |
aaeb6cdf | 2157 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
9d5c8243 AK |
2158 | dev_err(&pdev->dev, "Invalid MAC Address\n"); |
2159 | err = -EIO; | |
2160 | goto err_eeprom; | |
2161 | } | |
2162 | ||
d67974f0 CW |
2163 | /* get firmware version for ethtool -i */ |
2164 | igb_set_fw_version(adapter); | |
2165 | ||
c061b18d | 2166 | setup_timer(&adapter->watchdog_timer, igb_watchdog, |
0e340485 | 2167 | (unsigned long) adapter); |
c061b18d | 2168 | setup_timer(&adapter->phy_info_timer, igb_update_phy_info, |
0e340485 | 2169 | (unsigned long) adapter); |
9d5c8243 AK |
2170 | |
2171 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
2172 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
2173 | ||
450c87c8 | 2174 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
2175 | adapter->fc_autoneg = true; |
2176 | hw->mac.autoneg = true; | |
2177 | hw->phy.autoneg_advertised = 0x2f; | |
2178 | ||
0cce119a AD |
2179 | hw->fc.requested_mode = e1000_fc_default; |
2180 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 2181 | |
9d5c8243 AK |
2182 | igb_validate_mdi_setting(hw); |
2183 | ||
63d4a8f9 | 2184 | /* By default, support wake on port A */ |
a2cf8b6c | 2185 | if (hw->bus.func == 0) |
63d4a8f9 MV |
2186 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; |
2187 | ||
2188 | /* Check the NVM for wake support on non-port A ports */ | |
2189 | if (hw->mac.type >= e1000_82580) | |
55cac248 AD |
2190 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
2191 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
2192 | &eeprom_data); | |
a2cf8b6c AD |
2193 | else if (hw->bus.func == 1) |
2194 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 | 2195 | |
63d4a8f9 MV |
2196 | if (eeprom_data & IGB_EEPROM_APME) |
2197 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; | |
9d5c8243 AK |
2198 | |
2199 | /* now that we have the eeprom settings, apply the special cases where | |
2200 | * the eeprom may be wrong or the board simply won't support wake on | |
2201 | * lan on a particular port */ | |
2202 | switch (pdev->device) { | |
2203 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
63d4a8f9 | 2204 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
9d5c8243 AK |
2205 | break; |
2206 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
2207 | case E1000_DEV_ID_82576_FIBER: |
2208 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
2209 | /* Wake events only supported on port A for dual fiber |
2210 | * regardless of eeprom setting */ | |
2211 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
63d4a8f9 | 2212 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
9d5c8243 | 2213 | break; |
c8ea5ea9 | 2214 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 2215 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
2216 | /* if quad port adapter, disable WoL on all but port A */ |
2217 | if (global_quad_port_a != 0) | |
63d4a8f9 | 2218 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
c8ea5ea9 AD |
2219 | else |
2220 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
2221 | /* Reset for multiple quad port adapters */ | |
2222 | if (++global_quad_port_a == 4) | |
2223 | global_quad_port_a = 0; | |
2224 | break; | |
63d4a8f9 MV |
2225 | default: |
2226 | /* If the device can't wake, don't set software support */ | |
2227 | if (!device_can_wakeup(&adapter->pdev->dev)) | |
2228 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; | |
9d5c8243 AK |
2229 | } |
2230 | ||
2231 | /* initialize the wol settings based on the eeprom settings */ | |
63d4a8f9 MV |
2232 | if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) |
2233 | adapter->wol |= E1000_WUFC_MAG; | |
2234 | ||
2235 | /* Some vendors want WoL disabled by default, but still supported */ | |
2236 | if ((hw->mac.type == e1000_i350) && | |
2237 | (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { | |
2238 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; | |
2239 | adapter->wol = 0; | |
2240 | } | |
2241 | ||
2242 | device_set_wakeup_enable(&adapter->pdev->dev, | |
2243 | adapter->flags & IGB_FLAG_WOL_SUPPORTED); | |
9d5c8243 AK |
2244 | |
2245 | /* reset the hardware with the new settings */ | |
2246 | igb_reset(adapter); | |
2247 | ||
441fc6fd CW |
2248 | /* Init the I2C interface */ |
2249 | err = igb_init_i2c(adapter); | |
2250 | if (err) { | |
2251 | dev_err(&pdev->dev, "failed to init i2c interface\n"); | |
2252 | goto err_eeprom; | |
2253 | } | |
2254 | ||
9d5c8243 AK |
2255 | /* let the f/w know that the h/w is now under the control of the |
2256 | * driver. */ | |
2257 | igb_get_hw_control(adapter); | |
2258 | ||
9d5c8243 AK |
2259 | strcpy(netdev->name, "eth%d"); |
2260 | err = register_netdev(netdev); | |
2261 | if (err) | |
2262 | goto err_register; | |
2263 | ||
b168dfc5 JB |
2264 | /* carrier off reporting is important to ethtool even BEFORE open */ |
2265 | netif_carrier_off(netdev); | |
2266 | ||
421e02f0 | 2267 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 2268 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 2269 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 2270 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
2271 | igb_setup_dca(adapter); |
2272 | } | |
fe4506b6 | 2273 | |
38c845c7 | 2274 | #endif |
e428893b CW |
2275 | #ifdef CONFIG_IGB_HWMON |
2276 | /* Initialize the thermal sensor on i350 devices. */ | |
2277 | if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { | |
2278 | u16 ets_word; | |
3c89f6d0 | 2279 | |
e428893b CW |
2280 | /* |
2281 | * Read the NVM to determine if this i350 device supports an | |
2282 | * external thermal sensor. | |
2283 | */ | |
2284 | hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); | |
2285 | if (ets_word != 0x0000 && ets_word != 0xFFFF) | |
2286 | adapter->ets = true; | |
2287 | else | |
2288 | adapter->ets = false; | |
2289 | if (igb_sysfs_init(adapter)) | |
2290 | dev_err(&pdev->dev, | |
2291 | "failed to allocate sysfs resources\n"); | |
2292 | } else { | |
2293 | adapter->ets = false; | |
2294 | } | |
2295 | #endif | |
673b8b70 | 2296 | /* do hw tstamp init after resetting */ |
7ebae817 | 2297 | igb_ptp_init(adapter); |
673b8b70 | 2298 | |
9d5c8243 AK |
2299 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
2300 | /* print bus type/speed/width info */ | |
7c510e4b | 2301 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 | 2302 | netdev->name, |
559e9c49 | 2303 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
ff846f52 | 2304 | (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : |
559e9c49 | 2305 | "unknown"), |
59c3de89 AD |
2306 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
2307 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : | |
2308 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : | |
2309 | "unknown"), | |
7c510e4b | 2310 | netdev->dev_addr); |
9d5c8243 | 2311 | |
9835fd73 CW |
2312 | ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); |
2313 | if (ret_val) | |
2314 | strcpy(part_str, "Unknown"); | |
2315 | dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); | |
9d5c8243 AK |
2316 | dev_info(&pdev->dev, |
2317 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
2318 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 2319 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 | 2320 | adapter->num_rx_queues, adapter->num_tx_queues); |
09b068d4 CW |
2321 | switch (hw->mac.type) { |
2322 | case e1000_i350: | |
f96a8a0b CW |
2323 | case e1000_i210: |
2324 | case e1000_i211: | |
09b068d4 CW |
2325 | igb_set_eee_i350(hw); |
2326 | break; | |
2327 | default: | |
2328 | break; | |
2329 | } | |
749ab2cd YZ |
2330 | |
2331 | pm_runtime_put_noidle(&pdev->dev); | |
9d5c8243 AK |
2332 | return 0; |
2333 | ||
2334 | err_register: | |
2335 | igb_release_hw_control(adapter); | |
441fc6fd | 2336 | memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); |
9d5c8243 AK |
2337 | err_eeprom: |
2338 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 2339 | igb_reset_phy(hw); |
9d5c8243 AK |
2340 | |
2341 | if (hw->flash_address) | |
2342 | iounmap(hw->flash_address); | |
9d5c8243 | 2343 | err_sw_init: |
047e0030 | 2344 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
2345 | iounmap(hw->hw_addr); |
2346 | err_ioremap: | |
2347 | free_netdev(netdev); | |
2348 | err_alloc_etherdev: | |
559e9c49 AD |
2349 | pci_release_selected_regions(pdev, |
2350 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
2351 | err_pci_reg: |
2352 | err_dma: | |
2353 | pci_disable_device(pdev); | |
2354 | return err; | |
2355 | } | |
2356 | ||
fa44f2f1 GR |
2357 | #ifdef CONFIG_PCI_IOV |
2358 | static int igb_disable_sriov(struct pci_dev *pdev) | |
2359 | { | |
2360 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2361 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2362 | struct e1000_hw *hw = &adapter->hw; | |
2363 | ||
2364 | /* reclaim resources allocated to VFs */ | |
2365 | if (adapter->vf_data) { | |
2366 | /* disable iov and allow time for transactions to clear */ | |
2367 | if (igb_vfs_are_assigned(adapter)) { | |
2368 | dev_warn(&pdev->dev, | |
2369 | "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); | |
2370 | return -EPERM; | |
2371 | } else { | |
2372 | pci_disable_sriov(pdev); | |
2373 | msleep(500); | |
2374 | } | |
2375 | ||
2376 | kfree(adapter->vf_data); | |
2377 | adapter->vf_data = NULL; | |
2378 | adapter->vfs_allocated_count = 0; | |
2379 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
2380 | wrfl(); | |
2381 | msleep(100); | |
2382 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
2383 | ||
2384 | /* Re-enable DMA Coalescing flag since IOV is turned off */ | |
2385 | adapter->flags |= IGB_FLAG_DMAC; | |
2386 | } | |
2387 | ||
2388 | return 0; | |
2389 | } | |
2390 | ||
2391 | static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) | |
2392 | { | |
2393 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2394 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2395 | int old_vfs = pci_num_vf(pdev); | |
2396 | int err = 0; | |
2397 | int i; | |
2398 | ||
2399 | if (!num_vfs) | |
2400 | goto out; | |
2401 | else if (old_vfs && old_vfs == num_vfs) | |
2402 | goto out; | |
2403 | else if (old_vfs && old_vfs != num_vfs) | |
2404 | err = igb_disable_sriov(pdev); | |
2405 | ||
2406 | if (err) | |
2407 | goto out; | |
2408 | ||
2409 | if (num_vfs > 7) { | |
2410 | err = -EPERM; | |
2411 | goto out; | |
2412 | } | |
2413 | ||
2414 | adapter->vfs_allocated_count = num_vfs; | |
2415 | ||
2416 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
2417 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
2418 | ||
2419 | /* if allocation failed then we do not support SR-IOV */ | |
2420 | if (!adapter->vf_data) { | |
2421 | adapter->vfs_allocated_count = 0; | |
2422 | dev_err(&pdev->dev, | |
2423 | "Unable to allocate memory for VF Data Storage\n"); | |
2424 | err = -ENOMEM; | |
2425 | goto out; | |
2426 | } | |
2427 | ||
2428 | err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); | |
2429 | if (err) | |
2430 | goto err_out; | |
2431 | ||
2432 | dev_info(&pdev->dev, "%d VFs allocated\n", | |
2433 | adapter->vfs_allocated_count); | |
2434 | for (i = 0; i < adapter->vfs_allocated_count; i++) | |
2435 | igb_vf_configure(adapter, i); | |
2436 | ||
2437 | /* DMA Coalescing is not supported in IOV mode. */ | |
2438 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2439 | goto out; | |
2440 | ||
2441 | err_out: | |
2442 | kfree(adapter->vf_data); | |
2443 | adapter->vf_data = NULL; | |
2444 | adapter->vfs_allocated_count = 0; | |
2445 | out: | |
2446 | return err; | |
2447 | } | |
2448 | ||
2449 | #endif | |
441fc6fd CW |
2450 | /* |
2451 | * igb_remove_i2c - Cleanup I2C interface | |
2452 | * @adapter: pointer to adapter structure | |
2453 | * | |
2454 | */ | |
2455 | static void igb_remove_i2c(struct igb_adapter *adapter) | |
2456 | { | |
2457 | ||
2458 | /* free the adapter bus structure */ | |
2459 | i2c_del_adapter(&adapter->i2c_adap); | |
2460 | } | |
2461 | ||
9d5c8243 AK |
2462 | /** |
2463 | * igb_remove - Device Removal Routine | |
2464 | * @pdev: PCI device information struct | |
2465 | * | |
2466 | * igb_remove is called by the PCI subsystem to alert the driver | |
2467 | * that it should release a PCI device. The could be caused by a | |
2468 | * Hot-Plug event, or because the driver is going to be removed from | |
2469 | * memory. | |
2470 | **/ | |
9f9a12f8 | 2471 | static void igb_remove(struct pci_dev *pdev) |
9d5c8243 AK |
2472 | { |
2473 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2474 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 2475 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 2476 | |
749ab2cd | 2477 | pm_runtime_get_noresume(&pdev->dev); |
e428893b CW |
2478 | #ifdef CONFIG_IGB_HWMON |
2479 | igb_sysfs_exit(adapter); | |
2480 | #endif | |
441fc6fd | 2481 | igb_remove_i2c(adapter); |
a79f4f88 | 2482 | igb_ptp_stop(adapter); |
760141a5 TH |
2483 | /* |
2484 | * The watchdog timer may be rescheduled, so explicitly | |
2485 | * disable watchdog from being rescheduled. | |
2486 | */ | |
9d5c8243 AK |
2487 | set_bit(__IGB_DOWN, &adapter->state); |
2488 | del_timer_sync(&adapter->watchdog_timer); | |
2489 | del_timer_sync(&adapter->phy_info_timer); | |
2490 | ||
760141a5 TH |
2491 | cancel_work_sync(&adapter->reset_task); |
2492 | cancel_work_sync(&adapter->watchdog_task); | |
9d5c8243 | 2493 | |
421e02f0 | 2494 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 2495 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
2496 | dev_info(&pdev->dev, "DCA disabled\n"); |
2497 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 2498 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 2499 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
2500 | } |
2501 | #endif | |
2502 | ||
9d5c8243 AK |
2503 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
2504 | * would have already happened in close and is redundant. */ | |
2505 | igb_release_hw_control(adapter); | |
2506 | ||
2507 | unregister_netdev(netdev); | |
2508 | ||
047e0030 | 2509 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 2510 | |
37680117 | 2511 | #ifdef CONFIG_PCI_IOV |
fa44f2f1 | 2512 | igb_disable_sriov(pdev); |
37680117 | 2513 | #endif |
559e9c49 | 2514 | |
28b0759c AD |
2515 | iounmap(hw->hw_addr); |
2516 | if (hw->flash_address) | |
2517 | iounmap(hw->flash_address); | |
559e9c49 AD |
2518 | pci_release_selected_regions(pdev, |
2519 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 | 2520 | |
1128c756 | 2521 | kfree(adapter->shadow_vfta); |
9d5c8243 AK |
2522 | free_netdev(netdev); |
2523 | ||
19d5afd4 | 2524 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 2525 | |
9d5c8243 AK |
2526 | pci_disable_device(pdev); |
2527 | } | |
2528 | ||
a6b623e0 AD |
2529 | /** |
2530 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space | |
2531 | * @adapter: board private structure to initialize | |
2532 | * | |
2533 | * This function initializes the vf specific data storage and then attempts to | |
2534 | * allocate the VFs. The reason for ordering it this way is because it is much | |
2535 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
2536 | * the memory for the VFs. | |
2537 | **/ | |
9f9a12f8 | 2538 | static void igb_probe_vfs(struct igb_adapter *adapter) |
a6b623e0 AD |
2539 | { |
2540 | #ifdef CONFIG_PCI_IOV | |
2541 | struct pci_dev *pdev = adapter->pdev; | |
f96a8a0b | 2542 | struct e1000_hw *hw = &adapter->hw; |
a6b623e0 | 2543 | |
f96a8a0b CW |
2544 | /* Virtualization features not supported on i210 family. */ |
2545 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) | |
2546 | return; | |
2547 | ||
fa44f2f1 GR |
2548 | igb_enable_sriov(pdev, max_vfs); |
2549 | pci_sriov_set_totalvfs(pdev, 7); | |
0224d663 | 2550 | |
a6b623e0 AD |
2551 | #endif /* CONFIG_PCI_IOV */ |
2552 | } | |
2553 | ||
fa44f2f1 | 2554 | static void igb_init_queue_configuration(struct igb_adapter *adapter) |
9d5c8243 AK |
2555 | { |
2556 | struct e1000_hw *hw = &adapter->hw; | |
374a542d | 2557 | u32 max_rss_queues; |
9d5c8243 | 2558 | |
374a542d | 2559 | /* Determine the maximum number of RSS queues supported. */ |
f96a8a0b | 2560 | switch (hw->mac.type) { |
374a542d MV |
2561 | case e1000_i211: |
2562 | max_rss_queues = IGB_MAX_RX_QUEUES_I211; | |
2563 | break; | |
2564 | case e1000_82575: | |
f96a8a0b | 2565 | case e1000_i210: |
374a542d MV |
2566 | max_rss_queues = IGB_MAX_RX_QUEUES_82575; |
2567 | break; | |
2568 | case e1000_i350: | |
2569 | /* I350 cannot do RSS and SR-IOV at the same time */ | |
2570 | if (!!adapter->vfs_allocated_count) { | |
2571 | max_rss_queues = 1; | |
2572 | break; | |
2573 | } | |
2574 | /* fall through */ | |
2575 | case e1000_82576: | |
2576 | if (!!adapter->vfs_allocated_count) { | |
2577 | max_rss_queues = 2; | |
2578 | break; | |
2579 | } | |
2580 | /* fall through */ | |
2581 | case e1000_82580: | |
2582 | default: | |
2583 | max_rss_queues = IGB_MAX_RX_QUEUES; | |
f96a8a0b | 2584 | break; |
374a542d MV |
2585 | } |
2586 | ||
2587 | adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); | |
2588 | ||
2589 | /* Determine if we need to pair queues. */ | |
2590 | switch (hw->mac.type) { | |
2591 | case e1000_82575: | |
f96a8a0b | 2592 | case e1000_i211: |
374a542d | 2593 | /* Device supports enough interrupts without queue pairing. */ |
f96a8a0b | 2594 | break; |
374a542d MV |
2595 | case e1000_82576: |
2596 | /* | |
2597 | * If VFs are going to be allocated with RSS queues then we | |
2598 | * should pair the queues in order to conserve interrupts due | |
2599 | * to limited supply. | |
2600 | */ | |
2601 | if ((adapter->rss_queues > 1) && | |
2602 | (adapter->vfs_allocated_count > 6)) | |
2603 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
2604 | /* fall through */ | |
2605 | case e1000_82580: | |
2606 | case e1000_i350: | |
2607 | case e1000_i210: | |
f96a8a0b | 2608 | default: |
374a542d MV |
2609 | /* |
2610 | * If rss_queues > half of max_rss_queues, pair the queues in | |
2611 | * order to conserve interrupts due to limited supply. | |
2612 | */ | |
2613 | if (adapter->rss_queues > (max_rss_queues / 2)) | |
2614 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
f96a8a0b CW |
2615 | break; |
2616 | } | |
fa44f2f1 GR |
2617 | } |
2618 | ||
2619 | /** | |
2620 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
2621 | * @adapter: board private structure to initialize | |
2622 | * | |
2623 | * igb_sw_init initializes the Adapter private data structure. | |
2624 | * Fields are initialized based on PCI device information and | |
2625 | * OS network device settings (MTU size). | |
2626 | **/ | |
2627 | static int igb_sw_init(struct igb_adapter *adapter) | |
2628 | { | |
2629 | struct e1000_hw *hw = &adapter->hw; | |
2630 | struct net_device *netdev = adapter->netdev; | |
2631 | struct pci_dev *pdev = adapter->pdev; | |
2632 | ||
2633 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
2634 | ||
2635 | /* set default ring sizes */ | |
2636 | adapter->tx_ring_count = IGB_DEFAULT_TXD; | |
2637 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
2638 | ||
2639 | /* set default ITR values */ | |
2640 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; | |
2641 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
2642 | ||
2643 | /* set default work limits */ | |
2644 | adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; | |
2645 | ||
2646 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + | |
2647 | VLAN_HLEN; | |
2648 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
2649 | ||
2650 | spin_lock_init(&adapter->stats64_lock); | |
2651 | #ifdef CONFIG_PCI_IOV | |
2652 | switch (hw->mac.type) { | |
2653 | case e1000_82576: | |
2654 | case e1000_i350: | |
2655 | if (max_vfs > 7) { | |
2656 | dev_warn(&pdev->dev, | |
2657 | "Maximum of 7 VFs per PF, using max\n"); | |
2658 | adapter->vfs_allocated_count = 7; | |
2659 | } else | |
2660 | adapter->vfs_allocated_count = max_vfs; | |
2661 | if (adapter->vfs_allocated_count) | |
2662 | dev_warn(&pdev->dev, | |
2663 | "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); | |
2664 | break; | |
2665 | default: | |
2666 | break; | |
2667 | } | |
2668 | #endif /* CONFIG_PCI_IOV */ | |
2669 | ||
2670 | igb_init_queue_configuration(adapter); | |
a99955fc | 2671 | |
1128c756 CW |
2672 | /* Setup and initialize a copy of the hw vlan table array */ |
2673 | adapter->shadow_vfta = kzalloc(sizeof(u32) * | |
2674 | E1000_VLAN_FILTER_TBL_SIZE, | |
2675 | GFP_ATOMIC); | |
2676 | ||
a6b623e0 | 2677 | /* This call may decrease the number of queues */ |
53c7d064 | 2678 | if (igb_init_interrupt_scheme(adapter, true)) { |
9d5c8243 AK |
2679 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
2680 | return -ENOMEM; | |
2681 | } | |
2682 | ||
a6b623e0 AD |
2683 | igb_probe_vfs(adapter); |
2684 | ||
9d5c8243 AK |
2685 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
2686 | igb_irq_disable(adapter); | |
2687 | ||
f96a8a0b | 2688 | if (hw->mac.type >= e1000_i350) |
831ec0b4 CW |
2689 | adapter->flags &= ~IGB_FLAG_DMAC; |
2690 | ||
9d5c8243 AK |
2691 | set_bit(__IGB_DOWN, &adapter->state); |
2692 | return 0; | |
2693 | } | |
2694 | ||
2695 | /** | |
2696 | * igb_open - Called when a network interface is made active | |
2697 | * @netdev: network interface device structure | |
2698 | * | |
2699 | * Returns 0 on success, negative value on failure | |
2700 | * | |
2701 | * The open entry point is called when a network interface is made | |
2702 | * active by the system (IFF_UP). At this point all resources needed | |
2703 | * for transmit and receive operations are allocated, the interrupt | |
2704 | * handler is registered with the OS, the watchdog timer is started, | |
2705 | * and the stack is notified that the interface is ready. | |
2706 | **/ | |
749ab2cd | 2707 | static int __igb_open(struct net_device *netdev, bool resuming) |
9d5c8243 AK |
2708 | { |
2709 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2710 | struct e1000_hw *hw = &adapter->hw; | |
749ab2cd | 2711 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2712 | int err; |
2713 | int i; | |
2714 | ||
2715 | /* disallow open during test */ | |
749ab2cd YZ |
2716 | if (test_bit(__IGB_TESTING, &adapter->state)) { |
2717 | WARN_ON(resuming); | |
9d5c8243 | 2718 | return -EBUSY; |
749ab2cd YZ |
2719 | } |
2720 | ||
2721 | if (!resuming) | |
2722 | pm_runtime_get_sync(&pdev->dev); | |
9d5c8243 | 2723 | |
b168dfc5 JB |
2724 | netif_carrier_off(netdev); |
2725 | ||
9d5c8243 AK |
2726 | /* allocate transmit descriptors */ |
2727 | err = igb_setup_all_tx_resources(adapter); | |
2728 | if (err) | |
2729 | goto err_setup_tx; | |
2730 | ||
2731 | /* allocate receive descriptors */ | |
2732 | err = igb_setup_all_rx_resources(adapter); | |
2733 | if (err) | |
2734 | goto err_setup_rx; | |
2735 | ||
88a268c1 | 2736 | igb_power_up_link(adapter); |
9d5c8243 | 2737 | |
9d5c8243 AK |
2738 | /* before we allocate an interrupt, we must be ready to handle it. |
2739 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2740 | * as soon as we call pci_request_irq, so we have to setup our | |
2741 | * clean_rx handler before we do so. */ | |
2742 | igb_configure(adapter); | |
2743 | ||
2744 | err = igb_request_irq(adapter); | |
2745 | if (err) | |
2746 | goto err_req_irq; | |
2747 | ||
0c2cc02e AD |
2748 | /* Notify the stack of the actual queue counts. */ |
2749 | err = netif_set_real_num_tx_queues(adapter->netdev, | |
2750 | adapter->num_tx_queues); | |
2751 | if (err) | |
2752 | goto err_set_queues; | |
2753 | ||
2754 | err = netif_set_real_num_rx_queues(adapter->netdev, | |
2755 | adapter->num_rx_queues); | |
2756 | if (err) | |
2757 | goto err_set_queues; | |
2758 | ||
9d5c8243 AK |
2759 | /* From here on the code is the same as igb_up() */ |
2760 | clear_bit(__IGB_DOWN, &adapter->state); | |
2761 | ||
0d1ae7f4 AD |
2762 | for (i = 0; i < adapter->num_q_vectors; i++) |
2763 | napi_enable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 AK |
2764 | |
2765 | /* Clear any pending interrupts. */ | |
2766 | rd32(E1000_ICR); | |
844290e5 PW |
2767 | |
2768 | igb_irq_enable(adapter); | |
2769 | ||
d4960307 AD |
2770 | /* notify VFs that reset has been completed */ |
2771 | if (adapter->vfs_allocated_count) { | |
2772 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2773 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2774 | wr32(E1000_CTRL_EXT, reg_data); | |
2775 | } | |
2776 | ||
d55b53ff JK |
2777 | netif_tx_start_all_queues(netdev); |
2778 | ||
749ab2cd YZ |
2779 | if (!resuming) |
2780 | pm_runtime_put(&pdev->dev); | |
2781 | ||
25568a53 AD |
2782 | /* start the watchdog. */ |
2783 | hw->mac.get_link_status = 1; | |
2784 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2785 | |
2786 | return 0; | |
2787 | ||
0c2cc02e AD |
2788 | err_set_queues: |
2789 | igb_free_irq(adapter); | |
9d5c8243 AK |
2790 | err_req_irq: |
2791 | igb_release_hw_control(adapter); | |
88a268c1 | 2792 | igb_power_down_link(adapter); |
9d5c8243 AK |
2793 | igb_free_all_rx_resources(adapter); |
2794 | err_setup_rx: | |
2795 | igb_free_all_tx_resources(adapter); | |
2796 | err_setup_tx: | |
2797 | igb_reset(adapter); | |
749ab2cd YZ |
2798 | if (!resuming) |
2799 | pm_runtime_put(&pdev->dev); | |
9d5c8243 AK |
2800 | |
2801 | return err; | |
2802 | } | |
2803 | ||
749ab2cd YZ |
2804 | static int igb_open(struct net_device *netdev) |
2805 | { | |
2806 | return __igb_open(netdev, false); | |
2807 | } | |
2808 | ||
9d5c8243 AK |
2809 | /** |
2810 | * igb_close - Disables a network interface | |
2811 | * @netdev: network interface device structure | |
2812 | * | |
2813 | * Returns 0, this is not allowed to fail | |
2814 | * | |
2815 | * The close entry point is called when an interface is de-activated | |
2816 | * by the OS. The hardware is still under the driver's control, but | |
2817 | * needs to be disabled. A global MAC reset is issued to stop the | |
2818 | * hardware, and all transmit and receive resources are freed. | |
2819 | **/ | |
749ab2cd | 2820 | static int __igb_close(struct net_device *netdev, bool suspending) |
9d5c8243 AK |
2821 | { |
2822 | struct igb_adapter *adapter = netdev_priv(netdev); | |
749ab2cd | 2823 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2824 | |
2825 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
9d5c8243 | 2826 | |
749ab2cd YZ |
2827 | if (!suspending) |
2828 | pm_runtime_get_sync(&pdev->dev); | |
2829 | ||
2830 | igb_down(adapter); | |
9d5c8243 AK |
2831 | igb_free_irq(adapter); |
2832 | ||
2833 | igb_free_all_tx_resources(adapter); | |
2834 | igb_free_all_rx_resources(adapter); | |
2835 | ||
749ab2cd YZ |
2836 | if (!suspending) |
2837 | pm_runtime_put_sync(&pdev->dev); | |
9d5c8243 AK |
2838 | return 0; |
2839 | } | |
2840 | ||
749ab2cd YZ |
2841 | static int igb_close(struct net_device *netdev) |
2842 | { | |
2843 | return __igb_close(netdev, false); | |
2844 | } | |
2845 | ||
9d5c8243 AK |
2846 | /** |
2847 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
9d5c8243 AK |
2848 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
2849 | * | |
2850 | * Return 0 on success, negative on failure | |
2851 | **/ | |
80785298 | 2852 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2853 | { |
59d71989 | 2854 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
2855 | int size; |
2856 | ||
06034649 | 2857 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
f33005a6 AD |
2858 | |
2859 | tx_ring->tx_buffer_info = vzalloc(size); | |
06034649 | 2860 | if (!tx_ring->tx_buffer_info) |
9d5c8243 | 2861 | goto err; |
9d5c8243 AK |
2862 | |
2863 | /* round up to nearest 4K */ | |
85e8d004 | 2864 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2865 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2866 | ||
5536d210 AD |
2867 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
2868 | &tx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
2869 | if (!tx_ring->desc) |
2870 | goto err; | |
2871 | ||
9d5c8243 AK |
2872 | tx_ring->next_to_use = 0; |
2873 | tx_ring->next_to_clean = 0; | |
81c2fc22 | 2874 | |
9d5c8243 AK |
2875 | return 0; |
2876 | ||
2877 | err: | |
06034649 | 2878 | vfree(tx_ring->tx_buffer_info); |
f33005a6 AD |
2879 | tx_ring->tx_buffer_info = NULL; |
2880 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); | |
9d5c8243 AK |
2881 | return -ENOMEM; |
2882 | } | |
2883 | ||
2884 | /** | |
2885 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
2886 | * (Descriptors) for all queues | |
2887 | * @adapter: board private structure | |
2888 | * | |
2889 | * Return 0 on success, negative on failure | |
2890 | **/ | |
2891 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2892 | { | |
439705e1 | 2893 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2894 | int i, err = 0; |
2895 | ||
2896 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 2897 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
9d5c8243 | 2898 | if (err) { |
439705e1 | 2899 | dev_err(&pdev->dev, |
9d5c8243 AK |
2900 | "Allocation for Tx Queue %u failed\n", i); |
2901 | for (i--; i >= 0; i--) | |
3025a446 | 2902 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2903 | break; |
2904 | } | |
2905 | } | |
2906 | ||
2907 | return err; | |
2908 | } | |
2909 | ||
2910 | /** | |
85b430b4 AD |
2911 | * igb_setup_tctl - configure the transmit control registers |
2912 | * @adapter: Board private structure | |
9d5c8243 | 2913 | **/ |
d7ee5b3a | 2914 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2915 | { |
9d5c8243 AK |
2916 | struct e1000_hw *hw = &adapter->hw; |
2917 | u32 tctl; | |
9d5c8243 | 2918 | |
85b430b4 AD |
2919 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2920 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2921 | |
2922 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2923 | tctl = rd32(E1000_TCTL); |
2924 | tctl &= ~E1000_TCTL_CT; | |
2925 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2926 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2927 | ||
2928 | igb_config_collision_dist(hw); | |
2929 | ||
9d5c8243 AK |
2930 | /* Enable transmits */ |
2931 | tctl |= E1000_TCTL_EN; | |
2932 | ||
2933 | wr32(E1000_TCTL, tctl); | |
2934 | } | |
2935 | ||
85b430b4 AD |
2936 | /** |
2937 | * igb_configure_tx_ring - Configure transmit ring after Reset | |
2938 | * @adapter: board private structure | |
2939 | * @ring: tx ring to configure | |
2940 | * | |
2941 | * Configure a transmit ring after a reset. | |
2942 | **/ | |
d7ee5b3a AD |
2943 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
2944 | struct igb_ring *ring) | |
85b430b4 AD |
2945 | { |
2946 | struct e1000_hw *hw = &adapter->hw; | |
a74420e0 | 2947 | u32 txdctl = 0; |
85b430b4 AD |
2948 | u64 tdba = ring->dma; |
2949 | int reg_idx = ring->reg_idx; | |
2950 | ||
2951 | /* disable the queue */ | |
a74420e0 | 2952 | wr32(E1000_TXDCTL(reg_idx), 0); |
85b430b4 AD |
2953 | wrfl(); |
2954 | mdelay(10); | |
2955 | ||
2956 | wr32(E1000_TDLEN(reg_idx), | |
2957 | ring->count * sizeof(union e1000_adv_tx_desc)); | |
2958 | wr32(E1000_TDBAL(reg_idx), | |
2959 | tdba & 0x00000000ffffffffULL); | |
2960 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); | |
2961 | ||
fce99e34 | 2962 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); |
a74420e0 | 2963 | wr32(E1000_TDH(reg_idx), 0); |
fce99e34 | 2964 | writel(0, ring->tail); |
85b430b4 AD |
2965 | |
2966 | txdctl |= IGB_TX_PTHRESH; | |
2967 | txdctl |= IGB_TX_HTHRESH << 8; | |
2968 | txdctl |= IGB_TX_WTHRESH << 16; | |
2969 | ||
2970 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
2971 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
2972 | } | |
2973 | ||
2974 | /** | |
2975 | * igb_configure_tx - Configure transmit Unit after Reset | |
2976 | * @adapter: board private structure | |
2977 | * | |
2978 | * Configure the Tx unit of the MAC after a reset. | |
2979 | **/ | |
2980 | static void igb_configure_tx(struct igb_adapter *adapter) | |
2981 | { | |
2982 | int i; | |
2983 | ||
2984 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 2985 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
85b430b4 AD |
2986 | } |
2987 | ||
9d5c8243 AK |
2988 | /** |
2989 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
9d5c8243 AK |
2990 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
2991 | * | |
2992 | * Returns 0 on success, negative on failure | |
2993 | **/ | |
80785298 | 2994 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2995 | { |
59d71989 | 2996 | struct device *dev = rx_ring->dev; |
f33005a6 | 2997 | int size; |
9d5c8243 | 2998 | |
06034649 | 2999 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
f33005a6 AD |
3000 | |
3001 | rx_ring->rx_buffer_info = vzalloc(size); | |
06034649 | 3002 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3003 | goto err; |
9d5c8243 | 3004 | |
9d5c8243 | 3005 | /* Round up to nearest 4K */ |
f33005a6 | 3006 | rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); |
9d5c8243 AK |
3007 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
3008 | ||
5536d210 AD |
3009 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
3010 | &rx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
3011 | if (!rx_ring->desc) |
3012 | goto err; | |
3013 | ||
cbc8e55f | 3014 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3015 | rx_ring->next_to_clean = 0; |
3016 | rx_ring->next_to_use = 0; | |
9d5c8243 | 3017 | |
9d5c8243 AK |
3018 | return 0; |
3019 | ||
3020 | err: | |
06034649 AD |
3021 | vfree(rx_ring->rx_buffer_info); |
3022 | rx_ring->rx_buffer_info = NULL; | |
f33005a6 | 3023 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); |
9d5c8243 AK |
3024 | return -ENOMEM; |
3025 | } | |
3026 | ||
3027 | /** | |
3028 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
3029 | * (Descriptors) for all queues | |
3030 | * @adapter: board private structure | |
3031 | * | |
3032 | * Return 0 on success, negative on failure | |
3033 | **/ | |
3034 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
3035 | { | |
439705e1 | 3036 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
3037 | int i, err = 0; |
3038 | ||
3039 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 3040 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
9d5c8243 | 3041 | if (err) { |
439705e1 | 3042 | dev_err(&pdev->dev, |
9d5c8243 AK |
3043 | "Allocation for Rx Queue %u failed\n", i); |
3044 | for (i--; i >= 0; i--) | |
3025a446 | 3045 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3046 | break; |
3047 | } | |
3048 | } | |
3049 | ||
3050 | return err; | |
3051 | } | |
3052 | ||
06cf2666 AD |
3053 | /** |
3054 | * igb_setup_mrqc - configure the multiple receive queue control registers | |
3055 | * @adapter: Board private structure | |
3056 | **/ | |
3057 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
3058 | { | |
3059 | struct e1000_hw *hw = &adapter->hw; | |
3060 | u32 mrqc, rxcsum; | |
797fd4be | 3061 | u32 j, num_rx_queues, shift = 0; |
a57fe23e AD |
3062 | static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, |
3063 | 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, | |
3064 | 0xA32DCB77, 0x0CF23080, 0x3BB7426A, | |
3065 | 0xFA01ACBE }; | |
06cf2666 AD |
3066 | |
3067 | /* Fill out hash function seeds */ | |
a57fe23e AD |
3068 | for (j = 0; j < 10; j++) |
3069 | wr32(E1000_RSSRK(j), rsskey[j]); | |
06cf2666 | 3070 | |
a99955fc | 3071 | num_rx_queues = adapter->rss_queues; |
06cf2666 | 3072 | |
797fd4be AD |
3073 | switch (hw->mac.type) { |
3074 | case e1000_82575: | |
3075 | shift = 6; | |
3076 | break; | |
3077 | case e1000_82576: | |
3078 | /* 82576 supports 2 RSS queues for SR-IOV */ | |
3079 | if (adapter->vfs_allocated_count) { | |
06cf2666 AD |
3080 | shift = 3; |
3081 | num_rx_queues = 2; | |
06cf2666 | 3082 | } |
797fd4be AD |
3083 | break; |
3084 | default: | |
3085 | break; | |
06cf2666 AD |
3086 | } |
3087 | ||
797fd4be AD |
3088 | /* |
3089 | * Populate the indirection table 4 entries at a time. To do this | |
3090 | * we are generating the results for n and n+2 and then interleaving | |
3091 | * those with the results with n+1 and n+3. | |
3092 | */ | |
3093 | for (j = 0; j < 32; j++) { | |
3094 | /* first pass generates n and n+2 */ | |
3095 | u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; | |
3096 | u32 reta = (base & 0x07800780) >> (7 - shift); | |
3097 | ||
3098 | /* second pass generates n+1 and n+3 */ | |
3099 | base += 0x00010001 * num_rx_queues; | |
3100 | reta |= (base & 0x07800780) << (1 + shift); | |
3101 | ||
3102 | wr32(E1000_RETA(j), reta); | |
06cf2666 AD |
3103 | } |
3104 | ||
3105 | /* | |
3106 | * Disable raw packet checksumming so that RSS hash is placed in | |
3107 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum | |
3108 | * offloads as they are enabled by default | |
3109 | */ | |
3110 | rxcsum = rd32(E1000_RXCSUM); | |
3111 | rxcsum |= E1000_RXCSUM_PCSD; | |
3112 | ||
3113 | if (adapter->hw.mac.type >= e1000_82576) | |
3114 | /* Enable Receive Checksum Offload for SCTP */ | |
3115 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
3116 | ||
3117 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
3118 | wr32(E1000_RXCSUM, rxcsum); | |
f96a8a0b | 3119 | |
039454a8 AA |
3120 | /* Generate RSS hash based on packet types, TCP/UDP |
3121 | * port numbers and/or IPv4/v6 src and dst addresses | |
3122 | */ | |
f96a8a0b CW |
3123 | mrqc = E1000_MRQC_RSS_FIELD_IPV4 | |
3124 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
3125 | E1000_MRQC_RSS_FIELD_IPV6 | | |
3126 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
3127 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; | |
06cf2666 | 3128 | |
039454a8 AA |
3129 | if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) |
3130 | mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; | |
3131 | if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) | |
3132 | mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; | |
3133 | ||
06cf2666 AD |
3134 | /* If VMDq is enabled then we set the appropriate mode for that, else |
3135 | * we default to RSS so that an RSS hash is calculated per packet even | |
3136 | * if we are only using one queue */ | |
3137 | if (adapter->vfs_allocated_count) { | |
3138 | if (hw->mac.type > e1000_82575) { | |
3139 | /* Set the default pool for the PF's first queue */ | |
3140 | u32 vtctl = rd32(E1000_VT_CTL); | |
3141 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
3142 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
3143 | vtctl |= adapter->vfs_allocated_count << | |
3144 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
3145 | wr32(E1000_VT_CTL, vtctl); | |
3146 | } | |
a99955fc | 3147 | if (adapter->rss_queues > 1) |
f96a8a0b | 3148 | mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
06cf2666 | 3149 | else |
f96a8a0b | 3150 | mrqc |= E1000_MRQC_ENABLE_VMDQ; |
06cf2666 | 3151 | } else { |
f96a8a0b CW |
3152 | if (hw->mac.type != e1000_i211) |
3153 | mrqc |= E1000_MRQC_ENABLE_RSS_4Q; | |
06cf2666 AD |
3154 | } |
3155 | igb_vmm_control(adapter); | |
3156 | ||
06cf2666 AD |
3157 | wr32(E1000_MRQC, mrqc); |
3158 | } | |
3159 | ||
9d5c8243 AK |
3160 | /** |
3161 | * igb_setup_rctl - configure the receive control registers | |
3162 | * @adapter: Board private structure | |
3163 | **/ | |
d7ee5b3a | 3164 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
3165 | { |
3166 | struct e1000_hw *hw = &adapter->hw; | |
3167 | u32 rctl; | |
9d5c8243 AK |
3168 | |
3169 | rctl = rd32(E1000_RCTL); | |
3170 | ||
3171 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 3172 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 3173 | |
69d728ba | 3174 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 3175 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 3176 | |
87cb7e8c AK |
3177 | /* |
3178 | * enable stripping of CRC. It's unlikely this will break BMC | |
3179 | * redirection as it did with e1000. Newer features require | |
3180 | * that the HW strips the CRC. | |
73cd78f1 | 3181 | */ |
87cb7e8c | 3182 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 3183 | |
559e9c49 | 3184 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 3185 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 3186 | |
6ec43fe6 AD |
3187 | /* enable LPE to prevent packets larger than max_frame_size */ |
3188 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 3189 | |
952f72a8 AD |
3190 | /* disable queue 0 to prevent tail write w/o re-config */ |
3191 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 3192 | |
e1739522 AD |
3193 | /* Attention!!! For SR-IOV PF driver operations you must enable |
3194 | * queue drop for all VF and PF queues to prevent head of line blocking | |
3195 | * if an un-trusted VF does not provide descriptors to hardware. | |
3196 | */ | |
3197 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
3198 | /* set all queue drop enable bits */ |
3199 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
3200 | } |
3201 | ||
89eaefb6 BG |
3202 | /* This is useful for sniffing bad packets. */ |
3203 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3204 | /* UPE and MPE will be handled by normal PROMISC logic | |
3205 | * in e1000e_set_rx_mode */ | |
3206 | rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ | |
3207 | E1000_RCTL_BAM | /* RX All Bcast Pkts */ | |
3208 | E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3209 | ||
3210 | rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ | |
3211 | E1000_RCTL_DPF | /* Allow filtered pause */ | |
3212 | E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ | |
3213 | /* Do not mess with E1000_CTRL_VME, it affects transmit as well, | |
3214 | * and that breaks VLANs. | |
3215 | */ | |
3216 | } | |
3217 | ||
9d5c8243 AK |
3218 | wr32(E1000_RCTL, rctl); |
3219 | } | |
3220 | ||
7d5753f0 AD |
3221 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
3222 | int vfn) | |
3223 | { | |
3224 | struct e1000_hw *hw = &adapter->hw; | |
3225 | u32 vmolr; | |
3226 | ||
3227 | /* if it isn't the PF check to see if VFs are enabled and | |
3228 | * increase the size to support vlan tags */ | |
3229 | if (vfn < adapter->vfs_allocated_count && | |
3230 | adapter->vf_data[vfn].vlans_enabled) | |
3231 | size += VLAN_TAG_SIZE; | |
3232 | ||
3233 | vmolr = rd32(E1000_VMOLR(vfn)); | |
3234 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
3235 | vmolr |= size | E1000_VMOLR_LPE; | |
3236 | wr32(E1000_VMOLR(vfn), vmolr); | |
3237 | ||
3238 | return 0; | |
3239 | } | |
3240 | ||
e1739522 AD |
3241 | /** |
3242 | * igb_rlpml_set - set maximum receive packet size | |
3243 | * @adapter: board private structure | |
3244 | * | |
3245 | * Configure maximum receivable packet size. | |
3246 | **/ | |
3247 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
3248 | { | |
153285f9 | 3249 | u32 max_frame_size = adapter->max_frame_size; |
e1739522 AD |
3250 | struct e1000_hw *hw = &adapter->hw; |
3251 | u16 pf_id = adapter->vfs_allocated_count; | |
3252 | ||
e1739522 AD |
3253 | if (pf_id) { |
3254 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
153285f9 AD |
3255 | /* |
3256 | * If we're in VMDQ or SR-IOV mode, then set global RLPML | |
3257 | * to our max jumbo frame size, in case we need to enable | |
3258 | * jumbo frames on one of the rings later. | |
3259 | * This will not pass over-length frames into the default | |
3260 | * queue because it's gated by the VMOLR.RLPML. | |
3261 | */ | |
7d5753f0 | 3262 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
3263 | } |
3264 | ||
3265 | wr32(E1000_RLPML, max_frame_size); | |
3266 | } | |
3267 | ||
8151d294 WM |
3268 | static inline void igb_set_vmolr(struct igb_adapter *adapter, |
3269 | int vfn, bool aupe) | |
7d5753f0 AD |
3270 | { |
3271 | struct e1000_hw *hw = &adapter->hw; | |
3272 | u32 vmolr; | |
3273 | ||
3274 | /* | |
3275 | * This register exists only on 82576 and newer so if we are older then | |
3276 | * we should exit and do nothing | |
3277 | */ | |
3278 | if (hw->mac.type < e1000_82576) | |
3279 | return; | |
3280 | ||
3281 | vmolr = rd32(E1000_VMOLR(vfn)); | |
8151d294 WM |
3282 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
3283 | if (aupe) | |
3284 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ | |
3285 | else | |
3286 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | |
7d5753f0 AD |
3287 | |
3288 | /* clear all bits that might not be set */ | |
3289 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
3290 | ||
a99955fc | 3291 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 AD |
3292 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
3293 | /* | |
3294 | * for VMDq only allow the VFs and pool 0 to accept broadcast and | |
3295 | * multicast packets | |
3296 | */ | |
3297 | if (vfn <= adapter->vfs_allocated_count) | |
3298 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ | |
3299 | ||
3300 | wr32(E1000_VMOLR(vfn), vmolr); | |
3301 | } | |
3302 | ||
85b430b4 AD |
3303 | /** |
3304 | * igb_configure_rx_ring - Configure a receive ring after Reset | |
3305 | * @adapter: board private structure | |
3306 | * @ring: receive ring to be configured | |
3307 | * | |
3308 | * Configure the Rx unit of the MAC after a reset. | |
3309 | **/ | |
d7ee5b3a AD |
3310 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
3311 | struct igb_ring *ring) | |
85b430b4 AD |
3312 | { |
3313 | struct e1000_hw *hw = &adapter->hw; | |
3314 | u64 rdba = ring->dma; | |
3315 | int reg_idx = ring->reg_idx; | |
a74420e0 | 3316 | u32 srrctl = 0, rxdctl = 0; |
85b430b4 AD |
3317 | |
3318 | /* disable the queue */ | |
a74420e0 | 3319 | wr32(E1000_RXDCTL(reg_idx), 0); |
85b430b4 AD |
3320 | |
3321 | /* Set DMA base address registers */ | |
3322 | wr32(E1000_RDBAL(reg_idx), | |
3323 | rdba & 0x00000000ffffffffULL); | |
3324 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
3325 | wr32(E1000_RDLEN(reg_idx), | |
3326 | ring->count * sizeof(union e1000_adv_rx_desc)); | |
3327 | ||
3328 | /* initialize head and tail */ | |
fce99e34 | 3329 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); |
a74420e0 | 3330 | wr32(E1000_RDH(reg_idx), 0); |
fce99e34 | 3331 | writel(0, ring->tail); |
85b430b4 | 3332 | |
952f72a8 | 3333 | /* set descriptor configuration */ |
44390ca6 | 3334 | srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
de78d1f9 | 3335 | srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
1a1c225b | 3336 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; |
06218a8d | 3337 | if (hw->mac.type >= e1000_82580) |
757b77e2 | 3338 | srrctl |= E1000_SRRCTL_TIMESTAMP; |
e6bdb6fe NN |
3339 | /* Only set Drop Enable if we are supporting multiple queues */ |
3340 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | |
3341 | srrctl |= E1000_SRRCTL_DROP_EN; | |
952f72a8 AD |
3342 | |
3343 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
3344 | ||
7d5753f0 | 3345 | /* set filtering for VMDQ pools */ |
8151d294 | 3346 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
7d5753f0 | 3347 | |
85b430b4 AD |
3348 | rxdctl |= IGB_RX_PTHRESH; |
3349 | rxdctl |= IGB_RX_HTHRESH << 8; | |
3350 | rxdctl |= IGB_RX_WTHRESH << 16; | |
a74420e0 AD |
3351 | |
3352 | /* enable receive descriptor fetching */ | |
3353 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
85b430b4 AD |
3354 | wr32(E1000_RXDCTL(reg_idx), rxdctl); |
3355 | } | |
3356 | ||
9d5c8243 AK |
3357 | /** |
3358 | * igb_configure_rx - Configure receive Unit after Reset | |
3359 | * @adapter: board private structure | |
3360 | * | |
3361 | * Configure the Rx unit of the MAC after a reset. | |
3362 | **/ | |
3363 | static void igb_configure_rx(struct igb_adapter *adapter) | |
3364 | { | |
9107584e | 3365 | int i; |
9d5c8243 | 3366 | |
68d480c4 AD |
3367 | /* set UTA to appropriate mode */ |
3368 | igb_set_uta(adapter); | |
3369 | ||
26ad9178 AD |
3370 | /* set the correct pool for the PF default MAC address in entry 0 */ |
3371 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
3372 | adapter->vfs_allocated_count); | |
3373 | ||
06cf2666 AD |
3374 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
3375 | * the Base and Length of the Rx Descriptor Ring */ | |
3376 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3377 | igb_configure_rx_ring(adapter, adapter->rx_ring[i]); |
9d5c8243 AK |
3378 | } |
3379 | ||
3380 | /** | |
3381 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
3382 | * @tx_ring: Tx descriptor ring for a specific queue |
3383 | * | |
3384 | * Free all transmit software resources | |
3385 | **/ | |
68fd9910 | 3386 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 3387 | { |
3b644cf6 | 3388 | igb_clean_tx_ring(tx_ring); |
9d5c8243 | 3389 | |
06034649 AD |
3390 | vfree(tx_ring->tx_buffer_info); |
3391 | tx_ring->tx_buffer_info = NULL; | |
9d5c8243 | 3392 | |
439705e1 AD |
3393 | /* if not set, then don't free */ |
3394 | if (!tx_ring->desc) | |
3395 | return; | |
3396 | ||
59d71989 AD |
3397 | dma_free_coherent(tx_ring->dev, tx_ring->size, |
3398 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
3399 | |
3400 | tx_ring->desc = NULL; | |
3401 | } | |
3402 | ||
3403 | /** | |
3404 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
3405 | * @adapter: board private structure | |
3406 | * | |
3407 | * Free all transmit software resources | |
3408 | **/ | |
3409 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
3410 | { | |
3411 | int i; | |
3412 | ||
3413 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3414 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
3415 | } |
3416 | ||
ebe42d16 AD |
3417 | void igb_unmap_and_free_tx_resource(struct igb_ring *ring, |
3418 | struct igb_tx_buffer *tx_buffer) | |
3419 | { | |
3420 | if (tx_buffer->skb) { | |
3421 | dev_kfree_skb_any(tx_buffer->skb); | |
c9f14bf3 | 3422 | if (dma_unmap_len(tx_buffer, len)) |
ebe42d16 | 3423 | dma_unmap_single(ring->dev, |
c9f14bf3 AD |
3424 | dma_unmap_addr(tx_buffer, dma), |
3425 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 3426 | DMA_TO_DEVICE); |
c9f14bf3 | 3427 | } else if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 3428 | dma_unmap_page(ring->dev, |
c9f14bf3 AD |
3429 | dma_unmap_addr(tx_buffer, dma), |
3430 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
3431 | DMA_TO_DEVICE); |
3432 | } | |
3433 | tx_buffer->next_to_watch = NULL; | |
3434 | tx_buffer->skb = NULL; | |
c9f14bf3 | 3435 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 | 3436 | /* buffer_info must be completely set up in the transmit path */ |
9d5c8243 AK |
3437 | } |
3438 | ||
3439 | /** | |
3440 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
3441 | * @tx_ring: ring to be cleaned |
3442 | **/ | |
3b644cf6 | 3443 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 3444 | { |
06034649 | 3445 | struct igb_tx_buffer *buffer_info; |
9d5c8243 | 3446 | unsigned long size; |
6ad4edfc | 3447 | u16 i; |
9d5c8243 | 3448 | |
06034649 | 3449 | if (!tx_ring->tx_buffer_info) |
9d5c8243 AK |
3450 | return; |
3451 | /* Free all the Tx ring sk_buffs */ | |
3452 | ||
3453 | for (i = 0; i < tx_ring->count; i++) { | |
06034649 | 3454 | buffer_info = &tx_ring->tx_buffer_info[i]; |
80785298 | 3455 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
3456 | } |
3457 | ||
dad8a3b3 JF |
3458 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
3459 | ||
06034649 AD |
3460 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
3461 | memset(tx_ring->tx_buffer_info, 0, size); | |
9d5c8243 AK |
3462 | |
3463 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
3464 | memset(tx_ring->desc, 0, tx_ring->size); |
3465 | ||
3466 | tx_ring->next_to_use = 0; | |
3467 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
3468 | } |
3469 | ||
3470 | /** | |
3471 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
3472 | * @adapter: board private structure | |
3473 | **/ | |
3474 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
3475 | { | |
3476 | int i; | |
3477 | ||
3478 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3479 | igb_clean_tx_ring(adapter->tx_ring[i]); |
9d5c8243 AK |
3480 | } |
3481 | ||
3482 | /** | |
3483 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
3484 | * @rx_ring: ring to clean the resources from |
3485 | * | |
3486 | * Free all receive software resources | |
3487 | **/ | |
68fd9910 | 3488 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3489 | { |
3b644cf6 | 3490 | igb_clean_rx_ring(rx_ring); |
9d5c8243 | 3491 | |
06034649 AD |
3492 | vfree(rx_ring->rx_buffer_info); |
3493 | rx_ring->rx_buffer_info = NULL; | |
9d5c8243 | 3494 | |
439705e1 AD |
3495 | /* if not set, then don't free */ |
3496 | if (!rx_ring->desc) | |
3497 | return; | |
3498 | ||
59d71989 AD |
3499 | dma_free_coherent(rx_ring->dev, rx_ring->size, |
3500 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
3501 | |
3502 | rx_ring->desc = NULL; | |
3503 | } | |
3504 | ||
3505 | /** | |
3506 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
3507 | * @adapter: board private structure | |
3508 | * | |
3509 | * Free all receive software resources | |
3510 | **/ | |
3511 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
3512 | { | |
3513 | int i; | |
3514 | ||
3515 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3516 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3517 | } |
3518 | ||
3519 | /** | |
3520 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
3521 | * @rx_ring: ring to free buffers from |
3522 | **/ | |
3b644cf6 | 3523 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 3524 | { |
9d5c8243 | 3525 | unsigned long size; |
c023cd88 | 3526 | u16 i; |
9d5c8243 | 3527 | |
1a1c225b AD |
3528 | if (rx_ring->skb) |
3529 | dev_kfree_skb(rx_ring->skb); | |
3530 | rx_ring->skb = NULL; | |
3531 | ||
06034649 | 3532 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3533 | return; |
439705e1 | 3534 | |
9d5c8243 AK |
3535 | /* Free all the Rx ring sk_buffs */ |
3536 | for (i = 0; i < rx_ring->count; i++) { | |
06034649 | 3537 | struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
9d5c8243 | 3538 | |
cbc8e55f AD |
3539 | if (!buffer_info->page) |
3540 | continue; | |
3541 | ||
3542 | dma_unmap_page(rx_ring->dev, | |
3543 | buffer_info->dma, | |
3544 | PAGE_SIZE, | |
3545 | DMA_FROM_DEVICE); | |
3546 | __free_page(buffer_info->page); | |
3547 | ||
1a1c225b | 3548 | buffer_info->page = NULL; |
9d5c8243 AK |
3549 | } |
3550 | ||
06034649 AD |
3551 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
3552 | memset(rx_ring->rx_buffer_info, 0, size); | |
9d5c8243 AK |
3553 | |
3554 | /* Zero out the descriptor ring */ | |
3555 | memset(rx_ring->desc, 0, rx_ring->size); | |
3556 | ||
cbc8e55f | 3557 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3558 | rx_ring->next_to_clean = 0; |
3559 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
3560 | } |
3561 | ||
3562 | /** | |
3563 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
3564 | * @adapter: board private structure | |
3565 | **/ | |
3566 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
3567 | { | |
3568 | int i; | |
3569 | ||
3570 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3571 | igb_clean_rx_ring(adapter->rx_ring[i]); |
9d5c8243 AK |
3572 | } |
3573 | ||
3574 | /** | |
3575 | * igb_set_mac - Change the Ethernet Address of the NIC | |
3576 | * @netdev: network interface device structure | |
3577 | * @p: pointer to an address structure | |
3578 | * | |
3579 | * Returns 0 on success, negative on failure | |
3580 | **/ | |
3581 | static int igb_set_mac(struct net_device *netdev, void *p) | |
3582 | { | |
3583 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 3584 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3585 | struct sockaddr *addr = p; |
3586 | ||
3587 | if (!is_valid_ether_addr(addr->sa_data)) | |
3588 | return -EADDRNOTAVAIL; | |
3589 | ||
3590 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 3591 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 3592 | |
26ad9178 AD |
3593 | /* set the correct pool for the new PF MAC address in entry 0 */ |
3594 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
3595 | adapter->vfs_allocated_count); | |
e1739522 | 3596 | |
9d5c8243 AK |
3597 | return 0; |
3598 | } | |
3599 | ||
3600 | /** | |
68d480c4 | 3601 | * igb_write_mc_addr_list - write multicast addresses to MTA |
9d5c8243 AK |
3602 | * @netdev: network interface device structure |
3603 | * | |
68d480c4 AD |
3604 | * Writes multicast address list to the MTA hash table. |
3605 | * Returns: -ENOMEM on failure | |
3606 | * 0 on no addresses written | |
3607 | * X on writing X addresses to MTA | |
9d5c8243 | 3608 | **/ |
68d480c4 | 3609 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
3610 | { |
3611 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3612 | struct e1000_hw *hw = &adapter->hw; | |
22bedad3 | 3613 | struct netdev_hw_addr *ha; |
68d480c4 | 3614 | u8 *mta_list; |
9d5c8243 AK |
3615 | int i; |
3616 | ||
4cd24eaf | 3617 | if (netdev_mc_empty(netdev)) { |
68d480c4 AD |
3618 | /* nothing to program, so clear mc list */ |
3619 | igb_update_mc_addr_list(hw, NULL, 0); | |
3620 | igb_restore_vf_multicasts(adapter); | |
3621 | return 0; | |
3622 | } | |
9d5c8243 | 3623 | |
4cd24eaf | 3624 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
68d480c4 AD |
3625 | if (!mta_list) |
3626 | return -ENOMEM; | |
ff41f8dc | 3627 | |
68d480c4 | 3628 | /* The shared function expects a packed array of only addresses. */ |
48e2f183 | 3629 | i = 0; |
22bedad3 JP |
3630 | netdev_for_each_mc_addr(ha, netdev) |
3631 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); | |
68d480c4 | 3632 | |
68d480c4 AD |
3633 | igb_update_mc_addr_list(hw, mta_list, i); |
3634 | kfree(mta_list); | |
3635 | ||
4cd24eaf | 3636 | return netdev_mc_count(netdev); |
68d480c4 AD |
3637 | } |
3638 | ||
3639 | /** | |
3640 | * igb_write_uc_addr_list - write unicast addresses to RAR table | |
3641 | * @netdev: network interface device structure | |
3642 | * | |
3643 | * Writes unicast address list to the RAR table. | |
3644 | * Returns: -ENOMEM on failure/insufficient address space | |
3645 | * 0 on no addresses written | |
3646 | * X on writing X addresses to the RAR table | |
3647 | **/ | |
3648 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
3649 | { | |
3650 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3651 | struct e1000_hw *hw = &adapter->hw; | |
3652 | unsigned int vfn = adapter->vfs_allocated_count; | |
3653 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
3654 | int count = 0; | |
3655 | ||
3656 | /* return ENOMEM indicating insufficient memory for addresses */ | |
32e7bfc4 | 3657 | if (netdev_uc_count(netdev) > rar_entries) |
68d480c4 | 3658 | return -ENOMEM; |
9d5c8243 | 3659 | |
32e7bfc4 | 3660 | if (!netdev_uc_empty(netdev) && rar_entries) { |
ff41f8dc | 3661 | struct netdev_hw_addr *ha; |
32e7bfc4 JP |
3662 | |
3663 | netdev_for_each_uc_addr(ha, netdev) { | |
ff41f8dc AD |
3664 | if (!rar_entries) |
3665 | break; | |
26ad9178 AD |
3666 | igb_rar_set_qsel(adapter, ha->addr, |
3667 | rar_entries--, | |
68d480c4 AD |
3668 | vfn); |
3669 | count++; | |
ff41f8dc AD |
3670 | } |
3671 | } | |
3672 | /* write the addresses in reverse order to avoid write combining */ | |
3673 | for (; rar_entries > 0 ; rar_entries--) { | |
3674 | wr32(E1000_RAH(rar_entries), 0); | |
3675 | wr32(E1000_RAL(rar_entries), 0); | |
3676 | } | |
3677 | wrfl(); | |
3678 | ||
68d480c4 AD |
3679 | return count; |
3680 | } | |
3681 | ||
3682 | /** | |
3683 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set | |
3684 | * @netdev: network interface device structure | |
3685 | * | |
3686 | * The set_rx_mode entry point is called whenever the unicast or multicast | |
3687 | * address lists or the network interface flags are updated. This routine is | |
3688 | * responsible for configuring the hardware for proper unicast, multicast, | |
3689 | * promiscuous mode, and all-multi behavior. | |
3690 | **/ | |
3691 | static void igb_set_rx_mode(struct net_device *netdev) | |
3692 | { | |
3693 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3694 | struct e1000_hw *hw = &adapter->hw; | |
3695 | unsigned int vfn = adapter->vfs_allocated_count; | |
3696 | u32 rctl, vmolr = 0; | |
3697 | int count; | |
3698 | ||
3699 | /* Check for Promiscuous and All Multicast modes */ | |
3700 | rctl = rd32(E1000_RCTL); | |
3701 | ||
3702 | /* clear the effected bits */ | |
3703 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
3704 | ||
3705 | if (netdev->flags & IFF_PROMISC) { | |
3706 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3707 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
3708 | } else { | |
3709 | if (netdev->flags & IFF_ALLMULTI) { | |
3710 | rctl |= E1000_RCTL_MPE; | |
3711 | vmolr |= E1000_VMOLR_MPME; | |
3712 | } else { | |
3713 | /* | |
3714 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3715 | * then we should just turn on promiscuous mode so |
68d480c4 AD |
3716 | * that we can at least receive multicast traffic |
3717 | */ | |
3718 | count = igb_write_mc_addr_list(netdev); | |
3719 | if (count < 0) { | |
3720 | rctl |= E1000_RCTL_MPE; | |
3721 | vmolr |= E1000_VMOLR_MPME; | |
3722 | } else if (count) { | |
3723 | vmolr |= E1000_VMOLR_ROMPE; | |
3724 | } | |
3725 | } | |
3726 | /* | |
3727 | * Write addresses to available RAR registers, if there is not | |
3728 | * sufficient space to store all the addresses then enable | |
25985edc | 3729 | * unicast promiscuous mode |
68d480c4 AD |
3730 | */ |
3731 | count = igb_write_uc_addr_list(netdev); | |
3732 | if (count < 0) { | |
3733 | rctl |= E1000_RCTL_UPE; | |
3734 | vmolr |= E1000_VMOLR_ROPE; | |
3735 | } | |
3736 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 3737 | } |
68d480c4 | 3738 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 3739 | |
68d480c4 AD |
3740 | /* |
3741 | * In order to support SR-IOV and eventually VMDq it is necessary to set | |
3742 | * the VMOLR to enable the appropriate modes. Without this workaround | |
3743 | * we will have issues with VLAN tag stripping not being done for frames | |
3744 | * that are only arriving because we are the default pool | |
3745 | */ | |
f96a8a0b | 3746 | if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) |
28fc06f5 | 3747 | return; |
9d5c8243 | 3748 | |
68d480c4 AD |
3749 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
3750 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); | |
3751 | wr32(E1000_VMOLR(vfn), vmolr); | |
28fc06f5 | 3752 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
3753 | } |
3754 | ||
13800469 GR |
3755 | static void igb_check_wvbr(struct igb_adapter *adapter) |
3756 | { | |
3757 | struct e1000_hw *hw = &adapter->hw; | |
3758 | u32 wvbr = 0; | |
3759 | ||
3760 | switch (hw->mac.type) { | |
3761 | case e1000_82576: | |
3762 | case e1000_i350: | |
3763 | if (!(wvbr = rd32(E1000_WVBR))) | |
3764 | return; | |
3765 | break; | |
3766 | default: | |
3767 | break; | |
3768 | } | |
3769 | ||
3770 | adapter->wvbr |= wvbr; | |
3771 | } | |
3772 | ||
3773 | #define IGB_STAGGERED_QUEUE_OFFSET 8 | |
3774 | ||
3775 | static void igb_spoof_check(struct igb_adapter *adapter) | |
3776 | { | |
3777 | int j; | |
3778 | ||
3779 | if (!adapter->wvbr) | |
3780 | return; | |
3781 | ||
3782 | for(j = 0; j < adapter->vfs_allocated_count; j++) { | |
3783 | if (adapter->wvbr & (1 << j) || | |
3784 | adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { | |
3785 | dev_warn(&adapter->pdev->dev, | |
3786 | "Spoof event(s) detected on VF %d\n", j); | |
3787 | adapter->wvbr &= | |
3788 | ~((1 << j) | | |
3789 | (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); | |
3790 | } | |
3791 | } | |
3792 | } | |
3793 | ||
9d5c8243 AK |
3794 | /* Need to wait a few seconds after link up to get diagnostic information from |
3795 | * the phy */ | |
3796 | static void igb_update_phy_info(unsigned long data) | |
3797 | { | |
3798 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3799 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3800 | } |
3801 | ||
4d6b725e AD |
3802 | /** |
3803 | * igb_has_link - check shared code for link and determine up/down | |
3804 | * @adapter: pointer to driver private info | |
3805 | **/ | |
3145535a | 3806 | bool igb_has_link(struct igb_adapter *adapter) |
4d6b725e AD |
3807 | { |
3808 | struct e1000_hw *hw = &adapter->hw; | |
3809 | bool link_active = false; | |
3810 | s32 ret_val = 0; | |
3811 | ||
3812 | /* get_link_status is set on LSC (link status) interrupt or | |
3813 | * rx sequence error interrupt. get_link_status will stay | |
3814 | * false until the e1000_check_for_link establishes link | |
3815 | * for copper adapters ONLY | |
3816 | */ | |
3817 | switch (hw->phy.media_type) { | |
3818 | case e1000_media_type_copper: | |
3819 | if (hw->mac.get_link_status) { | |
3820 | ret_val = hw->mac.ops.check_for_link(hw); | |
3821 | link_active = !hw->mac.get_link_status; | |
3822 | } else { | |
3823 | link_active = true; | |
3824 | } | |
3825 | break; | |
4d6b725e AD |
3826 | case e1000_media_type_internal_serdes: |
3827 | ret_val = hw->mac.ops.check_for_link(hw); | |
3828 | link_active = hw->mac.serdes_has_link; | |
3829 | break; | |
3830 | default: | |
3831 | case e1000_media_type_unknown: | |
3832 | break; | |
3833 | } | |
3834 | ||
3835 | return link_active; | |
3836 | } | |
3837 | ||
563988dc SA |
3838 | static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) |
3839 | { | |
3840 | bool ret = false; | |
3841 | u32 ctrl_ext, thstat; | |
3842 | ||
f96a8a0b | 3843 | /* check for thermal sensor event on i350 copper only */ |
563988dc SA |
3844 | if (hw->mac.type == e1000_i350) { |
3845 | thstat = rd32(E1000_THSTAT); | |
3846 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
3847 | ||
3848 | if ((hw->phy.media_type == e1000_media_type_copper) && | |
3849 | !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { | |
3850 | ret = !!(thstat & event); | |
3851 | } | |
3852 | } | |
3853 | ||
3854 | return ret; | |
3855 | } | |
3856 | ||
9d5c8243 AK |
3857 | /** |
3858 | * igb_watchdog - Timer Call-back | |
3859 | * @data: pointer to adapter cast into an unsigned long | |
3860 | **/ | |
3861 | static void igb_watchdog(unsigned long data) | |
3862 | { | |
3863 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3864 | /* Do the rest outside of interrupt context */ | |
3865 | schedule_work(&adapter->watchdog_task); | |
3866 | } | |
3867 | ||
3868 | static void igb_watchdog_task(struct work_struct *work) | |
3869 | { | |
3870 | struct igb_adapter *adapter = container_of(work, | |
559e9c49 AD |
3871 | struct igb_adapter, |
3872 | watchdog_task); | |
9d5c8243 | 3873 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3874 | struct net_device *netdev = adapter->netdev; |
563988dc | 3875 | u32 link; |
7a6ea550 | 3876 | int i; |
9d5c8243 | 3877 | |
4d6b725e | 3878 | link = igb_has_link(adapter); |
9d5c8243 | 3879 | if (link) { |
749ab2cd YZ |
3880 | /* Cancel scheduled suspend requests. */ |
3881 | pm_runtime_resume(netdev->dev.parent); | |
3882 | ||
9d5c8243 AK |
3883 | if (!netif_carrier_ok(netdev)) { |
3884 | u32 ctrl; | |
330a6d6a AD |
3885 | hw->mac.ops.get_speed_and_duplex(hw, |
3886 | &adapter->link_speed, | |
3887 | &adapter->link_duplex); | |
9d5c8243 AK |
3888 | |
3889 | ctrl = rd32(E1000_CTRL); | |
527d47c1 | 3890 | /* Links status message must follow this format */ |
876d2d6f JK |
3891 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " |
3892 | "Duplex, Flow Control: %s\n", | |
559e9c49 AD |
3893 | netdev->name, |
3894 | adapter->link_speed, | |
3895 | adapter->link_duplex == FULL_DUPLEX ? | |
876d2d6f JK |
3896 | "Full" : "Half", |
3897 | (ctrl & E1000_CTRL_TFCE) && | |
3898 | (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : | |
3899 | (ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3900 | (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); | |
9d5c8243 | 3901 | |
563988dc | 3902 | /* check for thermal sensor event */ |
876d2d6f JK |
3903 | if (igb_thermal_sensor_event(hw, |
3904 | E1000_THSTAT_LINK_THROTTLE)) { | |
3905 | netdev_info(netdev, "The network adapter link " | |
3906 | "speed was downshifted because it " | |
3907 | "overheated\n"); | |
7ef5ed1c | 3908 | } |
563988dc | 3909 | |
d07f3e37 | 3910 | /* adjust timeout factor according to speed/duplex */ |
9d5c8243 AK |
3911 | adapter->tx_timeout_factor = 1; |
3912 | switch (adapter->link_speed) { | |
3913 | case SPEED_10: | |
9d5c8243 AK |
3914 | adapter->tx_timeout_factor = 14; |
3915 | break; | |
3916 | case SPEED_100: | |
9d5c8243 AK |
3917 | /* maybe add some timeout factor ? */ |
3918 | break; | |
3919 | } | |
3920 | ||
3921 | netif_carrier_on(netdev); | |
9d5c8243 | 3922 | |
4ae196df | 3923 | igb_ping_all_vfs(adapter); |
17dc566c | 3924 | igb_check_vf_rate_limit(adapter); |
4ae196df | 3925 | |
4b1a9877 | 3926 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3927 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3928 | mod_timer(&adapter->phy_info_timer, | |
3929 | round_jiffies(jiffies + 2 * HZ)); | |
3930 | } | |
3931 | } else { | |
3932 | if (netif_carrier_ok(netdev)) { | |
3933 | adapter->link_speed = 0; | |
3934 | adapter->link_duplex = 0; | |
563988dc SA |
3935 | |
3936 | /* check for thermal sensor event */ | |
876d2d6f JK |
3937 | if (igb_thermal_sensor_event(hw, |
3938 | E1000_THSTAT_PWR_DOWN)) { | |
3939 | netdev_err(netdev, "The network adapter was " | |
3940 | "stopped because it overheated\n"); | |
7ef5ed1c | 3941 | } |
563988dc | 3942 | |
527d47c1 AD |
3943 | /* Links status message must follow this format */ |
3944 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
3945 | netdev->name); | |
9d5c8243 | 3946 | netif_carrier_off(netdev); |
4b1a9877 | 3947 | |
4ae196df AD |
3948 | igb_ping_all_vfs(adapter); |
3949 | ||
4b1a9877 | 3950 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3951 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3952 | mod_timer(&adapter->phy_info_timer, | |
3953 | round_jiffies(jiffies + 2 * HZ)); | |
749ab2cd YZ |
3954 | |
3955 | pm_schedule_suspend(netdev->dev.parent, | |
3956 | MSEC_PER_SEC * 5); | |
9d5c8243 AK |
3957 | } |
3958 | } | |
3959 | ||
12dcd86b ED |
3960 | spin_lock(&adapter->stats64_lock); |
3961 | igb_update_stats(adapter, &adapter->stats64); | |
3962 | spin_unlock(&adapter->stats64_lock); | |
9d5c8243 | 3963 | |
dbabb065 | 3964 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 | 3965 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
dbabb065 | 3966 | if (!netif_carrier_ok(netdev)) { |
9d5c8243 AK |
3967 | /* We've lost link, so the controller stops DMA, |
3968 | * but we've got queued Tx work that's never going | |
3969 | * to get done, so reset controller to flush Tx. | |
3970 | * (Do the reset outside of interrupt context). */ | |
dbabb065 AD |
3971 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
3972 | adapter->tx_timeout_count++; | |
3973 | schedule_work(&adapter->reset_task); | |
3974 | /* return immediately since reset is imminent */ | |
3975 | return; | |
3976 | } | |
9d5c8243 | 3977 | } |
9d5c8243 | 3978 | |
dbabb065 | 3979 | /* Force detection of hung controller every watchdog period */ |
6d095fa8 | 3980 | set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
dbabb065 | 3981 | } |
f7ba205e | 3982 | |
9d5c8243 | 3983 | /* Cause software interrupt to ensure rx ring is cleaned */ |
7a6ea550 | 3984 | if (adapter->msix_entries) { |
047e0030 | 3985 | u32 eics = 0; |
0d1ae7f4 AD |
3986 | for (i = 0; i < adapter->num_q_vectors; i++) |
3987 | eics |= adapter->q_vector[i]->eims_value; | |
7a6ea550 AD |
3988 | wr32(E1000_EICS, eics); |
3989 | } else { | |
3990 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
3991 | } | |
9d5c8243 | 3992 | |
13800469 GR |
3993 | igb_spoof_check(adapter); |
3994 | ||
9d5c8243 AK |
3995 | /* Reset the timer */ |
3996 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3997 | mod_timer(&adapter->watchdog_timer, | |
3998 | round_jiffies(jiffies + 2 * HZ)); | |
3999 | } | |
4000 | ||
4001 | enum latency_range { | |
4002 | lowest_latency = 0, | |
4003 | low_latency = 1, | |
4004 | bulk_latency = 2, | |
4005 | latency_invalid = 255 | |
4006 | }; | |
4007 | ||
6eb5a7f1 AD |
4008 | /** |
4009 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
4010 | * | |
4011 | * Stores a new ITR value based on strictly on packet size. This | |
4012 | * algorithm is less sophisticated than that used in igb_update_itr, | |
4013 | * due to the difficulty of synchronizing statistics across multiple | |
eef35c2d | 4014 | * receive rings. The divisors and thresholds used by this function |
6eb5a7f1 AD |
4015 | * were determined based on theoretical maximum wire speed and testing |
4016 | * data, in order to minimize response time while increasing bulk | |
4017 | * throughput. | |
4018 | * This functionality is controlled by the InterruptThrottleRate module | |
4019 | * parameter (see igb_param.c) | |
4020 | * NOTE: This function is called only when operating in a multiqueue | |
4021 | * receive environment. | |
047e0030 | 4022 | * @q_vector: pointer to q_vector |
6eb5a7f1 | 4023 | **/ |
047e0030 | 4024 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4025 | { |
047e0030 | 4026 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 4027 | int avg_wire_size = 0; |
047e0030 | 4028 | struct igb_adapter *adapter = q_vector->adapter; |
12dcd86b | 4029 | unsigned int packets; |
9d5c8243 | 4030 | |
6eb5a7f1 AD |
4031 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
4032 | * ints/sec - ITR timer value of 120 ticks. | |
4033 | */ | |
4034 | if (adapter->link_speed != SPEED_1000) { | |
0ba82994 | 4035 | new_val = IGB_4K_ITR; |
6eb5a7f1 | 4036 | goto set_itr_val; |
9d5c8243 | 4037 | } |
047e0030 | 4038 | |
0ba82994 AD |
4039 | packets = q_vector->rx.total_packets; |
4040 | if (packets) | |
4041 | avg_wire_size = q_vector->rx.total_bytes / packets; | |
047e0030 | 4042 | |
0ba82994 AD |
4043 | packets = q_vector->tx.total_packets; |
4044 | if (packets) | |
4045 | avg_wire_size = max_t(u32, avg_wire_size, | |
4046 | q_vector->tx.total_bytes / packets); | |
047e0030 AD |
4047 | |
4048 | /* if avg_wire_size isn't set no work was done */ | |
4049 | if (!avg_wire_size) | |
4050 | goto clear_counts; | |
9d5c8243 | 4051 | |
6eb5a7f1 AD |
4052 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
4053 | avg_wire_size += 24; | |
4054 | ||
4055 | /* Don't starve jumbo frames */ | |
4056 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 4057 | |
6eb5a7f1 AD |
4058 | /* Give a little boost to mid-size frames */ |
4059 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
4060 | new_val = avg_wire_size / 3; | |
4061 | else | |
4062 | new_val = avg_wire_size / 2; | |
9d5c8243 | 4063 | |
0ba82994 AD |
4064 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
4065 | if (new_val < IGB_20K_ITR && | |
4066 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
4067 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
4068 | new_val = IGB_20K_ITR; | |
abe1c363 | 4069 | |
6eb5a7f1 | 4070 | set_itr_val: |
047e0030 AD |
4071 | if (new_val != q_vector->itr_val) { |
4072 | q_vector->itr_val = new_val; | |
4073 | q_vector->set_itr = 1; | |
9d5c8243 | 4074 | } |
6eb5a7f1 | 4075 | clear_counts: |
0ba82994 AD |
4076 | q_vector->rx.total_bytes = 0; |
4077 | q_vector->rx.total_packets = 0; | |
4078 | q_vector->tx.total_bytes = 0; | |
4079 | q_vector->tx.total_packets = 0; | |
9d5c8243 AK |
4080 | } |
4081 | ||
4082 | /** | |
4083 | * igb_update_itr - update the dynamic ITR value based on statistics | |
4084 | * Stores a new ITR value based on packets and byte | |
4085 | * counts during the last interrupt. The advantage of per interrupt | |
4086 | * computation is faster updates and more accurate ITR for the current | |
4087 | * traffic pattern. Constants in this function were computed | |
4088 | * based on theoretical maximum wire speed and thresholds were set based | |
4089 | * on testing data as well as attempting to minimize response time | |
4090 | * while increasing bulk throughput. | |
4091 | * this functionality is controlled by the InterruptThrottleRate module | |
4092 | * parameter (see igb_param.c) | |
4093 | * NOTE: These calculations are only valid when operating in a single- | |
4094 | * queue environment. | |
0ba82994 AD |
4095 | * @q_vector: pointer to q_vector |
4096 | * @ring_container: ring info to update the itr for | |
9d5c8243 | 4097 | **/ |
0ba82994 AD |
4098 | static void igb_update_itr(struct igb_q_vector *q_vector, |
4099 | struct igb_ring_container *ring_container) | |
9d5c8243 | 4100 | { |
0ba82994 AD |
4101 | unsigned int packets = ring_container->total_packets; |
4102 | unsigned int bytes = ring_container->total_bytes; | |
4103 | u8 itrval = ring_container->itr; | |
9d5c8243 | 4104 | |
0ba82994 | 4105 | /* no packets, exit with status unchanged */ |
9d5c8243 | 4106 | if (packets == 0) |
0ba82994 | 4107 | return; |
9d5c8243 | 4108 | |
0ba82994 | 4109 | switch (itrval) { |
9d5c8243 AK |
4110 | case lowest_latency: |
4111 | /* handle TSO and jumbo frames */ | |
4112 | if (bytes/packets > 8000) | |
0ba82994 | 4113 | itrval = bulk_latency; |
9d5c8243 | 4114 | else if ((packets < 5) && (bytes > 512)) |
0ba82994 | 4115 | itrval = low_latency; |
9d5c8243 AK |
4116 | break; |
4117 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
4118 | if (bytes > 10000) { | |
4119 | /* this if handles the TSO accounting */ | |
4120 | if (bytes/packets > 8000) { | |
0ba82994 | 4121 | itrval = bulk_latency; |
9d5c8243 | 4122 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { |
0ba82994 | 4123 | itrval = bulk_latency; |
9d5c8243 | 4124 | } else if ((packets > 35)) { |
0ba82994 | 4125 | itrval = lowest_latency; |
9d5c8243 AK |
4126 | } |
4127 | } else if (bytes/packets > 2000) { | |
0ba82994 | 4128 | itrval = bulk_latency; |
9d5c8243 | 4129 | } else if (packets <= 2 && bytes < 512) { |
0ba82994 | 4130 | itrval = lowest_latency; |
9d5c8243 AK |
4131 | } |
4132 | break; | |
4133 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
4134 | if (bytes > 25000) { | |
4135 | if (packets > 35) | |
0ba82994 | 4136 | itrval = low_latency; |
1e5c3d21 | 4137 | } else if (bytes < 1500) { |
0ba82994 | 4138 | itrval = low_latency; |
9d5c8243 AK |
4139 | } |
4140 | break; | |
4141 | } | |
4142 | ||
0ba82994 AD |
4143 | /* clear work counters since we have the values we need */ |
4144 | ring_container->total_bytes = 0; | |
4145 | ring_container->total_packets = 0; | |
4146 | ||
4147 | /* write updated itr to ring container */ | |
4148 | ring_container->itr = itrval; | |
9d5c8243 AK |
4149 | } |
4150 | ||
0ba82994 | 4151 | static void igb_set_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4152 | { |
0ba82994 | 4153 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 4154 | u32 new_itr = q_vector->itr_val; |
0ba82994 | 4155 | u8 current_itr = 0; |
9d5c8243 AK |
4156 | |
4157 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
4158 | if (adapter->link_speed != SPEED_1000) { | |
4159 | current_itr = 0; | |
0ba82994 | 4160 | new_itr = IGB_4K_ITR; |
9d5c8243 AK |
4161 | goto set_itr_now; |
4162 | } | |
4163 | ||
0ba82994 AD |
4164 | igb_update_itr(q_vector, &q_vector->tx); |
4165 | igb_update_itr(q_vector, &q_vector->rx); | |
9d5c8243 | 4166 | |
0ba82994 | 4167 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
9d5c8243 | 4168 | |
6eb5a7f1 | 4169 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
0ba82994 AD |
4170 | if (current_itr == lowest_latency && |
4171 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
4172 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
6eb5a7f1 AD |
4173 | current_itr = low_latency; |
4174 | ||
9d5c8243 AK |
4175 | switch (current_itr) { |
4176 | /* counts and packets in update_itr are dependent on these numbers */ | |
4177 | case lowest_latency: | |
0ba82994 | 4178 | new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ |
9d5c8243 AK |
4179 | break; |
4180 | case low_latency: | |
0ba82994 | 4181 | new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ |
9d5c8243 AK |
4182 | break; |
4183 | case bulk_latency: | |
0ba82994 | 4184 | new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ |
9d5c8243 AK |
4185 | break; |
4186 | default: | |
4187 | break; | |
4188 | } | |
4189 | ||
4190 | set_itr_now: | |
047e0030 | 4191 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
4192 | /* this attempts to bias the interrupt rate towards Bulk |
4193 | * by adding intermediate steps when interrupt rate is | |
4194 | * increasing */ | |
047e0030 AD |
4195 | new_itr = new_itr > q_vector->itr_val ? |
4196 | max((new_itr * q_vector->itr_val) / | |
4197 | (new_itr + (q_vector->itr_val >> 2)), | |
0ba82994 | 4198 | new_itr) : |
9d5c8243 AK |
4199 | new_itr; |
4200 | /* Don't write the value here; it resets the adapter's | |
4201 | * internal timer, and causes us to delay far longer than | |
4202 | * we should between interrupts. Instead, we write the ITR | |
4203 | * value at the beginning of the next interrupt so the timing | |
4204 | * ends up being correct. | |
4205 | */ | |
047e0030 AD |
4206 | q_vector->itr_val = new_itr; |
4207 | q_vector->set_itr = 1; | |
9d5c8243 | 4208 | } |
9d5c8243 AK |
4209 | } |
4210 | ||
c50b52a0 SH |
4211 | static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, |
4212 | u32 type_tucmd, u32 mss_l4len_idx) | |
7d13a7d0 AD |
4213 | { |
4214 | struct e1000_adv_tx_context_desc *context_desc; | |
4215 | u16 i = tx_ring->next_to_use; | |
4216 | ||
4217 | context_desc = IGB_TX_CTXTDESC(tx_ring, i); | |
4218 | ||
4219 | i++; | |
4220 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
4221 | ||
4222 | /* set bits to identify this as an advanced context descriptor */ | |
4223 | type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; | |
4224 | ||
4225 | /* For 82575, context index must be unique per ring. */ | |
866cff06 | 4226 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
7d13a7d0 AD |
4227 | mss_l4len_idx |= tx_ring->reg_idx << 4; |
4228 | ||
4229 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4230 | context_desc->seqnum_seed = 0; | |
4231 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
4232 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
4233 | } | |
4234 | ||
7af40ad9 AD |
4235 | static int igb_tso(struct igb_ring *tx_ring, |
4236 | struct igb_tx_buffer *first, | |
4237 | u8 *hdr_len) | |
9d5c8243 | 4238 | { |
7af40ad9 | 4239 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4240 | u32 vlan_macip_lens, type_tucmd; |
4241 | u32 mss_l4len_idx, l4len; | |
4242 | ||
ed6aa105 AD |
4243 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
4244 | return 0; | |
4245 | ||
7d13a7d0 AD |
4246 | if (!skb_is_gso(skb)) |
4247 | return 0; | |
9d5c8243 AK |
4248 | |
4249 | if (skb_header_cloned(skb)) { | |
7af40ad9 | 4250 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
9d5c8243 AK |
4251 | if (err) |
4252 | return err; | |
4253 | } | |
4254 | ||
7d13a7d0 AD |
4255 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
4256 | type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; | |
9d5c8243 | 4257 | |
7af40ad9 | 4258 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
9d5c8243 AK |
4259 | struct iphdr *iph = ip_hdr(skb); |
4260 | iph->tot_len = 0; | |
4261 | iph->check = 0; | |
4262 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
4263 | iph->daddr, 0, | |
4264 | IPPROTO_TCP, | |
4265 | 0); | |
7d13a7d0 | 4266 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
7af40ad9 AD |
4267 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4268 | IGB_TX_FLAGS_CSUM | | |
4269 | IGB_TX_FLAGS_IPV4; | |
8e1e8a47 | 4270 | } else if (skb_is_gso_v6(skb)) { |
9d5c8243 AK |
4271 | ipv6_hdr(skb)->payload_len = 0; |
4272 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
4273 | &ipv6_hdr(skb)->daddr, | |
4274 | 0, IPPROTO_TCP, 0); | |
7af40ad9 AD |
4275 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4276 | IGB_TX_FLAGS_CSUM; | |
9d5c8243 AK |
4277 | } |
4278 | ||
7af40ad9 | 4279 | /* compute header lengths */ |
7d13a7d0 AD |
4280 | l4len = tcp_hdrlen(skb); |
4281 | *hdr_len = skb_transport_offset(skb) + l4len; | |
9d5c8243 | 4282 | |
7af40ad9 AD |
4283 | /* update gso size and bytecount with header size */ |
4284 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
4285 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
4286 | ||
9d5c8243 | 4287 | /* MSS L4LEN IDX */ |
7d13a7d0 AD |
4288 | mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; |
4289 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; | |
9d5c8243 | 4290 | |
7d13a7d0 AD |
4291 | /* VLAN MACLEN IPLEN */ |
4292 | vlan_macip_lens = skb_network_header_len(skb); | |
4293 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; | |
7af40ad9 | 4294 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4295 | |
7d13a7d0 | 4296 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 | 4297 | |
7d13a7d0 | 4298 | return 1; |
9d5c8243 AK |
4299 | } |
4300 | ||
7af40ad9 | 4301 | static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) |
9d5c8243 | 4302 | { |
7af40ad9 | 4303 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4304 | u32 vlan_macip_lens = 0; |
4305 | u32 mss_l4len_idx = 0; | |
4306 | u32 type_tucmd = 0; | |
9d5c8243 | 4307 | |
7d13a7d0 | 4308 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7af40ad9 AD |
4309 | if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) |
4310 | return; | |
7d13a7d0 AD |
4311 | } else { |
4312 | u8 l4_hdr = 0; | |
7af40ad9 | 4313 | switch (first->protocol) { |
7d13a7d0 AD |
4314 | case __constant_htons(ETH_P_IP): |
4315 | vlan_macip_lens |= skb_network_header_len(skb); | |
4316 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; | |
4317 | l4_hdr = ip_hdr(skb)->protocol; | |
4318 | break; | |
4319 | case __constant_htons(ETH_P_IPV6): | |
4320 | vlan_macip_lens |= skb_network_header_len(skb); | |
4321 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
4322 | break; | |
4323 | default: | |
4324 | if (unlikely(net_ratelimit())) { | |
4325 | dev_warn(tx_ring->dev, | |
4326 | "partial checksum but proto=%x!\n", | |
7af40ad9 | 4327 | first->protocol); |
fa4a7ef3 | 4328 | } |
7d13a7d0 AD |
4329 | break; |
4330 | } | |
fa4a7ef3 | 4331 | |
7d13a7d0 AD |
4332 | switch (l4_hdr) { |
4333 | case IPPROTO_TCP: | |
4334 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
4335 | mss_l4len_idx = tcp_hdrlen(skb) << | |
4336 | E1000_ADVTXD_L4LEN_SHIFT; | |
4337 | break; | |
4338 | case IPPROTO_SCTP: | |
4339 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
4340 | mss_l4len_idx = sizeof(struct sctphdr) << | |
4341 | E1000_ADVTXD_L4LEN_SHIFT; | |
4342 | break; | |
4343 | case IPPROTO_UDP: | |
4344 | mss_l4len_idx = sizeof(struct udphdr) << | |
4345 | E1000_ADVTXD_L4LEN_SHIFT; | |
4346 | break; | |
4347 | default: | |
4348 | if (unlikely(net_ratelimit())) { | |
4349 | dev_warn(tx_ring->dev, | |
4350 | "partial checksum but l4 proto=%x!\n", | |
4351 | l4_hdr); | |
44b0cda3 | 4352 | } |
7d13a7d0 | 4353 | break; |
9d5c8243 | 4354 | } |
7af40ad9 AD |
4355 | |
4356 | /* update TX checksum flag */ | |
4357 | first->tx_flags |= IGB_TX_FLAGS_CSUM; | |
7d13a7d0 | 4358 | } |
9d5c8243 | 4359 | |
7d13a7d0 | 4360 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
7af40ad9 | 4361 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4362 | |
7d13a7d0 | 4363 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 AK |
4364 | } |
4365 | ||
1d9daf45 AD |
4366 | #define IGB_SET_FLAG(_input, _flag, _result) \ |
4367 | ((_flag <= _result) ? \ | |
4368 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
4369 | ((u32)(_input & _flag) / (_flag / _result))) | |
4370 | ||
4371 | static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) | |
e032afc8 AD |
4372 | { |
4373 | /* set type for advanced descriptor with frame checksum insertion */ | |
1d9daf45 AD |
4374 | u32 cmd_type = E1000_ADVTXD_DTYP_DATA | |
4375 | E1000_ADVTXD_DCMD_DEXT | | |
4376 | E1000_ADVTXD_DCMD_IFCS; | |
e032afc8 AD |
4377 | |
4378 | /* set HW vlan bit if vlan is present */ | |
1d9daf45 AD |
4379 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, |
4380 | (E1000_ADVTXD_DCMD_VLE)); | |
4381 | ||
4382 | /* set segmentation bits for TSO */ | |
4383 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, | |
4384 | (E1000_ADVTXD_DCMD_TSE)); | |
e032afc8 AD |
4385 | |
4386 | /* set timestamp bit if present */ | |
1d9daf45 AD |
4387 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, |
4388 | (E1000_ADVTXD_MAC_TSTAMP)); | |
e032afc8 | 4389 | |
1d9daf45 AD |
4390 | /* insert frame checksum */ |
4391 | cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); | |
e032afc8 AD |
4392 | |
4393 | return cmd_type; | |
4394 | } | |
4395 | ||
7af40ad9 AD |
4396 | static void igb_tx_olinfo_status(struct igb_ring *tx_ring, |
4397 | union e1000_adv_tx_desc *tx_desc, | |
4398 | u32 tx_flags, unsigned int paylen) | |
e032afc8 AD |
4399 | { |
4400 | u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; | |
4401 | ||
1d9daf45 AD |
4402 | /* 82575 requires a unique index per ring */ |
4403 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) | |
e032afc8 AD |
4404 | olinfo_status |= tx_ring->reg_idx << 4; |
4405 | ||
4406 | /* insert L4 checksum */ | |
1d9daf45 AD |
4407 | olinfo_status |= IGB_SET_FLAG(tx_flags, |
4408 | IGB_TX_FLAGS_CSUM, | |
4409 | (E1000_TXD_POPTS_TXSM << 8)); | |
e032afc8 | 4410 | |
1d9daf45 AD |
4411 | /* insert IPv4 checksum */ |
4412 | olinfo_status |= IGB_SET_FLAG(tx_flags, | |
4413 | IGB_TX_FLAGS_IPV4, | |
4414 | (E1000_TXD_POPTS_IXSM << 8)); | |
e032afc8 | 4415 | |
7af40ad9 | 4416 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
e032afc8 AD |
4417 | } |
4418 | ||
ebe42d16 AD |
4419 | /* |
4420 | * The largest size we can write to the descriptor is 65535. In order to | |
4421 | * maintain a power of two alignment we have to limit ourselves to 32K. | |
4422 | */ | |
4423 | #define IGB_MAX_TXD_PWR 15 | |
7af40ad9 | 4424 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) |
9d5c8243 | 4425 | |
7af40ad9 AD |
4426 | static void igb_tx_map(struct igb_ring *tx_ring, |
4427 | struct igb_tx_buffer *first, | |
ebe42d16 | 4428 | const u8 hdr_len) |
9d5c8243 | 4429 | { |
7af40ad9 | 4430 | struct sk_buff *skb = first->skb; |
c9f14bf3 | 4431 | struct igb_tx_buffer *tx_buffer; |
ebe42d16 | 4432 | union e1000_adv_tx_desc *tx_desc; |
80d0759e | 4433 | struct skb_frag_struct *frag; |
ebe42d16 | 4434 | dma_addr_t dma; |
80d0759e | 4435 | unsigned int data_len, size; |
7af40ad9 | 4436 | u32 tx_flags = first->tx_flags; |
1d9daf45 | 4437 | u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); |
ebe42d16 | 4438 | u16 i = tx_ring->next_to_use; |
ebe42d16 AD |
4439 | |
4440 | tx_desc = IGB_TX_DESC(tx_ring, i); | |
4441 | ||
80d0759e AD |
4442 | igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); |
4443 | ||
4444 | size = skb_headlen(skb); | |
4445 | data_len = skb->data_len; | |
ebe42d16 AD |
4446 | |
4447 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
9d5c8243 | 4448 | |
80d0759e AD |
4449 | tx_buffer = first; |
4450 | ||
4451 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
4452 | if (dma_mapping_error(tx_ring->dev, dma)) | |
4453 | goto dma_error; | |
4454 | ||
4455 | /* record length, and DMA address */ | |
4456 | dma_unmap_len_set(tx_buffer, len, size); | |
4457 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
4458 | ||
4459 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
ebe42d16 | 4460 | |
ebe42d16 AD |
4461 | while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { |
4462 | tx_desc->read.cmd_type_len = | |
1d9daf45 | 4463 | cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); |
ebe42d16 AD |
4464 | |
4465 | i++; | |
4466 | tx_desc++; | |
4467 | if (i == tx_ring->count) { | |
4468 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
4469 | i = 0; | |
4470 | } | |
80d0759e | 4471 | tx_desc->read.olinfo_status = 0; |
ebe42d16 AD |
4472 | |
4473 | dma += IGB_MAX_DATA_PER_TXD; | |
4474 | size -= IGB_MAX_DATA_PER_TXD; | |
4475 | ||
ebe42d16 AD |
4476 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
4477 | } | |
4478 | ||
4479 | if (likely(!data_len)) | |
4480 | break; | |
2bbfebe2 | 4481 | |
1d9daf45 | 4482 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
9d5c8243 | 4483 | |
65689fef | 4484 | i++; |
ebe42d16 AD |
4485 | tx_desc++; |
4486 | if (i == tx_ring->count) { | |
4487 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
65689fef | 4488 | i = 0; |
ebe42d16 | 4489 | } |
80d0759e | 4490 | tx_desc->read.olinfo_status = 0; |
65689fef | 4491 | |
9e903e08 | 4492 | size = skb_frag_size(frag); |
ebe42d16 AD |
4493 | data_len -= size; |
4494 | ||
4495 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, | |
80d0759e | 4496 | size, DMA_TO_DEVICE); |
6366ad33 | 4497 | |
c9f14bf3 | 4498 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
9d5c8243 AK |
4499 | } |
4500 | ||
ebe42d16 | 4501 | /* write last descriptor with RS and EOP bits */ |
1d9daf45 AD |
4502 | cmd_type |= size | IGB_TXD_DCMD; |
4503 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
8542db05 | 4504 | |
80d0759e AD |
4505 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
4506 | ||
8542db05 AD |
4507 | /* set the timestamp */ |
4508 | first->time_stamp = jiffies; | |
4509 | ||
ebe42d16 AD |
4510 | /* |
4511 | * Force memory writes to complete before letting h/w know there | |
4512 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
4513 | * memory model archs, such as IA-64). | |
4514 | * | |
4515 | * We also need this memory barrier to make certain all of the | |
4516 | * status bits have been updated before next_to_watch is written. | |
4517 | */ | |
4518 | wmb(); | |
4519 | ||
8542db05 | 4520 | /* set next_to_watch value indicating a packet is present */ |
ebe42d16 | 4521 | first->next_to_watch = tx_desc; |
9d5c8243 | 4522 | |
ebe42d16 AD |
4523 | i++; |
4524 | if (i == tx_ring->count) | |
4525 | i = 0; | |
6366ad33 | 4526 | |
ebe42d16 | 4527 | tx_ring->next_to_use = i; |
6366ad33 | 4528 | |
ebe42d16 | 4529 | writel(i, tx_ring->tail); |
6366ad33 | 4530 | |
ebe42d16 AD |
4531 | /* we need this if more than one processor can write to our tail |
4532 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
4533 | mmiowb(); | |
4534 | ||
4535 | return; | |
4536 | ||
4537 | dma_error: | |
4538 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
4539 | ||
4540 | /* clear dma mappings for failed tx_buffer_info map */ | |
4541 | for (;;) { | |
c9f14bf3 AD |
4542 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
4543 | igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
4544 | if (tx_buffer == first) | |
ebe42d16 | 4545 | break; |
a77ff709 NN |
4546 | if (i == 0) |
4547 | i = tx_ring->count; | |
6366ad33 | 4548 | i--; |
6366ad33 AD |
4549 | } |
4550 | ||
9d5c8243 | 4551 | tx_ring->next_to_use = i; |
9d5c8243 AK |
4552 | } |
4553 | ||
6ad4edfc | 4554 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4555 | { |
e694e964 AD |
4556 | struct net_device *netdev = tx_ring->netdev; |
4557 | ||
661086df | 4558 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 4559 | |
9d5c8243 AK |
4560 | /* Herbert's original patch had: |
4561 | * smp_mb__after_netif_stop_queue(); | |
4562 | * but since that doesn't exist yet, just open code it. */ | |
4563 | smp_mb(); | |
4564 | ||
4565 | /* We need to check again in a case another CPU has just | |
4566 | * made room available. */ | |
c493ea45 | 4567 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
4568 | return -EBUSY; |
4569 | ||
4570 | /* A reprieve! */ | |
661086df | 4571 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
12dcd86b ED |
4572 | |
4573 | u64_stats_update_begin(&tx_ring->tx_syncp2); | |
4574 | tx_ring->tx_stats.restart_queue2++; | |
4575 | u64_stats_update_end(&tx_ring->tx_syncp2); | |
4576 | ||
9d5c8243 AK |
4577 | return 0; |
4578 | } | |
4579 | ||
6ad4edfc | 4580 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4581 | { |
c493ea45 | 4582 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 4583 | return 0; |
e694e964 | 4584 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
4585 | } |
4586 | ||
cd392f5c AD |
4587 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, |
4588 | struct igb_ring *tx_ring) | |
9d5c8243 | 4589 | { |
1f6e8178 | 4590 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); |
8542db05 | 4591 | struct igb_tx_buffer *first; |
ebe42d16 | 4592 | int tso; |
91d4ee33 | 4593 | u32 tx_flags = 0; |
31f6adbb | 4594 | __be16 protocol = vlan_get_protocol(skb); |
91d4ee33 | 4595 | u8 hdr_len = 0; |
9d5c8243 | 4596 | |
9d5c8243 AK |
4597 | /* need: 1 descriptor per page, |
4598 | * + 2 desc gap to keep tail from touching head, | |
4599 | * + 1 desc for skb->data, | |
4600 | * + 1 desc for context descriptor, | |
4601 | * otherwise try next time */ | |
e694e964 | 4602 | if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { |
9d5c8243 | 4603 | /* this is a hard error */ |
9d5c8243 AK |
4604 | return NETDEV_TX_BUSY; |
4605 | } | |
33af6bcc | 4606 | |
7af40ad9 AD |
4607 | /* record the location of the first descriptor for this packet */ |
4608 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
4609 | first->skb = skb; | |
4610 | first->bytecount = skb->len; | |
4611 | first->gso_segs = 1; | |
4612 | ||
b66e2397 MV |
4613 | skb_tx_timestamp(skb); |
4614 | ||
1f6e8178 MV |
4615 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
4616 | !(adapter->ptp_tx_skb))) { | |
2244d07b | 4617 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
33af6bcc | 4618 | tx_flags |= IGB_TX_FLAGS_TSTAMP; |
1f6e8178 MV |
4619 | |
4620 | adapter->ptp_tx_skb = skb_get(skb); | |
4621 | if (adapter->hw.mac.type == e1000_82576) | |
4622 | schedule_work(&adapter->ptp_tx_work); | |
33af6bcc | 4623 | } |
9d5c8243 | 4624 | |
eab6d18d | 4625 | if (vlan_tx_tag_present(skb)) { |
9d5c8243 AK |
4626 | tx_flags |= IGB_TX_FLAGS_VLAN; |
4627 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
4628 | } | |
4629 | ||
7af40ad9 AD |
4630 | /* record initial flags and protocol */ |
4631 | first->tx_flags = tx_flags; | |
4632 | first->protocol = protocol; | |
cdfd01fc | 4633 | |
7af40ad9 AD |
4634 | tso = igb_tso(tx_ring, first, &hdr_len); |
4635 | if (tso < 0) | |
7d13a7d0 | 4636 | goto out_drop; |
7af40ad9 AD |
4637 | else if (!tso) |
4638 | igb_tx_csum(tx_ring, first); | |
9d5c8243 | 4639 | |
7af40ad9 | 4640 | igb_tx_map(tx_ring, first, hdr_len); |
85ad76b2 AD |
4641 | |
4642 | /* Make sure there is space in the ring for the next send. */ | |
e694e964 | 4643 | igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); |
85ad76b2 | 4644 | |
9d5c8243 | 4645 | return NETDEV_TX_OK; |
7d13a7d0 AD |
4646 | |
4647 | out_drop: | |
7af40ad9 AD |
4648 | igb_unmap_and_free_tx_resource(tx_ring, first); |
4649 | ||
7d13a7d0 | 4650 | return NETDEV_TX_OK; |
9d5c8243 AK |
4651 | } |
4652 | ||
1cc3bd87 AD |
4653 | static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, |
4654 | struct sk_buff *skb) | |
4655 | { | |
4656 | unsigned int r_idx = skb->queue_mapping; | |
4657 | ||
4658 | if (r_idx >= adapter->num_tx_queues) | |
4659 | r_idx = r_idx % adapter->num_tx_queues; | |
4660 | ||
4661 | return adapter->tx_ring[r_idx]; | |
4662 | } | |
4663 | ||
cd392f5c AD |
4664 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, |
4665 | struct net_device *netdev) | |
9d5c8243 AK |
4666 | { |
4667 | struct igb_adapter *adapter = netdev_priv(netdev); | |
b1a436c3 AD |
4668 | |
4669 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4670 | dev_kfree_skb_any(skb); | |
4671 | return NETDEV_TX_OK; | |
4672 | } | |
4673 | ||
4674 | if (skb->len <= 0) { | |
4675 | dev_kfree_skb_any(skb); | |
4676 | return NETDEV_TX_OK; | |
4677 | } | |
4678 | ||
1cc3bd87 AD |
4679 | /* |
4680 | * The minimum packet size with TCTL.PSP set is 17 so pad the skb | |
4681 | * in order to meet this minimum size requirement. | |
4682 | */ | |
ea5ceeab TD |
4683 | if (unlikely(skb->len < 17)) { |
4684 | if (skb_pad(skb, 17 - skb->len)) | |
1cc3bd87 AD |
4685 | return NETDEV_TX_OK; |
4686 | skb->len = 17; | |
ea5ceeab | 4687 | skb_set_tail_pointer(skb, 17); |
1cc3bd87 | 4688 | } |
9d5c8243 | 4689 | |
1cc3bd87 | 4690 | return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); |
9d5c8243 AK |
4691 | } |
4692 | ||
4693 | /** | |
4694 | * igb_tx_timeout - Respond to a Tx Hang | |
4695 | * @netdev: network interface device structure | |
4696 | **/ | |
4697 | static void igb_tx_timeout(struct net_device *netdev) | |
4698 | { | |
4699 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4700 | struct e1000_hw *hw = &adapter->hw; | |
4701 | ||
4702 | /* Do the reset outside of interrupt context */ | |
4703 | adapter->tx_timeout_count++; | |
f7ba205e | 4704 | |
06218a8d | 4705 | if (hw->mac.type >= e1000_82580) |
55cac248 AD |
4706 | hw->dev_spec._82575.global_device_reset = true; |
4707 | ||
9d5c8243 | 4708 | schedule_work(&adapter->reset_task); |
265de409 AD |
4709 | wr32(E1000_EICS, |
4710 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
4711 | } |
4712 | ||
4713 | static void igb_reset_task(struct work_struct *work) | |
4714 | { | |
4715 | struct igb_adapter *adapter; | |
4716 | adapter = container_of(work, struct igb_adapter, reset_task); | |
4717 | ||
c97ec42a TI |
4718 | igb_dump(adapter); |
4719 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
9d5c8243 AK |
4720 | igb_reinit_locked(adapter); |
4721 | } | |
4722 | ||
4723 | /** | |
12dcd86b | 4724 | * igb_get_stats64 - Get System Network Statistics |
9d5c8243 | 4725 | * @netdev: network interface device structure |
12dcd86b | 4726 | * @stats: rtnl_link_stats64 pointer |
9d5c8243 | 4727 | * |
9d5c8243 | 4728 | **/ |
12dcd86b ED |
4729 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, |
4730 | struct rtnl_link_stats64 *stats) | |
9d5c8243 | 4731 | { |
12dcd86b ED |
4732 | struct igb_adapter *adapter = netdev_priv(netdev); |
4733 | ||
4734 | spin_lock(&adapter->stats64_lock); | |
4735 | igb_update_stats(adapter, &adapter->stats64); | |
4736 | memcpy(stats, &adapter->stats64, sizeof(*stats)); | |
4737 | spin_unlock(&adapter->stats64_lock); | |
4738 | ||
4739 | return stats; | |
9d5c8243 AK |
4740 | } |
4741 | ||
4742 | /** | |
4743 | * igb_change_mtu - Change the Maximum Transfer Unit | |
4744 | * @netdev: network interface device structure | |
4745 | * @new_mtu: new value for maximum frame size | |
4746 | * | |
4747 | * Returns 0 on success, negative on failure | |
4748 | **/ | |
4749 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
4750 | { | |
4751 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4752 | struct pci_dev *pdev = adapter->pdev; |
153285f9 | 4753 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
9d5c8243 | 4754 | |
c809d227 | 4755 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 4756 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
4757 | return -EINVAL; |
4758 | } | |
4759 | ||
153285f9 | 4760 | #define MAX_STD_JUMBO_FRAME_SIZE 9238 |
9d5c8243 | 4761 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 4762 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
4763 | return -EINVAL; |
4764 | } | |
4765 | ||
4766 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
4767 | msleep(1); | |
73cd78f1 | 4768 | |
9d5c8243 AK |
4769 | /* igb_down has a dependency on max_frame_size */ |
4770 | adapter->max_frame_size = max_frame; | |
559e9c49 | 4771 | |
4c844851 AD |
4772 | if (netif_running(netdev)) |
4773 | igb_down(adapter); | |
9d5c8243 | 4774 | |
090b1795 | 4775 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
4776 | netdev->mtu, new_mtu); |
4777 | netdev->mtu = new_mtu; | |
4778 | ||
4779 | if (netif_running(netdev)) | |
4780 | igb_up(adapter); | |
4781 | else | |
4782 | igb_reset(adapter); | |
4783 | ||
4784 | clear_bit(__IGB_RESETTING, &adapter->state); | |
4785 | ||
4786 | return 0; | |
4787 | } | |
4788 | ||
4789 | /** | |
4790 | * igb_update_stats - Update the board statistics counters | |
4791 | * @adapter: board private structure | |
4792 | **/ | |
4793 | ||
12dcd86b ED |
4794 | void igb_update_stats(struct igb_adapter *adapter, |
4795 | struct rtnl_link_stats64 *net_stats) | |
9d5c8243 AK |
4796 | { |
4797 | struct e1000_hw *hw = &adapter->hw; | |
4798 | struct pci_dev *pdev = adapter->pdev; | |
fa3d9a6d | 4799 | u32 reg, mpc; |
9d5c8243 | 4800 | u16 phy_tmp; |
3f9c0164 AD |
4801 | int i; |
4802 | u64 bytes, packets; | |
12dcd86b ED |
4803 | unsigned int start; |
4804 | u64 _bytes, _packets; | |
9d5c8243 AK |
4805 | |
4806 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
4807 | ||
4808 | /* | |
4809 | * Prevent stats update while adapter is being reset, or if the pci | |
4810 | * connection is down. | |
4811 | */ | |
4812 | if (adapter->link_speed == 0) | |
4813 | return; | |
4814 | if (pci_channel_offline(pdev)) | |
4815 | return; | |
4816 | ||
3f9c0164 AD |
4817 | bytes = 0; |
4818 | packets = 0; | |
4819 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
ae1c07a6 | 4820 | u32 rqdpc = rd32(E1000_RQDPC(i)); |
3025a446 | 4821 | struct igb_ring *ring = adapter->rx_ring[i]; |
12dcd86b | 4822 | |
ae1c07a6 AD |
4823 | if (rqdpc) { |
4824 | ring->rx_stats.drops += rqdpc; | |
4825 | net_stats->rx_fifo_errors += rqdpc; | |
4826 | } | |
12dcd86b ED |
4827 | |
4828 | do { | |
4829 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
4830 | _bytes = ring->rx_stats.bytes; | |
4831 | _packets = ring->rx_stats.packets; | |
4832 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
4833 | bytes += _bytes; | |
4834 | packets += _packets; | |
3f9c0164 AD |
4835 | } |
4836 | ||
128e45eb AD |
4837 | net_stats->rx_bytes = bytes; |
4838 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
4839 | |
4840 | bytes = 0; | |
4841 | packets = 0; | |
4842 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 4843 | struct igb_ring *ring = adapter->tx_ring[i]; |
12dcd86b ED |
4844 | do { |
4845 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
4846 | _bytes = ring->tx_stats.bytes; | |
4847 | _packets = ring->tx_stats.packets; | |
4848 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
4849 | bytes += _bytes; | |
4850 | packets += _packets; | |
3f9c0164 | 4851 | } |
128e45eb AD |
4852 | net_stats->tx_bytes = bytes; |
4853 | net_stats->tx_packets = packets; | |
3f9c0164 AD |
4854 | |
4855 | /* read stats registers */ | |
9d5c8243 AK |
4856 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
4857 | adapter->stats.gprc += rd32(E1000_GPRC); | |
4858 | adapter->stats.gorc += rd32(E1000_GORCL); | |
4859 | rd32(E1000_GORCH); /* clear GORCL */ | |
4860 | adapter->stats.bprc += rd32(E1000_BPRC); | |
4861 | adapter->stats.mprc += rd32(E1000_MPRC); | |
4862 | adapter->stats.roc += rd32(E1000_ROC); | |
4863 | ||
4864 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
4865 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
4866 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
4867 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
4868 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
4869 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
4870 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
4871 | adapter->stats.sec += rd32(E1000_SEC); | |
4872 | ||
fa3d9a6d MW |
4873 | mpc = rd32(E1000_MPC); |
4874 | adapter->stats.mpc += mpc; | |
4875 | net_stats->rx_fifo_errors += mpc; | |
9d5c8243 AK |
4876 | adapter->stats.scc += rd32(E1000_SCC); |
4877 | adapter->stats.ecol += rd32(E1000_ECOL); | |
4878 | adapter->stats.mcc += rd32(E1000_MCC); | |
4879 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
4880 | adapter->stats.dc += rd32(E1000_DC); | |
4881 | adapter->stats.rlec += rd32(E1000_RLEC); | |
4882 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
4883 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
4884 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
4885 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
4886 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
4887 | adapter->stats.gptc += rd32(E1000_GPTC); | |
4888 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
4889 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
fa3d9a6d | 4890 | adapter->stats.rnbc += rd32(E1000_RNBC); |
9d5c8243 AK |
4891 | adapter->stats.ruc += rd32(E1000_RUC); |
4892 | adapter->stats.rfc += rd32(E1000_RFC); | |
4893 | adapter->stats.rjc += rd32(E1000_RJC); | |
4894 | adapter->stats.tor += rd32(E1000_TORH); | |
4895 | adapter->stats.tot += rd32(E1000_TOTH); | |
4896 | adapter->stats.tpr += rd32(E1000_TPR); | |
4897 | ||
4898 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
4899 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
4900 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
4901 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
4902 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4903 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4904 | ||
4905 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4906 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4907 | ||
2d0b0f69 NN |
4908 | adapter->stats.tpt += rd32(E1000_TPT); |
4909 | adapter->stats.colc += rd32(E1000_COLC); | |
9d5c8243 AK |
4910 | |
4911 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
43915c7c NN |
4912 | /* read internal phy specific stats */ |
4913 | reg = rd32(E1000_CTRL_EXT); | |
4914 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | |
4915 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3dbdf969 CW |
4916 | |
4917 | /* this stat has invalid values on i210/i211 */ | |
4918 | if ((hw->mac.type != e1000_i210) && | |
4919 | (hw->mac.type != e1000_i211)) | |
4920 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
43915c7c NN |
4921 | } |
4922 | ||
9d5c8243 AK |
4923 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
4924 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
4925 | ||
4926 | adapter->stats.iac += rd32(E1000_IAC); | |
4927 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
4928 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
4929 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
4930 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
4931 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
4932 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
4933 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
4934 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
4935 | ||
4936 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
4937 | net_stats->multicast = adapter->stats.mprc; |
4938 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
4939 | |
4940 | /* Rx Errors */ | |
4941 | ||
4942 | /* RLEC on some newer hardware can be incorrect so build | |
8c0ab70a | 4943 | * our own version based on RUC and ROC */ |
128e45eb | 4944 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
4945 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4946 | adapter->stats.ruc + adapter->stats.roc + | |
4947 | adapter->stats.cexterr; | |
128e45eb AD |
4948 | net_stats->rx_length_errors = adapter->stats.ruc + |
4949 | adapter->stats.roc; | |
4950 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
4951 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
4952 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
4953 | |
4954 | /* Tx Errors */ | |
128e45eb AD |
4955 | net_stats->tx_errors = adapter->stats.ecol + |
4956 | adapter->stats.latecol; | |
4957 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
4958 | net_stats->tx_window_errors = adapter->stats.latecol; | |
4959 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
4960 | |
4961 | /* Tx Dropped needs to be maintained elsewhere */ | |
4962 | ||
4963 | /* Phy Stats */ | |
4964 | if (hw->phy.media_type == e1000_media_type_copper) { | |
4965 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 4966 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
4967 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
4968 | adapter->phy_stats.idle_errors += phy_tmp; | |
4969 | } | |
4970 | } | |
4971 | ||
4972 | /* Management Stats */ | |
4973 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
4974 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
4975 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
0a915b95 CW |
4976 | |
4977 | /* OS2BMC Stats */ | |
4978 | reg = rd32(E1000_MANC); | |
4979 | if (reg & E1000_MANC_EN_BMC2OS) { | |
4980 | adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); | |
4981 | adapter->stats.o2bspc += rd32(E1000_O2BSPC); | |
4982 | adapter->stats.b2ospc += rd32(E1000_B2OSPC); | |
4983 | adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); | |
4984 | } | |
9d5c8243 AK |
4985 | } |
4986 | ||
9d5c8243 AK |
4987 | static irqreturn_t igb_msix_other(int irq, void *data) |
4988 | { | |
047e0030 | 4989 | struct igb_adapter *adapter = data; |
9d5c8243 | 4990 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 4991 | u32 icr = rd32(E1000_ICR); |
844290e5 | 4992 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 4993 | |
7f081d40 AD |
4994 | if (icr & E1000_ICR_DRSTA) |
4995 | schedule_work(&adapter->reset_task); | |
4996 | ||
047e0030 | 4997 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4998 | /* HW is reporting DMA is out of sync */ |
4999 | adapter->stats.doosync++; | |
13800469 GR |
5000 | /* The DMA Out of Sync is also indication of a spoof event |
5001 | * in IOV mode. Check the Wrong VM Behavior register to | |
5002 | * see if it is really a spoof event. */ | |
5003 | igb_check_wvbr(adapter); | |
dda0e083 | 5004 | } |
eebbbdba | 5005 | |
4ae196df AD |
5006 | /* Check for a mailbox event */ |
5007 | if (icr & E1000_ICR_VMMB) | |
5008 | igb_msg_task(adapter); | |
5009 | ||
5010 | if (icr & E1000_ICR_LSC) { | |
5011 | hw->mac.get_link_status = 1; | |
5012 | /* guard against interrupt when we're going down */ | |
5013 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5014 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5015 | } | |
5016 | ||
1f6e8178 MV |
5017 | if (icr & E1000_ICR_TS) { |
5018 | u32 tsicr = rd32(E1000_TSICR); | |
5019 | ||
5020 | if (tsicr & E1000_TSICR_TXTS) { | |
5021 | /* acknowledge the interrupt */ | |
5022 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5023 | /* retrieve hardware timestamp */ | |
5024 | schedule_work(&adapter->ptp_tx_work); | |
5025 | } | |
5026 | } | |
1f6e8178 | 5027 | |
844290e5 | 5028 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
5029 | |
5030 | return IRQ_HANDLED; | |
5031 | } | |
5032 | ||
047e0030 | 5033 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 5034 | { |
26b39276 | 5035 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 5036 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 5037 | |
047e0030 AD |
5038 | if (!q_vector->set_itr) |
5039 | return; | |
73cd78f1 | 5040 | |
047e0030 AD |
5041 | if (!itr_val) |
5042 | itr_val = 0x4; | |
661086df | 5043 | |
26b39276 AD |
5044 | if (adapter->hw.mac.type == e1000_82575) |
5045 | itr_val |= itr_val << 16; | |
661086df | 5046 | else |
0ba82994 | 5047 | itr_val |= E1000_EITR_CNT_IGNR; |
661086df | 5048 | |
047e0030 AD |
5049 | writel(itr_val, q_vector->itr_register); |
5050 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
5051 | } |
5052 | ||
047e0030 | 5053 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 5054 | { |
047e0030 | 5055 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 5056 | |
047e0030 AD |
5057 | /* Write the ITR value calculated from the previous interrupt. */ |
5058 | igb_write_itr(q_vector); | |
9d5c8243 | 5059 | |
047e0030 | 5060 | napi_schedule(&q_vector->napi); |
844290e5 | 5061 | |
047e0030 | 5062 | return IRQ_HANDLED; |
fe4506b6 JC |
5063 | } |
5064 | ||
421e02f0 | 5065 | #ifdef CONFIG_IGB_DCA |
6a05004a AD |
5066 | static void igb_update_tx_dca(struct igb_adapter *adapter, |
5067 | struct igb_ring *tx_ring, | |
5068 | int cpu) | |
5069 | { | |
5070 | struct e1000_hw *hw = &adapter->hw; | |
5071 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
5072 | ||
5073 | if (hw->mac.type != e1000_82575) | |
5074 | txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; | |
5075 | ||
5076 | /* | |
5077 | * We can enable relaxed ordering for reads, but not writes when | |
5078 | * DCA is enabled. This is due to a known issue in some chipsets | |
5079 | * which will cause the DCA tag to be cleared. | |
5080 | */ | |
5081 | txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | | |
5082 | E1000_DCA_TXCTRL_DATA_RRO_EN | | |
5083 | E1000_DCA_TXCTRL_DESC_DCA_EN; | |
5084 | ||
5085 | wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); | |
5086 | } | |
5087 | ||
5088 | static void igb_update_rx_dca(struct igb_adapter *adapter, | |
5089 | struct igb_ring *rx_ring, | |
5090 | int cpu) | |
5091 | { | |
5092 | struct e1000_hw *hw = &adapter->hw; | |
5093 | u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); | |
5094 | ||
5095 | if (hw->mac.type != e1000_82575) | |
5096 | rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; | |
5097 | ||
5098 | /* | |
5099 | * We can enable relaxed ordering for reads, but not writes when | |
5100 | * DCA is enabled. This is due to a known issue in some chipsets | |
5101 | * which will cause the DCA tag to be cleared. | |
5102 | */ | |
5103 | rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | | |
5104 | E1000_DCA_RXCTRL_DESC_DCA_EN; | |
5105 | ||
5106 | wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); | |
5107 | } | |
5108 | ||
047e0030 | 5109 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 5110 | { |
047e0030 | 5111 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 | 5112 | int cpu = get_cpu(); |
fe4506b6 | 5113 | |
047e0030 AD |
5114 | if (q_vector->cpu == cpu) |
5115 | goto out_no_update; | |
5116 | ||
6a05004a AD |
5117 | if (q_vector->tx.ring) |
5118 | igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); | |
5119 | ||
5120 | if (q_vector->rx.ring) | |
5121 | igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); | |
5122 | ||
047e0030 AD |
5123 | q_vector->cpu = cpu; |
5124 | out_no_update: | |
fe4506b6 JC |
5125 | put_cpu(); |
5126 | } | |
5127 | ||
5128 | static void igb_setup_dca(struct igb_adapter *adapter) | |
5129 | { | |
7e0e99ef | 5130 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
5131 | int i; |
5132 | ||
7dfc16fa | 5133 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
5134 | return; |
5135 | ||
7e0e99ef AD |
5136 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
5137 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
5138 | ||
047e0030 | 5139 | for (i = 0; i < adapter->num_q_vectors; i++) { |
26b39276 AD |
5140 | adapter->q_vector[i]->cpu = -1; |
5141 | igb_update_dca(adapter->q_vector[i]); | |
fe4506b6 JC |
5142 | } |
5143 | } | |
5144 | ||
5145 | static int __igb_notify_dca(struct device *dev, void *data) | |
5146 | { | |
5147 | struct net_device *netdev = dev_get_drvdata(dev); | |
5148 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 5149 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
5150 | struct e1000_hw *hw = &adapter->hw; |
5151 | unsigned long event = *(unsigned long *)data; | |
5152 | ||
5153 | switch (event) { | |
5154 | case DCA_PROVIDER_ADD: | |
5155 | /* if already enabled, don't do it again */ | |
7dfc16fa | 5156 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 5157 | break; |
fe4506b6 | 5158 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 5159 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 5160 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
5161 | igb_setup_dca(adapter); |
5162 | break; | |
5163 | } | |
5164 | /* Fall Through since DCA is disabled. */ | |
5165 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 5166 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 5167 | /* without this a class_device is left |
047e0030 | 5168 | * hanging around in the sysfs model */ |
fe4506b6 | 5169 | dca_remove_requester(dev); |
090b1795 | 5170 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 5171 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 5172 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
5173 | } |
5174 | break; | |
5175 | } | |
bbd98fe4 | 5176 | |
fe4506b6 | 5177 | return 0; |
9d5c8243 AK |
5178 | } |
5179 | ||
fe4506b6 JC |
5180 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
5181 | void *p) | |
5182 | { | |
5183 | int ret_val; | |
5184 | ||
5185 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
5186 | __igb_notify_dca); | |
5187 | ||
5188 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5189 | } | |
421e02f0 | 5190 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 5191 | |
0224d663 GR |
5192 | #ifdef CONFIG_PCI_IOV |
5193 | static int igb_vf_configure(struct igb_adapter *adapter, int vf) | |
5194 | { | |
5195 | unsigned char mac_addr[ETH_ALEN]; | |
0224d663 | 5196 | |
7efd26d0 | 5197 | eth_random_addr(mac_addr); |
0224d663 GR |
5198 | igb_set_vf_mac(adapter, vf, mac_addr); |
5199 | ||
f557147c | 5200 | return 0; |
0224d663 GR |
5201 | } |
5202 | ||
f557147c | 5203 | static bool igb_vfs_are_assigned(struct igb_adapter *adapter) |
0224d663 | 5204 | { |
0224d663 | 5205 | struct pci_dev *pdev = adapter->pdev; |
f557147c SA |
5206 | struct pci_dev *vfdev; |
5207 | int dev_id; | |
0224d663 GR |
5208 | |
5209 | switch (adapter->hw.mac.type) { | |
5210 | case e1000_82576: | |
f557147c | 5211 | dev_id = IGB_82576_VF_DEV_ID; |
0224d663 GR |
5212 | break; |
5213 | case e1000_i350: | |
f557147c | 5214 | dev_id = IGB_I350_VF_DEV_ID; |
0224d663 GR |
5215 | break; |
5216 | default: | |
f557147c | 5217 | return false; |
0224d663 GR |
5218 | } |
5219 | ||
f557147c SA |
5220 | /* loop through all the VFs to see if we own any that are assigned */ |
5221 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); | |
5222 | while (vfdev) { | |
5223 | /* if we don't own it we don't care */ | |
5224 | if (vfdev->is_virtfn && vfdev->physfn == pdev) { | |
5225 | /* if it is assigned we cannot release it */ | |
5226 | if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) | |
0224d663 GR |
5227 | return true; |
5228 | } | |
f557147c SA |
5229 | |
5230 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); | |
0224d663 | 5231 | } |
f557147c | 5232 | |
0224d663 GR |
5233 | return false; |
5234 | } | |
5235 | ||
5236 | #endif | |
4ae196df AD |
5237 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
5238 | { | |
5239 | struct e1000_hw *hw = &adapter->hw; | |
5240 | u32 ping; | |
5241 | int i; | |
5242 | ||
5243 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
5244 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 5245 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
5246 | ping |= E1000_VT_MSGTYPE_CTS; |
5247 | igb_write_mbx(hw, &ping, 1, i); | |
5248 | } | |
5249 | } | |
5250 | ||
7d5753f0 AD |
5251 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
5252 | { | |
5253 | struct e1000_hw *hw = &adapter->hw; | |
5254 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
5255 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5256 | ||
d85b9004 | 5257 | vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | |
7d5753f0 AD |
5258 | IGB_VF_FLAG_MULTI_PROMISC); |
5259 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
5260 | ||
5261 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
5262 | vmolr |= E1000_VMOLR_MPME; | |
d85b9004 | 5263 | vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; |
7d5753f0 AD |
5264 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; |
5265 | } else { | |
5266 | /* | |
5267 | * if we have hashes and we are clearing a multicast promisc | |
5268 | * flag we need to write the hashes to the MTA as this step | |
5269 | * was previously skipped | |
5270 | */ | |
5271 | if (vf_data->num_vf_mc_hashes > 30) { | |
5272 | vmolr |= E1000_VMOLR_MPME; | |
5273 | } else if (vf_data->num_vf_mc_hashes) { | |
5274 | int j; | |
5275 | vmolr |= E1000_VMOLR_ROMPE; | |
5276 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5277 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5278 | } | |
5279 | } | |
5280 | ||
5281 | wr32(E1000_VMOLR(vf), vmolr); | |
5282 | ||
5283 | /* there are flags left unprocessed, likely not supported */ | |
5284 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
5285 | return -EINVAL; | |
5286 | ||
5287 | return 0; | |
5288 | ||
5289 | } | |
5290 | ||
4ae196df AD |
5291 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
5292 | u32 *msgbuf, u32 vf) | |
5293 | { | |
5294 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5295 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
5296 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5297 | int i; | |
5298 | ||
7d5753f0 | 5299 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
5300 | * to this VF for later use to restore when the PF multi cast |
5301 | * list changes | |
5302 | */ | |
5303 | vf_data->num_vf_mc_hashes = n; | |
5304 | ||
7d5753f0 AD |
5305 | /* only up to 30 hash values supported */ |
5306 | if (n > 30) | |
5307 | n = 30; | |
5308 | ||
5309 | /* store the hashes for later use */ | |
4ae196df | 5310 | for (i = 0; i < n; i++) |
a419aef8 | 5311 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
5312 | |
5313 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5314 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5315 | |
5316 | return 0; | |
5317 | } | |
5318 | ||
5319 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
5320 | { | |
5321 | struct e1000_hw *hw = &adapter->hw; | |
5322 | struct vf_data_storage *vf_data; | |
5323 | int i, j; | |
5324 | ||
5325 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
5326 | u32 vmolr = rd32(E1000_VMOLR(i)); |
5327 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
5328 | ||
4ae196df | 5329 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
5330 | |
5331 | if ((vf_data->num_vf_mc_hashes > 30) || | |
5332 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
5333 | vmolr |= E1000_VMOLR_MPME; | |
5334 | } else if (vf_data->num_vf_mc_hashes) { | |
5335 | vmolr |= E1000_VMOLR_ROMPE; | |
5336 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5337 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5338 | } | |
5339 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
5340 | } |
5341 | } | |
5342 | ||
5343 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
5344 | { | |
5345 | struct e1000_hw *hw = &adapter->hw; | |
5346 | u32 pool_mask, reg, vid; | |
5347 | int i; | |
5348 | ||
5349 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5350 | ||
5351 | /* Find the vlan filter for this id */ | |
5352 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5353 | reg = rd32(E1000_VLVF(i)); | |
5354 | ||
5355 | /* remove the vf from the pool */ | |
5356 | reg &= ~pool_mask; | |
5357 | ||
5358 | /* if pool is empty then remove entry from vfta */ | |
5359 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
5360 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
5361 | reg = 0; | |
5362 | vid = reg & E1000_VLVF_VLANID_MASK; | |
5363 | igb_vfta_set(hw, vid, false); | |
5364 | } | |
5365 | ||
5366 | wr32(E1000_VLVF(i), reg); | |
5367 | } | |
ae641bdc AD |
5368 | |
5369 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
5370 | } |
5371 | ||
5372 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
5373 | { | |
5374 | struct e1000_hw *hw = &adapter->hw; | |
5375 | u32 reg, i; | |
5376 | ||
51466239 AD |
5377 | /* The vlvf table only exists on 82576 hardware and newer */ |
5378 | if (hw->mac.type < e1000_82576) | |
5379 | return -1; | |
5380 | ||
5381 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
5382 | if (!adapter->vfs_allocated_count) |
5383 | return -1; | |
5384 | ||
5385 | /* Find the vlan filter for this id */ | |
5386 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5387 | reg = rd32(E1000_VLVF(i)); | |
5388 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
5389 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
5390 | break; | |
5391 | } | |
5392 | ||
5393 | if (add) { | |
5394 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
5395 | /* Did not find a matching VLAN ID entry that was | |
5396 | * enabled. Search for a free filter entry, i.e. | |
5397 | * one without the enable bit set | |
5398 | */ | |
5399 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5400 | reg = rd32(E1000_VLVF(i)); | |
5401 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
5402 | break; | |
5403 | } | |
5404 | } | |
5405 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5406 | /* Found an enabled/available entry */ | |
5407 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5408 | ||
5409 | /* if !enabled we need to set this up in vfta */ | |
5410 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
5411 | /* add VID to filter table */ |
5412 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
5413 | reg |= E1000_VLVF_VLANID_ENABLE; |
5414 | } | |
cad6d05f AD |
5415 | reg &= ~E1000_VLVF_VLANID_MASK; |
5416 | reg |= vid; | |
4ae196df | 5417 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
5418 | |
5419 | /* do not modify RLPML for PF devices */ | |
5420 | if (vf >= adapter->vfs_allocated_count) | |
5421 | return 0; | |
5422 | ||
5423 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5424 | u32 size; | |
5425 | reg = rd32(E1000_VMOLR(vf)); | |
5426 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5427 | size += 4; | |
5428 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5429 | reg |= size; | |
5430 | wr32(E1000_VMOLR(vf), reg); | |
5431 | } | |
ae641bdc | 5432 | |
51466239 | 5433 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
5434 | } |
5435 | } else { | |
5436 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5437 | /* remove vf from the pool */ | |
5438 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
5439 | /* if pool is empty then remove entry from vfta */ | |
5440 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
5441 | reg = 0; | |
5442 | igb_vfta_set(hw, vid, false); | |
5443 | } | |
5444 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
5445 | |
5446 | /* do not modify RLPML for PF devices */ | |
5447 | if (vf >= adapter->vfs_allocated_count) | |
5448 | return 0; | |
5449 | ||
5450 | adapter->vf_data[vf].vlans_enabled--; | |
5451 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5452 | u32 size; | |
5453 | reg = rd32(E1000_VMOLR(vf)); | |
5454 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5455 | size -= 4; | |
5456 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5457 | reg |= size; | |
5458 | wr32(E1000_VMOLR(vf), reg); | |
5459 | } | |
4ae196df AD |
5460 | } |
5461 | } | |
8151d294 WM |
5462 | return 0; |
5463 | } | |
5464 | ||
5465 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | |
5466 | { | |
5467 | struct e1000_hw *hw = &adapter->hw; | |
5468 | ||
5469 | if (vid) | |
5470 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | |
5471 | else | |
5472 | wr32(E1000_VMVIR(vf), 0); | |
5473 | } | |
5474 | ||
5475 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
5476 | int vf, u16 vlan, u8 qos) | |
5477 | { | |
5478 | int err = 0; | |
5479 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5480 | ||
5481 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | |
5482 | return -EINVAL; | |
5483 | if (vlan || qos) { | |
5484 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | |
5485 | if (err) | |
5486 | goto out; | |
5487 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | |
5488 | igb_set_vmolr(adapter, vf, !vlan); | |
5489 | adapter->vf_data[vf].pf_vlan = vlan; | |
5490 | adapter->vf_data[vf].pf_qos = qos; | |
5491 | dev_info(&adapter->pdev->dev, | |
5492 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | |
5493 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
5494 | dev_warn(&adapter->pdev->dev, | |
5495 | "The VF VLAN has been set," | |
5496 | " but the PF device is not up.\n"); | |
5497 | dev_warn(&adapter->pdev->dev, | |
5498 | "Bring the PF device up before" | |
5499 | " attempting to use the VF device.\n"); | |
5500 | } | |
5501 | } else { | |
5502 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | |
5503 | false, vf); | |
5504 | igb_set_vmvir(adapter, vlan, vf); | |
5505 | igb_set_vmolr(adapter, vf, true); | |
5506 | adapter->vf_data[vf].pf_vlan = 0; | |
5507 | adapter->vf_data[vf].pf_qos = 0; | |
5508 | } | |
5509 | out: | |
5510 | return err; | |
4ae196df AD |
5511 | } |
5512 | ||
5513 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
5514 | { | |
5515 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5516 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
5517 | ||
5518 | return igb_vlvf_set(adapter, vid, add, vf); | |
5519 | } | |
5520 | ||
f2ca0dbe | 5521 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5522 | { |
8fa7e0f7 GR |
5523 | /* clear flags - except flag that indicates PF has set the MAC */ |
5524 | adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; | |
f2ca0dbe | 5525 | adapter->vf_data[vf].last_nack = jiffies; |
4ae196df AD |
5526 | |
5527 | /* reset offloads to defaults */ | |
8151d294 | 5528 | igb_set_vmolr(adapter, vf, true); |
4ae196df AD |
5529 | |
5530 | /* reset vlans for device */ | |
5531 | igb_clear_vf_vfta(adapter, vf); | |
8151d294 WM |
5532 | if (adapter->vf_data[vf].pf_vlan) |
5533 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | |
5534 | adapter->vf_data[vf].pf_vlan, | |
5535 | adapter->vf_data[vf].pf_qos); | |
5536 | else | |
5537 | igb_clear_vf_vfta(adapter, vf); | |
4ae196df AD |
5538 | |
5539 | /* reset multicast table array for vf */ | |
5540 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
5541 | ||
5542 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5543 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5544 | } |
5545 | ||
f2ca0dbe AD |
5546 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
5547 | { | |
5548 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
5549 | ||
5550 | /* generate a new mac address as we were hotplug removed/added */ | |
8151d294 | 5551 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
7efd26d0 | 5552 | eth_random_addr(vf_mac); |
f2ca0dbe AD |
5553 | |
5554 | /* process remaining reset events */ | |
5555 | igb_vf_reset(adapter, vf); | |
5556 | } | |
5557 | ||
5558 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
5559 | { |
5560 | struct e1000_hw *hw = &adapter->hw; | |
5561 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 5562 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
5563 | u32 reg, msgbuf[3]; |
5564 | u8 *addr = (u8 *)(&msgbuf[1]); | |
5565 | ||
5566 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 5567 | igb_vf_reset(adapter, vf); |
4ae196df AD |
5568 | |
5569 | /* set vf mac address */ | |
26ad9178 | 5570 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
5571 | |
5572 | /* enable transmit and receive for vf */ | |
5573 | reg = rd32(E1000_VFTE); | |
5574 | wr32(E1000_VFTE, reg | (1 << vf)); | |
5575 | reg = rd32(E1000_VFRE); | |
5576 | wr32(E1000_VFRE, reg | (1 << vf)); | |
5577 | ||
8fa7e0f7 | 5578 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; |
4ae196df AD |
5579 | |
5580 | /* reply to reset with ack and vf mac address */ | |
5581 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
5582 | memcpy(addr, vf_mac, 6); | |
5583 | igb_write_mbx(hw, msgbuf, 3, vf); | |
5584 | } | |
5585 | ||
5586 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
5587 | { | |
de42edde GR |
5588 | /* |
5589 | * The VF MAC Address is stored in a packed array of bytes | |
5590 | * starting at the second 32 bit word of the msg array | |
5591 | */ | |
f2ca0dbe AD |
5592 | unsigned char *addr = (char *)&msg[1]; |
5593 | int err = -1; | |
4ae196df | 5594 | |
f2ca0dbe AD |
5595 | if (is_valid_ether_addr(addr)) |
5596 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 5597 | |
f2ca0dbe | 5598 | return err; |
4ae196df AD |
5599 | } |
5600 | ||
5601 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
5602 | { | |
5603 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 5604 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5605 | u32 msg = E1000_VT_MSGTYPE_NACK; |
5606 | ||
5607 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
5608 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
5609 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 5610 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 5611 | vf_data->last_nack = jiffies; |
4ae196df AD |
5612 | } |
5613 | } | |
5614 | ||
f2ca0dbe | 5615 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5616 | { |
f2ca0dbe AD |
5617 | struct pci_dev *pdev = adapter->pdev; |
5618 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 5619 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 5620 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5621 | s32 retval; |
5622 | ||
f2ca0dbe | 5623 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df | 5624 | |
fef45f4c AD |
5625 | if (retval) { |
5626 | /* if receive failed revoke VF CTS stats and restart init */ | |
f2ca0dbe | 5627 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
fef45f4c AD |
5628 | vf_data->flags &= ~IGB_VF_FLAG_CTS; |
5629 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | |
5630 | return; | |
5631 | goto out; | |
5632 | } | |
4ae196df AD |
5633 | |
5634 | /* this is a message we already processed, do nothing */ | |
5635 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 5636 | return; |
4ae196df AD |
5637 | |
5638 | /* | |
5639 | * until the vf completes a reset it should not be | |
5640 | * allowed to start any configuration. | |
5641 | */ | |
5642 | ||
5643 | if (msgbuf[0] == E1000_VF_RESET) { | |
5644 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 5645 | return; |
4ae196df AD |
5646 | } |
5647 | ||
f2ca0dbe | 5648 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
fef45f4c AD |
5649 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
5650 | return; | |
5651 | retval = -1; | |
5652 | goto out; | |
4ae196df AD |
5653 | } |
5654 | ||
5655 | switch ((msgbuf[0] & 0xFFFF)) { | |
5656 | case E1000_VF_SET_MAC_ADDR: | |
a6b5ea35 GR |
5657 | retval = -EINVAL; |
5658 | if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) | |
5659 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
5660 | else | |
5661 | dev_warn(&pdev->dev, | |
5662 | "VF %d attempted to override administratively " | |
5663 | "set MAC address\nReload the VF driver to " | |
5664 | "resume operations\n", vf); | |
4ae196df | 5665 | break; |
7d5753f0 AD |
5666 | case E1000_VF_SET_PROMISC: |
5667 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
5668 | break; | |
4ae196df AD |
5669 | case E1000_VF_SET_MULTICAST: |
5670 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
5671 | break; | |
5672 | case E1000_VF_SET_LPE: | |
5673 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
5674 | break; | |
5675 | case E1000_VF_SET_VLAN: | |
a6b5ea35 GR |
5676 | retval = -1; |
5677 | if (vf_data->pf_vlan) | |
5678 | dev_warn(&pdev->dev, | |
5679 | "VF %d attempted to override administratively " | |
5680 | "set VLAN tag\nReload the VF driver to " | |
5681 | "resume operations\n", vf); | |
8151d294 WM |
5682 | else |
5683 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4ae196df AD |
5684 | break; |
5685 | default: | |
090b1795 | 5686 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
5687 | retval = -1; |
5688 | break; | |
5689 | } | |
5690 | ||
fef45f4c AD |
5691 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
5692 | out: | |
4ae196df AD |
5693 | /* notify the VF of the results of what it sent us */ |
5694 | if (retval) | |
5695 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
5696 | else | |
5697 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
5698 | ||
4ae196df | 5699 | igb_write_mbx(hw, msgbuf, 1, vf); |
f2ca0dbe | 5700 | } |
4ae196df | 5701 | |
f2ca0dbe AD |
5702 | static void igb_msg_task(struct igb_adapter *adapter) |
5703 | { | |
5704 | struct e1000_hw *hw = &adapter->hw; | |
5705 | u32 vf; | |
5706 | ||
5707 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
5708 | /* process any reset requests */ | |
5709 | if (!igb_check_for_rst(hw, vf)) | |
5710 | igb_vf_reset_event(adapter, vf); | |
5711 | ||
5712 | /* process any messages pending */ | |
5713 | if (!igb_check_for_msg(hw, vf)) | |
5714 | igb_rcv_msg_from_vf(adapter, vf); | |
5715 | ||
5716 | /* process any acks */ | |
5717 | if (!igb_check_for_ack(hw, vf)) | |
5718 | igb_rcv_ack_from_vf(adapter, vf); | |
5719 | } | |
4ae196df AD |
5720 | } |
5721 | ||
68d480c4 AD |
5722 | /** |
5723 | * igb_set_uta - Set unicast filter table address | |
5724 | * @adapter: board private structure | |
5725 | * | |
5726 | * The unicast table address is a register array of 32-bit registers. | |
5727 | * The table is meant to be used in a way similar to how the MTA is used | |
5728 | * however due to certain limitations in the hardware it is necessary to | |
25985edc LDM |
5729 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous |
5730 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
68d480c4 AD |
5731 | **/ |
5732 | static void igb_set_uta(struct igb_adapter *adapter) | |
5733 | { | |
5734 | struct e1000_hw *hw = &adapter->hw; | |
5735 | int i; | |
5736 | ||
5737 | /* The UTA table only exists on 82576 hardware and newer */ | |
5738 | if (hw->mac.type < e1000_82576) | |
5739 | return; | |
5740 | ||
5741 | /* we only need to do this if VMDq is enabled */ | |
5742 | if (!adapter->vfs_allocated_count) | |
5743 | return; | |
5744 | ||
5745 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
5746 | array_wr32(E1000_UTA, i, ~0); | |
5747 | } | |
5748 | ||
9d5c8243 AK |
5749 | /** |
5750 | * igb_intr_msi - Interrupt Handler | |
5751 | * @irq: interrupt number | |
5752 | * @data: pointer to a network interface device structure | |
5753 | **/ | |
5754 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
5755 | { | |
047e0030 AD |
5756 | struct igb_adapter *adapter = data; |
5757 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5758 | struct e1000_hw *hw = &adapter->hw; |
5759 | /* read ICR disables interrupts using IAM */ | |
5760 | u32 icr = rd32(E1000_ICR); | |
5761 | ||
047e0030 | 5762 | igb_write_itr(q_vector); |
9d5c8243 | 5763 | |
7f081d40 AD |
5764 | if (icr & E1000_ICR_DRSTA) |
5765 | schedule_work(&adapter->reset_task); | |
5766 | ||
047e0030 | 5767 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5768 | /* HW is reporting DMA is out of sync */ |
5769 | adapter->stats.doosync++; | |
5770 | } | |
5771 | ||
9d5c8243 AK |
5772 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5773 | hw->mac.get_link_status = 1; | |
5774 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5775 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5776 | } | |
5777 | ||
1f6e8178 MV |
5778 | if (icr & E1000_ICR_TS) { |
5779 | u32 tsicr = rd32(E1000_TSICR); | |
5780 | ||
5781 | if (tsicr & E1000_TSICR_TXTS) { | |
5782 | /* acknowledge the interrupt */ | |
5783 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5784 | /* retrieve hardware timestamp */ | |
5785 | schedule_work(&adapter->ptp_tx_work); | |
5786 | } | |
5787 | } | |
1f6e8178 | 5788 | |
047e0030 | 5789 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5790 | |
5791 | return IRQ_HANDLED; | |
5792 | } | |
5793 | ||
5794 | /** | |
4a3c6433 | 5795 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
5796 | * @irq: interrupt number |
5797 | * @data: pointer to a network interface device structure | |
5798 | **/ | |
5799 | static irqreturn_t igb_intr(int irq, void *data) | |
5800 | { | |
047e0030 AD |
5801 | struct igb_adapter *adapter = data; |
5802 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5803 | struct e1000_hw *hw = &adapter->hw; |
5804 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
5805 | * need for the IMC write */ | |
5806 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
5807 | |
5808 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
5809 | * not set, then the adapter didn't send an interrupt */ | |
5810 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
5811 | return IRQ_NONE; | |
5812 | ||
0ba82994 AD |
5813 | igb_write_itr(q_vector); |
5814 | ||
7f081d40 AD |
5815 | if (icr & E1000_ICR_DRSTA) |
5816 | schedule_work(&adapter->reset_task); | |
5817 | ||
047e0030 | 5818 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5819 | /* HW is reporting DMA is out of sync */ |
5820 | adapter->stats.doosync++; | |
5821 | } | |
5822 | ||
9d5c8243 AK |
5823 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5824 | hw->mac.get_link_status = 1; | |
5825 | /* guard against interrupt when we're going down */ | |
5826 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5827 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5828 | } | |
5829 | ||
1f6e8178 MV |
5830 | if (icr & E1000_ICR_TS) { |
5831 | u32 tsicr = rd32(E1000_TSICR); | |
5832 | ||
5833 | if (tsicr & E1000_TSICR_TXTS) { | |
5834 | /* acknowledge the interrupt */ | |
5835 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5836 | /* retrieve hardware timestamp */ | |
5837 | schedule_work(&adapter->ptp_tx_work); | |
5838 | } | |
5839 | } | |
1f6e8178 | 5840 | |
047e0030 | 5841 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5842 | |
5843 | return IRQ_HANDLED; | |
5844 | } | |
5845 | ||
c50b52a0 | 5846 | static void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 5847 | { |
047e0030 | 5848 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 5849 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5850 | |
0ba82994 AD |
5851 | if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || |
5852 | (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { | |
5853 | if ((adapter->num_q_vectors == 1) && !adapter->vf_data) | |
5854 | igb_set_itr(q_vector); | |
46544258 | 5855 | else |
047e0030 | 5856 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
5857 | } |
5858 | ||
46544258 AD |
5859 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
5860 | if (adapter->msix_entries) | |
047e0030 | 5861 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
5862 | else |
5863 | igb_irq_enable(adapter); | |
5864 | } | |
9d5c8243 AK |
5865 | } |
5866 | ||
46544258 AD |
5867 | /** |
5868 | * igb_poll - NAPI Rx polling callback | |
5869 | * @napi: napi polling structure | |
5870 | * @budget: count of how many packets we should handle | |
5871 | **/ | |
5872 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 5873 | { |
047e0030 AD |
5874 | struct igb_q_vector *q_vector = container_of(napi, |
5875 | struct igb_q_vector, | |
5876 | napi); | |
16eb8815 | 5877 | bool clean_complete = true; |
9d5c8243 | 5878 | |
421e02f0 | 5879 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
5880 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
5881 | igb_update_dca(q_vector); | |
fe4506b6 | 5882 | #endif |
0ba82994 | 5883 | if (q_vector->tx.ring) |
13fde97a | 5884 | clean_complete = igb_clean_tx_irq(q_vector); |
9d5c8243 | 5885 | |
0ba82994 | 5886 | if (q_vector->rx.ring) |
cd392f5c | 5887 | clean_complete &= igb_clean_rx_irq(q_vector, budget); |
047e0030 | 5888 | |
16eb8815 AD |
5889 | /* If all work not completed, return budget and keep polling */ |
5890 | if (!clean_complete) | |
5891 | return budget; | |
46544258 | 5892 | |
9d5c8243 | 5893 | /* If not enough Rx work done, exit the polling mode */ |
16eb8815 AD |
5894 | napi_complete(napi); |
5895 | igb_ring_irq_enable(q_vector); | |
9d5c8243 | 5896 | |
16eb8815 | 5897 | return 0; |
9d5c8243 | 5898 | } |
6d8126f9 | 5899 | |
9d5c8243 AK |
5900 | /** |
5901 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
047e0030 | 5902 | * @q_vector: pointer to q_vector containing needed info |
49ce9c2c | 5903 | * |
9d5c8243 AK |
5904 | * returns true if ring is completely cleaned |
5905 | **/ | |
047e0030 | 5906 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 5907 | { |
047e0030 | 5908 | struct igb_adapter *adapter = q_vector->adapter; |
0ba82994 | 5909 | struct igb_ring *tx_ring = q_vector->tx.ring; |
06034649 | 5910 | struct igb_tx_buffer *tx_buffer; |
f4128785 | 5911 | union e1000_adv_tx_desc *tx_desc; |
9d5c8243 | 5912 | unsigned int total_bytes = 0, total_packets = 0; |
0ba82994 | 5913 | unsigned int budget = q_vector->tx.work_limit; |
8542db05 | 5914 | unsigned int i = tx_ring->next_to_clean; |
9d5c8243 | 5915 | |
13fde97a AD |
5916 | if (test_bit(__IGB_DOWN, &adapter->state)) |
5917 | return true; | |
0e014cb1 | 5918 | |
06034649 | 5919 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
13fde97a | 5920 | tx_desc = IGB_TX_DESC(tx_ring, i); |
8542db05 | 5921 | i -= tx_ring->count; |
9d5c8243 | 5922 | |
f4128785 AD |
5923 | do { |
5924 | union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; | |
8542db05 AD |
5925 | |
5926 | /* if next_to_watch is not set then there is no work pending */ | |
5927 | if (!eop_desc) | |
5928 | break; | |
13fde97a | 5929 | |
f4128785 AD |
5930 | /* prevent any other reads prior to eop_desc */ |
5931 | rmb(); | |
5932 | ||
13fde97a AD |
5933 | /* if DD is not set pending work has not been completed */ |
5934 | if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) | |
5935 | break; | |
5936 | ||
8542db05 AD |
5937 | /* clear next_to_watch to prevent false hangs */ |
5938 | tx_buffer->next_to_watch = NULL; | |
9d5c8243 | 5939 | |
ebe42d16 AD |
5940 | /* update the statistics for this packet */ |
5941 | total_bytes += tx_buffer->bytecount; | |
5942 | total_packets += tx_buffer->gso_segs; | |
13fde97a | 5943 | |
ebe42d16 AD |
5944 | /* free the skb */ |
5945 | dev_kfree_skb_any(tx_buffer->skb); | |
13fde97a | 5946 | |
ebe42d16 AD |
5947 | /* unmap skb header data */ |
5948 | dma_unmap_single(tx_ring->dev, | |
c9f14bf3 AD |
5949 | dma_unmap_addr(tx_buffer, dma), |
5950 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
5951 | DMA_TO_DEVICE); |
5952 | ||
c9f14bf3 AD |
5953 | /* clear tx_buffer data */ |
5954 | tx_buffer->skb = NULL; | |
5955 | dma_unmap_len_set(tx_buffer, len, 0); | |
5956 | ||
ebe42d16 AD |
5957 | /* clear last DMA location and unmap remaining buffers */ |
5958 | while (tx_desc != eop_desc) { | |
13fde97a AD |
5959 | tx_buffer++; |
5960 | tx_desc++; | |
9d5c8243 | 5961 | i++; |
8542db05 AD |
5962 | if (unlikely(!i)) { |
5963 | i -= tx_ring->count; | |
06034649 | 5964 | tx_buffer = tx_ring->tx_buffer_info; |
13fde97a AD |
5965 | tx_desc = IGB_TX_DESC(tx_ring, 0); |
5966 | } | |
ebe42d16 AD |
5967 | |
5968 | /* unmap any remaining paged data */ | |
c9f14bf3 | 5969 | if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 5970 | dma_unmap_page(tx_ring->dev, |
c9f14bf3 AD |
5971 | dma_unmap_addr(tx_buffer, dma), |
5972 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 5973 | DMA_TO_DEVICE); |
c9f14bf3 | 5974 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 AD |
5975 | } |
5976 | } | |
5977 | ||
ebe42d16 AD |
5978 | /* move us one more past the eop_desc for start of next pkt */ |
5979 | tx_buffer++; | |
5980 | tx_desc++; | |
5981 | i++; | |
5982 | if (unlikely(!i)) { | |
5983 | i -= tx_ring->count; | |
5984 | tx_buffer = tx_ring->tx_buffer_info; | |
5985 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
5986 | } | |
f4128785 AD |
5987 | |
5988 | /* issue prefetch for next Tx descriptor */ | |
5989 | prefetch(tx_desc); | |
5990 | ||
5991 | /* update budget accounting */ | |
5992 | budget--; | |
5993 | } while (likely(budget)); | |
0e014cb1 | 5994 | |
bdbc0631 ED |
5995 | netdev_tx_completed_queue(txring_txq(tx_ring), |
5996 | total_packets, total_bytes); | |
8542db05 | 5997 | i += tx_ring->count; |
9d5c8243 | 5998 | tx_ring->next_to_clean = i; |
13fde97a AD |
5999 | u64_stats_update_begin(&tx_ring->tx_syncp); |
6000 | tx_ring->tx_stats.bytes += total_bytes; | |
6001 | tx_ring->tx_stats.packets += total_packets; | |
6002 | u64_stats_update_end(&tx_ring->tx_syncp); | |
0ba82994 AD |
6003 | q_vector->tx.total_bytes += total_bytes; |
6004 | q_vector->tx.total_packets += total_packets; | |
9d5c8243 | 6005 | |
6d095fa8 | 6006 | if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { |
13fde97a | 6007 | struct e1000_hw *hw = &adapter->hw; |
12dcd86b | 6008 | |
9d5c8243 AK |
6009 | /* Detect a transmit hang in hardware, this serializes the |
6010 | * check with the clearing of time_stamp and movement of i */ | |
6d095fa8 | 6011 | clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
f4128785 | 6012 | if (tx_buffer->next_to_watch && |
8542db05 | 6013 | time_after(jiffies, tx_buffer->time_stamp + |
8e95a202 JP |
6014 | (adapter->tx_timeout_factor * HZ)) && |
6015 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { | |
9d5c8243 | 6016 | |
9d5c8243 | 6017 | /* detected Tx unit hang */ |
59d71989 | 6018 | dev_err(tx_ring->dev, |
9d5c8243 | 6019 | "Detected Tx Unit Hang\n" |
2d064c06 | 6020 | " Tx Queue <%d>\n" |
9d5c8243 AK |
6021 | " TDH <%x>\n" |
6022 | " TDT <%x>\n" | |
6023 | " next_to_use <%x>\n" | |
6024 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
6025 | "buffer_info[next_to_clean]\n" |
6026 | " time_stamp <%lx>\n" | |
8542db05 | 6027 | " next_to_watch <%p>\n" |
9d5c8243 AK |
6028 | " jiffies <%lx>\n" |
6029 | " desc.status <%x>\n", | |
2d064c06 | 6030 | tx_ring->queue_index, |
238ac817 | 6031 | rd32(E1000_TDH(tx_ring->reg_idx)), |
fce99e34 | 6032 | readl(tx_ring->tail), |
9d5c8243 AK |
6033 | tx_ring->next_to_use, |
6034 | tx_ring->next_to_clean, | |
8542db05 | 6035 | tx_buffer->time_stamp, |
f4128785 | 6036 | tx_buffer->next_to_watch, |
9d5c8243 | 6037 | jiffies, |
f4128785 | 6038 | tx_buffer->next_to_watch->wb.status); |
13fde97a AD |
6039 | netif_stop_subqueue(tx_ring->netdev, |
6040 | tx_ring->queue_index); | |
6041 | ||
6042 | /* we are about to reset, no point in enabling stuff */ | |
6043 | return true; | |
9d5c8243 AK |
6044 | } |
6045 | } | |
13fde97a AD |
6046 | |
6047 | if (unlikely(total_packets && | |
6048 | netif_carrier_ok(tx_ring->netdev) && | |
6049 | igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { | |
6050 | /* Make sure that anybody stopping the queue after this | |
6051 | * sees the new next_to_clean. | |
6052 | */ | |
6053 | smp_mb(); | |
6054 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
6055 | tx_ring->queue_index) && | |
6056 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
6057 | netif_wake_subqueue(tx_ring->netdev, | |
6058 | tx_ring->queue_index); | |
6059 | ||
6060 | u64_stats_update_begin(&tx_ring->tx_syncp); | |
6061 | tx_ring->tx_stats.restart_queue++; | |
6062 | u64_stats_update_end(&tx_ring->tx_syncp); | |
6063 | } | |
6064 | } | |
6065 | ||
6066 | return !!budget; | |
9d5c8243 AK |
6067 | } |
6068 | ||
cbc8e55f AD |
6069 | /** |
6070 | * igb_reuse_rx_page - page flip buffer and store it back on the ring | |
6071 | * @rx_ring: rx descriptor ring to store buffers on | |
6072 | * @old_buff: donor buffer to have page reused | |
6073 | * | |
6074 | * Synchronizes page for reuse by the adapter | |
6075 | **/ | |
6076 | static void igb_reuse_rx_page(struct igb_ring *rx_ring, | |
6077 | struct igb_rx_buffer *old_buff) | |
6078 | { | |
6079 | struct igb_rx_buffer *new_buff; | |
6080 | u16 nta = rx_ring->next_to_alloc; | |
6081 | ||
6082 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
6083 | ||
6084 | /* update, and store next to alloc */ | |
6085 | nta++; | |
6086 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
6087 | ||
6088 | /* transfer page from old buffer to new buffer */ | |
6089 | memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); | |
6090 | ||
6091 | /* sync the buffer for use by the device */ | |
6092 | dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, | |
6093 | old_buff->page_offset, | |
de78d1f9 | 6094 | IGB_RX_BUFSZ, |
cbc8e55f AD |
6095 | DMA_FROM_DEVICE); |
6096 | } | |
6097 | ||
6098 | /** | |
6099 | * igb_add_rx_frag - Add contents of Rx buffer to sk_buff | |
6100 | * @rx_ring: rx descriptor ring to transact packets on | |
6101 | * @rx_buffer: buffer containing page to add | |
6102 | * @rx_desc: descriptor containing length of buffer written by hardware | |
6103 | * @skb: sk_buff to place the data into | |
6104 | * | |
6105 | * This function will add the data contained in rx_buffer->page to the skb. | |
6106 | * This is done either through a direct copy if the data in the buffer is | |
6107 | * less than the skb header size, otherwise it will just attach the page as | |
6108 | * a frag to the skb. | |
6109 | * | |
6110 | * The function will then update the page offset if necessary and return | |
6111 | * true if the buffer can be reused by the adapter. | |
6112 | **/ | |
6113 | static bool igb_add_rx_frag(struct igb_ring *rx_ring, | |
6114 | struct igb_rx_buffer *rx_buffer, | |
6115 | union e1000_adv_rx_desc *rx_desc, | |
6116 | struct sk_buff *skb) | |
6117 | { | |
6118 | struct page *page = rx_buffer->page; | |
6119 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
6120 | ||
6121 | if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { | |
6122 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
6123 | ||
cbc8e55f AD |
6124 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6125 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6126 | va += IGB_TS_HDR_LEN; | |
6127 | size -= IGB_TS_HDR_LEN; | |
6128 | } | |
6129 | ||
cbc8e55f AD |
6130 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
6131 | ||
6132 | /* we can reuse buffer as-is, just make sure it is local */ | |
6133 | if (likely(page_to_nid(page) == numa_node_id())) | |
6134 | return true; | |
6135 | ||
6136 | /* this page cannot be reused so discard it */ | |
6137 | put_page(page); | |
6138 | return false; | |
6139 | } | |
6140 | ||
6141 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
de78d1f9 | 6142 | rx_buffer->page_offset, size, IGB_RX_BUFSZ); |
cbc8e55f AD |
6143 | |
6144 | /* avoid re-using remote pages */ | |
6145 | if (unlikely(page_to_nid(page) != numa_node_id())) | |
6146 | return false; | |
6147 | ||
de78d1f9 | 6148 | #if (PAGE_SIZE < 8192) |
cbc8e55f AD |
6149 | /* if we are only owner of page we can reuse it */ |
6150 | if (unlikely(page_count(page) != 1)) | |
6151 | return false; | |
6152 | ||
6153 | /* flip page offset to other buffer */ | |
de78d1f9 | 6154 | rx_buffer->page_offset ^= IGB_RX_BUFSZ; |
cbc8e55f AD |
6155 | |
6156 | /* | |
6157 | * since we are the only owner of the page and we need to | |
6158 | * increment it, just set the value to 2 in order to avoid | |
6159 | * an unnecessary locked operation | |
6160 | */ | |
6161 | atomic_set(&page->_count, 2); | |
de78d1f9 AD |
6162 | #else |
6163 | /* move offset up to the next cache line */ | |
6164 | rx_buffer->page_offset += SKB_DATA_ALIGN(size); | |
6165 | ||
6166 | if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) | |
6167 | return false; | |
6168 | ||
6169 | /* bump ref count on page before it is given to the stack */ | |
6170 | get_page(page); | |
6171 | #endif | |
cbc8e55f AD |
6172 | |
6173 | return true; | |
6174 | } | |
6175 | ||
2e334eee AD |
6176 | static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, |
6177 | union e1000_adv_rx_desc *rx_desc, | |
6178 | struct sk_buff *skb) | |
6179 | { | |
6180 | struct igb_rx_buffer *rx_buffer; | |
6181 | struct page *page; | |
6182 | ||
6183 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
6184 | ||
6185 | /* | |
6186 | * This memory barrier is needed to keep us from reading | |
6187 | * any other fields out of the rx_desc until we know the | |
6188 | * RXD_STAT_DD bit is set | |
6189 | */ | |
6190 | rmb(); | |
6191 | ||
6192 | page = rx_buffer->page; | |
6193 | prefetchw(page); | |
6194 | ||
6195 | if (likely(!skb)) { | |
6196 | void *page_addr = page_address(page) + | |
6197 | rx_buffer->page_offset; | |
6198 | ||
6199 | /* prefetch first cache line of first page */ | |
6200 | prefetch(page_addr); | |
6201 | #if L1_CACHE_BYTES < 128 | |
6202 | prefetch(page_addr + L1_CACHE_BYTES); | |
6203 | #endif | |
6204 | ||
6205 | /* allocate a skb to store the frags */ | |
6206 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
6207 | IGB_RX_HDR_LEN); | |
6208 | if (unlikely(!skb)) { | |
6209 | rx_ring->rx_stats.alloc_failed++; | |
6210 | return NULL; | |
6211 | } | |
6212 | ||
6213 | /* | |
6214 | * we will be copying header into skb->data in | |
6215 | * pskb_may_pull so it is in our interest to prefetch | |
6216 | * it now to avoid a possible cache miss | |
6217 | */ | |
6218 | prefetchw(skb->data); | |
6219 | } | |
6220 | ||
6221 | /* we are reusing so sync this buffer for CPU use */ | |
6222 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
6223 | rx_buffer->dma, | |
6224 | rx_buffer->page_offset, | |
de78d1f9 | 6225 | IGB_RX_BUFSZ, |
2e334eee AD |
6226 | DMA_FROM_DEVICE); |
6227 | ||
6228 | /* pull page into skb */ | |
6229 | if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
6230 | /* hand second half of page back to the ring */ | |
6231 | igb_reuse_rx_page(rx_ring, rx_buffer); | |
6232 | } else { | |
6233 | /* we are not reusing the buffer so unmap it */ | |
6234 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
6235 | PAGE_SIZE, DMA_FROM_DEVICE); | |
6236 | } | |
6237 | ||
6238 | /* clear contents of rx_buffer */ | |
6239 | rx_buffer->page = NULL; | |
6240 | ||
6241 | return skb; | |
6242 | } | |
6243 | ||
cd392f5c | 6244 | static inline void igb_rx_checksum(struct igb_ring *ring, |
3ceb90fd AD |
6245 | union e1000_adv_rx_desc *rx_desc, |
6246 | struct sk_buff *skb) | |
9d5c8243 | 6247 | { |
bc8acf2c | 6248 | skb_checksum_none_assert(skb); |
9d5c8243 | 6249 | |
294e7d78 | 6250 | /* Ignore Checksum bit is set */ |
3ceb90fd | 6251 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) |
294e7d78 AD |
6252 | return; |
6253 | ||
6254 | /* Rx checksum disabled via ethtool */ | |
6255 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) | |
9d5c8243 | 6256 | return; |
85ad76b2 | 6257 | |
9d5c8243 | 6258 | /* TCP/UDP checksum error bit is set */ |
3ceb90fd AD |
6259 | if (igb_test_staterr(rx_desc, |
6260 | E1000_RXDEXT_STATERR_TCPE | | |
6261 | E1000_RXDEXT_STATERR_IPE)) { | |
b9473560 JB |
6262 | /* |
6263 | * work around errata with sctp packets where the TCPE aka | |
6264 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) | |
6265 | * packets, (aka let the stack check the crc32c) | |
6266 | */ | |
866cff06 AD |
6267 | if (!((skb->len == 60) && |
6268 | test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { | |
12dcd86b | 6269 | u64_stats_update_begin(&ring->rx_syncp); |
04a5fcaa | 6270 | ring->rx_stats.csum_err++; |
12dcd86b ED |
6271 | u64_stats_update_end(&ring->rx_syncp); |
6272 | } | |
9d5c8243 | 6273 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
6274 | return; |
6275 | } | |
6276 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3ceb90fd AD |
6277 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | |
6278 | E1000_RXD_STAT_UDPCS)) | |
9d5c8243 AK |
6279 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
6280 | ||
3ceb90fd AD |
6281 | dev_dbg(ring->dev, "cksum success: bits %08X\n", |
6282 | le32_to_cpu(rx_desc->wb.upper.status_error)); | |
9d5c8243 AK |
6283 | } |
6284 | ||
077887c3 AD |
6285 | static inline void igb_rx_hash(struct igb_ring *ring, |
6286 | union e1000_adv_rx_desc *rx_desc, | |
6287 | struct sk_buff *skb) | |
6288 | { | |
6289 | if (ring->netdev->features & NETIF_F_RXHASH) | |
6290 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
6291 | } | |
6292 | ||
2e334eee AD |
6293 | /** |
6294 | * igb_is_non_eop - process handling of non-EOP buffers | |
6295 | * @rx_ring: Rx ring being processed | |
6296 | * @rx_desc: Rx descriptor for current buffer | |
6297 | * @skb: current socket buffer containing buffer in progress | |
6298 | * | |
6299 | * This function updates next to clean. If the buffer is an EOP buffer | |
6300 | * this function exits returning false, otherwise it will place the | |
6301 | * sk_buff in the next buffer to be chained and return true indicating | |
6302 | * that this is in fact a non-EOP buffer. | |
6303 | **/ | |
6304 | static bool igb_is_non_eop(struct igb_ring *rx_ring, | |
6305 | union e1000_adv_rx_desc *rx_desc) | |
6306 | { | |
6307 | u32 ntc = rx_ring->next_to_clean + 1; | |
6308 | ||
6309 | /* fetch, update, and store next to clean */ | |
6310 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
6311 | rx_ring->next_to_clean = ntc; | |
6312 | ||
6313 | prefetch(IGB_RX_DESC(rx_ring, ntc)); | |
6314 | ||
6315 | if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) | |
6316 | return false; | |
6317 | ||
6318 | return true; | |
6319 | } | |
6320 | ||
1a1c225b AD |
6321 | /** |
6322 | * igb_get_headlen - determine size of header for LRO/GRO | |
6323 | * @data: pointer to the start of the headers | |
6324 | * @max_len: total length of section to find headers in | |
6325 | * | |
6326 | * This function is meant to determine the length of headers that will | |
6327 | * be recognized by hardware for LRO, and GRO offloads. The main | |
6328 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
6329 | * packets so that we can do basic things like calculating the gso_size | |
6330 | * based on the average data per packet. | |
6331 | **/ | |
6332 | static unsigned int igb_get_headlen(unsigned char *data, | |
6333 | unsigned int max_len) | |
6334 | { | |
6335 | union { | |
6336 | unsigned char *network; | |
6337 | /* l2 headers */ | |
6338 | struct ethhdr *eth; | |
6339 | struct vlan_hdr *vlan; | |
6340 | /* l3 headers */ | |
6341 | struct iphdr *ipv4; | |
6342 | struct ipv6hdr *ipv6; | |
6343 | } hdr; | |
6344 | __be16 protocol; | |
6345 | u8 nexthdr = 0; /* default to not TCP */ | |
6346 | u8 hlen; | |
6347 | ||
6348 | /* this should never happen, but better safe than sorry */ | |
6349 | if (max_len < ETH_HLEN) | |
6350 | return max_len; | |
6351 | ||
6352 | /* initialize network frame pointer */ | |
6353 | hdr.network = data; | |
6354 | ||
6355 | /* set first protocol and move network header forward */ | |
6356 | protocol = hdr.eth->h_proto; | |
6357 | hdr.network += ETH_HLEN; | |
6358 | ||
6359 | /* handle any vlan tag if present */ | |
6360 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6361 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
6362 | return max_len; | |
6363 | ||
6364 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
6365 | hdr.network += VLAN_HLEN; | |
6366 | } | |
6367 | ||
6368 | /* handle L3 protocols */ | |
6369 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6370 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
6371 | return max_len; | |
6372 | ||
6373 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
6374 | hlen = (hdr.network[0] & 0x0F) << 2; | |
6375 | ||
6376 | /* verify hlen meets minimum size requirements */ | |
6377 | if (hlen < sizeof(struct iphdr)) | |
6378 | return hdr.network - data; | |
6379 | ||
f2fb4ab2 AD |
6380 | /* record next protocol if header is present */ |
6381 | if (!hdr.ipv4->frag_off) | |
6382 | nexthdr = hdr.ipv4->protocol; | |
1a1c225b AD |
6383 | } else if (protocol == __constant_htons(ETH_P_IPV6)) { |
6384 | if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) | |
6385 | return max_len; | |
6386 | ||
6387 | /* record next protocol */ | |
6388 | nexthdr = hdr.ipv6->nexthdr; | |
f2fb4ab2 | 6389 | hlen = sizeof(struct ipv6hdr); |
1a1c225b AD |
6390 | } else { |
6391 | return hdr.network - data; | |
6392 | } | |
6393 | ||
f2fb4ab2 AD |
6394 | /* relocate pointer to start of L4 header */ |
6395 | hdr.network += hlen; | |
6396 | ||
1a1c225b AD |
6397 | /* finally sort out TCP */ |
6398 | if (nexthdr == IPPROTO_TCP) { | |
6399 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
6400 | return max_len; | |
6401 | ||
6402 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
6403 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
6404 | ||
6405 | /* verify hlen meets minimum size requirements */ | |
6406 | if (hlen < sizeof(struct tcphdr)) | |
6407 | return hdr.network - data; | |
6408 | ||
6409 | hdr.network += hlen; | |
6410 | } else if (nexthdr == IPPROTO_UDP) { | |
6411 | if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) | |
6412 | return max_len; | |
6413 | ||
6414 | hdr.network += sizeof(struct udphdr); | |
6415 | } | |
6416 | ||
6417 | /* | |
6418 | * If everything has gone correctly hdr.network should be the | |
6419 | * data section of the packet and will be the end of the header. | |
6420 | * If not then it probably represents the end of the last recognized | |
6421 | * header. | |
6422 | */ | |
6423 | if ((hdr.network - data) < max_len) | |
6424 | return hdr.network - data; | |
6425 | else | |
6426 | return max_len; | |
6427 | } | |
6428 | ||
6429 | /** | |
6430 | * igb_pull_tail - igb specific version of skb_pull_tail | |
6431 | * @rx_ring: rx descriptor ring packet is being transacted on | |
cbc8e55f | 6432 | * @rx_desc: pointer to the EOP Rx descriptor |
1a1c225b AD |
6433 | * @skb: pointer to current skb being adjusted |
6434 | * | |
6435 | * This function is an igb specific version of __pskb_pull_tail. The | |
6436 | * main difference between this version and the original function is that | |
6437 | * this function can make several assumptions about the state of things | |
6438 | * that allow for significant optimizations versus the standard function. | |
6439 | * As a result we can do things like drop a frag and maintain an accurate | |
6440 | * truesize for the skb. | |
6441 | */ | |
6442 | static void igb_pull_tail(struct igb_ring *rx_ring, | |
6443 | union e1000_adv_rx_desc *rx_desc, | |
6444 | struct sk_buff *skb) | |
2d94d8ab | 6445 | { |
1a1c225b AD |
6446 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
6447 | unsigned char *va; | |
6448 | unsigned int pull_len; | |
6449 | ||
6450 | /* | |
6451 | * it is valid to use page_address instead of kmap since we are | |
6452 | * working with pages allocated out of the lomem pool per | |
6453 | * alloc_page(GFP_ATOMIC) | |
2d94d8ab | 6454 | */ |
1a1c225b AD |
6455 | va = skb_frag_address(frag); |
6456 | ||
1a1c225b AD |
6457 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6458 | /* retrieve timestamp from buffer */ | |
6459 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6460 | ||
6461 | /* update pointers to remove timestamp header */ | |
6462 | skb_frag_size_sub(frag, IGB_TS_HDR_LEN); | |
6463 | frag->page_offset += IGB_TS_HDR_LEN; | |
6464 | skb->data_len -= IGB_TS_HDR_LEN; | |
6465 | skb->len -= IGB_TS_HDR_LEN; | |
6466 | ||
6467 | /* move va to start of packet data */ | |
6468 | va += IGB_TS_HDR_LEN; | |
6469 | } | |
6470 | ||
1a1c225b AD |
6471 | /* |
6472 | * we need the header to contain the greater of either ETH_HLEN or | |
6473 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
6474 | */ | |
6475 | pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); | |
6476 | ||
6477 | /* align pull length to size of long to optimize memcpy performance */ | |
6478 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
6479 | ||
6480 | /* update all of the pointers */ | |
6481 | skb_frag_size_sub(frag, pull_len); | |
6482 | frag->page_offset += pull_len; | |
6483 | skb->data_len -= pull_len; | |
6484 | skb->tail += pull_len; | |
6485 | } | |
6486 | ||
6487 | /** | |
6488 | * igb_cleanup_headers - Correct corrupted or empty headers | |
6489 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6490 | * @rx_desc: pointer to the EOP Rx descriptor | |
6491 | * @skb: pointer to current skb being fixed | |
6492 | * | |
6493 | * Address the case where we are pulling data in on pages only | |
6494 | * and as such no data is present in the skb header. | |
6495 | * | |
6496 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
6497 | * it is large enough to qualify as a valid Ethernet frame. | |
6498 | * | |
6499 | * Returns true if an error was encountered and skb was freed. | |
6500 | **/ | |
6501 | static bool igb_cleanup_headers(struct igb_ring *rx_ring, | |
6502 | union e1000_adv_rx_desc *rx_desc, | |
6503 | struct sk_buff *skb) | |
6504 | { | |
6505 | ||
6506 | if (unlikely((igb_test_staterr(rx_desc, | |
6507 | E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { | |
6508 | struct net_device *netdev = rx_ring->netdev; | |
6509 | if (!(netdev->features & NETIF_F_RXALL)) { | |
6510 | dev_kfree_skb_any(skb); | |
6511 | return true; | |
6512 | } | |
6513 | } | |
6514 | ||
6515 | /* place header in linear portion of buffer */ | |
6516 | if (skb_is_nonlinear(skb)) | |
6517 | igb_pull_tail(rx_ring, rx_desc, skb); | |
6518 | ||
6519 | /* if skb_pad returns an error the skb was freed */ | |
6520 | if (unlikely(skb->len < 60)) { | |
6521 | int pad_len = 60 - skb->len; | |
6522 | ||
6523 | if (skb_pad(skb, pad_len)) | |
6524 | return true; | |
6525 | __skb_put(skb, pad_len); | |
6526 | } | |
6527 | ||
6528 | return false; | |
2d94d8ab AD |
6529 | } |
6530 | ||
db2ee5bd AD |
6531 | /** |
6532 | * igb_process_skb_fields - Populate skb header fields from Rx descriptor | |
6533 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6534 | * @rx_desc: pointer to the EOP Rx descriptor | |
6535 | * @skb: pointer to current skb being populated | |
6536 | * | |
6537 | * This function checks the ring, descriptor, and packet information in | |
6538 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
6539 | * other fields within the skb. | |
6540 | **/ | |
6541 | static void igb_process_skb_fields(struct igb_ring *rx_ring, | |
6542 | union e1000_adv_rx_desc *rx_desc, | |
6543 | struct sk_buff *skb) | |
6544 | { | |
6545 | struct net_device *dev = rx_ring->netdev; | |
6546 | ||
6547 | igb_rx_hash(rx_ring, rx_desc, skb); | |
6548 | ||
6549 | igb_rx_checksum(rx_ring, rx_desc, skb); | |
6550 | ||
db2ee5bd | 6551 | igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
db2ee5bd AD |
6552 | |
6553 | if ((dev->features & NETIF_F_HW_VLAN_RX) && | |
6554 | igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { | |
6555 | u16 vid; | |
6556 | if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && | |
6557 | test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) | |
6558 | vid = be16_to_cpu(rx_desc->wb.upper.vlan); | |
6559 | else | |
6560 | vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
6561 | ||
6562 | __vlan_hwaccel_put_tag(skb, vid); | |
6563 | } | |
6564 | ||
6565 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
6566 | ||
6567 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
6568 | } | |
6569 | ||
2e334eee | 6570 | static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) |
9d5c8243 | 6571 | { |
0ba82994 | 6572 | struct igb_ring *rx_ring = q_vector->rx.ring; |
1a1c225b | 6573 | struct sk_buff *skb = rx_ring->skb; |
9d5c8243 | 6574 | unsigned int total_bytes = 0, total_packets = 0; |
16eb8815 | 6575 | u16 cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 | 6576 | |
2e334eee AD |
6577 | do { |
6578 | union e1000_adv_rx_desc *rx_desc; | |
bf36c1a0 | 6579 | |
2e334eee AD |
6580 | /* return some buffers to hardware, one at a time is too slow */ |
6581 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
6582 | igb_alloc_rx_buffers(rx_ring, cleaned_count); | |
6583 | cleaned_count = 0; | |
6584 | } | |
bf36c1a0 | 6585 | |
2e334eee | 6586 | rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); |
16eb8815 | 6587 | |
2e334eee AD |
6588 | if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) |
6589 | break; | |
9d5c8243 | 6590 | |
2e334eee AD |
6591 | /* retrieve a buffer from the ring */ |
6592 | skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); | |
9d5c8243 | 6593 | |
2e334eee AD |
6594 | /* exit if we failed to retrieve a buffer */ |
6595 | if (!skb) | |
6596 | break; | |
1a1c225b | 6597 | |
2e334eee | 6598 | cleaned_count++; |
1a1c225b | 6599 | |
2e334eee AD |
6600 | /* fetch next buffer in frame if non-eop */ |
6601 | if (igb_is_non_eop(rx_ring, rx_desc)) | |
6602 | continue; | |
1a1c225b AD |
6603 | |
6604 | /* verify the packet layout is correct */ | |
6605 | if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { | |
6606 | skb = NULL; | |
6607 | continue; | |
9d5c8243 | 6608 | } |
9d5c8243 | 6609 | |
db2ee5bd | 6610 | /* probably a little skewed due to removing CRC */ |
3ceb90fd | 6611 | total_bytes += skb->len; |
3ceb90fd | 6612 | |
db2ee5bd AD |
6613 | /* populate checksum, timestamp, VLAN, and protocol */ |
6614 | igb_process_skb_fields(rx_ring, rx_desc, skb); | |
3ceb90fd | 6615 | |
b2cb09b1 | 6616 | napi_gro_receive(&q_vector->napi, skb); |
9d5c8243 | 6617 | |
1a1c225b AD |
6618 | /* reset skb pointer */ |
6619 | skb = NULL; | |
6620 | ||
2e334eee AD |
6621 | /* update budget accounting */ |
6622 | total_packets++; | |
6623 | } while (likely(total_packets < budget)); | |
bf36c1a0 | 6624 | |
1a1c225b AD |
6625 | /* place incomplete frames back on ring for completion */ |
6626 | rx_ring->skb = skb; | |
6627 | ||
12dcd86b | 6628 | u64_stats_update_begin(&rx_ring->rx_syncp); |
9d5c8243 AK |
6629 | rx_ring->rx_stats.packets += total_packets; |
6630 | rx_ring->rx_stats.bytes += total_bytes; | |
12dcd86b | 6631 | u64_stats_update_end(&rx_ring->rx_syncp); |
0ba82994 AD |
6632 | q_vector->rx.total_packets += total_packets; |
6633 | q_vector->rx.total_bytes += total_bytes; | |
c023cd88 AD |
6634 | |
6635 | if (cleaned_count) | |
cd392f5c | 6636 | igb_alloc_rx_buffers(rx_ring, cleaned_count); |
c023cd88 | 6637 | |
2e334eee | 6638 | return (total_packets < budget); |
9d5c8243 AK |
6639 | } |
6640 | ||
c023cd88 | 6641 | static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, |
06034649 | 6642 | struct igb_rx_buffer *bi) |
c023cd88 AD |
6643 | { |
6644 | struct page *page = bi->page; | |
cbc8e55f | 6645 | dma_addr_t dma; |
c023cd88 | 6646 | |
cbc8e55f AD |
6647 | /* since we are recycling buffers we should seldom need to alloc */ |
6648 | if (likely(page)) | |
c023cd88 AD |
6649 | return true; |
6650 | ||
cbc8e55f AD |
6651 | /* alloc new page for storage */ |
6652 | page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); | |
6653 | if (unlikely(!page)) { | |
6654 | rx_ring->rx_stats.alloc_failed++; | |
6655 | return false; | |
c023cd88 AD |
6656 | } |
6657 | ||
cbc8e55f AD |
6658 | /* map page for use */ |
6659 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
c023cd88 | 6660 | |
cbc8e55f AD |
6661 | /* |
6662 | * if mapping failed free memory back to system since | |
6663 | * there isn't much point in holding memory we can't use | |
6664 | */ | |
1a1c225b | 6665 | if (dma_mapping_error(rx_ring->dev, dma)) { |
cbc8e55f AD |
6666 | __free_page(page); |
6667 | ||
c023cd88 AD |
6668 | rx_ring->rx_stats.alloc_failed++; |
6669 | return false; | |
6670 | } | |
6671 | ||
1a1c225b | 6672 | bi->dma = dma; |
cbc8e55f AD |
6673 | bi->page = page; |
6674 | bi->page_offset = 0; | |
1a1c225b | 6675 | |
c023cd88 AD |
6676 | return true; |
6677 | } | |
6678 | ||
9d5c8243 | 6679 | /** |
cd392f5c | 6680 | * igb_alloc_rx_buffers - Replace used receive buffers; packet split |
9d5c8243 AK |
6681 | * @adapter: address of board private structure |
6682 | **/ | |
cd392f5c | 6683 | void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) |
9d5c8243 | 6684 | { |
9d5c8243 | 6685 | union e1000_adv_rx_desc *rx_desc; |
06034649 | 6686 | struct igb_rx_buffer *bi; |
c023cd88 | 6687 | u16 i = rx_ring->next_to_use; |
9d5c8243 | 6688 | |
cbc8e55f AD |
6689 | /* nothing to do */ |
6690 | if (!cleaned_count) | |
6691 | return; | |
6692 | ||
60136906 | 6693 | rx_desc = IGB_RX_DESC(rx_ring, i); |
06034649 | 6694 | bi = &rx_ring->rx_buffer_info[i]; |
c023cd88 | 6695 | i -= rx_ring->count; |
9d5c8243 | 6696 | |
cbc8e55f | 6697 | do { |
1a1c225b | 6698 | if (!igb_alloc_mapped_page(rx_ring, bi)) |
c023cd88 | 6699 | break; |
9d5c8243 | 6700 | |
cbc8e55f AD |
6701 | /* |
6702 | * Refresh the desc even if buffer_addrs didn't change | |
6703 | * because each write-back erases this info. | |
6704 | */ | |
6705 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9d5c8243 | 6706 | |
c023cd88 AD |
6707 | rx_desc++; |
6708 | bi++; | |
9d5c8243 | 6709 | i++; |
c023cd88 | 6710 | if (unlikely(!i)) { |
60136906 | 6711 | rx_desc = IGB_RX_DESC(rx_ring, 0); |
06034649 | 6712 | bi = rx_ring->rx_buffer_info; |
c023cd88 AD |
6713 | i -= rx_ring->count; |
6714 | } | |
6715 | ||
6716 | /* clear the hdr_addr for the next_to_use descriptor */ | |
6717 | rx_desc->read.hdr_addr = 0; | |
cbc8e55f AD |
6718 | |
6719 | cleaned_count--; | |
6720 | } while (cleaned_count); | |
9d5c8243 | 6721 | |
c023cd88 AD |
6722 | i += rx_ring->count; |
6723 | ||
9d5c8243 | 6724 | if (rx_ring->next_to_use != i) { |
cbc8e55f | 6725 | /* record the next descriptor to use */ |
9d5c8243 | 6726 | rx_ring->next_to_use = i; |
9d5c8243 | 6727 | |
cbc8e55f AD |
6728 | /* update next to alloc since we have filled the ring */ |
6729 | rx_ring->next_to_alloc = i; | |
6730 | ||
6731 | /* | |
6732 | * Force memory writes to complete before letting h/w | |
9d5c8243 AK |
6733 | * know there are new descriptors to fetch. (Only |
6734 | * applicable for weak-ordered memory model archs, | |
cbc8e55f AD |
6735 | * such as IA-64). |
6736 | */ | |
9d5c8243 | 6737 | wmb(); |
fce99e34 | 6738 | writel(i, rx_ring->tail); |
9d5c8243 AK |
6739 | } |
6740 | } | |
6741 | ||
6742 | /** | |
6743 | * igb_mii_ioctl - | |
6744 | * @netdev: | |
6745 | * @ifreq: | |
6746 | * @cmd: | |
6747 | **/ | |
6748 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6749 | { | |
6750 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6751 | struct mii_ioctl_data *data = if_mii(ifr); | |
6752 | ||
6753 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
6754 | return -EOPNOTSUPP; | |
6755 | ||
6756 | switch (cmd) { | |
6757 | case SIOCGMIIPHY: | |
6758 | data->phy_id = adapter->hw.phy.addr; | |
6759 | break; | |
6760 | case SIOCGMIIREG: | |
f5f4cf08 AD |
6761 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
6762 | &data->val_out)) | |
9d5c8243 AK |
6763 | return -EIO; |
6764 | break; | |
6765 | case SIOCSMIIREG: | |
6766 | default: | |
6767 | return -EOPNOTSUPP; | |
6768 | } | |
6769 | return 0; | |
6770 | } | |
6771 | ||
6772 | /** | |
6773 | * igb_ioctl - | |
6774 | * @netdev: | |
6775 | * @ifreq: | |
6776 | * @cmd: | |
6777 | **/ | |
6778 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6779 | { | |
6780 | switch (cmd) { | |
6781 | case SIOCGMIIPHY: | |
6782 | case SIOCGMIIREG: | |
6783 | case SIOCSMIIREG: | |
6784 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b | 6785 | case SIOCSHWTSTAMP: |
a79f4f88 | 6786 | return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); |
9d5c8243 AK |
6787 | default: |
6788 | return -EOPNOTSUPP; | |
6789 | } | |
6790 | } | |
6791 | ||
009bc06e AD |
6792 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
6793 | { | |
6794 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6795 | |
23d028cc | 6796 | if (pcie_capability_read_word(adapter->pdev, reg, value)) |
009bc06e AD |
6797 | return -E1000_ERR_CONFIG; |
6798 | ||
009bc06e AD |
6799 | return 0; |
6800 | } | |
6801 | ||
6802 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
6803 | { | |
6804 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6805 | |
23d028cc | 6806 | if (pcie_capability_write_word(adapter->pdev, reg, *value)) |
009bc06e AD |
6807 | return -E1000_ERR_CONFIG; |
6808 | ||
009bc06e AD |
6809 | return 0; |
6810 | } | |
6811 | ||
c8f44aff | 6812 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) |
9d5c8243 AK |
6813 | { |
6814 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6815 | struct e1000_hw *hw = &adapter->hw; | |
6816 | u32 ctrl, rctl; | |
5faf030c | 6817 | bool enable = !!(features & NETIF_F_HW_VLAN_RX); |
9d5c8243 | 6818 | |
5faf030c | 6819 | if (enable) { |
9d5c8243 AK |
6820 | /* enable VLAN tag insert/strip */ |
6821 | ctrl = rd32(E1000_CTRL); | |
6822 | ctrl |= E1000_CTRL_VME; | |
6823 | wr32(E1000_CTRL, ctrl); | |
6824 | ||
51466239 | 6825 | /* Disable CFI check */ |
9d5c8243 | 6826 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
6827 | rctl &= ~E1000_RCTL_CFIEN; |
6828 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
6829 | } else { |
6830 | /* disable VLAN tag insert/strip */ | |
6831 | ctrl = rd32(E1000_CTRL); | |
6832 | ctrl &= ~E1000_CTRL_VME; | |
6833 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
6834 | } |
6835 | ||
e1739522 | 6836 | igb_rlpml_set(adapter); |
9d5c8243 AK |
6837 | } |
6838 | ||
8e586137 | 6839 | static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
9d5c8243 AK |
6840 | { |
6841 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6842 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6843 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 6844 | |
51466239 AD |
6845 | /* attempt to add filter to vlvf array */ |
6846 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 6847 | |
51466239 AD |
6848 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
6849 | igb_vfta_set(hw, vid, true); | |
b2cb09b1 JP |
6850 | |
6851 | set_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6852 | |
6853 | return 0; | |
9d5c8243 AK |
6854 | } |
6855 | ||
8e586137 | 6856 | static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
9d5c8243 AK |
6857 | { |
6858 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6859 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6860 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 6861 | s32 err; |
9d5c8243 | 6862 | |
51466239 AD |
6863 | /* remove vlan from VLVF table array */ |
6864 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 6865 | |
51466239 AD |
6866 | /* if vid was not present in VLVF just remove it from table */ |
6867 | if (err) | |
4ae196df | 6868 | igb_vfta_set(hw, vid, false); |
b2cb09b1 JP |
6869 | |
6870 | clear_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6871 | |
6872 | return 0; | |
9d5c8243 AK |
6873 | } |
6874 | ||
6875 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
6876 | { | |
b2cb09b1 | 6877 | u16 vid; |
9d5c8243 | 6878 | |
5faf030c AD |
6879 | igb_vlan_mode(adapter->netdev, adapter->netdev->features); |
6880 | ||
b2cb09b1 JP |
6881 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
6882 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
9d5c8243 AK |
6883 | } |
6884 | ||
14ad2513 | 6885 | int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) |
9d5c8243 | 6886 | { |
090b1795 | 6887 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
6888 | struct e1000_mac_info *mac = &adapter->hw.mac; |
6889 | ||
6890 | mac->autoneg = 0; | |
6891 | ||
14ad2513 DD |
6892 | /* Make sure dplx is at most 1 bit and lsb of speed is not set |
6893 | * for the switch() below to work */ | |
6894 | if ((spd & 1) || (dplx & ~1)) | |
6895 | goto err_inval; | |
6896 | ||
cd2638a8 CW |
6897 | /* Fiber NIC's only allow 1000 Gbps Full duplex */ |
6898 | if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && | |
14ad2513 DD |
6899 | spd != SPEED_1000 && |
6900 | dplx != DUPLEX_FULL) | |
6901 | goto err_inval; | |
cd2638a8 | 6902 | |
14ad2513 | 6903 | switch (spd + dplx) { |
9d5c8243 AK |
6904 | case SPEED_10 + DUPLEX_HALF: |
6905 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
6906 | break; | |
6907 | case SPEED_10 + DUPLEX_FULL: | |
6908 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
6909 | break; | |
6910 | case SPEED_100 + DUPLEX_HALF: | |
6911 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
6912 | break; | |
6913 | case SPEED_100 + DUPLEX_FULL: | |
6914 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
6915 | break; | |
6916 | case SPEED_1000 + DUPLEX_FULL: | |
6917 | mac->autoneg = 1; | |
6918 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
6919 | break; | |
6920 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
6921 | default: | |
14ad2513 | 6922 | goto err_inval; |
9d5c8243 | 6923 | } |
8376dad0 JB |
6924 | |
6925 | /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ | |
6926 | adapter->hw.phy.mdix = AUTO_ALL_MODES; | |
6927 | ||
9d5c8243 | 6928 | return 0; |
14ad2513 DD |
6929 | |
6930 | err_inval: | |
6931 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); | |
6932 | return -EINVAL; | |
9d5c8243 AK |
6933 | } |
6934 | ||
749ab2cd YZ |
6935 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, |
6936 | bool runtime) | |
9d5c8243 AK |
6937 | { |
6938 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6939 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6940 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 6941 | u32 ctrl, rctl, status; |
749ab2cd | 6942 | u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; |
9d5c8243 AK |
6943 | #ifdef CONFIG_PM |
6944 | int retval = 0; | |
6945 | #endif | |
6946 | ||
6947 | netif_device_detach(netdev); | |
6948 | ||
a88f10ec | 6949 | if (netif_running(netdev)) |
749ab2cd | 6950 | __igb_close(netdev, true); |
a88f10ec | 6951 | |
047e0030 | 6952 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
6953 | |
6954 | #ifdef CONFIG_PM | |
6955 | retval = pci_save_state(pdev); | |
6956 | if (retval) | |
6957 | return retval; | |
6958 | #endif | |
6959 | ||
6960 | status = rd32(E1000_STATUS); | |
6961 | if (status & E1000_STATUS_LU) | |
6962 | wufc &= ~E1000_WUFC_LNKC; | |
6963 | ||
6964 | if (wufc) { | |
6965 | igb_setup_rctl(adapter); | |
ff41f8dc | 6966 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
6967 | |
6968 | /* turn on all-multi mode if wake on multicast is enabled */ | |
6969 | if (wufc & E1000_WUFC_MC) { | |
6970 | rctl = rd32(E1000_RCTL); | |
6971 | rctl |= E1000_RCTL_MPE; | |
6972 | wr32(E1000_RCTL, rctl); | |
6973 | } | |
6974 | ||
6975 | ctrl = rd32(E1000_CTRL); | |
6976 | /* advertise wake from D3Cold */ | |
6977 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
6978 | /* phy power management enable */ | |
6979 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
6980 | ctrl |= E1000_CTRL_ADVD3WUC; | |
6981 | wr32(E1000_CTRL, ctrl); | |
6982 | ||
9d5c8243 | 6983 | /* Allow time for pending master requests to run */ |
330a6d6a | 6984 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
6985 | |
6986 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
6987 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
6988 | } else { |
6989 | wr32(E1000_WUC, 0); | |
6990 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
6991 | } |
6992 | ||
3fe7c4c9 RW |
6993 | *enable_wake = wufc || adapter->en_mng_pt; |
6994 | if (!*enable_wake) | |
88a268c1 NN |
6995 | igb_power_down_link(adapter); |
6996 | else | |
6997 | igb_power_up_link(adapter); | |
9d5c8243 AK |
6998 | |
6999 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
7000 | * would have already happened in close and is redundant. */ | |
7001 | igb_release_hw_control(adapter); | |
7002 | ||
7003 | pci_disable_device(pdev); | |
7004 | ||
9d5c8243 AK |
7005 | return 0; |
7006 | } | |
7007 | ||
7008 | #ifdef CONFIG_PM | |
d9dd966d | 7009 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 7010 | static int igb_suspend(struct device *dev) |
3fe7c4c9 RW |
7011 | { |
7012 | int retval; | |
7013 | bool wake; | |
749ab2cd | 7014 | struct pci_dev *pdev = to_pci_dev(dev); |
3fe7c4c9 | 7015 | |
749ab2cd | 7016 | retval = __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
7017 | if (retval) |
7018 | return retval; | |
7019 | ||
7020 | if (wake) { | |
7021 | pci_prepare_to_sleep(pdev); | |
7022 | } else { | |
7023 | pci_wake_from_d3(pdev, false); | |
7024 | pci_set_power_state(pdev, PCI_D3hot); | |
7025 | } | |
7026 | ||
7027 | return 0; | |
7028 | } | |
d9dd966d | 7029 | #endif /* CONFIG_PM_SLEEP */ |
3fe7c4c9 | 7030 | |
749ab2cd | 7031 | static int igb_resume(struct device *dev) |
9d5c8243 | 7032 | { |
749ab2cd | 7033 | struct pci_dev *pdev = to_pci_dev(dev); |
9d5c8243 AK |
7034 | struct net_device *netdev = pci_get_drvdata(pdev); |
7035 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7036 | struct e1000_hw *hw = &adapter->hw; | |
7037 | u32 err; | |
7038 | ||
7039 | pci_set_power_state(pdev, PCI_D0); | |
7040 | pci_restore_state(pdev); | |
b94f2d77 | 7041 | pci_save_state(pdev); |
42bfd33a | 7042 | |
aed5dec3 | 7043 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
7044 | if (err) { |
7045 | dev_err(&pdev->dev, | |
7046 | "igb: Cannot enable PCI device from suspend\n"); | |
7047 | return err; | |
7048 | } | |
7049 | pci_set_master(pdev); | |
7050 | ||
7051 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
7052 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
7053 | ||
53c7d064 | 7054 | if (igb_init_interrupt_scheme(adapter, true)) { |
a88f10ec AD |
7055 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
7056 | return -ENOMEM; | |
9d5c8243 AK |
7057 | } |
7058 | ||
9d5c8243 | 7059 | igb_reset(adapter); |
a8564f03 AD |
7060 | |
7061 | /* let the f/w know that the h/w is now under the control of the | |
7062 | * driver. */ | |
7063 | igb_get_hw_control(adapter); | |
7064 | ||
9d5c8243 AK |
7065 | wr32(E1000_WUS, ~0); |
7066 | ||
749ab2cd | 7067 | if (netdev->flags & IFF_UP) { |
0c2cc02e | 7068 | rtnl_lock(); |
749ab2cd | 7069 | err = __igb_open(netdev, true); |
0c2cc02e | 7070 | rtnl_unlock(); |
a88f10ec AD |
7071 | if (err) |
7072 | return err; | |
7073 | } | |
9d5c8243 AK |
7074 | |
7075 | netif_device_attach(netdev); | |
749ab2cd YZ |
7076 | return 0; |
7077 | } | |
7078 | ||
7079 | #ifdef CONFIG_PM_RUNTIME | |
7080 | static int igb_runtime_idle(struct device *dev) | |
7081 | { | |
7082 | struct pci_dev *pdev = to_pci_dev(dev); | |
7083 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7084 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7085 | ||
7086 | if (!igb_has_link(adapter)) | |
7087 | pm_schedule_suspend(dev, MSEC_PER_SEC * 5); | |
7088 | ||
7089 | return -EBUSY; | |
7090 | } | |
7091 | ||
7092 | static int igb_runtime_suspend(struct device *dev) | |
7093 | { | |
7094 | struct pci_dev *pdev = to_pci_dev(dev); | |
7095 | int retval; | |
7096 | bool wake; | |
7097 | ||
7098 | retval = __igb_shutdown(pdev, &wake, 1); | |
7099 | if (retval) | |
7100 | return retval; | |
7101 | ||
7102 | if (wake) { | |
7103 | pci_prepare_to_sleep(pdev); | |
7104 | } else { | |
7105 | pci_wake_from_d3(pdev, false); | |
7106 | pci_set_power_state(pdev, PCI_D3hot); | |
7107 | } | |
9d5c8243 | 7108 | |
9d5c8243 AK |
7109 | return 0; |
7110 | } | |
749ab2cd YZ |
7111 | |
7112 | static int igb_runtime_resume(struct device *dev) | |
7113 | { | |
7114 | return igb_resume(dev); | |
7115 | } | |
7116 | #endif /* CONFIG_PM_RUNTIME */ | |
9d5c8243 AK |
7117 | #endif |
7118 | ||
7119 | static void igb_shutdown(struct pci_dev *pdev) | |
7120 | { | |
3fe7c4c9 RW |
7121 | bool wake; |
7122 | ||
749ab2cd | 7123 | __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
7124 | |
7125 | if (system_state == SYSTEM_POWER_OFF) { | |
7126 | pci_wake_from_d3(pdev, wake); | |
7127 | pci_set_power_state(pdev, PCI_D3hot); | |
7128 | } | |
9d5c8243 AK |
7129 | } |
7130 | ||
fa44f2f1 GR |
7131 | #ifdef CONFIG_PCI_IOV |
7132 | static int igb_sriov_reinit(struct pci_dev *dev) | |
7133 | { | |
7134 | struct net_device *netdev = pci_get_drvdata(dev); | |
7135 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7136 | struct pci_dev *pdev = adapter->pdev; | |
7137 | ||
7138 | rtnl_lock(); | |
7139 | ||
7140 | if (netif_running(netdev)) | |
7141 | igb_close(netdev); | |
7142 | ||
7143 | igb_clear_interrupt_scheme(adapter); | |
7144 | ||
7145 | igb_init_queue_configuration(adapter); | |
7146 | ||
7147 | if (igb_init_interrupt_scheme(adapter, true)) { | |
7148 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
7149 | return -ENOMEM; | |
7150 | } | |
7151 | ||
7152 | if (netif_running(netdev)) | |
7153 | igb_open(netdev); | |
7154 | ||
7155 | rtnl_unlock(); | |
7156 | ||
7157 | return 0; | |
7158 | } | |
7159 | ||
7160 | static int igb_pci_disable_sriov(struct pci_dev *dev) | |
7161 | { | |
7162 | int err = igb_disable_sriov(dev); | |
7163 | ||
7164 | if (!err) | |
7165 | err = igb_sriov_reinit(dev); | |
7166 | ||
7167 | return err; | |
7168 | } | |
7169 | ||
7170 | static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) | |
7171 | { | |
7172 | int err = igb_enable_sriov(dev, num_vfs); | |
7173 | ||
7174 | if (err) | |
7175 | goto out; | |
7176 | ||
7177 | err = igb_sriov_reinit(dev); | |
7178 | if (!err) | |
7179 | return num_vfs; | |
7180 | ||
7181 | out: | |
7182 | return err; | |
7183 | } | |
7184 | ||
7185 | #endif | |
7186 | static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) | |
7187 | { | |
7188 | #ifdef CONFIG_PCI_IOV | |
7189 | if (num_vfs == 0) | |
7190 | return igb_pci_disable_sriov(dev); | |
7191 | else | |
7192 | return igb_pci_enable_sriov(dev, num_vfs); | |
7193 | #endif | |
7194 | return 0; | |
7195 | } | |
7196 | ||
9d5c8243 AK |
7197 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7198 | /* | |
7199 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
7200 | * without having to re-enable interrupts. It's not called while | |
7201 | * the interrupt routine is executing. | |
7202 | */ | |
7203 | static void igb_netpoll(struct net_device *netdev) | |
7204 | { | |
7205 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 7206 | struct e1000_hw *hw = &adapter->hw; |
0d1ae7f4 | 7207 | struct igb_q_vector *q_vector; |
9d5c8243 | 7208 | int i; |
9d5c8243 | 7209 | |
047e0030 | 7210 | for (i = 0; i < adapter->num_q_vectors; i++) { |
0d1ae7f4 AD |
7211 | q_vector = adapter->q_vector[i]; |
7212 | if (adapter->msix_entries) | |
7213 | wr32(E1000_EIMC, q_vector->eims_value); | |
7214 | else | |
7215 | igb_irq_disable(adapter); | |
047e0030 | 7216 | napi_schedule(&q_vector->napi); |
eebbbdba | 7217 | } |
9d5c8243 AK |
7218 | } |
7219 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
7220 | ||
7221 | /** | |
7222 | * igb_io_error_detected - called when PCI error is detected | |
7223 | * @pdev: Pointer to PCI device | |
7224 | * @state: The current pci connection state | |
7225 | * | |
7226 | * This function is called after a PCI bus error affecting | |
7227 | * this device has been detected. | |
7228 | */ | |
7229 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
7230 | pci_channel_state_t state) | |
7231 | { | |
7232 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7233 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7234 | ||
7235 | netif_device_detach(netdev); | |
7236 | ||
59ed6eec AD |
7237 | if (state == pci_channel_io_perm_failure) |
7238 | return PCI_ERS_RESULT_DISCONNECT; | |
7239 | ||
9d5c8243 AK |
7240 | if (netif_running(netdev)) |
7241 | igb_down(adapter); | |
7242 | pci_disable_device(pdev); | |
7243 | ||
7244 | /* Request a slot slot reset. */ | |
7245 | return PCI_ERS_RESULT_NEED_RESET; | |
7246 | } | |
7247 | ||
7248 | /** | |
7249 | * igb_io_slot_reset - called after the pci bus has been reset. | |
7250 | * @pdev: Pointer to PCI device | |
7251 | * | |
7252 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
7253 | * resembles the first-half of the igb_resume routine. | |
7254 | */ | |
7255 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
7256 | { | |
7257 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7258 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7259 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 7260 | pci_ers_result_t result; |
42bfd33a | 7261 | int err; |
9d5c8243 | 7262 | |
aed5dec3 | 7263 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
7264 | dev_err(&pdev->dev, |
7265 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
7266 | result = PCI_ERS_RESULT_DISCONNECT; |
7267 | } else { | |
7268 | pci_set_master(pdev); | |
7269 | pci_restore_state(pdev); | |
b94f2d77 | 7270 | pci_save_state(pdev); |
9d5c8243 | 7271 | |
40a914fa AD |
7272 | pci_enable_wake(pdev, PCI_D3hot, 0); |
7273 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 7274 | |
40a914fa AD |
7275 | igb_reset(adapter); |
7276 | wr32(E1000_WUS, ~0); | |
7277 | result = PCI_ERS_RESULT_RECOVERED; | |
7278 | } | |
9d5c8243 | 7279 | |
ea943d41 JK |
7280 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
7281 | if (err) { | |
7282 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
7283 | "failed 0x%0x\n", err); | |
7284 | /* non-fatal, continue */ | |
7285 | } | |
40a914fa AD |
7286 | |
7287 | return result; | |
9d5c8243 AK |
7288 | } |
7289 | ||
7290 | /** | |
7291 | * igb_io_resume - called when traffic can start flowing again. | |
7292 | * @pdev: Pointer to PCI device | |
7293 | * | |
7294 | * This callback is called when the error recovery driver tells us that | |
7295 | * its OK to resume normal operation. Implementation resembles the | |
7296 | * second-half of the igb_resume routine. | |
7297 | */ | |
7298 | static void igb_io_resume(struct pci_dev *pdev) | |
7299 | { | |
7300 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7301 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7302 | ||
9d5c8243 AK |
7303 | if (netif_running(netdev)) { |
7304 | if (igb_up(adapter)) { | |
7305 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
7306 | return; | |
7307 | } | |
7308 | } | |
7309 | ||
7310 | netif_device_attach(netdev); | |
7311 | ||
7312 | /* let the f/w know that the h/w is now under the control of the | |
7313 | * driver. */ | |
7314 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
7315 | } |
7316 | ||
26ad9178 AD |
7317 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
7318 | u8 qsel) | |
7319 | { | |
7320 | u32 rar_low, rar_high; | |
7321 | struct e1000_hw *hw = &adapter->hw; | |
7322 | ||
7323 | /* HW expects these in little endian so we reverse the byte order | |
7324 | * from network order (big endian) to little endian | |
7325 | */ | |
7326 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
7327 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
7328 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
7329 | ||
7330 | /* Indicate to hardware the Address is Valid. */ | |
7331 | rar_high |= E1000_RAH_AV; | |
7332 | ||
7333 | if (hw->mac.type == e1000_82575) | |
7334 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
7335 | else | |
7336 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
7337 | ||
7338 | wr32(E1000_RAL(index), rar_low); | |
7339 | wrfl(); | |
7340 | wr32(E1000_RAH(index), rar_high); | |
7341 | wrfl(); | |
7342 | } | |
7343 | ||
4ae196df AD |
7344 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
7345 | int vf, unsigned char *mac_addr) | |
7346 | { | |
7347 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc AD |
7348 | /* VF MAC addresses start at end of receive addresses and moves |
7349 | * torwards the first, as a result a collision should not be possible */ | |
7350 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); | |
4ae196df | 7351 | |
37680117 | 7352 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 7353 | |
26ad9178 | 7354 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
7355 | |
7356 | return 0; | |
7357 | } | |
7358 | ||
8151d294 WM |
7359 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
7360 | { | |
7361 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7362 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | |
7363 | return -EINVAL; | |
7364 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | |
7365 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | |
7366 | dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" | |
7367 | " change effective."); | |
7368 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
7369 | dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," | |
7370 | " but the PF device is not up.\n"); | |
7371 | dev_warn(&adapter->pdev->dev, "Bring the PF device up before" | |
7372 | " attempting to use the VF device.\n"); | |
7373 | } | |
7374 | return igb_set_vf_mac(adapter, vf, mac); | |
7375 | } | |
7376 | ||
17dc566c LL |
7377 | static int igb_link_mbps(int internal_link_speed) |
7378 | { | |
7379 | switch (internal_link_speed) { | |
7380 | case SPEED_100: | |
7381 | return 100; | |
7382 | case SPEED_1000: | |
7383 | return 1000; | |
7384 | default: | |
7385 | return 0; | |
7386 | } | |
7387 | } | |
7388 | ||
7389 | static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, | |
7390 | int link_speed) | |
7391 | { | |
7392 | int rf_dec, rf_int; | |
7393 | u32 bcnrc_val; | |
7394 | ||
7395 | if (tx_rate != 0) { | |
7396 | /* Calculate the rate factor values to set */ | |
7397 | rf_int = link_speed / tx_rate; | |
7398 | rf_dec = (link_speed - (rf_int * tx_rate)); | |
7399 | rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; | |
7400 | ||
7401 | bcnrc_val = E1000_RTTBCNRC_RS_ENA; | |
7402 | bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & | |
7403 | E1000_RTTBCNRC_RF_INT_MASK); | |
7404 | bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); | |
7405 | } else { | |
7406 | bcnrc_val = 0; | |
7407 | } | |
7408 | ||
7409 | wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ | |
f00b0da7 LL |
7410 | /* |
7411 | * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM | |
7412 | * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. | |
7413 | */ | |
7414 | wr32(E1000_RTTBCNRM, 0x14); | |
17dc566c LL |
7415 | wr32(E1000_RTTBCNRC, bcnrc_val); |
7416 | } | |
7417 | ||
7418 | static void igb_check_vf_rate_limit(struct igb_adapter *adapter) | |
7419 | { | |
7420 | int actual_link_speed, i; | |
7421 | bool reset_rate = false; | |
7422 | ||
7423 | /* VF TX rate limit was not set or not supported */ | |
7424 | if ((adapter->vf_rate_link_speed == 0) || | |
7425 | (adapter->hw.mac.type != e1000_82576)) | |
7426 | return; | |
7427 | ||
7428 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7429 | if (actual_link_speed != adapter->vf_rate_link_speed) { | |
7430 | reset_rate = true; | |
7431 | adapter->vf_rate_link_speed = 0; | |
7432 | dev_info(&adapter->pdev->dev, | |
7433 | "Link speed has been changed. VF Transmit " | |
7434 | "rate is disabled\n"); | |
7435 | } | |
7436 | ||
7437 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7438 | if (reset_rate) | |
7439 | adapter->vf_data[i].tx_rate = 0; | |
7440 | ||
7441 | igb_set_vf_rate_limit(&adapter->hw, i, | |
7442 | adapter->vf_data[i].tx_rate, | |
7443 | actual_link_speed); | |
7444 | } | |
7445 | } | |
7446 | ||
8151d294 WM |
7447 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) |
7448 | { | |
17dc566c LL |
7449 | struct igb_adapter *adapter = netdev_priv(netdev); |
7450 | struct e1000_hw *hw = &adapter->hw; | |
7451 | int actual_link_speed; | |
7452 | ||
7453 | if (hw->mac.type != e1000_82576) | |
7454 | return -EOPNOTSUPP; | |
7455 | ||
7456 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7457 | if ((vf >= adapter->vfs_allocated_count) || | |
7458 | (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || | |
7459 | (tx_rate < 0) || (tx_rate > actual_link_speed)) | |
7460 | return -EINVAL; | |
7461 | ||
7462 | adapter->vf_rate_link_speed = actual_link_speed; | |
7463 | adapter->vf_data[vf].tx_rate = (u16)tx_rate; | |
7464 | igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); | |
7465 | ||
7466 | return 0; | |
8151d294 WM |
7467 | } |
7468 | ||
7469 | static int igb_ndo_get_vf_config(struct net_device *netdev, | |
7470 | int vf, struct ifla_vf_info *ivi) | |
7471 | { | |
7472 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7473 | if (vf >= adapter->vfs_allocated_count) | |
7474 | return -EINVAL; | |
7475 | ivi->vf = vf; | |
7476 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | |
17dc566c | 7477 | ivi->tx_rate = adapter->vf_data[vf].tx_rate; |
8151d294 WM |
7478 | ivi->vlan = adapter->vf_data[vf].pf_vlan; |
7479 | ivi->qos = adapter->vf_data[vf].pf_qos; | |
7480 | return 0; | |
7481 | } | |
7482 | ||
4ae196df AD |
7483 | static void igb_vmm_control(struct igb_adapter *adapter) |
7484 | { | |
7485 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 7486 | u32 reg; |
4ae196df | 7487 | |
52a1dd4d AD |
7488 | switch (hw->mac.type) { |
7489 | case e1000_82575: | |
f96a8a0b CW |
7490 | case e1000_i210: |
7491 | case e1000_i211: | |
52a1dd4d AD |
7492 | default: |
7493 | /* replication is not supported for 82575 */ | |
4ae196df | 7494 | return; |
52a1dd4d AD |
7495 | case e1000_82576: |
7496 | /* notify HW that the MAC is adding vlan tags */ | |
7497 | reg = rd32(E1000_DTXCTL); | |
7498 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
7499 | wr32(E1000_DTXCTL, reg); | |
7500 | case e1000_82580: | |
7501 | /* enable replication vlan tag stripping */ | |
7502 | reg = rd32(E1000_RPLOLR); | |
7503 | reg |= E1000_RPLOLR_STRVLAN; | |
7504 | wr32(E1000_RPLOLR, reg); | |
d2ba2ed8 AD |
7505 | case e1000_i350: |
7506 | /* none of the above registers are supported by i350 */ | |
52a1dd4d AD |
7507 | break; |
7508 | } | |
10d8e907 | 7509 | |
d4960307 AD |
7510 | if (adapter->vfs_allocated_count) { |
7511 | igb_vmdq_set_loopback_pf(hw, true); | |
7512 | igb_vmdq_set_replication_pf(hw, true); | |
13800469 GR |
7513 | igb_vmdq_set_anti_spoofing_pf(hw, true, |
7514 | adapter->vfs_allocated_count); | |
d4960307 AD |
7515 | } else { |
7516 | igb_vmdq_set_loopback_pf(hw, false); | |
7517 | igb_vmdq_set_replication_pf(hw, false); | |
7518 | } | |
4ae196df AD |
7519 | } |
7520 | ||
b6e0c419 CW |
7521 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) |
7522 | { | |
7523 | struct e1000_hw *hw = &adapter->hw; | |
7524 | u32 dmac_thr; | |
7525 | u16 hwm; | |
7526 | ||
7527 | if (hw->mac.type > e1000_82580) { | |
7528 | if (adapter->flags & IGB_FLAG_DMAC) { | |
7529 | u32 reg; | |
7530 | ||
7531 | /* force threshold to 0. */ | |
7532 | wr32(E1000_DMCTXTH, 0); | |
7533 | ||
7534 | /* | |
e8c626e9 MV |
7535 | * DMA Coalescing high water mark needs to be greater |
7536 | * than the Rx threshold. Set hwm to PBA - max frame | |
7537 | * size in 16B units, capping it at PBA - 6KB. | |
b6e0c419 | 7538 | */ |
e8c626e9 MV |
7539 | hwm = 64 * pba - adapter->max_frame_size / 16; |
7540 | if (hwm < 64 * (pba - 6)) | |
7541 | hwm = 64 * (pba - 6); | |
7542 | reg = rd32(E1000_FCRTC); | |
7543 | reg &= ~E1000_FCRTC_RTH_COAL_MASK; | |
7544 | reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) | |
7545 | & E1000_FCRTC_RTH_COAL_MASK); | |
7546 | wr32(E1000_FCRTC, reg); | |
7547 | ||
7548 | /* | |
7549 | * Set the DMA Coalescing Rx threshold to PBA - 2 * max | |
7550 | * frame size, capping it at PBA - 10KB. | |
7551 | */ | |
7552 | dmac_thr = pba - adapter->max_frame_size / 512; | |
7553 | if (dmac_thr < pba - 10) | |
7554 | dmac_thr = pba - 10; | |
b6e0c419 CW |
7555 | reg = rd32(E1000_DMACR); |
7556 | reg &= ~E1000_DMACR_DMACTHR_MASK; | |
b6e0c419 CW |
7557 | reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) |
7558 | & E1000_DMACR_DMACTHR_MASK); | |
7559 | ||
7560 | /* transition to L0x or L1 if available..*/ | |
7561 | reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); | |
7562 | ||
7563 | /* watchdog timer= +-1000 usec in 32usec intervals */ | |
7564 | reg |= (1000 >> 5); | |
0c02dd98 MV |
7565 | |
7566 | /* Disable BMC-to-OS Watchdog Enable */ | |
7567 | reg &= ~E1000_DMACR_DC_BMC2OSW_EN; | |
b6e0c419 CW |
7568 | wr32(E1000_DMACR, reg); |
7569 | ||
7570 | /* | |
7571 | * no lower threshold to disable | |
7572 | * coalescing(smart fifb)-UTRESH=0 | |
7573 | */ | |
7574 | wr32(E1000_DMCRTRH, 0); | |
b6e0c419 CW |
7575 | |
7576 | reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); | |
7577 | ||
7578 | wr32(E1000_DMCTLX, reg); | |
7579 | ||
7580 | /* | |
7581 | * free space in tx packet buffer to wake from | |
7582 | * DMA coal | |
7583 | */ | |
7584 | wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - | |
7585 | (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); | |
7586 | ||
7587 | /* | |
7588 | * make low power state decision controlled | |
7589 | * by DMA coal | |
7590 | */ | |
7591 | reg = rd32(E1000_PCIEMISC); | |
7592 | reg &= ~E1000_PCIEMISC_LX_DECISION; | |
7593 | wr32(E1000_PCIEMISC, reg); | |
7594 | } /* endif adapter->dmac is not disabled */ | |
7595 | } else if (hw->mac.type == e1000_82580) { | |
7596 | u32 reg = rd32(E1000_PCIEMISC); | |
7597 | wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); | |
7598 | wr32(E1000_DMACR, 0); | |
7599 | } | |
7600 | } | |
7601 | ||
441fc6fd CW |
7602 | static DEFINE_SPINLOCK(i2c_clients_lock); |
7603 | ||
7604 | /* igb_get_i2c_client - returns matching client | |
7605 | * in adapters's client list. | |
7606 | * @adapter: adapter struct | |
7607 | * @dev_addr: device address of i2c needed. | |
7608 | */ | |
7609 | struct i2c_client * | |
7610 | igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr) | |
7611 | { | |
7612 | ulong flags; | |
7613 | struct igb_i2c_client_list *client_list; | |
7614 | struct i2c_client *client = NULL; | |
7615 | struct i2c_board_info client_info = { | |
7616 | I2C_BOARD_INFO("igb", 0x00), | |
7617 | }; | |
7618 | ||
7619 | spin_lock_irqsave(&i2c_clients_lock, flags); | |
7620 | client_list = adapter->i2c_clients; | |
7621 | ||
7622 | /* See if we already have an i2c_client */ | |
7623 | while (client_list) { | |
7624 | if (client_list->client->addr == (dev_addr >> 1)) { | |
7625 | client = client_list->client; | |
7626 | goto exit; | |
7627 | } else { | |
7628 | client_list = client_list->next; | |
7629 | } | |
7630 | } | |
7631 | ||
e428893b CW |
7632 | /* no client_list found, create a new one as long as |
7633 | * irqs are not disabled | |
7634 | */ | |
7635 | if (unlikely(irqs_disabled())) | |
7636 | goto exit; | |
7637 | ||
441fc6fd CW |
7638 | client_list = kzalloc(sizeof(*client_list), GFP_KERNEL); |
7639 | if (client_list == NULL) | |
7640 | goto exit; | |
7641 | ||
7642 | /* dev_addr passed to us is left-shifted by 1 bit | |
7643 | * i2c_new_device call expects it to be flush to the right. | |
7644 | */ | |
7645 | client_info.addr = dev_addr >> 1; | |
7646 | client_info.platform_data = adapter; | |
7647 | client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info); | |
7648 | if (client_list->client == NULL) { | |
e428893b CW |
7649 | dev_info(&adapter->pdev->dev, |
7650 | "Failed to create new i2c device..\n"); | |
441fc6fd CW |
7651 | goto err_no_client; |
7652 | } | |
7653 | ||
7654 | /* insert new client at head of list */ | |
7655 | client_list->next = adapter->i2c_clients; | |
7656 | adapter->i2c_clients = client_list; | |
7657 | ||
441fc6fd CW |
7658 | client = client_list->client; |
7659 | goto exit; | |
7660 | ||
7661 | err_no_client: | |
7662 | kfree(client_list); | |
7663 | exit: | |
7664 | spin_unlock_irqrestore(&i2c_clients_lock, flags); | |
7665 | return client; | |
7666 | } | |
7667 | ||
7668 | /* igb_read_i2c_byte - Reads 8 bit word over I2C | |
7669 | * @hw: pointer to hardware structure | |
7670 | * @byte_offset: byte offset to read | |
7671 | * @dev_addr: device address | |
7672 | * @data: value read | |
7673 | * | |
7674 | * Performs byte read operation over I2C interface at | |
7675 | * a specified device address. | |
7676 | */ | |
7677 | s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, | |
7678 | u8 dev_addr, u8 *data) | |
7679 | { | |
7680 | struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); | |
7681 | struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr); | |
7682 | s32 status; | |
7683 | u16 swfw_mask = 0; | |
7684 | ||
7685 | if (!this_client) | |
7686 | return E1000_ERR_I2C; | |
7687 | ||
7688 | swfw_mask = E1000_SWFW_PHY0_SM; | |
7689 | ||
7690 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) | |
7691 | != E1000_SUCCESS) | |
7692 | return E1000_ERR_SWFW_SYNC; | |
7693 | ||
7694 | status = i2c_smbus_read_byte_data(this_client, byte_offset); | |
7695 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |
7696 | ||
7697 | if (status < 0) | |
7698 | return E1000_ERR_I2C; | |
7699 | else { | |
7700 | *data = status; | |
7701 | return E1000_SUCCESS; | |
7702 | } | |
7703 | } | |
7704 | ||
7705 | /* igb_write_i2c_byte - Writes 8 bit word over I2C | |
7706 | * @hw: pointer to hardware structure | |
7707 | * @byte_offset: byte offset to write | |
7708 | * @dev_addr: device address | |
7709 | * @data: value to write | |
7710 | * | |
7711 | * Performs byte write operation over I2C interface at | |
7712 | * a specified device address. | |
7713 | */ | |
7714 | s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, | |
7715 | u8 dev_addr, u8 data) | |
7716 | { | |
7717 | struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); | |
7718 | struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr); | |
7719 | s32 status; | |
7720 | u16 swfw_mask = E1000_SWFW_PHY0_SM; | |
7721 | ||
7722 | if (!this_client) | |
7723 | return E1000_ERR_I2C; | |
7724 | ||
7725 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) | |
7726 | return E1000_ERR_SWFW_SYNC; | |
7727 | status = i2c_smbus_write_byte_data(this_client, byte_offset, data); | |
7728 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |
7729 | ||
7730 | if (status) | |
7731 | return E1000_ERR_I2C; | |
7732 | else | |
7733 | return E1000_SUCCESS; | |
7734 | ||
7735 | } | |
9d5c8243 | 7736 | /* igb_main.c */ |