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net: Don't write to current task flags on every packet received.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
200e5fd5 63#define MAJ 4
6699938b
CW		 64#define MIN 1
65#define BUILD 2
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
110 /* required last entry */
111 {0, }
112};
113
114MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
115
116void igb_reset(struct igb_adapter *);
117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c8f44aff 158static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 159static int igb_vlan_rx_add_vid(struct net_device *, u16);
160static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 161static void igb_restore_vlan(struct igb_adapter *);
26ad9178 162static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 163static void igb_ping_all_vfs(struct igb_adapter *);
164static void igb_msg_task(struct igb_adapter *);
4ae196df 165static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 166static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 167static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 168static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
169static int igb_ndo_set_vf_vlan(struct net_device *netdev,
170 int vf, u16 vlan, u8 qos);
171static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
172static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
173 struct ifla_vf_info *ivi);
17dc566c 174static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 175
176#ifdef CONFIG_PCI_IOV
0224d663 177static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 178static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 179#endif
9d5c8243 180
9d5c8243 181#ifdef CONFIG_PM
d9dd966d 182#ifdef CONFIG_PM_SLEEP
749ab2cd 183static int igb_suspend(struct device *);
d9dd966d 184#endif
749ab2cd
YZ		 185static int igb_resume(struct device *);
186#ifdef CONFIG_PM_RUNTIME
187static int igb_runtime_suspend(struct device *dev);
188static int igb_runtime_resume(struct device *dev);
189static int igb_runtime_idle(struct device *dev);
190#endif
191static const struct dev_pm_ops igb_pm_ops = {
192 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
193 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
194 igb_runtime_idle)
195};
9d5c8243
AK		 196#endif
197static void igb_shutdown(struct pci_dev *);
fa44f2f1 198static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 199#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 200static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
201static struct notifier_block dca_notifier = {
202 .notifier_call = igb_notify_dca,
203 .next = NULL,
204 .priority = 0
205};
206#endif
9d5c8243
AK		 207#ifdef CONFIG_NET_POLL_CONTROLLER
208/* for netdump / net console */
209static void igb_netpoll(struct net_device *);
210#endif
37680117 211#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 212static unsigned int max_vfs = 0;
213module_param(max_vfs, uint, 0);
214MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
215 "per physical function");
216#endif /* CONFIG_PCI_IOV */
217
9d5c8243
AK		 218static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221static void igb_io_resume(struct pci_dev *);
222
3646f0e5 223static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227};
228
b6e0c419 229static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 230
231static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
9f9a12f8 235 .remove = igb_remove,
9d5c8243 236#ifdef CONFIG_PM
749ab2cd 237 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 238#endif
239 .shutdown = igb_shutdown,
fa44f2f1 240 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 241 .err_handler = &igb_err_handler
242};
243
244MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246MODULE_LICENSE("GPL");
247MODULE_VERSION(DRV_VERSION);
248
b3f4d599 249#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250static int debug = -1;
251module_param(debug, int, 0);
252MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
c97ec42a
TI		 254struct igb_reg_info {
255 u32 ofs;
256 char *name;
257};
258
259static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293};
294
295/*
296 * igb_regdump - register printout routine
297 */
298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
363/*
364 * igb_dump - Print registers, tx-rings and rx-rings
365 */
366static void igb_dump(struct igb_adapter *adapter)
367{
368 struct net_device *netdev = adapter->netdev;
369 struct e1000_hw *hw = &adapter->hw;
370 struct igb_reg_info *reginfo;
c97ec42a
TI		 371 struct igb_ring *tx_ring;
372 union e1000_adv_tx_desc *tx_desc;
373 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 374 struct igb_ring *rx_ring;
375 union e1000_adv_rx_desc *rx_desc;
376 u32 staterr;
6ad4edfc 377 u16 i, n;
c97ec42a
TI		 378
379 if (!netif_msg_hw(adapter))
380 return;
381
382 /* Print netdevice Info */
383 if (netdev) {
384 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 385 pr_info("Device Name state trans_start "
386 "last_rx\n");
387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 389 }
390
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 393 pr_info(" Register Name Value\n");
c97ec42a
TI		 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
397 }
398
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
401 goto exit;
402
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 405 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 406 struct igb_tx_buffer *buffer_info;
c97ec42a 407 tx_ring = adapter->tx_ring[n];
06034649 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
c97ec42a
TI		 415 }
416
417 /* Print TX Rings */
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
420
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
422
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
433
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
440 "[bi->dma ] leng ntw timestamp "
441 "bi->skb\n");
c97ec42a
TI		 442
443 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 444 const char *next_desc;
06034649 445 struct igb_tx_buffer *buffer_info;
60136906 446 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 447 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 448 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 449 if (i == tx_ring->next_to_use &&
450 i == tx_ring->next_to_clean)
451 next_desc = " NTC/U";
452 else if (i == tx_ring->next_to_use)
453 next_desc = " NTU";
454 else if (i == tx_ring->next_to_clean)
455 next_desc = " NTC";
456 else
457 next_desc = "";
458
459 pr_info("T [0x%03X] %016llX %016llX %016llX"
460 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 461 le64_to_cpu(u0->a),
462 le64_to_cpu(u0->b),
c9f14bf3
AD		 463 (u64)dma_unmap_addr(buffer_info, dma),
464 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 465 buffer_info->next_to_watch,
466 (u64)buffer_info->time_stamp,
876d2d6f 467 buffer_info->skb, next_desc);
c97ec42a 468
b669588a 469 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 470 print_hex_dump(KERN_INFO, "",
471 DUMP_PREFIX_ADDRESS,
b669588a 472 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 473 dma_unmap_len(buffer_info, len),
474 true);
c97ec42a
TI		 475 }
476 }
477
478 /* Print RX Rings Summary */
479rx_ring_summary:
480 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 481 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 482 for (n = 0; n < adapter->num_rx_queues; n++) {
483 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 484 pr_info(" %5d %5X %5X\n",
485 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 486 }
487
488 /* Print RX Rings */
489 if (!netif_msg_rx_status(adapter))
490 goto exit;
491
492 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
493
494 /* Advanced Receive Descriptor (Read) Format
495 * 63 1 0
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
501 *
502 *
503 * Advanced Receive Descriptor (Write-Back) Format
504 *
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
513 */
514
515 for (n = 0; n < adapter->num_rx_queues; n++) {
516 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 517 pr_info("------------------------------------\n");
518 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
521 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
522 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
523 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 524
525 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 526 const char *next_desc;
06034649
AD		 527 struct igb_rx_buffer *buffer_info;
528 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 529 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 530 u0 = (struct my_u0 *)rx_desc;
531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 532
533 if (i == rx_ring->next_to_use)
534 next_desc = " NTU";
535 else if (i == rx_ring->next_to_clean)
536 next_desc = " NTC";
537 else
538 next_desc = "";
539
c97ec42a
TI		 540 if (staterr & E1000_RXD_STAT_DD) {
541 /* Descriptor Done */
1a1c225b
AD		 542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
543 "RWB", i,
c97ec42a
TI		 544 le64_to_cpu(u0->a),
545 le64_to_cpu(u0->b),
1a1c225b 546 next_desc);
c97ec42a 547 } else {
1a1c225b
AD		 548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
549 "R ", i,
c97ec42a
TI		 550 le64_to_cpu(u0->a),
551 le64_to_cpu(u0->b),
552 (u64)buffer_info->dma,
1a1c225b 553 next_desc);
c97ec42a 554
b669588a 555 if (netif_msg_pktdata(adapter) &&
1a1c225b 556 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 557 print_hex_dump(KERN_INFO, "",
558 DUMP_PREFIX_ADDRESS,
559 16, 1,
b669588a
ET		 560 page_address(buffer_info->page) +
561 buffer_info->page_offset,
de78d1f9 562 IGB_RX_BUFSZ, true);
c97ec42a
TI		 563 }
564 }
c97ec42a
TI		 565 }
566 }
567
568exit:
569 return;
570}
571
441fc6fd
CW		 572/* igb_get_i2c_data - Reads the I2C SDA data bit
573 * @hw: pointer to hardware structure
574 * @i2cctl: Current value of I2CCTL register
575 *
576 * Returns the I2C data bit value
577 */
578static int igb_get_i2c_data(void *data)
579{
580 struct igb_adapter *adapter = (struct igb_adapter *)data;
581 struct e1000_hw *hw = &adapter->hw;
582 s32 i2cctl = rd32(E1000_I2CPARAMS);
583
584 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
585}
586
587/* igb_set_i2c_data - Sets the I2C data bit
588 * @data: pointer to hardware structure
589 * @state: I2C data value (0 or 1) to set
590 *
591 * Sets the I2C data bit
592 */
593static void igb_set_i2c_data(void *data, int state)
594{
595 struct igb_adapter *adapter = (struct igb_adapter *)data;
596 struct e1000_hw *hw = &adapter->hw;
597 s32 i2cctl = rd32(E1000_I2CPARAMS);
598
599 if (state)
600 i2cctl |= E1000_I2C_DATA_OUT;
601 else
602 i2cctl &= ~E1000_I2C_DATA_OUT;
603
604 i2cctl &= ~E1000_I2C_DATA_OE_N;
605 i2cctl |= E1000_I2C_CLK_OE_N;
606 wr32(E1000_I2CPARAMS, i2cctl);
607 wrfl();
608
609}
610
611/* igb_set_i2c_clk - Sets the I2C SCL clock
612 * @data: pointer to hardware structure
613 * @state: state to set clock
614 *
615 * Sets the I2C clock line to state
616 */
617static void igb_set_i2c_clk(void *data, int state)
618{
619 struct igb_adapter *adapter = (struct igb_adapter *)data;
620 struct e1000_hw *hw = &adapter->hw;
621 s32 i2cctl = rd32(E1000_I2CPARAMS);
622
623 if (state) {
624 i2cctl |= E1000_I2C_CLK_OUT;
625 i2cctl &= ~E1000_I2C_CLK_OE_N;
626 } else {
627 i2cctl &= ~E1000_I2C_CLK_OUT;
628 i2cctl &= ~E1000_I2C_CLK_OE_N;
629 }
630 wr32(E1000_I2CPARAMS, i2cctl);
631 wrfl();
632}
633
634/* igb_get_i2c_clk - Gets the I2C SCL clock state
635 * @data: pointer to hardware structure
636 *
637 * Gets the I2C clock state
638 */
639static int igb_get_i2c_clk(void *data)
640{
641 struct igb_adapter *adapter = (struct igb_adapter *)data;
642 struct e1000_hw *hw = &adapter->hw;
643 s32 i2cctl = rd32(E1000_I2CPARAMS);
644
645 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
646}
647
648static const struct i2c_algo_bit_data igb_i2c_algo = {
649 .setsda = igb_set_i2c_data,
650 .setscl = igb_set_i2c_clk,
651 .getsda = igb_get_i2c_data,
652 .getscl = igb_get_i2c_clk,
653 .udelay = 5,
654 .timeout = 20,
655};
656
9d5c8243 657/**
c041076a 658 * igb_get_hw_dev - return device
9d5c8243
AK		 659 * used by hardware layer to print debugging information
660 **/
c041076a 661struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 662{
663 struct igb_adapter *adapter = hw->back;
c041076a 664 return adapter->netdev;
9d5c8243 665}
38c845c7 666
9d5c8243
AK		 667/**
668 * igb_init_module - Driver Registration Routine
669 *
670 * igb_init_module is the first routine called when the driver is
671 * loaded. All it does is register with the PCI subsystem.
672 **/
673static int __init igb_init_module(void)
674{
675 int ret;
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243
AK		 677 igb_driver_string, igb_driver_version);
678
876d2d6f 679 pr_info("%s\n", igb_copyright);
9d5c8243 680
421e02f0 681#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 682 dca_register_notify(&dca_notifier);
683#endif
bbd98fe4 684 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 685 return ret;
686}
687
688module_init(igb_init_module);
689
690/**
691 * igb_exit_module - Driver Exit Cleanup Routine
692 *
693 * igb_exit_module is called just before the driver is removed
694 * from memory.
695 **/
696static void __exit igb_exit_module(void)
697{
421e02f0 698#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 699 dca_unregister_notify(&dca_notifier);
700#endif
9d5c8243
AK		 701 pci_unregister_driver(&igb_driver);
702}
703
704module_exit(igb_exit_module);
705
26bc19ec
AD		 706#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
707/**
708 * igb_cache_ring_register - Descriptor ring to register mapping
709 * @adapter: board private structure to initialize
710 *
711 * Once we know the feature-set enabled for the device, we'll cache
712 * the register offset the descriptor ring is assigned to.
713 **/
714static void igb_cache_ring_register(struct igb_adapter *adapter)
715{
ee1b9f06 716 int i = 0, j = 0;
047e0030 717 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 718
719 switch (adapter->hw.mac.type) {
720 case e1000_82576:
721 /* The queues are allocated for virtualization such that VF 0
722 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
723 * In order to avoid collision we start at the first free queue
724 * and continue consuming queues in the same sequence
725 */
ee1b9f06 726 if (adapter->vfs_allocated_count) {
a99955fc 727 for (; i < adapter->rss_queues; i++)
3025a446
AD		 728 adapter->rx_ring[i]->reg_idx = rbase_offset +
729 Q_IDX_82576(i);
ee1b9f06 730 }
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
26bc19ec 736 default:
ee1b9f06 737 for (; i < adapter->num_rx_queues; i++)
3025a446 738 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 739 for (; j < adapter->num_tx_queues; j++)
3025a446 740 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 741 break;
742 }
743}
744
4be000c8
AD		 745/**
746 * igb_write_ivar - configure ivar for given MSI-X vector
747 * @hw: pointer to the HW structure
748 * @msix_vector: vector number we are allocating to a given ring
749 * @index: row index of IVAR register to write within IVAR table
750 * @offset: column offset of in IVAR, should be multiple of 8
751 *
752 * This function is intended to handle the writing of the IVAR register
753 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
754 * each containing an cause allocation for an Rx and Tx ring, and a
755 * variable number of rows depending on the number of queues supported.
756 **/
757static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
758 int index, int offset)
759{
760 u32 ivar = array_rd32(E1000_IVAR0, index);
761
762 /* clear any bits that are currently set */
763 ivar &= ~((u32)0xFF << offset);
764
765 /* write vector and valid bit */
766 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
767
768 array_wr32(E1000_IVAR0, index, ivar);
769}
770
9d5c8243 771#define IGB_N0_QUEUE -1
047e0030 772static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 773{
047e0030 774 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 775 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 776 int rx_queue = IGB_N0_QUEUE;
777 int tx_queue = IGB_N0_QUEUE;
4be000c8 778 u32 msixbm = 0;
047e0030 779
0ba82994
AD		 780 if (q_vector->rx.ring)
781 rx_queue = q_vector->rx.ring->reg_idx;
782 if (q_vector->tx.ring)
783 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 784
785 switch (hw->mac.type) {
786 case e1000_82575:
9d5c8243
AK		 787 /* The 82575 assigns vectors using a bitmask, which matches the
788 bitmask for the EICR/EIMS/EIMC registers. To assign one
789 or more queues to a vector, we write the appropriate bits
790 into the MSIXBM register for that vector. */
047e0030 791 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 792 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 793 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 794 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 795 if (!adapter->msix_entries && msix_vector == 0)
796 msixbm |= E1000_EIMS_OTHER;
9d5c8243 797 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 798 q_vector->eims_value = msixbm;
2d064c06
AD		 799 break;
800 case e1000_82576:
4be000c8
AD		 801 /*
802 * 82576 uses a table that essentially consists of 2 columns
803 * with 8 rows. The ordering is column-major so we use the
804 * lower 3 bits as the row index, and the 4th bit as the
805 * column offset.
806 */
807 if (rx_queue > IGB_N0_QUEUE)
808 igb_write_ivar(hw, msix_vector,
809 rx_queue & 0x7,
810 (rx_queue & 0x8) << 1);
811 if (tx_queue > IGB_N0_QUEUE)
812 igb_write_ivar(hw, msix_vector,
813 tx_queue & 0x7,
814 ((tx_queue & 0x8) << 1) + 8);
047e0030 815 q_vector->eims_value = 1 << msix_vector;
2d064c06 816 break;
55cac248 817 case e1000_82580:
d2ba2ed8 818 case e1000_i350:
f96a8a0b
CW		 819 case e1000_i210:
820 case e1000_i211:
4be000c8
AD		 821 /*
822 * On 82580 and newer adapters the scheme is similar to 82576
823 * however instead of ordering column-major we have things
824 * ordered row-major. So we traverse the table by using
825 * bit 0 as the column offset, and the remaining bits as the
826 * row index.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue >> 1,
831 (rx_queue & 0x1) << 4);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue >> 1,
835 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 836 q_vector->eims_value = 1 << msix_vector;
837 break;
2d064c06
AD		 838 default:
839 BUG();
840 break;
841 }
26b39276
AD		 842
843 /* add q_vector eims value to global eims_enable_mask */
844 adapter->eims_enable_mask |= q_vector->eims_value;
845
846 /* configure q_vector to set itr on first interrupt */
847 q_vector->set_itr = 1;
9d5c8243
AK		 848}
849
850/**
851 * igb_configure_msix - Configure MSI-X hardware
852 *
853 * igb_configure_msix sets up the hardware to properly
854 * generate MSI-X interrupts.
855 **/
856static void igb_configure_msix(struct igb_adapter *adapter)
857{
858 u32 tmp;
859 int i, vector = 0;
860 struct e1000_hw *hw = &adapter->hw;
861
862 adapter->eims_enable_mask = 0;
9d5c8243
AK		 863
864 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 865 switch (hw->mac.type) {
866 case e1000_82575:
9d5c8243
AK		 867 tmp = rd32(E1000_CTRL_EXT);
868 /* enable MSI-X PBA support*/
869 tmp |= E1000_CTRL_EXT_PBA_CLR;
870
871 /* Auto-Mask interrupts upon ICR read. */
872 tmp |= E1000_CTRL_EXT_EIAME;
873 tmp |= E1000_CTRL_EXT_IRCA;
874
875 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 876
877 /* enable msix_other interrupt */
878 array_wr32(E1000_MSIXBM(0), vector++,
879 E1000_EIMS_OTHER);
844290e5 880 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 881
2d064c06
AD		 882 break;
883
884 case e1000_82576:
55cac248 885 case e1000_82580:
d2ba2ed8 886 case e1000_i350:
f96a8a0b
CW		 887 case e1000_i210:
888 case e1000_i211:
047e0030
AD		 889 /* Turn on MSI-X capability first, or our settings
890 * won't stick. And it will take days to debug. */
891 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
892 E1000_GPIE_PBA | E1000_GPIE_EIAME |
893 E1000_GPIE_NSICR);
894
895 /* enable msix_other interrupt */
896 adapter->eims_other = 1 << vector;
2d064c06 897 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 898
047e0030 899 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 900 break;
901 default:
902 /* do nothing, since nothing else supports MSI-X */
903 break;
904 } /* switch (hw->mac.type) */
047e0030
AD		 905
906 adapter->eims_enable_mask |= adapter->eims_other;
907
26b39276
AD		 908 for (i = 0; i < adapter->num_q_vectors; i++)
909 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 910
9d5c8243
AK		 911 wrfl();
912}
913
914/**
915 * igb_request_msix - Initialize MSI-X interrupts
916 *
917 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
918 * kernel.
919 **/
920static int igb_request_msix(struct igb_adapter *adapter)
921{
922 struct net_device *netdev = adapter->netdev;
047e0030 923 struct e1000_hw *hw = &adapter->hw;
52285b76 924 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 925
047e0030 926 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 927 igb_msix_other, 0, netdev->name, adapter);
047e0030 928 if (err)
52285b76 929 goto err_out;
047e0030
AD		 930
931 for (i = 0; i < adapter->num_q_vectors; i++) {
932 struct igb_q_vector *q_vector = adapter->q_vector[i];
933
52285b76
SA		 934 vector++;
935
047e0030
AD		 936 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
937
0ba82994 938 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 939 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 940 q_vector->rx.ring->queue_index);
941 else if (q_vector->tx.ring)
047e0030 942 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 943 q_vector->tx.ring->queue_index);
944 else if (q_vector->rx.ring)
047e0030 945 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 946 q_vector->rx.ring->queue_index);
9d5c8243 947 else
047e0030
AD		 948 sprintf(q_vector->name, "%s-unused", netdev->name);
949
9d5c8243 950 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 951 igb_msix_ring, 0, q_vector->name,
047e0030 952 q_vector);
9d5c8243 953 if (err)
52285b76 954 goto err_free;
9d5c8243
AK		 955 }
956
9d5c8243
AK		 957 igb_configure_msix(adapter);
958 return 0;
52285b76
SA		 959
960err_free:
961 /* free already assigned IRQs */
962 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
963
964 vector--;
965 for (i = 0; i < vector; i++) {
966 free_irq(adapter->msix_entries[free_vector++].vector,
967 adapter->q_vector[i]);
968 }
969err_out:
9d5c8243
AK		 970 return err;
971}
972
973static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
974{
975 if (adapter->msix_entries) {
976 pci_disable_msix(adapter->pdev);
977 kfree(adapter->msix_entries);
978 adapter->msix_entries = NULL;
047e0030 979 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 980 pci_disable_msi(adapter->pdev);
047e0030 981 }
9d5c8243
AK		 982}
983
5536d210
AD		 984/**
985 * igb_free_q_vector - Free memory allocated for specific interrupt vector
986 * @adapter: board private structure to initialize
987 * @v_idx: Index of vector to be freed
988 *
989 * This function frees the memory allocated to the q_vector. In addition if
990 * NAPI is enabled it will delete any references to the NAPI struct prior
991 * to freeing the q_vector.
992 **/
993static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
994{
995 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
996
997 if (q_vector->tx.ring)
998 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
999
1000 if (q_vector->rx.ring)
1001 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1002
1003 adapter->q_vector[v_idx] = NULL;
1004 netif_napi_del(&q_vector->napi);
1005
1006 /*
1007 * ixgbe_get_stats64() might access the rings on this vector,
1008 * we must wait a grace period before freeing it.
1009 */
1010 kfree_rcu(q_vector, rcu);
1011}
1012
047e0030
AD		 1013/**
1014 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1015 * @adapter: board private structure to initialize
1016 *
1017 * This function frees the memory allocated to the q_vectors. In addition if
1018 * NAPI is enabled it will delete any references to the NAPI struct prior
1019 * to freeing the q_vector.
1020 **/
1021static void igb_free_q_vectors(struct igb_adapter *adapter)
1022{
5536d210
AD		 1023 int v_idx = adapter->num_q_vectors;
1024
1025 adapter->num_tx_queues = 0;
1026 adapter->num_rx_queues = 0;
047e0030 1027 adapter->num_q_vectors = 0;
5536d210
AD		 1028
1029 while (v_idx--)
1030 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1031}
1032
1033/**
1034 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1035 *
1036 * This function resets the device so that it has 0 rx queues, tx queues, and
1037 * MSI-X interrupts allocated.
1038 */
1039static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1040{
047e0030
AD		 1041 igb_free_q_vectors(adapter);
1042 igb_reset_interrupt_capability(adapter);
1043}
9d5c8243
AK		 1044
1045/**
1046 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1047 *
1048 * Attempt to configure interrupts using the best available
1049 * capabilities of the hardware and kernel.
1050 **/
53c7d064 1051static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1052{
1053 int err;
1054 int numvecs, i;
1055
53c7d064
SA		 1056 if (!msix)
1057 goto msi_only;
1058
83b7180d 1059 /* Number of supported queues. */
a99955fc 1060 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1061 if (adapter->vfs_allocated_count)
1062 adapter->num_tx_queues = 1;
1063 else
1064 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1065
047e0030
AD		 1066 /* start with one vector for every rx queue */
1067 numvecs = adapter->num_rx_queues;
1068
3ad2f3fb 1069 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1070 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1071 numvecs += adapter->num_tx_queues;
047e0030
AD		 1072
1073 /* store the number of vectors reserved for queues */
1074 adapter->num_q_vectors = numvecs;
1075
1076 /* add 1 vector for link status interrupts */
1077 numvecs++;
9d5c8243
AK		 1078 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1079 GFP_KERNEL);
f96a8a0b 1080
9d5c8243
AK		 1081 if (!adapter->msix_entries)
1082 goto msi_only;
1083
1084 for (i = 0; i < numvecs; i++)
1085 adapter->msix_entries[i].entry = i;
1086
1087 err = pci_enable_msix(adapter->pdev,
1088 adapter->msix_entries,
1089 numvecs);
1090 if (err == 0)
0c2cc02e 1091 return;
9d5c8243
AK		 1092
1093 igb_reset_interrupt_capability(adapter);
1094
1095 /* If we can't do MSI-X, try MSI */
1096msi_only:
2a3abf6d
AD		 1097#ifdef CONFIG_PCI_IOV
1098 /* disable SR-IOV for non MSI-X configurations */
1099 if (adapter->vf_data) {
1100 struct e1000_hw *hw = &adapter->hw;
1101 /* disable iov and allow time for transactions to clear */
1102 pci_disable_sriov(adapter->pdev);
1103 msleep(500);
1104
1105 kfree(adapter->vf_data);
1106 adapter->vf_data = NULL;
1107 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1108 wrfl();
2a3abf6d
AD		 1109 msleep(100);
1110 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1111 }
1112#endif
4fc82adf 1113 adapter->vfs_allocated_count = 0;
a99955fc 1114 adapter->rss_queues = 1;
4fc82adf 1115 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1116 adapter->num_rx_queues = 1;
661086df 1117 adapter->num_tx_queues = 1;
047e0030 1118 adapter->num_q_vectors = 1;
9d5c8243 1119 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1120 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1121}
1122
5536d210
AD		 1123static void igb_add_ring(struct igb_ring *ring,
1124 struct igb_ring_container *head)
1125{
1126 head->ring = ring;
1127 head->count++;
1128}
1129
047e0030 1130/**
5536d210 1131 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1132 * @adapter: board private structure to initialize
5536d210
AD		 1133 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1134 * @v_idx: index of vector in adapter struct
1135 * @txr_count: total number of Tx rings to allocate
1136 * @txr_idx: index of first Tx ring to allocate
1137 * @rxr_count: total number of Rx rings to allocate
1138 * @rxr_idx: index of first Rx ring to allocate
047e0030 1139 *
5536d210 1140 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1141 **/
5536d210
AD		 1142static int igb_alloc_q_vector(struct igb_adapter *adapter,
1143 int v_count, int v_idx,
1144 int txr_count, int txr_idx,
1145 int rxr_count, int rxr_idx)
047e0030
AD		 1146{
1147 struct igb_q_vector *q_vector;
5536d210
AD		 1148 struct igb_ring *ring;
1149 int ring_count, size;
047e0030 1150
5536d210
AD		 1151 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1152 if (txr_count > 1 || rxr_count > 1)
1153 return -ENOMEM;
1154
1155 ring_count = txr_count + rxr_count;
1156 size = sizeof(struct igb_q_vector) +
1157 (sizeof(struct igb_ring) * ring_count);
1158
1159 /* allocate q_vector and rings */
1160 q_vector = kzalloc(size, GFP_KERNEL);
1161 if (!q_vector)
1162 return -ENOMEM;
1163
1164 /* initialize NAPI */
1165 netif_napi_add(adapter->netdev, &q_vector->napi,
1166 igb_poll, 64);
1167
1168 /* tie q_vector and adapter together */
1169 adapter->q_vector[v_idx] = q_vector;
1170 q_vector->adapter = adapter;
1171
1172 /* initialize work limits */
1173 q_vector->tx.work_limit = adapter->tx_work_limit;
1174
1175 /* initialize ITR configuration */
1176 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1177 q_vector->itr_val = IGB_START_ITR;
1178
1179 /* initialize pointer to rings */
1180 ring = q_vector->ring;
1181
1182 if (txr_count) {
1183 /* assign generic ring traits */
1184 ring->dev = &adapter->pdev->dev;
1185 ring->netdev = adapter->netdev;
1186
1187 /* configure backlink on ring */
1188 ring->q_vector = q_vector;
1189
1190 /* update q_vector Tx values */
1191 igb_add_ring(ring, &q_vector->tx);
1192
1193 /* For 82575, context index must be unique per ring. */
1194 if (adapter->hw.mac.type == e1000_82575)
1195 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1196
1197 /* apply Tx specific ring traits */
1198 ring->count = adapter->tx_ring_count;
1199 ring->queue_index = txr_idx;
1200
1201 /* assign ring to adapter */
1202 adapter->tx_ring[txr_idx] = ring;
1203
1204 /* push pointer to next ring */
1205 ring++;
047e0030 1206 }
81c2fc22 1207
5536d210
AD		 1208 if (rxr_count) {
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
047e0030 1212
5536d210
AD		 1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
047e0030 1215
5536d210
AD		 1216 /* update q_vector Rx values */
1217 igb_add_ring(ring, &q_vector->rx);
047e0030 1218
5536d210
AD		 1219 /* set flag indicating ring supports SCTP checksum offload */
1220 if (adapter->hw.mac.type >= e1000_82576)
1221 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1222
5536d210
AD		 1223 /*
1224 * On i350, i210, and i211, loopback VLAN packets
1225 * have the tag byte-swapped.
1226 * */
1227 if (adapter->hw.mac.type >= e1000_i350)
1228 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1229
5536d210
AD		 1230 /* apply Rx specific ring traits */
1231 ring->count = adapter->rx_ring_count;
1232 ring->queue_index = rxr_idx;
1233
1234 /* assign ring to adapter */
1235 adapter->rx_ring[rxr_idx] = ring;
1236 }
1237
1238 return 0;
047e0030
AD		 1239}
1240
5536d210 1241
047e0030 1242/**
5536d210
AD		 1243 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1244 * @adapter: board private structure to initialize
047e0030 1245 *
5536d210
AD		 1246 * We allocate one q_vector per queue interrupt. If allocation fails we
1247 * return -ENOMEM.
047e0030 1248 **/
5536d210 1249static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1250{
5536d210
AD		 1251 int q_vectors = adapter->num_q_vectors;
1252 int rxr_remaining = adapter->num_rx_queues;
1253 int txr_remaining = adapter->num_tx_queues;
1254 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1255 int err;
047e0030 1256
5536d210
AD		 1257 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1258 for (; rxr_remaining; v_idx++) {
1259 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1260 0, 0, 1, rxr_idx);
047e0030 1261
5536d210
AD		 1262 if (err)
1263 goto err_out;
1264
1265 /* update counts and index */
1266 rxr_remaining--;
1267 rxr_idx++;
047e0030 1268 }
047e0030 1269 }
5536d210
AD		 1270
1271 for (; v_idx < q_vectors; v_idx++) {
1272 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1273 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1274 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1275 tqpv, txr_idx, rqpv, rxr_idx);
1276
1277 if (err)
1278 goto err_out;
1279
1280 /* update counts and index */
1281 rxr_remaining -= rqpv;
1282 txr_remaining -= tqpv;
1283 rxr_idx++;
1284 txr_idx++;
1285 }
1286
047e0030 1287 return 0;
5536d210
AD		 1288
1289err_out:
1290 adapter->num_tx_queues = 0;
1291 adapter->num_rx_queues = 0;
1292 adapter->num_q_vectors = 0;
1293
1294 while (v_idx--)
1295 igb_free_q_vector(adapter, v_idx);
1296
1297 return -ENOMEM;
047e0030
AD		 1298}
1299
1300/**
1301 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1302 *
1303 * This function initializes the interrupts and allocates all of the queues.
1304 **/
53c7d064 1305static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1306{
1307 struct pci_dev *pdev = adapter->pdev;
1308 int err;
1309
53c7d064 1310 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1311
1312 err = igb_alloc_q_vectors(adapter);
1313 if (err) {
1314 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1315 goto err_alloc_q_vectors;
1316 }
1317
5536d210 1318 igb_cache_ring_register(adapter);
047e0030
AD		 1319
1320 return 0;
5536d210 1321
047e0030
AD		 1322err_alloc_q_vectors:
1323 igb_reset_interrupt_capability(adapter);
1324 return err;
1325}
1326
9d5c8243
AK		 1327/**
1328 * igb_request_irq - initialize interrupts
1329 *
1330 * Attempts to configure interrupts using the best available
1331 * capabilities of the hardware and kernel.
1332 **/
1333static int igb_request_irq(struct igb_adapter *adapter)
1334{
1335 struct net_device *netdev = adapter->netdev;
047e0030 1336 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1337 int err = 0;
1338
1339 if (adapter->msix_entries) {
1340 err = igb_request_msix(adapter);
844290e5 1341 if (!err)
9d5c8243 1342 goto request_done;
9d5c8243 1343 /* fall back to MSI */
5536d210
AD		 1344 igb_free_all_tx_resources(adapter);
1345 igb_free_all_rx_resources(adapter);
53c7d064 1346
047e0030 1347 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1348 err = igb_init_interrupt_scheme(adapter, false);
1349 if (err)
047e0030 1350 goto request_done;
53c7d064 1351
047e0030
AD		 1352 igb_setup_all_tx_resources(adapter);
1353 igb_setup_all_rx_resources(adapter);
53c7d064 1354 igb_configure(adapter);
9d5c8243 1355 }
844290e5 1356
c74d588e
AD		 1357 igb_assign_vector(adapter->q_vector[0], 0);
1358
7dfc16fa 1359 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1360 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1361 netdev->name, adapter);
9d5c8243
AK		 1362 if (!err)
1363 goto request_done;
047e0030 1364
9d5c8243
AK		 1365 /* fall back to legacy interrupts */
1366 igb_reset_interrupt_capability(adapter);
7dfc16fa 1367 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1368 }
1369
c74d588e 1370 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1371 netdev->name, adapter);
9d5c8243 1372
6cb5e577 1373 if (err)
c74d588e 1374 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1375 err);
9d5c8243
AK		 1376
1377request_done:
1378 return err;
1379}
1380
1381static void igb_free_irq(struct igb_adapter *adapter)
1382{
9d5c8243
AK		 1383 if (adapter->msix_entries) {
1384 int vector = 0, i;
1385
047e0030 1386 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1387
0d1ae7f4 1388 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1389 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1390 adapter->q_vector[i]);
047e0030
AD		 1391 } else {
1392 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1393 }
9d5c8243
AK		 1394}
1395
1396/**
1397 * igb_irq_disable - Mask off interrupt generation on the NIC
1398 * @adapter: board private structure
1399 **/
1400static void igb_irq_disable(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403
25568a53
AD		 1404 /*
1405 * we need to be careful when disabling interrupts. The VFs are also
1406 * mapped into these registers and so clearing the bits can cause
1407 * issues on the VF drivers so we only need to clear what we set
1408 */
9d5c8243 1409 if (adapter->msix_entries) {
2dfd1212
AD		 1410 u32 regval = rd32(E1000_EIAM);
1411 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1412 wr32(E1000_EIMC, adapter->eims_enable_mask);
1413 regval = rd32(E1000_EIAC);
1414 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1415 }
844290e5
PW		 1416
1417 wr32(E1000_IAM, 0);
9d5c8243
AK		 1418 wr32(E1000_IMC, ~0);
1419 wrfl();
81a61859
ET		 1420 if (adapter->msix_entries) {
1421 int i;
1422 for (i = 0; i < adapter->num_q_vectors; i++)
1423 synchronize_irq(adapter->msix_entries[i].vector);
1424 } else {
1425 synchronize_irq(adapter->pdev->irq);
1426 }
9d5c8243
AK		 1427}
1428
1429/**
1430 * igb_irq_enable - Enable default interrupt generation settings
1431 * @adapter: board private structure
1432 **/
1433static void igb_irq_enable(struct igb_adapter *adapter)
1434{
1435 struct e1000_hw *hw = &adapter->hw;
1436
1437 if (adapter->msix_entries) {
06218a8d 1438 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1439 u32 regval = rd32(E1000_EIAC);
1440 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1441 regval = rd32(E1000_EIAM);
1442 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1443 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1444 if (adapter->vfs_allocated_count) {
4ae196df 1445 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1446 ims |= E1000_IMS_VMMB;
1447 }
1448 wr32(E1000_IMS, ims);
844290e5 1449 } else {
55cac248
AD		 1450 wr32(E1000_IMS, IMS_ENABLE_MASK |
1451 E1000_IMS_DRSTA);
1452 wr32(E1000_IAM, IMS_ENABLE_MASK |
1453 E1000_IMS_DRSTA);
844290e5 1454 }
9d5c8243
AK		 1455}
1456
1457static void igb_update_mng_vlan(struct igb_adapter *adapter)
1458{
51466239 1459 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1460 u16 vid = adapter->hw.mng_cookie.vlan_id;
1461 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1462
1463 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1464 /* add VID to filter table */
1465 igb_vfta_set(hw, vid, true);
1466 adapter->mng_vlan_id = vid;
1467 } else {
1468 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1469 }
1470
1471 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1472 (vid != old_vid) &&
b2cb09b1 1473 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1474 /* remove VID from filter table */
1475 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1476 }
1477}
1478
1479/**
1480 * igb_release_hw_control - release control of the h/w to f/w
1481 * @adapter: address of board private structure
1482 *
1483 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1484 * For ASF and Pass Through versions of f/w this means that the
1485 * driver is no longer loaded.
1486 *
1487 **/
1488static void igb_release_hw_control(struct igb_adapter *adapter)
1489{
1490 struct e1000_hw *hw = &adapter->hw;
1491 u32 ctrl_ext;
1492
1493 /* Let firmware take over control of h/w */
1494 ctrl_ext = rd32(E1000_CTRL_EXT);
1495 wr32(E1000_CTRL_EXT,
1496 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1497}
1498
9d5c8243
AK		 1499/**
1500 * igb_get_hw_control - get control of the h/w from f/w
1501 * @adapter: address of board private structure
1502 *
1503 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1504 * For ASF and Pass Through versions of f/w this means that
1505 * the driver is loaded.
1506 *
1507 **/
1508static void igb_get_hw_control(struct igb_adapter *adapter)
1509{
1510 struct e1000_hw *hw = &adapter->hw;
1511 u32 ctrl_ext;
1512
1513 /* Let firmware know the driver has taken over */
1514 ctrl_ext = rd32(E1000_CTRL_EXT);
1515 wr32(E1000_CTRL_EXT,
1516 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1517}
1518
9d5c8243
AK		 1519/**
1520 * igb_configure - configure the hardware for RX and TX
1521 * @adapter: private board structure
1522 **/
1523static void igb_configure(struct igb_adapter *adapter)
1524{
1525 struct net_device *netdev = adapter->netdev;
1526 int i;
1527
1528 igb_get_hw_control(adapter);
ff41f8dc 1529 igb_set_rx_mode(netdev);
9d5c8243
AK		 1530
1531 igb_restore_vlan(adapter);
9d5c8243 1532
85b430b4 1533 igb_setup_tctl(adapter);
06cf2666 1534 igb_setup_mrqc(adapter);
9d5c8243 1535 igb_setup_rctl(adapter);
85b430b4
AD		 1536
1537 igb_configure_tx(adapter);
9d5c8243 1538 igb_configure_rx(adapter);
662d7205
AD		 1539
1540 igb_rx_fifo_flush_82575(&adapter->hw);
1541
c493ea45 1542 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1543 * at least 1 descriptor unused to make sure
1544 * next_to_use != next_to_clean */
1545 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1546 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1547 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1548 }
9d5c8243
AK		 1549}
1550
88a268c1
NN		 1551/**
1552 * igb_power_up_link - Power up the phy/serdes link
1553 * @adapter: address of board private structure
1554 **/
1555void igb_power_up_link(struct igb_adapter *adapter)
1556{
76886596
AA		 1557 igb_reset_phy(&adapter->hw);
1558
88a268c1
NN		 1559 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1560 igb_power_up_phy_copper(&adapter->hw);
1561 else
1562 igb_power_up_serdes_link_82575(&adapter->hw);
1563}
1564
1565/**
1566 * igb_power_down_link - Power down the phy/serdes link
1567 * @adapter: address of board private structure
1568 */
1569static void igb_power_down_link(struct igb_adapter *adapter)
1570{
1571 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1572 igb_power_down_phy_copper_82575(&adapter->hw);
1573 else
1574 igb_shutdown_serdes_link_82575(&adapter->hw);
1575}
9d5c8243
AK		 1576
1577/**
1578 * igb_up - Open the interface and prepare it to handle traffic
1579 * @adapter: board private structure
1580 **/
9d5c8243
AK		 1581int igb_up(struct igb_adapter *adapter)
1582{
1583 struct e1000_hw *hw = &adapter->hw;
1584 int i;
1585
1586 /* hardware has been reset, we need to reload some things */
1587 igb_configure(adapter);
1588
1589 clear_bit(__IGB_DOWN, &adapter->state);
1590
0d1ae7f4
AD		 1591 for (i = 0; i < adapter->num_q_vectors; i++)
1592 napi_enable(&(adapter->q_vector[i]->napi));
1593
844290e5 1594 if (adapter->msix_entries)
9d5c8243 1595 igb_configure_msix(adapter);
feeb2721
AD		 1596 else
1597 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1598
1599 /* Clear any pending interrupts. */
1600 rd32(E1000_ICR);
1601 igb_irq_enable(adapter);
1602
d4960307
AD		 1603 /* notify VFs that reset has been completed */
1604 if (adapter->vfs_allocated_count) {
1605 u32 reg_data = rd32(E1000_CTRL_EXT);
1606 reg_data |= E1000_CTRL_EXT_PFRSTD;
1607 wr32(E1000_CTRL_EXT, reg_data);
1608 }
1609
4cb9be7a
JB		 1610 netif_tx_start_all_queues(adapter->netdev);
1611
25568a53
AD		 1612 /* start the watchdog. */
1613 hw->mac.get_link_status = 1;
1614 schedule_work(&adapter->watchdog_task);
1615
9d5c8243
AK		 1616 return 0;
1617}
1618
1619void igb_down(struct igb_adapter *adapter)
1620{
9d5c8243 1621 struct net_device *netdev = adapter->netdev;
330a6d6a 1622 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1623 u32 tctl, rctl;
1624 int i;
1625
1626 /* signal that we're down so the interrupt handler does not
1627 * reschedule our watchdog timer */
1628 set_bit(__IGB_DOWN, &adapter->state);
1629
1630 /* disable receives in the hardware */
1631 rctl = rd32(E1000_RCTL);
1632 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1633 /* flush and sleep below */
1634
fd2ea0a7 1635 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1636
1637 /* disable transmits in the hardware */
1638 tctl = rd32(E1000_TCTL);
1639 tctl &= ~E1000_TCTL_EN;
1640 wr32(E1000_TCTL, tctl);
1641 /* flush both disables and wait for them to finish */
1642 wrfl();
1643 msleep(10);
1644
0d1ae7f4
AD		 1645 for (i = 0; i < adapter->num_q_vectors; i++)
1646 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1647
9d5c8243
AK		 1648 igb_irq_disable(adapter);
1649
1650 del_timer_sync(&adapter->watchdog_timer);
1651 del_timer_sync(&adapter->phy_info_timer);
1652
9d5c8243 1653 netif_carrier_off(netdev);
04fe6358
AD		 1654
1655 /* record the stats before reset*/
12dcd86b
ED		 1656 spin_lock(&adapter->stats64_lock);
1657 igb_update_stats(adapter, &adapter->stats64);
1658 spin_unlock(&adapter->stats64_lock);
04fe6358 1659
9d5c8243
AK		 1660 adapter->link_speed = 0;
1661 adapter->link_duplex = 0;
1662
3023682e
JK		 1663 if (!pci_channel_offline(adapter->pdev))
1664 igb_reset(adapter);
9d5c8243
AK		 1665 igb_clean_all_tx_rings(adapter);
1666 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1667#ifdef CONFIG_IGB_DCA
1668
1669 /* since we reset the hardware DCA settings were cleared */
1670 igb_setup_dca(adapter);
1671#endif
9d5c8243
AK		 1672}
1673
1674void igb_reinit_locked(struct igb_adapter *adapter)
1675{
1676 WARN_ON(in_interrupt());
1677 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1678 msleep(1);
1679 igb_down(adapter);
1680 igb_up(adapter);
1681 clear_bit(__IGB_RESETTING, &adapter->state);
1682}
1683
1684void igb_reset(struct igb_adapter *adapter)
1685{
090b1795 1686 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1687 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1688 struct e1000_mac_info *mac = &hw->mac;
1689 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1690 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1691
1692 /* Repartition Pba for greater than 9k mtu
1693 * To take effect CTRL.RST is required.
1694 */
fa4dfae0 1695 switch (mac->type) {
d2ba2ed8 1696 case e1000_i350:
55cac248
AD		 1697 case e1000_82580:
1698 pba = rd32(E1000_RXPBS);
1699 pba = igb_rxpbs_adjust_82580(pba);
1700 break;
fa4dfae0 1701 case e1000_82576:
d249be54
AD		 1702 pba = rd32(E1000_RXPBS);
1703 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1704 break;
1705 case e1000_82575:
f96a8a0b
CW		 1706 case e1000_i210:
1707 case e1000_i211:
fa4dfae0
AD		 1708 default:
1709 pba = E1000_PBA_34K;
1710 break;
2d064c06 1711 }
9d5c8243 1712
2d064c06
AD		 1713 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1714 (mac->type < e1000_82576)) {
9d5c8243
AK		 1715 /* adjust PBA for jumbo frames */
1716 wr32(E1000_PBA, pba);
1717
1718 /* To maintain wire speed transmits, the Tx FIFO should be
1719 * large enough to accommodate two full transmit packets,
1720 * rounded up to the next 1KB and expressed in KB. Likewise,
1721 * the Rx FIFO should be large enough to accommodate at least
1722 * one full receive packet and is similarly rounded up and
1723 * expressed in KB. */
1724 pba = rd32(E1000_PBA);
1725 /* upper 16 bits has Tx packet buffer allocation size in KB */
1726 tx_space = pba >> 16;
1727 /* lower 16 bits has Rx packet buffer allocation size in KB */
1728 pba &= 0xffff;
1729 /* the tx fifo also stores 16 bytes of information about the tx
1730 * but don't include ethernet FCS because hardware appends it */
1731 min_tx_space = (adapter->max_frame_size +
85e8d004 1732 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1733 ETH_FCS_LEN) * 2;
1734 min_tx_space = ALIGN(min_tx_space, 1024);
1735 min_tx_space >>= 10;
1736 /* software strips receive CRC, so leave room for it */
1737 min_rx_space = adapter->max_frame_size;
1738 min_rx_space = ALIGN(min_rx_space, 1024);
1739 min_rx_space >>= 10;
1740
1741 /* If current Tx allocation is less than the min Tx FIFO size,
1742 * and the min Tx FIFO size is less than the current Rx FIFO
1743 * allocation, take space away from current Rx allocation */
1744 if (tx_space < min_tx_space &&
1745 ((min_tx_space - tx_space) < pba)) {
1746 pba = pba - (min_tx_space - tx_space);
1747
1748 /* if short on rx space, rx wins and must trump tx
1749 * adjustment */
1750 if (pba < min_rx_space)
1751 pba = min_rx_space;
1752 }
2d064c06 1753 wr32(E1000_PBA, pba);
9d5c8243 1754 }
9d5c8243
AK		 1755
1756 /* flow control settings */
1757 /* The high water mark must be low enough to fit one full frame
1758 * (or the size used for early receive) above it in the Rx FIFO.
1759 * Set it to the lower of:
1760 * - 90% of the Rx FIFO size, or
1761 * - the full Rx FIFO size minus one full frame */
1762 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1763 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1764
d48507fe 1765 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1766 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1767 fc->pause_time = 0xFFFF;
1768 fc->send_xon = 1;
0cce119a 1769 fc->current_mode = fc->requested_mode;
9d5c8243 1770
4ae196df
AD		 1771 /* disable receive for all VFs and wait one second */
1772 if (adapter->vfs_allocated_count) {
1773 int i;
1774 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1775 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1776
1777 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1778 igb_ping_all_vfs(adapter);
4ae196df
AD		 1779
1780 /* disable transmits and receives */
1781 wr32(E1000_VFRE, 0);
1782 wr32(E1000_VFTE, 0);
1783 }
1784
9d5c8243 1785 /* Allow time for pending master requests to run */
330a6d6a 1786 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1787 wr32(E1000_WUC, 0);
1788
330a6d6a 1789 if (hw->mac.ops.init_hw(hw))
090b1795 1790 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1791
a27416bb
MV		 1792 /*
1793 * Flow control settings reset on hardware reset, so guarantee flow
1794 * control is off when forcing speed.
1795 */
1796 if (!hw->mac.autoneg)
1797 igb_force_mac_fc(hw);
1798
b6e0c419 1799 igb_init_dmac(adapter, pba);
e428893b
CW		 1800#ifdef CONFIG_IGB_HWMON
1801 /* Re-initialize the thermal sensor on i350 devices. */
1802 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1803 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1804 /* If present, re-initialize the external thermal sensor
1805 * interface.
1806 */
1807 if (adapter->ets)
1808 mac->ops.init_thermal_sensor_thresh(hw);
1809 }
1810 }
1811#endif
88a268c1
NN		 1812 if (!netif_running(adapter->netdev))
1813 igb_power_down_link(adapter);
1814
9d5c8243
AK		 1815 igb_update_mng_vlan(adapter);
1816
1817 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1818 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1819
1f6e8178
MV		 1820 /* Re-enable PTP, where applicable. */
1821 igb_ptp_reset(adapter);
1f6e8178 1822
330a6d6a 1823 igb_get_phy_info(hw);
9d5c8243
AK		 1824}
1825
c8f44aff
MM		 1826static netdev_features_t igb_fix_features(struct net_device *netdev,
1827 netdev_features_t features)
b2cb09b1
JP		 1828{
1829 /*
1830 * Since there is no support for separate rx/tx vlan accel
1831 * enable/disable make sure tx flag is always in same state as rx.
1832 */
1833 if (features & NETIF_F_HW_VLAN_RX)
1834 features |= NETIF_F_HW_VLAN_TX;
1835 else
1836 features &= ~NETIF_F_HW_VLAN_TX;
1837
1838 return features;
1839}
1840
c8f44aff
MM		 1841static int igb_set_features(struct net_device *netdev,
1842 netdev_features_t features)
ac52caa3 1843{
c8f44aff 1844 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1845 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1846
b2cb09b1
JP		 1847 if (changed & NETIF_F_HW_VLAN_RX)
1848 igb_vlan_mode(netdev, features);
1849
89eaefb6
BG		 1850 if (!(changed & NETIF_F_RXALL))
1851 return 0;
1852
1853 netdev->features = features;
1854
1855 if (netif_running(netdev))
1856 igb_reinit_locked(adapter);
1857 else
1858 igb_reset(adapter);
1859
ac52caa3
MM		 1860 return 0;
1861}
1862
2e5c6922 1863static const struct net_device_ops igb_netdev_ops = {
559e9c49 1864 .ndo_open = igb_open,
2e5c6922 1865 .ndo_stop = igb_close,
cd392f5c 1866 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1867 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1868 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1869 .ndo_set_mac_address = igb_set_mac,
1870 .ndo_change_mtu = igb_change_mtu,
1871 .ndo_do_ioctl = igb_ioctl,
1872 .ndo_tx_timeout = igb_tx_timeout,
1873 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1874 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1875 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1876 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1877 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1878 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1879 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1880#ifdef CONFIG_NET_POLL_CONTROLLER
1881 .ndo_poll_controller = igb_netpoll,
1882#endif
b2cb09b1
JP		 1883 .ndo_fix_features = igb_fix_features,
1884 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1885};
1886
d67974f0
CW		 1887/**
1888 * igb_set_fw_version - Configure version string for ethtool
1889 * @adapter: adapter struct
1890 *
1891 **/
1892void igb_set_fw_version(struct igb_adapter *adapter)
1893{
1894 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1895 struct e1000_fw_version fw;
1896
1897 igb_get_fw_version(hw, &fw);
1898
1899 switch (hw->mac.type) {
1900 case e1000_i211:
d67974f0 1901 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1902 "%2d.%2d-%d",
1903 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1904 break;
1905
1906 default:
1907 /* if option is rom valid, display its version too */
1908 if (fw.or_valid) {
1909 snprintf(adapter->fw_version,
1910 sizeof(adapter->fw_version),
1911 "%d.%d, 0x%08x, %d.%d.%d",
1912 fw.eep_major, fw.eep_minor, fw.etrack_id,
1913 fw.or_major, fw.or_build, fw.or_patch);
1914 /* no option rom */
1915 } else {
1916 snprintf(adapter->fw_version,
1917 sizeof(adapter->fw_version),
1918 "%d.%d, 0x%08x",
1919 fw.eep_major, fw.eep_minor, fw.etrack_id);
1920 }
1921 break;
d67974f0 1922 }
d67974f0
CW		 1923 return;
1924}
1925
441fc6fd
CW		 1926static const struct i2c_board_info i350_sensor_info = {
1927 I2C_BOARD_INFO("i350bb", 0Xf8),
1928};
1929
1930/* igb_init_i2c - Init I2C interface
1931 * @adapter: pointer to adapter structure
1932 *
1933 */
1934static s32 igb_init_i2c(struct igb_adapter *adapter)
1935{
1936 s32 status = E1000_SUCCESS;
1937
1938 /* I2C interface supported on i350 devices */
1939 if (adapter->hw.mac.type != e1000_i350)
1940 return E1000_SUCCESS;
1941
1942 /* Initialize the i2c bus which is controlled by the registers.
1943 * This bus will use the i2c_algo_bit structue that implements
1944 * the protocol through toggling of the 4 bits in the register.
1945 */
1946 adapter->i2c_adap.owner = THIS_MODULE;
1947 adapter->i2c_algo = igb_i2c_algo;
1948 adapter->i2c_algo.data = adapter;
1949 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1950 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1951 strlcpy(adapter->i2c_adap.name, "igb BB",
1952 sizeof(adapter->i2c_adap.name));
1953 status = i2c_bit_add_bus(&adapter->i2c_adap);
1954 return status;
1955}
1956
9d5c8243
AK		 1957/**
1958 * igb_probe - Device Initialization Routine
1959 * @pdev: PCI device information struct
1960 * @ent: entry in igb_pci_tbl
1961 *
1962 * Returns 0 on success, negative on failure
1963 *
1964 * igb_probe initializes an adapter identified by a pci_dev structure.
1965 * The OS initialization, configuring of the adapter private structure,
1966 * and a hardware reset occur.
1967 **/
1dd06ae8 1968static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1969{
1970 struct net_device *netdev;
1971 struct igb_adapter *adapter;
1972 struct e1000_hw *hw;
4337e993 1973 u16 eeprom_data = 0;
9835fd73 1974 s32 ret_val;
4337e993 1975 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1976 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1977 unsigned long mmio_start, mmio_len;
2d6a5e95 1978 int err, pci_using_dac;
9835fd73 1979 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1980
bded64a7
AG		 1981 /* Catch broken hardware that put the wrong VF device ID in
1982 * the PCIe SR-IOV capability.
1983 */
1984 if (pdev->is_virtfn) {
1985 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1986 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1987 return -EINVAL;
1988 }
1989
aed5dec3 1990 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1991 if (err)
1992 return err;
1993
1994 pci_using_dac = 0;
59d71989 1995 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1996 if (!err) {
59d71989 1997 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1998 if (!err)
1999 pci_using_dac = 1;
2000 } else {
59d71989 2001 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2002 if (err) {
59d71989 2003 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 2004 if (err) {
2005 dev_err(&pdev->dev, "No usable DMA "
2006 "configuration, aborting\n");
2007 goto err_dma;
2008 }
2009 }
2010 }
2011
aed5dec3
AD		 2012 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2013 IORESOURCE_MEM),
2014 igb_driver_name);
9d5c8243
AK		 2015 if (err)
2016 goto err_pci_reg;
2017
19d5afd4 2018 pci_enable_pcie_error_reporting(pdev);
40a914fa 2019
9d5c8243 2020 pci_set_master(pdev);
c682fc23 2021 pci_save_state(pdev);
9d5c8243
AK		 2022
2023 err = -ENOMEM;
1bfaf07b 2024 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2025 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2026 if (!netdev)
2027 goto err_alloc_etherdev;
2028
2029 SET_NETDEV_DEV(netdev, &pdev->dev);
2030
2031 pci_set_drvdata(pdev, netdev);
2032 adapter = netdev_priv(netdev);
2033 adapter->netdev = netdev;
2034 adapter->pdev = pdev;
2035 hw = &adapter->hw;
2036 hw->back = adapter;
b3f4d599 2037 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2038
2039 mmio_start = pci_resource_start(pdev, 0);
2040 mmio_len = pci_resource_len(pdev, 0);
2041
2042 err = -EIO;
28b0759c
AD		 2043 hw->hw_addr = ioremap(mmio_start, mmio_len);
2044 if (!hw->hw_addr)
9d5c8243
AK		 2045 goto err_ioremap;
2046
2e5c6922 2047 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2048 igb_set_ethtool_ops(netdev);
9d5c8243 2049 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2050
2051 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2052
2053 netdev->mem_start = mmio_start;
2054 netdev->mem_end = mmio_start + mmio_len;
2055
9d5c8243
AK		 2056 /* PCI config space info */
2057 hw->vendor_id = pdev->vendor;
2058 hw->device_id = pdev->device;
2059 hw->revision_id = pdev->revision;
2060 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2061 hw->subsystem_device_id = pdev->subsystem_device;
2062
9d5c8243
AK		 2063 /* Copy the default MAC, PHY and NVM function pointers */
2064 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2065 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2066 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2067 /* Initialize skew-specific constants */
2068 err = ei->get_invariants(hw);
2069 if (err)
450c87c8 2070 goto err_sw_init;
9d5c8243 2071
450c87c8 2072 /* setup the private structure */
9d5c8243
AK		 2073 err = igb_sw_init(adapter);
2074 if (err)
2075 goto err_sw_init;
2076
2077 igb_get_bus_info_pcie(hw);
2078
2079 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2080
2081 /* Copper options */
2082 if (hw->phy.media_type == e1000_media_type_copper) {
2083 hw->phy.mdix = AUTO_ALL_MODES;
2084 hw->phy.disable_polarity_correction = false;
2085 hw->phy.ms_type = e1000_ms_hw_default;
2086 }
2087
2088 if (igb_check_reset_block(hw))
2089 dev_info(&pdev->dev,
2090 "PHY reset is blocked due to SOL/IDER session.\n");
2091
077887c3
AD		 2092 /*
2093 * features is initialized to 0 in allocation, it might have bits
2094 * set by igb_sw_init so we should use an or instead of an
2095 * assignment.
2096 */
2097 netdev->features |= NETIF_F_SG |
2098 NETIF_F_IP_CSUM |
2099 NETIF_F_IPV6_CSUM |
2100 NETIF_F_TSO |
2101 NETIF_F_TSO6 |
2102 NETIF_F_RXHASH |
2103 NETIF_F_RXCSUM |
2104 NETIF_F_HW_VLAN_RX |
2105 NETIF_F_HW_VLAN_TX;
2106
2107 /* copy netdev features into list of user selectable features */
2108 netdev->hw_features |= netdev->features;
89eaefb6 2109 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2110
2111 /* set this bit last since it cannot be part of hw_features */
2112 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2113
2114 netdev->vlan_features |= NETIF_F_TSO |
2115 NETIF_F_TSO6 |
2116 NETIF_F_IP_CSUM |
2117 NETIF_F_IPV6_CSUM |
2118 NETIF_F_SG;
48f29ffc 2119
6b8f0922
BG		 2120 netdev->priv_flags |= IFF_SUPP_NOFCS;
2121
7b872a55 2122 if (pci_using_dac) {
9d5c8243 2123 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2124 netdev->vlan_features |= NETIF_F_HIGHDMA;
2125 }
9d5c8243 2126
ac52caa3
MM		 2127 if (hw->mac.type >= e1000_82576) {
2128 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2129 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2130 }
b9473560 2131
01789349
JP		 2132 netdev->priv_flags |= IFF_UNICAST_FLT;
2133
330a6d6a 2134 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2135
2136 /* before reading the NVM, reset the controller to put the device in a
2137 * known good starting state */
2138 hw->mac.ops.reset_hw(hw);
2139
f96a8a0b
CW		 2140 /*
2141 * make sure the NVM is good , i211 parts have special NVM that
2142 * doesn't contain a checksum
2143 */
2144 if (hw->mac.type != e1000_i211) {
2145 if (hw->nvm.ops.validate(hw) < 0) {
2146 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2147 err = -EIO;
2148 goto err_eeprom;
2149 }
9d5c8243
AK		 2150 }
2151
2152 /* copy the MAC address out of the NVM */
2153 if (hw->mac.ops.read_mac_addr(hw))
2154 dev_err(&pdev->dev, "NVM Read Error\n");
2155
2156 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2157
aaeb6cdf 2158 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2159 dev_err(&pdev->dev, "Invalid MAC Address\n");
2160 err = -EIO;
2161 goto err_eeprom;
2162 }
2163
d67974f0
CW		 2164 /* get firmware version for ethtool -i */
2165 igb_set_fw_version(adapter);
2166
c061b18d 2167 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2168 (unsigned long) adapter);
c061b18d 2169 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2170 (unsigned long) adapter);
9d5c8243
AK		 2171
2172 INIT_WORK(&adapter->reset_task, igb_reset_task);
2173 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2174
450c87c8 2175 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2176 adapter->fc_autoneg = true;
2177 hw->mac.autoneg = true;
2178 hw->phy.autoneg_advertised = 0x2f;
2179
0cce119a
AD		 2180 hw->fc.requested_mode = e1000_fc_default;
2181 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2182
9d5c8243
AK		 2183 igb_validate_mdi_setting(hw);
2184
63d4a8f9 2185 /* By default, support wake on port A */
a2cf8b6c 2186 if (hw->bus.func == 0)
63d4a8f9
MV		 2187 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2188
2189 /* Check the NVM for wake support on non-port A ports */
2190 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2191 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2192 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2193 &eeprom_data);
a2cf8b6c
AD		 2194 else if (hw->bus.func == 1)
2195 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2196
63d4a8f9
MV		 2197 if (eeprom_data & IGB_EEPROM_APME)
2198 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2199
2200 /* now that we have the eeprom settings, apply the special cases where
2201 * the eeprom may be wrong or the board simply won't support wake on
2202 * lan on a particular port */
2203 switch (pdev->device) {
2204 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2205 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2206 break;
2207 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2208 case E1000_DEV_ID_82576_FIBER:
2209 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2210 /* Wake events only supported on port A for dual fiber
2211 * regardless of eeprom setting */
2212 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2213 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2214 break;
c8ea5ea9 2215 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2216 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2217 /* if quad port adapter, disable WoL on all but port A */
2218 if (global_quad_port_a != 0)
63d4a8f9 2219 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2220 else
2221 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2222 /* Reset for multiple quad port adapters */
2223 if (++global_quad_port_a == 4)
2224 global_quad_port_a = 0;
2225 break;
63d4a8f9
MV		 2226 default:
2227 /* If the device can't wake, don't set software support */
2228 if (!device_can_wakeup(&adapter->pdev->dev))
2229 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2230 }
2231
2232 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2233 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2234 adapter->wol |= E1000_WUFC_MAG;
2235
2236 /* Some vendors want WoL disabled by default, but still supported */
2237 if ((hw->mac.type == e1000_i350) &&
2238 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2239 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2240 adapter->wol = 0;
2241 }
2242
2243 device_set_wakeup_enable(&adapter->pdev->dev,
2244 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2245
2246 /* reset the hardware with the new settings */
2247 igb_reset(adapter);
2248
441fc6fd
CW		 2249 /* Init the I2C interface */
2250 err = igb_init_i2c(adapter);
2251 if (err) {
2252 dev_err(&pdev->dev, "failed to init i2c interface\n");
2253 goto err_eeprom;
2254 }
2255
9d5c8243
AK		 2256 /* let the f/w know that the h/w is now under the control of the
2257 * driver. */
2258 igb_get_hw_control(adapter);
2259
9d5c8243
AK		 2260 strcpy(netdev->name, "eth%d");
2261 err = register_netdev(netdev);
2262 if (err)
2263 goto err_register;
2264
b168dfc5
JB		 2265 /* carrier off reporting is important to ethtool even BEFORE open */
2266 netif_carrier_off(netdev);
2267
421e02f0 2268#ifdef CONFIG_IGB_DCA
bbd98fe4 2269 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2270 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2271 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2272 igb_setup_dca(adapter);
2273 }
fe4506b6 2274
38c845c7 2275#endif
e428893b
CW		 2276#ifdef CONFIG_IGB_HWMON
2277 /* Initialize the thermal sensor on i350 devices. */
2278 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2279 u16 ets_word;
3c89f6d0 2280
e428893b
CW		 2281 /*
2282 * Read the NVM to determine if this i350 device supports an
2283 * external thermal sensor.
2284 */
2285 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2286 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2287 adapter->ets = true;
2288 else
2289 adapter->ets = false;
2290 if (igb_sysfs_init(adapter))
2291 dev_err(&pdev->dev,
2292 "failed to allocate sysfs resources\n");
2293 } else {
2294 adapter->ets = false;
2295 }
2296#endif
673b8b70 2297 /* do hw tstamp init after resetting */
7ebae817 2298 igb_ptp_init(adapter);
673b8b70 2299
9d5c8243
AK		 2300 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2301 /* print bus type/speed/width info */
7c510e4b 2302 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2303 netdev->name,
559e9c49 2304 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2305 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2306 "unknown"),
59c3de89
AD		 2307 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2308 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2309 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2310 "unknown"),
7c510e4b 2311 netdev->dev_addr);
9d5c8243 2312
9835fd73
CW		 2313 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2314 if (ret_val)
2315 strcpy(part_str, "Unknown");
2316 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2317 dev_info(&pdev->dev,
2318 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2319 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2320 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2321 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2322 switch (hw->mac.type) {
2323 case e1000_i350:
f96a8a0b
CW		 2324 case e1000_i210:
2325 case e1000_i211:
09b068d4
CW		 2326 igb_set_eee_i350(hw);
2327 break;
2328 default:
2329 break;
2330 }
749ab2cd
YZ		 2331
2332 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2333 return 0;
2334
2335err_register:
2336 igb_release_hw_control(adapter);
441fc6fd 2337 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2338err_eeprom:
2339 if (!igb_check_reset_block(hw))
f5f4cf08 2340 igb_reset_phy(hw);
9d5c8243
AK		 2341
2342 if (hw->flash_address)
2343 iounmap(hw->flash_address);
9d5c8243 2344err_sw_init:
047e0030 2345 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2346 iounmap(hw->hw_addr);
2347err_ioremap:
2348 free_netdev(netdev);
2349err_alloc_etherdev:
559e9c49
AD		 2350 pci_release_selected_regions(pdev,
2351 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2352err_pci_reg:
2353err_dma:
2354 pci_disable_device(pdev);
2355 return err;
2356}
2357
fa44f2f1
GR		 2358#ifdef CONFIG_PCI_IOV
2359static int igb_disable_sriov(struct pci_dev *pdev)
2360{
2361 struct net_device *netdev = pci_get_drvdata(pdev);
2362 struct igb_adapter *adapter = netdev_priv(netdev);
2363 struct e1000_hw *hw = &adapter->hw;
2364
2365 /* reclaim resources allocated to VFs */
2366 if (adapter->vf_data) {
2367 /* disable iov and allow time for transactions to clear */
2368 if (igb_vfs_are_assigned(adapter)) {
2369 dev_warn(&pdev->dev,
2370 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2371 return -EPERM;
2372 } else {
2373 pci_disable_sriov(pdev);
2374 msleep(500);
2375 }
2376
2377 kfree(adapter->vf_data);
2378 adapter->vf_data = NULL;
2379 adapter->vfs_allocated_count = 0;
2380 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2381 wrfl();
2382 msleep(100);
2383 dev_info(&pdev->dev, "IOV Disabled\n");
2384
2385 /* Re-enable DMA Coalescing flag since IOV is turned off */
2386 adapter->flags |= IGB_FLAG_DMAC;
2387 }
2388
2389 return 0;
2390}
2391
2392static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2393{
2394 struct net_device *netdev = pci_get_drvdata(pdev);
2395 struct igb_adapter *adapter = netdev_priv(netdev);
2396 int old_vfs = pci_num_vf(pdev);
2397 int err = 0;
2398 int i;
2399
2400 if (!num_vfs)
2401 goto out;
2402 else if (old_vfs && old_vfs == num_vfs)
2403 goto out;
2404 else if (old_vfs && old_vfs != num_vfs)
2405 err = igb_disable_sriov(pdev);
2406
2407 if (err)
2408 goto out;
2409
2410 if (num_vfs > 7) {
2411 err = -EPERM;
2412 goto out;
2413 }
2414
2415 adapter->vfs_allocated_count = num_vfs;
2416
2417 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2418 sizeof(struct vf_data_storage), GFP_KERNEL);
2419
2420 /* if allocation failed then we do not support SR-IOV */
2421 if (!adapter->vf_data) {
2422 adapter->vfs_allocated_count = 0;
2423 dev_err(&pdev->dev,
2424 "Unable to allocate memory for VF Data Storage\n");
2425 err = -ENOMEM;
2426 goto out;
2427 }
2428
2429 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2430 if (err)
2431 goto err_out;
2432
2433 dev_info(&pdev->dev, "%d VFs allocated\n",
2434 adapter->vfs_allocated_count);
2435 for (i = 0; i < adapter->vfs_allocated_count; i++)
2436 igb_vf_configure(adapter, i);
2437
2438 /* DMA Coalescing is not supported in IOV mode. */
2439 adapter->flags &= ~IGB_FLAG_DMAC;
2440 goto out;
2441
2442err_out:
2443 kfree(adapter->vf_data);
2444 adapter->vf_data = NULL;
2445 adapter->vfs_allocated_count = 0;
2446out:
2447 return err;
2448}
2449
2450#endif
441fc6fd
CW		 2451/*
2452 * igb_remove_i2c - Cleanup I2C interface
2453 * @adapter: pointer to adapter structure
2454 *
2455 */
2456static void igb_remove_i2c(struct igb_adapter *adapter)
2457{
2458
2459 /* free the adapter bus structure */
2460 i2c_del_adapter(&adapter->i2c_adap);
2461}
2462
9d5c8243
AK		 2463/**
2464 * igb_remove - Device Removal Routine
2465 * @pdev: PCI device information struct
2466 *
2467 * igb_remove is called by the PCI subsystem to alert the driver
2468 * that it should release a PCI device. The could be caused by a
2469 * Hot-Plug event, or because the driver is going to be removed from
2470 * memory.
2471 **/
9f9a12f8 2472static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2473{
2474 struct net_device *netdev = pci_get_drvdata(pdev);
2475 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2476 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2477
749ab2cd 2478 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2479#ifdef CONFIG_IGB_HWMON
2480 igb_sysfs_exit(adapter);
2481#endif
441fc6fd 2482 igb_remove_i2c(adapter);
a79f4f88 2483 igb_ptp_stop(adapter);
760141a5
TH		 2484 /*
2485 * The watchdog timer may be rescheduled, so explicitly
2486 * disable watchdog from being rescheduled.
2487 */
9d5c8243
AK		 2488 set_bit(__IGB_DOWN, &adapter->state);
2489 del_timer_sync(&adapter->watchdog_timer);
2490 del_timer_sync(&adapter->phy_info_timer);
2491
760141a5
TH		 2492 cancel_work_sync(&adapter->reset_task);
2493 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2494
421e02f0 2495#ifdef CONFIG_IGB_DCA
7dfc16fa 2496 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2497 dev_info(&pdev->dev, "DCA disabled\n");
2498 dca_remove_requester(&pdev->dev);
7dfc16fa 2499 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2500 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2501 }
2502#endif
2503
9d5c8243
AK		 2504 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2505 * would have already happened in close and is redundant. */
2506 igb_release_hw_control(adapter);
2507
2508 unregister_netdev(netdev);
2509
047e0030 2510 igb_clear_interrupt_scheme(adapter);
9d5c8243 2511
37680117 2512#ifdef CONFIG_PCI_IOV
fa44f2f1 2513 igb_disable_sriov(pdev);
37680117 2514#endif
559e9c49 2515
28b0759c
AD		 2516 iounmap(hw->hw_addr);
2517 if (hw->flash_address)
2518 iounmap(hw->flash_address);
559e9c49
AD		 2519 pci_release_selected_regions(pdev,
2520 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2521
1128c756 2522 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2523 free_netdev(netdev);
2524
19d5afd4 2525 pci_disable_pcie_error_reporting(pdev);
40a914fa 2526
9d5c8243
AK		 2527 pci_disable_device(pdev);
2528}
2529
a6b623e0
AD		 2530/**
2531 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2532 * @adapter: board private structure to initialize
2533 *
2534 * This function initializes the vf specific data storage and then attempts to
2535 * allocate the VFs. The reason for ordering it this way is because it is much
2536 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2537 * the memory for the VFs.
2538 **/
9f9a12f8 2539static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2540{
2541#ifdef CONFIG_PCI_IOV
2542 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2543 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2544
f96a8a0b
CW		 2545 /* Virtualization features not supported on i210 family. */
2546 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2547 return;
2548
fa44f2f1
GR		 2549 igb_enable_sriov(pdev, max_vfs);
2550 pci_sriov_set_totalvfs(pdev, 7);
0224d663 2551
a6b623e0
AD		 2552#endif /* CONFIG_PCI_IOV */
2553}
2554
fa44f2f1 2555static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2556{
2557 struct e1000_hw *hw = &adapter->hw;
374a542d 2558 u32 max_rss_queues;
9d5c8243 2559
374a542d 2560 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2561 switch (hw->mac.type) {
374a542d
MV		 2562 case e1000_i211:
2563 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2564 break;
2565 case e1000_82575:
f96a8a0b 2566 case e1000_i210:
374a542d
MV		 2567 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2568 break;
2569 case e1000_i350:
2570 /* I350 cannot do RSS and SR-IOV at the same time */
2571 if (!!adapter->vfs_allocated_count) {
2572 max_rss_queues = 1;
2573 break;
2574 }
2575 /* fall through */
2576 case e1000_82576:
2577 if (!!adapter->vfs_allocated_count) {
2578 max_rss_queues = 2;
2579 break;
2580 }
2581 /* fall through */
2582 case e1000_82580:
2583 default:
2584 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2585 break;
374a542d
MV		 2586 }
2587
2588 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2589
2590 /* Determine if we need to pair queues. */
2591 switch (hw->mac.type) {
2592 case e1000_82575:
f96a8a0b 2593 case e1000_i211:
374a542d 2594 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2595 break;
374a542d
MV		 2596 case e1000_82576:
2597 /*
2598 * If VFs are going to be allocated with RSS queues then we
2599 * should pair the queues in order to conserve interrupts due
2600 * to limited supply.
2601 */
2602 if ((adapter->rss_queues > 1) &&
2603 (adapter->vfs_allocated_count > 6))
2604 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2605 /* fall through */
2606 case e1000_82580:
2607 case e1000_i350:
2608 case e1000_i210:
f96a8a0b 2609 default:
374a542d
MV		 2610 /*
2611 * If rss_queues > half of max_rss_queues, pair the queues in
2612 * order to conserve interrupts due to limited supply.
2613 */
2614 if (adapter->rss_queues > (max_rss_queues / 2))
2615 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2616 break;
2617 }
fa44f2f1
GR		 2618}
2619
2620/**
2621 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2622 * @adapter: board private structure to initialize
2623 *
2624 * igb_sw_init initializes the Adapter private data structure.
2625 * Fields are initialized based on PCI device information and
2626 * OS network device settings (MTU size).
2627 **/
2628static int igb_sw_init(struct igb_adapter *adapter)
2629{
2630 struct e1000_hw *hw = &adapter->hw;
2631 struct net_device *netdev = adapter->netdev;
2632 struct pci_dev *pdev = adapter->pdev;
2633
2634 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2635
2636 /* set default ring sizes */
2637 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2638 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2639
2640 /* set default ITR values */
2641 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2642 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2643
2644 /* set default work limits */
2645 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2646
2647 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2648 VLAN_HLEN;
2649 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2650
2651 spin_lock_init(&adapter->stats64_lock);
2652#ifdef CONFIG_PCI_IOV
2653 switch (hw->mac.type) {
2654 case e1000_82576:
2655 case e1000_i350:
2656 if (max_vfs > 7) {
2657 dev_warn(&pdev->dev,
2658 "Maximum of 7 VFs per PF, using max\n");
2659 adapter->vfs_allocated_count = 7;
2660 } else
2661 adapter->vfs_allocated_count = max_vfs;
2662 if (adapter->vfs_allocated_count)
2663 dev_warn(&pdev->dev,
2664 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2665 break;
2666 default:
2667 break;
2668 }
2669#endif /* CONFIG_PCI_IOV */
2670
2671 igb_init_queue_configuration(adapter);
a99955fc 2672
1128c756 2673 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2674 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2675 GFP_ATOMIC);
1128c756 2676
a6b623e0 2677 /* This call may decrease the number of queues */
53c7d064 2678 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2679 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2680 return -ENOMEM;
2681 }
2682
a6b623e0
AD		 2683 igb_probe_vfs(adapter);
2684
9d5c8243
AK		 2685 /* Explicitly disable IRQ since the NIC can be in any state. */
2686 igb_irq_disable(adapter);
2687
f96a8a0b 2688 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2689 adapter->flags &= ~IGB_FLAG_DMAC;
2690
9d5c8243
AK		 2691 set_bit(__IGB_DOWN, &adapter->state);
2692 return 0;
2693}
2694
2695/**
2696 * igb_open - Called when a network interface is made active
2697 * @netdev: network interface device structure
2698 *
2699 * Returns 0 on success, negative value on failure
2700 *
2701 * The open entry point is called when a network interface is made
2702 * active by the system (IFF_UP). At this point all resources needed
2703 * for transmit and receive operations are allocated, the interrupt
2704 * handler is registered with the OS, the watchdog timer is started,
2705 * and the stack is notified that the interface is ready.
2706 **/
749ab2cd 2707static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2708{
2709 struct igb_adapter *adapter = netdev_priv(netdev);
2710 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2711 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2712 int err;
2713 int i;
2714
2715 /* disallow open during test */
749ab2cd
YZ		 2716 if (test_bit(__IGB_TESTING, &adapter->state)) {
2717 WARN_ON(resuming);
9d5c8243 2718 return -EBUSY;
749ab2cd
YZ		 2719 }
2720
2721 if (!resuming)
2722 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2723
b168dfc5
JB		 2724 netif_carrier_off(netdev);
2725
9d5c8243
AK		 2726 /* allocate transmit descriptors */
2727 err = igb_setup_all_tx_resources(adapter);
2728 if (err)
2729 goto err_setup_tx;
2730
2731 /* allocate receive descriptors */
2732 err = igb_setup_all_rx_resources(adapter);
2733 if (err)
2734 goto err_setup_rx;
2735
88a268c1 2736 igb_power_up_link(adapter);
9d5c8243 2737
9d5c8243
AK		 2738 /* before we allocate an interrupt, we must be ready to handle it.
2739 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2740 * as soon as we call pci_request_irq, so we have to setup our
2741 * clean_rx handler before we do so. */
2742 igb_configure(adapter);
2743
2744 err = igb_request_irq(adapter);
2745 if (err)
2746 goto err_req_irq;
2747
0c2cc02e
AD		 2748 /* Notify the stack of the actual queue counts. */
2749 err = netif_set_real_num_tx_queues(adapter->netdev,
2750 adapter->num_tx_queues);
2751 if (err)
2752 goto err_set_queues;
2753
2754 err = netif_set_real_num_rx_queues(adapter->netdev,
2755 adapter->num_rx_queues);
2756 if (err)
2757 goto err_set_queues;
2758
9d5c8243
AK		 2759 /* From here on the code is the same as igb_up() */
2760 clear_bit(__IGB_DOWN, &adapter->state);
2761
0d1ae7f4
AD		 2762 for (i = 0; i < adapter->num_q_vectors; i++)
2763 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2764
2765 /* Clear any pending interrupts. */
2766 rd32(E1000_ICR);
844290e5
PW		 2767
2768 igb_irq_enable(adapter);
2769
d4960307
AD		 2770 /* notify VFs that reset has been completed */
2771 if (adapter->vfs_allocated_count) {
2772 u32 reg_data = rd32(E1000_CTRL_EXT);
2773 reg_data |= E1000_CTRL_EXT_PFRSTD;
2774 wr32(E1000_CTRL_EXT, reg_data);
2775 }
2776
d55b53ff
JK		 2777 netif_tx_start_all_queues(netdev);
2778
749ab2cd
YZ		 2779 if (!resuming)
2780 pm_runtime_put(&pdev->dev);
2781
25568a53
AD		 2782 /* start the watchdog. */
2783 hw->mac.get_link_status = 1;
2784 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2785
2786 return 0;
2787
0c2cc02e
AD		 2788err_set_queues:
2789 igb_free_irq(adapter);
9d5c8243
AK		 2790err_req_irq:
2791 igb_release_hw_control(adapter);
88a268c1 2792 igb_power_down_link(adapter);
9d5c8243
AK		 2793 igb_free_all_rx_resources(adapter);
2794err_setup_rx:
2795 igb_free_all_tx_resources(adapter);
2796err_setup_tx:
2797 igb_reset(adapter);
749ab2cd
YZ		 2798 if (!resuming)
2799 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2800
2801 return err;
2802}
2803
749ab2cd
YZ		 2804static int igb_open(struct net_device *netdev)
2805{
2806 return __igb_open(netdev, false);
2807}
2808
9d5c8243
AK		 2809/**
2810 * igb_close - Disables a network interface
2811 * @netdev: network interface device structure
2812 *
2813 * Returns 0, this is not allowed to fail
2814 *
2815 * The close entry point is called when an interface is de-activated
2816 * by the OS. The hardware is still under the driver's control, but
2817 * needs to be disabled. A global MAC reset is issued to stop the
2818 * hardware, and all transmit and receive resources are freed.
2819 **/
749ab2cd 2820static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2821{
2822 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2823 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2824
2825 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2826
749ab2cd
YZ		 2827 if (!suspending)
2828 pm_runtime_get_sync(&pdev->dev);
2829
2830 igb_down(adapter);
9d5c8243
AK		 2831 igb_free_irq(adapter);
2832
2833 igb_free_all_tx_resources(adapter);
2834 igb_free_all_rx_resources(adapter);
2835
749ab2cd
YZ		 2836 if (!suspending)
2837 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2838 return 0;
2839}
2840
749ab2cd
YZ		 2841static int igb_close(struct net_device *netdev)
2842{
2843 return __igb_close(netdev, false);
2844}
2845
9d5c8243
AK		 2846/**
2847 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2848 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2849 *
2850 * Return 0 on success, negative on failure
2851 **/
80785298 2852int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2853{
59d71989 2854 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2855 int size;
2856
06034649 2857 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2858
2859 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2860 if (!tx_ring->tx_buffer_info)
9d5c8243 2861 goto err;
9d5c8243
AK		 2862
2863 /* round up to nearest 4K */
85e8d004 2864 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2865 tx_ring->size = ALIGN(tx_ring->size, 4096);
2866
5536d210
AD		 2867 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2868 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2869 if (!tx_ring->desc)
2870 goto err;
2871
9d5c8243
AK		 2872 tx_ring->next_to_use = 0;
2873 tx_ring->next_to_clean = 0;
81c2fc22 2874
9d5c8243
AK		 2875 return 0;
2876
2877err:
06034649 2878 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2879 tx_ring->tx_buffer_info = NULL;
2880 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2881 return -ENOMEM;
2882}
2883
2884/**
2885 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2886 * (Descriptors) for all queues
2887 * @adapter: board private structure
2888 *
2889 * Return 0 on success, negative on failure
2890 **/
2891static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2892{
439705e1 2893 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2894 int i, err = 0;
2895
2896 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2897 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2898 if (err) {
439705e1 2899 dev_err(&pdev->dev,
9d5c8243
AK		 2900 "Allocation for Tx Queue %u failed\n", i);
2901 for (i--; i >= 0; i--)
3025a446 2902 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2903 break;
2904 }
2905 }
2906
2907 return err;
2908}
2909
2910/**
85b430b4
AD		 2911 * igb_setup_tctl - configure the transmit control registers
2912 * @adapter: Board private structure
9d5c8243 2913 **/
d7ee5b3a 2914void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2915{
9d5c8243
AK		 2916 struct e1000_hw *hw = &adapter->hw;
2917 u32 tctl;
9d5c8243 2918
85b430b4
AD		 2919 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2920 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2921
2922 /* Program the Transmit Control Register */
9d5c8243
AK		 2923 tctl = rd32(E1000_TCTL);
2924 tctl &= ~E1000_TCTL_CT;
2925 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2926 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2927
2928 igb_config_collision_dist(hw);
2929
9d5c8243
AK		 2930 /* Enable transmits */
2931 tctl |= E1000_TCTL_EN;
2932
2933 wr32(E1000_TCTL, tctl);
2934}
2935
85b430b4
AD		 2936/**
2937 * igb_configure_tx_ring - Configure transmit ring after Reset
2938 * @adapter: board private structure
2939 * @ring: tx ring to configure
2940 *
2941 * Configure a transmit ring after a reset.
2942 **/
d7ee5b3a
AD		 2943void igb_configure_tx_ring(struct igb_adapter *adapter,
2944 struct igb_ring *ring)
85b430b4
AD		 2945{
2946 struct e1000_hw *hw = &adapter->hw;
a74420e0 2947 u32 txdctl = 0;
85b430b4
AD		 2948 u64 tdba = ring->dma;
2949 int reg_idx = ring->reg_idx;
2950
2951 /* disable the queue */
a74420e0 2952 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2953 wrfl();
2954 mdelay(10);
2955
2956 wr32(E1000_TDLEN(reg_idx),
2957 ring->count * sizeof(union e1000_adv_tx_desc));
2958 wr32(E1000_TDBAL(reg_idx),
2959 tdba & 0x00000000ffffffffULL);
2960 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2961
fce99e34 2962 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2963 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2964 writel(0, ring->tail);
85b430b4
AD		 2965
2966 txdctl |= IGB_TX_PTHRESH;
2967 txdctl |= IGB_TX_HTHRESH << 8;
2968 txdctl |= IGB_TX_WTHRESH << 16;
2969
2970 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2971 wr32(E1000_TXDCTL(reg_idx), txdctl);
2972}
2973
2974/**
2975 * igb_configure_tx - Configure transmit Unit after Reset
2976 * @adapter: board private structure
2977 *
2978 * Configure the Tx unit of the MAC after a reset.
2979 **/
2980static void igb_configure_tx(struct igb_adapter *adapter)
2981{
2982 int i;
2983
2984 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2985 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2986}
2987
9d5c8243
AK		 2988/**
2989 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2990 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2991 *
2992 * Returns 0 on success, negative on failure
2993 **/
80785298 2994int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2995{
59d71989 2996 struct device *dev = rx_ring->dev;
f33005a6 2997 int size;
9d5c8243 2998
06034649 2999 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3000
3001 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3002 if (!rx_ring->rx_buffer_info)
9d5c8243 3003 goto err;
9d5c8243 3004
9d5c8243 3005 /* Round up to nearest 4K */
f33005a6 3006 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3007 rx_ring->size = ALIGN(rx_ring->size, 4096);
3008
5536d210
AD		 3009 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3010 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3011 if (!rx_ring->desc)
3012 goto err;
3013
cbc8e55f 3014 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3015 rx_ring->next_to_clean = 0;
3016 rx_ring->next_to_use = 0;
9d5c8243 3017
9d5c8243
AK		 3018 return 0;
3019
3020err:
06034649
AD		 3021 vfree(rx_ring->rx_buffer_info);
3022 rx_ring->rx_buffer_info = NULL;
f33005a6 3023 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3024 return -ENOMEM;
3025}
3026
3027/**
3028 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3029 * (Descriptors) for all queues
3030 * @adapter: board private structure
3031 *
3032 * Return 0 on success, negative on failure
3033 **/
3034static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3035{
439705e1 3036 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3037 int i, err = 0;
3038
3039 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3040 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3041 if (err) {
439705e1 3042 dev_err(&pdev->dev,
9d5c8243
AK		 3043 "Allocation for Rx Queue %u failed\n", i);
3044 for (i--; i >= 0; i--)
3025a446 3045 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3046 break;
3047 }
3048 }
3049
3050 return err;
3051}
3052
06cf2666
AD		 3053/**
3054 * igb_setup_mrqc - configure the multiple receive queue control registers
3055 * @adapter: Board private structure
3056 **/
3057static void igb_setup_mrqc(struct igb_adapter *adapter)
3058{
3059 struct e1000_hw *hw = &adapter->hw;
3060 u32 mrqc, rxcsum;
797fd4be 3061 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3062 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3063 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3064 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3065 0xFA01ACBE };
06cf2666
AD		 3066
3067 /* Fill out hash function seeds */
a57fe23e
AD		 3068 for (j = 0; j < 10; j++)
3069 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3070
a99955fc 3071 num_rx_queues = adapter->rss_queues;
06cf2666 3072
797fd4be
AD		 3073 switch (hw->mac.type) {
3074 case e1000_82575:
3075 shift = 6;
3076 break;
3077 case e1000_82576:
3078 /* 82576 supports 2 RSS queues for SR-IOV */
3079 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3080 shift = 3;
3081 num_rx_queues = 2;
06cf2666 3082 }
797fd4be
AD		 3083 break;
3084 default:
3085 break;
06cf2666
AD		 3086 }
3087
797fd4be
AD		 3088 /*
3089 * Populate the indirection table 4 entries at a time. To do this
3090 * we are generating the results for n and n+2 and then interleaving
3091 * those with the results with n+1 and n+3.
3092 */
3093 for (j = 0; j < 32; j++) {
3094 /* first pass generates n and n+2 */
3095 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3096 u32 reta = (base & 0x07800780) >> (7 - shift);
3097
3098 /* second pass generates n+1 and n+3 */
3099 base += 0x00010001 * num_rx_queues;
3100 reta |= (base & 0x07800780) << (1 + shift);
3101
3102 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3103 }
3104
3105 /*
3106 * Disable raw packet checksumming so that RSS hash is placed in
3107 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3108 * offloads as they are enabled by default
3109 */
3110 rxcsum = rd32(E1000_RXCSUM);
3111 rxcsum |= E1000_RXCSUM_PCSD;
3112
3113 if (adapter->hw.mac.type >= e1000_82576)
3114 /* Enable Receive Checksum Offload for SCTP */
3115 rxcsum |= E1000_RXCSUM_CRCOFL;
3116
3117 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3118 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3119
039454a8
AA		 3120 /* Generate RSS hash based on packet types, TCP/UDP
3121 * port numbers and/or IPv4/v6 src and dst addresses
3122 */
f96a8a0b
CW		 3123 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3124 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3125 E1000_MRQC_RSS_FIELD_IPV6 |
3126 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3127 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3128
039454a8
AA		 3129 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3130 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3131 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3132 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3133
06cf2666
AD		 3134 /* If VMDq is enabled then we set the appropriate mode for that, else
3135 * we default to RSS so that an RSS hash is calculated per packet even
3136 * if we are only using one queue */
3137 if (adapter->vfs_allocated_count) {
3138 if (hw->mac.type > e1000_82575) {
3139 /* Set the default pool for the PF's first queue */
3140 u32 vtctl = rd32(E1000_VT_CTL);
3141 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3142 E1000_VT_CTL_DISABLE_DEF_POOL);
3143 vtctl |= adapter->vfs_allocated_count <<
3144 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3145 wr32(E1000_VT_CTL, vtctl);
3146 }
a99955fc 3147 if (adapter->rss_queues > 1)
f96a8a0b 3148 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3149 else
f96a8a0b 3150 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3151 } else {
f96a8a0b
CW		 3152 if (hw->mac.type != e1000_i211)
3153 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3154 }
3155 igb_vmm_control(adapter);
3156
06cf2666
AD		 3157 wr32(E1000_MRQC, mrqc);
3158}
3159
9d5c8243
AK		 3160/**
3161 * igb_setup_rctl - configure the receive control registers
3162 * @adapter: Board private structure
3163 **/
d7ee5b3a 3164void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3165{
3166 struct e1000_hw *hw = &adapter->hw;
3167 u32 rctl;
9d5c8243
AK		 3168
3169 rctl = rd32(E1000_RCTL);
3170
3171 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3172 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3173
69d728ba 3174 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3175 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3176
87cb7e8c
AK		 3177 /*
3178 * enable stripping of CRC. It's unlikely this will break BMC
3179 * redirection as it did with e1000. Newer features require
3180 * that the HW strips the CRC.
73cd78f1 3181 */
87cb7e8c 3182 rctl |= E1000_RCTL_SECRC;
9d5c8243 3183
559e9c49 3184 /* disable store bad packets and clear size bits. */
ec54d7d6 3185 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3186
6ec43fe6
AD		 3187 /* enable LPE to prevent packets larger than max_frame_size */
3188 rctl |= E1000_RCTL_LPE;
9d5c8243 3189
952f72a8
AD		 3190 /* disable queue 0 to prevent tail write w/o re-config */
3191 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3192
e1739522
AD		 3193 /* Attention!!! For SR-IOV PF driver operations you must enable
3194 * queue drop for all VF and PF queues to prevent head of line blocking
3195 * if an un-trusted VF does not provide descriptors to hardware.
3196 */
3197 if (adapter->vfs_allocated_count) {
e1739522
AD		 3198 /* set all queue drop enable bits */
3199 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3200 }
3201
89eaefb6
BG		 3202 /* This is useful for sniffing bad packets. */
3203 if (adapter->netdev->features & NETIF_F_RXALL) {
3204 /* UPE and MPE will be handled by normal PROMISC logic
3205 * in e1000e_set_rx_mode */
3206 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3207 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3208 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3209
3210 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3211 E1000_RCTL_DPF | /* Allow filtered pause */
3212 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3213 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3214 * and that breaks VLANs.
3215 */
3216 }
3217
9d5c8243
AK		 3218 wr32(E1000_RCTL, rctl);
3219}
3220
7d5753f0
AD		 3221static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3222 int vfn)
3223{
3224 struct e1000_hw *hw = &adapter->hw;
3225 u32 vmolr;
3226
3227 /* if it isn't the PF check to see if VFs are enabled and
3228 * increase the size to support vlan tags */
3229 if (vfn < adapter->vfs_allocated_count &&
3230 adapter->vf_data[vfn].vlans_enabled)
3231 size += VLAN_TAG_SIZE;
3232
3233 vmolr = rd32(E1000_VMOLR(vfn));
3234 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3235 vmolr |= size | E1000_VMOLR_LPE;
3236 wr32(E1000_VMOLR(vfn), vmolr);
3237
3238 return 0;
3239}
3240
e1739522
AD		 3241/**
3242 * igb_rlpml_set - set maximum receive packet size
3243 * @adapter: board private structure
3244 *
3245 * Configure maximum receivable packet size.
3246 **/
3247static void igb_rlpml_set(struct igb_adapter *adapter)
3248{
153285f9 3249 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3250 struct e1000_hw *hw = &adapter->hw;
3251 u16 pf_id = adapter->vfs_allocated_count;
3252
e1739522
AD		 3253 if (pf_id) {
3254 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3255 /*
3256 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3257 * to our max jumbo frame size, in case we need to enable
3258 * jumbo frames on one of the rings later.
3259 * This will not pass over-length frames into the default
3260 * queue because it's gated by the VMOLR.RLPML.
3261 */
7d5753f0 3262 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3263 }
3264
3265 wr32(E1000_RLPML, max_frame_size);
3266}
3267
8151d294
WM		 3268static inline void igb_set_vmolr(struct igb_adapter *adapter,
3269 int vfn, bool aupe)
7d5753f0
AD		 3270{
3271 struct e1000_hw *hw = &adapter->hw;
3272 u32 vmolr;
3273
3274 /*
3275 * This register exists only on 82576 and newer so if we are older then
3276 * we should exit and do nothing
3277 */
3278 if (hw->mac.type < e1000_82576)
3279 return;
3280
3281 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3282 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3283 if (aupe)
3284 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3285 else
3286 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3287
3288 /* clear all bits that might not be set */
3289 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3290
a99955fc 3291 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3292 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3293 /*
3294 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3295 * multicast packets
3296 */
3297 if (vfn <= adapter->vfs_allocated_count)
3298 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3299
3300 wr32(E1000_VMOLR(vfn), vmolr);
3301}
3302
85b430b4
AD		 3303/**
3304 * igb_configure_rx_ring - Configure a receive ring after Reset
3305 * @adapter: board private structure
3306 * @ring: receive ring to be configured
3307 *
3308 * Configure the Rx unit of the MAC after a reset.
3309 **/
d7ee5b3a
AD		 3310void igb_configure_rx_ring(struct igb_adapter *adapter,
3311 struct igb_ring *ring)
85b430b4
AD		 3312{
3313 struct e1000_hw *hw = &adapter->hw;
3314 u64 rdba = ring->dma;
3315 int reg_idx = ring->reg_idx;
a74420e0 3316 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3317
3318 /* disable the queue */
a74420e0 3319 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3320
3321 /* Set DMA base address registers */
3322 wr32(E1000_RDBAL(reg_idx),
3323 rdba & 0x00000000ffffffffULL);
3324 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3325 wr32(E1000_RDLEN(reg_idx),
3326 ring->count * sizeof(union e1000_adv_rx_desc));
3327
3328 /* initialize head and tail */
fce99e34 3329 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3330 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3331 writel(0, ring->tail);
85b430b4 3332
952f72a8 3333 /* set descriptor configuration */
44390ca6 3334 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3335 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3336 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3337 if (hw->mac.type >= e1000_82580)
757b77e2 3338 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3339 /* Only set Drop Enable if we are supporting multiple queues */
3340 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3341 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3342
3343 wr32(E1000_SRRCTL(reg_idx), srrctl);
3344
7d5753f0 3345 /* set filtering for VMDQ pools */
8151d294 3346 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3347
85b430b4
AD		 3348 rxdctl |= IGB_RX_PTHRESH;
3349 rxdctl |= IGB_RX_HTHRESH << 8;
3350 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3351
3352 /* enable receive descriptor fetching */
3353 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3354 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3355}
3356
9d5c8243
AK		 3357/**
3358 * igb_configure_rx - Configure receive Unit after Reset
3359 * @adapter: board private structure
3360 *
3361 * Configure the Rx unit of the MAC after a reset.
3362 **/
3363static void igb_configure_rx(struct igb_adapter *adapter)
3364{
9107584e 3365 int i;
9d5c8243 3366
68d480c4
AD		 3367 /* set UTA to appropriate mode */
3368 igb_set_uta(adapter);
3369
26ad9178
AD		 3370 /* set the correct pool for the PF default MAC address in entry 0 */
3371 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3372 adapter->vfs_allocated_count);
3373
06cf2666
AD		 3374 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3375 * the Base and Length of the Rx Descriptor Ring */
3376 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3377 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3378}
3379
3380/**
3381 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3382 * @tx_ring: Tx descriptor ring for a specific queue
3383 *
3384 * Free all transmit software resources
3385 **/
68fd9910 3386void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3387{
3b644cf6 3388 igb_clean_tx_ring(tx_ring);
9d5c8243 3389
06034649
AD		 3390 vfree(tx_ring->tx_buffer_info);
3391 tx_ring->tx_buffer_info = NULL;
9d5c8243 3392
439705e1
AD		 3393 /* if not set, then don't free */
3394 if (!tx_ring->desc)
3395 return;
3396
59d71989
AD		 3397 dma_free_coherent(tx_ring->dev, tx_ring->size,
3398 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3399
3400 tx_ring->desc = NULL;
3401}
3402
3403/**
3404 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3405 * @adapter: board private structure
3406 *
3407 * Free all transmit software resources
3408 **/
3409static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3410{
3411 int i;
3412
3413 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3414 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3415}
3416
ebe42d16
AD		 3417void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3418 struct igb_tx_buffer *tx_buffer)
3419{
3420 if (tx_buffer->skb) {
3421 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3422 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3423 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3424 dma_unmap_addr(tx_buffer, dma),
3425 dma_unmap_len(tx_buffer, len),
ebe42d16 3426 DMA_TO_DEVICE);
c9f14bf3 3427 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3428 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3429 dma_unmap_addr(tx_buffer, dma),
3430 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3431 DMA_TO_DEVICE);
3432 }
3433 tx_buffer->next_to_watch = NULL;
3434 tx_buffer->skb = NULL;
c9f14bf3 3435 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3436 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3437}
3438
3439/**
3440 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3441 * @tx_ring: ring to be cleaned
3442 **/
3b644cf6 3443static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3444{
06034649 3445 struct igb_tx_buffer *buffer_info;
9d5c8243 3446 unsigned long size;
6ad4edfc 3447 u16 i;
9d5c8243 3448
06034649 3449 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3450 return;
3451 /* Free all the Tx ring sk_buffs */
3452
3453 for (i = 0; i < tx_ring->count; i++) {
06034649 3454 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3455 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3456 }
3457
dad8a3b3
JF		 3458 netdev_tx_reset_queue(txring_txq(tx_ring));
3459
06034649
AD		 3460 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3461 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3462
3463 /* Zero out the descriptor ring */
9d5c8243
AK		 3464 memset(tx_ring->desc, 0, tx_ring->size);
3465
3466 tx_ring->next_to_use = 0;
3467 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3468}
3469
3470/**
3471 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3472 * @adapter: board private structure
3473 **/
3474static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3475{
3476 int i;
3477
3478 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3479 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3480}
3481
3482/**
3483 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3484 * @rx_ring: ring to clean the resources from
3485 *
3486 * Free all receive software resources
3487 **/
68fd9910 3488void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3489{
3b644cf6 3490 igb_clean_rx_ring(rx_ring);
9d5c8243 3491
06034649
AD		 3492 vfree(rx_ring->rx_buffer_info);
3493 rx_ring->rx_buffer_info = NULL;
9d5c8243 3494
439705e1
AD		 3495 /* if not set, then don't free */
3496 if (!rx_ring->desc)
3497 return;
3498
59d71989
AD		 3499 dma_free_coherent(rx_ring->dev, rx_ring->size,
3500 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3501
3502 rx_ring->desc = NULL;
3503}
3504
3505/**
3506 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3507 * @adapter: board private structure
3508 *
3509 * Free all receive software resources
3510 **/
3511static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3512{
3513 int i;
3514
3515 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3516 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3517}
3518
3519/**
3520 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3521 * @rx_ring: ring to free buffers from
3522 **/
3b644cf6 3523static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3524{
9d5c8243 3525 unsigned long size;
c023cd88 3526 u16 i;
9d5c8243 3527
1a1c225b
AD		 3528 if (rx_ring->skb)
3529 dev_kfree_skb(rx_ring->skb);
3530 rx_ring->skb = NULL;
3531
06034649 3532 if (!rx_ring->rx_buffer_info)
9d5c8243 3533 return;
439705e1 3534
9d5c8243
AK		 3535 /* Free all the Rx ring sk_buffs */
3536 for (i = 0; i < rx_ring->count; i++) {
06034649 3537 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3538
cbc8e55f
AD		 3539 if (!buffer_info->page)
3540 continue;
3541
3542 dma_unmap_page(rx_ring->dev,
3543 buffer_info->dma,
3544 PAGE_SIZE,
3545 DMA_FROM_DEVICE);
3546 __free_page(buffer_info->page);
3547
1a1c225b 3548 buffer_info->page = NULL;
9d5c8243
AK		 3549 }
3550
06034649
AD		 3551 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3552 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3553
3554 /* Zero out the descriptor ring */
3555 memset(rx_ring->desc, 0, rx_ring->size);
3556
cbc8e55f 3557 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3558 rx_ring->next_to_clean = 0;
3559 rx_ring->next_to_use = 0;
9d5c8243
AK		 3560}
3561
3562/**
3563 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3564 * @adapter: board private structure
3565 **/
3566static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3567{
3568 int i;
3569
3570 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3571 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3572}
3573
3574/**
3575 * igb_set_mac - Change the Ethernet Address of the NIC
3576 * @netdev: network interface device structure
3577 * @p: pointer to an address structure
3578 *
3579 * Returns 0 on success, negative on failure
3580 **/
3581static int igb_set_mac(struct net_device *netdev, void *p)
3582{
3583 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3584 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3585 struct sockaddr *addr = p;
3586
3587 if (!is_valid_ether_addr(addr->sa_data))
3588 return -EADDRNOTAVAIL;
3589
3590 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3591 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3592
26ad9178
AD		 3593 /* set the correct pool for the new PF MAC address in entry 0 */
3594 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3595 adapter->vfs_allocated_count);
e1739522 3596
9d5c8243
AK		 3597 return 0;
3598}
3599
3600/**
68d480c4 3601 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3602 * @netdev: network interface device structure
3603 *
68d480c4
AD		 3604 * Writes multicast address list to the MTA hash table.
3605 * Returns: -ENOMEM on failure
3606 * 0 on no addresses written
3607 * X on writing X addresses to MTA
9d5c8243 3608 **/
68d480c4 3609static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3610{
3611 struct igb_adapter *adapter = netdev_priv(netdev);
3612 struct e1000_hw *hw = &adapter->hw;
22bedad3 3613 struct netdev_hw_addr *ha;
68d480c4 3614 u8 *mta_list;
9d5c8243
AK		 3615 int i;
3616
4cd24eaf 3617 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3618 /* nothing to program, so clear mc list */
3619 igb_update_mc_addr_list(hw, NULL, 0);
3620 igb_restore_vf_multicasts(adapter);
3621 return 0;
3622 }
9d5c8243 3623
4cd24eaf 3624 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3625 if (!mta_list)
3626 return -ENOMEM;
ff41f8dc 3627
68d480c4 3628 /* The shared function expects a packed array of only addresses. */
48e2f183 3629 i = 0;
22bedad3
JP		 3630 netdev_for_each_mc_addr(ha, netdev)
3631 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3632
68d480c4
AD		 3633 igb_update_mc_addr_list(hw, mta_list, i);
3634 kfree(mta_list);
3635
4cd24eaf 3636 return netdev_mc_count(netdev);
68d480c4
AD		 3637}
3638
3639/**
3640 * igb_write_uc_addr_list - write unicast addresses to RAR table
3641 * @netdev: network interface device structure
3642 *
3643 * Writes unicast address list to the RAR table.
3644 * Returns: -ENOMEM on failure/insufficient address space
3645 * 0 on no addresses written
3646 * X on writing X addresses to the RAR table
3647 **/
3648static int igb_write_uc_addr_list(struct net_device *netdev)
3649{
3650 struct igb_adapter *adapter = netdev_priv(netdev);
3651 struct e1000_hw *hw = &adapter->hw;
3652 unsigned int vfn = adapter->vfs_allocated_count;
3653 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3654 int count = 0;
3655
3656 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3657 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3658 return -ENOMEM;
9d5c8243 3659
32e7bfc4 3660 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3661 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3662
3663 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3664 if (!rar_entries)
3665 break;
26ad9178
AD		 3666 igb_rar_set_qsel(adapter, ha->addr,
3667 rar_entries--,
68d480c4
AD		 3668 vfn);
3669 count++;
ff41f8dc
AD		 3670 }
3671 }
3672 /* write the addresses in reverse order to avoid write combining */
3673 for (; rar_entries > 0 ; rar_entries--) {
3674 wr32(E1000_RAH(rar_entries), 0);
3675 wr32(E1000_RAL(rar_entries), 0);
3676 }
3677 wrfl();
3678
68d480c4
AD		 3679 return count;
3680}
3681
3682/**
3683 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3684 * @netdev: network interface device structure
3685 *
3686 * The set_rx_mode entry point is called whenever the unicast or multicast
3687 * address lists or the network interface flags are updated. This routine is
3688 * responsible for configuring the hardware for proper unicast, multicast,
3689 * promiscuous mode, and all-multi behavior.
3690 **/
3691static void igb_set_rx_mode(struct net_device *netdev)
3692{
3693 struct igb_adapter *adapter = netdev_priv(netdev);
3694 struct e1000_hw *hw = &adapter->hw;
3695 unsigned int vfn = adapter->vfs_allocated_count;
3696 u32 rctl, vmolr = 0;
3697 int count;
3698
3699 /* Check for Promiscuous and All Multicast modes */
3700 rctl = rd32(E1000_RCTL);
3701
3702 /* clear the effected bits */
3703 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3704
3705 if (netdev->flags & IFF_PROMISC) {
3706 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3707 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3708 } else {
3709 if (netdev->flags & IFF_ALLMULTI) {
3710 rctl |= E1000_RCTL_MPE;
3711 vmolr |= E1000_VMOLR_MPME;
3712 } else {
3713 /*
3714 * Write addresses to the MTA, if the attempt fails
25985edc 3715 * then we should just turn on promiscuous mode so
68d480c4
AD		 3716 * that we can at least receive multicast traffic
3717 */
3718 count = igb_write_mc_addr_list(netdev);
3719 if (count < 0) {
3720 rctl |= E1000_RCTL_MPE;
3721 vmolr |= E1000_VMOLR_MPME;
3722 } else if (count) {
3723 vmolr |= E1000_VMOLR_ROMPE;
3724 }
3725 }
3726 /*
3727 * Write addresses to available RAR registers, if there is not
3728 * sufficient space to store all the addresses then enable
25985edc 3729 * unicast promiscuous mode
68d480c4
AD		 3730 */
3731 count = igb_write_uc_addr_list(netdev);
3732 if (count < 0) {
3733 rctl |= E1000_RCTL_UPE;
3734 vmolr |= E1000_VMOLR_ROPE;
3735 }
3736 rctl |= E1000_RCTL_VFE;
28fc06f5 3737 }
68d480c4 3738 wr32(E1000_RCTL, rctl);
28fc06f5 3739
68d480c4
AD		 3740 /*
3741 * In order to support SR-IOV and eventually VMDq it is necessary to set
3742 * the VMOLR to enable the appropriate modes. Without this workaround
3743 * we will have issues with VLAN tag stripping not being done for frames
3744 * that are only arriving because we are the default pool
3745 */
f96a8a0b 3746 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3747 return;
9d5c8243 3748
68d480c4
AD		 3749 vmolr |= rd32(E1000_VMOLR(vfn)) &
3750 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3751 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3752 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3753}
3754
13800469
GR		 3755static void igb_check_wvbr(struct igb_adapter *adapter)
3756{
3757 struct e1000_hw *hw = &adapter->hw;
3758 u32 wvbr = 0;
3759
3760 switch (hw->mac.type) {
3761 case e1000_82576:
3762 case e1000_i350:
3763 if (!(wvbr = rd32(E1000_WVBR)))
3764 return;
3765 break;
3766 default:
3767 break;
3768 }
3769
3770 adapter->wvbr |= wvbr;
3771}
3772
3773#define IGB_STAGGERED_QUEUE_OFFSET 8
3774
3775static void igb_spoof_check(struct igb_adapter *adapter)
3776{
3777 int j;
3778
3779 if (!adapter->wvbr)
3780 return;
3781
3782 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3783 if (adapter->wvbr & (1 << j) ||
3784 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3785 dev_warn(&adapter->pdev->dev,
3786 "Spoof event(s) detected on VF %d\n", j);
3787 adapter->wvbr &=
3788 ~((1 << j) |
3789 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3790 }
3791 }
3792}
3793
9d5c8243
AK		 3794/* Need to wait a few seconds after link up to get diagnostic information from
3795 * the phy */
3796static void igb_update_phy_info(unsigned long data)
3797{
3798 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3799 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3800}
3801
4d6b725e
AD		 3802/**
3803 * igb_has_link - check shared code for link and determine up/down
3804 * @adapter: pointer to driver private info
3805 **/
3145535a 3806bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3807{
3808 struct e1000_hw *hw = &adapter->hw;
3809 bool link_active = false;
3810 s32 ret_val = 0;
3811
3812 /* get_link_status is set on LSC (link status) interrupt or
3813 * rx sequence error interrupt. get_link_status will stay
3814 * false until the e1000_check_for_link establishes link
3815 * for copper adapters ONLY
3816 */
3817 switch (hw->phy.media_type) {
3818 case e1000_media_type_copper:
3819 if (hw->mac.get_link_status) {
3820 ret_val = hw->mac.ops.check_for_link(hw);
3821 link_active = !hw->mac.get_link_status;
3822 } else {
3823 link_active = true;
3824 }
3825 break;
4d6b725e
AD		 3826 case e1000_media_type_internal_serdes:
3827 ret_val = hw->mac.ops.check_for_link(hw);
3828 link_active = hw->mac.serdes_has_link;
3829 break;
3830 default:
3831 case e1000_media_type_unknown:
3832 break;
3833 }
3834
3835 return link_active;
3836}
3837
563988dc
SA		 3838static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3839{
3840 bool ret = false;
3841 u32 ctrl_ext, thstat;
3842
f96a8a0b 3843 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3844 if (hw->mac.type == e1000_i350) {
3845 thstat = rd32(E1000_THSTAT);
3846 ctrl_ext = rd32(E1000_CTRL_EXT);
3847
3848 if ((hw->phy.media_type == e1000_media_type_copper) &&
3849 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3850 ret = !!(thstat & event);
3851 }
3852 }
3853
3854 return ret;
3855}
3856
9d5c8243
AK		 3857/**
3858 * igb_watchdog - Timer Call-back
3859 * @data: pointer to adapter cast into an unsigned long
3860 **/
3861static void igb_watchdog(unsigned long data)
3862{
3863 struct igb_adapter *adapter = (struct igb_adapter *)data;
3864 /* Do the rest outside of interrupt context */
3865 schedule_work(&adapter->watchdog_task);
3866}
3867
3868static void igb_watchdog_task(struct work_struct *work)
3869{
3870 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3871 struct igb_adapter,
3872 watchdog_task);
9d5c8243 3873 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3874 struct net_device *netdev = adapter->netdev;
563988dc 3875 u32 link;
7a6ea550 3876 int i;
9d5c8243 3877
4d6b725e 3878 link = igb_has_link(adapter);
9d5c8243 3879 if (link) {
749ab2cd
YZ		 3880 /* Cancel scheduled suspend requests. */
3881 pm_runtime_resume(netdev->dev.parent);
3882
9d5c8243
AK		 3883 if (!netif_carrier_ok(netdev)) {
3884 u32 ctrl;
330a6d6a
AD		 3885 hw->mac.ops.get_speed_and_duplex(hw,
3886 &adapter->link_speed,
3887 &adapter->link_duplex);
9d5c8243
AK		 3888
3889 ctrl = rd32(E1000_CTRL);
527d47c1 3890 /* Links status message must follow this format */
876d2d6f
JK		 3891 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3892 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3893 netdev->name,
3894 adapter->link_speed,
3895 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3896 "Full" : "Half",
3897 (ctrl & E1000_CTRL_TFCE) &&
3898 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3899 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3900 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3901
563988dc 3902 /* check for thermal sensor event */
876d2d6f
JK		 3903 if (igb_thermal_sensor_event(hw,
3904 E1000_THSTAT_LINK_THROTTLE)) {
3905 netdev_info(netdev, "The network adapter link "
3906 "speed was downshifted because it "
3907 "overheated\n");
7ef5ed1c 3908 }
563988dc 3909
d07f3e37 3910 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3911 adapter->tx_timeout_factor = 1;
3912 switch (adapter->link_speed) {
3913 case SPEED_10:
9d5c8243
AK		 3914 adapter->tx_timeout_factor = 14;
3915 break;
3916 case SPEED_100:
9d5c8243
AK		 3917 /* maybe add some timeout factor ? */
3918 break;
3919 }
3920
3921 netif_carrier_on(netdev);
9d5c8243 3922
4ae196df 3923 igb_ping_all_vfs(adapter);
17dc566c 3924 igb_check_vf_rate_limit(adapter);
4ae196df 3925
4b1a9877 3926 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3927 if (!test_bit(__IGB_DOWN, &adapter->state))
3928 mod_timer(&adapter->phy_info_timer,
3929 round_jiffies(jiffies + 2 * HZ));
3930 }
3931 } else {
3932 if (netif_carrier_ok(netdev)) {
3933 adapter->link_speed = 0;
3934 adapter->link_duplex = 0;
563988dc
SA		 3935
3936 /* check for thermal sensor event */
876d2d6f
JK		 3937 if (igb_thermal_sensor_event(hw,
3938 E1000_THSTAT_PWR_DOWN)) {
3939 netdev_err(netdev, "The network adapter was "
3940 "stopped because it overheated\n");
7ef5ed1c 3941 }
563988dc 3942
527d47c1
AD		 3943 /* Links status message must follow this format */
3944 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3945 netdev->name);
9d5c8243 3946 netif_carrier_off(netdev);
4b1a9877 3947
4ae196df
AD		 3948 igb_ping_all_vfs(adapter);
3949
4b1a9877 3950 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3951 if (!test_bit(__IGB_DOWN, &adapter->state))
3952 mod_timer(&adapter->phy_info_timer,
3953 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3954
3955 pm_schedule_suspend(netdev->dev.parent,
3956 MSEC_PER_SEC * 5);
9d5c8243
AK		 3957 }
3958 }
3959
12dcd86b
ED		 3960 spin_lock(&adapter->stats64_lock);
3961 igb_update_stats(adapter, &adapter->stats64);
3962 spin_unlock(&adapter->stats64_lock);
9d5c8243 3963
dbabb065 3964 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3965 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3966 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3967 /* We've lost link, so the controller stops DMA,
3968 * but we've got queued Tx work that's never going
3969 * to get done, so reset controller to flush Tx.
3970 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3971 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3972 adapter->tx_timeout_count++;
3973 schedule_work(&adapter->reset_task);
3974 /* return immediately since reset is imminent */
3975 return;
3976 }
9d5c8243 3977 }
9d5c8243 3978
dbabb065 3979 /* Force detection of hung controller every watchdog period */
6d095fa8 3980 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3981 }
f7ba205e 3982
9d5c8243 3983 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3984 if (adapter->msix_entries) {
047e0030 3985 u32 eics = 0;
0d1ae7f4
AD		 3986 for (i = 0; i < adapter->num_q_vectors; i++)
3987 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3988 wr32(E1000_EICS, eics);
3989 } else {
3990 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3991 }
9d5c8243 3992
13800469 3993 igb_spoof_check(adapter);
fc580751 3994 igb_ptp_rx_hang(adapter);
13800469 3995
9d5c8243
AK		 3996 /* Reset the timer */
3997 if (!test_bit(__IGB_DOWN, &adapter->state))
3998 mod_timer(&adapter->watchdog_timer,
3999 round_jiffies(jiffies + 2 * HZ));
4000}
4001
4002enum latency_range {
4003 lowest_latency = 0,
4004 low_latency = 1,
4005 bulk_latency = 2,
4006 latency_invalid = 255
4007};
4008
6eb5a7f1
AD		 4009/**
4010 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4011 *
4012 * Stores a new ITR value based on strictly on packet size. This
4013 * algorithm is less sophisticated than that used in igb_update_itr,
4014 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 4015 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 4016 * were determined based on theoretical maximum wire speed and testing
4017 * data, in order to minimize response time while increasing bulk
4018 * throughput.
4019 * This functionality is controlled by the InterruptThrottleRate module
4020 * parameter (see igb_param.c)
4021 * NOTE: This function is called only when operating in a multiqueue
4022 * receive environment.
047e0030 4023 * @q_vector: pointer to q_vector
6eb5a7f1 4024 **/
047e0030 4025static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4026{
047e0030 4027 int new_val = q_vector->itr_val;
6eb5a7f1 4028 int avg_wire_size = 0;
047e0030 4029 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4030 unsigned int packets;
9d5c8243 4031
6eb5a7f1
AD		 4032 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4033 * ints/sec - ITR timer value of 120 ticks.
4034 */
4035 if (adapter->link_speed != SPEED_1000) {
0ba82994 4036 new_val = IGB_4K_ITR;
6eb5a7f1 4037 goto set_itr_val;
9d5c8243 4038 }
047e0030 4039
0ba82994
AD		 4040 packets = q_vector->rx.total_packets;
4041 if (packets)
4042 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4043
0ba82994
AD		 4044 packets = q_vector->tx.total_packets;
4045 if (packets)
4046 avg_wire_size = max_t(u32, avg_wire_size,
4047 q_vector->tx.total_bytes / packets);
047e0030
AD		 4048
4049 /* if avg_wire_size isn't set no work was done */
4050 if (!avg_wire_size)
4051 goto clear_counts;
9d5c8243 4052
6eb5a7f1
AD		 4053 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4054 avg_wire_size += 24;
4055
4056 /* Don't starve jumbo frames */
4057 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4058
6eb5a7f1
AD		 4059 /* Give a little boost to mid-size frames */
4060 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4061 new_val = avg_wire_size / 3;
4062 else
4063 new_val = avg_wire_size / 2;
9d5c8243 4064
0ba82994
AD		 4065 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4066 if (new_val < IGB_20K_ITR &&
4067 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4068 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4069 new_val = IGB_20K_ITR;
abe1c363 4070
6eb5a7f1 4071set_itr_val:
047e0030
AD		 4072 if (new_val != q_vector->itr_val) {
4073 q_vector->itr_val = new_val;
4074 q_vector->set_itr = 1;
9d5c8243 4075 }
6eb5a7f1 4076clear_counts:
0ba82994
AD		 4077 q_vector->rx.total_bytes = 0;
4078 q_vector->rx.total_packets = 0;
4079 q_vector->tx.total_bytes = 0;
4080 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4081}
4082
4083/**
4084 * igb_update_itr - update the dynamic ITR value based on statistics
4085 * Stores a new ITR value based on packets and byte
4086 * counts during the last interrupt. The advantage of per interrupt
4087 * computation is faster updates and more accurate ITR for the current
4088 * traffic pattern. Constants in this function were computed
4089 * based on theoretical maximum wire speed and thresholds were set based
4090 * on testing data as well as attempting to minimize response time
4091 * while increasing bulk throughput.
4092 * this functionality is controlled by the InterruptThrottleRate module
4093 * parameter (see igb_param.c)
4094 * NOTE: These calculations are only valid when operating in a single-
4095 * queue environment.
0ba82994
AD		 4096 * @q_vector: pointer to q_vector
4097 * @ring_container: ring info to update the itr for
9d5c8243 4098 **/
0ba82994
AD		 4099static void igb_update_itr(struct igb_q_vector *q_vector,
4100 struct igb_ring_container *ring_container)
9d5c8243 4101{
0ba82994
AD		 4102 unsigned int packets = ring_container->total_packets;
4103 unsigned int bytes = ring_container->total_bytes;
4104 u8 itrval = ring_container->itr;
9d5c8243 4105
0ba82994 4106 /* no packets, exit with status unchanged */
9d5c8243 4107 if (packets == 0)
0ba82994 4108 return;
9d5c8243 4109
0ba82994 4110 switch (itrval) {
9d5c8243
AK		 4111 case lowest_latency:
4112 /* handle TSO and jumbo frames */
4113 if (bytes/packets > 8000)
0ba82994 4114 itrval = bulk_latency;
9d5c8243 4115 else if ((packets < 5) && (bytes > 512))
0ba82994 4116 itrval = low_latency;
9d5c8243
AK		 4117 break;
4118 case low_latency: /* 50 usec aka 20000 ints/s */
4119 if (bytes > 10000) {
4120 /* this if handles the TSO accounting */
4121 if (bytes/packets > 8000) {
0ba82994 4122 itrval = bulk_latency;
9d5c8243 4123 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4124 itrval = bulk_latency;
9d5c8243 4125 } else if ((packets > 35)) {
0ba82994 4126 itrval = lowest_latency;
9d5c8243
AK		 4127 }
4128 } else if (bytes/packets > 2000) {
0ba82994 4129 itrval = bulk_latency;
9d5c8243 4130 } else if (packets <= 2 && bytes < 512) {
0ba82994 4131 itrval = lowest_latency;
9d5c8243
AK		 4132 }
4133 break;
4134 case bulk_latency: /* 250 usec aka 4000 ints/s */
4135 if (bytes > 25000) {
4136 if (packets > 35)
0ba82994 4137 itrval = low_latency;
1e5c3d21 4138 } else if (bytes < 1500) {
0ba82994 4139 itrval = low_latency;
9d5c8243
AK		 4140 }
4141 break;
4142 }
4143
0ba82994
AD		 4144 /* clear work counters since we have the values we need */
4145 ring_container->total_bytes = 0;
4146 ring_container->total_packets = 0;
4147
4148 /* write updated itr to ring container */
4149 ring_container->itr = itrval;
9d5c8243
AK		 4150}
4151
0ba82994 4152static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4153{
0ba82994 4154 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4155 u32 new_itr = q_vector->itr_val;
0ba82994 4156 u8 current_itr = 0;
9d5c8243
AK		 4157
4158 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4159 if (adapter->link_speed != SPEED_1000) {
4160 current_itr = 0;
0ba82994 4161 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4162 goto set_itr_now;
4163 }
4164
0ba82994
AD		 4165 igb_update_itr(q_vector, &q_vector->tx);
4166 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4167
0ba82994 4168 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4169
6eb5a7f1 4170 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4171 if (current_itr == lowest_latency &&
4172 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4173 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4174 current_itr = low_latency;
4175
9d5c8243
AK		 4176 switch (current_itr) {
4177 /* counts and packets in update_itr are dependent on these numbers */
4178 case lowest_latency:
0ba82994 4179 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4180 break;
4181 case low_latency:
0ba82994 4182 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4183 break;
4184 case bulk_latency:
0ba82994 4185 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4186 break;
4187 default:
4188 break;
4189 }
4190
4191set_itr_now:
047e0030 4192 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4193 /* this attempts to bias the interrupt rate towards Bulk
4194 * by adding intermediate steps when interrupt rate is
4195 * increasing */
047e0030
AD		 4196 new_itr = new_itr > q_vector->itr_val ?
4197 max((new_itr * q_vector->itr_val) /
4198 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 4199 new_itr) :
9d5c8243
AK		 4200 new_itr;
4201 /* Don't write the value here; it resets the adapter's
4202 * internal timer, and causes us to delay far longer than
4203 * we should between interrupts. Instead, we write the ITR
4204 * value at the beginning of the next interrupt so the timing
4205 * ends up being correct.
4206 */
047e0030
AD		 4207 q_vector->itr_val = new_itr;
4208 q_vector->set_itr = 1;
9d5c8243 4209 }
9d5c8243
AK		 4210}
4211
c50b52a0
SH		 4212static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4213 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4214{
4215 struct e1000_adv_tx_context_desc *context_desc;
4216 u16 i = tx_ring->next_to_use;
4217
4218 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4219
4220 i++;
4221 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4222
4223 /* set bits to identify this as an advanced context descriptor */
4224 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4225
4226 /* For 82575, context index must be unique per ring. */
866cff06 4227 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4228 mss_l4len_idx |= tx_ring->reg_idx << 4;
4229
4230 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4231 context_desc->seqnum_seed = 0;
4232 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4233 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4234}
4235
7af40ad9
AD		 4236static int igb_tso(struct igb_ring *tx_ring,
4237 struct igb_tx_buffer *first,
4238 u8 *hdr_len)
9d5c8243 4239{
7af40ad9 4240 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4241 u32 vlan_macip_lens, type_tucmd;
4242 u32 mss_l4len_idx, l4len;
4243
ed6aa105
AD		 4244 if (skb->ip_summed != CHECKSUM_PARTIAL)
4245 return 0;
4246
7d13a7d0
AD		 4247 if (!skb_is_gso(skb))
4248 return 0;
9d5c8243
AK		 4249
4250 if (skb_header_cloned(skb)) {
7af40ad9 4251 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4252 if (err)
4253 return err;
4254 }
4255
7d13a7d0
AD		 4256 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4257 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4258
7af40ad9 4259 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4260 struct iphdr *iph = ip_hdr(skb);
4261 iph->tot_len = 0;
4262 iph->check = 0;
4263 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4264 iph->daddr, 0,
4265 IPPROTO_TCP,
4266 0);
7d13a7d0 4267 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4268 first->tx_flags |= IGB_TX_FLAGS_TSO |
4269 IGB_TX_FLAGS_CSUM |
4270 IGB_TX_FLAGS_IPV4;
8e1e8a47 4271 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4272 ipv6_hdr(skb)->payload_len = 0;
4273 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4274 &ipv6_hdr(skb)->daddr,
4275 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4276 first->tx_flags |= IGB_TX_FLAGS_TSO |
4277 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4278 }
4279
7af40ad9 4280 /* compute header lengths */
7d13a7d0
AD		 4281 l4len = tcp_hdrlen(skb);
4282 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4283
7af40ad9
AD		 4284 /* update gso size and bytecount with header size */
4285 first->gso_segs = skb_shinfo(skb)->gso_segs;
4286 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4287
9d5c8243 4288 /* MSS L4LEN IDX */
7d13a7d0
AD		 4289 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4290 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4291
7d13a7d0
AD		 4292 /* VLAN MACLEN IPLEN */
4293 vlan_macip_lens = skb_network_header_len(skb);
4294 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4295 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4296
7d13a7d0 4297 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4298
7d13a7d0 4299 return 1;
9d5c8243
AK		 4300}
4301
7af40ad9 4302static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4303{
7af40ad9 4304 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4305 u32 vlan_macip_lens = 0;
4306 u32 mss_l4len_idx = 0;
4307 u32 type_tucmd = 0;
9d5c8243 4308
7d13a7d0 4309 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4310 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4311 return;
7d13a7d0
AD		 4312 } else {
4313 u8 l4_hdr = 0;
7af40ad9 4314 switch (first->protocol) {
7d13a7d0
AD		 4315 case __constant_htons(ETH_P_IP):
4316 vlan_macip_lens |= skb_network_header_len(skb);
4317 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4318 l4_hdr = ip_hdr(skb)->protocol;
4319 break;
4320 case __constant_htons(ETH_P_IPV6):
4321 vlan_macip_lens |= skb_network_header_len(skb);
4322 l4_hdr = ipv6_hdr(skb)->nexthdr;
4323 break;
4324 default:
4325 if (unlikely(net_ratelimit())) {
4326 dev_warn(tx_ring->dev,
4327 "partial checksum but proto=%x!\n",
7af40ad9 4328 first->protocol);
fa4a7ef3 4329 }
7d13a7d0
AD		 4330 break;
4331 }
fa4a7ef3 4332
7d13a7d0
AD		 4333 switch (l4_hdr) {
4334 case IPPROTO_TCP:
4335 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4336 mss_l4len_idx = tcp_hdrlen(skb) <<
4337 E1000_ADVTXD_L4LEN_SHIFT;
4338 break;
4339 case IPPROTO_SCTP:
4340 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4341 mss_l4len_idx = sizeof(struct sctphdr) <<
4342 E1000_ADVTXD_L4LEN_SHIFT;
4343 break;
4344 case IPPROTO_UDP:
4345 mss_l4len_idx = sizeof(struct udphdr) <<
4346 E1000_ADVTXD_L4LEN_SHIFT;
4347 break;
4348 default:
4349 if (unlikely(net_ratelimit())) {
4350 dev_warn(tx_ring->dev,
4351 "partial checksum but l4 proto=%x!\n",
4352 l4_hdr);
44b0cda3 4353 }
7d13a7d0 4354 break;
9d5c8243 4355 }
7af40ad9
AD		 4356
4357 /* update TX checksum flag */
4358 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4359 }
9d5c8243 4360
7d13a7d0 4361 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4362 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4363
7d13a7d0 4364 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4365}
4366
1d9daf45
AD		 4367#define IGB_SET_FLAG(_input, _flag, _result) \
4368 ((_flag <= _result) ? \
4369 ((u32)(_input & _flag) * (_result / _flag)) : \
4370 ((u32)(_input & _flag) / (_flag / _result)))
4371
4372static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4373{
4374 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4375 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4376 E1000_ADVTXD_DCMD_DEXT |
4377 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4378
4379 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4380 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4381 (E1000_ADVTXD_DCMD_VLE));
4382
4383 /* set segmentation bits for TSO */
4384 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4385 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4386
4387 /* set timestamp bit if present */
1d9daf45
AD		 4388 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4389 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4390
1d9daf45
AD		 4391 /* insert frame checksum */
4392 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4393
4394 return cmd_type;
4395}
4396
7af40ad9
AD		 4397static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4398 union e1000_adv_tx_desc *tx_desc,
4399 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4400{
4401 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4402
1d9daf45
AD		 4403 /* 82575 requires a unique index per ring */
4404 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4405 olinfo_status |= tx_ring->reg_idx << 4;
4406
4407 /* insert L4 checksum */
1d9daf45
AD		 4408 olinfo_status |= IGB_SET_FLAG(tx_flags,
4409 IGB_TX_FLAGS_CSUM,
4410 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4411
1d9daf45
AD		 4412 /* insert IPv4 checksum */
4413 olinfo_status |= IGB_SET_FLAG(tx_flags,
4414 IGB_TX_FLAGS_IPV4,
4415 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4416
7af40ad9 4417 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4418}
4419
ebe42d16
AD		 4420/*
4421 * The largest size we can write to the descriptor is 65535. In order to
4422 * maintain a power of two alignment we have to limit ourselves to 32K.
4423 */
4424#define IGB_MAX_TXD_PWR 15
7af40ad9 4425#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4426
7af40ad9
AD		 4427static void igb_tx_map(struct igb_ring *tx_ring,
4428 struct igb_tx_buffer *first,
ebe42d16 4429 const u8 hdr_len)
9d5c8243 4430{
7af40ad9 4431 struct sk_buff *skb = first->skb;
c9f14bf3 4432 struct igb_tx_buffer *tx_buffer;
ebe42d16 4433 union e1000_adv_tx_desc *tx_desc;
80d0759e 4434 struct skb_frag_struct *frag;
ebe42d16 4435 dma_addr_t dma;
80d0759e 4436 unsigned int data_len, size;
7af40ad9 4437 u32 tx_flags = first->tx_flags;
1d9daf45 4438 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4439 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4440
4441 tx_desc = IGB_TX_DESC(tx_ring, i);
4442
80d0759e
AD		 4443 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4444
4445 size = skb_headlen(skb);
4446 data_len = skb->data_len;
ebe42d16
AD		 4447
4448 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4449
80d0759e
AD		 4450 tx_buffer = first;
4451
4452 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4453 if (dma_mapping_error(tx_ring->dev, dma))
4454 goto dma_error;
4455
4456 /* record length, and DMA address */
4457 dma_unmap_len_set(tx_buffer, len, size);
4458 dma_unmap_addr_set(tx_buffer, dma, dma);
4459
4460 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4461
ebe42d16
AD		 4462 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4463 tx_desc->read.cmd_type_len =
1d9daf45 4464 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4465
4466 i++;
4467 tx_desc++;
4468 if (i == tx_ring->count) {
4469 tx_desc = IGB_TX_DESC(tx_ring, 0);
4470 i = 0;
4471 }
80d0759e 4472 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4473
4474 dma += IGB_MAX_DATA_PER_TXD;
4475 size -= IGB_MAX_DATA_PER_TXD;
4476
ebe42d16
AD		 4477 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4478 }
4479
4480 if (likely(!data_len))
4481 break;
2bbfebe2 4482
1d9daf45 4483 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4484
65689fef 4485 i++;
ebe42d16
AD		 4486 tx_desc++;
4487 if (i == tx_ring->count) {
4488 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4489 i = 0;
ebe42d16 4490 }
80d0759e 4491 tx_desc->read.olinfo_status = 0;
65689fef 4492
9e903e08 4493 size = skb_frag_size(frag);
ebe42d16
AD		 4494 data_len -= size;
4495
4496 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4497 size, DMA_TO_DEVICE);
6366ad33 4498
c9f14bf3 4499 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4500 }
4501
ebe42d16 4502 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4503 cmd_type |= size | IGB_TXD_DCMD;
4504 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4505
80d0759e
AD		 4506 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4507
8542db05
AD		 4508 /* set the timestamp */
4509 first->time_stamp = jiffies;
4510
ebe42d16
AD		 4511 /*
4512 * Force memory writes to complete before letting h/w know there
4513 * are new descriptors to fetch. (Only applicable for weak-ordered
4514 * memory model archs, such as IA-64).
4515 *
4516 * We also need this memory barrier to make certain all of the
4517 * status bits have been updated before next_to_watch is written.
4518 */
4519 wmb();
4520
8542db05 4521 /* set next_to_watch value indicating a packet is present */
ebe42d16 4522 first->next_to_watch = tx_desc;
9d5c8243 4523
ebe42d16
AD		 4524 i++;
4525 if (i == tx_ring->count)
4526 i = 0;
6366ad33 4527
ebe42d16 4528 tx_ring->next_to_use = i;
6366ad33 4529
ebe42d16 4530 writel(i, tx_ring->tail);
6366ad33 4531
ebe42d16
AD		 4532 /* we need this if more than one processor can write to our tail
4533 * at a time, it syncronizes IO on IA64/Altix systems */
4534 mmiowb();
4535
4536 return;
4537
4538dma_error:
4539 dev_err(tx_ring->dev, "TX DMA map failed\n");
4540
4541 /* clear dma mappings for failed tx_buffer_info map */
4542 for (;;) {
c9f14bf3
AD		 4543 tx_buffer = &tx_ring->tx_buffer_info[i];
4544 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4545 if (tx_buffer == first)
ebe42d16 4546 break;
a77ff709
NN		 4547 if (i == 0)
4548 i = tx_ring->count;
6366ad33 4549 i--;
6366ad33
AD		 4550 }
4551
9d5c8243 4552 tx_ring->next_to_use = i;
9d5c8243
AK		 4553}
4554
6ad4edfc 4555static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4556{
e694e964
AD		 4557 struct net_device *netdev = tx_ring->netdev;
4558
661086df 4559 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4560
9d5c8243
AK		 4561 /* Herbert's original patch had:
4562 * smp_mb__after_netif_stop_queue();
4563 * but since that doesn't exist yet, just open code it. */
4564 smp_mb();
4565
4566 /* We need to check again in a case another CPU has just
4567 * made room available. */
c493ea45 4568 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4569 return -EBUSY;
4570
4571 /* A reprieve! */
661086df 4572 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4573
4574 u64_stats_update_begin(&tx_ring->tx_syncp2);
4575 tx_ring->tx_stats.restart_queue2++;
4576 u64_stats_update_end(&tx_ring->tx_syncp2);
4577
9d5c8243
AK		 4578 return 0;
4579}
4580
6ad4edfc 4581static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4582{
c493ea45 4583 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4584 return 0;
e694e964 4585 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4586}
4587
cd392f5c
AD		 4588netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4589 struct igb_ring *tx_ring)
9d5c8243 4590{
1f6e8178 4591 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4592 struct igb_tx_buffer *first;
ebe42d16 4593 int tso;
91d4ee33 4594 u32 tx_flags = 0;
31f6adbb 4595 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4596 u8 hdr_len = 0;
9d5c8243 4597
9d5c8243
AK		 4598 /* need: 1 descriptor per page,
4599 * + 2 desc gap to keep tail from touching head,
4600 * + 1 desc for skb->data,
4601 * + 1 desc for context descriptor,
4602 * otherwise try next time */
e694e964 4603 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4604 /* this is a hard error */
9d5c8243
AK		 4605 return NETDEV_TX_BUSY;
4606 }
33af6bcc 4607
7af40ad9
AD		 4608 /* record the location of the first descriptor for this packet */
4609 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4610 first->skb = skb;
4611 first->bytecount = skb->len;
4612 first->gso_segs = 1;
4613
b66e2397
MV		 4614 skb_tx_timestamp(skb);
4615
1f6e8178
MV		 4616 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4617 !(adapter->ptp_tx_skb))) {
2244d07b 4618 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4619 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4620
4621 adapter->ptp_tx_skb = skb_get(skb);
428f1f71 4622 adapter->ptp_tx_start = jiffies;
1f6e8178
MV		 4623 if (adapter->hw.mac.type == e1000_82576)
4624 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4625 }
9d5c8243 4626
eab6d18d 4627 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4628 tx_flags |= IGB_TX_FLAGS_VLAN;
4629 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4630 }
4631
7af40ad9
AD		 4632 /* record initial flags and protocol */
4633 first->tx_flags = tx_flags;
4634 first->protocol = protocol;
cdfd01fc 4635
7af40ad9
AD		 4636 tso = igb_tso(tx_ring, first, &hdr_len);
4637 if (tso < 0)
7d13a7d0 4638 goto out_drop;
7af40ad9
AD		 4639 else if (!tso)
4640 igb_tx_csum(tx_ring, first);
9d5c8243 4641
7af40ad9 4642 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4643
4644 /* Make sure there is space in the ring for the next send. */
e694e964 4645 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4646
9d5c8243 4647 return NETDEV_TX_OK;
7d13a7d0
AD		 4648
4649out_drop:
7af40ad9
AD		 4650 igb_unmap_and_free_tx_resource(tx_ring, first);
4651
7d13a7d0 4652 return NETDEV_TX_OK;
9d5c8243
AK		 4653}
4654
1cc3bd87
AD		 4655static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4656 struct sk_buff *skb)
4657{
4658 unsigned int r_idx = skb->queue_mapping;
4659
4660 if (r_idx >= adapter->num_tx_queues)
4661 r_idx = r_idx % adapter->num_tx_queues;
4662
4663 return adapter->tx_ring[r_idx];
4664}
4665
cd392f5c
AD		 4666static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4667 struct net_device *netdev)
9d5c8243
AK		 4668{
4669 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4670
4671 if (test_bit(__IGB_DOWN, &adapter->state)) {
4672 dev_kfree_skb_any(skb);
4673 return NETDEV_TX_OK;
4674 }
4675
4676 if (skb->len <= 0) {
4677 dev_kfree_skb_any(skb);
4678 return NETDEV_TX_OK;
4679 }
4680
1cc3bd87
AD		 4681 /*
4682 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4683 * in order to meet this minimum size requirement.
4684 */
ea5ceeab
TD		 4685 if (unlikely(skb->len < 17)) {
4686 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4687 return NETDEV_TX_OK;
4688 skb->len = 17;
ea5ceeab 4689 skb_set_tail_pointer(skb, 17);
1cc3bd87 4690 }
9d5c8243 4691
1cc3bd87 4692 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4693}
4694
4695/**
4696 * igb_tx_timeout - Respond to a Tx Hang
4697 * @netdev: network interface device structure
4698 **/
4699static void igb_tx_timeout(struct net_device *netdev)
4700{
4701 struct igb_adapter *adapter = netdev_priv(netdev);
4702 struct e1000_hw *hw = &adapter->hw;
4703
4704 /* Do the reset outside of interrupt context */
4705 adapter->tx_timeout_count++;
f7ba205e 4706
06218a8d 4707 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4708 hw->dev_spec._82575.global_device_reset = true;
4709
9d5c8243 4710 schedule_work(&adapter->reset_task);
265de409
AD		 4711 wr32(E1000_EICS,
4712 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4713}
4714
4715static void igb_reset_task(struct work_struct *work)
4716{
4717 struct igb_adapter *adapter;
4718 adapter = container_of(work, struct igb_adapter, reset_task);
4719
c97ec42a
TI		 4720 igb_dump(adapter);
4721 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4722 igb_reinit_locked(adapter);
4723}
4724
4725/**
12dcd86b 4726 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4727 * @netdev: network interface device structure
12dcd86b 4728 * @stats: rtnl_link_stats64 pointer
9d5c8243 4729 *
9d5c8243 4730 **/
12dcd86b
ED		 4731static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4732 struct rtnl_link_stats64 *stats)
9d5c8243 4733{
12dcd86b
ED		 4734 struct igb_adapter *adapter = netdev_priv(netdev);
4735
4736 spin_lock(&adapter->stats64_lock);
4737 igb_update_stats(adapter, &adapter->stats64);
4738 memcpy(stats, &adapter->stats64, sizeof(*stats));
4739 spin_unlock(&adapter->stats64_lock);
4740
4741 return stats;
9d5c8243
AK		 4742}
4743
4744/**
4745 * igb_change_mtu - Change the Maximum Transfer Unit
4746 * @netdev: network interface device structure
4747 * @new_mtu: new value for maximum frame size
4748 *
4749 * Returns 0 on success, negative on failure
4750 **/
4751static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4752{
4753 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4754 struct pci_dev *pdev = adapter->pdev;
153285f9 4755 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4756
c809d227 4757 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4758 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4759 return -EINVAL;
4760 }
4761
153285f9 4762#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4763 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4764 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4765 return -EINVAL;
4766 }
4767
4768 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4769 msleep(1);
73cd78f1 4770
9d5c8243
AK		 4771 /* igb_down has a dependency on max_frame_size */
4772 adapter->max_frame_size = max_frame;
559e9c49 4773
4c844851
AD		 4774 if (netif_running(netdev))
4775 igb_down(adapter);
9d5c8243 4776
090b1795 4777 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4778 netdev->mtu, new_mtu);
4779 netdev->mtu = new_mtu;
4780
4781 if (netif_running(netdev))
4782 igb_up(adapter);
4783 else
4784 igb_reset(adapter);
4785
4786 clear_bit(__IGB_RESETTING, &adapter->state);
4787
4788 return 0;
4789}
4790
4791/**
4792 * igb_update_stats - Update the board statistics counters
4793 * @adapter: board private structure
4794 **/
4795
12dcd86b
ED		 4796void igb_update_stats(struct igb_adapter *adapter,
4797 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4798{
4799 struct e1000_hw *hw = &adapter->hw;
4800 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4801 u32 reg, mpc;
9d5c8243 4802 u16 phy_tmp;
3f9c0164
AD		 4803 int i;
4804 u64 bytes, packets;
12dcd86b
ED		 4805 unsigned int start;
4806 u64 _bytes, _packets;
9d5c8243
AK		 4807
4808#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4809
4810 /*
4811 * Prevent stats update while adapter is being reset, or if the pci
4812 * connection is down.
4813 */
4814 if (adapter->link_speed == 0)
4815 return;
4816 if (pci_channel_offline(pdev))
4817 return;
4818
3f9c0164
AD		 4819 bytes = 0;
4820 packets = 0;
4821 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4822 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4823 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4824
ae1c07a6
AD		 4825 if (rqdpc) {
4826 ring->rx_stats.drops += rqdpc;
4827 net_stats->rx_fifo_errors += rqdpc;
4828 }
12dcd86b
ED		 4829
4830 do {
4831 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4832 _bytes = ring->rx_stats.bytes;
4833 _packets = ring->rx_stats.packets;
4834 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4835 bytes += _bytes;
4836 packets += _packets;
3f9c0164
AD		 4837 }
4838
128e45eb
AD		 4839 net_stats->rx_bytes = bytes;
4840 net_stats->rx_packets = packets;
3f9c0164
AD		 4841
4842 bytes = 0;
4843 packets = 0;
4844 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4845 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4846 do {
4847 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4848 _bytes = ring->tx_stats.bytes;
4849 _packets = ring->tx_stats.packets;
4850 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4851 bytes += _bytes;
4852 packets += _packets;
3f9c0164 4853 }
128e45eb
AD		 4854 net_stats->tx_bytes = bytes;
4855 net_stats->tx_packets = packets;
3f9c0164
AD		 4856
4857 /* read stats registers */
9d5c8243
AK		 4858 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4859 adapter->stats.gprc += rd32(E1000_GPRC);
4860 adapter->stats.gorc += rd32(E1000_GORCL);
4861 rd32(E1000_GORCH); /* clear GORCL */
4862 adapter->stats.bprc += rd32(E1000_BPRC);
4863 adapter->stats.mprc += rd32(E1000_MPRC);
4864 adapter->stats.roc += rd32(E1000_ROC);
4865
4866 adapter->stats.prc64 += rd32(E1000_PRC64);
4867 adapter->stats.prc127 += rd32(E1000_PRC127);
4868 adapter->stats.prc255 += rd32(E1000_PRC255);
4869 adapter->stats.prc511 += rd32(E1000_PRC511);
4870 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4871 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4872 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4873 adapter->stats.sec += rd32(E1000_SEC);
4874
fa3d9a6d
MW		 4875 mpc = rd32(E1000_MPC);
4876 adapter->stats.mpc += mpc;
4877 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4878 adapter->stats.scc += rd32(E1000_SCC);
4879 adapter->stats.ecol += rd32(E1000_ECOL);
4880 adapter->stats.mcc += rd32(E1000_MCC);
4881 adapter->stats.latecol += rd32(E1000_LATECOL);
4882 adapter->stats.dc += rd32(E1000_DC);
4883 adapter->stats.rlec += rd32(E1000_RLEC);
4884 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4885 adapter->stats.xontxc += rd32(E1000_XONTXC);
4886 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4887 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4888 adapter->stats.fcruc += rd32(E1000_FCRUC);
4889 adapter->stats.gptc += rd32(E1000_GPTC);
4890 adapter->stats.gotc += rd32(E1000_GOTCL);
4891 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4892 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4893 adapter->stats.ruc += rd32(E1000_RUC);
4894 adapter->stats.rfc += rd32(E1000_RFC);
4895 adapter->stats.rjc += rd32(E1000_RJC);
4896 adapter->stats.tor += rd32(E1000_TORH);
4897 adapter->stats.tot += rd32(E1000_TOTH);
4898 adapter->stats.tpr += rd32(E1000_TPR);
4899
4900 adapter->stats.ptc64 += rd32(E1000_PTC64);
4901 adapter->stats.ptc127 += rd32(E1000_PTC127);
4902 adapter->stats.ptc255 += rd32(E1000_PTC255);
4903 adapter->stats.ptc511 += rd32(E1000_PTC511);
4904 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4905 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4906
4907 adapter->stats.mptc += rd32(E1000_MPTC);
4908 adapter->stats.bptc += rd32(E1000_BPTC);
4909
2d0b0f69
NN		 4910 adapter->stats.tpt += rd32(E1000_TPT);
4911 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4912
4913 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4914 /* read internal phy specific stats */
4915 reg = rd32(E1000_CTRL_EXT);
4916 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4917 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4918
4919 /* this stat has invalid values on i210/i211 */
4920 if ((hw->mac.type != e1000_i210) &&
4921 (hw->mac.type != e1000_i211))
4922 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4923 }
4924
9d5c8243
AK		 4925 adapter->stats.tsctc += rd32(E1000_TSCTC);
4926 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4927
4928 adapter->stats.iac += rd32(E1000_IAC);
4929 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4930 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4931 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4932 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4933 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4934 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4935 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4936 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4937
4938 /* Fill out the OS statistics structure */
128e45eb
AD		 4939 net_stats->multicast = adapter->stats.mprc;
4940 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4941
4942 /* Rx Errors */
4943
4944 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4945 * our own version based on RUC and ROC */
128e45eb 4946 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4947 adapter->stats.crcerrs + adapter->stats.algnerrc +
4948 adapter->stats.ruc + adapter->stats.roc +
4949 adapter->stats.cexterr;
128e45eb
AD		 4950 net_stats->rx_length_errors = adapter->stats.ruc +
4951 adapter->stats.roc;
4952 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4953 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4954 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4955
4956 /* Tx Errors */
128e45eb
AD		 4957 net_stats->tx_errors = adapter->stats.ecol +
4958 adapter->stats.latecol;
4959 net_stats->tx_aborted_errors = adapter->stats.ecol;
4960 net_stats->tx_window_errors = adapter->stats.latecol;
4961 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4962
4963 /* Tx Dropped needs to be maintained elsewhere */
4964
4965 /* Phy Stats */
4966 if (hw->phy.media_type == e1000_media_type_copper) {
4967 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4968 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4969 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4970 adapter->phy_stats.idle_errors += phy_tmp;
4971 }
4972 }
4973
4974 /* Management Stats */
4975 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4976 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4977 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4978
4979 /* OS2BMC Stats */
4980 reg = rd32(E1000_MANC);
4981 if (reg & E1000_MANC_EN_BMC2OS) {
4982 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4983 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4984 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4985 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4986 }
9d5c8243
AK		 4987}
4988
9d5c8243
AK		 4989static irqreturn_t igb_msix_other(int irq, void *data)
4990{
047e0030 4991 struct igb_adapter *adapter = data;
9d5c8243 4992 struct e1000_hw *hw = &adapter->hw;
844290e5 4993 u32 icr = rd32(E1000_ICR);
844290e5 4994 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4995
7f081d40
AD		 4996 if (icr & E1000_ICR_DRSTA)
4997 schedule_work(&adapter->reset_task);
4998
047e0030 4999 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5000 /* HW is reporting DMA is out of sync */
5001 adapter->stats.doosync++;
13800469
GR		 5002 /* The DMA Out of Sync is also indication of a spoof event
5003 * in IOV mode. Check the Wrong VM Behavior register to
5004 * see if it is really a spoof event. */
5005 igb_check_wvbr(adapter);
dda0e083 5006 }
eebbbdba 5007
4ae196df
AD		 5008 /* Check for a mailbox event */
5009 if (icr & E1000_ICR_VMMB)
5010 igb_msg_task(adapter);
5011
5012 if (icr & E1000_ICR_LSC) {
5013 hw->mac.get_link_status = 1;
5014 /* guard against interrupt when we're going down */
5015 if (!test_bit(__IGB_DOWN, &adapter->state))
5016 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5017 }
5018
1f6e8178
MV		 5019 if (icr & E1000_ICR_TS) {
5020 u32 tsicr = rd32(E1000_TSICR);
5021
5022 if (tsicr & E1000_TSICR_TXTS) {
5023 /* acknowledge the interrupt */
5024 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5025 /* retrieve hardware timestamp */
5026 schedule_work(&adapter->ptp_tx_work);
5027 }
5028 }
1f6e8178 5029
844290e5 5030 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5031
5032 return IRQ_HANDLED;
5033}
5034
047e0030 5035static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5036{
26b39276 5037 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5038 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5039
047e0030
AD		 5040 if (!q_vector->set_itr)
5041 return;
73cd78f1 5042
047e0030
AD		 5043 if (!itr_val)
5044 itr_val = 0x4;
661086df 5045
26b39276
AD		 5046 if (adapter->hw.mac.type == e1000_82575)
5047 itr_val |= itr_val << 16;
661086df 5048 else
0ba82994 5049 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5050
047e0030
AD		 5051 writel(itr_val, q_vector->itr_register);
5052 q_vector->set_itr = 0;
6eb5a7f1
AD		 5053}
5054
047e0030 5055static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5056{
047e0030 5057 struct igb_q_vector *q_vector = data;
9d5c8243 5058
047e0030
AD		 5059 /* Write the ITR value calculated from the previous interrupt. */
5060 igb_write_itr(q_vector);
9d5c8243 5061
047e0030 5062 napi_schedule(&q_vector->napi);
844290e5 5063
047e0030 5064 return IRQ_HANDLED;
fe4506b6
JC		 5065}
5066
421e02f0 5067#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5068static void igb_update_tx_dca(struct igb_adapter *adapter,
5069 struct igb_ring *tx_ring,
5070 int cpu)
5071{
5072 struct e1000_hw *hw = &adapter->hw;
5073 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5074
5075 if (hw->mac.type != e1000_82575)
5076 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5077
5078 /*
5079 * We can enable relaxed ordering for reads, but not writes when
5080 * DCA is enabled. This is due to a known issue in some chipsets
5081 * which will cause the DCA tag to be cleared.
5082 */
5083 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5084 E1000_DCA_TXCTRL_DATA_RRO_EN |
5085 E1000_DCA_TXCTRL_DESC_DCA_EN;
5086
5087 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5088}
5089
5090static void igb_update_rx_dca(struct igb_adapter *adapter,
5091 struct igb_ring *rx_ring,
5092 int cpu)
5093{
5094 struct e1000_hw *hw = &adapter->hw;
5095 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5096
5097 if (hw->mac.type != e1000_82575)
5098 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5099
5100 /*
5101 * We can enable relaxed ordering for reads, but not writes when
5102 * DCA is enabled. This is due to a known issue in some chipsets
5103 * which will cause the DCA tag to be cleared.
5104 */
5105 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5106 E1000_DCA_RXCTRL_DESC_DCA_EN;
5107
5108 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5109}
5110
047e0030 5111static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5112{
047e0030 5113 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5114 int cpu = get_cpu();
fe4506b6 5115
047e0030
AD		 5116 if (q_vector->cpu == cpu)
5117 goto out_no_update;
5118
6a05004a
AD		 5119 if (q_vector->tx.ring)
5120 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5121
5122 if (q_vector->rx.ring)
5123 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5124
047e0030
AD		 5125 q_vector->cpu = cpu;
5126out_no_update:
fe4506b6
JC		 5127 put_cpu();
5128}
5129
5130static void igb_setup_dca(struct igb_adapter *adapter)
5131{
7e0e99ef 5132 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5133 int i;
5134
7dfc16fa 5135 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5136 return;
5137
7e0e99ef
AD		 5138 /* Always use CB2 mode, difference is masked in the CB driver. */
5139 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5140
047e0030 5141 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5142 adapter->q_vector[i]->cpu = -1;
5143 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5144 }
5145}
5146
5147static int __igb_notify_dca(struct device *dev, void *data)
5148{
5149 struct net_device *netdev = dev_get_drvdata(dev);
5150 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5151 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5152 struct e1000_hw *hw = &adapter->hw;
5153 unsigned long event = *(unsigned long *)data;
5154
5155 switch (event) {
5156 case DCA_PROVIDER_ADD:
5157 /* if already enabled, don't do it again */
7dfc16fa 5158 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5159 break;
fe4506b6 5160 if (dca_add_requester(dev) == 0) {
bbd98fe4 5161 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5162 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5163 igb_setup_dca(adapter);
5164 break;
5165 }
5166 /* Fall Through since DCA is disabled. */
5167 case DCA_PROVIDER_REMOVE:
7dfc16fa 5168 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5169 /* without this a class_device is left
047e0030 5170 * hanging around in the sysfs model */
fe4506b6 5171 dca_remove_requester(dev);
090b1795 5172 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5173 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5174 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5175 }
5176 break;
5177 }
bbd98fe4 5178
fe4506b6 5179 return 0;
9d5c8243
AK		 5180}
5181
fe4506b6
JC		 5182static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5183 void *p)
5184{
5185 int ret_val;
5186
5187 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5188 __igb_notify_dca);
5189
5190 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5191}
421e02f0 5192#endif /* CONFIG_IGB_DCA */
9d5c8243 5193
0224d663
GR		 5194#ifdef CONFIG_PCI_IOV
5195static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5196{
5197 unsigned char mac_addr[ETH_ALEN];
0224d663 5198
5ac6f91d 5199 eth_zero_addr(mac_addr);
0224d663
GR		 5200 igb_set_vf_mac(adapter, vf, mac_addr);
5201
f557147c 5202 return 0;
0224d663
GR		 5203}
5204
f557147c 5205static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 5206{
0224d663 5207 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 5208 struct pci_dev *vfdev;
5209 int dev_id;
0224d663
GR		 5210
5211 switch (adapter->hw.mac.type) {
5212 case e1000_82576:
f557147c 5213 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 5214 break;
5215 case e1000_i350:
f557147c 5216 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 5217 break;
5218 default:
f557147c 5219 return false;
0224d663
GR		 5220 }
5221
f557147c
SA		 5222 /* loop through all the VFs to see if we own any that are assigned */
5223 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5224 while (vfdev) {
5225 /* if we don't own it we don't care */
5226 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5227 /* if it is assigned we cannot release it */
5228 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5229 return true;
5230 }
f557147c
SA		 5231
5232 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5233 }
f557147c 5234
0224d663
GR		 5235 return false;
5236}
5237
5238#endif
4ae196df
AD		 5239static void igb_ping_all_vfs(struct igb_adapter *adapter)
5240{
5241 struct e1000_hw *hw = &adapter->hw;
5242 u32 ping;
5243 int i;
5244
5245 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5246 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5247 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5248 ping |= E1000_VT_MSGTYPE_CTS;
5249 igb_write_mbx(hw, &ping, 1, i);
5250 }
5251}
5252
7d5753f0
AD		 5253static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5254{
5255 struct e1000_hw *hw = &adapter->hw;
5256 u32 vmolr = rd32(E1000_VMOLR(vf));
5257 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5258
d85b9004 5259 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5260 IGB_VF_FLAG_MULTI_PROMISC);
5261 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5262
5263 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5264 vmolr |= E1000_VMOLR_MPME;
d85b9004 5265 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5266 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5267 } else {
5268 /*
5269 * if we have hashes and we are clearing a multicast promisc
5270 * flag we need to write the hashes to the MTA as this step
5271 * was previously skipped
5272 */
5273 if (vf_data->num_vf_mc_hashes > 30) {
5274 vmolr |= E1000_VMOLR_MPME;
5275 } else if (vf_data->num_vf_mc_hashes) {
5276 int j;
5277 vmolr |= E1000_VMOLR_ROMPE;
5278 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5279 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5280 }
5281 }
5282
5283 wr32(E1000_VMOLR(vf), vmolr);
5284
5285 /* there are flags left unprocessed, likely not supported */
5286 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5287 return -EINVAL;
5288
5289 return 0;
5290
5291}
5292
4ae196df
AD		 5293static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5294 u32 *msgbuf, u32 vf)
5295{
5296 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5297 u16 *hash_list = (u16 *)&msgbuf[1];
5298 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5299 int i;
5300
7d5753f0 5301 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5302 * to this VF for later use to restore when the PF multi cast
5303 * list changes
5304 */
5305 vf_data->num_vf_mc_hashes = n;
5306
7d5753f0
AD		 5307 /* only up to 30 hash values supported */
5308 if (n > 30)
5309 n = 30;
5310
5311 /* store the hashes for later use */
4ae196df 5312 for (i = 0; i < n; i++)
a419aef8 5313 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5314
5315 /* Flush and reset the mta with the new values */
ff41f8dc 5316 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5317
5318 return 0;
5319}
5320
5321static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5322{
5323 struct e1000_hw *hw = &adapter->hw;
5324 struct vf_data_storage *vf_data;
5325 int i, j;
5326
5327 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5328 u32 vmolr = rd32(E1000_VMOLR(i));
5329 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5330
4ae196df 5331 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5332
5333 if ((vf_data->num_vf_mc_hashes > 30) ||
5334 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5335 vmolr |= E1000_VMOLR_MPME;
5336 } else if (vf_data->num_vf_mc_hashes) {
5337 vmolr |= E1000_VMOLR_ROMPE;
5338 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5339 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5340 }
5341 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5342 }
5343}
5344
5345static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5346{
5347 struct e1000_hw *hw = &adapter->hw;
5348 u32 pool_mask, reg, vid;
5349 int i;
5350
5351 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5352
5353 /* Find the vlan filter for this id */
5354 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5355 reg = rd32(E1000_VLVF(i));
5356
5357 /* remove the vf from the pool */
5358 reg &= ~pool_mask;
5359
5360 /* if pool is empty then remove entry from vfta */
5361 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5362 (reg & E1000_VLVF_VLANID_ENABLE)) {
5363 reg = 0;
5364 vid = reg & E1000_VLVF_VLANID_MASK;
5365 igb_vfta_set(hw, vid, false);
5366 }
5367
5368 wr32(E1000_VLVF(i), reg);
5369 }
ae641bdc
AD		 5370
5371 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5372}
5373
5374static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5375{
5376 struct e1000_hw *hw = &adapter->hw;
5377 u32 reg, i;
5378
51466239
AD		 5379 /* The vlvf table only exists on 82576 hardware and newer */
5380 if (hw->mac.type < e1000_82576)
5381 return -1;
5382
5383 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5384 if (!adapter->vfs_allocated_count)
5385 return -1;
5386
5387 /* Find the vlan filter for this id */
5388 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5389 reg = rd32(E1000_VLVF(i));
5390 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5391 vid == (reg & E1000_VLVF_VLANID_MASK))
5392 break;
5393 }
5394
5395 if (add) {
5396 if (i == E1000_VLVF_ARRAY_SIZE) {
5397 /* Did not find a matching VLAN ID entry that was
5398 * enabled. Search for a free filter entry, i.e.
5399 * one without the enable bit set
5400 */
5401 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5402 reg = rd32(E1000_VLVF(i));
5403 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5404 break;
5405 }
5406 }
5407 if (i < E1000_VLVF_ARRAY_SIZE) {
5408 /* Found an enabled/available entry */
5409 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5410
5411 /* if !enabled we need to set this up in vfta */
5412 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5413 /* add VID to filter table */
5414 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5415 reg |= E1000_VLVF_VLANID_ENABLE;
5416 }
cad6d05f
AD		 5417 reg &= ~E1000_VLVF_VLANID_MASK;
5418 reg |= vid;
4ae196df 5419 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5420
5421 /* do not modify RLPML for PF devices */
5422 if (vf >= adapter->vfs_allocated_count)
5423 return 0;
5424
5425 if (!adapter->vf_data[vf].vlans_enabled) {
5426 u32 size;
5427 reg = rd32(E1000_VMOLR(vf));
5428 size = reg & E1000_VMOLR_RLPML_MASK;
5429 size += 4;
5430 reg &= ~E1000_VMOLR_RLPML_MASK;
5431 reg |= size;
5432 wr32(E1000_VMOLR(vf), reg);
5433 }
ae641bdc 5434
51466239 5435 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5436 }
5437 } else {
5438 if (i < E1000_VLVF_ARRAY_SIZE) {
5439 /* remove vf from the pool */
5440 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5441 /* if pool is empty then remove entry from vfta */
5442 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5443 reg = 0;
5444 igb_vfta_set(hw, vid, false);
5445 }
5446 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5447
5448 /* do not modify RLPML for PF devices */
5449 if (vf >= adapter->vfs_allocated_count)
5450 return 0;
5451
5452 adapter->vf_data[vf].vlans_enabled--;
5453 if (!adapter->vf_data[vf].vlans_enabled) {
5454 u32 size;
5455 reg = rd32(E1000_VMOLR(vf));
5456 size = reg & E1000_VMOLR_RLPML_MASK;
5457 size -= 4;
5458 reg &= ~E1000_VMOLR_RLPML_MASK;
5459 reg |= size;
5460 wr32(E1000_VMOLR(vf), reg);
5461 }
4ae196df
AD		 5462 }
5463 }
8151d294
WM		 5464 return 0;
5465}
5466
5467static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5468{
5469 struct e1000_hw *hw = &adapter->hw;
5470
5471 if (vid)
5472 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5473 else
5474 wr32(E1000_VMVIR(vf), 0);
5475}
5476
5477static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5478 int vf, u16 vlan, u8 qos)
5479{
5480 int err = 0;
5481 struct igb_adapter *adapter = netdev_priv(netdev);
5482
5483 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5484 return -EINVAL;
5485 if (vlan || qos) {
5486 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5487 if (err)
5488 goto out;
5489 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5490 igb_set_vmolr(adapter, vf, !vlan);
5491 adapter->vf_data[vf].pf_vlan = vlan;
5492 adapter->vf_data[vf].pf_qos = qos;
5493 dev_info(&adapter->pdev->dev,
5494 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5495 if (test_bit(__IGB_DOWN, &adapter->state)) {
5496 dev_warn(&adapter->pdev->dev,
5497 "The VF VLAN has been set,"
5498 " but the PF device is not up.\n");
5499 dev_warn(&adapter->pdev->dev,
5500 "Bring the PF device up before"
5501 " attempting to use the VF device.\n");
5502 }
5503 } else {
5504 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5505 false, vf);
5506 igb_set_vmvir(adapter, vlan, vf);
5507 igb_set_vmolr(adapter, vf, true);
5508 adapter->vf_data[vf].pf_vlan = 0;
5509 adapter->vf_data[vf].pf_qos = 0;
5510 }
5511out:
5512 return err;
4ae196df
AD		 5513}
5514
5515static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5516{
5517 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5518 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5519
5520 return igb_vlvf_set(adapter, vid, add, vf);
5521}
5522
f2ca0dbe 5523static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5524{
8fa7e0f7
GR		 5525 /* clear flags - except flag that indicates PF has set the MAC */
5526 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5527 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5528
5529 /* reset offloads to defaults */
8151d294 5530 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5531
5532 /* reset vlans for device */
5533 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5534 if (adapter->vf_data[vf].pf_vlan)
5535 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5536 adapter->vf_data[vf].pf_vlan,
5537 adapter->vf_data[vf].pf_qos);
5538 else
5539 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5540
5541 /* reset multicast table array for vf */
5542 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5543
5544 /* Flush and reset the mta with the new values */
ff41f8dc 5545 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5546}
5547
f2ca0dbe
AD		 5548static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5549{
5550 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5551
5ac6f91d 5552 /* clear mac address as we were hotplug removed/added */
8151d294 5553 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5554 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5555
5556 /* process remaining reset events */
5557 igb_vf_reset(adapter, vf);
5558}
5559
5560static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5561{
5562 struct e1000_hw *hw = &adapter->hw;
5563 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5564 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5565 u32 reg, msgbuf[3];
5566 u8 *addr = (u8 *)(&msgbuf[1]);
5567
5568 /* process all the same items cleared in a function level reset */
f2ca0dbe 5569 igb_vf_reset(adapter, vf);
4ae196df
AD		 5570
5571 /* set vf mac address */
26ad9178 5572 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5573
5574 /* enable transmit and receive for vf */
5575 reg = rd32(E1000_VFTE);
5576 wr32(E1000_VFTE, reg | (1 << vf));
5577 reg = rd32(E1000_VFRE);
5578 wr32(E1000_VFRE, reg | (1 << vf));
5579
8fa7e0f7 5580 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5581
5582 /* reply to reset with ack and vf mac address */
5583 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5584 memcpy(addr, vf_mac, 6);
5585 igb_write_mbx(hw, msgbuf, 3, vf);
5586}
5587
5588static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5589{
de42edde
GR		 5590 /*
5591 * The VF MAC Address is stored in a packed array of bytes
5592 * starting at the second 32 bit word of the msg array
5593 */
f2ca0dbe
AD		 5594 unsigned char *addr = (char *)&msg[1];
5595 int err = -1;
4ae196df 5596
f2ca0dbe
AD		 5597 if (is_valid_ether_addr(addr))
5598 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5599
f2ca0dbe 5600 return err;
4ae196df
AD		 5601}
5602
5603static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5604{
5605 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5606 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5607 u32 msg = E1000_VT_MSGTYPE_NACK;
5608
5609 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5610 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5611 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5612 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5613 vf_data->last_nack = jiffies;
4ae196df
AD		 5614 }
5615}
5616
f2ca0dbe 5617static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5618{
f2ca0dbe
AD		 5619 struct pci_dev *pdev = adapter->pdev;
5620 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5621 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5622 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5623 s32 retval;
5624
f2ca0dbe 5625 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5626
fef45f4c
AD		 5627 if (retval) {
5628 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5629 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5630 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5631 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5632 return;
5633 goto out;
5634 }
4ae196df
AD		 5635
5636 /* this is a message we already processed, do nothing */
5637 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5638 return;
4ae196df
AD		 5639
5640 /*
5641 * until the vf completes a reset it should not be
5642 * allowed to start any configuration.
5643 */
5644
5645 if (msgbuf[0] == E1000_VF_RESET) {
5646 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5647 return;
4ae196df
AD		 5648 }
5649
f2ca0dbe 5650 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5651 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5652 return;
5653 retval = -1;
5654 goto out;
4ae196df
AD		 5655 }
5656
5657 switch ((msgbuf[0] & 0xFFFF)) {
5658 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5659 retval = -EINVAL;
5660 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5661 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5662 else
5663 dev_warn(&pdev->dev,
5664 "VF %d attempted to override administratively "
5665 "set MAC address\nReload the VF driver to "
5666 "resume operations\n", vf);
4ae196df 5667 break;
7d5753f0
AD		 5668 case E1000_VF_SET_PROMISC:
5669 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5670 break;
4ae196df
AD		 5671 case E1000_VF_SET_MULTICAST:
5672 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5673 break;
5674 case E1000_VF_SET_LPE:
5675 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5676 break;
5677 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5678 retval = -1;
5679 if (vf_data->pf_vlan)
5680 dev_warn(&pdev->dev,
5681 "VF %d attempted to override administratively "
5682 "set VLAN tag\nReload the VF driver to "
5683 "resume operations\n", vf);
8151d294
WM		 5684 else
5685 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5686 break;
5687 default:
090b1795 5688 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5689 retval = -1;
5690 break;
5691 }
5692
fef45f4c
AD		 5693 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5694out:
4ae196df
AD		 5695 /* notify the VF of the results of what it sent us */
5696 if (retval)
5697 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5698 else
5699 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5700
4ae196df 5701 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5702}
4ae196df 5703
f2ca0dbe
AD		 5704static void igb_msg_task(struct igb_adapter *adapter)
5705{
5706 struct e1000_hw *hw = &adapter->hw;
5707 u32 vf;
5708
5709 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5710 /* process any reset requests */
5711 if (!igb_check_for_rst(hw, vf))
5712 igb_vf_reset_event(adapter, vf);
5713
5714 /* process any messages pending */
5715 if (!igb_check_for_msg(hw, vf))
5716 igb_rcv_msg_from_vf(adapter, vf);
5717
5718 /* process any acks */
5719 if (!igb_check_for_ack(hw, vf))
5720 igb_rcv_ack_from_vf(adapter, vf);
5721 }
4ae196df
AD		 5722}
5723
68d480c4
AD		 5724/**
5725 * igb_set_uta - Set unicast filter table address
5726 * @adapter: board private structure
5727 *
5728 * The unicast table address is a register array of 32-bit registers.
5729 * The table is meant to be used in a way similar to how the MTA is used
5730 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5731 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5732 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5733 **/
5734static void igb_set_uta(struct igb_adapter *adapter)
5735{
5736 struct e1000_hw *hw = &adapter->hw;
5737 int i;
5738
5739 /* The UTA table only exists on 82576 hardware and newer */
5740 if (hw->mac.type < e1000_82576)
5741 return;
5742
5743 /* we only need to do this if VMDq is enabled */
5744 if (!adapter->vfs_allocated_count)
5745 return;
5746
5747 for (i = 0; i < hw->mac.uta_reg_count; i++)
5748 array_wr32(E1000_UTA, i, ~0);
5749}
5750
9d5c8243
AK		 5751/**
5752 * igb_intr_msi - Interrupt Handler
5753 * @irq: interrupt number
5754 * @data: pointer to a network interface device structure
5755 **/
5756static irqreturn_t igb_intr_msi(int irq, void *data)
5757{
047e0030
AD		 5758 struct igb_adapter *adapter = data;
5759 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5760 struct e1000_hw *hw = &adapter->hw;
5761 /* read ICR disables interrupts using IAM */
5762 u32 icr = rd32(E1000_ICR);
5763
047e0030 5764 igb_write_itr(q_vector);
9d5c8243 5765
7f081d40
AD		 5766 if (icr & E1000_ICR_DRSTA)
5767 schedule_work(&adapter->reset_task);
5768
047e0030 5769 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5770 /* HW is reporting DMA is out of sync */
5771 adapter->stats.doosync++;
5772 }
5773
9d5c8243
AK		 5774 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5775 hw->mac.get_link_status = 1;
5776 if (!test_bit(__IGB_DOWN, &adapter->state))
5777 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5778 }
5779
1f6e8178
MV		 5780 if (icr & E1000_ICR_TS) {
5781 u32 tsicr = rd32(E1000_TSICR);
5782
5783 if (tsicr & E1000_TSICR_TXTS) {
5784 /* acknowledge the interrupt */
5785 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5786 /* retrieve hardware timestamp */
5787 schedule_work(&adapter->ptp_tx_work);
5788 }
5789 }
1f6e8178 5790
047e0030 5791 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5792
5793 return IRQ_HANDLED;
5794}
5795
5796/**
4a3c6433 5797 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5798 * @irq: interrupt number
5799 * @data: pointer to a network interface device structure
5800 **/
5801static irqreturn_t igb_intr(int irq, void *data)
5802{
047e0030
AD		 5803 struct igb_adapter *adapter = data;
5804 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5805 struct e1000_hw *hw = &adapter->hw;
5806 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5807 * need for the IMC write */
5808 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5809
5810 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5811 * not set, then the adapter didn't send an interrupt */
5812 if (!(icr & E1000_ICR_INT_ASSERTED))
5813 return IRQ_NONE;
5814
0ba82994
AD		 5815 igb_write_itr(q_vector);
5816
7f081d40
AD		 5817 if (icr & E1000_ICR_DRSTA)
5818 schedule_work(&adapter->reset_task);
5819
047e0030 5820 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5821 /* HW is reporting DMA is out of sync */
5822 adapter->stats.doosync++;
5823 }
5824
9d5c8243
AK		 5825 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5826 hw->mac.get_link_status = 1;
5827 /* guard against interrupt when we're going down */
5828 if (!test_bit(__IGB_DOWN, &adapter->state))
5829 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5830 }
5831
1f6e8178
MV		 5832 if (icr & E1000_ICR_TS) {
5833 u32 tsicr = rd32(E1000_TSICR);
5834
5835 if (tsicr & E1000_TSICR_TXTS) {
5836 /* acknowledge the interrupt */
5837 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5838 /* retrieve hardware timestamp */
5839 schedule_work(&adapter->ptp_tx_work);
5840 }
5841 }
1f6e8178 5842
047e0030 5843 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5844
5845 return IRQ_HANDLED;
5846}
5847
c50b52a0 5848static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5849{
047e0030 5850 struct igb_adapter *adapter = q_vector->adapter;
46544258 5851 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5852
0ba82994
AD		 5853 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5854 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5855 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5856 igb_set_itr(q_vector);
46544258 5857 else
047e0030 5858 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5859 }
5860
46544258
AD		 5861 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5862 if (adapter->msix_entries)
047e0030 5863 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5864 else
5865 igb_irq_enable(adapter);
5866 }
9d5c8243
AK		 5867}
5868
46544258
AD		 5869/**
5870 * igb_poll - NAPI Rx polling callback
5871 * @napi: napi polling structure
5872 * @budget: count of how many packets we should handle
5873 **/
5874static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5875{
047e0030
AD		 5876 struct igb_q_vector *q_vector = container_of(napi,
5877 struct igb_q_vector,
5878 napi);
16eb8815 5879 bool clean_complete = true;
9d5c8243 5880
421e02f0 5881#ifdef CONFIG_IGB_DCA
047e0030
AD		 5882 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5883 igb_update_dca(q_vector);
fe4506b6 5884#endif
0ba82994 5885 if (q_vector->tx.ring)
13fde97a 5886 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5887
0ba82994 5888 if (q_vector->rx.ring)
cd392f5c 5889 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5890
16eb8815
AD		 5891 /* If all work not completed, return budget and keep polling */
5892 if (!clean_complete)
5893 return budget;
46544258 5894
9d5c8243 5895 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5896 napi_complete(napi);
5897 igb_ring_irq_enable(q_vector);
9d5c8243 5898
16eb8815 5899 return 0;
9d5c8243 5900}
6d8126f9 5901
9d5c8243
AK		 5902/**
5903 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5904 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5905 *
9d5c8243
AK		 5906 * returns true if ring is completely cleaned
5907 **/
047e0030 5908static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5909{
047e0030 5910 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5911 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5912 struct igb_tx_buffer *tx_buffer;
f4128785 5913 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5914 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5915 unsigned int budget = q_vector->tx.work_limit;
8542db05 5916 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5917
13fde97a
AD		 5918 if (test_bit(__IGB_DOWN, &adapter->state))
5919 return true;
0e014cb1 5920
06034649 5921 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5922 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5923 i -= tx_ring->count;
9d5c8243 5924
f4128785
AD		 5925 do {
5926 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5927
5928 /* if next_to_watch is not set then there is no work pending */
5929 if (!eop_desc)
5930 break;
13fde97a 5931
f4128785 5932 /* prevent any other reads prior to eop_desc */
70d289bc 5933 read_barrier_depends();
f4128785 5934
13fde97a
AD		 5935 /* if DD is not set pending work has not been completed */
5936 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5937 break;
5938
8542db05
AD		 5939 /* clear next_to_watch to prevent false hangs */
5940 tx_buffer->next_to_watch = NULL;
9d5c8243 5941
ebe42d16
AD		 5942 /* update the statistics for this packet */
5943 total_bytes += tx_buffer->bytecount;
5944 total_packets += tx_buffer->gso_segs;
13fde97a 5945
ebe42d16
AD		 5946 /* free the skb */
5947 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5948
ebe42d16
AD		 5949 /* unmap skb header data */
5950 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5951 dma_unmap_addr(tx_buffer, dma),
5952 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5953 DMA_TO_DEVICE);
5954
c9f14bf3
AD		 5955 /* clear tx_buffer data */
5956 tx_buffer->skb = NULL;
5957 dma_unmap_len_set(tx_buffer, len, 0);
5958
ebe42d16
AD		 5959 /* clear last DMA location and unmap remaining buffers */
5960 while (tx_desc != eop_desc) {
13fde97a
AD		 5961 tx_buffer++;
5962 tx_desc++;
9d5c8243 5963 i++;
8542db05
AD		 5964 if (unlikely(!i)) {
5965 i -= tx_ring->count;
06034649 5966 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5967 tx_desc = IGB_TX_DESC(tx_ring, 0);
5968 }
ebe42d16
AD		 5969
5970 /* unmap any remaining paged data */
c9f14bf3 5971 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5972 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5973 dma_unmap_addr(tx_buffer, dma),
5974 dma_unmap_len(tx_buffer, len),
ebe42d16 5975 DMA_TO_DEVICE);
c9f14bf3 5976 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5977 }
5978 }
5979
ebe42d16
AD		 5980 /* move us one more past the eop_desc for start of next pkt */
5981 tx_buffer++;
5982 tx_desc++;
5983 i++;
5984 if (unlikely(!i)) {
5985 i -= tx_ring->count;
5986 tx_buffer = tx_ring->tx_buffer_info;
5987 tx_desc = IGB_TX_DESC(tx_ring, 0);
5988 }
f4128785
AD		 5989
5990 /* issue prefetch for next Tx descriptor */
5991 prefetch(tx_desc);
5992
5993 /* update budget accounting */
5994 budget--;
5995 } while (likely(budget));
0e014cb1 5996
bdbc0631
ED		 5997 netdev_tx_completed_queue(txring_txq(tx_ring),
5998 total_packets, total_bytes);
8542db05 5999 i += tx_ring->count;
9d5c8243 6000 tx_ring->next_to_clean = i;
13fde97a
AD		 6001 u64_stats_update_begin(&tx_ring->tx_syncp);
6002 tx_ring->tx_stats.bytes += total_bytes;
6003 tx_ring->tx_stats.packets += total_packets;
6004 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6005 q_vector->tx.total_bytes += total_bytes;
6006 q_vector->tx.total_packets += total_packets;
9d5c8243 6007
6d095fa8 6008 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6009 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6010
9d5c8243
AK		 6011 /* Detect a transmit hang in hardware, this serializes the
6012 * check with the clearing of time_stamp and movement of i */
6d095fa8 6013 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6014 if (tx_buffer->next_to_watch &&
8542db05 6015 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6016 (adapter->tx_timeout_factor * HZ)) &&
6017 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6018
9d5c8243 6019 /* detected Tx unit hang */
59d71989 6020 dev_err(tx_ring->dev,
9d5c8243 6021 "Detected Tx Unit Hang\n"
2d064c06 6022 " Tx Queue <%d>\n"
9d5c8243
AK		 6023 " TDH <%x>\n"
6024 " TDT <%x>\n"
6025 " next_to_use <%x>\n"
6026 " next_to_clean <%x>\n"
9d5c8243
AK		 6027 "buffer_info[next_to_clean]\n"
6028 " time_stamp <%lx>\n"
8542db05 6029 " next_to_watch <%p>\n"
9d5c8243
AK		 6030 " jiffies <%lx>\n"
6031 " desc.status <%x>\n",
2d064c06 6032 tx_ring->queue_index,
238ac817 6033 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6034 readl(tx_ring->tail),
9d5c8243
AK		 6035 tx_ring->next_to_use,
6036 tx_ring->next_to_clean,
8542db05 6037 tx_buffer->time_stamp,
f4128785 6038 tx_buffer->next_to_watch,
9d5c8243 6039 jiffies,
f4128785 6040 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6041 netif_stop_subqueue(tx_ring->netdev,
6042 tx_ring->queue_index);
6043
6044 /* we are about to reset, no point in enabling stuff */
6045 return true;
9d5c8243
AK		 6046 }
6047 }
13fde97a
AD		 6048
6049 if (unlikely(total_packets &&
6050 netif_carrier_ok(tx_ring->netdev) &&
6051 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
6052 /* Make sure that anybody stopping the queue after this
6053 * sees the new next_to_clean.
6054 */
6055 smp_mb();
6056 if (__netif_subqueue_stopped(tx_ring->netdev,
6057 tx_ring->queue_index) &&
6058 !(test_bit(__IGB_DOWN, &adapter->state))) {
6059 netif_wake_subqueue(tx_ring->netdev,
6060 tx_ring->queue_index);
6061
6062 u64_stats_update_begin(&tx_ring->tx_syncp);
6063 tx_ring->tx_stats.restart_queue++;
6064 u64_stats_update_end(&tx_ring->tx_syncp);
6065 }
6066 }
6067
6068 return !!budget;
9d5c8243
AK		 6069}
6070
cbc8e55f
AD		 6071/**
6072 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6073 * @rx_ring: rx descriptor ring to store buffers on
6074 * @old_buff: donor buffer to have page reused
6075 *
6076 * Synchronizes page for reuse by the adapter
6077 **/
6078static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6079 struct igb_rx_buffer *old_buff)
6080{
6081 struct igb_rx_buffer *new_buff;
6082 u16 nta = rx_ring->next_to_alloc;
6083
6084 new_buff = &rx_ring->rx_buffer_info[nta];
6085
6086 /* update, and store next to alloc */
6087 nta++;
6088 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6089
6090 /* transfer page from old buffer to new buffer */
6091 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6092
6093 /* sync the buffer for use by the device */
6094 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6095 old_buff->page_offset,
de78d1f9 6096 IGB_RX_BUFSZ,
cbc8e55f
AD		 6097 DMA_FROM_DEVICE);
6098}
6099
6100/**
6101 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6102 * @rx_ring: rx descriptor ring to transact packets on
6103 * @rx_buffer: buffer containing page to add
6104 * @rx_desc: descriptor containing length of buffer written by hardware
6105 * @skb: sk_buff to place the data into
6106 *
6107 * This function will add the data contained in rx_buffer->page to the skb.
6108 * This is done either through a direct copy if the data in the buffer is
6109 * less than the skb header size, otherwise it will just attach the page as
6110 * a frag to the skb.
6111 *
6112 * The function will then update the page offset if necessary and return
6113 * true if the buffer can be reused by the adapter.
6114 **/
6115static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6116 struct igb_rx_buffer *rx_buffer,
6117 union e1000_adv_rx_desc *rx_desc,
6118 struct sk_buff *skb)
6119{
6120 struct page *page = rx_buffer->page;
6121 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6122
6123 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6124 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6125
cbc8e55f
AD		 6126 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6127 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6128 va += IGB_TS_HDR_LEN;
6129 size -= IGB_TS_HDR_LEN;
6130 }
6131
cbc8e55f
AD		 6132 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6133
6134 /* we can reuse buffer as-is, just make sure it is local */
6135 if (likely(page_to_nid(page) == numa_node_id()))
6136 return true;
6137
6138 /* this page cannot be reused so discard it */
6139 put_page(page);
6140 return false;
6141 }
6142
6143 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 6144 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 6145
6146 /* avoid re-using remote pages */
6147 if (unlikely(page_to_nid(page) != numa_node_id()))
6148 return false;
6149
de78d1f9 6150#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 6151 /* if we are only owner of page we can reuse it */
6152 if (unlikely(page_count(page) != 1))
6153 return false;
6154
6155 /* flip page offset to other buffer */
de78d1f9 6156 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 6157
6158 /*
6159 * since we are the only owner of the page and we need to
6160 * increment it, just set the value to 2 in order to avoid
6161 * an unnecessary locked operation
6162 */
6163 atomic_set(&page->_count, 2);
de78d1f9
AD		 6164#else
6165 /* move offset up to the next cache line */
6166 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
6167
6168 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6169 return false;
6170
6171 /* bump ref count on page before it is given to the stack */
6172 get_page(page);
6173#endif
cbc8e55f
AD		 6174
6175 return true;
6176}
6177
2e334eee
AD		 6178static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6179 union e1000_adv_rx_desc *rx_desc,
6180 struct sk_buff *skb)
6181{
6182 struct igb_rx_buffer *rx_buffer;
6183 struct page *page;
6184
6185 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6186
6187 /*
6188 * This memory barrier is needed to keep us from reading
6189 * any other fields out of the rx_desc until we know the
6190 * RXD_STAT_DD bit is set
6191 */
6192 rmb();
6193
6194 page = rx_buffer->page;
6195 prefetchw(page);
6196
6197 if (likely(!skb)) {
6198 void *page_addr = page_address(page) +
6199 rx_buffer->page_offset;
6200
6201 /* prefetch first cache line of first page */
6202 prefetch(page_addr);
6203#if L1_CACHE_BYTES < 128
6204 prefetch(page_addr + L1_CACHE_BYTES);
6205#endif
6206
6207 /* allocate a skb to store the frags */
6208 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6209 IGB_RX_HDR_LEN);
6210 if (unlikely(!skb)) {
6211 rx_ring->rx_stats.alloc_failed++;
6212 return NULL;
6213 }
6214
6215 /*
6216 * we will be copying header into skb->data in
6217 * pskb_may_pull so it is in our interest to prefetch
6218 * it now to avoid a possible cache miss
6219 */
6220 prefetchw(skb->data);
6221 }
6222
6223 /* we are reusing so sync this buffer for CPU use */
6224 dma_sync_single_range_for_cpu(rx_ring->dev,
6225 rx_buffer->dma,
6226 rx_buffer->page_offset,
de78d1f9 6227 IGB_RX_BUFSZ,
2e334eee
AD		 6228 DMA_FROM_DEVICE);
6229
6230 /* pull page into skb */
6231 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6232 /* hand second half of page back to the ring */
6233 igb_reuse_rx_page(rx_ring, rx_buffer);
6234 } else {
6235 /* we are not reusing the buffer so unmap it */
6236 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6237 PAGE_SIZE, DMA_FROM_DEVICE);
6238 }
6239
6240 /* clear contents of rx_buffer */
6241 rx_buffer->page = NULL;
6242
6243 return skb;
6244}
6245
cd392f5c 6246static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6247 union e1000_adv_rx_desc *rx_desc,
6248 struct sk_buff *skb)
9d5c8243 6249{
bc8acf2c 6250 skb_checksum_none_assert(skb);
9d5c8243 6251
294e7d78 6252 /* Ignore Checksum bit is set */
3ceb90fd 6253 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6254 return;
6255
6256 /* Rx checksum disabled via ethtool */
6257 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6258 return;
85ad76b2 6259
9d5c8243 6260 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6261 if (igb_test_staterr(rx_desc,
6262 E1000_RXDEXT_STATERR_TCPE |
6263 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6264 /*
6265 * work around errata with sctp packets where the TCPE aka
6266 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6267 * packets, (aka let the stack check the crc32c)
6268 */
866cff06
AD		 6269 if (!((skb->len == 60) &&
6270 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6271 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6272 ring->rx_stats.csum_err++;
12dcd86b
ED		 6273 u64_stats_update_end(&ring->rx_syncp);
6274 }
9d5c8243 6275 /* let the stack verify checksum errors */
9d5c8243
AK		 6276 return;
6277 }
6278 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6279 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6280 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6281 skb->ip_summed = CHECKSUM_UNNECESSARY;
6282
3ceb90fd
AD		 6283 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6284 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6285}
6286
077887c3
AD		 6287static inline void igb_rx_hash(struct igb_ring *ring,
6288 union e1000_adv_rx_desc *rx_desc,
6289 struct sk_buff *skb)
6290{
6291 if (ring->netdev->features & NETIF_F_RXHASH)
6292 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6293}
6294
2e334eee
AD		 6295/**
6296 * igb_is_non_eop - process handling of non-EOP buffers
6297 * @rx_ring: Rx ring being processed
6298 * @rx_desc: Rx descriptor for current buffer
6299 * @skb: current socket buffer containing buffer in progress
6300 *
6301 * This function updates next to clean. If the buffer is an EOP buffer
6302 * this function exits returning false, otherwise it will place the
6303 * sk_buff in the next buffer to be chained and return true indicating
6304 * that this is in fact a non-EOP buffer.
6305 **/
6306static bool igb_is_non_eop(struct igb_ring *rx_ring,
6307 union e1000_adv_rx_desc *rx_desc)
6308{
6309 u32 ntc = rx_ring->next_to_clean + 1;
6310
6311 /* fetch, update, and store next to clean */
6312 ntc = (ntc < rx_ring->count) ? ntc : 0;
6313 rx_ring->next_to_clean = ntc;
6314
6315 prefetch(IGB_RX_DESC(rx_ring, ntc));
6316
6317 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6318 return false;
6319
6320 return true;
6321}
6322
1a1c225b
AD		 6323/**
6324 * igb_get_headlen - determine size of header for LRO/GRO
6325 * @data: pointer to the start of the headers
6326 * @max_len: total length of section to find headers in
6327 *
6328 * This function is meant to determine the length of headers that will
6329 * be recognized by hardware for LRO, and GRO offloads. The main
6330 * motivation of doing this is to only perform one pull for IPv4 TCP
6331 * packets so that we can do basic things like calculating the gso_size
6332 * based on the average data per packet.
6333 **/
6334static unsigned int igb_get_headlen(unsigned char *data,
6335 unsigned int max_len)
6336{
6337 union {
6338 unsigned char *network;
6339 /* l2 headers */
6340 struct ethhdr *eth;
6341 struct vlan_hdr *vlan;
6342 /* l3 headers */
6343 struct iphdr *ipv4;
6344 struct ipv6hdr *ipv6;
6345 } hdr;
6346 __be16 protocol;
6347 u8 nexthdr = 0; /* default to not TCP */
6348 u8 hlen;
6349
6350 /* this should never happen, but better safe than sorry */
6351 if (max_len < ETH_HLEN)
6352 return max_len;
6353
6354 /* initialize network frame pointer */
6355 hdr.network = data;
6356
6357 /* set first protocol and move network header forward */
6358 protocol = hdr.eth->h_proto;
6359 hdr.network += ETH_HLEN;
6360
6361 /* handle any vlan tag if present */
6362 if (protocol == __constant_htons(ETH_P_8021Q)) {
6363 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6364 return max_len;
6365
6366 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6367 hdr.network += VLAN_HLEN;
6368 }
6369
6370 /* handle L3 protocols */
6371 if (protocol == __constant_htons(ETH_P_IP)) {
6372 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6373 return max_len;
6374
6375 /* access ihl as a u8 to avoid unaligned access on ia64 */
6376 hlen = (hdr.network[0] & 0x0F) << 2;
6377
6378 /* verify hlen meets minimum size requirements */
6379 if (hlen < sizeof(struct iphdr))
6380 return hdr.network - data;
6381
f2fb4ab2
AD		 6382 /* record next protocol if header is present */
6383 if (!hdr.ipv4->frag_off)
6384 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6385 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6386 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6387 return max_len;
6388
6389 /* record next protocol */
6390 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6391 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6392 } else {
6393 return hdr.network - data;
6394 }
6395
f2fb4ab2
AD		 6396 /* relocate pointer to start of L4 header */
6397 hdr.network += hlen;
6398
1a1c225b
AD		 6399 /* finally sort out TCP */
6400 if (nexthdr == IPPROTO_TCP) {
6401 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6402 return max_len;
6403
6404 /* access doff as a u8 to avoid unaligned access on ia64 */
6405 hlen = (hdr.network[12] & 0xF0) >> 2;
6406
6407 /* verify hlen meets minimum size requirements */
6408 if (hlen < sizeof(struct tcphdr))
6409 return hdr.network - data;
6410
6411 hdr.network += hlen;
6412 } else if (nexthdr == IPPROTO_UDP) {
6413 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6414 return max_len;
6415
6416 hdr.network += sizeof(struct udphdr);
6417 }
6418
6419 /*
6420 * If everything has gone correctly hdr.network should be the
6421 * data section of the packet and will be the end of the header.
6422 * If not then it probably represents the end of the last recognized
6423 * header.
6424 */
6425 if ((hdr.network - data) < max_len)
6426 return hdr.network - data;
6427 else
6428 return max_len;
6429}
6430
6431/**
6432 * igb_pull_tail - igb specific version of skb_pull_tail
6433 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6434 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6435 * @skb: pointer to current skb being adjusted
6436 *
6437 * This function is an igb specific version of __pskb_pull_tail. The
6438 * main difference between this version and the original function is that
6439 * this function can make several assumptions about the state of things
6440 * that allow for significant optimizations versus the standard function.
6441 * As a result we can do things like drop a frag and maintain an accurate
6442 * truesize for the skb.
6443 */
6444static void igb_pull_tail(struct igb_ring *rx_ring,
6445 union e1000_adv_rx_desc *rx_desc,
6446 struct sk_buff *skb)
2d94d8ab 6447{
1a1c225b
AD		 6448 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6449 unsigned char *va;
6450 unsigned int pull_len;
6451
6452 /*
6453 * it is valid to use page_address instead of kmap since we are
6454 * working with pages allocated out of the lomem pool per
6455 * alloc_page(GFP_ATOMIC)
2d94d8ab 6456 */
1a1c225b
AD		 6457 va = skb_frag_address(frag);
6458
1a1c225b
AD		 6459 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6460 /* retrieve timestamp from buffer */
6461 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6462
6463 /* update pointers to remove timestamp header */
6464 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6465 frag->page_offset += IGB_TS_HDR_LEN;
6466 skb->data_len -= IGB_TS_HDR_LEN;
6467 skb->len -= IGB_TS_HDR_LEN;
6468
6469 /* move va to start of packet data */
6470 va += IGB_TS_HDR_LEN;
6471 }
6472
1a1c225b
AD		 6473 /*
6474 * we need the header to contain the greater of either ETH_HLEN or
6475 * 60 bytes if the skb->len is less than 60 for skb_pad.
6476 */
6477 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6478
6479 /* align pull length to size of long to optimize memcpy performance */
6480 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6481
6482 /* update all of the pointers */
6483 skb_frag_size_sub(frag, pull_len);
6484 frag->page_offset += pull_len;
6485 skb->data_len -= pull_len;
6486 skb->tail += pull_len;
6487}
6488
6489/**
6490 * igb_cleanup_headers - Correct corrupted or empty headers
6491 * @rx_ring: rx descriptor ring packet is being transacted on
6492 * @rx_desc: pointer to the EOP Rx descriptor
6493 * @skb: pointer to current skb being fixed
6494 *
6495 * Address the case where we are pulling data in on pages only
6496 * and as such no data is present in the skb header.
6497 *
6498 * In addition if skb is not at least 60 bytes we need to pad it so that
6499 * it is large enough to qualify as a valid Ethernet frame.
6500 *
6501 * Returns true if an error was encountered and skb was freed.
6502 **/
6503static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6504 union e1000_adv_rx_desc *rx_desc,
6505 struct sk_buff *skb)
6506{
6507
6508 if (unlikely((igb_test_staterr(rx_desc,
6509 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6510 struct net_device *netdev = rx_ring->netdev;
6511 if (!(netdev->features & NETIF_F_RXALL)) {
6512 dev_kfree_skb_any(skb);
6513 return true;
6514 }
6515 }
6516
6517 /* place header in linear portion of buffer */
6518 if (skb_is_nonlinear(skb))
6519 igb_pull_tail(rx_ring, rx_desc, skb);
6520
6521 /* if skb_pad returns an error the skb was freed */
6522 if (unlikely(skb->len < 60)) {
6523 int pad_len = 60 - skb->len;
6524
6525 if (skb_pad(skb, pad_len))
6526 return true;
6527 __skb_put(skb, pad_len);
6528 }
6529
6530 return false;
2d94d8ab
AD		 6531}
6532
db2ee5bd
AD		 6533/**
6534 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6535 * @rx_ring: rx descriptor ring packet is being transacted on
6536 * @rx_desc: pointer to the EOP Rx descriptor
6537 * @skb: pointer to current skb being populated
6538 *
6539 * This function checks the ring, descriptor, and packet information in
6540 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6541 * other fields within the skb.
6542 **/
6543static void igb_process_skb_fields(struct igb_ring *rx_ring,
6544 union e1000_adv_rx_desc *rx_desc,
6545 struct sk_buff *skb)
6546{
6547 struct net_device *dev = rx_ring->netdev;
6548
6549 igb_rx_hash(rx_ring, rx_desc, skb);
6550
6551 igb_rx_checksum(rx_ring, rx_desc, skb);
6552
db2ee5bd 6553 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6554
6555 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6556 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6557 u16 vid;
6558 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6559 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6560 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6561 else
6562 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6563
6564 __vlan_hwaccel_put_tag(skb, vid);
6565 }
6566
6567 skb_record_rx_queue(skb, rx_ring->queue_index);
6568
6569 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6570}
6571
2e334eee 6572static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6573{
0ba82994 6574 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6575 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6576 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6577 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6578
2e334eee
AD		 6579 do {
6580 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6581
2e334eee
AD		 6582 /* return some buffers to hardware, one at a time is too slow */
6583 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6584 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6585 cleaned_count = 0;
6586 }
bf36c1a0 6587
2e334eee 6588 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6589
2e334eee
AD		 6590 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6591 break;
9d5c8243 6592
2e334eee
AD		 6593 /* retrieve a buffer from the ring */
6594 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6595
2e334eee
AD		 6596 /* exit if we failed to retrieve a buffer */
6597 if (!skb)
6598 break;
1a1c225b 6599
2e334eee 6600 cleaned_count++;
1a1c225b 6601
2e334eee
AD		 6602 /* fetch next buffer in frame if non-eop */
6603 if (igb_is_non_eop(rx_ring, rx_desc))
6604 continue;
1a1c225b
AD		 6605
6606 /* verify the packet layout is correct */
6607 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6608 skb = NULL;
6609 continue;
9d5c8243 6610 }
9d5c8243 6611
db2ee5bd 6612 /* probably a little skewed due to removing CRC */
3ceb90fd 6613 total_bytes += skb->len;
3ceb90fd 6614
db2ee5bd
AD		 6615 /* populate checksum, timestamp, VLAN, and protocol */
6616 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6617
b2cb09b1 6618 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6619
1a1c225b
AD		 6620 /* reset skb pointer */
6621 skb = NULL;
6622
2e334eee
AD		 6623 /* update budget accounting */
6624 total_packets++;
6625 } while (likely(total_packets < budget));
bf36c1a0 6626
1a1c225b
AD		 6627 /* place incomplete frames back on ring for completion */
6628 rx_ring->skb = skb;
6629
12dcd86b 6630 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6631 rx_ring->rx_stats.packets += total_packets;
6632 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6633 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6634 q_vector->rx.total_packets += total_packets;
6635 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6636
6637 if (cleaned_count)
cd392f5c 6638 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6639
2e334eee 6640 return (total_packets < budget);
9d5c8243
AK		 6641}
6642
c023cd88 6643static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6644 struct igb_rx_buffer *bi)
c023cd88
AD		 6645{
6646 struct page *page = bi->page;
cbc8e55f 6647 dma_addr_t dma;
c023cd88 6648
cbc8e55f
AD		 6649 /* since we are recycling buffers we should seldom need to alloc */
6650 if (likely(page))
c023cd88
AD		 6651 return true;
6652
cbc8e55f
AD		 6653 /* alloc new page for storage */
6654 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6655 if (unlikely(!page)) {
6656 rx_ring->rx_stats.alloc_failed++;
6657 return false;
c023cd88
AD		 6658 }
6659
cbc8e55f
AD		 6660 /* map page for use */
6661 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6662
cbc8e55f
AD		 6663 /*
6664 * if mapping failed free memory back to system since
6665 * there isn't much point in holding memory we can't use
6666 */
1a1c225b 6667 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6668 __free_page(page);
6669
c023cd88
AD		 6670 rx_ring->rx_stats.alloc_failed++;
6671 return false;
6672 }
6673
1a1c225b 6674 bi->dma = dma;
cbc8e55f
AD		 6675 bi->page = page;
6676 bi->page_offset = 0;
1a1c225b 6677
c023cd88
AD		 6678 return true;
6679}
6680
9d5c8243 6681/**
cd392f5c 6682 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6683 * @adapter: address of board private structure
6684 **/
cd392f5c 6685void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6686{
9d5c8243 6687 union e1000_adv_rx_desc *rx_desc;
06034649 6688 struct igb_rx_buffer *bi;
c023cd88 6689 u16 i = rx_ring->next_to_use;
9d5c8243 6690
cbc8e55f
AD		 6691 /* nothing to do */
6692 if (!cleaned_count)
6693 return;
6694
60136906 6695 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6696 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6697 i -= rx_ring->count;
9d5c8243 6698
cbc8e55f 6699 do {
1a1c225b 6700 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6701 break;
9d5c8243 6702
cbc8e55f
AD		 6703 /*
6704 * Refresh the desc even if buffer_addrs didn't change
6705 * because each write-back erases this info.
6706 */
6707 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6708
c023cd88
AD		 6709 rx_desc++;
6710 bi++;
9d5c8243 6711 i++;
c023cd88 6712 if (unlikely(!i)) {
60136906 6713 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6714 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6715 i -= rx_ring->count;
6716 }
6717
6718 /* clear the hdr_addr for the next_to_use descriptor */
6719 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6720
6721 cleaned_count--;
6722 } while (cleaned_count);
9d5c8243 6723
c023cd88
AD		 6724 i += rx_ring->count;
6725
9d5c8243 6726 if (rx_ring->next_to_use != i) {
cbc8e55f 6727 /* record the next descriptor to use */
9d5c8243 6728 rx_ring->next_to_use = i;
9d5c8243 6729
cbc8e55f
AD		 6730 /* update next to alloc since we have filled the ring */
6731 rx_ring->next_to_alloc = i;
6732
6733 /*
6734 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6735 * know there are new descriptors to fetch. (Only
6736 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6737 * such as IA-64).
6738 */
9d5c8243 6739 wmb();
fce99e34 6740 writel(i, rx_ring->tail);
9d5c8243
AK		 6741 }
6742}
6743
6744/**
6745 * igb_mii_ioctl -
6746 * @netdev:
6747 * @ifreq:
6748 * @cmd:
6749 **/
6750static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6751{
6752 struct igb_adapter *adapter = netdev_priv(netdev);
6753 struct mii_ioctl_data *data = if_mii(ifr);
6754
6755 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6756 return -EOPNOTSUPP;
6757
6758 switch (cmd) {
6759 case SIOCGMIIPHY:
6760 data->phy_id = adapter->hw.phy.addr;
6761 break;
6762 case SIOCGMIIREG:
f5f4cf08
AD		 6763 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6764 &data->val_out))
9d5c8243
AK		 6765 return -EIO;
6766 break;
6767 case SIOCSMIIREG:
6768 default:
6769 return -EOPNOTSUPP;
6770 }
6771 return 0;
6772}
6773
6774/**
6775 * igb_ioctl -
6776 * @netdev:
6777 * @ifreq:
6778 * @cmd:
6779 **/
6780static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6781{
6782 switch (cmd) {
6783 case SIOCGMIIPHY:
6784 case SIOCGMIIREG:
6785 case SIOCSMIIREG:
6786 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6787 case SIOCSHWTSTAMP:
a79f4f88 6788 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6789 default:
6790 return -EOPNOTSUPP;
6791 }
6792}
6793
009bc06e
AD		 6794s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6795{
6796 struct igb_adapter *adapter = hw->back;
009bc06e 6797
23d028cc 6798 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6799 return -E1000_ERR_CONFIG;
6800
009bc06e
AD		 6801 return 0;
6802}
6803
6804s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6805{
6806 struct igb_adapter *adapter = hw->back;
009bc06e 6807
23d028cc 6808 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6809 return -E1000_ERR_CONFIG;
6810
009bc06e
AD		 6811 return 0;
6812}
6813
c8f44aff 6814static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6815{
6816 struct igb_adapter *adapter = netdev_priv(netdev);
6817 struct e1000_hw *hw = &adapter->hw;
6818 u32 ctrl, rctl;
5faf030c 6819 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6820
5faf030c 6821 if (enable) {
9d5c8243
AK		 6822 /* enable VLAN tag insert/strip */
6823 ctrl = rd32(E1000_CTRL);
6824 ctrl |= E1000_CTRL_VME;
6825 wr32(E1000_CTRL, ctrl);
6826
51466239 6827 /* Disable CFI check */
9d5c8243 6828 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6829 rctl &= ~E1000_RCTL_CFIEN;
6830 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6831 } else {
6832 /* disable VLAN tag insert/strip */
6833 ctrl = rd32(E1000_CTRL);
6834 ctrl &= ~E1000_CTRL_VME;
6835 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6836 }
6837
e1739522 6838 igb_rlpml_set(adapter);
9d5c8243
AK		 6839}
6840
8e586137 6841static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6842{
6843 struct igb_adapter *adapter = netdev_priv(netdev);
6844 struct e1000_hw *hw = &adapter->hw;
4ae196df 6845 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6846
51466239
AD		 6847 /* attempt to add filter to vlvf array */
6848 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6849
51466239
AD		 6850 /* add the filter since PF can receive vlans w/o entry in vlvf */
6851 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6852
6853 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6854
6855 return 0;
9d5c8243
AK		 6856}
6857
8e586137 6858static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6859{
6860 struct igb_adapter *adapter = netdev_priv(netdev);
6861 struct e1000_hw *hw = &adapter->hw;
4ae196df 6862 int pf_id = adapter->vfs_allocated_count;
51466239 6863 s32 err;
9d5c8243 6864
51466239
AD		 6865 /* remove vlan from VLVF table array */
6866 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6867
51466239
AD		 6868 /* if vid was not present in VLVF just remove it from table */
6869 if (err)
4ae196df 6870 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6871
6872 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6873
6874 return 0;
9d5c8243
AK		 6875}
6876
6877static void igb_restore_vlan(struct igb_adapter *adapter)
6878{
b2cb09b1 6879 u16 vid;
9d5c8243 6880
5faf030c
AD		 6881 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6882
b2cb09b1
JP		 6883 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6884 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6885}
6886
14ad2513 6887int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6888{
090b1795 6889 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6890 struct e1000_mac_info *mac = &adapter->hw.mac;
6891
6892 mac->autoneg = 0;
6893
14ad2513
DD		 6894 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6895 * for the switch() below to work */
6896 if ((spd & 1) || (dplx & ~1))
6897 goto err_inval;
6898
cd2638a8
CW		 6899 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6900 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6901 spd != SPEED_1000 &&
6902 dplx != DUPLEX_FULL)
6903 goto err_inval;
cd2638a8 6904
14ad2513 6905 switch (spd + dplx) {
9d5c8243
AK		 6906 case SPEED_10 + DUPLEX_HALF:
6907 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6908 break;
6909 case SPEED_10 + DUPLEX_FULL:
6910 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6911 break;
6912 case SPEED_100 + DUPLEX_HALF:
6913 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6914 break;
6915 case SPEED_100 + DUPLEX_FULL:
6916 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6917 break;
6918 case SPEED_1000 + DUPLEX_FULL:
6919 mac->autoneg = 1;
6920 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6921 break;
6922 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6923 default:
14ad2513 6924 goto err_inval;
9d5c8243 6925 }
8376dad0
JB		 6926
6927 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6928 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6929
9d5c8243 6930 return 0;
14ad2513
DD		 6931
6932err_inval:
6933 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6934 return -EINVAL;
9d5c8243
AK		 6935}
6936
749ab2cd
YZ		 6937static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6938 bool runtime)
9d5c8243
AK		 6939{
6940 struct net_device *netdev = pci_get_drvdata(pdev);
6941 struct igb_adapter *adapter = netdev_priv(netdev);
6942 struct e1000_hw *hw = &adapter->hw;
2d064c06 6943 u32 ctrl, rctl, status;
749ab2cd 6944 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6945#ifdef CONFIG_PM
6946 int retval = 0;
6947#endif
6948
6949 netif_device_detach(netdev);
6950
a88f10ec 6951 if (netif_running(netdev))
749ab2cd 6952 __igb_close(netdev, true);
a88f10ec 6953
047e0030 6954 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6955
6956#ifdef CONFIG_PM
6957 retval = pci_save_state(pdev);
6958 if (retval)
6959 return retval;
6960#endif
6961
6962 status = rd32(E1000_STATUS);
6963 if (status & E1000_STATUS_LU)
6964 wufc &= ~E1000_WUFC_LNKC;
6965
6966 if (wufc) {
6967 igb_setup_rctl(adapter);
ff41f8dc 6968 igb_set_rx_mode(netdev);
9d5c8243
AK		 6969
6970 /* turn on all-multi mode if wake on multicast is enabled */
6971 if (wufc & E1000_WUFC_MC) {
6972 rctl = rd32(E1000_RCTL);
6973 rctl |= E1000_RCTL_MPE;
6974 wr32(E1000_RCTL, rctl);
6975 }
6976
6977 ctrl = rd32(E1000_CTRL);
6978 /* advertise wake from D3Cold */
6979 #define E1000_CTRL_ADVD3WUC 0x00100000
6980 /* phy power management enable */
6981 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6982 ctrl |= E1000_CTRL_ADVD3WUC;
6983 wr32(E1000_CTRL, ctrl);
6984
9d5c8243 6985 /* Allow time for pending master requests to run */
330a6d6a 6986 igb_disable_pcie_master(hw);
9d5c8243
AK		 6987
6988 wr32(E1000_WUC, E1000_WUC_PME_EN);
6989 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6990 } else {
6991 wr32(E1000_WUC, 0);
6992 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6993 }
6994
3fe7c4c9
RW		 6995 *enable_wake = wufc || adapter->en_mng_pt;
6996 if (!*enable_wake)
88a268c1
NN		 6997 igb_power_down_link(adapter);
6998 else
6999 igb_power_up_link(adapter);
9d5c8243
AK		 7000
7001 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7002 * would have already happened in close and is redundant. */
7003 igb_release_hw_control(adapter);
7004
7005 pci_disable_device(pdev);
7006
9d5c8243
AK		 7007 return 0;
7008}
7009
7010#ifdef CONFIG_PM
d9dd966d 7011#ifdef CONFIG_PM_SLEEP
749ab2cd 7012static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7013{
7014 int retval;
7015 bool wake;
749ab2cd 7016 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7017
749ab2cd 7018 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7019 if (retval)
7020 return retval;
7021
7022 if (wake) {
7023 pci_prepare_to_sleep(pdev);
7024 } else {
7025 pci_wake_from_d3(pdev, false);
7026 pci_set_power_state(pdev, PCI_D3hot);
7027 }
7028
7029 return 0;
7030}
d9dd966d 7031#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7032
749ab2cd 7033static int igb_resume(struct device *dev)
9d5c8243 7034{
749ab2cd 7035 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7036 struct net_device *netdev = pci_get_drvdata(pdev);
7037 struct igb_adapter *adapter = netdev_priv(netdev);
7038 struct e1000_hw *hw = &adapter->hw;
7039 u32 err;
7040
7041 pci_set_power_state(pdev, PCI_D0);
7042 pci_restore_state(pdev);
b94f2d77 7043 pci_save_state(pdev);
42bfd33a 7044
aed5dec3 7045 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7046 if (err) {
7047 dev_err(&pdev->dev,
7048 "igb: Cannot enable PCI device from suspend\n");
7049 return err;
7050 }
7051 pci_set_master(pdev);
7052
7053 pci_enable_wake(pdev, PCI_D3hot, 0);
7054 pci_enable_wake(pdev, PCI_D3cold, 0);
7055
53c7d064 7056 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7057 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7058 return -ENOMEM;
9d5c8243
AK		 7059 }
7060
9d5c8243 7061 igb_reset(adapter);
a8564f03
AD		 7062
7063 /* let the f/w know that the h/w is now under the control of the
7064 * driver. */
7065 igb_get_hw_control(adapter);
7066
9d5c8243
AK		 7067 wr32(E1000_WUS, ~0);
7068
749ab2cd 7069 if (netdev->flags & IFF_UP) {
0c2cc02e 7070 rtnl_lock();
749ab2cd 7071 err = __igb_open(netdev, true);
0c2cc02e 7072 rtnl_unlock();
a88f10ec
AD		 7073 if (err)
7074 return err;
7075 }
9d5c8243
AK		 7076
7077 netif_device_attach(netdev);
749ab2cd
YZ		 7078 return 0;
7079}
7080
7081#ifdef CONFIG_PM_RUNTIME
7082static int igb_runtime_idle(struct device *dev)
7083{
7084 struct pci_dev *pdev = to_pci_dev(dev);
7085 struct net_device *netdev = pci_get_drvdata(pdev);
7086 struct igb_adapter *adapter = netdev_priv(netdev);
7087
7088 if (!igb_has_link(adapter))
7089 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7090
7091 return -EBUSY;
7092}
7093
7094static int igb_runtime_suspend(struct device *dev)
7095{
7096 struct pci_dev *pdev = to_pci_dev(dev);
7097 int retval;
7098 bool wake;
7099
7100 retval = __igb_shutdown(pdev, &wake, 1);
7101 if (retval)
7102 return retval;
7103
7104 if (wake) {
7105 pci_prepare_to_sleep(pdev);
7106 } else {
7107 pci_wake_from_d3(pdev, false);
7108 pci_set_power_state(pdev, PCI_D3hot);
7109 }
9d5c8243 7110
9d5c8243
AK		 7111 return 0;
7112}
749ab2cd
YZ		 7113
7114static int igb_runtime_resume(struct device *dev)
7115{
7116 return igb_resume(dev);
7117}
7118#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7119#endif
7120
7121static void igb_shutdown(struct pci_dev *pdev)
7122{
3fe7c4c9
RW		 7123 bool wake;
7124
749ab2cd 7125 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7126
7127 if (system_state == SYSTEM_POWER_OFF) {
7128 pci_wake_from_d3(pdev, wake);
7129 pci_set_power_state(pdev, PCI_D3hot);
7130 }
9d5c8243
AK		 7131}
7132
fa44f2f1
GR		 7133#ifdef CONFIG_PCI_IOV
7134static int igb_sriov_reinit(struct pci_dev *dev)
7135{
7136 struct net_device *netdev = pci_get_drvdata(dev);
7137 struct igb_adapter *adapter = netdev_priv(netdev);
7138 struct pci_dev *pdev = adapter->pdev;
7139
7140 rtnl_lock();
7141
7142 if (netif_running(netdev))
7143 igb_close(netdev);
7144
7145 igb_clear_interrupt_scheme(adapter);
7146
7147 igb_init_queue_configuration(adapter);
7148
7149 if (igb_init_interrupt_scheme(adapter, true)) {
7150 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7151 return -ENOMEM;
7152 }
7153
7154 if (netif_running(netdev))
7155 igb_open(netdev);
7156
7157 rtnl_unlock();
7158
7159 return 0;
7160}
7161
7162static int igb_pci_disable_sriov(struct pci_dev *dev)
7163{
7164 int err = igb_disable_sriov(dev);
7165
7166 if (!err)
7167 err = igb_sriov_reinit(dev);
7168
7169 return err;
7170}
7171
7172static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7173{
7174 int err = igb_enable_sriov(dev, num_vfs);
7175
7176 if (err)
7177 goto out;
7178
7179 err = igb_sriov_reinit(dev);
7180 if (!err)
7181 return num_vfs;
7182
7183out:
7184 return err;
7185}
7186
7187#endif
7188static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7189{
7190#ifdef CONFIG_PCI_IOV
7191 if (num_vfs == 0)
7192 return igb_pci_disable_sriov(dev);
7193 else
7194 return igb_pci_enable_sriov(dev, num_vfs);
7195#endif
7196 return 0;
7197}
7198
9d5c8243
AK		 7199#ifdef CONFIG_NET_POLL_CONTROLLER
7200/*
7201 * Polling 'interrupt' - used by things like netconsole to send skbs
7202 * without having to re-enable interrupts. It's not called while
7203 * the interrupt routine is executing.
7204 */
7205static void igb_netpoll(struct net_device *netdev)
7206{
7207 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7208 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7209 struct igb_q_vector *q_vector;
9d5c8243 7210 int i;
9d5c8243 7211
047e0030 7212 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7213 q_vector = adapter->q_vector[i];
7214 if (adapter->msix_entries)
7215 wr32(E1000_EIMC, q_vector->eims_value);
7216 else
7217 igb_irq_disable(adapter);
047e0030 7218 napi_schedule(&q_vector->napi);
eebbbdba 7219 }
9d5c8243
AK		 7220}
7221#endif /* CONFIG_NET_POLL_CONTROLLER */
7222
7223/**
7224 * igb_io_error_detected - called when PCI error is detected
7225 * @pdev: Pointer to PCI device
7226 * @state: The current pci connection state
7227 *
7228 * This function is called after a PCI bus error affecting
7229 * this device has been detected.
7230 */
7231static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7232 pci_channel_state_t state)
7233{
7234 struct net_device *netdev = pci_get_drvdata(pdev);
7235 struct igb_adapter *adapter = netdev_priv(netdev);
7236
7237 netif_device_detach(netdev);
7238
59ed6eec
AD		 7239 if (state == pci_channel_io_perm_failure)
7240 return PCI_ERS_RESULT_DISCONNECT;
7241
9d5c8243
AK		 7242 if (netif_running(netdev))
7243 igb_down(adapter);
7244 pci_disable_device(pdev);
7245
7246 /* Request a slot slot reset. */
7247 return PCI_ERS_RESULT_NEED_RESET;
7248}
7249
7250/**
7251 * igb_io_slot_reset - called after the pci bus has been reset.
7252 * @pdev: Pointer to PCI device
7253 *
7254 * Restart the card from scratch, as if from a cold-boot. Implementation
7255 * resembles the first-half of the igb_resume routine.
7256 */
7257static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7258{
7259 struct net_device *netdev = pci_get_drvdata(pdev);
7260 struct igb_adapter *adapter = netdev_priv(netdev);
7261 struct e1000_hw *hw = &adapter->hw;
40a914fa 7262 pci_ers_result_t result;
42bfd33a 7263 int err;
9d5c8243 7264
aed5dec3 7265 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7266 dev_err(&pdev->dev,
7267 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7268 result = PCI_ERS_RESULT_DISCONNECT;
7269 } else {
7270 pci_set_master(pdev);
7271 pci_restore_state(pdev);
b94f2d77 7272 pci_save_state(pdev);
9d5c8243 7273
40a914fa
AD		 7274 pci_enable_wake(pdev, PCI_D3hot, 0);
7275 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7276
40a914fa
AD		 7277 igb_reset(adapter);
7278 wr32(E1000_WUS, ~0);
7279 result = PCI_ERS_RESULT_RECOVERED;
7280 }
9d5c8243 7281
ea943d41
JK		 7282 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7283 if (err) {
7284 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7285 "failed 0x%0x\n", err);
7286 /* non-fatal, continue */
7287 }
40a914fa
AD		 7288
7289 return result;
9d5c8243
AK		 7290}
7291
7292/**
7293 * igb_io_resume - called when traffic can start flowing again.
7294 * @pdev: Pointer to PCI device
7295 *
7296 * This callback is called when the error recovery driver tells us that
7297 * its OK to resume normal operation. Implementation resembles the
7298 * second-half of the igb_resume routine.
7299 */
7300static void igb_io_resume(struct pci_dev *pdev)
7301{
7302 struct net_device *netdev = pci_get_drvdata(pdev);
7303 struct igb_adapter *adapter = netdev_priv(netdev);
7304
9d5c8243
AK		 7305 if (netif_running(netdev)) {
7306 if (igb_up(adapter)) {
7307 dev_err(&pdev->dev, "igb_up failed after reset\n");
7308 return;
7309 }
7310 }
7311
7312 netif_device_attach(netdev);
7313
7314 /* let the f/w know that the h/w is now under the control of the
7315 * driver. */
7316 igb_get_hw_control(adapter);
9d5c8243
AK		 7317}
7318
26ad9178
AD		 7319static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7320 u8 qsel)
7321{
7322 u32 rar_low, rar_high;
7323 struct e1000_hw *hw = &adapter->hw;
7324
7325 /* HW expects these in little endian so we reverse the byte order
7326 * from network order (big endian) to little endian
7327 */
7328 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7329 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7330 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7331
7332 /* Indicate to hardware the Address is Valid. */
7333 rar_high |= E1000_RAH_AV;
7334
7335 if (hw->mac.type == e1000_82575)
7336 rar_high |= E1000_RAH_POOL_1 * qsel;
7337 else
7338 rar_high |= E1000_RAH_POOL_1 << qsel;
7339
7340 wr32(E1000_RAL(index), rar_low);
7341 wrfl();
7342 wr32(E1000_RAH(index), rar_high);
7343 wrfl();
7344}
7345
4ae196df
AD		 7346static int igb_set_vf_mac(struct igb_adapter *adapter,
7347 int vf, unsigned char *mac_addr)
7348{
7349 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7350 /* VF MAC addresses start at end of receive addresses and moves
7351 * torwards the first, as a result a collision should not be possible */
7352 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7353
37680117 7354 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7355
26ad9178 7356 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7357
7358 return 0;
7359}
7360
8151d294
WM		 7361static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7362{
7363 struct igb_adapter *adapter = netdev_priv(netdev);
7364 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7365 return -EINVAL;
7366 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7367 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7368 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7369 " change effective.");
7370 if (test_bit(__IGB_DOWN, &adapter->state)) {
7371 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7372 " but the PF device is not up.\n");
7373 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7374 " attempting to use the VF device.\n");
7375 }
7376 return igb_set_vf_mac(adapter, vf, mac);
7377}
7378
17dc566c
LL		 7379static int igb_link_mbps(int internal_link_speed)
7380{
7381 switch (internal_link_speed) {
7382 case SPEED_100:
7383 return 100;
7384 case SPEED_1000:
7385 return 1000;
7386 default:
7387 return 0;
7388 }
7389}
7390
7391static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7392 int link_speed)
7393{
7394 int rf_dec, rf_int;
7395 u32 bcnrc_val;
7396
7397 if (tx_rate != 0) {
7398 /* Calculate the rate factor values to set */
7399 rf_int = link_speed / tx_rate;
7400 rf_dec = (link_speed - (rf_int * tx_rate));
7401 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7402
7403 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7404 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7405 E1000_RTTBCNRC_RF_INT_MASK);
7406 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7407 } else {
7408 bcnrc_val = 0;
7409 }
7410
7411 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7412 /*
7413 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7414 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7415 */
7416 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7417 wr32(E1000_RTTBCNRC, bcnrc_val);
7418}
7419
7420static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7421{
7422 int actual_link_speed, i;
7423 bool reset_rate = false;
7424
7425 /* VF TX rate limit was not set or not supported */
7426 if ((adapter->vf_rate_link_speed == 0) ||
7427 (adapter->hw.mac.type != e1000_82576))
7428 return;
7429
7430 actual_link_speed = igb_link_mbps(adapter->link_speed);
7431 if (actual_link_speed != adapter->vf_rate_link_speed) {
7432 reset_rate = true;
7433 adapter->vf_rate_link_speed = 0;
7434 dev_info(&adapter->pdev->dev,
7435 "Link speed has been changed. VF Transmit "
7436 "rate is disabled\n");
7437 }
7438
7439 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7440 if (reset_rate)
7441 adapter->vf_data[i].tx_rate = 0;
7442
7443 igb_set_vf_rate_limit(&adapter->hw, i,
7444 adapter->vf_data[i].tx_rate,
7445 actual_link_speed);
7446 }
7447}
7448
8151d294
WM		 7449static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7450{
17dc566c
LL		 7451 struct igb_adapter *adapter = netdev_priv(netdev);
7452 struct e1000_hw *hw = &adapter->hw;
7453 int actual_link_speed;
7454
7455 if (hw->mac.type != e1000_82576)
7456 return -EOPNOTSUPP;
7457
7458 actual_link_speed = igb_link_mbps(adapter->link_speed);
7459 if ((vf >= adapter->vfs_allocated_count) ||
7460 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7461 (tx_rate < 0) || (tx_rate > actual_link_speed))
7462 return -EINVAL;
7463
7464 adapter->vf_rate_link_speed = actual_link_speed;
7465 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7466 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7467
7468 return 0;
8151d294
WM		 7469}
7470
7471static int igb_ndo_get_vf_config(struct net_device *netdev,
7472 int vf, struct ifla_vf_info *ivi)
7473{
7474 struct igb_adapter *adapter = netdev_priv(netdev);
7475 if (vf >= adapter->vfs_allocated_count)
7476 return -EINVAL;
7477 ivi->vf = vf;
7478 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7479 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7480 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7481 ivi->qos = adapter->vf_data[vf].pf_qos;
7482 return 0;
7483}
7484
4ae196df
AD		 7485static void igb_vmm_control(struct igb_adapter *adapter)
7486{
7487 struct e1000_hw *hw = &adapter->hw;
10d8e907 7488 u32 reg;
4ae196df 7489
52a1dd4d
AD		 7490 switch (hw->mac.type) {
7491 case e1000_82575:
f96a8a0b
CW		 7492 case e1000_i210:
7493 case e1000_i211:
52a1dd4d
AD		 7494 default:
7495 /* replication is not supported for 82575 */
4ae196df 7496 return;
52a1dd4d
AD		 7497 case e1000_82576:
7498 /* notify HW that the MAC is adding vlan tags */
7499 reg = rd32(E1000_DTXCTL);
7500 reg |= E1000_DTXCTL_VLAN_ADDED;
7501 wr32(E1000_DTXCTL, reg);
7502 case e1000_82580:
7503 /* enable replication vlan tag stripping */
7504 reg = rd32(E1000_RPLOLR);
7505 reg |= E1000_RPLOLR_STRVLAN;
7506 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7507 case e1000_i350:
7508 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7509 break;
7510 }
10d8e907 7511
d4960307
AD		 7512 if (adapter->vfs_allocated_count) {
7513 igb_vmdq_set_loopback_pf(hw, true);
7514 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7515 igb_vmdq_set_anti_spoofing_pf(hw, true,
7516 adapter->vfs_allocated_count);
d4960307
AD		 7517 } else {
7518 igb_vmdq_set_loopback_pf(hw, false);
7519 igb_vmdq_set_replication_pf(hw, false);
7520 }
4ae196df
AD		 7521}
7522
b6e0c419
CW		 7523static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7524{
7525 struct e1000_hw *hw = &adapter->hw;
7526 u32 dmac_thr;
7527 u16 hwm;
7528
7529 if (hw->mac.type > e1000_82580) {
7530 if (adapter->flags & IGB_FLAG_DMAC) {
7531 u32 reg;
7532
7533 /* force threshold to 0. */
7534 wr32(E1000_DMCTXTH, 0);
7535
7536 /*
e8c626e9
MV		 7537 * DMA Coalescing high water mark needs to be greater
7538 * than the Rx threshold. Set hwm to PBA - max frame
7539 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7540 */
e8c626e9
MV		 7541 hwm = 64 * pba - adapter->max_frame_size / 16;
7542 if (hwm < 64 * (pba - 6))
7543 hwm = 64 * (pba - 6);
7544 reg = rd32(E1000_FCRTC);
7545 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7546 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7547 & E1000_FCRTC_RTH_COAL_MASK);
7548 wr32(E1000_FCRTC, reg);
7549
7550 /*
7551 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7552 * frame size, capping it at PBA - 10KB.
7553 */
7554 dmac_thr = pba - adapter->max_frame_size / 512;
7555 if (dmac_thr < pba - 10)
7556 dmac_thr = pba - 10;
b6e0c419
CW		 7557 reg = rd32(E1000_DMACR);
7558 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7559 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7560 & E1000_DMACR_DMACTHR_MASK);
7561
7562 /* transition to L0x or L1 if available..*/
7563 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7564
7565 /* watchdog timer= +-1000 usec in 32usec intervals */
7566 reg |= (1000 >> 5);
0c02dd98
MV		 7567
7568 /* Disable BMC-to-OS Watchdog Enable */
7569 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7570 wr32(E1000_DMACR, reg);
7571
7572 /*
7573 * no lower threshold to disable
7574 * coalescing(smart fifb)-UTRESH=0
7575 */
7576 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7577
7578 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7579
7580 wr32(E1000_DMCTLX, reg);
7581
7582 /*
7583 * free space in tx packet buffer to wake from
7584 * DMA coal
7585 */
7586 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7587 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7588
7589 /*
7590 * make low power state decision controlled
7591 * by DMA coal
7592 */
7593 reg = rd32(E1000_PCIEMISC);
7594 reg &= ~E1000_PCIEMISC_LX_DECISION;
7595 wr32(E1000_PCIEMISC, reg);
7596 } /* endif adapter->dmac is not disabled */
7597 } else if (hw->mac.type == e1000_82580) {
7598 u32 reg = rd32(E1000_PCIEMISC);
7599 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7600 wr32(E1000_DMACR, 0);
7601 }
7602}
7603
441fc6fd
CW		 7604static DEFINE_SPINLOCK(i2c_clients_lock);
7605
7606/* igb_get_i2c_client - returns matching client
7607 * in adapters's client list.
7608 * @adapter: adapter struct
7609 * @dev_addr: device address of i2c needed.
7610 */
7611struct i2c_client *
7612igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr)
7613{
7614 ulong flags;
7615 struct igb_i2c_client_list *client_list;
7616 struct i2c_client *client = NULL;
7617 struct i2c_board_info client_info = {
7618 I2C_BOARD_INFO("igb", 0x00),
7619 };
7620
7621 spin_lock_irqsave(&i2c_clients_lock, flags);
7622 client_list = adapter->i2c_clients;
7623
7624 /* See if we already have an i2c_client */
7625 while (client_list) {
7626 if (client_list->client->addr == (dev_addr >> 1)) {
7627 client = client_list->client;
7628 goto exit;
7629 } else {
7630 client_list = client_list->next;
7631 }
7632 }
7633
e428893b
CW		 7634 /* no client_list found, create a new one as long as
7635 * irqs are not disabled
7636 */
7637 if (unlikely(irqs_disabled()))
7638 goto exit;
7639
441fc6fd
CW		 7640 client_list = kzalloc(sizeof(*client_list), GFP_KERNEL);
7641 if (client_list == NULL)
7642 goto exit;
7643
7644 /* dev_addr passed to us is left-shifted by 1 bit
7645 * i2c_new_device call expects it to be flush to the right.
7646 */
7647 client_info.addr = dev_addr >> 1;
7648 client_info.platform_data = adapter;
7649 client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info);
7650 if (client_list->client == NULL) {
e428893b
CW		 7651 dev_info(&adapter->pdev->dev,
7652 "Failed to create new i2c device..\n");
441fc6fd
CW		 7653 goto err_no_client;
7654 }
7655
7656 /* insert new client at head of list */
7657 client_list->next = adapter->i2c_clients;
7658 adapter->i2c_clients = client_list;
7659
441fc6fd
CW		 7660 client = client_list->client;
7661 goto exit;
7662
7663err_no_client:
7664 kfree(client_list);
7665exit:
7666 spin_unlock_irqrestore(&i2c_clients_lock, flags);
7667 return client;
7668}
7669
7670/* igb_read_i2c_byte - Reads 8 bit word over I2C
7671 * @hw: pointer to hardware structure
7672 * @byte_offset: byte offset to read
7673 * @dev_addr: device address
7674 * @data: value read
7675 *
7676 * Performs byte read operation over I2C interface at
7677 * a specified device address.
7678 */
7679s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7680 u8 dev_addr, u8 *data)
7681{
7682 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7683 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7684 s32 status;
7685 u16 swfw_mask = 0;
7686
7687 if (!this_client)
7688 return E1000_ERR_I2C;
7689
7690 swfw_mask = E1000_SWFW_PHY0_SM;
7691
7692 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7693 != E1000_SUCCESS)
7694 return E1000_ERR_SWFW_SYNC;
7695
7696 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7697 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7698
7699 if (status < 0)
7700 return E1000_ERR_I2C;
7701 else {
7702 *data = status;
7703 return E1000_SUCCESS;
7704 }
7705}
7706
7707/* igb_write_i2c_byte - Writes 8 bit word over I2C
7708 * @hw: pointer to hardware structure
7709 * @byte_offset: byte offset to write
7710 * @dev_addr: device address
7711 * @data: value to write
7712 *
7713 * Performs byte write operation over I2C interface at
7714 * a specified device address.
7715 */
7716s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7717 u8 dev_addr, u8 data)
7718{
7719 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7720 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7721 s32 status;
7722 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7723
7724 if (!this_client)
7725 return E1000_ERR_I2C;
7726
7727 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7728 return E1000_ERR_SWFW_SYNC;
7729 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7730 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7731
7732 if (status)
7733 return E1000_ERR_I2C;
7734 else
7735 return E1000_SUCCESS;
7736
7737}
9d5c8243 7738/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)