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net: init perm_addr in register_netdevice()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
9d5c8243
AK		 60#include "igb.h"
61
200e5fd5 62#define MAJ 4
6699938b
CW		 63#define MIN 1
64#define BUILD 2
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 72
9d5c8243
AK		 73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
a3aa1884 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 119static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 121static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
53c7d064 125static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 126static void igb_configure_tx(struct igb_adapter *);
127static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 128static void igb_clean_all_tx_rings(struct igb_adapter *);
129static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 130static void igb_clean_tx_ring(struct igb_ring *);
131static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 132static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 133static void igb_update_phy_info(unsigned long);
134static void igb_watchdog(unsigned long);
135static void igb_watchdog_task(struct work_struct *);
cd392f5c 136static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
138 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 139static int igb_change_mtu(struct net_device *, int);
140static int igb_set_mac(struct net_device *, void *);
68d480c4 141static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 142static irqreturn_t igb_intr(int irq, void *);
143static irqreturn_t igb_intr_msi(int irq, void *);
144static irqreturn_t igb_msix_other(int irq, void *);
047e0030 145static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 146#ifdef CONFIG_IGB_DCA
047e0030 147static void igb_update_dca(struct igb_q_vector *);
fe4506b6 148static void igb_setup_dca(struct igb_adapter *);
421e02f0 149#endif /* CONFIG_IGB_DCA */
661086df 150static int igb_poll(struct napi_struct *, int);
13fde97a 151static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 152static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 153static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
154static void igb_tx_timeout(struct net_device *);
155static void igb_reset_task(struct work_struct *);
c8f44aff 156static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 157static int igb_vlan_rx_add_vid(struct net_device *, u16);
158static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 159static void igb_restore_vlan(struct igb_adapter *);
26ad9178 160static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 161static void igb_ping_all_vfs(struct igb_adapter *);
162static void igb_msg_task(struct igb_adapter *);
4ae196df 163static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 164static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 165static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 166static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
167static int igb_ndo_set_vf_vlan(struct net_device *netdev,
168 int vf, u16 vlan, u8 qos);
169static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
17dc566c 172static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 173
174#ifdef CONFIG_PCI_IOV
0224d663 175static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 176static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 177#endif
9d5c8243 178
9d5c8243 179#ifdef CONFIG_PM
d9dd966d 180#ifdef CONFIG_PM_SLEEP
749ab2cd 181static int igb_suspend(struct device *);
d9dd966d 182#endif
749ab2cd
YZ		 183static int igb_resume(struct device *);
184#ifdef CONFIG_PM_RUNTIME
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188#endif
189static const struct dev_pm_ops igb_pm_ops = {
190 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
191 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
192 igb_runtime_idle)
193};
9d5c8243
AK		 194#endif
195static void igb_shutdown(struct pci_dev *);
421e02f0 196#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 197static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
198static struct notifier_block dca_notifier = {
199 .notifier_call = igb_notify_dca,
200 .next = NULL,
201 .priority = 0
202};
203#endif
9d5c8243
AK		 204#ifdef CONFIG_NET_POLL_CONTROLLER
205/* for netdump / net console */
206static void igb_netpoll(struct net_device *);
207#endif
37680117 208#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 209static unsigned int max_vfs = 0;
210module_param(max_vfs, uint, 0);
211MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
212 "per physical function");
213#endif /* CONFIG_PCI_IOV */
214
9d5c8243
AK		 215static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
216 pci_channel_state_t);
217static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
218static void igb_io_resume(struct pci_dev *);
219
3646f0e5 220static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 221 .error_detected = igb_io_error_detected,
222 .slot_reset = igb_io_slot_reset,
223 .resume = igb_io_resume,
224};
225
b6e0c419 226static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 227
228static struct pci_driver igb_driver = {
229 .name = igb_driver_name,
230 .id_table = igb_pci_tbl,
231 .probe = igb_probe,
9f9a12f8 232 .remove = igb_remove,
9d5c8243 233#ifdef CONFIG_PM
749ab2cd 234 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 235#endif
236 .shutdown = igb_shutdown,
237 .err_handler = &igb_err_handler
238};
239
240MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
241MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
242MODULE_LICENSE("GPL");
243MODULE_VERSION(DRV_VERSION);
244
b3f4d599 245#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
246static int debug = -1;
247module_param(debug, int, 0);
248MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
249
c97ec42a
TI		 250struct igb_reg_info {
251 u32 ofs;
252 char *name;
253};
254
255static const struct igb_reg_info igb_reg_info_tbl[] = {
256
257 /* General Registers */
258 {E1000_CTRL, "CTRL"},
259 {E1000_STATUS, "STATUS"},
260 {E1000_CTRL_EXT, "CTRL_EXT"},
261
262 /* Interrupt Registers */
263 {E1000_ICR, "ICR"},
264
265 /* RX Registers */
266 {E1000_RCTL, "RCTL"},
267 {E1000_RDLEN(0), "RDLEN"},
268 {E1000_RDH(0), "RDH"},
269 {E1000_RDT(0), "RDT"},
270 {E1000_RXDCTL(0), "RXDCTL"},
271 {E1000_RDBAL(0), "RDBAL"},
272 {E1000_RDBAH(0), "RDBAH"},
273
274 /* TX Registers */
275 {E1000_TCTL, "TCTL"},
276 {E1000_TDBAL(0), "TDBAL"},
277 {E1000_TDBAH(0), "TDBAH"},
278 {E1000_TDLEN(0), "TDLEN"},
279 {E1000_TDH(0), "TDH"},
280 {E1000_TDT(0), "TDT"},
281 {E1000_TXDCTL(0), "TXDCTL"},
282 {E1000_TDFH, "TDFH"},
283 {E1000_TDFT, "TDFT"},
284 {E1000_TDFHS, "TDFHS"},
285 {E1000_TDFPC, "TDFPC"},
286
287 /* List Terminator */
288 {}
289};
290
291/*
292 * igb_regdump - register printout routine
293 */
294static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
295{
296 int n = 0;
297 char rname[16];
298 u32 regs[8];
299
300 switch (reginfo->ofs) {
301 case E1000_RDLEN(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDLEN(n));
304 break;
305 case E1000_RDH(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDH(n));
308 break;
309 case E1000_RDT(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDT(n));
312 break;
313 case E1000_RXDCTL(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RXDCTL(n));
316 break;
317 case E1000_RDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDBAL(n));
320 break;
321 case E1000_RDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAH(n));
324 break;
325 case E1000_TDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_TDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDBAH(n));
332 break;
333 case E1000_TDLEN(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDLEN(n));
336 break;
337 case E1000_TDH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDH(n));
340 break;
341 case E1000_TDT(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDT(n));
344 break;
345 case E1000_TXDCTL(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TXDCTL(n));
348 break;
349 default:
876d2d6f 350 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 351 return;
352 }
353
354 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 355 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
356 regs[2], regs[3]);
c97ec42a
TI		 357}
358
359/*
360 * igb_dump - Print registers, tx-rings and rx-rings
361 */
362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
c97ec42a
TI		 367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
6ad4edfc 373 u16 i, n;
c97ec42a
TI		 374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 381 pr_info("Device Name state trans_start "
382 "last_rx\n");
383 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
384 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 385 }
386
387 /* Print Registers */
388 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 389 pr_info(" Register Name Value\n");
c97ec42a
TI		 390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
391 reginfo->name; reginfo++) {
392 igb_regdump(hw, reginfo);
393 }
394
395 /* Print TX Ring Summary */
396 if (!netdev || !netif_running(netdev))
397 goto exit;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 401 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 402 struct igb_tx_buffer *buffer_info;
c97ec42a 403 tx_ring = adapter->tx_ring[n];
06034649 404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
406 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 407 (u64)dma_unmap_addr(buffer_info, dma),
408 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 409 buffer_info->next_to_watch,
410 (u64)buffer_info->time_stamp);
c97ec42a
TI		 411 }
412
413 /* Print TX Rings */
414 if (!netif_msg_tx_done(adapter))
415 goto rx_ring_summary;
416
417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
418
419 /* Transmit Descriptor Formats
420 *
421 * Advanced Transmit Descriptor
422 * +--------------------------------------------------------------+
423 * 0 | Buffer Address [63:0] |
424 * +--------------------------------------------------------------+
425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
426 * +--------------------------------------------------------------+
427 * 63 46 45 40 39 38 36 35 32 31 24 15 0
428 */
429
430 for (n = 0; n < adapter->num_tx_queues; n++) {
431 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 432 pr_info("------------------------------------\n");
433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
434 pr_info("------------------------------------\n");
435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
436 "[bi->dma ] leng ntw timestamp "
437 "bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
455 pr_info("T [0x%03X] %016llX %016llX %016llX"
456 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
c9f14bf3
AD		 459 (u64)dma_unmap_addr(buffer_info, dma),
460 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 461 buffer_info->next_to_watch,
462 (u64)buffer_info->time_stamp,
876d2d6f 463 buffer_info->skb, next_desc);
c97ec42a 464
b669588a 465 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 466 print_hex_dump(KERN_INFO, "",
467 DUMP_PREFIX_ADDRESS,
b669588a 468 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 469 dma_unmap_len(buffer_info, len),
470 true);
c97ec42a
TI		 471 }
472 }
473
474 /* Print RX Rings Summary */
475rx_ring_summary:
476 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 477 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 478 for (n = 0; n < adapter->num_rx_queues; n++) {
479 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 480 pr_info(" %5d %5X %5X\n",
481 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 482 }
483
484 /* Print RX Rings */
485 if (!netif_msg_rx_status(adapter))
486 goto exit;
487
488 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
489
490 /* Advanced Receive Descriptor (Read) Format
491 * 63 1 0
492 * +-----------------------------------------------------+
493 * 0 | Packet Buffer Address [63:1] |A0/NSE|
494 * +----------------------------------------------+------+
495 * 8 | Header Buffer Address [63:1] | DD |
496 * +-----------------------------------------------------+
497 *
498 *
499 * Advanced Receive Descriptor (Write-Back) Format
500 *
501 * 63 48 47 32 31 30 21 20 17 16 4 3 0
502 * +------------------------------------------------------+
503 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
504 * | Checksum Ident | | | | Type | Type |
505 * +------------------------------------------------------+
506 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
507 * +------------------------------------------------------+
508 * 63 48 47 32 31 20 19 0
509 */
510
511 for (n = 0; n < adapter->num_rx_queues; n++) {
512 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 513 pr_info("------------------------------------\n");
514 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
515 pr_info("------------------------------------\n");
516 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
517 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
519 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 520
521 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 522 const char *next_desc;
06034649
AD		 523 struct igb_rx_buffer *buffer_info;
524 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 525 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 526 u0 = (struct my_u0 *)rx_desc;
527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 528
529 if (i == rx_ring->next_to_use)
530 next_desc = " NTU";
531 else if (i == rx_ring->next_to_clean)
532 next_desc = " NTC";
533 else
534 next_desc = "";
535
c97ec42a
TI		 536 if (staterr & E1000_RXD_STAT_DD) {
537 /* Descriptor Done */
1a1c225b
AD		 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
539 "RWB", i,
c97ec42a
TI		 540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
1a1c225b 542 next_desc);
c97ec42a 543 } else {
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
545 "R ", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
548 (u64)buffer_info->dma,
1a1c225b 549 next_desc);
c97ec42a 550
b669588a 551 if (netif_msg_pktdata(adapter) &&
1a1c225b 552 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 553 print_hex_dump(KERN_INFO, "",
554 DUMP_PREFIX_ADDRESS,
555 16, 1,
b669588a
ET		 556 page_address(buffer_info->page) +
557 buffer_info->page_offset,
de78d1f9 558 IGB_RX_BUFSZ, true);
c97ec42a
TI		 559 }
560 }
c97ec42a
TI		 561 }
562 }
563
564exit:
565 return;
566}
567
9d5c8243 568/**
c041076a 569 * igb_get_hw_dev - return device
9d5c8243
AK		 570 * used by hardware layer to print debugging information
571 **/
c041076a 572struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 573{
574 struct igb_adapter *adapter = hw->back;
c041076a 575 return adapter->netdev;
9d5c8243 576}
38c845c7 577
9d5c8243
AK		 578/**
579 * igb_init_module - Driver Registration Routine
580 *
581 * igb_init_module is the first routine called when the driver is
582 * loaded. All it does is register with the PCI subsystem.
583 **/
584static int __init igb_init_module(void)
585{
586 int ret;
876d2d6f 587 pr_info("%s - version %s\n",
9d5c8243
AK		 588 igb_driver_string, igb_driver_version);
589
876d2d6f 590 pr_info("%s\n", igb_copyright);
9d5c8243 591
421e02f0 592#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 593 dca_register_notify(&dca_notifier);
594#endif
bbd98fe4 595 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 596 return ret;
597}
598
599module_init(igb_init_module);
600
601/**
602 * igb_exit_module - Driver Exit Cleanup Routine
603 *
604 * igb_exit_module is called just before the driver is removed
605 * from memory.
606 **/
607static void __exit igb_exit_module(void)
608{
421e02f0 609#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 610 dca_unregister_notify(&dca_notifier);
611#endif
9d5c8243
AK		 612 pci_unregister_driver(&igb_driver);
613}
614
615module_exit(igb_exit_module);
616
26bc19ec
AD		 617#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
618/**
619 * igb_cache_ring_register - Descriptor ring to register mapping
620 * @adapter: board private structure to initialize
621 *
622 * Once we know the feature-set enabled for the device, we'll cache
623 * the register offset the descriptor ring is assigned to.
624 **/
625static void igb_cache_ring_register(struct igb_adapter *adapter)
626{
ee1b9f06 627 int i = 0, j = 0;
047e0030 628 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 629
630 switch (adapter->hw.mac.type) {
631 case e1000_82576:
632 /* The queues are allocated for virtualization such that VF 0
633 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
634 * In order to avoid collision we start at the first free queue
635 * and continue consuming queues in the same sequence
636 */
ee1b9f06 637 if (adapter->vfs_allocated_count) {
a99955fc 638 for (; i < adapter->rss_queues; i++)
3025a446
AD		 639 adapter->rx_ring[i]->reg_idx = rbase_offset +
640 Q_IDX_82576(i);
ee1b9f06 641 }
26bc19ec 642 case e1000_82575:
55cac248 643 case e1000_82580:
d2ba2ed8 644 case e1000_i350:
f96a8a0b
CW		 645 case e1000_i210:
646 case e1000_i211:
26bc19ec 647 default:
ee1b9f06 648 for (; i < adapter->num_rx_queues; i++)
3025a446 649 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 650 for (; j < adapter->num_tx_queues; j++)
3025a446 651 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 652 break;
653 }
654}
655
4be000c8
AD		 656/**
657 * igb_write_ivar - configure ivar for given MSI-X vector
658 * @hw: pointer to the HW structure
659 * @msix_vector: vector number we are allocating to a given ring
660 * @index: row index of IVAR register to write within IVAR table
661 * @offset: column offset of in IVAR, should be multiple of 8
662 *
663 * This function is intended to handle the writing of the IVAR register
664 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
665 * each containing an cause allocation for an Rx and Tx ring, and a
666 * variable number of rows depending on the number of queues supported.
667 **/
668static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
669 int index, int offset)
670{
671 u32 ivar = array_rd32(E1000_IVAR0, index);
672
673 /* clear any bits that are currently set */
674 ivar &= ~((u32)0xFF << offset);
675
676 /* write vector and valid bit */
677 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
678
679 array_wr32(E1000_IVAR0, index, ivar);
680}
681
9d5c8243 682#define IGB_N0_QUEUE -1
047e0030 683static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 684{
047e0030 685 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 686 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 687 int rx_queue = IGB_N0_QUEUE;
688 int tx_queue = IGB_N0_QUEUE;
4be000c8 689 u32 msixbm = 0;
047e0030 690
0ba82994
AD		 691 if (q_vector->rx.ring)
692 rx_queue = q_vector->rx.ring->reg_idx;
693 if (q_vector->tx.ring)
694 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 695
696 switch (hw->mac.type) {
697 case e1000_82575:
9d5c8243
AK		 698 /* The 82575 assigns vectors using a bitmask, which matches the
699 bitmask for the EICR/EIMS/EIMC registers. To assign one
700 or more queues to a vector, we write the appropriate bits
701 into the MSIXBM register for that vector. */
047e0030 702 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 703 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 704 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 705 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 706 if (!adapter->msix_entries && msix_vector == 0)
707 msixbm |= E1000_EIMS_OTHER;
9d5c8243 708 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 709 q_vector->eims_value = msixbm;
2d064c06
AD		 710 break;
711 case e1000_82576:
4be000c8
AD		 712 /*
713 * 82576 uses a table that essentially consists of 2 columns
714 * with 8 rows. The ordering is column-major so we use the
715 * lower 3 bits as the row index, and the 4th bit as the
716 * column offset.
717 */
718 if (rx_queue > IGB_N0_QUEUE)
719 igb_write_ivar(hw, msix_vector,
720 rx_queue & 0x7,
721 (rx_queue & 0x8) << 1);
722 if (tx_queue > IGB_N0_QUEUE)
723 igb_write_ivar(hw, msix_vector,
724 tx_queue & 0x7,
725 ((tx_queue & 0x8) << 1) + 8);
047e0030 726 q_vector->eims_value = 1 << msix_vector;
2d064c06 727 break;
55cac248 728 case e1000_82580:
d2ba2ed8 729 case e1000_i350:
f96a8a0b
CW		 730 case e1000_i210:
731 case e1000_i211:
4be000c8
AD		 732 /*
733 * On 82580 and newer adapters the scheme is similar to 82576
734 * however instead of ordering column-major we have things
735 * ordered row-major. So we traverse the table by using
736 * bit 0 as the column offset, and the remaining bits as the
737 * row index.
738 */
739 if (rx_queue > IGB_N0_QUEUE)
740 igb_write_ivar(hw, msix_vector,
741 rx_queue >> 1,
742 (rx_queue & 0x1) << 4);
743 if (tx_queue > IGB_N0_QUEUE)
744 igb_write_ivar(hw, msix_vector,
745 tx_queue >> 1,
746 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 747 q_vector->eims_value = 1 << msix_vector;
748 break;
2d064c06
AD		 749 default:
750 BUG();
751 break;
752 }
26b39276
AD		 753
754 /* add q_vector eims value to global eims_enable_mask */
755 adapter->eims_enable_mask |= q_vector->eims_value;
756
757 /* configure q_vector to set itr on first interrupt */
758 q_vector->set_itr = 1;
9d5c8243
AK		 759}
760
761/**
762 * igb_configure_msix - Configure MSI-X hardware
763 *
764 * igb_configure_msix sets up the hardware to properly
765 * generate MSI-X interrupts.
766 **/
767static void igb_configure_msix(struct igb_adapter *adapter)
768{
769 u32 tmp;
770 int i, vector = 0;
771 struct e1000_hw *hw = &adapter->hw;
772
773 adapter->eims_enable_mask = 0;
9d5c8243
AK		 774
775 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 776 switch (hw->mac.type) {
777 case e1000_82575:
9d5c8243
AK		 778 tmp = rd32(E1000_CTRL_EXT);
779 /* enable MSI-X PBA support*/
780 tmp |= E1000_CTRL_EXT_PBA_CLR;
781
782 /* Auto-Mask interrupts upon ICR read. */
783 tmp |= E1000_CTRL_EXT_EIAME;
784 tmp |= E1000_CTRL_EXT_IRCA;
785
786 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 787
788 /* enable msix_other interrupt */
789 array_wr32(E1000_MSIXBM(0), vector++,
790 E1000_EIMS_OTHER);
844290e5 791 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 792
2d064c06
AD		 793 break;
794
795 case e1000_82576:
55cac248 796 case e1000_82580:
d2ba2ed8 797 case e1000_i350:
f96a8a0b
CW		 798 case e1000_i210:
799 case e1000_i211:
047e0030
AD		 800 /* Turn on MSI-X capability first, or our settings
801 * won't stick. And it will take days to debug. */
802 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
803 E1000_GPIE_PBA | E1000_GPIE_EIAME |
804 E1000_GPIE_NSICR);
805
806 /* enable msix_other interrupt */
807 adapter->eims_other = 1 << vector;
2d064c06 808 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 809
047e0030 810 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 811 break;
812 default:
813 /* do nothing, since nothing else supports MSI-X */
814 break;
815 } /* switch (hw->mac.type) */
047e0030
AD		 816
817 adapter->eims_enable_mask |= adapter->eims_other;
818
26b39276
AD		 819 for (i = 0; i < adapter->num_q_vectors; i++)
820 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 821
9d5c8243
AK		 822 wrfl();
823}
824
825/**
826 * igb_request_msix - Initialize MSI-X interrupts
827 *
828 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
829 * kernel.
830 **/
831static int igb_request_msix(struct igb_adapter *adapter)
832{
833 struct net_device *netdev = adapter->netdev;
047e0030 834 struct e1000_hw *hw = &adapter->hw;
52285b76 835 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 836
047e0030 837 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 838 igb_msix_other, 0, netdev->name, adapter);
047e0030 839 if (err)
52285b76 840 goto err_out;
047e0030
AD		 841
842 for (i = 0; i < adapter->num_q_vectors; i++) {
843 struct igb_q_vector *q_vector = adapter->q_vector[i];
844
52285b76
SA		 845 vector++;
846
047e0030
AD		 847 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
848
0ba82994 849 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 850 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 851 q_vector->rx.ring->queue_index);
852 else if (q_vector->tx.ring)
047e0030 853 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 854 q_vector->tx.ring->queue_index);
855 else if (q_vector->rx.ring)
047e0030 856 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 857 q_vector->rx.ring->queue_index);
9d5c8243 858 else
047e0030
AD		 859 sprintf(q_vector->name, "%s-unused", netdev->name);
860
9d5c8243 861 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 862 igb_msix_ring, 0, q_vector->name,
047e0030 863 q_vector);
9d5c8243 864 if (err)
52285b76 865 goto err_free;
9d5c8243
AK		 866 }
867
9d5c8243
AK		 868 igb_configure_msix(adapter);
869 return 0;
52285b76
SA		 870
871err_free:
872 /* free already assigned IRQs */
873 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
874
875 vector--;
876 for (i = 0; i < vector; i++) {
877 free_irq(adapter->msix_entries[free_vector++].vector,
878 adapter->q_vector[i]);
879 }
880err_out:
9d5c8243
AK		 881 return err;
882}
883
884static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
885{
886 if (adapter->msix_entries) {
887 pci_disable_msix(adapter->pdev);
888 kfree(adapter->msix_entries);
889 adapter->msix_entries = NULL;
047e0030 890 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 891 pci_disable_msi(adapter->pdev);
047e0030 892 }
9d5c8243
AK		 893}
894
5536d210
AD		 895/**
896 * igb_free_q_vector - Free memory allocated for specific interrupt vector
897 * @adapter: board private structure to initialize
898 * @v_idx: Index of vector to be freed
899 *
900 * This function frees the memory allocated to the q_vector. In addition if
901 * NAPI is enabled it will delete any references to the NAPI struct prior
902 * to freeing the q_vector.
903 **/
904static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
905{
906 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
907
908 if (q_vector->tx.ring)
909 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
910
911 if (q_vector->rx.ring)
912 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
913
914 adapter->q_vector[v_idx] = NULL;
915 netif_napi_del(&q_vector->napi);
916
917 /*
918 * ixgbe_get_stats64() might access the rings on this vector,
919 * we must wait a grace period before freeing it.
920 */
921 kfree_rcu(q_vector, rcu);
922}
923
047e0030
AD		 924/**
925 * igb_free_q_vectors - Free memory allocated for interrupt vectors
926 * @adapter: board private structure to initialize
927 *
928 * This function frees the memory allocated to the q_vectors. In addition if
929 * NAPI is enabled it will delete any references to the NAPI struct prior
930 * to freeing the q_vector.
931 **/
932static void igb_free_q_vectors(struct igb_adapter *adapter)
933{
5536d210
AD		 934 int v_idx = adapter->num_q_vectors;
935
936 adapter->num_tx_queues = 0;
937 adapter->num_rx_queues = 0;
047e0030 938 adapter->num_q_vectors = 0;
5536d210
AD		 939
940 while (v_idx--)
941 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 942}
943
944/**
945 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
946 *
947 * This function resets the device so that it has 0 rx queues, tx queues, and
948 * MSI-X interrupts allocated.
949 */
950static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
951{
047e0030
AD		 952 igb_free_q_vectors(adapter);
953 igb_reset_interrupt_capability(adapter);
954}
9d5c8243
AK		 955
956/**
957 * igb_set_interrupt_capability - set MSI or MSI-X if supported
958 *
959 * Attempt to configure interrupts using the best available
960 * capabilities of the hardware and kernel.
961 **/
53c7d064 962static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 963{
964 int err;
965 int numvecs, i;
966
53c7d064
SA		 967 if (!msix)
968 goto msi_only;
969
83b7180d 970 /* Number of supported queues. */
a99955fc 971 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 972 if (adapter->vfs_allocated_count)
973 adapter->num_tx_queues = 1;
974 else
975 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 976
047e0030
AD		 977 /* start with one vector for every rx queue */
978 numvecs = adapter->num_rx_queues;
979
3ad2f3fb 980 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 981 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
982 numvecs += adapter->num_tx_queues;
047e0030
AD		 983
984 /* store the number of vectors reserved for queues */
985 adapter->num_q_vectors = numvecs;
986
987 /* add 1 vector for link status interrupts */
988 numvecs++;
9d5c8243
AK		 989 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
990 GFP_KERNEL);
f96a8a0b 991
9d5c8243
AK		 992 if (!adapter->msix_entries)
993 goto msi_only;
994
995 for (i = 0; i < numvecs; i++)
996 adapter->msix_entries[i].entry = i;
997
998 err = pci_enable_msix(adapter->pdev,
999 adapter->msix_entries,
1000 numvecs);
1001 if (err == 0)
0c2cc02e 1002 return;
9d5c8243
AK		 1003
1004 igb_reset_interrupt_capability(adapter);
1005
1006 /* If we can't do MSI-X, try MSI */
1007msi_only:
2a3abf6d
AD		 1008#ifdef CONFIG_PCI_IOV
1009 /* disable SR-IOV for non MSI-X configurations */
1010 if (adapter->vf_data) {
1011 struct e1000_hw *hw = &adapter->hw;
1012 /* disable iov and allow time for transactions to clear */
1013 pci_disable_sriov(adapter->pdev);
1014 msleep(500);
1015
1016 kfree(adapter->vf_data);
1017 adapter->vf_data = NULL;
1018 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1019 wrfl();
2a3abf6d
AD		 1020 msleep(100);
1021 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1022 }
1023#endif
4fc82adf 1024 adapter->vfs_allocated_count = 0;
a99955fc 1025 adapter->rss_queues = 1;
4fc82adf 1026 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1027 adapter->num_rx_queues = 1;
661086df 1028 adapter->num_tx_queues = 1;
047e0030 1029 adapter->num_q_vectors = 1;
9d5c8243 1030 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1031 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1032}
1033
5536d210
AD		 1034static void igb_add_ring(struct igb_ring *ring,
1035 struct igb_ring_container *head)
1036{
1037 head->ring = ring;
1038 head->count++;
1039}
1040
047e0030 1041/**
5536d210 1042 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1043 * @adapter: board private structure to initialize
5536d210
AD		 1044 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1045 * @v_idx: index of vector in adapter struct
1046 * @txr_count: total number of Tx rings to allocate
1047 * @txr_idx: index of first Tx ring to allocate
1048 * @rxr_count: total number of Rx rings to allocate
1049 * @rxr_idx: index of first Rx ring to allocate
047e0030 1050 *
5536d210 1051 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1052 **/
5536d210
AD		 1053static int igb_alloc_q_vector(struct igb_adapter *adapter,
1054 int v_count, int v_idx,
1055 int txr_count, int txr_idx,
1056 int rxr_count, int rxr_idx)
047e0030
AD		 1057{
1058 struct igb_q_vector *q_vector;
5536d210
AD		 1059 struct igb_ring *ring;
1060 int ring_count, size;
047e0030 1061
5536d210
AD		 1062 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1063 if (txr_count > 1 || rxr_count > 1)
1064 return -ENOMEM;
1065
1066 ring_count = txr_count + rxr_count;
1067 size = sizeof(struct igb_q_vector) +
1068 (sizeof(struct igb_ring) * ring_count);
1069
1070 /* allocate q_vector and rings */
1071 q_vector = kzalloc(size, GFP_KERNEL);
1072 if (!q_vector)
1073 return -ENOMEM;
1074
1075 /* initialize NAPI */
1076 netif_napi_add(adapter->netdev, &q_vector->napi,
1077 igb_poll, 64);
1078
1079 /* tie q_vector and adapter together */
1080 adapter->q_vector[v_idx] = q_vector;
1081 q_vector->adapter = adapter;
1082
1083 /* initialize work limits */
1084 q_vector->tx.work_limit = adapter->tx_work_limit;
1085
1086 /* initialize ITR configuration */
1087 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1088 q_vector->itr_val = IGB_START_ITR;
1089
1090 /* initialize pointer to rings */
1091 ring = q_vector->ring;
1092
1093 if (txr_count) {
1094 /* assign generic ring traits */
1095 ring->dev = &adapter->pdev->dev;
1096 ring->netdev = adapter->netdev;
1097
1098 /* configure backlink on ring */
1099 ring->q_vector = q_vector;
1100
1101 /* update q_vector Tx values */
1102 igb_add_ring(ring, &q_vector->tx);
1103
1104 /* For 82575, context index must be unique per ring. */
1105 if (adapter->hw.mac.type == e1000_82575)
1106 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1107
1108 /* apply Tx specific ring traits */
1109 ring->count = adapter->tx_ring_count;
1110 ring->queue_index = txr_idx;
1111
1112 /* assign ring to adapter */
1113 adapter->tx_ring[txr_idx] = ring;
1114
1115 /* push pointer to next ring */
1116 ring++;
047e0030 1117 }
81c2fc22 1118
5536d210
AD		 1119 if (rxr_count) {
1120 /* assign generic ring traits */
1121 ring->dev = &adapter->pdev->dev;
1122 ring->netdev = adapter->netdev;
047e0030 1123
5536d210
AD		 1124 /* configure backlink on ring */
1125 ring->q_vector = q_vector;
047e0030 1126
5536d210
AD		 1127 /* update q_vector Rx values */
1128 igb_add_ring(ring, &q_vector->rx);
047e0030 1129
5536d210
AD		 1130 /* set flag indicating ring supports SCTP checksum offload */
1131 if (adapter->hw.mac.type >= e1000_82576)
1132 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1133
5536d210
AD		 1134 /*
1135 * On i350, i210, and i211, loopback VLAN packets
1136 * have the tag byte-swapped.
1137 * */
1138 if (adapter->hw.mac.type >= e1000_i350)
1139 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1140
5536d210
AD		 1141 /* apply Rx specific ring traits */
1142 ring->count = adapter->rx_ring_count;
1143 ring->queue_index = rxr_idx;
1144
1145 /* assign ring to adapter */
1146 adapter->rx_ring[rxr_idx] = ring;
1147 }
1148
1149 return 0;
047e0030
AD		 1150}
1151
5536d210 1152
047e0030 1153/**
5536d210
AD		 1154 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1155 * @adapter: board private structure to initialize
047e0030 1156 *
5536d210
AD		 1157 * We allocate one q_vector per queue interrupt. If allocation fails we
1158 * return -ENOMEM.
047e0030 1159 **/
5536d210 1160static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1161{
5536d210
AD		 1162 int q_vectors = adapter->num_q_vectors;
1163 int rxr_remaining = adapter->num_rx_queues;
1164 int txr_remaining = adapter->num_tx_queues;
1165 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1166 int err;
047e0030 1167
5536d210
AD		 1168 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1169 for (; rxr_remaining; v_idx++) {
1170 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1171 0, 0, 1, rxr_idx);
047e0030 1172
5536d210
AD		 1173 if (err)
1174 goto err_out;
1175
1176 /* update counts and index */
1177 rxr_remaining--;
1178 rxr_idx++;
047e0030 1179 }
047e0030 1180 }
5536d210
AD		 1181
1182 for (; v_idx < q_vectors; v_idx++) {
1183 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1184 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1185 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1186 tqpv, txr_idx, rqpv, rxr_idx);
1187
1188 if (err)
1189 goto err_out;
1190
1191 /* update counts and index */
1192 rxr_remaining -= rqpv;
1193 txr_remaining -= tqpv;
1194 rxr_idx++;
1195 txr_idx++;
1196 }
1197
047e0030 1198 return 0;
5536d210
AD		 1199
1200err_out:
1201 adapter->num_tx_queues = 0;
1202 adapter->num_rx_queues = 0;
1203 adapter->num_q_vectors = 0;
1204
1205 while (v_idx--)
1206 igb_free_q_vector(adapter, v_idx);
1207
1208 return -ENOMEM;
047e0030
AD		 1209}
1210
1211/**
1212 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1213 *
1214 * This function initializes the interrupts and allocates all of the queues.
1215 **/
53c7d064 1216static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1217{
1218 struct pci_dev *pdev = adapter->pdev;
1219 int err;
1220
53c7d064 1221 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1222
1223 err = igb_alloc_q_vectors(adapter);
1224 if (err) {
1225 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1226 goto err_alloc_q_vectors;
1227 }
1228
5536d210 1229 igb_cache_ring_register(adapter);
047e0030
AD		 1230
1231 return 0;
5536d210 1232
047e0030
AD		 1233err_alloc_q_vectors:
1234 igb_reset_interrupt_capability(adapter);
1235 return err;
1236}
1237
9d5c8243
AK		 1238/**
1239 * igb_request_irq - initialize interrupts
1240 *
1241 * Attempts to configure interrupts using the best available
1242 * capabilities of the hardware and kernel.
1243 **/
1244static int igb_request_irq(struct igb_adapter *adapter)
1245{
1246 struct net_device *netdev = adapter->netdev;
047e0030 1247 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1248 int err = 0;
1249
1250 if (adapter->msix_entries) {
1251 err = igb_request_msix(adapter);
844290e5 1252 if (!err)
9d5c8243 1253 goto request_done;
9d5c8243 1254 /* fall back to MSI */
5536d210
AD		 1255 igb_free_all_tx_resources(adapter);
1256 igb_free_all_rx_resources(adapter);
53c7d064 1257
047e0030 1258 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1259 err = igb_init_interrupt_scheme(adapter, false);
1260 if (err)
047e0030 1261 goto request_done;
53c7d064 1262
047e0030
AD		 1263 igb_setup_all_tx_resources(adapter);
1264 igb_setup_all_rx_resources(adapter);
53c7d064 1265 igb_configure(adapter);
9d5c8243 1266 }
844290e5 1267
c74d588e
AD		 1268 igb_assign_vector(adapter->q_vector[0], 0);
1269
7dfc16fa 1270 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1271 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1272 netdev->name, adapter);
9d5c8243
AK		 1273 if (!err)
1274 goto request_done;
047e0030 1275
9d5c8243
AK		 1276 /* fall back to legacy interrupts */
1277 igb_reset_interrupt_capability(adapter);
7dfc16fa 1278 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1279 }
1280
c74d588e 1281 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1282 netdev->name, adapter);
9d5c8243 1283
6cb5e577 1284 if (err)
c74d588e 1285 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1286 err);
9d5c8243
AK		 1287
1288request_done:
1289 return err;
1290}
1291
1292static void igb_free_irq(struct igb_adapter *adapter)
1293{
9d5c8243
AK		 1294 if (adapter->msix_entries) {
1295 int vector = 0, i;
1296
047e0030 1297 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1298
0d1ae7f4 1299 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1300 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1301 adapter->q_vector[i]);
047e0030
AD		 1302 } else {
1303 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1304 }
9d5c8243
AK		 1305}
1306
1307/**
1308 * igb_irq_disable - Mask off interrupt generation on the NIC
1309 * @adapter: board private structure
1310 **/
1311static void igb_irq_disable(struct igb_adapter *adapter)
1312{
1313 struct e1000_hw *hw = &adapter->hw;
1314
25568a53
AD		 1315 /*
1316 * we need to be careful when disabling interrupts. The VFs are also
1317 * mapped into these registers and so clearing the bits can cause
1318 * issues on the VF drivers so we only need to clear what we set
1319 */
9d5c8243 1320 if (adapter->msix_entries) {
2dfd1212
AD		 1321 u32 regval = rd32(E1000_EIAM);
1322 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1323 wr32(E1000_EIMC, adapter->eims_enable_mask);
1324 regval = rd32(E1000_EIAC);
1325 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1326 }
844290e5
PW		 1327
1328 wr32(E1000_IAM, 0);
9d5c8243
AK		 1329 wr32(E1000_IMC, ~0);
1330 wrfl();
81a61859
ET		 1331 if (adapter->msix_entries) {
1332 int i;
1333 for (i = 0; i < adapter->num_q_vectors; i++)
1334 synchronize_irq(adapter->msix_entries[i].vector);
1335 } else {
1336 synchronize_irq(adapter->pdev->irq);
1337 }
9d5c8243
AK		 1338}
1339
1340/**
1341 * igb_irq_enable - Enable default interrupt generation settings
1342 * @adapter: board private structure
1343 **/
1344static void igb_irq_enable(struct igb_adapter *adapter)
1345{
1346 struct e1000_hw *hw = &adapter->hw;
1347
1348 if (adapter->msix_entries) {
06218a8d 1349 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1350 u32 regval = rd32(E1000_EIAC);
1351 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1352 regval = rd32(E1000_EIAM);
1353 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1354 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1355 if (adapter->vfs_allocated_count) {
4ae196df 1356 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1357 ims |= E1000_IMS_VMMB;
1358 }
1359 wr32(E1000_IMS, ims);
844290e5 1360 } else {
55cac248
AD		 1361 wr32(E1000_IMS, IMS_ENABLE_MASK |
1362 E1000_IMS_DRSTA);
1363 wr32(E1000_IAM, IMS_ENABLE_MASK |
1364 E1000_IMS_DRSTA);
844290e5 1365 }
9d5c8243
AK		 1366}
1367
1368static void igb_update_mng_vlan(struct igb_adapter *adapter)
1369{
51466239 1370 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1371 u16 vid = adapter->hw.mng_cookie.vlan_id;
1372 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1373
1374 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1375 /* add VID to filter table */
1376 igb_vfta_set(hw, vid, true);
1377 adapter->mng_vlan_id = vid;
1378 } else {
1379 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1380 }
1381
1382 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1383 (vid != old_vid) &&
b2cb09b1 1384 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1385 /* remove VID from filter table */
1386 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1387 }
1388}
1389
1390/**
1391 * igb_release_hw_control - release control of the h/w to f/w
1392 * @adapter: address of board private structure
1393 *
1394 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1395 * For ASF and Pass Through versions of f/w this means that the
1396 * driver is no longer loaded.
1397 *
1398 **/
1399static void igb_release_hw_control(struct igb_adapter *adapter)
1400{
1401 struct e1000_hw *hw = &adapter->hw;
1402 u32 ctrl_ext;
1403
1404 /* Let firmware take over control of h/w */
1405 ctrl_ext = rd32(E1000_CTRL_EXT);
1406 wr32(E1000_CTRL_EXT,
1407 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1408}
1409
9d5c8243
AK		 1410/**
1411 * igb_get_hw_control - get control of the h/w from f/w
1412 * @adapter: address of board private structure
1413 *
1414 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1415 * For ASF and Pass Through versions of f/w this means that
1416 * the driver is loaded.
1417 *
1418 **/
1419static void igb_get_hw_control(struct igb_adapter *adapter)
1420{
1421 struct e1000_hw *hw = &adapter->hw;
1422 u32 ctrl_ext;
1423
1424 /* Let firmware know the driver has taken over */
1425 ctrl_ext = rd32(E1000_CTRL_EXT);
1426 wr32(E1000_CTRL_EXT,
1427 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1428}
1429
9d5c8243
AK		 1430/**
1431 * igb_configure - configure the hardware for RX and TX
1432 * @adapter: private board structure
1433 **/
1434static void igb_configure(struct igb_adapter *adapter)
1435{
1436 struct net_device *netdev = adapter->netdev;
1437 int i;
1438
1439 igb_get_hw_control(adapter);
ff41f8dc 1440 igb_set_rx_mode(netdev);
9d5c8243
AK		 1441
1442 igb_restore_vlan(adapter);
9d5c8243 1443
85b430b4 1444 igb_setup_tctl(adapter);
06cf2666 1445 igb_setup_mrqc(adapter);
9d5c8243 1446 igb_setup_rctl(adapter);
85b430b4
AD		 1447
1448 igb_configure_tx(adapter);
9d5c8243 1449 igb_configure_rx(adapter);
662d7205
AD		 1450
1451 igb_rx_fifo_flush_82575(&adapter->hw);
1452
c493ea45 1453 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1454 * at least 1 descriptor unused to make sure
1455 * next_to_use != next_to_clean */
1456 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1457 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1458 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1459 }
9d5c8243
AK		 1460}
1461
88a268c1
NN		 1462/**
1463 * igb_power_up_link - Power up the phy/serdes link
1464 * @adapter: address of board private structure
1465 **/
1466void igb_power_up_link(struct igb_adapter *adapter)
1467{
76886596
AA		 1468 igb_reset_phy(&adapter->hw);
1469
88a268c1
NN		 1470 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1471 igb_power_up_phy_copper(&adapter->hw);
1472 else
1473 igb_power_up_serdes_link_82575(&adapter->hw);
1474}
1475
1476/**
1477 * igb_power_down_link - Power down the phy/serdes link
1478 * @adapter: address of board private structure
1479 */
1480static void igb_power_down_link(struct igb_adapter *adapter)
1481{
1482 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1483 igb_power_down_phy_copper_82575(&adapter->hw);
1484 else
1485 igb_shutdown_serdes_link_82575(&adapter->hw);
1486}
9d5c8243
AK		 1487
1488/**
1489 * igb_up - Open the interface and prepare it to handle traffic
1490 * @adapter: board private structure
1491 **/
9d5c8243
AK		 1492int igb_up(struct igb_adapter *adapter)
1493{
1494 struct e1000_hw *hw = &adapter->hw;
1495 int i;
1496
1497 /* hardware has been reset, we need to reload some things */
1498 igb_configure(adapter);
1499
1500 clear_bit(__IGB_DOWN, &adapter->state);
1501
0d1ae7f4
AD		 1502 for (i = 0; i < adapter->num_q_vectors; i++)
1503 napi_enable(&(adapter->q_vector[i]->napi));
1504
844290e5 1505 if (adapter->msix_entries)
9d5c8243 1506 igb_configure_msix(adapter);
feeb2721
AD		 1507 else
1508 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1509
1510 /* Clear any pending interrupts. */
1511 rd32(E1000_ICR);
1512 igb_irq_enable(adapter);
1513
d4960307
AD		 1514 /* notify VFs that reset has been completed */
1515 if (adapter->vfs_allocated_count) {
1516 u32 reg_data = rd32(E1000_CTRL_EXT);
1517 reg_data |= E1000_CTRL_EXT_PFRSTD;
1518 wr32(E1000_CTRL_EXT, reg_data);
1519 }
1520
4cb9be7a
JB		 1521 netif_tx_start_all_queues(adapter->netdev);
1522
25568a53
AD		 1523 /* start the watchdog. */
1524 hw->mac.get_link_status = 1;
1525 schedule_work(&adapter->watchdog_task);
1526
9d5c8243
AK		 1527 return 0;
1528}
1529
1530void igb_down(struct igb_adapter *adapter)
1531{
9d5c8243 1532 struct net_device *netdev = adapter->netdev;
330a6d6a 1533 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1534 u32 tctl, rctl;
1535 int i;
1536
1537 /* signal that we're down so the interrupt handler does not
1538 * reschedule our watchdog timer */
1539 set_bit(__IGB_DOWN, &adapter->state);
1540
1541 /* disable receives in the hardware */
1542 rctl = rd32(E1000_RCTL);
1543 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1544 /* flush and sleep below */
1545
fd2ea0a7 1546 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1547
1548 /* disable transmits in the hardware */
1549 tctl = rd32(E1000_TCTL);
1550 tctl &= ~E1000_TCTL_EN;
1551 wr32(E1000_TCTL, tctl);
1552 /* flush both disables and wait for them to finish */
1553 wrfl();
1554 msleep(10);
1555
0d1ae7f4
AD		 1556 for (i = 0; i < adapter->num_q_vectors; i++)
1557 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1558
9d5c8243
AK		 1559 igb_irq_disable(adapter);
1560
1561 del_timer_sync(&adapter->watchdog_timer);
1562 del_timer_sync(&adapter->phy_info_timer);
1563
9d5c8243 1564 netif_carrier_off(netdev);
04fe6358
AD		 1565
1566 /* record the stats before reset*/
12dcd86b
ED		 1567 spin_lock(&adapter->stats64_lock);
1568 igb_update_stats(adapter, &adapter->stats64);
1569 spin_unlock(&adapter->stats64_lock);
04fe6358 1570
9d5c8243
AK		 1571 adapter->link_speed = 0;
1572 adapter->link_duplex = 0;
1573
3023682e
JK		 1574 if (!pci_channel_offline(adapter->pdev))
1575 igb_reset(adapter);
9d5c8243
AK		 1576 igb_clean_all_tx_rings(adapter);
1577 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1578#ifdef CONFIG_IGB_DCA
1579
1580 /* since we reset the hardware DCA settings were cleared */
1581 igb_setup_dca(adapter);
1582#endif
9d5c8243
AK		 1583}
1584
1585void igb_reinit_locked(struct igb_adapter *adapter)
1586{
1587 WARN_ON(in_interrupt());
1588 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1589 msleep(1);
1590 igb_down(adapter);
1591 igb_up(adapter);
1592 clear_bit(__IGB_RESETTING, &adapter->state);
1593}
1594
1595void igb_reset(struct igb_adapter *adapter)
1596{
090b1795 1597 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1598 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1599 struct e1000_mac_info *mac = &hw->mac;
1600 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1601 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1602
1603 /* Repartition Pba for greater than 9k mtu
1604 * To take effect CTRL.RST is required.
1605 */
fa4dfae0 1606 switch (mac->type) {
d2ba2ed8 1607 case e1000_i350:
55cac248
AD		 1608 case e1000_82580:
1609 pba = rd32(E1000_RXPBS);
1610 pba = igb_rxpbs_adjust_82580(pba);
1611 break;
fa4dfae0 1612 case e1000_82576:
d249be54
AD		 1613 pba = rd32(E1000_RXPBS);
1614 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1615 break;
1616 case e1000_82575:
f96a8a0b
CW		 1617 case e1000_i210:
1618 case e1000_i211:
fa4dfae0
AD		 1619 default:
1620 pba = E1000_PBA_34K;
1621 break;
2d064c06 1622 }
9d5c8243 1623
2d064c06
AD		 1624 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1625 (mac->type < e1000_82576)) {
9d5c8243
AK		 1626 /* adjust PBA for jumbo frames */
1627 wr32(E1000_PBA, pba);
1628
1629 /* To maintain wire speed transmits, the Tx FIFO should be
1630 * large enough to accommodate two full transmit packets,
1631 * rounded up to the next 1KB and expressed in KB. Likewise,
1632 * the Rx FIFO should be large enough to accommodate at least
1633 * one full receive packet and is similarly rounded up and
1634 * expressed in KB. */
1635 pba = rd32(E1000_PBA);
1636 /* upper 16 bits has Tx packet buffer allocation size in KB */
1637 tx_space = pba >> 16;
1638 /* lower 16 bits has Rx packet buffer allocation size in KB */
1639 pba &= 0xffff;
1640 /* the tx fifo also stores 16 bytes of information about the tx
1641 * but don't include ethernet FCS because hardware appends it */
1642 min_tx_space = (adapter->max_frame_size +
85e8d004 1643 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1644 ETH_FCS_LEN) * 2;
1645 min_tx_space = ALIGN(min_tx_space, 1024);
1646 min_tx_space >>= 10;
1647 /* software strips receive CRC, so leave room for it */
1648 min_rx_space = adapter->max_frame_size;
1649 min_rx_space = ALIGN(min_rx_space, 1024);
1650 min_rx_space >>= 10;
1651
1652 /* If current Tx allocation is less than the min Tx FIFO size,
1653 * and the min Tx FIFO size is less than the current Rx FIFO
1654 * allocation, take space away from current Rx allocation */
1655 if (tx_space < min_tx_space &&
1656 ((min_tx_space - tx_space) < pba)) {
1657 pba = pba - (min_tx_space - tx_space);
1658
1659 /* if short on rx space, rx wins and must trump tx
1660 * adjustment */
1661 if (pba < min_rx_space)
1662 pba = min_rx_space;
1663 }
2d064c06 1664 wr32(E1000_PBA, pba);
9d5c8243 1665 }
9d5c8243
AK		 1666
1667 /* flow control settings */
1668 /* The high water mark must be low enough to fit one full frame
1669 * (or the size used for early receive) above it in the Rx FIFO.
1670 * Set it to the lower of:
1671 * - 90% of the Rx FIFO size, or
1672 * - the full Rx FIFO size minus one full frame */
1673 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1674 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1675
d48507fe 1676 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1677 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1678 fc->pause_time = 0xFFFF;
1679 fc->send_xon = 1;
0cce119a 1680 fc->current_mode = fc->requested_mode;
9d5c8243 1681
4ae196df
AD		 1682 /* disable receive for all VFs and wait one second */
1683 if (adapter->vfs_allocated_count) {
1684 int i;
1685 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1686 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1687
1688 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1689 igb_ping_all_vfs(adapter);
4ae196df
AD		 1690
1691 /* disable transmits and receives */
1692 wr32(E1000_VFRE, 0);
1693 wr32(E1000_VFTE, 0);
1694 }
1695
9d5c8243 1696 /* Allow time for pending master requests to run */
330a6d6a 1697 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1698 wr32(E1000_WUC, 0);
1699
330a6d6a 1700 if (hw->mac.ops.init_hw(hw))
090b1795 1701 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1702
a27416bb
MV		 1703 /*
1704 * Flow control settings reset on hardware reset, so guarantee flow
1705 * control is off when forcing speed.
1706 */
1707 if (!hw->mac.autoneg)
1708 igb_force_mac_fc(hw);
1709
b6e0c419 1710 igb_init_dmac(adapter, pba);
88a268c1
NN		 1711 if (!netif_running(adapter->netdev))
1712 igb_power_down_link(adapter);
1713
9d5c8243
AK		 1714 igb_update_mng_vlan(adapter);
1715
1716 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1717 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1718
1f6e8178
MV		 1719 /* Re-enable PTP, where applicable. */
1720 igb_ptp_reset(adapter);
1f6e8178 1721
330a6d6a 1722 igb_get_phy_info(hw);
9d5c8243
AK		 1723}
1724
c8f44aff
MM		 1725static netdev_features_t igb_fix_features(struct net_device *netdev,
1726 netdev_features_t features)
b2cb09b1
JP		 1727{
1728 /*
1729 * Since there is no support for separate rx/tx vlan accel
1730 * enable/disable make sure tx flag is always in same state as rx.
1731 */
1732 if (features & NETIF_F_HW_VLAN_RX)
1733 features |= NETIF_F_HW_VLAN_TX;
1734 else
1735 features &= ~NETIF_F_HW_VLAN_TX;
1736
1737 return features;
1738}
1739
c8f44aff
MM		 1740static int igb_set_features(struct net_device *netdev,
1741 netdev_features_t features)
ac52caa3 1742{
c8f44aff 1743 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1744 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1745
b2cb09b1
JP		 1746 if (changed & NETIF_F_HW_VLAN_RX)
1747 igb_vlan_mode(netdev, features);
1748
89eaefb6
BG		 1749 if (!(changed & NETIF_F_RXALL))
1750 return 0;
1751
1752 netdev->features = features;
1753
1754 if (netif_running(netdev))
1755 igb_reinit_locked(adapter);
1756 else
1757 igb_reset(adapter);
1758
ac52caa3
MM		 1759 return 0;
1760}
1761
2e5c6922 1762static const struct net_device_ops igb_netdev_ops = {
559e9c49 1763 .ndo_open = igb_open,
2e5c6922 1764 .ndo_stop = igb_close,
cd392f5c 1765 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1766 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1767 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1768 .ndo_set_mac_address = igb_set_mac,
1769 .ndo_change_mtu = igb_change_mtu,
1770 .ndo_do_ioctl = igb_ioctl,
1771 .ndo_tx_timeout = igb_tx_timeout,
1772 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1773 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1774 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1775 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1776 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1777 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1778 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1779#ifdef CONFIG_NET_POLL_CONTROLLER
1780 .ndo_poll_controller = igb_netpoll,
1781#endif
b2cb09b1
JP		 1782 .ndo_fix_features = igb_fix_features,
1783 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1784};
1785
d67974f0
CW		 1786/**
1787 * igb_set_fw_version - Configure version string for ethtool
1788 * @adapter: adapter struct
1789 *
1790 **/
1791void igb_set_fw_version(struct igb_adapter *adapter)
1792{
1793 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1794 struct e1000_fw_version fw;
1795
1796 igb_get_fw_version(hw, &fw);
1797
1798 switch (hw->mac.type) {
1799 case e1000_i211:
d67974f0 1800 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1801 "%2d.%2d-%d",
1802 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1803 break;
1804
1805 default:
1806 /* if option is rom valid, display its version too */
1807 if (fw.or_valid) {
1808 snprintf(adapter->fw_version,
1809 sizeof(adapter->fw_version),
1810 "%d.%d, 0x%08x, %d.%d.%d",
1811 fw.eep_major, fw.eep_minor, fw.etrack_id,
1812 fw.or_major, fw.or_build, fw.or_patch);
1813 /* no option rom */
1814 } else {
1815 snprintf(adapter->fw_version,
1816 sizeof(adapter->fw_version),
1817 "%d.%d, 0x%08x",
1818 fw.eep_major, fw.eep_minor, fw.etrack_id);
1819 }
1820 break;
d67974f0 1821 }
d67974f0
CW		 1822 return;
1823}
1824
9d5c8243
AK		 1825/**
1826 * igb_probe - Device Initialization Routine
1827 * @pdev: PCI device information struct
1828 * @ent: entry in igb_pci_tbl
1829 *
1830 * Returns 0 on success, negative on failure
1831 *
1832 * igb_probe initializes an adapter identified by a pci_dev structure.
1833 * The OS initialization, configuring of the adapter private structure,
1834 * and a hardware reset occur.
1835 **/
1dd06ae8 1836static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1837{
1838 struct net_device *netdev;
1839 struct igb_adapter *adapter;
1840 struct e1000_hw *hw;
4337e993 1841 u16 eeprom_data = 0;
9835fd73 1842 s32 ret_val;
4337e993 1843 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1844 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1845 unsigned long mmio_start, mmio_len;
2d6a5e95 1846 int err, pci_using_dac;
9835fd73 1847 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1848
bded64a7
AG		 1849 /* Catch broken hardware that put the wrong VF device ID in
1850 * the PCIe SR-IOV capability.
1851 */
1852 if (pdev->is_virtfn) {
1853 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1854 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1855 return -EINVAL;
1856 }
1857
aed5dec3 1858 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1859 if (err)
1860 return err;
1861
1862 pci_using_dac = 0;
59d71989 1863 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1864 if (!err) {
59d71989 1865 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1866 if (!err)
1867 pci_using_dac = 1;
1868 } else {
59d71989 1869 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1870 if (err) {
59d71989 1871 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1872 if (err) {
1873 dev_err(&pdev->dev, "No usable DMA "
1874 "configuration, aborting\n");
1875 goto err_dma;
1876 }
1877 }
1878 }
1879
aed5dec3
AD		 1880 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1881 IORESOURCE_MEM),
1882 igb_driver_name);
9d5c8243
AK		 1883 if (err)
1884 goto err_pci_reg;
1885
19d5afd4 1886 pci_enable_pcie_error_reporting(pdev);
40a914fa 1887
9d5c8243 1888 pci_set_master(pdev);
c682fc23 1889 pci_save_state(pdev);
9d5c8243
AK		 1890
1891 err = -ENOMEM;
1bfaf07b 1892 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1893 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1894 if (!netdev)
1895 goto err_alloc_etherdev;
1896
1897 SET_NETDEV_DEV(netdev, &pdev->dev);
1898
1899 pci_set_drvdata(pdev, netdev);
1900 adapter = netdev_priv(netdev);
1901 adapter->netdev = netdev;
1902 adapter->pdev = pdev;
1903 hw = &adapter->hw;
1904 hw->back = adapter;
b3f4d599 1905 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 1906
1907 mmio_start = pci_resource_start(pdev, 0);
1908 mmio_len = pci_resource_len(pdev, 0);
1909
1910 err = -EIO;
28b0759c
AD		 1911 hw->hw_addr = ioremap(mmio_start, mmio_len);
1912 if (!hw->hw_addr)
9d5c8243
AK		 1913 goto err_ioremap;
1914
2e5c6922 1915 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1916 igb_set_ethtool_ops(netdev);
9d5c8243 1917 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1918
1919 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1920
1921 netdev->mem_start = mmio_start;
1922 netdev->mem_end = mmio_start + mmio_len;
1923
9d5c8243
AK		 1924 /* PCI config space info */
1925 hw->vendor_id = pdev->vendor;
1926 hw->device_id = pdev->device;
1927 hw->revision_id = pdev->revision;
1928 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1929 hw->subsystem_device_id = pdev->subsystem_device;
1930
9d5c8243
AK		 1931 /* Copy the default MAC, PHY and NVM function pointers */
1932 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1933 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1934 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1935 /* Initialize skew-specific constants */
1936 err = ei->get_invariants(hw);
1937 if (err)
450c87c8 1938 goto err_sw_init;
9d5c8243 1939
450c87c8 1940 /* setup the private structure */
9d5c8243
AK		 1941 err = igb_sw_init(adapter);
1942 if (err)
1943 goto err_sw_init;
1944
1945 igb_get_bus_info_pcie(hw);
1946
1947 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1948
1949 /* Copper options */
1950 if (hw->phy.media_type == e1000_media_type_copper) {
1951 hw->phy.mdix = AUTO_ALL_MODES;
1952 hw->phy.disable_polarity_correction = false;
1953 hw->phy.ms_type = e1000_ms_hw_default;
1954 }
1955
1956 if (igb_check_reset_block(hw))
1957 dev_info(&pdev->dev,
1958 "PHY reset is blocked due to SOL/IDER session.\n");
1959
077887c3
AD		 1960 /*
1961 * features is initialized to 0 in allocation, it might have bits
1962 * set by igb_sw_init so we should use an or instead of an
1963 * assignment.
1964 */
1965 netdev->features |= NETIF_F_SG |
1966 NETIF_F_IP_CSUM |
1967 NETIF_F_IPV6_CSUM |
1968 NETIF_F_TSO |
1969 NETIF_F_TSO6 |
1970 NETIF_F_RXHASH |
1971 NETIF_F_RXCSUM |
1972 NETIF_F_HW_VLAN_RX |
1973 NETIF_F_HW_VLAN_TX;
1974
1975 /* copy netdev features into list of user selectable features */
1976 netdev->hw_features |= netdev->features;
89eaefb6 1977 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 1978
1979 /* set this bit last since it cannot be part of hw_features */
1980 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1981
1982 netdev->vlan_features |= NETIF_F_TSO |
1983 NETIF_F_TSO6 |
1984 NETIF_F_IP_CSUM |
1985 NETIF_F_IPV6_CSUM |
1986 NETIF_F_SG;
48f29ffc 1987
6b8f0922
BG		 1988 netdev->priv_flags |= IFF_SUPP_NOFCS;
1989
7b872a55 1990 if (pci_using_dac) {
9d5c8243 1991 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1992 netdev->vlan_features |= NETIF_F_HIGHDMA;
1993 }
9d5c8243 1994
ac52caa3
MM		 1995 if (hw->mac.type >= e1000_82576) {
1996 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1997 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1998 }
b9473560 1999
01789349
JP		 2000 netdev->priv_flags |= IFF_UNICAST_FLT;
2001
330a6d6a 2002 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2003
2004 /* before reading the NVM, reset the controller to put the device in a
2005 * known good starting state */
2006 hw->mac.ops.reset_hw(hw);
2007
f96a8a0b
CW		 2008 /*
2009 * make sure the NVM is good , i211 parts have special NVM that
2010 * doesn't contain a checksum
2011 */
2012 if (hw->mac.type != e1000_i211) {
2013 if (hw->nvm.ops.validate(hw) < 0) {
2014 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2015 err = -EIO;
2016 goto err_eeprom;
2017 }
9d5c8243
AK		 2018 }
2019
2020 /* copy the MAC address out of the NVM */
2021 if (hw->mac.ops.read_mac_addr(hw))
2022 dev_err(&pdev->dev, "NVM Read Error\n");
2023
2024 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2025 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2026
2027 if (!is_valid_ether_addr(netdev->perm_addr)) {
2028 dev_err(&pdev->dev, "Invalid MAC Address\n");
2029 err = -EIO;
2030 goto err_eeprom;
2031 }
2032
d67974f0
CW		 2033 /* get firmware version for ethtool -i */
2034 igb_set_fw_version(adapter);
2035
c061b18d 2036 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2037 (unsigned long) adapter);
c061b18d 2038 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2039 (unsigned long) adapter);
9d5c8243
AK		 2040
2041 INIT_WORK(&adapter->reset_task, igb_reset_task);
2042 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2043
450c87c8 2044 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2045 adapter->fc_autoneg = true;
2046 hw->mac.autoneg = true;
2047 hw->phy.autoneg_advertised = 0x2f;
2048
0cce119a
AD		 2049 hw->fc.requested_mode = e1000_fc_default;
2050 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2051
9d5c8243
AK		 2052 igb_validate_mdi_setting(hw);
2053
63d4a8f9 2054 /* By default, support wake on port A */
a2cf8b6c 2055 if (hw->bus.func == 0)
63d4a8f9
MV		 2056 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2057
2058 /* Check the NVM for wake support on non-port A ports */
2059 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2060 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2061 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2062 &eeprom_data);
a2cf8b6c
AD		 2063 else if (hw->bus.func == 1)
2064 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2065
63d4a8f9
MV		 2066 if (eeprom_data & IGB_EEPROM_APME)
2067 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2068
2069 /* now that we have the eeprom settings, apply the special cases where
2070 * the eeprom may be wrong or the board simply won't support wake on
2071 * lan on a particular port */
2072 switch (pdev->device) {
2073 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2074 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2075 break;
2076 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2077 case E1000_DEV_ID_82576_FIBER:
2078 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2079 /* Wake events only supported on port A for dual fiber
2080 * regardless of eeprom setting */
2081 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2082 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2083 break;
c8ea5ea9 2084 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2085 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2086 /* if quad port adapter, disable WoL on all but port A */
2087 if (global_quad_port_a != 0)
63d4a8f9 2088 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2089 else
2090 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2091 /* Reset for multiple quad port adapters */
2092 if (++global_quad_port_a == 4)
2093 global_quad_port_a = 0;
2094 break;
63d4a8f9
MV		 2095 default:
2096 /* If the device can't wake, don't set software support */
2097 if (!device_can_wakeup(&adapter->pdev->dev))
2098 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2099 }
2100
2101 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2102 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2103 adapter->wol |= E1000_WUFC_MAG;
2104
2105 /* Some vendors want WoL disabled by default, but still supported */
2106 if ((hw->mac.type == e1000_i350) &&
2107 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2108 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2109 adapter->wol = 0;
2110 }
2111
2112 device_set_wakeup_enable(&adapter->pdev->dev,
2113 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2114
2115 /* reset the hardware with the new settings */
2116 igb_reset(adapter);
2117
2118 /* let the f/w know that the h/w is now under the control of the
2119 * driver. */
2120 igb_get_hw_control(adapter);
2121
9d5c8243
AK		 2122 strcpy(netdev->name, "eth%d");
2123 err = register_netdev(netdev);
2124 if (err)
2125 goto err_register;
2126
b168dfc5
JB		 2127 /* carrier off reporting is important to ethtool even BEFORE open */
2128 netif_carrier_off(netdev);
2129
421e02f0 2130#ifdef CONFIG_IGB_DCA
bbd98fe4 2131 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2132 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2133 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2134 igb_setup_dca(adapter);
2135 }
fe4506b6 2136
38c845c7 2137#endif
3c89f6d0 2138
673b8b70 2139 /* do hw tstamp init after resetting */
7ebae817 2140 igb_ptp_init(adapter);
673b8b70 2141
9d5c8243
AK		 2142 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2143 /* print bus type/speed/width info */
7c510e4b 2144 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2145 netdev->name,
559e9c49 2146 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2147 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2148 "unknown"),
59c3de89
AD		 2149 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2150 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2151 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2152 "unknown"),
7c510e4b 2153 netdev->dev_addr);
9d5c8243 2154
9835fd73
CW		 2155 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2156 if (ret_val)
2157 strcpy(part_str, "Unknown");
2158 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2159 dev_info(&pdev->dev,
2160 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2161 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2162 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2163 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2164 switch (hw->mac.type) {
2165 case e1000_i350:
f96a8a0b
CW		 2166 case e1000_i210:
2167 case e1000_i211:
09b068d4
CW		 2168 igb_set_eee_i350(hw);
2169 break;
2170 default:
2171 break;
2172 }
749ab2cd
YZ		 2173
2174 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2175 return 0;
2176
2177err_register:
2178 igb_release_hw_control(adapter);
2179err_eeprom:
2180 if (!igb_check_reset_block(hw))
f5f4cf08 2181 igb_reset_phy(hw);
9d5c8243
AK		 2182
2183 if (hw->flash_address)
2184 iounmap(hw->flash_address);
9d5c8243 2185err_sw_init:
047e0030 2186 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2187 iounmap(hw->hw_addr);
2188err_ioremap:
2189 free_netdev(netdev);
2190err_alloc_etherdev:
559e9c49
AD		 2191 pci_release_selected_regions(pdev,
2192 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2193err_pci_reg:
2194err_dma:
2195 pci_disable_device(pdev);
2196 return err;
2197}
2198
2199/**
2200 * igb_remove - Device Removal Routine
2201 * @pdev: PCI device information struct
2202 *
2203 * igb_remove is called by the PCI subsystem to alert the driver
2204 * that it should release a PCI device. The could be caused by a
2205 * Hot-Plug event, or because the driver is going to be removed from
2206 * memory.
2207 **/
9f9a12f8 2208static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2209{
2210 struct net_device *netdev = pci_get_drvdata(pdev);
2211 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2212 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2213
749ab2cd 2214 pm_runtime_get_noresume(&pdev->dev);
a79f4f88 2215 igb_ptp_stop(adapter);
749ab2cd 2216
760141a5
TH		 2217 /*
2218 * The watchdog timer may be rescheduled, so explicitly
2219 * disable watchdog from being rescheduled.
2220 */
9d5c8243
AK		 2221 set_bit(__IGB_DOWN, &adapter->state);
2222 del_timer_sync(&adapter->watchdog_timer);
2223 del_timer_sync(&adapter->phy_info_timer);
2224
760141a5
TH		 2225 cancel_work_sync(&adapter->reset_task);
2226 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2227
421e02f0 2228#ifdef CONFIG_IGB_DCA
7dfc16fa 2229 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2230 dev_info(&pdev->dev, "DCA disabled\n");
2231 dca_remove_requester(&pdev->dev);
7dfc16fa 2232 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2233 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2234 }
2235#endif
2236
9d5c8243
AK		 2237 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2238 * would have already happened in close and is redundant. */
2239 igb_release_hw_control(adapter);
2240
2241 unregister_netdev(netdev);
2242
047e0030 2243 igb_clear_interrupt_scheme(adapter);
9d5c8243 2244
37680117
AD		 2245#ifdef CONFIG_PCI_IOV
2246 /* reclaim resources allocated to VFs */
2247 if (adapter->vf_data) {
2248 /* disable iov and allow time for transactions to clear */
f557147c
SA		 2249 if (igb_vfs_are_assigned(adapter)) {
2250 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2251 } else {
0224d663
GR		 2252 pci_disable_sriov(pdev);
2253 msleep(500);
0224d663 2254 }
37680117
AD		 2255
2256 kfree(adapter->vf_data);
2257 adapter->vf_data = NULL;
2258 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2259 wrfl();
37680117
AD		 2260 msleep(100);
2261 dev_info(&pdev->dev, "IOV Disabled\n");
2262 }
2263#endif
559e9c49 2264
28b0759c
AD		 2265 iounmap(hw->hw_addr);
2266 if (hw->flash_address)
2267 iounmap(hw->flash_address);
559e9c49
AD		 2268 pci_release_selected_regions(pdev,
2269 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2270
1128c756 2271 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2272 free_netdev(netdev);
2273
19d5afd4 2274 pci_disable_pcie_error_reporting(pdev);
40a914fa 2275
9d5c8243
AK		 2276 pci_disable_device(pdev);
2277}
2278
a6b623e0
AD		 2279/**
2280 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2281 * @adapter: board private structure to initialize
2282 *
2283 * This function initializes the vf specific data storage and then attempts to
2284 * allocate the VFs. The reason for ordering it this way is because it is much
2285 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2286 * the memory for the VFs.
2287 **/
9f9a12f8 2288static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2289{
2290#ifdef CONFIG_PCI_IOV
2291 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2292 struct e1000_hw *hw = &adapter->hw;
f557147c 2293 int old_vfs = pci_num_vf(adapter->pdev);
0224d663 2294 int i;
a6b623e0 2295
f96a8a0b
CW		 2296 /* Virtualization features not supported on i210 family. */
2297 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2298 return;
2299
0224d663
GR		 2300 if (old_vfs) {
2301 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2302 "max_vfs setting of %d\n", old_vfs, max_vfs);
2303 adapter->vfs_allocated_count = old_vfs;
a6b623e0
AD		 2304 }
2305
0224d663
GR		 2306 if (!adapter->vfs_allocated_count)
2307 return;
2308
2309 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2310 sizeof(struct vf_data_storage), GFP_KERNEL);
f96a8a0b 2311
0224d663
GR		 2312 /* if allocation failed then we do not support SR-IOV */
2313 if (!adapter->vf_data) {
a6b623e0 2314 adapter->vfs_allocated_count = 0;
0224d663
GR		 2315 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2316 "Data Storage\n");
2317 goto out;
a6b623e0 2318 }
0224d663
GR		 2319
2320 if (!old_vfs) {
2321 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2322 goto err_out;
2323 }
2324 dev_info(&pdev->dev, "%d VFs allocated\n",
2325 adapter->vfs_allocated_count);
2326 for (i = 0; i < adapter->vfs_allocated_count; i++)
2327 igb_vf_configure(adapter, i);
2328
2329 /* DMA Coalescing is not supported in IOV mode. */
2330 adapter->flags &= ~IGB_FLAG_DMAC;
2331 goto out;
2332err_out:
2333 kfree(adapter->vf_data);
2334 adapter->vf_data = NULL;
2335 adapter->vfs_allocated_count = 0;
2336out:
2337 return;
a6b623e0
AD		 2338#endif /* CONFIG_PCI_IOV */
2339}
2340
9d5c8243
AK		 2341/**
2342 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2343 * @adapter: board private structure to initialize
2344 *
2345 * igb_sw_init initializes the Adapter private data structure.
2346 * Fields are initialized based on PCI device information and
2347 * OS network device settings (MTU size).
2348 **/
9f9a12f8 2349static int igb_sw_init(struct igb_adapter *adapter)
9d5c8243
AK		 2350{
2351 struct e1000_hw *hw = &adapter->hw;
2352 struct net_device *netdev = adapter->netdev;
2353 struct pci_dev *pdev = adapter->pdev;
374a542d 2354 u32 max_rss_queues;
9d5c8243
AK		 2355
2356 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2357
13fde97a 2358 /* set default ring sizes */
68fd9910
AD		 2359 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2360 adapter->rx_ring_count = IGB_DEFAULT_RXD;
13fde97a
AD		 2361
2362 /* set default ITR values */
4fc82adf
AD		 2363 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2364 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2365
13fde97a
AD		 2366 /* set default work limits */
2367 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2368
153285f9
AD		 2369 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2370 VLAN_HLEN;
9d5c8243
AK		 2371 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2372
12dcd86b 2373 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2374#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2375 switch (hw->mac.type) {
2376 case e1000_82576:
2377 case e1000_i350:
9b082d73
SA		 2378 if (max_vfs > 7) {
2379 dev_warn(&pdev->dev,
2380 "Maximum of 7 VFs per PF, using max\n");
2381 adapter->vfs_allocated_count = 7;
2382 } else
2383 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2384 break;
2385 default:
2386 break;
2387 }
a6b623e0 2388#endif /* CONFIG_PCI_IOV */
374a542d
MV		 2389
2390 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2391 switch (hw->mac.type) {
374a542d
MV		 2392 case e1000_i211:
2393 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2394 break;
2395 case e1000_82575:
f96a8a0b 2396 case e1000_i210:
374a542d
MV		 2397 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2398 break;
2399 case e1000_i350:
2400 /* I350 cannot do RSS and SR-IOV at the same time */
2401 if (!!adapter->vfs_allocated_count) {
2402 max_rss_queues = 1;
2403 break;
2404 }
2405 /* fall through */
2406 case e1000_82576:
2407 if (!!adapter->vfs_allocated_count) {
2408 max_rss_queues = 2;
2409 break;
2410 }
2411 /* fall through */
2412 case e1000_82580:
2413 default:
2414 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2415 break;
374a542d
MV		 2416 }
2417
2418 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2419
2420 /* Determine if we need to pair queues. */
2421 switch (hw->mac.type) {
2422 case e1000_82575:
f96a8a0b 2423 case e1000_i211:
374a542d 2424 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2425 break;
374a542d
MV		 2426 case e1000_82576:
2427 /*
2428 * If VFs are going to be allocated with RSS queues then we
2429 * should pair the queues in order to conserve interrupts due
2430 * to limited supply.
2431 */
2432 if ((adapter->rss_queues > 1) &&
2433 (adapter->vfs_allocated_count > 6))
2434 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2435 /* fall through */
2436 case e1000_82580:
2437 case e1000_i350:
2438 case e1000_i210:
f96a8a0b 2439 default:
374a542d
MV		 2440 /*
2441 * If rss_queues > half of max_rss_queues, pair the queues in
2442 * order to conserve interrupts due to limited supply.
2443 */
2444 if (adapter->rss_queues > (max_rss_queues / 2))
2445 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2446 break;
2447 }
a99955fc 2448
1128c756
CW		 2449 /* Setup and initialize a copy of the hw vlan table array */
2450 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2451 E1000_VLAN_FILTER_TBL_SIZE,
2452 GFP_ATOMIC);
2453
a6b623e0 2454 /* This call may decrease the number of queues */
53c7d064 2455 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2456 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2457 return -ENOMEM;
2458 }
2459
a6b623e0
AD		 2460 igb_probe_vfs(adapter);
2461
9d5c8243
AK		 2462 /* Explicitly disable IRQ since the NIC can be in any state. */
2463 igb_irq_disable(adapter);
2464
f96a8a0b 2465 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2466 adapter->flags &= ~IGB_FLAG_DMAC;
2467
9d5c8243
AK		 2468 set_bit(__IGB_DOWN, &adapter->state);
2469 return 0;
2470}
2471
2472/**
2473 * igb_open - Called when a network interface is made active
2474 * @netdev: network interface device structure
2475 *
2476 * Returns 0 on success, negative value on failure
2477 *
2478 * The open entry point is called when a network interface is made
2479 * active by the system (IFF_UP). At this point all resources needed
2480 * for transmit and receive operations are allocated, the interrupt
2481 * handler is registered with the OS, the watchdog timer is started,
2482 * and the stack is notified that the interface is ready.
2483 **/
749ab2cd 2484static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2485{
2486 struct igb_adapter *adapter = netdev_priv(netdev);
2487 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2488 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2489 int err;
2490 int i;
2491
2492 /* disallow open during test */
749ab2cd
YZ		 2493 if (test_bit(__IGB_TESTING, &adapter->state)) {
2494 WARN_ON(resuming);
9d5c8243 2495 return -EBUSY;
749ab2cd
YZ		 2496 }
2497
2498 if (!resuming)
2499 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2500
b168dfc5
JB		 2501 netif_carrier_off(netdev);
2502
9d5c8243
AK		 2503 /* allocate transmit descriptors */
2504 err = igb_setup_all_tx_resources(adapter);
2505 if (err)
2506 goto err_setup_tx;
2507
2508 /* allocate receive descriptors */
2509 err = igb_setup_all_rx_resources(adapter);
2510 if (err)
2511 goto err_setup_rx;
2512
88a268c1 2513 igb_power_up_link(adapter);
9d5c8243 2514
9d5c8243
AK		 2515 /* before we allocate an interrupt, we must be ready to handle it.
2516 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2517 * as soon as we call pci_request_irq, so we have to setup our
2518 * clean_rx handler before we do so. */
2519 igb_configure(adapter);
2520
2521 err = igb_request_irq(adapter);
2522 if (err)
2523 goto err_req_irq;
2524
0c2cc02e
AD		 2525 /* Notify the stack of the actual queue counts. */
2526 err = netif_set_real_num_tx_queues(adapter->netdev,
2527 adapter->num_tx_queues);
2528 if (err)
2529 goto err_set_queues;
2530
2531 err = netif_set_real_num_rx_queues(adapter->netdev,
2532 adapter->num_rx_queues);
2533 if (err)
2534 goto err_set_queues;
2535
9d5c8243
AK		 2536 /* From here on the code is the same as igb_up() */
2537 clear_bit(__IGB_DOWN, &adapter->state);
2538
0d1ae7f4
AD		 2539 for (i = 0; i < adapter->num_q_vectors; i++)
2540 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2541
2542 /* Clear any pending interrupts. */
2543 rd32(E1000_ICR);
844290e5
PW		 2544
2545 igb_irq_enable(adapter);
2546
d4960307
AD		 2547 /* notify VFs that reset has been completed */
2548 if (adapter->vfs_allocated_count) {
2549 u32 reg_data = rd32(E1000_CTRL_EXT);
2550 reg_data |= E1000_CTRL_EXT_PFRSTD;
2551 wr32(E1000_CTRL_EXT, reg_data);
2552 }
2553
d55b53ff
JK		 2554 netif_tx_start_all_queues(netdev);
2555
749ab2cd
YZ		 2556 if (!resuming)
2557 pm_runtime_put(&pdev->dev);
2558
25568a53
AD		 2559 /* start the watchdog. */
2560 hw->mac.get_link_status = 1;
2561 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2562
2563 return 0;
2564
0c2cc02e
AD		 2565err_set_queues:
2566 igb_free_irq(adapter);
9d5c8243
AK		 2567err_req_irq:
2568 igb_release_hw_control(adapter);
88a268c1 2569 igb_power_down_link(adapter);
9d5c8243
AK		 2570 igb_free_all_rx_resources(adapter);
2571err_setup_rx:
2572 igb_free_all_tx_resources(adapter);
2573err_setup_tx:
2574 igb_reset(adapter);
749ab2cd
YZ		 2575 if (!resuming)
2576 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2577
2578 return err;
2579}
2580
749ab2cd
YZ		 2581static int igb_open(struct net_device *netdev)
2582{
2583 return __igb_open(netdev, false);
2584}
2585
9d5c8243
AK		 2586/**
2587 * igb_close - Disables a network interface
2588 * @netdev: network interface device structure
2589 *
2590 * Returns 0, this is not allowed to fail
2591 *
2592 * The close entry point is called when an interface is de-activated
2593 * by the OS. The hardware is still under the driver's control, but
2594 * needs to be disabled. A global MAC reset is issued to stop the
2595 * hardware, and all transmit and receive resources are freed.
2596 **/
749ab2cd 2597static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2598{
2599 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2600 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2601
2602 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2603
749ab2cd
YZ		 2604 if (!suspending)
2605 pm_runtime_get_sync(&pdev->dev);
2606
2607 igb_down(adapter);
9d5c8243
AK		 2608 igb_free_irq(adapter);
2609
2610 igb_free_all_tx_resources(adapter);
2611 igb_free_all_rx_resources(adapter);
2612
749ab2cd
YZ		 2613 if (!suspending)
2614 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2615 return 0;
2616}
2617
749ab2cd
YZ		 2618static int igb_close(struct net_device *netdev)
2619{
2620 return __igb_close(netdev, false);
2621}
2622
9d5c8243
AK		 2623/**
2624 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2625 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2626 *
2627 * Return 0 on success, negative on failure
2628 **/
80785298 2629int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2630{
59d71989 2631 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2632 int size;
2633
06034649 2634 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2635
2636 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2637 if (!tx_ring->tx_buffer_info)
9d5c8243 2638 goto err;
9d5c8243
AK		 2639
2640 /* round up to nearest 4K */
85e8d004 2641 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2642 tx_ring->size = ALIGN(tx_ring->size, 4096);
2643
5536d210
AD		 2644 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2645 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2646 if (!tx_ring->desc)
2647 goto err;
2648
9d5c8243
AK		 2649 tx_ring->next_to_use = 0;
2650 tx_ring->next_to_clean = 0;
81c2fc22 2651
9d5c8243
AK		 2652 return 0;
2653
2654err:
06034649 2655 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2656 tx_ring->tx_buffer_info = NULL;
2657 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2658 return -ENOMEM;
2659}
2660
2661/**
2662 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2663 * (Descriptors) for all queues
2664 * @adapter: board private structure
2665 *
2666 * Return 0 on success, negative on failure
2667 **/
2668static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2669{
439705e1 2670 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2671 int i, err = 0;
2672
2673 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2674 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2675 if (err) {
439705e1 2676 dev_err(&pdev->dev,
9d5c8243
AK		 2677 "Allocation for Tx Queue %u failed\n", i);
2678 for (i--; i >= 0; i--)
3025a446 2679 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2680 break;
2681 }
2682 }
2683
2684 return err;
2685}
2686
2687/**
85b430b4
AD		 2688 * igb_setup_tctl - configure the transmit control registers
2689 * @adapter: Board private structure
9d5c8243 2690 **/
d7ee5b3a 2691void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2692{
9d5c8243
AK		 2693 struct e1000_hw *hw = &adapter->hw;
2694 u32 tctl;
9d5c8243 2695
85b430b4
AD		 2696 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2697 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2698
2699 /* Program the Transmit Control Register */
9d5c8243
AK		 2700 tctl = rd32(E1000_TCTL);
2701 tctl &= ~E1000_TCTL_CT;
2702 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2703 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2704
2705 igb_config_collision_dist(hw);
2706
9d5c8243
AK		 2707 /* Enable transmits */
2708 tctl |= E1000_TCTL_EN;
2709
2710 wr32(E1000_TCTL, tctl);
2711}
2712
85b430b4
AD		 2713/**
2714 * igb_configure_tx_ring - Configure transmit ring after Reset
2715 * @adapter: board private structure
2716 * @ring: tx ring to configure
2717 *
2718 * Configure a transmit ring after a reset.
2719 **/
d7ee5b3a
AD		 2720void igb_configure_tx_ring(struct igb_adapter *adapter,
2721 struct igb_ring *ring)
85b430b4
AD		 2722{
2723 struct e1000_hw *hw = &adapter->hw;
a74420e0 2724 u32 txdctl = 0;
85b430b4
AD		 2725 u64 tdba = ring->dma;
2726 int reg_idx = ring->reg_idx;
2727
2728 /* disable the queue */
a74420e0 2729 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2730 wrfl();
2731 mdelay(10);
2732
2733 wr32(E1000_TDLEN(reg_idx),
2734 ring->count * sizeof(union e1000_adv_tx_desc));
2735 wr32(E1000_TDBAL(reg_idx),
2736 tdba & 0x00000000ffffffffULL);
2737 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2738
fce99e34 2739 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2740 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2741 writel(0, ring->tail);
85b430b4
AD		 2742
2743 txdctl |= IGB_TX_PTHRESH;
2744 txdctl |= IGB_TX_HTHRESH << 8;
2745 txdctl |= IGB_TX_WTHRESH << 16;
2746
2747 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2748 wr32(E1000_TXDCTL(reg_idx), txdctl);
2749}
2750
2751/**
2752 * igb_configure_tx - Configure transmit Unit after Reset
2753 * @adapter: board private structure
2754 *
2755 * Configure the Tx unit of the MAC after a reset.
2756 **/
2757static void igb_configure_tx(struct igb_adapter *adapter)
2758{
2759 int i;
2760
2761 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2762 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2763}
2764
9d5c8243
AK		 2765/**
2766 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2767 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2768 *
2769 * Returns 0 on success, negative on failure
2770 **/
80785298 2771int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2772{
59d71989 2773 struct device *dev = rx_ring->dev;
f33005a6 2774 int size;
9d5c8243 2775
06034649 2776 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2777
2778 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2779 if (!rx_ring->rx_buffer_info)
9d5c8243 2780 goto err;
9d5c8243 2781
9d5c8243 2782 /* Round up to nearest 4K */
f33005a6 2783 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2784 rx_ring->size = ALIGN(rx_ring->size, 4096);
2785
5536d210
AD		 2786 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2787 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2788 if (!rx_ring->desc)
2789 goto err;
2790
cbc8e55f 2791 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 2792 rx_ring->next_to_clean = 0;
2793 rx_ring->next_to_use = 0;
9d5c8243 2794
9d5c8243
AK		 2795 return 0;
2796
2797err:
06034649
AD		 2798 vfree(rx_ring->rx_buffer_info);
2799 rx_ring->rx_buffer_info = NULL;
f33005a6 2800 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2801 return -ENOMEM;
2802}
2803
2804/**
2805 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2806 * (Descriptors) for all queues
2807 * @adapter: board private structure
2808 *
2809 * Return 0 on success, negative on failure
2810 **/
2811static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2812{
439705e1 2813 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2814 int i, err = 0;
2815
2816 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2817 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2818 if (err) {
439705e1 2819 dev_err(&pdev->dev,
9d5c8243
AK		 2820 "Allocation for Rx Queue %u failed\n", i);
2821 for (i--; i >= 0; i--)
3025a446 2822 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2823 break;
2824 }
2825 }
2826
2827 return err;
2828}
2829
06cf2666
AD		 2830/**
2831 * igb_setup_mrqc - configure the multiple receive queue control registers
2832 * @adapter: Board private structure
2833 **/
2834static void igb_setup_mrqc(struct igb_adapter *adapter)
2835{
2836 struct e1000_hw *hw = &adapter->hw;
2837 u32 mrqc, rxcsum;
797fd4be 2838 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 2839 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2840 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2841 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2842 0xFA01ACBE };
06cf2666
AD		 2843
2844 /* Fill out hash function seeds */
a57fe23e
AD		 2845 for (j = 0; j < 10; j++)
2846 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 2847
a99955fc 2848 num_rx_queues = adapter->rss_queues;
06cf2666 2849
797fd4be
AD		 2850 switch (hw->mac.type) {
2851 case e1000_82575:
2852 shift = 6;
2853 break;
2854 case e1000_82576:
2855 /* 82576 supports 2 RSS queues for SR-IOV */
2856 if (adapter->vfs_allocated_count) {
06cf2666
AD		 2857 shift = 3;
2858 num_rx_queues = 2;
06cf2666 2859 }
797fd4be
AD		 2860 break;
2861 default:
2862 break;
06cf2666
AD		 2863 }
2864
797fd4be
AD		 2865 /*
2866 * Populate the indirection table 4 entries at a time. To do this
2867 * we are generating the results for n and n+2 and then interleaving
2868 * those with the results with n+1 and n+3.
2869 */
2870 for (j = 0; j < 32; j++) {
2871 /* first pass generates n and n+2 */
2872 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2873 u32 reta = (base & 0x07800780) >> (7 - shift);
2874
2875 /* second pass generates n+1 and n+3 */
2876 base += 0x00010001 * num_rx_queues;
2877 reta |= (base & 0x07800780) << (1 + shift);
2878
2879 wr32(E1000_RETA(j), reta);
06cf2666
AD		 2880 }
2881
2882 /*
2883 * Disable raw packet checksumming so that RSS hash is placed in
2884 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2885 * offloads as they are enabled by default
2886 */
2887 rxcsum = rd32(E1000_RXCSUM);
2888 rxcsum |= E1000_RXCSUM_PCSD;
2889
2890 if (adapter->hw.mac.type >= e1000_82576)
2891 /* Enable Receive Checksum Offload for SCTP */
2892 rxcsum |= E1000_RXCSUM_CRCOFL;
2893
2894 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2895 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 2896
039454a8
AA		 2897 /* Generate RSS hash based on packet types, TCP/UDP
2898 * port numbers and/or IPv4/v6 src and dst addresses
2899 */
f96a8a0b
CW		 2900 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2901 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2902 E1000_MRQC_RSS_FIELD_IPV6 |
2903 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2904 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 2905
039454a8
AA		 2906 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2907 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2908 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2909 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2910
06cf2666
AD		 2911 /* If VMDq is enabled then we set the appropriate mode for that, else
2912 * we default to RSS so that an RSS hash is calculated per packet even
2913 * if we are only using one queue */
2914 if (adapter->vfs_allocated_count) {
2915 if (hw->mac.type > e1000_82575) {
2916 /* Set the default pool for the PF's first queue */
2917 u32 vtctl = rd32(E1000_VT_CTL);
2918 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2919 E1000_VT_CTL_DISABLE_DEF_POOL);
2920 vtctl |= adapter->vfs_allocated_count <<
2921 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2922 wr32(E1000_VT_CTL, vtctl);
2923 }
a99955fc 2924 if (adapter->rss_queues > 1)
f96a8a0b 2925 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 2926 else
f96a8a0b 2927 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 2928 } else {
f96a8a0b
CW		 2929 if (hw->mac.type != e1000_i211)
2930 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 2931 }
2932 igb_vmm_control(adapter);
2933
06cf2666
AD		 2934 wr32(E1000_MRQC, mrqc);
2935}
2936
9d5c8243
AK		 2937/**
2938 * igb_setup_rctl - configure the receive control registers
2939 * @adapter: Board private structure
2940 **/
d7ee5b3a 2941void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2942{
2943 struct e1000_hw *hw = &adapter->hw;
2944 u32 rctl;
9d5c8243
AK		 2945
2946 rctl = rd32(E1000_RCTL);
2947
2948 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2949 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2950
69d728ba 2951 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2952 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2953
87cb7e8c
AK		 2954 /*
2955 * enable stripping of CRC. It's unlikely this will break BMC
2956 * redirection as it did with e1000. Newer features require
2957 * that the HW strips the CRC.
73cd78f1 2958 */
87cb7e8c 2959 rctl |= E1000_RCTL_SECRC;
9d5c8243 2960
559e9c49 2961 /* disable store bad packets and clear size bits. */
ec54d7d6 2962 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2963
6ec43fe6
AD		 2964 /* enable LPE to prevent packets larger than max_frame_size */
2965 rctl |= E1000_RCTL_LPE;
9d5c8243 2966
952f72a8
AD		 2967 /* disable queue 0 to prevent tail write w/o re-config */
2968 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2969
e1739522
AD		 2970 /* Attention!!! For SR-IOV PF driver operations you must enable
2971 * queue drop for all VF and PF queues to prevent head of line blocking
2972 * if an un-trusted VF does not provide descriptors to hardware.
2973 */
2974 if (adapter->vfs_allocated_count) {
e1739522
AD		 2975 /* set all queue drop enable bits */
2976 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2977 }
2978
89eaefb6
BG		 2979 /* This is useful for sniffing bad packets. */
2980 if (adapter->netdev->features & NETIF_F_RXALL) {
2981 /* UPE and MPE will be handled by normal PROMISC logic
2982 * in e1000e_set_rx_mode */
2983 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2984 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2985 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2986
2987 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2988 E1000_RCTL_DPF | /* Allow filtered pause */
2989 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2990 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2991 * and that breaks VLANs.
2992 */
2993 }
2994
9d5c8243
AK		 2995 wr32(E1000_RCTL, rctl);
2996}
2997
7d5753f0
AD		 2998static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2999 int vfn)
3000{
3001 struct e1000_hw *hw = &adapter->hw;
3002 u32 vmolr;
3003
3004 /* if it isn't the PF check to see if VFs are enabled and
3005 * increase the size to support vlan tags */
3006 if (vfn < adapter->vfs_allocated_count &&
3007 adapter->vf_data[vfn].vlans_enabled)
3008 size += VLAN_TAG_SIZE;
3009
3010 vmolr = rd32(E1000_VMOLR(vfn));
3011 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3012 vmolr |= size | E1000_VMOLR_LPE;
3013 wr32(E1000_VMOLR(vfn), vmolr);
3014
3015 return 0;
3016}
3017
e1739522
AD		 3018/**
3019 * igb_rlpml_set - set maximum receive packet size
3020 * @adapter: board private structure
3021 *
3022 * Configure maximum receivable packet size.
3023 **/
3024static void igb_rlpml_set(struct igb_adapter *adapter)
3025{
153285f9 3026 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3027 struct e1000_hw *hw = &adapter->hw;
3028 u16 pf_id = adapter->vfs_allocated_count;
3029
e1739522
AD		 3030 if (pf_id) {
3031 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3032 /*
3033 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3034 * to our max jumbo frame size, in case we need to enable
3035 * jumbo frames on one of the rings later.
3036 * This will not pass over-length frames into the default
3037 * queue because it's gated by the VMOLR.RLPML.
3038 */
7d5753f0 3039 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3040 }
3041
3042 wr32(E1000_RLPML, max_frame_size);
3043}
3044
8151d294
WM		 3045static inline void igb_set_vmolr(struct igb_adapter *adapter,
3046 int vfn, bool aupe)
7d5753f0
AD		 3047{
3048 struct e1000_hw *hw = &adapter->hw;
3049 u32 vmolr;
3050
3051 /*
3052 * This register exists only on 82576 and newer so if we are older then
3053 * we should exit and do nothing
3054 */
3055 if (hw->mac.type < e1000_82576)
3056 return;
3057
3058 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3059 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3060 if (aupe)
3061 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3062 else
3063 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3064
3065 /* clear all bits that might not be set */
3066 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3067
a99955fc 3068 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3069 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3070 /*
3071 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3072 * multicast packets
3073 */
3074 if (vfn <= adapter->vfs_allocated_count)
3075 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3076
3077 wr32(E1000_VMOLR(vfn), vmolr);
3078}
3079
85b430b4
AD		 3080/**
3081 * igb_configure_rx_ring - Configure a receive ring after Reset
3082 * @adapter: board private structure
3083 * @ring: receive ring to be configured
3084 *
3085 * Configure the Rx unit of the MAC after a reset.
3086 **/
d7ee5b3a
AD		 3087void igb_configure_rx_ring(struct igb_adapter *adapter,
3088 struct igb_ring *ring)
85b430b4
AD		 3089{
3090 struct e1000_hw *hw = &adapter->hw;
3091 u64 rdba = ring->dma;
3092 int reg_idx = ring->reg_idx;
a74420e0 3093 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3094
3095 /* disable the queue */
a74420e0 3096 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3097
3098 /* Set DMA base address registers */
3099 wr32(E1000_RDBAL(reg_idx),
3100 rdba & 0x00000000ffffffffULL);
3101 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3102 wr32(E1000_RDLEN(reg_idx),
3103 ring->count * sizeof(union e1000_adv_rx_desc));
3104
3105 /* initialize head and tail */
fce99e34 3106 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3107 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3108 writel(0, ring->tail);
85b430b4 3109
952f72a8 3110 /* set descriptor configuration */
44390ca6 3111 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3112 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3113 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3114 if (hw->mac.type >= e1000_82580)
757b77e2 3115 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3116 /* Only set Drop Enable if we are supporting multiple queues */
3117 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3118 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3119
3120 wr32(E1000_SRRCTL(reg_idx), srrctl);
3121
7d5753f0 3122 /* set filtering for VMDQ pools */
8151d294 3123 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3124
85b430b4
AD		 3125 rxdctl |= IGB_RX_PTHRESH;
3126 rxdctl |= IGB_RX_HTHRESH << 8;
3127 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3128
3129 /* enable receive descriptor fetching */
3130 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3131 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3132}
3133
9d5c8243
AK		 3134/**
3135 * igb_configure_rx - Configure receive Unit after Reset
3136 * @adapter: board private structure
3137 *
3138 * Configure the Rx unit of the MAC after a reset.
3139 **/
3140static void igb_configure_rx(struct igb_adapter *adapter)
3141{
9107584e 3142 int i;
9d5c8243 3143
68d480c4
AD		 3144 /* set UTA to appropriate mode */
3145 igb_set_uta(adapter);
3146
26ad9178
AD		 3147 /* set the correct pool for the PF default MAC address in entry 0 */
3148 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3149 adapter->vfs_allocated_count);
3150
06cf2666
AD		 3151 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3152 * the Base and Length of the Rx Descriptor Ring */
3153 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3154 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3155}
3156
3157/**
3158 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3159 * @tx_ring: Tx descriptor ring for a specific queue
3160 *
3161 * Free all transmit software resources
3162 **/
68fd9910 3163void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3164{
3b644cf6 3165 igb_clean_tx_ring(tx_ring);
9d5c8243 3166
06034649
AD		 3167 vfree(tx_ring->tx_buffer_info);
3168 tx_ring->tx_buffer_info = NULL;
9d5c8243 3169
439705e1
AD		 3170 /* if not set, then don't free */
3171 if (!tx_ring->desc)
3172 return;
3173
59d71989
AD		 3174 dma_free_coherent(tx_ring->dev, tx_ring->size,
3175 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3176
3177 tx_ring->desc = NULL;
3178}
3179
3180/**
3181 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3182 * @adapter: board private structure
3183 *
3184 * Free all transmit software resources
3185 **/
3186static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3187{
3188 int i;
3189
3190 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3191 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3192}
3193
ebe42d16
AD		 3194void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3195 struct igb_tx_buffer *tx_buffer)
3196{
3197 if (tx_buffer->skb) {
3198 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3199 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3200 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3201 dma_unmap_addr(tx_buffer, dma),
3202 dma_unmap_len(tx_buffer, len),
ebe42d16 3203 DMA_TO_DEVICE);
c9f14bf3 3204 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3205 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3206 dma_unmap_addr(tx_buffer, dma),
3207 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3208 DMA_TO_DEVICE);
3209 }
3210 tx_buffer->next_to_watch = NULL;
3211 tx_buffer->skb = NULL;
c9f14bf3 3212 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3213 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3214}
3215
3216/**
3217 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3218 * @tx_ring: ring to be cleaned
3219 **/
3b644cf6 3220static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3221{
06034649 3222 struct igb_tx_buffer *buffer_info;
9d5c8243 3223 unsigned long size;
6ad4edfc 3224 u16 i;
9d5c8243 3225
06034649 3226 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3227 return;
3228 /* Free all the Tx ring sk_buffs */
3229
3230 for (i = 0; i < tx_ring->count; i++) {
06034649 3231 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3232 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3233 }
3234
dad8a3b3
JF		 3235 netdev_tx_reset_queue(txring_txq(tx_ring));
3236
06034649
AD		 3237 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3238 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3239
3240 /* Zero out the descriptor ring */
9d5c8243
AK		 3241 memset(tx_ring->desc, 0, tx_ring->size);
3242
3243 tx_ring->next_to_use = 0;
3244 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3245}
3246
3247/**
3248 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3249 * @adapter: board private structure
3250 **/
3251static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3252{
3253 int i;
3254
3255 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3256 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3257}
3258
3259/**
3260 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3261 * @rx_ring: ring to clean the resources from
3262 *
3263 * Free all receive software resources
3264 **/
68fd9910 3265void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3266{
3b644cf6 3267 igb_clean_rx_ring(rx_ring);
9d5c8243 3268
06034649
AD		 3269 vfree(rx_ring->rx_buffer_info);
3270 rx_ring->rx_buffer_info = NULL;
9d5c8243 3271
439705e1
AD		 3272 /* if not set, then don't free */
3273 if (!rx_ring->desc)
3274 return;
3275
59d71989
AD		 3276 dma_free_coherent(rx_ring->dev, rx_ring->size,
3277 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3278
3279 rx_ring->desc = NULL;
3280}
3281
3282/**
3283 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3284 * @adapter: board private structure
3285 *
3286 * Free all receive software resources
3287 **/
3288static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3289{
3290 int i;
3291
3292 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3293 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3294}
3295
3296/**
3297 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3298 * @rx_ring: ring to free buffers from
3299 **/
3b644cf6 3300static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3301{
9d5c8243 3302 unsigned long size;
c023cd88 3303 u16 i;
9d5c8243 3304
1a1c225b
AD		 3305 if (rx_ring->skb)
3306 dev_kfree_skb(rx_ring->skb);
3307 rx_ring->skb = NULL;
3308
06034649 3309 if (!rx_ring->rx_buffer_info)
9d5c8243 3310 return;
439705e1 3311
9d5c8243
AK		 3312 /* Free all the Rx ring sk_buffs */
3313 for (i = 0; i < rx_ring->count; i++) {
06034649 3314 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3315
cbc8e55f
AD		 3316 if (!buffer_info->page)
3317 continue;
3318
3319 dma_unmap_page(rx_ring->dev,
3320 buffer_info->dma,
3321 PAGE_SIZE,
3322 DMA_FROM_DEVICE);
3323 __free_page(buffer_info->page);
3324
1a1c225b 3325 buffer_info->page = NULL;
9d5c8243
AK		 3326 }
3327
06034649
AD		 3328 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3329 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3330
3331 /* Zero out the descriptor ring */
3332 memset(rx_ring->desc, 0, rx_ring->size);
3333
cbc8e55f 3334 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3335 rx_ring->next_to_clean = 0;
3336 rx_ring->next_to_use = 0;
9d5c8243
AK		 3337}
3338
3339/**
3340 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3341 * @adapter: board private structure
3342 **/
3343static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3344{
3345 int i;
3346
3347 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3348 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3349}
3350
3351/**
3352 * igb_set_mac - Change the Ethernet Address of the NIC
3353 * @netdev: network interface device structure
3354 * @p: pointer to an address structure
3355 *
3356 * Returns 0 on success, negative on failure
3357 **/
3358static int igb_set_mac(struct net_device *netdev, void *p)
3359{
3360 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3361 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3362 struct sockaddr *addr = p;
3363
3364 if (!is_valid_ether_addr(addr->sa_data))
3365 return -EADDRNOTAVAIL;
3366
3367 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3368 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3369
26ad9178
AD		 3370 /* set the correct pool for the new PF MAC address in entry 0 */
3371 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3372 adapter->vfs_allocated_count);
e1739522 3373
9d5c8243
AK		 3374 return 0;
3375}
3376
3377/**
68d480c4 3378 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3379 * @netdev: network interface device structure
3380 *
68d480c4
AD		 3381 * Writes multicast address list to the MTA hash table.
3382 * Returns: -ENOMEM on failure
3383 * 0 on no addresses written
3384 * X on writing X addresses to MTA
9d5c8243 3385 **/
68d480c4 3386static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3387{
3388 struct igb_adapter *adapter = netdev_priv(netdev);
3389 struct e1000_hw *hw = &adapter->hw;
22bedad3 3390 struct netdev_hw_addr *ha;
68d480c4 3391 u8 *mta_list;
9d5c8243
AK		 3392 int i;
3393
4cd24eaf 3394 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3395 /* nothing to program, so clear mc list */
3396 igb_update_mc_addr_list(hw, NULL, 0);
3397 igb_restore_vf_multicasts(adapter);
3398 return 0;
3399 }
9d5c8243 3400
4cd24eaf 3401 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3402 if (!mta_list)
3403 return -ENOMEM;
ff41f8dc 3404
68d480c4 3405 /* The shared function expects a packed array of only addresses. */
48e2f183 3406 i = 0;
22bedad3
JP		 3407 netdev_for_each_mc_addr(ha, netdev)
3408 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3409
68d480c4
AD		 3410 igb_update_mc_addr_list(hw, mta_list, i);
3411 kfree(mta_list);
3412
4cd24eaf 3413 return netdev_mc_count(netdev);
68d480c4
AD		 3414}
3415
3416/**
3417 * igb_write_uc_addr_list - write unicast addresses to RAR table
3418 * @netdev: network interface device structure
3419 *
3420 * Writes unicast address list to the RAR table.
3421 * Returns: -ENOMEM on failure/insufficient address space
3422 * 0 on no addresses written
3423 * X on writing X addresses to the RAR table
3424 **/
3425static int igb_write_uc_addr_list(struct net_device *netdev)
3426{
3427 struct igb_adapter *adapter = netdev_priv(netdev);
3428 struct e1000_hw *hw = &adapter->hw;
3429 unsigned int vfn = adapter->vfs_allocated_count;
3430 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3431 int count = 0;
3432
3433 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3434 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3435 return -ENOMEM;
9d5c8243 3436
32e7bfc4 3437 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3438 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3439
3440 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3441 if (!rar_entries)
3442 break;
26ad9178
AD		 3443 igb_rar_set_qsel(adapter, ha->addr,
3444 rar_entries--,
68d480c4
AD		 3445 vfn);
3446 count++;
ff41f8dc
AD		 3447 }
3448 }
3449 /* write the addresses in reverse order to avoid write combining */
3450 for (; rar_entries > 0 ; rar_entries--) {
3451 wr32(E1000_RAH(rar_entries), 0);
3452 wr32(E1000_RAL(rar_entries), 0);
3453 }
3454 wrfl();
3455
68d480c4
AD		 3456 return count;
3457}
3458
3459/**
3460 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3461 * @netdev: network interface device structure
3462 *
3463 * The set_rx_mode entry point is called whenever the unicast or multicast
3464 * address lists or the network interface flags are updated. This routine is
3465 * responsible for configuring the hardware for proper unicast, multicast,
3466 * promiscuous mode, and all-multi behavior.
3467 **/
3468static void igb_set_rx_mode(struct net_device *netdev)
3469{
3470 struct igb_adapter *adapter = netdev_priv(netdev);
3471 struct e1000_hw *hw = &adapter->hw;
3472 unsigned int vfn = adapter->vfs_allocated_count;
3473 u32 rctl, vmolr = 0;
3474 int count;
3475
3476 /* Check for Promiscuous and All Multicast modes */
3477 rctl = rd32(E1000_RCTL);
3478
3479 /* clear the effected bits */
3480 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3481
3482 if (netdev->flags & IFF_PROMISC) {
3483 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3484 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3485 } else {
3486 if (netdev->flags & IFF_ALLMULTI) {
3487 rctl |= E1000_RCTL_MPE;
3488 vmolr |= E1000_VMOLR_MPME;
3489 } else {
3490 /*
3491 * Write addresses to the MTA, if the attempt fails
25985edc 3492 * then we should just turn on promiscuous mode so
68d480c4
AD		 3493 * that we can at least receive multicast traffic
3494 */
3495 count = igb_write_mc_addr_list(netdev);
3496 if (count < 0) {
3497 rctl |= E1000_RCTL_MPE;
3498 vmolr |= E1000_VMOLR_MPME;
3499 } else if (count) {
3500 vmolr |= E1000_VMOLR_ROMPE;
3501 }
3502 }
3503 /*
3504 * Write addresses to available RAR registers, if there is not
3505 * sufficient space to store all the addresses then enable
25985edc 3506 * unicast promiscuous mode
68d480c4
AD		 3507 */
3508 count = igb_write_uc_addr_list(netdev);
3509 if (count < 0) {
3510 rctl |= E1000_RCTL_UPE;
3511 vmolr |= E1000_VMOLR_ROPE;
3512 }
3513 rctl |= E1000_RCTL_VFE;
28fc06f5 3514 }
68d480c4 3515 wr32(E1000_RCTL, rctl);
28fc06f5 3516
68d480c4
AD		 3517 /*
3518 * In order to support SR-IOV and eventually VMDq it is necessary to set
3519 * the VMOLR to enable the appropriate modes. Without this workaround
3520 * we will have issues with VLAN tag stripping not being done for frames
3521 * that are only arriving because we are the default pool
3522 */
f96a8a0b 3523 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3524 return;
9d5c8243 3525
68d480c4
AD		 3526 vmolr |= rd32(E1000_VMOLR(vfn)) &
3527 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3528 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3529 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3530}
3531
13800469
GR		 3532static void igb_check_wvbr(struct igb_adapter *adapter)
3533{
3534 struct e1000_hw *hw = &adapter->hw;
3535 u32 wvbr = 0;
3536
3537 switch (hw->mac.type) {
3538 case e1000_82576:
3539 case e1000_i350:
3540 if (!(wvbr = rd32(E1000_WVBR)))
3541 return;
3542 break;
3543 default:
3544 break;
3545 }
3546
3547 adapter->wvbr |= wvbr;
3548}
3549
3550#define IGB_STAGGERED_QUEUE_OFFSET 8
3551
3552static void igb_spoof_check(struct igb_adapter *adapter)
3553{
3554 int j;
3555
3556 if (!adapter->wvbr)
3557 return;
3558
3559 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3560 if (adapter->wvbr & (1 << j) ||
3561 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3562 dev_warn(&adapter->pdev->dev,
3563 "Spoof event(s) detected on VF %d\n", j);
3564 adapter->wvbr &=
3565 ~((1 << j) |
3566 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3567 }
3568 }
3569}
3570
9d5c8243
AK		 3571/* Need to wait a few seconds after link up to get diagnostic information from
3572 * the phy */
3573static void igb_update_phy_info(unsigned long data)
3574{
3575 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3576 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3577}
3578
4d6b725e
AD		 3579/**
3580 * igb_has_link - check shared code for link and determine up/down
3581 * @adapter: pointer to driver private info
3582 **/
3145535a 3583bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3584{
3585 struct e1000_hw *hw = &adapter->hw;
3586 bool link_active = false;
3587 s32 ret_val = 0;
3588
3589 /* get_link_status is set on LSC (link status) interrupt or
3590 * rx sequence error interrupt. get_link_status will stay
3591 * false until the e1000_check_for_link establishes link
3592 * for copper adapters ONLY
3593 */
3594 switch (hw->phy.media_type) {
3595 case e1000_media_type_copper:
3596 if (hw->mac.get_link_status) {
3597 ret_val = hw->mac.ops.check_for_link(hw);
3598 link_active = !hw->mac.get_link_status;
3599 } else {
3600 link_active = true;
3601 }
3602 break;
4d6b725e
AD		 3603 case e1000_media_type_internal_serdes:
3604 ret_val = hw->mac.ops.check_for_link(hw);
3605 link_active = hw->mac.serdes_has_link;
3606 break;
3607 default:
3608 case e1000_media_type_unknown:
3609 break;
3610 }
3611
3612 return link_active;
3613}
3614
563988dc
SA		 3615static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3616{
3617 bool ret = false;
3618 u32 ctrl_ext, thstat;
3619
f96a8a0b 3620 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3621 if (hw->mac.type == e1000_i350) {
3622 thstat = rd32(E1000_THSTAT);
3623 ctrl_ext = rd32(E1000_CTRL_EXT);
3624
3625 if ((hw->phy.media_type == e1000_media_type_copper) &&
3626 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3627 ret = !!(thstat & event);
3628 }
3629 }
3630
3631 return ret;
3632}
3633
9d5c8243
AK		 3634/**
3635 * igb_watchdog - Timer Call-back
3636 * @data: pointer to adapter cast into an unsigned long
3637 **/
3638static void igb_watchdog(unsigned long data)
3639{
3640 struct igb_adapter *adapter = (struct igb_adapter *)data;
3641 /* Do the rest outside of interrupt context */
3642 schedule_work(&adapter->watchdog_task);
3643}
3644
3645static void igb_watchdog_task(struct work_struct *work)
3646{
3647 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3648 struct igb_adapter,
3649 watchdog_task);
9d5c8243 3650 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3651 struct net_device *netdev = adapter->netdev;
563988dc 3652 u32 link;
7a6ea550 3653 int i;
9d5c8243 3654
4d6b725e 3655 link = igb_has_link(adapter);
9d5c8243 3656 if (link) {
749ab2cd
YZ		 3657 /* Cancel scheduled suspend requests. */
3658 pm_runtime_resume(netdev->dev.parent);
3659
9d5c8243
AK		 3660 if (!netif_carrier_ok(netdev)) {
3661 u32 ctrl;
330a6d6a
AD		 3662 hw->mac.ops.get_speed_and_duplex(hw,
3663 &adapter->link_speed,
3664 &adapter->link_duplex);
9d5c8243
AK		 3665
3666 ctrl = rd32(E1000_CTRL);
527d47c1 3667 /* Links status message must follow this format */
876d2d6f
JK		 3668 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3669 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3670 netdev->name,
3671 adapter->link_speed,
3672 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3673 "Full" : "Half",
3674 (ctrl & E1000_CTRL_TFCE) &&
3675 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3676 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3677 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3678
563988dc 3679 /* check for thermal sensor event */
876d2d6f
JK		 3680 if (igb_thermal_sensor_event(hw,
3681 E1000_THSTAT_LINK_THROTTLE)) {
3682 netdev_info(netdev, "The network adapter link "
3683 "speed was downshifted because it "
3684 "overheated\n");
7ef5ed1c 3685 }
563988dc 3686
d07f3e37 3687 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3688 adapter->tx_timeout_factor = 1;
3689 switch (adapter->link_speed) {
3690 case SPEED_10:
9d5c8243
AK		 3691 adapter->tx_timeout_factor = 14;
3692 break;
3693 case SPEED_100:
9d5c8243
AK		 3694 /* maybe add some timeout factor ? */
3695 break;
3696 }
3697
3698 netif_carrier_on(netdev);
9d5c8243 3699
4ae196df 3700 igb_ping_all_vfs(adapter);
17dc566c 3701 igb_check_vf_rate_limit(adapter);
4ae196df 3702
4b1a9877 3703 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3704 if (!test_bit(__IGB_DOWN, &adapter->state))
3705 mod_timer(&adapter->phy_info_timer,
3706 round_jiffies(jiffies + 2 * HZ));
3707 }
3708 } else {
3709 if (netif_carrier_ok(netdev)) {
3710 adapter->link_speed = 0;
3711 adapter->link_duplex = 0;
563988dc
SA		 3712
3713 /* check for thermal sensor event */
876d2d6f
JK		 3714 if (igb_thermal_sensor_event(hw,
3715 E1000_THSTAT_PWR_DOWN)) {
3716 netdev_err(netdev, "The network adapter was "
3717 "stopped because it overheated\n");
7ef5ed1c 3718 }
563988dc 3719
527d47c1
AD		 3720 /* Links status message must follow this format */
3721 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3722 netdev->name);
9d5c8243 3723 netif_carrier_off(netdev);
4b1a9877 3724
4ae196df
AD		 3725 igb_ping_all_vfs(adapter);
3726
4b1a9877 3727 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3728 if (!test_bit(__IGB_DOWN, &adapter->state))
3729 mod_timer(&adapter->phy_info_timer,
3730 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3731
3732 pm_schedule_suspend(netdev->dev.parent,
3733 MSEC_PER_SEC * 5);
9d5c8243
AK		 3734 }
3735 }
3736
12dcd86b
ED		 3737 spin_lock(&adapter->stats64_lock);
3738 igb_update_stats(adapter, &adapter->stats64);
3739 spin_unlock(&adapter->stats64_lock);
9d5c8243 3740
dbabb065 3741 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3742 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3743 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3744 /* We've lost link, so the controller stops DMA,
3745 * but we've got queued Tx work that's never going
3746 * to get done, so reset controller to flush Tx.
3747 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3748 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3749 adapter->tx_timeout_count++;
3750 schedule_work(&adapter->reset_task);
3751 /* return immediately since reset is imminent */
3752 return;
3753 }
9d5c8243 3754 }
9d5c8243 3755
dbabb065 3756 /* Force detection of hung controller every watchdog period */
6d095fa8 3757 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3758 }
f7ba205e 3759
9d5c8243 3760 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3761 if (adapter->msix_entries) {
047e0030 3762 u32 eics = 0;
0d1ae7f4
AD		 3763 for (i = 0; i < adapter->num_q_vectors; i++)
3764 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3765 wr32(E1000_EICS, eics);
3766 } else {
3767 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3768 }
9d5c8243 3769
13800469
GR		 3770 igb_spoof_check(adapter);
3771
9d5c8243
AK		 3772 /* Reset the timer */
3773 if (!test_bit(__IGB_DOWN, &adapter->state))
3774 mod_timer(&adapter->watchdog_timer,
3775 round_jiffies(jiffies + 2 * HZ));
3776}
3777
3778enum latency_range {
3779 lowest_latency = 0,
3780 low_latency = 1,
3781 bulk_latency = 2,
3782 latency_invalid = 255
3783};
3784
6eb5a7f1
AD		 3785/**
3786 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3787 *
3788 * Stores a new ITR value based on strictly on packet size. This
3789 * algorithm is less sophisticated than that used in igb_update_itr,
3790 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3791 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3792 * were determined based on theoretical maximum wire speed and testing
3793 * data, in order to minimize response time while increasing bulk
3794 * throughput.
3795 * This functionality is controlled by the InterruptThrottleRate module
3796 * parameter (see igb_param.c)
3797 * NOTE: This function is called only when operating in a multiqueue
3798 * receive environment.
047e0030 3799 * @q_vector: pointer to q_vector
6eb5a7f1 3800 **/
047e0030 3801static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3802{
047e0030 3803 int new_val = q_vector->itr_val;
6eb5a7f1 3804 int avg_wire_size = 0;
047e0030 3805 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3806 unsigned int packets;
9d5c8243 3807
6eb5a7f1
AD		 3808 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3809 * ints/sec - ITR timer value of 120 ticks.
3810 */
3811 if (adapter->link_speed != SPEED_1000) {
0ba82994 3812 new_val = IGB_4K_ITR;
6eb5a7f1 3813 goto set_itr_val;
9d5c8243 3814 }
047e0030 3815
0ba82994
AD		 3816 packets = q_vector->rx.total_packets;
3817 if (packets)
3818 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3819
0ba82994
AD		 3820 packets = q_vector->tx.total_packets;
3821 if (packets)
3822 avg_wire_size = max_t(u32, avg_wire_size,
3823 q_vector->tx.total_bytes / packets);
047e0030
AD		 3824
3825 /* if avg_wire_size isn't set no work was done */
3826 if (!avg_wire_size)
3827 goto clear_counts;
9d5c8243 3828
6eb5a7f1
AD		 3829 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3830 avg_wire_size += 24;
3831
3832 /* Don't starve jumbo frames */
3833 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3834
6eb5a7f1
AD		 3835 /* Give a little boost to mid-size frames */
3836 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3837 new_val = avg_wire_size / 3;
3838 else
3839 new_val = avg_wire_size / 2;
9d5c8243 3840
0ba82994
AD		 3841 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3842 if (new_val < IGB_20K_ITR &&
3843 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3844 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3845 new_val = IGB_20K_ITR;
abe1c363 3846
6eb5a7f1 3847set_itr_val:
047e0030
AD		 3848 if (new_val != q_vector->itr_val) {
3849 q_vector->itr_val = new_val;
3850 q_vector->set_itr = 1;
9d5c8243 3851 }
6eb5a7f1 3852clear_counts:
0ba82994
AD		 3853 q_vector->rx.total_bytes = 0;
3854 q_vector->rx.total_packets = 0;
3855 q_vector->tx.total_bytes = 0;
3856 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3857}
3858
3859/**
3860 * igb_update_itr - update the dynamic ITR value based on statistics
3861 * Stores a new ITR value based on packets and byte
3862 * counts during the last interrupt. The advantage of per interrupt
3863 * computation is faster updates and more accurate ITR for the current
3864 * traffic pattern. Constants in this function were computed
3865 * based on theoretical maximum wire speed and thresholds were set based
3866 * on testing data as well as attempting to minimize response time
3867 * while increasing bulk throughput.
3868 * this functionality is controlled by the InterruptThrottleRate module
3869 * parameter (see igb_param.c)
3870 * NOTE: These calculations are only valid when operating in a single-
3871 * queue environment.
0ba82994
AD		 3872 * @q_vector: pointer to q_vector
3873 * @ring_container: ring info to update the itr for
9d5c8243 3874 **/
0ba82994
AD		 3875static void igb_update_itr(struct igb_q_vector *q_vector,
3876 struct igb_ring_container *ring_container)
9d5c8243 3877{
0ba82994
AD		 3878 unsigned int packets = ring_container->total_packets;
3879 unsigned int bytes = ring_container->total_bytes;
3880 u8 itrval = ring_container->itr;
9d5c8243 3881
0ba82994 3882 /* no packets, exit with status unchanged */
9d5c8243 3883 if (packets == 0)
0ba82994 3884 return;
9d5c8243 3885
0ba82994 3886 switch (itrval) {
9d5c8243
AK		 3887 case lowest_latency:
3888 /* handle TSO and jumbo frames */
3889 if (bytes/packets > 8000)
0ba82994 3890 itrval = bulk_latency;
9d5c8243 3891 else if ((packets < 5) && (bytes > 512))
0ba82994 3892 itrval = low_latency;
9d5c8243
AK		 3893 break;
3894 case low_latency: /* 50 usec aka 20000 ints/s */
3895 if (bytes > 10000) {
3896 /* this if handles the TSO accounting */
3897 if (bytes/packets > 8000) {
0ba82994 3898 itrval = bulk_latency;
9d5c8243 3899 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3900 itrval = bulk_latency;
9d5c8243 3901 } else if ((packets > 35)) {
0ba82994 3902 itrval = lowest_latency;
9d5c8243
AK		 3903 }
3904 } else if (bytes/packets > 2000) {
0ba82994 3905 itrval = bulk_latency;
9d5c8243 3906 } else if (packets <= 2 && bytes < 512) {
0ba82994 3907 itrval = lowest_latency;
9d5c8243
AK		 3908 }
3909 break;
3910 case bulk_latency: /* 250 usec aka 4000 ints/s */
3911 if (bytes > 25000) {
3912 if (packets > 35)
0ba82994 3913 itrval = low_latency;
1e5c3d21 3914 } else if (bytes < 1500) {
0ba82994 3915 itrval = low_latency;
9d5c8243
AK		 3916 }
3917 break;
3918 }
3919
0ba82994
AD		 3920 /* clear work counters since we have the values we need */
3921 ring_container->total_bytes = 0;
3922 ring_container->total_packets = 0;
3923
3924 /* write updated itr to ring container */
3925 ring_container->itr = itrval;
9d5c8243
AK		 3926}
3927
0ba82994 3928static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3929{
0ba82994 3930 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3931 u32 new_itr = q_vector->itr_val;
0ba82994 3932 u8 current_itr = 0;
9d5c8243
AK		 3933
3934 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3935 if (adapter->link_speed != SPEED_1000) {
3936 current_itr = 0;
0ba82994 3937 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3938 goto set_itr_now;
3939 }
3940
0ba82994
AD		 3941 igb_update_itr(q_vector, &q_vector->tx);
3942 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3943
0ba82994 3944 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3945
6eb5a7f1 3946 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3947 if (current_itr == lowest_latency &&
3948 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3949 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 3950 current_itr = low_latency;
3951
9d5c8243
AK		 3952 switch (current_itr) {
3953 /* counts and packets in update_itr are dependent on these numbers */
3954 case lowest_latency:
0ba82994 3955 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 3956 break;
3957 case low_latency:
0ba82994 3958 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 3959 break;
3960 case bulk_latency:
0ba82994 3961 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 3962 break;
3963 default:
3964 break;
3965 }
3966
3967set_itr_now:
047e0030 3968 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3969 /* this attempts to bias the interrupt rate towards Bulk
3970 * by adding intermediate steps when interrupt rate is
3971 * increasing */
047e0030
AD		 3972 new_itr = new_itr > q_vector->itr_val ?
3973 max((new_itr * q_vector->itr_val) /
3974 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 3975 new_itr) :
9d5c8243
AK		 3976 new_itr;
3977 /* Don't write the value here; it resets the adapter's
3978 * internal timer, and causes us to delay far longer than
3979 * we should between interrupts. Instead, we write the ITR
3980 * value at the beginning of the next interrupt so the timing
3981 * ends up being correct.
3982 */
047e0030
AD		 3983 q_vector->itr_val = new_itr;
3984 q_vector->set_itr = 1;
9d5c8243 3985 }
9d5c8243
AK		 3986}
3987
c50b52a0
SH		 3988static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3989 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 3990{
3991 struct e1000_adv_tx_context_desc *context_desc;
3992 u16 i = tx_ring->next_to_use;
3993
3994 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3995
3996 i++;
3997 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3998
3999 /* set bits to identify this as an advanced context descriptor */
4000 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4001
4002 /* For 82575, context index must be unique per ring. */
866cff06 4003 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4004 mss_l4len_idx |= tx_ring->reg_idx << 4;
4005
4006 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4007 context_desc->seqnum_seed = 0;
4008 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4009 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4010}
4011
7af40ad9
AD		 4012static int igb_tso(struct igb_ring *tx_ring,
4013 struct igb_tx_buffer *first,
4014 u8 *hdr_len)
9d5c8243 4015{
7af40ad9 4016 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4017 u32 vlan_macip_lens, type_tucmd;
4018 u32 mss_l4len_idx, l4len;
4019
ed6aa105
AD		 4020 if (skb->ip_summed != CHECKSUM_PARTIAL)
4021 return 0;
4022
7d13a7d0
AD		 4023 if (!skb_is_gso(skb))
4024 return 0;
9d5c8243
AK		 4025
4026 if (skb_header_cloned(skb)) {
7af40ad9 4027 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4028 if (err)
4029 return err;
4030 }
4031
7d13a7d0
AD		 4032 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4033 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4034
7af40ad9 4035 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4036 struct iphdr *iph = ip_hdr(skb);
4037 iph->tot_len = 0;
4038 iph->check = 0;
4039 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4040 iph->daddr, 0,
4041 IPPROTO_TCP,
4042 0);
7d13a7d0 4043 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4044 first->tx_flags |= IGB_TX_FLAGS_TSO |
4045 IGB_TX_FLAGS_CSUM |
4046 IGB_TX_FLAGS_IPV4;
8e1e8a47 4047 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4048 ipv6_hdr(skb)->payload_len = 0;
4049 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4050 &ipv6_hdr(skb)->daddr,
4051 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4052 first->tx_flags |= IGB_TX_FLAGS_TSO |
4053 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4054 }
4055
7af40ad9 4056 /* compute header lengths */
7d13a7d0
AD		 4057 l4len = tcp_hdrlen(skb);
4058 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4059
7af40ad9
AD		 4060 /* update gso size and bytecount with header size */
4061 first->gso_segs = skb_shinfo(skb)->gso_segs;
4062 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4063
9d5c8243 4064 /* MSS L4LEN IDX */
7d13a7d0
AD		 4065 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4066 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4067
7d13a7d0
AD		 4068 /* VLAN MACLEN IPLEN */
4069 vlan_macip_lens = skb_network_header_len(skb);
4070 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4071 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4072
7d13a7d0 4073 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4074
7d13a7d0 4075 return 1;
9d5c8243
AK		 4076}
4077
7af40ad9 4078static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4079{
7af40ad9 4080 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4081 u32 vlan_macip_lens = 0;
4082 u32 mss_l4len_idx = 0;
4083 u32 type_tucmd = 0;
9d5c8243 4084
7d13a7d0 4085 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4086 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4087 return;
7d13a7d0
AD		 4088 } else {
4089 u8 l4_hdr = 0;
7af40ad9 4090 switch (first->protocol) {
7d13a7d0
AD		 4091 case __constant_htons(ETH_P_IP):
4092 vlan_macip_lens |= skb_network_header_len(skb);
4093 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4094 l4_hdr = ip_hdr(skb)->protocol;
4095 break;
4096 case __constant_htons(ETH_P_IPV6):
4097 vlan_macip_lens |= skb_network_header_len(skb);
4098 l4_hdr = ipv6_hdr(skb)->nexthdr;
4099 break;
4100 default:
4101 if (unlikely(net_ratelimit())) {
4102 dev_warn(tx_ring->dev,
4103 "partial checksum but proto=%x!\n",
7af40ad9 4104 first->protocol);
fa4a7ef3 4105 }
7d13a7d0
AD		 4106 break;
4107 }
fa4a7ef3 4108
7d13a7d0
AD		 4109 switch (l4_hdr) {
4110 case IPPROTO_TCP:
4111 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4112 mss_l4len_idx = tcp_hdrlen(skb) <<
4113 E1000_ADVTXD_L4LEN_SHIFT;
4114 break;
4115 case IPPROTO_SCTP:
4116 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4117 mss_l4len_idx = sizeof(struct sctphdr) <<
4118 E1000_ADVTXD_L4LEN_SHIFT;
4119 break;
4120 case IPPROTO_UDP:
4121 mss_l4len_idx = sizeof(struct udphdr) <<
4122 E1000_ADVTXD_L4LEN_SHIFT;
4123 break;
4124 default:
4125 if (unlikely(net_ratelimit())) {
4126 dev_warn(tx_ring->dev,
4127 "partial checksum but l4 proto=%x!\n",
4128 l4_hdr);
44b0cda3 4129 }
7d13a7d0 4130 break;
9d5c8243 4131 }
7af40ad9
AD		 4132
4133 /* update TX checksum flag */
4134 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4135 }
9d5c8243 4136
7d13a7d0 4137 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4138 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4139
7d13a7d0 4140 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4141}
4142
1d9daf45
AD		 4143#define IGB_SET_FLAG(_input, _flag, _result) \
4144 ((_flag <= _result) ? \
4145 ((u32)(_input & _flag) * (_result / _flag)) : \
4146 ((u32)(_input & _flag) / (_flag / _result)))
4147
4148static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4149{
4150 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4151 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4152 E1000_ADVTXD_DCMD_DEXT |
4153 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4154
4155 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4156 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4157 (E1000_ADVTXD_DCMD_VLE));
4158
4159 /* set segmentation bits for TSO */
4160 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4161 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4162
4163 /* set timestamp bit if present */
1d9daf45
AD		 4164 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4165 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4166
1d9daf45
AD		 4167 /* insert frame checksum */
4168 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4169
4170 return cmd_type;
4171}
4172
7af40ad9
AD		 4173static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4174 union e1000_adv_tx_desc *tx_desc,
4175 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4176{
4177 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4178
1d9daf45
AD		 4179 /* 82575 requires a unique index per ring */
4180 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4181 olinfo_status |= tx_ring->reg_idx << 4;
4182
4183 /* insert L4 checksum */
1d9daf45
AD		 4184 olinfo_status |= IGB_SET_FLAG(tx_flags,
4185 IGB_TX_FLAGS_CSUM,
4186 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4187
1d9daf45
AD		 4188 /* insert IPv4 checksum */
4189 olinfo_status |= IGB_SET_FLAG(tx_flags,
4190 IGB_TX_FLAGS_IPV4,
4191 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4192
7af40ad9 4193 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4194}
4195
ebe42d16
AD		 4196/*
4197 * The largest size we can write to the descriptor is 65535. In order to
4198 * maintain a power of two alignment we have to limit ourselves to 32K.
4199 */
4200#define IGB_MAX_TXD_PWR 15
7af40ad9 4201#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4202
7af40ad9
AD		 4203static void igb_tx_map(struct igb_ring *tx_ring,
4204 struct igb_tx_buffer *first,
ebe42d16 4205 const u8 hdr_len)
9d5c8243 4206{
7af40ad9 4207 struct sk_buff *skb = first->skb;
c9f14bf3 4208 struct igb_tx_buffer *tx_buffer;
ebe42d16 4209 union e1000_adv_tx_desc *tx_desc;
80d0759e 4210 struct skb_frag_struct *frag;
ebe42d16 4211 dma_addr_t dma;
80d0759e 4212 unsigned int data_len, size;
7af40ad9 4213 u32 tx_flags = first->tx_flags;
1d9daf45 4214 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4215 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4216
4217 tx_desc = IGB_TX_DESC(tx_ring, i);
4218
80d0759e
AD		 4219 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4220
4221 size = skb_headlen(skb);
4222 data_len = skb->data_len;
ebe42d16
AD		 4223
4224 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4225
80d0759e
AD		 4226 tx_buffer = first;
4227
4228 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4229 if (dma_mapping_error(tx_ring->dev, dma))
4230 goto dma_error;
4231
4232 /* record length, and DMA address */
4233 dma_unmap_len_set(tx_buffer, len, size);
4234 dma_unmap_addr_set(tx_buffer, dma, dma);
4235
4236 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4237
ebe42d16
AD		 4238 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4239 tx_desc->read.cmd_type_len =
1d9daf45 4240 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4241
4242 i++;
4243 tx_desc++;
4244 if (i == tx_ring->count) {
4245 tx_desc = IGB_TX_DESC(tx_ring, 0);
4246 i = 0;
4247 }
80d0759e 4248 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4249
4250 dma += IGB_MAX_DATA_PER_TXD;
4251 size -= IGB_MAX_DATA_PER_TXD;
4252
ebe42d16
AD		 4253 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4254 }
4255
4256 if (likely(!data_len))
4257 break;
2bbfebe2 4258
1d9daf45 4259 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4260
65689fef 4261 i++;
ebe42d16
AD		 4262 tx_desc++;
4263 if (i == tx_ring->count) {
4264 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4265 i = 0;
ebe42d16 4266 }
80d0759e 4267 tx_desc->read.olinfo_status = 0;
65689fef 4268
9e903e08 4269 size = skb_frag_size(frag);
ebe42d16
AD		 4270 data_len -= size;
4271
4272 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4273 size, DMA_TO_DEVICE);
6366ad33 4274
c9f14bf3 4275 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4276 }
4277
ebe42d16 4278 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4279 cmd_type |= size | IGB_TXD_DCMD;
4280 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4281
80d0759e
AD		 4282 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4283
8542db05
AD		 4284 /* set the timestamp */
4285 first->time_stamp = jiffies;
4286
ebe42d16
AD		 4287 /*
4288 * Force memory writes to complete before letting h/w know there
4289 * are new descriptors to fetch. (Only applicable for weak-ordered
4290 * memory model archs, such as IA-64).
4291 *
4292 * We also need this memory barrier to make certain all of the
4293 * status bits have been updated before next_to_watch is written.
4294 */
4295 wmb();
4296
8542db05 4297 /* set next_to_watch value indicating a packet is present */
ebe42d16 4298 first->next_to_watch = tx_desc;
9d5c8243 4299
ebe42d16
AD		 4300 i++;
4301 if (i == tx_ring->count)
4302 i = 0;
6366ad33 4303
ebe42d16 4304 tx_ring->next_to_use = i;
6366ad33 4305
ebe42d16 4306 writel(i, tx_ring->tail);
6366ad33 4307
ebe42d16
AD		 4308 /* we need this if more than one processor can write to our tail
4309 * at a time, it syncronizes IO on IA64/Altix systems */
4310 mmiowb();
4311
4312 return;
4313
4314dma_error:
4315 dev_err(tx_ring->dev, "TX DMA map failed\n");
4316
4317 /* clear dma mappings for failed tx_buffer_info map */
4318 for (;;) {
c9f14bf3
AD		 4319 tx_buffer = &tx_ring->tx_buffer_info[i];
4320 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4321 if (tx_buffer == first)
ebe42d16 4322 break;
a77ff709
NN		 4323 if (i == 0)
4324 i = tx_ring->count;
6366ad33 4325 i--;
6366ad33
AD		 4326 }
4327
9d5c8243 4328 tx_ring->next_to_use = i;
9d5c8243
AK		 4329}
4330
6ad4edfc 4331static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4332{
e694e964
AD		 4333 struct net_device *netdev = tx_ring->netdev;
4334
661086df 4335 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4336
9d5c8243
AK		 4337 /* Herbert's original patch had:
4338 * smp_mb__after_netif_stop_queue();
4339 * but since that doesn't exist yet, just open code it. */
4340 smp_mb();
4341
4342 /* We need to check again in a case another CPU has just
4343 * made room available. */
c493ea45 4344 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4345 return -EBUSY;
4346
4347 /* A reprieve! */
661086df 4348 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4349
4350 u64_stats_update_begin(&tx_ring->tx_syncp2);
4351 tx_ring->tx_stats.restart_queue2++;
4352 u64_stats_update_end(&tx_ring->tx_syncp2);
4353
9d5c8243
AK		 4354 return 0;
4355}
4356
6ad4edfc 4357static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4358{
c493ea45 4359 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4360 return 0;
e694e964 4361 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4362}
4363
cd392f5c
AD		 4364netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4365 struct igb_ring *tx_ring)
9d5c8243 4366{
1f6e8178 4367 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4368 struct igb_tx_buffer *first;
ebe42d16 4369 int tso;
91d4ee33 4370 u32 tx_flags = 0;
31f6adbb 4371 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4372 u8 hdr_len = 0;
9d5c8243 4373
9d5c8243
AK		 4374 /* need: 1 descriptor per page,
4375 * + 2 desc gap to keep tail from touching head,
4376 * + 1 desc for skb->data,
4377 * + 1 desc for context descriptor,
4378 * otherwise try next time */
e694e964 4379 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4380 /* this is a hard error */
9d5c8243
AK		 4381 return NETDEV_TX_BUSY;
4382 }
33af6bcc 4383
7af40ad9
AD		 4384 /* record the location of the first descriptor for this packet */
4385 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4386 first->skb = skb;
4387 first->bytecount = skb->len;
4388 first->gso_segs = 1;
4389
1f6e8178
MV		 4390 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4391 !(adapter->ptp_tx_skb))) {
2244d07b 4392 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4393 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4394
4395 adapter->ptp_tx_skb = skb_get(skb);
4396 if (adapter->hw.mac.type == e1000_82576)
4397 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4398 }
9d5c8243 4399
eab6d18d 4400 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4401 tx_flags |= IGB_TX_FLAGS_VLAN;
4402 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4403 }
4404
7af40ad9
AD		 4405 /* record initial flags and protocol */
4406 first->tx_flags = tx_flags;
4407 first->protocol = protocol;
cdfd01fc 4408
7af40ad9
AD		 4409 tso = igb_tso(tx_ring, first, &hdr_len);
4410 if (tso < 0)
7d13a7d0 4411 goto out_drop;
7af40ad9
AD		 4412 else if (!tso)
4413 igb_tx_csum(tx_ring, first);
9d5c8243 4414
7af40ad9 4415 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4416
4417 /* Make sure there is space in the ring for the next send. */
e694e964 4418 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4419
9d5c8243 4420 return NETDEV_TX_OK;
7d13a7d0
AD		 4421
4422out_drop:
7af40ad9
AD		 4423 igb_unmap_and_free_tx_resource(tx_ring, first);
4424
7d13a7d0 4425 return NETDEV_TX_OK;
9d5c8243
AK		 4426}
4427
1cc3bd87
AD		 4428static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4429 struct sk_buff *skb)
4430{
4431 unsigned int r_idx = skb->queue_mapping;
4432
4433 if (r_idx >= adapter->num_tx_queues)
4434 r_idx = r_idx % adapter->num_tx_queues;
4435
4436 return adapter->tx_ring[r_idx];
4437}
4438
cd392f5c
AD		 4439static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4440 struct net_device *netdev)
9d5c8243
AK		 4441{
4442 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4443
4444 if (test_bit(__IGB_DOWN, &adapter->state)) {
4445 dev_kfree_skb_any(skb);
4446 return NETDEV_TX_OK;
4447 }
4448
4449 if (skb->len <= 0) {
4450 dev_kfree_skb_any(skb);
4451 return NETDEV_TX_OK;
4452 }
4453
1cc3bd87
AD		 4454 /*
4455 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4456 * in order to meet this minimum size requirement.
4457 */
ea5ceeab
TD		 4458 if (unlikely(skb->len < 17)) {
4459 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4460 return NETDEV_TX_OK;
4461 skb->len = 17;
ea5ceeab 4462 skb_set_tail_pointer(skb, 17);
1cc3bd87 4463 }
9d5c8243 4464
1cc3bd87 4465 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4466}
4467
4468/**
4469 * igb_tx_timeout - Respond to a Tx Hang
4470 * @netdev: network interface device structure
4471 **/
4472static void igb_tx_timeout(struct net_device *netdev)
4473{
4474 struct igb_adapter *adapter = netdev_priv(netdev);
4475 struct e1000_hw *hw = &adapter->hw;
4476
4477 /* Do the reset outside of interrupt context */
4478 adapter->tx_timeout_count++;
f7ba205e 4479
06218a8d 4480 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4481 hw->dev_spec._82575.global_device_reset = true;
4482
9d5c8243 4483 schedule_work(&adapter->reset_task);
265de409
AD		 4484 wr32(E1000_EICS,
4485 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4486}
4487
4488static void igb_reset_task(struct work_struct *work)
4489{
4490 struct igb_adapter *adapter;
4491 adapter = container_of(work, struct igb_adapter, reset_task);
4492
c97ec42a
TI		 4493 igb_dump(adapter);
4494 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4495 igb_reinit_locked(adapter);
4496}
4497
4498/**
12dcd86b 4499 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4500 * @netdev: network interface device structure
12dcd86b 4501 * @stats: rtnl_link_stats64 pointer
9d5c8243 4502 *
9d5c8243 4503 **/
12dcd86b
ED		 4504static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4505 struct rtnl_link_stats64 *stats)
9d5c8243 4506{
12dcd86b
ED		 4507 struct igb_adapter *adapter = netdev_priv(netdev);
4508
4509 spin_lock(&adapter->stats64_lock);
4510 igb_update_stats(adapter, &adapter->stats64);
4511 memcpy(stats, &adapter->stats64, sizeof(*stats));
4512 spin_unlock(&adapter->stats64_lock);
4513
4514 return stats;
9d5c8243
AK		 4515}
4516
4517/**
4518 * igb_change_mtu - Change the Maximum Transfer Unit
4519 * @netdev: network interface device structure
4520 * @new_mtu: new value for maximum frame size
4521 *
4522 * Returns 0 on success, negative on failure
4523 **/
4524static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4525{
4526 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4527 struct pci_dev *pdev = adapter->pdev;
153285f9 4528 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4529
c809d227 4530 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4531 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4532 return -EINVAL;
4533 }
4534
153285f9 4535#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4536 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4537 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4538 return -EINVAL;
4539 }
4540
4541 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4542 msleep(1);
73cd78f1 4543
9d5c8243
AK		 4544 /* igb_down has a dependency on max_frame_size */
4545 adapter->max_frame_size = max_frame;
559e9c49 4546
4c844851
AD		 4547 if (netif_running(netdev))
4548 igb_down(adapter);
9d5c8243 4549
090b1795 4550 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4551 netdev->mtu, new_mtu);
4552 netdev->mtu = new_mtu;
4553
4554 if (netif_running(netdev))
4555 igb_up(adapter);
4556 else
4557 igb_reset(adapter);
4558
4559 clear_bit(__IGB_RESETTING, &adapter->state);
4560
4561 return 0;
4562}
4563
4564/**
4565 * igb_update_stats - Update the board statistics counters
4566 * @adapter: board private structure
4567 **/
4568
12dcd86b
ED		 4569void igb_update_stats(struct igb_adapter *adapter,
4570 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4571{
4572 struct e1000_hw *hw = &adapter->hw;
4573 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4574 u32 reg, mpc;
9d5c8243 4575 u16 phy_tmp;
3f9c0164
AD		 4576 int i;
4577 u64 bytes, packets;
12dcd86b
ED		 4578 unsigned int start;
4579 u64 _bytes, _packets;
9d5c8243
AK		 4580
4581#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4582
4583 /*
4584 * Prevent stats update while adapter is being reset, or if the pci
4585 * connection is down.
4586 */
4587 if (adapter->link_speed == 0)
4588 return;
4589 if (pci_channel_offline(pdev))
4590 return;
4591
3f9c0164
AD		 4592 bytes = 0;
4593 packets = 0;
4594 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4595 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4596 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4597
ae1c07a6
AD		 4598 if (rqdpc) {
4599 ring->rx_stats.drops += rqdpc;
4600 net_stats->rx_fifo_errors += rqdpc;
4601 }
12dcd86b
ED		 4602
4603 do {
4604 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4605 _bytes = ring->rx_stats.bytes;
4606 _packets = ring->rx_stats.packets;
4607 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4608 bytes += _bytes;
4609 packets += _packets;
3f9c0164
AD		 4610 }
4611
128e45eb
AD		 4612 net_stats->rx_bytes = bytes;
4613 net_stats->rx_packets = packets;
3f9c0164
AD		 4614
4615 bytes = 0;
4616 packets = 0;
4617 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4618 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4619 do {
4620 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4621 _bytes = ring->tx_stats.bytes;
4622 _packets = ring->tx_stats.packets;
4623 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4624 bytes += _bytes;
4625 packets += _packets;
3f9c0164 4626 }
128e45eb
AD		 4627 net_stats->tx_bytes = bytes;
4628 net_stats->tx_packets = packets;
3f9c0164
AD		 4629
4630 /* read stats registers */
9d5c8243
AK		 4631 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4632 adapter->stats.gprc += rd32(E1000_GPRC);
4633 adapter->stats.gorc += rd32(E1000_GORCL);
4634 rd32(E1000_GORCH); /* clear GORCL */
4635 adapter->stats.bprc += rd32(E1000_BPRC);
4636 adapter->stats.mprc += rd32(E1000_MPRC);
4637 adapter->stats.roc += rd32(E1000_ROC);
4638
4639 adapter->stats.prc64 += rd32(E1000_PRC64);
4640 adapter->stats.prc127 += rd32(E1000_PRC127);
4641 adapter->stats.prc255 += rd32(E1000_PRC255);
4642 adapter->stats.prc511 += rd32(E1000_PRC511);
4643 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4644 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4645 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4646 adapter->stats.sec += rd32(E1000_SEC);
4647
fa3d9a6d
MW		 4648 mpc = rd32(E1000_MPC);
4649 adapter->stats.mpc += mpc;
4650 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4651 adapter->stats.scc += rd32(E1000_SCC);
4652 adapter->stats.ecol += rd32(E1000_ECOL);
4653 adapter->stats.mcc += rd32(E1000_MCC);
4654 adapter->stats.latecol += rd32(E1000_LATECOL);
4655 adapter->stats.dc += rd32(E1000_DC);
4656 adapter->stats.rlec += rd32(E1000_RLEC);
4657 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4658 adapter->stats.xontxc += rd32(E1000_XONTXC);
4659 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4660 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4661 adapter->stats.fcruc += rd32(E1000_FCRUC);
4662 adapter->stats.gptc += rd32(E1000_GPTC);
4663 adapter->stats.gotc += rd32(E1000_GOTCL);
4664 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4665 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4666 adapter->stats.ruc += rd32(E1000_RUC);
4667 adapter->stats.rfc += rd32(E1000_RFC);
4668 adapter->stats.rjc += rd32(E1000_RJC);
4669 adapter->stats.tor += rd32(E1000_TORH);
4670 adapter->stats.tot += rd32(E1000_TOTH);
4671 adapter->stats.tpr += rd32(E1000_TPR);
4672
4673 adapter->stats.ptc64 += rd32(E1000_PTC64);
4674 adapter->stats.ptc127 += rd32(E1000_PTC127);
4675 adapter->stats.ptc255 += rd32(E1000_PTC255);
4676 adapter->stats.ptc511 += rd32(E1000_PTC511);
4677 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4678 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4679
4680 adapter->stats.mptc += rd32(E1000_MPTC);
4681 adapter->stats.bptc += rd32(E1000_BPTC);
4682
2d0b0f69
NN		 4683 adapter->stats.tpt += rd32(E1000_TPT);
4684 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4685
4686 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4687 /* read internal phy specific stats */
4688 reg = rd32(E1000_CTRL_EXT);
4689 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4690 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4691
4692 /* this stat has invalid values on i210/i211 */
4693 if ((hw->mac.type != e1000_i210) &&
4694 (hw->mac.type != e1000_i211))
4695 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4696 }
4697
9d5c8243
AK		 4698 adapter->stats.tsctc += rd32(E1000_TSCTC);
4699 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4700
4701 adapter->stats.iac += rd32(E1000_IAC);
4702 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4703 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4704 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4705 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4706 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4707 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4708 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4709 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4710
4711 /* Fill out the OS statistics structure */
128e45eb
AD		 4712 net_stats->multicast = adapter->stats.mprc;
4713 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4714
4715 /* Rx Errors */
4716
4717 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4718 * our own version based on RUC and ROC */
128e45eb 4719 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4720 adapter->stats.crcerrs + adapter->stats.algnerrc +
4721 adapter->stats.ruc + adapter->stats.roc +
4722 adapter->stats.cexterr;
128e45eb
AD		 4723 net_stats->rx_length_errors = adapter->stats.ruc +
4724 adapter->stats.roc;
4725 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4726 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4727 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4728
4729 /* Tx Errors */
128e45eb
AD		 4730 net_stats->tx_errors = adapter->stats.ecol +
4731 adapter->stats.latecol;
4732 net_stats->tx_aborted_errors = adapter->stats.ecol;
4733 net_stats->tx_window_errors = adapter->stats.latecol;
4734 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4735
4736 /* Tx Dropped needs to be maintained elsewhere */
4737
4738 /* Phy Stats */
4739 if (hw->phy.media_type == e1000_media_type_copper) {
4740 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4741 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4742 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4743 adapter->phy_stats.idle_errors += phy_tmp;
4744 }
4745 }
4746
4747 /* Management Stats */
4748 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4749 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4750 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4751
4752 /* OS2BMC Stats */
4753 reg = rd32(E1000_MANC);
4754 if (reg & E1000_MANC_EN_BMC2OS) {
4755 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4756 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4757 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4758 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4759 }
9d5c8243
AK		 4760}
4761
9d5c8243
AK		 4762static irqreturn_t igb_msix_other(int irq, void *data)
4763{
047e0030 4764 struct igb_adapter *adapter = data;
9d5c8243 4765 struct e1000_hw *hw = &adapter->hw;
844290e5 4766 u32 icr = rd32(E1000_ICR);
844290e5 4767 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4768
7f081d40
AD		 4769 if (icr & E1000_ICR_DRSTA)
4770 schedule_work(&adapter->reset_task);
4771
047e0030 4772 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4773 /* HW is reporting DMA is out of sync */
4774 adapter->stats.doosync++;
13800469
GR		 4775 /* The DMA Out of Sync is also indication of a spoof event
4776 * in IOV mode. Check the Wrong VM Behavior register to
4777 * see if it is really a spoof event. */
4778 igb_check_wvbr(adapter);
dda0e083 4779 }
eebbbdba 4780
4ae196df
AD		 4781 /* Check for a mailbox event */
4782 if (icr & E1000_ICR_VMMB)
4783 igb_msg_task(adapter);
4784
4785 if (icr & E1000_ICR_LSC) {
4786 hw->mac.get_link_status = 1;
4787 /* guard against interrupt when we're going down */
4788 if (!test_bit(__IGB_DOWN, &adapter->state))
4789 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4790 }
4791
1f6e8178
MV		 4792 if (icr & E1000_ICR_TS) {
4793 u32 tsicr = rd32(E1000_TSICR);
4794
4795 if (tsicr & E1000_TSICR_TXTS) {
4796 /* acknowledge the interrupt */
4797 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4798 /* retrieve hardware timestamp */
4799 schedule_work(&adapter->ptp_tx_work);
4800 }
4801 }
1f6e8178 4802
844290e5 4803 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4804
4805 return IRQ_HANDLED;
4806}
4807
047e0030 4808static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4809{
26b39276 4810 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4811 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4812
047e0030
AD		 4813 if (!q_vector->set_itr)
4814 return;
73cd78f1 4815
047e0030
AD		 4816 if (!itr_val)
4817 itr_val = 0x4;
661086df 4818
26b39276
AD		 4819 if (adapter->hw.mac.type == e1000_82575)
4820 itr_val |= itr_val << 16;
661086df 4821 else
0ba82994 4822 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4823
047e0030
AD		 4824 writel(itr_val, q_vector->itr_register);
4825 q_vector->set_itr = 0;
6eb5a7f1
AD		 4826}
4827
047e0030 4828static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4829{
047e0030 4830 struct igb_q_vector *q_vector = data;
9d5c8243 4831
047e0030
AD		 4832 /* Write the ITR value calculated from the previous interrupt. */
4833 igb_write_itr(q_vector);
9d5c8243 4834
047e0030 4835 napi_schedule(&q_vector->napi);
844290e5 4836
047e0030 4837 return IRQ_HANDLED;
fe4506b6
JC		 4838}
4839
421e02f0 4840#ifdef CONFIG_IGB_DCA
6a05004a
AD		 4841static void igb_update_tx_dca(struct igb_adapter *adapter,
4842 struct igb_ring *tx_ring,
4843 int cpu)
4844{
4845 struct e1000_hw *hw = &adapter->hw;
4846 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4847
4848 if (hw->mac.type != e1000_82575)
4849 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4850
4851 /*
4852 * We can enable relaxed ordering for reads, but not writes when
4853 * DCA is enabled. This is due to a known issue in some chipsets
4854 * which will cause the DCA tag to be cleared.
4855 */
4856 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4857 E1000_DCA_TXCTRL_DATA_RRO_EN |
4858 E1000_DCA_TXCTRL_DESC_DCA_EN;
4859
4860 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4861}
4862
4863static void igb_update_rx_dca(struct igb_adapter *adapter,
4864 struct igb_ring *rx_ring,
4865 int cpu)
4866{
4867 struct e1000_hw *hw = &adapter->hw;
4868 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4869
4870 if (hw->mac.type != e1000_82575)
4871 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4872
4873 /*
4874 * We can enable relaxed ordering for reads, but not writes when
4875 * DCA is enabled. This is due to a known issue in some chipsets
4876 * which will cause the DCA tag to be cleared.
4877 */
4878 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4879 E1000_DCA_RXCTRL_DESC_DCA_EN;
4880
4881 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4882}
4883
047e0030 4884static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4885{
047e0030 4886 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 4887 int cpu = get_cpu();
fe4506b6 4888
047e0030
AD		 4889 if (q_vector->cpu == cpu)
4890 goto out_no_update;
4891
6a05004a
AD		 4892 if (q_vector->tx.ring)
4893 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4894
4895 if (q_vector->rx.ring)
4896 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4897
047e0030
AD		 4898 q_vector->cpu = cpu;
4899out_no_update:
fe4506b6
JC		 4900 put_cpu();
4901}
4902
4903static void igb_setup_dca(struct igb_adapter *adapter)
4904{
7e0e99ef 4905 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4906 int i;
4907
7dfc16fa 4908 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4909 return;
4910
7e0e99ef
AD		 4911 /* Always use CB2 mode, difference is masked in the CB driver. */
4912 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4913
047e0030 4914 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4915 adapter->q_vector[i]->cpu = -1;
4916 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4917 }
4918}
4919
4920static int __igb_notify_dca(struct device *dev, void *data)
4921{
4922 struct net_device *netdev = dev_get_drvdata(dev);
4923 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4924 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4925 struct e1000_hw *hw = &adapter->hw;
4926 unsigned long event = *(unsigned long *)data;
4927
4928 switch (event) {
4929 case DCA_PROVIDER_ADD:
4930 /* if already enabled, don't do it again */
7dfc16fa 4931 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4932 break;
fe4506b6 4933 if (dca_add_requester(dev) == 0) {
bbd98fe4 4934 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4935 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4936 igb_setup_dca(adapter);
4937 break;
4938 }
4939 /* Fall Through since DCA is disabled. */
4940 case DCA_PROVIDER_REMOVE:
7dfc16fa 4941 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4942 /* without this a class_device is left
047e0030 4943 * hanging around in the sysfs model */
fe4506b6 4944 dca_remove_requester(dev);
090b1795 4945 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4946 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4947 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4948 }
4949 break;
4950 }
bbd98fe4 4951
fe4506b6 4952 return 0;
9d5c8243
AK		 4953}
4954
fe4506b6
JC		 4955static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4956 void *p)
4957{
4958 int ret_val;
4959
4960 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4961 __igb_notify_dca);
4962
4963 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4964}
421e02f0 4965#endif /* CONFIG_IGB_DCA */
9d5c8243 4966
0224d663
GR		 4967#ifdef CONFIG_PCI_IOV
4968static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4969{
4970 unsigned char mac_addr[ETH_ALEN];
0224d663 4971
7efd26d0 4972 eth_random_addr(mac_addr);
0224d663
GR		 4973 igb_set_vf_mac(adapter, vf, mac_addr);
4974
f557147c 4975 return 0;
0224d663
GR		 4976}
4977
f557147c 4978static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 4979{
0224d663 4980 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 4981 struct pci_dev *vfdev;
4982 int dev_id;
0224d663
GR		 4983
4984 switch (adapter->hw.mac.type) {
4985 case e1000_82576:
f557147c 4986 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 4987 break;
4988 case e1000_i350:
f557147c 4989 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 4990 break;
4991 default:
f557147c 4992 return false;
0224d663
GR		 4993 }
4994
f557147c
SA		 4995 /* loop through all the VFs to see if we own any that are assigned */
4996 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4997 while (vfdev) {
4998 /* if we don't own it we don't care */
4999 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5000 /* if it is assigned we cannot release it */
5001 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5002 return true;
5003 }
f557147c
SA		 5004
5005 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5006 }
f557147c 5007
0224d663
GR		 5008 return false;
5009}
5010
5011#endif
4ae196df
AD		 5012static void igb_ping_all_vfs(struct igb_adapter *adapter)
5013{
5014 struct e1000_hw *hw = &adapter->hw;
5015 u32 ping;
5016 int i;
5017
5018 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5019 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5020 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5021 ping |= E1000_VT_MSGTYPE_CTS;
5022 igb_write_mbx(hw, &ping, 1, i);
5023 }
5024}
5025
7d5753f0
AD		 5026static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5027{
5028 struct e1000_hw *hw = &adapter->hw;
5029 u32 vmolr = rd32(E1000_VMOLR(vf));
5030 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5031
d85b9004 5032 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5033 IGB_VF_FLAG_MULTI_PROMISC);
5034 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5035
5036 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5037 vmolr |= E1000_VMOLR_MPME;
d85b9004 5038 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5039 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5040 } else {
5041 /*
5042 * if we have hashes and we are clearing a multicast promisc
5043 * flag we need to write the hashes to the MTA as this step
5044 * was previously skipped
5045 */
5046 if (vf_data->num_vf_mc_hashes > 30) {
5047 vmolr |= E1000_VMOLR_MPME;
5048 } else if (vf_data->num_vf_mc_hashes) {
5049 int j;
5050 vmolr |= E1000_VMOLR_ROMPE;
5051 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5052 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5053 }
5054 }
5055
5056 wr32(E1000_VMOLR(vf), vmolr);
5057
5058 /* there are flags left unprocessed, likely not supported */
5059 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5060 return -EINVAL;
5061
5062 return 0;
5063
5064}
5065
4ae196df
AD		 5066static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5067 u32 *msgbuf, u32 vf)
5068{
5069 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5070 u16 *hash_list = (u16 *)&msgbuf[1];
5071 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5072 int i;
5073
7d5753f0 5074 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5075 * to this VF for later use to restore when the PF multi cast
5076 * list changes
5077 */
5078 vf_data->num_vf_mc_hashes = n;
5079
7d5753f0
AD		 5080 /* only up to 30 hash values supported */
5081 if (n > 30)
5082 n = 30;
5083
5084 /* store the hashes for later use */
4ae196df 5085 for (i = 0; i < n; i++)
a419aef8 5086 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5087
5088 /* Flush and reset the mta with the new values */
ff41f8dc 5089 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5090
5091 return 0;
5092}
5093
5094static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5095{
5096 struct e1000_hw *hw = &adapter->hw;
5097 struct vf_data_storage *vf_data;
5098 int i, j;
5099
5100 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5101 u32 vmolr = rd32(E1000_VMOLR(i));
5102 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5103
4ae196df 5104 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5105
5106 if ((vf_data->num_vf_mc_hashes > 30) ||
5107 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5108 vmolr |= E1000_VMOLR_MPME;
5109 } else if (vf_data->num_vf_mc_hashes) {
5110 vmolr |= E1000_VMOLR_ROMPE;
5111 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5112 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5113 }
5114 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5115 }
5116}
5117
5118static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5119{
5120 struct e1000_hw *hw = &adapter->hw;
5121 u32 pool_mask, reg, vid;
5122 int i;
5123
5124 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5125
5126 /* Find the vlan filter for this id */
5127 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5128 reg = rd32(E1000_VLVF(i));
5129
5130 /* remove the vf from the pool */
5131 reg &= ~pool_mask;
5132
5133 /* if pool is empty then remove entry from vfta */
5134 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5135 (reg & E1000_VLVF_VLANID_ENABLE)) {
5136 reg = 0;
5137 vid = reg & E1000_VLVF_VLANID_MASK;
5138 igb_vfta_set(hw, vid, false);
5139 }
5140
5141 wr32(E1000_VLVF(i), reg);
5142 }
ae641bdc
AD		 5143
5144 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5145}
5146
5147static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5148{
5149 struct e1000_hw *hw = &adapter->hw;
5150 u32 reg, i;
5151
51466239
AD		 5152 /* The vlvf table only exists on 82576 hardware and newer */
5153 if (hw->mac.type < e1000_82576)
5154 return -1;
5155
5156 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5157 if (!adapter->vfs_allocated_count)
5158 return -1;
5159
5160 /* Find the vlan filter for this id */
5161 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5162 reg = rd32(E1000_VLVF(i));
5163 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5164 vid == (reg & E1000_VLVF_VLANID_MASK))
5165 break;
5166 }
5167
5168 if (add) {
5169 if (i == E1000_VLVF_ARRAY_SIZE) {
5170 /* Did not find a matching VLAN ID entry that was
5171 * enabled. Search for a free filter entry, i.e.
5172 * one without the enable bit set
5173 */
5174 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5175 reg = rd32(E1000_VLVF(i));
5176 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5177 break;
5178 }
5179 }
5180 if (i < E1000_VLVF_ARRAY_SIZE) {
5181 /* Found an enabled/available entry */
5182 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5183
5184 /* if !enabled we need to set this up in vfta */
5185 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5186 /* add VID to filter table */
5187 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5188 reg |= E1000_VLVF_VLANID_ENABLE;
5189 }
cad6d05f
AD		 5190 reg &= ~E1000_VLVF_VLANID_MASK;
5191 reg |= vid;
4ae196df 5192 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5193
5194 /* do not modify RLPML for PF devices */
5195 if (vf >= adapter->vfs_allocated_count)
5196 return 0;
5197
5198 if (!adapter->vf_data[vf].vlans_enabled) {
5199 u32 size;
5200 reg = rd32(E1000_VMOLR(vf));
5201 size = reg & E1000_VMOLR_RLPML_MASK;
5202 size += 4;
5203 reg &= ~E1000_VMOLR_RLPML_MASK;
5204 reg |= size;
5205 wr32(E1000_VMOLR(vf), reg);
5206 }
ae641bdc 5207
51466239 5208 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5209 }
5210 } else {
5211 if (i < E1000_VLVF_ARRAY_SIZE) {
5212 /* remove vf from the pool */
5213 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5214 /* if pool is empty then remove entry from vfta */
5215 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5216 reg = 0;
5217 igb_vfta_set(hw, vid, false);
5218 }
5219 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5220
5221 /* do not modify RLPML for PF devices */
5222 if (vf >= adapter->vfs_allocated_count)
5223 return 0;
5224
5225 adapter->vf_data[vf].vlans_enabled--;
5226 if (!adapter->vf_data[vf].vlans_enabled) {
5227 u32 size;
5228 reg = rd32(E1000_VMOLR(vf));
5229 size = reg & E1000_VMOLR_RLPML_MASK;
5230 size -= 4;
5231 reg &= ~E1000_VMOLR_RLPML_MASK;
5232 reg |= size;
5233 wr32(E1000_VMOLR(vf), reg);
5234 }
4ae196df
AD		 5235 }
5236 }
8151d294
WM		 5237 return 0;
5238}
5239
5240static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5241{
5242 struct e1000_hw *hw = &adapter->hw;
5243
5244 if (vid)
5245 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5246 else
5247 wr32(E1000_VMVIR(vf), 0);
5248}
5249
5250static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5251 int vf, u16 vlan, u8 qos)
5252{
5253 int err = 0;
5254 struct igb_adapter *adapter = netdev_priv(netdev);
5255
5256 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5257 return -EINVAL;
5258 if (vlan || qos) {
5259 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5260 if (err)
5261 goto out;
5262 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5263 igb_set_vmolr(adapter, vf, !vlan);
5264 adapter->vf_data[vf].pf_vlan = vlan;
5265 adapter->vf_data[vf].pf_qos = qos;
5266 dev_info(&adapter->pdev->dev,
5267 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5268 if (test_bit(__IGB_DOWN, &adapter->state)) {
5269 dev_warn(&adapter->pdev->dev,
5270 "The VF VLAN has been set,"
5271 " but the PF device is not up.\n");
5272 dev_warn(&adapter->pdev->dev,
5273 "Bring the PF device up before"
5274 " attempting to use the VF device.\n");
5275 }
5276 } else {
5277 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5278 false, vf);
5279 igb_set_vmvir(adapter, vlan, vf);
5280 igb_set_vmolr(adapter, vf, true);
5281 adapter->vf_data[vf].pf_vlan = 0;
5282 adapter->vf_data[vf].pf_qos = 0;
5283 }
5284out:
5285 return err;
4ae196df
AD		 5286}
5287
5288static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5289{
5290 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5291 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5292
5293 return igb_vlvf_set(adapter, vid, add, vf);
5294}
5295
f2ca0dbe 5296static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5297{
8fa7e0f7
GR		 5298 /* clear flags - except flag that indicates PF has set the MAC */
5299 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5300 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5301
5302 /* reset offloads to defaults */
8151d294 5303 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5304
5305 /* reset vlans for device */
5306 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5307 if (adapter->vf_data[vf].pf_vlan)
5308 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5309 adapter->vf_data[vf].pf_vlan,
5310 adapter->vf_data[vf].pf_qos);
5311 else
5312 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5313
5314 /* reset multicast table array for vf */
5315 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5316
5317 /* Flush and reset the mta with the new values */
ff41f8dc 5318 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5319}
5320
f2ca0dbe
AD		 5321static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5322{
5323 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5324
5325 /* generate a new mac address as we were hotplug removed/added */
8151d294 5326 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5327 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5328
5329 /* process remaining reset events */
5330 igb_vf_reset(adapter, vf);
5331}
5332
5333static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5334{
5335 struct e1000_hw *hw = &adapter->hw;
5336 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5337 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5338 u32 reg, msgbuf[3];
5339 u8 *addr = (u8 *)(&msgbuf[1]);
5340
5341 /* process all the same items cleared in a function level reset */
f2ca0dbe 5342 igb_vf_reset(adapter, vf);
4ae196df
AD		 5343
5344 /* set vf mac address */
26ad9178 5345 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5346
5347 /* enable transmit and receive for vf */
5348 reg = rd32(E1000_VFTE);
5349 wr32(E1000_VFTE, reg | (1 << vf));
5350 reg = rd32(E1000_VFRE);
5351 wr32(E1000_VFRE, reg | (1 << vf));
5352
8fa7e0f7 5353 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5354
5355 /* reply to reset with ack and vf mac address */
5356 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5357 memcpy(addr, vf_mac, 6);
5358 igb_write_mbx(hw, msgbuf, 3, vf);
5359}
5360
5361static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5362{
de42edde
GR		 5363 /*
5364 * The VF MAC Address is stored in a packed array of bytes
5365 * starting at the second 32 bit word of the msg array
5366 */
f2ca0dbe
AD		 5367 unsigned char *addr = (char *)&msg[1];
5368 int err = -1;
4ae196df 5369
f2ca0dbe
AD		 5370 if (is_valid_ether_addr(addr))
5371 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5372
f2ca0dbe 5373 return err;
4ae196df
AD		 5374}
5375
5376static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5377{
5378 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5379 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5380 u32 msg = E1000_VT_MSGTYPE_NACK;
5381
5382 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5383 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5384 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5385 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5386 vf_data->last_nack = jiffies;
4ae196df
AD		 5387 }
5388}
5389
f2ca0dbe 5390static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5391{
f2ca0dbe
AD		 5392 struct pci_dev *pdev = adapter->pdev;
5393 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5394 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5395 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5396 s32 retval;
5397
f2ca0dbe 5398 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5399
fef45f4c
AD		 5400 if (retval) {
5401 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5402 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5403 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5404 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5405 return;
5406 goto out;
5407 }
4ae196df
AD		 5408
5409 /* this is a message we already processed, do nothing */
5410 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5411 return;
4ae196df
AD		 5412
5413 /*
5414 * until the vf completes a reset it should not be
5415 * allowed to start any configuration.
5416 */
5417
5418 if (msgbuf[0] == E1000_VF_RESET) {
5419 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5420 return;
4ae196df
AD		 5421 }
5422
f2ca0dbe 5423 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5424 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5425 return;
5426 retval = -1;
5427 goto out;
4ae196df
AD		 5428 }
5429
5430 switch ((msgbuf[0] & 0xFFFF)) {
5431 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5432 retval = -EINVAL;
5433 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5434 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5435 else
5436 dev_warn(&pdev->dev,
5437 "VF %d attempted to override administratively "
5438 "set MAC address\nReload the VF driver to "
5439 "resume operations\n", vf);
4ae196df 5440 break;
7d5753f0
AD		 5441 case E1000_VF_SET_PROMISC:
5442 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5443 break;
4ae196df
AD		 5444 case E1000_VF_SET_MULTICAST:
5445 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5446 break;
5447 case E1000_VF_SET_LPE:
5448 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5449 break;
5450 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5451 retval = -1;
5452 if (vf_data->pf_vlan)
5453 dev_warn(&pdev->dev,
5454 "VF %d attempted to override administratively "
5455 "set VLAN tag\nReload the VF driver to "
5456 "resume operations\n", vf);
8151d294
WM		 5457 else
5458 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5459 break;
5460 default:
090b1795 5461 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5462 retval = -1;
5463 break;
5464 }
5465
fef45f4c
AD		 5466 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5467out:
4ae196df
AD		 5468 /* notify the VF of the results of what it sent us */
5469 if (retval)
5470 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5471 else
5472 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5473
4ae196df 5474 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5475}
4ae196df 5476
f2ca0dbe
AD		 5477static void igb_msg_task(struct igb_adapter *adapter)
5478{
5479 struct e1000_hw *hw = &adapter->hw;
5480 u32 vf;
5481
5482 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5483 /* process any reset requests */
5484 if (!igb_check_for_rst(hw, vf))
5485 igb_vf_reset_event(adapter, vf);
5486
5487 /* process any messages pending */
5488 if (!igb_check_for_msg(hw, vf))
5489 igb_rcv_msg_from_vf(adapter, vf);
5490
5491 /* process any acks */
5492 if (!igb_check_for_ack(hw, vf))
5493 igb_rcv_ack_from_vf(adapter, vf);
5494 }
4ae196df
AD		 5495}
5496
68d480c4
AD		 5497/**
5498 * igb_set_uta - Set unicast filter table address
5499 * @adapter: board private structure
5500 *
5501 * The unicast table address is a register array of 32-bit registers.
5502 * The table is meant to be used in a way similar to how the MTA is used
5503 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5504 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5505 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5506 **/
5507static void igb_set_uta(struct igb_adapter *adapter)
5508{
5509 struct e1000_hw *hw = &adapter->hw;
5510 int i;
5511
5512 /* The UTA table only exists on 82576 hardware and newer */
5513 if (hw->mac.type < e1000_82576)
5514 return;
5515
5516 /* we only need to do this if VMDq is enabled */
5517 if (!adapter->vfs_allocated_count)
5518 return;
5519
5520 for (i = 0; i < hw->mac.uta_reg_count; i++)
5521 array_wr32(E1000_UTA, i, ~0);
5522}
5523
9d5c8243
AK		 5524/**
5525 * igb_intr_msi - Interrupt Handler
5526 * @irq: interrupt number
5527 * @data: pointer to a network interface device structure
5528 **/
5529static irqreturn_t igb_intr_msi(int irq, void *data)
5530{
047e0030
AD		 5531 struct igb_adapter *adapter = data;
5532 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5533 struct e1000_hw *hw = &adapter->hw;
5534 /* read ICR disables interrupts using IAM */
5535 u32 icr = rd32(E1000_ICR);
5536
047e0030 5537 igb_write_itr(q_vector);
9d5c8243 5538
7f081d40
AD		 5539 if (icr & E1000_ICR_DRSTA)
5540 schedule_work(&adapter->reset_task);
5541
047e0030 5542 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5543 /* HW is reporting DMA is out of sync */
5544 adapter->stats.doosync++;
5545 }
5546
9d5c8243
AK		 5547 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5548 hw->mac.get_link_status = 1;
5549 if (!test_bit(__IGB_DOWN, &adapter->state))
5550 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5551 }
5552
1f6e8178
MV		 5553 if (icr & E1000_ICR_TS) {
5554 u32 tsicr = rd32(E1000_TSICR);
5555
5556 if (tsicr & E1000_TSICR_TXTS) {
5557 /* acknowledge the interrupt */
5558 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5559 /* retrieve hardware timestamp */
5560 schedule_work(&adapter->ptp_tx_work);
5561 }
5562 }
1f6e8178 5563
047e0030 5564 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5565
5566 return IRQ_HANDLED;
5567}
5568
5569/**
4a3c6433 5570 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5571 * @irq: interrupt number
5572 * @data: pointer to a network interface device structure
5573 **/
5574static irqreturn_t igb_intr(int irq, void *data)
5575{
047e0030
AD		 5576 struct igb_adapter *adapter = data;
5577 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5578 struct e1000_hw *hw = &adapter->hw;
5579 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5580 * need for the IMC write */
5581 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5582
5583 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5584 * not set, then the adapter didn't send an interrupt */
5585 if (!(icr & E1000_ICR_INT_ASSERTED))
5586 return IRQ_NONE;
5587
0ba82994
AD		 5588 igb_write_itr(q_vector);
5589
7f081d40
AD		 5590 if (icr & E1000_ICR_DRSTA)
5591 schedule_work(&adapter->reset_task);
5592
047e0030 5593 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5594 /* HW is reporting DMA is out of sync */
5595 adapter->stats.doosync++;
5596 }
5597
9d5c8243
AK		 5598 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5599 hw->mac.get_link_status = 1;
5600 /* guard against interrupt when we're going down */
5601 if (!test_bit(__IGB_DOWN, &adapter->state))
5602 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5603 }
5604
1f6e8178
MV		 5605 if (icr & E1000_ICR_TS) {
5606 u32 tsicr = rd32(E1000_TSICR);
5607
5608 if (tsicr & E1000_TSICR_TXTS) {
5609 /* acknowledge the interrupt */
5610 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5611 /* retrieve hardware timestamp */
5612 schedule_work(&adapter->ptp_tx_work);
5613 }
5614 }
1f6e8178 5615
047e0030 5616 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5617
5618 return IRQ_HANDLED;
5619}
5620
c50b52a0 5621static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5622{
047e0030 5623 struct igb_adapter *adapter = q_vector->adapter;
46544258 5624 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5625
0ba82994
AD		 5626 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5627 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5628 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5629 igb_set_itr(q_vector);
46544258 5630 else
047e0030 5631 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5632 }
5633
46544258
AD		 5634 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5635 if (adapter->msix_entries)
047e0030 5636 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5637 else
5638 igb_irq_enable(adapter);
5639 }
9d5c8243
AK		 5640}
5641
46544258
AD		 5642/**
5643 * igb_poll - NAPI Rx polling callback
5644 * @napi: napi polling structure
5645 * @budget: count of how many packets we should handle
5646 **/
5647static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5648{
047e0030
AD		 5649 struct igb_q_vector *q_vector = container_of(napi,
5650 struct igb_q_vector,
5651 napi);
16eb8815 5652 bool clean_complete = true;
9d5c8243 5653
421e02f0 5654#ifdef CONFIG_IGB_DCA
047e0030
AD		 5655 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5656 igb_update_dca(q_vector);
fe4506b6 5657#endif
0ba82994 5658 if (q_vector->tx.ring)
13fde97a 5659 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5660
0ba82994 5661 if (q_vector->rx.ring)
cd392f5c 5662 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5663
16eb8815
AD		 5664 /* If all work not completed, return budget and keep polling */
5665 if (!clean_complete)
5666 return budget;
46544258 5667
9d5c8243 5668 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5669 napi_complete(napi);
5670 igb_ring_irq_enable(q_vector);
9d5c8243 5671
16eb8815 5672 return 0;
9d5c8243 5673}
6d8126f9 5674
9d5c8243
AK		 5675/**
5676 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5677 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5678 *
9d5c8243
AK		 5679 * returns true if ring is completely cleaned
5680 **/
047e0030 5681static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5682{
047e0030 5683 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5684 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5685 struct igb_tx_buffer *tx_buffer;
f4128785 5686 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5687 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5688 unsigned int budget = q_vector->tx.work_limit;
8542db05 5689 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5690
13fde97a
AD		 5691 if (test_bit(__IGB_DOWN, &adapter->state))
5692 return true;
0e014cb1 5693
06034649 5694 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5695 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5696 i -= tx_ring->count;
9d5c8243 5697
f4128785
AD		 5698 do {
5699 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5700
5701 /* if next_to_watch is not set then there is no work pending */
5702 if (!eop_desc)
5703 break;
13fde97a 5704
f4128785
AD		 5705 /* prevent any other reads prior to eop_desc */
5706 rmb();
5707
13fde97a
AD		 5708 /* if DD is not set pending work has not been completed */
5709 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5710 break;
5711
8542db05
AD		 5712 /* clear next_to_watch to prevent false hangs */
5713 tx_buffer->next_to_watch = NULL;
9d5c8243 5714
ebe42d16
AD		 5715 /* update the statistics for this packet */
5716 total_bytes += tx_buffer->bytecount;
5717 total_packets += tx_buffer->gso_segs;
13fde97a 5718
ebe42d16
AD		 5719 /* free the skb */
5720 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5721
ebe42d16
AD		 5722 /* unmap skb header data */
5723 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5724 dma_unmap_addr(tx_buffer, dma),
5725 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5726 DMA_TO_DEVICE);
5727
c9f14bf3
AD		 5728 /* clear tx_buffer data */
5729 tx_buffer->skb = NULL;
5730 dma_unmap_len_set(tx_buffer, len, 0);
5731
ebe42d16
AD		 5732 /* clear last DMA location and unmap remaining buffers */
5733 while (tx_desc != eop_desc) {
13fde97a
AD		 5734 tx_buffer++;
5735 tx_desc++;
9d5c8243 5736 i++;
8542db05
AD		 5737 if (unlikely(!i)) {
5738 i -= tx_ring->count;
06034649 5739 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5740 tx_desc = IGB_TX_DESC(tx_ring, 0);
5741 }
ebe42d16
AD		 5742
5743 /* unmap any remaining paged data */
c9f14bf3 5744 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5745 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5746 dma_unmap_addr(tx_buffer, dma),
5747 dma_unmap_len(tx_buffer, len),
ebe42d16 5748 DMA_TO_DEVICE);
c9f14bf3 5749 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5750 }
5751 }
5752
ebe42d16
AD		 5753 /* move us one more past the eop_desc for start of next pkt */
5754 tx_buffer++;
5755 tx_desc++;
5756 i++;
5757 if (unlikely(!i)) {
5758 i -= tx_ring->count;
5759 tx_buffer = tx_ring->tx_buffer_info;
5760 tx_desc = IGB_TX_DESC(tx_ring, 0);
5761 }
f4128785
AD		 5762
5763 /* issue prefetch for next Tx descriptor */
5764 prefetch(tx_desc);
5765
5766 /* update budget accounting */
5767 budget--;
5768 } while (likely(budget));
0e014cb1 5769
bdbc0631
ED		 5770 netdev_tx_completed_queue(txring_txq(tx_ring),
5771 total_packets, total_bytes);
8542db05 5772 i += tx_ring->count;
9d5c8243 5773 tx_ring->next_to_clean = i;
13fde97a
AD		 5774 u64_stats_update_begin(&tx_ring->tx_syncp);
5775 tx_ring->tx_stats.bytes += total_bytes;
5776 tx_ring->tx_stats.packets += total_packets;
5777 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5778 q_vector->tx.total_bytes += total_bytes;
5779 q_vector->tx.total_packets += total_packets;
9d5c8243 5780
6d095fa8 5781 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5782 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5783
9d5c8243
AK		 5784 /* Detect a transmit hang in hardware, this serializes the
5785 * check with the clearing of time_stamp and movement of i */
6d095fa8 5786 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5787 if (tx_buffer->next_to_watch &&
8542db05 5788 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5789 (adapter->tx_timeout_factor * HZ)) &&
5790 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5791
9d5c8243 5792 /* detected Tx unit hang */
59d71989 5793 dev_err(tx_ring->dev,
9d5c8243 5794 "Detected Tx Unit Hang\n"
2d064c06 5795 " Tx Queue <%d>\n"
9d5c8243
AK		 5796 " TDH <%x>\n"
5797 " TDT <%x>\n"
5798 " next_to_use <%x>\n"
5799 " next_to_clean <%x>\n"
9d5c8243
AK		 5800 "buffer_info[next_to_clean]\n"
5801 " time_stamp <%lx>\n"
8542db05 5802 " next_to_watch <%p>\n"
9d5c8243
AK		 5803 " jiffies <%lx>\n"
5804 " desc.status <%x>\n",
2d064c06 5805 tx_ring->queue_index,
238ac817 5806 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5807 readl(tx_ring->tail),
9d5c8243
AK		 5808 tx_ring->next_to_use,
5809 tx_ring->next_to_clean,
8542db05 5810 tx_buffer->time_stamp,
f4128785 5811 tx_buffer->next_to_watch,
9d5c8243 5812 jiffies,
f4128785 5813 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 5814 netif_stop_subqueue(tx_ring->netdev,
5815 tx_ring->queue_index);
5816
5817 /* we are about to reset, no point in enabling stuff */
5818 return true;
9d5c8243
AK		 5819 }
5820 }
13fde97a
AD		 5821
5822 if (unlikely(total_packets &&
5823 netif_carrier_ok(tx_ring->netdev) &&
5824 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5825 /* Make sure that anybody stopping the queue after this
5826 * sees the new next_to_clean.
5827 */
5828 smp_mb();
5829 if (__netif_subqueue_stopped(tx_ring->netdev,
5830 tx_ring->queue_index) &&
5831 !(test_bit(__IGB_DOWN, &adapter->state))) {
5832 netif_wake_subqueue(tx_ring->netdev,
5833 tx_ring->queue_index);
5834
5835 u64_stats_update_begin(&tx_ring->tx_syncp);
5836 tx_ring->tx_stats.restart_queue++;
5837 u64_stats_update_end(&tx_ring->tx_syncp);
5838 }
5839 }
5840
5841 return !!budget;
9d5c8243
AK		 5842}
5843
cbc8e55f
AD		 5844/**
5845 * igb_reuse_rx_page - page flip buffer and store it back on the ring
5846 * @rx_ring: rx descriptor ring to store buffers on
5847 * @old_buff: donor buffer to have page reused
5848 *
5849 * Synchronizes page for reuse by the adapter
5850 **/
5851static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5852 struct igb_rx_buffer *old_buff)
5853{
5854 struct igb_rx_buffer *new_buff;
5855 u16 nta = rx_ring->next_to_alloc;
5856
5857 new_buff = &rx_ring->rx_buffer_info[nta];
5858
5859 /* update, and store next to alloc */
5860 nta++;
5861 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5862
5863 /* transfer page from old buffer to new buffer */
5864 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5865
5866 /* sync the buffer for use by the device */
5867 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5868 old_buff->page_offset,
de78d1f9 5869 IGB_RX_BUFSZ,
cbc8e55f
AD		 5870 DMA_FROM_DEVICE);
5871}
5872
5873/**
5874 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5875 * @rx_ring: rx descriptor ring to transact packets on
5876 * @rx_buffer: buffer containing page to add
5877 * @rx_desc: descriptor containing length of buffer written by hardware
5878 * @skb: sk_buff to place the data into
5879 *
5880 * This function will add the data contained in rx_buffer->page to the skb.
5881 * This is done either through a direct copy if the data in the buffer is
5882 * less than the skb header size, otherwise it will just attach the page as
5883 * a frag to the skb.
5884 *
5885 * The function will then update the page offset if necessary and return
5886 * true if the buffer can be reused by the adapter.
5887 **/
5888static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5889 struct igb_rx_buffer *rx_buffer,
5890 union e1000_adv_rx_desc *rx_desc,
5891 struct sk_buff *skb)
5892{
5893 struct page *page = rx_buffer->page;
5894 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5895
5896 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5897 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5898
cbc8e55f
AD		 5899 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5900 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5901 va += IGB_TS_HDR_LEN;
5902 size -= IGB_TS_HDR_LEN;
5903 }
5904
cbc8e55f
AD		 5905 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5906
5907 /* we can reuse buffer as-is, just make sure it is local */
5908 if (likely(page_to_nid(page) == numa_node_id()))
5909 return true;
5910
5911 /* this page cannot be reused so discard it */
5912 put_page(page);
5913 return false;
5914 }
5915
5916 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 5917 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 5918
5919 /* avoid re-using remote pages */
5920 if (unlikely(page_to_nid(page) != numa_node_id()))
5921 return false;
5922
de78d1f9 5923#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 5924 /* if we are only owner of page we can reuse it */
5925 if (unlikely(page_count(page) != 1))
5926 return false;
5927
5928 /* flip page offset to other buffer */
de78d1f9 5929 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 5930
5931 /*
5932 * since we are the only owner of the page and we need to
5933 * increment it, just set the value to 2 in order to avoid
5934 * an unnecessary locked operation
5935 */
5936 atomic_set(&page->_count, 2);
de78d1f9
AD		 5937#else
5938 /* move offset up to the next cache line */
5939 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5940
5941 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5942 return false;
5943
5944 /* bump ref count on page before it is given to the stack */
5945 get_page(page);
5946#endif
cbc8e55f
AD		 5947
5948 return true;
5949}
5950
2e334eee
AD		 5951static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5952 union e1000_adv_rx_desc *rx_desc,
5953 struct sk_buff *skb)
5954{
5955 struct igb_rx_buffer *rx_buffer;
5956 struct page *page;
5957
5958 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5959
5960 /*
5961 * This memory barrier is needed to keep us from reading
5962 * any other fields out of the rx_desc until we know the
5963 * RXD_STAT_DD bit is set
5964 */
5965 rmb();
5966
5967 page = rx_buffer->page;
5968 prefetchw(page);
5969
5970 if (likely(!skb)) {
5971 void *page_addr = page_address(page) +
5972 rx_buffer->page_offset;
5973
5974 /* prefetch first cache line of first page */
5975 prefetch(page_addr);
5976#if L1_CACHE_BYTES < 128
5977 prefetch(page_addr + L1_CACHE_BYTES);
5978#endif
5979
5980 /* allocate a skb to store the frags */
5981 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5982 IGB_RX_HDR_LEN);
5983 if (unlikely(!skb)) {
5984 rx_ring->rx_stats.alloc_failed++;
5985 return NULL;
5986 }
5987
5988 /*
5989 * we will be copying header into skb->data in
5990 * pskb_may_pull so it is in our interest to prefetch
5991 * it now to avoid a possible cache miss
5992 */
5993 prefetchw(skb->data);
5994 }
5995
5996 /* we are reusing so sync this buffer for CPU use */
5997 dma_sync_single_range_for_cpu(rx_ring->dev,
5998 rx_buffer->dma,
5999 rx_buffer->page_offset,
de78d1f9 6000 IGB_RX_BUFSZ,
2e334eee
AD		 6001 DMA_FROM_DEVICE);
6002
6003 /* pull page into skb */
6004 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6005 /* hand second half of page back to the ring */
6006 igb_reuse_rx_page(rx_ring, rx_buffer);
6007 } else {
6008 /* we are not reusing the buffer so unmap it */
6009 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6010 PAGE_SIZE, DMA_FROM_DEVICE);
6011 }
6012
6013 /* clear contents of rx_buffer */
6014 rx_buffer->page = NULL;
6015
6016 return skb;
6017}
6018
cd392f5c 6019static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6020 union e1000_adv_rx_desc *rx_desc,
6021 struct sk_buff *skb)
9d5c8243 6022{
bc8acf2c 6023 skb_checksum_none_assert(skb);
9d5c8243 6024
294e7d78 6025 /* Ignore Checksum bit is set */
3ceb90fd 6026 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6027 return;
6028
6029 /* Rx checksum disabled via ethtool */
6030 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6031 return;
85ad76b2 6032
9d5c8243 6033 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6034 if (igb_test_staterr(rx_desc,
6035 E1000_RXDEXT_STATERR_TCPE |
6036 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6037 /*
6038 * work around errata with sctp packets where the TCPE aka
6039 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6040 * packets, (aka let the stack check the crc32c)
6041 */
866cff06
AD		 6042 if (!((skb->len == 60) &&
6043 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6044 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6045 ring->rx_stats.csum_err++;
12dcd86b
ED		 6046 u64_stats_update_end(&ring->rx_syncp);
6047 }
9d5c8243 6048 /* let the stack verify checksum errors */
9d5c8243
AK		 6049 return;
6050 }
6051 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6052 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6053 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6054 skb->ip_summed = CHECKSUM_UNNECESSARY;
6055
3ceb90fd
AD		 6056 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6057 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6058}
6059
077887c3
AD		 6060static inline void igb_rx_hash(struct igb_ring *ring,
6061 union e1000_adv_rx_desc *rx_desc,
6062 struct sk_buff *skb)
6063{
6064 if (ring->netdev->features & NETIF_F_RXHASH)
6065 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6066}
6067
2e334eee
AD		 6068/**
6069 * igb_is_non_eop - process handling of non-EOP buffers
6070 * @rx_ring: Rx ring being processed
6071 * @rx_desc: Rx descriptor for current buffer
6072 * @skb: current socket buffer containing buffer in progress
6073 *
6074 * This function updates next to clean. If the buffer is an EOP buffer
6075 * this function exits returning false, otherwise it will place the
6076 * sk_buff in the next buffer to be chained and return true indicating
6077 * that this is in fact a non-EOP buffer.
6078 **/
6079static bool igb_is_non_eop(struct igb_ring *rx_ring,
6080 union e1000_adv_rx_desc *rx_desc)
6081{
6082 u32 ntc = rx_ring->next_to_clean + 1;
6083
6084 /* fetch, update, and store next to clean */
6085 ntc = (ntc < rx_ring->count) ? ntc : 0;
6086 rx_ring->next_to_clean = ntc;
6087
6088 prefetch(IGB_RX_DESC(rx_ring, ntc));
6089
6090 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6091 return false;
6092
6093 return true;
6094}
6095
1a1c225b
AD		 6096/**
6097 * igb_get_headlen - determine size of header for LRO/GRO
6098 * @data: pointer to the start of the headers
6099 * @max_len: total length of section to find headers in
6100 *
6101 * This function is meant to determine the length of headers that will
6102 * be recognized by hardware for LRO, and GRO offloads. The main
6103 * motivation of doing this is to only perform one pull for IPv4 TCP
6104 * packets so that we can do basic things like calculating the gso_size
6105 * based on the average data per packet.
6106 **/
6107static unsigned int igb_get_headlen(unsigned char *data,
6108 unsigned int max_len)
6109{
6110 union {
6111 unsigned char *network;
6112 /* l2 headers */
6113 struct ethhdr *eth;
6114 struct vlan_hdr *vlan;
6115 /* l3 headers */
6116 struct iphdr *ipv4;
6117 struct ipv6hdr *ipv6;
6118 } hdr;
6119 __be16 protocol;
6120 u8 nexthdr = 0; /* default to not TCP */
6121 u8 hlen;
6122
6123 /* this should never happen, but better safe than sorry */
6124 if (max_len < ETH_HLEN)
6125 return max_len;
6126
6127 /* initialize network frame pointer */
6128 hdr.network = data;
6129
6130 /* set first protocol and move network header forward */
6131 protocol = hdr.eth->h_proto;
6132 hdr.network += ETH_HLEN;
6133
6134 /* handle any vlan tag if present */
6135 if (protocol == __constant_htons(ETH_P_8021Q)) {
6136 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6137 return max_len;
6138
6139 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6140 hdr.network += VLAN_HLEN;
6141 }
6142
6143 /* handle L3 protocols */
6144 if (protocol == __constant_htons(ETH_P_IP)) {
6145 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6146 return max_len;
6147
6148 /* access ihl as a u8 to avoid unaligned access on ia64 */
6149 hlen = (hdr.network[0] & 0x0F) << 2;
6150
6151 /* verify hlen meets minimum size requirements */
6152 if (hlen < sizeof(struct iphdr))
6153 return hdr.network - data;
6154
f2fb4ab2
AD		 6155 /* record next protocol if header is present */
6156 if (!hdr.ipv4->frag_off)
6157 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6158 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6159 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6160 return max_len;
6161
6162 /* record next protocol */
6163 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6164 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6165 } else {
6166 return hdr.network - data;
6167 }
6168
f2fb4ab2
AD		 6169 /* relocate pointer to start of L4 header */
6170 hdr.network += hlen;
6171
1a1c225b
AD		 6172 /* finally sort out TCP */
6173 if (nexthdr == IPPROTO_TCP) {
6174 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6175 return max_len;
6176
6177 /* access doff as a u8 to avoid unaligned access on ia64 */
6178 hlen = (hdr.network[12] & 0xF0) >> 2;
6179
6180 /* verify hlen meets minimum size requirements */
6181 if (hlen < sizeof(struct tcphdr))
6182 return hdr.network - data;
6183
6184 hdr.network += hlen;
6185 } else if (nexthdr == IPPROTO_UDP) {
6186 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6187 return max_len;
6188
6189 hdr.network += sizeof(struct udphdr);
6190 }
6191
6192 /*
6193 * If everything has gone correctly hdr.network should be the
6194 * data section of the packet and will be the end of the header.
6195 * If not then it probably represents the end of the last recognized
6196 * header.
6197 */
6198 if ((hdr.network - data) < max_len)
6199 return hdr.network - data;
6200 else
6201 return max_len;
6202}
6203
6204/**
6205 * igb_pull_tail - igb specific version of skb_pull_tail
6206 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6207 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6208 * @skb: pointer to current skb being adjusted
6209 *
6210 * This function is an igb specific version of __pskb_pull_tail. The
6211 * main difference between this version and the original function is that
6212 * this function can make several assumptions about the state of things
6213 * that allow for significant optimizations versus the standard function.
6214 * As a result we can do things like drop a frag and maintain an accurate
6215 * truesize for the skb.
6216 */
6217static void igb_pull_tail(struct igb_ring *rx_ring,
6218 union e1000_adv_rx_desc *rx_desc,
6219 struct sk_buff *skb)
2d94d8ab 6220{
1a1c225b
AD		 6221 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6222 unsigned char *va;
6223 unsigned int pull_len;
6224
6225 /*
6226 * it is valid to use page_address instead of kmap since we are
6227 * working with pages allocated out of the lomem pool per
6228 * alloc_page(GFP_ATOMIC)
2d94d8ab 6229 */
1a1c225b
AD		 6230 va = skb_frag_address(frag);
6231
1a1c225b
AD		 6232 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6233 /* retrieve timestamp from buffer */
6234 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6235
6236 /* update pointers to remove timestamp header */
6237 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6238 frag->page_offset += IGB_TS_HDR_LEN;
6239 skb->data_len -= IGB_TS_HDR_LEN;
6240 skb->len -= IGB_TS_HDR_LEN;
6241
6242 /* move va to start of packet data */
6243 va += IGB_TS_HDR_LEN;
6244 }
6245
1a1c225b
AD		 6246 /*
6247 * we need the header to contain the greater of either ETH_HLEN or
6248 * 60 bytes if the skb->len is less than 60 for skb_pad.
6249 */
6250 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6251
6252 /* align pull length to size of long to optimize memcpy performance */
6253 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6254
6255 /* update all of the pointers */
6256 skb_frag_size_sub(frag, pull_len);
6257 frag->page_offset += pull_len;
6258 skb->data_len -= pull_len;
6259 skb->tail += pull_len;
6260}
6261
6262/**
6263 * igb_cleanup_headers - Correct corrupted or empty headers
6264 * @rx_ring: rx descriptor ring packet is being transacted on
6265 * @rx_desc: pointer to the EOP Rx descriptor
6266 * @skb: pointer to current skb being fixed
6267 *
6268 * Address the case where we are pulling data in on pages only
6269 * and as such no data is present in the skb header.
6270 *
6271 * In addition if skb is not at least 60 bytes we need to pad it so that
6272 * it is large enough to qualify as a valid Ethernet frame.
6273 *
6274 * Returns true if an error was encountered and skb was freed.
6275 **/
6276static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6277 union e1000_adv_rx_desc *rx_desc,
6278 struct sk_buff *skb)
6279{
6280
6281 if (unlikely((igb_test_staterr(rx_desc,
6282 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6283 struct net_device *netdev = rx_ring->netdev;
6284 if (!(netdev->features & NETIF_F_RXALL)) {
6285 dev_kfree_skb_any(skb);
6286 return true;
6287 }
6288 }
6289
6290 /* place header in linear portion of buffer */
6291 if (skb_is_nonlinear(skb))
6292 igb_pull_tail(rx_ring, rx_desc, skb);
6293
6294 /* if skb_pad returns an error the skb was freed */
6295 if (unlikely(skb->len < 60)) {
6296 int pad_len = 60 - skb->len;
6297
6298 if (skb_pad(skb, pad_len))
6299 return true;
6300 __skb_put(skb, pad_len);
6301 }
6302
6303 return false;
2d94d8ab
AD		 6304}
6305
db2ee5bd
AD		 6306/**
6307 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6308 * @rx_ring: rx descriptor ring packet is being transacted on
6309 * @rx_desc: pointer to the EOP Rx descriptor
6310 * @skb: pointer to current skb being populated
6311 *
6312 * This function checks the ring, descriptor, and packet information in
6313 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6314 * other fields within the skb.
6315 **/
6316static void igb_process_skb_fields(struct igb_ring *rx_ring,
6317 union e1000_adv_rx_desc *rx_desc,
6318 struct sk_buff *skb)
6319{
6320 struct net_device *dev = rx_ring->netdev;
6321
6322 igb_rx_hash(rx_ring, rx_desc, skb);
6323
6324 igb_rx_checksum(rx_ring, rx_desc, skb);
6325
db2ee5bd 6326 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6327
6328 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6329 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6330 u16 vid;
6331 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6332 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6333 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6334 else
6335 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6336
6337 __vlan_hwaccel_put_tag(skb, vid);
6338 }
6339
6340 skb_record_rx_queue(skb, rx_ring->queue_index);
6341
6342 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6343}
6344
2e334eee 6345static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6346{
0ba82994 6347 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6348 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6349 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6350 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6351
2e334eee
AD		 6352 do {
6353 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6354
2e334eee
AD		 6355 /* return some buffers to hardware, one at a time is too slow */
6356 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6357 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6358 cleaned_count = 0;
6359 }
bf36c1a0 6360
2e334eee 6361 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6362
2e334eee
AD		 6363 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6364 break;
9d5c8243 6365
2e334eee
AD		 6366 /* retrieve a buffer from the ring */
6367 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6368
2e334eee
AD		 6369 /* exit if we failed to retrieve a buffer */
6370 if (!skb)
6371 break;
1a1c225b 6372
2e334eee 6373 cleaned_count++;
1a1c225b 6374
2e334eee
AD		 6375 /* fetch next buffer in frame if non-eop */
6376 if (igb_is_non_eop(rx_ring, rx_desc))
6377 continue;
1a1c225b
AD		 6378
6379 /* verify the packet layout is correct */
6380 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6381 skb = NULL;
6382 continue;
9d5c8243 6383 }
9d5c8243 6384
db2ee5bd 6385 /* probably a little skewed due to removing CRC */
3ceb90fd 6386 total_bytes += skb->len;
3ceb90fd 6387
db2ee5bd
AD		 6388 /* populate checksum, timestamp, VLAN, and protocol */
6389 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6390
b2cb09b1 6391 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6392
1a1c225b
AD		 6393 /* reset skb pointer */
6394 skb = NULL;
6395
2e334eee
AD		 6396 /* update budget accounting */
6397 total_packets++;
6398 } while (likely(total_packets < budget));
bf36c1a0 6399
1a1c225b
AD		 6400 /* place incomplete frames back on ring for completion */
6401 rx_ring->skb = skb;
6402
12dcd86b 6403 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6404 rx_ring->rx_stats.packets += total_packets;
6405 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6406 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6407 q_vector->rx.total_packets += total_packets;
6408 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6409
6410 if (cleaned_count)
cd392f5c 6411 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6412
2e334eee 6413 return (total_packets < budget);
9d5c8243
AK		 6414}
6415
c023cd88 6416static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6417 struct igb_rx_buffer *bi)
c023cd88
AD		 6418{
6419 struct page *page = bi->page;
cbc8e55f 6420 dma_addr_t dma;
c023cd88 6421
cbc8e55f
AD		 6422 /* since we are recycling buffers we should seldom need to alloc */
6423 if (likely(page))
c023cd88
AD		 6424 return true;
6425
cbc8e55f
AD		 6426 /* alloc new page for storage */
6427 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6428 if (unlikely(!page)) {
6429 rx_ring->rx_stats.alloc_failed++;
6430 return false;
c023cd88
AD		 6431 }
6432
cbc8e55f
AD		 6433 /* map page for use */
6434 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6435
cbc8e55f
AD		 6436 /*
6437 * if mapping failed free memory back to system since
6438 * there isn't much point in holding memory we can't use
6439 */
1a1c225b 6440 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6441 __free_page(page);
6442
c023cd88
AD		 6443 rx_ring->rx_stats.alloc_failed++;
6444 return false;
6445 }
6446
1a1c225b 6447 bi->dma = dma;
cbc8e55f
AD		 6448 bi->page = page;
6449 bi->page_offset = 0;
1a1c225b 6450
c023cd88
AD		 6451 return true;
6452}
6453
9d5c8243 6454/**
cd392f5c 6455 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6456 * @adapter: address of board private structure
6457 **/
cd392f5c 6458void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6459{
9d5c8243 6460 union e1000_adv_rx_desc *rx_desc;
06034649 6461 struct igb_rx_buffer *bi;
c023cd88 6462 u16 i = rx_ring->next_to_use;
9d5c8243 6463
cbc8e55f
AD		 6464 /* nothing to do */
6465 if (!cleaned_count)
6466 return;
6467
60136906 6468 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6469 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6470 i -= rx_ring->count;
9d5c8243 6471
cbc8e55f 6472 do {
1a1c225b 6473 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6474 break;
9d5c8243 6475
cbc8e55f
AD		 6476 /*
6477 * Refresh the desc even if buffer_addrs didn't change
6478 * because each write-back erases this info.
6479 */
6480 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6481
c023cd88
AD		 6482 rx_desc++;
6483 bi++;
9d5c8243 6484 i++;
c023cd88 6485 if (unlikely(!i)) {
60136906 6486 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6487 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6488 i -= rx_ring->count;
6489 }
6490
6491 /* clear the hdr_addr for the next_to_use descriptor */
6492 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6493
6494 cleaned_count--;
6495 } while (cleaned_count);
9d5c8243 6496
c023cd88
AD		 6497 i += rx_ring->count;
6498
9d5c8243 6499 if (rx_ring->next_to_use != i) {
cbc8e55f 6500 /* record the next descriptor to use */
9d5c8243 6501 rx_ring->next_to_use = i;
9d5c8243 6502
cbc8e55f
AD		 6503 /* update next to alloc since we have filled the ring */
6504 rx_ring->next_to_alloc = i;
6505
6506 /*
6507 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6508 * know there are new descriptors to fetch. (Only
6509 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6510 * such as IA-64).
6511 */
9d5c8243 6512 wmb();
fce99e34 6513 writel(i, rx_ring->tail);
9d5c8243
AK		 6514 }
6515}
6516
6517/**
6518 * igb_mii_ioctl -
6519 * @netdev:
6520 * @ifreq:
6521 * @cmd:
6522 **/
6523static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6524{
6525 struct igb_adapter *adapter = netdev_priv(netdev);
6526 struct mii_ioctl_data *data = if_mii(ifr);
6527
6528 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6529 return -EOPNOTSUPP;
6530
6531 switch (cmd) {
6532 case SIOCGMIIPHY:
6533 data->phy_id = adapter->hw.phy.addr;
6534 break;
6535 case SIOCGMIIREG:
f5f4cf08
AD		 6536 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6537 &data->val_out))
9d5c8243
AK		 6538 return -EIO;
6539 break;
6540 case SIOCSMIIREG:
6541 default:
6542 return -EOPNOTSUPP;
6543 }
6544 return 0;
6545}
6546
6547/**
6548 * igb_ioctl -
6549 * @netdev:
6550 * @ifreq:
6551 * @cmd:
6552 **/
6553static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6554{
6555 switch (cmd) {
6556 case SIOCGMIIPHY:
6557 case SIOCGMIIREG:
6558 case SIOCSMIIREG:
6559 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6560 case SIOCSHWTSTAMP:
a79f4f88 6561 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6562 default:
6563 return -EOPNOTSUPP;
6564 }
6565}
6566
009bc06e
AD		 6567s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6568{
6569 struct igb_adapter *adapter = hw->back;
009bc06e 6570
23d028cc 6571 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6572 return -E1000_ERR_CONFIG;
6573
009bc06e
AD		 6574 return 0;
6575}
6576
6577s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6578{
6579 struct igb_adapter *adapter = hw->back;
009bc06e 6580
23d028cc 6581 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6582 return -E1000_ERR_CONFIG;
6583
009bc06e
AD		 6584 return 0;
6585}
6586
c8f44aff 6587static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6588{
6589 struct igb_adapter *adapter = netdev_priv(netdev);
6590 struct e1000_hw *hw = &adapter->hw;
6591 u32 ctrl, rctl;
5faf030c 6592 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6593
5faf030c 6594 if (enable) {
9d5c8243
AK		 6595 /* enable VLAN tag insert/strip */
6596 ctrl = rd32(E1000_CTRL);
6597 ctrl |= E1000_CTRL_VME;
6598 wr32(E1000_CTRL, ctrl);
6599
51466239 6600 /* Disable CFI check */
9d5c8243 6601 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6602 rctl &= ~E1000_RCTL_CFIEN;
6603 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6604 } else {
6605 /* disable VLAN tag insert/strip */
6606 ctrl = rd32(E1000_CTRL);
6607 ctrl &= ~E1000_CTRL_VME;
6608 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6609 }
6610
e1739522 6611 igb_rlpml_set(adapter);
9d5c8243
AK		 6612}
6613
8e586137 6614static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6615{
6616 struct igb_adapter *adapter = netdev_priv(netdev);
6617 struct e1000_hw *hw = &adapter->hw;
4ae196df 6618 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6619
51466239
AD		 6620 /* attempt to add filter to vlvf array */
6621 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6622
51466239
AD		 6623 /* add the filter since PF can receive vlans w/o entry in vlvf */
6624 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6625
6626 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6627
6628 return 0;
9d5c8243
AK		 6629}
6630
8e586137 6631static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6632{
6633 struct igb_adapter *adapter = netdev_priv(netdev);
6634 struct e1000_hw *hw = &adapter->hw;
4ae196df 6635 int pf_id = adapter->vfs_allocated_count;
51466239 6636 s32 err;
9d5c8243 6637
51466239
AD		 6638 /* remove vlan from VLVF table array */
6639 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6640
51466239
AD		 6641 /* if vid was not present in VLVF just remove it from table */
6642 if (err)
4ae196df 6643 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6644
6645 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6646
6647 return 0;
9d5c8243
AK		 6648}
6649
6650static void igb_restore_vlan(struct igb_adapter *adapter)
6651{
b2cb09b1 6652 u16 vid;
9d5c8243 6653
5faf030c
AD		 6654 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6655
b2cb09b1
JP		 6656 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6657 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6658}
6659
14ad2513 6660int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6661{
090b1795 6662 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6663 struct e1000_mac_info *mac = &adapter->hw.mac;
6664
6665 mac->autoneg = 0;
6666
14ad2513
DD		 6667 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6668 * for the switch() below to work */
6669 if ((spd & 1) || (dplx & ~1))
6670 goto err_inval;
6671
cd2638a8
CW		 6672 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6673 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6674 spd != SPEED_1000 &&
6675 dplx != DUPLEX_FULL)
6676 goto err_inval;
cd2638a8 6677
14ad2513 6678 switch (spd + dplx) {
9d5c8243
AK		 6679 case SPEED_10 + DUPLEX_HALF:
6680 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6681 break;
6682 case SPEED_10 + DUPLEX_FULL:
6683 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6684 break;
6685 case SPEED_100 + DUPLEX_HALF:
6686 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6687 break;
6688 case SPEED_100 + DUPLEX_FULL:
6689 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6690 break;
6691 case SPEED_1000 + DUPLEX_FULL:
6692 mac->autoneg = 1;
6693 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6694 break;
6695 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6696 default:
14ad2513 6697 goto err_inval;
9d5c8243 6698 }
8376dad0
JB		 6699
6700 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6701 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6702
9d5c8243 6703 return 0;
14ad2513
DD		 6704
6705err_inval:
6706 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6707 return -EINVAL;
9d5c8243
AK		 6708}
6709
749ab2cd
YZ		 6710static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6711 bool runtime)
9d5c8243
AK		 6712{
6713 struct net_device *netdev = pci_get_drvdata(pdev);
6714 struct igb_adapter *adapter = netdev_priv(netdev);
6715 struct e1000_hw *hw = &adapter->hw;
2d064c06 6716 u32 ctrl, rctl, status;
749ab2cd 6717 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6718#ifdef CONFIG_PM
6719 int retval = 0;
6720#endif
6721
6722 netif_device_detach(netdev);
6723
a88f10ec 6724 if (netif_running(netdev))
749ab2cd 6725 __igb_close(netdev, true);
a88f10ec 6726
047e0030 6727 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6728
6729#ifdef CONFIG_PM
6730 retval = pci_save_state(pdev);
6731 if (retval)
6732 return retval;
6733#endif
6734
6735 status = rd32(E1000_STATUS);
6736 if (status & E1000_STATUS_LU)
6737 wufc &= ~E1000_WUFC_LNKC;
6738
6739 if (wufc) {
6740 igb_setup_rctl(adapter);
ff41f8dc 6741 igb_set_rx_mode(netdev);
9d5c8243
AK		 6742
6743 /* turn on all-multi mode if wake on multicast is enabled */
6744 if (wufc & E1000_WUFC_MC) {
6745 rctl = rd32(E1000_RCTL);
6746 rctl |= E1000_RCTL_MPE;
6747 wr32(E1000_RCTL, rctl);
6748 }
6749
6750 ctrl = rd32(E1000_CTRL);
6751 /* advertise wake from D3Cold */
6752 #define E1000_CTRL_ADVD3WUC 0x00100000
6753 /* phy power management enable */
6754 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6755 ctrl |= E1000_CTRL_ADVD3WUC;
6756 wr32(E1000_CTRL, ctrl);
6757
9d5c8243 6758 /* Allow time for pending master requests to run */
330a6d6a 6759 igb_disable_pcie_master(hw);
9d5c8243
AK		 6760
6761 wr32(E1000_WUC, E1000_WUC_PME_EN);
6762 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6763 } else {
6764 wr32(E1000_WUC, 0);
6765 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6766 }
6767
3fe7c4c9
RW		 6768 *enable_wake = wufc || adapter->en_mng_pt;
6769 if (!*enable_wake)
88a268c1
NN		 6770 igb_power_down_link(adapter);
6771 else
6772 igb_power_up_link(adapter);
9d5c8243
AK		 6773
6774 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6775 * would have already happened in close and is redundant. */
6776 igb_release_hw_control(adapter);
6777
6778 pci_disable_device(pdev);
6779
9d5c8243
AK		 6780 return 0;
6781}
6782
6783#ifdef CONFIG_PM
d9dd966d 6784#ifdef CONFIG_PM_SLEEP
749ab2cd 6785static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6786{
6787 int retval;
6788 bool wake;
749ab2cd 6789 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6790
749ab2cd 6791 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6792 if (retval)
6793 return retval;
6794
6795 if (wake) {
6796 pci_prepare_to_sleep(pdev);
6797 } else {
6798 pci_wake_from_d3(pdev, false);
6799 pci_set_power_state(pdev, PCI_D3hot);
6800 }
6801
6802 return 0;
6803}
d9dd966d 6804#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6805
749ab2cd 6806static int igb_resume(struct device *dev)
9d5c8243 6807{
749ab2cd 6808 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6809 struct net_device *netdev = pci_get_drvdata(pdev);
6810 struct igb_adapter *adapter = netdev_priv(netdev);
6811 struct e1000_hw *hw = &adapter->hw;
6812 u32 err;
6813
6814 pci_set_power_state(pdev, PCI_D0);
6815 pci_restore_state(pdev);
b94f2d77 6816 pci_save_state(pdev);
42bfd33a 6817
aed5dec3 6818 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6819 if (err) {
6820 dev_err(&pdev->dev,
6821 "igb: Cannot enable PCI device from suspend\n");
6822 return err;
6823 }
6824 pci_set_master(pdev);
6825
6826 pci_enable_wake(pdev, PCI_D3hot, 0);
6827 pci_enable_wake(pdev, PCI_D3cold, 0);
6828
53c7d064 6829 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 6830 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6831 return -ENOMEM;
9d5c8243
AK		 6832 }
6833
9d5c8243 6834 igb_reset(adapter);
a8564f03
AD		 6835
6836 /* let the f/w know that the h/w is now under the control of the
6837 * driver. */
6838 igb_get_hw_control(adapter);
6839
9d5c8243
AK		 6840 wr32(E1000_WUS, ~0);
6841
749ab2cd 6842 if (netdev->flags & IFF_UP) {
0c2cc02e 6843 rtnl_lock();
749ab2cd 6844 err = __igb_open(netdev, true);
0c2cc02e 6845 rtnl_unlock();
a88f10ec
AD		 6846 if (err)
6847 return err;
6848 }
9d5c8243
AK		 6849
6850 netif_device_attach(netdev);
749ab2cd
YZ		 6851 return 0;
6852}
6853
6854#ifdef CONFIG_PM_RUNTIME
6855static int igb_runtime_idle(struct device *dev)
6856{
6857 struct pci_dev *pdev = to_pci_dev(dev);
6858 struct net_device *netdev = pci_get_drvdata(pdev);
6859 struct igb_adapter *adapter = netdev_priv(netdev);
6860
6861 if (!igb_has_link(adapter))
6862 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6863
6864 return -EBUSY;
6865}
6866
6867static int igb_runtime_suspend(struct device *dev)
6868{
6869 struct pci_dev *pdev = to_pci_dev(dev);
6870 int retval;
6871 bool wake;
6872
6873 retval = __igb_shutdown(pdev, &wake, 1);
6874 if (retval)
6875 return retval;
6876
6877 if (wake) {
6878 pci_prepare_to_sleep(pdev);
6879 } else {
6880 pci_wake_from_d3(pdev, false);
6881 pci_set_power_state(pdev, PCI_D3hot);
6882 }
9d5c8243 6883
9d5c8243
AK		 6884 return 0;
6885}
749ab2cd
YZ		 6886
6887static int igb_runtime_resume(struct device *dev)
6888{
6889 return igb_resume(dev);
6890}
6891#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 6892#endif
6893
6894static void igb_shutdown(struct pci_dev *pdev)
6895{
3fe7c4c9
RW		 6896 bool wake;
6897
749ab2cd 6898 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6899
6900 if (system_state == SYSTEM_POWER_OFF) {
6901 pci_wake_from_d3(pdev, wake);
6902 pci_set_power_state(pdev, PCI_D3hot);
6903 }
9d5c8243
AK		 6904}
6905
6906#ifdef CONFIG_NET_POLL_CONTROLLER
6907/*
6908 * Polling 'interrupt' - used by things like netconsole to send skbs
6909 * without having to re-enable interrupts. It's not called while
6910 * the interrupt routine is executing.
6911 */
6912static void igb_netpoll(struct net_device *netdev)
6913{
6914 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6915 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 6916 struct igb_q_vector *q_vector;
9d5c8243 6917 int i;
9d5c8243 6918
047e0030 6919 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 6920 q_vector = adapter->q_vector[i];
6921 if (adapter->msix_entries)
6922 wr32(E1000_EIMC, q_vector->eims_value);
6923 else
6924 igb_irq_disable(adapter);
047e0030 6925 napi_schedule(&q_vector->napi);
eebbbdba 6926 }
9d5c8243
AK		 6927}
6928#endif /* CONFIG_NET_POLL_CONTROLLER */
6929
6930/**
6931 * igb_io_error_detected - called when PCI error is detected
6932 * @pdev: Pointer to PCI device
6933 * @state: The current pci connection state
6934 *
6935 * This function is called after a PCI bus error affecting
6936 * this device has been detected.
6937 */
6938static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6939 pci_channel_state_t state)
6940{
6941 struct net_device *netdev = pci_get_drvdata(pdev);
6942 struct igb_adapter *adapter = netdev_priv(netdev);
6943
6944 netif_device_detach(netdev);
6945
59ed6eec
AD		 6946 if (state == pci_channel_io_perm_failure)
6947 return PCI_ERS_RESULT_DISCONNECT;
6948
9d5c8243
AK		 6949 if (netif_running(netdev))
6950 igb_down(adapter);
6951 pci_disable_device(pdev);
6952
6953 /* Request a slot slot reset. */
6954 return PCI_ERS_RESULT_NEED_RESET;
6955}
6956
6957/**
6958 * igb_io_slot_reset - called after the pci bus has been reset.
6959 * @pdev: Pointer to PCI device
6960 *
6961 * Restart the card from scratch, as if from a cold-boot. Implementation
6962 * resembles the first-half of the igb_resume routine.
6963 */
6964static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6965{
6966 struct net_device *netdev = pci_get_drvdata(pdev);
6967 struct igb_adapter *adapter = netdev_priv(netdev);
6968 struct e1000_hw *hw = &adapter->hw;
40a914fa 6969 pci_ers_result_t result;
42bfd33a 6970 int err;
9d5c8243 6971
aed5dec3 6972 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6973 dev_err(&pdev->dev,
6974 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6975 result = PCI_ERS_RESULT_DISCONNECT;
6976 } else {
6977 pci_set_master(pdev);
6978 pci_restore_state(pdev);
b94f2d77 6979 pci_save_state(pdev);
9d5c8243 6980
40a914fa
AD		 6981 pci_enable_wake(pdev, PCI_D3hot, 0);
6982 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6983
40a914fa
AD		 6984 igb_reset(adapter);
6985 wr32(E1000_WUS, ~0);
6986 result = PCI_ERS_RESULT_RECOVERED;
6987 }
9d5c8243 6988
ea943d41
JK		 6989 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6990 if (err) {
6991 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6992 "failed 0x%0x\n", err);
6993 /* non-fatal, continue */
6994 }
40a914fa
AD		 6995
6996 return result;
9d5c8243
AK		 6997}
6998
6999/**
7000 * igb_io_resume - called when traffic can start flowing again.
7001 * @pdev: Pointer to PCI device
7002 *
7003 * This callback is called when the error recovery driver tells us that
7004 * its OK to resume normal operation. Implementation resembles the
7005 * second-half of the igb_resume routine.
7006 */
7007static void igb_io_resume(struct pci_dev *pdev)
7008{
7009 struct net_device *netdev = pci_get_drvdata(pdev);
7010 struct igb_adapter *adapter = netdev_priv(netdev);
7011
9d5c8243
AK		 7012 if (netif_running(netdev)) {
7013 if (igb_up(adapter)) {
7014 dev_err(&pdev->dev, "igb_up failed after reset\n");
7015 return;
7016 }
7017 }
7018
7019 netif_device_attach(netdev);
7020
7021 /* let the f/w know that the h/w is now under the control of the
7022 * driver. */
7023 igb_get_hw_control(adapter);
9d5c8243
AK		 7024}
7025
26ad9178
AD		 7026static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7027 u8 qsel)
7028{
7029 u32 rar_low, rar_high;
7030 struct e1000_hw *hw = &adapter->hw;
7031
7032 /* HW expects these in little endian so we reverse the byte order
7033 * from network order (big endian) to little endian
7034 */
7035 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7036 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7037 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7038
7039 /* Indicate to hardware the Address is Valid. */
7040 rar_high |= E1000_RAH_AV;
7041
7042 if (hw->mac.type == e1000_82575)
7043 rar_high |= E1000_RAH_POOL_1 * qsel;
7044 else
7045 rar_high |= E1000_RAH_POOL_1 << qsel;
7046
7047 wr32(E1000_RAL(index), rar_low);
7048 wrfl();
7049 wr32(E1000_RAH(index), rar_high);
7050 wrfl();
7051}
7052
4ae196df
AD		 7053static int igb_set_vf_mac(struct igb_adapter *adapter,
7054 int vf, unsigned char *mac_addr)
7055{
7056 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7057 /* VF MAC addresses start at end of receive addresses and moves
7058 * torwards the first, as a result a collision should not be possible */
7059 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7060
37680117 7061 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7062
26ad9178 7063 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7064
7065 return 0;
7066}
7067
8151d294
WM		 7068static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7069{
7070 struct igb_adapter *adapter = netdev_priv(netdev);
7071 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7072 return -EINVAL;
7073 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7074 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7075 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7076 " change effective.");
7077 if (test_bit(__IGB_DOWN, &adapter->state)) {
7078 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7079 " but the PF device is not up.\n");
7080 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7081 " attempting to use the VF device.\n");
7082 }
7083 return igb_set_vf_mac(adapter, vf, mac);
7084}
7085
17dc566c
LL		 7086static int igb_link_mbps(int internal_link_speed)
7087{
7088 switch (internal_link_speed) {
7089 case SPEED_100:
7090 return 100;
7091 case SPEED_1000:
7092 return 1000;
7093 default:
7094 return 0;
7095 }
7096}
7097
7098static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7099 int link_speed)
7100{
7101 int rf_dec, rf_int;
7102 u32 bcnrc_val;
7103
7104 if (tx_rate != 0) {
7105 /* Calculate the rate factor values to set */
7106 rf_int = link_speed / tx_rate;
7107 rf_dec = (link_speed - (rf_int * tx_rate));
7108 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7109
7110 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7111 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7112 E1000_RTTBCNRC_RF_INT_MASK);
7113 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7114 } else {
7115 bcnrc_val = 0;
7116 }
7117
7118 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7119 /*
7120 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7121 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7122 */
7123 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7124 wr32(E1000_RTTBCNRC, bcnrc_val);
7125}
7126
7127static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7128{
7129 int actual_link_speed, i;
7130 bool reset_rate = false;
7131
7132 /* VF TX rate limit was not set or not supported */
7133 if ((adapter->vf_rate_link_speed == 0) ||
7134 (adapter->hw.mac.type != e1000_82576))
7135 return;
7136
7137 actual_link_speed = igb_link_mbps(adapter->link_speed);
7138 if (actual_link_speed != adapter->vf_rate_link_speed) {
7139 reset_rate = true;
7140 adapter->vf_rate_link_speed = 0;
7141 dev_info(&adapter->pdev->dev,
7142 "Link speed has been changed. VF Transmit "
7143 "rate is disabled\n");
7144 }
7145
7146 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7147 if (reset_rate)
7148 adapter->vf_data[i].tx_rate = 0;
7149
7150 igb_set_vf_rate_limit(&adapter->hw, i,
7151 adapter->vf_data[i].tx_rate,
7152 actual_link_speed);
7153 }
7154}
7155
8151d294
WM		 7156static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7157{
17dc566c
LL		 7158 struct igb_adapter *adapter = netdev_priv(netdev);
7159 struct e1000_hw *hw = &adapter->hw;
7160 int actual_link_speed;
7161
7162 if (hw->mac.type != e1000_82576)
7163 return -EOPNOTSUPP;
7164
7165 actual_link_speed = igb_link_mbps(adapter->link_speed);
7166 if ((vf >= adapter->vfs_allocated_count) ||
7167 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7168 (tx_rate < 0) || (tx_rate > actual_link_speed))
7169 return -EINVAL;
7170
7171 adapter->vf_rate_link_speed = actual_link_speed;
7172 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7173 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7174
7175 return 0;
8151d294
WM		 7176}
7177
7178static int igb_ndo_get_vf_config(struct net_device *netdev,
7179 int vf, struct ifla_vf_info *ivi)
7180{
7181 struct igb_adapter *adapter = netdev_priv(netdev);
7182 if (vf >= adapter->vfs_allocated_count)
7183 return -EINVAL;
7184 ivi->vf = vf;
7185 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7186 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7187 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7188 ivi->qos = adapter->vf_data[vf].pf_qos;
7189 return 0;
7190}
7191
4ae196df
AD		 7192static void igb_vmm_control(struct igb_adapter *adapter)
7193{
7194 struct e1000_hw *hw = &adapter->hw;
10d8e907 7195 u32 reg;
4ae196df 7196
52a1dd4d
AD		 7197 switch (hw->mac.type) {
7198 case e1000_82575:
f96a8a0b
CW		 7199 case e1000_i210:
7200 case e1000_i211:
52a1dd4d
AD		 7201 default:
7202 /* replication is not supported for 82575 */
4ae196df 7203 return;
52a1dd4d
AD		 7204 case e1000_82576:
7205 /* notify HW that the MAC is adding vlan tags */
7206 reg = rd32(E1000_DTXCTL);
7207 reg |= E1000_DTXCTL_VLAN_ADDED;
7208 wr32(E1000_DTXCTL, reg);
7209 case e1000_82580:
7210 /* enable replication vlan tag stripping */
7211 reg = rd32(E1000_RPLOLR);
7212 reg |= E1000_RPLOLR_STRVLAN;
7213 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7214 case e1000_i350:
7215 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7216 break;
7217 }
10d8e907 7218
d4960307
AD		 7219 if (adapter->vfs_allocated_count) {
7220 igb_vmdq_set_loopback_pf(hw, true);
7221 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7222 igb_vmdq_set_anti_spoofing_pf(hw, true,
7223 adapter->vfs_allocated_count);
d4960307
AD		 7224 } else {
7225 igb_vmdq_set_loopback_pf(hw, false);
7226 igb_vmdq_set_replication_pf(hw, false);
7227 }
4ae196df
AD		 7228}
7229
b6e0c419
CW		 7230static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7231{
7232 struct e1000_hw *hw = &adapter->hw;
7233 u32 dmac_thr;
7234 u16 hwm;
7235
7236 if (hw->mac.type > e1000_82580) {
7237 if (adapter->flags & IGB_FLAG_DMAC) {
7238 u32 reg;
7239
7240 /* force threshold to 0. */
7241 wr32(E1000_DMCTXTH, 0);
7242
7243 /*
e8c626e9
MV		 7244 * DMA Coalescing high water mark needs to be greater
7245 * than the Rx threshold. Set hwm to PBA - max frame
7246 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7247 */
e8c626e9
MV		 7248 hwm = 64 * pba - adapter->max_frame_size / 16;
7249 if (hwm < 64 * (pba - 6))
7250 hwm = 64 * (pba - 6);
7251 reg = rd32(E1000_FCRTC);
7252 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7253 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7254 & E1000_FCRTC_RTH_COAL_MASK);
7255 wr32(E1000_FCRTC, reg);
7256
7257 /*
7258 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7259 * frame size, capping it at PBA - 10KB.
7260 */
7261 dmac_thr = pba - adapter->max_frame_size / 512;
7262 if (dmac_thr < pba - 10)
7263 dmac_thr = pba - 10;
b6e0c419
CW		 7264 reg = rd32(E1000_DMACR);
7265 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7266 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7267 & E1000_DMACR_DMACTHR_MASK);
7268
7269 /* transition to L0x or L1 if available..*/
7270 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7271
7272 /* watchdog timer= +-1000 usec in 32usec intervals */
7273 reg |= (1000 >> 5);
0c02dd98
MV		 7274
7275 /* Disable BMC-to-OS Watchdog Enable */
7276 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7277 wr32(E1000_DMACR, reg);
7278
7279 /*
7280 * no lower threshold to disable
7281 * coalescing(smart fifb)-UTRESH=0
7282 */
7283 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7284
7285 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7286
7287 wr32(E1000_DMCTLX, reg);
7288
7289 /*
7290 * free space in tx packet buffer to wake from
7291 * DMA coal
7292 */
7293 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7294 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7295
7296 /*
7297 * make low power state decision controlled
7298 * by DMA coal
7299 */
7300 reg = rd32(E1000_PCIEMISC);
7301 reg &= ~E1000_PCIEMISC_LX_DECISION;
7302 wr32(E1000_PCIEMISC, reg);
7303 } /* endif adapter->dmac is not disabled */
7304 } else if (hw->mac.type == e1000_82580) {
7305 u32 reg = rd32(E1000_PCIEMISC);
7306 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7307 wr32(E1000_DMACR, 0);
7308 }
7309}
7310
9d5c8243 7311/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)