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igb: Refix sparse warning in igb_get_i2c_client
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
200e5fd5 63#define MAJ 4
6699938b
CW		 64#define MIN 1
65#define BUILD 2
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
110 /* required last entry */
111 {0, }
112};
113
114MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
115
116void igb_reset(struct igb_adapter *);
117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c8f44aff 158static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 159static int igb_vlan_rx_add_vid(struct net_device *, u16);
160static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 161static void igb_restore_vlan(struct igb_adapter *);
26ad9178 162static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 163static void igb_ping_all_vfs(struct igb_adapter *);
164static void igb_msg_task(struct igb_adapter *);
4ae196df 165static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 166static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 167static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 168static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
169static int igb_ndo_set_vf_vlan(struct net_device *netdev,
170 int vf, u16 vlan, u8 qos);
171static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
172static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
173 struct ifla_vf_info *ivi);
17dc566c 174static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 175
176#ifdef CONFIG_PCI_IOV
0224d663 177static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 178static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 179#endif
9d5c8243 180
9d5c8243 181#ifdef CONFIG_PM
d9dd966d 182#ifdef CONFIG_PM_SLEEP
749ab2cd 183static int igb_suspend(struct device *);
d9dd966d 184#endif
749ab2cd
YZ		 185static int igb_resume(struct device *);
186#ifdef CONFIG_PM_RUNTIME
187static int igb_runtime_suspend(struct device *dev);
188static int igb_runtime_resume(struct device *dev);
189static int igb_runtime_idle(struct device *dev);
190#endif
191static const struct dev_pm_ops igb_pm_ops = {
192 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
193 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
194 igb_runtime_idle)
195};
9d5c8243
AK		 196#endif
197static void igb_shutdown(struct pci_dev *);
fa44f2f1 198static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 199#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 200static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
201static struct notifier_block dca_notifier = {
202 .notifier_call = igb_notify_dca,
203 .next = NULL,
204 .priority = 0
205};
206#endif
9d5c8243
AK		 207#ifdef CONFIG_NET_POLL_CONTROLLER
208/* for netdump / net console */
209static void igb_netpoll(struct net_device *);
210#endif
37680117 211#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 212static unsigned int max_vfs = 0;
213module_param(max_vfs, uint, 0);
214MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
215 "per physical function");
216#endif /* CONFIG_PCI_IOV */
217
9d5c8243
AK		 218static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221static void igb_io_resume(struct pci_dev *);
222
3646f0e5 223static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227};
228
b6e0c419 229static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 230
231static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
9f9a12f8 235 .remove = igb_remove,
9d5c8243 236#ifdef CONFIG_PM
749ab2cd 237 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 238#endif
239 .shutdown = igb_shutdown,
fa44f2f1 240 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 241 .err_handler = &igb_err_handler
242};
243
244MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246MODULE_LICENSE("GPL");
247MODULE_VERSION(DRV_VERSION);
248
b3f4d599 249#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250static int debug = -1;
251module_param(debug, int, 0);
252MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
c97ec42a
TI		 254struct igb_reg_info {
255 u32 ofs;
256 char *name;
257};
258
259static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293};
294
295/*
296 * igb_regdump - register printout routine
297 */
298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
363/*
364 * igb_dump - Print registers, tx-rings and rx-rings
365 */
366static void igb_dump(struct igb_adapter *adapter)
367{
368 struct net_device *netdev = adapter->netdev;
369 struct e1000_hw *hw = &adapter->hw;
370 struct igb_reg_info *reginfo;
c97ec42a
TI		 371 struct igb_ring *tx_ring;
372 union e1000_adv_tx_desc *tx_desc;
373 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 374 struct igb_ring *rx_ring;
375 union e1000_adv_rx_desc *rx_desc;
376 u32 staterr;
6ad4edfc 377 u16 i, n;
c97ec42a
TI		 378
379 if (!netif_msg_hw(adapter))
380 return;
381
382 /* Print netdevice Info */
383 if (netdev) {
384 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 385 pr_info("Device Name state trans_start "
386 "last_rx\n");
387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 389 }
390
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 393 pr_info(" Register Name Value\n");
c97ec42a
TI		 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
397 }
398
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
401 goto exit;
402
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 405 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 406 struct igb_tx_buffer *buffer_info;
c97ec42a 407 tx_ring = adapter->tx_ring[n];
06034649 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
c97ec42a
TI		 415 }
416
417 /* Print TX Rings */
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
420
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
422
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
433
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
440 "[bi->dma ] leng ntw timestamp "
441 "bi->skb\n");
c97ec42a
TI		 442
443 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 444 const char *next_desc;
06034649 445 struct igb_tx_buffer *buffer_info;
60136906 446 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 447 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 448 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 449 if (i == tx_ring->next_to_use &&
450 i == tx_ring->next_to_clean)
451 next_desc = " NTC/U";
452 else if (i == tx_ring->next_to_use)
453 next_desc = " NTU";
454 else if (i == tx_ring->next_to_clean)
455 next_desc = " NTC";
456 else
457 next_desc = "";
458
459 pr_info("T [0x%03X] %016llX %016llX %016llX"
460 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 461 le64_to_cpu(u0->a),
462 le64_to_cpu(u0->b),
c9f14bf3
AD		 463 (u64)dma_unmap_addr(buffer_info, dma),
464 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 465 buffer_info->next_to_watch,
466 (u64)buffer_info->time_stamp,
876d2d6f 467 buffer_info->skb, next_desc);
c97ec42a 468
b669588a 469 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 470 print_hex_dump(KERN_INFO, "",
471 DUMP_PREFIX_ADDRESS,
b669588a 472 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 473 dma_unmap_len(buffer_info, len),
474 true);
c97ec42a
TI		 475 }
476 }
477
478 /* Print RX Rings Summary */
479rx_ring_summary:
480 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 481 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 482 for (n = 0; n < adapter->num_rx_queues; n++) {
483 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 484 pr_info(" %5d %5X %5X\n",
485 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 486 }
487
488 /* Print RX Rings */
489 if (!netif_msg_rx_status(adapter))
490 goto exit;
491
492 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
493
494 /* Advanced Receive Descriptor (Read) Format
495 * 63 1 0
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
501 *
502 *
503 * Advanced Receive Descriptor (Write-Back) Format
504 *
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
513 */
514
515 for (n = 0; n < adapter->num_rx_queues; n++) {
516 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 517 pr_info("------------------------------------\n");
518 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
521 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
522 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
523 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 524
525 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 526 const char *next_desc;
06034649
AD		 527 struct igb_rx_buffer *buffer_info;
528 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 529 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 530 u0 = (struct my_u0 *)rx_desc;
531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 532
533 if (i == rx_ring->next_to_use)
534 next_desc = " NTU";
535 else if (i == rx_ring->next_to_clean)
536 next_desc = " NTC";
537 else
538 next_desc = "";
539
c97ec42a
TI		 540 if (staterr & E1000_RXD_STAT_DD) {
541 /* Descriptor Done */
1a1c225b
AD		 542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
543 "RWB", i,
c97ec42a
TI		 544 le64_to_cpu(u0->a),
545 le64_to_cpu(u0->b),
1a1c225b 546 next_desc);
c97ec42a 547 } else {
1a1c225b
AD		 548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
549 "R ", i,
c97ec42a
TI		 550 le64_to_cpu(u0->a),
551 le64_to_cpu(u0->b),
552 (u64)buffer_info->dma,
1a1c225b 553 next_desc);
c97ec42a 554
b669588a 555 if (netif_msg_pktdata(adapter) &&
1a1c225b 556 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 557 print_hex_dump(KERN_INFO, "",
558 DUMP_PREFIX_ADDRESS,
559 16, 1,
b669588a
ET		 560 page_address(buffer_info->page) +
561 buffer_info->page_offset,
de78d1f9 562 IGB_RX_BUFSZ, true);
c97ec42a
TI		 563 }
564 }
c97ec42a
TI		 565 }
566 }
567
568exit:
569 return;
570}
571
441fc6fd
CW		 572/* igb_get_i2c_data - Reads the I2C SDA data bit
573 * @hw: pointer to hardware structure
574 * @i2cctl: Current value of I2CCTL register
575 *
576 * Returns the I2C data bit value
577 */
578static int igb_get_i2c_data(void *data)
579{
580 struct igb_adapter *adapter = (struct igb_adapter *)data;
581 struct e1000_hw *hw = &adapter->hw;
582 s32 i2cctl = rd32(E1000_I2CPARAMS);
583
584 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
585}
586
587/* igb_set_i2c_data - Sets the I2C data bit
588 * @data: pointer to hardware structure
589 * @state: I2C data value (0 or 1) to set
590 *
591 * Sets the I2C data bit
592 */
593static void igb_set_i2c_data(void *data, int state)
594{
595 struct igb_adapter *adapter = (struct igb_adapter *)data;
596 struct e1000_hw *hw = &adapter->hw;
597 s32 i2cctl = rd32(E1000_I2CPARAMS);
598
599 if (state)
600 i2cctl |= E1000_I2C_DATA_OUT;
601 else
602 i2cctl &= ~E1000_I2C_DATA_OUT;
603
604 i2cctl &= ~E1000_I2C_DATA_OE_N;
605 i2cctl |= E1000_I2C_CLK_OE_N;
606 wr32(E1000_I2CPARAMS, i2cctl);
607 wrfl();
608
609}
610
611/* igb_set_i2c_clk - Sets the I2C SCL clock
612 * @data: pointer to hardware structure
613 * @state: state to set clock
614 *
615 * Sets the I2C clock line to state
616 */
617static void igb_set_i2c_clk(void *data, int state)
618{
619 struct igb_adapter *adapter = (struct igb_adapter *)data;
620 struct e1000_hw *hw = &adapter->hw;
621 s32 i2cctl = rd32(E1000_I2CPARAMS);
622
623 if (state) {
624 i2cctl |= E1000_I2C_CLK_OUT;
625 i2cctl &= ~E1000_I2C_CLK_OE_N;
626 } else {
627 i2cctl &= ~E1000_I2C_CLK_OUT;
628 i2cctl &= ~E1000_I2C_CLK_OE_N;
629 }
630 wr32(E1000_I2CPARAMS, i2cctl);
631 wrfl();
632}
633
634/* igb_get_i2c_clk - Gets the I2C SCL clock state
635 * @data: pointer to hardware structure
636 *
637 * Gets the I2C clock state
638 */
639static int igb_get_i2c_clk(void *data)
640{
641 struct igb_adapter *adapter = (struct igb_adapter *)data;
642 struct e1000_hw *hw = &adapter->hw;
643 s32 i2cctl = rd32(E1000_I2CPARAMS);
644
645 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
646}
647
648static const struct i2c_algo_bit_data igb_i2c_algo = {
649 .setsda = igb_set_i2c_data,
650 .setscl = igb_set_i2c_clk,
651 .getsda = igb_get_i2c_data,
652 .getscl = igb_get_i2c_clk,
653 .udelay = 5,
654 .timeout = 20,
655};
656
9d5c8243 657/**
c041076a 658 * igb_get_hw_dev - return device
9d5c8243
AK		 659 * used by hardware layer to print debugging information
660 **/
c041076a 661struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 662{
663 struct igb_adapter *adapter = hw->back;
c041076a 664 return adapter->netdev;
9d5c8243 665}
38c845c7 666
9d5c8243
AK		 667/**
668 * igb_init_module - Driver Registration Routine
669 *
670 * igb_init_module is the first routine called when the driver is
671 * loaded. All it does is register with the PCI subsystem.
672 **/
673static int __init igb_init_module(void)
674{
675 int ret;
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243
AK		 677 igb_driver_string, igb_driver_version);
678
876d2d6f 679 pr_info("%s\n", igb_copyright);
9d5c8243 680
421e02f0 681#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 682 dca_register_notify(&dca_notifier);
683#endif
bbd98fe4 684 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 685 return ret;
686}
687
688module_init(igb_init_module);
689
690/**
691 * igb_exit_module - Driver Exit Cleanup Routine
692 *
693 * igb_exit_module is called just before the driver is removed
694 * from memory.
695 **/
696static void __exit igb_exit_module(void)
697{
421e02f0 698#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 699 dca_unregister_notify(&dca_notifier);
700#endif
9d5c8243
AK		 701 pci_unregister_driver(&igb_driver);
702}
703
704module_exit(igb_exit_module);
705
26bc19ec
AD		 706#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
707/**
708 * igb_cache_ring_register - Descriptor ring to register mapping
709 * @adapter: board private structure to initialize
710 *
711 * Once we know the feature-set enabled for the device, we'll cache
712 * the register offset the descriptor ring is assigned to.
713 **/
714static void igb_cache_ring_register(struct igb_adapter *adapter)
715{
ee1b9f06 716 int i = 0, j = 0;
047e0030 717 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 718
719 switch (adapter->hw.mac.type) {
720 case e1000_82576:
721 /* The queues are allocated for virtualization such that VF 0
722 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
723 * In order to avoid collision we start at the first free queue
724 * and continue consuming queues in the same sequence
725 */
ee1b9f06 726 if (adapter->vfs_allocated_count) {
a99955fc 727 for (; i < adapter->rss_queues; i++)
3025a446
AD		 728 adapter->rx_ring[i]->reg_idx = rbase_offset +
729 Q_IDX_82576(i);
ee1b9f06 730 }
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
26bc19ec 736 default:
ee1b9f06 737 for (; i < adapter->num_rx_queues; i++)
3025a446 738 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 739 for (; j < adapter->num_tx_queues; j++)
3025a446 740 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 741 break;
742 }
743}
744
4be000c8
AD		 745/**
746 * igb_write_ivar - configure ivar for given MSI-X vector
747 * @hw: pointer to the HW structure
748 * @msix_vector: vector number we are allocating to a given ring
749 * @index: row index of IVAR register to write within IVAR table
750 * @offset: column offset of in IVAR, should be multiple of 8
751 *
752 * This function is intended to handle the writing of the IVAR register
753 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
754 * each containing an cause allocation for an Rx and Tx ring, and a
755 * variable number of rows depending on the number of queues supported.
756 **/
757static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
758 int index, int offset)
759{
760 u32 ivar = array_rd32(E1000_IVAR0, index);
761
762 /* clear any bits that are currently set */
763 ivar &= ~((u32)0xFF << offset);
764
765 /* write vector and valid bit */
766 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
767
768 array_wr32(E1000_IVAR0, index, ivar);
769}
770
9d5c8243 771#define IGB_N0_QUEUE -1
047e0030 772static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 773{
047e0030 774 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 775 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 776 int rx_queue = IGB_N0_QUEUE;
777 int tx_queue = IGB_N0_QUEUE;
4be000c8 778 u32 msixbm = 0;
047e0030 779
0ba82994
AD		 780 if (q_vector->rx.ring)
781 rx_queue = q_vector->rx.ring->reg_idx;
782 if (q_vector->tx.ring)
783 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 784
785 switch (hw->mac.type) {
786 case e1000_82575:
9d5c8243
AK		 787 /* The 82575 assigns vectors using a bitmask, which matches the
788 bitmask for the EICR/EIMS/EIMC registers. To assign one
789 or more queues to a vector, we write the appropriate bits
790 into the MSIXBM register for that vector. */
047e0030 791 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 792 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 793 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 794 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 795 if (!adapter->msix_entries && msix_vector == 0)
796 msixbm |= E1000_EIMS_OTHER;
9d5c8243 797 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 798 q_vector->eims_value = msixbm;
2d064c06
AD		 799 break;
800 case e1000_82576:
4be000c8
AD		 801 /*
802 * 82576 uses a table that essentially consists of 2 columns
803 * with 8 rows. The ordering is column-major so we use the
804 * lower 3 bits as the row index, and the 4th bit as the
805 * column offset.
806 */
807 if (rx_queue > IGB_N0_QUEUE)
808 igb_write_ivar(hw, msix_vector,
809 rx_queue & 0x7,
810 (rx_queue & 0x8) << 1);
811 if (tx_queue > IGB_N0_QUEUE)
812 igb_write_ivar(hw, msix_vector,
813 tx_queue & 0x7,
814 ((tx_queue & 0x8) << 1) + 8);
047e0030 815 q_vector->eims_value = 1 << msix_vector;
2d064c06 816 break;
55cac248 817 case e1000_82580:
d2ba2ed8 818 case e1000_i350:
f96a8a0b
CW		 819 case e1000_i210:
820 case e1000_i211:
4be000c8
AD		 821 /*
822 * On 82580 and newer adapters the scheme is similar to 82576
823 * however instead of ordering column-major we have things
824 * ordered row-major. So we traverse the table by using
825 * bit 0 as the column offset, and the remaining bits as the
826 * row index.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue >> 1,
831 (rx_queue & 0x1) << 4);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue >> 1,
835 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 836 q_vector->eims_value = 1 << msix_vector;
837 break;
2d064c06
AD		 838 default:
839 BUG();
840 break;
841 }
26b39276
AD		 842
843 /* add q_vector eims value to global eims_enable_mask */
844 adapter->eims_enable_mask |= q_vector->eims_value;
845
846 /* configure q_vector to set itr on first interrupt */
847 q_vector->set_itr = 1;
9d5c8243
AK		 848}
849
850/**
851 * igb_configure_msix - Configure MSI-X hardware
852 *
853 * igb_configure_msix sets up the hardware to properly
854 * generate MSI-X interrupts.
855 **/
856static void igb_configure_msix(struct igb_adapter *adapter)
857{
858 u32 tmp;
859 int i, vector = 0;
860 struct e1000_hw *hw = &adapter->hw;
861
862 adapter->eims_enable_mask = 0;
9d5c8243
AK		 863
864 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 865 switch (hw->mac.type) {
866 case e1000_82575:
9d5c8243
AK		 867 tmp = rd32(E1000_CTRL_EXT);
868 /* enable MSI-X PBA support*/
869 tmp |= E1000_CTRL_EXT_PBA_CLR;
870
871 /* Auto-Mask interrupts upon ICR read. */
872 tmp |= E1000_CTRL_EXT_EIAME;
873 tmp |= E1000_CTRL_EXT_IRCA;
874
875 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 876
877 /* enable msix_other interrupt */
878 array_wr32(E1000_MSIXBM(0), vector++,
879 E1000_EIMS_OTHER);
844290e5 880 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 881
2d064c06
AD		 882 break;
883
884 case e1000_82576:
55cac248 885 case e1000_82580:
d2ba2ed8 886 case e1000_i350:
f96a8a0b
CW		 887 case e1000_i210:
888 case e1000_i211:
047e0030
AD		 889 /* Turn on MSI-X capability first, or our settings
890 * won't stick. And it will take days to debug. */
891 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
892 E1000_GPIE_PBA | E1000_GPIE_EIAME |
893 E1000_GPIE_NSICR);
894
895 /* enable msix_other interrupt */
896 adapter->eims_other = 1 << vector;
2d064c06 897 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 898
047e0030 899 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 900 break;
901 default:
902 /* do nothing, since nothing else supports MSI-X */
903 break;
904 } /* switch (hw->mac.type) */
047e0030
AD		 905
906 adapter->eims_enable_mask |= adapter->eims_other;
907
26b39276
AD		 908 for (i = 0; i < adapter->num_q_vectors; i++)
909 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 910
9d5c8243
AK		 911 wrfl();
912}
913
914/**
915 * igb_request_msix - Initialize MSI-X interrupts
916 *
917 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
918 * kernel.
919 **/
920static int igb_request_msix(struct igb_adapter *adapter)
921{
922 struct net_device *netdev = adapter->netdev;
047e0030 923 struct e1000_hw *hw = &adapter->hw;
52285b76 924 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 925
047e0030 926 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 927 igb_msix_other, 0, netdev->name, adapter);
047e0030 928 if (err)
52285b76 929 goto err_out;
047e0030
AD		 930
931 for (i = 0; i < adapter->num_q_vectors; i++) {
932 struct igb_q_vector *q_vector = adapter->q_vector[i];
933
52285b76
SA		 934 vector++;
935
047e0030
AD		 936 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
937
0ba82994 938 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 939 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 940 q_vector->rx.ring->queue_index);
941 else if (q_vector->tx.ring)
047e0030 942 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 943 q_vector->tx.ring->queue_index);
944 else if (q_vector->rx.ring)
047e0030 945 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 946 q_vector->rx.ring->queue_index);
9d5c8243 947 else
047e0030
AD		 948 sprintf(q_vector->name, "%s-unused", netdev->name);
949
9d5c8243 950 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 951 igb_msix_ring, 0, q_vector->name,
047e0030 952 q_vector);
9d5c8243 953 if (err)
52285b76 954 goto err_free;
9d5c8243
AK		 955 }
956
9d5c8243
AK		 957 igb_configure_msix(adapter);
958 return 0;
52285b76
SA		 959
960err_free:
961 /* free already assigned IRQs */
962 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
963
964 vector--;
965 for (i = 0; i < vector; i++) {
966 free_irq(adapter->msix_entries[free_vector++].vector,
967 adapter->q_vector[i]);
968 }
969err_out:
9d5c8243
AK		 970 return err;
971}
972
973static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
974{
975 if (adapter->msix_entries) {
976 pci_disable_msix(adapter->pdev);
977 kfree(adapter->msix_entries);
978 adapter->msix_entries = NULL;
047e0030 979 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 980 pci_disable_msi(adapter->pdev);
047e0030 981 }
9d5c8243
AK		 982}
983
5536d210
AD		 984/**
985 * igb_free_q_vector - Free memory allocated for specific interrupt vector
986 * @adapter: board private structure to initialize
987 * @v_idx: Index of vector to be freed
988 *
989 * This function frees the memory allocated to the q_vector. In addition if
990 * NAPI is enabled it will delete any references to the NAPI struct prior
991 * to freeing the q_vector.
992 **/
993static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
994{
995 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
996
997 if (q_vector->tx.ring)
998 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
999
1000 if (q_vector->rx.ring)
1001 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1002
1003 adapter->q_vector[v_idx] = NULL;
1004 netif_napi_del(&q_vector->napi);
1005
1006 /*
1007 * ixgbe_get_stats64() might access the rings on this vector,
1008 * we must wait a grace period before freeing it.
1009 */
1010 kfree_rcu(q_vector, rcu);
1011}
1012
047e0030
AD		 1013/**
1014 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1015 * @adapter: board private structure to initialize
1016 *
1017 * This function frees the memory allocated to the q_vectors. In addition if
1018 * NAPI is enabled it will delete any references to the NAPI struct prior
1019 * to freeing the q_vector.
1020 **/
1021static void igb_free_q_vectors(struct igb_adapter *adapter)
1022{
5536d210
AD		 1023 int v_idx = adapter->num_q_vectors;
1024
1025 adapter->num_tx_queues = 0;
1026 adapter->num_rx_queues = 0;
047e0030 1027 adapter->num_q_vectors = 0;
5536d210
AD		 1028
1029 while (v_idx--)
1030 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1031}
1032
1033/**
1034 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1035 *
1036 * This function resets the device so that it has 0 rx queues, tx queues, and
1037 * MSI-X interrupts allocated.
1038 */
1039static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1040{
047e0030
AD		 1041 igb_free_q_vectors(adapter);
1042 igb_reset_interrupt_capability(adapter);
1043}
9d5c8243
AK		 1044
1045/**
1046 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1047 *
1048 * Attempt to configure interrupts using the best available
1049 * capabilities of the hardware and kernel.
1050 **/
53c7d064 1051static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1052{
1053 int err;
1054 int numvecs, i;
1055
53c7d064
SA		 1056 if (!msix)
1057 goto msi_only;
1058
83b7180d 1059 /* Number of supported queues. */
a99955fc 1060 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1061 if (adapter->vfs_allocated_count)
1062 adapter->num_tx_queues = 1;
1063 else
1064 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1065
047e0030
AD		 1066 /* start with one vector for every rx queue */
1067 numvecs = adapter->num_rx_queues;
1068
3ad2f3fb 1069 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1070 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1071 numvecs += adapter->num_tx_queues;
047e0030
AD		 1072
1073 /* store the number of vectors reserved for queues */
1074 adapter->num_q_vectors = numvecs;
1075
1076 /* add 1 vector for link status interrupts */
1077 numvecs++;
9d5c8243
AK		 1078 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1079 GFP_KERNEL);
f96a8a0b 1080
9d5c8243
AK		 1081 if (!adapter->msix_entries)
1082 goto msi_only;
1083
1084 for (i = 0; i < numvecs; i++)
1085 adapter->msix_entries[i].entry = i;
1086
1087 err = pci_enable_msix(adapter->pdev,
1088 adapter->msix_entries,
1089 numvecs);
1090 if (err == 0)
0c2cc02e 1091 return;
9d5c8243
AK		 1092
1093 igb_reset_interrupt_capability(adapter);
1094
1095 /* If we can't do MSI-X, try MSI */
1096msi_only:
2a3abf6d
AD		 1097#ifdef CONFIG_PCI_IOV
1098 /* disable SR-IOV for non MSI-X configurations */
1099 if (adapter->vf_data) {
1100 struct e1000_hw *hw = &adapter->hw;
1101 /* disable iov and allow time for transactions to clear */
1102 pci_disable_sriov(adapter->pdev);
1103 msleep(500);
1104
1105 kfree(adapter->vf_data);
1106 adapter->vf_data = NULL;
1107 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1108 wrfl();
2a3abf6d
AD		 1109 msleep(100);
1110 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1111 }
1112#endif
4fc82adf 1113 adapter->vfs_allocated_count = 0;
a99955fc 1114 adapter->rss_queues = 1;
4fc82adf 1115 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1116 adapter->num_rx_queues = 1;
661086df 1117 adapter->num_tx_queues = 1;
047e0030 1118 adapter->num_q_vectors = 1;
9d5c8243 1119 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1120 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1121}
1122
5536d210
AD		 1123static void igb_add_ring(struct igb_ring *ring,
1124 struct igb_ring_container *head)
1125{
1126 head->ring = ring;
1127 head->count++;
1128}
1129
047e0030 1130/**
5536d210 1131 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1132 * @adapter: board private structure to initialize
5536d210
AD		 1133 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1134 * @v_idx: index of vector in adapter struct
1135 * @txr_count: total number of Tx rings to allocate
1136 * @txr_idx: index of first Tx ring to allocate
1137 * @rxr_count: total number of Rx rings to allocate
1138 * @rxr_idx: index of first Rx ring to allocate
047e0030 1139 *
5536d210 1140 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1141 **/
5536d210
AD		 1142static int igb_alloc_q_vector(struct igb_adapter *adapter,
1143 int v_count, int v_idx,
1144 int txr_count, int txr_idx,
1145 int rxr_count, int rxr_idx)
047e0030
AD		 1146{
1147 struct igb_q_vector *q_vector;
5536d210
AD		 1148 struct igb_ring *ring;
1149 int ring_count, size;
047e0030 1150
5536d210
AD		 1151 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1152 if (txr_count > 1 || rxr_count > 1)
1153 return -ENOMEM;
1154
1155 ring_count = txr_count + rxr_count;
1156 size = sizeof(struct igb_q_vector) +
1157 (sizeof(struct igb_ring) * ring_count);
1158
1159 /* allocate q_vector and rings */
1160 q_vector = kzalloc(size, GFP_KERNEL);
1161 if (!q_vector)
1162 return -ENOMEM;
1163
1164 /* initialize NAPI */
1165 netif_napi_add(adapter->netdev, &q_vector->napi,
1166 igb_poll, 64);
1167
1168 /* tie q_vector and adapter together */
1169 adapter->q_vector[v_idx] = q_vector;
1170 q_vector->adapter = adapter;
1171
1172 /* initialize work limits */
1173 q_vector->tx.work_limit = adapter->tx_work_limit;
1174
1175 /* initialize ITR configuration */
1176 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1177 q_vector->itr_val = IGB_START_ITR;
1178
1179 /* initialize pointer to rings */
1180 ring = q_vector->ring;
1181
1182 if (txr_count) {
1183 /* assign generic ring traits */
1184 ring->dev = &adapter->pdev->dev;
1185 ring->netdev = adapter->netdev;
1186
1187 /* configure backlink on ring */
1188 ring->q_vector = q_vector;
1189
1190 /* update q_vector Tx values */
1191 igb_add_ring(ring, &q_vector->tx);
1192
1193 /* For 82575, context index must be unique per ring. */
1194 if (adapter->hw.mac.type == e1000_82575)
1195 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1196
1197 /* apply Tx specific ring traits */
1198 ring->count = adapter->tx_ring_count;
1199 ring->queue_index = txr_idx;
1200
1201 /* assign ring to adapter */
1202 adapter->tx_ring[txr_idx] = ring;
1203
1204 /* push pointer to next ring */
1205 ring++;
047e0030 1206 }
81c2fc22 1207
5536d210
AD		 1208 if (rxr_count) {
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
047e0030 1212
5536d210
AD		 1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
047e0030 1215
5536d210
AD		 1216 /* update q_vector Rx values */
1217 igb_add_ring(ring, &q_vector->rx);
047e0030 1218
5536d210
AD		 1219 /* set flag indicating ring supports SCTP checksum offload */
1220 if (adapter->hw.mac.type >= e1000_82576)
1221 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1222
5536d210
AD		 1223 /*
1224 * On i350, i210, and i211, loopback VLAN packets
1225 * have the tag byte-swapped.
1226 * */
1227 if (adapter->hw.mac.type >= e1000_i350)
1228 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1229
5536d210
AD		 1230 /* apply Rx specific ring traits */
1231 ring->count = adapter->rx_ring_count;
1232 ring->queue_index = rxr_idx;
1233
1234 /* assign ring to adapter */
1235 adapter->rx_ring[rxr_idx] = ring;
1236 }
1237
1238 return 0;
047e0030
AD		 1239}
1240
5536d210 1241
047e0030 1242/**
5536d210
AD		 1243 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1244 * @adapter: board private structure to initialize
047e0030 1245 *
5536d210
AD		 1246 * We allocate one q_vector per queue interrupt. If allocation fails we
1247 * return -ENOMEM.
047e0030 1248 **/
5536d210 1249static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1250{
5536d210
AD		 1251 int q_vectors = adapter->num_q_vectors;
1252 int rxr_remaining = adapter->num_rx_queues;
1253 int txr_remaining = adapter->num_tx_queues;
1254 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1255 int err;
047e0030 1256
5536d210
AD		 1257 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1258 for (; rxr_remaining; v_idx++) {
1259 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1260 0, 0, 1, rxr_idx);
047e0030 1261
5536d210
AD		 1262 if (err)
1263 goto err_out;
1264
1265 /* update counts and index */
1266 rxr_remaining--;
1267 rxr_idx++;
047e0030 1268 }
047e0030 1269 }
5536d210
AD		 1270
1271 for (; v_idx < q_vectors; v_idx++) {
1272 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1273 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1274 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1275 tqpv, txr_idx, rqpv, rxr_idx);
1276
1277 if (err)
1278 goto err_out;
1279
1280 /* update counts and index */
1281 rxr_remaining -= rqpv;
1282 txr_remaining -= tqpv;
1283 rxr_idx++;
1284 txr_idx++;
1285 }
1286
047e0030 1287 return 0;
5536d210
AD		 1288
1289err_out:
1290 adapter->num_tx_queues = 0;
1291 adapter->num_rx_queues = 0;
1292 adapter->num_q_vectors = 0;
1293
1294 while (v_idx--)
1295 igb_free_q_vector(adapter, v_idx);
1296
1297 return -ENOMEM;
047e0030
AD		 1298}
1299
1300/**
1301 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1302 *
1303 * This function initializes the interrupts and allocates all of the queues.
1304 **/
53c7d064 1305static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1306{
1307 struct pci_dev *pdev = adapter->pdev;
1308 int err;
1309
53c7d064 1310 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1311
1312 err = igb_alloc_q_vectors(adapter);
1313 if (err) {
1314 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1315 goto err_alloc_q_vectors;
1316 }
1317
5536d210 1318 igb_cache_ring_register(adapter);
047e0030
AD		 1319
1320 return 0;
5536d210 1321
047e0030
AD		 1322err_alloc_q_vectors:
1323 igb_reset_interrupt_capability(adapter);
1324 return err;
1325}
1326
9d5c8243
AK		 1327/**
1328 * igb_request_irq - initialize interrupts
1329 *
1330 * Attempts to configure interrupts using the best available
1331 * capabilities of the hardware and kernel.
1332 **/
1333static int igb_request_irq(struct igb_adapter *adapter)
1334{
1335 struct net_device *netdev = adapter->netdev;
047e0030 1336 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1337 int err = 0;
1338
1339 if (adapter->msix_entries) {
1340 err = igb_request_msix(adapter);
844290e5 1341 if (!err)
9d5c8243 1342 goto request_done;
9d5c8243 1343 /* fall back to MSI */
5536d210
AD		 1344 igb_free_all_tx_resources(adapter);
1345 igb_free_all_rx_resources(adapter);
53c7d064 1346
047e0030 1347 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1348 err = igb_init_interrupt_scheme(adapter, false);
1349 if (err)
047e0030 1350 goto request_done;
53c7d064 1351
047e0030
AD		 1352 igb_setup_all_tx_resources(adapter);
1353 igb_setup_all_rx_resources(adapter);
53c7d064 1354 igb_configure(adapter);
9d5c8243 1355 }
844290e5 1356
c74d588e
AD		 1357 igb_assign_vector(adapter->q_vector[0], 0);
1358
7dfc16fa 1359 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1360 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1361 netdev->name, adapter);
9d5c8243
AK		 1362 if (!err)
1363 goto request_done;
047e0030 1364
9d5c8243
AK		 1365 /* fall back to legacy interrupts */
1366 igb_reset_interrupt_capability(adapter);
7dfc16fa 1367 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1368 }
1369
c74d588e 1370 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1371 netdev->name, adapter);
9d5c8243 1372
6cb5e577 1373 if (err)
c74d588e 1374 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1375 err);
9d5c8243
AK		 1376
1377request_done:
1378 return err;
1379}
1380
1381static void igb_free_irq(struct igb_adapter *adapter)
1382{
9d5c8243
AK		 1383 if (adapter->msix_entries) {
1384 int vector = 0, i;
1385
047e0030 1386 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1387
0d1ae7f4 1388 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1389 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1390 adapter->q_vector[i]);
047e0030
AD		 1391 } else {
1392 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1393 }
9d5c8243
AK		 1394}
1395
1396/**
1397 * igb_irq_disable - Mask off interrupt generation on the NIC
1398 * @adapter: board private structure
1399 **/
1400static void igb_irq_disable(struct igb_adapter *adapter)
1401{
1402 struct e1000_hw *hw = &adapter->hw;
1403
25568a53
AD		 1404 /*
1405 * we need to be careful when disabling interrupts. The VFs are also
1406 * mapped into these registers and so clearing the bits can cause
1407 * issues on the VF drivers so we only need to clear what we set
1408 */
9d5c8243 1409 if (adapter->msix_entries) {
2dfd1212
AD		 1410 u32 regval = rd32(E1000_EIAM);
1411 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1412 wr32(E1000_EIMC, adapter->eims_enable_mask);
1413 regval = rd32(E1000_EIAC);
1414 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1415 }
844290e5
PW		 1416
1417 wr32(E1000_IAM, 0);
9d5c8243
AK		 1418 wr32(E1000_IMC, ~0);
1419 wrfl();
81a61859
ET		 1420 if (adapter->msix_entries) {
1421 int i;
1422 for (i = 0; i < adapter->num_q_vectors; i++)
1423 synchronize_irq(adapter->msix_entries[i].vector);
1424 } else {
1425 synchronize_irq(adapter->pdev->irq);
1426 }
9d5c8243
AK		 1427}
1428
1429/**
1430 * igb_irq_enable - Enable default interrupt generation settings
1431 * @adapter: board private structure
1432 **/
1433static void igb_irq_enable(struct igb_adapter *adapter)
1434{
1435 struct e1000_hw *hw = &adapter->hw;
1436
1437 if (adapter->msix_entries) {
06218a8d 1438 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1439 u32 regval = rd32(E1000_EIAC);
1440 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1441 regval = rd32(E1000_EIAM);
1442 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1443 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1444 if (adapter->vfs_allocated_count) {
4ae196df 1445 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1446 ims |= E1000_IMS_VMMB;
1447 }
1448 wr32(E1000_IMS, ims);
844290e5 1449 } else {
55cac248
AD		 1450 wr32(E1000_IMS, IMS_ENABLE_MASK |
1451 E1000_IMS_DRSTA);
1452 wr32(E1000_IAM, IMS_ENABLE_MASK |
1453 E1000_IMS_DRSTA);
844290e5 1454 }
9d5c8243
AK		 1455}
1456
1457static void igb_update_mng_vlan(struct igb_adapter *adapter)
1458{
51466239 1459 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1460 u16 vid = adapter->hw.mng_cookie.vlan_id;
1461 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1462
1463 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1464 /* add VID to filter table */
1465 igb_vfta_set(hw, vid, true);
1466 adapter->mng_vlan_id = vid;
1467 } else {
1468 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1469 }
1470
1471 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1472 (vid != old_vid) &&
b2cb09b1 1473 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1474 /* remove VID from filter table */
1475 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1476 }
1477}
1478
1479/**
1480 * igb_release_hw_control - release control of the h/w to f/w
1481 * @adapter: address of board private structure
1482 *
1483 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1484 * For ASF and Pass Through versions of f/w this means that the
1485 * driver is no longer loaded.
1486 *
1487 **/
1488static void igb_release_hw_control(struct igb_adapter *adapter)
1489{
1490 struct e1000_hw *hw = &adapter->hw;
1491 u32 ctrl_ext;
1492
1493 /* Let firmware take over control of h/w */
1494 ctrl_ext = rd32(E1000_CTRL_EXT);
1495 wr32(E1000_CTRL_EXT,
1496 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1497}
1498
9d5c8243
AK		 1499/**
1500 * igb_get_hw_control - get control of the h/w from f/w
1501 * @adapter: address of board private structure
1502 *
1503 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1504 * For ASF and Pass Through versions of f/w this means that
1505 * the driver is loaded.
1506 *
1507 **/
1508static void igb_get_hw_control(struct igb_adapter *adapter)
1509{
1510 struct e1000_hw *hw = &adapter->hw;
1511 u32 ctrl_ext;
1512
1513 /* Let firmware know the driver has taken over */
1514 ctrl_ext = rd32(E1000_CTRL_EXT);
1515 wr32(E1000_CTRL_EXT,
1516 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1517}
1518
9d5c8243
AK		 1519/**
1520 * igb_configure - configure the hardware for RX and TX
1521 * @adapter: private board structure
1522 **/
1523static void igb_configure(struct igb_adapter *adapter)
1524{
1525 struct net_device *netdev = adapter->netdev;
1526 int i;
1527
1528 igb_get_hw_control(adapter);
ff41f8dc 1529 igb_set_rx_mode(netdev);
9d5c8243
AK		 1530
1531 igb_restore_vlan(adapter);
9d5c8243 1532
85b430b4 1533 igb_setup_tctl(adapter);
06cf2666 1534 igb_setup_mrqc(adapter);
9d5c8243 1535 igb_setup_rctl(adapter);
85b430b4
AD		 1536
1537 igb_configure_tx(adapter);
9d5c8243 1538 igb_configure_rx(adapter);
662d7205
AD		 1539
1540 igb_rx_fifo_flush_82575(&adapter->hw);
1541
c493ea45 1542 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1543 * at least 1 descriptor unused to make sure
1544 * next_to_use != next_to_clean */
1545 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1546 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1547 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1548 }
9d5c8243
AK		 1549}
1550
88a268c1
NN		 1551/**
1552 * igb_power_up_link - Power up the phy/serdes link
1553 * @adapter: address of board private structure
1554 **/
1555void igb_power_up_link(struct igb_adapter *adapter)
1556{
76886596
AA		 1557 igb_reset_phy(&adapter->hw);
1558
88a268c1
NN		 1559 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1560 igb_power_up_phy_copper(&adapter->hw);
1561 else
1562 igb_power_up_serdes_link_82575(&adapter->hw);
1563}
1564
1565/**
1566 * igb_power_down_link - Power down the phy/serdes link
1567 * @adapter: address of board private structure
1568 */
1569static void igb_power_down_link(struct igb_adapter *adapter)
1570{
1571 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1572 igb_power_down_phy_copper_82575(&adapter->hw);
1573 else
1574 igb_shutdown_serdes_link_82575(&adapter->hw);
1575}
9d5c8243
AK		 1576
1577/**
1578 * igb_up - Open the interface and prepare it to handle traffic
1579 * @adapter: board private structure
1580 **/
9d5c8243
AK		 1581int igb_up(struct igb_adapter *adapter)
1582{
1583 struct e1000_hw *hw = &adapter->hw;
1584 int i;
1585
1586 /* hardware has been reset, we need to reload some things */
1587 igb_configure(adapter);
1588
1589 clear_bit(__IGB_DOWN, &adapter->state);
1590
0d1ae7f4
AD		 1591 for (i = 0; i < adapter->num_q_vectors; i++)
1592 napi_enable(&(adapter->q_vector[i]->napi));
1593
844290e5 1594 if (adapter->msix_entries)
9d5c8243 1595 igb_configure_msix(adapter);
feeb2721
AD		 1596 else
1597 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1598
1599 /* Clear any pending interrupts. */
1600 rd32(E1000_ICR);
1601 igb_irq_enable(adapter);
1602
d4960307
AD		 1603 /* notify VFs that reset has been completed */
1604 if (adapter->vfs_allocated_count) {
1605 u32 reg_data = rd32(E1000_CTRL_EXT);
1606 reg_data |= E1000_CTRL_EXT_PFRSTD;
1607 wr32(E1000_CTRL_EXT, reg_data);
1608 }
1609
4cb9be7a
JB		 1610 netif_tx_start_all_queues(adapter->netdev);
1611
25568a53
AD		 1612 /* start the watchdog. */
1613 hw->mac.get_link_status = 1;
1614 schedule_work(&adapter->watchdog_task);
1615
9d5c8243
AK		 1616 return 0;
1617}
1618
1619void igb_down(struct igb_adapter *adapter)
1620{
9d5c8243 1621 struct net_device *netdev = adapter->netdev;
330a6d6a 1622 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1623 u32 tctl, rctl;
1624 int i;
1625
1626 /* signal that we're down so the interrupt handler does not
1627 * reschedule our watchdog timer */
1628 set_bit(__IGB_DOWN, &adapter->state);
1629
1630 /* disable receives in the hardware */
1631 rctl = rd32(E1000_RCTL);
1632 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1633 /* flush and sleep below */
1634
fd2ea0a7 1635 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1636
1637 /* disable transmits in the hardware */
1638 tctl = rd32(E1000_TCTL);
1639 tctl &= ~E1000_TCTL_EN;
1640 wr32(E1000_TCTL, tctl);
1641 /* flush both disables and wait for them to finish */
1642 wrfl();
1643 msleep(10);
1644
0d1ae7f4
AD		 1645 for (i = 0; i < adapter->num_q_vectors; i++)
1646 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1647
9d5c8243
AK		 1648 igb_irq_disable(adapter);
1649
1650 del_timer_sync(&adapter->watchdog_timer);
1651 del_timer_sync(&adapter->phy_info_timer);
1652
9d5c8243 1653 netif_carrier_off(netdev);
04fe6358
AD		 1654
1655 /* record the stats before reset*/
12dcd86b
ED		 1656 spin_lock(&adapter->stats64_lock);
1657 igb_update_stats(adapter, &adapter->stats64);
1658 spin_unlock(&adapter->stats64_lock);
04fe6358 1659
9d5c8243
AK		 1660 adapter->link_speed = 0;
1661 adapter->link_duplex = 0;
1662
3023682e
JK		 1663 if (!pci_channel_offline(adapter->pdev))
1664 igb_reset(adapter);
9d5c8243
AK		 1665 igb_clean_all_tx_rings(adapter);
1666 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1667#ifdef CONFIG_IGB_DCA
1668
1669 /* since we reset the hardware DCA settings were cleared */
1670 igb_setup_dca(adapter);
1671#endif
9d5c8243
AK		 1672}
1673
1674void igb_reinit_locked(struct igb_adapter *adapter)
1675{
1676 WARN_ON(in_interrupt());
1677 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1678 msleep(1);
1679 igb_down(adapter);
1680 igb_up(adapter);
1681 clear_bit(__IGB_RESETTING, &adapter->state);
1682}
1683
1684void igb_reset(struct igb_adapter *adapter)
1685{
090b1795 1686 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1687 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1688 struct e1000_mac_info *mac = &hw->mac;
1689 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1690 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1691
1692 /* Repartition Pba for greater than 9k mtu
1693 * To take effect CTRL.RST is required.
1694 */
fa4dfae0 1695 switch (mac->type) {
d2ba2ed8 1696 case e1000_i350:
55cac248
AD		 1697 case e1000_82580:
1698 pba = rd32(E1000_RXPBS);
1699 pba = igb_rxpbs_adjust_82580(pba);
1700 break;
fa4dfae0 1701 case e1000_82576:
d249be54
AD		 1702 pba = rd32(E1000_RXPBS);
1703 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1704 break;
1705 case e1000_82575:
f96a8a0b
CW		 1706 case e1000_i210:
1707 case e1000_i211:
fa4dfae0
AD		 1708 default:
1709 pba = E1000_PBA_34K;
1710 break;
2d064c06 1711 }
9d5c8243 1712
2d064c06
AD		 1713 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1714 (mac->type < e1000_82576)) {
9d5c8243
AK		 1715 /* adjust PBA for jumbo frames */
1716 wr32(E1000_PBA, pba);
1717
1718 /* To maintain wire speed transmits, the Tx FIFO should be
1719 * large enough to accommodate two full transmit packets,
1720 * rounded up to the next 1KB and expressed in KB. Likewise,
1721 * the Rx FIFO should be large enough to accommodate at least
1722 * one full receive packet and is similarly rounded up and
1723 * expressed in KB. */
1724 pba = rd32(E1000_PBA);
1725 /* upper 16 bits has Tx packet buffer allocation size in KB */
1726 tx_space = pba >> 16;
1727 /* lower 16 bits has Rx packet buffer allocation size in KB */
1728 pba &= 0xffff;
1729 /* the tx fifo also stores 16 bytes of information about the tx
1730 * but don't include ethernet FCS because hardware appends it */
1731 min_tx_space = (adapter->max_frame_size +
85e8d004 1732 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1733 ETH_FCS_LEN) * 2;
1734 min_tx_space = ALIGN(min_tx_space, 1024);
1735 min_tx_space >>= 10;
1736 /* software strips receive CRC, so leave room for it */
1737 min_rx_space = adapter->max_frame_size;
1738 min_rx_space = ALIGN(min_rx_space, 1024);
1739 min_rx_space >>= 10;
1740
1741 /* If current Tx allocation is less than the min Tx FIFO size,
1742 * and the min Tx FIFO size is less than the current Rx FIFO
1743 * allocation, take space away from current Rx allocation */
1744 if (tx_space < min_tx_space &&
1745 ((min_tx_space - tx_space) < pba)) {
1746 pba = pba - (min_tx_space - tx_space);
1747
1748 /* if short on rx space, rx wins and must trump tx
1749 * adjustment */
1750 if (pba < min_rx_space)
1751 pba = min_rx_space;
1752 }
2d064c06 1753 wr32(E1000_PBA, pba);
9d5c8243 1754 }
9d5c8243
AK		 1755
1756 /* flow control settings */
1757 /* The high water mark must be low enough to fit one full frame
1758 * (or the size used for early receive) above it in the Rx FIFO.
1759 * Set it to the lower of:
1760 * - 90% of the Rx FIFO size, or
1761 * - the full Rx FIFO size minus one full frame */
1762 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1763 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1764
d48507fe 1765 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1766 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1767 fc->pause_time = 0xFFFF;
1768 fc->send_xon = 1;
0cce119a 1769 fc->current_mode = fc->requested_mode;
9d5c8243 1770
4ae196df
AD		 1771 /* disable receive for all VFs and wait one second */
1772 if (adapter->vfs_allocated_count) {
1773 int i;
1774 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1775 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1776
1777 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1778 igb_ping_all_vfs(adapter);
4ae196df
AD		 1779
1780 /* disable transmits and receives */
1781 wr32(E1000_VFRE, 0);
1782 wr32(E1000_VFTE, 0);
1783 }
1784
9d5c8243 1785 /* Allow time for pending master requests to run */
330a6d6a 1786 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1787 wr32(E1000_WUC, 0);
1788
330a6d6a 1789 if (hw->mac.ops.init_hw(hw))
090b1795 1790 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1791
a27416bb
MV		 1792 /*
1793 * Flow control settings reset on hardware reset, so guarantee flow
1794 * control is off when forcing speed.
1795 */
1796 if (!hw->mac.autoneg)
1797 igb_force_mac_fc(hw);
1798
b6e0c419 1799 igb_init_dmac(adapter, pba);
e428893b
CW		 1800#ifdef CONFIG_IGB_HWMON
1801 /* Re-initialize the thermal sensor on i350 devices. */
1802 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1803 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1804 /* If present, re-initialize the external thermal sensor
1805 * interface.
1806 */
1807 if (adapter->ets)
1808 mac->ops.init_thermal_sensor_thresh(hw);
1809 }
1810 }
1811#endif
88a268c1
NN		 1812 if (!netif_running(adapter->netdev))
1813 igb_power_down_link(adapter);
1814
9d5c8243
AK		 1815 igb_update_mng_vlan(adapter);
1816
1817 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1818 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1819
1f6e8178
MV		 1820 /* Re-enable PTP, where applicable. */
1821 igb_ptp_reset(adapter);
1f6e8178 1822
330a6d6a 1823 igb_get_phy_info(hw);
9d5c8243
AK		 1824}
1825
c8f44aff
MM		 1826static netdev_features_t igb_fix_features(struct net_device *netdev,
1827 netdev_features_t features)
b2cb09b1
JP		 1828{
1829 /*
1830 * Since there is no support for separate rx/tx vlan accel
1831 * enable/disable make sure tx flag is always in same state as rx.
1832 */
1833 if (features & NETIF_F_HW_VLAN_RX)
1834 features |= NETIF_F_HW_VLAN_TX;
1835 else
1836 features &= ~NETIF_F_HW_VLAN_TX;
1837
1838 return features;
1839}
1840
c8f44aff
MM		 1841static int igb_set_features(struct net_device *netdev,
1842 netdev_features_t features)
ac52caa3 1843{
c8f44aff 1844 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1845 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1846
b2cb09b1
JP		 1847 if (changed & NETIF_F_HW_VLAN_RX)
1848 igb_vlan_mode(netdev, features);
1849
89eaefb6
BG		 1850 if (!(changed & NETIF_F_RXALL))
1851 return 0;
1852
1853 netdev->features = features;
1854
1855 if (netif_running(netdev))
1856 igb_reinit_locked(adapter);
1857 else
1858 igb_reset(adapter);
1859
ac52caa3
MM		 1860 return 0;
1861}
1862
2e5c6922 1863static const struct net_device_ops igb_netdev_ops = {
559e9c49 1864 .ndo_open = igb_open,
2e5c6922 1865 .ndo_stop = igb_close,
cd392f5c 1866 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1867 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1868 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1869 .ndo_set_mac_address = igb_set_mac,
1870 .ndo_change_mtu = igb_change_mtu,
1871 .ndo_do_ioctl = igb_ioctl,
1872 .ndo_tx_timeout = igb_tx_timeout,
1873 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1874 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1875 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1876 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1877 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1878 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1879 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1880#ifdef CONFIG_NET_POLL_CONTROLLER
1881 .ndo_poll_controller = igb_netpoll,
1882#endif
b2cb09b1
JP		 1883 .ndo_fix_features = igb_fix_features,
1884 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1885};
1886
d67974f0
CW		 1887/**
1888 * igb_set_fw_version - Configure version string for ethtool
1889 * @adapter: adapter struct
1890 *
1891 **/
1892void igb_set_fw_version(struct igb_adapter *adapter)
1893{
1894 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1895 struct e1000_fw_version fw;
1896
1897 igb_get_fw_version(hw, &fw);
1898
1899 switch (hw->mac.type) {
1900 case e1000_i211:
d67974f0 1901 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1902 "%2d.%2d-%d",
1903 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1904 break;
1905
1906 default:
1907 /* if option is rom valid, display its version too */
1908 if (fw.or_valid) {
1909 snprintf(adapter->fw_version,
1910 sizeof(adapter->fw_version),
1911 "%d.%d, 0x%08x, %d.%d.%d",
1912 fw.eep_major, fw.eep_minor, fw.etrack_id,
1913 fw.or_major, fw.or_build, fw.or_patch);
1914 /* no option rom */
1915 } else {
1916 snprintf(adapter->fw_version,
1917 sizeof(adapter->fw_version),
1918 "%d.%d, 0x%08x",
1919 fw.eep_major, fw.eep_minor, fw.etrack_id);
1920 }
1921 break;
d67974f0 1922 }
d67974f0
CW		 1923 return;
1924}
1925
441fc6fd
CW		 1926static const struct i2c_board_info i350_sensor_info = {
1927 I2C_BOARD_INFO("i350bb", 0Xf8),
1928};
1929
1930/* igb_init_i2c - Init I2C interface
1931 * @adapter: pointer to adapter structure
1932 *
1933 */
1934static s32 igb_init_i2c(struct igb_adapter *adapter)
1935{
1936 s32 status = E1000_SUCCESS;
1937
1938 /* I2C interface supported on i350 devices */
1939 if (adapter->hw.mac.type != e1000_i350)
1940 return E1000_SUCCESS;
1941
1942 /* Initialize the i2c bus which is controlled by the registers.
1943 * This bus will use the i2c_algo_bit structue that implements
1944 * the protocol through toggling of the 4 bits in the register.
1945 */
1946 adapter->i2c_adap.owner = THIS_MODULE;
1947 adapter->i2c_algo = igb_i2c_algo;
1948 adapter->i2c_algo.data = adapter;
1949 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1950 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1951 strlcpy(adapter->i2c_adap.name, "igb BB",
1952 sizeof(adapter->i2c_adap.name));
1953 status = i2c_bit_add_bus(&adapter->i2c_adap);
1954 return status;
1955}
1956
9d5c8243
AK		 1957/**
1958 * igb_probe - Device Initialization Routine
1959 * @pdev: PCI device information struct
1960 * @ent: entry in igb_pci_tbl
1961 *
1962 * Returns 0 on success, negative on failure
1963 *
1964 * igb_probe initializes an adapter identified by a pci_dev structure.
1965 * The OS initialization, configuring of the adapter private structure,
1966 * and a hardware reset occur.
1967 **/
1dd06ae8 1968static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1969{
1970 struct net_device *netdev;
1971 struct igb_adapter *adapter;
1972 struct e1000_hw *hw;
4337e993 1973 u16 eeprom_data = 0;
9835fd73 1974 s32 ret_val;
4337e993 1975 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1976 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1977 unsigned long mmio_start, mmio_len;
2d6a5e95 1978 int err, pci_using_dac;
9835fd73 1979 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1980
bded64a7
AG		 1981 /* Catch broken hardware that put the wrong VF device ID in
1982 * the PCIe SR-IOV capability.
1983 */
1984 if (pdev->is_virtfn) {
1985 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1986 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1987 return -EINVAL;
1988 }
1989
aed5dec3 1990 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1991 if (err)
1992 return err;
1993
1994 pci_using_dac = 0;
59d71989 1995 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1996 if (!err) {
59d71989 1997 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1998 if (!err)
1999 pci_using_dac = 1;
2000 } else {
59d71989 2001 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2002 if (err) {
59d71989 2003 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 2004 if (err) {
2005 dev_err(&pdev->dev, "No usable DMA "
2006 "configuration, aborting\n");
2007 goto err_dma;
2008 }
2009 }
2010 }
2011
aed5dec3
AD		 2012 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2013 IORESOURCE_MEM),
2014 igb_driver_name);
9d5c8243
AK		 2015 if (err)
2016 goto err_pci_reg;
2017
19d5afd4 2018 pci_enable_pcie_error_reporting(pdev);
40a914fa 2019
9d5c8243 2020 pci_set_master(pdev);
c682fc23 2021 pci_save_state(pdev);
9d5c8243
AK		 2022
2023 err = -ENOMEM;
1bfaf07b 2024 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2025 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2026 if (!netdev)
2027 goto err_alloc_etherdev;
2028
2029 SET_NETDEV_DEV(netdev, &pdev->dev);
2030
2031 pci_set_drvdata(pdev, netdev);
2032 adapter = netdev_priv(netdev);
2033 adapter->netdev = netdev;
2034 adapter->pdev = pdev;
2035 hw = &adapter->hw;
2036 hw->back = adapter;
b3f4d599 2037 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2038
2039 mmio_start = pci_resource_start(pdev, 0);
2040 mmio_len = pci_resource_len(pdev, 0);
2041
2042 err = -EIO;
28b0759c
AD		 2043 hw->hw_addr = ioremap(mmio_start, mmio_len);
2044 if (!hw->hw_addr)
9d5c8243
AK		 2045 goto err_ioremap;
2046
2e5c6922 2047 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2048 igb_set_ethtool_ops(netdev);
9d5c8243 2049 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2050
2051 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2052
2053 netdev->mem_start = mmio_start;
2054 netdev->mem_end = mmio_start + mmio_len;
2055
9d5c8243
AK		 2056 /* PCI config space info */
2057 hw->vendor_id = pdev->vendor;
2058 hw->device_id = pdev->device;
2059 hw->revision_id = pdev->revision;
2060 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2061 hw->subsystem_device_id = pdev->subsystem_device;
2062
9d5c8243
AK		 2063 /* Copy the default MAC, PHY and NVM function pointers */
2064 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2065 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2066 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2067 /* Initialize skew-specific constants */
2068 err = ei->get_invariants(hw);
2069 if (err)
450c87c8 2070 goto err_sw_init;
9d5c8243 2071
450c87c8 2072 /* setup the private structure */
9d5c8243
AK		 2073 err = igb_sw_init(adapter);
2074 if (err)
2075 goto err_sw_init;
2076
2077 igb_get_bus_info_pcie(hw);
2078
2079 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2080
2081 /* Copper options */
2082 if (hw->phy.media_type == e1000_media_type_copper) {
2083 hw->phy.mdix = AUTO_ALL_MODES;
2084 hw->phy.disable_polarity_correction = false;
2085 hw->phy.ms_type = e1000_ms_hw_default;
2086 }
2087
2088 if (igb_check_reset_block(hw))
2089 dev_info(&pdev->dev,
2090 "PHY reset is blocked due to SOL/IDER session.\n");
2091
077887c3
AD		 2092 /*
2093 * features is initialized to 0 in allocation, it might have bits
2094 * set by igb_sw_init so we should use an or instead of an
2095 * assignment.
2096 */
2097 netdev->features |= NETIF_F_SG |
2098 NETIF_F_IP_CSUM |
2099 NETIF_F_IPV6_CSUM |
2100 NETIF_F_TSO |
2101 NETIF_F_TSO6 |
2102 NETIF_F_RXHASH |
2103 NETIF_F_RXCSUM |
2104 NETIF_F_HW_VLAN_RX |
2105 NETIF_F_HW_VLAN_TX;
2106
2107 /* copy netdev features into list of user selectable features */
2108 netdev->hw_features |= netdev->features;
89eaefb6 2109 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2110
2111 /* set this bit last since it cannot be part of hw_features */
2112 netdev->features |= NETIF_F_HW_VLAN_FILTER;
2113
2114 netdev->vlan_features |= NETIF_F_TSO |
2115 NETIF_F_TSO6 |
2116 NETIF_F_IP_CSUM |
2117 NETIF_F_IPV6_CSUM |
2118 NETIF_F_SG;
48f29ffc 2119
6b8f0922
BG		 2120 netdev->priv_flags |= IFF_SUPP_NOFCS;
2121
7b872a55 2122 if (pci_using_dac) {
9d5c8243 2123 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2124 netdev->vlan_features |= NETIF_F_HIGHDMA;
2125 }
9d5c8243 2126
ac52caa3
MM		 2127 if (hw->mac.type >= e1000_82576) {
2128 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2129 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2130 }
b9473560 2131
01789349
JP		 2132 netdev->priv_flags |= IFF_UNICAST_FLT;
2133
330a6d6a 2134 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2135
2136 /* before reading the NVM, reset the controller to put the device in a
2137 * known good starting state */
2138 hw->mac.ops.reset_hw(hw);
2139
f96a8a0b
CW		 2140 /*
2141 * make sure the NVM is good , i211 parts have special NVM that
2142 * doesn't contain a checksum
2143 */
2144 if (hw->mac.type != e1000_i211) {
2145 if (hw->nvm.ops.validate(hw) < 0) {
2146 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2147 err = -EIO;
2148 goto err_eeprom;
2149 }
9d5c8243
AK		 2150 }
2151
2152 /* copy the MAC address out of the NVM */
2153 if (hw->mac.ops.read_mac_addr(hw))
2154 dev_err(&pdev->dev, "NVM Read Error\n");
2155
2156 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2157
aaeb6cdf 2158 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2159 dev_err(&pdev->dev, "Invalid MAC Address\n");
2160 err = -EIO;
2161 goto err_eeprom;
2162 }
2163
d67974f0
CW		 2164 /* get firmware version for ethtool -i */
2165 igb_set_fw_version(adapter);
2166
c061b18d 2167 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2168 (unsigned long) adapter);
c061b18d 2169 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2170 (unsigned long) adapter);
9d5c8243
AK		 2171
2172 INIT_WORK(&adapter->reset_task, igb_reset_task);
2173 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2174
450c87c8 2175 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2176 adapter->fc_autoneg = true;
2177 hw->mac.autoneg = true;
2178 hw->phy.autoneg_advertised = 0x2f;
2179
0cce119a
AD		 2180 hw->fc.requested_mode = e1000_fc_default;
2181 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2182
9d5c8243
AK		 2183 igb_validate_mdi_setting(hw);
2184
63d4a8f9 2185 /* By default, support wake on port A */
a2cf8b6c 2186 if (hw->bus.func == 0)
63d4a8f9
MV		 2187 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2188
2189 /* Check the NVM for wake support on non-port A ports */
2190 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2191 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2192 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2193 &eeprom_data);
a2cf8b6c
AD		 2194 else if (hw->bus.func == 1)
2195 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2196
63d4a8f9
MV		 2197 if (eeprom_data & IGB_EEPROM_APME)
2198 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2199
2200 /* now that we have the eeprom settings, apply the special cases where
2201 * the eeprom may be wrong or the board simply won't support wake on
2202 * lan on a particular port */
2203 switch (pdev->device) {
2204 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2205 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2206 break;
2207 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2208 case E1000_DEV_ID_82576_FIBER:
2209 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2210 /* Wake events only supported on port A for dual fiber
2211 * regardless of eeprom setting */
2212 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2213 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2214 break;
c8ea5ea9 2215 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2216 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2217 /* if quad port adapter, disable WoL on all but port A */
2218 if (global_quad_port_a != 0)
63d4a8f9 2219 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2220 else
2221 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2222 /* Reset for multiple quad port adapters */
2223 if (++global_quad_port_a == 4)
2224 global_quad_port_a = 0;
2225 break;
63d4a8f9
MV		 2226 default:
2227 /* If the device can't wake, don't set software support */
2228 if (!device_can_wakeup(&adapter->pdev->dev))
2229 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2230 }
2231
2232 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2233 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2234 adapter->wol |= E1000_WUFC_MAG;
2235
2236 /* Some vendors want WoL disabled by default, but still supported */
2237 if ((hw->mac.type == e1000_i350) &&
2238 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2239 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2240 adapter->wol = 0;
2241 }
2242
2243 device_set_wakeup_enable(&adapter->pdev->dev,
2244 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2245
2246 /* reset the hardware with the new settings */
2247 igb_reset(adapter);
2248
441fc6fd
CW		 2249 /* Init the I2C interface */
2250 err = igb_init_i2c(adapter);
2251 if (err) {
2252 dev_err(&pdev->dev, "failed to init i2c interface\n");
2253 goto err_eeprom;
2254 }
2255
9d5c8243
AK		 2256 /* let the f/w know that the h/w is now under the control of the
2257 * driver. */
2258 igb_get_hw_control(adapter);
2259
9d5c8243
AK		 2260 strcpy(netdev->name, "eth%d");
2261 err = register_netdev(netdev);
2262 if (err)
2263 goto err_register;
2264
b168dfc5
JB		 2265 /* carrier off reporting is important to ethtool even BEFORE open */
2266 netif_carrier_off(netdev);
2267
421e02f0 2268#ifdef CONFIG_IGB_DCA
bbd98fe4 2269 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2270 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2271 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2272 igb_setup_dca(adapter);
2273 }
fe4506b6 2274
38c845c7 2275#endif
e428893b
CW		 2276#ifdef CONFIG_IGB_HWMON
2277 /* Initialize the thermal sensor on i350 devices. */
2278 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2279 u16 ets_word;
3c89f6d0 2280
e428893b
CW		 2281 /*
2282 * Read the NVM to determine if this i350 device supports an
2283 * external thermal sensor.
2284 */
2285 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2286 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2287 adapter->ets = true;
2288 else
2289 adapter->ets = false;
2290 if (igb_sysfs_init(adapter))
2291 dev_err(&pdev->dev,
2292 "failed to allocate sysfs resources\n");
2293 } else {
2294 adapter->ets = false;
2295 }
2296#endif
673b8b70 2297 /* do hw tstamp init after resetting */
7ebae817 2298 igb_ptp_init(adapter);
673b8b70 2299
9d5c8243
AK		 2300 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2301 /* print bus type/speed/width info */
7c510e4b 2302 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2303 netdev->name,
559e9c49 2304 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2305 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2306 "unknown"),
59c3de89
AD		 2307 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2308 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2309 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2310 "unknown"),
7c510e4b 2311 netdev->dev_addr);
9d5c8243 2312
9835fd73
CW		 2313 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2314 if (ret_val)
2315 strcpy(part_str, "Unknown");
2316 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2317 dev_info(&pdev->dev,
2318 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2319 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2320 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2321 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2322 switch (hw->mac.type) {
2323 case e1000_i350:
f96a8a0b
CW		 2324 case e1000_i210:
2325 case e1000_i211:
09b068d4
CW		 2326 igb_set_eee_i350(hw);
2327 break;
2328 default:
2329 break;
2330 }
749ab2cd
YZ		 2331
2332 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2333 return 0;
2334
2335err_register:
2336 igb_release_hw_control(adapter);
441fc6fd 2337 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2338err_eeprom:
2339 if (!igb_check_reset_block(hw))
f5f4cf08 2340 igb_reset_phy(hw);
9d5c8243
AK		 2341
2342 if (hw->flash_address)
2343 iounmap(hw->flash_address);
9d5c8243 2344err_sw_init:
047e0030 2345 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2346 iounmap(hw->hw_addr);
2347err_ioremap:
2348 free_netdev(netdev);
2349err_alloc_etherdev:
559e9c49
AD		 2350 pci_release_selected_regions(pdev,
2351 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2352err_pci_reg:
2353err_dma:
2354 pci_disable_device(pdev);
2355 return err;
2356}
2357
fa44f2f1
GR		 2358#ifdef CONFIG_PCI_IOV
2359static int igb_disable_sriov(struct pci_dev *pdev)
2360{
2361 struct net_device *netdev = pci_get_drvdata(pdev);
2362 struct igb_adapter *adapter = netdev_priv(netdev);
2363 struct e1000_hw *hw = &adapter->hw;
2364
2365 /* reclaim resources allocated to VFs */
2366 if (adapter->vf_data) {
2367 /* disable iov and allow time for transactions to clear */
2368 if (igb_vfs_are_assigned(adapter)) {
2369 dev_warn(&pdev->dev,
2370 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2371 return -EPERM;
2372 } else {
2373 pci_disable_sriov(pdev);
2374 msleep(500);
2375 }
2376
2377 kfree(adapter->vf_data);
2378 adapter->vf_data = NULL;
2379 adapter->vfs_allocated_count = 0;
2380 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2381 wrfl();
2382 msleep(100);
2383 dev_info(&pdev->dev, "IOV Disabled\n");
2384
2385 /* Re-enable DMA Coalescing flag since IOV is turned off */
2386 adapter->flags |= IGB_FLAG_DMAC;
2387 }
2388
2389 return 0;
2390}
2391
2392static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2393{
2394 struct net_device *netdev = pci_get_drvdata(pdev);
2395 struct igb_adapter *adapter = netdev_priv(netdev);
2396 int old_vfs = pci_num_vf(pdev);
2397 int err = 0;
2398 int i;
2399
2400 if (!num_vfs)
2401 goto out;
2402 else if (old_vfs && old_vfs == num_vfs)
2403 goto out;
2404 else if (old_vfs && old_vfs != num_vfs)
2405 err = igb_disable_sriov(pdev);
2406
2407 if (err)
2408 goto out;
2409
2410 if (num_vfs > 7) {
2411 err = -EPERM;
2412 goto out;
2413 }
2414
2415 adapter->vfs_allocated_count = num_vfs;
2416
2417 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2418 sizeof(struct vf_data_storage), GFP_KERNEL);
2419
2420 /* if allocation failed then we do not support SR-IOV */
2421 if (!adapter->vf_data) {
2422 adapter->vfs_allocated_count = 0;
2423 dev_err(&pdev->dev,
2424 "Unable to allocate memory for VF Data Storage\n");
2425 err = -ENOMEM;
2426 goto out;
2427 }
2428
2429 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2430 if (err)
2431 goto err_out;
2432
2433 dev_info(&pdev->dev, "%d VFs allocated\n",
2434 adapter->vfs_allocated_count);
2435 for (i = 0; i < adapter->vfs_allocated_count; i++)
2436 igb_vf_configure(adapter, i);
2437
2438 /* DMA Coalescing is not supported in IOV mode. */
2439 adapter->flags &= ~IGB_FLAG_DMAC;
2440 goto out;
2441
2442err_out:
2443 kfree(adapter->vf_data);
2444 adapter->vf_data = NULL;
2445 adapter->vfs_allocated_count = 0;
2446out:
2447 return err;
2448}
2449
2450#endif
441fc6fd
CW		 2451/*
2452 * igb_remove_i2c - Cleanup I2C interface
2453 * @adapter: pointer to adapter structure
2454 *
2455 */
2456static void igb_remove_i2c(struct igb_adapter *adapter)
2457{
2458
2459 /* free the adapter bus structure */
2460 i2c_del_adapter(&adapter->i2c_adap);
2461}
2462
9d5c8243
AK		 2463/**
2464 * igb_remove - Device Removal Routine
2465 * @pdev: PCI device information struct
2466 *
2467 * igb_remove is called by the PCI subsystem to alert the driver
2468 * that it should release a PCI device. The could be caused by a
2469 * Hot-Plug event, or because the driver is going to be removed from
2470 * memory.
2471 **/
9f9a12f8 2472static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2473{
2474 struct net_device *netdev = pci_get_drvdata(pdev);
2475 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2476 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2477
749ab2cd 2478 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2479#ifdef CONFIG_IGB_HWMON
2480 igb_sysfs_exit(adapter);
2481#endif
441fc6fd 2482 igb_remove_i2c(adapter);
a79f4f88 2483 igb_ptp_stop(adapter);
760141a5
TH		 2484 /*
2485 * The watchdog timer may be rescheduled, so explicitly
2486 * disable watchdog from being rescheduled.
2487 */
9d5c8243
AK		 2488 set_bit(__IGB_DOWN, &adapter->state);
2489 del_timer_sync(&adapter->watchdog_timer);
2490 del_timer_sync(&adapter->phy_info_timer);
2491
760141a5
TH		 2492 cancel_work_sync(&adapter->reset_task);
2493 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2494
421e02f0 2495#ifdef CONFIG_IGB_DCA
7dfc16fa 2496 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2497 dev_info(&pdev->dev, "DCA disabled\n");
2498 dca_remove_requester(&pdev->dev);
7dfc16fa 2499 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2500 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2501 }
2502#endif
2503
9d5c8243
AK		 2504 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2505 * would have already happened in close and is redundant. */
2506 igb_release_hw_control(adapter);
2507
2508 unregister_netdev(netdev);
2509
047e0030 2510 igb_clear_interrupt_scheme(adapter);
9d5c8243 2511
37680117 2512#ifdef CONFIG_PCI_IOV
fa44f2f1 2513 igb_disable_sriov(pdev);
37680117 2514#endif
559e9c49 2515
28b0759c
AD		 2516 iounmap(hw->hw_addr);
2517 if (hw->flash_address)
2518 iounmap(hw->flash_address);
559e9c49
AD		 2519 pci_release_selected_regions(pdev,
2520 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2521
1128c756 2522 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2523 free_netdev(netdev);
2524
19d5afd4 2525 pci_disable_pcie_error_reporting(pdev);
40a914fa 2526
9d5c8243
AK		 2527 pci_disable_device(pdev);
2528}
2529
a6b623e0
AD		 2530/**
2531 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2532 * @adapter: board private structure to initialize
2533 *
2534 * This function initializes the vf specific data storage and then attempts to
2535 * allocate the VFs. The reason for ordering it this way is because it is much
2536 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2537 * the memory for the VFs.
2538 **/
9f9a12f8 2539static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2540{
2541#ifdef CONFIG_PCI_IOV
2542 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2543 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2544
f96a8a0b
CW		 2545 /* Virtualization features not supported on i210 family. */
2546 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2547 return;
2548
fa44f2f1
GR		 2549 igb_enable_sriov(pdev, max_vfs);
2550 pci_sriov_set_totalvfs(pdev, 7);
0224d663 2551
a6b623e0
AD		 2552#endif /* CONFIG_PCI_IOV */
2553}
2554
fa44f2f1 2555static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2556{
2557 struct e1000_hw *hw = &adapter->hw;
374a542d 2558 u32 max_rss_queues;
9d5c8243 2559
374a542d 2560 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2561 switch (hw->mac.type) {
374a542d
MV		 2562 case e1000_i211:
2563 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2564 break;
2565 case e1000_82575:
f96a8a0b 2566 case e1000_i210:
374a542d
MV		 2567 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2568 break;
2569 case e1000_i350:
2570 /* I350 cannot do RSS and SR-IOV at the same time */
2571 if (!!adapter->vfs_allocated_count) {
2572 max_rss_queues = 1;
2573 break;
2574 }
2575 /* fall through */
2576 case e1000_82576:
2577 if (!!adapter->vfs_allocated_count) {
2578 max_rss_queues = 2;
2579 break;
2580 }
2581 /* fall through */
2582 case e1000_82580:
2583 default:
2584 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2585 break;
374a542d
MV		 2586 }
2587
2588 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2589
2590 /* Determine if we need to pair queues. */
2591 switch (hw->mac.type) {
2592 case e1000_82575:
f96a8a0b 2593 case e1000_i211:
374a542d 2594 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2595 break;
374a542d
MV		 2596 case e1000_82576:
2597 /*
2598 * If VFs are going to be allocated with RSS queues then we
2599 * should pair the queues in order to conserve interrupts due
2600 * to limited supply.
2601 */
2602 if ((adapter->rss_queues > 1) &&
2603 (adapter->vfs_allocated_count > 6))
2604 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2605 /* fall through */
2606 case e1000_82580:
2607 case e1000_i350:
2608 case e1000_i210:
f96a8a0b 2609 default:
374a542d
MV		 2610 /*
2611 * If rss_queues > half of max_rss_queues, pair the queues in
2612 * order to conserve interrupts due to limited supply.
2613 */
2614 if (adapter->rss_queues > (max_rss_queues / 2))
2615 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2616 break;
2617 }
fa44f2f1
GR		 2618}
2619
2620/**
2621 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2622 * @adapter: board private structure to initialize
2623 *
2624 * igb_sw_init initializes the Adapter private data structure.
2625 * Fields are initialized based on PCI device information and
2626 * OS network device settings (MTU size).
2627 **/
2628static int igb_sw_init(struct igb_adapter *adapter)
2629{
2630 struct e1000_hw *hw = &adapter->hw;
2631 struct net_device *netdev = adapter->netdev;
2632 struct pci_dev *pdev = adapter->pdev;
2633
2634 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2635
2636 /* set default ring sizes */
2637 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2638 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2639
2640 /* set default ITR values */
2641 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2642 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2643
2644 /* set default work limits */
2645 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2646
2647 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2648 VLAN_HLEN;
2649 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2650
2651 spin_lock_init(&adapter->stats64_lock);
2652#ifdef CONFIG_PCI_IOV
2653 switch (hw->mac.type) {
2654 case e1000_82576:
2655 case e1000_i350:
2656 if (max_vfs > 7) {
2657 dev_warn(&pdev->dev,
2658 "Maximum of 7 VFs per PF, using max\n");
2659 adapter->vfs_allocated_count = 7;
2660 } else
2661 adapter->vfs_allocated_count = max_vfs;
2662 if (adapter->vfs_allocated_count)
2663 dev_warn(&pdev->dev,
2664 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2665 break;
2666 default:
2667 break;
2668 }
2669#endif /* CONFIG_PCI_IOV */
2670
2671 igb_init_queue_configuration(adapter);
a99955fc 2672
1128c756 2673 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2674 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2675 GFP_ATOMIC);
1128c756 2676
a6b623e0 2677 /* This call may decrease the number of queues */
53c7d064 2678 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2679 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2680 return -ENOMEM;
2681 }
2682
a6b623e0
AD		 2683 igb_probe_vfs(adapter);
2684
9d5c8243
AK		 2685 /* Explicitly disable IRQ since the NIC can be in any state. */
2686 igb_irq_disable(adapter);
2687
f96a8a0b 2688 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2689 adapter->flags &= ~IGB_FLAG_DMAC;
2690
9d5c8243
AK		 2691 set_bit(__IGB_DOWN, &adapter->state);
2692 return 0;
2693}
2694
2695/**
2696 * igb_open - Called when a network interface is made active
2697 * @netdev: network interface device structure
2698 *
2699 * Returns 0 on success, negative value on failure
2700 *
2701 * The open entry point is called when a network interface is made
2702 * active by the system (IFF_UP). At this point all resources needed
2703 * for transmit and receive operations are allocated, the interrupt
2704 * handler is registered with the OS, the watchdog timer is started,
2705 * and the stack is notified that the interface is ready.
2706 **/
749ab2cd 2707static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2708{
2709 struct igb_adapter *adapter = netdev_priv(netdev);
2710 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2711 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2712 int err;
2713 int i;
2714
2715 /* disallow open during test */
749ab2cd
YZ		 2716 if (test_bit(__IGB_TESTING, &adapter->state)) {
2717 WARN_ON(resuming);
9d5c8243 2718 return -EBUSY;
749ab2cd
YZ		 2719 }
2720
2721 if (!resuming)
2722 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2723
b168dfc5
JB		 2724 netif_carrier_off(netdev);
2725
9d5c8243
AK		 2726 /* allocate transmit descriptors */
2727 err = igb_setup_all_tx_resources(adapter);
2728 if (err)
2729 goto err_setup_tx;
2730
2731 /* allocate receive descriptors */
2732 err = igb_setup_all_rx_resources(adapter);
2733 if (err)
2734 goto err_setup_rx;
2735
88a268c1 2736 igb_power_up_link(adapter);
9d5c8243 2737
9d5c8243
AK		 2738 /* before we allocate an interrupt, we must be ready to handle it.
2739 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2740 * as soon as we call pci_request_irq, so we have to setup our
2741 * clean_rx handler before we do so. */
2742 igb_configure(adapter);
2743
2744 err = igb_request_irq(adapter);
2745 if (err)
2746 goto err_req_irq;
2747
0c2cc02e
AD		 2748 /* Notify the stack of the actual queue counts. */
2749 err = netif_set_real_num_tx_queues(adapter->netdev,
2750 adapter->num_tx_queues);
2751 if (err)
2752 goto err_set_queues;
2753
2754 err = netif_set_real_num_rx_queues(adapter->netdev,
2755 adapter->num_rx_queues);
2756 if (err)
2757 goto err_set_queues;
2758
9d5c8243
AK		 2759 /* From here on the code is the same as igb_up() */
2760 clear_bit(__IGB_DOWN, &adapter->state);
2761
0d1ae7f4
AD		 2762 for (i = 0; i < adapter->num_q_vectors; i++)
2763 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2764
2765 /* Clear any pending interrupts. */
2766 rd32(E1000_ICR);
844290e5
PW		 2767
2768 igb_irq_enable(adapter);
2769
d4960307
AD		 2770 /* notify VFs that reset has been completed */
2771 if (adapter->vfs_allocated_count) {
2772 u32 reg_data = rd32(E1000_CTRL_EXT);
2773 reg_data |= E1000_CTRL_EXT_PFRSTD;
2774 wr32(E1000_CTRL_EXT, reg_data);
2775 }
2776
d55b53ff
JK		 2777 netif_tx_start_all_queues(netdev);
2778
749ab2cd
YZ		 2779 if (!resuming)
2780 pm_runtime_put(&pdev->dev);
2781
25568a53
AD		 2782 /* start the watchdog. */
2783 hw->mac.get_link_status = 1;
2784 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2785
2786 return 0;
2787
0c2cc02e
AD		 2788err_set_queues:
2789 igb_free_irq(adapter);
9d5c8243
AK		 2790err_req_irq:
2791 igb_release_hw_control(adapter);
88a268c1 2792 igb_power_down_link(adapter);
9d5c8243
AK		 2793 igb_free_all_rx_resources(adapter);
2794err_setup_rx:
2795 igb_free_all_tx_resources(adapter);
2796err_setup_tx:
2797 igb_reset(adapter);
749ab2cd
YZ		 2798 if (!resuming)
2799 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2800
2801 return err;
2802}
2803
749ab2cd
YZ		 2804static int igb_open(struct net_device *netdev)
2805{
2806 return __igb_open(netdev, false);
2807}
2808
9d5c8243
AK		 2809/**
2810 * igb_close - Disables a network interface
2811 * @netdev: network interface device structure
2812 *
2813 * Returns 0, this is not allowed to fail
2814 *
2815 * The close entry point is called when an interface is de-activated
2816 * by the OS. The hardware is still under the driver's control, but
2817 * needs to be disabled. A global MAC reset is issued to stop the
2818 * hardware, and all transmit and receive resources are freed.
2819 **/
749ab2cd 2820static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2821{
2822 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2823 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2824
2825 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2826
749ab2cd
YZ		 2827 if (!suspending)
2828 pm_runtime_get_sync(&pdev->dev);
2829
2830 igb_down(adapter);
9d5c8243
AK		 2831 igb_free_irq(adapter);
2832
2833 igb_free_all_tx_resources(adapter);
2834 igb_free_all_rx_resources(adapter);
2835
749ab2cd
YZ		 2836 if (!suspending)
2837 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2838 return 0;
2839}
2840
749ab2cd
YZ		 2841static int igb_close(struct net_device *netdev)
2842{
2843 return __igb_close(netdev, false);
2844}
2845
9d5c8243
AK		 2846/**
2847 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2848 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2849 *
2850 * Return 0 on success, negative on failure
2851 **/
80785298 2852int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2853{
59d71989 2854 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2855 int size;
2856
06034649 2857 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2858
2859 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2860 if (!tx_ring->tx_buffer_info)
9d5c8243 2861 goto err;
9d5c8243
AK		 2862
2863 /* round up to nearest 4K */
85e8d004 2864 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2865 tx_ring->size = ALIGN(tx_ring->size, 4096);
2866
5536d210
AD		 2867 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2868 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2869 if (!tx_ring->desc)
2870 goto err;
2871
9d5c8243
AK		 2872 tx_ring->next_to_use = 0;
2873 tx_ring->next_to_clean = 0;
81c2fc22 2874
9d5c8243
AK		 2875 return 0;
2876
2877err:
06034649 2878 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2879 tx_ring->tx_buffer_info = NULL;
2880 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2881 return -ENOMEM;
2882}
2883
2884/**
2885 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2886 * (Descriptors) for all queues
2887 * @adapter: board private structure
2888 *
2889 * Return 0 on success, negative on failure
2890 **/
2891static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2892{
439705e1 2893 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2894 int i, err = 0;
2895
2896 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2897 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2898 if (err) {
439705e1 2899 dev_err(&pdev->dev,
9d5c8243
AK		 2900 "Allocation for Tx Queue %u failed\n", i);
2901 for (i--; i >= 0; i--)
3025a446 2902 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2903 break;
2904 }
2905 }
2906
2907 return err;
2908}
2909
2910/**
85b430b4
AD		 2911 * igb_setup_tctl - configure the transmit control registers
2912 * @adapter: Board private structure
9d5c8243 2913 **/
d7ee5b3a 2914void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2915{
9d5c8243
AK		 2916 struct e1000_hw *hw = &adapter->hw;
2917 u32 tctl;
9d5c8243 2918
85b430b4
AD		 2919 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2920 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2921
2922 /* Program the Transmit Control Register */
9d5c8243
AK		 2923 tctl = rd32(E1000_TCTL);
2924 tctl &= ~E1000_TCTL_CT;
2925 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2926 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2927
2928 igb_config_collision_dist(hw);
2929
9d5c8243
AK		 2930 /* Enable transmits */
2931 tctl |= E1000_TCTL_EN;
2932
2933 wr32(E1000_TCTL, tctl);
2934}
2935
85b430b4
AD		 2936/**
2937 * igb_configure_tx_ring - Configure transmit ring after Reset
2938 * @adapter: board private structure
2939 * @ring: tx ring to configure
2940 *
2941 * Configure a transmit ring after a reset.
2942 **/
d7ee5b3a
AD		 2943void igb_configure_tx_ring(struct igb_adapter *adapter,
2944 struct igb_ring *ring)
85b430b4
AD		 2945{
2946 struct e1000_hw *hw = &adapter->hw;
a74420e0 2947 u32 txdctl = 0;
85b430b4
AD		 2948 u64 tdba = ring->dma;
2949 int reg_idx = ring->reg_idx;
2950
2951 /* disable the queue */
a74420e0 2952 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2953 wrfl();
2954 mdelay(10);
2955
2956 wr32(E1000_TDLEN(reg_idx),
2957 ring->count * sizeof(union e1000_adv_tx_desc));
2958 wr32(E1000_TDBAL(reg_idx),
2959 tdba & 0x00000000ffffffffULL);
2960 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2961
fce99e34 2962 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2963 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2964 writel(0, ring->tail);
85b430b4
AD		 2965
2966 txdctl |= IGB_TX_PTHRESH;
2967 txdctl |= IGB_TX_HTHRESH << 8;
2968 txdctl |= IGB_TX_WTHRESH << 16;
2969
2970 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2971 wr32(E1000_TXDCTL(reg_idx), txdctl);
2972}
2973
2974/**
2975 * igb_configure_tx - Configure transmit Unit after Reset
2976 * @adapter: board private structure
2977 *
2978 * Configure the Tx unit of the MAC after a reset.
2979 **/
2980static void igb_configure_tx(struct igb_adapter *adapter)
2981{
2982 int i;
2983
2984 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2985 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2986}
2987
9d5c8243
AK		 2988/**
2989 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2990 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2991 *
2992 * Returns 0 on success, negative on failure
2993 **/
80785298 2994int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2995{
59d71989 2996 struct device *dev = rx_ring->dev;
f33005a6 2997 int size;
9d5c8243 2998
06034649 2999 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3000
3001 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3002 if (!rx_ring->rx_buffer_info)
9d5c8243 3003 goto err;
9d5c8243 3004
9d5c8243 3005 /* Round up to nearest 4K */
f33005a6 3006 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3007 rx_ring->size = ALIGN(rx_ring->size, 4096);
3008
5536d210
AD		 3009 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3010 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3011 if (!rx_ring->desc)
3012 goto err;
3013
cbc8e55f 3014 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3015 rx_ring->next_to_clean = 0;
3016 rx_ring->next_to_use = 0;
9d5c8243 3017
9d5c8243
AK		 3018 return 0;
3019
3020err:
06034649
AD		 3021 vfree(rx_ring->rx_buffer_info);
3022 rx_ring->rx_buffer_info = NULL;
f33005a6 3023 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3024 return -ENOMEM;
3025}
3026
3027/**
3028 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3029 * (Descriptors) for all queues
3030 * @adapter: board private structure
3031 *
3032 * Return 0 on success, negative on failure
3033 **/
3034static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3035{
439705e1 3036 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3037 int i, err = 0;
3038
3039 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3040 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3041 if (err) {
439705e1 3042 dev_err(&pdev->dev,
9d5c8243
AK		 3043 "Allocation for Rx Queue %u failed\n", i);
3044 for (i--; i >= 0; i--)
3025a446 3045 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3046 break;
3047 }
3048 }
3049
3050 return err;
3051}
3052
06cf2666
AD		 3053/**
3054 * igb_setup_mrqc - configure the multiple receive queue control registers
3055 * @adapter: Board private structure
3056 **/
3057static void igb_setup_mrqc(struct igb_adapter *adapter)
3058{
3059 struct e1000_hw *hw = &adapter->hw;
3060 u32 mrqc, rxcsum;
797fd4be 3061 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3062 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3063 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3064 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3065 0xFA01ACBE };
06cf2666
AD		 3066
3067 /* Fill out hash function seeds */
a57fe23e
AD		 3068 for (j = 0; j < 10; j++)
3069 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3070
a99955fc 3071 num_rx_queues = adapter->rss_queues;
06cf2666 3072
797fd4be
AD		 3073 switch (hw->mac.type) {
3074 case e1000_82575:
3075 shift = 6;
3076 break;
3077 case e1000_82576:
3078 /* 82576 supports 2 RSS queues for SR-IOV */
3079 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3080 shift = 3;
3081 num_rx_queues = 2;
06cf2666 3082 }
797fd4be
AD		 3083 break;
3084 default:
3085 break;
06cf2666
AD		 3086 }
3087
797fd4be
AD		 3088 /*
3089 * Populate the indirection table 4 entries at a time. To do this
3090 * we are generating the results for n and n+2 and then interleaving
3091 * those with the results with n+1 and n+3.
3092 */
3093 for (j = 0; j < 32; j++) {
3094 /* first pass generates n and n+2 */
3095 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3096 u32 reta = (base & 0x07800780) >> (7 - shift);
3097
3098 /* second pass generates n+1 and n+3 */
3099 base += 0x00010001 * num_rx_queues;
3100 reta |= (base & 0x07800780) << (1 + shift);
3101
3102 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3103 }
3104
3105 /*
3106 * Disable raw packet checksumming so that RSS hash is placed in
3107 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3108 * offloads as they are enabled by default
3109 */
3110 rxcsum = rd32(E1000_RXCSUM);
3111 rxcsum |= E1000_RXCSUM_PCSD;
3112
3113 if (adapter->hw.mac.type >= e1000_82576)
3114 /* Enable Receive Checksum Offload for SCTP */
3115 rxcsum |= E1000_RXCSUM_CRCOFL;
3116
3117 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3118 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3119
039454a8
AA		 3120 /* Generate RSS hash based on packet types, TCP/UDP
3121 * port numbers and/or IPv4/v6 src and dst addresses
3122 */
f96a8a0b
CW		 3123 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3124 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3125 E1000_MRQC_RSS_FIELD_IPV6 |
3126 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3127 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3128
039454a8
AA		 3129 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3130 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3131 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3132 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3133
06cf2666
AD		 3134 /* If VMDq is enabled then we set the appropriate mode for that, else
3135 * we default to RSS so that an RSS hash is calculated per packet even
3136 * if we are only using one queue */
3137 if (adapter->vfs_allocated_count) {
3138 if (hw->mac.type > e1000_82575) {
3139 /* Set the default pool for the PF's first queue */
3140 u32 vtctl = rd32(E1000_VT_CTL);
3141 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3142 E1000_VT_CTL_DISABLE_DEF_POOL);
3143 vtctl |= adapter->vfs_allocated_count <<
3144 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3145 wr32(E1000_VT_CTL, vtctl);
3146 }
a99955fc 3147 if (adapter->rss_queues > 1)
f96a8a0b 3148 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3149 else
f96a8a0b 3150 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3151 } else {
f96a8a0b
CW		 3152 if (hw->mac.type != e1000_i211)
3153 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3154 }
3155 igb_vmm_control(adapter);
3156
06cf2666
AD		 3157 wr32(E1000_MRQC, mrqc);
3158}
3159
9d5c8243
AK		 3160/**
3161 * igb_setup_rctl - configure the receive control registers
3162 * @adapter: Board private structure
3163 **/
d7ee5b3a 3164void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3165{
3166 struct e1000_hw *hw = &adapter->hw;
3167 u32 rctl;
9d5c8243
AK		 3168
3169 rctl = rd32(E1000_RCTL);
3170
3171 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3172 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3173
69d728ba 3174 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3175 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3176
87cb7e8c
AK		 3177 /*
3178 * enable stripping of CRC. It's unlikely this will break BMC
3179 * redirection as it did with e1000. Newer features require
3180 * that the HW strips the CRC.
73cd78f1 3181 */
87cb7e8c 3182 rctl |= E1000_RCTL_SECRC;
9d5c8243 3183
559e9c49 3184 /* disable store bad packets and clear size bits. */
ec54d7d6 3185 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3186
6ec43fe6
AD		 3187 /* enable LPE to prevent packets larger than max_frame_size */
3188 rctl |= E1000_RCTL_LPE;
9d5c8243 3189
952f72a8
AD		 3190 /* disable queue 0 to prevent tail write w/o re-config */
3191 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3192
e1739522
AD		 3193 /* Attention!!! For SR-IOV PF driver operations you must enable
3194 * queue drop for all VF and PF queues to prevent head of line blocking
3195 * if an un-trusted VF does not provide descriptors to hardware.
3196 */
3197 if (adapter->vfs_allocated_count) {
e1739522
AD		 3198 /* set all queue drop enable bits */
3199 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3200 }
3201
89eaefb6
BG		 3202 /* This is useful for sniffing bad packets. */
3203 if (adapter->netdev->features & NETIF_F_RXALL) {
3204 /* UPE and MPE will be handled by normal PROMISC logic
3205 * in e1000e_set_rx_mode */
3206 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3207 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3208 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3209
3210 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3211 E1000_RCTL_DPF | /* Allow filtered pause */
3212 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3213 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3214 * and that breaks VLANs.
3215 */
3216 }
3217
9d5c8243
AK		 3218 wr32(E1000_RCTL, rctl);
3219}
3220
7d5753f0
AD		 3221static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3222 int vfn)
3223{
3224 struct e1000_hw *hw = &adapter->hw;
3225 u32 vmolr;
3226
3227 /* if it isn't the PF check to see if VFs are enabled and
3228 * increase the size to support vlan tags */
3229 if (vfn < adapter->vfs_allocated_count &&
3230 adapter->vf_data[vfn].vlans_enabled)
3231 size += VLAN_TAG_SIZE;
3232
3233 vmolr = rd32(E1000_VMOLR(vfn));
3234 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3235 vmolr |= size | E1000_VMOLR_LPE;
3236 wr32(E1000_VMOLR(vfn), vmolr);
3237
3238 return 0;
3239}
3240
e1739522
AD		 3241/**
3242 * igb_rlpml_set - set maximum receive packet size
3243 * @adapter: board private structure
3244 *
3245 * Configure maximum receivable packet size.
3246 **/
3247static void igb_rlpml_set(struct igb_adapter *adapter)
3248{
153285f9 3249 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3250 struct e1000_hw *hw = &adapter->hw;
3251 u16 pf_id = adapter->vfs_allocated_count;
3252
e1739522
AD		 3253 if (pf_id) {
3254 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3255 /*
3256 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3257 * to our max jumbo frame size, in case we need to enable
3258 * jumbo frames on one of the rings later.
3259 * This will not pass over-length frames into the default
3260 * queue because it's gated by the VMOLR.RLPML.
3261 */
7d5753f0 3262 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3263 }
3264
3265 wr32(E1000_RLPML, max_frame_size);
3266}
3267
8151d294
WM		 3268static inline void igb_set_vmolr(struct igb_adapter *adapter,
3269 int vfn, bool aupe)
7d5753f0
AD		 3270{
3271 struct e1000_hw *hw = &adapter->hw;
3272 u32 vmolr;
3273
3274 /*
3275 * This register exists only on 82576 and newer so if we are older then
3276 * we should exit and do nothing
3277 */
3278 if (hw->mac.type < e1000_82576)
3279 return;
3280
3281 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3282 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3283 if (aupe)
3284 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3285 else
3286 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3287
3288 /* clear all bits that might not be set */
3289 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3290
a99955fc 3291 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3292 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3293 /*
3294 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3295 * multicast packets
3296 */
3297 if (vfn <= adapter->vfs_allocated_count)
3298 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3299
3300 wr32(E1000_VMOLR(vfn), vmolr);
3301}
3302
85b430b4
AD		 3303/**
3304 * igb_configure_rx_ring - Configure a receive ring after Reset
3305 * @adapter: board private structure
3306 * @ring: receive ring to be configured
3307 *
3308 * Configure the Rx unit of the MAC after a reset.
3309 **/
d7ee5b3a
AD		 3310void igb_configure_rx_ring(struct igb_adapter *adapter,
3311 struct igb_ring *ring)
85b430b4
AD		 3312{
3313 struct e1000_hw *hw = &adapter->hw;
3314 u64 rdba = ring->dma;
3315 int reg_idx = ring->reg_idx;
a74420e0 3316 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3317
3318 /* disable the queue */
a74420e0 3319 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3320
3321 /* Set DMA base address registers */
3322 wr32(E1000_RDBAL(reg_idx),
3323 rdba & 0x00000000ffffffffULL);
3324 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3325 wr32(E1000_RDLEN(reg_idx),
3326 ring->count * sizeof(union e1000_adv_rx_desc));
3327
3328 /* initialize head and tail */
fce99e34 3329 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3330 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3331 writel(0, ring->tail);
85b430b4 3332
952f72a8 3333 /* set descriptor configuration */
44390ca6 3334 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3335 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3336 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3337 if (hw->mac.type >= e1000_82580)
757b77e2 3338 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3339 /* Only set Drop Enable if we are supporting multiple queues */
3340 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3341 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3342
3343 wr32(E1000_SRRCTL(reg_idx), srrctl);
3344
7d5753f0 3345 /* set filtering for VMDQ pools */
8151d294 3346 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3347
85b430b4
AD		 3348 rxdctl |= IGB_RX_PTHRESH;
3349 rxdctl |= IGB_RX_HTHRESH << 8;
3350 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3351
3352 /* enable receive descriptor fetching */
3353 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3354 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3355}
3356
74e238ea
AD		 3357static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
3358 struct igb_ring *rx_ring)
3359{
3360#define IGB_MAX_BUILD_SKB_SIZE \
3361 (SKB_WITH_OVERHEAD(IGB_RX_BUFSZ) - \
3362 (NET_SKB_PAD + NET_IP_ALIGN + IGB_TS_HDR_LEN))
3363
3364 /* set build_skb flag */
3365 if (adapter->max_frame_size <= IGB_MAX_BUILD_SKB_SIZE)
3366 set_ring_build_skb_enabled(rx_ring);
3367 else
3368 clear_ring_build_skb_enabled(rx_ring);
3369}
3370
9d5c8243
AK		 3371/**
3372 * igb_configure_rx - Configure receive Unit after Reset
3373 * @adapter: board private structure
3374 *
3375 * Configure the Rx unit of the MAC after a reset.
3376 **/
3377static void igb_configure_rx(struct igb_adapter *adapter)
3378{
9107584e 3379 int i;
9d5c8243 3380
68d480c4
AD		 3381 /* set UTA to appropriate mode */
3382 igb_set_uta(adapter);
3383
26ad9178
AD		 3384 /* set the correct pool for the PF default MAC address in entry 0 */
3385 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3386 adapter->vfs_allocated_count);
3387
06cf2666
AD		 3388 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3389 * the Base and Length of the Rx Descriptor Ring */
74e238ea
AD		 3390 for (i = 0; i < adapter->num_rx_queues; i++) {
3391 struct igb_ring *rx_ring = adapter->rx_ring[i];
3392 igb_set_rx_buffer_len(adapter, rx_ring);
3393 igb_configure_rx_ring(adapter, rx_ring);
3394 }
9d5c8243
AK		 3395}
3396
3397/**
3398 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3399 * @tx_ring: Tx descriptor ring for a specific queue
3400 *
3401 * Free all transmit software resources
3402 **/
68fd9910 3403void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3404{
3b644cf6 3405 igb_clean_tx_ring(tx_ring);
9d5c8243 3406
06034649
AD		 3407 vfree(tx_ring->tx_buffer_info);
3408 tx_ring->tx_buffer_info = NULL;
9d5c8243 3409
439705e1
AD		 3410 /* if not set, then don't free */
3411 if (!tx_ring->desc)
3412 return;
3413
59d71989
AD		 3414 dma_free_coherent(tx_ring->dev, tx_ring->size,
3415 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3416
3417 tx_ring->desc = NULL;
3418}
3419
3420/**
3421 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3422 * @adapter: board private structure
3423 *
3424 * Free all transmit software resources
3425 **/
3426static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3427{
3428 int i;
3429
3430 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3431 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3432}
3433
ebe42d16
AD		 3434void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3435 struct igb_tx_buffer *tx_buffer)
3436{
3437 if (tx_buffer->skb) {
3438 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3439 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3440 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3441 dma_unmap_addr(tx_buffer, dma),
3442 dma_unmap_len(tx_buffer, len),
ebe42d16 3443 DMA_TO_DEVICE);
c9f14bf3 3444 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3445 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3446 dma_unmap_addr(tx_buffer, dma),
3447 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3448 DMA_TO_DEVICE);
3449 }
3450 tx_buffer->next_to_watch = NULL;
3451 tx_buffer->skb = NULL;
c9f14bf3 3452 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3453 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3454}
3455
3456/**
3457 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3458 * @tx_ring: ring to be cleaned
3459 **/
3b644cf6 3460static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3461{
06034649 3462 struct igb_tx_buffer *buffer_info;
9d5c8243 3463 unsigned long size;
6ad4edfc 3464 u16 i;
9d5c8243 3465
06034649 3466 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3467 return;
3468 /* Free all the Tx ring sk_buffs */
3469
3470 for (i = 0; i < tx_ring->count; i++) {
06034649 3471 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3472 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3473 }
3474
dad8a3b3
JF		 3475 netdev_tx_reset_queue(txring_txq(tx_ring));
3476
06034649
AD		 3477 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3478 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3479
3480 /* Zero out the descriptor ring */
9d5c8243
AK		 3481 memset(tx_ring->desc, 0, tx_ring->size);
3482
3483 tx_ring->next_to_use = 0;
3484 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3485}
3486
3487/**
3488 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3489 * @adapter: board private structure
3490 **/
3491static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3492{
3493 int i;
3494
3495 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3496 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3497}
3498
3499/**
3500 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3501 * @rx_ring: ring to clean the resources from
3502 *
3503 * Free all receive software resources
3504 **/
68fd9910 3505void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3506{
3b644cf6 3507 igb_clean_rx_ring(rx_ring);
9d5c8243 3508
06034649
AD		 3509 vfree(rx_ring->rx_buffer_info);
3510 rx_ring->rx_buffer_info = NULL;
9d5c8243 3511
439705e1
AD		 3512 /* if not set, then don't free */
3513 if (!rx_ring->desc)
3514 return;
3515
59d71989
AD		 3516 dma_free_coherent(rx_ring->dev, rx_ring->size,
3517 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3518
3519 rx_ring->desc = NULL;
3520}
3521
3522/**
3523 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3524 * @adapter: board private structure
3525 *
3526 * Free all receive software resources
3527 **/
3528static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3529{
3530 int i;
3531
3532 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3533 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3534}
3535
3536/**
3537 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3538 * @rx_ring: ring to free buffers from
3539 **/
3b644cf6 3540static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3541{
9d5c8243 3542 unsigned long size;
c023cd88 3543 u16 i;
9d5c8243 3544
1a1c225b
AD		 3545 if (rx_ring->skb)
3546 dev_kfree_skb(rx_ring->skb);
3547 rx_ring->skb = NULL;
3548
06034649 3549 if (!rx_ring->rx_buffer_info)
9d5c8243 3550 return;
439705e1 3551
9d5c8243
AK		 3552 /* Free all the Rx ring sk_buffs */
3553 for (i = 0; i < rx_ring->count; i++) {
06034649 3554 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3555
cbc8e55f
AD		 3556 if (!buffer_info->page)
3557 continue;
3558
3559 dma_unmap_page(rx_ring->dev,
3560 buffer_info->dma,
3561 PAGE_SIZE,
3562 DMA_FROM_DEVICE);
3563 __free_page(buffer_info->page);
3564
1a1c225b 3565 buffer_info->page = NULL;
9d5c8243
AK		 3566 }
3567
06034649
AD		 3568 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3569 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3570
3571 /* Zero out the descriptor ring */
3572 memset(rx_ring->desc, 0, rx_ring->size);
3573
cbc8e55f 3574 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3575 rx_ring->next_to_clean = 0;
3576 rx_ring->next_to_use = 0;
9d5c8243
AK		 3577}
3578
3579/**
3580 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3581 * @adapter: board private structure
3582 **/
3583static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3584{
3585 int i;
3586
3587 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3588 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3589}
3590
3591/**
3592 * igb_set_mac - Change the Ethernet Address of the NIC
3593 * @netdev: network interface device structure
3594 * @p: pointer to an address structure
3595 *
3596 * Returns 0 on success, negative on failure
3597 **/
3598static int igb_set_mac(struct net_device *netdev, void *p)
3599{
3600 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3601 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3602 struct sockaddr *addr = p;
3603
3604 if (!is_valid_ether_addr(addr->sa_data))
3605 return -EADDRNOTAVAIL;
3606
3607 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3608 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3609
26ad9178
AD		 3610 /* set the correct pool for the new PF MAC address in entry 0 */
3611 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3612 adapter->vfs_allocated_count);
e1739522 3613
9d5c8243
AK		 3614 return 0;
3615}
3616
3617/**
68d480c4 3618 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3619 * @netdev: network interface device structure
3620 *
68d480c4
AD		 3621 * Writes multicast address list to the MTA hash table.
3622 * Returns: -ENOMEM on failure
3623 * 0 on no addresses written
3624 * X on writing X addresses to MTA
9d5c8243 3625 **/
68d480c4 3626static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3627{
3628 struct igb_adapter *adapter = netdev_priv(netdev);
3629 struct e1000_hw *hw = &adapter->hw;
22bedad3 3630 struct netdev_hw_addr *ha;
68d480c4 3631 u8 *mta_list;
9d5c8243
AK		 3632 int i;
3633
4cd24eaf 3634 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3635 /* nothing to program, so clear mc list */
3636 igb_update_mc_addr_list(hw, NULL, 0);
3637 igb_restore_vf_multicasts(adapter);
3638 return 0;
3639 }
9d5c8243 3640
4cd24eaf 3641 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3642 if (!mta_list)
3643 return -ENOMEM;
ff41f8dc 3644
68d480c4 3645 /* The shared function expects a packed array of only addresses. */
48e2f183 3646 i = 0;
22bedad3
JP		 3647 netdev_for_each_mc_addr(ha, netdev)
3648 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3649
68d480c4
AD		 3650 igb_update_mc_addr_list(hw, mta_list, i);
3651 kfree(mta_list);
3652
4cd24eaf 3653 return netdev_mc_count(netdev);
68d480c4
AD		 3654}
3655
3656/**
3657 * igb_write_uc_addr_list - write unicast addresses to RAR table
3658 * @netdev: network interface device structure
3659 *
3660 * Writes unicast address list to the RAR table.
3661 * Returns: -ENOMEM on failure/insufficient address space
3662 * 0 on no addresses written
3663 * X on writing X addresses to the RAR table
3664 **/
3665static int igb_write_uc_addr_list(struct net_device *netdev)
3666{
3667 struct igb_adapter *adapter = netdev_priv(netdev);
3668 struct e1000_hw *hw = &adapter->hw;
3669 unsigned int vfn = adapter->vfs_allocated_count;
3670 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3671 int count = 0;
3672
3673 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3674 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3675 return -ENOMEM;
9d5c8243 3676
32e7bfc4 3677 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3678 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3679
3680 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3681 if (!rar_entries)
3682 break;
26ad9178
AD		 3683 igb_rar_set_qsel(adapter, ha->addr,
3684 rar_entries--,
68d480c4
AD		 3685 vfn);
3686 count++;
ff41f8dc
AD		 3687 }
3688 }
3689 /* write the addresses in reverse order to avoid write combining */
3690 for (; rar_entries > 0 ; rar_entries--) {
3691 wr32(E1000_RAH(rar_entries), 0);
3692 wr32(E1000_RAL(rar_entries), 0);
3693 }
3694 wrfl();
3695
68d480c4
AD		 3696 return count;
3697}
3698
3699/**
3700 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3701 * @netdev: network interface device structure
3702 *
3703 * The set_rx_mode entry point is called whenever the unicast or multicast
3704 * address lists or the network interface flags are updated. This routine is
3705 * responsible for configuring the hardware for proper unicast, multicast,
3706 * promiscuous mode, and all-multi behavior.
3707 **/
3708static void igb_set_rx_mode(struct net_device *netdev)
3709{
3710 struct igb_adapter *adapter = netdev_priv(netdev);
3711 struct e1000_hw *hw = &adapter->hw;
3712 unsigned int vfn = adapter->vfs_allocated_count;
3713 u32 rctl, vmolr = 0;
3714 int count;
3715
3716 /* Check for Promiscuous and All Multicast modes */
3717 rctl = rd32(E1000_RCTL);
3718
3719 /* clear the effected bits */
3720 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3721
3722 if (netdev->flags & IFF_PROMISC) {
3723 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3724 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3725 } else {
3726 if (netdev->flags & IFF_ALLMULTI) {
3727 rctl |= E1000_RCTL_MPE;
3728 vmolr |= E1000_VMOLR_MPME;
3729 } else {
3730 /*
3731 * Write addresses to the MTA, if the attempt fails
25985edc 3732 * then we should just turn on promiscuous mode so
68d480c4
AD		 3733 * that we can at least receive multicast traffic
3734 */
3735 count = igb_write_mc_addr_list(netdev);
3736 if (count < 0) {
3737 rctl |= E1000_RCTL_MPE;
3738 vmolr |= E1000_VMOLR_MPME;
3739 } else if (count) {
3740 vmolr |= E1000_VMOLR_ROMPE;
3741 }
3742 }
3743 /*
3744 * Write addresses to available RAR registers, if there is not
3745 * sufficient space to store all the addresses then enable
25985edc 3746 * unicast promiscuous mode
68d480c4
AD		 3747 */
3748 count = igb_write_uc_addr_list(netdev);
3749 if (count < 0) {
3750 rctl |= E1000_RCTL_UPE;
3751 vmolr |= E1000_VMOLR_ROPE;
3752 }
3753 rctl |= E1000_RCTL_VFE;
28fc06f5 3754 }
68d480c4 3755 wr32(E1000_RCTL, rctl);
28fc06f5 3756
68d480c4
AD		 3757 /*
3758 * In order to support SR-IOV and eventually VMDq it is necessary to set
3759 * the VMOLR to enable the appropriate modes. Without this workaround
3760 * we will have issues with VLAN tag stripping not being done for frames
3761 * that are only arriving because we are the default pool
3762 */
f96a8a0b 3763 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3764 return;
9d5c8243 3765
68d480c4
AD		 3766 vmolr |= rd32(E1000_VMOLR(vfn)) &
3767 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3768 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3769 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3770}
3771
13800469
GR		 3772static void igb_check_wvbr(struct igb_adapter *adapter)
3773{
3774 struct e1000_hw *hw = &adapter->hw;
3775 u32 wvbr = 0;
3776
3777 switch (hw->mac.type) {
3778 case e1000_82576:
3779 case e1000_i350:
3780 if (!(wvbr = rd32(E1000_WVBR)))
3781 return;
3782 break;
3783 default:
3784 break;
3785 }
3786
3787 adapter->wvbr |= wvbr;
3788}
3789
3790#define IGB_STAGGERED_QUEUE_OFFSET 8
3791
3792static void igb_spoof_check(struct igb_adapter *adapter)
3793{
3794 int j;
3795
3796 if (!adapter->wvbr)
3797 return;
3798
3799 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3800 if (adapter->wvbr & (1 << j) ||
3801 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3802 dev_warn(&adapter->pdev->dev,
3803 "Spoof event(s) detected on VF %d\n", j);
3804 adapter->wvbr &=
3805 ~((1 << j) |
3806 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3807 }
3808 }
3809}
3810
9d5c8243
AK		 3811/* Need to wait a few seconds after link up to get diagnostic information from
3812 * the phy */
3813static void igb_update_phy_info(unsigned long data)
3814{
3815 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3816 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3817}
3818
4d6b725e
AD		 3819/**
3820 * igb_has_link - check shared code for link and determine up/down
3821 * @adapter: pointer to driver private info
3822 **/
3145535a 3823bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3824{
3825 struct e1000_hw *hw = &adapter->hw;
3826 bool link_active = false;
3827 s32 ret_val = 0;
3828
3829 /* get_link_status is set on LSC (link status) interrupt or
3830 * rx sequence error interrupt. get_link_status will stay
3831 * false until the e1000_check_for_link establishes link
3832 * for copper adapters ONLY
3833 */
3834 switch (hw->phy.media_type) {
3835 case e1000_media_type_copper:
3836 if (hw->mac.get_link_status) {
3837 ret_val = hw->mac.ops.check_for_link(hw);
3838 link_active = !hw->mac.get_link_status;
3839 } else {
3840 link_active = true;
3841 }
3842 break;
4d6b725e
AD		 3843 case e1000_media_type_internal_serdes:
3844 ret_val = hw->mac.ops.check_for_link(hw);
3845 link_active = hw->mac.serdes_has_link;
3846 break;
3847 default:
3848 case e1000_media_type_unknown:
3849 break;
3850 }
3851
3852 return link_active;
3853}
3854
563988dc
SA		 3855static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3856{
3857 bool ret = false;
3858 u32 ctrl_ext, thstat;
3859
f96a8a0b 3860 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3861 if (hw->mac.type == e1000_i350) {
3862 thstat = rd32(E1000_THSTAT);
3863 ctrl_ext = rd32(E1000_CTRL_EXT);
3864
3865 if ((hw->phy.media_type == e1000_media_type_copper) &&
3866 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3867 ret = !!(thstat & event);
3868 }
3869 }
3870
3871 return ret;
3872}
3873
9d5c8243
AK		 3874/**
3875 * igb_watchdog - Timer Call-back
3876 * @data: pointer to adapter cast into an unsigned long
3877 **/
3878static void igb_watchdog(unsigned long data)
3879{
3880 struct igb_adapter *adapter = (struct igb_adapter *)data;
3881 /* Do the rest outside of interrupt context */
3882 schedule_work(&adapter->watchdog_task);
3883}
3884
3885static void igb_watchdog_task(struct work_struct *work)
3886{
3887 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3888 struct igb_adapter,
3889 watchdog_task);
9d5c8243 3890 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3891 struct net_device *netdev = adapter->netdev;
563988dc 3892 u32 link;
7a6ea550 3893 int i;
9d5c8243 3894
4d6b725e 3895 link = igb_has_link(adapter);
9d5c8243 3896 if (link) {
749ab2cd
YZ		 3897 /* Cancel scheduled suspend requests. */
3898 pm_runtime_resume(netdev->dev.parent);
3899
9d5c8243
AK		 3900 if (!netif_carrier_ok(netdev)) {
3901 u32 ctrl;
330a6d6a
AD		 3902 hw->mac.ops.get_speed_and_duplex(hw,
3903 &adapter->link_speed,
3904 &adapter->link_duplex);
9d5c8243
AK		 3905
3906 ctrl = rd32(E1000_CTRL);
527d47c1 3907 /* Links status message must follow this format */
876d2d6f
JK		 3908 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3909 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3910 netdev->name,
3911 adapter->link_speed,
3912 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3913 "Full" : "Half",
3914 (ctrl & E1000_CTRL_TFCE) &&
3915 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3916 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3917 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3918
563988dc 3919 /* check for thermal sensor event */
876d2d6f
JK		 3920 if (igb_thermal_sensor_event(hw,
3921 E1000_THSTAT_LINK_THROTTLE)) {
3922 netdev_info(netdev, "The network adapter link "
3923 "speed was downshifted because it "
3924 "overheated\n");
7ef5ed1c 3925 }
563988dc 3926
d07f3e37 3927 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3928 adapter->tx_timeout_factor = 1;
3929 switch (adapter->link_speed) {
3930 case SPEED_10:
9d5c8243
AK		 3931 adapter->tx_timeout_factor = 14;
3932 break;
3933 case SPEED_100:
9d5c8243
AK		 3934 /* maybe add some timeout factor ? */
3935 break;
3936 }
3937
3938 netif_carrier_on(netdev);
9d5c8243 3939
4ae196df 3940 igb_ping_all_vfs(adapter);
17dc566c 3941 igb_check_vf_rate_limit(adapter);
4ae196df 3942
4b1a9877 3943 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3944 if (!test_bit(__IGB_DOWN, &adapter->state))
3945 mod_timer(&adapter->phy_info_timer,
3946 round_jiffies(jiffies + 2 * HZ));
3947 }
3948 } else {
3949 if (netif_carrier_ok(netdev)) {
3950 adapter->link_speed = 0;
3951 adapter->link_duplex = 0;
563988dc
SA		 3952
3953 /* check for thermal sensor event */
876d2d6f
JK		 3954 if (igb_thermal_sensor_event(hw,
3955 E1000_THSTAT_PWR_DOWN)) {
3956 netdev_err(netdev, "The network adapter was "
3957 "stopped because it overheated\n");
7ef5ed1c 3958 }
563988dc 3959
527d47c1
AD		 3960 /* Links status message must follow this format */
3961 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3962 netdev->name);
9d5c8243 3963 netif_carrier_off(netdev);
4b1a9877 3964
4ae196df
AD		 3965 igb_ping_all_vfs(adapter);
3966
4b1a9877 3967 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3968 if (!test_bit(__IGB_DOWN, &adapter->state))
3969 mod_timer(&adapter->phy_info_timer,
3970 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3971
3972 pm_schedule_suspend(netdev->dev.parent,
3973 MSEC_PER_SEC * 5);
9d5c8243
AK		 3974 }
3975 }
3976
12dcd86b
ED		 3977 spin_lock(&adapter->stats64_lock);
3978 igb_update_stats(adapter, &adapter->stats64);
3979 spin_unlock(&adapter->stats64_lock);
9d5c8243 3980
dbabb065 3981 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3982 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3983 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3984 /* We've lost link, so the controller stops DMA,
3985 * but we've got queued Tx work that's never going
3986 * to get done, so reset controller to flush Tx.
3987 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3988 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3989 adapter->tx_timeout_count++;
3990 schedule_work(&adapter->reset_task);
3991 /* return immediately since reset is imminent */
3992 return;
3993 }
9d5c8243 3994 }
9d5c8243 3995
dbabb065 3996 /* Force detection of hung controller every watchdog period */
6d095fa8 3997 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3998 }
f7ba205e 3999
9d5c8243 4000 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 4001 if (adapter->msix_entries) {
047e0030 4002 u32 eics = 0;
0d1ae7f4
AD		 4003 for (i = 0; i < adapter->num_q_vectors; i++)
4004 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4005 wr32(E1000_EICS, eics);
4006 } else {
4007 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4008 }
9d5c8243 4009
13800469 4010 igb_spoof_check(adapter);
fc580751 4011 igb_ptp_rx_hang(adapter);
13800469 4012
9d5c8243
AK		 4013 /* Reset the timer */
4014 if (!test_bit(__IGB_DOWN, &adapter->state))
4015 mod_timer(&adapter->watchdog_timer,
4016 round_jiffies(jiffies + 2 * HZ));
4017}
4018
4019enum latency_range {
4020 lowest_latency = 0,
4021 low_latency = 1,
4022 bulk_latency = 2,
4023 latency_invalid = 255
4024};
4025
6eb5a7f1
AD		 4026/**
4027 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4028 *
4029 * Stores a new ITR value based on strictly on packet size. This
4030 * algorithm is less sophisticated than that used in igb_update_itr,
4031 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 4032 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 4033 * were determined based on theoretical maximum wire speed and testing
4034 * data, in order to minimize response time while increasing bulk
4035 * throughput.
4036 * This functionality is controlled by the InterruptThrottleRate module
4037 * parameter (see igb_param.c)
4038 * NOTE: This function is called only when operating in a multiqueue
4039 * receive environment.
047e0030 4040 * @q_vector: pointer to q_vector
6eb5a7f1 4041 **/
047e0030 4042static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4043{
047e0030 4044 int new_val = q_vector->itr_val;
6eb5a7f1 4045 int avg_wire_size = 0;
047e0030 4046 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4047 unsigned int packets;
9d5c8243 4048
6eb5a7f1
AD		 4049 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4050 * ints/sec - ITR timer value of 120 ticks.
4051 */
4052 if (adapter->link_speed != SPEED_1000) {
0ba82994 4053 new_val = IGB_4K_ITR;
6eb5a7f1 4054 goto set_itr_val;
9d5c8243 4055 }
047e0030 4056
0ba82994
AD		 4057 packets = q_vector->rx.total_packets;
4058 if (packets)
4059 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4060
0ba82994
AD		 4061 packets = q_vector->tx.total_packets;
4062 if (packets)
4063 avg_wire_size = max_t(u32, avg_wire_size,
4064 q_vector->tx.total_bytes / packets);
047e0030
AD		 4065
4066 /* if avg_wire_size isn't set no work was done */
4067 if (!avg_wire_size)
4068 goto clear_counts;
9d5c8243 4069
6eb5a7f1
AD		 4070 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4071 avg_wire_size += 24;
4072
4073 /* Don't starve jumbo frames */
4074 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4075
6eb5a7f1
AD		 4076 /* Give a little boost to mid-size frames */
4077 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4078 new_val = avg_wire_size / 3;
4079 else
4080 new_val = avg_wire_size / 2;
9d5c8243 4081
0ba82994
AD		 4082 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4083 if (new_val < IGB_20K_ITR &&
4084 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4085 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4086 new_val = IGB_20K_ITR;
abe1c363 4087
6eb5a7f1 4088set_itr_val:
047e0030
AD		 4089 if (new_val != q_vector->itr_val) {
4090 q_vector->itr_val = new_val;
4091 q_vector->set_itr = 1;
9d5c8243 4092 }
6eb5a7f1 4093clear_counts:
0ba82994
AD		 4094 q_vector->rx.total_bytes = 0;
4095 q_vector->rx.total_packets = 0;
4096 q_vector->tx.total_bytes = 0;
4097 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4098}
4099
4100/**
4101 * igb_update_itr - update the dynamic ITR value based on statistics
4102 * Stores a new ITR value based on packets and byte
4103 * counts during the last interrupt. The advantage of per interrupt
4104 * computation is faster updates and more accurate ITR for the current
4105 * traffic pattern. Constants in this function were computed
4106 * based on theoretical maximum wire speed and thresholds were set based
4107 * on testing data as well as attempting to minimize response time
4108 * while increasing bulk throughput.
4109 * this functionality is controlled by the InterruptThrottleRate module
4110 * parameter (see igb_param.c)
4111 * NOTE: These calculations are only valid when operating in a single-
4112 * queue environment.
0ba82994
AD		 4113 * @q_vector: pointer to q_vector
4114 * @ring_container: ring info to update the itr for
9d5c8243 4115 **/
0ba82994
AD		 4116static void igb_update_itr(struct igb_q_vector *q_vector,
4117 struct igb_ring_container *ring_container)
9d5c8243 4118{
0ba82994
AD		 4119 unsigned int packets = ring_container->total_packets;
4120 unsigned int bytes = ring_container->total_bytes;
4121 u8 itrval = ring_container->itr;
9d5c8243 4122
0ba82994 4123 /* no packets, exit with status unchanged */
9d5c8243 4124 if (packets == 0)
0ba82994 4125 return;
9d5c8243 4126
0ba82994 4127 switch (itrval) {
9d5c8243
AK		 4128 case lowest_latency:
4129 /* handle TSO and jumbo frames */
4130 if (bytes/packets > 8000)
0ba82994 4131 itrval = bulk_latency;
9d5c8243 4132 else if ((packets < 5) && (bytes > 512))
0ba82994 4133 itrval = low_latency;
9d5c8243
AK		 4134 break;
4135 case low_latency: /* 50 usec aka 20000 ints/s */
4136 if (bytes > 10000) {
4137 /* this if handles the TSO accounting */
4138 if (bytes/packets > 8000) {
0ba82994 4139 itrval = bulk_latency;
9d5c8243 4140 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4141 itrval = bulk_latency;
9d5c8243 4142 } else if ((packets > 35)) {
0ba82994 4143 itrval = lowest_latency;
9d5c8243
AK		 4144 }
4145 } else if (bytes/packets > 2000) {
0ba82994 4146 itrval = bulk_latency;
9d5c8243 4147 } else if (packets <= 2 && bytes < 512) {
0ba82994 4148 itrval = lowest_latency;
9d5c8243
AK		 4149 }
4150 break;
4151 case bulk_latency: /* 250 usec aka 4000 ints/s */
4152 if (bytes > 25000) {
4153 if (packets > 35)
0ba82994 4154 itrval = low_latency;
1e5c3d21 4155 } else if (bytes < 1500) {
0ba82994 4156 itrval = low_latency;
9d5c8243
AK		 4157 }
4158 break;
4159 }
4160
0ba82994
AD		 4161 /* clear work counters since we have the values we need */
4162 ring_container->total_bytes = 0;
4163 ring_container->total_packets = 0;
4164
4165 /* write updated itr to ring container */
4166 ring_container->itr = itrval;
9d5c8243
AK		 4167}
4168
0ba82994 4169static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4170{
0ba82994 4171 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4172 u32 new_itr = q_vector->itr_val;
0ba82994 4173 u8 current_itr = 0;
9d5c8243
AK		 4174
4175 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4176 if (adapter->link_speed != SPEED_1000) {
4177 current_itr = 0;
0ba82994 4178 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4179 goto set_itr_now;
4180 }
4181
0ba82994
AD		 4182 igb_update_itr(q_vector, &q_vector->tx);
4183 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4184
0ba82994 4185 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4186
6eb5a7f1 4187 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4188 if (current_itr == lowest_latency &&
4189 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4190 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4191 current_itr = low_latency;
4192
9d5c8243
AK		 4193 switch (current_itr) {
4194 /* counts and packets in update_itr are dependent on these numbers */
4195 case lowest_latency:
0ba82994 4196 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4197 break;
4198 case low_latency:
0ba82994 4199 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4200 break;
4201 case bulk_latency:
0ba82994 4202 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4203 break;
4204 default:
4205 break;
4206 }
4207
4208set_itr_now:
047e0030 4209 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4210 /* this attempts to bias the interrupt rate towards Bulk
4211 * by adding intermediate steps when interrupt rate is
4212 * increasing */
047e0030
AD		 4213 new_itr = new_itr > q_vector->itr_val ?
4214 max((new_itr * q_vector->itr_val) /
4215 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 4216 new_itr) :
9d5c8243
AK		 4217 new_itr;
4218 /* Don't write the value here; it resets the adapter's
4219 * internal timer, and causes us to delay far longer than
4220 * we should between interrupts. Instead, we write the ITR
4221 * value at the beginning of the next interrupt so the timing
4222 * ends up being correct.
4223 */
047e0030
AD		 4224 q_vector->itr_val = new_itr;
4225 q_vector->set_itr = 1;
9d5c8243 4226 }
9d5c8243
AK		 4227}
4228
c50b52a0
SH		 4229static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4230 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4231{
4232 struct e1000_adv_tx_context_desc *context_desc;
4233 u16 i = tx_ring->next_to_use;
4234
4235 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4236
4237 i++;
4238 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4239
4240 /* set bits to identify this as an advanced context descriptor */
4241 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4242
4243 /* For 82575, context index must be unique per ring. */
866cff06 4244 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4245 mss_l4len_idx |= tx_ring->reg_idx << 4;
4246
4247 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4248 context_desc->seqnum_seed = 0;
4249 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4250 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4251}
4252
7af40ad9
AD		 4253static int igb_tso(struct igb_ring *tx_ring,
4254 struct igb_tx_buffer *first,
4255 u8 *hdr_len)
9d5c8243 4256{
7af40ad9 4257 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4258 u32 vlan_macip_lens, type_tucmd;
4259 u32 mss_l4len_idx, l4len;
4260
ed6aa105
AD		 4261 if (skb->ip_summed != CHECKSUM_PARTIAL)
4262 return 0;
4263
7d13a7d0
AD		 4264 if (!skb_is_gso(skb))
4265 return 0;
9d5c8243
AK		 4266
4267 if (skb_header_cloned(skb)) {
7af40ad9 4268 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4269 if (err)
4270 return err;
4271 }
4272
7d13a7d0
AD		 4273 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4274 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4275
7af40ad9 4276 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4277 struct iphdr *iph = ip_hdr(skb);
4278 iph->tot_len = 0;
4279 iph->check = 0;
4280 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4281 iph->daddr, 0,
4282 IPPROTO_TCP,
4283 0);
7d13a7d0 4284 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4285 first->tx_flags |= IGB_TX_FLAGS_TSO |
4286 IGB_TX_FLAGS_CSUM |
4287 IGB_TX_FLAGS_IPV4;
8e1e8a47 4288 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4289 ipv6_hdr(skb)->payload_len = 0;
4290 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4291 &ipv6_hdr(skb)->daddr,
4292 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4293 first->tx_flags |= IGB_TX_FLAGS_TSO |
4294 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4295 }
4296
7af40ad9 4297 /* compute header lengths */
7d13a7d0
AD		 4298 l4len = tcp_hdrlen(skb);
4299 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4300
7af40ad9
AD		 4301 /* update gso size and bytecount with header size */
4302 first->gso_segs = skb_shinfo(skb)->gso_segs;
4303 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4304
9d5c8243 4305 /* MSS L4LEN IDX */
7d13a7d0
AD		 4306 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4307 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4308
7d13a7d0
AD		 4309 /* VLAN MACLEN IPLEN */
4310 vlan_macip_lens = skb_network_header_len(skb);
4311 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4312 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4313
7d13a7d0 4314 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4315
7d13a7d0 4316 return 1;
9d5c8243
AK		 4317}
4318
7af40ad9 4319static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4320{
7af40ad9 4321 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4322 u32 vlan_macip_lens = 0;
4323 u32 mss_l4len_idx = 0;
4324 u32 type_tucmd = 0;
9d5c8243 4325
7d13a7d0 4326 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4327 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4328 return;
7d13a7d0
AD		 4329 } else {
4330 u8 l4_hdr = 0;
7af40ad9 4331 switch (first->protocol) {
7d13a7d0
AD		 4332 case __constant_htons(ETH_P_IP):
4333 vlan_macip_lens |= skb_network_header_len(skb);
4334 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4335 l4_hdr = ip_hdr(skb)->protocol;
4336 break;
4337 case __constant_htons(ETH_P_IPV6):
4338 vlan_macip_lens |= skb_network_header_len(skb);
4339 l4_hdr = ipv6_hdr(skb)->nexthdr;
4340 break;
4341 default:
4342 if (unlikely(net_ratelimit())) {
4343 dev_warn(tx_ring->dev,
4344 "partial checksum but proto=%x!\n",
7af40ad9 4345 first->protocol);
fa4a7ef3 4346 }
7d13a7d0
AD		 4347 break;
4348 }
fa4a7ef3 4349
7d13a7d0
AD		 4350 switch (l4_hdr) {
4351 case IPPROTO_TCP:
4352 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4353 mss_l4len_idx = tcp_hdrlen(skb) <<
4354 E1000_ADVTXD_L4LEN_SHIFT;
4355 break;
4356 case IPPROTO_SCTP:
4357 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4358 mss_l4len_idx = sizeof(struct sctphdr) <<
4359 E1000_ADVTXD_L4LEN_SHIFT;
4360 break;
4361 case IPPROTO_UDP:
4362 mss_l4len_idx = sizeof(struct udphdr) <<
4363 E1000_ADVTXD_L4LEN_SHIFT;
4364 break;
4365 default:
4366 if (unlikely(net_ratelimit())) {
4367 dev_warn(tx_ring->dev,
4368 "partial checksum but l4 proto=%x!\n",
4369 l4_hdr);
44b0cda3 4370 }
7d13a7d0 4371 break;
9d5c8243 4372 }
7af40ad9
AD		 4373
4374 /* update TX checksum flag */
4375 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4376 }
9d5c8243 4377
7d13a7d0 4378 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4379 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4380
7d13a7d0 4381 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4382}
4383
1d9daf45
AD		 4384#define IGB_SET_FLAG(_input, _flag, _result) \
4385 ((_flag <= _result) ? \
4386 ((u32)(_input & _flag) * (_result / _flag)) : \
4387 ((u32)(_input & _flag) / (_flag / _result)))
4388
4389static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4390{
4391 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4392 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4393 E1000_ADVTXD_DCMD_DEXT |
4394 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4395
4396 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4397 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4398 (E1000_ADVTXD_DCMD_VLE));
4399
4400 /* set segmentation bits for TSO */
4401 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4402 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4403
4404 /* set timestamp bit if present */
1d9daf45
AD		 4405 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4406 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4407
1d9daf45
AD		 4408 /* insert frame checksum */
4409 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4410
4411 return cmd_type;
4412}
4413
7af40ad9
AD		 4414static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4415 union e1000_adv_tx_desc *tx_desc,
4416 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4417{
4418 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4419
1d9daf45
AD		 4420 /* 82575 requires a unique index per ring */
4421 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4422 olinfo_status |= tx_ring->reg_idx << 4;
4423
4424 /* insert L4 checksum */
1d9daf45
AD		 4425 olinfo_status |= IGB_SET_FLAG(tx_flags,
4426 IGB_TX_FLAGS_CSUM,
4427 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4428
1d9daf45
AD		 4429 /* insert IPv4 checksum */
4430 olinfo_status |= IGB_SET_FLAG(tx_flags,
4431 IGB_TX_FLAGS_IPV4,
4432 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4433
7af40ad9 4434 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4435}
4436
ebe42d16
AD		 4437/*
4438 * The largest size we can write to the descriptor is 65535. In order to
4439 * maintain a power of two alignment we have to limit ourselves to 32K.
4440 */
4441#define IGB_MAX_TXD_PWR 15
7af40ad9 4442#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4443
7af40ad9
AD		 4444static void igb_tx_map(struct igb_ring *tx_ring,
4445 struct igb_tx_buffer *first,
ebe42d16 4446 const u8 hdr_len)
9d5c8243 4447{
7af40ad9 4448 struct sk_buff *skb = first->skb;
c9f14bf3 4449 struct igb_tx_buffer *tx_buffer;
ebe42d16 4450 union e1000_adv_tx_desc *tx_desc;
80d0759e 4451 struct skb_frag_struct *frag;
ebe42d16 4452 dma_addr_t dma;
80d0759e 4453 unsigned int data_len, size;
7af40ad9 4454 u32 tx_flags = first->tx_flags;
1d9daf45 4455 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4456 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4457
4458 tx_desc = IGB_TX_DESC(tx_ring, i);
4459
80d0759e
AD		 4460 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4461
4462 size = skb_headlen(skb);
4463 data_len = skb->data_len;
ebe42d16
AD		 4464
4465 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4466
80d0759e
AD		 4467 tx_buffer = first;
4468
4469 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4470 if (dma_mapping_error(tx_ring->dev, dma))
4471 goto dma_error;
4472
4473 /* record length, and DMA address */
4474 dma_unmap_len_set(tx_buffer, len, size);
4475 dma_unmap_addr_set(tx_buffer, dma, dma);
4476
4477 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4478
ebe42d16
AD		 4479 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4480 tx_desc->read.cmd_type_len =
1d9daf45 4481 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4482
4483 i++;
4484 tx_desc++;
4485 if (i == tx_ring->count) {
4486 tx_desc = IGB_TX_DESC(tx_ring, 0);
4487 i = 0;
4488 }
80d0759e 4489 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4490
4491 dma += IGB_MAX_DATA_PER_TXD;
4492 size -= IGB_MAX_DATA_PER_TXD;
4493
ebe42d16
AD		 4494 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4495 }
4496
4497 if (likely(!data_len))
4498 break;
2bbfebe2 4499
1d9daf45 4500 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4501
65689fef 4502 i++;
ebe42d16
AD		 4503 tx_desc++;
4504 if (i == tx_ring->count) {
4505 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4506 i = 0;
ebe42d16 4507 }
80d0759e 4508 tx_desc->read.olinfo_status = 0;
65689fef 4509
9e903e08 4510 size = skb_frag_size(frag);
ebe42d16
AD		 4511 data_len -= size;
4512
4513 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4514 size, DMA_TO_DEVICE);
6366ad33 4515
c9f14bf3 4516 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4517 }
4518
ebe42d16 4519 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4520 cmd_type |= size | IGB_TXD_DCMD;
4521 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4522
80d0759e
AD		 4523 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4524
8542db05
AD		 4525 /* set the timestamp */
4526 first->time_stamp = jiffies;
4527
ebe42d16
AD		 4528 /*
4529 * Force memory writes to complete before letting h/w know there
4530 * are new descriptors to fetch. (Only applicable for weak-ordered
4531 * memory model archs, such as IA-64).
4532 *
4533 * We also need this memory barrier to make certain all of the
4534 * status bits have been updated before next_to_watch is written.
4535 */
4536 wmb();
4537
8542db05 4538 /* set next_to_watch value indicating a packet is present */
ebe42d16 4539 first->next_to_watch = tx_desc;
9d5c8243 4540
ebe42d16
AD		 4541 i++;
4542 if (i == tx_ring->count)
4543 i = 0;
6366ad33 4544
ebe42d16 4545 tx_ring->next_to_use = i;
6366ad33 4546
ebe42d16 4547 writel(i, tx_ring->tail);
6366ad33 4548
ebe42d16
AD		 4549 /* we need this if more than one processor can write to our tail
4550 * at a time, it syncronizes IO on IA64/Altix systems */
4551 mmiowb();
4552
4553 return;
4554
4555dma_error:
4556 dev_err(tx_ring->dev, "TX DMA map failed\n");
4557
4558 /* clear dma mappings for failed tx_buffer_info map */
4559 for (;;) {
c9f14bf3
AD		 4560 tx_buffer = &tx_ring->tx_buffer_info[i];
4561 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4562 if (tx_buffer == first)
ebe42d16 4563 break;
a77ff709
NN		 4564 if (i == 0)
4565 i = tx_ring->count;
6366ad33 4566 i--;
6366ad33
AD		 4567 }
4568
9d5c8243 4569 tx_ring->next_to_use = i;
9d5c8243
AK		 4570}
4571
6ad4edfc 4572static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4573{
e694e964
AD		 4574 struct net_device *netdev = tx_ring->netdev;
4575
661086df 4576 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4577
9d5c8243
AK		 4578 /* Herbert's original patch had:
4579 * smp_mb__after_netif_stop_queue();
4580 * but since that doesn't exist yet, just open code it. */
4581 smp_mb();
4582
4583 /* We need to check again in a case another CPU has just
4584 * made room available. */
c493ea45 4585 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4586 return -EBUSY;
4587
4588 /* A reprieve! */
661086df 4589 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4590
4591 u64_stats_update_begin(&tx_ring->tx_syncp2);
4592 tx_ring->tx_stats.restart_queue2++;
4593 u64_stats_update_end(&tx_ring->tx_syncp2);
4594
9d5c8243
AK		 4595 return 0;
4596}
4597
6ad4edfc 4598static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4599{
c493ea45 4600 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4601 return 0;
e694e964 4602 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4603}
4604
cd392f5c
AD		 4605netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4606 struct igb_ring *tx_ring)
9d5c8243 4607{
1f6e8178 4608 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4609 struct igb_tx_buffer *first;
ebe42d16 4610 int tso;
91d4ee33 4611 u32 tx_flags = 0;
31f6adbb 4612 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4613 u8 hdr_len = 0;
9d5c8243 4614
9d5c8243
AK		 4615 /* need: 1 descriptor per page,
4616 * + 2 desc gap to keep tail from touching head,
4617 * + 1 desc for skb->data,
4618 * + 1 desc for context descriptor,
4619 * otherwise try next time */
e694e964 4620 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4621 /* this is a hard error */
9d5c8243
AK		 4622 return NETDEV_TX_BUSY;
4623 }
33af6bcc 4624
7af40ad9
AD		 4625 /* record the location of the first descriptor for this packet */
4626 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4627 first->skb = skb;
4628 first->bytecount = skb->len;
4629 first->gso_segs = 1;
4630
b66e2397
MV		 4631 skb_tx_timestamp(skb);
4632
1f6e8178
MV		 4633 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4634 !(adapter->ptp_tx_skb))) {
2244d07b 4635 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4636 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4637
4638 adapter->ptp_tx_skb = skb_get(skb);
428f1f71 4639 adapter->ptp_tx_start = jiffies;
1f6e8178
MV		 4640 if (adapter->hw.mac.type == e1000_82576)
4641 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4642 }
9d5c8243 4643
eab6d18d 4644 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4645 tx_flags |= IGB_TX_FLAGS_VLAN;
4646 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4647 }
4648
7af40ad9
AD		 4649 /* record initial flags and protocol */
4650 first->tx_flags = tx_flags;
4651 first->protocol = protocol;
cdfd01fc 4652
7af40ad9
AD		 4653 tso = igb_tso(tx_ring, first, &hdr_len);
4654 if (tso < 0)
7d13a7d0 4655 goto out_drop;
7af40ad9
AD		 4656 else if (!tso)
4657 igb_tx_csum(tx_ring, first);
9d5c8243 4658
7af40ad9 4659 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4660
4661 /* Make sure there is space in the ring for the next send. */
e694e964 4662 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4663
9d5c8243 4664 return NETDEV_TX_OK;
7d13a7d0
AD		 4665
4666out_drop:
7af40ad9
AD		 4667 igb_unmap_and_free_tx_resource(tx_ring, first);
4668
7d13a7d0 4669 return NETDEV_TX_OK;
9d5c8243
AK		 4670}
4671
1cc3bd87
AD		 4672static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4673 struct sk_buff *skb)
4674{
4675 unsigned int r_idx = skb->queue_mapping;
4676
4677 if (r_idx >= adapter->num_tx_queues)
4678 r_idx = r_idx % adapter->num_tx_queues;
4679
4680 return adapter->tx_ring[r_idx];
4681}
4682
cd392f5c
AD		 4683static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4684 struct net_device *netdev)
9d5c8243
AK		 4685{
4686 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4687
4688 if (test_bit(__IGB_DOWN, &adapter->state)) {
4689 dev_kfree_skb_any(skb);
4690 return NETDEV_TX_OK;
4691 }
4692
4693 if (skb->len <= 0) {
4694 dev_kfree_skb_any(skb);
4695 return NETDEV_TX_OK;
4696 }
4697
1cc3bd87
AD		 4698 /*
4699 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4700 * in order to meet this minimum size requirement.
4701 */
ea5ceeab
TD		 4702 if (unlikely(skb->len < 17)) {
4703 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4704 return NETDEV_TX_OK;
4705 skb->len = 17;
ea5ceeab 4706 skb_set_tail_pointer(skb, 17);
1cc3bd87 4707 }
9d5c8243 4708
1cc3bd87 4709 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4710}
4711
4712/**
4713 * igb_tx_timeout - Respond to a Tx Hang
4714 * @netdev: network interface device structure
4715 **/
4716static void igb_tx_timeout(struct net_device *netdev)
4717{
4718 struct igb_adapter *adapter = netdev_priv(netdev);
4719 struct e1000_hw *hw = &adapter->hw;
4720
4721 /* Do the reset outside of interrupt context */
4722 adapter->tx_timeout_count++;
f7ba205e 4723
06218a8d 4724 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4725 hw->dev_spec._82575.global_device_reset = true;
4726
9d5c8243 4727 schedule_work(&adapter->reset_task);
265de409
AD		 4728 wr32(E1000_EICS,
4729 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4730}
4731
4732static void igb_reset_task(struct work_struct *work)
4733{
4734 struct igb_adapter *adapter;
4735 adapter = container_of(work, struct igb_adapter, reset_task);
4736
c97ec42a
TI		 4737 igb_dump(adapter);
4738 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4739 igb_reinit_locked(adapter);
4740}
4741
4742/**
12dcd86b 4743 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4744 * @netdev: network interface device structure
12dcd86b 4745 * @stats: rtnl_link_stats64 pointer
9d5c8243 4746 *
9d5c8243 4747 **/
12dcd86b
ED		 4748static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4749 struct rtnl_link_stats64 *stats)
9d5c8243 4750{
12dcd86b
ED		 4751 struct igb_adapter *adapter = netdev_priv(netdev);
4752
4753 spin_lock(&adapter->stats64_lock);
4754 igb_update_stats(adapter, &adapter->stats64);
4755 memcpy(stats, &adapter->stats64, sizeof(*stats));
4756 spin_unlock(&adapter->stats64_lock);
4757
4758 return stats;
9d5c8243
AK		 4759}
4760
4761/**
4762 * igb_change_mtu - Change the Maximum Transfer Unit
4763 * @netdev: network interface device structure
4764 * @new_mtu: new value for maximum frame size
4765 *
4766 * Returns 0 on success, negative on failure
4767 **/
4768static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4769{
4770 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4771 struct pci_dev *pdev = adapter->pdev;
153285f9 4772 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4773
c809d227 4774 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4775 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4776 return -EINVAL;
4777 }
4778
153285f9 4779#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4780 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4781 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4782 return -EINVAL;
4783 }
4784
4785 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4786 msleep(1);
73cd78f1 4787
9d5c8243
AK		 4788 /* igb_down has a dependency on max_frame_size */
4789 adapter->max_frame_size = max_frame;
559e9c49 4790
4c844851
AD		 4791 if (netif_running(netdev))
4792 igb_down(adapter);
9d5c8243 4793
090b1795 4794 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4795 netdev->mtu, new_mtu);
4796 netdev->mtu = new_mtu;
4797
4798 if (netif_running(netdev))
4799 igb_up(adapter);
4800 else
4801 igb_reset(adapter);
4802
4803 clear_bit(__IGB_RESETTING, &adapter->state);
4804
4805 return 0;
4806}
4807
4808/**
4809 * igb_update_stats - Update the board statistics counters
4810 * @adapter: board private structure
4811 **/
4812
12dcd86b
ED		 4813void igb_update_stats(struct igb_adapter *adapter,
4814 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4815{
4816 struct e1000_hw *hw = &adapter->hw;
4817 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4818 u32 reg, mpc;
9d5c8243 4819 u16 phy_tmp;
3f9c0164
AD		 4820 int i;
4821 u64 bytes, packets;
12dcd86b
ED		 4822 unsigned int start;
4823 u64 _bytes, _packets;
9d5c8243
AK		 4824
4825#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4826
4827 /*
4828 * Prevent stats update while adapter is being reset, or if the pci
4829 * connection is down.
4830 */
4831 if (adapter->link_speed == 0)
4832 return;
4833 if (pci_channel_offline(pdev))
4834 return;
4835
3f9c0164
AD		 4836 bytes = 0;
4837 packets = 0;
4838 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4839 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4840 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4841
ae1c07a6
AD		 4842 if (rqdpc) {
4843 ring->rx_stats.drops += rqdpc;
4844 net_stats->rx_fifo_errors += rqdpc;
4845 }
12dcd86b
ED		 4846
4847 do {
4848 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4849 _bytes = ring->rx_stats.bytes;
4850 _packets = ring->rx_stats.packets;
4851 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4852 bytes += _bytes;
4853 packets += _packets;
3f9c0164
AD		 4854 }
4855
128e45eb
AD		 4856 net_stats->rx_bytes = bytes;
4857 net_stats->rx_packets = packets;
3f9c0164
AD		 4858
4859 bytes = 0;
4860 packets = 0;
4861 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4862 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4863 do {
4864 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4865 _bytes = ring->tx_stats.bytes;
4866 _packets = ring->tx_stats.packets;
4867 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4868 bytes += _bytes;
4869 packets += _packets;
3f9c0164 4870 }
128e45eb
AD		 4871 net_stats->tx_bytes = bytes;
4872 net_stats->tx_packets = packets;
3f9c0164
AD		 4873
4874 /* read stats registers */
9d5c8243
AK		 4875 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4876 adapter->stats.gprc += rd32(E1000_GPRC);
4877 adapter->stats.gorc += rd32(E1000_GORCL);
4878 rd32(E1000_GORCH); /* clear GORCL */
4879 adapter->stats.bprc += rd32(E1000_BPRC);
4880 adapter->stats.mprc += rd32(E1000_MPRC);
4881 adapter->stats.roc += rd32(E1000_ROC);
4882
4883 adapter->stats.prc64 += rd32(E1000_PRC64);
4884 adapter->stats.prc127 += rd32(E1000_PRC127);
4885 adapter->stats.prc255 += rd32(E1000_PRC255);
4886 adapter->stats.prc511 += rd32(E1000_PRC511);
4887 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4888 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4889 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4890 adapter->stats.sec += rd32(E1000_SEC);
4891
fa3d9a6d
MW		 4892 mpc = rd32(E1000_MPC);
4893 adapter->stats.mpc += mpc;
4894 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4895 adapter->stats.scc += rd32(E1000_SCC);
4896 adapter->stats.ecol += rd32(E1000_ECOL);
4897 adapter->stats.mcc += rd32(E1000_MCC);
4898 adapter->stats.latecol += rd32(E1000_LATECOL);
4899 adapter->stats.dc += rd32(E1000_DC);
4900 adapter->stats.rlec += rd32(E1000_RLEC);
4901 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4902 adapter->stats.xontxc += rd32(E1000_XONTXC);
4903 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4904 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4905 adapter->stats.fcruc += rd32(E1000_FCRUC);
4906 adapter->stats.gptc += rd32(E1000_GPTC);
4907 adapter->stats.gotc += rd32(E1000_GOTCL);
4908 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4909 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4910 adapter->stats.ruc += rd32(E1000_RUC);
4911 adapter->stats.rfc += rd32(E1000_RFC);
4912 adapter->stats.rjc += rd32(E1000_RJC);
4913 adapter->stats.tor += rd32(E1000_TORH);
4914 adapter->stats.tot += rd32(E1000_TOTH);
4915 adapter->stats.tpr += rd32(E1000_TPR);
4916
4917 adapter->stats.ptc64 += rd32(E1000_PTC64);
4918 adapter->stats.ptc127 += rd32(E1000_PTC127);
4919 adapter->stats.ptc255 += rd32(E1000_PTC255);
4920 adapter->stats.ptc511 += rd32(E1000_PTC511);
4921 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4922 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4923
4924 adapter->stats.mptc += rd32(E1000_MPTC);
4925 adapter->stats.bptc += rd32(E1000_BPTC);
4926
2d0b0f69
NN		 4927 adapter->stats.tpt += rd32(E1000_TPT);
4928 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4929
4930 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4931 /* read internal phy specific stats */
4932 reg = rd32(E1000_CTRL_EXT);
4933 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4934 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4935
4936 /* this stat has invalid values on i210/i211 */
4937 if ((hw->mac.type != e1000_i210) &&
4938 (hw->mac.type != e1000_i211))
4939 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4940 }
4941
9d5c8243
AK		 4942 adapter->stats.tsctc += rd32(E1000_TSCTC);
4943 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4944
4945 adapter->stats.iac += rd32(E1000_IAC);
4946 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4947 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4948 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4949 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4950 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4951 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4952 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4953 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4954
4955 /* Fill out the OS statistics structure */
128e45eb
AD		 4956 net_stats->multicast = adapter->stats.mprc;
4957 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4958
4959 /* Rx Errors */
4960
4961 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4962 * our own version based on RUC and ROC */
128e45eb 4963 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4964 adapter->stats.crcerrs + adapter->stats.algnerrc +
4965 adapter->stats.ruc + adapter->stats.roc +
4966 adapter->stats.cexterr;
128e45eb
AD		 4967 net_stats->rx_length_errors = adapter->stats.ruc +
4968 adapter->stats.roc;
4969 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4970 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4971 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4972
4973 /* Tx Errors */
128e45eb
AD		 4974 net_stats->tx_errors = adapter->stats.ecol +
4975 adapter->stats.latecol;
4976 net_stats->tx_aborted_errors = adapter->stats.ecol;
4977 net_stats->tx_window_errors = adapter->stats.latecol;
4978 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4979
4980 /* Tx Dropped needs to be maintained elsewhere */
4981
4982 /* Phy Stats */
4983 if (hw->phy.media_type == e1000_media_type_copper) {
4984 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4985 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4986 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4987 adapter->phy_stats.idle_errors += phy_tmp;
4988 }
4989 }
4990
4991 /* Management Stats */
4992 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4993 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4994 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4995
4996 /* OS2BMC Stats */
4997 reg = rd32(E1000_MANC);
4998 if (reg & E1000_MANC_EN_BMC2OS) {
4999 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5000 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5001 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5002 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5003 }
9d5c8243
AK		 5004}
5005
9d5c8243
AK		 5006static irqreturn_t igb_msix_other(int irq, void *data)
5007{
047e0030 5008 struct igb_adapter *adapter = data;
9d5c8243 5009 struct e1000_hw *hw = &adapter->hw;
844290e5 5010 u32 icr = rd32(E1000_ICR);
844290e5 5011 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5012
7f081d40
AD		 5013 if (icr & E1000_ICR_DRSTA)
5014 schedule_work(&adapter->reset_task);
5015
047e0030 5016 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5017 /* HW is reporting DMA is out of sync */
5018 adapter->stats.doosync++;
13800469
GR		 5019 /* The DMA Out of Sync is also indication of a spoof event
5020 * in IOV mode. Check the Wrong VM Behavior register to
5021 * see if it is really a spoof event. */
5022 igb_check_wvbr(adapter);
dda0e083 5023 }
eebbbdba 5024
4ae196df
AD		 5025 /* Check for a mailbox event */
5026 if (icr & E1000_ICR_VMMB)
5027 igb_msg_task(adapter);
5028
5029 if (icr & E1000_ICR_LSC) {
5030 hw->mac.get_link_status = 1;
5031 /* guard against interrupt when we're going down */
5032 if (!test_bit(__IGB_DOWN, &adapter->state))
5033 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5034 }
5035
1f6e8178
MV		 5036 if (icr & E1000_ICR_TS) {
5037 u32 tsicr = rd32(E1000_TSICR);
5038
5039 if (tsicr & E1000_TSICR_TXTS) {
5040 /* acknowledge the interrupt */
5041 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5042 /* retrieve hardware timestamp */
5043 schedule_work(&adapter->ptp_tx_work);
5044 }
5045 }
1f6e8178 5046
844290e5 5047 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5048
5049 return IRQ_HANDLED;
5050}
5051
047e0030 5052static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5053{
26b39276 5054 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5055 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5056
047e0030
AD		 5057 if (!q_vector->set_itr)
5058 return;
73cd78f1 5059
047e0030
AD		 5060 if (!itr_val)
5061 itr_val = 0x4;
661086df 5062
26b39276
AD		 5063 if (adapter->hw.mac.type == e1000_82575)
5064 itr_val |= itr_val << 16;
661086df 5065 else
0ba82994 5066 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5067
047e0030
AD		 5068 writel(itr_val, q_vector->itr_register);
5069 q_vector->set_itr = 0;
6eb5a7f1
AD		 5070}
5071
047e0030 5072static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5073{
047e0030 5074 struct igb_q_vector *q_vector = data;
9d5c8243 5075
047e0030
AD		 5076 /* Write the ITR value calculated from the previous interrupt. */
5077 igb_write_itr(q_vector);
9d5c8243 5078
047e0030 5079 napi_schedule(&q_vector->napi);
844290e5 5080
047e0030 5081 return IRQ_HANDLED;
fe4506b6
JC		 5082}
5083
421e02f0 5084#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5085static void igb_update_tx_dca(struct igb_adapter *adapter,
5086 struct igb_ring *tx_ring,
5087 int cpu)
5088{
5089 struct e1000_hw *hw = &adapter->hw;
5090 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5091
5092 if (hw->mac.type != e1000_82575)
5093 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5094
5095 /*
5096 * We can enable relaxed ordering for reads, but not writes when
5097 * DCA is enabled. This is due to a known issue in some chipsets
5098 * which will cause the DCA tag to be cleared.
5099 */
5100 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5101 E1000_DCA_TXCTRL_DATA_RRO_EN |
5102 E1000_DCA_TXCTRL_DESC_DCA_EN;
5103
5104 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5105}
5106
5107static void igb_update_rx_dca(struct igb_adapter *adapter,
5108 struct igb_ring *rx_ring,
5109 int cpu)
5110{
5111 struct e1000_hw *hw = &adapter->hw;
5112 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5113
5114 if (hw->mac.type != e1000_82575)
5115 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5116
5117 /*
5118 * We can enable relaxed ordering for reads, but not writes when
5119 * DCA is enabled. This is due to a known issue in some chipsets
5120 * which will cause the DCA tag to be cleared.
5121 */
5122 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5123 E1000_DCA_RXCTRL_DESC_DCA_EN;
5124
5125 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5126}
5127
047e0030 5128static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5129{
047e0030 5130 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5131 int cpu = get_cpu();
fe4506b6 5132
047e0030
AD		 5133 if (q_vector->cpu == cpu)
5134 goto out_no_update;
5135
6a05004a
AD		 5136 if (q_vector->tx.ring)
5137 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5138
5139 if (q_vector->rx.ring)
5140 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5141
047e0030
AD		 5142 q_vector->cpu = cpu;
5143out_no_update:
fe4506b6
JC		 5144 put_cpu();
5145}
5146
5147static void igb_setup_dca(struct igb_adapter *adapter)
5148{
7e0e99ef 5149 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5150 int i;
5151
7dfc16fa 5152 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5153 return;
5154
7e0e99ef
AD		 5155 /* Always use CB2 mode, difference is masked in the CB driver. */
5156 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5157
047e0030 5158 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5159 adapter->q_vector[i]->cpu = -1;
5160 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5161 }
5162}
5163
5164static int __igb_notify_dca(struct device *dev, void *data)
5165{
5166 struct net_device *netdev = dev_get_drvdata(dev);
5167 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5168 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5169 struct e1000_hw *hw = &adapter->hw;
5170 unsigned long event = *(unsigned long *)data;
5171
5172 switch (event) {
5173 case DCA_PROVIDER_ADD:
5174 /* if already enabled, don't do it again */
7dfc16fa 5175 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5176 break;
fe4506b6 5177 if (dca_add_requester(dev) == 0) {
bbd98fe4 5178 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5179 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5180 igb_setup_dca(adapter);
5181 break;
5182 }
5183 /* Fall Through since DCA is disabled. */
5184 case DCA_PROVIDER_REMOVE:
7dfc16fa 5185 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5186 /* without this a class_device is left
047e0030 5187 * hanging around in the sysfs model */
fe4506b6 5188 dca_remove_requester(dev);
090b1795 5189 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5190 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5191 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5192 }
5193 break;
5194 }
bbd98fe4 5195
fe4506b6 5196 return 0;
9d5c8243
AK		 5197}
5198
fe4506b6
JC		 5199static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5200 void *p)
5201{
5202 int ret_val;
5203
5204 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5205 __igb_notify_dca);
5206
5207 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5208}
421e02f0 5209#endif /* CONFIG_IGB_DCA */
9d5c8243 5210
0224d663
GR		 5211#ifdef CONFIG_PCI_IOV
5212static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5213{
5214 unsigned char mac_addr[ETH_ALEN];
0224d663 5215
5ac6f91d 5216 eth_zero_addr(mac_addr);
0224d663
GR		 5217 igb_set_vf_mac(adapter, vf, mac_addr);
5218
f557147c 5219 return 0;
0224d663
GR		 5220}
5221
f557147c 5222static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 5223{
0224d663 5224 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 5225 struct pci_dev *vfdev;
5226 int dev_id;
0224d663
GR		 5227
5228 switch (adapter->hw.mac.type) {
5229 case e1000_82576:
f557147c 5230 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 5231 break;
5232 case e1000_i350:
f557147c 5233 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 5234 break;
5235 default:
f557147c 5236 return false;
0224d663
GR		 5237 }
5238
f557147c
SA		 5239 /* loop through all the VFs to see if we own any that are assigned */
5240 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5241 while (vfdev) {
5242 /* if we don't own it we don't care */
5243 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5244 /* if it is assigned we cannot release it */
5245 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5246 return true;
5247 }
f557147c
SA		 5248
5249 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5250 }
f557147c 5251
0224d663
GR		 5252 return false;
5253}
5254
5255#endif
4ae196df
AD		 5256static void igb_ping_all_vfs(struct igb_adapter *adapter)
5257{
5258 struct e1000_hw *hw = &adapter->hw;
5259 u32 ping;
5260 int i;
5261
5262 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5263 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5264 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5265 ping |= E1000_VT_MSGTYPE_CTS;
5266 igb_write_mbx(hw, &ping, 1, i);
5267 }
5268}
5269
7d5753f0
AD		 5270static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5271{
5272 struct e1000_hw *hw = &adapter->hw;
5273 u32 vmolr = rd32(E1000_VMOLR(vf));
5274 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5275
d85b9004 5276 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5277 IGB_VF_FLAG_MULTI_PROMISC);
5278 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5279
5280 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5281 vmolr |= E1000_VMOLR_MPME;
d85b9004 5282 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5283 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5284 } else {
5285 /*
5286 * if we have hashes and we are clearing a multicast promisc
5287 * flag we need to write the hashes to the MTA as this step
5288 * was previously skipped
5289 */
5290 if (vf_data->num_vf_mc_hashes > 30) {
5291 vmolr |= E1000_VMOLR_MPME;
5292 } else if (vf_data->num_vf_mc_hashes) {
5293 int j;
5294 vmolr |= E1000_VMOLR_ROMPE;
5295 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5296 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5297 }
5298 }
5299
5300 wr32(E1000_VMOLR(vf), vmolr);
5301
5302 /* there are flags left unprocessed, likely not supported */
5303 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5304 return -EINVAL;
5305
5306 return 0;
5307
5308}
5309
4ae196df
AD		 5310static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5311 u32 *msgbuf, u32 vf)
5312{
5313 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5314 u16 *hash_list = (u16 *)&msgbuf[1];
5315 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5316 int i;
5317
7d5753f0 5318 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5319 * to this VF for later use to restore when the PF multi cast
5320 * list changes
5321 */
5322 vf_data->num_vf_mc_hashes = n;
5323
7d5753f0
AD		 5324 /* only up to 30 hash values supported */
5325 if (n > 30)
5326 n = 30;
5327
5328 /* store the hashes for later use */
4ae196df 5329 for (i = 0; i < n; i++)
a419aef8 5330 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5331
5332 /* Flush and reset the mta with the new values */
ff41f8dc 5333 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5334
5335 return 0;
5336}
5337
5338static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5339{
5340 struct e1000_hw *hw = &adapter->hw;
5341 struct vf_data_storage *vf_data;
5342 int i, j;
5343
5344 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5345 u32 vmolr = rd32(E1000_VMOLR(i));
5346 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5347
4ae196df 5348 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5349
5350 if ((vf_data->num_vf_mc_hashes > 30) ||
5351 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5352 vmolr |= E1000_VMOLR_MPME;
5353 } else if (vf_data->num_vf_mc_hashes) {
5354 vmolr |= E1000_VMOLR_ROMPE;
5355 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5356 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5357 }
5358 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5359 }
5360}
5361
5362static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5363{
5364 struct e1000_hw *hw = &adapter->hw;
5365 u32 pool_mask, reg, vid;
5366 int i;
5367
5368 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5369
5370 /* Find the vlan filter for this id */
5371 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5372 reg = rd32(E1000_VLVF(i));
5373
5374 /* remove the vf from the pool */
5375 reg &= ~pool_mask;
5376
5377 /* if pool is empty then remove entry from vfta */
5378 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5379 (reg & E1000_VLVF_VLANID_ENABLE)) {
5380 reg = 0;
5381 vid = reg & E1000_VLVF_VLANID_MASK;
5382 igb_vfta_set(hw, vid, false);
5383 }
5384
5385 wr32(E1000_VLVF(i), reg);
5386 }
ae641bdc
AD		 5387
5388 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5389}
5390
5391static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5392{
5393 struct e1000_hw *hw = &adapter->hw;
5394 u32 reg, i;
5395
51466239
AD		 5396 /* The vlvf table only exists on 82576 hardware and newer */
5397 if (hw->mac.type < e1000_82576)
5398 return -1;
5399
5400 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5401 if (!adapter->vfs_allocated_count)
5402 return -1;
5403
5404 /* Find the vlan filter for this id */
5405 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5406 reg = rd32(E1000_VLVF(i));
5407 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5408 vid == (reg & E1000_VLVF_VLANID_MASK))
5409 break;
5410 }
5411
5412 if (add) {
5413 if (i == E1000_VLVF_ARRAY_SIZE) {
5414 /* Did not find a matching VLAN ID entry that was
5415 * enabled. Search for a free filter entry, i.e.
5416 * one without the enable bit set
5417 */
5418 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5419 reg = rd32(E1000_VLVF(i));
5420 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5421 break;
5422 }
5423 }
5424 if (i < E1000_VLVF_ARRAY_SIZE) {
5425 /* Found an enabled/available entry */
5426 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5427
5428 /* if !enabled we need to set this up in vfta */
5429 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5430 /* add VID to filter table */
5431 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5432 reg |= E1000_VLVF_VLANID_ENABLE;
5433 }
cad6d05f
AD		 5434 reg &= ~E1000_VLVF_VLANID_MASK;
5435 reg |= vid;
4ae196df 5436 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5437
5438 /* do not modify RLPML for PF devices */
5439 if (vf >= adapter->vfs_allocated_count)
5440 return 0;
5441
5442 if (!adapter->vf_data[vf].vlans_enabled) {
5443 u32 size;
5444 reg = rd32(E1000_VMOLR(vf));
5445 size = reg & E1000_VMOLR_RLPML_MASK;
5446 size += 4;
5447 reg &= ~E1000_VMOLR_RLPML_MASK;
5448 reg |= size;
5449 wr32(E1000_VMOLR(vf), reg);
5450 }
ae641bdc 5451
51466239 5452 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5453 }
5454 } else {
5455 if (i < E1000_VLVF_ARRAY_SIZE) {
5456 /* remove vf from the pool */
5457 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5458 /* if pool is empty then remove entry from vfta */
5459 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5460 reg = 0;
5461 igb_vfta_set(hw, vid, false);
5462 }
5463 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5464
5465 /* do not modify RLPML for PF devices */
5466 if (vf >= adapter->vfs_allocated_count)
5467 return 0;
5468
5469 adapter->vf_data[vf].vlans_enabled--;
5470 if (!adapter->vf_data[vf].vlans_enabled) {
5471 u32 size;
5472 reg = rd32(E1000_VMOLR(vf));
5473 size = reg & E1000_VMOLR_RLPML_MASK;
5474 size -= 4;
5475 reg &= ~E1000_VMOLR_RLPML_MASK;
5476 reg |= size;
5477 wr32(E1000_VMOLR(vf), reg);
5478 }
4ae196df
AD		 5479 }
5480 }
8151d294
WM		 5481 return 0;
5482}
5483
5484static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5485{
5486 struct e1000_hw *hw = &adapter->hw;
5487
5488 if (vid)
5489 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5490 else
5491 wr32(E1000_VMVIR(vf), 0);
5492}
5493
5494static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5495 int vf, u16 vlan, u8 qos)
5496{
5497 int err = 0;
5498 struct igb_adapter *adapter = netdev_priv(netdev);
5499
5500 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5501 return -EINVAL;
5502 if (vlan || qos) {
5503 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5504 if (err)
5505 goto out;
5506 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5507 igb_set_vmolr(adapter, vf, !vlan);
5508 adapter->vf_data[vf].pf_vlan = vlan;
5509 adapter->vf_data[vf].pf_qos = qos;
5510 dev_info(&adapter->pdev->dev,
5511 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5512 if (test_bit(__IGB_DOWN, &adapter->state)) {
5513 dev_warn(&adapter->pdev->dev,
5514 "The VF VLAN has been set,"
5515 " but the PF device is not up.\n");
5516 dev_warn(&adapter->pdev->dev,
5517 "Bring the PF device up before"
5518 " attempting to use the VF device.\n");
5519 }
5520 } else {
5521 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5522 false, vf);
5523 igb_set_vmvir(adapter, vlan, vf);
5524 igb_set_vmolr(adapter, vf, true);
5525 adapter->vf_data[vf].pf_vlan = 0;
5526 adapter->vf_data[vf].pf_qos = 0;
5527 }
5528out:
5529 return err;
4ae196df
AD		 5530}
5531
5532static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5533{
5534 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5535 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5536
5537 return igb_vlvf_set(adapter, vid, add, vf);
5538}
5539
f2ca0dbe 5540static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5541{
8fa7e0f7
GR		 5542 /* clear flags - except flag that indicates PF has set the MAC */
5543 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5544 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5545
5546 /* reset offloads to defaults */
8151d294 5547 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5548
5549 /* reset vlans for device */
5550 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5551 if (adapter->vf_data[vf].pf_vlan)
5552 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5553 adapter->vf_data[vf].pf_vlan,
5554 adapter->vf_data[vf].pf_qos);
5555 else
5556 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5557
5558 /* reset multicast table array for vf */
5559 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5560
5561 /* Flush and reset the mta with the new values */
ff41f8dc 5562 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5563}
5564
f2ca0dbe
AD		 5565static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5566{
5567 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5568
5ac6f91d 5569 /* clear mac address as we were hotplug removed/added */
8151d294 5570 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5571 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5572
5573 /* process remaining reset events */
5574 igb_vf_reset(adapter, vf);
5575}
5576
5577static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5578{
5579 struct e1000_hw *hw = &adapter->hw;
5580 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5581 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5582 u32 reg, msgbuf[3];
5583 u8 *addr = (u8 *)(&msgbuf[1]);
5584
5585 /* process all the same items cleared in a function level reset */
f2ca0dbe 5586 igb_vf_reset(adapter, vf);
4ae196df
AD		 5587
5588 /* set vf mac address */
26ad9178 5589 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5590
5591 /* enable transmit and receive for vf */
5592 reg = rd32(E1000_VFTE);
5593 wr32(E1000_VFTE, reg | (1 << vf));
5594 reg = rd32(E1000_VFRE);
5595 wr32(E1000_VFRE, reg | (1 << vf));
5596
8fa7e0f7 5597 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5598
5599 /* reply to reset with ack and vf mac address */
5600 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5601 memcpy(addr, vf_mac, 6);
5602 igb_write_mbx(hw, msgbuf, 3, vf);
5603}
5604
5605static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5606{
de42edde
GR		 5607 /*
5608 * The VF MAC Address is stored in a packed array of bytes
5609 * starting at the second 32 bit word of the msg array
5610 */
f2ca0dbe
AD		 5611 unsigned char *addr = (char *)&msg[1];
5612 int err = -1;
4ae196df 5613
f2ca0dbe
AD		 5614 if (is_valid_ether_addr(addr))
5615 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5616
f2ca0dbe 5617 return err;
4ae196df
AD		 5618}
5619
5620static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5621{
5622 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5623 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5624 u32 msg = E1000_VT_MSGTYPE_NACK;
5625
5626 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5627 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5628 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5629 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5630 vf_data->last_nack = jiffies;
4ae196df
AD		 5631 }
5632}
5633
f2ca0dbe 5634static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5635{
f2ca0dbe
AD		 5636 struct pci_dev *pdev = adapter->pdev;
5637 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5638 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5639 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5640 s32 retval;
5641
f2ca0dbe 5642 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5643
fef45f4c
AD		 5644 if (retval) {
5645 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5646 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5647 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5648 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5649 return;
5650 goto out;
5651 }
4ae196df
AD		 5652
5653 /* this is a message we already processed, do nothing */
5654 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5655 return;
4ae196df
AD		 5656
5657 /*
5658 * until the vf completes a reset it should not be
5659 * allowed to start any configuration.
5660 */
5661
5662 if (msgbuf[0] == E1000_VF_RESET) {
5663 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5664 return;
4ae196df
AD		 5665 }
5666
f2ca0dbe 5667 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5668 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5669 return;
5670 retval = -1;
5671 goto out;
4ae196df
AD		 5672 }
5673
5674 switch ((msgbuf[0] & 0xFFFF)) {
5675 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5676 retval = -EINVAL;
5677 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5678 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5679 else
5680 dev_warn(&pdev->dev,
5681 "VF %d attempted to override administratively "
5682 "set MAC address\nReload the VF driver to "
5683 "resume operations\n", vf);
4ae196df 5684 break;
7d5753f0
AD		 5685 case E1000_VF_SET_PROMISC:
5686 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5687 break;
4ae196df
AD		 5688 case E1000_VF_SET_MULTICAST:
5689 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5690 break;
5691 case E1000_VF_SET_LPE:
5692 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5693 break;
5694 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5695 retval = -1;
5696 if (vf_data->pf_vlan)
5697 dev_warn(&pdev->dev,
5698 "VF %d attempted to override administratively "
5699 "set VLAN tag\nReload the VF driver to "
5700 "resume operations\n", vf);
8151d294
WM		 5701 else
5702 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5703 break;
5704 default:
090b1795 5705 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5706 retval = -1;
5707 break;
5708 }
5709
fef45f4c
AD		 5710 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5711out:
4ae196df
AD		 5712 /* notify the VF of the results of what it sent us */
5713 if (retval)
5714 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5715 else
5716 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5717
4ae196df 5718 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5719}
4ae196df 5720
f2ca0dbe
AD		 5721static void igb_msg_task(struct igb_adapter *adapter)
5722{
5723 struct e1000_hw *hw = &adapter->hw;
5724 u32 vf;
5725
5726 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5727 /* process any reset requests */
5728 if (!igb_check_for_rst(hw, vf))
5729 igb_vf_reset_event(adapter, vf);
5730
5731 /* process any messages pending */
5732 if (!igb_check_for_msg(hw, vf))
5733 igb_rcv_msg_from_vf(adapter, vf);
5734
5735 /* process any acks */
5736 if (!igb_check_for_ack(hw, vf))
5737 igb_rcv_ack_from_vf(adapter, vf);
5738 }
4ae196df
AD		 5739}
5740
68d480c4
AD		 5741/**
5742 * igb_set_uta - Set unicast filter table address
5743 * @adapter: board private structure
5744 *
5745 * The unicast table address is a register array of 32-bit registers.
5746 * The table is meant to be used in a way similar to how the MTA is used
5747 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5748 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5749 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5750 **/
5751static void igb_set_uta(struct igb_adapter *adapter)
5752{
5753 struct e1000_hw *hw = &adapter->hw;
5754 int i;
5755
5756 /* The UTA table only exists on 82576 hardware and newer */
5757 if (hw->mac.type < e1000_82576)
5758 return;
5759
5760 /* we only need to do this if VMDq is enabled */
5761 if (!adapter->vfs_allocated_count)
5762 return;
5763
5764 for (i = 0; i < hw->mac.uta_reg_count; i++)
5765 array_wr32(E1000_UTA, i, ~0);
5766}
5767
9d5c8243
AK		 5768/**
5769 * igb_intr_msi - Interrupt Handler
5770 * @irq: interrupt number
5771 * @data: pointer to a network interface device structure
5772 **/
5773static irqreturn_t igb_intr_msi(int irq, void *data)
5774{
047e0030
AD		 5775 struct igb_adapter *adapter = data;
5776 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5777 struct e1000_hw *hw = &adapter->hw;
5778 /* read ICR disables interrupts using IAM */
5779 u32 icr = rd32(E1000_ICR);
5780
047e0030 5781 igb_write_itr(q_vector);
9d5c8243 5782
7f081d40
AD		 5783 if (icr & E1000_ICR_DRSTA)
5784 schedule_work(&adapter->reset_task);
5785
047e0030 5786 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5787 /* HW is reporting DMA is out of sync */
5788 adapter->stats.doosync++;
5789 }
5790
9d5c8243
AK		 5791 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5792 hw->mac.get_link_status = 1;
5793 if (!test_bit(__IGB_DOWN, &adapter->state))
5794 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5795 }
5796
1f6e8178
MV		 5797 if (icr & E1000_ICR_TS) {
5798 u32 tsicr = rd32(E1000_TSICR);
5799
5800 if (tsicr & E1000_TSICR_TXTS) {
5801 /* acknowledge the interrupt */
5802 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5803 /* retrieve hardware timestamp */
5804 schedule_work(&adapter->ptp_tx_work);
5805 }
5806 }
1f6e8178 5807
047e0030 5808 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5809
5810 return IRQ_HANDLED;
5811}
5812
5813/**
4a3c6433 5814 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5815 * @irq: interrupt number
5816 * @data: pointer to a network interface device structure
5817 **/
5818static irqreturn_t igb_intr(int irq, void *data)
5819{
047e0030
AD		 5820 struct igb_adapter *adapter = data;
5821 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5822 struct e1000_hw *hw = &adapter->hw;
5823 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5824 * need for the IMC write */
5825 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5826
5827 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5828 * not set, then the adapter didn't send an interrupt */
5829 if (!(icr & E1000_ICR_INT_ASSERTED))
5830 return IRQ_NONE;
5831
0ba82994
AD		 5832 igb_write_itr(q_vector);
5833
7f081d40
AD		 5834 if (icr & E1000_ICR_DRSTA)
5835 schedule_work(&adapter->reset_task);
5836
047e0030 5837 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5838 /* HW is reporting DMA is out of sync */
5839 adapter->stats.doosync++;
5840 }
5841
9d5c8243
AK		 5842 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5843 hw->mac.get_link_status = 1;
5844 /* guard against interrupt when we're going down */
5845 if (!test_bit(__IGB_DOWN, &adapter->state))
5846 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5847 }
5848
1f6e8178
MV		 5849 if (icr & E1000_ICR_TS) {
5850 u32 tsicr = rd32(E1000_TSICR);
5851
5852 if (tsicr & E1000_TSICR_TXTS) {
5853 /* acknowledge the interrupt */
5854 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5855 /* retrieve hardware timestamp */
5856 schedule_work(&adapter->ptp_tx_work);
5857 }
5858 }
1f6e8178 5859
047e0030 5860 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5861
5862 return IRQ_HANDLED;
5863}
5864
c50b52a0 5865static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5866{
047e0030 5867 struct igb_adapter *adapter = q_vector->adapter;
46544258 5868 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5869
0ba82994
AD		 5870 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5871 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5872 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5873 igb_set_itr(q_vector);
46544258 5874 else
047e0030 5875 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5876 }
5877
46544258
AD		 5878 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5879 if (adapter->msix_entries)
047e0030 5880 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5881 else
5882 igb_irq_enable(adapter);
5883 }
9d5c8243
AK		 5884}
5885
46544258
AD		 5886/**
5887 * igb_poll - NAPI Rx polling callback
5888 * @napi: napi polling structure
5889 * @budget: count of how many packets we should handle
5890 **/
5891static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5892{
047e0030
AD		 5893 struct igb_q_vector *q_vector = container_of(napi,
5894 struct igb_q_vector,
5895 napi);
16eb8815 5896 bool clean_complete = true;
9d5c8243 5897
421e02f0 5898#ifdef CONFIG_IGB_DCA
047e0030
AD		 5899 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5900 igb_update_dca(q_vector);
fe4506b6 5901#endif
0ba82994 5902 if (q_vector->tx.ring)
13fde97a 5903 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5904
0ba82994 5905 if (q_vector->rx.ring)
cd392f5c 5906 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5907
16eb8815
AD		 5908 /* If all work not completed, return budget and keep polling */
5909 if (!clean_complete)
5910 return budget;
46544258 5911
9d5c8243 5912 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5913 napi_complete(napi);
5914 igb_ring_irq_enable(q_vector);
9d5c8243 5915
16eb8815 5916 return 0;
9d5c8243 5917}
6d8126f9 5918
9d5c8243
AK		 5919/**
5920 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5921 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5922 *
9d5c8243
AK		 5923 * returns true if ring is completely cleaned
5924 **/
047e0030 5925static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5926{
047e0030 5927 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5928 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5929 struct igb_tx_buffer *tx_buffer;
f4128785 5930 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5931 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5932 unsigned int budget = q_vector->tx.work_limit;
8542db05 5933 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5934
13fde97a
AD		 5935 if (test_bit(__IGB_DOWN, &adapter->state))
5936 return true;
0e014cb1 5937
06034649 5938 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5939 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5940 i -= tx_ring->count;
9d5c8243 5941
f4128785
AD		 5942 do {
5943 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5944
5945 /* if next_to_watch is not set then there is no work pending */
5946 if (!eop_desc)
5947 break;
13fde97a 5948
f4128785 5949 /* prevent any other reads prior to eop_desc */
70d289bc 5950 read_barrier_depends();
f4128785 5951
13fde97a
AD		 5952 /* if DD is not set pending work has not been completed */
5953 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5954 break;
5955
8542db05
AD		 5956 /* clear next_to_watch to prevent false hangs */
5957 tx_buffer->next_to_watch = NULL;
9d5c8243 5958
ebe42d16
AD		 5959 /* update the statistics for this packet */
5960 total_bytes += tx_buffer->bytecount;
5961 total_packets += tx_buffer->gso_segs;
13fde97a 5962
ebe42d16
AD		 5963 /* free the skb */
5964 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5965
ebe42d16
AD		 5966 /* unmap skb header data */
5967 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5968 dma_unmap_addr(tx_buffer, dma),
5969 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5970 DMA_TO_DEVICE);
5971
c9f14bf3
AD		 5972 /* clear tx_buffer data */
5973 tx_buffer->skb = NULL;
5974 dma_unmap_len_set(tx_buffer, len, 0);
5975
ebe42d16
AD		 5976 /* clear last DMA location and unmap remaining buffers */
5977 while (tx_desc != eop_desc) {
13fde97a
AD		 5978 tx_buffer++;
5979 tx_desc++;
9d5c8243 5980 i++;
8542db05
AD		 5981 if (unlikely(!i)) {
5982 i -= tx_ring->count;
06034649 5983 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5984 tx_desc = IGB_TX_DESC(tx_ring, 0);
5985 }
ebe42d16
AD		 5986
5987 /* unmap any remaining paged data */
c9f14bf3 5988 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5989 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5990 dma_unmap_addr(tx_buffer, dma),
5991 dma_unmap_len(tx_buffer, len),
ebe42d16 5992 DMA_TO_DEVICE);
c9f14bf3 5993 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5994 }
5995 }
5996
ebe42d16
AD		 5997 /* move us one more past the eop_desc for start of next pkt */
5998 tx_buffer++;
5999 tx_desc++;
6000 i++;
6001 if (unlikely(!i)) {
6002 i -= tx_ring->count;
6003 tx_buffer = tx_ring->tx_buffer_info;
6004 tx_desc = IGB_TX_DESC(tx_ring, 0);
6005 }
f4128785
AD		 6006
6007 /* issue prefetch for next Tx descriptor */
6008 prefetch(tx_desc);
6009
6010 /* update budget accounting */
6011 budget--;
6012 } while (likely(budget));
0e014cb1 6013
bdbc0631
ED		 6014 netdev_tx_completed_queue(txring_txq(tx_ring),
6015 total_packets, total_bytes);
8542db05 6016 i += tx_ring->count;
9d5c8243 6017 tx_ring->next_to_clean = i;
13fde97a
AD		 6018 u64_stats_update_begin(&tx_ring->tx_syncp);
6019 tx_ring->tx_stats.bytes += total_bytes;
6020 tx_ring->tx_stats.packets += total_packets;
6021 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6022 q_vector->tx.total_bytes += total_bytes;
6023 q_vector->tx.total_packets += total_packets;
9d5c8243 6024
6d095fa8 6025 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6026 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6027
9d5c8243
AK		 6028 /* Detect a transmit hang in hardware, this serializes the
6029 * check with the clearing of time_stamp and movement of i */
6d095fa8 6030 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6031 if (tx_buffer->next_to_watch &&
8542db05 6032 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6033 (adapter->tx_timeout_factor * HZ)) &&
6034 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6035
9d5c8243 6036 /* detected Tx unit hang */
59d71989 6037 dev_err(tx_ring->dev,
9d5c8243 6038 "Detected Tx Unit Hang\n"
2d064c06 6039 " Tx Queue <%d>\n"
9d5c8243
AK		 6040 " TDH <%x>\n"
6041 " TDT <%x>\n"
6042 " next_to_use <%x>\n"
6043 " next_to_clean <%x>\n"
9d5c8243
AK		 6044 "buffer_info[next_to_clean]\n"
6045 " time_stamp <%lx>\n"
8542db05 6046 " next_to_watch <%p>\n"
9d5c8243
AK		 6047 " jiffies <%lx>\n"
6048 " desc.status <%x>\n",
2d064c06 6049 tx_ring->queue_index,
238ac817 6050 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6051 readl(tx_ring->tail),
9d5c8243
AK		 6052 tx_ring->next_to_use,
6053 tx_ring->next_to_clean,
8542db05 6054 tx_buffer->time_stamp,
f4128785 6055 tx_buffer->next_to_watch,
9d5c8243 6056 jiffies,
f4128785 6057 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6058 netif_stop_subqueue(tx_ring->netdev,
6059 tx_ring->queue_index);
6060
6061 /* we are about to reset, no point in enabling stuff */
6062 return true;
9d5c8243
AK		 6063 }
6064 }
13fde97a
AD		 6065
6066 if (unlikely(total_packets &&
6067 netif_carrier_ok(tx_ring->netdev) &&
6068 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
6069 /* Make sure that anybody stopping the queue after this
6070 * sees the new next_to_clean.
6071 */
6072 smp_mb();
6073 if (__netif_subqueue_stopped(tx_ring->netdev,
6074 tx_ring->queue_index) &&
6075 !(test_bit(__IGB_DOWN, &adapter->state))) {
6076 netif_wake_subqueue(tx_ring->netdev,
6077 tx_ring->queue_index);
6078
6079 u64_stats_update_begin(&tx_ring->tx_syncp);
6080 tx_ring->tx_stats.restart_queue++;
6081 u64_stats_update_end(&tx_ring->tx_syncp);
6082 }
6083 }
6084
6085 return !!budget;
9d5c8243
AK		 6086}
6087
cbc8e55f
AD		 6088/**
6089 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6090 * @rx_ring: rx descriptor ring to store buffers on
6091 * @old_buff: donor buffer to have page reused
6092 *
6093 * Synchronizes page for reuse by the adapter
6094 **/
6095static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6096 struct igb_rx_buffer *old_buff)
6097{
6098 struct igb_rx_buffer *new_buff;
6099 u16 nta = rx_ring->next_to_alloc;
6100
6101 new_buff = &rx_ring->rx_buffer_info[nta];
6102
6103 /* update, and store next to alloc */
6104 nta++;
6105 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6106
6107 /* transfer page from old buffer to new buffer */
6108 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6109
6110 /* sync the buffer for use by the device */
6111 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6112 old_buff->page_offset,
de78d1f9 6113 IGB_RX_BUFSZ,
cbc8e55f
AD		 6114 DMA_FROM_DEVICE);
6115}
6116
74e238ea
AD		 6117static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6118 struct page *page,
6119 unsigned int truesize)
6120{
6121 /* avoid re-using remote pages */
6122 if (unlikely(page_to_nid(page) != numa_node_id()))
6123 return false;
6124
6125#if (PAGE_SIZE < 8192)
6126 /* if we are only owner of page we can reuse it */
6127 if (unlikely(page_count(page) != 1))
6128 return false;
6129
6130 /* flip page offset to other buffer */
6131 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6132
6133 /* since we are the only owner of the page and we need to
6134 * increment it, just set the value to 2 in order to avoid
6135 * an unnecessary locked operation
6136 */
6137 atomic_set(&page->_count, 2);
6138#else
6139 /* move offset up to the next cache line */
6140 rx_buffer->page_offset += truesize;
6141
6142 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6143 return false;
6144
6145 /* bump ref count on page before it is given to the stack */
6146 get_page(page);
6147#endif
6148
6149 return true;
6150}
6151
cbc8e55f
AD		 6152/**
6153 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6154 * @rx_ring: rx descriptor ring to transact packets on
6155 * @rx_buffer: buffer containing page to add
6156 * @rx_desc: descriptor containing length of buffer written by hardware
6157 * @skb: sk_buff to place the data into
6158 *
6159 * This function will add the data contained in rx_buffer->page to the skb.
6160 * This is done either through a direct copy if the data in the buffer is
6161 * less than the skb header size, otherwise it will just attach the page as
6162 * a frag to the skb.
6163 *
6164 * The function will then update the page offset if necessary and return
6165 * true if the buffer can be reused by the adapter.
6166 **/
6167static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6168 struct igb_rx_buffer *rx_buffer,
6169 union e1000_adv_rx_desc *rx_desc,
6170 struct sk_buff *skb)
6171{
6172 struct page *page = rx_buffer->page;
6173 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6174#if (PAGE_SIZE < 8192)
6175 unsigned int truesize = IGB_RX_BUFSZ;
6176#else
6177 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6178#endif
cbc8e55f
AD		 6179
6180 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6181 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6182
cbc8e55f
AD		 6183 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6184 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6185 va += IGB_TS_HDR_LEN;
6186 size -= IGB_TS_HDR_LEN;
6187 }
6188
cbc8e55f
AD		 6189 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6190
6191 /* we can reuse buffer as-is, just make sure it is local */
6192 if (likely(page_to_nid(page) == numa_node_id()))
6193 return true;
6194
6195 /* this page cannot be reused so discard it */
6196 put_page(page);
6197 return false;
6198 }
6199
6200 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6201 rx_buffer->page_offset, size, truesize);
cbc8e55f 6202
74e238ea
AD		 6203 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6204}
cbc8e55f 6205
74e238ea
AD		 6206static struct sk_buff *igb_build_rx_buffer(struct igb_ring *rx_ring,
6207 union e1000_adv_rx_desc *rx_desc)
6208{
6209 struct igb_rx_buffer *rx_buffer;
6210 struct sk_buff *skb;
6211 struct page *page;
6212 void *page_addr;
6213 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
de78d1f9 6214#if (PAGE_SIZE < 8192)
74e238ea
AD		 6215 unsigned int truesize = IGB_RX_BUFSZ;
6216#else
6217 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
6218 SKB_DATA_ALIGN(NET_SKB_PAD +
6219 NET_IP_ALIGN +
6220 size);
6221#endif
cbc8e55f 6222
74e238ea
AD		 6223 /* If we spanned a buffer we have a huge mess so test for it */
6224 BUG_ON(unlikely(!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)));
cbc8e55f 6225
74e238ea
AD		 6226 /* Guarantee this function can be used by verifying buffer sizes */
6227 BUILD_BUG_ON(SKB_WITH_OVERHEAD(IGB_RX_BUFSZ) < (NET_SKB_PAD +
6228 NET_IP_ALIGN +
6229 IGB_TS_HDR_LEN +
6230 ETH_FRAME_LEN +
6231 ETH_FCS_LEN));
de78d1f9 6232
74e238ea
AD		 6233 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6234 page = rx_buffer->page;
6235 prefetchw(page);
de78d1f9 6236
74e238ea
AD		 6237 page_addr = page_address(page) + rx_buffer->page_offset;
6238
6239 /* prefetch first cache line of first page */
6240 prefetch(page_addr + NET_SKB_PAD + NET_IP_ALIGN);
6241#if L1_CACHE_BYTES < 128
6242 prefetch(page_addr + L1_CACHE_BYTES + NET_SKB_PAD + NET_IP_ALIGN);
de78d1f9 6243#endif
cbc8e55f 6244
74e238ea
AD		 6245 /* build an skb to around the page buffer */
6246 skb = build_skb(page_addr, truesize);
6247 if (unlikely(!skb)) {
6248 rx_ring->rx_stats.alloc_failed++;
6249 return NULL;
6250 }
6251
6252 /* we are reusing so sync this buffer for CPU use */
6253 dma_sync_single_range_for_cpu(rx_ring->dev,
6254 rx_buffer->dma,
6255 rx_buffer->page_offset,
6256 IGB_RX_BUFSZ,
6257 DMA_FROM_DEVICE);
6258
6259 /* update pointers within the skb to store the data */
6260 skb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD);
6261 __skb_put(skb, size);
6262
6263 /* pull timestamp out of packet data */
6264 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6265 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);
6266 __skb_pull(skb, IGB_TS_HDR_LEN);
6267 }
6268
6269 if (igb_can_reuse_rx_page(rx_buffer, page, truesize)) {
6270 /* hand second half of page back to the ring */
6271 igb_reuse_rx_page(rx_ring, rx_buffer);
6272 } else {
6273 /* we are not reusing the buffer so unmap it */
6274 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6275 PAGE_SIZE, DMA_FROM_DEVICE);
6276 }
6277
6278 /* clear contents of buffer_info */
6279 rx_buffer->dma = 0;
6280 rx_buffer->page = NULL;
6281
6282 return skb;
cbc8e55f
AD		 6283}
6284
2e334eee
AD		 6285static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6286 union e1000_adv_rx_desc *rx_desc,
6287 struct sk_buff *skb)
6288{
6289 struct igb_rx_buffer *rx_buffer;
6290 struct page *page;
6291
6292 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6293
2e334eee
AD		 6294 page = rx_buffer->page;
6295 prefetchw(page);
6296
6297 if (likely(!skb)) {
6298 void *page_addr = page_address(page) +
6299 rx_buffer->page_offset;
6300
6301 /* prefetch first cache line of first page */
6302 prefetch(page_addr);
6303#if L1_CACHE_BYTES < 128
6304 prefetch(page_addr + L1_CACHE_BYTES);
6305#endif
6306
6307 /* allocate a skb to store the frags */
6308 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6309 IGB_RX_HDR_LEN);
6310 if (unlikely(!skb)) {
6311 rx_ring->rx_stats.alloc_failed++;
6312 return NULL;
6313 }
6314
6315 /*
6316 * we will be copying header into skb->data in
6317 * pskb_may_pull so it is in our interest to prefetch
6318 * it now to avoid a possible cache miss
6319 */
6320 prefetchw(skb->data);
6321 }
6322
6323 /* we are reusing so sync this buffer for CPU use */
6324 dma_sync_single_range_for_cpu(rx_ring->dev,
6325 rx_buffer->dma,
6326 rx_buffer->page_offset,
de78d1f9 6327 IGB_RX_BUFSZ,
2e334eee
AD		 6328 DMA_FROM_DEVICE);
6329
6330 /* pull page into skb */
6331 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6332 /* hand second half of page back to the ring */
6333 igb_reuse_rx_page(rx_ring, rx_buffer);
6334 } else {
6335 /* we are not reusing the buffer so unmap it */
6336 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6337 PAGE_SIZE, DMA_FROM_DEVICE);
6338 }
6339
6340 /* clear contents of rx_buffer */
6341 rx_buffer->page = NULL;
6342
6343 return skb;
6344}
6345
cd392f5c 6346static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6347 union e1000_adv_rx_desc *rx_desc,
6348 struct sk_buff *skb)
9d5c8243 6349{
bc8acf2c 6350 skb_checksum_none_assert(skb);
9d5c8243 6351
294e7d78 6352 /* Ignore Checksum bit is set */
3ceb90fd 6353 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6354 return;
6355
6356 /* Rx checksum disabled via ethtool */
6357 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6358 return;
85ad76b2 6359
9d5c8243 6360 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6361 if (igb_test_staterr(rx_desc,
6362 E1000_RXDEXT_STATERR_TCPE |
6363 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6364 /*
6365 * work around errata with sctp packets where the TCPE aka
6366 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6367 * packets, (aka let the stack check the crc32c)
6368 */
866cff06
AD		 6369 if (!((skb->len == 60) &&
6370 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6371 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6372 ring->rx_stats.csum_err++;
12dcd86b
ED		 6373 u64_stats_update_end(&ring->rx_syncp);
6374 }
9d5c8243 6375 /* let the stack verify checksum errors */
9d5c8243
AK		 6376 return;
6377 }
6378 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6379 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6380 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6381 skb->ip_summed = CHECKSUM_UNNECESSARY;
6382
3ceb90fd
AD		 6383 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6384 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6385}
6386
077887c3
AD		 6387static inline void igb_rx_hash(struct igb_ring *ring,
6388 union e1000_adv_rx_desc *rx_desc,
6389 struct sk_buff *skb)
6390{
6391 if (ring->netdev->features & NETIF_F_RXHASH)
6392 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6393}
6394
2e334eee
AD		 6395/**
6396 * igb_is_non_eop - process handling of non-EOP buffers
6397 * @rx_ring: Rx ring being processed
6398 * @rx_desc: Rx descriptor for current buffer
6399 * @skb: current socket buffer containing buffer in progress
6400 *
6401 * This function updates next to clean. If the buffer is an EOP buffer
6402 * this function exits returning false, otherwise it will place the
6403 * sk_buff in the next buffer to be chained and return true indicating
6404 * that this is in fact a non-EOP buffer.
6405 **/
6406static bool igb_is_non_eop(struct igb_ring *rx_ring,
6407 union e1000_adv_rx_desc *rx_desc)
6408{
6409 u32 ntc = rx_ring->next_to_clean + 1;
6410
6411 /* fetch, update, and store next to clean */
6412 ntc = (ntc < rx_ring->count) ? ntc : 0;
6413 rx_ring->next_to_clean = ntc;
6414
6415 prefetch(IGB_RX_DESC(rx_ring, ntc));
6416
6417 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6418 return false;
6419
6420 return true;
6421}
6422
1a1c225b
AD		 6423/**
6424 * igb_get_headlen - determine size of header for LRO/GRO
6425 * @data: pointer to the start of the headers
6426 * @max_len: total length of section to find headers in
6427 *
6428 * This function is meant to determine the length of headers that will
6429 * be recognized by hardware for LRO, and GRO offloads. The main
6430 * motivation of doing this is to only perform one pull for IPv4 TCP
6431 * packets so that we can do basic things like calculating the gso_size
6432 * based on the average data per packet.
6433 **/
6434static unsigned int igb_get_headlen(unsigned char *data,
6435 unsigned int max_len)
6436{
6437 union {
6438 unsigned char *network;
6439 /* l2 headers */
6440 struct ethhdr *eth;
6441 struct vlan_hdr *vlan;
6442 /* l3 headers */
6443 struct iphdr *ipv4;
6444 struct ipv6hdr *ipv6;
6445 } hdr;
6446 __be16 protocol;
6447 u8 nexthdr = 0; /* default to not TCP */
6448 u8 hlen;
6449
6450 /* this should never happen, but better safe than sorry */
6451 if (max_len < ETH_HLEN)
6452 return max_len;
6453
6454 /* initialize network frame pointer */
6455 hdr.network = data;
6456
6457 /* set first protocol and move network header forward */
6458 protocol = hdr.eth->h_proto;
6459 hdr.network += ETH_HLEN;
6460
6461 /* handle any vlan tag if present */
6462 if (protocol == __constant_htons(ETH_P_8021Q)) {
6463 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6464 return max_len;
6465
6466 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6467 hdr.network += VLAN_HLEN;
6468 }
6469
6470 /* handle L3 protocols */
6471 if (protocol == __constant_htons(ETH_P_IP)) {
6472 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6473 return max_len;
6474
6475 /* access ihl as a u8 to avoid unaligned access on ia64 */
6476 hlen = (hdr.network[0] & 0x0F) << 2;
6477
6478 /* verify hlen meets minimum size requirements */
6479 if (hlen < sizeof(struct iphdr))
6480 return hdr.network - data;
6481
f2fb4ab2
AD		 6482 /* record next protocol if header is present */
6483 if (!hdr.ipv4->frag_off)
6484 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6485 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6486 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6487 return max_len;
6488
6489 /* record next protocol */
6490 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6491 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6492 } else {
6493 return hdr.network - data;
6494 }
6495
f2fb4ab2
AD		 6496 /* relocate pointer to start of L4 header */
6497 hdr.network += hlen;
6498
1a1c225b
AD		 6499 /* finally sort out TCP */
6500 if (nexthdr == IPPROTO_TCP) {
6501 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6502 return max_len;
6503
6504 /* access doff as a u8 to avoid unaligned access on ia64 */
6505 hlen = (hdr.network[12] & 0xF0) >> 2;
6506
6507 /* verify hlen meets minimum size requirements */
6508 if (hlen < sizeof(struct tcphdr))
6509 return hdr.network - data;
6510
6511 hdr.network += hlen;
6512 } else if (nexthdr == IPPROTO_UDP) {
6513 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6514 return max_len;
6515
6516 hdr.network += sizeof(struct udphdr);
6517 }
6518
6519 /*
6520 * If everything has gone correctly hdr.network should be the
6521 * data section of the packet and will be the end of the header.
6522 * If not then it probably represents the end of the last recognized
6523 * header.
6524 */
6525 if ((hdr.network - data) < max_len)
6526 return hdr.network - data;
6527 else
6528 return max_len;
6529}
6530
6531/**
6532 * igb_pull_tail - igb specific version of skb_pull_tail
6533 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6534 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6535 * @skb: pointer to current skb being adjusted
6536 *
6537 * This function is an igb specific version of __pskb_pull_tail. The
6538 * main difference between this version and the original function is that
6539 * this function can make several assumptions about the state of things
6540 * that allow for significant optimizations versus the standard function.
6541 * As a result we can do things like drop a frag and maintain an accurate
6542 * truesize for the skb.
6543 */
6544static void igb_pull_tail(struct igb_ring *rx_ring,
6545 union e1000_adv_rx_desc *rx_desc,
6546 struct sk_buff *skb)
2d94d8ab 6547{
1a1c225b
AD		 6548 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6549 unsigned char *va;
6550 unsigned int pull_len;
6551
6552 /*
6553 * it is valid to use page_address instead of kmap since we are
6554 * working with pages allocated out of the lomem pool per
6555 * alloc_page(GFP_ATOMIC)
2d94d8ab 6556 */
1a1c225b
AD		 6557 va = skb_frag_address(frag);
6558
1a1c225b
AD		 6559 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6560 /* retrieve timestamp from buffer */
6561 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6562
6563 /* update pointers to remove timestamp header */
6564 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6565 frag->page_offset += IGB_TS_HDR_LEN;
6566 skb->data_len -= IGB_TS_HDR_LEN;
6567 skb->len -= IGB_TS_HDR_LEN;
6568
6569 /* move va to start of packet data */
6570 va += IGB_TS_HDR_LEN;
6571 }
6572
1a1c225b
AD		 6573 /*
6574 * we need the header to contain the greater of either ETH_HLEN or
6575 * 60 bytes if the skb->len is less than 60 for skb_pad.
6576 */
6577 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6578
6579 /* align pull length to size of long to optimize memcpy performance */
6580 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6581
6582 /* update all of the pointers */
6583 skb_frag_size_sub(frag, pull_len);
6584 frag->page_offset += pull_len;
6585 skb->data_len -= pull_len;
6586 skb->tail += pull_len;
6587}
6588
6589/**
6590 * igb_cleanup_headers - Correct corrupted or empty headers
6591 * @rx_ring: rx descriptor ring packet is being transacted on
6592 * @rx_desc: pointer to the EOP Rx descriptor
6593 * @skb: pointer to current skb being fixed
6594 *
6595 * Address the case where we are pulling data in on pages only
6596 * and as such no data is present in the skb header.
6597 *
6598 * In addition if skb is not at least 60 bytes we need to pad it so that
6599 * it is large enough to qualify as a valid Ethernet frame.
6600 *
6601 * Returns true if an error was encountered and skb was freed.
6602 **/
6603static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6604 union e1000_adv_rx_desc *rx_desc,
6605 struct sk_buff *skb)
6606{
6607
6608 if (unlikely((igb_test_staterr(rx_desc,
6609 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6610 struct net_device *netdev = rx_ring->netdev;
6611 if (!(netdev->features & NETIF_F_RXALL)) {
6612 dev_kfree_skb_any(skb);
6613 return true;
6614 }
6615 }
6616
6617 /* place header in linear portion of buffer */
6618 if (skb_is_nonlinear(skb))
6619 igb_pull_tail(rx_ring, rx_desc, skb);
6620
6621 /* if skb_pad returns an error the skb was freed */
6622 if (unlikely(skb->len < 60)) {
6623 int pad_len = 60 - skb->len;
6624
6625 if (skb_pad(skb, pad_len))
6626 return true;
6627 __skb_put(skb, pad_len);
6628 }
6629
6630 return false;
2d94d8ab
AD		 6631}
6632
db2ee5bd
AD		 6633/**
6634 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6635 * @rx_ring: rx descriptor ring packet is being transacted on
6636 * @rx_desc: pointer to the EOP Rx descriptor
6637 * @skb: pointer to current skb being populated
6638 *
6639 * This function checks the ring, descriptor, and packet information in
6640 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6641 * other fields within the skb.
6642 **/
6643static void igb_process_skb_fields(struct igb_ring *rx_ring,
6644 union e1000_adv_rx_desc *rx_desc,
6645 struct sk_buff *skb)
6646{
6647 struct net_device *dev = rx_ring->netdev;
6648
6649 igb_rx_hash(rx_ring, rx_desc, skb);
6650
6651 igb_rx_checksum(rx_ring, rx_desc, skb);
6652
db2ee5bd 6653 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6654
6655 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6656 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6657 u16 vid;
6658 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6659 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6660 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6661 else
6662 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6663
6664 __vlan_hwaccel_put_tag(skb, vid);
6665 }
6666
6667 skb_record_rx_queue(skb, rx_ring->queue_index);
6668
6669 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6670}
6671
2e334eee 6672static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6673{
0ba82994 6674 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6675 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6676 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6677 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6678
2e334eee
AD		 6679 do {
6680 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6681
2e334eee
AD		 6682 /* return some buffers to hardware, one at a time is too slow */
6683 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6684 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6685 cleaned_count = 0;
6686 }
bf36c1a0 6687
2e334eee 6688 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6689
2e334eee
AD		 6690 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6691 break;
9d5c8243 6692
74e238ea
AD		 6693 /* This memory barrier is needed to keep us from reading
6694 * any other fields out of the rx_desc until we know the
6695 * RXD_STAT_DD bit is set
6696 */
6697 rmb();
6698
2e334eee 6699 /* retrieve a buffer from the ring */
74e238ea
AD		 6700 if (ring_uses_build_skb(rx_ring))
6701 skb = igb_build_rx_buffer(rx_ring, rx_desc);
6702 else
6703 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6704
2e334eee
AD		 6705 /* exit if we failed to retrieve a buffer */
6706 if (!skb)
6707 break;
1a1c225b 6708
2e334eee 6709 cleaned_count++;
1a1c225b 6710
2e334eee
AD		 6711 /* fetch next buffer in frame if non-eop */
6712 if (igb_is_non_eop(rx_ring, rx_desc))
6713 continue;
1a1c225b
AD		 6714
6715 /* verify the packet layout is correct */
6716 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6717 skb = NULL;
6718 continue;
9d5c8243 6719 }
9d5c8243 6720
db2ee5bd 6721 /* probably a little skewed due to removing CRC */
3ceb90fd 6722 total_bytes += skb->len;
3ceb90fd 6723
db2ee5bd
AD		 6724 /* populate checksum, timestamp, VLAN, and protocol */
6725 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6726
b2cb09b1 6727 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6728
1a1c225b
AD		 6729 /* reset skb pointer */
6730 skb = NULL;
6731
2e334eee
AD		 6732 /* update budget accounting */
6733 total_packets++;
6734 } while (likely(total_packets < budget));
bf36c1a0 6735
1a1c225b
AD		 6736 /* place incomplete frames back on ring for completion */
6737 rx_ring->skb = skb;
6738
12dcd86b 6739 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6740 rx_ring->rx_stats.packets += total_packets;
6741 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6742 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6743 q_vector->rx.total_packets += total_packets;
6744 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6745
6746 if (cleaned_count)
cd392f5c 6747 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6748
2e334eee 6749 return (total_packets < budget);
9d5c8243
AK		 6750}
6751
c023cd88 6752static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6753 struct igb_rx_buffer *bi)
c023cd88
AD		 6754{
6755 struct page *page = bi->page;
cbc8e55f 6756 dma_addr_t dma;
c023cd88 6757
cbc8e55f
AD		 6758 /* since we are recycling buffers we should seldom need to alloc */
6759 if (likely(page))
c023cd88
AD		 6760 return true;
6761
cbc8e55f
AD		 6762 /* alloc new page for storage */
6763 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6764 if (unlikely(!page)) {
6765 rx_ring->rx_stats.alloc_failed++;
6766 return false;
c023cd88
AD		 6767 }
6768
cbc8e55f
AD		 6769 /* map page for use */
6770 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6771
cbc8e55f
AD		 6772 /*
6773 * if mapping failed free memory back to system since
6774 * there isn't much point in holding memory we can't use
6775 */
1a1c225b 6776 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6777 __free_page(page);
6778
c023cd88
AD		 6779 rx_ring->rx_stats.alloc_failed++;
6780 return false;
6781 }
6782
1a1c225b 6783 bi->dma = dma;
cbc8e55f
AD		 6784 bi->page = page;
6785 bi->page_offset = 0;
1a1c225b 6786
c023cd88
AD		 6787 return true;
6788}
6789
74e238ea
AD		 6790static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring)
6791{
6792 if (ring_uses_build_skb(rx_ring))
6793 return NET_SKB_PAD + NET_IP_ALIGN;
6794 else
6795 return 0;
6796}
6797
9d5c8243 6798/**
cd392f5c 6799 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6800 * @adapter: address of board private structure
6801 **/
cd392f5c 6802void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6803{
9d5c8243 6804 union e1000_adv_rx_desc *rx_desc;
06034649 6805 struct igb_rx_buffer *bi;
c023cd88 6806 u16 i = rx_ring->next_to_use;
9d5c8243 6807
cbc8e55f
AD		 6808 /* nothing to do */
6809 if (!cleaned_count)
6810 return;
6811
60136906 6812 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6813 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6814 i -= rx_ring->count;
9d5c8243 6815
cbc8e55f 6816 do {
1a1c225b 6817 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6818 break;
9d5c8243 6819
cbc8e55f
AD		 6820 /*
6821 * Refresh the desc even if buffer_addrs didn't change
6822 * because each write-back erases this info.
6823 */
74e238ea
AD		 6824 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma +
6825 bi->page_offset +
6826 igb_rx_offset(rx_ring));
9d5c8243 6827
c023cd88
AD		 6828 rx_desc++;
6829 bi++;
9d5c8243 6830 i++;
c023cd88 6831 if (unlikely(!i)) {
60136906 6832 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6833 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6834 i -= rx_ring->count;
6835 }
6836
6837 /* clear the hdr_addr for the next_to_use descriptor */
6838 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6839
6840 cleaned_count--;
6841 } while (cleaned_count);
9d5c8243 6842
c023cd88
AD		 6843 i += rx_ring->count;
6844
9d5c8243 6845 if (rx_ring->next_to_use != i) {
cbc8e55f 6846 /* record the next descriptor to use */
9d5c8243 6847 rx_ring->next_to_use = i;
9d5c8243 6848
cbc8e55f
AD		 6849 /* update next to alloc since we have filled the ring */
6850 rx_ring->next_to_alloc = i;
6851
6852 /*
6853 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6854 * know there are new descriptors to fetch. (Only
6855 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6856 * such as IA-64).
6857 */
9d5c8243 6858 wmb();
fce99e34 6859 writel(i, rx_ring->tail);
9d5c8243
AK		 6860 }
6861}
6862
6863/**
6864 * igb_mii_ioctl -
6865 * @netdev:
6866 * @ifreq:
6867 * @cmd:
6868 **/
6869static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6870{
6871 struct igb_adapter *adapter = netdev_priv(netdev);
6872 struct mii_ioctl_data *data = if_mii(ifr);
6873
6874 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6875 return -EOPNOTSUPP;
6876
6877 switch (cmd) {
6878 case SIOCGMIIPHY:
6879 data->phy_id = adapter->hw.phy.addr;
6880 break;
6881 case SIOCGMIIREG:
f5f4cf08
AD		 6882 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6883 &data->val_out))
9d5c8243
AK		 6884 return -EIO;
6885 break;
6886 case SIOCSMIIREG:
6887 default:
6888 return -EOPNOTSUPP;
6889 }
6890 return 0;
6891}
6892
6893/**
6894 * igb_ioctl -
6895 * @netdev:
6896 * @ifreq:
6897 * @cmd:
6898 **/
6899static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6900{
6901 switch (cmd) {
6902 case SIOCGMIIPHY:
6903 case SIOCGMIIREG:
6904 case SIOCSMIIREG:
6905 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6906 case SIOCSHWTSTAMP:
a79f4f88 6907 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6908 default:
6909 return -EOPNOTSUPP;
6910 }
6911}
6912
009bc06e
AD		 6913s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6914{
6915 struct igb_adapter *adapter = hw->back;
009bc06e 6916
23d028cc 6917 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6918 return -E1000_ERR_CONFIG;
6919
009bc06e
AD		 6920 return 0;
6921}
6922
6923s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6924{
6925 struct igb_adapter *adapter = hw->back;
009bc06e 6926
23d028cc 6927 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6928 return -E1000_ERR_CONFIG;
6929
009bc06e
AD		 6930 return 0;
6931}
6932
c8f44aff 6933static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6934{
6935 struct igb_adapter *adapter = netdev_priv(netdev);
6936 struct e1000_hw *hw = &adapter->hw;
6937 u32 ctrl, rctl;
5faf030c 6938 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6939
5faf030c 6940 if (enable) {
9d5c8243
AK		 6941 /* enable VLAN tag insert/strip */
6942 ctrl = rd32(E1000_CTRL);
6943 ctrl |= E1000_CTRL_VME;
6944 wr32(E1000_CTRL, ctrl);
6945
51466239 6946 /* Disable CFI check */
9d5c8243 6947 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6948 rctl &= ~E1000_RCTL_CFIEN;
6949 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6950 } else {
6951 /* disable VLAN tag insert/strip */
6952 ctrl = rd32(E1000_CTRL);
6953 ctrl &= ~E1000_CTRL_VME;
6954 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6955 }
6956
e1739522 6957 igb_rlpml_set(adapter);
9d5c8243
AK		 6958}
6959
8e586137 6960static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6961{
6962 struct igb_adapter *adapter = netdev_priv(netdev);
6963 struct e1000_hw *hw = &adapter->hw;
4ae196df 6964 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6965
51466239
AD		 6966 /* attempt to add filter to vlvf array */
6967 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6968
51466239
AD		 6969 /* add the filter since PF can receive vlans w/o entry in vlvf */
6970 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6971
6972 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6973
6974 return 0;
9d5c8243
AK		 6975}
6976
8e586137 6977static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6978{
6979 struct igb_adapter *adapter = netdev_priv(netdev);
6980 struct e1000_hw *hw = &adapter->hw;
4ae196df 6981 int pf_id = adapter->vfs_allocated_count;
51466239 6982 s32 err;
9d5c8243 6983
51466239
AD		 6984 /* remove vlan from VLVF table array */
6985 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6986
51466239
AD		 6987 /* if vid was not present in VLVF just remove it from table */
6988 if (err)
4ae196df 6989 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6990
6991 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6992
6993 return 0;
9d5c8243
AK		 6994}
6995
6996static void igb_restore_vlan(struct igb_adapter *adapter)
6997{
b2cb09b1 6998 u16 vid;
9d5c8243 6999
5faf030c
AD		 7000 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7001
b2cb09b1
JP		 7002 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7003 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 7004}
7005
14ad2513 7006int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7007{
090b1795 7008 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7009 struct e1000_mac_info *mac = &adapter->hw.mac;
7010
7011 mac->autoneg = 0;
7012
14ad2513
DD		 7013 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7014 * for the switch() below to work */
7015 if ((spd & 1) || (dplx & ~1))
7016 goto err_inval;
7017
cd2638a8
CW		 7018 /* Fiber NIC's only allow 1000 Gbps Full duplex */
7019 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 7020 spd != SPEED_1000 &&
7021 dplx != DUPLEX_FULL)
7022 goto err_inval;
cd2638a8 7023
14ad2513 7024 switch (spd + dplx) {
9d5c8243
AK		 7025 case SPEED_10 + DUPLEX_HALF:
7026 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7027 break;
7028 case SPEED_10 + DUPLEX_FULL:
7029 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7030 break;
7031 case SPEED_100 + DUPLEX_HALF:
7032 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7033 break;
7034 case SPEED_100 + DUPLEX_FULL:
7035 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7036 break;
7037 case SPEED_1000 + DUPLEX_FULL:
7038 mac->autoneg = 1;
7039 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7040 break;
7041 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7042 default:
14ad2513 7043 goto err_inval;
9d5c8243 7044 }
8376dad0
JB		 7045
7046 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7047 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7048
9d5c8243 7049 return 0;
14ad2513
DD		 7050
7051err_inval:
7052 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7053 return -EINVAL;
9d5c8243
AK		 7054}
7055
749ab2cd
YZ		 7056static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7057 bool runtime)
9d5c8243
AK		 7058{
7059 struct net_device *netdev = pci_get_drvdata(pdev);
7060 struct igb_adapter *adapter = netdev_priv(netdev);
7061 struct e1000_hw *hw = &adapter->hw;
2d064c06 7062 u32 ctrl, rctl, status;
749ab2cd 7063 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7064#ifdef CONFIG_PM
7065 int retval = 0;
7066#endif
7067
7068 netif_device_detach(netdev);
7069
a88f10ec 7070 if (netif_running(netdev))
749ab2cd 7071 __igb_close(netdev, true);
a88f10ec 7072
047e0030 7073 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7074
7075#ifdef CONFIG_PM
7076 retval = pci_save_state(pdev);
7077 if (retval)
7078 return retval;
7079#endif
7080
7081 status = rd32(E1000_STATUS);
7082 if (status & E1000_STATUS_LU)
7083 wufc &= ~E1000_WUFC_LNKC;
7084
7085 if (wufc) {
7086 igb_setup_rctl(adapter);
ff41f8dc 7087 igb_set_rx_mode(netdev);
9d5c8243
AK		 7088
7089 /* turn on all-multi mode if wake on multicast is enabled */
7090 if (wufc & E1000_WUFC_MC) {
7091 rctl = rd32(E1000_RCTL);
7092 rctl |= E1000_RCTL_MPE;
7093 wr32(E1000_RCTL, rctl);
7094 }
7095
7096 ctrl = rd32(E1000_CTRL);
7097 /* advertise wake from D3Cold */
7098 #define E1000_CTRL_ADVD3WUC 0x00100000
7099 /* phy power management enable */
7100 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7101 ctrl |= E1000_CTRL_ADVD3WUC;
7102 wr32(E1000_CTRL, ctrl);
7103
9d5c8243 7104 /* Allow time for pending master requests to run */
330a6d6a 7105 igb_disable_pcie_master(hw);
9d5c8243
AK		 7106
7107 wr32(E1000_WUC, E1000_WUC_PME_EN);
7108 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7109 } else {
7110 wr32(E1000_WUC, 0);
7111 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7112 }
7113
3fe7c4c9
RW		 7114 *enable_wake = wufc || adapter->en_mng_pt;
7115 if (!*enable_wake)
88a268c1
NN		 7116 igb_power_down_link(adapter);
7117 else
7118 igb_power_up_link(adapter);
9d5c8243
AK		 7119
7120 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7121 * would have already happened in close and is redundant. */
7122 igb_release_hw_control(adapter);
7123
7124 pci_disable_device(pdev);
7125
9d5c8243
AK		 7126 return 0;
7127}
7128
7129#ifdef CONFIG_PM
d9dd966d 7130#ifdef CONFIG_PM_SLEEP
749ab2cd 7131static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7132{
7133 int retval;
7134 bool wake;
749ab2cd 7135 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7136
749ab2cd 7137 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7138 if (retval)
7139 return retval;
7140
7141 if (wake) {
7142 pci_prepare_to_sleep(pdev);
7143 } else {
7144 pci_wake_from_d3(pdev, false);
7145 pci_set_power_state(pdev, PCI_D3hot);
7146 }
7147
7148 return 0;
7149}
d9dd966d 7150#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7151
749ab2cd 7152static int igb_resume(struct device *dev)
9d5c8243 7153{
749ab2cd 7154 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7155 struct net_device *netdev = pci_get_drvdata(pdev);
7156 struct igb_adapter *adapter = netdev_priv(netdev);
7157 struct e1000_hw *hw = &adapter->hw;
7158 u32 err;
7159
7160 pci_set_power_state(pdev, PCI_D0);
7161 pci_restore_state(pdev);
b94f2d77 7162 pci_save_state(pdev);
42bfd33a 7163
aed5dec3 7164 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7165 if (err) {
7166 dev_err(&pdev->dev,
7167 "igb: Cannot enable PCI device from suspend\n");
7168 return err;
7169 }
7170 pci_set_master(pdev);
7171
7172 pci_enable_wake(pdev, PCI_D3hot, 0);
7173 pci_enable_wake(pdev, PCI_D3cold, 0);
7174
53c7d064 7175 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7176 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7177 return -ENOMEM;
9d5c8243
AK		 7178 }
7179
9d5c8243 7180 igb_reset(adapter);
a8564f03
AD		 7181
7182 /* let the f/w know that the h/w is now under the control of the
7183 * driver. */
7184 igb_get_hw_control(adapter);
7185
9d5c8243
AK		 7186 wr32(E1000_WUS, ~0);
7187
749ab2cd 7188 if (netdev->flags & IFF_UP) {
0c2cc02e 7189 rtnl_lock();
749ab2cd 7190 err = __igb_open(netdev, true);
0c2cc02e 7191 rtnl_unlock();
a88f10ec
AD		 7192 if (err)
7193 return err;
7194 }
9d5c8243
AK		 7195
7196 netif_device_attach(netdev);
749ab2cd
YZ		 7197 return 0;
7198}
7199
7200#ifdef CONFIG_PM_RUNTIME
7201static int igb_runtime_idle(struct device *dev)
7202{
7203 struct pci_dev *pdev = to_pci_dev(dev);
7204 struct net_device *netdev = pci_get_drvdata(pdev);
7205 struct igb_adapter *adapter = netdev_priv(netdev);
7206
7207 if (!igb_has_link(adapter))
7208 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7209
7210 return -EBUSY;
7211}
7212
7213static int igb_runtime_suspend(struct device *dev)
7214{
7215 struct pci_dev *pdev = to_pci_dev(dev);
7216 int retval;
7217 bool wake;
7218
7219 retval = __igb_shutdown(pdev, &wake, 1);
7220 if (retval)
7221 return retval;
7222
7223 if (wake) {
7224 pci_prepare_to_sleep(pdev);
7225 } else {
7226 pci_wake_from_d3(pdev, false);
7227 pci_set_power_state(pdev, PCI_D3hot);
7228 }
9d5c8243 7229
9d5c8243
AK		 7230 return 0;
7231}
749ab2cd
YZ		 7232
7233static int igb_runtime_resume(struct device *dev)
7234{
7235 return igb_resume(dev);
7236}
7237#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7238#endif
7239
7240static void igb_shutdown(struct pci_dev *pdev)
7241{
3fe7c4c9
RW		 7242 bool wake;
7243
749ab2cd 7244 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7245
7246 if (system_state == SYSTEM_POWER_OFF) {
7247 pci_wake_from_d3(pdev, wake);
7248 pci_set_power_state(pdev, PCI_D3hot);
7249 }
9d5c8243
AK		 7250}
7251
fa44f2f1
GR		 7252#ifdef CONFIG_PCI_IOV
7253static int igb_sriov_reinit(struct pci_dev *dev)
7254{
7255 struct net_device *netdev = pci_get_drvdata(dev);
7256 struct igb_adapter *adapter = netdev_priv(netdev);
7257 struct pci_dev *pdev = adapter->pdev;
7258
7259 rtnl_lock();
7260
7261 if (netif_running(netdev))
7262 igb_close(netdev);
7263
7264 igb_clear_interrupt_scheme(adapter);
7265
7266 igb_init_queue_configuration(adapter);
7267
7268 if (igb_init_interrupt_scheme(adapter, true)) {
7269 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7270 return -ENOMEM;
7271 }
7272
7273 if (netif_running(netdev))
7274 igb_open(netdev);
7275
7276 rtnl_unlock();
7277
7278 return 0;
7279}
7280
7281static int igb_pci_disable_sriov(struct pci_dev *dev)
7282{
7283 int err = igb_disable_sriov(dev);
7284
7285 if (!err)
7286 err = igb_sriov_reinit(dev);
7287
7288 return err;
7289}
7290
7291static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7292{
7293 int err = igb_enable_sriov(dev, num_vfs);
7294
7295 if (err)
7296 goto out;
7297
7298 err = igb_sriov_reinit(dev);
7299 if (!err)
7300 return num_vfs;
7301
7302out:
7303 return err;
7304}
7305
7306#endif
7307static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7308{
7309#ifdef CONFIG_PCI_IOV
7310 if (num_vfs == 0)
7311 return igb_pci_disable_sriov(dev);
7312 else
7313 return igb_pci_enable_sriov(dev, num_vfs);
7314#endif
7315 return 0;
7316}
7317
9d5c8243
AK		 7318#ifdef CONFIG_NET_POLL_CONTROLLER
7319/*
7320 * Polling 'interrupt' - used by things like netconsole to send skbs
7321 * without having to re-enable interrupts. It's not called while
7322 * the interrupt routine is executing.
7323 */
7324static void igb_netpoll(struct net_device *netdev)
7325{
7326 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7327 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7328 struct igb_q_vector *q_vector;
9d5c8243 7329 int i;
9d5c8243 7330
047e0030 7331 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7332 q_vector = adapter->q_vector[i];
7333 if (adapter->msix_entries)
7334 wr32(E1000_EIMC, q_vector->eims_value);
7335 else
7336 igb_irq_disable(adapter);
047e0030 7337 napi_schedule(&q_vector->napi);
eebbbdba 7338 }
9d5c8243
AK		 7339}
7340#endif /* CONFIG_NET_POLL_CONTROLLER */
7341
7342/**
7343 * igb_io_error_detected - called when PCI error is detected
7344 * @pdev: Pointer to PCI device
7345 * @state: The current pci connection state
7346 *
7347 * This function is called after a PCI bus error affecting
7348 * this device has been detected.
7349 */
7350static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7351 pci_channel_state_t state)
7352{
7353 struct net_device *netdev = pci_get_drvdata(pdev);
7354 struct igb_adapter *adapter = netdev_priv(netdev);
7355
7356 netif_device_detach(netdev);
7357
59ed6eec
AD		 7358 if (state == pci_channel_io_perm_failure)
7359 return PCI_ERS_RESULT_DISCONNECT;
7360
9d5c8243
AK		 7361 if (netif_running(netdev))
7362 igb_down(adapter);
7363 pci_disable_device(pdev);
7364
7365 /* Request a slot slot reset. */
7366 return PCI_ERS_RESULT_NEED_RESET;
7367}
7368
7369/**
7370 * igb_io_slot_reset - called after the pci bus has been reset.
7371 * @pdev: Pointer to PCI device
7372 *
7373 * Restart the card from scratch, as if from a cold-boot. Implementation
7374 * resembles the first-half of the igb_resume routine.
7375 */
7376static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7377{
7378 struct net_device *netdev = pci_get_drvdata(pdev);
7379 struct igb_adapter *adapter = netdev_priv(netdev);
7380 struct e1000_hw *hw = &adapter->hw;
40a914fa 7381 pci_ers_result_t result;
42bfd33a 7382 int err;
9d5c8243 7383
aed5dec3 7384 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7385 dev_err(&pdev->dev,
7386 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7387 result = PCI_ERS_RESULT_DISCONNECT;
7388 } else {
7389 pci_set_master(pdev);
7390 pci_restore_state(pdev);
b94f2d77 7391 pci_save_state(pdev);
9d5c8243 7392
40a914fa
AD		 7393 pci_enable_wake(pdev, PCI_D3hot, 0);
7394 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7395
40a914fa
AD		 7396 igb_reset(adapter);
7397 wr32(E1000_WUS, ~0);
7398 result = PCI_ERS_RESULT_RECOVERED;
7399 }
9d5c8243 7400
ea943d41
JK		 7401 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7402 if (err) {
7403 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7404 "failed 0x%0x\n", err);
7405 /* non-fatal, continue */
7406 }
40a914fa
AD		 7407
7408 return result;
9d5c8243
AK		 7409}
7410
7411/**
7412 * igb_io_resume - called when traffic can start flowing again.
7413 * @pdev: Pointer to PCI device
7414 *
7415 * This callback is called when the error recovery driver tells us that
7416 * its OK to resume normal operation. Implementation resembles the
7417 * second-half of the igb_resume routine.
7418 */
7419static void igb_io_resume(struct pci_dev *pdev)
7420{
7421 struct net_device *netdev = pci_get_drvdata(pdev);
7422 struct igb_adapter *adapter = netdev_priv(netdev);
7423
9d5c8243
AK		 7424 if (netif_running(netdev)) {
7425 if (igb_up(adapter)) {
7426 dev_err(&pdev->dev, "igb_up failed after reset\n");
7427 return;
7428 }
7429 }
7430
7431 netif_device_attach(netdev);
7432
7433 /* let the f/w know that the h/w is now under the control of the
7434 * driver. */
7435 igb_get_hw_control(adapter);
9d5c8243
AK		 7436}
7437
26ad9178
AD		 7438static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7439 u8 qsel)
7440{
7441 u32 rar_low, rar_high;
7442 struct e1000_hw *hw = &adapter->hw;
7443
7444 /* HW expects these in little endian so we reverse the byte order
7445 * from network order (big endian) to little endian
7446 */
7447 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7448 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7449 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7450
7451 /* Indicate to hardware the Address is Valid. */
7452 rar_high |= E1000_RAH_AV;
7453
7454 if (hw->mac.type == e1000_82575)
7455 rar_high |= E1000_RAH_POOL_1 * qsel;
7456 else
7457 rar_high |= E1000_RAH_POOL_1 << qsel;
7458
7459 wr32(E1000_RAL(index), rar_low);
7460 wrfl();
7461 wr32(E1000_RAH(index), rar_high);
7462 wrfl();
7463}
7464
4ae196df
AD		 7465static int igb_set_vf_mac(struct igb_adapter *adapter,
7466 int vf, unsigned char *mac_addr)
7467{
7468 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7469 /* VF MAC addresses start at end of receive addresses and moves
7470 * torwards the first, as a result a collision should not be possible */
7471 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7472
37680117 7473 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7474
26ad9178 7475 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7476
7477 return 0;
7478}
7479
8151d294
WM		 7480static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7481{
7482 struct igb_adapter *adapter = netdev_priv(netdev);
7483 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7484 return -EINVAL;
7485 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7486 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7487 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7488 " change effective.");
7489 if (test_bit(__IGB_DOWN, &adapter->state)) {
7490 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7491 " but the PF device is not up.\n");
7492 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7493 " attempting to use the VF device.\n");
7494 }
7495 return igb_set_vf_mac(adapter, vf, mac);
7496}
7497
17dc566c
LL		 7498static int igb_link_mbps(int internal_link_speed)
7499{
7500 switch (internal_link_speed) {
7501 case SPEED_100:
7502 return 100;
7503 case SPEED_1000:
7504 return 1000;
7505 default:
7506 return 0;
7507 }
7508}
7509
7510static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7511 int link_speed)
7512{
7513 int rf_dec, rf_int;
7514 u32 bcnrc_val;
7515
7516 if (tx_rate != 0) {
7517 /* Calculate the rate factor values to set */
7518 rf_int = link_speed / tx_rate;
7519 rf_dec = (link_speed - (rf_int * tx_rate));
7520 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7521
7522 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7523 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7524 E1000_RTTBCNRC_RF_INT_MASK);
7525 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7526 } else {
7527 bcnrc_val = 0;
7528 }
7529
7530 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7531 /*
7532 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7533 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7534 */
7535 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7536 wr32(E1000_RTTBCNRC, bcnrc_val);
7537}
7538
7539static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7540{
7541 int actual_link_speed, i;
7542 bool reset_rate = false;
7543
7544 /* VF TX rate limit was not set or not supported */
7545 if ((adapter->vf_rate_link_speed == 0) ||
7546 (adapter->hw.mac.type != e1000_82576))
7547 return;
7548
7549 actual_link_speed = igb_link_mbps(adapter->link_speed);
7550 if (actual_link_speed != adapter->vf_rate_link_speed) {
7551 reset_rate = true;
7552 adapter->vf_rate_link_speed = 0;
7553 dev_info(&adapter->pdev->dev,
7554 "Link speed has been changed. VF Transmit "
7555 "rate is disabled\n");
7556 }
7557
7558 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7559 if (reset_rate)
7560 adapter->vf_data[i].tx_rate = 0;
7561
7562 igb_set_vf_rate_limit(&adapter->hw, i,
7563 adapter->vf_data[i].tx_rate,
7564 actual_link_speed);
7565 }
7566}
7567
8151d294
WM		 7568static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7569{
17dc566c
LL		 7570 struct igb_adapter *adapter = netdev_priv(netdev);
7571 struct e1000_hw *hw = &adapter->hw;
7572 int actual_link_speed;
7573
7574 if (hw->mac.type != e1000_82576)
7575 return -EOPNOTSUPP;
7576
7577 actual_link_speed = igb_link_mbps(adapter->link_speed);
7578 if ((vf >= adapter->vfs_allocated_count) ||
7579 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7580 (tx_rate < 0) || (tx_rate > actual_link_speed))
7581 return -EINVAL;
7582
7583 adapter->vf_rate_link_speed = actual_link_speed;
7584 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7585 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7586
7587 return 0;
8151d294
WM		 7588}
7589
7590static int igb_ndo_get_vf_config(struct net_device *netdev,
7591 int vf, struct ifla_vf_info *ivi)
7592{
7593 struct igb_adapter *adapter = netdev_priv(netdev);
7594 if (vf >= adapter->vfs_allocated_count)
7595 return -EINVAL;
7596 ivi->vf = vf;
7597 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7598 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7599 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7600 ivi->qos = adapter->vf_data[vf].pf_qos;
7601 return 0;
7602}
7603
4ae196df
AD		 7604static void igb_vmm_control(struct igb_adapter *adapter)
7605{
7606 struct e1000_hw *hw = &adapter->hw;
10d8e907 7607 u32 reg;
4ae196df 7608
52a1dd4d
AD		 7609 switch (hw->mac.type) {
7610 case e1000_82575:
f96a8a0b
CW		 7611 case e1000_i210:
7612 case e1000_i211:
52a1dd4d
AD		 7613 default:
7614 /* replication is not supported for 82575 */
4ae196df 7615 return;
52a1dd4d
AD		 7616 case e1000_82576:
7617 /* notify HW that the MAC is adding vlan tags */
7618 reg = rd32(E1000_DTXCTL);
7619 reg |= E1000_DTXCTL_VLAN_ADDED;
7620 wr32(E1000_DTXCTL, reg);
7621 case e1000_82580:
7622 /* enable replication vlan tag stripping */
7623 reg = rd32(E1000_RPLOLR);
7624 reg |= E1000_RPLOLR_STRVLAN;
7625 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7626 case e1000_i350:
7627 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7628 break;
7629 }
10d8e907 7630
d4960307
AD		 7631 if (adapter->vfs_allocated_count) {
7632 igb_vmdq_set_loopback_pf(hw, true);
7633 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7634 igb_vmdq_set_anti_spoofing_pf(hw, true,
7635 adapter->vfs_allocated_count);
d4960307
AD		 7636 } else {
7637 igb_vmdq_set_loopback_pf(hw, false);
7638 igb_vmdq_set_replication_pf(hw, false);
7639 }
4ae196df
AD		 7640}
7641
b6e0c419
CW		 7642static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7643{
7644 struct e1000_hw *hw = &adapter->hw;
7645 u32 dmac_thr;
7646 u16 hwm;
7647
7648 if (hw->mac.type > e1000_82580) {
7649 if (adapter->flags & IGB_FLAG_DMAC) {
7650 u32 reg;
7651
7652 /* force threshold to 0. */
7653 wr32(E1000_DMCTXTH, 0);
7654
7655 /*
e8c626e9
MV		 7656 * DMA Coalescing high water mark needs to be greater
7657 * than the Rx threshold. Set hwm to PBA - max frame
7658 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7659 */
e8c626e9
MV		 7660 hwm = 64 * pba - adapter->max_frame_size / 16;
7661 if (hwm < 64 * (pba - 6))
7662 hwm = 64 * (pba - 6);
7663 reg = rd32(E1000_FCRTC);
7664 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7665 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7666 & E1000_FCRTC_RTH_COAL_MASK);
7667 wr32(E1000_FCRTC, reg);
7668
7669 /*
7670 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7671 * frame size, capping it at PBA - 10KB.
7672 */
7673 dmac_thr = pba - adapter->max_frame_size / 512;
7674 if (dmac_thr < pba - 10)
7675 dmac_thr = pba - 10;
b6e0c419
CW		 7676 reg = rd32(E1000_DMACR);
7677 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7678 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7679 & E1000_DMACR_DMACTHR_MASK);
7680
7681 /* transition to L0x or L1 if available..*/
7682 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7683
7684 /* watchdog timer= +-1000 usec in 32usec intervals */
7685 reg |= (1000 >> 5);
0c02dd98
MV		 7686
7687 /* Disable BMC-to-OS Watchdog Enable */
7688 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7689 wr32(E1000_DMACR, reg);
7690
7691 /*
7692 * no lower threshold to disable
7693 * coalescing(smart fifb)-UTRESH=0
7694 */
7695 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7696
7697 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7698
7699 wr32(E1000_DMCTLX, reg);
7700
7701 /*
7702 * free space in tx packet buffer to wake from
7703 * DMA coal
7704 */
7705 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7706 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7707
7708 /*
7709 * make low power state decision controlled
7710 * by DMA coal
7711 */
7712 reg = rd32(E1000_PCIEMISC);
7713 reg &= ~E1000_PCIEMISC_LX_DECISION;
7714 wr32(E1000_PCIEMISC, reg);
7715 } /* endif adapter->dmac is not disabled */
7716 } else if (hw->mac.type == e1000_82580) {
7717 u32 reg = rd32(E1000_PCIEMISC);
7718 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7719 wr32(E1000_DMACR, 0);
7720 }
7721}
7722
441fc6fd
CW		 7723static DEFINE_SPINLOCK(i2c_clients_lock);
7724
7725/* igb_get_i2c_client - returns matching client
7726 * in adapters's client list.
7727 * @adapter: adapter struct
7728 * @dev_addr: device address of i2c needed.
7729 */
2c7d7724 7730static struct i2c_client *
441fc6fd
CW		 7731igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr)
7732{
7733 ulong flags;
7734 struct igb_i2c_client_list *client_list;
7735 struct i2c_client *client = NULL;
7736 struct i2c_board_info client_info = {
7737 I2C_BOARD_INFO("igb", 0x00),
7738 };
7739
7740 spin_lock_irqsave(&i2c_clients_lock, flags);
7741 client_list = adapter->i2c_clients;
7742
7743 /* See if we already have an i2c_client */
7744 while (client_list) {
7745 if (client_list->client->addr == (dev_addr >> 1)) {
7746 client = client_list->client;
7747 goto exit;
7748 } else {
7749 client_list = client_list->next;
7750 }
7751 }
7752
d3f8ef11 7753 /* no client_list found, create a new one */
199f6cca 7754 client_list = kzalloc(sizeof(*client_list), GFP_ATOMIC);
441fc6fd
CW		 7755 if (client_list == NULL)
7756 goto exit;
7757
7758 /* dev_addr passed to us is left-shifted by 1 bit
7759 * i2c_new_device call expects it to be flush to the right.
7760 */
7761 client_info.addr = dev_addr >> 1;
7762 client_info.platform_data = adapter;
7763 client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info);
7764 if (client_list->client == NULL) {
e428893b
CW		 7765 dev_info(&adapter->pdev->dev,
7766 "Failed to create new i2c device..\n");
441fc6fd
CW		 7767 goto err_no_client;
7768 }
7769
7770 /* insert new client at head of list */
7771 client_list->next = adapter->i2c_clients;
7772 adapter->i2c_clients = client_list;
7773
441fc6fd
CW		 7774 client = client_list->client;
7775 goto exit;
7776
7777err_no_client:
7778 kfree(client_list);
7779exit:
7780 spin_unlock_irqrestore(&i2c_clients_lock, flags);
7781 return client;
7782}
7783
7784/* igb_read_i2c_byte - Reads 8 bit word over I2C
7785 * @hw: pointer to hardware structure
7786 * @byte_offset: byte offset to read
7787 * @dev_addr: device address
7788 * @data: value read
7789 *
7790 * Performs byte read operation over I2C interface at
7791 * a specified device address.
7792 */
7793s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7794 u8 dev_addr, u8 *data)
7795{
7796 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7797 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7798 s32 status;
7799 u16 swfw_mask = 0;
7800
7801 if (!this_client)
7802 return E1000_ERR_I2C;
7803
7804 swfw_mask = E1000_SWFW_PHY0_SM;
7805
7806 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7807 != E1000_SUCCESS)
7808 return E1000_ERR_SWFW_SYNC;
7809
7810 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7811 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7812
7813 if (status < 0)
7814 return E1000_ERR_I2C;
7815 else {
7816 *data = status;
7817 return E1000_SUCCESS;
7818 }
7819}
7820
7821/* igb_write_i2c_byte - Writes 8 bit word over I2C
7822 * @hw: pointer to hardware structure
7823 * @byte_offset: byte offset to write
7824 * @dev_addr: device address
7825 * @data: value to write
7826 *
7827 * Performs byte write operation over I2C interface at
7828 * a specified device address.
7829 */
7830s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7831 u8 dev_addr, u8 data)
7832{
7833 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7834 struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7835 s32 status;
7836 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7837
7838 if (!this_client)
7839 return E1000_ERR_I2C;
7840
7841 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7842 return E1000_ERR_SWFW_SYNC;
7843 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7844 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7845
7846 if (status)
7847 return E1000_ERR_I2C;
7848 else
7849 return E1000_SUCCESS;
7850
7851}
9d5c8243 7852/* igb_main.c */
kernel source for telekom puls (alcatel/mediatek)