[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
                                           (hw->mac.type > e1000_82575 ? 8 : 4))
#define IGB_ABS_MAX_TX_QUEUES              8
#define IGB_MAX_TX_QUEUES                  IGB_MAX_RX_QUEUES

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_64    64     /* Used for packet split */
#define IGB_RXBUFFER_128   128    /* Used for packet split */
#define IGB_RXBUFFER_1024  1024
#define IGB_RXBUFFER_2048  2048
#define IGB_RXBUFFER_16384 16384

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
			unsigned int bytecount;
			u16 gso_segs;
			u8 tx_flags;
			u8 mapped_as_page;
		};
		/* RX */
		struct {
			struct page *page;
			dma_addr_t page_dma;
			u16 page_offset;
		};
	};
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector; /* backlink to q_vector */
	struct net_device *netdev;     /* back pointer to net_device */
	struct device *dev;            /* device pointer for dma mapping */
	dma_addr_t dma;                /* phys address of the ring */
	void *desc;                    /* descriptor ring memory */
	unsigned int size;             /* length of desc. ring in bytes */
	u16 count;                     /* number of desc. in the ring */
	u16 next_to_use;
	u16 next_to_clean;
	u8 queue_index;
	u8 reg_idx;
	void __iomem *head;
	void __iomem *tail;
	struct igb_buffer *buffer_info; /* array of buffer info structs */

	unsigned int total_bytes;
	unsigned int total_packets;

	u32 flags;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
			u32 rx_buffer_len;
		};
	};
};

#define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
#define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */

#define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */

#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)

#define E1000_RX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
#define E1000_TX_DESC_ADV(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
#define E1000_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* TX */
	struct igb_ring *tx_ring[16];
	u32 tx_timeout_count;

	/* RX */
	struct igb_ring *rx_ring[16];
	int num_tx_queues;
	int num_rx_queues;

	u32 max_frame_size;
	u32 min_frame_size;

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	unsigned int num_q_vectors;
	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	unsigned long state;
	unsigned int flags;
	u32 eeprom_wol;

	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
#define IGB_FLAG_DMAC              (1 << 4)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE           20408
#define IGB_TX_BUF_4096            4096
#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_buffer *);
extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4297f99b	4	Copyright(c) 2007-2011 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
38c845c7	42
9d5c8243 AK	43	struct igb_adapter;
9d5c8243 AK	44
6eb5a7f1 AD	45	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	46	#define IGB_START_ITR 648
9d5c8243	47
9d5c8243 AK	48	/* TX/RX descriptor defines */
	49	#define IGB_DEFAULT_TXD 256
	50	#define IGB_MIN_TXD 80
	51	#define IGB_MAX_TXD 4096
	52
	53	#define IGB_DEFAULT_RXD 256
	54	#define IGB_MIN_RXD 80
	55	#define IGB_MAX_RXD 4096
	56
	57	#define IGB_DEFAULT_ITR 3 /* dynamic */
	58	#define IGB_MAX_ITR_USECS 10000
	59	#define IGB_MIN_ITR_USECS 10
047e0030 AD	60	#define NON_Q_VECTORS 1
047e0030 AD	61	#define MAX_Q_VECTORS 8
9d5c8243 AK	62
9d5c8243 AK	63	/* Transmit and receive queues */
a99955fc AD	64	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
	65	(hw->mac.type > e1000_82575 ? 8 : 4))
	66	#define IGB_ABS_MAX_TX_QUEUES 8
	67	#define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
9d5c8243	68
4ae196df AD	69	#define IGB_MAX_VF_MC_ENTRIES 30
	70	#define IGB_MAX_VF_FUNCTIONS 8
	71	#define IGB_MAX_VFTA_ENTRIES 128
	72
	73	struct vf_data_storage {
	74	unsigned char vf_mac_addresses[ETH_ALEN];
	75	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	76	u16 num_vf_mc_hashes;
ae641bdc	77	u16 vlans_enabled;
f2ca0dbe AD	78	u32 flags;
f2ca0dbe AD	79	unsigned long last_nack;
8151d294 WM	80	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	81	u16 pf_qos;
17dc566c	82	u16 tx_rate;
4ae196df AD	83	};
4ae196df AD	84
f2ca0dbe	85	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	86	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	87	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	88	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	89
9d5c8243 AK	90	/* RX descriptor control thresholds.
	91	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	92	* descriptors available in its onboard memory.
	93	* Setting this to 0 disables RX descriptor prefetch.
	94	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	95	* available in host memory.
	96	* If PTHRESH is 0, this should also be 0.
	97	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	98	* descriptors until either it has this many to write back, or the
	99	* ITR timer expires.
	100	*/
58fd62f5	101	#define IGB_RX_PTHRESH 8
9d5c8243	102	#define IGB_RX_HTHRESH 8
85b430b4 AD	103	#define IGB_TX_PTHRESH 8
85b430b4 AD	104	#define IGB_TX_HTHRESH 1
a74420e0 AD	105	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0 AD	106	adapter->msix_entries) ? 1 : 4)
85b430b4	107	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0	108	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	109
	110	/* this is the size past which hardware will drop packets when setting LPE=0 */
	111	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	112
	113	/* Supported Rx Buffer Sizes */
757b77e2	114	#define IGB_RXBUFFER_64 64 /* Used for packet split */
9d5c8243	115	#define IGB_RXBUFFER_128 128 /* Used for packet split */
9d5c8243 AK	116	#define IGB_RXBUFFER_1024 1024
9d5c8243 AK	117	#define IGB_RXBUFFER_2048 2048
9d5c8243 AK	118	#define IGB_RXBUFFER_16384 16384
9d5c8243 AK	119
9d5c8243 AK	120	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	121	#define IGB_TX_QUEUE_WAKE 16
	122	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	123	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	124
	125	#define AUTO_ALL_MODES 0
	126	#define IGB_EEPROM_APME 0x0400
	127
	128	#ifndef IGB_MASTER_SLAVE
	129	/* Switch to override PHY master/slave setting */
	130	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	131	#endif
	132
	133	#define IGB_MNG_VLAN_NONE -1
	134
	135	/* wrapper around a pointer to a socket buffer,
	136	* so a DMA handle can be stored along with the buffer */
	137	struct igb_buffer {
	138	struct sk_buff *skb;
	139	dma_addr_t dma;
	140	union {
	141	/* TX */
	142	struct {
	143	unsigned long time_stamp;
0e014cb1 AD	144	u16 length;
0e014cb1 AD	145	u16 next_to_watch;
2873957d	146	unsigned int bytecount;
40e90c26	147	u16 gso_segs;
2244d07b	148	u8 tx_flags;
2873957d	149	u8 mapped_as_page;
9d5c8243 AK	150	};
	151	/* RX */
	152	struct {
	153	struct page *page;
6366ad33 AD	154	dma_addr_t page_dma;
6366ad33 AD	155	u16 page_offset;
9d5c8243 AK	156	};
	157	};
	158	};
	159
8c0ab70a	160	struct igb_tx_queue_stats {
9d5c8243 AK	161	u64 packets;
9d5c8243 AK	162	u64 bytes;
04a5fcaa	163	u64 restart_queue;
12dcd86b	164	u64 restart_queue2;
9d5c8243 AK	165	};
9d5c8243 AK	166
8c0ab70a JDB	167	struct igb_rx_queue_stats {
	168	u64 packets;
	169	u64 bytes;
	170	u64 drops;
04a5fcaa AD	171	u64 csum_err;
04a5fcaa AD	172	u64 alloc_failed;
8c0ab70a JDB	173	};
8c0ab70a JDB	174
047e0030	175	struct igb_q_vector {
9d5c8243	176	struct igb_adapter adapter; / backlink */
047e0030 AD	177	struct igb_ring *rx_ring;
	178	struct igb_ring *tx_ring;
	179	struct napi_struct napi;
	180
	181	u32 eims_value;
	182	u16 cpu;
	183
	184	u16 itr_val;
	185	u8 set_itr;
047e0030 AD	186	void __iomem *itr_register;
	187
	188	char name[IFNAMSIZ + 9];
	189	};
	190
	191	struct igb_ring {
	192	struct igb_q_vector q_vector; / backlink to q_vector */
e694e964	193	struct net_device netdev; / back pointer to net_device */
59d71989	194	struct device dev; / device pointer for dma mapping */
047e0030	195	dma_addr_t dma; /* phys address of the ring */
e694e964	196	void desc; / descriptor ring memory */
047e0030	197	unsigned int size; /* length of desc. ring in bytes */
2e5655e7	198	u16 count; /* number of desc. in the ring */
9d5c8243 AK	199	u16 next_to_use;
9d5c8243 AK	200	u16 next_to_clean;
2e5655e7 AD	201	u8 queue_index;
2e5655e7 AD	202	u8 reg_idx;
fce99e34 AD	203	void __iomem *head;
fce99e34 AD	204	void __iomem *tail;
9d5c8243 AK	205	struct igb_buffer buffer_info; / array of buffer info structs */
9d5c8243 AK	206
9d5c8243 AK	207	unsigned int total_bytes;
	208	unsigned int total_packets;
	209
85ad76b2 AD	210	u32 flags;
85ad76b2 AD	211
9d5c8243 AK	212	union {
	213	/* TX */
	214	struct {
8c0ab70a	215	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	216	struct u64_stats_sync tx_syncp;
12dcd86b ED	217	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	218	bool detect_tx_hung;
	219	};
	220	/* RX */
	221	struct {
8c0ab70a	222	struct igb_rx_queue_stats rx_stats;
12dcd86b	223	struct u64_stats_sync rx_syncp;
4c844851	224	u32 rx_buffer_len;
9d5c8243 AK	225	};
9d5c8243 AK	226	};
9d5c8243 AK	227	};
9d5c8243 AK	228
85ad76b2 AD	229	#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
	230	#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
	231
	232	#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
	233
	234	#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP \| E1000_TXD_CMD_RS)
	235
9d5c8243 AK	236	#define E1000_RX_DESC_ADV(R, i) \
	237	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
	238	#define E1000_TX_DESC_ADV(R, i) \
	239	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
	240	#define E1000_TX_CTXTDESC_ADV(R, i) \
	241	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
9d5c8243	242
d7ee5b3a AD	243	/* igb_desc_unused - calculate if we have unused descriptors */
	244	static inline int igb_desc_unused(struct igb_ring *ring)
	245	{
	246	if (ring->next_to_clean > ring->next_to_use)
	247	return ring->next_to_clean - ring->next_to_use - 1;
	248
	249	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	250	}
	251
9d5c8243	252	/* board specific private data structure */
9d5c8243 AK	253	struct igb_adapter {
	254	struct timer_list watchdog_timer;
	255	struct timer_list phy_info_timer;
b2cb09b1	256	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9d5c8243 AK	257	u16 mng_vlan_id;
9d5c8243 AK	258	u32 bd_number;
9d5c8243 AK	259	u32 wol;
	260	u32 en_mng_pt;
	261	u16 link_speed;
	262	u16 link_duplex;
2e5655e7	263
9d5c8243	264	/* Interrupt Throttle Rate */
4fc82adf AD	265	u32 rx_itr_setting;
4fc82adf AD	266	u32 tx_itr_setting;
9d5c8243 AK	267	u16 tx_itr;
9d5c8243 AK	268	u16 rx_itr;
9d5c8243 AK	269
	270	struct work_struct reset_task;
	271	struct work_struct watchdog_task;
	272	bool fc_autoneg;
	273	u8 tx_timeout_factor;
	274	struct timer_list blink_timer;
	275	unsigned long led_status;
	276
	277	/* TX */
3025a446	278	struct igb_ring *tx_ring[16];
9d5c8243 AK	279	u32 tx_timeout_count;
	280
	281	/* RX */
3025a446	282	struct igb_ring *rx_ring[16];
9d5c8243 AK	283	int num_tx_queues;
	284	int num_rx_queues;
	285
9d5c8243 AK	286	u32 max_frame_size;
	287	u32 min_frame_size;
	288
	289	/* OS defined structs */
	290	struct net_device *netdev;
9d5c8243	291	struct pci_dev *pdev;
38c845c7 PO	292	struct cyclecounter cycles;
38c845c7 PO	293	struct timecounter clock;
33af6bcc PO	294	struct timecompare compare;
33af6bcc PO	295	struct hwtstamp_config hwtstamp_config;
9d5c8243	296
12dcd86b ED	297	spinlock_t stats64_lock;
	298	struct rtnl_link_stats64 stats64;
	299
9d5c8243 AK	300	/* structs defined in e1000_hw.h */
	301	struct e1000_hw hw;
	302	struct e1000_hw_stats stats;
	303	struct e1000_phy_info phy_info;
	304	struct e1000_phy_stats phy_stats;
	305
	306	u32 test_icr;
	307	struct igb_ring test_tx_ring;
	308	struct igb_ring test_rx_ring;
	309
	310	int msg_enable;
047e0030 AD	311
	312	unsigned int num_q_vectors;
	313	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243 AK	314	struct msix_entry *msix_entries;
9d5c8243 AK	315	u32 eims_enable_mask;
844290e5	316	u32 eims_other;
9d5c8243 AK	317
	318	/* to not mess up cache alignment, always add to the bottom */
	319	unsigned long state;
7dfc16fa	320	unsigned int flags;
9d5c8243	321	u32 eeprom_wol;
42bfd33a	322
1bfaf07b	323	struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
2e5655e7 AD	324	u16 tx_ring_count;
2e5655e7 AD	325	u16 rx_ring_count;
1bfaf07b	326	unsigned int vfs_allocated_count;
4ae196df	327	struct vf_data_storage *vf_data;
17dc566c	328	int vf_rate_link_speed;
a99955fc	329	u32 rss_queues;
13800469	330	u32 wvbr;
9d5c8243 AK	331	};
9d5c8243 AK	332
7dfc16fa	333	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	334	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	335	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
4fc82adf	336	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
831ec0b4 CW	337	#define IGB_FLAG_DMAC (1 << 4)
	338
	339	/* DMA Coalescing defines */
	340	#define IGB_MIN_TXPBSIZE 20408
	341	#define IGB_TX_BUF_4096 4096
	342	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	343
c5b9bd5e	344	#define IGB_82576_TSYNC_SHIFT 19
55cac248	345	#define IGB_82580_TSYNC_SHIFT 24
757b77e2	346	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	347	enum e1000_state_t {
	348	__IGB_TESTING,
	349	__IGB_RESETTING,
	350	__IGB_DOWN
	351	};
	352
	353	enum igb_boards {
	354	board_82575,
	355	};
	356
	357	extern char igb_driver_name[];
	358	extern char igb_driver_version[];
	359
9d5c8243 AK	360	extern int igb_up(struct igb_adapter *);
	361	extern void igb_down(struct igb_adapter *);
	362	extern void igb_reinit_locked(struct igb_adapter *);
	363	extern void igb_reset(struct igb_adapter *);
14ad2513	364	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	365	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	366	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	367	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	368	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	369	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	370	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	371	extern void igb_setup_tctl(struct igb_adapter *);
	372	extern void igb_setup_rctl(struct igb_adapter *);
b1a436c3 AD	373	extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff , struct igb_ring );
	374	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
	375	struct igb_buffer *);
d7ee5b3a	376	extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
12dcd86b	377	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	378	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	379	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	380	extern void igb_power_up_link(struct igb_adapter *);
9d5c8243	381
f5f4cf08 AD	382	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	383	{
a8d2a0c2 AD	384	if (hw->phy.ops.reset)
a8d2a0c2 AD	385	return hw->phy.ops.reset(hw);
f5f4cf08 AD	386
	387	return 0;
	388	}
	389
	390	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	391	{
a8d2a0c2 AD	392	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	393	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	394
	395	return 0;
	396	}
	397
	398	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	399	{
a8d2a0c2 AD	400	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	401	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	402
	403	return 0;
	404	}
	405
	406	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	407	{
	408	if (hw->phy.ops.get_phy_info)
	409	return hw->phy.ops.get_phy_info(hw);
	410
	411	return 0;
	412	}
	413
9d5c8243	414	#endif /* _IGB_H_ */