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7f12ad74 GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
7f12ad74 GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
7f12ad74 GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
7ed3f5f0 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
7ed3f5f0 | 29 | |
7f12ad74 | 30 | #include "i40evf.h" |
ed0980c4 | 31 | #include "i40e_trace.h" |
206812b5 | 32 | #include "i40e_prototype.h" |
7f12ad74 GR |
33 | |
34 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
35 | u32 td_tag) | |
36 | { | |
37 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
38 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
39 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
40 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
41 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
42 | } | |
43 | ||
44 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) | |
45 | ||
46 | /** | |
47 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer | |
48 | * @ring: the ring that owns the buffer | |
49 | * @tx_buffer: the buffer to free | |
50 | **/ | |
51 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, | |
52 | struct i40e_tx_buffer *tx_buffer) | |
53 | { | |
54 | if (tx_buffer->skb) { | |
64bfd68e AD |
55 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
56 | kfree(tx_buffer->raw_buf); | |
57 | else | |
58 | dev_kfree_skb_any(tx_buffer->skb); | |
7f12ad74 GR |
59 | if (dma_unmap_len(tx_buffer, len)) |
60 | dma_unmap_single(ring->dev, | |
61 | dma_unmap_addr(tx_buffer, dma), | |
62 | dma_unmap_len(tx_buffer, len), | |
63 | DMA_TO_DEVICE); | |
64 | } else if (dma_unmap_len(tx_buffer, len)) { | |
65 | dma_unmap_page(ring->dev, | |
66 | dma_unmap_addr(tx_buffer, dma), | |
67 | dma_unmap_len(tx_buffer, len), | |
68 | DMA_TO_DEVICE); | |
69 | } | |
a42e7a36 | 70 | |
7f12ad74 GR |
71 | tx_buffer->next_to_watch = NULL; |
72 | tx_buffer->skb = NULL; | |
73 | dma_unmap_len_set(tx_buffer, len, 0); | |
74 | /* tx_buffer must be completely set up in the transmit path */ | |
75 | } | |
76 | ||
77 | /** | |
78 | * i40evf_clean_tx_ring - Free any empty Tx buffers | |
79 | * @tx_ring: ring to be cleaned | |
80 | **/ | |
81 | void i40evf_clean_tx_ring(struct i40e_ring *tx_ring) | |
82 | { | |
83 | unsigned long bi_size; | |
84 | u16 i; | |
85 | ||
86 | /* ring already cleared, nothing to do */ | |
87 | if (!tx_ring->tx_bi) | |
88 | return; | |
89 | ||
90 | /* Free all the Tx ring sk_buffs */ | |
91 | for (i = 0; i < tx_ring->count; i++) | |
92 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
93 | ||
94 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
95 | memset(tx_ring->tx_bi, 0, bi_size); | |
96 | ||
97 | /* Zero out the descriptor ring */ | |
98 | memset(tx_ring->desc, 0, tx_ring->size); | |
99 | ||
100 | tx_ring->next_to_use = 0; | |
101 | tx_ring->next_to_clean = 0; | |
102 | ||
103 | if (!tx_ring->netdev) | |
104 | return; | |
105 | ||
106 | /* cleanup Tx queue statistics */ | |
e486bdfd | 107 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
7f12ad74 GR |
108 | } |
109 | ||
110 | /** | |
111 | * i40evf_free_tx_resources - Free Tx resources per queue | |
112 | * @tx_ring: Tx descriptor ring for a specific queue | |
113 | * | |
114 | * Free all transmit software resources | |
115 | **/ | |
116 | void i40evf_free_tx_resources(struct i40e_ring *tx_ring) | |
117 | { | |
118 | i40evf_clean_tx_ring(tx_ring); | |
119 | kfree(tx_ring->tx_bi); | |
120 | tx_ring->tx_bi = NULL; | |
121 | ||
122 | if (tx_ring->desc) { | |
123 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
124 | tx_ring->desc, tx_ring->dma); | |
125 | tx_ring->desc = NULL; | |
126 | } | |
127 | } | |
128 | ||
a68de58d | 129 | /** |
9c6c1259 KP |
130 | * i40evf_get_tx_pending - how many Tx descriptors not processed |
131 | * @tx_ring: the ring of descriptors | |
dd353109 | 132 | * @in_sw: is tx_pending being checked in SW or HW |
a68de58d | 133 | * |
9c6c1259 KP |
134 | * Since there is no access to the ring head register |
135 | * in XL710, we need to use our local copies | |
a68de58d | 136 | **/ |
dd353109 | 137 | u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
a68de58d | 138 | { |
9c6c1259 | 139 | u32 head, tail; |
a68de58d | 140 | |
b1cb07db | 141 | head = ring->next_to_clean; |
9c6c1259 KP |
142 | tail = readl(ring->tail); |
143 | ||
144 | if (head != tail) | |
145 | return (head < tail) ? | |
146 | tail - head : (tail + ring->count - head); | |
147 | ||
148 | return 0; | |
a68de58d JB |
149 | } |
150 | ||
1dc8b538 | 151 | #define WB_STRIDE 4 |
c29af37f | 152 | |
7f12ad74 GR |
153 | /** |
154 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
155 | * @vsi: the VSI we care about |
156 | * @tx_ring: Tx ring to clean | |
157 | * @napi_budget: Used to determine if we are in netpoll | |
7f12ad74 GR |
158 | * |
159 | * Returns true if there's any budget left (e.g. the clean is finished) | |
160 | **/ | |
a619afe8 AD |
161 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
162 | struct i40e_ring *tx_ring, int napi_budget) | |
7f12ad74 GR |
163 | { |
164 | u16 i = tx_ring->next_to_clean; | |
165 | struct i40e_tx_buffer *tx_buf; | |
166 | struct i40e_tx_desc *tx_desc; | |
a619afe8 AD |
167 | unsigned int total_bytes = 0, total_packets = 0; |
168 | unsigned int budget = vsi->work_limit; | |
7f12ad74 GR |
169 | |
170 | tx_buf = &tx_ring->tx_bi[i]; | |
171 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
172 | i -= tx_ring->count; | |
173 | ||
174 | do { | |
175 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
176 | ||
177 | /* if next_to_watch is not set then there is no work pending */ | |
178 | if (!eop_desc) | |
179 | break; | |
180 | ||
181 | /* prevent any other reads prior to eop_desc */ | |
182 | read_barrier_depends(); | |
183 | ||
ed0980c4 | 184 | i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); |
b1cb07db PB |
185 | /* if the descriptor isn't done, no work yet to do */ |
186 | if (!(eop_desc->cmd_type_offset_bsz & | |
187 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
7f12ad74 GR |
188 | break; |
189 | ||
190 | /* clear next_to_watch to prevent false hangs */ | |
191 | tx_buf->next_to_watch = NULL; | |
192 | ||
193 | /* update the statistics for this packet */ | |
194 | total_bytes += tx_buf->bytecount; | |
195 | total_packets += tx_buf->gso_segs; | |
196 | ||
197 | /* free the skb */ | |
a619afe8 | 198 | napi_consume_skb(tx_buf->skb, napi_budget); |
7f12ad74 GR |
199 | |
200 | /* unmap skb header data */ | |
201 | dma_unmap_single(tx_ring->dev, | |
202 | dma_unmap_addr(tx_buf, dma), | |
203 | dma_unmap_len(tx_buf, len), | |
204 | DMA_TO_DEVICE); | |
205 | ||
206 | /* clear tx_buffer data */ | |
207 | tx_buf->skb = NULL; | |
208 | dma_unmap_len_set(tx_buf, len, 0); | |
209 | ||
210 | /* unmap remaining buffers */ | |
211 | while (tx_desc != eop_desc) { | |
ed0980c4 SP |
212 | i40e_trace(clean_tx_irq_unmap, |
213 | tx_ring, tx_desc, tx_buf); | |
7f12ad74 GR |
214 | |
215 | tx_buf++; | |
216 | tx_desc++; | |
217 | i++; | |
218 | if (unlikely(!i)) { | |
219 | i -= tx_ring->count; | |
220 | tx_buf = tx_ring->tx_bi; | |
221 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
222 | } | |
223 | ||
224 | /* unmap any remaining paged data */ | |
225 | if (dma_unmap_len(tx_buf, len)) { | |
226 | dma_unmap_page(tx_ring->dev, | |
227 | dma_unmap_addr(tx_buf, dma), | |
228 | dma_unmap_len(tx_buf, len), | |
229 | DMA_TO_DEVICE); | |
230 | dma_unmap_len_set(tx_buf, len, 0); | |
231 | } | |
232 | } | |
233 | ||
234 | /* move us one more past the eop_desc for start of next pkt */ | |
235 | tx_buf++; | |
236 | tx_desc++; | |
237 | i++; | |
238 | if (unlikely(!i)) { | |
239 | i -= tx_ring->count; | |
240 | tx_buf = tx_ring->tx_bi; | |
241 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
242 | } | |
243 | ||
016890b9 JB |
244 | prefetch(tx_desc); |
245 | ||
7f12ad74 GR |
246 | /* update budget accounting */ |
247 | budget--; | |
248 | } while (likely(budget)); | |
249 | ||
250 | i += tx_ring->count; | |
251 | tx_ring->next_to_clean = i; | |
252 | u64_stats_update_begin(&tx_ring->syncp); | |
253 | tx_ring->stats.bytes += total_bytes; | |
254 | tx_ring->stats.packets += total_packets; | |
255 | u64_stats_update_end(&tx_ring->syncp); | |
256 | tx_ring->q_vector->tx.total_bytes += total_bytes; | |
257 | tx_ring->q_vector->tx.total_packets += total_packets; | |
258 | ||
f6d83d13 | 259 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
f6d83d13 ASJ |
260 | /* check to see if there are < 4 descriptors |
261 | * waiting to be written back, then kick the hardware to force | |
262 | * them to be written back in case we stay in NAPI. | |
263 | * In this mode on X722 we do not enable Interrupt. | |
264 | */ | |
88dc9e6f | 265 | unsigned int j = i40evf_get_tx_pending(tx_ring, false); |
f6d83d13 ASJ |
266 | |
267 | if (budget && | |
1dc8b538 | 268 | ((j / WB_STRIDE) == 0) && (j > 0) && |
0da36b97 | 269 | !test_bit(__I40E_VSI_DOWN, vsi->state) && |
f6d83d13 ASJ |
270 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
271 | tx_ring->arm_wb = true; | |
272 | } | |
273 | ||
e486bdfd AD |
274 | /* notify netdev of completed buffers */ |
275 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7f12ad74 GR |
276 | total_packets, total_bytes); |
277 | ||
278 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) | |
279 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
280 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
281 | /* Make sure that anybody stopping the queue after this | |
282 | * sees the new next_to_clean. | |
283 | */ | |
284 | smp_mb(); | |
285 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
286 | tx_ring->queue_index) && | |
0da36b97 | 287 | !test_bit(__I40E_VSI_DOWN, vsi->state)) { |
7f12ad74 GR |
288 | netif_wake_subqueue(tx_ring->netdev, |
289 | tx_ring->queue_index); | |
290 | ++tx_ring->tx_stats.restart_queue; | |
291 | } | |
292 | } | |
293 | ||
b03a8c1f | 294 | return !!budget; |
7f12ad74 GR |
295 | } |
296 | ||
c29af37f | 297 | /** |
ecc6a239 | 298 | * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
c29af37f | 299 | * @vsi: the VSI we care about |
ecc6a239 | 300 | * @q_vector: the vector on which to enable writeback |
c29af37f ASJ |
301 | * |
302 | **/ | |
ecc6a239 ASJ |
303 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
304 | struct i40e_q_vector *q_vector) | |
c29af37f | 305 | { |
8e0764b4 | 306 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 307 | u32 val; |
8e0764b4 | 308 | |
ecc6a239 ASJ |
309 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
310 | return; | |
311 | ||
312 | if (q_vector->arm_wb_state) | |
313 | return; | |
314 | ||
315 | val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | | |
316 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */ | |
317 | ||
318 | wr32(&vsi->back->hw, | |
319 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + | |
320 | vsi->base_vector - 1), val); | |
321 | q_vector->arm_wb_state = true; | |
322 | } | |
323 | ||
324 | /** | |
325 | * i40evf_force_wb - Issue SW Interrupt so HW does a wb | |
326 | * @vsi: the VSI we care about | |
327 | * @q_vector: the vector on which to force writeback | |
328 | * | |
329 | **/ | |
330 | void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
331 | { | |
332 | u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
333 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */ | |
334 | I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK | | |
335 | I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK | |
336 | /* allow 00 to be written to the index */; | |
337 | ||
338 | wr32(&vsi->back->hw, | |
339 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1), | |
340 | val); | |
c29af37f ASJ |
341 | } |
342 | ||
7f12ad74 GR |
343 | /** |
344 | * i40e_set_new_dynamic_itr - Find new ITR level | |
345 | * @rc: structure containing ring performance data | |
346 | * | |
8f5e39ce JB |
347 | * Returns true if ITR changed, false if not |
348 | * | |
7f12ad74 GR |
349 | * Stores a new ITR value based on packets and byte counts during |
350 | * the last interrupt. The advantage of per interrupt computation | |
351 | * is faster updates and more accurate ITR for the current traffic | |
352 | * pattern. Constants in this function were computed based on | |
353 | * theoretical maximum wire speed and thresholds were set based on | |
354 | * testing data as well as attempting to minimize response time | |
355 | * while increasing bulk throughput. | |
356 | **/ | |
8f5e39ce | 357 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
7f12ad74 GR |
358 | { |
359 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 360 | struct i40e_q_vector *qv = rc->ring->q_vector; |
7f12ad74 GR |
361 | u32 new_itr = rc->itr; |
362 | int bytes_per_int; | |
51cc6d9f | 363 | int usecs; |
7f12ad74 GR |
364 | |
365 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 366 | return false; |
7f12ad74 GR |
367 | |
368 | /* simple throttlerate management | |
c56625d5 | 369 | * 0-10MB/s lowest (50000 ints/s) |
7f12ad74 | 370 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
371 | * 20-1249MB/s bulk (18000 ints/s) |
372 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
373 | * |
374 | * The math works out because the divisor is in 10^(-6) which | |
375 | * turns the bytes/us input value into MB/s values, but | |
376 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
377 | * are in 2 usec increments in the ITR registers, and make sure |
378 | * to use the smoothed values that the countdown timer gives us. | |
7f12ad74 | 379 | */ |
ee2319cf | 380 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 381 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 382 | |
de32e3ef | 383 | switch (new_latency_range) { |
7f12ad74 GR |
384 | case I40E_LOWEST_LATENCY: |
385 | if (bytes_per_int > 10) | |
386 | new_latency_range = I40E_LOW_LATENCY; | |
387 | break; | |
388 | case I40E_LOW_LATENCY: | |
389 | if (bytes_per_int > 20) | |
390 | new_latency_range = I40E_BULK_LATENCY; | |
391 | else if (bytes_per_int <= 10) | |
392 | new_latency_range = I40E_LOWEST_LATENCY; | |
393 | break; | |
394 | case I40E_BULK_LATENCY: | |
c56625d5 | 395 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
396 | default: |
397 | if (bytes_per_int <= 20) | |
398 | new_latency_range = I40E_LOW_LATENCY; | |
7f12ad74 GR |
399 | break; |
400 | } | |
c56625d5 JB |
401 | |
402 | /* this is to adjust RX more aggressively when streaming small | |
403 | * packets. The value of 40000 was picked as it is just beyond | |
404 | * what the hardware can receive per second if in low latency | |
405 | * mode. | |
406 | */ | |
407 | #define RX_ULTRA_PACKET_RATE 40000 | |
408 | ||
409 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
410 | (&qv->rx == rc)) | |
411 | new_latency_range = I40E_ULTRA_LATENCY; | |
412 | ||
de32e3ef | 413 | rc->latency_range = new_latency_range; |
7f12ad74 GR |
414 | |
415 | switch (new_latency_range) { | |
416 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 417 | new_itr = I40E_ITR_50K; |
7f12ad74 GR |
418 | break; |
419 | case I40E_LOW_LATENCY: | |
420 | new_itr = I40E_ITR_20K; | |
421 | break; | |
422 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
423 | new_itr = I40E_ITR_18K; |
424 | break; | |
425 | case I40E_ULTRA_LATENCY: | |
7f12ad74 GR |
426 | new_itr = I40E_ITR_8K; |
427 | break; | |
428 | default: | |
429 | break; | |
430 | } | |
431 | ||
7f12ad74 GR |
432 | rc->total_bytes = 0; |
433 | rc->total_packets = 0; | |
8f5e39ce JB |
434 | |
435 | if (new_itr != rc->itr) { | |
436 | rc->itr = new_itr; | |
437 | return true; | |
438 | } | |
439 | ||
440 | return false; | |
7f12ad74 GR |
441 | } |
442 | ||
4eeb1fff | 443 | /** |
7f12ad74 GR |
444 | * i40evf_setup_tx_descriptors - Allocate the Tx descriptors |
445 | * @tx_ring: the tx ring to set up | |
446 | * | |
447 | * Return 0 on success, negative on error | |
448 | **/ | |
449 | int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
450 | { | |
451 | struct device *dev = tx_ring->dev; | |
452 | int bi_size; | |
453 | ||
454 | if (!dev) | |
455 | return -ENOMEM; | |
456 | ||
67c818a1 MW |
457 | /* warn if we are about to overwrite the pointer */ |
458 | WARN_ON(tx_ring->tx_bi); | |
7f12ad74 GR |
459 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
460 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
461 | if (!tx_ring->tx_bi) | |
462 | goto err; | |
463 | ||
464 | /* round up to nearest 4K */ | |
465 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
466 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
467 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
468 | &tx_ring->dma, GFP_KERNEL); | |
469 | if (!tx_ring->desc) { | |
470 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
471 | tx_ring->size); | |
472 | goto err; | |
473 | } | |
474 | ||
475 | tx_ring->next_to_use = 0; | |
476 | tx_ring->next_to_clean = 0; | |
477 | return 0; | |
478 | ||
479 | err: | |
480 | kfree(tx_ring->tx_bi); | |
481 | tx_ring->tx_bi = NULL; | |
482 | return -ENOMEM; | |
483 | } | |
484 | ||
485 | /** | |
486 | * i40evf_clean_rx_ring - Free Rx buffers | |
487 | * @rx_ring: ring to be cleaned | |
488 | **/ | |
489 | void i40evf_clean_rx_ring(struct i40e_ring *rx_ring) | |
490 | { | |
7f12ad74 GR |
491 | unsigned long bi_size; |
492 | u16 i; | |
493 | ||
494 | /* ring already cleared, nothing to do */ | |
495 | if (!rx_ring->rx_bi) | |
496 | return; | |
497 | ||
e72e5659 SP |
498 | if (rx_ring->skb) { |
499 | dev_kfree_skb(rx_ring->skb); | |
500 | rx_ring->skb = NULL; | |
501 | } | |
502 | ||
7f12ad74 GR |
503 | /* Free all the Rx ring sk_buffs */ |
504 | for (i = 0; i < rx_ring->count; i++) { | |
ab9ad98e JB |
505 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
506 | ||
ab9ad98e JB |
507 | if (!rx_bi->page) |
508 | continue; | |
509 | ||
59605bc0 AD |
510 | /* Invalidate cache lines that may have been written to by |
511 | * device so that we avoid corrupting memory. | |
512 | */ | |
513 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
514 | rx_bi->dma, | |
515 | rx_bi->page_offset, | |
98efd694 | 516 | rx_ring->rx_buf_len, |
59605bc0 AD |
517 | DMA_FROM_DEVICE); |
518 | ||
519 | /* free resources associated with mapping */ | |
520 | dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, | |
98efd694 | 521 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
522 | DMA_FROM_DEVICE, |
523 | I40E_RX_DMA_ATTR); | |
98efd694 | 524 | |
1793668c | 525 | __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); |
ab9ad98e JB |
526 | |
527 | rx_bi->page = NULL; | |
528 | rx_bi->page_offset = 0; | |
7f12ad74 GR |
529 | } |
530 | ||
531 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
532 | memset(rx_ring->rx_bi, 0, bi_size); | |
533 | ||
534 | /* Zero out the descriptor ring */ | |
535 | memset(rx_ring->desc, 0, rx_ring->size); | |
536 | ||
ab9ad98e | 537 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
538 | rx_ring->next_to_clean = 0; |
539 | rx_ring->next_to_use = 0; | |
540 | } | |
541 | ||
542 | /** | |
543 | * i40evf_free_rx_resources - Free Rx resources | |
544 | * @rx_ring: ring to clean the resources from | |
545 | * | |
546 | * Free all receive software resources | |
547 | **/ | |
548 | void i40evf_free_rx_resources(struct i40e_ring *rx_ring) | |
549 | { | |
550 | i40evf_clean_rx_ring(rx_ring); | |
551 | kfree(rx_ring->rx_bi); | |
552 | rx_ring->rx_bi = NULL; | |
553 | ||
554 | if (rx_ring->desc) { | |
555 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
556 | rx_ring->desc, rx_ring->dma); | |
557 | rx_ring->desc = NULL; | |
558 | } | |
559 | } | |
560 | ||
561 | /** | |
562 | * i40evf_setup_rx_descriptors - Allocate Rx descriptors | |
563 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
564 | * | |
565 | * Returns 0 on success, negative on failure | |
566 | **/ | |
567 | int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
568 | { | |
569 | struct device *dev = rx_ring->dev; | |
570 | int bi_size; | |
571 | ||
67c818a1 MW |
572 | /* warn if we are about to overwrite the pointer */ |
573 | WARN_ON(rx_ring->rx_bi); | |
7f12ad74 GR |
574 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
575 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
576 | if (!rx_ring->rx_bi) | |
577 | goto err; | |
578 | ||
f217d6ca | 579 | u64_stats_init(&rx_ring->syncp); |
638702bd | 580 | |
7f12ad74 | 581 | /* Round up to nearest 4K */ |
ab9ad98e | 582 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
7f12ad74 GR |
583 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
584 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
585 | &rx_ring->dma, GFP_KERNEL); | |
586 | ||
587 | if (!rx_ring->desc) { | |
588 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
589 | rx_ring->size); | |
590 | goto err; | |
591 | } | |
592 | ||
ab9ad98e | 593 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
594 | rx_ring->next_to_clean = 0; |
595 | rx_ring->next_to_use = 0; | |
596 | ||
597 | return 0; | |
598 | err: | |
599 | kfree(rx_ring->rx_bi); | |
600 | rx_ring->rx_bi = NULL; | |
601 | return -ENOMEM; | |
602 | } | |
603 | ||
604 | /** | |
605 | * i40e_release_rx_desc - Store the new tail and head values | |
606 | * @rx_ring: ring to bump | |
607 | * @val: new head index | |
608 | **/ | |
609 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
610 | { | |
611 | rx_ring->next_to_use = val; | |
ab9ad98e JB |
612 | |
613 | /* update next to alloc since we have filled the ring */ | |
614 | rx_ring->next_to_alloc = val; | |
615 | ||
7f12ad74 GR |
616 | /* Force memory writes to complete before letting h/w |
617 | * know there are new descriptors to fetch. (Only | |
618 | * applicable for weak-ordered memory model archs, | |
619 | * such as IA-64). | |
620 | */ | |
621 | wmb(); | |
622 | writel(val, rx_ring->tail); | |
623 | } | |
624 | ||
ca9ec088 AD |
625 | /** |
626 | * i40e_rx_offset - Return expected offset into page to access data | |
627 | * @rx_ring: Ring we are requesting offset of | |
628 | * | |
629 | * Returns the offset value for ring into the data buffer. | |
630 | */ | |
631 | static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) | |
632 | { | |
633 | return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; | |
634 | } | |
635 | ||
7f12ad74 | 636 | /** |
ab9ad98e JB |
637 | * i40e_alloc_mapped_page - recycle or make a new page |
638 | * @rx_ring: ring to use | |
639 | * @bi: rx_buffer struct to modify | |
c2e245ab | 640 | * |
ab9ad98e JB |
641 | * Returns true if the page was successfully allocated or |
642 | * reused. | |
a132af24 | 643 | **/ |
ab9ad98e JB |
644 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
645 | struct i40e_rx_buffer *bi) | |
a132af24 | 646 | { |
ab9ad98e JB |
647 | struct page *page = bi->page; |
648 | dma_addr_t dma; | |
a132af24 | 649 | |
ab9ad98e JB |
650 | /* since we are recycling buffers we should seldom need to alloc */ |
651 | if (likely(page)) { | |
652 | rx_ring->rx_stats.page_reuse_count++; | |
653 | return true; | |
654 | } | |
a132af24 | 655 | |
ab9ad98e | 656 | /* alloc new page for storage */ |
98efd694 | 657 | page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); |
ab9ad98e JB |
658 | if (unlikely(!page)) { |
659 | rx_ring->rx_stats.alloc_page_failed++; | |
660 | return false; | |
661 | } | |
a132af24 | 662 | |
ab9ad98e | 663 | /* map page for use */ |
59605bc0 | 664 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
98efd694 | 665 | i40e_rx_pg_size(rx_ring), |
59605bc0 AD |
666 | DMA_FROM_DEVICE, |
667 | I40E_RX_DMA_ATTR); | |
f16704e5 | 668 | |
ab9ad98e JB |
669 | /* if mapping failed free memory back to system since |
670 | * there isn't much point in holding memory we can't use | |
f16704e5 | 671 | */ |
ab9ad98e | 672 | if (dma_mapping_error(rx_ring->dev, dma)) { |
98efd694 | 673 | __free_pages(page, i40e_rx_pg_order(rx_ring)); |
ab9ad98e JB |
674 | rx_ring->rx_stats.alloc_page_failed++; |
675 | return false; | |
a132af24 MW |
676 | } |
677 | ||
ab9ad98e JB |
678 | bi->dma = dma; |
679 | bi->page = page; | |
ca9ec088 | 680 | bi->page_offset = i40e_rx_offset(rx_ring); |
a0cfc313 AD |
681 | |
682 | /* initialize pagecnt_bias to 1 representing we fully own page */ | |
1793668c | 683 | bi->pagecnt_bias = 1; |
c2e245ab | 684 | |
ab9ad98e JB |
685 | return true; |
686 | } | |
c2e245ab | 687 | |
ab9ad98e JB |
688 | /** |
689 | * i40e_receive_skb - Send a completed packet up the stack | |
690 | * @rx_ring: rx ring in play | |
691 | * @skb: packet to send up | |
692 | * @vlan_tag: vlan tag for packet | |
693 | **/ | |
694 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
695 | struct sk_buff *skb, u16 vlan_tag) | |
696 | { | |
697 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 698 | |
ab9ad98e JB |
699 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
700 | (vlan_tag & VLAN_VID_MASK)) | |
701 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
702 | ||
703 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
704 | } |
705 | ||
706 | /** | |
ab9ad98e | 707 | * i40evf_alloc_rx_buffers - Replace used receive buffers |
7f12ad74 GR |
708 | * @rx_ring: ring to place buffers on |
709 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 710 | * |
ab9ad98e | 711 | * Returns false if all allocations were successful, true if any fail |
7f12ad74 | 712 | **/ |
ab9ad98e | 713 | bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
7f12ad74 | 714 | { |
ab9ad98e | 715 | u16 ntu = rx_ring->next_to_use; |
7f12ad74 GR |
716 | union i40e_rx_desc *rx_desc; |
717 | struct i40e_rx_buffer *bi; | |
7f12ad74 GR |
718 | |
719 | /* do nothing if no valid netdev defined */ | |
720 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 721 | return false; |
7f12ad74 | 722 | |
ab9ad98e JB |
723 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
724 | bi = &rx_ring->rx_bi[ntu]; | |
7f12ad74 | 725 | |
ab9ad98e JB |
726 | do { |
727 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
728 | goto no_buffers; | |
7f12ad74 | 729 | |
59605bc0 AD |
730 | /* sync the buffer for use by the device */ |
731 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
732 | bi->page_offset, | |
98efd694 | 733 | rx_ring->rx_buf_len, |
59605bc0 AD |
734 | DMA_FROM_DEVICE); |
735 | ||
ab9ad98e JB |
736 | /* Refresh the desc even if buffer_addrs didn't change |
737 | * because each write-back erases this info. | |
738 | */ | |
739 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
7f12ad74 | 740 | |
ab9ad98e JB |
741 | rx_desc++; |
742 | bi++; | |
743 | ntu++; | |
744 | if (unlikely(ntu == rx_ring->count)) { | |
745 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
746 | bi = rx_ring->rx_bi; | |
747 | ntu = 0; | |
748 | } | |
749 | ||
750 | /* clear the status bits for the next_to_use descriptor */ | |
751 | rx_desc->wb.qword1.status_error_len = 0; | |
752 | ||
753 | cleaned_count--; | |
754 | } while (cleaned_count); | |
755 | ||
756 | if (rx_ring->next_to_use != ntu) | |
757 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
758 | |
759 | return false; | |
760 | ||
7f12ad74 | 761 | no_buffers: |
ab9ad98e JB |
762 | if (rx_ring->next_to_use != ntu) |
763 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
764 | |
765 | /* make sure to come back via polling to try again after | |
766 | * allocation failure | |
767 | */ | |
768 | return true; | |
7f12ad74 GR |
769 | } |
770 | ||
7f12ad74 GR |
771 | /** |
772 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
773 | * @vsi: the VSI we care about | |
774 | * @skb: skb currently being received and modified | |
ab9ad98e | 775 | * @rx_desc: the receive descriptor |
7f12ad74 GR |
776 | **/ |
777 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
778 | struct sk_buff *skb, | |
ab9ad98e | 779 | union i40e_rx_desc *rx_desc) |
7f12ad74 | 780 | { |
ab9ad98e | 781 | struct i40e_rx_ptype_decoded decoded; |
ab9ad98e | 782 | u32 rx_error, rx_status; |
858296c8 | 783 | bool ipv4, ipv6; |
ab9ad98e JB |
784 | u8 ptype; |
785 | u64 qword; | |
786 | ||
787 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
788 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
789 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
790 | I40E_RXD_QW1_ERROR_SHIFT; | |
791 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
792 | I40E_RXD_QW1_STATUS_SHIFT; | |
793 | decoded = decode_rx_desc_ptype(ptype); | |
7f12ad74 | 794 | |
7f12ad74 GR |
795 | skb->ip_summed = CHECKSUM_NONE; |
796 | ||
ab9ad98e JB |
797 | skb_checksum_none_assert(skb); |
798 | ||
7f12ad74 | 799 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
800 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
801 | return; | |
802 | ||
803 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 804 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
805 | return; |
806 | ||
807 | /* both known and outer_ip must be set for the below code to work */ | |
808 | if (!(decoded.known && decoded.outer_ip)) | |
7f12ad74 GR |
809 | return; |
810 | ||
fad57330 AD |
811 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
812 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
813 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
814 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
815 | |
816 | if (ipv4 && | |
41a1d04b JB |
817 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
818 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
819 | goto checksum_fail; |
820 | ||
ddf1d0d7 | 821 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 822 | if (ipv6 && |
41a1d04b | 823 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 824 | /* don't increment checksum err here, non-fatal err */ |
7f12ad74 GR |
825 | return; |
826 | ||
8a3c91cc | 827 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 828 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
829 | goto checksum_fail; |
830 | ||
831 | /* handle packets that were not able to be checksummed due | |
832 | * to arrival speed, in this case the stack can compute | |
833 | * the csum. | |
834 | */ | |
41a1d04b | 835 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
7f12ad74 | 836 | return; |
7f12ad74 | 837 | |
858296c8 AD |
838 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ |
839 | switch (decoded.inner_prot) { | |
840 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
841 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
842 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
843 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
844 | /* fall though */ | |
845 | default: | |
846 | break; | |
847 | } | |
8a3c91cc JB |
848 | |
849 | return; | |
850 | ||
851 | checksum_fail: | |
852 | vsi->back->hw_csum_rx_error++; | |
7f12ad74 GR |
853 | } |
854 | ||
855 | /** | |
857942fd | 856 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
857 | * @ptype: the ptype value from the descriptor |
858 | * | |
859 | * Returns a hash type to be used by skb_set_hash | |
860 | **/ | |
ab9ad98e | 861 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
862 | { |
863 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
864 | ||
865 | if (!decoded.known) | |
866 | return PKT_HASH_TYPE_NONE; | |
867 | ||
868 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
869 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
870 | return PKT_HASH_TYPE_L4; | |
871 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
872 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
873 | return PKT_HASH_TYPE_L3; | |
874 | else | |
875 | return PKT_HASH_TYPE_L2; | |
876 | } | |
877 | ||
857942fd ASJ |
878 | /** |
879 | * i40e_rx_hash - set the hash value in the skb | |
880 | * @ring: descriptor ring | |
881 | * @rx_desc: specific descriptor | |
882 | **/ | |
883 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
884 | union i40e_rx_desc *rx_desc, | |
885 | struct sk_buff *skb, | |
886 | u8 rx_ptype) | |
887 | { | |
888 | u32 hash; | |
ab9ad98e | 889 | const __le64 rss_mask = |
857942fd ASJ |
890 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
891 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
892 | ||
893 | if (ring->netdev->features & NETIF_F_RXHASH) | |
894 | return; | |
895 | ||
896 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
897 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
898 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
899 | } | |
900 | } | |
901 | ||
7f12ad74 | 902 | /** |
ab9ad98e JB |
903 | * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor |
904 | * @rx_ring: rx descriptor ring packet is being transacted on | |
905 | * @rx_desc: pointer to the EOP Rx descriptor | |
906 | * @skb: pointer to current skb being populated | |
907 | * @rx_ptype: the packet type decoded by hardware | |
7f12ad74 | 908 | * |
ab9ad98e JB |
909 | * This function checks the ring, descriptor, and packet information in |
910 | * order to populate the hash, checksum, VLAN, protocol, and | |
911 | * other fields within the skb. | |
7f12ad74 | 912 | **/ |
ab9ad98e JB |
913 | static inline |
914 | void i40evf_process_skb_fields(struct i40e_ring *rx_ring, | |
915 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
916 | u8 rx_ptype) | |
7f12ad74 | 917 | { |
ab9ad98e | 918 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); |
7f12ad74 | 919 | |
ab9ad98e | 920 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); |
a132af24 | 921 | |
ab9ad98e | 922 | skb_record_rx_queue(skb, rx_ring->queue_index); |
a5b268e4 AD |
923 | |
924 | /* modifies the skb - consumes the enet header */ | |
925 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
ab9ad98e | 926 | } |
a132af24 | 927 | |
ab9ad98e JB |
928 | /** |
929 | * i40e_cleanup_headers - Correct empty headers | |
930 | * @rx_ring: rx descriptor ring packet is being transacted on | |
931 | * @skb: pointer to current skb being fixed | |
932 | * | |
933 | * Also address the case where we are pulling data in on pages only | |
934 | * and as such no data is present in the skb header. | |
935 | * | |
936 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
937 | * it is large enough to qualify as a valid Ethernet frame. | |
938 | * | |
939 | * Returns true if an error was encountered and skb was freed. | |
940 | **/ | |
941 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
942 | { | |
ab9ad98e JB |
943 | /* if eth_skb_pad returns an error the skb was freed */ |
944 | if (eth_skb_pad(skb)) | |
945 | return true; | |
7f12ad74 | 946 | |
ab9ad98e JB |
947 | return false; |
948 | } | |
857942fd | 949 | |
ab9ad98e JB |
950 | /** |
951 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
952 | * @rx_ring: rx descriptor ring to store buffers on | |
953 | * @old_buff: donor buffer to have page reused | |
954 | * | |
955 | * Synchronizes page for reuse by the adapter | |
956 | **/ | |
957 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
958 | struct i40e_rx_buffer *old_buff) | |
959 | { | |
960 | struct i40e_rx_buffer *new_buff; | |
961 | u16 nta = rx_ring->next_to_alloc; | |
7f12ad74 | 962 | |
ab9ad98e | 963 | new_buff = &rx_ring->rx_bi[nta]; |
7f12ad74 | 964 | |
ab9ad98e JB |
965 | /* update, and store next to alloc */ |
966 | nta++; | |
967 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
7f12ad74 | 968 | |
ab9ad98e | 969 | /* transfer page from old buffer to new buffer */ |
1793668c AD |
970 | new_buff->dma = old_buff->dma; |
971 | new_buff->page = old_buff->page; | |
972 | new_buff->page_offset = old_buff->page_offset; | |
973 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; | |
ab9ad98e JB |
974 | } |
975 | ||
976 | /** | |
9b37c937 | 977 | * i40e_page_is_reusable - check if any reuse is possible |
ab9ad98e | 978 | * @page: page struct to check |
9b37c937 SP |
979 | * |
980 | * A page is not reusable if it was allocated under low memory | |
981 | * conditions, or it's not in the same NUMA node as this CPU. | |
ab9ad98e | 982 | */ |
9b37c937 | 983 | static inline bool i40e_page_is_reusable(struct page *page) |
ab9ad98e | 984 | { |
9b37c937 SP |
985 | return (page_to_nid(page) == numa_mem_id()) && |
986 | !page_is_pfmemalloc(page); | |
987 | } | |
988 | ||
989 | /** | |
990 | * i40e_can_reuse_rx_page - Determine if this page can be reused by | |
991 | * the adapter for another receive | |
992 | * | |
993 | * @rx_buffer: buffer containing the page | |
9b37c937 SP |
994 | * |
995 | * If page is reusable, rx_buffer->page_offset is adjusted to point to | |
996 | * an unused region in the page. | |
997 | * | |
998 | * For small pages, @truesize will be a constant value, half the size | |
999 | * of the memory at page. We'll attempt to alternate between high and | |
1000 | * low halves of the page, with one half ready for use by the hardware | |
1001 | * and the other half being consumed by the stack. We use the page | |
1002 | * ref count to determine whether the stack has finished consuming the | |
1003 | * portion of this page that was passed up with a previous packet. If | |
1004 | * the page ref count is >1, we'll assume the "other" half page is | |
1005 | * still busy, and this page cannot be reused. | |
1006 | * | |
1007 | * For larger pages, @truesize will be the actual space used by the | |
1008 | * received packet (adjusted upward to an even multiple of the cache | |
1009 | * line size). This will advance through the page by the amount | |
1010 | * actually consumed by the received packets while there is still | |
1011 | * space for a buffer. Each region of larger pages will be used at | |
1012 | * most once, after which the page will not be reused. | |
1013 | * | |
1014 | * In either case, if the page is reusable its refcount is increased. | |
1015 | **/ | |
a0cfc313 | 1016 | static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) |
9b37c937 | 1017 | { |
a0cfc313 AD |
1018 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
1019 | struct page *page = rx_buffer->page; | |
9b37c937 SP |
1020 | |
1021 | /* Is any reuse possible? */ | |
1022 | if (unlikely(!i40e_page_is_reusable(page))) | |
1023 | return false; | |
1024 | ||
1025 | #if (PAGE_SIZE < 8192) | |
1026 | /* if we are only owner of page we can reuse it */ | |
a0cfc313 | 1027 | if (unlikely((page_count(page) - pagecnt_bias) > 1)) |
9b37c937 | 1028 | return false; |
9b37c937 | 1029 | #else |
98efd694 AD |
1030 | #define I40E_LAST_OFFSET \ |
1031 | (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) | |
1032 | if (rx_buffer->page_offset > I40E_LAST_OFFSET) | |
9b37c937 SP |
1033 | return false; |
1034 | #endif | |
1035 | ||
1793668c AD |
1036 | /* If we have drained the page fragment pool we need to update |
1037 | * the pagecnt_bias and page count so that we fully restock the | |
1038 | * number of references the driver holds. | |
1039 | */ | |
a0cfc313 | 1040 | if (unlikely(!pagecnt_bias)) { |
1793668c AD |
1041 | page_ref_add(page, USHRT_MAX); |
1042 | rx_buffer->pagecnt_bias = USHRT_MAX; | |
1043 | } | |
9b37c937 SP |
1044 | |
1045 | return true; | |
ab9ad98e JB |
1046 | } |
1047 | ||
1048 | /** | |
1049 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1050 | * @rx_ring: rx descriptor ring to transact packets on | |
1051 | * @rx_buffer: buffer containing page to add | |
ab9ad98e | 1052 | * @skb: sk_buff to place the data into |
a0cfc313 | 1053 | * @size: packet length from rx_desc |
ab9ad98e JB |
1054 | * |
1055 | * This function will add the data contained in rx_buffer->page to the skb. | |
fa2343e9 | 1056 | * It will just attach the page as a frag to the skb. |
ab9ad98e | 1057 | * |
fa2343e9 | 1058 | * The function will then update the page offset. |
ab9ad98e | 1059 | **/ |
a0cfc313 | 1060 | static void i40e_add_rx_frag(struct i40e_ring *rx_ring, |
ab9ad98e | 1061 | struct i40e_rx_buffer *rx_buffer, |
a0cfc313 AD |
1062 | struct sk_buff *skb, |
1063 | unsigned int size) | |
ab9ad98e | 1064 | { |
ab9ad98e | 1065 | #if (PAGE_SIZE < 8192) |
98efd694 | 1066 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
ab9ad98e | 1067 | #else |
ca9ec088 | 1068 | unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)); |
a132af24 | 1069 | #endif |
ab9ad98e | 1070 | |
fa2343e9 AD |
1071 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
1072 | rx_buffer->page_offset, size, truesize); | |
ab9ad98e | 1073 | |
a0cfc313 AD |
1074 | /* page is being used so we must update the page offset */ |
1075 | #if (PAGE_SIZE < 8192) | |
1076 | rx_buffer->page_offset ^= truesize; | |
1077 | #else | |
1078 | rx_buffer->page_offset += truesize; | |
1079 | #endif | |
ab9ad98e JB |
1080 | } |
1081 | ||
9a064128 AD |
1082 | /** |
1083 | * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use | |
1084 | * @rx_ring: rx descriptor ring to transact packets on | |
1085 | * @size: size of buffer to add to skb | |
1086 | * | |
1087 | * This function will pull an Rx buffer from the ring and synchronize it | |
1088 | * for use by the CPU. | |
1089 | */ | |
1090 | static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, | |
1091 | const unsigned int size) | |
1092 | { | |
1093 | struct i40e_rx_buffer *rx_buffer; | |
1094 | ||
1095 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1096 | prefetchw(rx_buffer->page); | |
1097 | ||
1098 | /* we are reusing so sync this buffer for CPU use */ | |
1099 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1100 | rx_buffer->dma, | |
1101 | rx_buffer->page_offset, | |
1102 | size, | |
1103 | DMA_FROM_DEVICE); | |
1104 | ||
a0cfc313 AD |
1105 | /* We have pulled a buffer for use, so decrement pagecnt_bias */ |
1106 | rx_buffer->pagecnt_bias--; | |
1107 | ||
9a064128 AD |
1108 | return rx_buffer; |
1109 | } | |
1110 | ||
ab9ad98e | 1111 | /** |
fa2343e9 | 1112 | * i40e_construct_skb - Allocate skb and populate it |
ab9ad98e | 1113 | * @rx_ring: rx descriptor ring to transact packets on |
9a064128 | 1114 | * @rx_buffer: rx buffer to pull data from |
d57c0e08 | 1115 | * @size: size of buffer to add to skb |
ab9ad98e | 1116 | * |
fa2343e9 AD |
1117 | * This function allocates an skb. It then populates it with the page |
1118 | * data from the current receive descriptor, taking care to set up the | |
1119 | * skb correctly. | |
ab9ad98e | 1120 | */ |
fa2343e9 AD |
1121 | static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, |
1122 | struct i40e_rx_buffer *rx_buffer, | |
1123 | unsigned int size) | |
ab9ad98e | 1124 | { |
fa2343e9 AD |
1125 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; |
1126 | #if (PAGE_SIZE < 8192) | |
98efd694 | 1127 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; |
fa2343e9 AD |
1128 | #else |
1129 | unsigned int truesize = SKB_DATA_ALIGN(size); | |
1130 | #endif | |
1131 | unsigned int headlen; | |
1132 | struct sk_buff *skb; | |
ab9ad98e | 1133 | |
fa2343e9 AD |
1134 | /* prefetch first cache line of first page */ |
1135 | prefetch(va); | |
ab9ad98e | 1136 | #if L1_CACHE_BYTES < 128 |
fa2343e9 | 1137 | prefetch(va + L1_CACHE_BYTES); |
ab9ad98e JB |
1138 | #endif |
1139 | ||
fa2343e9 AD |
1140 | /* allocate a skb to store the frags */ |
1141 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1142 | I40E_RX_HDR_SIZE, | |
1143 | GFP_ATOMIC | __GFP_NOWARN); | |
1144 | if (unlikely(!skb)) | |
1145 | return NULL; | |
1146 | ||
1147 | /* Determine available headroom for copy */ | |
1148 | headlen = size; | |
1149 | if (headlen > I40E_RX_HDR_SIZE) | |
1150 | headlen = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
ab9ad98e | 1151 | |
fa2343e9 AD |
1152 | /* align pull length to size of long to optimize memcpy performance */ |
1153 | memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); | |
1154 | ||
1155 | /* update all of the pointers */ | |
1156 | size -= headlen; | |
1157 | if (size) { | |
1158 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
1159 | rx_buffer->page_offset + headlen, | |
1160 | size, truesize); | |
1161 | ||
1162 | /* buffer is used by skb, update page_offset */ | |
1163 | #if (PAGE_SIZE < 8192) | |
1164 | rx_buffer->page_offset ^= truesize; | |
1165 | #else | |
1166 | rx_buffer->page_offset += truesize; | |
1167 | #endif | |
1168 | } else { | |
1169 | /* buffer is unused, reset bias back to rx_buffer */ | |
1170 | rx_buffer->pagecnt_bias++; | |
1171 | } | |
a0cfc313 AD |
1172 | |
1173 | return skb; | |
1174 | } | |
1175 | ||
f8b45b74 AD |
1176 | /** |
1177 | * i40e_build_skb - Build skb around an existing buffer | |
1178 | * @rx_ring: Rx descriptor ring to transact packets on | |
1179 | * @rx_buffer: Rx buffer to pull data from | |
1180 | * @size: size of buffer to add to skb | |
1181 | * | |
1182 | * This function builds an skb around an existing Rx buffer, taking care | |
1183 | * to set up the skb correctly and avoid any memcpy overhead. | |
1184 | */ | |
1185 | static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, | |
1186 | struct i40e_rx_buffer *rx_buffer, | |
1187 | unsigned int size) | |
1188 | { | |
1189 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; | |
1190 | #if (PAGE_SIZE < 8192) | |
1191 | unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; | |
1192 | #else | |
2aae918c BT |
1193 | unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1194 | SKB_DATA_ALIGN(I40E_SKB_PAD + size); | |
f8b45b74 AD |
1195 | #endif |
1196 | struct sk_buff *skb; | |
1197 | ||
1198 | /* prefetch first cache line of first page */ | |
1199 | prefetch(va); | |
1200 | #if L1_CACHE_BYTES < 128 | |
1201 | prefetch(va + L1_CACHE_BYTES); | |
1202 | #endif | |
1203 | /* build an skb around the page buffer */ | |
1204 | skb = build_skb(va - I40E_SKB_PAD, truesize); | |
1205 | if (unlikely(!skb)) | |
1206 | return NULL; | |
1207 | ||
1208 | /* update pointers within the skb to store the data */ | |
1209 | skb_reserve(skb, I40E_SKB_PAD); | |
1210 | __skb_put(skb, size); | |
1211 | ||
1212 | /* buffer is used by skb, update page_offset */ | |
1213 | #if (PAGE_SIZE < 8192) | |
1214 | rx_buffer->page_offset ^= truesize; | |
1215 | #else | |
1216 | rx_buffer->page_offset += truesize; | |
1217 | #endif | |
1218 | ||
1219 | return skb; | |
1220 | } | |
1221 | ||
a0cfc313 AD |
1222 | /** |
1223 | * i40e_put_rx_buffer - Clean up used buffer and either recycle or free | |
1224 | * @rx_ring: rx descriptor ring to transact packets on | |
1225 | * @rx_buffer: rx buffer to pull data from | |
1226 | * | |
1227 | * This function will clean up the contents of the rx_buffer. It will | |
1228 | * either recycle the bufer or unmap it and free the associated resources. | |
1229 | */ | |
1230 | static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, | |
1231 | struct i40e_rx_buffer *rx_buffer) | |
1232 | { | |
1233 | if (i40e_can_reuse_rx_page(rx_buffer)) { | |
ab9ad98e JB |
1234 | /* hand second half of page back to the ring */ |
1235 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1236 | rx_ring->rx_stats.page_reuse_count++; | |
1237 | } else { | |
1238 | /* we are not reusing the buffer so unmap it */ | |
98efd694 AD |
1239 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, |
1240 | i40e_rx_pg_size(rx_ring), | |
59605bc0 | 1241 | DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); |
1793668c AD |
1242 | __page_frag_cache_drain(rx_buffer->page, |
1243 | rx_buffer->pagecnt_bias); | |
ab9ad98e JB |
1244 | } |
1245 | ||
1246 | /* clear contents of buffer_info */ | |
1247 | rx_buffer->page = NULL; | |
ab9ad98e JB |
1248 | } |
1249 | ||
1250 | /** | |
1251 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1252 | * @rx_ring: Rx ring being processed | |
1253 | * @rx_desc: Rx descriptor for current buffer | |
1254 | * @skb: Current socket buffer containing buffer in progress | |
1255 | * | |
1256 | * This function updates next to clean. If the buffer is an EOP buffer | |
1257 | * this function exits returning false, otherwise it will place the | |
1258 | * sk_buff in the next buffer to be chained and return true indicating | |
1259 | * that this is in fact a non-EOP buffer. | |
1260 | **/ | |
1261 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, | |
1262 | union i40e_rx_desc *rx_desc, | |
1263 | struct sk_buff *skb) | |
1264 | { | |
1265 | u32 ntc = rx_ring->next_to_clean + 1; | |
1266 | ||
1267 | /* fetch, update, and store next to clean */ | |
1268 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1269 | rx_ring->next_to_clean = ntc; | |
1270 | ||
1271 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1272 | ||
1273 | /* if we are the last buffer then there is nothing else to do */ | |
1274 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1275 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1276 | return false; | |
1277 | ||
ab9ad98e JB |
1278 | rx_ring->rx_stats.non_eop_descs++; |
1279 | ||
1280 | return true; | |
a132af24 MW |
1281 | } |
1282 | ||
1283 | /** | |
ab9ad98e JB |
1284 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf |
1285 | * @rx_ring: rx descriptor ring to transact packets on | |
1286 | * @budget: Total limit on number of packets to process | |
1287 | * | |
1288 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1289 | * processing. The advantage to this is that on systems that have | |
1290 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1291 | * it by maintaining the mapping of the page to the system. | |
a132af24 | 1292 | * |
ab9ad98e | 1293 | * Returns amount of work completed |
a132af24 | 1294 | **/ |
ab9ad98e | 1295 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) |
a132af24 MW |
1296 | { |
1297 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
e72e5659 | 1298 | struct sk_buff *skb = rx_ring->skb; |
a132af24 | 1299 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); |
c2e245ab | 1300 | bool failure = false; |
a132af24 | 1301 | |
ab9ad98e | 1302 | while (likely(total_rx_packets < budget)) { |
9a064128 | 1303 | struct i40e_rx_buffer *rx_buffer; |
ab9ad98e | 1304 | union i40e_rx_desc *rx_desc; |
d57c0e08 | 1305 | unsigned int size; |
a132af24 | 1306 | u16 vlan_tag; |
ab9ad98e JB |
1307 | u8 rx_ptype; |
1308 | u64 qword; | |
1309 | ||
7f12ad74 GR |
1310 | /* return some buffers to hardware, one at a time is too slow */ |
1311 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1312 | failure = failure || |
ab9ad98e | 1313 | i40evf_alloc_rx_buffers(rx_ring, cleaned_count); |
7f12ad74 GR |
1314 | cleaned_count = 0; |
1315 | } | |
1316 | ||
ab9ad98e JB |
1317 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1318 | ||
ab9ad98e JB |
1319 | /* status_error_len will always be zero for unused descriptors |
1320 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1321 | * which is always zero because packet split isn't used, if the | |
d57c0e08 | 1322 | * hardware wrote DD then the length will be non-zero |
ab9ad98e | 1323 | */ |
d57c0e08 | 1324 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
ab9ad98e | 1325 | |
a132af24 | 1326 | /* This memory barrier is needed to keep us from reading |
d57c0e08 AD |
1327 | * any other fields out of the rx_desc until we have |
1328 | * verified the descriptor has been written back. | |
a132af24 | 1329 | */ |
67317166 | 1330 | dma_rmb(); |
a132af24 | 1331 | |
0e626ff7 AD |
1332 | size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> |
1333 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1334 | if (!size) | |
1335 | break; | |
1336 | ||
ed0980c4 | 1337 | i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb); |
9a064128 AD |
1338 | rx_buffer = i40e_get_rx_buffer(rx_ring, size); |
1339 | ||
fa2343e9 AD |
1340 | /* retrieve a buffer from the ring */ |
1341 | if (skb) | |
1342 | i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); | |
f8b45b74 AD |
1343 | else if (ring_uses_build_skb(rx_ring)) |
1344 | skb = i40e_build_skb(rx_ring, rx_buffer, size); | |
fa2343e9 AD |
1345 | else |
1346 | skb = i40e_construct_skb(rx_ring, rx_buffer, size); | |
1347 | ||
1348 | /* exit if we failed to retrieve a buffer */ | |
1349 | if (!skb) { | |
1350 | rx_ring->rx_stats.alloc_buff_failed++; | |
1351 | rx_buffer->pagecnt_bias++; | |
ab9ad98e | 1352 | break; |
fa2343e9 | 1353 | } |
a132af24 | 1354 | |
a0cfc313 | 1355 | i40e_put_rx_buffer(rx_ring, rx_buffer); |
a132af24 MW |
1356 | cleaned_count++; |
1357 | ||
ab9ad98e | 1358 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 1359 | continue; |
a132af24 | 1360 | |
ab9ad98e JB |
1361 | /* ERR_MASK will only have valid bits if EOP set, and |
1362 | * what we are doing here is actually checking | |
1363 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1364 | * the error field | |
1365 | */ | |
1366 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 1367 | dev_kfree_skb_any(skb); |
741b8b83 | 1368 | skb = NULL; |
a132af24 MW |
1369 | continue; |
1370 | } | |
1371 | ||
e72e5659 SP |
1372 | if (i40e_cleanup_headers(rx_ring, skb)) { |
1373 | skb = NULL; | |
ab9ad98e | 1374 | continue; |
e72e5659 | 1375 | } |
ab9ad98e | 1376 | |
a132af24 MW |
1377 | /* probably a little skewed due to removing CRC */ |
1378 | total_rx_bytes += skb->len; | |
a132af24 | 1379 | |
99dad8b3 AD |
1380 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1381 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
1382 | I40E_RXD_QW1_PTYPE_SHIFT; | |
1383 | ||
ab9ad98e JB |
1384 | /* populate checksum, VLAN, and protocol */ |
1385 | i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 1386 | |
a132af24 | 1387 | |
ab9ad98e JB |
1388 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? |
1389 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
1390 | ||
ed0980c4 | 1391 | i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); |
a132af24 | 1392 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
e72e5659 | 1393 | skb = NULL; |
a132af24 | 1394 | |
ab9ad98e JB |
1395 | /* update budget accounting */ |
1396 | total_rx_packets++; | |
1397 | } | |
7f12ad74 | 1398 | |
e72e5659 SP |
1399 | rx_ring->skb = skb; |
1400 | ||
7f12ad74 GR |
1401 | u64_stats_update_begin(&rx_ring->syncp); |
1402 | rx_ring->stats.packets += total_rx_packets; | |
1403 | rx_ring->stats.bytes += total_rx_bytes; | |
1404 | u64_stats_update_end(&rx_ring->syncp); | |
1405 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
1406 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1407 | ||
ab9ad98e | 1408 | /* guarantee a trip back through this routine if there was a failure */ |
c2e245ab | 1409 | return failure ? budget : total_rx_packets; |
7f12ad74 GR |
1410 | } |
1411 | ||
8f5e39ce JB |
1412 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1413 | { | |
1414 | u32 val; | |
1415 | ||
1416 | val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
40d72a50 JB |
1417 | /* Don't clear PBA because that can cause lost interrupts that |
1418 | * came in while we were cleaning/polling | |
1419 | */ | |
8f5e39ce JB |
1420 | (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | |
1421 | (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT); | |
1422 | ||
1423 | return val; | |
1424 | } | |
1425 | ||
1426 | /* a small macro to shorten up some long lines */ | |
1427 | #define INTREG I40E_VFINT_DYN_CTLN1 | |
3c234c47 | 1428 | static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 JK |
1429 | { |
1430 | struct i40evf_adapter *adapter = vsi->back; | |
1431 | ||
3c234c47 | 1432 | return adapter->rx_rings[idx].rx_itr_setting; |
65e87c03 JK |
1433 | } |
1434 | ||
3c234c47 | 1435 | static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 JK |
1436 | { |
1437 | struct i40evf_adapter *adapter = vsi->back; | |
1438 | ||
3c234c47 | 1439 | return adapter->tx_rings[idx].tx_itr_setting; |
65e87c03 | 1440 | } |
8f5e39ce | 1441 | |
de32e3ef CW |
1442 | /** |
1443 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
1444 | * @vsi: the VSI we care about | |
1445 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
1446 | * | |
1447 | **/ | |
1448 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
1449 | struct i40e_q_vector *q_vector) | |
1450 | { | |
1451 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
1452 | bool rx = false, tx = false; |
1453 | u32 rxval, txval; | |
de32e3ef | 1454 | int vector; |
65e87c03 JK |
1455 | int idx = q_vector->v_idx; |
1456 | int rx_itr_setting, tx_itr_setting; | |
de32e3ef CW |
1457 | |
1458 | vector = (q_vector->v_idx + vsi->base_vector); | |
ee2319cf JB |
1459 | |
1460 | /* avoid dynamic calculation if in countdown mode OR if | |
1461 | * all dynamic is disabled | |
1462 | */ | |
8f5e39ce JB |
1463 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
1464 | ||
3c234c47 CW |
1465 | rx_itr_setting = get_rx_itr(vsi, idx); |
1466 | tx_itr_setting = get_tx_itr(vsi, idx); | |
65e87c03 | 1467 | |
ee2319cf | 1468 | if (q_vector->itr_countdown > 0 || |
65e87c03 JK |
1469 | (!ITR_IS_DYNAMIC(rx_itr_setting) && |
1470 | !ITR_IS_DYNAMIC(tx_itr_setting))) { | |
ee2319cf JB |
1471 | goto enable_int; |
1472 | } | |
1473 | ||
65e87c03 | 1474 | if (ITR_IS_DYNAMIC(rx_itr_setting)) { |
8f5e39ce JB |
1475 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
1476 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 1477 | } |
4eeb1fff | 1478 | |
65e87c03 | 1479 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
1480 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
1481 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
1482 | } | |
4eeb1fff | 1483 | |
8f5e39ce JB |
1484 | if (rx || tx) { |
1485 | /* get the higher of the two ITR adjustments and | |
1486 | * use the same value for both ITR registers | |
1487 | * when in adaptive mode (Rx and/or Tx) | |
1488 | */ | |
1489 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
1490 | ||
1491 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
1492 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
1493 | tx = true; | |
1494 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
1495 | rx = true; | |
de32e3ef | 1496 | } |
8f5e39ce JB |
1497 | |
1498 | /* only need to enable the interrupt once, but need | |
1499 | * to possibly update both ITR values | |
1500 | */ | |
1501 | if (rx) { | |
1502 | /* set the INTENA_MSK_MASK so that this first write | |
1503 | * won't actually enable the interrupt, instead just | |
1504 | * updating the ITR (it's bit 31 PF and VF) | |
1505 | */ | |
1506 | rxval |= BIT(31); | |
1507 | /* don't check _DOWN because interrupt isn't being enabled */ | |
1508 | wr32(hw, INTREG(vector - 1), rxval); | |
1509 | } | |
1510 | ||
ee2319cf | 1511 | enable_int: |
0da36b97 | 1512 | if (!test_bit(__I40E_VSI_DOWN, vsi->state)) |
8f5e39ce | 1513 | wr32(hw, INTREG(vector - 1), txval); |
ee2319cf JB |
1514 | |
1515 | if (q_vector->itr_countdown) | |
1516 | q_vector->itr_countdown--; | |
1517 | else | |
1518 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
1519 | } |
1520 | ||
7f12ad74 GR |
1521 | /** |
1522 | * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1523 | * @napi: napi struct with our devices info in it | |
1524 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1525 | * | |
1526 | * This function will clean all queues associated with a q_vector. | |
1527 | * | |
1528 | * Returns the amount of work done | |
1529 | **/ | |
1530 | int i40evf_napi_poll(struct napi_struct *napi, int budget) | |
1531 | { | |
1532 | struct i40e_q_vector *q_vector = | |
1533 | container_of(napi, struct i40e_q_vector, napi); | |
1534 | struct i40e_vsi *vsi = q_vector->vsi; | |
1535 | struct i40e_ring *ring; | |
1536 | bool clean_complete = true; | |
c29af37f | 1537 | bool arm_wb = false; |
7f12ad74 | 1538 | int budget_per_ring; |
32b3e08f | 1539 | int work_done = 0; |
7f12ad74 | 1540 | |
0da36b97 | 1541 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) { |
7f12ad74 GR |
1542 | napi_complete(napi); |
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | /* Since the actual Tx work is minimal, we can give the Tx a larger | |
1547 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1548 | */ | |
c29af37f | 1549 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 1550 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
1551 | clean_complete = false; |
1552 | continue; | |
1553 | } | |
1554 | arm_wb |= ring->arm_wb; | |
0deda868 | 1555 | ring->arm_wb = false; |
c29af37f | 1556 | } |
7f12ad74 | 1557 | |
c67caceb AD |
1558 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1559 | if (budget <= 0) | |
1560 | goto tx_only; | |
1561 | ||
7f12ad74 GR |
1562 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1563 | * allow the budget to go below 1 because that would exit polling early. | |
1564 | */ | |
1565 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
1566 | ||
a132af24 | 1567 | i40e_for_each_ring(ring, q_vector->rx) { |
ab9ad98e | 1568 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
1569 | |
1570 | work_done += cleaned; | |
f2edaaaa AD |
1571 | /* if we clean as many as budgeted, we must not be done */ |
1572 | if (cleaned >= budget_per_ring) | |
1573 | clean_complete = false; | |
a132af24 | 1574 | } |
7f12ad74 GR |
1575 | |
1576 | /* If work not completed, return budget and polling will return */ | |
c29af37f | 1577 | if (!clean_complete) { |
96db776a AB |
1578 | const cpumask_t *aff_mask = &q_vector->affinity_mask; |
1579 | int cpu_id = smp_processor_id(); | |
1580 | ||
1581 | /* It is possible that the interrupt affinity has changed but, | |
1582 | * if the cpu is pegged at 100%, polling will never exit while | |
1583 | * traffic continues and the interrupt will be stuck on this | |
1584 | * cpu. We check to make sure affinity is correct before we | |
1585 | * continue to poll, otherwise we must stop polling so the | |
1586 | * interrupt can move to the correct cpu. | |
1587 | */ | |
1588 | if (likely(cpumask_test_cpu(cpu_id, aff_mask))) { | |
c67caceb | 1589 | tx_only: |
96db776a AB |
1590 | if (arm_wb) { |
1591 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
1592 | i40e_enable_wb_on_itr(vsi, q_vector); | |
1593 | } | |
1594 | return budget; | |
164c9f54 | 1595 | } |
c29af37f | 1596 | } |
7f12ad74 | 1597 | |
8e0764b4 ASJ |
1598 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
1599 | q_vector->arm_wb_state = false; | |
1600 | ||
7f12ad74 | 1601 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 1602 | napi_complete_done(napi, work_done); |
96db776a AB |
1603 | |
1604 | /* If we're prematurely stopping polling to fix the interrupt | |
1605 | * affinity we want to make sure polling starts back up so we | |
1606 | * issue a call to i40evf_force_wb which triggers a SW interrupt. | |
1607 | */ | |
1608 | if (!clean_complete) | |
1609 | i40evf_force_wb(vsi, q_vector); | |
1610 | else | |
1611 | i40e_update_enable_itr(vsi, q_vector); | |
1612 | ||
6beb84a7 | 1613 | return min(work_done, budget - 1); |
7f12ad74 GR |
1614 | } |
1615 | ||
1616 | /** | |
3e587cf3 | 1617 | * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW |
7f12ad74 GR |
1618 | * @skb: send buffer |
1619 | * @tx_ring: ring to send buffer on | |
1620 | * @flags: the tx flags to be set | |
1621 | * | |
1622 | * Checks the skb and set up correspondingly several generic transmit flags | |
1623 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
1624 | * | |
1625 | * Returns error code indicate the frame should be dropped upon error and the | |
1626 | * otherwise returns 0 to indicate the flags has been set properly. | |
1627 | **/ | |
3e587cf3 JB |
1628 | static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb, |
1629 | struct i40e_ring *tx_ring, | |
1630 | u32 *flags) | |
7f12ad74 GR |
1631 | { |
1632 | __be16 protocol = skb->protocol; | |
1633 | u32 tx_flags = 0; | |
1634 | ||
31eaaccf GR |
1635 | if (protocol == htons(ETH_P_8021Q) && |
1636 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
1637 | /* When HW VLAN acceleration is turned off by the user the | |
1638 | * stack sets the protocol to 8021q so that the driver | |
1639 | * can take any steps required to support the SW only | |
1640 | * VLAN handling. In our case the driver doesn't need | |
1641 | * to take any further steps so just set the protocol | |
1642 | * to the encapsulated ethertype. | |
1643 | */ | |
1644 | skb->protocol = vlan_get_protocol(skb); | |
1645 | goto out; | |
1646 | } | |
1647 | ||
7f12ad74 | 1648 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
1649 | if (skb_vlan_tag_present(skb)) { |
1650 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
7f12ad74 GR |
1651 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
1652 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
1653 | } else if (protocol == htons(ETH_P_8021Q)) { | |
1654 | struct vlan_hdr *vhdr, _vhdr; | |
6995b36c | 1655 | |
7f12ad74 GR |
1656 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
1657 | if (!vhdr) | |
1658 | return -EINVAL; | |
1659 | ||
1660 | protocol = vhdr->h_vlan_encapsulated_proto; | |
1661 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
1662 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
1663 | } | |
1664 | ||
31eaaccf | 1665 | out: |
7f12ad74 GR |
1666 | *flags = tx_flags; |
1667 | return 0; | |
1668 | } | |
1669 | ||
1670 | /** | |
1671 | * i40e_tso - set up the tso context descriptor | |
52ea3e80 | 1672 | * @first: pointer to first Tx buffer for xmit |
7f12ad74 | 1673 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 1674 | * @cd_type_cmd_tso_mss: Quad Word 1 |
7f12ad74 GR |
1675 | * |
1676 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
1677 | **/ | |
52ea3e80 AD |
1678 | static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, |
1679 | u64 *cd_type_cmd_tso_mss) | |
7f12ad74 | 1680 | { |
52ea3e80 | 1681 | struct sk_buff *skb = first->skb; |
03f9d6a5 | 1682 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
1683 | union { |
1684 | struct iphdr *v4; | |
1685 | struct ipv6hdr *v6; | |
1686 | unsigned char *hdr; | |
1687 | } ip; | |
c49a7bc3 AD |
1688 | union { |
1689 | struct tcphdr *tcp; | |
5453205c | 1690 | struct udphdr *udp; |
c49a7bc3 AD |
1691 | unsigned char *hdr; |
1692 | } l4; | |
1693 | u32 paylen, l4_offset; | |
52ea3e80 | 1694 | u16 gso_segs, gso_size; |
7f12ad74 | 1695 | int err; |
7f12ad74 | 1696 | |
e9f6563d SN |
1697 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1698 | return 0; | |
1699 | ||
7f12ad74 GR |
1700 | if (!skb_is_gso(skb)) |
1701 | return 0; | |
1702 | ||
fe6d4aa4 FR |
1703 | err = skb_cow_head(skb, 0); |
1704 | if (err < 0) | |
1705 | return err; | |
7f12ad74 | 1706 | |
c777019a AD |
1707 | ip.hdr = skb_network_header(skb); |
1708 | l4.hdr = skb_transport_header(skb); | |
85e76d03 | 1709 | |
c777019a AD |
1710 | /* initialize outer IP header fields */ |
1711 | if (ip.v4->version == 4) { | |
1712 | ip.v4->tot_len = 0; | |
1713 | ip.v4->check = 0; | |
c49a7bc3 | 1714 | } else { |
c777019a AD |
1715 | ip.v6->payload_len = 0; |
1716 | } | |
1717 | ||
577389a5 | 1718 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 1719 | SKB_GSO_GRE_CSUM | |
7e13318d | 1720 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 1721 | SKB_GSO_IPXIP6 | |
577389a5 | 1722 | SKB_GSO_UDP_TUNNEL | |
5453205c | 1723 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
1724 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
1725 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
1726 | l4.udp->len = 0; | |
1727 | ||
5453205c AD |
1728 | /* determine offset of outer transport header */ |
1729 | l4_offset = l4.hdr - skb->data; | |
1730 | ||
1731 | /* remove payload length from outer checksum */ | |
24d41e5e | 1732 | paylen = skb->len - l4_offset; |
b9c015d4 JK |
1733 | csum_replace_by_diff(&l4.udp->check, |
1734 | (__force __wsum)htonl(paylen)); | |
5453205c AD |
1735 | } |
1736 | ||
c777019a AD |
1737 | /* reset pointers to inner headers */ |
1738 | ip.hdr = skb_inner_network_header(skb); | |
1739 | l4.hdr = skb_inner_transport_header(skb); | |
1740 | ||
1741 | /* initialize inner IP header fields */ | |
1742 | if (ip.v4->version == 4) { | |
1743 | ip.v4->tot_len = 0; | |
1744 | ip.v4->check = 0; | |
1745 | } else { | |
1746 | ip.v6->payload_len = 0; | |
1747 | } | |
7f12ad74 GR |
1748 | } |
1749 | ||
c49a7bc3 AD |
1750 | /* determine offset of inner transport header */ |
1751 | l4_offset = l4.hdr - skb->data; | |
1752 | ||
1753 | /* remove payload length from inner checksum */ | |
24d41e5e | 1754 | paylen = skb->len - l4_offset; |
b9c015d4 | 1755 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); |
c49a7bc3 AD |
1756 | |
1757 | /* compute length of segmentation header */ | |
1758 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
7f12ad74 | 1759 | |
52ea3e80 AD |
1760 | /* pull values out of skb_shinfo */ |
1761 | gso_size = skb_shinfo(skb)->gso_size; | |
1762 | gso_segs = skb_shinfo(skb)->gso_segs; | |
1763 | ||
1764 | /* update GSO size and bytecount with header size */ | |
1765 | first->gso_segs = gso_segs; | |
1766 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
1767 | ||
7f12ad74 GR |
1768 | /* find the field values */ |
1769 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
1770 | cd_tso_len = skb->len - *hdr_len; | |
52ea3e80 | 1771 | cd_mss = gso_size; |
03f9d6a5 AD |
1772 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
1773 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
1774 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
7f12ad74 GR |
1775 | return 1; |
1776 | } | |
1777 | ||
1778 | /** | |
1779 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
1780 | * @skb: send buffer | |
89232c3b | 1781 | * @tx_flags: pointer to Tx flags currently set |
7f12ad74 GR |
1782 | * @td_cmd: Tx descriptor command bits to set |
1783 | * @td_offset: Tx descriptor header offsets to set | |
529f1f65 | 1784 | * @tx_ring: Tx descriptor ring |
7f12ad74 GR |
1785 | * @cd_tunneling: ptr to context desc bits |
1786 | **/ | |
529f1f65 AD |
1787 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
1788 | u32 *td_cmd, u32 *td_offset, | |
1789 | struct i40e_ring *tx_ring, | |
1790 | u32 *cd_tunneling) | |
7f12ad74 | 1791 | { |
b96b78f2 AD |
1792 | union { |
1793 | struct iphdr *v4; | |
1794 | struct ipv6hdr *v6; | |
1795 | unsigned char *hdr; | |
1796 | } ip; | |
1797 | union { | |
1798 | struct tcphdr *tcp; | |
1799 | struct udphdr *udp; | |
1800 | unsigned char *hdr; | |
1801 | } l4; | |
a3fd9d88 | 1802 | unsigned char *exthdr; |
d1bd743b | 1803 | u32 offset, cmd = 0; |
a3fd9d88 | 1804 | __be16 frag_off; |
b96b78f2 AD |
1805 | u8 l4_proto = 0; |
1806 | ||
529f1f65 AD |
1807 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1808 | return 0; | |
1809 | ||
b96b78f2 AD |
1810 | ip.hdr = skb_network_header(skb); |
1811 | l4.hdr = skb_transport_header(skb); | |
7f12ad74 | 1812 | |
475b4205 AD |
1813 | /* compute outer L2 header size */ |
1814 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
1815 | ||
7f12ad74 | 1816 | if (skb->encapsulation) { |
d1bd743b | 1817 | u32 tunnel = 0; |
a0064728 AD |
1818 | /* define outer network header type */ |
1819 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
1820 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1821 | I40E_TX_CTX_EXT_IP_IPV4 : | |
1822 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1823 | ||
a0064728 AD |
1824 | l4_proto = ip.v4->protocol; |
1825 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 1826 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
1827 | |
1828 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 1829 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
1830 | if (l4.hdr != exthdr) |
1831 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1832 | &l4_proto, &frag_off); | |
a0064728 AD |
1833 | } |
1834 | ||
1835 | /* define outer transport */ | |
1836 | switch (l4_proto) { | |
45991204 | 1837 | case IPPROTO_UDP: |
475b4205 | 1838 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
89232c3b | 1839 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
45991204 | 1840 | break; |
a0064728 | 1841 | case IPPROTO_GRE: |
475b4205 | 1842 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 AD |
1843 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
1844 | break; | |
577389a5 AD |
1845 | case IPPROTO_IPIP: |
1846 | case IPPROTO_IPV6: | |
1847 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; | |
1848 | l4.hdr = skb_inner_network_header(skb); | |
1849 | break; | |
45991204 | 1850 | default: |
529f1f65 AD |
1851 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1852 | return -1; | |
1853 | ||
1854 | skb_checksum_help(skb); | |
1855 | return 0; | |
45991204 | 1856 | } |
b96b78f2 | 1857 | |
577389a5 AD |
1858 | /* compute outer L3 header size */ |
1859 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
1860 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
1861 | ||
1862 | /* switch IP header pointer from outer to inner header */ | |
1863 | ip.hdr = skb_inner_network_header(skb); | |
1864 | ||
475b4205 AD |
1865 | /* compute tunnel header size */ |
1866 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
1867 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
1868 | ||
5453205c AD |
1869 | /* indicate if we need to offload outer UDP header */ |
1870 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 1871 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
1872 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
1873 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
1874 | ||
475b4205 AD |
1875 | /* record tunnel offload values */ |
1876 | *cd_tunneling |= tunnel; | |
1877 | ||
b96b78f2 | 1878 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 1879 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 1880 | l4_proto = 0; |
7f12ad74 | 1881 | |
a0064728 AD |
1882 | /* reset type as we transition from outer to inner headers */ |
1883 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
1884 | if (ip.v4->version == 4) | |
1885 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
1886 | if (ip.v6->version == 6) | |
89232c3b | 1887 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
7f12ad74 GR |
1888 | } |
1889 | ||
1890 | /* Enable IP checksum offloads */ | |
89232c3b | 1891 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 1892 | l4_proto = ip.v4->protocol; |
7f12ad74 GR |
1893 | /* the stack computes the IP header already, the only time we |
1894 | * need the hardware to recompute it is in the case of TSO. | |
1895 | */ | |
475b4205 AD |
1896 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1897 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
1898 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 1899 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 1900 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
1901 | |
1902 | exthdr = ip.hdr + sizeof(*ip.v6); | |
1903 | l4_proto = ip.v6->nexthdr; | |
1904 | if (l4.hdr != exthdr) | |
1905 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1906 | &l4_proto, &frag_off); | |
7f12ad74 | 1907 | } |
b96b78f2 | 1908 | |
475b4205 AD |
1909 | /* compute inner L3 header size */ |
1910 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
7f12ad74 GR |
1911 | |
1912 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 1913 | switch (l4_proto) { |
7f12ad74 GR |
1914 | case IPPROTO_TCP: |
1915 | /* enable checksum offloads */ | |
475b4205 AD |
1916 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
1917 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1918 | break; |
1919 | case IPPROTO_SCTP: | |
1920 | /* enable SCTP checksum offload */ | |
475b4205 AD |
1921 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
1922 | offset |= (sizeof(struct sctphdr) >> 2) << | |
1923 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1924 | break; |
1925 | case IPPROTO_UDP: | |
1926 | /* enable UDP checksum offload */ | |
475b4205 AD |
1927 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
1928 | offset |= (sizeof(struct udphdr) >> 2) << | |
1929 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1930 | break; |
1931 | default: | |
529f1f65 AD |
1932 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1933 | return -1; | |
1934 | skb_checksum_help(skb); | |
1935 | return 0; | |
7f12ad74 | 1936 | } |
475b4205 AD |
1937 | |
1938 | *td_cmd |= cmd; | |
1939 | *td_offset |= offset; | |
529f1f65 AD |
1940 | |
1941 | return 1; | |
7f12ad74 GR |
1942 | } |
1943 | ||
1944 | /** | |
1945 | * i40e_create_tx_ctx Build the Tx context descriptor | |
1946 | * @tx_ring: ring to create the descriptor on | |
1947 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
1948 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
1949 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
1950 | **/ | |
1951 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
1952 | const u64 cd_type_cmd_tso_mss, | |
1953 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
1954 | { | |
1955 | struct i40e_tx_context_desc *context_desc; | |
1956 | int i = tx_ring->next_to_use; | |
1957 | ||
ff40dd5d JB |
1958 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
1959 | !cd_tunneling && !cd_l2tag2) | |
7f12ad74 GR |
1960 | return; |
1961 | ||
1962 | /* grab the next descriptor */ | |
1963 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); | |
1964 | ||
1965 | i++; | |
1966 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
1967 | ||
1968 | /* cpu_to_le32 and assign to struct fields */ | |
1969 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
1970 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 1971 | context_desc->rsvd = cpu_to_le16(0); |
7f12ad74 GR |
1972 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
1973 | } | |
1974 | ||
4eeb1fff | 1975 | /** |
3f3f7cb8 | 1976 | * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 1977 | * @skb: send buffer |
71da6197 | 1978 | * |
3f3f7cb8 AD |
1979 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
1980 | * and so we need to figure out the cases where we need to linearize the skb. | |
1981 | * | |
1982 | * For TSO we need to count the TSO header and segment payload separately. | |
1983 | * As such we need to check cases where we have 7 fragments or more as we | |
1984 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
1985 | * the segment payload in the first descriptor, and another 7 for the | |
1986 | * fragments. | |
71da6197 | 1987 | **/ |
2d37490b | 1988 | bool __i40evf_chk_linearize(struct sk_buff *skb) |
71da6197 | 1989 | { |
2d37490b | 1990 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 1991 | int nr_frags, sum; |
71da6197 | 1992 | |
3f3f7cb8 | 1993 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 1994 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 1995 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 1996 | return false; |
71da6197 | 1997 | |
2d37490b | 1998 | /* We need to walk through the list and validate that each group |
841493a3 | 1999 | * of 6 fragments totals at least gso_size. |
2d37490b | 2000 | */ |
3f3f7cb8 | 2001 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
2002 | frag = &skb_shinfo(skb)->frags[0]; |
2003 | ||
2004 | /* Initialize size to the negative value of gso_size minus 1. We | |
2005 | * use this as the worst case scenerio in which the frag ahead | |
2006 | * of us only provides one byte which is why we are limited to 6 | |
2007 | * descriptors for a single transmit as the header and previous | |
2008 | * fragment are already consuming 2 descriptors. | |
2009 | */ | |
3f3f7cb8 | 2010 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 2011 | |
3f3f7cb8 AD |
2012 | /* Add size of frags 0 through 4 to create our initial sum */ |
2013 | sum += skb_frag_size(frag++); | |
2014 | sum += skb_frag_size(frag++); | |
2015 | sum += skb_frag_size(frag++); | |
2016 | sum += skb_frag_size(frag++); | |
2017 | sum += skb_frag_size(frag++); | |
2d37490b AD |
2018 | |
2019 | /* Walk through fragments adding latest fragment, testing it, and | |
2020 | * then removing stale fragments from the sum. | |
2021 | */ | |
2022 | stale = &skb_shinfo(skb)->frags[0]; | |
2023 | for (;;) { | |
3f3f7cb8 | 2024 | sum += skb_frag_size(frag++); |
2d37490b AD |
2025 | |
2026 | /* if sum is negative we failed to make sufficient progress */ | |
2027 | if (sum < 0) | |
2028 | return true; | |
2029 | ||
841493a3 | 2030 | if (!nr_frags--) |
2d37490b AD |
2031 | break; |
2032 | ||
3f3f7cb8 | 2033 | sum -= skb_frag_size(stale++); |
71da6197 AS |
2034 | } |
2035 | ||
2d37490b | 2036 | return false; |
71da6197 AS |
2037 | } |
2038 | ||
8f6a2b05 JB |
2039 | /** |
2040 | * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions | |
2041 | * @tx_ring: the ring to be checked | |
2042 | * @size: the size buffer we want to assure is available | |
2043 | * | |
2044 | * Returns -EBUSY if a stop is needed, else 0 | |
2045 | **/ | |
4ec441df | 2046 | int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
8f6a2b05 JB |
2047 | { |
2048 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2049 | /* Memory barrier before checking head and tail */ | |
2050 | smp_mb(); | |
2051 | ||
2052 | /* Check again in a case another CPU has just made room available. */ | |
2053 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
2054 | return -EBUSY; | |
2055 | ||
2056 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
2057 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
2058 | ++tx_ring->tx_stats.restart_queue; | |
2059 | return 0; | |
2060 | } | |
2061 | ||
7f12ad74 | 2062 | /** |
3e587cf3 | 2063 | * i40evf_tx_map - Build the Tx descriptor |
7f12ad74 GR |
2064 | * @tx_ring: ring to send buffer on |
2065 | * @skb: send buffer | |
2066 | * @first: first buffer info buffer to use | |
2067 | * @tx_flags: collected send information | |
2068 | * @hdr_len: size of the packet header | |
2069 | * @td_cmd: the command field in the descriptor | |
2070 | * @td_offset: offset for checksum or crc | |
2071 | **/ | |
3e587cf3 JB |
2072 | static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
2073 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2074 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
7f12ad74 GR |
2075 | { |
2076 | unsigned int data_len = skb->data_len; | |
2077 | unsigned int size = skb_headlen(skb); | |
2078 | struct skb_frag_struct *frag; | |
2079 | struct i40e_tx_buffer *tx_bi; | |
2080 | struct i40e_tx_desc *tx_desc; | |
2081 | u16 i = tx_ring->next_to_use; | |
2082 | u32 td_tag = 0; | |
2083 | dma_addr_t dma; | |
7f12ad74 GR |
2084 | |
2085 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { | |
2086 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2087 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2088 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2089 | } | |
2090 | ||
7f12ad74 GR |
2091 | first->tx_flags = tx_flags; |
2092 | ||
2093 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2094 | ||
2095 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
2096 | tx_bi = first; | |
2097 | ||
2098 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
2099 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
2100 | ||
7f12ad74 GR |
2101 | if (dma_mapping_error(tx_ring->dev, dma)) |
2102 | goto dma_error; | |
2103 | ||
2104 | /* record length, and DMA address */ | |
2105 | dma_unmap_len_set(tx_bi, len, size); | |
2106 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2107 | ||
5c4654da AD |
2108 | /* align size to end of page */ |
2109 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
7f12ad74 GR |
2110 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2111 | ||
2112 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
2113 | tx_desc->cmd_type_offset_bsz = | |
2114 | build_ctob(td_cmd, td_offset, | |
5c4654da | 2115 | max_data, td_tag); |
7f12ad74 GR |
2116 | |
2117 | tx_desc++; | |
2118 | i++; | |
6a7fded7 | 2119 | |
7f12ad74 GR |
2120 | if (i == tx_ring->count) { |
2121 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2122 | i = 0; | |
2123 | } | |
2124 | ||
5c4654da AD |
2125 | dma += max_data; |
2126 | size -= max_data; | |
7f12ad74 | 2127 | |
5c4654da | 2128 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
7f12ad74 GR |
2129 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2130 | } | |
2131 | ||
2132 | if (likely(!data_len)) | |
2133 | break; | |
2134 | ||
2135 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, | |
2136 | size, td_tag); | |
2137 | ||
2138 | tx_desc++; | |
2139 | i++; | |
6a7fded7 | 2140 | |
7f12ad74 GR |
2141 | if (i == tx_ring->count) { |
2142 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2143 | i = 0; | |
2144 | } | |
2145 | ||
2146 | size = skb_frag_size(frag); | |
2147 | data_len -= size; | |
2148 | ||
2149 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, | |
2150 | DMA_TO_DEVICE); | |
2151 | ||
2152 | tx_bi = &tx_ring->tx_bi[i]; | |
2153 | } | |
2154 | ||
1dc8b538 | 2155 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
7f12ad74 GR |
2156 | |
2157 | i++; | |
2158 | if (i == tx_ring->count) | |
2159 | i = 0; | |
2160 | ||
2161 | tx_ring->next_to_use = i; | |
2162 | ||
4ec441df | 2163 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
6a7fded7 | 2164 | |
b1cb07db PB |
2165 | /* write last descriptor with RS and EOP bits */ |
2166 | td_cmd |= I40E_TXD_CMD; | |
6a7fded7 | 2167 | tx_desc->cmd_type_offset_bsz = |
1dc8b538 AD |
2168 | build_ctob(td_cmd, td_offset, size, td_tag); |
2169 | ||
2170 | /* Force memory writes to complete before letting h/w know there | |
2171 | * are new descriptors to fetch. | |
2172 | * | |
2173 | * We also use this memory barrier to make certain all of the | |
2174 | * status bits have been updated before next_to_watch is written. | |
2175 | */ | |
2176 | wmb(); | |
2177 | ||
2178 | /* set next_to_watch value indicating a packet is present */ | |
2179 | first->next_to_watch = tx_desc; | |
6a7fded7 | 2180 | |
7f12ad74 | 2181 | /* notify HW of packet */ |
b1cb07db | 2182 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { |
6a7fded7 | 2183 | writel(i, tx_ring->tail); |
1dc8b538 AD |
2184 | |
2185 | /* we need this if more than one processor can write to our tail | |
2186 | * at a time, it synchronizes IO on IA64/Altix systems | |
2187 | */ | |
2188 | mmiowb(); | |
6a7fded7 | 2189 | } |
1dc8b538 | 2190 | |
7f12ad74 GR |
2191 | return; |
2192 | ||
2193 | dma_error: | |
2194 | dev_info(tx_ring->dev, "TX DMA map failed\n"); | |
2195 | ||
2196 | /* clear dma mappings for failed tx_bi map */ | |
2197 | for (;;) { | |
2198 | tx_bi = &tx_ring->tx_bi[i]; | |
2199 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); | |
2200 | if (tx_bi == first) | |
2201 | break; | |
2202 | if (i == 0) | |
2203 | i = tx_ring->count; | |
2204 | i--; | |
2205 | } | |
2206 | ||
2207 | tx_ring->next_to_use = i; | |
2208 | } | |
2209 | ||
7f12ad74 GR |
2210 | /** |
2211 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2212 | * @skb: send buffer | |
2213 | * @tx_ring: ring to send buffer on | |
2214 | * | |
2215 | * Returns NETDEV_TX_OK if sent, else an error code | |
2216 | **/ | |
2217 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2218 | struct i40e_ring *tx_ring) | |
2219 | { | |
2220 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2221 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2222 | struct i40e_tx_buffer *first; | |
2223 | u32 td_offset = 0; | |
2224 | u32 tx_flags = 0; | |
2225 | __be16 protocol; | |
2226 | u32 td_cmd = 0; | |
2227 | u8 hdr_len = 0; | |
4ec441df | 2228 | int tso, count; |
6995b36c | 2229 | |
b74118f0 JB |
2230 | /* prefetch the data, we'll need it later */ |
2231 | prefetch(skb->data); | |
2232 | ||
ed0980c4 SP |
2233 | i40e_trace(xmit_frame_ring, skb, tx_ring); |
2234 | ||
4ec441df | 2235 | count = i40e_xmit_descriptor_count(skb); |
2d37490b | 2236 | if (i40e_chk_linearize(skb, count)) { |
52ea3e80 AD |
2237 | if (__skb_linearize(skb)) { |
2238 | dev_kfree_skb_any(skb); | |
2239 | return NETDEV_TX_OK; | |
2240 | } | |
5c4654da | 2241 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
2242 | tx_ring->tx_stats.tx_linearize++; |
2243 | } | |
4ec441df AD |
2244 | |
2245 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2246 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
2247 | * + 4 desc gap to avoid the cache line where head is, | |
2248 | * + 1 desc for context descriptor, | |
2249 | * otherwise try next time | |
2250 | */ | |
2251 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
2252 | tx_ring->tx_stats.tx_busy++; | |
7f12ad74 | 2253 | return NETDEV_TX_BUSY; |
4ec441df | 2254 | } |
7f12ad74 | 2255 | |
52ea3e80 AD |
2256 | /* record the location of the first descriptor for this packet */ |
2257 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2258 | first->skb = skb; | |
2259 | first->bytecount = skb->len; | |
2260 | first->gso_segs = 1; | |
2261 | ||
7f12ad74 | 2262 | /* prepare the xmit flags */ |
3e587cf3 | 2263 | if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) |
7f12ad74 GR |
2264 | goto out_drop; |
2265 | ||
2266 | /* obtain protocol of skb */ | |
a12c4158 | 2267 | protocol = vlan_get_protocol(skb); |
7f12ad74 | 2268 | |
7f12ad74 GR |
2269 | /* setup IPv4/IPv6 offloads */ |
2270 | if (protocol == htons(ETH_P_IP)) | |
2271 | tx_flags |= I40E_TX_FLAGS_IPV4; | |
2272 | else if (protocol == htons(ETH_P_IPV6)) | |
2273 | tx_flags |= I40E_TX_FLAGS_IPV6; | |
2274 | ||
52ea3e80 | 2275 | tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); |
7f12ad74 GR |
2276 | |
2277 | if (tso < 0) | |
2278 | goto out_drop; | |
2279 | else if (tso) | |
2280 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2281 | ||
7f12ad74 | 2282 | /* Always offload the checksum, since it's in the data descriptor */ |
529f1f65 AD |
2283 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, |
2284 | tx_ring, &cd_tunneling); | |
2285 | if (tso < 0) | |
2286 | goto out_drop; | |
7f12ad74 | 2287 | |
3bc67973 AD |
2288 | skb_tx_timestamp(skb); |
2289 | ||
2290 | /* always enable CRC insertion offload */ | |
2291 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2292 | ||
7f12ad74 GR |
2293 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
2294 | cd_tunneling, cd_l2tag2); | |
2295 | ||
3e587cf3 JB |
2296 | i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len, |
2297 | td_cmd, td_offset); | |
7f12ad74 | 2298 | |
7f12ad74 GR |
2299 | return NETDEV_TX_OK; |
2300 | ||
2301 | out_drop: | |
ed0980c4 | 2302 | i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); |
52ea3e80 AD |
2303 | dev_kfree_skb_any(first->skb); |
2304 | first->skb = NULL; | |
7f12ad74 GR |
2305 | return NETDEV_TX_OK; |
2306 | } | |
2307 | ||
2308 | /** | |
2309 | * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
2310 | * @skb: send buffer | |
2311 | * @netdev: network interface device structure | |
2312 | * | |
2313 | * Returns NETDEV_TX_OK if sent, else an error code | |
2314 | **/ | |
2315 | netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2316 | { | |
2317 | struct i40evf_adapter *adapter = netdev_priv(netdev); | |
0dd438d8 | 2318 | struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping]; |
7f12ad74 GR |
2319 | |
2320 | /* hardware can't handle really short frames, hardware padding works | |
2321 | * beyond this point | |
2322 | */ | |
2323 | if (unlikely(skb->len < I40E_MIN_TX_LEN)) { | |
2324 | if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len)) | |
2325 | return NETDEV_TX_OK; | |
2326 | skb->len = I40E_MIN_TX_LEN; | |
2327 | skb_set_tail_pointer(skb, I40E_MIN_TX_LEN); | |
2328 | } | |
2329 | ||
2330 | return i40e_xmit_frame_ring(skb, tx_ring); | |
2331 | } |