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defconfig: exynos9610: Re-add dropped Wi-Fi AP options lost
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / ethernet / dec / tulip / uli526x.c
CommitLineData
4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
e02fb7aa
JP		 15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
4689ced9
PC		 17#define DRV_NAME "uli526x"
18#define DRV_VERSION "0.9.3"
19#define DRV_RELDATE "2005-7-29"
20
21#include <linux/module.h>
22
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/timer.h>
4689ced9
PC		 26#include <linux/errno.h>
27#include <linux/ioport.h>
4689ced9
PC		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/skbuff.h>
35#include <linux/delay.h>
36#include <linux/spinlock.h>
6cafa99f 37#include <linux/dma-mapping.h>
1977f032 38#include <linux/bitops.h>
4689ced9
PC		 39
40#include <asm/processor.h>
4689ced9
PC		 41#include <asm/io.h>
42#include <asm/dma.h>
7c0f6ba6 43#include <linux/uaccess.h>
4689ced9 44
3acf4b5c
FR		 45#define uw32(reg, val) iowrite32(val, ioaddr + (reg))
46#define ur32(reg) ioread32(ioaddr + (reg))
4689ced9
PC		 47
48/* Board/System/Debug information/definition ---------------- */
49#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
50#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
51
52#define ULI526X_IO_SIZE 0x100
53#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
54#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
55#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
56#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
57#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
58#define TX_BUF_ALLOC 0x600
59#define RX_ALLOC_SIZE 0x620
60#define ULI526X_RESET 1
61#define CR0_DEFAULT 0
945a7876 62#define CR6_DEFAULT 0x22200000
4689ced9
PC		 63#define CR7_DEFAULT 0x180c1
64#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
65#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
66#define MAX_PACKET_SIZE 1514
67#define ULI5261_MAX_MULTICAST 14
68#define RX_COPY_SIZE 100
69#define MAX_CHECK_PACKET 0x8000
70
71#define ULI526X_10MHF 0
72#define ULI526X_100MHF 1
73#define ULI526X_10MFD 4
74#define ULI526X_100MFD 5
75#define ULI526X_AUTO 8
76
77#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
78#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
79#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
80#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
81#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
82#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
83
84#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
85#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
86#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
87
e02fb7aa
JP		 88#define ULI526X_DBUG(dbug_now, msg, value) \
89do { \
90 if (uli526x_debug || (dbug_now)) \
91 pr_err("%s %lx\n", (msg), (long) (value)); \
92} while (0)
4689ced9 93
e02fb7aa
JP		 94#define SHOW_MEDIA_TYPE(mode) \
95 pr_err("Change Speed to %sMhz %s duplex\n", \
96 mode & 1 ? "100" : "10", \
97 mode & 4 ? "full" : "half");
4689ced9
PC		 98
99
100/* CR9 definition: SROM/MII */
101#define CR9_SROM_READ 0x4800
102#define CR9_SRCS 0x1
103#define CR9_SRCLK 0x2
104#define CR9_CRDOUT 0x8
105#define SROM_DATA_0 0x0
106#define SROM_DATA_1 0x4
107#define PHY_DATA_1 0x20000
108#define PHY_DATA_0 0x00000
109#define MDCLKH 0x10000
110
111#define PHY_POWER_DOWN 0x800
112
113#define SROM_V41_CODE 0x14
114
4689ced9
PC		 115/* Structure/enum declaration ------------------------------- */
116struct tx_desc {
c559a5bc 117 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 118 char *tx_buf_ptr; /* Data for us */
119 struct tx_desc *next_tx_desc;
120} __attribute__(( aligned(32) ));
121
122struct rx_desc {
c559a5bc 123 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 124 struct sk_buff *rx_skb_ptr; /* Data for us */
125 struct rx_desc *next_rx_desc;
126} __attribute__(( aligned(32) ));
127
128struct uli526x_board_info {
3acf4b5c
FR		 129 struct uli_phy_ops {
130 void (*write)(struct uli526x_board_info *, u8, u8, u16);
131 u16 (*read)(struct uli526x_board_info *, u8, u8);
132 } phy;
945a7876 133 struct net_device *next_dev; /* next device */
4689ced9
PC		 134 struct pci_dev *pdev; /* PCI device */
135 spinlock_t lock;
136
3acf4b5c 137 void __iomem *ioaddr; /* I/O base address */
4689ced9
PC		 138 u32 cr0_data;
139 u32 cr5_data;
140 u32 cr6_data;
141 u32 cr7_data;
142 u32 cr15_data;
143
144 /* pointer for memory physical address */
145 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
146 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
147 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
148 dma_addr_t first_tx_desc_dma;
149 dma_addr_t first_rx_desc_dma;
150
151 /* descriptor pointer */
152 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
153 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
154 unsigned char *desc_pool_ptr; /* descriptor pool memory */
155 struct tx_desc *first_tx_desc;
156 struct tx_desc *tx_insert_ptr;
157 struct tx_desc *tx_remove_ptr;
158 struct rx_desc *first_rx_desc;
159 struct rx_desc *rx_insert_ptr;
160 struct rx_desc *rx_ready_ptr; /* packet come pointer */
161 unsigned long tx_packet_cnt; /* transmitted packet count */
162 unsigned long rx_avail_cnt; /* available rx descriptor count */
163 unsigned long interval_rx_cnt; /* rx packet count a callback time */
164
165 u16 dbug_cnt;
166 u16 NIC_capability; /* NIC media capability */
167 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
168
169 u8 media_mode; /* user specify media mode */
170 u8 op_mode; /* real work media mode */
171 u8 phy_addr;
172 u8 link_failed; /* Ever link failed */
173 u8 wait_reset; /* Hardware failed, need to reset */
174 struct timer_list timer;
175
4689ced9
PC		 176 /* Driver defined statistic counter */
177 unsigned long tx_fifo_underrun;
178 unsigned long tx_loss_carrier;
179 unsigned long tx_no_carrier;
180 unsigned long tx_late_collision;
181 unsigned long tx_excessive_collision;
182 unsigned long tx_jabber_timeout;
183 unsigned long reset_count;
184 unsigned long reset_cr8;
185 unsigned long reset_fatal;
186 unsigned long reset_TXtimeout;
187
188 /* NIC SROM data */
189 unsigned char srom[128];
f3b197ac 190 u8 init;
4689ced9
PC		 191};
192
193enum uli526x_offsets {
194 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
195 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
196 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
197 DCR15 = 0x78
198};
199
200enum uli526x_CR6_bits {
201 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
202 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
203 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
204};
205
206/* Global variable declaration ----------------------------- */
779c1a85
BP		 207static int printed_version;
208static const char version[] =
1c3319fb 209 "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
4689ced9
PC		 210
211static int uli526x_debug;
212static unsigned char uli526x_media_mode = ULI526X_AUTO;
213static u32 uli526x_cr6_user_set;
214
215/* For module input parameter */
216static int debug;
217static u32 cr6set;
99bb2579 218static int mode = 8;
4689ced9
PC		 219
220/* function declaration ------------------------------------- */
945a7876 221static int uli526x_open(struct net_device *);
ad096463
SH		 222static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
223 struct net_device *);
945a7876 224static int uli526x_stop(struct net_device *);
945a7876 225static void uli526x_set_filter_mode(struct net_device *);
7282d491 226static const struct ethtool_ops netdev_ethtool_ops;
3acf4b5c 227static u16 read_srom_word(struct uli526x_board_info *, int);
7d12e780 228static irqreturn_t uli526x_interrupt(int, void *);
7fa0cba3
AV		 229#ifdef CONFIG_NET_POLL_CONTROLLER
230static void uli526x_poll(struct net_device *dev);
231#endif
3acf4b5c 232static void uli526x_descriptor_init(struct net_device *, void __iomem *);
1ab0d2ec 233static void allocate_rx_buffer(struct net_device *);
3acf4b5c 234static void update_cr6(u32, void __iomem *);
945a7876 235static void send_filter_frame(struct net_device *, int);
3acf4b5c
FR		 236static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
237static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
238static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
239static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
240static void phy_write_1bit(struct uli526x_board_info *db, u32);
241static u16 phy_read_1bit(struct uli526x_board_info *db);
4689ced9
PC		 242static u8 uli526x_sense_speed(struct uli526x_board_info *);
243static void uli526x_process_mode(struct uli526x_board_info *);
244static void uli526x_timer(unsigned long);
945a7876
PC		 245static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
246static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 247static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 248static void uli526x_dynamic_reset(struct net_device *);
4689ced9 249static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 250static void uli526x_init(struct net_device *);
4689ced9
PC		 251static void uli526x_set_phyxcer(struct uli526x_board_info *);
252
3acf4b5c
FR		 253static void srom_clk_write(struct uli526x_board_info *db, u32 data)
254{
255 void __iomem *ioaddr = db->ioaddr;
256
257 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
258 udelay(5);
259 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
260 udelay(5);
261 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
262 udelay(5);
263}
264
945a7876 265/* ULI526X network board routine ---------------------------- */
4689ced9 266
dfefe02b
SH		 267static const struct net_device_ops netdev_ops = {
268 .ndo_open = uli526x_open,
269 .ndo_stop = uli526x_stop,
270 .ndo_start_xmit = uli526x_start_xmit,
afc4b13d 271 .ndo_set_rx_mode = uli526x_set_filter_mode,
dfefe02b
SH		 272 .ndo_set_mac_address = eth_mac_addr,
273 .ndo_validate_addr = eth_validate_addr,
274#ifdef CONFIG_NET_POLL_CONTROLLER
275 .ndo_poll_controller = uli526x_poll,
276#endif
277};
278
4689ced9 279/*
945a7876 280 * Search ULI526X board, allocate space and register it
4689ced9
PC		 281 */
282
779c1a85
BP		 283static int uli526x_init_one(struct pci_dev *pdev,
284 const struct pci_device_id *ent)
4689ced9
PC		 285{
286 struct uli526x_board_info *db; /* board information structure */
287 struct net_device *dev;
3acf4b5c 288 void __iomem *ioaddr;
4689ced9 289 int i, err;
f3b197ac 290
4689ced9
PC		 291 ULI526X_DBUG(0, "uli526x_init_one()", 0);
292
293 if (!printed_version++)
1c3319fb 294 pr_info("%s\n", version);
4689ced9
PC		 295
296 /* Init network device */
297 dev = alloc_etherdev(sizeof(*db));
298 if (dev == NULL)
299 return -ENOMEM;
4689ced9
PC		 300 SET_NETDEV_DEV(dev, &pdev->dev);
301
284901a9 302 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
163ef0b5 303 pr_warn("32-bit PCI DMA not available\n");
4689ced9
PC		 304 err = -ENODEV;
305 goto err_out_free;
306 }
307
308 /* Enable Master/IO access, Disable memory access */
309 err = pci_enable_device(pdev);
310 if (err)
311 goto err_out_free;
312
313 if (!pci_resource_start(pdev, 0)) {
e02fb7aa 314 pr_err("I/O base is zero\n");
4689ced9
PC		 315 err = -ENODEV;
316 goto err_out_disable;
317 }
318
319 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
e02fb7aa 320 pr_err("Allocated I/O size too small\n");
4689ced9
PC		 321 err = -ENODEV;
322 goto err_out_disable;
323 }
324
5e58deb9
FR		 325 err = pci_request_regions(pdev, DRV_NAME);
326 if (err < 0) {
e02fb7aa 327 pr_err("Failed to request PCI regions\n");
4689ced9
PC		 328 goto err_out_disable;
329 }
330
4689ced9
PC		 331 /* Init system & device */
332 db = netdev_priv(dev);
333
334 /* Allocate Tx/Rx descriptor memory */
5e58deb9
FR		 335 err = -ENOMEM;
336
4689ced9 337 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
5e58deb9
FR		 338 if (!db->desc_pool_ptr)
339 goto err_out_release;
340
4689ced9 341 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
5e58deb9
FR		 342 if (!db->buf_pool_ptr)
343 goto err_out_free_tx_desc;
f3b197ac 344
4689ced9
PC		 345 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
346 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
347 db->buf_pool_start = db->buf_pool_ptr;
348 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
349
3acf4b5c
FR		 350 switch (ent->driver_data) {
351 case PCI_ULI5263_ID:
352 db->phy.write = phy_writeby_cr10;
353 db->phy.read = phy_readby_cr10;
354 break;
355 default:
356 db->phy.write = phy_writeby_cr9;
357 db->phy.read = phy_readby_cr9;
358 break;
359 }
360
361 /* IO region. */
362 ioaddr = pci_iomap(pdev, 0, 0);
363 if (!ioaddr)
364 goto err_out_free_tx_buf;
f3b197ac 365
3acf4b5c 366 db->ioaddr = ioaddr;
4689ced9
PC		 367 db->pdev = pdev;
368 db->init = 1;
f3b197ac 369
4689ced9 370 pci_set_drvdata(pdev, dev);
f3b197ac 371
4689ced9 372 /* Register some necessary functions */
dfefe02b 373 dev->netdev_ops = &netdev_ops;
4689ced9 374 dev->ethtool_ops = &netdev_ethtool_ops;
dfefe02b 375
4689ced9
PC		 376 spin_lock_init(&db->lock);
377
f3b197ac 378
4689ced9
PC		 379 /* read 64 word srom data */
380 for (i = 0; i < 64; i++)
3acf4b5c 381 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
4689ced9
PC		 382
383 /* Set Node address */
945a7876 384 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9 385 {
3acf4b5c
FR		 386 uw32(DCR0, 0x10000); //Diagnosis mode
387 uw32(DCR13, 0x1c0); //Reset dianostic pointer port
388 uw32(DCR14, 0); //Clear reset port
389 uw32(DCR14, 0x10); //Reset ID Table pointer
390 uw32(DCR14, 0); //Clear reset port
391 uw32(DCR13, 0); //Clear CR13
392 uw32(DCR13, 0x1b0); //Select ID Table access port
4689ced9
PC		 393 //Read MAC address from CR14
394 for (i = 0; i < 6; i++)
3acf4b5c 395 dev->dev_addr[i] = ur32(DCR14);
4689ced9 396 //Read end
3acf4b5c
FR		 397 uw32(DCR13, 0); //Clear CR13
398 uw32(DCR0, 0); //Clear CR0
4689ced9
PC		 399 udelay(10);
400 }
401 else /*Exist SROM*/
402 {
403 for (i = 0; i < 6; i++)
404 dev->dev_addr[i] = db->srom[20 + i];
405 }
406 err = register_netdev (dev);
407 if (err)
3acf4b5c 408 goto err_out_unmap;
4689ced9 409
163ef0b5
JP		 410 netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
411 ent->driver_data >> 16, pci_name(pdev),
3acf4b5c 412 dev->dev_addr, pdev->irq);
4689ced9
PC		 413
414 pci_set_master(pdev);
415
416 return 0;
417
3acf4b5c
FR		 418err_out_unmap:
419 pci_iounmap(pdev, db->ioaddr);
5e58deb9
FR		 420err_out_free_tx_buf:
421 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
422 db->buf_pool_ptr, db->buf_pool_dma_ptr);
423err_out_free_tx_desc:
424 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
425 db->desc_pool_ptr, db->desc_pool_dma_ptr);
426err_out_release:
4689ced9
PC		 427 pci_release_regions(pdev);
428err_out_disable:
429 pci_disable_device(pdev);
430err_out_free:
4689ced9
PC		 431 free_netdev(dev);
432
433 return err;
434}
435
436
779c1a85 437static void uli526x_remove_one(struct pci_dev *pdev)
4689ced9
PC		 438{
439 struct net_device *dev = pci_get_drvdata(pdev);
440 struct uli526x_board_info *db = netdev_priv(dev);
441
5e58deb9 442 unregister_netdev(dev);
3acf4b5c 443 pci_iounmap(pdev, db->ioaddr);
945a7876
PC		 444 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
445 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
446 db->desc_pool_dma_ptr);
447 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
448 db->buf_pool_ptr, db->buf_pool_dma_ptr);
945a7876 449 pci_release_regions(pdev);
945a7876 450 pci_disable_device(pdev);
5e58deb9 451 free_netdev(dev);
4689ced9
PC		 452}
453
454
455/*
456 * Open the interface.
945a7876 457 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 458 */
459
945a7876 460static int uli526x_open(struct net_device *dev)
4689ced9
PC		 461{
462 int ret;
463 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 464
4689ced9
PC		 465 ULI526X_DBUG(0, "uli526x_open", 0);
466
4689ced9
PC		 467 /* system variable init */
468 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 469 db->tx_packet_cnt = 0;
470 db->rx_avail_cnt = 0;
471 db->link_failed = 1;
472 netif_carrier_off(dev);
473 db->wait_reset = 0;
474
475 db->NIC_capability = 0xf; /* All capability*/
476 db->PHY_reg4 = 0x1e0;
477
478 /* CR6 operation mode decision */
479 db->cr6_data |= ULI526X_TXTH_256;
480 db->cr0_data = CR0_DEFAULT;
f3b197ac 481
945a7876 482 /* Initialize ULI526X board */
4689ced9
PC		 483 uli526x_init(dev);
484
3acf4b5c
FR		 485 ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
486 dev->name, dev);
afd8e399
AV		 487 if (ret)
488 return ret;
489
4689ced9
PC		 490 /* Active System Interface */
491 netif_wake_queue(dev);
492
493 /* set and active a timer process */
494 init_timer(&db->timer);
495 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
496 db->timer.data = (unsigned long)dev;
c061b18d 497 db->timer.function = uli526x_timer;
4689ced9
PC		 498 add_timer(&db->timer);
499
500 return 0;
501}
502
503
945a7876 504/* Initialize ULI526X board
4689ced9 505 * Reset ULI526X board
945a7876 506 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 507 * Send the set-up frame
508 * Enable Tx/Rx machine
509 */
510
945a7876 511static void uli526x_init(struct net_device *dev)
4689ced9
PC		 512{
513 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c
FR		 514 struct uli_phy_ops *phy = &db->phy;
515 void __iomem *ioaddr = db->ioaddr;
4689ced9 516 u8 phy_tmp;
7a7d23da 517 u8 timeout;
4689ced9
PC		 518 u16 phy_reg_reset;
519
7a7d23da 520
4689ced9
PC		 521 ULI526X_DBUG(0, "uli526x_init()", 0);
522
523 /* Reset M526x MAC controller */
3acf4b5c 524 uw32(DCR0, ULI526X_RESET); /* RESET MAC */
4689ced9 525 udelay(100);
3acf4b5c 526 uw32(DCR0, db->cr0_data);
4689ced9
PC		 527 udelay(5);
528
529 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
530 db->phy_addr = 1;
3acf4b5c
FR		 531 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
532 u16 phy_value;
533
534 phy_value = phy->read(db, phy_tmp, 3); //peer add
535 if (phy_value != 0xffff && phy_value != 0) {
4689ced9
PC		 536 db->phy_addr = phy_tmp;
537 break;
538 }
539 }
3acf4b5c
FR		 540
541 if (phy_tmp == 32)
163ef0b5 542 pr_warn("Can not find the phy address!!!\n");
4689ced9
PC		 543 /* Parser SROM and media mode */
544 db->media_mode = uli526x_media_mode;
545
7a7d23da 546 /* phyxcer capability setting */
3acf4b5c 547 phy_reg_reset = phy->read(db, db->phy_addr, 0);
4689ced9 548 phy_reg_reset = (phy_reg_reset | 0x8000);
3acf4b5c 549 phy->write(db, db->phy_addr, 0, phy_reg_reset);
7a7d23da
GG		 550
551 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
552 * functions") or phy data sheet for details on phy reset
553 */
4689ced9 554 udelay(500);
7a7d23da 555 timeout = 10;
3acf4b5c
FR		 556 while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
557 udelay(100);
4689ced9
PC		 558
559 /* Process Phyxcer Media Mode */
560 uli526x_set_phyxcer(db);
561
562 /* Media Mode Process */
563 if ( !(db->media_mode & ULI526X_AUTO) )
3acf4b5c 564 db->op_mode = db->media_mode; /* Force Mode */
4689ced9 565
dbedd44e 566 /* Initialize Transmit/Receive descriptor and CR3/4 */
1ab0d2ec 567 uli526x_descriptor_init(dev, ioaddr);
4689ced9
PC		 568
569 /* Init CR6 to program M526X operation */
570 update_cr6(db->cr6_data, ioaddr);
571
572 /* Send setup frame */
4cd24eaf 573 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
4689ced9
PC		 574
575 /* Init CR7, interrupt active bit */
576 db->cr7_data = CR7_DEFAULT;
3acf4b5c 577 uw32(DCR7, db->cr7_data);
4689ced9
PC		 578
579 /* Init CR15, Tx jabber and Rx watchdog timer */
3acf4b5c 580 uw32(DCR15, db->cr15_data);
4689ced9
PC		 581
582 /* Enable ULI526X Tx/Rx function */
583 db->cr6_data |= CR6_RXSC | CR6_TXSC;
584 update_cr6(db->cr6_data, ioaddr);
585}
586
587
588/*
589 * Hardware start transmission.
590 * Send a packet to media from the upper layer.
591 */
592
ad096463
SH		 593static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
594 struct net_device *dev)
4689ced9
PC		 595{
596 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 597 void __iomem *ioaddr = db->ioaddr;
4689ced9
PC		 598 struct tx_desc *txptr;
599 unsigned long flags;
600
601 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
602
603 /* Resource flag check */
604 netif_stop_queue(dev);
605
606 /* Too large packet check */
607 if (skb->len > MAX_PACKET_SIZE) {
163ef0b5 608 netdev_err(dev, "big packet = %d\n", (u16)skb->len);
290a79db 609 dev_kfree_skb_any(skb);
6ed10654 610 return NETDEV_TX_OK;
4689ced9
PC		 611 }
612
613 spin_lock_irqsave(&db->lock, flags);
614
615 /* No Tx resource check, it never happen nromally */
616 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
617 spin_unlock_irqrestore(&db->lock, flags);
163ef0b5 618 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
5b548140 619 return NETDEV_TX_BUSY;
4689ced9
PC		 620 }
621
622 /* Disable NIC interrupt */
3acf4b5c 623 uw32(DCR7, 0);
4689ced9
PC		 624
625 /* transmit this packet */
626 txptr = db->tx_insert_ptr;
d626f62b 627 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 628 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
629
630 /* Point to next transmit free descriptor */
631 db->tx_insert_ptr = txptr->next_tx_desc;
632
633 /* Transmit Packet Process */
3acf4b5c 634 if (db->tx_packet_cnt < TX_DESC_CNT) {
4689ced9
PC		 635 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
636 db->tx_packet_cnt++; /* Ready to send */
3acf4b5c 637 uw32(DCR1, 0x1); /* Issue Tx polling */
860e9538 638 netif_trans_update(dev); /* saved time stamp */
4689ced9
PC		 639 }
640
641 /* Tx resource check */
642 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
643 netif_wake_queue(dev);
644
645 /* Restore CR7 to enable interrupt */
646 spin_unlock_irqrestore(&db->lock, flags);
3acf4b5c 647 uw32(DCR7, db->cr7_data);
f3b197ac 648
4689ced9 649 /* free this SKB */
290a79db 650 dev_consume_skb_any(skb);
4689ced9 651
6ed10654 652 return NETDEV_TX_OK;
4689ced9
PC		 653}
654
655
656/*
657 * Stop the interface.
658 * The interface is stopped when it is brought.
659 */
660
945a7876 661static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 662{
663 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 664 void __iomem *ioaddr = db->ioaddr;
4689ced9
PC		 665
666 /* disable system */
667 netif_stop_queue(dev);
668
669 /* deleted timer */
670 del_timer_sync(&db->timer);
671
672 /* Reset & stop ULI526X board */
3acf4b5c 673 uw32(DCR0, ULI526X_RESET);
4689ced9 674 udelay(5);
3acf4b5c 675 db->phy.write(db, db->phy_addr, 0, 0x8000);
4689ced9
PC		 676
677 /* free interrupt */
3acf4b5c 678 free_irq(db->pdev->irq, dev);
4689ced9
PC		 679
680 /* free allocated rx buffer */
681 uli526x_free_rxbuffer(db);
682
4689ced9
PC		 683 return 0;
684}
685
686
687/*
688 * M5261/M5263 insterrupt handler
689 * receive the packet to upper layer, free the transmitted packet
690 */
691
7d12e780 692static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 693{
945a7876 694 struct net_device *dev = dev_id;
4689ced9 695 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 696 void __iomem *ioaddr = db->ioaddr;
4689ced9
PC		 697 unsigned long flags;
698
4689ced9 699 spin_lock_irqsave(&db->lock, flags);
3acf4b5c 700 uw32(DCR7, 0);
4689ced9
PC		 701
702 /* Got ULI526X status */
3acf4b5c
FR		 703 db->cr5_data = ur32(DCR5);
704 uw32(DCR5, db->cr5_data);
4689ced9 705 if ( !(db->cr5_data & 0x180c1) ) {
7fa0cba3 706 /* Restore CR7 to enable interrupt mask */
3acf4b5c 707 uw32(DCR7, db->cr7_data);
7fa0cba3 708 spin_unlock_irqrestore(&db->lock, flags);
4689ced9
PC		 709 return IRQ_HANDLED;
710 }
711
4689ced9
PC		 712 /* Check system status */
713 if (db->cr5_data & 0x2000) {
714 /* system bus error happen */
715 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
716 db->reset_fatal++;
717 db->wait_reset = 1; /* Need to RESET */
718 spin_unlock_irqrestore(&db->lock, flags);
719 return IRQ_HANDLED;
720 }
721
722 /* Received the coming packet */
723 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
724 uli526x_rx_packet(dev, db);
725
726 /* reallocate rx descriptor buffer */
727 if (db->rx_avail_cnt<RX_DESC_CNT)
1ab0d2ec 728 allocate_rx_buffer(dev);
4689ced9
PC		 729
730 /* Free the transmitted descriptor */
731 if ( db->cr5_data & 0x01)
732 uli526x_free_tx_pkt(dev, db);
733
734 /* Restore CR7 to enable interrupt mask */
3acf4b5c 735 uw32(DCR7, db->cr7_data);
4689ced9
PC		 736
737 spin_unlock_irqrestore(&db->lock, flags);
738 return IRQ_HANDLED;
739}
740
7fa0cba3
AV		 741#ifdef CONFIG_NET_POLL_CONTROLLER
742static void uli526x_poll(struct net_device *dev)
743{
3acf4b5c
FR		 744 struct uli526x_board_info *db = netdev_priv(dev);
745
7fa0cba3 746 /* ISR grabs the irqsave lock, so this should be safe */
3acf4b5c 747 uli526x_interrupt(db->pdev->irq, dev);
7fa0cba3
AV		 748}
749#endif
4689ced9
PC		 750
751/*
752 * Free TX resource after TX complete
753 */
754
dfefe02b
SH		 755static void uli526x_free_tx_pkt(struct net_device *dev,
756 struct uli526x_board_info * db)
4689ced9
PC		 757{
758 struct tx_desc *txptr;
4689ced9
PC		 759 u32 tdes0;
760
761 txptr = db->tx_remove_ptr;
762 while(db->tx_packet_cnt) {
763 tdes0 = le32_to_cpu(txptr->tdes0);
4689ced9
PC		 764 if (tdes0 & 0x80000000)
765 break;
766
767 /* A packet sent completed */
768 db->tx_packet_cnt--;
dfefe02b 769 dev->stats.tx_packets++;
4689ced9
PC		 770
771 /* Transmit statistic counter */
772 if ( tdes0 != 0x7fffffff ) {
dfefe02b
SH		 773 dev->stats.collisions += (tdes0 >> 3) & 0xf;
774 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
4689ced9 775 if (tdes0 & TDES0_ERR_MASK) {
dfefe02b 776 dev->stats.tx_errors++;
4689ced9
PC		 777 if (tdes0 & 0x0002) { /* UnderRun */
778 db->tx_fifo_underrun++;
779 if ( !(db->cr6_data & CR6_SFT) ) {
780 db->cr6_data = db->cr6_data | CR6_SFT;
781 update_cr6(db->cr6_data, db->ioaddr);
782 }
783 }
784 if (tdes0 & 0x0100)
785 db->tx_excessive_collision++;
786 if (tdes0 & 0x0200)
787 db->tx_late_collision++;
788 if (tdes0 & 0x0400)
789 db->tx_no_carrier++;
790 if (tdes0 & 0x0800)
791 db->tx_loss_carrier++;
792 if (tdes0 & 0x4000)
793 db->tx_jabber_timeout++;
794 }
795 }
796
797 txptr = txptr->next_tx_desc;
798 }/* End of while */
799
800 /* Update TX remove pointer to next */
801 db->tx_remove_ptr = txptr;
802
803 /* Resource available check */
804 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
805 netif_wake_queue(dev); /* Active upper layer, send again */
806}
807
808
809/*
810 * Receive the come packet and pass to upper layer
811 */
812
945a7876 813static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 814{
815 struct rx_desc *rxptr;
816 struct sk_buff *skb;
817 int rxlen;
818 u32 rdes0;
f3b197ac 819
4689ced9
PC		 820 rxptr = db->rx_ready_ptr;
821
822 while(db->rx_avail_cnt) {
823 rdes0 = le32_to_cpu(rxptr->rdes0);
824 if (rdes0 & 0x80000000) /* packet owner check */
825 {
826 break;
827 }
828
829 db->rx_avail_cnt--;
830 db->interval_rx_cnt++;
831
832 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
833 if ( (rdes0 & 0x300) != 0x300) {
834 /* A packet without First/Last flag */
835 /* reuse this SKB */
836 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
837 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
838 } else {
839 /* A packet with First/Last flag */
840 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
841
842 /* error summary bit check */
843 if (rdes0 & 0x8000) {
844 /* This is a error packet */
dfefe02b 845 dev->stats.rx_errors++;
4689ced9 846 if (rdes0 & 1)
dfefe02b 847 dev->stats.rx_fifo_errors++;
4689ced9 848 if (rdes0 & 2)
dfefe02b 849 dev->stats.rx_crc_errors++;
4689ced9 850 if (rdes0 & 0x80)
dfefe02b 851 dev->stats.rx_length_errors++;
4689ced9
PC		 852 }
853
854 if ( !(rdes0 & 0x8000) ||
855 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
ac90a149
KM		 856 struct sk_buff *new_skb = NULL;
857
4689ced9 858 skb = rxptr->rx_skb_ptr;
f3b197ac 859
4689ced9
PC		 860 /* Good packet, send to upper layer */
861 /* Shorst packet used new SKB */
ac90a149 862 if ((rxlen < RX_COPY_SIZE) &&
1ab0d2ec 863 (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
ac90a149 864 skb = new_skb;
4689ced9 865 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 866 skb_reserve(skb, 2); /* 16byte align */
59ae1d12
JB		 867 skb_put_data(skb,
868 skb_tail_pointer(rxptr->rx_skb_ptr),
869 rxlen);
4689ced9 870 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 871 } else
4689ced9 872 skb_put(skb, rxlen);
4c13eb66 873
4689ced9
PC		 874 skb->protocol = eth_type_trans(skb, dev);
875 netif_rx(skb);
dfefe02b
SH		 876 dev->stats.rx_packets++;
877 dev->stats.rx_bytes += rxlen;
f3b197ac 878
4689ced9
PC		 879 } else {
880 /* Reuse SKB buffer when the packet is error */
881 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
882 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
883 }
884 }
885
886 rxptr = rxptr->next_rx_desc;
887 }
888
889 db->rx_ready_ptr = rxptr;
890}
891
892
4689ced9
PC		 893/*
894 * Set ULI526X multicast address
895 */
896
945a7876 897static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9 898{
8f15ea42 899 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 900 unsigned long flags;
901
902 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
903 spin_lock_irqsave(&db->lock, flags);
904
905 if (dev->flags & IFF_PROMISC) {
906 ULI526X_DBUG(0, "Enable PROM Mode", 0);
907 db->cr6_data |= CR6_PM | CR6_PBF;
908 update_cr6(db->cr6_data, db->ioaddr);
909 spin_unlock_irqrestore(&db->lock, flags);
910 return;
911 }
912
4cd24eaf
JP		 913 if (dev->flags & IFF_ALLMULTI ||
914 netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
915 ULI526X_DBUG(0, "Pass all multicast address",
916 netdev_mc_count(dev));
4689ced9
PC		 917 db->cr6_data &= ~(CR6_PM | CR6_PBF);
918 db->cr6_data |= CR6_PAM;
919 spin_unlock_irqrestore(&db->lock, flags);
920 return;
921 }
922
4cd24eaf
JP		 923 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
924 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
4689ced9
PC		 925 spin_unlock_irqrestore(&db->lock, flags);
926}
927
928static void
6711a87a
PR		 929ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
930 struct ethtool_link_ksettings *cmd)
4689ced9 931{
6711a87a
PR		 932 u32 supported, advertising;
933
934 supported = (SUPPORTED_10baseT_Half |
945a7876
PC		 935 SUPPORTED_10baseT_Full |
936 SUPPORTED_100baseT_Half |
937 SUPPORTED_100baseT_Full |
938 SUPPORTED_Autoneg |
939 SUPPORTED_MII);
f3b197ac 940
6711a87a 941 advertising = (ADVERTISED_10baseT_Half |
945a7876
PC		 942 ADVERTISED_10baseT_Full |
943 ADVERTISED_100baseT_Half |
944 ADVERTISED_100baseT_Full |
945 ADVERTISED_Autoneg |
946 ADVERTISED_MII);
4689ced9 947
6711a87a
PR		 948 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
949 supported);
950 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
951 advertising);
4689ced9 952
6711a87a
PR		 953 cmd->base.port = PORT_MII;
954 cmd->base.phy_address = db->phy_addr;
f3b197ac 955
6711a87a
PR		 956 cmd->base.speed = SPEED_10;
957 cmd->base.duplex = DUPLEX_HALF;
f3b197ac 958
4689ced9
PC		 959 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
960 {
6711a87a 961 cmd->base.speed = SPEED_100;
4689ced9
PC		 962 }
963 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
964 {
6711a87a 965 cmd->base.duplex = DUPLEX_FULL;
4689ced9
PC		 966 }
967 if(db->link_failed)
968 {
6711a87a
PR		 969 cmd->base.speed = SPEED_UNKNOWN;
970 cmd->base.duplex = DUPLEX_UNKNOWN;
4689ced9 971 }
f3b197ac 972
4689ced9 973 if (db->media_mode & ULI526X_AUTO)
f3b197ac 974 {
6711a87a 975 cmd->base.autoneg = AUTONEG_ENABLE;
4689ced9 976 }
4689ced9
PC		 977}
978
979static void netdev_get_drvinfo(struct net_device *dev,
980 struct ethtool_drvinfo *info)
981{
982 struct uli526x_board_info *np = netdev_priv(dev);
983
68aad78c
RJ		 984 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
985 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3acf4b5c 986 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
4689ced9
PC		 987}
988
6711a87a
PR		 989static int netdev_get_link_ksettings(struct net_device *dev,
990 struct ethtool_link_ksettings *cmd)
991{
4689ced9 992 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 993
6711a87a 994 ULi_ethtool_get_link_ksettings(np, cmd);
f3b197ac 995
4689ced9
PC		 996 return 0;
997}
998
999static u32 netdev_get_link(struct net_device *dev) {
1000 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 1001
4689ced9
PC		 1002 if(np->link_failed)
1003 return 0;
1004 else
1005 return 1;
1006}
1007
1008static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1009{
1010 wol->supported = WAKE_PHY | WAKE_MAGIC;
1011 wol->wolopts = 0;
1012}
1013
7282d491 1014static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9 1015 .get_drvinfo = netdev_get_drvinfo,
4689ced9
PC		 1016 .get_link = netdev_get_link,
1017 .get_wol = uli526x_get_wol,
6711a87a 1018 .get_link_ksettings = netdev_get_link_ksettings,
4689ced9
PC		 1019};
1020
1021/*
1022 * A periodic timer routine
1023 * Dynamic media sense, allocate Rx buffer...
1024 */
1025
1026static void uli526x_timer(unsigned long data)
1027{
945a7876 1028 struct net_device *dev = (struct net_device *) data;
4689ced9 1029 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c
FR		 1030 struct uli_phy_ops *phy = &db->phy;
1031 void __iomem *ioaddr = db->ioaddr;
4689ced9 1032 unsigned long flags;
3acf4b5c
FR		 1033 u8 tmp_cr12 = 0;
1034 u32 tmp_cr8;
f3b197ac 1035
4689ced9
PC		 1036 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1037 spin_lock_irqsave(&db->lock, flags);
1038
f3b197ac 1039
4689ced9 1040 /* Dynamic reset ULI526X : system error or transmit time-out */
3acf4b5c 1041 tmp_cr8 = ur32(DCR8);
4689ced9
PC		 1042 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1043 db->reset_cr8++;
1044 db->wait_reset = 1;
1045 }
1046 db->interval_rx_cnt = 0;
1047
1048 /* TX polling kick monitor */
1049 if ( db->tx_packet_cnt &&
1ae5dc34 1050 time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
3acf4b5c 1051 uw32(DCR1, 0x1); // Tx polling again
4689ced9 1052
f3b197ac 1053 // TX Timeout
1ae5dc34 1054 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
4689ced9
PC		 1055 db->reset_TXtimeout++;
1056 db->wait_reset = 1;
1c3319fb 1057 netdev_err(dev, " Tx timeout - resetting\n");
4689ced9
PC		 1058 }
1059 }
1060
1061 if (db->wait_reset) {
1062 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1063 db->reset_count++;
1064 uli526x_dynamic_reset(dev);
1065 db->timer.expires = ULI526X_TIMER_WUT;
1066 add_timer(&db->timer);
1067 spin_unlock_irqrestore(&db->lock, flags);
1068 return;
1069 }
1070
1071 /* Link status check, Dynamic media type change */
3acf4b5c 1072 if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
4689ced9
PC		 1073 tmp_cr12 = 3;
1074
1075 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1076 /* Link Failed */
1077 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1078 netif_carrier_off(dev);
163ef0b5 1079 netdev_info(dev, "NIC Link is Down\n");
4689ced9
PC		 1080 db->link_failed = 1;
1081
1082 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1083 /* AUTO don't need */
1084 if ( !(db->media_mode & 0x8) )
3acf4b5c 1085 phy->write(db, db->phy_addr, 0, 0x1000);
4689ced9
PC		 1086
1087 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1088 if (db->media_mode & ULI526X_AUTO) {
1089 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1090 update_cr6(db->cr6_data, db->ioaddr);
1091 }
1092 } else
1093 if ((tmp_cr12 & 0x3) && db->link_failed) {
1094 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1095 db->link_failed = 0;
1096
1097 /* Auto Sense Speed */
1098 if ( (db->media_mode & ULI526X_AUTO) &&
1099 uli526x_sense_speed(db) )
1100 db->link_failed = 1;
1101 uli526x_process_mode(db);
f3b197ac 1102
4689ced9
PC		 1103 if(db->link_failed==0)
1104 {
163ef0b5
JP		 1105 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1106 (db->op_mode == ULI526X_100MHF ||
1107 db->op_mode == ULI526X_100MFD)
1108 ? 100 : 10,
1109 (db->op_mode == ULI526X_10MFD ||
1110 db->op_mode == ULI526X_100MFD)
1111 ? "Full" : "Half");
4689ced9
PC		 1112 netif_carrier_on(dev);
1113 }
1114 /* SHOW_MEDIA_TYPE(db->op_mode); */
1115 }
1116 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1117 {
1118 if(db->init==1)
1119 {
163ef0b5 1120 netdev_info(dev, "NIC Link is Down\n");
4689ced9
PC		 1121 netif_carrier_off(dev);
1122 }
1123 }
e1395a32 1124 db->init = 0;
4689ced9
PC		 1125
1126 /* Timer active again */
1127 db->timer.expires = ULI526X_TIMER_WUT;
1128 add_timer(&db->timer);
1129 spin_unlock_irqrestore(&db->lock, flags);
1130}
1131
1132
1133/*
4689ced9
PC		 1134 * Stop ULI526X board
1135 * Free Tx/Rx allocated memory
b6aec32a 1136 * Init system variable
4689ced9
PC		 1137 */
1138
b6aec32a 1139static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1140{
1141 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 1142 void __iomem *ioaddr = db->ioaddr;
4689ced9 1143
4689ced9
PC		 1144 /* Sopt MAC controller */
1145 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
3acf4b5c
FR		 1146 update_cr6(db->cr6_data, ioaddr);
1147 uw32(DCR7, 0); /* Disable Interrupt */
1148 uw32(DCR5, ur32(DCR5));
4689ced9
PC		 1149
1150 /* Disable upper layer interface */
1151 netif_stop_queue(dev);
1152
1153 /* Free Rx Allocate buffer */
1154 uli526x_free_rxbuffer(db);
1155
1156 /* system variable init */
1157 db->tx_packet_cnt = 0;
1158 db->rx_avail_cnt = 0;
1159 db->link_failed = 1;
1160 db->init=1;
1161 db->wait_reset = 0;
b6aec32a
RW		 1162}
1163
1164
1165/*
1166 * Dynamic reset the ULI526X board
1167 * Stop ULI526X board
1168 * Free Tx/Rx allocated memory
1169 * Reset ULI526X board
1170 * Re-initialize ULI526X board
1171 */
1172
1173static void uli526x_dynamic_reset(struct net_device *dev)
1174{
1175 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1176
1177 uli526x_reset_prepare(dev);
4689ced9 1178
945a7876 1179 /* Re-initialize ULI526X board */
4689ced9
PC		 1180 uli526x_init(dev);
1181
1182 /* Restart upper layer interface */
1183 netif_wake_queue(dev);
1184}
1185
1186
b6aec32a
RW		 1187#ifdef CONFIG_PM
1188
1189/*
1190 * Suspend the interface.
1191 */
1192
1193static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1194{
1195 struct net_device *dev = pci_get_drvdata(pdev);
1196 pci_power_t power_state;
1197 int err;
1198
1199 ULI526X_DBUG(0, "uli526x_suspend", 0);
1200
b6aec32a
RW		 1201 pci_save_state(pdev);
1202
1203 if (!netif_running(dev))
1204 return 0;
1205
1206 netif_device_detach(dev);
1207 uli526x_reset_prepare(dev);
1208
1209 power_state = pci_choose_state(pdev, state);
1210 pci_enable_wake(pdev, power_state, 0);
1211 err = pci_set_power_state(pdev, power_state);
1212 if (err) {
1213 netif_device_attach(dev);
1214 /* Re-initialize ULI526X board */
1215 uli526x_init(dev);
1216 /* Restart upper layer interface */
1217 netif_wake_queue(dev);
1218 }
1219
1220 return err;
1221}
1222
1223/*
1224 * Resume the interface.
1225 */
1226
1227static int uli526x_resume(struct pci_dev *pdev)
1228{
1229 struct net_device *dev = pci_get_drvdata(pdev);
1230 int err;
1231
1232 ULI526X_DBUG(0, "uli526x_resume", 0);
1233
b6aec32a
RW		 1234 pci_restore_state(pdev);
1235
1236 if (!netif_running(dev))
1237 return 0;
1238
1239 err = pci_set_power_state(pdev, PCI_D0);
1240 if (err) {
163ef0b5 1241 netdev_warn(dev, "Could not put device into D0\n");
b6aec32a
RW		 1242 return err;
1243 }
1244
1245 netif_device_attach(dev);
1246 /* Re-initialize ULI526X board */
1247 uli526x_init(dev);
1248 /* Restart upper layer interface */
1249 netif_wake_queue(dev);
1250
1251 return 0;
1252}
1253
1254#else /* !CONFIG_PM */
1255
1256#define uli526x_suspend NULL
1257#define uli526x_resume NULL
1258
1259#endif /* !CONFIG_PM */
1260
1261
4689ced9
PC		 1262/*
1263 * free all allocated rx buffer
1264 */
1265
1266static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1267{
1268 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1269
1270 /* free allocated rx buffer */
1271 while (db->rx_avail_cnt) {
1272 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1273 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1274 db->rx_avail_cnt--;
1275 }
1276}
1277
1278
1279/*
1280 * Reuse the SK buffer
1281 */
1282
1283static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1284{
1285 struct rx_desc *rxptr = db->rx_insert_ptr;
1286
1287 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1288 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1289 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1290 skb_tail_pointer(skb),
1291 RX_ALLOC_SIZE,
1292 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1293 wmb();
1294 rxptr->rdes0 = cpu_to_le32(0x80000000);
1295 db->rx_avail_cnt++;
1296 db->rx_insert_ptr = rxptr->next_rx_desc;
1297 } else
1298 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1299}
1300
1301
1302/*
1303 * Initialize transmit/Receive descriptor
1304 * Using Chain structure, and allocate Tx/Rx buffer
1305 */
1306
3acf4b5c 1307static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
4689ced9 1308{
1ab0d2ec 1309 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 1310 struct tx_desc *tmp_tx;
1311 struct rx_desc *tmp_rx;
1312 unsigned char *tmp_buf;
1313 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1314 dma_addr_t tmp_buf_dma;
1315 int i;
1316
1317 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1318
1319 /* tx descriptor start pointer */
1320 db->tx_insert_ptr = db->first_tx_desc;
1321 db->tx_remove_ptr = db->first_tx_desc;
3acf4b5c 1322 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
4689ced9
PC		 1323
1324 /* rx descriptor start pointer */
1325 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1326 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1327 db->rx_insert_ptr = db->first_rx_desc;
1328 db->rx_ready_ptr = db->first_rx_desc;
3acf4b5c 1329 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
4689ced9
PC		 1330
1331 /* Init Transmit chain */
1332 tmp_buf = db->buf_pool_start;
1333 tmp_buf_dma = db->buf_pool_dma_start;
1334 tmp_tx_dma = db->first_tx_desc_dma;
1335 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1336 tmp_tx->tx_buf_ptr = tmp_buf;
1337 tmp_tx->tdes0 = cpu_to_le32(0);
1338 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1339 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1340 tmp_tx_dma += sizeof(struct tx_desc);
1341 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1342 tmp_tx->next_tx_desc = tmp_tx + 1;
1343 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1344 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1345 }
1346 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1347 tmp_tx->next_tx_desc = db->first_tx_desc;
1348
1349 /* Init Receive descriptor chain */
1350 tmp_rx_dma=db->first_rx_desc_dma;
1351 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1352 tmp_rx->rdes0 = cpu_to_le32(0);
1353 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1354 tmp_rx_dma += sizeof(struct rx_desc);
1355 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1356 tmp_rx->next_rx_desc = tmp_rx + 1;
1357 }
1358 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1359 tmp_rx->next_rx_desc = db->first_rx_desc;
1360
1361 /* pre-allocate Rx buffer */
1ab0d2ec 1362 allocate_rx_buffer(dev);
4689ced9
PC		 1363}
1364
1365
1366/*
1367 * Update CR6 value
945a7876 1368 * Firstly stop ULI526X, then written value and start
4689ced9 1369 */
3acf4b5c 1370static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
4689ced9 1371{
3acf4b5c 1372 uw32(DCR6, cr6_data);
4689ced9
PC		 1373 udelay(5);
1374}
1375
1376
1377/*
1378 * Send a setup frame for M5261/M5263
945a7876 1379 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1380 */
1381
e284e5c6
AV		 1382#ifdef __BIG_ENDIAN
1383#define FLT_SHIFT 16
1384#else
1385#define FLT_SHIFT 0
1386#endif
1387
945a7876 1388static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1389{
1390 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 1391 void __iomem *ioaddr = db->ioaddr;
22bedad3 1392 struct netdev_hw_addr *ha;
4689ced9
PC		 1393 struct tx_desc *txptr;
1394 u16 * addrptr;
1395 u32 * suptr;
1396 int i;
1397
1398 ULI526X_DBUG(0, "send_filter_frame()", 0);
1399
1400 txptr = db->tx_insert_ptr;
1401 suptr = (u32 *) txptr->tx_buf_ptr;
1402
1403 /* Node address */
1404 addrptr = (u16 *) dev->dev_addr;
e284e5c6
AV		 1405 *suptr++ = addrptr[0] << FLT_SHIFT;
1406 *suptr++ = addrptr[1] << FLT_SHIFT;
1407 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1408
1409 /* broadcast address */
e284e5c6
AV		 1410 *suptr++ = 0xffff << FLT_SHIFT;
1411 *suptr++ = 0xffff << FLT_SHIFT;
1412 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1413
1414 /* fit the multicast address */
22bedad3
JP		 1415 netdev_for_each_mc_addr(ha, dev) {
1416 addrptr = (u16 *) ha->addr;
e284e5c6
AV		 1417 *suptr++ = addrptr[0] << FLT_SHIFT;
1418 *suptr++ = addrptr[1] << FLT_SHIFT;
1419 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1420 }
1421
4302b67e 1422 for (i = netdev_mc_count(dev); i < 14; i++) {
e284e5c6
AV		 1423 *suptr++ = 0xffff << FLT_SHIFT;
1424 *suptr++ = 0xffff << FLT_SHIFT;
1425 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1426 }
1427
1428 /* prepare the setup frame */
1429 db->tx_insert_ptr = txptr->next_tx_desc;
1430 txptr->tdes1 = cpu_to_le32(0x890000c0);
1431
1432 /* Resource Check and Send the setup packet */
1433 if (db->tx_packet_cnt < TX_DESC_CNT) {
1434 /* Resource Empty */
1435 db->tx_packet_cnt++;
1436 txptr->tdes0 = cpu_to_le32(0x80000000);
3acf4b5c
FR		 1437 update_cr6(db->cr6_data | 0x2000, ioaddr);
1438 uw32(DCR1, 0x1); /* Issue Tx polling */
1439 update_cr6(db->cr6_data, ioaddr);
860e9538 1440 netif_trans_update(dev);
4689ced9 1441 } else
163ef0b5 1442 netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
4689ced9
PC		 1443}
1444
1445
1446/*
1447 * Allocate rx buffer,
1448 * As possible as allocate maxiumn Rx buffer
1449 */
1450
1ab0d2ec 1451static void allocate_rx_buffer(struct net_device *dev)
4689ced9 1452{
1ab0d2ec 1453 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 1454 struct rx_desc *rxptr;
1455 struct sk_buff *skb;
1456
1457 rxptr = db->rx_insert_ptr;
1458
1459 while(db->rx_avail_cnt < RX_DESC_CNT) {
1ab0d2ec
PD		 1460 skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1461 if (skb == NULL)
4689ced9
PC		 1462 break;
1463 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1464 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1465 skb_tail_pointer(skb),
1466 RX_ALLOC_SIZE,
1467 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1468 wmb();
1469 rxptr->rdes0 = cpu_to_le32(0x80000000);
1470 rxptr = rxptr->next_rx_desc;
1471 db->rx_avail_cnt++;
1472 }
1473
1474 db->rx_insert_ptr = rxptr;
1475}
1476
1477
1478/*
1479 * Read one word data from the serial ROM
1480 */
1481
3acf4b5c 1482static u16 read_srom_word(struct uli526x_board_info *db, int offset)
4689ced9 1483{
3acf4b5c 1484 void __iomem *ioaddr = db->ioaddr;
4689ced9 1485 u16 srom_data = 0;
3acf4b5c 1486 int i;
4689ced9 1487
3acf4b5c
FR		 1488 uw32(DCR9, CR9_SROM_READ);
1489 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
4689ced9
PC		 1490
1491 /* Send the Read Command 110b */
3acf4b5c
FR		 1492 srom_clk_write(db, SROM_DATA_1);
1493 srom_clk_write(db, SROM_DATA_1);
1494 srom_clk_write(db, SROM_DATA_0);
4689ced9
PC		 1495
1496 /* Send the offset */
1497 for (i = 5; i >= 0; i--) {
1498 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
3acf4b5c 1499 srom_clk_write(db, srom_data);
4689ced9
PC		 1500 }
1501
3acf4b5c 1502 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
4689ced9
PC		 1503
1504 for (i = 16; i > 0; i--) {
3acf4b5c 1505 uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
4689ced9 1506 udelay(5);
3acf4b5c
FR		 1507 srom_data = (srom_data << 1) |
1508 ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1509 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
4689ced9
PC		 1510 udelay(5);
1511 }
1512
3acf4b5c 1513 uw32(DCR9, CR9_SROM_READ);
4689ced9
PC		 1514 return srom_data;
1515}
1516
1517
1518/*
1519 * Auto sense the media mode
1520 */
1521
1522static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1523{
3acf4b5c 1524 struct uli_phy_ops *phy = &db->phy;
4689ced9
PC		 1525 u8 ErrFlag = 0;
1526 u16 phy_mode;
1527
3acf4b5c
FR		 1528 phy_mode = phy->read(db, db->phy_addr, 1);
1529 phy_mode = phy->read(db, db->phy_addr, 1);
4689ced9
PC		 1530
1531 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1532
3acf4b5c 1533 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
4689ced9
PC		 1534 if(phy_mode&0x8000)
1535 phy_mode = 0x8000;
1536 else if(phy_mode&0x4000)
1537 phy_mode = 0x4000;
1538 else if(phy_mode&0x2000)
1539 phy_mode = 0x2000;
1540 else
1541 phy_mode = 0x1000;
f3b197ac 1542
4689ced9
PC		 1543 switch (phy_mode) {
1544 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1545 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1546 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1547 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1548 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1549 }
1550 } else {
1551 db->op_mode = ULI526X_10MHF;
1552 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1553 ErrFlag = 1;
1554 }
1555
1556 return ErrFlag;
1557}
1558
1559
1560/*
1561 * Set 10/100 phyxcer capability
1562 * AUTO mode : phyxcer register4 is NIC capability
1563 * Force mode: phyxcer register4 is the force media
1564 */
1565
1566static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1567{
3acf4b5c 1568 struct uli_phy_ops *phy = &db->phy;
4689ced9 1569 u16 phy_reg;
f3b197ac 1570
4689ced9 1571 /* Phyxcer capability setting */
3acf4b5c 1572 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
4689ced9
PC		 1573
1574 if (db->media_mode & ULI526X_AUTO) {
1575 /* AUTO Mode */
1576 phy_reg |= db->PHY_reg4;
1577 } else {
1578 /* Force Mode */
1579 switch(db->media_mode) {
1580 case ULI526X_10MHF: phy_reg |= 0x20; break;
1581 case ULI526X_10MFD: phy_reg |= 0x40; break;
1582 case ULI526X_100MHF: phy_reg |= 0x80; break;
1583 case ULI526X_100MFD: phy_reg |= 0x100; break;
1584 }
f3b197ac 1585
4689ced9
PC		 1586 }
1587
1588 /* Write new capability to Phyxcer Reg4 */
1589 if ( !(phy_reg & 0x01e0)) {
1590 phy_reg|=db->PHY_reg4;
1591 db->media_mode|=ULI526X_AUTO;
1592 }
3acf4b5c 1593 phy->write(db, db->phy_addr, 4, phy_reg);
4689ced9
PC		 1594
1595 /* Restart Auto-Negotiation */
3acf4b5c 1596 phy->write(db, db->phy_addr, 0, 0x1200);
4689ced9
PC		 1597 udelay(50);
1598}
1599
1600
1601/*
1602 * Process op-mode
1603 AUTO mode : PHY controller in Auto-negotiation Mode
1604 * Force mode: PHY controller in force mode with HUB
1605 * N-way force capability with SWITCH
1606 */
1607
1608static void uli526x_process_mode(struct uli526x_board_info *db)
1609{
3acf4b5c 1610 struct uli_phy_ops *phy = &db->phy;
4689ced9
PC		 1611 u16 phy_reg;
1612
1613 /* Full Duplex Mode Check */
1614 if (db->op_mode & 0x4)
1615 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1616 else
1617 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1618
1619 update_cr6(db->cr6_data, db->ioaddr);
1620
1621 /* 10/100M phyxcer force mode need */
3acf4b5c 1622 if (!(db->media_mode & 0x8)) {
4689ced9 1623 /* Forece Mode */
3acf4b5c
FR		 1624 phy_reg = phy->read(db, db->phy_addr, 6);
1625 if (!(phy_reg & 0x1)) {
4689ced9
PC		 1626 /* parter without N-Way capability */
1627 phy_reg = 0x0;
1628 switch(db->op_mode) {
1629 case ULI526X_10MHF: phy_reg = 0x0; break;
1630 case ULI526X_10MFD: phy_reg = 0x100; break;
1631 case ULI526X_100MHF: phy_reg = 0x2000; break;
1632 case ULI526X_100MFD: phy_reg = 0x2100; break;
1633 }
3acf4b5c 1634 phy->write(db, db->phy_addr, 0, phy_reg);
4689ced9
PC		 1635 }
1636 }
1637}
1638
1639
3acf4b5c
FR		 1640/* M5261/M5263 Chip */
1641static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1642 u8 offset, u16 phy_data)
4689ced9
PC		 1643{
1644 u16 i;
4689ced9
PC		 1645
1646 /* Send 33 synchronization clock to Phy controller */
1647 for (i = 0; i < 35; i++)
3acf4b5c 1648 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1649
1650 /* Send start command(01) to Phy */
3acf4b5c
FR		 1651 phy_write_1bit(db, PHY_DATA_0);
1652 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1653
1654 /* Send write command(01) to Phy */
3acf4b5c
FR		 1655 phy_write_1bit(db, PHY_DATA_0);
1656 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1657
1658 /* Send Phy address */
1659 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1660 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1661
1662 /* Send register address */
1663 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1664 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1665
1666 /* written trasnition */
3acf4b5c
FR		 1667 phy_write_1bit(db, PHY_DATA_1);
1668 phy_write_1bit(db, PHY_DATA_0);
4689ced9
PC		 1669
1670 /* Write a word data to PHY controller */
3acf4b5c
FR		 1671 for (i = 0x8000; i > 0; i >>= 1)
1672 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1673}
1674
3acf4b5c 1675static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
4689ced9 1676{
4689ced9 1677 u16 phy_data;
3acf4b5c 1678 int i;
f3b197ac 1679
4689ced9
PC		 1680 /* Send 33 synchronization clock to Phy controller */
1681 for (i = 0; i < 35; i++)
3acf4b5c 1682 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1683
1684 /* Send start command(01) to Phy */
3acf4b5c
FR		 1685 phy_write_1bit(db, PHY_DATA_0);
1686 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1687
1688 /* Send read command(10) to Phy */
3acf4b5c
FR		 1689 phy_write_1bit(db, PHY_DATA_1);
1690 phy_write_1bit(db, PHY_DATA_0);
4689ced9
PC		 1691
1692 /* Send Phy address */
1693 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1694 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1695
1696 /* Send register address */
1697 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1698 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1699
1700 /* Skip transition state */
3acf4b5c 1701 phy_read_1bit(db);
4689ced9
PC		 1702
1703 /* read 16bit data */
1704 for (phy_data = 0, i = 0; i < 16; i++) {
1705 phy_data <<= 1;
3acf4b5c 1706 phy_data |= phy_read_1bit(db);
4689ced9
PC		 1707 }
1708
1709 return phy_data;
1710}
1711
3acf4b5c
FR		 1712static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1713 u8 offset)
4689ced9 1714{
3acf4b5c
FR		 1715 void __iomem *ioaddr = db->ioaddr;
1716 u32 cr10_value = phy_addr;
f3b197ac 1717
3acf4b5c
FR		 1718 cr10_value = (cr10_value << 5) + offset;
1719 cr10_value = (cr10_value << 16) + 0x08000000;
1720 uw32(DCR10, cr10_value);
4689ced9 1721 udelay(1);
3acf4b5c
FR		 1722 while (1) {
1723 cr10_value = ur32(DCR10);
1724 if (cr10_value & 0x10000000)
4689ced9
PC		 1725 break;
1726 }
807540ba 1727 return cr10_value & 0x0ffff;
4689ced9
PC		 1728}
1729
3acf4b5c
FR		 1730static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1731 u8 offset, u16 phy_data)
4689ced9 1732{
3acf4b5c
FR		 1733 void __iomem *ioaddr = db->ioaddr;
1734 u32 cr10_value = phy_addr;
f3b197ac 1735
3acf4b5c
FR		 1736 cr10_value = (cr10_value << 5) + offset;
1737 cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1738 uw32(DCR10, cr10_value);
4689ced9
PC		 1739 udelay(1);
1740}
1741/*
1742 * Write one bit data to Phy Controller
1743 */
1744
3acf4b5c 1745static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
4689ced9 1746{
3acf4b5c
FR		 1747 void __iomem *ioaddr = db->ioaddr;
1748
1749 uw32(DCR9, data); /* MII Clock Low */
4689ced9 1750 udelay(1);
3acf4b5c 1751 uw32(DCR9, data | MDCLKH); /* MII Clock High */
4689ced9 1752 udelay(1);
3acf4b5c 1753 uw32(DCR9, data); /* MII Clock Low */
4689ced9
PC		 1754 udelay(1);
1755}
1756
1757
1758/*
1759 * Read one bit phy data from PHY controller
1760 */
1761
3acf4b5c 1762static u16 phy_read_1bit(struct uli526x_board_info *db)
4689ced9 1763{
3acf4b5c 1764 void __iomem *ioaddr = db->ioaddr;
4689ced9 1765 u16 phy_data;
f3b197ac 1766
3acf4b5c 1767 uw32(DCR9, 0x50000);
4689ced9 1768 udelay(1);
3acf4b5c
FR		 1769 phy_data = (ur32(DCR9) >> 19) & 0x1;
1770 uw32(DCR9, 0x40000);
4689ced9
PC		 1771 udelay(1);
1772
1773 return phy_data;
1774}
1775
1776
9baa3c34 1777static const struct pci_device_id uli526x_pci_tbl[] = {
4689ced9
PC		 1778 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1779 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1780 { 0, }
1781};
1782MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1783
1784
1785static struct pci_driver uli526x_driver = {
1786 .name = "uli526x",
1787 .id_table = uli526x_pci_tbl,
1788 .probe = uli526x_init_one,
779c1a85 1789 .remove = uli526x_remove_one,
b6aec32a
RW		 1790 .suspend = uli526x_suspend,
1791 .resume = uli526x_resume,
4689ced9
PC		 1792};
1793
1794MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1795MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1796MODULE_LICENSE("GPL");
1797
c213460f
ES		 1798module_param(debug, int, 0644);
1799module_param(mode, int, 0);
1800module_param(cr6set, int, 0);
4689ced9
PC		 1801MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1802MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1803
1804/* Description:
1805 * when user used insmod to add module, system invoked init_module()
945a7876 1806 * to register the services.
4689ced9
PC		 1807 */
1808
1809static int __init uli526x_init_module(void)
1810{
4689ced9 1811
1c3319fb 1812 pr_info("%s\n", version);
4689ced9
PC		 1813 printed_version = 1;
1814
1815 ULI526X_DBUG(0, "init_module() ", debug);
1816
1817 if (debug)
1818 uli526x_debug = debug; /* set debug flag */
1819 if (cr6set)
1820 uli526x_cr6_user_set = cr6set;
1821
e1c3e501 1822 switch (mode) {
4689ced9
PC		 1823 case ULI526X_10MHF:
1824 case ULI526X_100MHF:
1825 case ULI526X_10MFD:
1826 case ULI526X_100MFD:
1827 uli526x_media_mode = mode;
1828 break;
e1c3e501
HK		 1829 default:
1830 uli526x_media_mode = ULI526X_AUTO;
4689ced9
PC		 1831 break;
1832 }
1833
e1c3e501 1834 return pci_register_driver(&uli526x_driver);
4689ced9
PC		 1835}
1836
1837
1838/*
1839 * Description:
1840 * when user used rmmod to delete module, system invoked clean_module()
1841 * to un-register all registered services.
1842 */
1843
1844static void __exit uli526x_cleanup_module(void)
1845{
791a1ddd 1846 ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
4689ced9
PC		 1847 pci_unregister_driver(&uli526x_driver);
1848}
1849
1850module_init(uli526x_init_module);
1851module_exit(uli526x_cleanup_module);