Commit | Line | Data |
---|---|---|
4689ced9 PC |
1 | /* |
2 | This program is free software; you can redistribute it and/or | |
3 | modify it under the terms of the GNU General Public License | |
4 | as published by the Free Software Foundation; either version 2 | |
5 | of the License, or (at your option) any later version. | |
6 | ||
7 | This program is distributed in the hope that it will be useful, | |
8 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | GNU General Public License for more details. | |
11 | ||
f3b197ac | 12 | |
4689ced9 PC |
13 | */ |
14 | ||
e02fb7aa JP |
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
16 | ||
4689ced9 PC |
17 | #define DRV_NAME "uli526x" |
18 | #define DRV_VERSION "0.9.3" | |
19 | #define DRV_RELDATE "2005-7-29" | |
20 | ||
21 | #include <linux/module.h> | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/timer.h> | |
4689ced9 PC |
26 | #include <linux/errno.h> |
27 | #include <linux/ioport.h> | |
4689ced9 PC |
28 | #include <linux/interrupt.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/spinlock.h> | |
6cafa99f | 37 | #include <linux/dma-mapping.h> |
1977f032 | 38 | #include <linux/bitops.h> |
4689ced9 PC |
39 | |
40 | #include <asm/processor.h> | |
4689ced9 PC |
41 | #include <asm/io.h> |
42 | #include <asm/dma.h> | |
7c0f6ba6 | 43 | #include <linux/uaccess.h> |
4689ced9 | 44 | |
3acf4b5c FR |
45 | #define uw32(reg, val) iowrite32(val, ioaddr + (reg)) |
46 | #define ur32(reg) ioread32(ioaddr + (reg)) | |
4689ced9 PC |
47 | |
48 | /* Board/System/Debug information/definition ---------------- */ | |
49 | #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ | |
50 | #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ | |
51 | ||
52 | #define ULI526X_IO_SIZE 0x100 | |
53 | #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ | |
54 | #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ | |
55 | #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ | |
56 | #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ | |
57 | #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) | |
58 | #define TX_BUF_ALLOC 0x600 | |
59 | #define RX_ALLOC_SIZE 0x620 | |
60 | #define ULI526X_RESET 1 | |
61 | #define CR0_DEFAULT 0 | |
945a7876 | 62 | #define CR6_DEFAULT 0x22200000 |
4689ced9 PC |
63 | #define CR7_DEFAULT 0x180c1 |
64 | #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ | |
65 | #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ | |
66 | #define MAX_PACKET_SIZE 1514 | |
67 | #define ULI5261_MAX_MULTICAST 14 | |
68 | #define RX_COPY_SIZE 100 | |
69 | #define MAX_CHECK_PACKET 0x8000 | |
70 | ||
71 | #define ULI526X_10MHF 0 | |
72 | #define ULI526X_100MHF 1 | |
73 | #define ULI526X_10MFD 4 | |
74 | #define ULI526X_100MFD 5 | |
75 | #define ULI526X_AUTO 8 | |
76 | ||
77 | #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ | |
78 | #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ | |
79 | #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ | |
80 | #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ | |
81 | #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ | |
82 | #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ | |
83 | ||
84 | #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ | |
85 | #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */ | |
86 | #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */ | |
87 | ||
e02fb7aa JP |
88 | #define ULI526X_DBUG(dbug_now, msg, value) \ |
89 | do { \ | |
90 | if (uli526x_debug || (dbug_now)) \ | |
91 | pr_err("%s %lx\n", (msg), (long) (value)); \ | |
92 | } while (0) | |
4689ced9 | 93 | |
e02fb7aa JP |
94 | #define SHOW_MEDIA_TYPE(mode) \ |
95 | pr_err("Change Speed to %sMhz %s duplex\n", \ | |
96 | mode & 1 ? "100" : "10", \ | |
97 | mode & 4 ? "full" : "half"); | |
4689ced9 PC |
98 | |
99 | ||
100 | /* CR9 definition: SROM/MII */ | |
101 | #define CR9_SROM_READ 0x4800 | |
102 | #define CR9_SRCS 0x1 | |
103 | #define CR9_SRCLK 0x2 | |
104 | #define CR9_CRDOUT 0x8 | |
105 | #define SROM_DATA_0 0x0 | |
106 | #define SROM_DATA_1 0x4 | |
107 | #define PHY_DATA_1 0x20000 | |
108 | #define PHY_DATA_0 0x00000 | |
109 | #define MDCLKH 0x10000 | |
110 | ||
111 | #define PHY_POWER_DOWN 0x800 | |
112 | ||
113 | #define SROM_V41_CODE 0x14 | |
114 | ||
4689ced9 PC |
115 | /* Structure/enum declaration ------------------------------- */ |
116 | struct tx_desc { | |
c559a5bc | 117 | __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ |
4689ced9 PC |
118 | char *tx_buf_ptr; /* Data for us */ |
119 | struct tx_desc *next_tx_desc; | |
120 | } __attribute__(( aligned(32) )); | |
121 | ||
122 | struct rx_desc { | |
c559a5bc | 123 | __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ |
4689ced9 PC |
124 | struct sk_buff *rx_skb_ptr; /* Data for us */ |
125 | struct rx_desc *next_rx_desc; | |
126 | } __attribute__(( aligned(32) )); | |
127 | ||
128 | struct uli526x_board_info { | |
3acf4b5c FR |
129 | struct uli_phy_ops { |
130 | void (*write)(struct uli526x_board_info *, u8, u8, u16); | |
131 | u16 (*read)(struct uli526x_board_info *, u8, u8); | |
132 | } phy; | |
945a7876 | 133 | struct net_device *next_dev; /* next device */ |
4689ced9 PC |
134 | struct pci_dev *pdev; /* PCI device */ |
135 | spinlock_t lock; | |
136 | ||
3acf4b5c | 137 | void __iomem *ioaddr; /* I/O base address */ |
4689ced9 PC |
138 | u32 cr0_data; |
139 | u32 cr5_data; | |
140 | u32 cr6_data; | |
141 | u32 cr7_data; | |
142 | u32 cr15_data; | |
143 | ||
144 | /* pointer for memory physical address */ | |
145 | dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ | |
146 | dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ | |
147 | dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ | |
148 | dma_addr_t first_tx_desc_dma; | |
149 | dma_addr_t first_rx_desc_dma; | |
150 | ||
151 | /* descriptor pointer */ | |
152 | unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ | |
153 | unsigned char *buf_pool_start; /* Tx buffer pool align dword */ | |
154 | unsigned char *desc_pool_ptr; /* descriptor pool memory */ | |
155 | struct tx_desc *first_tx_desc; | |
156 | struct tx_desc *tx_insert_ptr; | |
157 | struct tx_desc *tx_remove_ptr; | |
158 | struct rx_desc *first_rx_desc; | |
159 | struct rx_desc *rx_insert_ptr; | |
160 | struct rx_desc *rx_ready_ptr; /* packet come pointer */ | |
161 | unsigned long tx_packet_cnt; /* transmitted packet count */ | |
162 | unsigned long rx_avail_cnt; /* available rx descriptor count */ | |
163 | unsigned long interval_rx_cnt; /* rx packet count a callback time */ | |
164 | ||
165 | u16 dbug_cnt; | |
166 | u16 NIC_capability; /* NIC media capability */ | |
167 | u16 PHY_reg4; /* Saved Phyxcer register 4 value */ | |
168 | ||
169 | u8 media_mode; /* user specify media mode */ | |
170 | u8 op_mode; /* real work media mode */ | |
171 | u8 phy_addr; | |
172 | u8 link_failed; /* Ever link failed */ | |
173 | u8 wait_reset; /* Hardware failed, need to reset */ | |
174 | struct timer_list timer; | |
175 | ||
4689ced9 PC |
176 | /* Driver defined statistic counter */ |
177 | unsigned long tx_fifo_underrun; | |
178 | unsigned long tx_loss_carrier; | |
179 | unsigned long tx_no_carrier; | |
180 | unsigned long tx_late_collision; | |
181 | unsigned long tx_excessive_collision; | |
182 | unsigned long tx_jabber_timeout; | |
183 | unsigned long reset_count; | |
184 | unsigned long reset_cr8; | |
185 | unsigned long reset_fatal; | |
186 | unsigned long reset_TXtimeout; | |
187 | ||
188 | /* NIC SROM data */ | |
189 | unsigned char srom[128]; | |
f3b197ac | 190 | u8 init; |
4689ced9 PC |
191 | }; |
192 | ||
193 | enum uli526x_offsets { | |
194 | DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, | |
195 | DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, | |
196 | DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, | |
197 | DCR15 = 0x78 | |
198 | }; | |
199 | ||
200 | enum uli526x_CR6_bits { | |
201 | CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, | |
202 | CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, | |
203 | CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 | |
204 | }; | |
205 | ||
206 | /* Global variable declaration ----------------------------- */ | |
779c1a85 BP |
207 | static int printed_version; |
208 | static const char version[] = | |
1c3319fb | 209 | "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")"; |
4689ced9 PC |
210 | |
211 | static int uli526x_debug; | |
212 | static unsigned char uli526x_media_mode = ULI526X_AUTO; | |
213 | static u32 uli526x_cr6_user_set; | |
214 | ||
215 | /* For module input parameter */ | |
216 | static int debug; | |
217 | static u32 cr6set; | |
99bb2579 | 218 | static int mode = 8; |
4689ced9 PC |
219 | |
220 | /* function declaration ------------------------------------- */ | |
945a7876 | 221 | static int uli526x_open(struct net_device *); |
ad096463 SH |
222 | static netdev_tx_t uli526x_start_xmit(struct sk_buff *, |
223 | struct net_device *); | |
945a7876 | 224 | static int uli526x_stop(struct net_device *); |
945a7876 | 225 | static void uli526x_set_filter_mode(struct net_device *); |
7282d491 | 226 | static const struct ethtool_ops netdev_ethtool_ops; |
3acf4b5c | 227 | static u16 read_srom_word(struct uli526x_board_info *, int); |
7d12e780 | 228 | static irqreturn_t uli526x_interrupt(int, void *); |
7fa0cba3 AV |
229 | #ifdef CONFIG_NET_POLL_CONTROLLER |
230 | static void uli526x_poll(struct net_device *dev); | |
231 | #endif | |
3acf4b5c | 232 | static void uli526x_descriptor_init(struct net_device *, void __iomem *); |
1ab0d2ec | 233 | static void allocate_rx_buffer(struct net_device *); |
3acf4b5c | 234 | static void update_cr6(u32, void __iomem *); |
945a7876 | 235 | static void send_filter_frame(struct net_device *, int); |
3acf4b5c FR |
236 | static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8); |
237 | static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8); | |
238 | static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16); | |
239 | static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16); | |
240 | static void phy_write_1bit(struct uli526x_board_info *db, u32); | |
241 | static u16 phy_read_1bit(struct uli526x_board_info *db); | |
4689ced9 PC |
242 | static u8 uli526x_sense_speed(struct uli526x_board_info *); |
243 | static void uli526x_process_mode(struct uli526x_board_info *); | |
244 | static void uli526x_timer(unsigned long); | |
945a7876 PC |
245 | static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *); |
246 | static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *); | |
4689ced9 | 247 | static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *); |
945a7876 | 248 | static void uli526x_dynamic_reset(struct net_device *); |
4689ced9 | 249 | static void uli526x_free_rxbuffer(struct uli526x_board_info *); |
945a7876 | 250 | static void uli526x_init(struct net_device *); |
4689ced9 PC |
251 | static void uli526x_set_phyxcer(struct uli526x_board_info *); |
252 | ||
3acf4b5c FR |
253 | static void srom_clk_write(struct uli526x_board_info *db, u32 data) |
254 | { | |
255 | void __iomem *ioaddr = db->ioaddr; | |
256 | ||
257 | uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS); | |
258 | udelay(5); | |
259 | uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK); | |
260 | udelay(5); | |
261 | uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS); | |
262 | udelay(5); | |
263 | } | |
264 | ||
945a7876 | 265 | /* ULI526X network board routine ---------------------------- */ |
4689ced9 | 266 | |
dfefe02b SH |
267 | static const struct net_device_ops netdev_ops = { |
268 | .ndo_open = uli526x_open, | |
269 | .ndo_stop = uli526x_stop, | |
270 | .ndo_start_xmit = uli526x_start_xmit, | |
afc4b13d | 271 | .ndo_set_rx_mode = uli526x_set_filter_mode, |
dfefe02b SH |
272 | .ndo_set_mac_address = eth_mac_addr, |
273 | .ndo_validate_addr = eth_validate_addr, | |
274 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
275 | .ndo_poll_controller = uli526x_poll, | |
276 | #endif | |
277 | }; | |
278 | ||
4689ced9 | 279 | /* |
945a7876 | 280 | * Search ULI526X board, allocate space and register it |
4689ced9 PC |
281 | */ |
282 | ||
779c1a85 BP |
283 | static int uli526x_init_one(struct pci_dev *pdev, |
284 | const struct pci_device_id *ent) | |
4689ced9 PC |
285 | { |
286 | struct uli526x_board_info *db; /* board information structure */ | |
287 | struct net_device *dev; | |
3acf4b5c | 288 | void __iomem *ioaddr; |
4689ced9 | 289 | int i, err; |
f3b197ac | 290 | |
4689ced9 PC |
291 | ULI526X_DBUG(0, "uli526x_init_one()", 0); |
292 | ||
293 | if (!printed_version++) | |
1c3319fb | 294 | pr_info("%s\n", version); |
4689ced9 PC |
295 | |
296 | /* Init network device */ | |
297 | dev = alloc_etherdev(sizeof(*db)); | |
298 | if (dev == NULL) | |
299 | return -ENOMEM; | |
4689ced9 PC |
300 | SET_NETDEV_DEV(dev, &pdev->dev); |
301 | ||
284901a9 | 302 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
163ef0b5 | 303 | pr_warn("32-bit PCI DMA not available\n"); |
4689ced9 PC |
304 | err = -ENODEV; |
305 | goto err_out_free; | |
306 | } | |
307 | ||
308 | /* Enable Master/IO access, Disable memory access */ | |
309 | err = pci_enable_device(pdev); | |
310 | if (err) | |
311 | goto err_out_free; | |
312 | ||
313 | if (!pci_resource_start(pdev, 0)) { | |
e02fb7aa | 314 | pr_err("I/O base is zero\n"); |
4689ced9 PC |
315 | err = -ENODEV; |
316 | goto err_out_disable; | |
317 | } | |
318 | ||
319 | if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { | |
e02fb7aa | 320 | pr_err("Allocated I/O size too small\n"); |
4689ced9 PC |
321 | err = -ENODEV; |
322 | goto err_out_disable; | |
323 | } | |
324 | ||
5e58deb9 FR |
325 | err = pci_request_regions(pdev, DRV_NAME); |
326 | if (err < 0) { | |
e02fb7aa | 327 | pr_err("Failed to request PCI regions\n"); |
4689ced9 PC |
328 | goto err_out_disable; |
329 | } | |
330 | ||
4689ced9 PC |
331 | /* Init system & device */ |
332 | db = netdev_priv(dev); | |
333 | ||
334 | /* Allocate Tx/Rx descriptor memory */ | |
5e58deb9 FR |
335 | err = -ENOMEM; |
336 | ||
4689ced9 | 337 | db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); |
5e58deb9 FR |
338 | if (!db->desc_pool_ptr) |
339 | goto err_out_release; | |
340 | ||
4689ced9 | 341 | db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); |
5e58deb9 FR |
342 | if (!db->buf_pool_ptr) |
343 | goto err_out_free_tx_desc; | |
f3b197ac | 344 | |
4689ced9 PC |
345 | db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; |
346 | db->first_tx_desc_dma = db->desc_pool_dma_ptr; | |
347 | db->buf_pool_start = db->buf_pool_ptr; | |
348 | db->buf_pool_dma_start = db->buf_pool_dma_ptr; | |
349 | ||
3acf4b5c FR |
350 | switch (ent->driver_data) { |
351 | case PCI_ULI5263_ID: | |
352 | db->phy.write = phy_writeby_cr10; | |
353 | db->phy.read = phy_readby_cr10; | |
354 | break; | |
355 | default: | |
356 | db->phy.write = phy_writeby_cr9; | |
357 | db->phy.read = phy_readby_cr9; | |
358 | break; | |
359 | } | |
360 | ||
361 | /* IO region. */ | |
362 | ioaddr = pci_iomap(pdev, 0, 0); | |
363 | if (!ioaddr) | |
364 | goto err_out_free_tx_buf; | |
f3b197ac | 365 | |
3acf4b5c | 366 | db->ioaddr = ioaddr; |
4689ced9 PC |
367 | db->pdev = pdev; |
368 | db->init = 1; | |
f3b197ac | 369 | |
4689ced9 | 370 | pci_set_drvdata(pdev, dev); |
f3b197ac | 371 | |
4689ced9 | 372 | /* Register some necessary functions */ |
dfefe02b | 373 | dev->netdev_ops = &netdev_ops; |
4689ced9 | 374 | dev->ethtool_ops = &netdev_ethtool_ops; |
dfefe02b | 375 | |
4689ced9 PC |
376 | spin_lock_init(&db->lock); |
377 | ||
f3b197ac | 378 | |
4689ced9 PC |
379 | /* read 64 word srom data */ |
380 | for (i = 0; i < 64; i++) | |
3acf4b5c | 381 | ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i)); |
4689ced9 PC |
382 | |
383 | /* Set Node address */ | |
945a7876 | 384 | if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */ |
4689ced9 | 385 | { |
3acf4b5c FR |
386 | uw32(DCR0, 0x10000); //Diagnosis mode |
387 | uw32(DCR13, 0x1c0); //Reset dianostic pointer port | |
388 | uw32(DCR14, 0); //Clear reset port | |
389 | uw32(DCR14, 0x10); //Reset ID Table pointer | |
390 | uw32(DCR14, 0); //Clear reset port | |
391 | uw32(DCR13, 0); //Clear CR13 | |
392 | uw32(DCR13, 0x1b0); //Select ID Table access port | |
4689ced9 PC |
393 | //Read MAC address from CR14 |
394 | for (i = 0; i < 6; i++) | |
3acf4b5c | 395 | dev->dev_addr[i] = ur32(DCR14); |
4689ced9 | 396 | //Read end |
3acf4b5c FR |
397 | uw32(DCR13, 0); //Clear CR13 |
398 | uw32(DCR0, 0); //Clear CR0 | |
4689ced9 PC |
399 | udelay(10); |
400 | } | |
401 | else /*Exist SROM*/ | |
402 | { | |
403 | for (i = 0; i < 6; i++) | |
404 | dev->dev_addr[i] = db->srom[20 + i]; | |
405 | } | |
406 | err = register_netdev (dev); | |
407 | if (err) | |
3acf4b5c | 408 | goto err_out_unmap; |
4689ced9 | 409 | |
163ef0b5 JP |
410 | netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n", |
411 | ent->driver_data >> 16, pci_name(pdev), | |
3acf4b5c | 412 | dev->dev_addr, pdev->irq); |
4689ced9 PC |
413 | |
414 | pci_set_master(pdev); | |
415 | ||
416 | return 0; | |
417 | ||
3acf4b5c FR |
418 | err_out_unmap: |
419 | pci_iounmap(pdev, db->ioaddr); | |
5e58deb9 FR |
420 | err_out_free_tx_buf: |
421 | pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | |
422 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | |
423 | err_out_free_tx_desc: | |
424 | pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, | |
425 | db->desc_pool_ptr, db->desc_pool_dma_ptr); | |
426 | err_out_release: | |
4689ced9 PC |
427 | pci_release_regions(pdev); |
428 | err_out_disable: | |
429 | pci_disable_device(pdev); | |
430 | err_out_free: | |
4689ced9 PC |
431 | free_netdev(dev); |
432 | ||
433 | return err; | |
434 | } | |
435 | ||
436 | ||
779c1a85 | 437 | static void uli526x_remove_one(struct pci_dev *pdev) |
4689ced9 PC |
438 | { |
439 | struct net_device *dev = pci_get_drvdata(pdev); | |
440 | struct uli526x_board_info *db = netdev_priv(dev); | |
441 | ||
5e58deb9 | 442 | unregister_netdev(dev); |
3acf4b5c | 443 | pci_iounmap(pdev, db->ioaddr); |
945a7876 PC |
444 | pci_free_consistent(db->pdev, sizeof(struct tx_desc) * |
445 | DESC_ALL_CNT + 0x20, db->desc_pool_ptr, | |
446 | db->desc_pool_dma_ptr); | |
447 | pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | |
448 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | |
945a7876 | 449 | pci_release_regions(pdev); |
945a7876 | 450 | pci_disable_device(pdev); |
5e58deb9 | 451 | free_netdev(dev); |
4689ced9 PC |
452 | } |
453 | ||
454 | ||
455 | /* | |
456 | * Open the interface. | |
945a7876 | 457 | * The interface is opened whenever "ifconfig" activates it. |
4689ced9 PC |
458 | */ |
459 | ||
945a7876 | 460 | static int uli526x_open(struct net_device *dev) |
4689ced9 PC |
461 | { |
462 | int ret; | |
463 | struct uli526x_board_info *db = netdev_priv(dev); | |
f3b197ac | 464 | |
4689ced9 PC |
465 | ULI526X_DBUG(0, "uli526x_open", 0); |
466 | ||
4689ced9 PC |
467 | /* system variable init */ |
468 | db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set; | |
4689ced9 PC |
469 | db->tx_packet_cnt = 0; |
470 | db->rx_avail_cnt = 0; | |
471 | db->link_failed = 1; | |
472 | netif_carrier_off(dev); | |
473 | db->wait_reset = 0; | |
474 | ||
475 | db->NIC_capability = 0xf; /* All capability*/ | |
476 | db->PHY_reg4 = 0x1e0; | |
477 | ||
478 | /* CR6 operation mode decision */ | |
479 | db->cr6_data |= ULI526X_TXTH_256; | |
480 | db->cr0_data = CR0_DEFAULT; | |
f3b197ac | 481 | |
945a7876 | 482 | /* Initialize ULI526X board */ |
4689ced9 PC |
483 | uli526x_init(dev); |
484 | ||
3acf4b5c FR |
485 | ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED, |
486 | dev->name, dev); | |
afd8e399 AV |
487 | if (ret) |
488 | return ret; | |
489 | ||
4689ced9 PC |
490 | /* Active System Interface */ |
491 | netif_wake_queue(dev); | |
492 | ||
493 | /* set and active a timer process */ | |
494 | init_timer(&db->timer); | |
495 | db->timer.expires = ULI526X_TIMER_WUT + HZ * 2; | |
496 | db->timer.data = (unsigned long)dev; | |
c061b18d | 497 | db->timer.function = uli526x_timer; |
4689ced9 PC |
498 | add_timer(&db->timer); |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | ||
945a7876 | 504 | /* Initialize ULI526X board |
4689ced9 | 505 | * Reset ULI526X board |
945a7876 | 506 | * Initialize TX/Rx descriptor chain structure |
4689ced9 PC |
507 | * Send the set-up frame |
508 | * Enable Tx/Rx machine | |
509 | */ | |
510 | ||
945a7876 | 511 | static void uli526x_init(struct net_device *dev) |
4689ced9 PC |
512 | { |
513 | struct uli526x_board_info *db = netdev_priv(dev); | |
3acf4b5c FR |
514 | struct uli_phy_ops *phy = &db->phy; |
515 | void __iomem *ioaddr = db->ioaddr; | |
4689ced9 | 516 | u8 phy_tmp; |
7a7d23da | 517 | u8 timeout; |
4689ced9 PC |
518 | u16 phy_reg_reset; |
519 | ||
7a7d23da | 520 | |
4689ced9 PC |
521 | ULI526X_DBUG(0, "uli526x_init()", 0); |
522 | ||
523 | /* Reset M526x MAC controller */ | |
3acf4b5c | 524 | uw32(DCR0, ULI526X_RESET); /* RESET MAC */ |
4689ced9 | 525 | udelay(100); |
3acf4b5c | 526 | uw32(DCR0, db->cr0_data); |
4689ced9 PC |
527 | udelay(5); |
528 | ||
529 | /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ | |
530 | db->phy_addr = 1; | |
3acf4b5c FR |
531 | for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) { |
532 | u16 phy_value; | |
533 | ||
534 | phy_value = phy->read(db, phy_tmp, 3); //peer add | |
535 | if (phy_value != 0xffff && phy_value != 0) { | |
4689ced9 PC |
536 | db->phy_addr = phy_tmp; |
537 | break; | |
538 | } | |
539 | } | |
3acf4b5c FR |
540 | |
541 | if (phy_tmp == 32) | |
163ef0b5 | 542 | pr_warn("Can not find the phy address!!!\n"); |
4689ced9 PC |
543 | /* Parser SROM and media mode */ |
544 | db->media_mode = uli526x_media_mode; | |
545 | ||
7a7d23da | 546 | /* phyxcer capability setting */ |
3acf4b5c | 547 | phy_reg_reset = phy->read(db, db->phy_addr, 0); |
4689ced9 | 548 | phy_reg_reset = (phy_reg_reset | 0x8000); |
3acf4b5c | 549 | phy->write(db, db->phy_addr, 0, phy_reg_reset); |
7a7d23da GG |
550 | |
551 | /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management | |
552 | * functions") or phy data sheet for details on phy reset | |
553 | */ | |
4689ced9 | 554 | udelay(500); |
7a7d23da | 555 | timeout = 10; |
3acf4b5c FR |
556 | while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000) |
557 | udelay(100); | |
4689ced9 PC |
558 | |
559 | /* Process Phyxcer Media Mode */ | |
560 | uli526x_set_phyxcer(db); | |
561 | ||
562 | /* Media Mode Process */ | |
563 | if ( !(db->media_mode & ULI526X_AUTO) ) | |
3acf4b5c | 564 | db->op_mode = db->media_mode; /* Force Mode */ |
4689ced9 | 565 | |
dbedd44e | 566 | /* Initialize Transmit/Receive descriptor and CR3/4 */ |
1ab0d2ec | 567 | uli526x_descriptor_init(dev, ioaddr); |
4689ced9 PC |
568 | |
569 | /* Init CR6 to program M526X operation */ | |
570 | update_cr6(db->cr6_data, ioaddr); | |
571 | ||
572 | /* Send setup frame */ | |
4cd24eaf | 573 | send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */ |
4689ced9 PC |
574 | |
575 | /* Init CR7, interrupt active bit */ | |
576 | db->cr7_data = CR7_DEFAULT; | |
3acf4b5c | 577 | uw32(DCR7, db->cr7_data); |
4689ced9 PC |
578 | |
579 | /* Init CR15, Tx jabber and Rx watchdog timer */ | |
3acf4b5c | 580 | uw32(DCR15, db->cr15_data); |
4689ced9 PC |
581 | |
582 | /* Enable ULI526X Tx/Rx function */ | |
583 | db->cr6_data |= CR6_RXSC | CR6_TXSC; | |
584 | update_cr6(db->cr6_data, ioaddr); | |
585 | } | |
586 | ||
587 | ||
588 | /* | |
589 | * Hardware start transmission. | |
590 | * Send a packet to media from the upper layer. | |
591 | */ | |
592 | ||
ad096463 SH |
593 | static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb, |
594 | struct net_device *dev) | |
4689ced9 PC |
595 | { |
596 | struct uli526x_board_info *db = netdev_priv(dev); | |
3acf4b5c | 597 | void __iomem *ioaddr = db->ioaddr; |
4689ced9 PC |
598 | struct tx_desc *txptr; |
599 | unsigned long flags; | |
600 | ||
601 | ULI526X_DBUG(0, "uli526x_start_xmit", 0); | |
602 | ||
603 | /* Resource flag check */ | |
604 | netif_stop_queue(dev); | |
605 | ||
606 | /* Too large packet check */ | |
607 | if (skb->len > MAX_PACKET_SIZE) { | |
163ef0b5 | 608 | netdev_err(dev, "big packet = %d\n", (u16)skb->len); |
290a79db | 609 | dev_kfree_skb_any(skb); |
6ed10654 | 610 | return NETDEV_TX_OK; |
4689ced9 PC |
611 | } |
612 | ||
613 | spin_lock_irqsave(&db->lock, flags); | |
614 | ||
615 | /* No Tx resource check, it never happen nromally */ | |
616 | if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { | |
617 | spin_unlock_irqrestore(&db->lock, flags); | |
163ef0b5 | 618 | netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt); |
5b548140 | 619 | return NETDEV_TX_BUSY; |
4689ced9 PC |
620 | } |
621 | ||
622 | /* Disable NIC interrupt */ | |
3acf4b5c | 623 | uw32(DCR7, 0); |
4689ced9 PC |
624 | |
625 | /* transmit this packet */ | |
626 | txptr = db->tx_insert_ptr; | |
d626f62b | 627 | skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len); |
4689ced9 PC |
628 | txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); |
629 | ||
630 | /* Point to next transmit free descriptor */ | |
631 | db->tx_insert_ptr = txptr->next_tx_desc; | |
632 | ||
633 | /* Transmit Packet Process */ | |
3acf4b5c | 634 | if (db->tx_packet_cnt < TX_DESC_CNT) { |
4689ced9 PC |
635 | txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ |
636 | db->tx_packet_cnt++; /* Ready to send */ | |
3acf4b5c | 637 | uw32(DCR1, 0x1); /* Issue Tx polling */ |
860e9538 | 638 | netif_trans_update(dev); /* saved time stamp */ |
4689ced9 PC |
639 | } |
640 | ||
641 | /* Tx resource check */ | |
642 | if ( db->tx_packet_cnt < TX_FREE_DESC_CNT ) | |
643 | netif_wake_queue(dev); | |
644 | ||
645 | /* Restore CR7 to enable interrupt */ | |
646 | spin_unlock_irqrestore(&db->lock, flags); | |
3acf4b5c | 647 | uw32(DCR7, db->cr7_data); |
f3b197ac | 648 | |
4689ced9 | 649 | /* free this SKB */ |
290a79db | 650 | dev_consume_skb_any(skb); |
4689ced9 | 651 | |
6ed10654 | 652 | return NETDEV_TX_OK; |
4689ced9 PC |
653 | } |
654 | ||
655 | ||
656 | /* | |
657 | * Stop the interface. | |
658 | * The interface is stopped when it is brought. | |
659 | */ | |
660 | ||
945a7876 | 661 | static int uli526x_stop(struct net_device *dev) |
4689ced9 PC |
662 | { |
663 | struct uli526x_board_info *db = netdev_priv(dev); | |
3acf4b5c | 664 | void __iomem *ioaddr = db->ioaddr; |
4689ced9 PC |
665 | |
666 | /* disable system */ | |
667 | netif_stop_queue(dev); | |
668 | ||
669 | /* deleted timer */ | |
670 | del_timer_sync(&db->timer); | |
671 | ||
672 | /* Reset & stop ULI526X board */ | |
3acf4b5c | 673 | uw32(DCR0, ULI526X_RESET); |
4689ced9 | 674 | udelay(5); |
3acf4b5c | 675 | db->phy.write(db, db->phy_addr, 0, 0x8000); |
4689ced9 PC |
676 | |
677 | /* free interrupt */ | |
3acf4b5c | 678 | free_irq(db->pdev->irq, dev); |
4689ced9 PC |
679 | |
680 | /* free allocated rx buffer */ | |
681 | uli526x_free_rxbuffer(db); | |
682 | ||
4689ced9 PC |
683 | return 0; |
684 | } | |
685 | ||
686 | ||
687 | /* | |
688 | * M5261/M5263 insterrupt handler | |
689 | * receive the packet to upper layer, free the transmitted packet | |
690 | */ | |
691 | ||
7d12e780 | 692 | static irqreturn_t uli526x_interrupt(int irq, void *dev_id) |
4689ced9 | 693 | { |
945a7876 | 694 | struct net_device *dev = dev_id; |
4689ced9 | 695 | struct uli526x_board_info *db = netdev_priv(dev); |
3acf4b5c | 696 | void __iomem *ioaddr = db->ioaddr; |
4689ced9 PC |
697 | unsigned long flags; |
698 | ||
4689ced9 | 699 | spin_lock_irqsave(&db->lock, flags); |
3acf4b5c | 700 | uw32(DCR7, 0); |
4689ced9 PC |
701 | |
702 | /* Got ULI526X status */ | |
3acf4b5c FR |
703 | db->cr5_data = ur32(DCR5); |
704 | uw32(DCR5, db->cr5_data); | |
4689ced9 | 705 | if ( !(db->cr5_data & 0x180c1) ) { |
7fa0cba3 | 706 | /* Restore CR7 to enable interrupt mask */ |
3acf4b5c | 707 | uw32(DCR7, db->cr7_data); |
7fa0cba3 | 708 | spin_unlock_irqrestore(&db->lock, flags); |
4689ced9 PC |
709 | return IRQ_HANDLED; |
710 | } | |
711 | ||
4689ced9 PC |
712 | /* Check system status */ |
713 | if (db->cr5_data & 0x2000) { | |
714 | /* system bus error happen */ | |
715 | ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data); | |
716 | db->reset_fatal++; | |
717 | db->wait_reset = 1; /* Need to RESET */ | |
718 | spin_unlock_irqrestore(&db->lock, flags); | |
719 | return IRQ_HANDLED; | |
720 | } | |
721 | ||
722 | /* Received the coming packet */ | |
723 | if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) | |
724 | uli526x_rx_packet(dev, db); | |
725 | ||
726 | /* reallocate rx descriptor buffer */ | |
727 | if (db->rx_avail_cnt<RX_DESC_CNT) | |
1ab0d2ec | 728 | allocate_rx_buffer(dev); |
4689ced9 PC |
729 | |
730 | /* Free the transmitted descriptor */ | |
731 | if ( db->cr5_data & 0x01) | |
732 | uli526x_free_tx_pkt(dev, db); | |
733 | ||
734 | /* Restore CR7 to enable interrupt mask */ | |
3acf4b5c | 735 | uw32(DCR7, db->cr7_data); |
4689ced9 PC |
736 | |
737 | spin_unlock_irqrestore(&db->lock, flags); | |
738 | return IRQ_HANDLED; | |
739 | } | |
740 | ||
7fa0cba3 AV |
741 | #ifdef CONFIG_NET_POLL_CONTROLLER |
742 | static void uli526x_poll(struct net_device *dev) | |
743 | { | |
3acf4b5c FR |
744 | struct uli526x_board_info *db = netdev_priv(dev); |
745 | ||
7fa0cba3 | 746 | /* ISR grabs the irqsave lock, so this should be safe */ |
3acf4b5c | 747 | uli526x_interrupt(db->pdev->irq, dev); |
7fa0cba3 AV |
748 | } |
749 | #endif | |
4689ced9 PC |
750 | |
751 | /* | |
752 | * Free TX resource after TX complete | |
753 | */ | |
754 | ||
dfefe02b SH |
755 | static void uli526x_free_tx_pkt(struct net_device *dev, |
756 | struct uli526x_board_info * db) | |
4689ced9 PC |
757 | { |
758 | struct tx_desc *txptr; | |
4689ced9 PC |
759 | u32 tdes0; |
760 | ||
761 | txptr = db->tx_remove_ptr; | |
762 | while(db->tx_packet_cnt) { | |
763 | tdes0 = le32_to_cpu(txptr->tdes0); | |
4689ced9 PC |
764 | if (tdes0 & 0x80000000) |
765 | break; | |
766 | ||
767 | /* A packet sent completed */ | |
768 | db->tx_packet_cnt--; | |
dfefe02b | 769 | dev->stats.tx_packets++; |
4689ced9 PC |
770 | |
771 | /* Transmit statistic counter */ | |
772 | if ( tdes0 != 0x7fffffff ) { | |
dfefe02b SH |
773 | dev->stats.collisions += (tdes0 >> 3) & 0xf; |
774 | dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; | |
4689ced9 | 775 | if (tdes0 & TDES0_ERR_MASK) { |
dfefe02b | 776 | dev->stats.tx_errors++; |
4689ced9 PC |
777 | if (tdes0 & 0x0002) { /* UnderRun */ |
778 | db->tx_fifo_underrun++; | |
779 | if ( !(db->cr6_data & CR6_SFT) ) { | |
780 | db->cr6_data = db->cr6_data | CR6_SFT; | |
781 | update_cr6(db->cr6_data, db->ioaddr); | |
782 | } | |
783 | } | |
784 | if (tdes0 & 0x0100) | |
785 | db->tx_excessive_collision++; | |
786 | if (tdes0 & 0x0200) | |
787 | db->tx_late_collision++; | |
788 | if (tdes0 & 0x0400) | |
789 | db->tx_no_carrier++; | |
790 | if (tdes0 & 0x0800) | |
791 | db->tx_loss_carrier++; | |
792 | if (tdes0 & 0x4000) | |
793 | db->tx_jabber_timeout++; | |
794 | } | |
795 | } | |
796 | ||
797 | txptr = txptr->next_tx_desc; | |
798 | }/* End of while */ | |
799 | ||
800 | /* Update TX remove pointer to next */ | |
801 | db->tx_remove_ptr = txptr; | |
802 | ||
803 | /* Resource available check */ | |
804 | if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT ) | |
805 | netif_wake_queue(dev); /* Active upper layer, send again */ | |
806 | } | |
807 | ||
808 | ||
809 | /* | |
810 | * Receive the come packet and pass to upper layer | |
811 | */ | |
812 | ||
945a7876 | 813 | static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db) |
4689ced9 PC |
814 | { |
815 | struct rx_desc *rxptr; | |
816 | struct sk_buff *skb; | |
817 | int rxlen; | |
818 | u32 rdes0; | |
f3b197ac | 819 | |
4689ced9 PC |
820 | rxptr = db->rx_ready_ptr; |
821 | ||
822 | while(db->rx_avail_cnt) { | |
823 | rdes0 = le32_to_cpu(rxptr->rdes0); | |
824 | if (rdes0 & 0x80000000) /* packet owner check */ | |
825 | { | |
826 | break; | |
827 | } | |
828 | ||
829 | db->rx_avail_cnt--; | |
830 | db->interval_rx_cnt++; | |
831 | ||
832 | pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
833 | if ( (rdes0 & 0x300) != 0x300) { | |
834 | /* A packet without First/Last flag */ | |
835 | /* reuse this SKB */ | |
836 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | |
837 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | |
838 | } else { | |
839 | /* A packet with First/Last flag */ | |
840 | rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; | |
841 | ||
842 | /* error summary bit check */ | |
843 | if (rdes0 & 0x8000) { | |
844 | /* This is a error packet */ | |
dfefe02b | 845 | dev->stats.rx_errors++; |
4689ced9 | 846 | if (rdes0 & 1) |
dfefe02b | 847 | dev->stats.rx_fifo_errors++; |
4689ced9 | 848 | if (rdes0 & 2) |
dfefe02b | 849 | dev->stats.rx_crc_errors++; |
4689ced9 | 850 | if (rdes0 & 0x80) |
dfefe02b | 851 | dev->stats.rx_length_errors++; |
4689ced9 PC |
852 | } |
853 | ||
854 | if ( !(rdes0 & 0x8000) || | |
855 | ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { | |
ac90a149 KM |
856 | struct sk_buff *new_skb = NULL; |
857 | ||
4689ced9 | 858 | skb = rxptr->rx_skb_ptr; |
f3b197ac | 859 | |
4689ced9 PC |
860 | /* Good packet, send to upper layer */ |
861 | /* Shorst packet used new SKB */ | |
ac90a149 | 862 | if ((rxlen < RX_COPY_SIZE) && |
1ab0d2ec | 863 | (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) { |
ac90a149 | 864 | skb = new_skb; |
4689ced9 | 865 | /* size less than COPY_SIZE, allocate a rxlen SKB */ |
4689ced9 | 866 | skb_reserve(skb, 2); /* 16byte align */ |
27a884dc ACM |
867 | memcpy(skb_put(skb, rxlen), |
868 | skb_tail_pointer(rxptr->rx_skb_ptr), | |
869 | rxlen); | |
4689ced9 | 870 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); |
4c13eb66 | 871 | } else |
4689ced9 | 872 | skb_put(skb, rxlen); |
4c13eb66 | 873 | |
4689ced9 PC |
874 | skb->protocol = eth_type_trans(skb, dev); |
875 | netif_rx(skb); | |
dfefe02b SH |
876 | dev->stats.rx_packets++; |
877 | dev->stats.rx_bytes += rxlen; | |
f3b197ac | 878 | |
4689ced9 PC |
879 | } else { |
880 | /* Reuse SKB buffer when the packet is error */ | |
881 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | |
882 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | |
883 | } | |
884 | } | |
885 | ||
886 | rxptr = rxptr->next_rx_desc; | |
887 | } | |
888 | ||
889 | db->rx_ready_ptr = rxptr; | |
890 | } | |
891 | ||
892 | ||
4689ced9 PC |
893 | /* |
894 | * Set ULI526X multicast address | |
895 | */ | |
896 | ||
945a7876 | 897 | static void uli526x_set_filter_mode(struct net_device * dev) |
4689ced9 | 898 | { |
8f15ea42 | 899 | struct uli526x_board_info *db = netdev_priv(dev); |
4689ced9 PC |
900 | unsigned long flags; |
901 | ||
902 | ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); | |
903 | spin_lock_irqsave(&db->lock, flags); | |
904 | ||
905 | if (dev->flags & IFF_PROMISC) { | |
906 | ULI526X_DBUG(0, "Enable PROM Mode", 0); | |
907 | db->cr6_data |= CR6_PM | CR6_PBF; | |
908 | update_cr6(db->cr6_data, db->ioaddr); | |
909 | spin_unlock_irqrestore(&db->lock, flags); | |
910 | return; | |
911 | } | |
912 | ||
4cd24eaf JP |
913 | if (dev->flags & IFF_ALLMULTI || |
914 | netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) { | |
915 | ULI526X_DBUG(0, "Pass all multicast address", | |
916 | netdev_mc_count(dev)); | |
4689ced9 PC |
917 | db->cr6_data &= ~(CR6_PM | CR6_PBF); |
918 | db->cr6_data |= CR6_PAM; | |
919 | spin_unlock_irqrestore(&db->lock, flags); | |
920 | return; | |
921 | } | |
922 | ||
4cd24eaf JP |
923 | ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev)); |
924 | send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */ | |
4689ced9 PC |
925 | spin_unlock_irqrestore(&db->lock, flags); |
926 | } | |
927 | ||
928 | static void | |
929 | ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd) | |
930 | { | |
945a7876 PC |
931 | ecmd->supported = (SUPPORTED_10baseT_Half | |
932 | SUPPORTED_10baseT_Full | | |
933 | SUPPORTED_100baseT_Half | | |
934 | SUPPORTED_100baseT_Full | | |
935 | SUPPORTED_Autoneg | | |
936 | SUPPORTED_MII); | |
f3b197ac | 937 | |
945a7876 PC |
938 | ecmd->advertising = (ADVERTISED_10baseT_Half | |
939 | ADVERTISED_10baseT_Full | | |
940 | ADVERTISED_100baseT_Half | | |
941 | ADVERTISED_100baseT_Full | | |
942 | ADVERTISED_Autoneg | | |
943 | ADVERTISED_MII); | |
4689ced9 PC |
944 | |
945 | ||
945a7876 PC |
946 | ecmd->port = PORT_MII; |
947 | ecmd->phy_address = db->phy_addr; | |
4689ced9 | 948 | |
945a7876 | 949 | ecmd->transceiver = XCVR_EXTERNAL; |
f3b197ac | 950 | |
70739497 | 951 | ethtool_cmd_speed_set(ecmd, SPEED_10); |
4689ced9 | 952 | ecmd->duplex = DUPLEX_HALF; |
f3b197ac | 953 | |
4689ced9 PC |
954 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) |
955 | { | |
70739497 | 956 | ethtool_cmd_speed_set(ecmd, SPEED_100); |
4689ced9 PC |
957 | } |
958 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | |
959 | { | |
960 | ecmd->duplex = DUPLEX_FULL; | |
961 | } | |
962 | if(db->link_failed) | |
963 | { | |
537fae01 JP |
964 | ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); |
965 | ecmd->duplex = DUPLEX_UNKNOWN; | |
4689ced9 | 966 | } |
f3b197ac | 967 | |
4689ced9 | 968 | if (db->media_mode & ULI526X_AUTO) |
f3b197ac | 969 | { |
4689ced9 PC |
970 | ecmd->autoneg = AUTONEG_ENABLE; |
971 | } | |
4689ced9 PC |
972 | } |
973 | ||
974 | static void netdev_get_drvinfo(struct net_device *dev, | |
975 | struct ethtool_drvinfo *info) | |
976 | { | |
977 | struct uli526x_board_info *np = netdev_priv(dev); | |
978 | ||
68aad78c RJ |
979 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
980 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
3acf4b5c | 981 | strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); |
4689ced9 PC |
982 | } |
983 | ||
984 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { | |
985 | struct uli526x_board_info *np = netdev_priv(dev); | |
f3b197ac | 986 | |
4689ced9 | 987 | ULi_ethtool_gset(np, cmd); |
f3b197ac | 988 | |
4689ced9 PC |
989 | return 0; |
990 | } | |
991 | ||
992 | static u32 netdev_get_link(struct net_device *dev) { | |
993 | struct uli526x_board_info *np = netdev_priv(dev); | |
f3b197ac | 994 | |
4689ced9 PC |
995 | if(np->link_failed) |
996 | return 0; | |
997 | else | |
998 | return 1; | |
999 | } | |
1000 | ||
1001 | static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1002 | { | |
1003 | wol->supported = WAKE_PHY | WAKE_MAGIC; | |
1004 | wol->wolopts = 0; | |
1005 | } | |
1006 | ||
7282d491 | 1007 | static const struct ethtool_ops netdev_ethtool_ops = { |
4689ced9 PC |
1008 | .get_drvinfo = netdev_get_drvinfo, |
1009 | .get_settings = netdev_get_settings, | |
1010 | .get_link = netdev_get_link, | |
1011 | .get_wol = uli526x_get_wol, | |
1012 | }; | |
1013 | ||
1014 | /* | |
1015 | * A periodic timer routine | |
1016 | * Dynamic media sense, allocate Rx buffer... | |
1017 | */ | |
1018 | ||
1019 | static void uli526x_timer(unsigned long data) | |
1020 | { | |
945a7876 | 1021 | struct net_device *dev = (struct net_device *) data; |
4689ced9 | 1022 | struct uli526x_board_info *db = netdev_priv(dev); |
3acf4b5c FR |
1023 | struct uli_phy_ops *phy = &db->phy; |
1024 | void __iomem *ioaddr = db->ioaddr; | |
4689ced9 | 1025 | unsigned long flags; |
3acf4b5c FR |
1026 | u8 tmp_cr12 = 0; |
1027 | u32 tmp_cr8; | |
f3b197ac | 1028 | |
4689ced9 PC |
1029 | //ULI526X_DBUG(0, "uli526x_timer()", 0); |
1030 | spin_lock_irqsave(&db->lock, flags); | |
1031 | ||
f3b197ac | 1032 | |
4689ced9 | 1033 | /* Dynamic reset ULI526X : system error or transmit time-out */ |
3acf4b5c | 1034 | tmp_cr8 = ur32(DCR8); |
4689ced9 PC |
1035 | if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { |
1036 | db->reset_cr8++; | |
1037 | db->wait_reset = 1; | |
1038 | } | |
1039 | db->interval_rx_cnt = 0; | |
1040 | ||
1041 | /* TX polling kick monitor */ | |
1042 | if ( db->tx_packet_cnt && | |
1ae5dc34 | 1043 | time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) { |
3acf4b5c | 1044 | uw32(DCR1, 0x1); // Tx polling again |
4689ced9 | 1045 | |
f3b197ac | 1046 | // TX Timeout |
1ae5dc34 | 1047 | if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) { |
4689ced9 PC |
1048 | db->reset_TXtimeout++; |
1049 | db->wait_reset = 1; | |
1c3319fb | 1050 | netdev_err(dev, " Tx timeout - resetting\n"); |
4689ced9 PC |
1051 | } |
1052 | } | |
1053 | ||
1054 | if (db->wait_reset) { | |
1055 | ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); | |
1056 | db->reset_count++; | |
1057 | uli526x_dynamic_reset(dev); | |
1058 | db->timer.expires = ULI526X_TIMER_WUT; | |
1059 | add_timer(&db->timer); | |
1060 | spin_unlock_irqrestore(&db->lock, flags); | |
1061 | return; | |
1062 | } | |
1063 | ||
1064 | /* Link status check, Dynamic media type change */ | |
3acf4b5c | 1065 | if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0) |
4689ced9 PC |
1066 | tmp_cr12 = 3; |
1067 | ||
1068 | if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { | |
1069 | /* Link Failed */ | |
1070 | ULI526X_DBUG(0, "Link Failed", tmp_cr12); | |
1071 | netif_carrier_off(dev); | |
163ef0b5 | 1072 | netdev_info(dev, "NIC Link is Down\n"); |
4689ced9 PC |
1073 | db->link_failed = 1; |
1074 | ||
1075 | /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ | |
1076 | /* AUTO don't need */ | |
1077 | if ( !(db->media_mode & 0x8) ) | |
3acf4b5c | 1078 | phy->write(db, db->phy_addr, 0, 0x1000); |
4689ced9 PC |
1079 | |
1080 | /* AUTO mode, if INT phyxcer link failed, select EXT device */ | |
1081 | if (db->media_mode & ULI526X_AUTO) { | |
1082 | db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ | |
1083 | update_cr6(db->cr6_data, db->ioaddr); | |
1084 | } | |
1085 | } else | |
1086 | if ((tmp_cr12 & 0x3) && db->link_failed) { | |
1087 | ULI526X_DBUG(0, "Link link OK", tmp_cr12); | |
1088 | db->link_failed = 0; | |
1089 | ||
1090 | /* Auto Sense Speed */ | |
1091 | if ( (db->media_mode & ULI526X_AUTO) && | |
1092 | uli526x_sense_speed(db) ) | |
1093 | db->link_failed = 1; | |
1094 | uli526x_process_mode(db); | |
f3b197ac | 1095 | |
4689ced9 PC |
1096 | if(db->link_failed==0) |
1097 | { | |
163ef0b5 JP |
1098 | netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n", |
1099 | (db->op_mode == ULI526X_100MHF || | |
1100 | db->op_mode == ULI526X_100MFD) | |
1101 | ? 100 : 10, | |
1102 | (db->op_mode == ULI526X_10MFD || | |
1103 | db->op_mode == ULI526X_100MFD) | |
1104 | ? "Full" : "Half"); | |
4689ced9 PC |
1105 | netif_carrier_on(dev); |
1106 | } | |
1107 | /* SHOW_MEDIA_TYPE(db->op_mode); */ | |
1108 | } | |
1109 | else if(!(tmp_cr12 & 0x3) && db->link_failed) | |
1110 | { | |
1111 | if(db->init==1) | |
1112 | { | |
163ef0b5 | 1113 | netdev_info(dev, "NIC Link is Down\n"); |
4689ced9 PC |
1114 | netif_carrier_off(dev); |
1115 | } | |
1116 | } | |
e1395a32 | 1117 | db->init = 0; |
4689ced9 PC |
1118 | |
1119 | /* Timer active again */ | |
1120 | db->timer.expires = ULI526X_TIMER_WUT; | |
1121 | add_timer(&db->timer); | |
1122 | spin_unlock_irqrestore(&db->lock, flags); | |
1123 | } | |
1124 | ||
1125 | ||
1126 | /* | |
4689ced9 PC |
1127 | * Stop ULI526X board |
1128 | * Free Tx/Rx allocated memory | |
b6aec32a | 1129 | * Init system variable |
4689ced9 PC |
1130 | */ |
1131 | ||
b6aec32a | 1132 | static void uli526x_reset_prepare(struct net_device *dev) |
4689ced9 PC |
1133 | { |
1134 | struct uli526x_board_info *db = netdev_priv(dev); | |
3acf4b5c | 1135 | void __iomem *ioaddr = db->ioaddr; |
4689ced9 | 1136 | |
4689ced9 PC |
1137 | /* Sopt MAC controller */ |
1138 | db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ | |
3acf4b5c FR |
1139 | update_cr6(db->cr6_data, ioaddr); |
1140 | uw32(DCR7, 0); /* Disable Interrupt */ | |
1141 | uw32(DCR5, ur32(DCR5)); | |
4689ced9 PC |
1142 | |
1143 | /* Disable upper layer interface */ | |
1144 | netif_stop_queue(dev); | |
1145 | ||
1146 | /* Free Rx Allocate buffer */ | |
1147 | uli526x_free_rxbuffer(db); | |
1148 | ||
1149 | /* system variable init */ | |
1150 | db->tx_packet_cnt = 0; | |
1151 | db->rx_avail_cnt = 0; | |
1152 | db->link_failed = 1; | |
1153 | db->init=1; | |
1154 | db->wait_reset = 0; | |
b6aec32a RW |
1155 | } |
1156 | ||
1157 | ||
1158 | /* | |
1159 | * Dynamic reset the ULI526X board | |
1160 | * Stop ULI526X board | |
1161 | * Free Tx/Rx allocated memory | |
1162 | * Reset ULI526X board | |
1163 | * Re-initialize ULI526X board | |
1164 | */ | |
1165 | ||
1166 | static void uli526x_dynamic_reset(struct net_device *dev) | |
1167 | { | |
1168 | ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); | |
1169 | ||
1170 | uli526x_reset_prepare(dev); | |
4689ced9 | 1171 | |
945a7876 | 1172 | /* Re-initialize ULI526X board */ |
4689ced9 PC |
1173 | uli526x_init(dev); |
1174 | ||
1175 | /* Restart upper layer interface */ | |
1176 | netif_wake_queue(dev); | |
1177 | } | |
1178 | ||
1179 | ||
b6aec32a RW |
1180 | #ifdef CONFIG_PM |
1181 | ||
1182 | /* | |
1183 | * Suspend the interface. | |
1184 | */ | |
1185 | ||
1186 | static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state) | |
1187 | { | |
1188 | struct net_device *dev = pci_get_drvdata(pdev); | |
1189 | pci_power_t power_state; | |
1190 | int err; | |
1191 | ||
1192 | ULI526X_DBUG(0, "uli526x_suspend", 0); | |
1193 | ||
b6aec32a RW |
1194 | pci_save_state(pdev); |
1195 | ||
1196 | if (!netif_running(dev)) | |
1197 | return 0; | |
1198 | ||
1199 | netif_device_detach(dev); | |
1200 | uli526x_reset_prepare(dev); | |
1201 | ||
1202 | power_state = pci_choose_state(pdev, state); | |
1203 | pci_enable_wake(pdev, power_state, 0); | |
1204 | err = pci_set_power_state(pdev, power_state); | |
1205 | if (err) { | |
1206 | netif_device_attach(dev); | |
1207 | /* Re-initialize ULI526X board */ | |
1208 | uli526x_init(dev); | |
1209 | /* Restart upper layer interface */ | |
1210 | netif_wake_queue(dev); | |
1211 | } | |
1212 | ||
1213 | return err; | |
1214 | } | |
1215 | ||
1216 | /* | |
1217 | * Resume the interface. | |
1218 | */ | |
1219 | ||
1220 | static int uli526x_resume(struct pci_dev *pdev) | |
1221 | { | |
1222 | struct net_device *dev = pci_get_drvdata(pdev); | |
1223 | int err; | |
1224 | ||
1225 | ULI526X_DBUG(0, "uli526x_resume", 0); | |
1226 | ||
b6aec32a RW |
1227 | pci_restore_state(pdev); |
1228 | ||
1229 | if (!netif_running(dev)) | |
1230 | return 0; | |
1231 | ||
1232 | err = pci_set_power_state(pdev, PCI_D0); | |
1233 | if (err) { | |
163ef0b5 | 1234 | netdev_warn(dev, "Could not put device into D0\n"); |
b6aec32a RW |
1235 | return err; |
1236 | } | |
1237 | ||
1238 | netif_device_attach(dev); | |
1239 | /* Re-initialize ULI526X board */ | |
1240 | uli526x_init(dev); | |
1241 | /* Restart upper layer interface */ | |
1242 | netif_wake_queue(dev); | |
1243 | ||
1244 | return 0; | |
1245 | } | |
1246 | ||
1247 | #else /* !CONFIG_PM */ | |
1248 | ||
1249 | #define uli526x_suspend NULL | |
1250 | #define uli526x_resume NULL | |
1251 | ||
1252 | #endif /* !CONFIG_PM */ | |
1253 | ||
1254 | ||
4689ced9 PC |
1255 | /* |
1256 | * free all allocated rx buffer | |
1257 | */ | |
1258 | ||
1259 | static void uli526x_free_rxbuffer(struct uli526x_board_info * db) | |
1260 | { | |
1261 | ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); | |
1262 | ||
1263 | /* free allocated rx buffer */ | |
1264 | while (db->rx_avail_cnt) { | |
1265 | dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); | |
1266 | db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; | |
1267 | db->rx_avail_cnt--; | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | ||
1272 | /* | |
1273 | * Reuse the SK buffer | |
1274 | */ | |
1275 | ||
1276 | static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb) | |
1277 | { | |
1278 | struct rx_desc *rxptr = db->rx_insert_ptr; | |
1279 | ||
1280 | if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { | |
1281 | rxptr->rx_skb_ptr = skb; | |
27a884dc ACM |
1282 | rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, |
1283 | skb_tail_pointer(skb), | |
1284 | RX_ALLOC_SIZE, | |
1285 | PCI_DMA_FROMDEVICE)); | |
4689ced9 PC |
1286 | wmb(); |
1287 | rxptr->rdes0 = cpu_to_le32(0x80000000); | |
1288 | db->rx_avail_cnt++; | |
1289 | db->rx_insert_ptr = rxptr->next_rx_desc; | |
1290 | } else | |
1291 | ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); | |
1292 | } | |
1293 | ||
1294 | ||
1295 | /* | |
1296 | * Initialize transmit/Receive descriptor | |
1297 | * Using Chain structure, and allocate Tx/Rx buffer | |
1298 | */ | |
1299 | ||
3acf4b5c | 1300 | static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr) |
4689ced9 | 1301 | { |
1ab0d2ec | 1302 | struct uli526x_board_info *db = netdev_priv(dev); |
4689ced9 PC |
1303 | struct tx_desc *tmp_tx; |
1304 | struct rx_desc *tmp_rx; | |
1305 | unsigned char *tmp_buf; | |
1306 | dma_addr_t tmp_tx_dma, tmp_rx_dma; | |
1307 | dma_addr_t tmp_buf_dma; | |
1308 | int i; | |
1309 | ||
1310 | ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); | |
1311 | ||
1312 | /* tx descriptor start pointer */ | |
1313 | db->tx_insert_ptr = db->first_tx_desc; | |
1314 | db->tx_remove_ptr = db->first_tx_desc; | |
3acf4b5c | 1315 | uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */ |
4689ced9 PC |
1316 | |
1317 | /* rx descriptor start pointer */ | |
1318 | db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; | |
1319 | db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; | |
1320 | db->rx_insert_ptr = db->first_rx_desc; | |
1321 | db->rx_ready_ptr = db->first_rx_desc; | |
3acf4b5c | 1322 | uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */ |
4689ced9 PC |
1323 | |
1324 | /* Init Transmit chain */ | |
1325 | tmp_buf = db->buf_pool_start; | |
1326 | tmp_buf_dma = db->buf_pool_dma_start; | |
1327 | tmp_tx_dma = db->first_tx_desc_dma; | |
1328 | for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { | |
1329 | tmp_tx->tx_buf_ptr = tmp_buf; | |
1330 | tmp_tx->tdes0 = cpu_to_le32(0); | |
1331 | tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ | |
1332 | tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); | |
1333 | tmp_tx_dma += sizeof(struct tx_desc); | |
1334 | tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); | |
1335 | tmp_tx->next_tx_desc = tmp_tx + 1; | |
1336 | tmp_buf = tmp_buf + TX_BUF_ALLOC; | |
1337 | tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; | |
1338 | } | |
1339 | (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); | |
1340 | tmp_tx->next_tx_desc = db->first_tx_desc; | |
1341 | ||
1342 | /* Init Receive descriptor chain */ | |
1343 | tmp_rx_dma=db->first_rx_desc_dma; | |
1344 | for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { | |
1345 | tmp_rx->rdes0 = cpu_to_le32(0); | |
1346 | tmp_rx->rdes1 = cpu_to_le32(0x01000600); | |
1347 | tmp_rx_dma += sizeof(struct rx_desc); | |
1348 | tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); | |
1349 | tmp_rx->next_rx_desc = tmp_rx + 1; | |
1350 | } | |
1351 | (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); | |
1352 | tmp_rx->next_rx_desc = db->first_rx_desc; | |
1353 | ||
1354 | /* pre-allocate Rx buffer */ | |
1ab0d2ec | 1355 | allocate_rx_buffer(dev); |
4689ced9 PC |
1356 | } |
1357 | ||
1358 | ||
1359 | /* | |
1360 | * Update CR6 value | |
945a7876 | 1361 | * Firstly stop ULI526X, then written value and start |
4689ced9 | 1362 | */ |
3acf4b5c | 1363 | static void update_cr6(u32 cr6_data, void __iomem *ioaddr) |
4689ced9 | 1364 | { |
3acf4b5c | 1365 | uw32(DCR6, cr6_data); |
4689ced9 PC |
1366 | udelay(5); |
1367 | } | |
1368 | ||
1369 | ||
1370 | /* | |
1371 | * Send a setup frame for M5261/M5263 | |
945a7876 | 1372 | * This setup frame initialize ULI526X address filter mode |
4689ced9 PC |
1373 | */ |
1374 | ||
e284e5c6 AV |
1375 | #ifdef __BIG_ENDIAN |
1376 | #define FLT_SHIFT 16 | |
1377 | #else | |
1378 | #define FLT_SHIFT 0 | |
1379 | #endif | |
1380 | ||
945a7876 | 1381 | static void send_filter_frame(struct net_device *dev, int mc_cnt) |
4689ced9 PC |
1382 | { |
1383 | struct uli526x_board_info *db = netdev_priv(dev); | |
3acf4b5c | 1384 | void __iomem *ioaddr = db->ioaddr; |
22bedad3 | 1385 | struct netdev_hw_addr *ha; |
4689ced9 PC |
1386 | struct tx_desc *txptr; |
1387 | u16 * addrptr; | |
1388 | u32 * suptr; | |
1389 | int i; | |
1390 | ||
1391 | ULI526X_DBUG(0, "send_filter_frame()", 0); | |
1392 | ||
1393 | txptr = db->tx_insert_ptr; | |
1394 | suptr = (u32 *) txptr->tx_buf_ptr; | |
1395 | ||
1396 | /* Node address */ | |
1397 | addrptr = (u16 *) dev->dev_addr; | |
e284e5c6 AV |
1398 | *suptr++ = addrptr[0] << FLT_SHIFT; |
1399 | *suptr++ = addrptr[1] << FLT_SHIFT; | |
1400 | *suptr++ = addrptr[2] << FLT_SHIFT; | |
4689ced9 PC |
1401 | |
1402 | /* broadcast address */ | |
e284e5c6 AV |
1403 | *suptr++ = 0xffff << FLT_SHIFT; |
1404 | *suptr++ = 0xffff << FLT_SHIFT; | |
1405 | *suptr++ = 0xffff << FLT_SHIFT; | |
4689ced9 PC |
1406 | |
1407 | /* fit the multicast address */ | |
22bedad3 JP |
1408 | netdev_for_each_mc_addr(ha, dev) { |
1409 | addrptr = (u16 *) ha->addr; | |
e284e5c6 AV |
1410 | *suptr++ = addrptr[0] << FLT_SHIFT; |
1411 | *suptr++ = addrptr[1] << FLT_SHIFT; | |
1412 | *suptr++ = addrptr[2] << FLT_SHIFT; | |
4689ced9 PC |
1413 | } |
1414 | ||
4302b67e | 1415 | for (i = netdev_mc_count(dev); i < 14; i++) { |
e284e5c6 AV |
1416 | *suptr++ = 0xffff << FLT_SHIFT; |
1417 | *suptr++ = 0xffff << FLT_SHIFT; | |
1418 | *suptr++ = 0xffff << FLT_SHIFT; | |
4689ced9 PC |
1419 | } |
1420 | ||
1421 | /* prepare the setup frame */ | |
1422 | db->tx_insert_ptr = txptr->next_tx_desc; | |
1423 | txptr->tdes1 = cpu_to_le32(0x890000c0); | |
1424 | ||
1425 | /* Resource Check and Send the setup packet */ | |
1426 | if (db->tx_packet_cnt < TX_DESC_CNT) { | |
1427 | /* Resource Empty */ | |
1428 | db->tx_packet_cnt++; | |
1429 | txptr->tdes0 = cpu_to_le32(0x80000000); | |
3acf4b5c FR |
1430 | update_cr6(db->cr6_data | 0x2000, ioaddr); |
1431 | uw32(DCR1, 0x1); /* Issue Tx polling */ | |
1432 | update_cr6(db->cr6_data, ioaddr); | |
860e9538 | 1433 | netif_trans_update(dev); |
4689ced9 | 1434 | } else |
163ef0b5 | 1435 | netdev_err(dev, "No Tx resource - Send_filter_frame!\n"); |
4689ced9 PC |
1436 | } |
1437 | ||
1438 | ||
1439 | /* | |
1440 | * Allocate rx buffer, | |
1441 | * As possible as allocate maxiumn Rx buffer | |
1442 | */ | |
1443 | ||
1ab0d2ec | 1444 | static void allocate_rx_buffer(struct net_device *dev) |
4689ced9 | 1445 | { |
1ab0d2ec | 1446 | struct uli526x_board_info *db = netdev_priv(dev); |
4689ced9 PC |
1447 | struct rx_desc *rxptr; |
1448 | struct sk_buff *skb; | |
1449 | ||
1450 | rxptr = db->rx_insert_ptr; | |
1451 | ||
1452 | while(db->rx_avail_cnt < RX_DESC_CNT) { | |
1ab0d2ec PD |
1453 | skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE); |
1454 | if (skb == NULL) | |
4689ced9 PC |
1455 | break; |
1456 | rxptr->rx_skb_ptr = skb; /* FIXME (?) */ | |
27a884dc ACM |
1457 | rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, |
1458 | skb_tail_pointer(skb), | |
1459 | RX_ALLOC_SIZE, | |
1460 | PCI_DMA_FROMDEVICE)); | |
4689ced9 PC |
1461 | wmb(); |
1462 | rxptr->rdes0 = cpu_to_le32(0x80000000); | |
1463 | rxptr = rxptr->next_rx_desc; | |
1464 | db->rx_avail_cnt++; | |
1465 | } | |
1466 | ||
1467 | db->rx_insert_ptr = rxptr; | |
1468 | } | |
1469 | ||
1470 | ||
1471 | /* | |
1472 | * Read one word data from the serial ROM | |
1473 | */ | |
1474 | ||
3acf4b5c | 1475 | static u16 read_srom_word(struct uli526x_board_info *db, int offset) |
4689ced9 | 1476 | { |
3acf4b5c | 1477 | void __iomem *ioaddr = db->ioaddr; |
4689ced9 | 1478 | u16 srom_data = 0; |
3acf4b5c | 1479 | int i; |
4689ced9 | 1480 | |
3acf4b5c FR |
1481 | uw32(DCR9, CR9_SROM_READ); |
1482 | uw32(DCR9, CR9_SROM_READ | CR9_SRCS); | |
4689ced9 PC |
1483 | |
1484 | /* Send the Read Command 110b */ | |
3acf4b5c FR |
1485 | srom_clk_write(db, SROM_DATA_1); |
1486 | srom_clk_write(db, SROM_DATA_1); | |
1487 | srom_clk_write(db, SROM_DATA_0); | |
4689ced9 PC |
1488 | |
1489 | /* Send the offset */ | |
1490 | for (i = 5; i >= 0; i--) { | |
1491 | srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; | |
3acf4b5c | 1492 | srom_clk_write(db, srom_data); |
4689ced9 PC |
1493 | } |
1494 | ||
3acf4b5c | 1495 | uw32(DCR9, CR9_SROM_READ | CR9_SRCS); |
4689ced9 PC |
1496 | |
1497 | for (i = 16; i > 0; i--) { | |
3acf4b5c | 1498 | uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK); |
4689ced9 | 1499 | udelay(5); |
3acf4b5c FR |
1500 | srom_data = (srom_data << 1) | |
1501 | ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0); | |
1502 | uw32(DCR9, CR9_SROM_READ | CR9_SRCS); | |
4689ced9 PC |
1503 | udelay(5); |
1504 | } | |
1505 | ||
3acf4b5c | 1506 | uw32(DCR9, CR9_SROM_READ); |
4689ced9 PC |
1507 | return srom_data; |
1508 | } | |
1509 | ||
1510 | ||
1511 | /* | |
1512 | * Auto sense the media mode | |
1513 | */ | |
1514 | ||
1515 | static u8 uli526x_sense_speed(struct uli526x_board_info * db) | |
1516 | { | |
3acf4b5c | 1517 | struct uli_phy_ops *phy = &db->phy; |
4689ced9 PC |
1518 | u8 ErrFlag = 0; |
1519 | u16 phy_mode; | |
1520 | ||
3acf4b5c FR |
1521 | phy_mode = phy->read(db, db->phy_addr, 1); |
1522 | phy_mode = phy->read(db, db->phy_addr, 1); | |
4689ced9 PC |
1523 | |
1524 | if ( (phy_mode & 0x24) == 0x24 ) { | |
f3b197ac | 1525 | |
3acf4b5c | 1526 | phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7); |
4689ced9 PC |
1527 | if(phy_mode&0x8000) |
1528 | phy_mode = 0x8000; | |
1529 | else if(phy_mode&0x4000) | |
1530 | phy_mode = 0x4000; | |
1531 | else if(phy_mode&0x2000) | |
1532 | phy_mode = 0x2000; | |
1533 | else | |
1534 | phy_mode = 0x1000; | |
f3b197ac | 1535 | |
4689ced9 PC |
1536 | switch (phy_mode) { |
1537 | case 0x1000: db->op_mode = ULI526X_10MHF; break; | |
1538 | case 0x2000: db->op_mode = ULI526X_10MFD; break; | |
1539 | case 0x4000: db->op_mode = ULI526X_100MHF; break; | |
1540 | case 0x8000: db->op_mode = ULI526X_100MFD; break; | |
1541 | default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break; | |
1542 | } | |
1543 | } else { | |
1544 | db->op_mode = ULI526X_10MHF; | |
1545 | ULI526X_DBUG(0, "Link Failed :", phy_mode); | |
1546 | ErrFlag = 1; | |
1547 | } | |
1548 | ||
1549 | return ErrFlag; | |
1550 | } | |
1551 | ||
1552 | ||
1553 | /* | |
1554 | * Set 10/100 phyxcer capability | |
1555 | * AUTO mode : phyxcer register4 is NIC capability | |
1556 | * Force mode: phyxcer register4 is the force media | |
1557 | */ | |
1558 | ||
1559 | static void uli526x_set_phyxcer(struct uli526x_board_info *db) | |
1560 | { | |
3acf4b5c | 1561 | struct uli_phy_ops *phy = &db->phy; |
4689ced9 | 1562 | u16 phy_reg; |
f3b197ac | 1563 | |
4689ced9 | 1564 | /* Phyxcer capability setting */ |
3acf4b5c | 1565 | phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0; |
4689ced9 PC |
1566 | |
1567 | if (db->media_mode & ULI526X_AUTO) { | |
1568 | /* AUTO Mode */ | |
1569 | phy_reg |= db->PHY_reg4; | |
1570 | } else { | |
1571 | /* Force Mode */ | |
1572 | switch(db->media_mode) { | |
1573 | case ULI526X_10MHF: phy_reg |= 0x20; break; | |
1574 | case ULI526X_10MFD: phy_reg |= 0x40; break; | |
1575 | case ULI526X_100MHF: phy_reg |= 0x80; break; | |
1576 | case ULI526X_100MFD: phy_reg |= 0x100; break; | |
1577 | } | |
f3b197ac | 1578 | |
4689ced9 PC |
1579 | } |
1580 | ||
1581 | /* Write new capability to Phyxcer Reg4 */ | |
1582 | if ( !(phy_reg & 0x01e0)) { | |
1583 | phy_reg|=db->PHY_reg4; | |
1584 | db->media_mode|=ULI526X_AUTO; | |
1585 | } | |
3acf4b5c | 1586 | phy->write(db, db->phy_addr, 4, phy_reg); |
4689ced9 PC |
1587 | |
1588 | /* Restart Auto-Negotiation */ | |
3acf4b5c | 1589 | phy->write(db, db->phy_addr, 0, 0x1200); |
4689ced9 PC |
1590 | udelay(50); |
1591 | } | |
1592 | ||
1593 | ||
1594 | /* | |
1595 | * Process op-mode | |
1596 | AUTO mode : PHY controller in Auto-negotiation Mode | |
1597 | * Force mode: PHY controller in force mode with HUB | |
1598 | * N-way force capability with SWITCH | |
1599 | */ | |
1600 | ||
1601 | static void uli526x_process_mode(struct uli526x_board_info *db) | |
1602 | { | |
3acf4b5c | 1603 | struct uli_phy_ops *phy = &db->phy; |
4689ced9 PC |
1604 | u16 phy_reg; |
1605 | ||
1606 | /* Full Duplex Mode Check */ | |
1607 | if (db->op_mode & 0x4) | |
1608 | db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ | |
1609 | else | |
1610 | db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ | |
1611 | ||
1612 | update_cr6(db->cr6_data, db->ioaddr); | |
1613 | ||
1614 | /* 10/100M phyxcer force mode need */ | |
3acf4b5c | 1615 | if (!(db->media_mode & 0x8)) { |
4689ced9 | 1616 | /* Forece Mode */ |
3acf4b5c FR |
1617 | phy_reg = phy->read(db, db->phy_addr, 6); |
1618 | if (!(phy_reg & 0x1)) { | |
4689ced9 PC |
1619 | /* parter without N-Way capability */ |
1620 | phy_reg = 0x0; | |
1621 | switch(db->op_mode) { | |
1622 | case ULI526X_10MHF: phy_reg = 0x0; break; | |
1623 | case ULI526X_10MFD: phy_reg = 0x100; break; | |
1624 | case ULI526X_100MHF: phy_reg = 0x2000; break; | |
1625 | case ULI526X_100MFD: phy_reg = 0x2100; break; | |
1626 | } | |
3acf4b5c | 1627 | phy->write(db, db->phy_addr, 0, phy_reg); |
4689ced9 PC |
1628 | } |
1629 | } | |
1630 | } | |
1631 | ||
1632 | ||
3acf4b5c FR |
1633 | /* M5261/M5263 Chip */ |
1634 | static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr, | |
1635 | u8 offset, u16 phy_data) | |
4689ced9 PC |
1636 | { |
1637 | u16 i; | |
4689ced9 PC |
1638 | |
1639 | /* Send 33 synchronization clock to Phy controller */ | |
1640 | for (i = 0; i < 35; i++) | |
3acf4b5c | 1641 | phy_write_1bit(db, PHY_DATA_1); |
4689ced9 PC |
1642 | |
1643 | /* Send start command(01) to Phy */ | |
3acf4b5c FR |
1644 | phy_write_1bit(db, PHY_DATA_0); |
1645 | phy_write_1bit(db, PHY_DATA_1); | |
4689ced9 PC |
1646 | |
1647 | /* Send write command(01) to Phy */ | |
3acf4b5c FR |
1648 | phy_write_1bit(db, PHY_DATA_0); |
1649 | phy_write_1bit(db, PHY_DATA_1); | |
4689ced9 PC |
1650 | |
1651 | /* Send Phy address */ | |
1652 | for (i = 0x10; i > 0; i = i >> 1) | |
3acf4b5c | 1653 | phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); |
4689ced9 PC |
1654 | |
1655 | /* Send register address */ | |
1656 | for (i = 0x10; i > 0; i = i >> 1) | |
3acf4b5c | 1657 | phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0); |
4689ced9 PC |
1658 | |
1659 | /* written trasnition */ | |
3acf4b5c FR |
1660 | phy_write_1bit(db, PHY_DATA_1); |
1661 | phy_write_1bit(db, PHY_DATA_0); | |
4689ced9 PC |
1662 | |
1663 | /* Write a word data to PHY controller */ | |
3acf4b5c FR |
1664 | for (i = 0x8000; i > 0; i >>= 1) |
1665 | phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0); | |
4689ced9 PC |
1666 | } |
1667 | ||
3acf4b5c | 1668 | static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset) |
4689ced9 | 1669 | { |
4689ced9 | 1670 | u16 phy_data; |
3acf4b5c | 1671 | int i; |
f3b197ac | 1672 | |
4689ced9 PC |
1673 | /* Send 33 synchronization clock to Phy controller */ |
1674 | for (i = 0; i < 35; i++) | |
3acf4b5c | 1675 | phy_write_1bit(db, PHY_DATA_1); |
4689ced9 PC |
1676 | |
1677 | /* Send start command(01) to Phy */ | |
3acf4b5c FR |
1678 | phy_write_1bit(db, PHY_DATA_0); |
1679 | phy_write_1bit(db, PHY_DATA_1); | |
4689ced9 PC |
1680 | |
1681 | /* Send read command(10) to Phy */ | |
3acf4b5c FR |
1682 | phy_write_1bit(db, PHY_DATA_1); |
1683 | phy_write_1bit(db, PHY_DATA_0); | |
4689ced9 PC |
1684 | |
1685 | /* Send Phy address */ | |
1686 | for (i = 0x10; i > 0; i = i >> 1) | |
3acf4b5c | 1687 | phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); |
4689ced9 PC |
1688 | |
1689 | /* Send register address */ | |
1690 | for (i = 0x10; i > 0; i = i >> 1) | |
3acf4b5c | 1691 | phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0); |
4689ced9 PC |
1692 | |
1693 | /* Skip transition state */ | |
3acf4b5c | 1694 | phy_read_1bit(db); |
4689ced9 PC |
1695 | |
1696 | /* read 16bit data */ | |
1697 | for (phy_data = 0, i = 0; i < 16; i++) { | |
1698 | phy_data <<= 1; | |
3acf4b5c | 1699 | phy_data |= phy_read_1bit(db); |
4689ced9 PC |
1700 | } |
1701 | ||
1702 | return phy_data; | |
1703 | } | |
1704 | ||
3acf4b5c FR |
1705 | static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr, |
1706 | u8 offset) | |
4689ced9 | 1707 | { |
3acf4b5c FR |
1708 | void __iomem *ioaddr = db->ioaddr; |
1709 | u32 cr10_value = phy_addr; | |
f3b197ac | 1710 | |
3acf4b5c FR |
1711 | cr10_value = (cr10_value << 5) + offset; |
1712 | cr10_value = (cr10_value << 16) + 0x08000000; | |
1713 | uw32(DCR10, cr10_value); | |
4689ced9 | 1714 | udelay(1); |
3acf4b5c FR |
1715 | while (1) { |
1716 | cr10_value = ur32(DCR10); | |
1717 | if (cr10_value & 0x10000000) | |
4689ced9 PC |
1718 | break; |
1719 | } | |
807540ba | 1720 | return cr10_value & 0x0ffff; |
4689ced9 PC |
1721 | } |
1722 | ||
3acf4b5c FR |
1723 | static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr, |
1724 | u8 offset, u16 phy_data) | |
4689ced9 | 1725 | { |
3acf4b5c FR |
1726 | void __iomem *ioaddr = db->ioaddr; |
1727 | u32 cr10_value = phy_addr; | |
f3b197ac | 1728 | |
3acf4b5c FR |
1729 | cr10_value = (cr10_value << 5) + offset; |
1730 | cr10_value = (cr10_value << 16) + 0x04000000 + phy_data; | |
1731 | uw32(DCR10, cr10_value); | |
4689ced9 PC |
1732 | udelay(1); |
1733 | } | |
1734 | /* | |
1735 | * Write one bit data to Phy Controller | |
1736 | */ | |
1737 | ||
3acf4b5c | 1738 | static void phy_write_1bit(struct uli526x_board_info *db, u32 data) |
4689ced9 | 1739 | { |
3acf4b5c FR |
1740 | void __iomem *ioaddr = db->ioaddr; |
1741 | ||
1742 | uw32(DCR9, data); /* MII Clock Low */ | |
4689ced9 | 1743 | udelay(1); |
3acf4b5c | 1744 | uw32(DCR9, data | MDCLKH); /* MII Clock High */ |
4689ced9 | 1745 | udelay(1); |
3acf4b5c | 1746 | uw32(DCR9, data); /* MII Clock Low */ |
4689ced9 PC |
1747 | udelay(1); |
1748 | } | |
1749 | ||
1750 | ||
1751 | /* | |
1752 | * Read one bit phy data from PHY controller | |
1753 | */ | |
1754 | ||
3acf4b5c | 1755 | static u16 phy_read_1bit(struct uli526x_board_info *db) |
4689ced9 | 1756 | { |
3acf4b5c | 1757 | void __iomem *ioaddr = db->ioaddr; |
4689ced9 | 1758 | u16 phy_data; |
f3b197ac | 1759 | |
3acf4b5c | 1760 | uw32(DCR9, 0x50000); |
4689ced9 | 1761 | udelay(1); |
3acf4b5c FR |
1762 | phy_data = (ur32(DCR9) >> 19) & 0x1; |
1763 | uw32(DCR9, 0x40000); | |
4689ced9 PC |
1764 | udelay(1); |
1765 | ||
1766 | return phy_data; | |
1767 | } | |
1768 | ||
1769 | ||
9baa3c34 | 1770 | static const struct pci_device_id uli526x_pci_tbl[] = { |
4689ced9 PC |
1771 | { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID }, |
1772 | { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID }, | |
1773 | { 0, } | |
1774 | }; | |
1775 | MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl); | |
1776 | ||
1777 | ||
1778 | static struct pci_driver uli526x_driver = { | |
1779 | .name = "uli526x", | |
1780 | .id_table = uli526x_pci_tbl, | |
1781 | .probe = uli526x_init_one, | |
779c1a85 | 1782 | .remove = uli526x_remove_one, |
b6aec32a RW |
1783 | .suspend = uli526x_suspend, |
1784 | .resume = uli526x_resume, | |
4689ced9 PC |
1785 | }; |
1786 | ||
1787 | MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw"); | |
1788 | MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver"); | |
1789 | MODULE_LICENSE("GPL"); | |
1790 | ||
c213460f ES |
1791 | module_param(debug, int, 0644); |
1792 | module_param(mode, int, 0); | |
1793 | module_param(cr6set, int, 0); | |
4689ced9 PC |
1794 | MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)"); |
1795 | MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); | |
1796 | ||
1797 | /* Description: | |
1798 | * when user used insmod to add module, system invoked init_module() | |
945a7876 | 1799 | * to register the services. |
4689ced9 PC |
1800 | */ |
1801 | ||
1802 | static int __init uli526x_init_module(void) | |
1803 | { | |
4689ced9 | 1804 | |
1c3319fb | 1805 | pr_info("%s\n", version); |
4689ced9 PC |
1806 | printed_version = 1; |
1807 | ||
1808 | ULI526X_DBUG(0, "init_module() ", debug); | |
1809 | ||
1810 | if (debug) | |
1811 | uli526x_debug = debug; /* set debug flag */ | |
1812 | if (cr6set) | |
1813 | uli526x_cr6_user_set = cr6set; | |
1814 | ||
e1c3e501 | 1815 | switch (mode) { |
4689ced9 PC |
1816 | case ULI526X_10MHF: |
1817 | case ULI526X_100MHF: | |
1818 | case ULI526X_10MFD: | |
1819 | case ULI526X_100MFD: | |
1820 | uli526x_media_mode = mode; | |
1821 | break; | |
e1c3e501 HK |
1822 | default: |
1823 | uli526x_media_mode = ULI526X_AUTO; | |
4689ced9 PC |
1824 | break; |
1825 | } | |
1826 | ||
e1c3e501 | 1827 | return pci_register_driver(&uli526x_driver); |
4689ced9 PC |
1828 | } |
1829 | ||
1830 | ||
1831 | /* | |
1832 | * Description: | |
1833 | * when user used rmmod to delete module, system invoked clean_module() | |
1834 | * to un-register all registered services. | |
1835 | */ | |
1836 | ||
1837 | static void __exit uli526x_cleanup_module(void) | |
1838 | { | |
791a1ddd | 1839 | ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug); |
4689ced9 PC |
1840 | pci_unregister_driver(&uli526x_driver); |
1841 | } | |
1842 | ||
1843 | module_init(uli526x_init_module); | |
1844 | module_exit(uli526x_cleanup_module); |