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bna: make function tables cont
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / brocade / bna / bfa_ioc_ct.c
CommitLineData
8b230ed8
RM		 1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#include "bfa_ioc.h"
20#include "cna.h"
21#include "bfi.h"
a9602490 22#include "bfi_reg.h"
8b230ed8
RM		 23#include "bfa_defs.h"
24
1d32f769
RM		 25#define bfa_ioc_ct_sync_pos(__ioc) \
26 ((u32) (1 << bfa_ioc_pcifn(__ioc)))
27#define BFA_IOC_SYNC_REQD_SH 16
28#define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
29#define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
30#define bfa_ioc_ct_get_sync_reqd(__val) (__val >> BFA_IOC_SYNC_REQD_SH)
31#define bfa_ioc_ct_sync_reqd_pos(__ioc) \
32 (bfa_ioc_ct_sync_pos(__ioc) << BFA_IOC_SYNC_REQD_SH)
33
8b230ed8
RM		 34/*
35 * forward declarations
36 */
37static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
38static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
39static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
40static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
41static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
1d32f769 42static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
8b230ed8 43static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
79ea6c89 44static bool bfa_ioc_ct_sync_start(struct bfa_ioc *ioc);
1d32f769
RM		 45static void bfa_ioc_ct_sync_join(struct bfa_ioc *ioc);
46static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc);
47static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
48static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
078086f3
RM		 49static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
50 enum bfi_asic_mode asic_mode);
8b230ed8 51
d91d25d5 52static const struct bfa_ioc_hwif nw_hwif_ct = {
53 .ioc_pll_init = bfa_ioc_ct_pll_init,
54 .ioc_firmware_lock = bfa_ioc_ct_firmware_lock,
55 .ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock,
56 .ioc_reg_init = bfa_ioc_ct_reg_init,
57 .ioc_map_port = bfa_ioc_ct_map_port,
58 .ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set,
59 .ioc_notify_fail = bfa_ioc_ct_notify_fail,
60 .ioc_ownership_reset = bfa_ioc_ct_ownership_reset,
61 .ioc_sync_start = bfa_ioc_ct_sync_start,
62 .ioc_sync_join = bfa_ioc_ct_sync_join,
63 .ioc_sync_leave = bfa_ioc_ct_sync_leave,
64 .ioc_sync_ack = bfa_ioc_ct_sync_ack,
65 .ioc_sync_complete = bfa_ioc_ct_sync_complete,
66};
6a1ccaef 67
8b230ed8
RM		 68/**
69 * Called from bfa_ioc_attach() to map asic specific calls.
70 */
71void
8a891429 72bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
8b230ed8 73{
8a891429 74 ioc->ioc_hwif = &nw_hwif_ct;
8b230ed8
RM		 75}
76
77/**
78 * Return true if firmware of current driver matches the running firmware.
79 */
80static bool
81bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
82{
83 enum bfi_ioc_state ioc_fwstate;
84 u32 usecnt;
85 struct bfi_ioc_image_hdr fwhdr;
86
8b230ed8
RM		 87 /**
88 * If bios boot (flash based) -- do not increment usage count
89 */
078086f3 90 if (bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)) <
8b230ed8
RM		 91 BFA_IOC_FWIMG_MINSZ)
92 return true;
93
8a891429 94 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
8b230ed8
RM		 95 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
96
97 /**
98 * If usage count is 0, always return TRUE.
99 */
100 if (usecnt == 0) {
101 writel(1, ioc->ioc_regs.ioc_usage_reg);
8a891429 102 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
1d32f769 103 writel(0, ioc->ioc_regs.ioc_fail_sync);
8b230ed8
RM		 104 return true;
105 }
106
107 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
108
109 /**
110 * Use count cannot be non-zero and chip in uninitialized state.
111 */
112 BUG_ON(!(ioc_fwstate != BFI_IOC_UNINIT));
113
114 /**
115 * Check if another driver with a different firmware is active
116 */
8a891429
RM		 117 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
118 if (!bfa_nw_ioc_fwver_cmp(ioc, &fwhdr)) {
119 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
8b230ed8
RM		 120 return false;
121 }
122
123 /**
124 * Same firmware version. Increment the reference count.
125 */
126 usecnt++;
127 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
8a891429 128 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
8b230ed8
RM		 129 return true;
130}
131
132static void
133bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
134{
135 u32 usecnt;
136
8b230ed8
RM		 137 /**
138 * If bios boot (flash based) -- do not decrement usage count
139 */
078086f3 140 if (bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)) <
8b230ed8
RM		 141 BFA_IOC_FWIMG_MINSZ)
142 return;
143
144 /**
145 * decrement usage count
146 */
8a891429 147 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
8b230ed8
RM		 148 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
149 BUG_ON(!(usecnt > 0));
150
151 usecnt--;
152 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
153
8a891429 154 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
8b230ed8
RM		 155}
156
157/**
158 * Notify other functions on HB failure.
159 */
160static void
1d32f769 161bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
8b230ed8 162{
078086f3
RM		 163 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
164 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
165 /* Wait for halt to take effect */
166 readl(ioc->ioc_regs.ll_halt);
167 readl(ioc->ioc_regs.alt_ll_halt);
8b230ed8
RM		 168}
169
170/**
171 * Host to LPU mailbox message addresses
172 */
078086f3 173static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } ct_fnreg[] = {
8b230ed8
RM		 174 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
175 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
176 { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
177 { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
178};
179
180/**
181 * Host <-> LPU mailbox command/status registers - port 0
182 */
a9602490
RM		 183static struct { u32 hfn, lpu; } ct_p0reg[] = {
184 { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
185 { HOSTFN1_LPU0_CMD_STAT, LPU0_HOSTFN1_CMD_STAT },
186 { HOSTFN2_LPU0_CMD_STAT, LPU0_HOSTFN2_CMD_STAT },
187 { HOSTFN3_LPU0_CMD_STAT, LPU0_HOSTFN3_CMD_STAT }
8b230ed8
RM		 188};
189
190/**
191 * Host <-> LPU mailbox command/status registers - port 1
192 */
a9602490
RM		 193static struct { u32 hfn, lpu; } ct_p1reg[] = {
194 { HOSTFN0_LPU1_CMD_STAT, LPU1_HOSTFN0_CMD_STAT },
195 { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT },
196 { HOSTFN2_LPU1_CMD_STAT, LPU1_HOSTFN2_CMD_STAT },
197 { HOSTFN3_LPU1_CMD_STAT, LPU1_HOSTFN3_CMD_STAT }
8b230ed8
RM		 198};
199
200static void
201bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
202{
203 void __iomem *rb;
204 int pcifn = bfa_ioc_pcifn(ioc);
205
206 rb = bfa_ioc_bar0(ioc);
207
078086f3
RM		 208 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox;
209 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox;
210 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn;
8b230ed8
RM		 211
212 if (ioc->port_id == 0) {
213 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
214 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
1d32f769 215 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
a9602490
RM		 216 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn;
217 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu;
8b230ed8 218 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
1d32f769 219 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
8b230ed8
RM		 220 } else {
221 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
222 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
1d32f769 223 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
a9602490
RM		 224 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;
225 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
8b230ed8 226 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
1d32f769 227 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
8b230ed8
RM		 228 }
229
230 /*
231 * PSS control registers
232 */
233 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
234 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
a9602490
RM		 235 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
236 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
8b230ed8
RM		 237
238 /*
239 * IOC semaphore registers and serialization
240 */
241 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
242 ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
243 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
244 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
1d32f769 245 ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
8b230ed8
RM		 246
247 /**
248 * sram memory access
249 */
250 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
251 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
252
253 /*
254 * err set reg : for notification of hb failure in fcmode
255 */
256 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
257}
258
259/**
260 * Initialize IOC to port mapping.
261 */
262
263#define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
264static void
265bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
266{
267 void __iomem *rb = ioc->pcidev.pci_bar_kva;
268 u32 r32;
269
270 /**
271 * For catapult, base port id on personality register and IOC type
272 */
273 r32 = readl(rb + FNC_PERS_REG);
274 r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
275 ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
276
277}
278
279/**
280 * Set interrupt mode for a function: INTX or MSIX
281 */
282static void
283bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
284{
285 void __iomem *rb = ioc->pcidev.pci_bar_kva;
286 u32 r32, mode;
287
288 r32 = readl(rb + FNC_PERS_REG);
289
290 mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
291 __F0_INTX_STATUS;
292
293 /**
294 * If already in desired mode, do not change anything
295 */
6a1ccaef 296 if ((!msix && mode) || (msix && !mode))
8b230ed8
RM		 297 return;
298
299 if (msix)
300 mode = __F0_INTX_STATUS_MSIX;
301 else
302 mode = __F0_INTX_STATUS_INTA;
303
304 r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
305 r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
306
307 writel(r32, rb + FNC_PERS_REG);
308}
309
310/**
311 * Cleanup hw semaphore and usecnt registers
312 */
313static void
314bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
315{
078086f3
RM		 316 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
317 writel(0, ioc->ioc_regs.ioc_usage_reg);
318 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
8b230ed8
RM		 319
320 /*
321 * Read the hw sem reg to make sure that it is locked
322 * before we clear it. If it is not locked, writing 1
323 * will lock it instead of clearing it.
324 */
325 readl(ioc->ioc_regs.ioc_sem_reg);
8a891429 326 bfa_nw_ioc_hw_sem_release(ioc);
8b230ed8
RM		 327}
328
79ea6c89
RM		 329/**
330 * Synchronized IOC failure processing routines
331 */
332static bool
333bfa_ioc_ct_sync_start(struct bfa_ioc *ioc)
334{
335 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
336 u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
337
338 /*
339 * Driver load time. If the sync required bit for this PCI fn
340 * is set, it is due to an unclean exit by the driver for this
341 * PCI fn in the previous incarnation. Whoever comes here first
342 * should clean it up, no matter which PCI fn.
343 */
344
345 if (sync_reqd & bfa_ioc_ct_sync_pos(ioc)) {
346 writel(0, ioc->ioc_regs.ioc_fail_sync);
347 writel(1, ioc->ioc_regs.ioc_usage_reg);
348 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
349 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
350 return true;
351 }
352
353 return bfa_ioc_ct_sync_complete(ioc);
354}
1d32f769
RM		 355/**
356 * Synchronized IOC failure processing routines
357 */
358static void
359bfa_ioc_ct_sync_join(struct bfa_ioc *ioc)
360{
361 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
362 u32 sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc);
363
364 writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
365}
366
367static void
368bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc)
369{
370 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
371 u32 sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) |
372 bfa_ioc_ct_sync_pos(ioc);
373
374 writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
375}
376
377static void
378bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
379{
380 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
381
382 writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
383}
384
385static bool
386bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc)
387{
388 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
389 u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
390 u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
391 u32 tmp_ackd;
392
393 if (sync_ackd == 0)
394 return true;
395
396 /**
397 * The check below is to see whether any other PCI fn
398 * has reinitialized the ASIC (reset sync_ackd bits)
399 * and failed again while this IOC was waiting for hw
400 * semaphore (in bfa_iocpf_sm_semwait()).
401 */
402 tmp_ackd = sync_ackd;
403 if ((sync_reqd & bfa_ioc_ct_sync_pos(ioc)) &&
404 !(sync_ackd & bfa_ioc_ct_sync_pos(ioc)))
405 sync_ackd |= bfa_ioc_ct_sync_pos(ioc);
406
407 if (sync_reqd == sync_ackd) {
408 writel(bfa_ioc_ct_clear_sync_ackd(r32),
409 ioc->ioc_regs.ioc_fail_sync);
410 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
411 writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
412 return true;
413 }
414
415 /**
416 * If another PCI fn reinitialized and failed again while
417 * this IOC was waiting for hw sem, the sync_ackd bit for
418 * this IOC need to be set again to allow reinitialization.
419 */
420 if (tmp_ackd != sync_ackd)
421 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
422
423 return false;
424}
425
8a891429 426static enum bfa_status
078086f3 427bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
8b230ed8
RM		 428{
429 u32 pll_sclk, pll_fclk, r32;
078086f3 430 bool fcmode = (asic_mode == BFI_ASIC_MODE_FC);
8b230ed8 431
a9602490
RM		 432 pll_sclk = __APP_PLL_SCLK_LRESETN | __APP_PLL_SCLK_ENARST |
433 __APP_PLL_SCLK_RSEL200500 | __APP_PLL_SCLK_P0_1(3U) |
434 __APP_PLL_SCLK_JITLMT0_1(3U) |
435 __APP_PLL_SCLK_CNTLMT0_1(1U);
436 pll_fclk = __APP_PLL_LCLK_LRESETN | __APP_PLL_LCLK_ENARST |
437 __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
438 __APP_PLL_LCLK_JITLMT0_1(3U) |
439 __APP_PLL_LCLK_CNTLMT0_1(1U);
440
8b230ed8
RM		 441 if (fcmode) {
442 writel(0, (rb + OP_MODE));
443 writel(__APP_EMS_CMLCKSEL |
444 __APP_EMS_REFCKBUFEN2 |
445 __APP_EMS_CHANNEL_SEL,
446 (rb + ETH_MAC_SER_REG));
447 } else {
448 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
449 writel(__APP_EMS_REFCKBUFEN1,
450 (rb + ETH_MAC_SER_REG));
451 }
452 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
453 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
454 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
455 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
456 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
457 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
458 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
459 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
460 writel(pll_sclk |
a9602490
RM		 461 __APP_PLL_SCLK_LOGIC_SOFT_RESET,
462 rb + APP_PLL_SCLK_CTL_REG);
8b230ed8 463 writel(pll_fclk |
a9602490
RM		 464 __APP_PLL_LCLK_LOGIC_SOFT_RESET,
465 rb + APP_PLL_LCLK_CTL_REG);
8b230ed8 466 writel(pll_sclk |
a9602490
RM		 467 __APP_PLL_SCLK_LOGIC_SOFT_RESET | __APP_PLL_SCLK_ENABLE,
468 rb + APP_PLL_SCLK_CTL_REG);
8b230ed8 469 writel(pll_fclk |
a9602490
RM		 470 __APP_PLL_LCLK_LOGIC_SOFT_RESET | __APP_PLL_LCLK_ENABLE,
471 rb + APP_PLL_LCLK_CTL_REG);
8b230ed8
RM		 472 readl(rb + HOSTFN0_INT_MSK);
473 udelay(2000);
474 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
475 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
476 writel(pll_sclk |
a9602490
RM		 477 __APP_PLL_SCLK_ENABLE,
478 rb + APP_PLL_SCLK_CTL_REG);
8b230ed8 479 writel(pll_fclk |
a9602490
RM		 480 __APP_PLL_LCLK_ENABLE,
481 rb + APP_PLL_LCLK_CTL_REG);
482
8b230ed8
RM		 483 if (!fcmode) {
484 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
485 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
486 }
487 r32 = readl((rb + PSS_CTL_REG));
488 r32 &= ~__PSS_LMEM_RESET;
489 writel(r32, (rb + PSS_CTL_REG));
490 udelay(1000);
491 if (!fcmode) {
492 writel(0, (rb + PMM_1T_RESET_REG_P0));
493 writel(0, (rb + PMM_1T_RESET_REG_P1));
494 }
495
496 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
497 udelay(1000);
498 r32 = readl((rb + MBIST_STAT_REG));
499 writel(0, (rb + MBIST_CTL_REG));
500 return BFA_STATUS_OK;
501}
kernel source for telekom puls (alcatel/mediatek)