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bnx2x: Fix KR2 link
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.c
CommitLineData
247fa82b 1/* Copyright 2008-2013 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a 27#include "bnx2x.h"
619c5cb6
VZ		 28#include "bnx2x_cmn.h"
29
ea4e040a 30/********************************************************/
3196a88a 31#define ETH_HLEN 14
cd88ccee
YR		 32/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
ea4e040a
YR		 34#define ETH_MIN_PACKET_SIZE 60
35#define ETH_MAX_PACKET_SIZE 1500
36#define ETH_MAX_JUMBO_PACKET_SIZE 9600
37#define MDIO_ACCESS_TIMEOUT 1000
3c9ada22
YR		 38#define WC_LANE_MAX 4
39#define I2C_SWITCH_WIDTH 2
40#define I2C_BSC0 0
41#define I2C_BSC1 1
42#define I2C_WA_RETRY_CNT 3
50a29845 43#define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
3c9ada22
YR		 44#define MCPR_IMC_COMMAND_READ_OP 1
45#define MCPR_IMC_COMMAND_WRITE_OP 2
ea4e040a 46
26ffaf36
YR		 47/* LED Blink rate that will achieve ~15.9Hz */
48#define LED_BLINK_RATE_VAL_E3 354
49#define LED_BLINK_RATE_VAL_E1X_E2 480
ea4e040a 50/***********************************************************/
3196a88a 51/* Shortcut definitions */
ea4e040a
YR		 52/***********************************************************/
53
2f904460
EG		 54#define NIG_LATCH_BC_ENABLE_MI_INT 0
55
56#define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 58#define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60#define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64#define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66#define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68#define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70#define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72#define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
74
75#define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
78
79#define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
85
86#define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
91
92#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
cd88ccee 94#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
3196a88a 95#define AUTONEG_PARALLEL \
ea4e040a 96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 97#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 99#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 100
101#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105#define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113#define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115#define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
ea4e040a
YR		 117#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118#define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
3c9ada22
YR		 120#define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121#define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122#define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123#define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
4e7b4997 124#define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
cd88ccee
YR		 125#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
126#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
ea4e040a 127#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
cd88ccee 128#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
ea4e040a
YR		 129#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
130#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
131#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
132#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
133#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
134#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
135#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
cd88ccee
YR		 136#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
137#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
3c9ada22
YR		 138#define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
139#define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
6583e33b 140
4978140c
YR		 141#define LINK_UPDATE_MASK \
142 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
143 LINK_STATUS_LINK_UP | \
144 LINK_STATUS_PHYSICAL_LINK_FLAG | \
145 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
146 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
147 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
148 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
149 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
150 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
6583e33b 151
589abe3a 152#define SFP_EEPROM_CON_TYPE_ADDR 0x2
cd88ccee 153 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
589abe3a
EG		 154 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
155
4d295db0
EG		 156
157#define SFP_EEPROM_COMP_CODE_ADDR 0x3
158 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
159 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
160 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
161
589abe3a
EG		 162#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
163 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
cd88ccee 164 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 165
cd88ccee 166#define SFP_EEPROM_OPTIONS_ADDR 0x40
589abe3a 167 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
cd88ccee 168#define SFP_EEPROM_OPTIONS_SIZE 2
589abe3a 169
cd88ccee
YR		 170#define EDC_MODE_LINEAR 0x0022
171#define EDC_MODE_LIMITING 0x0044
172#define EDC_MODE_PASSIVE_DAC 0x0055
4d295db0 173
866cedae 174/* ETS defines*/
9380bb9e
YR		 175#define DCBX_INVALID_COS (0xFF)
176
bcab15c5
VZ		 177#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
178#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
9380bb9e
YR		 179#define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
180#define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
181#define ETS_E3B0_PBF_MIN_W_VAL (10000)
182
183#define MAX_PACKET_SIZE (9700)
a9077bfd 184#define MAX_KR_LINK_RETRY 4
9380bb9e 185
ea4e040a
YR		 186/**********************************************************/
187/* INTERFACE */
188/**********************************************************/
e10bc84d 189
cd2be89b 190#define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 191 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 192 (_phy)->def_md_devad, \
ea4e040a
YR		 193 (_bank + (_addr & 0xf)), \
194 _val)
195
cd2be89b 196#define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 197 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 198 (_phy)->def_md_devad, \
ea4e040a
YR		 199 (_bank + (_addr & 0xf)), \
200 _val)
201
ea4e040a
YR		 202static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
203{
204 u32 val = REG_RD(bp, reg);
205
206 val |= bits;
207 REG_WR(bp, reg, val);
208 return val;
209}
210
211static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
212{
213 u32 val = REG_RD(bp, reg);
214
215 val &= ~bits;
216 REG_WR(bp, reg, val);
217 return val;
218}
219
d3a8f13b
YR		 220/*
221 * bnx2x_check_lfa - This function checks if link reinitialization is required,
222 * or link flap can be avoided.
223 *
224 * @params: link parameters
225 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
226 * condition code.
227 */
228static int bnx2x_check_lfa(struct link_params *params)
229{
230 u32 link_status, cfg_idx, lfa_mask, cfg_size;
231 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
232 u32 saved_val, req_val, eee_status;
233 struct bnx2x *bp = params->bp;
234
235 additional_config =
236 REG_RD(bp, params->lfa_base +
237 offsetof(struct shmem_lfa, additional_config));
238
239 /* NOTE: must be first condition checked -
240 * to verify DCC bit is cleared in any case!
241 */
242 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
243 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
244 REG_WR(bp, params->lfa_base +
245 offsetof(struct shmem_lfa, additional_config),
246 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
247 return LFA_DCC_LFA_DISABLED;
248 }
249
250 /* Verify that link is up */
251 link_status = REG_RD(bp, params->shmem_base +
252 offsetof(struct shmem_region,
253 port_mb[params->port].link_status));
254 if (!(link_status & LINK_STATUS_LINK_UP))
255 return LFA_LINK_DOWN;
256
c63da990
BW		 257 /* if loaded after BOOT from SAN, don't flap the link in any case and
258 * rely on link set by preboot driver
259 */
260 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
261 return 0;
262
d3a8f13b
YR		 263 /* Verify that loopback mode is not set */
264 if (params->loopback_mode)
265 return LFA_LOOPBACK_ENABLED;
266
267 /* Verify that MFW supports LFA */
268 if (!params->lfa_base)
269 return LFA_MFW_IS_TOO_OLD;
270
271 if (params->num_phys == 3) {
272 cfg_size = 2;
273 lfa_mask = 0xffffffff;
274 } else {
275 cfg_size = 1;
276 lfa_mask = 0xffff;
277 }
278
279 /* Compare Duplex */
280 saved_val = REG_RD(bp, params->lfa_base +
281 offsetof(struct shmem_lfa, req_duplex));
282 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
283 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
284 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
285 (saved_val & lfa_mask), (req_val & lfa_mask));
286 return LFA_DUPLEX_MISMATCH;
287 }
288 /* Compare Flow Control */
289 saved_val = REG_RD(bp, params->lfa_base +
290 offsetof(struct shmem_lfa, req_flow_ctrl));
291 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
292 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
293 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
294 (saved_val & lfa_mask), (req_val & lfa_mask));
295 return LFA_FLOW_CTRL_MISMATCH;
296 }
297 /* Compare Link Speed */
298 saved_val = REG_RD(bp, params->lfa_base +
299 offsetof(struct shmem_lfa, req_line_speed));
300 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
301 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
302 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
303 (saved_val & lfa_mask), (req_val & lfa_mask));
304 return LFA_LINK_SPEED_MISMATCH;
305 }
306
307 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
308 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
309 offsetof(struct shmem_lfa,
310 speed_cap_mask[cfg_idx]));
311
312 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
313 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
314 cur_speed_cap_mask,
315 params->speed_cap_mask[cfg_idx]);
316 return LFA_SPEED_CAP_MISMATCH;
317 }
318 }
319
320 cur_req_fc_auto_adv =
321 REG_RD(bp, params->lfa_base +
322 offsetof(struct shmem_lfa, additional_config)) &
323 REQ_FC_AUTO_ADV_MASK;
324
325 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
326 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
327 cur_req_fc_auto_adv, params->req_fc_auto_adv);
328 return LFA_FLOW_CTRL_MISMATCH;
329 }
330
331 eee_status = REG_RD(bp, params->shmem2_base +
332 offsetof(struct shmem2_region,
333 eee_status[params->port]));
334
335 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
336 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
337 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
338 (params->eee_mode & EEE_MODE_ADV_LPI))) {
339 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
340 eee_status);
341 return LFA_EEE_MISMATCH;
342 }
343
344 /* LFA conditions are met */
345 return 0;
346}
3c9ada22
YR		 347/******************************************************************/
348/* EPIO/GPIO section */
349/******************************************************************/
3deb8167
YR		 350static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
351{
352 u32 epio_mask, gp_oenable;
353 *en = 0;
354 /* Sanity check */
355 if (epio_pin > 31) {
356 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
357 return;
358 }
359
360 epio_mask = 1 << epio_pin;
361 /* Set this EPIO to output */
362 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
363 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
364
365 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
366}
3c9ada22
YR		 367static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
368{
369 u32 epio_mask, gp_output, gp_oenable;
370
371 /* Sanity check */
372 if (epio_pin > 31) {
373 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
374 return;
375 }
376 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
377 epio_mask = 1 << epio_pin;
378 /* Set this EPIO to output */
379 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
380 if (en)
381 gp_output |= epio_mask;
382 else
383 gp_output &= ~epio_mask;
384
385 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
386
387 /* Set the value for this EPIO */
388 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
389 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
390}
391
392static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
393{
394 if (pin_cfg == PIN_CFG_NA)
395 return;
396 if (pin_cfg >= PIN_CFG_EPIO0) {
397 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
398 } else {
399 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
400 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
401 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
402 }
403}
404
3deb8167
YR		 405static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
406{
407 if (pin_cfg == PIN_CFG_NA)
408 return -EINVAL;
409 if (pin_cfg >= PIN_CFG_EPIO0) {
410 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
411 } else {
412 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
413 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
414 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
415 }
416 return 0;
417
418}
bcab15c5
VZ		 419/******************************************************************/
420/* ETS section */
421/******************************************************************/
6c3218c6 422static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
bcab15c5
VZ		 423{
424 /* ETS disabled configuration*/
425 struct bnx2x *bp = params->bp;
426
6c3218c6 427 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
bcab15c5 428
8f73f0b9 429 /* mapping between entry priority to client number (0,1,2 -debug and
bcab15c5
VZ		 430 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
431 * 3bits client num.
432 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
433 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
434 */
435
436 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
8f73f0b9 437 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
bcab15c5
VZ		 438 * as strict. Bits 0,1,2 - debug and management entries, 3 -
439 * COS0 entry, 4 - COS1 entry.
440 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
441 * bit4 bit3 bit2 bit1 bit0
442 * MCP and debug are strict
443 */
444
445 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
446 /* defines which entries (clients) are subjected to WFQ arbitration */
447 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
8f73f0b9 448 /* For strict priority entries defines the number of consecutive
2cf7acf9
YR		 449 * slots for the highest priority.
450 */
bcab15c5 451 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
8f73f0b9 452 /* mapping between the CREDIT_WEIGHT registers and actual client
bcab15c5
VZ		 453 * numbers
454 */
455 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
456 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
457 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
458
459 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
460 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
461 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
462 /* ETS mode disable */
463 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
8f73f0b9 464 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
bcab15c5
VZ		 465 * weight for COS0/COS1.
466 */
467 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
468 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
469 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
470 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
471 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
472 /* Defines the number of consecutive slots for the strict priority */
473 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
474}
6c3218c6
YR		 475/******************************************************************************
476* Description:
477* Getting min_w_val will be set according to line speed .
478*.
479******************************************************************************/
480static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
481{
482 u32 min_w_val = 0;
483 /* Calculate min_w_val.*/
484 if (vars->link_up) {
de0396f4 485 if (vars->line_speed == SPEED_20000)
6c3218c6
YR		 486 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
487 else
488 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
489 } else
490 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
8f73f0b9
YR		 491 /* If the link isn't up (static configuration for example ) The
492 * link will be according to 20GBPS.
493 */
6c3218c6
YR		 494 return min_w_val;
495}
496/******************************************************************************
497* Description:
498* Getting credit upper bound form min_w_val.
499*.
500******************************************************************************/
501static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
502{
503 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
504 MAX_PACKET_SIZE);
505 return credit_upper_bound;
506}
507/******************************************************************************
508* Description:
509* Set credit upper bound for NIG.
510*.
511******************************************************************************/
512static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
513 const struct link_params *params,
514 const u32 min_w_val)
515{
516 struct bnx2x *bp = params->bp;
517 const u8 port = params->port;
518 const u32 credit_upper_bound =
519 bnx2x_ets_get_credit_upper_bound(min_w_val);
520
521 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
522 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
523 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
524 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
525 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
526 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
527 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
528 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
529 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
530 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
531 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
532 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
533
de0396f4 534 if (!port) {
6c3218c6
YR		 535 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
536 credit_upper_bound);
537 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
538 credit_upper_bound);
539 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
540 credit_upper_bound);
541 }
542}
543/******************************************************************************
544* Description:
545* Will return the NIG ETS registers to init values.Except
546* credit_upper_bound.
547* That isn't used in this configuration (No WFQ is enabled) and will be
548* configured acording to spec
549*.
550******************************************************************************/
551static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
552 const struct link_vars *vars)
553{
554 struct bnx2x *bp = params->bp;
555 const u8 port = params->port;
556 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
8f73f0b9 557 /* Mapping between entry priority to client number (0,1,2 -debug and
6c3218c6
YR		 558 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
559 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
560 * reset value or init tool
561 */
562 if (port) {
563 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
564 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
565 } else {
566 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
567 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
568 }
8f73f0b9
YR		 569 /* For strict priority entries defines the number of consecutive
570 * slots for the highest priority.
571 */
6c3218c6
YR		 572 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
573 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
8f73f0b9 574 /* Mapping between the CREDIT_WEIGHT registers and actual client
6c3218c6
YR		 575 * numbers
576 */
6c3218c6
YR		 577 if (port) {
578 /*Port 1 has 6 COS*/
579 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
580 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
581 } else {
582 /*Port 0 has 9 COS*/
583 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
584 0x43210876);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
586 }
587
8f73f0b9 588 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
6c3218c6
YR		 589 * as strict. Bits 0,1,2 - debug and management entries, 3 -
590 * COS0 entry, 4 - COS1 entry.
591 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
592 * bit4 bit3 bit2 bit1 bit0
593 * MCP and debug are strict
594 */
595 if (port)
596 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
597 else
598 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
599 /* defines which entries (clients) are subjected to WFQ arbitration */
600 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
601 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
602
8f73f0b9
YR		 603 /* Please notice the register address are note continuous and a
604 * for here is note appropriate.In 2 port mode port0 only COS0-5
605 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
606 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
607 * are never used for WFQ
608 */
6c3218c6
YR		 609 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
610 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
611 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
612 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
613 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
614 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
615 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
616 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
617 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
618 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
619 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
620 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
de0396f4 621 if (!port) {
6c3218c6
YR		 622 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
623 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
624 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
625 }
626
627 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
628}
629/******************************************************************************
630* Description:
631* Set credit upper bound for PBF.
632*.
633******************************************************************************/
634static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
635 const struct link_params *params,
636 const u32 min_w_val)
637{
638 struct bnx2x *bp = params->bp;
639 const u32 credit_upper_bound =
640 bnx2x_ets_get_credit_upper_bound(min_w_val);
641 const u8 port = params->port;
642 u32 base_upper_bound = 0;
643 u8 max_cos = 0;
644 u8 i = 0;
8f73f0b9
YR		 645 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
646 * port mode port1 has COS0-2 that can be used for WFQ.
647 */
de0396f4 648 if (!port) {
6c3218c6
YR		 649 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
650 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
651 } else {
652 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
653 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
654 }
655
656 for (i = 0; i < max_cos; i++)
657 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
658}
659
660/******************************************************************************
661* Description:
662* Will return the PBF ETS registers to init values.Except
663* credit_upper_bound.
664* That isn't used in this configuration (No WFQ is enabled) and will be
665* configured acording to spec
666*.
667******************************************************************************/
668static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
669{
670 struct bnx2x *bp = params->bp;
671 const u8 port = params->port;
672 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
673 u8 i = 0;
674 u32 base_weight = 0;
675 u8 max_cos = 0;
676
8f73f0b9 677 /* Mapping between entry priority to client number 0 - COS0
6c3218c6
YR		 678 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
679 * TODO_ETS - Should be done by reset value or init tool
680 */
681 if (port)
682 /* 0x688 (|011|0 10|00 1|000) */
683 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
684 else
685 /* (10 1|100 |011|0 10|00 1|000) */
686 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
687
688 /* TODO_ETS - Should be done by reset value or init tool */
689 if (port)
690 /* 0x688 (|011|0 10|00 1|000)*/
691 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
692 else
693 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
694 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
695
696 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
697 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
698
699
700 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
701 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
702
703 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
704 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
8f73f0b9
YR		 705 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
706 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
707 */
de0396f4 708 if (!port) {
6c3218c6
YR		 709 base_weight = PBF_REG_COS0_WEIGHT_P0;
710 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
711 } else {
712 base_weight = PBF_REG_COS0_WEIGHT_P1;
713 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
714 }
715
716 for (i = 0; i < max_cos; i++)
717 REG_WR(bp, base_weight + (0x4 * i), 0);
718
719 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
720}
721/******************************************************************************
722* Description:
723* E3B0 disable will return basicly the values to init values.
724*.
725******************************************************************************/
726static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
727 const struct link_vars *vars)
728{
729 struct bnx2x *bp = params->bp;
730
731 if (!CHIP_IS_E3B0(bp)) {
94f05b0f
JP		 732 DP(NETIF_MSG_LINK,
733 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
6c3218c6
YR		 734 return -EINVAL;
735 }
736
737 bnx2x_ets_e3b0_nig_disabled(params, vars);
738
739 bnx2x_ets_e3b0_pbf_disabled(params);
740
741 return 0;
742}
743
744/******************************************************************************
745* Description:
746* Disable will return basicly the values to init values.
8f73f0b9 747*
6c3218c6
YR		 748******************************************************************************/
749int bnx2x_ets_disabled(struct link_params *params,
750 struct link_vars *vars)
751{
752 struct bnx2x *bp = params->bp;
753 int bnx2x_status = 0;
754
755 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
756 bnx2x_ets_e2e3a0_disabled(params);
757 else if (CHIP_IS_E3B0(bp))
758 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
759 else {
760 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
761 return -EINVAL;
762 }
763
764 return bnx2x_status;
765}
766
767/******************************************************************************
768* Description
769* Set the COS mappimg to SP and BW until this point all the COS are not
770* set as SP or BW.
771******************************************************************************/
772static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
773 const struct bnx2x_ets_params *ets_params,
774 const u8 cos_sp_bitmap,
775 const u8 cos_bw_bitmap)
776{
777 struct bnx2x *bp = params->bp;
778 const u8 port = params->port;
779 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
780 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
781 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
782 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
783
784 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
785 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
786
787 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
788 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
bcab15c5 789
6c3218c6
YR		 790 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
791 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
792 nig_cli_subject2wfq_bitmap);
793
794 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
795 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
796 pbf_cli_subject2wfq_bitmap);
797
798 return 0;
799}
800
801/******************************************************************************
802* Description:
803* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
804* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
805******************************************************************************/
806static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
807 const u8 cos_entry,
808 const u32 min_w_val_nig,
809 const u32 min_w_val_pbf,
810 const u16 total_bw,
811 const u8 bw,
812 const u8 port)
813{
814 u32 nig_reg_adress_crd_weight = 0;
815 u32 pbf_reg_adress_crd_weight = 0;
c482e6c0
YR		 816 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
817 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
818 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
6c3218c6
YR		 819
820 switch (cos_entry) {
821 case 0:
822 nig_reg_adress_crd_weight =
823 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
824 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
825 pbf_reg_adress_crd_weight = (port) ?
826 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
827 break;
828 case 1:
829 nig_reg_adress_crd_weight = (port) ?
830 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
831 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
832 pbf_reg_adress_crd_weight = (port) ?
833 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
834 break;
835 case 2:
836 nig_reg_adress_crd_weight = (port) ?
837 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
838 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
839
840 pbf_reg_adress_crd_weight = (port) ?
841 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
842 break;
843 case 3:
844 if (port)
845 return -EINVAL;
846 nig_reg_adress_crd_weight =
847 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
848 pbf_reg_adress_crd_weight =
849 PBF_REG_COS3_WEIGHT_P0;
850 break;
851 case 4:
852 if (port)
853 return -EINVAL;
854 nig_reg_adress_crd_weight =
855 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
856 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
857 break;
858 case 5:
859 if (port)
860 return -EINVAL;
861 nig_reg_adress_crd_weight =
862 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
863 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
864 break;
865 }
866
867 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
868
869 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
870
871 return 0;
872}
873/******************************************************************************
874* Description:
875* Calculate the total BW.A value of 0 isn't legal.
8f73f0b9 876*
6c3218c6
YR		 877******************************************************************************/
878static int bnx2x_ets_e3b0_get_total_bw(
879 const struct link_params *params,
870516e1 880 struct bnx2x_ets_params *ets_params,
6c3218c6
YR		 881 u16 *total_bw)
882{
883 struct bnx2x *bp = params->bp;
884 u8 cos_idx = 0;
870516e1 885 u8 is_bw_cos_exist = 0;
6c3218c6
YR		 886
887 *total_bw = 0 ;
888 /* Calculate total BW requested */
889 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
de0396f4 890 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
870516e1
YR		 891 is_bw_cos_exist = 1;
892 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
893 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
894 "was set to 0\n");
8f73f0b9 895 /* This is to prevent a state when ramrods
870516e1 896 * can't be sent
8f73f0b9 897 */
870516e1
YR		 898 ets_params->cos[cos_idx].params.bw_params.bw
899 = 1;
900 }
c482e6c0
YR		 901 *total_bw +=
902 ets_params->cos[cos_idx].params.bw_params.bw;
6c3218c6 903 }
6c3218c6
YR		 904 }
905
c482e6c0 906 /* Check total BW is valid */
de0396f4
YR		 907 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
908 if (*total_bw == 0) {
94f05b0f 909 DP(NETIF_MSG_LINK,
2f751a80 910 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
6c3218c6
YR		 911 return -EINVAL;
912 }
94f05b0f 913 DP(NETIF_MSG_LINK,
2f751a80 914 "bnx2x_ets_E3B0_config total BW should be 100\n");
8f73f0b9 915 /* We can handle a case whre the BW isn't 100 this can happen
2f751a80
YR		 916 * if the TC are joined.
917 */
6c3218c6
YR		 918 }
919 return 0;
920}
921
922/******************************************************************************
923* Description:
924* Invalidate all the sp_pri_to_cos.
8f73f0b9 925*
6c3218c6
YR		 926******************************************************************************/
927static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
928{
929 u8 pri = 0;
930 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
931 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
932}
933/******************************************************************************
934* Description:
935* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
936* according to sp_pri_to_cos.
8f73f0b9 937*
6c3218c6
YR		 938******************************************************************************/
939static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
940 u8 *sp_pri_to_cos, const u8 pri,
941 const u8 cos_entry)
942{
943 struct bnx2x *bp = params->bp;
944 const u8 port = params->port;
945 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
946 DCBX_E3B0_MAX_NUM_COS_PORT0;
947
7e5998aa
DC		 948 if (pri >= max_num_of_cos) {
949 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
950 "parameter Illegal strict priority\n");
951 return -EINVAL;
952 }
953
de0396f4 954 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
6c3218c6 955 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
94f05b0f 956 "parameter There can't be two COS's with "
6c3218c6
YR		 957 "the same strict pri\n");
958 return -EINVAL;
959 }
960
6c3218c6
YR		 961 sp_pri_to_cos[pri] = cos_entry;
962 return 0;
963
964}
965
966/******************************************************************************
967* Description:
968* Returns the correct value according to COS and priority in
969* the sp_pri_cli register.
8f73f0b9 970*
6c3218c6
YR		 971******************************************************************************/
972static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
973 const u8 pri_set,
974 const u8 pri_offset,
975 const u8 entry_size)
976{
977 u64 pri_cli_nig = 0;
978 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
979 (pri_set + pri_offset));
980
981 return pri_cli_nig;
982}
983/******************************************************************************
984* Description:
985* Returns the correct value according to COS and priority in the
986* sp_pri_cli register for NIG.
8f73f0b9 987*
6c3218c6
YR		 988******************************************************************************/
989static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
990{
991 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
992 const u8 nig_cos_offset = 3;
993 const u8 nig_pri_offset = 3;
994
995 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
996 nig_pri_offset, 4);
997
998}
999/******************************************************************************
1000* Description:
1001* Returns the correct value according to COS and priority in the
1002* sp_pri_cli register for PBF.
8f73f0b9 1003*
6c3218c6
YR		 1004******************************************************************************/
1005static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1006{
1007 const u8 pbf_cos_offset = 0;
1008 const u8 pbf_pri_offset = 0;
1009
1010 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1011 pbf_pri_offset, 3);
1012
1013}
1014
1015/******************************************************************************
1016* Description:
1017* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1018* according to sp_pri_to_cos.(which COS has higher priority)
8f73f0b9 1019*
6c3218c6
YR		 1020******************************************************************************/
1021static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1022 u8 *sp_pri_to_cos)
1023{
1024 struct bnx2x *bp = params->bp;
1025 u8 i = 0;
1026 const u8 port = params->port;
1027 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1028 u64 pri_cli_nig = 0x210;
1029 u32 pri_cli_pbf = 0x0;
1030 u8 pri_set = 0;
1031 u8 pri_bitmask = 0;
1032 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1033 DCBX_E3B0_MAX_NUM_COS_PORT0;
1034
1035 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1036
1037 /* Set all the strict priority first */
1038 for (i = 0; i < max_num_of_cos; i++) {
de0396f4
YR		 1039 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1040 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
6c3218c6
YR		 1041 DP(NETIF_MSG_LINK,
1042 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1043 "invalid cos entry\n");
1044 return -EINVAL;
1045 }
1046
1047 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1048 sp_pri_to_cos[i], pri_set);
1049
1050 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1051 sp_pri_to_cos[i], pri_set);
1052 pri_bitmask = 1 << sp_pri_to_cos[i];
1053 /* COS is used remove it from bitmap.*/
de0396f4 1054 if (!(pri_bitmask & cos_bit_to_set)) {
6c3218c6
YR		 1055 DP(NETIF_MSG_LINK,
1056 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1057 "invalid There can't be two COS's with"
1058 " the same strict pri\n");
1059 return -EINVAL;
1060 }
1061 cos_bit_to_set &= ~pri_bitmask;
1062 pri_set++;
1063 }
1064 }
1065
1066 /* Set all the Non strict priority i= COS*/
1067 for (i = 0; i < max_num_of_cos; i++) {
1068 pri_bitmask = 1 << i;
1069 /* Check if COS was already used for SP */
1070 if (pri_bitmask & cos_bit_to_set) {
1071 /* COS wasn't used for SP */
1072 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1073 i, pri_set);
1074
1075 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1076 i, pri_set);
1077 /* COS is used remove it from bitmap.*/
1078 cos_bit_to_set &= ~pri_bitmask;
1079 pri_set++;
1080 }
1081 }
1082
1083 if (pri_set != max_num_of_cos) {
1084 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1085 "entries were set\n");
1086 return -EINVAL;
1087 }
1088
1089 if (port) {
1090 /* Only 6 usable clients*/
1091 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1092 (u32)pri_cli_nig);
1093
1094 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1095 } else {
1096 /* Only 9 usable clients*/
1097 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1098 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1099
1100 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1101 pri_cli_nig_lsb);
1102 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1103 pri_cli_nig_msb);
1104
1105 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1106 }
1107 return 0;
1108}
1109
1110/******************************************************************************
1111* Description:
1112* Configure the COS to ETS according to BW and SP settings.
1113******************************************************************************/
1114int bnx2x_ets_e3b0_config(const struct link_params *params,
1115 const struct link_vars *vars,
870516e1 1116 struct bnx2x_ets_params *ets_params)
6c3218c6
YR		 1117{
1118 struct bnx2x *bp = params->bp;
1119 int bnx2x_status = 0;
1120 const u8 port = params->port;
1121 u16 total_bw = 0;
1122 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1123 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1124 u8 cos_bw_bitmap = 0;
1125 u8 cos_sp_bitmap = 0;
1126 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1127 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1128 DCBX_E3B0_MAX_NUM_COS_PORT0;
1129 u8 cos_entry = 0;
1130
1131 if (!CHIP_IS_E3B0(bp)) {
94f05b0f
JP		 1132 DP(NETIF_MSG_LINK,
1133 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
6c3218c6
YR		 1134 return -EINVAL;
1135 }
1136
1137 if ((ets_params->num_of_cos > max_num_of_cos)) {
1138 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1139 "isn't supported\n");
1140 return -EINVAL;
1141 }
1142
1143 /* Prepare sp strict priority parameters*/
1144 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1145
1146 /* Prepare BW parameters*/
1147 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1148 &total_bw);
de0396f4 1149 if (bnx2x_status) {
94f05b0f
JP		 1150 DP(NETIF_MSG_LINK,
1151 "bnx2x_ets_E3B0_config get_total_bw failed\n");
6c3218c6
YR		 1152 return -EINVAL;
1153 }
1154
8f73f0b9 1155 /* Upper bound is set according to current link speed (min_w_val
2f751a80 1156 * should be the same for upper bound and COS credit val).
6c3218c6
YR		 1157 */
1158 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1159 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1160
1161
1162 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1163 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1164 cos_bw_bitmap |= (1 << cos_entry);
8f73f0b9 1165 /* The function also sets the BW in HW(not the mappin
6c3218c6
YR		 1166 * yet)
1167 */
1168 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1169 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1170 total_bw,
1171 ets_params->cos[cos_entry].params.bw_params.bw,
1172 port);
1173 } else if (bnx2x_cos_state_strict ==
1174 ets_params->cos[cos_entry].state){
1175 cos_sp_bitmap |= (1 << cos_entry);
1176
1177 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1178 params,
1179 sp_pri_to_cos,
1180 ets_params->cos[cos_entry].params.sp_params.pri,
1181 cos_entry);
1182
1183 } else {
94f05b0f
JP		 1184 DP(NETIF_MSG_LINK,
1185 "bnx2x_ets_e3b0_config cos state not valid\n");
6c3218c6
YR		 1186 return -EINVAL;
1187 }
de0396f4 1188 if (bnx2x_status) {
94f05b0f
JP		 1189 DP(NETIF_MSG_LINK,
1190 "bnx2x_ets_e3b0_config set cos bw failed\n");
6c3218c6
YR		 1191 return bnx2x_status;
1192 }
1193 }
1194
1195 /* Set SP register (which COS has higher priority) */
1196 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1197 sp_pri_to_cos);
1198
de0396f4 1199 if (bnx2x_status) {
94f05b0f
JP		 1200 DP(NETIF_MSG_LINK,
1201 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
6c3218c6
YR		 1202 return bnx2x_status;
1203 }
1204
1205 /* Set client mapping of BW and strict */
1206 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1207 cos_sp_bitmap,
1208 cos_bw_bitmap);
1209
de0396f4 1210 if (bnx2x_status) {
6c3218c6
YR		 1211 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1212 return bnx2x_status;
1213 }
1214 return 0;
1215}
65a001ba 1216static void bnx2x_ets_bw_limit_common(const struct link_params *params)
bcab15c5
VZ		 1217{
1218 /* ETS disabled configuration */
1219 struct bnx2x *bp = params->bp;
1220 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
8f73f0b9 1221 /* Defines which entries (clients) are subjected to WFQ arbitration
2cf7acf9
YR		 1222 * COS0 0x8
1223 * COS1 0x10
1224 */
bcab15c5 1225 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
8f73f0b9 1226 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
2cf7acf9
YR		 1227 * client numbers (WEIGHT_0 does not actually have to represent
1228 * client 0)
1229 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1230 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1231 */
bcab15c5
VZ		 1232 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1233
1234 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1235 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1236 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1237 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1238
1239 /* ETS mode enabled*/
1240 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1241
1242 /* Defines the number of consecutive slots for the strict priority */
1243 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
8f73f0b9 1244 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2cf7acf9
YR		 1245 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1246 * entry, 4 - COS1 entry.
1247 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1248 * bit4 bit3 bit2 bit1 bit0
1249 * MCP and debug are strict
1250 */
bcab15c5
VZ		 1251 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1252
1253 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1254 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1255 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1256 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1257 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1258}
1259
1260void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1261 const u32 cos1_bw)
1262{
1263 /* ETS disabled configuration*/
1264 struct bnx2x *bp = params->bp;
1265 const u32 total_bw = cos0_bw + cos1_bw;
1266 u32 cos0_credit_weight = 0;
1267 u32 cos1_credit_weight = 0;
1268
1269 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1270
de0396f4
YR		 1271 if ((!total_bw) ||
1272 (!cos0_bw) ||
1273 (!cos1_bw)) {
cd88ccee 1274 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
bcab15c5
VZ		 1275 return;
1276 }
1277
1278 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1279 total_bw;
1280 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1281 total_bw;
1282
1283 bnx2x_ets_bw_limit_common(params);
1284
1285 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1286 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1287
1288 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1289 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1290}
1291
fcf5b650 1292int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
bcab15c5
VZ		 1293{
1294 /* ETS disabled configuration*/
1295 struct bnx2x *bp = params->bp;
1296 u32 val = 0;
1297
bcab15c5 1298 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
8f73f0b9 1299 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
bcab15c5
VZ		 1300 * as strict. Bits 0,1,2 - debug and management entries,
1301 * 3 - COS0 entry, 4 - COS1 entry.
1302 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1303 * bit4 bit3 bit2 bit1 bit0
1304 * MCP and debug are strict
1305 */
1306 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
8f73f0b9 1307 /* For strict priority entries defines the number of consecutive slots
bcab15c5
VZ		 1308 * for the highest priority.
1309 */
1310 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1311 /* ETS mode disable */
1312 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1313 /* Defines the number of consecutive slots for the strict priority */
1314 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1315
1316 /* Defines the number of consecutive slots for the strict priority */
1317 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1318
8f73f0b9 1319 /* Mapping between entry priority to client number (0,1,2 -debug and
2cf7acf9
YR		 1320 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1321 * 3bits client num.
1322 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1323 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1324 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1325 */
de0396f4 1326 val = (!strict_cos) ? 0x2318 : 0x22E0;
bcab15c5
VZ		 1327 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1328
1329 return 0;
1330}
c8c60d88 1331
bcab15c5 1332/******************************************************************/
e8920674 1333/* PFC section */
bcab15c5 1334/******************************************************************/
9380bb9e
YR		 1335static void bnx2x_update_pfc_xmac(struct link_params *params,
1336 struct link_vars *vars,
1337 u8 is_lb)
1338{
1339 struct bnx2x *bp = params->bp;
1340 u32 xmac_base;
1341 u32 pause_val, pfc0_val, pfc1_val;
1342
1343 /* XMAC base adrr */
1344 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1345
1346 /* Initialize pause and pfc registers */
1347 pause_val = 0x18000;
1348 pfc0_val = 0xFFFF8000;
1349 pfc1_val = 0x2;
1350
1351 /* No PFC support */
1352 if (!(params->feature_config_flags &
1353 FEATURE_CONFIG_PFC_ENABLED)) {
1354
8f73f0b9 1355 /* RX flow control - Process pause frame in receive direction
9380bb9e
YR		 1356 */
1357 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1358 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1359
8f73f0b9 1360 /* TX flow control - Send pause packet when buffer is full */
9380bb9e
YR		 1361 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1362 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1363 } else {/* PFC support */
1364 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1365 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1366 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
27d9129f
YR		 1367 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1368 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1369 /* Write pause and PFC registers */
1370 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1371 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1372 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1373 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374
9380bb9e
YR		 1375 }
1376
1377 /* Write pause and PFC registers */
1378 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1379 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1380 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1381
9380bb9e 1382
b8d6d082
YR		 1383 /* Set MAC address for source TX Pause/PFC frames */
1384 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1385 ((params->mac_addr[2] << 24) |
1386 (params->mac_addr[3] << 16) |
1387 (params->mac_addr[4] << 8) |
1388 (params->mac_addr[5])));
1389 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1390 ((params->mac_addr[0] << 8) |
1391 (params->mac_addr[1])));
9380bb9e 1392
b8d6d082
YR		 1393 udelay(30);
1394}
bcab15c5 1395
bcab15c5 1396
bcab15c5
VZ		 1397static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1398 u32 pfc_frames_sent[2],
1399 u32 pfc_frames_received[2])
1400{
1401 /* Read pfc statistic */
1402 struct bnx2x *bp = params->bp;
1403 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1404 u32 val_xon = 0;
1405 u32 val_xoff = 0;
1406
1407 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1408
1409 /* PFC received frames */
1410 val_xoff = REG_RD(bp, emac_base +
1411 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1412 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1413 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1414 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1415
1416 pfc_frames_received[0] = val_xon + val_xoff;
1417
1418 /* PFC received sent */
1419 val_xoff = REG_RD(bp, emac_base +
1420 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1421 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1422 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1423 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1424
1425 pfc_frames_sent[0] = val_xon + val_xoff;
1426}
1427
b8d6d082 1428/* Read pfc statistic*/
bcab15c5
VZ		 1429void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1430 u32 pfc_frames_sent[2],
1431 u32 pfc_frames_received[2])
1432{
1433 /* Read pfc statistic */
1434 struct bnx2x *bp = params->bp;
b8d6d082 1435
bcab15c5
VZ		 1436 DP(NETIF_MSG_LINK, "pfc statistic\n");
1437
1438 if (!vars->link_up)
1439 return;
1440
de0396f4 1441 if (vars->mac_type == MAC_TYPE_EMAC) {
b8d6d082 1442 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
bcab15c5
VZ		 1443 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1444 pfc_frames_received);
bcab15c5
VZ		 1445 }
1446}
1447/******************************************************************/
1448/* MAC/PBF section */
1449/******************************************************************/
55386fe8
YR		 1450static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1451 u32 emac_base)
a198c142 1452{
55386fe8
YR		 1453 u32 new_mode, cur_mode;
1454 u32 clc_cnt;
8f73f0b9 1455 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
a198c142
YR		 1456 * (a value of 49==0x31) and make sure that the AUTO poll is off
1457 */
55386fe8 1458 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
a198c142 1459
3c9ada22 1460 if (USES_WARPCORE(bp))
55386fe8 1461 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
3c9ada22 1462 else
55386fe8 1463 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
a198c142 1464
55386fe8
YR		 1465 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1466 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1467 return;
1468
1469 new_mode = cur_mode &
1470 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1471 new_mode |= clc_cnt;
1472 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
a198c142 1473
55386fe8
YR		 1474 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1475 cur_mode, new_mode);
1476 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
a198c142
YR		 1477 udelay(40);
1478}
55386fe8
YR		 1479
1480static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1481 struct link_params *params)
1482{
1483 u8 phy_index;
1484 /* Set mdio clock per phy */
1485 for (phy_index = INT_PHY; phy_index < params->num_phys;
1486 phy_index++)
1487 bnx2x_set_mdio_clk(bp, params->chip_id,
1488 params->phy[phy_index].mdio_ctrl);
1489}
1490
2f751a80
YR		 1491static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1492{
1493 u32 port4mode_ovwr_val;
1494 /* Check 4-port override enabled */
1495 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1496 if (port4mode_ovwr_val & (1<<0)) {
1497 /* Return 4-port mode override value */
1498 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1499 }
1500 /* Return 4-port mode from input pin */
1501 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1502}
a198c142 1503
ea4e040a 1504static void bnx2x_emac_init(struct link_params *params,
cd88ccee 1505 struct link_vars *vars)
ea4e040a
YR		 1506{
1507 /* reset and unreset the emac core */
1508 struct bnx2x *bp = params->bp;
1509 u8 port = params->port;
1510 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1511 u32 val;
1512 u16 timeout;
1513
1514 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
cd88ccee 1515 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 1516 udelay(5);
1517 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 1518 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 1519
1520 /* init emac - use read-modify-write */
1521 /* self clear reset */
1522 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 1523 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 1524
1525 timeout = 200;
3196a88a 1526 do {
ea4e040a
YR		 1527 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1529 if (!timeout) {
1530 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1531 return;
1532 }
1533 timeout--;
3196a88a 1534 } while (val & EMAC_MODE_RESET);
55386fe8
YR		 1535
1536 bnx2x_set_mdio_emac_per_phy(bp, params);
ea4e040a
YR		 1537 /* Set mac address */
1538 val = ((params->mac_addr[0] << 8) |
1539 params->mac_addr[1]);
3196a88a 1540 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 1541
1542 val = ((params->mac_addr[2] << 24) |
1543 (params->mac_addr[3] << 16) |
1544 (params->mac_addr[4] << 8) |
1545 params->mac_addr[5]);
3196a88a 1546 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 1547}
1548
9380bb9e
YR		 1549static void bnx2x_set_xumac_nig(struct link_params *params,
1550 u16 tx_pause_en,
1551 u8 enable)
1552{
1553 struct bnx2x *bp = params->bp;
1554
1555 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1556 enable);
1557 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1558 enable);
1559 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1560 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1561}
1562
d3a8f13b 1563static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
ce7c0489
YR		 1564{
1565 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
d3a8f13b 1566 u32 val;
ce7c0489
YR		 1567 struct bnx2x *bp = params->bp;
1568 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1569 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1570 return;
d3a8f13b
YR		 1571 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1572 if (en)
1573 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1574 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1575 else
1576 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1577 UMAC_COMMAND_CONFIG_REG_RX_ENA);
ce7c0489 1578 /* Disable RX and TX */
d3a8f13b 1579 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
ce7c0489
YR		 1580}
1581
9380bb9e
YR		 1582static void bnx2x_umac_enable(struct link_params *params,
1583 struct link_vars *vars, u8 lb)
1584{
1585 u32 val;
1586 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1587 struct bnx2x *bp = params->bp;
1588 /* Reset UMAC */
1589 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1590 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
d231023e 1591 usleep_range(1000, 2000);
9380bb9e
YR		 1592
1593 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1594 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1595
1596 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1597
9380bb9e
YR		 1598 /* This register opens the gate for the UMAC despite its name */
1599 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1600
1601 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1602 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1603 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1604 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1605 switch (vars->line_speed) {
1606 case SPEED_10:
1607 val |= (0<<2);
1608 break;
1609 case SPEED_100:
1610 val |= (1<<2);
1611 break;
1612 case SPEED_1000:
1613 val |= (2<<2);
1614 break;
1615 case SPEED_2500:
1616 val |= (3<<2);
1617 break;
1618 default:
1619 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1620 vars->line_speed);
1621 break;
1622 }
9d5b36be
YR		 1623 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1624 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1625
1626 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1627 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1628
e18c56b2
MY		 1629 if (vars->duplex == DUPLEX_HALF)
1630 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1631
9380bb9e
YR		 1632 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1633 udelay(50);
1634
26964bb7
YM		 1635 /* Configure UMAC for EEE */
1636 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1637 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1638 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1639 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1640 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1641 } else {
1642 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1643 }
1644
b8d6d082
YR		 1645 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1646 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1647 ((params->mac_addr[2] << 24) |
1648 (params->mac_addr[3] << 16) |
1649 (params->mac_addr[4] << 8) |
1650 (params->mac_addr[5])));
1651 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1652 ((params->mac_addr[0] << 8) |
1653 (params->mac_addr[1])));
1654
9380bb9e
YR		 1655 /* Enable RX and TX */
1656 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1657 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
3c9ada22 1658 UMAC_COMMAND_CONFIG_REG_RX_ENA;
9380bb9e
YR		 1659 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1660 udelay(50);
1661
1662 /* Remove SW Reset */
1663 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1664
1665 /* Check loopback mode */
1666 if (lb)
1667 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1668 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1669
8f73f0b9 1670 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
9380bb9e
YR		 1671 * length used by the MAC receive logic to check frames.
1672 */
1673 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1674 bnx2x_set_xumac_nig(params,
1675 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1676 vars->mac_type = MAC_TYPE_UMAC;
1677
1678}
1679
9380bb9e 1680/* Define the XMAC mode */
ce7c0489 1681static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
9380bb9e 1682{
ce7c0489 1683 struct bnx2x *bp = params->bp;
9380bb9e
YR		 1684 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1685
8f73f0b9 1686 /* In 4-port mode, need to set the mode only once, so if XMAC is
2f751a80
YR		 1687 * already out of reset, it means the mode has already been set,
1688 * and it must not* reset the XMAC again, since it controls both
1689 * ports of the path
1690 */
9380bb9e 1691
4e7b4997
YR		 1692 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1693 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1694 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1695 is_port4mode &&
ce7c0489 1696 (REG_RD(bp, MISC_REG_RESET_REG_2) &
9380bb9e 1697 MISC_REGISTERS_RESET_REG_2_XMAC)) {
94f05b0f
JP		 1698 DP(NETIF_MSG_LINK,
1699 "XMAC already out of reset in 4-port mode\n");
9380bb9e
YR		 1700 return;
1701 }
1702
1703 /* Hard reset */
1704 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1705 MISC_REGISTERS_RESET_REG_2_XMAC);
d231023e 1706 usleep_range(1000, 2000);
9380bb9e
YR		 1707
1708 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1709 MISC_REGISTERS_RESET_REG_2_XMAC);
1710 if (is_port4mode) {
1711 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1712
8f73f0b9 1713 /* Set the number of ports on the system side to up to 2 */
9380bb9e
YR		 1714 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1715
1716 /* Set the number of ports on the Warp Core to 10G */
1717 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1718 } else {
8f73f0b9 1719 /* Set the number of ports on the system side to 1 */
9380bb9e
YR		 1720 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1721 if (max_speed == SPEED_10000) {
94f05b0f
JP		 1722 DP(NETIF_MSG_LINK,
1723 "Init XMAC to 10G x 1 port per path\n");
9380bb9e
YR		 1724 /* Set the number of ports on the Warp Core to 10G */
1725 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1726 } else {
94f05b0f
JP		 1727 DP(NETIF_MSG_LINK,
1728 "Init XMAC to 20G x 2 ports per path\n");
9380bb9e
YR		 1729 /* Set the number of ports on the Warp Core to 20G */
1730 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1731 }
1732 }
1733 /* Soft reset */
1734 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1735 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
d231023e 1736 usleep_range(1000, 2000);
9380bb9e
YR		 1737
1738 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1739 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1740
1741}
1742
d3a8f13b 1743static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
9380bb9e
YR		 1744{
1745 u8 port = params->port;
1746 struct bnx2x *bp = params->bp;
b5077662 1747 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
d3a8f13b 1748 u32 val;
9380bb9e
YR		 1749
1750 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1751 MISC_REGISTERS_RESET_REG_2_XMAC) {
8f73f0b9 1752 /* Send an indication to change the state in the NIG back to XON
b5077662
YR		 1753 * Clearing this bit enables the next set of this bit to get
1754 * rising edge
1755 */
1756 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1757 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1758 (pfc_ctrl & ~(1<<1)));
1759 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1760 (pfc_ctrl | (1<<1)));
9380bb9e 1761 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
d3a8f13b
YR		 1762 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1763 if (en)
1764 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1765 else
1766 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1767 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
9380bb9e
YR		 1768 }
1769}
1770
1771static int bnx2x_xmac_enable(struct link_params *params,
1772 struct link_vars *vars, u8 lb)
1773{
1774 u32 val, xmac_base;
1775 struct bnx2x *bp = params->bp;
1776 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1777
1778 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1779
ce7c0489 1780 bnx2x_xmac_init(params, vars->line_speed);
9380bb9e 1781
8f73f0b9 1782 /* This register determines on which events the MAC will assert
9380bb9e
YR		 1783 * error on the i/f to the NIG along w/ EOP.
1784 */
1785
8f73f0b9 1786 /* This register tells the NIG whether to send traffic to UMAC
9380bb9e
YR		 1787 * or XMAC
1788 */
1789 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1790
4e7b4997
YR		 1791 /* When XMAC is in XLGMII mode, disable sending idles for fault
1792 * detection.
1793 */
1794 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1795 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1796 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1797 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1798 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1799 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1800 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1801 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1802 }
9380bb9e
YR		 1803 /* Set Max packet size */
1804 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1805
1806 /* CRC append for Tx packets */
1807 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1808
1809 /* update PFC */
1810 bnx2x_update_pfc_xmac(params, vars, 0);
1811
c8c60d88
YM		 1812 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1813 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1814 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1815 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1816 } else {
1817 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1818 }
1819
9380bb9e
YR		 1820 /* Enable TX and RX */
1821 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1822
4e7b4997
YR		 1823 /* Set MAC in XLGMII mode for dual-mode */
1824 if ((vars->line_speed == SPEED_20000) &&
1825 (params->phy[INT_PHY].supported &
1826 SUPPORTED_20000baseKR2_Full))
1827 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1828
9380bb9e
YR		 1829 /* Check loopback mode */
1830 if (lb)
4d7e25d6 1831 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
9380bb9e
YR		 1832 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1833 bnx2x_set_xumac_nig(params,
1834 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1835
1836 vars->mac_type = MAC_TYPE_XMAC;
1837
1838 return 0;
1839}
2f751a80 1840
fcf5b650 1841static int bnx2x_emac_enable(struct link_params *params,
9045f6b4 1842 struct link_vars *vars, u8 lb)
ea4e040a
YR		 1843{
1844 struct bnx2x *bp = params->bp;
1845 u8 port = params->port;
1846 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1847 u32 val;
1848
1849 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1850
de6f3377
YR		 1851 /* Disable BMAC */
1852 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1853 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1854
ea4e040a
YR		 1855 /* enable emac and not bmac */
1856 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1857
ea4e040a
YR		 1858 /* ASIC */
1859 if (vars->phy_flags & PHY_XGXS_FLAG) {
1860 u32 ser_lane = ((params->lane_config &
cd88ccee
YR		 1861 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1862 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
ea4e040a
YR		 1863
1864 DP(NETIF_MSG_LINK, "XGXS\n");
1865 /* select the master lanes (out of 0-3) */
cd88ccee 1866 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
ea4e040a 1867 /* select XGXS */
cd88ccee 1868 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
ea4e040a
YR		 1869
1870 } else { /* SerDes */
1871 DP(NETIF_MSG_LINK, "SerDes\n");
1872 /* select SerDes */
cd88ccee 1873 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
ea4e040a
YR		 1874 }
1875
811a2f2d 1876 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
cd88ccee 1877 EMAC_RX_MODE_RESET);
811a2f2d 1878 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
cd88ccee 1879 EMAC_TX_MODE_RESET);
ea4e040a 1880
ea4e040a
YR		 1881 /* pause enable/disable */
1882 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1883 EMAC_RX_MODE_FLOW_EN);
ea4e040a
YR		 1884
1885 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
bcab15c5
VZ		 1886 (EMAC_TX_MODE_EXT_PAUSE_EN |
1887 EMAC_TX_MODE_FLOW_EN));
1888 if (!(params->feature_config_flags &
1889 FEATURE_CONFIG_PFC_ENABLED)) {
1890 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1891 bnx2x_bits_en(bp, emac_base +
1892 EMAC_REG_EMAC_RX_MODE,
1893 EMAC_RX_MODE_FLOW_EN);
1894
1895 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1896 bnx2x_bits_en(bp, emac_base +
1897 EMAC_REG_EMAC_TX_MODE,
1898 (EMAC_TX_MODE_EXT_PAUSE_EN |
1899 EMAC_TX_MODE_FLOW_EN));
1900 } else
1901 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1902 EMAC_TX_MODE_FLOW_EN);
ea4e040a
YR		 1903
1904 /* KEEP_VLAN_TAG, promiscuous */
1905 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1906 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
bcab15c5 1907
8f73f0b9 1908 /* Setting this bit causes MAC control frames (except for pause
2cf7acf9
YR		 1909 * frames) to be passed on for processing. This setting has no
1910 * affect on the operation of the pause frames. This bit effects
1911 * all packets regardless of RX Parser packet sorting logic.
1912 * Turn the PFC off to make sure we are in Xon state before
1913 * enabling it.
1914 */
bcab15c5
VZ		 1915 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1916 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1917 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1918 /* Enable PFC again */
1919 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1920 EMAC_REG_RX_PFC_MODE_RX_EN |
1921 EMAC_REG_RX_PFC_MODE_TX_EN |
1922 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1923
1924 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1925 ((0x0101 <<
1926 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1927 (0x00ff <<
1928 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1929 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1930 }
3196a88a 1931 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 1932
1933 /* Set Loopback */
1934 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1935 if (lb)
1936 val |= 0x810;
1937 else
1938 val &= ~0x810;
3196a88a 1939 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 1940
d231023e 1941 /* Enable emac */
6c55c3cd
EG		 1942 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1943
d231023e 1944 /* Enable emac for jumbo packets */
3196a88a 1945 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 1946 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1947 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1948
d231023e 1949 /* Strip CRC */
ea4e040a
YR		 1950 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1951
d231023e 1952 /* Disable the NIG in/out to the bmac */
ea4e040a
YR		 1953 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1954 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1955 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1956
d231023e 1957 /* Enable the NIG in/out to the emac */
ea4e040a
YR		 1958 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1959 val = 0;
bcab15c5
VZ		 1960 if ((params->feature_config_flags &
1961 FEATURE_CONFIG_PFC_ENABLED) ||
1962 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 1963 val = 1;
1964
1965 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1966 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1967
02a23165 1968 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 1969
1970 vars->mac_type = MAC_TYPE_EMAC;
1971 return 0;
1972}
1973
bcab15c5
VZ		 1974static void bnx2x_update_pfc_bmac1(struct link_params *params,
1975 struct link_vars *vars)
1976{
1977 u32 wb_data[2];
1978 struct bnx2x *bp = params->bp;
1979 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1980 NIG_REG_INGRESS_BMAC0_MEM;
1981
1982 u32 val = 0x14;
1983 if ((!(params->feature_config_flags &
1984 FEATURE_CONFIG_PFC_ENABLED)) &&
1985 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1986 /* Enable BigMAC to react on received Pause packets */
1987 val |= (1<<5);
1988 wb_data[0] = val;
1989 wb_data[1] = 0;
1990 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1991
d231023e 1992 /* TX control */
bcab15c5
VZ		 1993 val = 0xc0;
1994 if (!(params->feature_config_flags &
1995 FEATURE_CONFIG_PFC_ENABLED) &&
1996 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1997 val |= 0x800000;
1998 wb_data[0] = val;
1999 wb_data[1] = 0;
2000 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2001}
2002
2003static void bnx2x_update_pfc_bmac2(struct link_params *params,
2004 struct link_vars *vars,
2005 u8 is_lb)
f2e0899f 2006{
8f73f0b9 2007 /* Set rx control: Strip CRC and enable BigMAC to relay
f2e0899f
DK		 2008 * control packets to the system as well
2009 */
2010 u32 wb_data[2];
2011 struct bnx2x *bp = params->bp;
2012 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2013 NIG_REG_INGRESS_BMAC0_MEM;
2014 u32 val = 0x14;
ea4e040a 2015
bcab15c5
VZ		 2016 if ((!(params->feature_config_flags &
2017 FEATURE_CONFIG_PFC_ENABLED)) &&
2018 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
f2e0899f
DK		 2019 /* Enable BigMAC to react on received Pause packets */
2020 val |= (1<<5);
2021 wb_data[0] = val;
2022 wb_data[1] = 0;
cd88ccee 2023 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
f2e0899f 2024 udelay(30);
ea4e040a 2025
f2e0899f
DK		 2026 /* Tx control */
2027 val = 0xc0;
bcab15c5
VZ		 2028 if (!(params->feature_config_flags &
2029 FEATURE_CONFIG_PFC_ENABLED) &&
2030 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
f2e0899f
DK		 2031 val |= 0x800000;
2032 wb_data[0] = val;
2033 wb_data[1] = 0;
bcab15c5
VZ		 2034 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2035
2036 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2037 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2038 /* Enable PFC RX & TX & STATS and set 8 COS */
2039 wb_data[0] = 0x0;
2040 wb_data[0] |= (1<<0); /* RX */
2041 wb_data[0] |= (1<<1); /* TX */
2042 wb_data[0] |= (1<<2); /* Force initial Xon */
2043 wb_data[0] |= (1<<3); /* 8 cos */
2044 wb_data[0] |= (1<<5); /* STATS */
2045 wb_data[1] = 0;
2046 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2047 wb_data, 2);
2048 /* Clear the force Xon */
2049 wb_data[0] &= ~(1<<2);
2050 } else {
2051 DP(NETIF_MSG_LINK, "PFC is disabled\n");
d231023e 2052 /* Disable PFC RX & TX & STATS and set 8 COS */
bcab15c5
VZ		 2053 wb_data[0] = 0x8;
2054 wb_data[1] = 0;
2055 }
2056
2057 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
f2e0899f 2058
8f73f0b9 2059 /* Set Time (based unit is 512 bit time) between automatic
2cf7acf9
YR		 2060 * re-sending of PP packets amd enable automatic re-send of
2061 * Per-Priroity Packet as long as pp_gen is asserted and
2062 * pp_disable is low.
2063 */
f2e0899f 2064 val = 0x8000;
bcab15c5
VZ		 2065 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2066 val |= (1<<16); /* enable automatic re-send */
2067
f2e0899f
DK		 2068 wb_data[0] = val;
2069 wb_data[1] = 0;
2070 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
cd88ccee 2071 wb_data, 2);
f2e0899f
DK		 2072
2073 /* mac control */
2074 val = 0x3; /* Enable RX and TX */
2075 if (is_lb) {
2076 val |= 0x4; /* Local loopback */
2077 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2078 }
bcab15c5
VZ		 2079 /* When PFC enabled, Pass pause frames towards the NIG. */
2080 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2081 val |= ((1<<6)|(1<<5));
f2e0899f
DK		 2082
2083 wb_data[0] = val;
2084 wb_data[1] = 0;
cd88ccee 2085 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 2086}
2087
619c5cb6
VZ		 2088/******************************************************************************
2089* Description:
2090* This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2091* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2092******************************************************************************/
d231023e
YM		 2093static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2094 u8 cos_entry,
2095 u32 priority_mask, u8 port)
619c5cb6
VZ		 2096{
2097 u32 nig_reg_rx_priority_mask_add = 0;
2098
2099 switch (cos_entry) {
2100 case 0:
2101 nig_reg_rx_priority_mask_add = (port) ?
2102 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2103 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2104 break;
2105 case 1:
2106 nig_reg_rx_priority_mask_add = (port) ?
2107 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2108 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2109 break;
2110 case 2:
2111 nig_reg_rx_priority_mask_add = (port) ?
2112 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2113 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2114 break;
2115 case 3:
2116 if (port)
2117 return -EINVAL;
2118 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2119 break;
2120 case 4:
2121 if (port)
2122 return -EINVAL;
2123 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2124 break;
2125 case 5:
2126 if (port)
2127 return -EINVAL;
2128 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2129 break;
2130 }
2131
2132 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2133
2134 return 0;
2135}
b8d6d082
YR		 2136static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2137{
2138 struct bnx2x *bp = params->bp;
2139
2140 REG_WR(bp, params->shmem_base +
2141 offsetof(struct shmem_region,
2142 port_mb[params->port].link_status), link_status);
2143}
2144
4e7b4997
YR		 2145static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2146{
2147 struct bnx2x *bp = params->bp;
2148
2149 if (SHMEM2_HAS(bp, link_attr_sync))
2150 REG_WR(bp, params->shmem2_base +
2151 offsetof(struct shmem2_region,
2152 link_attr_sync[params->port]), link_attr);
2153}
2154
bcab15c5
VZ		 2155static void bnx2x_update_pfc_nig(struct link_params *params,
2156 struct link_vars *vars,
2157 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2158{
2159 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
127302bb 2160 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
bcab15c5 2161 u32 pkt_priority_to_cos = 0;
bcab15c5 2162 struct bnx2x *bp = params->bp;
9380bb9e
YR		 2163 u8 port = params->port;
2164
bcab15c5
VZ		 2165 int set_pfc = params->feature_config_flags &
2166 FEATURE_CONFIG_PFC_ENABLED;
2167 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2168
8f73f0b9 2169 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
bcab15c5
VZ		 2170 * MAC control frames (that are not pause packets)
2171 * will be forwarded to the XCM.
2172 */
127302bb
YR		 2173 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2174 NIG_REG_LLH0_XCM_MASK);
8f73f0b9 2175 /* NIG params will override non PFC params, since it's possible to
bcab15c5
VZ		 2176 * do transition from PFC to SAFC
2177 */
2178 if (set_pfc) {
2179 pause_enable = 0;
2180 llfc_out_en = 0;
2181 llfc_enable = 0;
9380bb9e
YR		 2182 if (CHIP_IS_E3(bp))
2183 ppp_enable = 0;
2184 else
503976e9 2185 ppp_enable = 1;
bcab15c5
VZ		 2186 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2187 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
127302bb
YR		 2188 xcm_out_en = 0;
2189 hwpfc_enable = 1;
bcab15c5
VZ		 2190 } else {
2191 if (nig_params) {
2192 llfc_out_en = nig_params->llfc_out_en;
2193 llfc_enable = nig_params->llfc_enable;
2194 pause_enable = nig_params->pause_enable;
8f73f0b9 2195 } else /* Default non PFC mode - PAUSE */
bcab15c5
VZ		 2196 pause_enable = 1;
2197
2198 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2199 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
127302bb 2200 xcm_out_en = 1;
bcab15c5
VZ		 2201 }
2202
9380bb9e
YR		 2203 if (CHIP_IS_E3(bp))
2204 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2205 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
bcab15c5
VZ		 2206 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2207 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2208 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2209 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2210 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2211 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2212
2213 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2214 NIG_REG_PPP_ENABLE_0, ppp_enable);
2215
2216 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2217 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2218
127302bb
YR		 2219 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2220 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
bcab15c5 2221
d231023e 2222 /* Output enable for RX_XCM # IF */
127302bb
YR		 2223 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2224 NIG_REG_XCM0_OUT_EN, xcm_out_en);
bcab15c5
VZ		 2225
2226 /* HW PFC TX enable */
127302bb
YR		 2227 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2228 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
bcab15c5 2229
bcab15c5 2230 if (nig_params) {
619c5cb6 2231 u8 i = 0;
bcab15c5
VZ		 2232 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2233
619c5cb6
VZ		 2234 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2235 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2236 nig_params->rx_cos_priority_mask[i], port);
bcab15c5
VZ		 2237
2238 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2239 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2240 nig_params->llfc_high_priority_classes);
2241
2242 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2243 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2244 nig_params->llfc_low_priority_classes);
2245 }
2246 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2247 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2248 pkt_priority_to_cos);
2249}
2250
9380bb9e 2251int bnx2x_update_pfc(struct link_params *params,
bcab15c5
VZ		 2252 struct link_vars *vars,
2253 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2254{
8f73f0b9 2255 /* The PFC and pause are orthogonal to one another, meaning when
bcab15c5
VZ		 2256 * PFC is enabled, the pause are disabled, and when PFC is
2257 * disabled, pause are set according to the pause result.
2258 */
2259 u32 val;
2260 struct bnx2x *bp = params->bp;
9380bb9e
YR		 2261 int bnx2x_status = 0;
2262 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
b8d6d082
YR		 2263
2264 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2265 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2266 else
2267 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2268
2269 bnx2x_update_mng(params, vars->link_status);
2270
d231023e 2271 /* Update NIG params */
bcab15c5
VZ		 2272 bnx2x_update_pfc_nig(params, vars, pfc_params);
2273
bcab15c5 2274 if (!vars->link_up)
9380bb9e 2275 return bnx2x_status;
bcab15c5
VZ		 2276
2277 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
375944cb
YR		 2278
2279 if (CHIP_IS_E3(bp)) {
2280 if (vars->mac_type == MAC_TYPE_XMAC)
2281 bnx2x_update_pfc_xmac(params, vars, 0);
2282 } else {
9380bb9e
YR		 2283 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2284 if ((val &
3c9ada22 2285 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
9380bb9e
YR		 2286 == 0) {
2287 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2288 bnx2x_emac_enable(params, vars, 0);
2289 return bnx2x_status;
2290 }
9380bb9e
YR		 2291 if (CHIP_IS_E2(bp))
2292 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2293 else
2294 bnx2x_update_pfc_bmac1(params, vars);
2295
2296 val = 0;
2297 if ((params->feature_config_flags &
2298 FEATURE_CONFIG_PFC_ENABLED) ||
2299 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2300 val = 1;
2301 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2302 }
2303 return bnx2x_status;
bcab15c5 2304}
f2e0899f 2305
fcf5b650
YR		 2306static int bnx2x_bmac1_enable(struct link_params *params,
2307 struct link_vars *vars,
2308 u8 is_lb)
ea4e040a
YR		 2309{
2310 struct bnx2x *bp = params->bp;
2311 u8 port = params->port;
2312 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2313 NIG_REG_INGRESS_BMAC0_MEM;
2314 u32 wb_data[2];
2315 u32 val;
2316
f2e0899f 2317 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
ea4e040a
YR		 2318
2319 /* XGXS control */
2320 wb_data[0] = 0x3c;
2321 wb_data[1] = 0;
cd88ccee
YR		 2322 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2323 wb_data, 2);
ea4e040a 2324
d231023e 2325 /* TX MAC SA */
ea4e040a
YR		 2326 wb_data[0] = ((params->mac_addr[2] << 24) |
2327 (params->mac_addr[3] << 16) |
2328 (params->mac_addr[4] << 8) |
2329 params->mac_addr[5]);
2330 wb_data[1] = ((params->mac_addr[0] << 8) |
2331 params->mac_addr[1]);
cd88ccee 2332 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
ea4e040a 2333
d231023e 2334 /* MAC control */
ea4e040a
YR		 2335 val = 0x3;
2336 if (is_lb) {
2337 val |= 0x4;
2338 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2339 }
2340 wb_data[0] = val;
2341 wb_data[1] = 0;
cd88ccee 2342 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
ea4e040a 2343
d231023e 2344 /* Set rx mtu */
ea4e040a
YR		 2345 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2346 wb_data[1] = 0;
cd88ccee 2347 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
ea4e040a 2348
bcab15c5 2349 bnx2x_update_pfc_bmac1(params, vars);
ea4e040a 2350
d231023e 2351 /* Set tx mtu */
ea4e040a
YR		 2352 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2353 wb_data[1] = 0;
cd88ccee 2354 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
ea4e040a 2355
d231023e 2356 /* Set cnt max size */
ea4e040a
YR		 2357 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2358 wb_data[1] = 0;
cd88ccee 2359 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
ea4e040a 2360
d231023e 2361 /* Configure SAFC */
ea4e040a
YR		 2362 wb_data[0] = 0x1000200;
2363 wb_data[1] = 0;
2364 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2365 wb_data, 2);
f2e0899f
DK		 2366
2367 return 0;
2368}
2369
fcf5b650
YR		 2370static int bnx2x_bmac2_enable(struct link_params *params,
2371 struct link_vars *vars,
2372 u8 is_lb)
f2e0899f
DK		 2373{
2374 struct bnx2x *bp = params->bp;
2375 u8 port = params->port;
2376 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2377 NIG_REG_INGRESS_BMAC0_MEM;
2378 u32 wb_data[2];
2379
2380 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2381
2382 wb_data[0] = 0;
2383 wb_data[1] = 0;
cd88ccee 2384 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 2385 udelay(30);
2386
2387 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2388 wb_data[0] = 0x3c;
2389 wb_data[1] = 0;
cd88ccee
YR		 2390 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2391 wb_data, 2);
f2e0899f
DK		 2392
2393 udelay(30);
2394
d231023e 2395 /* TX MAC SA */
f2e0899f
DK		 2396 wb_data[0] = ((params->mac_addr[2] << 24) |
2397 (params->mac_addr[3] << 16) |
2398 (params->mac_addr[4] << 8) |
2399 params->mac_addr[5]);
2400 wb_data[1] = ((params->mac_addr[0] << 8) |
2401 params->mac_addr[1]);
2402 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
cd88ccee 2403 wb_data, 2);
f2e0899f
DK		 2404
2405 udelay(30);
2406
2407 /* Configure SAFC */
2408 wb_data[0] = 0x1000200;
2409 wb_data[1] = 0;
2410 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
cd88ccee 2411 wb_data, 2);
f2e0899f
DK		 2412 udelay(30);
2413
d231023e 2414 /* Set RX MTU */
f2e0899f
DK		 2415 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2416 wb_data[1] = 0;
cd88ccee 2417 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
f2e0899f
DK		 2418 udelay(30);
2419
d231023e 2420 /* Set TX MTU */
f2e0899f
DK		 2421 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2422 wb_data[1] = 0;
cd88ccee 2423 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
f2e0899f 2424 udelay(30);
d231023e 2425 /* Set cnt max size */
f2e0899f
DK		 2426 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2427 wb_data[1] = 0;
cd88ccee 2428 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
f2e0899f 2429 udelay(30);
bcab15c5 2430 bnx2x_update_pfc_bmac2(params, vars, is_lb);
f2e0899f
DK		 2431
2432 return 0;
2433}
2434
fcf5b650
YR		 2435static int bnx2x_bmac_enable(struct link_params *params,
2436 struct link_vars *vars,
d3a8f13b 2437 u8 is_lb, u8 reset_bmac)
f2e0899f 2438{
fcf5b650
YR		 2439 int rc = 0;
2440 u8 port = params->port;
f2e0899f
DK		 2441 struct bnx2x *bp = params->bp;
2442 u32 val;
d231023e 2443 /* Reset and unreset the BigMac */
d3a8f13b
YR		 2444 if (reset_bmac) {
2445 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2446 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2447 usleep_range(1000, 2000);
2448 }
f2e0899f
DK		 2449
2450 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 2451 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
f2e0899f 2452
d231023e 2453 /* Enable access for bmac registers */
f2e0899f
DK		 2454 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2455
2456 /* Enable BMAC according to BMAC type*/
2457 if (CHIP_IS_E2(bp))
2458 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2459 else
2460 rc = bnx2x_bmac1_enable(params, vars, is_lb);
ea4e040a
YR		 2461 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2462 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2463 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2464 val = 0;
bcab15c5
VZ		 2465 if ((params->feature_config_flags &
2466 FEATURE_CONFIG_PFC_ENABLED) ||
2467 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 2468 val = 1;
2469 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2470 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2471 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2472 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2473 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2474 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2475
2476 vars->mac_type = MAC_TYPE_BMAC;
f2e0899f 2477 return rc;
ea4e040a
YR		 2478}
2479
d3a8f13b 2480static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
ea4e040a
YR		 2481{
2482 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
cd88ccee 2483 NIG_REG_INGRESS_BMAC0_MEM;
ea4e040a 2484 u32 wb_data[2];
3196a88a 2485 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a 2486
d3a8f13b
YR		 2487 if (CHIP_IS_E2(bp))
2488 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2489 else
2490 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
ea4e040a
YR		 2491 /* Only if the bmac is out of reset */
2492 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2493 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2494 nig_bmac_enable) {
d3a8f13b
YR		 2495 /* Clear Rx Enable bit in BMAC_CONTROL register */
2496 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2497 if (en)
2498 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2499 else
f2e0899f 2500 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
d3a8f13b 2501 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
d231023e 2502 usleep_range(1000, 2000);
ea4e040a
YR		 2503 }
2504}
2505
fcf5b650
YR		 2506static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2507 u32 line_speed)
ea4e040a
YR		 2508{
2509 struct bnx2x *bp = params->bp;
2510 u8 port = params->port;
2511 u32 init_crd, crd;
2512 u32 count = 1000;
ea4e040a 2513
d231023e 2514 /* Disable port */
ea4e040a
YR		 2515 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2516
d231023e 2517 /* Wait for init credit */
ea4e040a
YR		 2518 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2519 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2520 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2521
2522 while ((init_crd != crd) && count) {
d231023e 2523 usleep_range(5000, 10000);
ea4e040a
YR		 2524 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525 count--;
2526 }
2527 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2528 if (init_crd != crd) {
2529 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2530 init_crd, crd);
2531 return -EINVAL;
2532 }
2533
c0700f90 2534 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 2535 line_speed == SPEED_10 ||
2536 line_speed == SPEED_100 ||
2537 line_speed == SPEED_1000 ||
2538 line_speed == SPEED_2500) {
2539 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
d231023e 2540 /* Update threshold */
ea4e040a 2541 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
d231023e 2542 /* Update init credit */
cd88ccee 2543 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 2544
2545 } else {
2546 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2547 ETH_OVREHEAD)/16;
8c99e7b0 2548 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
d231023e 2549 /* Update threshold */
ea4e040a 2550 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
d231023e 2551 /* Update init credit */
ea4e040a 2552 switch (line_speed) {
ea4e040a
YR		 2553 case SPEED_10000:
2554 init_crd = thresh + 553 - 22;
2555 break;
ea4e040a
YR		 2556 default:
2557 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2558 line_speed);
2559 return -EINVAL;
ea4e040a
YR		 2560 }
2561 }
2562 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2563 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2564 line_speed, init_crd);
2565
d231023e 2566 /* Probe the credit changes */
ea4e040a 2567 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
d231023e 2568 usleep_range(5000, 10000);
ea4e040a
YR		 2569 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2570
d231023e 2571 /* Enable port */
ea4e040a
YR		 2572 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2573 return 0;
2574}
2575
e8920674
DK		 2576/**
2577 * bnx2x_get_emac_base - retrive emac base address
2cf7acf9 2578 *
e8920674
DK		 2579 * @bp: driver handle
2580 * @mdc_mdio_access: access type
2581 * @port: port id
2cf7acf9
YR		 2582 *
2583 * This function selects the MDC/MDIO access (through emac0 or
2584 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2585 * phy has a default access mode, which could also be overridden
2586 * by nvram configuration. This parameter, whether this is the
2587 * default phy configuration, or the nvram overrun
2588 * configuration, is passed here as mdc_mdio_access and selects
2589 * the emac_base for the CL45 read/writes operations
2590 */
c18aa15d
YR		 2591static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2592 u32 mdc_mdio_access, u8 port)
ea4e040a 2593{
c18aa15d
YR		 2594 u32 emac_base = 0;
2595 switch (mdc_mdio_access) {
2596 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2597 break;
2598 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2599 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2600 emac_base = GRCBASE_EMAC1;
2601 else
2602 emac_base = GRCBASE_EMAC0;
2603 break;
2604 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 2605 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2606 emac_base = GRCBASE_EMAC0;
2607 else
2608 emac_base = GRCBASE_EMAC1;
ea4e040a 2609 break;
c18aa15d
YR		 2610 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2611 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2612 break;
2613 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 2614 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 2615 break;
2616 default:
ea4e040a
YR		 2617 break;
2618 }
2619 return emac_base;
2620
2621}
2622
6583e33b
YR		 2623/******************************************************************/
2624/* CL22 access functions */
2625/******************************************************************/
2626static int bnx2x_cl22_write(struct bnx2x *bp,
2627 struct bnx2x_phy *phy,
2628 u16 reg, u16 val)
2629{
2630 u32 tmp, mode;
2631 u8 i;
2632 int rc = 0;
2633 /* Switch to CL22 */
2634 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2635 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2636 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2637
d231023e 2638 /* Address */
6583e33b
YR		 2639 tmp = ((phy->addr << 21) | (reg << 16) | val |
2640 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2641 EMAC_MDIO_COMM_START_BUSY);
2642 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2643
2644 for (i = 0; i < 50; i++) {
2645 udelay(10);
2646
2647 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2648 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2649 udelay(5);
2650 break;
2651 }
2652 }
2653 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2654 DP(NETIF_MSG_LINK, "write phy register failed\n");
2655 rc = -EFAULT;
2656 }
2657 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2658 return rc;
2659}
2660
2661static int bnx2x_cl22_read(struct bnx2x *bp,
2662 struct bnx2x_phy *phy,
2663 u16 reg, u16 *ret_val)
2664{
2665 u32 val, mode;
2666 u16 i;
2667 int rc = 0;
2668
2669 /* Switch to CL22 */
2670 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2671 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2672 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2673
d231023e 2674 /* Address */
6583e33b
YR		 2675 val = ((phy->addr << 21) | (reg << 16) |
2676 EMAC_MDIO_COMM_COMMAND_READ_22 |
2677 EMAC_MDIO_COMM_START_BUSY);
2678 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2679
2680 for (i = 0; i < 50; i++) {
2681 udelay(10);
2682
2683 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2684 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2685 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2686 udelay(5);
2687 break;
2688 }
2689 }
2690 if (val & EMAC_MDIO_COMM_START_BUSY) {
2691 DP(NETIF_MSG_LINK, "read phy register failed\n");
2692
2693 *ret_val = 0;
2694 rc = -EFAULT;
2695 }
2696 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2697 return rc;
2698}
2699
2cf7acf9
YR		 2700/******************************************************************/
2701/* CL45 access functions */
2702/******************************************************************/
a198c142
YR		 2703static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2704 u8 devad, u16 reg, u16 *ret_val)
ea4e040a 2705{
a198c142
YR		 2706 u32 val;
2707 u16 i;
fcf5b650 2708 int rc = 0;
55386fe8
YR		 2709 u32 chip_id;
2710 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2711 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2712 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2713 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2714 }
2715
157fa283
YR		 2716 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2717 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2718 EMAC_MDIO_STATUS_10MB);
d231023e 2719 /* Address */
a198c142 2720 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 2721 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2722 EMAC_MDIO_COMM_START_BUSY);
a198c142 2723 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 2724
2725 for (i = 0; i < 50; i++) {
2726 udelay(10);
2727
a198c142
YR		 2728 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2729 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
ea4e040a
YR		 2730 udelay(5);
2731 break;
2732 }
2733 }
a198c142
YR		 2734 if (val & EMAC_MDIO_COMM_START_BUSY) {
2735 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 2736 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
a198c142 2737 *ret_val = 0;
ea4e040a
YR		 2738 rc = -EFAULT;
2739 } else {
d231023e 2740 /* Data */
a198c142
YR		 2741 val = ((phy->addr << 21) | (devad << 16) |
2742 EMAC_MDIO_COMM_COMMAND_READ_45 |
ea4e040a 2743 EMAC_MDIO_COMM_START_BUSY);
a198c142 2744 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 2745
2746 for (i = 0; i < 50; i++) {
2747 udelay(10);
2748
a198c142 2749 val = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 2750 EMAC_REG_EMAC_MDIO_COMM);
a198c142
YR		 2751 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2752 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
ea4e040a
YR		 2753 break;
2754 }
2755 }
a198c142
YR		 2756 if (val & EMAC_MDIO_COMM_START_BUSY) {
2757 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 2758 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
a198c142 2759 *ret_val = 0;
ea4e040a
YR		 2760 rc = -EFAULT;
2761 }
2762 }
3c9ada22
YR		 2763 /* Work around for E3 A0 */
2764 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2765 phy->flags ^= FLAGS_DUMMY_READ;
2766 if (phy->flags & FLAGS_DUMMY_READ) {
2767 u16 temp_val;
2768 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2769 }
2770 }
ea4e040a 2771
157fa283
YR		 2772 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2773 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2774 EMAC_MDIO_STATUS_10MB);
ea4e040a
YR		 2775 return rc;
2776}
2777
a198c142
YR		 2778static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2779 u8 devad, u16 reg, u16 val)
ea4e040a 2780{
a198c142
YR		 2781 u32 tmp;
2782 u8 i;
fcf5b650 2783 int rc = 0;
55386fe8
YR		 2784 u32 chip_id;
2785 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2786 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2787 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2788 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2789 }
2790
157fa283
YR		 2791 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2792 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2793 EMAC_MDIO_STATUS_10MB);
ea4e040a 2794
d231023e 2795 /* Address */
a198c142 2796 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 2797 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2798 EMAC_MDIO_COMM_START_BUSY);
a198c142 2799 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 2800
2801 for (i = 0; i < 50; i++) {
2802 udelay(10);
2803
a198c142
YR		 2804 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2805 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
ea4e040a
YR		 2806 udelay(5);
2807 break;
2808 }
2809 }
a198c142
YR		 2810 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2811 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 2812 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a 2813 rc = -EFAULT;
ea4e040a 2814 } else {
d231023e 2815 /* Data */
a198c142
YR		 2816 tmp = ((phy->addr << 21) | (devad << 16) | val |
2817 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
ea4e040a 2818 EMAC_MDIO_COMM_START_BUSY);
a198c142 2819 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 2820
2821 for (i = 0; i < 50; i++) {
2822 udelay(10);
2823
a198c142 2824 tmp = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 2825 EMAC_REG_EMAC_MDIO_COMM);
a198c142
YR		 2826 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2827 udelay(5);
ea4e040a
YR		 2828 break;
2829 }
2830 }
a198c142
YR		 2831 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2832 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 2833 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 2834 rc = -EFAULT;
2835 }
2836 }
3c9ada22
YR		 2837 /* Work around for E3 A0 */
2838 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2839 phy->flags ^= FLAGS_DUMMY_READ;
2840 if (phy->flags & FLAGS_DUMMY_READ) {
2841 u16 temp_val;
2842 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2843 }
2844 }
157fa283
YR		 2845 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2846 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2847 EMAC_MDIO_STATUS_10MB);
3c9ada22
YR		 2848 return rc;
2849}
ec4010ec
YM		 2850
2851/******************************************************************/
2852/* EEE section */
2853/******************************************************************/
2854static u8 bnx2x_eee_has_cap(struct link_params *params)
2855{
2856 struct bnx2x *bp = params->bp;
2857
2858 if (REG_RD(bp, params->shmem2_base) <=
2859 offsetof(struct shmem2_region, eee_status[params->port]))
2860 return 0;
2861
2862 return 1;
2863}
2864
2865static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2866{
2867 switch (nvram_mode) {
2868 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2869 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2870 break;
2871 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2872 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2873 break;
2874 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2875 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2876 break;
2877 default:
2878 *idle_timer = 0;
2879 break;
2880 }
2881
2882 return 0;
2883}
2884
2885static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2886{
2887 switch (idle_timer) {
2888 case EEE_MODE_NVRAM_BALANCED_TIME:
2889 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2890 break;
2891 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2892 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2893 break;
2894 case EEE_MODE_NVRAM_LATENCY_TIME:
2895 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2896 break;
2897 default:
2898 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2899 break;
2900 }
2901
2902 return 0;
2903}
2904
2905static u32 bnx2x_eee_calc_timer(struct link_params *params)
2906{
2907 u32 eee_mode, eee_idle;
2908 struct bnx2x *bp = params->bp;
2909
2910 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2911 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2912 /* time value in eee_mode --> used directly*/
2913 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2914 } else {
2915 /* hsi value in eee_mode --> time */
2916 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2917 EEE_MODE_NVRAM_MASK,
2918 &eee_idle))
2919 return 0;
2920 }
2921 } else {
2922 /* hsi values in nvram --> time*/
2923 eee_mode = ((REG_RD(bp, params->shmem_base +
2924 offsetof(struct shmem_region, dev_info.
2925 port_feature_config[params->port].
2926 eee_power_mode)) &
2927 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2928 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2929
2930 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2931 return 0;
2932 }
2933
2934 return eee_idle;
2935}
2936
2937static int bnx2x_eee_set_timers(struct link_params *params,
2938 struct link_vars *vars)
2939{
2940 u32 eee_idle = 0, eee_mode;
2941 struct bnx2x *bp = params->bp;
2942
2943 eee_idle = bnx2x_eee_calc_timer(params);
2944
2945 if (eee_idle) {
2946 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2947 eee_idle);
2948 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2949 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2950 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2951 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2952 return -EINVAL;
2953 }
2954
2955 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2956 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2957 /* eee_idle in 1u --> eee_status in 16u */
2958 eee_idle >>= 4;
2959 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2960 SHMEM_EEE_TIME_OUTPUT_BIT;
2961 } else {
2962 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2963 return -EINVAL;
2964 vars->eee_status |= eee_mode;
2965 }
2966
2967 return 0;
2968}
2969
2970static int bnx2x_eee_initial_config(struct link_params *params,
2971 struct link_vars *vars, u8 mode)
2972{
2973 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2974
2975 /* Propogate params' bits --> vars (for migration exposure) */
2976 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2977 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2978 else
2979 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2980
2981 if (params->eee_mode & EEE_MODE_ADV_LPI)
2982 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2983 else
2984 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2985
2986 return bnx2x_eee_set_timers(params, vars);
2987}
2988
2989static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2990 struct link_params *params,
2991 struct link_vars *vars)
2992{
2993 struct bnx2x *bp = params->bp;
2994
2995 /* Make Certain LPI is disabled */
2996 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2997
2998 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2999
3000 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3001
3002 return 0;
3003}
3004
3005static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3006 struct link_params *params,
3007 struct link_vars *vars, u8 modes)
3008{
3009 struct bnx2x *bp = params->bp;
3010 u16 val = 0;
3011
3012 /* Mask events preventing LPI generation */
3013 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3014
3015 if (modes & SHMEM_EEE_10G_ADV) {
3016 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3017 val |= 0x8;
3018 }
3019 if (modes & SHMEM_EEE_1G_ADV) {
3020 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3021 val |= 0x4;
3022 }
3023
3024 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3025
3026 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3027 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3028
3029 return 0;
3030}
3031
3032static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3033{
3034 struct bnx2x *bp = params->bp;
3035
3036 if (bnx2x_eee_has_cap(params))
3037 REG_WR(bp, params->shmem2_base +
3038 offsetof(struct shmem2_region,
3039 eee_status[params->port]), eee_status);
3040}
3041
3042static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3043 struct link_params *params,
3044 struct link_vars *vars)
3045{
3046 struct bnx2x *bp = params->bp;
3047 u16 adv = 0, lp = 0;
3048 u32 lp_adv = 0;
3049 u8 neg = 0;
3050
3051 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3052 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3053
3054 if (lp & 0x2) {
3055 lp_adv |= SHMEM_EEE_100M_ADV;
3056 if (adv & 0x2) {
3057 if (vars->line_speed == SPEED_100)
3058 neg = 1;
3059 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3060 }
3061 }
3062 if (lp & 0x14) {
3063 lp_adv |= SHMEM_EEE_1G_ADV;
3064 if (adv & 0x14) {
3065 if (vars->line_speed == SPEED_1000)
3066 neg = 1;
3067 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3068 }
3069 }
3070 if (lp & 0x68) {
3071 lp_adv |= SHMEM_EEE_10G_ADV;
3072 if (adv & 0x68) {
3073 if (vars->line_speed == SPEED_10000)
3074 neg = 1;
3075 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3076 }
3077 }
3078
3079 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3080 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3081
3082 if (neg) {
3083 DP(NETIF_MSG_LINK, "EEE is active\n");
3084 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3085 }
3086
3087}
3088
3c9ada22
YR		 3089/******************************************************************/
3090/* BSC access functions from E3 */
3091/******************************************************************/
3092static void bnx2x_bsc_module_sel(struct link_params *params)
3093{
3094 int idx;
3095 u32 board_cfg, sfp_ctrl;
3096 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3097 struct bnx2x *bp = params->bp;
3098 u8 port = params->port;
3099 /* Read I2C output PINs */
3100 board_cfg = REG_RD(bp, params->shmem_base +
3101 offsetof(struct shmem_region,
3102 dev_info.shared_hw_config.board));
3103 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3104 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3105 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3106
3107 /* Read I2C output value */
3108 sfp_ctrl = REG_RD(bp, params->shmem_base +
3109 offsetof(struct shmem_region,
3110 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3111 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3112 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3113 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3114 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3115 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3116}
3117
3118static int bnx2x_bsc_read(struct link_params *params,
3119 struct bnx2x_phy *phy,
3120 u8 sl_devid,
3121 u16 sl_addr,
3122 u8 lc_addr,
3123 u8 xfer_cnt,
3124 u32 *data_array)
3125{
3126 u32 val, i;
3127 int rc = 0;
3128 struct bnx2x *bp = params->bp;
3129
3130 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3131 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3132 return -EINVAL;
3133 }
3134
3135 if (xfer_cnt > 16) {
3136 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137 xfer_cnt);
3138 return -EINVAL;
3139 }
3140 bnx2x_bsc_module_sel(params);
3141
3142 xfer_cnt = 16 - lc_addr;
3143
d231023e 3144 /* Enable the engine */
3c9ada22
YR		 3145 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146 val |= MCPR_IMC_COMMAND_ENABLE;
3147 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
d231023e 3149 /* Program slave device ID */
3c9ada22
YR		 3150 val = (sl_devid << 16) | sl_addr;
3151 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
d231023e 3153 /* Start xfer with 0 byte to update the address pointer ???*/
3c9ada22
YR		 3154 val = (MCPR_IMC_COMMAND_ENABLE) |
3155 (MCPR_IMC_COMMAND_WRITE_OP <<
3156 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
d231023e 3160 /* Poll for completion */
3c9ada22
YR		 3161 i = 0;
3162 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164 udelay(10);
3165 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166 if (i++ > 1000) {
3167 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168 i);
3169 rc = -EFAULT;
3170 break;
3171 }
3172 }
3173 if (rc == -EFAULT)
3174 return rc;
3175
d231023e 3176 /* Start xfer with read op */
3c9ada22
YR		 3177 val = (MCPR_IMC_COMMAND_ENABLE) |
3178 (MCPR_IMC_COMMAND_READ_OP <<
3179 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181 (xfer_cnt);
3182 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
d231023e 3184 /* Poll for completion */
3c9ada22
YR		 3185 i = 0;
3186 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188 udelay(10);
3189 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190 if (i++ > 1000) {
3191 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192 rc = -EFAULT;
3193 break;
3194 }
3195 }
3196 if (rc == -EFAULT)
3197 return rc;
3198
3199 for (i = (lc_addr >> 2); i < 4; i++) {
3200 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201#ifdef __BIG_ENDIAN
3202 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203 ((data_array[i] & 0x0000ff00) << 8) |
3204 ((data_array[i] & 0x00ff0000) >> 8) |
3205 ((data_array[i] & 0xff000000) >> 24);
3206#endif
3207 }
ea4e040a
YR		 3208 return rc;
3209}
3210
3c9ada22
YR		 3211static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212 u8 devad, u16 reg, u16 or_val)
3213{
3214 u16 val;
3215 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217}
3218
4e7b4997
YR		 3219static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220 struct bnx2x_phy *phy,
3221 u8 devad, u16 reg, u16 and_val)
3222{
3223 u16 val;
3224 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226}
3227
fcf5b650
YR		 3228int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229 u8 devad, u16 reg, u16 *ret_val)
e10bc84d
YR		 3230{
3231 u8 phy_index;
8f73f0b9 3232 /* Probe for the phy according to the given phy_addr, and execute
e10bc84d
YR		 3233 * the read request on it
3234 */
3235 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236 if (params->phy[phy_index].addr == phy_addr) {
3237 return bnx2x_cl45_read(params->bp,
3238 &params->phy[phy_index], devad,
3239 reg, ret_val);
3240 }
3241 }
3242 return -EINVAL;
3243}
3244
fcf5b650
YR		 3245int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246 u8 devad, u16 reg, u16 val)
e10bc84d
YR		 3247{
3248 u8 phy_index;
8f73f0b9 3249 /* Probe for the phy according to the given phy_addr, and execute
e10bc84d
YR		 3250 * the write request on it
3251 */
3252 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253 if (params->phy[phy_index].addr == phy_addr) {
3254 return bnx2x_cl45_write(params->bp,
3255 &params->phy[phy_index], devad,
3256 reg, val);
3257 }
3258 }
3259 return -EINVAL;
3260}
3c9ada22
YR		 3261static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262 struct link_params *params)
3263{
3264 u8 lane = 0;
3265 struct bnx2x *bp = params->bp;
3266 u32 path_swap, path_swap_ovr;
3267 u8 path, port;
3268
3269 path = BP_PATH(bp);
3270 port = params->port;
3271
3272 if (bnx2x_is_4_port_mode(bp)) {
3273 u32 port_swap, port_swap_ovr;
3274
8f73f0b9 3275 /* Figure out path swap value */
3c9ada22
YR		 3276 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277 if (path_swap_ovr & 0x1)
3278 path_swap = (path_swap_ovr & 0x2);
3279 else
3280 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282 if (path_swap)
3283 path = path ^ 1;
3284
8f73f0b9 3285 /* Figure out port swap value */
3c9ada22
YR		 3286 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287 if (port_swap_ovr & 0x1)
3288 port_swap = (port_swap_ovr & 0x2);
3289 else
3290 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292 if (port_swap)
3293 port = port ^ 1;
3294
3295 lane = (port<<1) + path;
d231023e 3296 } else { /* Two port mode - no port swap */
3c9ada22 3297
8f73f0b9 3298 /* Figure out path swap value */
3c9ada22
YR		 3299 path_swap_ovr =
3300 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301 if (path_swap_ovr & 0x1) {
3302 path_swap = (path_swap_ovr & 0x2);
3303 } else {
3304 path_swap =
3305 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306 }
3307 if (path_swap)
3308 path = path ^ 1;
3309
3310 lane = path << 1 ;
3311 }
3312 return lane;
3313}
e10bc84d 3314
ec146a6f
YR		 3315static void bnx2x_set_aer_mmd(struct link_params *params,
3316 struct bnx2x_phy *phy)
ea4e040a 3317{
ea4e040a 3318 u32 ser_lane;
f2e0899f
DK		 3319 u16 offset, aer_val;
3320 struct bnx2x *bp = params->bp;
ea4e040a
YR		 3321 ser_lane = ((params->lane_config &
3322 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
ec146a6f
YR		 3325 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326 (phy->addr + ser_lane) : 0;
3327
3c9ada22
YR		 3328 if (USES_WARPCORE(bp)) {
3329 aer_val = bnx2x_get_warpcore_lane(phy, params);
8f73f0b9 3330 /* In Dual-lane mode, two lanes are joined together,
3c9ada22
YR		 3331 * so in order to configure them, the AER broadcast method is
3332 * used here.
3333 * 0x200 is the broadcast address for lanes 0,1
3334 * 0x201 is the broadcast address for lanes 2,3
3335 */
3336 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337 aer_val = (aer_val >> 1) | 0x200;
3338 } else if (CHIP_IS_E2(bp))
82a0d475 3339 aer_val = 0x3800 + offset - 1;
f2e0899f
DK		 3340 else
3341 aer_val = 0x3800 + offset;
2f751a80 3342
cd2be89b 3343 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
cd88ccee 3344 MDIO_AER_BLOCK_AER_REG, aer_val);
ec146a6f 3345
ea4e040a
YR		 3346}
3347
de6eae1f
YR		 3348/******************************************************************/
3349/* Internal phy section */
3350/******************************************************************/
ea4e040a 3351
de6eae1f
YR		 3352static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353{
3354 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a 3355
de6eae1f
YR		 3356 /* Set Clause 22 */
3357 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359 udelay(500);
3360 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361 udelay(500);
3362 /* Set Clause 45 */
3363 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
ea4e040a
YR		 3364}
3365
de6eae1f 3366static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 3367{
de6eae1f 3368 u32 val;
ea4e040a 3369
de6eae1f 3370 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 3371
de6eae1f 3372 val = SERDES_RESET_BITS << (port*16);
c1b73990 3373
d231023e 3374 /* Reset and unreset the SerDes/XGXS */
de6eae1f
YR		 3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376 udelay(500);
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
ea4e040a 3378
de6eae1f 3379 bnx2x_set_serdes_access(bp, port);
ea4e040a 3380
cd88ccee
YR		 3381 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382 DEFAULT_PHY_DEV_ADDR);
de6eae1f
YR		 3383}
3384
a75bb001
YR		 3385static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386 struct link_params *params,
3387 u32 action)
3388{
3389 struct bnx2x *bp = params->bp;
3390 switch (action) {
3391 case PHY_INIT:
3392 /* Set correct devad */
3393 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395 phy->def_md_devad);
3396 break;
3397 }
3398}
3399
de6eae1f
YR		 3400static void bnx2x_xgxs_deassert(struct link_params *params)
3401{
3402 struct bnx2x *bp = params->bp;
3403 u8 port;
3404 u32 val;
3405 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406 port = params->port;
3407
3408 val = XGXS_RESET_BITS << (port*16);
3409
d231023e 3410 /* Reset and unreset the SerDes/XGXS */
de6eae1f
YR		 3411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412 udelay(500);
3413 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
a75bb001
YR		 3414 bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415 PHY_INIT);
de6eae1f
YR		 3416}
3417
9045f6b4
YR		 3418static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419 struct link_params *params, u16 *ieee_fc)
3420{
3421 struct bnx2x *bp = params->bp;
3422 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
8f73f0b9 3423 /* Resolve pause mode and advertisement Please refer to Table
9045f6b4
YR		 3424 * 28B-3 of the 802.3ab-1999 spec
3425 */
3426
3427 switch (phy->req_flow_ctrl) {
3428 case BNX2X_FLOW_CTRL_AUTO:
3429 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3430 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3431 else
3432 *ieee_fc |=
3433 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3434 break;
3435
3436 case BNX2X_FLOW_CTRL_TX:
3437 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3438 break;
3439
3440 case BNX2X_FLOW_CTRL_RX:
3441 case BNX2X_FLOW_CTRL_BOTH:
3442 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3443 break;
3444
3445 case BNX2X_FLOW_CTRL_NONE:
3446 default:
3447 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3448 break;
3449 }
3450 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3451}
3452
3453static void set_phy_vars(struct link_params *params,
3454 struct link_vars *vars)
3455{
3456 struct bnx2x *bp = params->bp;
3457 u8 actual_phy_idx, phy_index, link_cfg_idx;
3458 u8 phy_config_swapped = params->multi_phy_config &
3459 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3460 for (phy_index = INT_PHY; phy_index < params->num_phys;
3461 phy_index++) {
3462 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3463 actual_phy_idx = phy_index;
3464 if (phy_config_swapped) {
3465 if (phy_index == EXT_PHY1)
3466 actual_phy_idx = EXT_PHY2;
3467 else if (phy_index == EXT_PHY2)
3468 actual_phy_idx = EXT_PHY1;
3469 }
3470 params->phy[actual_phy_idx].req_flow_ctrl =
3471 params->req_flow_ctrl[link_cfg_idx];
3472
3473 params->phy[actual_phy_idx].req_line_speed =
3474 params->req_line_speed[link_cfg_idx];
3475
3476 params->phy[actual_phy_idx].speed_cap_mask =
3477 params->speed_cap_mask[link_cfg_idx];
a22f0788 3478
9045f6b4
YR		 3479 params->phy[actual_phy_idx].req_duplex =
3480 params->req_duplex[link_cfg_idx];
3481
3482 if (params->req_line_speed[link_cfg_idx] ==
3483 SPEED_AUTO_NEG)
3484 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3485
3486 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3487 " speed_cap_mask %x\n",
3488 params->phy[actual_phy_idx].req_flow_ctrl,
3489 params->phy[actual_phy_idx].req_line_speed,
3490 params->phy[actual_phy_idx].speed_cap_mask);
3491 }
3492}
3493
3494static void bnx2x_ext_phy_set_pause(struct link_params *params,
3495 struct bnx2x_phy *phy,
3496 struct link_vars *vars)
3497{
3498 u16 val;
3499 struct bnx2x *bp = params->bp;
d231023e 3500 /* Read modify write pause advertizing */
9045f6b4
YR		 3501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3502
3503 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3504
3505 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3506 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3507 if ((vars->ieee_fc &
3508 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3509 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3510 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3511 }
3512 if ((vars->ieee_fc &
3513 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3514 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3515 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3516 }
3517 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3518 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3519}
3520
3521static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3522{ /* LD LP */
3523 switch (pause_result) { /* ASYM P ASYM P */
3524 case 0xb: /* 1 0 1 1 */
3525 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3526 break;
3527
3528 case 0xe: /* 1 1 1 0 */
3529 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3530 break;
3531
3532 case 0x5: /* 0 1 0 1 */
3533 case 0x7: /* 0 1 1 1 */
3534 case 0xd: /* 1 1 0 1 */
3535 case 0xf: /* 1 1 1 1 */
3536 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3537 break;
3538
3539 default:
3540 break;
3541 }
3542 if (pause_result & (1<<0))
3543 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3544 if (pause_result & (1<<1))
3545 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
8f73f0b9 3546
9045f6b4
YR		 3547}
3548
9e7e8399
MY		 3549static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3550 struct link_params *params,
3551 struct link_vars *vars)
9045f6b4 3552{
9045f6b4
YR		 3553 u16 ld_pause; /* local */
3554 u16 lp_pause; /* link partner */
3555 u16 pause_result;
9e7e8399
MY		 3556 struct bnx2x *bp = params->bp;
3557 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3558 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3559 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
ca05f29c
YR		 3560 } else if (CHIP_IS_E3(bp) &&
3561 SINGLE_MEDIA_DIRECT(params)) {
3562 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3563 u16 gp_status, gp_mask;
3564 bnx2x_cl45_read(bp, phy,
3565 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3566 &gp_status);
3567 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3568 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3569 lane;
3570 if ((gp_status & gp_mask) == gp_mask) {
3571 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3572 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3573 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3574 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3575 } else {
3576 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3577 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3578 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3579 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3580 ld_pause = ((ld_pause &
3581 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3582 << 3);
3583 lp_pause = ((lp_pause &
3584 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3585 << 3);
3586 }
9e7e8399
MY		 3587 } else {
3588 bnx2x_cl45_read(bp, phy,
3589 MDIO_AN_DEVAD,
3590 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3591 bnx2x_cl45_read(bp, phy,
3592 MDIO_AN_DEVAD,
3593 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3594 }
3595 pause_result = (ld_pause &
3596 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3597 pause_result |= (lp_pause &
3598 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3599 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3600 bnx2x_pause_resolve(vars, pause_result);
9045f6b4 3601
9e7e8399 3602}
8f73f0b9 3603
9e7e8399
MY		 3604static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3605 struct link_params *params,
3606 struct link_vars *vars)
3607{
3608 u8 ret = 0;
9045f6b4 3609 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
9e7e8399
MY		 3610 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3611 /* Update the advertised flow-controled of LD/LP in AN */
3612 if (phy->req_line_speed == SPEED_AUTO_NEG)
3613 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3614 /* But set the flow-control result as the requested one */
9045f6b4 3615 vars->flow_ctrl = phy->req_flow_ctrl;
9e7e8399 3616 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
9045f6b4
YR		 3617 vars->flow_ctrl = params->req_fc_auto_adv;
3618 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3619 ret = 1;
9e7e8399 3620 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
9045f6b4
YR		 3621 }
3622 return ret;
3623}
3c9ada22
YR		 3624/******************************************************************/
3625/* Warpcore section */
3626/******************************************************************/
3627/* The init_internal_warpcore should mirror the xgxs,
3628 * i.e. reset the lane (if needed), set aer for the
3629 * init configuration, and set/clear SGMII flag. Internal
3630 * phy init is done purely in phy_init stage.
3631 */
4e7b4997
YR		 3632static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3633 struct link_params *params,
3634 struct link_vars *vars)
3635{
3636 struct bnx2x *bp = params->bp;
3637 u16 i;
3638 static struct bnx2x_reg_set reg_set[] = {
3639 /* Step 1 - Program the TX/RX alignment markers */
3640 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3642 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3643 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3644 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3645 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3646 /* Step 2 - Configure the NP registers */
3647 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3648 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3649 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3651 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3652 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3653 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3654 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3655 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3656 };
3657 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3658
3659 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3660 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3661
b5a05550 3662 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4e7b4997
YR		 3663 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3664 reg_set[i].val);
3665
3666 /* Start KR2 work-around timer which handles BCM8073 link-parner */
3667 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3668 bnx2x_update_link_attr(params, vars->link_attr_sync);
3669}
ec4010ec
YM		 3670
3671static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3672 struct link_params *params)
3673{
3674 struct bnx2x *bp = params->bp;
3675
3676 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3677 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3679 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3680 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3681}
3682
4e7b4997
YR		 3683static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3684 struct link_params *params)
3685{
3686 /* Restart autoneg on the leading lane only */
3687 struct bnx2x *bp = params->bp;
3688 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3689 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3690 MDIO_AER_BLOCK_AER_REG, lane);
3691 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3692 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3693
3694 /* Restore AER */
3695 bnx2x_set_aer_mmd(params, phy);
3696}
3697
3c9ada22
YR		 3698static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3699 struct link_params *params,
3700 struct link_vars *vars) {
cd1a26a3
YR		 3701 u16 lane, i, cl72_ctrl, an_adv = 0;
3702 u16 ucode_ver;
a351d497
YM		 3703 struct bnx2x *bp = params->bp;
3704 static struct bnx2x_reg_set reg_set[] = {
3705 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
a351d497
YM		 3706 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3707 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3708 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3709 /* Disable Autoneg: re-enable it after adv is done. */
4e7b4997
YR		 3710 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3711 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3712 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
a351d497 3713 };
3c9ada22 3714 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
6a51c0d1 3715 /* Set to default registers that may be overriden by 10G force */
b5a05550 3716 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
a351d497
YM		 3717 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3718 reg_set[i].val);
a9077bfd 3719
b457bcb9 3720 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
503976e9 3721 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4e7b4997 3722 cl72_ctrl &= 0x08ff;
b457bcb9
YR		 3723 cl72_ctrl |= 0x3800;
3724 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
503976e9 3725 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
b457bcb9 3726
3c9ada22
YR		 3727 /* Check adding advertisement for 1G KX */
3728 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3729 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3730 (vars->line_speed == SPEED_1000)) {
a351d497 3731 u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
cd1a26a3 3732 an_adv |= (1<<5);
3c9ada22
YR		 3733
3734 /* Enable CL37 1G Parallel Detect */
a351d497 3735 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3c9ada22
YR		 3736 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3737 }
3738 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3739 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3740 (vars->line_speed == SPEED_10000)) {
3741 /* Check adding advertisement for 10G KR */
cd1a26a3 3742 an_adv |= (1<<7);
3c9ada22 3743 /* Enable 10G Parallel Detect */
cd1a26a3
YR		 3744 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3745 MDIO_AER_BLOCK_AER_REG, 0);
3746
3c9ada22 3747 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
a351d497 3748 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
cd1a26a3 3749 bnx2x_set_aer_mmd(params, phy);
3c9ada22
YR		 3750 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3751 }
3752
3753 /* Set Transmit PMD settings */
3754 lane = bnx2x_get_warpcore_lane(phy, params);
3755 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3757 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3758 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3759 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4e7b4997
YR		 3760 /* Configure the next lane if dual mode */
3761 if (phy->flags & FLAGS_WC_DUAL_MODE)
3762 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3763 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3764 ((0x02 <<
3765 MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3766 (0x06 <<
3767 MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3768 (0x09 <<
3769 MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3c9ada22
YR		 3770 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3772 0x03f0);
3773 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3774 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3775 0x03f0);
3c9ada22
YR		 3776
3777 /* Advertised speeds */
3778 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
cd1a26a3 3779 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3c9ada22 3780
6b1f3900
YR		 3781 /* Advertised and set FEC (Forward Error Correction) */
3782 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3783 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3784 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3785 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3786
a34bc969
YR		 3787 /* Enable CL37 BAM */
3788 if (REG_RD(bp, params->shmem_base +
3789 offsetof(struct shmem_region, dev_info.
3790 port_hw_config[params->port].default_cfg)) &
3791 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
a351d497
YM		 3792 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3793 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3794 1);
a34bc969
YR		 3795 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3796 }
3797
3c9ada22
YR		 3798 /* Advertise pause */
3799 bnx2x_ext_phy_set_pause(params, phy, vars);
8f73f0b9 3800 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
6ab48a5c
YR		 3801 */
3802 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
cd1a26a3
YR		 3803 MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver);
3804 if (ucode_ver < 0xd108) {
3805 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n",
3806 ucode_ver);
6ab48a5c
YR		 3807 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3808 }
a351d497
YM		 3809 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3810 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
a9077bfd
YR		 3811
3812 /* Over 1G - AN local device user page 1 */
3813 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3815
4e7b4997
YR		 3816 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3817 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3818 (phy->req_line_speed == SPEED_20000)) {
3819
3820 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3821 MDIO_AER_BLOCK_AER_REG, lane);
3822
3823 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3824 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3825 (1<<11));
3826
3827 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3829 bnx2x_set_aer_mmd(params, phy);
a9077bfd 3830
4e7b4997
YR		 3831 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3832 }
3833
3834 /* Enable Autoneg: only on the main lane */
3835 bnx2x_warpcore_restart_AN_KR(phy, params);
3c9ada22
YR		 3836}
3837
3838static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3839 struct link_params *params,
3840 struct link_vars *vars)
3841{
3842 struct bnx2x *bp = params->bp;
cd1a26a3 3843 u16 val16, i, lane;
a351d497
YM		 3844 static struct bnx2x_reg_set reg_set[] = {
3845 /* Disable Autoneg */
3846 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
a351d497
YM		 3847 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3848 0x3f00},
3849 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3850 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3851 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3852 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
a351d497 3853 /* Leave cl72 training enable, needed for KR */
4e7b4997 3854 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
a351d497
YM		 3855 };
3856
b5a05550 3857 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
a351d497
YM		 3858 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3859 reg_set[i].val);
3c9ada22 3860
cd1a26a3
YR		 3861 lane = bnx2x_get_warpcore_lane(phy, params);
3862 /* Global registers */
3863 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3864 MDIO_AER_BLOCK_AER_REG, 0);
3865 /* Disable CL36 PCS Tx */
3866 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3867 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3868 val16 &= ~(0x0011 << lane);
3869 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3870 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3c9ada22 3871
cd1a26a3
YR		 3872 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3873 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3874 val16 |= (0x0303 << (lane << 1));
3875 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3877 /* Restore AER */
3878 bnx2x_set_aer_mmd(params, phy);
3c9ada22
YR		 3879 /* Set speed via PMA/PMD register */
3880 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3881 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3882
3883 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3884 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3885
8f73f0b9 3886 /* Enable encoded forced speed */
3c9ada22
YR		 3887 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3889
3890 /* Turn TX scramble payload only the 64/66 scrambler */
3891 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3892 MDIO_WC_REG_TX66_CONTROL, 0x9);
3893
3894 /* Turn RX scramble payload only the 64/66 scrambler */
3895 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3896 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3897
d231023e 3898 /* Set and clear loopback to cause a reset to 64/66 decoder */
3c9ada22
YR		 3899 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3901 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3902 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3903
3904}
3905
3906static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3907 struct link_params *params,
3908 u8 is_xfi)
3909{
3910 struct bnx2x *bp = params->bp;
3911 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3912 /* Hold rxSeqStart */
a351d497
YM		 3913 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3914 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3c9ada22
YR		 3915
3916 /* Hold tx_fifo_reset */
a351d497
YM		 3917 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3918 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3c9ada22
YR		 3919
3920 /* Disable CL73 AN */
3921 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3922
3923 /* Disable 100FX Enable and Auto-Detect */
503976e9
YR		 3924 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3925 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3c9ada22
YR		 3926
3927 /* Disable 100FX Idle detect */
a351d497
YM		 3928 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3929 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3c9ada22
YR		 3930
3931 /* Set Block address to Remote PHY & Clear forced_speed[5] */
503976e9
YR		 3932 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3933 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3c9ada22
YR		 3934
3935 /* Turn off auto-detect & fiber mode */
503976e9
YR		 3936 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3937 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3938 0xFFEE);
3c9ada22
YR		 3939
3940 /* Set filter_force_link, disable_false_link and parallel_detect */
3941 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3942 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3943 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3944 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3945 ((val | 0x0006) & 0xFFFE));
3946
3947 /* Set XFI / SFI */
3948 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3949 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3950
3951 misc1_val &= ~(0x1f);
3952
3953 if (is_xfi) {
3954 misc1_val |= 0x5;
3955 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3956 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3957 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3958 tx_driver_val =
3959 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3960 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3961 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3962
3963 } else {
3964 misc1_val |= 0x9;
25182fc2
YR		 3965 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3966 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3967 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3c9ada22 3968 tx_driver_val =
25182fc2 3969 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3c9ada22 3970 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
25182fc2 3971 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3c9ada22
YR		 3972 }
3973 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3974 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3975
3976 /* Set Transmit PMD settings */
3977 lane = bnx2x_get_warpcore_lane(phy, params);
3978 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3979 MDIO_WC_REG_TX_FIR_TAP,
3980 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3981 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3982 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3983 tx_driver_val);
3984
3985 /* Enable fiber mode, enable and invert sig_det */
a351d497
YM		 3986 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3987 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3c9ada22
YR		 3988
3989 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
a351d497
YM		 3990 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3991 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3c9ada22 3992
ec4010ec 3993 bnx2x_warpcore_set_lpi_passthrough(phy, params);
c8c60d88 3994
3c9ada22
YR		 3995 /* 10G XFI Full Duplex */
3996 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3997 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3998
3999 /* Release tx_fifo_reset */
503976e9
YR		 4000 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4001 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4002 0xFFFE);
3c9ada22 4003 /* Release rxSeqStart */
503976e9
YR		 4004 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4005 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3c9ada22
YR		 4006}
4007
4e7b4997
YR		 4008static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4009 struct link_params *params)
3c9ada22 4010{
4e7b4997
YR		 4011 u16 val;
4012 struct bnx2x *bp = params->bp;
4013 /* Set global registers, so set AER lane to 0 */
4014 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4015 MDIO_AER_BLOCK_AER_REG, 0);
4016
4017 /* Disable sequencer */
4018 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4019 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4020
4021 bnx2x_set_aer_mmd(params, phy);
4022
4023 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4024 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4025 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4026 MDIO_AN_REG_CTRL, 0);
4027 /* Turn off CL73 */
4028 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4029 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4030 val &= ~(1<<5);
4031 val |= (1<<6);
4032 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4033 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4034
4035 /* Set 20G KR2 force speed */
4036 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4037 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4038
4039 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4040 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4041
4042 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4043 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4044 val &= ~(3<<14);
4045 val |= (1<<15);
4046 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4048 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4049 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4050
4051 /* Enable sequencer (over lane 0) */
4052 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4053 MDIO_AER_BLOCK_AER_REG, 0);
4054
4055 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4056 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4057
4058 bnx2x_set_aer_mmd(params, phy);
3c9ada22
YR		 4059}
4060
4061static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4062 struct bnx2x_phy *phy,
4063 u16 lane)
4064{
4065 /* Rx0 anaRxControl1G */
4066 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4068
4069 /* Rx2 anaRxControl1G */
4070 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4071 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4072
4073 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4074 MDIO_WC_REG_RX66_SCW0, 0xE070);
4075
4076 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4077 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4078
4079 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4080 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4081
4082 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4083 MDIO_WC_REG_RX66_SCW3, 0x8090);
4084
4085 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4087
4088 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4089 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4090
4091 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4093
4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4096
4097 /* Serdes Digital Misc1 */
4098 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4099 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4100
4101 /* Serdes Digital4 Misc3 */
4102 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4103 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4104
4105 /* Set Transmit PMD settings */
4106 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107 MDIO_WC_REG_TX_FIR_TAP,
4108 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4109 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4110 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4111 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4112 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4113 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4114 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4115 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4116 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4117}
4118
4119static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4120 struct link_params *params,
521683da
YR		 4121 u8 fiber_mode,
4122 u8 always_autoneg)
3c9ada22
YR		 4123{
4124 struct bnx2x *bp = params->bp;
4125 u16 val16, digctrl_kx1, digctrl_kx2;
3c9ada22
YR		 4126
4127 /* Clear XFI clock comp in non-10G single lane mode. */
503976e9
YR		 4128 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4129 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
3c9ada22 4130
26964bb7
YM		 4131 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4132
521683da 4133 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
3c9ada22 4134 /* SGMII Autoneg */
503976e9
YR		 4135 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4136 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4137 0x1000);
3c9ada22
YR		 4138 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4139 } else {
4140 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4141 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
521683da 4142 val16 &= 0xcebf;
3c9ada22
YR		 4143 switch (phy->req_line_speed) {
4144 case SPEED_10:
4145 break;
4146 case SPEED_100:
4147 val16 |= 0x2000;
4148 break;
4149 case SPEED_1000:
4150 val16 |= 0x0040;
4151 break;
4152 default:
94f05b0f
JP		 4153 DP(NETIF_MSG_LINK,
4154 "Speed not supported: 0x%x\n", phy->req_line_speed);
3c9ada22
YR		 4155 return;
4156 }
4157
4158 if (phy->req_duplex == DUPLEX_FULL)
4159 val16 |= 0x0100;
4160
4161 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4162 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4163
4164 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4165 phy->req_line_speed);
4166 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4167 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4168 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4169 }
4170
4171 /* SGMII Slave mode and disable signal detect */
4172 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4173 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4174 if (fiber_mode)
4175 digctrl_kx1 = 1;
4176 else
4177 digctrl_kx1 &= 0xff4a;
4178
4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4181 digctrl_kx1);
4182
4183 /* Turn off parallel detect */
4184 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4185 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4186 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4187 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4188 (digctrl_kx2 & ~(1<<2)));
4189
4190 /* Re-enable parallel detect */
4191 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4192 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4193 (digctrl_kx2 | (1<<2)));
4194
4195 /* Enable autodet */
4196 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4197 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4198 (digctrl_kx1 | 0x10));
4199}
4200
4201static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4202 struct bnx2x_phy *phy,
4203 u8 reset)
4204{
4205 u16 val;
4206 /* Take lane out of reset after configuration is finished */
4207 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4208 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4209 if (reset)
4210 val |= 0xC000;
4211 else
4212 val &= 0x3FFF;
4213 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4214 MDIO_WC_REG_DIGITAL5_MISC6, val);
4215 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4216 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4217}
2f751a80 4218/* Clear SFI/XFI link settings registers */
3c9ada22
YR		 4219static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4220 struct link_params *params,
4221 u16 lane)
4222{
4223 struct bnx2x *bp = params->bp;
a351d497
YM		 4224 u16 i;
4225 static struct bnx2x_reg_set wc_regs[] = {
4226 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4227 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4228 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4229 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4230 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4231 0x0195},
4232 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4233 0x0007},
4234 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4235 0x0002},
4236 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4237 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4238 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4239 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4240 };
3c9ada22 4241 /* Set XFI clock comp as default. */
a351d497
YM		 4242 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4243 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4244
b5a05550 4245 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
a351d497
YM		 4246 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4247 wc_regs[i].val);
3c9ada22 4248
3c9ada22 4249 lane = bnx2x_get_warpcore_lane(phy, params);
3c9ada22
YR		 4250 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4251 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
a351d497 4252
3c9ada22
YR		 4253}
4254
4255static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4256 u32 chip_id,
4257 u32 shmem_base, u8 port,
4258 u8 *gpio_num, u8 *gpio_port)
4259{
4260 u32 cfg_pin;
4261 *gpio_num = 0;
4262 *gpio_port = 0;
4263 if (CHIP_IS_E3(bp)) {
4264 cfg_pin = (REG_RD(bp, shmem_base +
4265 offsetof(struct shmem_region,
4266 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4267 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4268 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4269
8f73f0b9 4270 /* Should not happen. This function called upon interrupt
3c9ada22
YR		 4271 * triggered by GPIO ( since EPIO can only generate interrupts
4272 * to MCP).
4273 * So if this function was called and none of the GPIOs was set,
4274 * it means the shit hit the fan.
4275 */
4276 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4277 (cfg_pin > PIN_CFG_GPIO3_P1)) {
94f05b0f 4278 DP(NETIF_MSG_LINK,
503976e9 4279 "No cfg pin %x for module detect indication\n",
94f05b0f 4280 cfg_pin);
3c9ada22
YR		 4281 return -EINVAL;
4282 }
4283
4284 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4285 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4286 } else {
4287 *gpio_num = MISC_REGISTERS_GPIO_3;
4288 *gpio_port = port;
4289 }
503976e9 4290
3c9ada22
YR		 4291 return 0;
4292}
4293
4294static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4295 struct link_params *params)
4296{
4297 struct bnx2x *bp = params->bp;
4298 u8 gpio_num, gpio_port;
4299 u32 gpio_val;
4300 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4301 params->shmem_base, params->port,
4302 &gpio_num, &gpio_port) != 0)
4303 return 0;
4304 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4305
4306 /* Call the handling function in case module is detected */
4307 if (gpio_val == 0)
4308 return 1;
4309 else
4310 return 0;
4311}
a9077bfd 4312static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
503976e9 4313 struct link_params *params)
a9077bfd
YR		 4314{
4315 u16 gp2_status_reg0, lane;
4316 struct bnx2x *bp = params->bp;
4317
4318 lane = bnx2x_get_warpcore_lane(phy, params);
4319
4320 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4321 &gp2_status_reg0);
4322
4323 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4324}
4325
4326static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
503976e9
YR		 4327 struct link_params *params,
4328 struct link_vars *vars)
a9077bfd
YR		 4329{
4330 struct bnx2x *bp = params->bp;
4331 u32 serdes_net_if;
4332 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4333 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4334
4335 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4336
4337 if (!vars->turn_to_run_wc_rt)
4338 return;
4339
d231023e 4340 /* Return if there is no link partner */
a9077bfd
YR		 4341 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4342 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4343 return;
4344 }
4345
4346 if (vars->rx_tx_asic_rst) {
4347 serdes_net_if = (REG_RD(bp, params->shmem_base +
4348 offsetof(struct shmem_region, dev_info.
4349 port_hw_config[params->port].default_cfg)) &
4350 PORT_HW_CFG_NET_SERDES_IF_MASK);
4351
4352 switch (serdes_net_if) {
4353 case PORT_HW_CFG_NET_SERDES_IF_KR:
4354 /* Do we get link yet? */
4355 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
503976e9 4356 &gp_status1);
a9077bfd
YR		 4357 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4358 /*10G KR*/
4359 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4360
4361 DP(NETIF_MSG_LINK,
4362 "gp_status1 0x%x\n", gp_status1);
4363
4364 if (lnkup_kr || lnkup) {
4365 vars->rx_tx_asic_rst = 0;
4366 DP(NETIF_MSG_LINK,
4367 "link up, rx_tx_asic_rst 0x%x\n",
4368 vars->rx_tx_asic_rst);
4369 } else {
8f73f0b9 4370 /* Reset the lane to see if link comes up.*/
a9077bfd
YR		 4371 bnx2x_warpcore_reset_lane(bp, phy, 1);
4372 bnx2x_warpcore_reset_lane(bp, phy, 0);
4373
d231023e 4374 /* Restart Autoneg */
a9077bfd
YR		 4375 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4376 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4377
4378 vars->rx_tx_asic_rst--;
4379 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4380 vars->rx_tx_asic_rst);
4381 }
4382 break;
4383
4384 default:
4385 break;
4386 }
4387
4388 } /*params->rx_tx_asic_rst*/
4389
4390}
dbef807e
YM		 4391static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4392 struct link_params *params)
4393{
4394 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4395 struct bnx2x *bp = params->bp;
4396 bnx2x_warpcore_clear_regs(phy, params, lane);
4397 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4398 SPEED_10000) &&
4399 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4400 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4401 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4402 } else {
4403 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4404 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4405 }
4406}
4407
5a1fbf40
YR		 4408static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4409 struct bnx2x_phy *phy,
4410 u8 tx_en)
4411{
4412 struct bnx2x *bp = params->bp;
4413 u32 cfg_pin;
4414 u8 port = params->port;
4415
4416 cfg_pin = REG_RD(bp, params->shmem_base +
4417 offsetof(struct shmem_region,
4418 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4419 PORT_HW_CFG_E3_TX_LASER_MASK;
4420 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4421 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4422
4423 /* For 20G, the expected pin to be used is 3 pins after the current */
4424 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4425 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4426 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4427}
4428
3c9ada22
YR		 4429static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4430 struct link_params *params,
4431 struct link_vars *vars)
4432{
4433 struct bnx2x *bp = params->bp;
4434 u32 serdes_net_if;
4435 u8 fiber_mode;
4436 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4437 serdes_net_if = (REG_RD(bp, params->shmem_base +
4438 offsetof(struct shmem_region, dev_info.
4439 port_hw_config[params->port].default_cfg)) &
4440 PORT_HW_CFG_NET_SERDES_IF_MASK);
4441 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4442 "serdes_net_if = 0x%x\n",
4443 vars->line_speed, serdes_net_if);
4444 bnx2x_set_aer_mmd(params, phy);
d3a8f13b 4445 bnx2x_warpcore_reset_lane(bp, phy, 1);
3c9ada22
YR		 4446 vars->phy_flags |= PHY_XGXS_FLAG;
4447 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4448 (phy->req_line_speed &&
4449 ((phy->req_line_speed == SPEED_100) ||
4450 (phy->req_line_speed == SPEED_10)))) {
4451 vars->phy_flags |= PHY_SGMII_FLAG;
4452 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4453 bnx2x_warpcore_clear_regs(phy, params, lane);
521683da 4454 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
3c9ada22
YR		 4455 } else {
4456 switch (serdes_net_if) {
4457 case PORT_HW_CFG_NET_SERDES_IF_KR:
4458 /* Enable KR Auto Neg */
6a51c0d1 4459 if (params->loopback_mode != LOOPBACK_EXT)
3c9ada22
YR		 4460 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4461 else {
4462 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4463 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4464 }
4465 break;
4466
4467 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4468 bnx2x_warpcore_clear_regs(phy, params, lane);
4469 if (vars->line_speed == SPEED_10000) {
4470 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4471 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4472 } else {
4473 if (SINGLE_MEDIA_DIRECT(params)) {
4474 DP(NETIF_MSG_LINK, "1G Fiber\n");
4475 fiber_mode = 1;
4476 } else {
4477 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4478 fiber_mode = 0;
4479 }
4480 bnx2x_warpcore_set_sgmii_speed(phy,
4481 params,
521683da
YR		 4482 fiber_mode,
4483 0);
3c9ada22
YR		 4484 }
4485
4486 break;
4487
4488 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5a1fbf40
YR		 4489 /* Issue Module detection if module is plugged, or
4490 * enabled transmitter to avoid current leakage in case
4491 * no module is connected
4492 */
3c9ada22
YR		 4493 if (bnx2x_is_sfp_module_plugged(phy, params))
4494 bnx2x_sfp_module_detection(phy, params);
5a1fbf40
YR		 4495 else
4496 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
dbef807e
YM		 4497
4498 bnx2x_warpcore_config_sfi(phy, params);
3c9ada22
YR		 4499 break;
4500
4501 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4502 if (vars->line_speed != SPEED_20000) {
4503 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4504 return;
4505 }
4506 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4507 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4508 /* Issue Module detection */
4509
4510 bnx2x_sfp_module_detection(phy, params);
4511 break;
3c9ada22 4512 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4e7b4997
YR		 4513 if (!params->loopback_mode) {
4514 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4515 } else {
4516 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4517 bnx2x_warpcore_set_20G_force_KR2(phy, params);
3c9ada22 4518 }
3c9ada22 4519 break;
3c9ada22 4520 default:
94f05b0f
JP		 4521 DP(NETIF_MSG_LINK,
4522 "Unsupported Serdes Net Interface 0x%x\n",
4523 serdes_net_if);
3c9ada22
YR		 4524 return;
4525 }
4526 }
4527
4528 /* Take lane out of reset after configuration is finished */
4529 bnx2x_warpcore_reset_lane(bp, phy, 0);
4530 DP(NETIF_MSG_LINK, "Exit config init\n");
4531}
4532
3c9ada22
YR		 4533static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4534 struct link_params *params)
4535{
4536 struct bnx2x *bp = params->bp;
cd1a26a3 4537 u16 val16, lane;
3c9ada22 4538 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
55386fe8 4539 bnx2x_set_mdio_emac_per_phy(bp, params);
3c9ada22
YR		 4540 bnx2x_set_aer_mmd(params, phy);
4541 /* Global register */
4542 bnx2x_warpcore_reset_lane(bp, phy, 1);
4543
4544 /* Clear loopback settings (if any) */
4545 /* 10G & 20G */
503976e9
YR		 4546 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4547 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
3c9ada22 4548
503976e9
YR		 4549 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4550 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
3c9ada22
YR		 4551
4552 /* Update those 1-copy registers */
4553 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4554 MDIO_AER_BLOCK_AER_REG, 0);
8f73f0b9 4555 /* Enable 1G MDIO (1-copy) */
503976e9
YR		 4556 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4557 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4558 ~0x10);
3c9ada22 4559
503976e9
YR		 4560 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4561 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
cd1a26a3
YR		 4562 lane = bnx2x_get_warpcore_lane(phy, params);
4563 /* Disable CL36 PCS Tx */
4564 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4565 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4566 val16 |= (0x11 << lane);
4567 if (phy->flags & FLAGS_WC_DUAL_MODE)
4568 val16 |= (0x22 << lane);
4569 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4570 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4571
4572 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4573 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4574 val16 &= ~(0x0303 << (lane << 1));
4575 val16 |= (0x0101 << (lane << 1));
4576 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4577 val16 &= ~(0x0c0c << (lane << 1));
4578 val16 |= (0x0404 << (lane << 1));
4579 }
4580
4581 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4582 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4583 /* Restore AER */
4584 bnx2x_set_aer_mmd(params, phy);
4585
3c9ada22
YR		 4586}
4587
4588static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4589 struct link_params *params)
4590{
4591 struct bnx2x *bp = params->bp;
4592 u16 val16;
4593 u32 lane;
4594 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4595 params->loopback_mode, phy->req_line_speed);
4596
4e7b4997
YR		 4597 if (phy->req_line_speed < SPEED_10000 ||
4598 phy->supported & SUPPORTED_20000baseKR2_Full) {
4599 /* 10/100/1000/20G-KR2 */
3c9ada22
YR		 4600
4601 /* Update those 1-copy registers */
4602 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4603 MDIO_AER_BLOCK_AER_REG, 0);
4604 /* Enable 1G MDIO (1-copy) */
a351d497
YM		 4605 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4606 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4607 0x10);
3c9ada22
YR		 4608 /* Set 1G loopback based on lane (1-copy) */
4609 lane = bnx2x_get_warpcore_lane(phy, params);
4610 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4611 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4e7b4997
YR		 4612 val16 |= (1<<lane);
4613 if (phy->flags & FLAGS_WC_DUAL_MODE)
4614 val16 |= (2<<lane);
3c9ada22 4615 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
503976e9
YR		 4616 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4617 val16);
3c9ada22
YR		 4618
4619 /* Switch back to 4-copy registers */
4620 bnx2x_set_aer_mmd(params, phy);
3c9ada22 4621 } else {
4e7b4997 4622 /* 10G / 20G-DXGXS */
a351d497
YM		 4623 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4624 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4625 0x4000);
a351d497
YM		 4626 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4627 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
3c9ada22
YR		 4628 }
4629}
4630
4631
d231023e
YM		 4632
4633static void bnx2x_sync_link(struct link_params *params,
4634 struct link_vars *vars)
de6eae1f
YR		 4635{
4636 struct bnx2x *bp = params->bp;
9380bb9e 4637 u8 link_10g_plus;
de6f3377
YR		 4638 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4639 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
2f751a80 4640 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
de6eae1f
YR		 4641 if (vars->link_up) {
4642 DP(NETIF_MSG_LINK, "phy link up\n");
4643
4644 vars->phy_link_up = 1;
4645 vars->duplex = DUPLEX_FULL;
4646 switch (vars->link_status &
cd88ccee 4647 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
8f73f0b9
YR		 4648 case LINK_10THD:
4649 vars->duplex = DUPLEX_HALF;
4650 /* Fall thru */
4651 case LINK_10TFD:
4652 vars->line_speed = SPEED_10;
4653 break;
de6eae1f 4654
8f73f0b9
YR		 4655 case LINK_100TXHD:
4656 vars->duplex = DUPLEX_HALF;
4657 /* Fall thru */
4658 case LINK_100T4:
4659 case LINK_100TXFD:
4660 vars->line_speed = SPEED_100;
4661 break;
de6eae1f 4662
8f73f0b9
YR		 4663 case LINK_1000THD:
4664 vars->duplex = DUPLEX_HALF;
4665 /* Fall thru */
4666 case LINK_1000TFD:
4667 vars->line_speed = SPEED_1000;
4668 break;
de6eae1f 4669
8f73f0b9
YR		 4670 case LINK_2500THD:
4671 vars->duplex = DUPLEX_HALF;
4672 /* Fall thru */
4673 case LINK_2500TFD:
4674 vars->line_speed = SPEED_2500;
4675 break;
de6eae1f 4676
8f73f0b9
YR		 4677 case LINK_10GTFD:
4678 vars->line_speed = SPEED_10000;
4679 break;
4680 case LINK_20GTFD:
4681 vars->line_speed = SPEED_20000;
4682 break;
4683 default:
4684 break;
de6eae1f 4685 }
de6eae1f
YR		 4686 vars->flow_ctrl = 0;
4687 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4688 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4689
4690 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4691 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4692
4693 if (!vars->flow_ctrl)
4694 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4695
4696 if (vars->line_speed &&
4697 ((vars->line_speed == SPEED_10) ||
4698 (vars->line_speed == SPEED_100))) {
4699 vars->phy_flags |= PHY_SGMII_FLAG;
4700 } else {
4701 vars->phy_flags &= ~PHY_SGMII_FLAG;
4702 }
3c9ada22
YR		 4703 if (vars->line_speed &&
4704 USES_WARPCORE(bp) &&
4705 (vars->line_speed == SPEED_1000))
4706 vars->phy_flags |= PHY_SGMII_FLAG;
d231023e 4707 /* Anything 10 and over uses the bmac */
9380bb9e
YR		 4708 link_10g_plus = (vars->line_speed >= SPEED_10000);
4709
4710 if (link_10g_plus) {
4711 if (USES_WARPCORE(bp))
4712 vars->mac_type = MAC_TYPE_XMAC;
4713 else
3c9ada22 4714 vars->mac_type = MAC_TYPE_BMAC;
9380bb9e
YR		 4715 } else {
4716 if (USES_WARPCORE(bp))
4717 vars->mac_type = MAC_TYPE_UMAC;
3c9ada22
YR		 4718 else
4719 vars->mac_type = MAC_TYPE_EMAC;
9380bb9e 4720 }
d231023e 4721 } else { /* Link down */
de6eae1f
YR		 4722 DP(NETIF_MSG_LINK, "phy link down\n");
4723
4724 vars->phy_link_up = 0;
4725
4726 vars->line_speed = 0;
4727 vars->duplex = DUPLEX_FULL;
4728 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4729
d231023e 4730 /* Indicate no mac active */
de6eae1f 4731 vars->mac_type = MAC_TYPE_NONE;
de6f3377
YR		 4732 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4733 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
d0b8a6f9
YM		 4734 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4735 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
de6eae1f 4736 }
2f751a80
YR		 4737}
4738
4739void bnx2x_link_status_update(struct link_params *params,
4740 struct link_vars *vars)
4741{
4742 struct bnx2x *bp = params->bp;
4743 u8 port = params->port;
4744 u32 sync_offset, media_types;
4745 /* Update PHY configuration */
4746 set_phy_vars(params, vars);
de6eae1f 4747
2f751a80
YR		 4748 vars->link_status = REG_RD(bp, params->shmem_base +
4749 offsetof(struct shmem_region,
4750 port_mb[port].link_status));
7614fe88
MB		 4751
4752 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4753 if (bp->link_params.loopback_mode != LOOPBACK_NONE &&
4754 bp->link_params.loopback_mode != LOOPBACK_EXT)
4755 vars->link_status |= LINK_STATUS_LINK_UP;
4756
08e9acc2
YM		 4757 if (bnx2x_eee_has_cap(params))
4758 vars->eee_status = REG_RD(bp, params->shmem2_base +
4759 offsetof(struct shmem2_region,
4760 eee_status[params->port]));
2f751a80
YR		 4761
4762 vars->phy_flags = PHY_XGXS_FLAG;
4763 bnx2x_sync_link(params, vars);
1ac9e428
YR		 4764 /* Sync media type */
4765 sync_offset = params->shmem_base +
4766 offsetof(struct shmem_region,
4767 dev_info.port_hw_config[port].media_type);
4768 media_types = REG_RD(bp, sync_offset);
4769
4770 params->phy[INT_PHY].media_type =
4771 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4772 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4773 params->phy[EXT_PHY1].media_type =
4774 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4775 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4776 params->phy[EXT_PHY2].media_type =
4777 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4778 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4779 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4780
020c7e3f
YR		 4781 /* Sync AEU offset */
4782 sync_offset = params->shmem_base +
4783 offsetof(struct shmem_region,
4784 dev_info.port_hw_config[port].aeu_int_mask);
4785
4786 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4787
b8d6d082
YR		 4788 /* Sync PFC status */
4789 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4790 params->feature_config_flags |=
4791 FEATURE_CONFIG_PFC_ENABLED;
4792 else
4793 params->feature_config_flags &=
4794 ~FEATURE_CONFIG_PFC_ENABLED;
4795
4e7b4997
YR		 4796 if (SHMEM2_HAS(bp, link_attr_sync))
4797 vars->link_attr_sync = SHMEM2_RD(bp,
4798 link_attr_sync[params->port]);
4799
020c7e3f
YR		 4800 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4801 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
de6eae1f
YR		 4802 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4803 vars->line_speed, vars->duplex, vars->flow_ctrl);
4804}
4805
de6eae1f
YR		 4806static void bnx2x_set_master_ln(struct link_params *params,
4807 struct bnx2x_phy *phy)
4808{
4809 struct bnx2x *bp = params->bp;
4810 u16 new_master_ln, ser_lane;
cd88ccee 4811 ser_lane = ((params->lane_config &
de6eae1f 4812 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
cd88ccee 4813 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
de6eae1f 4814
d231023e 4815 /* Set the master_ln for AN */
cd2be89b 4816 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4817 MDIO_REG_BANK_XGXS_BLOCK2,
4818 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4819 &new_master_ln);
de6eae1f 4820
cd2be89b 4821 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4822 MDIO_REG_BANK_XGXS_BLOCK2 ,
4823 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4824 (new_master_ln | ser_lane));
de6eae1f
YR		 4825}
4826
fcf5b650
YR		 4827static int bnx2x_reset_unicore(struct link_params *params,
4828 struct bnx2x_phy *phy,
4829 u8 set_serdes)
de6eae1f
YR		 4830{
4831 struct bnx2x *bp = params->bp;
4832 u16 mii_control;
4833 u16 i;
cd2be89b 4834 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4835 MDIO_REG_BANK_COMBO_IEEE0,
4836 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
de6eae1f 4837
d231023e 4838 /* Reset the unicore */
cd2be89b 4839 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4840 MDIO_REG_BANK_COMBO_IEEE0,
4841 MDIO_COMBO_IEEE0_MII_CONTROL,
4842 (mii_control |
4843 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
de6eae1f
YR		 4844 if (set_serdes)
4845 bnx2x_set_serdes_access(bp, params->port);
4846
d231023e 4847 /* Wait for the reset to self clear */
de6eae1f
YR		 4848 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4849 udelay(5);
4850
d231023e 4851 /* The reset erased the previous bank value */
cd2be89b 4852 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4853 MDIO_REG_BANK_COMBO_IEEE0,
4854 MDIO_COMBO_IEEE0_MII_CONTROL,
4855 &mii_control);
de6eae1f
YR		 4856
4857 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4858 udelay(5);
4859 return 0;
4860 }
4861 }
ea4e040a 4862
6d870c39
YR		 4863 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4864 " Port %d\n",
4865 params->port);
ea4e040a
YR		 4866 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4867 return -EINVAL;
4868
4869}
4870
e10bc84d
YR		 4871static void bnx2x_set_swap_lanes(struct link_params *params,
4872 struct bnx2x_phy *phy)
ea4e040a
YR		 4873{
4874 struct bnx2x *bp = params->bp;
8f73f0b9
YR		 4875 /* Each two bits represents a lane number:
4876 * No swap is 0123 => 0x1b no need to enable the swap
2cf7acf9 4877 */
2f751a80 4878 u16 rx_lane_swap, tx_lane_swap;
ea4e040a 4879
ea4e040a 4880 rx_lane_swap = ((params->lane_config &
cd88ccee
YR		 4881 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4882 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
ea4e040a 4883 tx_lane_swap = ((params->lane_config &
cd88ccee
YR		 4884 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4885 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
ea4e040a
YR		 4886
4887 if (rx_lane_swap != 0x1b) {
cd2be89b 4888 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4889 MDIO_REG_BANK_XGXS_BLOCK2,
4890 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4891 (rx_lane_swap |
4892 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4893 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
ea4e040a 4894 } else {
cd2be89b 4895 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4896 MDIO_REG_BANK_XGXS_BLOCK2,
4897 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
ea4e040a
YR		 4898 }
4899
4900 if (tx_lane_swap != 0x1b) {
cd2be89b 4901 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4902 MDIO_REG_BANK_XGXS_BLOCK2,
4903 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4904 (tx_lane_swap |
4905 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
ea4e040a 4906 } else {
cd2be89b 4907 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4908 MDIO_REG_BANK_XGXS_BLOCK2,
4909 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
ea4e040a
YR		 4910 }
4911}
4912
e10bc84d
YR		 4913static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4914 struct link_params *params)
ea4e040a
YR		 4915{
4916 struct bnx2x *bp = params->bp;
4917 u16 control2;
cd2be89b 4918 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4919 MDIO_REG_BANK_SERDES_DIGITAL,
4920 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4921 &control2);
7aa0711f 4922 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 4923 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4924 else
4925 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 4926 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4927 phy->speed_cap_mask, control2);
cd2be89b 4928 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4929 MDIO_REG_BANK_SERDES_DIGITAL,
4930 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4931 control2);
ea4e040a 4932
e10bc84d 4933 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 4934 (phy->speed_cap_mask &
18afb0a6 4935 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 4936 DP(NETIF_MSG_LINK, "XGXS\n");
4937
cd2be89b 4938 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4939 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4940 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4941 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
ea4e040a 4942
cd2be89b 4943 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4944 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4945 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4946 &control2);
ea4e040a
YR		 4947
4948
4949 control2 |=
4950 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4951
cd2be89b 4952 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4953 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4954 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4955 control2);
ea4e040a
YR		 4956
4957 /* Disable parallel detection of HiG */
cd2be89b 4958 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4959 MDIO_REG_BANK_XGXS_BLOCK2,
4960 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4961 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4962 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
ea4e040a
YR		 4963 }
4964}
4965
e10bc84d
YR		 4966static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4967 struct link_params *params,
cd88ccee
YR		 4968 struct link_vars *vars,
4969 u8 enable_cl73)
ea4e040a
YR		 4970{
4971 struct bnx2x *bp = params->bp;
4972 u16 reg_val;
4973
4974 /* CL37 Autoneg */
cd2be89b 4975 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4976 MDIO_REG_BANK_COMBO_IEEE0,
4977 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a
YR		 4978
4979 /* CL37 Autoneg Enabled */
8c99e7b0 4980 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 4981 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4982 else /* CL37 Autoneg Disabled */
4983 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4984 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4985
cd2be89b 4986 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 4987 MDIO_REG_BANK_COMBO_IEEE0,
4988 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a
YR		 4989
4990 /* Enable/Disable Autodetection */
4991
cd2be89b 4992 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 4993 MDIO_REG_BANK_SERDES_DIGITAL,
4994 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 4995 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4996 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4997 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 4998 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 4999 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5000 else
5001 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5002
cd2be89b 5003 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5004 MDIO_REG_BANK_SERDES_DIGITAL,
5005 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
ea4e040a
YR		 5006
5007 /* Enable TetonII and BAM autoneg */
cd2be89b 5008 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5009 MDIO_REG_BANK_BAM_NEXT_PAGE,
5010 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
ea4e040a 5011 &reg_val);
8c99e7b0 5012 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 5013 /* Enable BAM aneg Mode and TetonII aneg Mode */
5014 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5015 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5016 } else {
5017 /* TetonII and BAM Autoneg Disabled */
5018 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5019 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5020 }
cd2be89b 5021 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5022 MDIO_REG_BANK_BAM_NEXT_PAGE,
5023 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5024 reg_val);
ea4e040a 5025
239d686d
EG		 5026 if (enable_cl73) {
5027 /* Enable Cl73 FSM status bits */
cd2be89b 5028 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5029 MDIO_REG_BANK_CL73_USERB0,
5030 MDIO_CL73_USERB0_CL73_UCTRL,
5031 0xe);
239d686d
EG		 5032
5033 /* Enable BAM Station Manager*/
cd2be89b 5034 CL22_WR_OVER_CL45(bp, phy,
239d686d
EG		 5035 MDIO_REG_BANK_CL73_USERB0,
5036 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5037 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5038 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5039 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5040
7846e471 5041 /* Advertise CL73 link speeds */
cd2be89b 5042 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5043 MDIO_REG_BANK_CL73_IEEEB1,
5044 MDIO_CL73_IEEEB1_AN_ADV2,
5045 &reg_val);
7aa0711f 5046 if (phy->speed_cap_mask &
7846e471
YR		 5047 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5048 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 5049 if (phy->speed_cap_mask &
7846e471
YR		 5050 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5051 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 5052
cd2be89b 5053 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5054 MDIO_REG_BANK_CL73_IEEEB1,
5055 MDIO_CL73_IEEEB1_AN_ADV2,
5056 reg_val);
239d686d 5057
239d686d
EG		 5058 /* CL73 Autoneg Enabled */
5059 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5060
5061 } else /* CL73 Autoneg Disabled */
5062 reg_val = 0;
ea4e040a 5063
cd2be89b 5064 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5065 MDIO_REG_BANK_CL73_IEEEB0,
5066 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
ea4e040a
YR		 5067}
5068
d231023e 5069/* Program SerDes, forced speed */
e10bc84d
YR		 5070static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5071 struct link_params *params,
cd88ccee 5072 struct link_vars *vars)
ea4e040a
YR		 5073{
5074 struct bnx2x *bp = params->bp;
5075 u16 reg_val;
5076
d231023e 5077 /* Program duplex, disable autoneg and sgmii*/
cd2be89b 5078 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5079 MDIO_REG_BANK_COMBO_IEEE0,
5080 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a 5081 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 5082 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5083 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 5084 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 5085 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 5086 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5087 MDIO_REG_BANK_COMBO_IEEE0,
5088 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a 5089
8f73f0b9 5090 /* Program speed
2cf7acf9
YR		 5091 * - needed only if the speed is greater than 1G (2.5G or 10G)
5092 */
cd2be89b 5093 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5094 MDIO_REG_BANK_SERDES_DIGITAL,
5095 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
d231023e 5096 /* Clearing the speed value before setting the right speed */
8c99e7b0
YR		 5097 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5098
5099 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5100 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5101
5102 if (!((vars->line_speed == SPEED_1000) ||
5103 (vars->line_speed == SPEED_100) ||
5104 (vars->line_speed == SPEED_10))) {
5105
ea4e040a
YR		 5106 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5107 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 5108 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 5109 reg_val |=
5110 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0
YR		 5111 }
5112
cd2be89b 5113 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5114 MDIO_REG_BANK_SERDES_DIGITAL,
5115 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 5116
ea4e040a
YR		 5117}
5118
9045f6b4
YR		 5119static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5120 struct link_params *params)
ea4e040a
YR		 5121{
5122 struct bnx2x *bp = params->bp;
5123 u16 val = 0;
5124
d231023e 5125 /* Set extended capabilities */
7aa0711f 5126 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 5127 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 5128 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 5129 val |= MDIO_OVER_1G_UP1_10G;
cd2be89b 5130 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5131 MDIO_REG_BANK_OVER_1G,
5132 MDIO_OVER_1G_UP1, val);
ea4e040a 5133
cd2be89b 5134 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5135 MDIO_REG_BANK_OVER_1G,
5136 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 5137}
5138
9045f6b4
YR		 5139static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5140 struct link_params *params,
5141 u16 ieee_fc)
8c99e7b0
YR		 5142{
5143 struct bnx2x *bp = params->bp;
7846e471 5144 u16 val;
d231023e 5145 /* For AN, we are always publishing full duplex */
ea4e040a 5146
cd2be89b 5147 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5148 MDIO_REG_BANK_COMBO_IEEE0,
5149 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
cd2be89b 5150 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5151 MDIO_REG_BANK_CL73_IEEEB1,
5152 MDIO_CL73_IEEEB1_AN_ADV1, &val);
7846e471
YR		 5153 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5154 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
cd2be89b 5155 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5156 MDIO_REG_BANK_CL73_IEEEB1,
5157 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 5158}
5159
e10bc84d
YR		 5160static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5161 struct link_params *params,
5162 u8 enable_cl73)
ea4e040a
YR		 5163{
5164 struct bnx2x *bp = params->bp;
3a36f2ef 5165 u16 mii_control;
239d686d 5166
ea4e040a 5167 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 5168 /* Enable and restart BAM/CL37 aneg */
ea4e040a 5169
239d686d 5170 if (enable_cl73) {
cd2be89b 5171 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5172 MDIO_REG_BANK_CL73_IEEEB0,
5173 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5174 &mii_control);
239d686d 5175
cd2be89b 5176 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5177 MDIO_REG_BANK_CL73_IEEEB0,
5178 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5179 (mii_control |
5180 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5181 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
239d686d
EG		 5182 } else {
5183
cd2be89b 5184 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5185 MDIO_REG_BANK_COMBO_IEEE0,
5186 MDIO_COMBO_IEEE0_MII_CONTROL,
5187 &mii_control);
239d686d
EG		 5188 DP(NETIF_MSG_LINK,
5189 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5190 mii_control);
cd2be89b 5191 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5192 MDIO_REG_BANK_COMBO_IEEE0,
5193 MDIO_COMBO_IEEE0_MII_CONTROL,
5194 (mii_control |
5195 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5196 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
239d686d 5197 }
ea4e040a
YR		 5198}
5199
e10bc84d
YR		 5200static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5201 struct link_params *params,
cd88ccee 5202 struct link_vars *vars)
ea4e040a
YR		 5203{
5204 struct bnx2x *bp = params->bp;
5205 u16 control1;
5206
d231023e 5207 /* In SGMII mode, the unicore is always slave */
ea4e040a 5208
cd2be89b 5209 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5210 MDIO_REG_BANK_SERDES_DIGITAL,
5211 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5212 &control1);
ea4e040a 5213 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
d231023e 5214 /* Set sgmii mode (and not fiber) */
ea4e040a
YR		 5215 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5216 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5217 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
cd2be89b 5218 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5219 MDIO_REG_BANK_SERDES_DIGITAL,
5220 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5221 control1);
ea4e040a 5222
d231023e 5223 /* If forced speed */
8c99e7b0 5224 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
d231023e 5225 /* Set speed, disable autoneg */
ea4e040a
YR		 5226 u16 mii_control;
5227
cd2be89b 5228 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5229 MDIO_REG_BANK_COMBO_IEEE0,
5230 MDIO_COMBO_IEEE0_MII_CONTROL,
5231 &mii_control);
ea4e040a
YR		 5232 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5233 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5234 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5235
8c99e7b0 5236 switch (vars->line_speed) {
ea4e040a
YR		 5237 case SPEED_100:
5238 mii_control |=
5239 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5240 break;
5241 case SPEED_1000:
5242 mii_control |=
5243 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5244 break;
5245 case SPEED_10:
d231023e 5246 /* There is nothing to set for 10M */
ea4e040a
YR		 5247 break;
5248 default:
d231023e 5249 /* Invalid speed for SGMII */
8c99e7b0
YR		 5250 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5251 vars->line_speed);
ea4e040a
YR		 5252 break;
5253 }
5254
d231023e 5255 /* Setting the full duplex */
7aa0711f 5256 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 5257 mii_control |=
5258 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 5259 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5260 MDIO_REG_BANK_COMBO_IEEE0,
5261 MDIO_COMBO_IEEE0_MII_CONTROL,
5262 mii_control);
ea4e040a
YR		 5263
5264 } else { /* AN mode */
d231023e 5265 /* Enable and restart AN */
e10bc84d 5266 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 5267 }
5268}
5269
8f73f0b9 5270/* Link management
ea4e040a 5271 */
fcf5b650
YR		 5272static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5273 struct link_params *params)
15ddd2d0
YR		 5274{
5275 struct bnx2x *bp = params->bp;
5276 u16 pd_10g, status2_1000x;
7aa0711f
YR		 5277 if (phy->req_line_speed != SPEED_AUTO_NEG)
5278 return 0;
cd2be89b 5279 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5280 MDIO_REG_BANK_SERDES_DIGITAL,
5281 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5282 &status2_1000x);
cd2be89b 5283 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5284 MDIO_REG_BANK_SERDES_DIGITAL,
5285 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5286 &status2_1000x);
15ddd2d0
YR		 5287 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5288 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5289 params->port);
5290 return 1;
5291 }
5292
cd2be89b 5293 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5294 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5295 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5296 &pd_10g);
15ddd2d0
YR		 5297
5298 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5299 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5300 params->port);
5301 return 1;
5302 }
5303 return 0;
5304}
ea4e040a 5305
9e7e8399
MY		 5306static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5307 struct link_params *params,
5308 struct link_vars *vars,
5309 u32 gp_status)
5310{
5311 u16 ld_pause; /* local driver */
5312 u16 lp_pause; /* link partner */
5313 u16 pause_result;
5314 struct bnx2x *bp = params->bp;
5315 if ((gp_status &
5316 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5317 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5318 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5319 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5320
5321 CL22_RD_OVER_CL45(bp, phy,
5322 MDIO_REG_BANK_CL73_IEEEB1,
5323 MDIO_CL73_IEEEB1_AN_ADV1,
5324 &ld_pause);
5325 CL22_RD_OVER_CL45(bp, phy,
5326 MDIO_REG_BANK_CL73_IEEEB1,
5327 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5328 &lp_pause);
5329 pause_result = (ld_pause &
5330 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5331 pause_result |= (lp_pause &
5332 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5333 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5334 } else {
5335 CL22_RD_OVER_CL45(bp, phy,
5336 MDIO_REG_BANK_COMBO_IEEE0,
5337 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5338 &ld_pause);
5339 CL22_RD_OVER_CL45(bp, phy,
5340 MDIO_REG_BANK_COMBO_IEEE0,
5341 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5342 &lp_pause);
5343 pause_result = (ld_pause &
5344 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5345 pause_result |= (lp_pause &
5346 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5347 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5348 }
5349 bnx2x_pause_resolve(vars, pause_result);
5350
5351}
5352
e10bc84d
YR		 5353static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5354 struct link_params *params,
5355 struct link_vars *vars,
5356 u32 gp_status)
ea4e040a
YR		 5357{
5358 struct bnx2x *bp = params->bp;
c0700f90 5359 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5360
d231023e 5361 /* Resolve from gp_status in case of AN complete and not sgmii */
9e7e8399
MY		 5362 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5363 /* Update the advertised flow-controled of LD/LP in AN */
5364 if (phy->req_line_speed == SPEED_AUTO_NEG)
5365 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5366 /* But set the flow-control result as the requested one */
7aa0711f 5367 vars->flow_ctrl = phy->req_flow_ctrl;
9e7e8399 5368 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
7aa0711f
YR		 5369 vars->flow_ctrl = params->req_fc_auto_adv;
5370 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5371 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 5372 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 5373 vars->flow_ctrl = params->req_fc_auto_adv;
5374 return;
5375 }
9e7e8399 5376 bnx2x_update_adv_fc(phy, params, vars, gp_status);
ea4e040a
YR		 5377 }
5378 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5379}
5380
e10bc84d
YR		 5381static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5382 struct link_params *params)
239d686d
EG		 5383{
5384 struct bnx2x *bp = params->bp;
9045f6b4 5385 u16 rx_status, ustat_val, cl37_fsm_received;
239d686d
EG		 5386 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5387 /* Step 1: Make sure signal is detected */
cd2be89b 5388 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5389 MDIO_REG_BANK_RX0,
5390 MDIO_RX0_RX_STATUS,
5391 &rx_status);
239d686d
EG		 5392 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5393 (MDIO_RX0_RX_STATUS_SIGDET)) {
5394 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5395 "rx_status(0x80b0) = 0x%x\n", rx_status);
cd2be89b 5396 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5397 MDIO_REG_BANK_CL73_IEEEB0,
5398 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5399 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
239d686d
EG		 5400 return;
5401 }
5402 /* Step 2: Check CL73 state machine */
cd2be89b 5403 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5404 MDIO_REG_BANK_CL73_USERB0,
5405 MDIO_CL73_USERB0_CL73_USTAT1,
5406 &ustat_val);
239d686d
EG		 5407 if ((ustat_val &
5408 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5409 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5410 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5411 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5412 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5413 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5414 return;
5415 }
8f73f0b9 5416 /* Step 3: Check CL37 Message Pages received to indicate LP
2cf7acf9
YR		 5417 * supports only CL37
5418 */
cd2be89b 5419 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5420 MDIO_REG_BANK_REMOTE_PHY,
5421 MDIO_REMOTE_PHY_MISC_RX_STATUS,
9045f6b4
YR		 5422 &cl37_fsm_received);
5423 if ((cl37_fsm_received &
239d686d
EG		 5424 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5425 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5426 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5427 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5428 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5429 "misc_rx_status(0x8330) = 0x%x\n",
9045f6b4 5430 cl37_fsm_received);
239d686d
EG		 5431 return;
5432 }
8f73f0b9 5433 /* The combined cl37/cl73 fsm state information indicating that
2cf7acf9
YR		 5434 * we are connected to a device which does not support cl73, but
5435 * does support cl37 BAM. In this case we disable cl73 and
5436 * restart cl37 auto-neg
5437 */
5438
239d686d 5439 /* Disable CL73 */
cd2be89b 5440 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5441 MDIO_REG_BANK_CL73_IEEEB0,
5442 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5443 0);
239d686d 5444 /* Restart CL37 autoneg */
e10bc84d 5445 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 5446 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5447}
7aa0711f
YR		 5448
5449static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5450 struct link_params *params,
5451 struct link_vars *vars,
5452 u32 gp_status)
5453{
5454 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5455 vars->link_status |=
5456 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5457
5458 if (bnx2x_direct_parallel_detect_used(phy, params))
5459 vars->link_status |=
5460 LINK_STATUS_PARALLEL_DETECTION_USED;
5461}
3c9ada22
YR		 5462static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5463 struct link_params *params,
5464 struct link_vars *vars,
5465 u16 is_link_up,
5466 u16 speed_mask,
5467 u16 is_duplex)
ea4e040a
YR		 5468{
5469 struct bnx2x *bp = params->bp;
7aa0711f
YR		 5470 if (phy->req_line_speed == SPEED_AUTO_NEG)
5471 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3c9ada22
YR		 5472 if (is_link_up) {
5473 DP(NETIF_MSG_LINK, "phy link up\n");
ea4e040a
YR		 5474
5475 vars->phy_link_up = 1;
5476 vars->link_status |= LINK_STATUS_LINK_UP;
5477
3c9ada22 5478 switch (speed_mask) {
ea4e040a 5479 case GP_STATUS_10M:
3c9ada22 5480 vars->line_speed = SPEED_10;
430d172a 5481 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5482 vars->link_status |= LINK_10TFD;
5483 else
5484 vars->link_status |= LINK_10THD;
5485 break;
5486
5487 case GP_STATUS_100M:
3c9ada22 5488 vars->line_speed = SPEED_100;
430d172a 5489 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5490 vars->link_status |= LINK_100TXFD;
5491 else
5492 vars->link_status |= LINK_100TXHD;
5493 break;
5494
5495 case GP_STATUS_1G:
5496 case GP_STATUS_1G_KX:
3c9ada22 5497 vars->line_speed = SPEED_1000;
430d172a 5498 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5499 vars->link_status |= LINK_1000TFD;
5500 else
5501 vars->link_status |= LINK_1000THD;
5502 break;
5503
5504 case GP_STATUS_2_5G:
3c9ada22 5505 vars->line_speed = SPEED_2500;
430d172a 5506 if (is_duplex == DUPLEX_FULL)
ea4e040a
YR		 5507 vars->link_status |= LINK_2500TFD;
5508 else
5509 vars->link_status |= LINK_2500THD;
5510 break;
5511
5512 case GP_STATUS_5G:
5513 case GP_STATUS_6G:
5514 DP(NETIF_MSG_LINK,
5515 "link speed unsupported gp_status 0x%x\n",
3c9ada22 5516 speed_mask);
ea4e040a 5517 return -EINVAL;
ab6ad5a4 5518
ea4e040a
YR		 5519 case GP_STATUS_10G_KX4:
5520 case GP_STATUS_10G_HIG:
5521 case GP_STATUS_10G_CX4:
3c9ada22
YR		 5522 case GP_STATUS_10G_KR:
5523 case GP_STATUS_10G_SFI:
5524 case GP_STATUS_10G_XFI:
5525 vars->line_speed = SPEED_10000;
ea4e040a
YR		 5526 vars->link_status |= LINK_10GTFD;
5527 break;
3c9ada22 5528 case GP_STATUS_20G_DXGXS:
4e7b4997 5529 case GP_STATUS_20G_KR2:
3c9ada22
YR		 5530 vars->line_speed = SPEED_20000;
5531 vars->link_status |= LINK_20GTFD;
5532 break;
ea4e040a
YR		 5533 default:
5534 DP(NETIF_MSG_LINK,
5535 "link speed unsupported gp_status 0x%x\n",
3c9ada22 5536 speed_mask);
ab6ad5a4 5537 return -EINVAL;
ea4e040a 5538 }
ea4e040a
YR		 5539 } else { /* link_down */
5540 DP(NETIF_MSG_LINK, "phy link down\n");
5541
5542 vars->phy_link_up = 0;
57963ed9 5543
ea4e040a 5544 vars->duplex = DUPLEX_FULL;
c0700f90 5545 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5546 vars->mac_type = MAC_TYPE_NONE;
3c9ada22
YR		 5547 }
5548 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5549 vars->phy_link_up, vars->line_speed);
5550 return 0;
5551}
5552
5553static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5554 struct link_params *params,
5555 struct link_vars *vars)
5556{
3c9ada22
YR		 5557 struct bnx2x *bp = params->bp;
5558
5559 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5560 int rc = 0;
5561
5562 /* Read gp_status */
5563 CL22_RD_OVER_CL45(bp, phy,
5564 MDIO_REG_BANK_GP_STATUS,
5565 MDIO_GP_STATUS_TOP_AN_STATUS1,
5566 &gp_status);
5567 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5568 duplex = DUPLEX_FULL;
5569 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5570 link_up = 1;
5571 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5572 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5573 gp_status, link_up, speed_mask);
5574 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5575 duplex);
5576 if (rc == -EINVAL)
5577 return rc;
239d686d 5578
3c9ada22
YR		 5579 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5580 if (SINGLE_MEDIA_DIRECT(params)) {
430d172a 5581 vars->duplex = duplex;
3c9ada22
YR		 5582 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5583 if (phy->req_line_speed == SPEED_AUTO_NEG)
5584 bnx2x_xgxs_an_resolve(phy, params, vars,
5585 gp_status);
5586 }
d231023e 5587 } else { /* Link_down */
c18aa15d
YR		 5588 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5589 SINGLE_MEDIA_DIRECT(params)) {
239d686d 5590 /* Check signal is detected */
c18aa15d 5591 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 5592 }
ea4e040a
YR		 5593 }
5594
9e7e8399
MY		 5595 /* Read LP advertised speeds*/
5596 if (SINGLE_MEDIA_DIRECT(params) &&
5597 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5598 u16 val;
5599
5600 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5601 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5602
5603 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5604 vars->link_status |=
5605 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5606 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5607 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5608 vars->link_status |=
5609 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5610
5611 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5612 MDIO_OVER_1G_LP_UP1, &val);
5613
5614 if (val & MDIO_OVER_1G_UP1_2_5G)
5615 vars->link_status |=
5616 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5617 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5618 vars->link_status |=
5619 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5620 }
5621
a22f0788
YR		 5622 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5623 vars->duplex, vars->flow_ctrl, vars->link_status);
ea4e040a
YR		 5624 return rc;
5625}
5626
3c9ada22
YR		 5627static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5628 struct link_params *params,
5629 struct link_vars *vars)
5630{
3c9ada22 5631 struct bnx2x *bp = params->bp;
3c9ada22
YR		 5632 u8 lane;
5633 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5634 int rc = 0;
5635 lane = bnx2x_get_warpcore_lane(phy, params);
5636 /* Read gp_status */
4e7b4997
YR		 5637 if ((params->loopback_mode) &&
5638 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5639 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5640 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5641 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5642 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5643 link_up &= 0x1;
5644 } else if ((phy->req_line_speed > SPEED_10000) &&
5645 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
3c9ada22
YR		 5646 u16 temp_link_up;
5647 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5648 1, &temp_link_up);
5649 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5650 1, &link_up);
5651 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5652 temp_link_up, link_up);
5653 link_up &= (1<<2);
5654 if (link_up)
5655 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5656 } else {
5657 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4e7b4997
YR		 5658 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5659 &gp_status1);
3c9ada22 5660 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
4e7b4997
YR		 5661 /* Check for either KR, 1G, or AN up. */
5662 link_up = ((gp_status1 >> 8) |
5663 (gp_status1 >> 12) |
5664 (gp_status1)) &
5665 (1 << lane);
5666 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5667 u16 an_link;
5668 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5669 MDIO_AN_REG_STATUS, &an_link);
5670 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5671 MDIO_AN_REG_STATUS, &an_link);
5672 link_up |= (an_link & (1<<2));
5673 }
3c9ada22
YR		 5674 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5675 u16 pd, gp_status4;
5676 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5677 /* Check Autoneg complete */
5678 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5679 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5680 &gp_status4);
5681 if (gp_status4 & ((1<<12)<<lane))
5682 vars->link_status |=
5683 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5684
5685 /* Check parallel detect used */
5686 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5687 MDIO_WC_REG_PAR_DET_10G_STATUS,
5688 &pd);
5689 if (pd & (1<<15))
5690 vars->link_status |=
5691 LINK_STATUS_PARALLEL_DETECTION_USED;
5692 }
5693 bnx2x_ext_phy_resolve_fc(phy, params, vars);
430d172a 5694 vars->duplex = duplex;
3c9ada22
YR		 5695 }
5696 }
5697
9e7e8399
MY		 5698 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5699 SINGLE_MEDIA_DIRECT(params)) {
5700 u16 val;
5701
5702 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5703 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5704
5705 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5706 vars->link_status |=
5707 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5708 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5709 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5710 vars->link_status |=
5711 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5712
5713 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5714 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5715
5716 if (val & MDIO_OVER_1G_UP1_2_5G)
5717 vars->link_status |=
5718 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5719 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5720 vars->link_status |=
5721 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5722
5723 }
5724
5725
3c9ada22
YR		 5726 if (lane < 2) {
5727 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5728 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5729 } else {
5730 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5731 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5732 }
5733 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5734
5735 if ((lane & 1) == 0)
5736 gp_speed <<= 8;
5737 gp_speed &= 0x3f00;
4e7b4997 5738 link_up = !!link_up;
3c9ada22
YR		 5739
5740 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5741 duplex);
5742
5743 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5744 vars->duplex, vars->flow_ctrl, vars->link_status);
5745 return rc;
5746}
ed8680a7 5747static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 5748{
5749 struct bnx2x *bp = params->bp;
e10bc84d 5750 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 5751 u16 lp_up2;
5752 u16 tx_driver;
c2c8b03e 5753 u16 bank;
ea4e040a 5754
d231023e 5755 /* Read precomp */
cd2be89b 5756 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5757 MDIO_REG_BANK_OVER_1G,
5758 MDIO_OVER_1G_LP_UP2, &lp_up2);
ea4e040a 5759
d231023e 5760 /* Bits [10:7] at lp_up2, positioned at [15:12] */
ea4e040a
YR		 5761 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5762 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5763 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5764
c2c8b03e
EG		 5765 if (lp_up2 == 0)
5766 return;
5767
5768 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5769 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
cd2be89b 5770 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 5771 bank,
5772 MDIO_TX0_TX_DRIVER, &tx_driver);
c2c8b03e 5773
d231023e 5774 /* Replace tx_driver bits [15:12] */
c2c8b03e
EG		 5775 if (lp_up2 !=
5776 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5777 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5778 tx_driver |= lp_up2;
cd2be89b 5779 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 5780 bank,
5781 MDIO_TX0_TX_DRIVER, tx_driver);
c2c8b03e 5782 }
ea4e040a
YR		 5783 }
5784}
5785
fcf5b650
YR		 5786static int bnx2x_emac_program(struct link_params *params,
5787 struct link_vars *vars)
ea4e040a
YR		 5788{
5789 struct bnx2x *bp = params->bp;
5790 u8 port = params->port;
5791 u16 mode = 0;
5792
5793 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5794 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
cd88ccee
YR		 5795 EMAC_REG_EMAC_MODE,
5796 (EMAC_MODE_25G_MODE |
5797 EMAC_MODE_PORT_MII_10M |
5798 EMAC_MODE_HALF_DUPLEX));
b7737c9b 5799 switch (vars->line_speed) {
ea4e040a
YR		 5800 case SPEED_10:
5801 mode |= EMAC_MODE_PORT_MII_10M;
5802 break;
5803
5804 case SPEED_100:
5805 mode |= EMAC_MODE_PORT_MII;
5806 break;
5807
5808 case SPEED_1000:
5809 mode |= EMAC_MODE_PORT_GMII;
5810 break;
5811
5812 case SPEED_2500:
5813 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5814 break;
5815
5816 default:
5817 /* 10G not valid for EMAC */
b7737c9b
YR		 5818 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5819 vars->line_speed);
ea4e040a
YR		 5820 return -EINVAL;
5821 }
5822
b7737c9b 5823 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 5824 mode |= EMAC_MODE_HALF_DUPLEX;
5825 bnx2x_bits_en(bp,
cd88ccee
YR		 5826 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5827 mode);
ea4e040a 5828
7f02c4ad 5829 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 5830 return 0;
5831}
5832
de6eae1f
YR		 5833static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5834 struct link_params *params)
b7737c9b 5835{
de6eae1f
YR		 5836
5837 u16 bank, i = 0;
5838 struct bnx2x *bp = params->bp;
5839
5840 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5841 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
cd2be89b 5842 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 5843 bank,
5844 MDIO_RX0_RX_EQ_BOOST,
5845 phy->rx_preemphasis[i]);
5846 }
5847
5848 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5849 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
cd2be89b 5850 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 5851 bank,
5852 MDIO_TX0_TX_DRIVER,
5853 phy->tx_preemphasis[i]);
5854 }
5855}
5856
ec146a6f
YR		 5857static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5858 struct link_params *params,
5859 struct link_vars *vars)
de6eae1f
YR		 5860{
5861 struct bnx2x *bp = params->bp;
5862 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5863 (params->loopback_mode == LOOPBACK_XGXS));
5864 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5865 if (SINGLE_MEDIA_DIRECT(params) &&
5866 (params->feature_config_flags &
5867 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5868 bnx2x_set_preemphasis(phy, params);
5869
d231023e 5870 /* Forced speed requested? */
de6eae1f
YR		 5871 if (vars->line_speed != SPEED_AUTO_NEG ||
5872 (SINGLE_MEDIA_DIRECT(params) &&
cd88ccee 5873 params->loopback_mode == LOOPBACK_EXT)) {
de6eae1f
YR		 5874 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5875
d231023e 5876 /* Disable autoneg */
de6eae1f
YR		 5877 bnx2x_set_autoneg(phy, params, vars, 0);
5878
d231023e 5879 /* Program speed and duplex */
de6eae1f
YR		 5880 bnx2x_program_serdes(phy, params, vars);
5881
5882 } else { /* AN_mode */
5883 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5884
5885 /* AN enabled */
9045f6b4 5886 bnx2x_set_brcm_cl37_advertisement(phy, params);
de6eae1f 5887
d231023e 5888 /* Program duplex & pause advertisement (for aneg) */
9045f6b4
YR		 5889 bnx2x_set_ieee_aneg_advertisement(phy, params,
5890 vars->ieee_fc);
de6eae1f 5891
d231023e 5892 /* Enable autoneg */
de6eae1f
YR		 5893 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5894
d231023e 5895 /* Enable and restart AN */
de6eae1f
YR		 5896 bnx2x_restart_autoneg(phy, params, enable_cl73);
5897 }
5898
5899 } else { /* SGMII mode */
5900 DP(NETIF_MSG_LINK, "SGMII\n");
5901
5902 bnx2x_initialize_sgmii_process(phy, params, vars);
5903 }
5904}
5905
ec146a6f
YR		 5906static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5907 struct link_params *params,
5908 struct link_vars *vars)
b7737c9b 5909{
fcf5b650 5910 int rc;
ec146a6f 5911 vars->phy_flags |= PHY_XGXS_FLAG;
b7737c9b
YR		 5912 if ((phy->req_line_speed &&
5913 ((phy->req_line_speed == SPEED_100) ||
5914 (phy->req_line_speed == SPEED_10))) ||
5915 (!phy->req_line_speed &&
5916 (phy->speed_cap_mask >=
5917 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5918 (phy->speed_cap_mask <
ec146a6f
YR		 5919 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5920 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
b7737c9b
YR		 5921 vars->phy_flags |= PHY_SGMII_FLAG;
5922 else
5923 vars->phy_flags &= ~PHY_SGMII_FLAG;
5924
5925 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
ec146a6f
YR		 5926 bnx2x_set_aer_mmd(params, phy);
5927 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5928 bnx2x_set_master_ln(params, phy);
b7737c9b
YR		 5929
5930 rc = bnx2x_reset_unicore(params, phy, 0);
d231023e
YM		 5931 /* Reset the SerDes and wait for reset bit return low */
5932 if (rc)
b7737c9b
YR		 5933 return rc;
5934
ec146a6f 5935 bnx2x_set_aer_mmd(params, phy);
d231023e 5936 /* Setting the masterLn_def again after the reset */
ec146a6f
YR		 5937 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5938 bnx2x_set_master_ln(params, phy);
5939 bnx2x_set_swap_lanes(params, phy);
5940 }
b7737c9b
YR		 5941
5942 return rc;
5943}
c18aa15d 5944
de6eae1f 5945static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6d870c39
YR		 5946 struct bnx2x_phy *phy,
5947 struct link_params *params)
ea4e040a 5948{
de6eae1f 5949 u16 cnt, ctrl;
25985edc 5950 /* Wait for soft reset to get cleared up to 1 sec */
de6eae1f 5951 for (cnt = 0; cnt < 1000; cnt++) {
52c4d6c4 5952 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6583e33b
YR		 5953 bnx2x_cl22_read(bp, phy,
5954 MDIO_PMA_REG_CTRL, &ctrl);
5955 else
5956 bnx2x_cl45_read(bp, phy,
5957 MDIO_PMA_DEVAD,
5958 MDIO_PMA_REG_CTRL, &ctrl);
de6eae1f
YR		 5959 if (!(ctrl & (1<<15)))
5960 break;
d231023e 5961 usleep_range(1000, 2000);
de6eae1f 5962 }
6d870c39
YR		 5963
5964 if (cnt == 1000)
5965 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5966 " Port %d\n",
5967 params->port);
de6eae1f
YR		 5968 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5969 return cnt;
ea4e040a
YR		 5970}
5971
de6eae1f 5972static void bnx2x_link_int_enable(struct link_params *params)
a35da8db 5973{
de6eae1f
YR		 5974 u8 port = params->port;
5975 u32 mask;
5976 struct bnx2x *bp = params->bp;
c18aa15d 5977
2cf7acf9 5978 /* Setting the status to report on link up for either XGXS or SerDes */
3c9ada22
YR		 5979 if (CHIP_IS_E3(bp)) {
5980 mask = NIG_MASK_XGXS0_LINK_STATUS;
5981 if (!(SINGLE_MEDIA_DIRECT(params)))
5982 mask |= NIG_MASK_MI_INT;
5983 } else if (params->switch_cfg == SWITCH_CFG_10G) {
de6eae1f
YR		 5984 mask = (NIG_MASK_XGXS0_LINK10G |
5985 NIG_MASK_XGXS0_LINK_STATUS);
5986 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5987 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5988 params->phy[INT_PHY].type !=
5989 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5990 mask |= NIG_MASK_MI_INT;
5991 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5992 }
5993
5994 } else { /* SerDes */
5995 mask = NIG_MASK_SERDES0_LINK_STATUS;
5996 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5997 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5998 params->phy[INT_PHY].type !=
5999 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6000 mask |= NIG_MASK_MI_INT;
6001 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6002 }
6003 }
6004 bnx2x_bits_en(bp,
6005 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6006 mask);
6007
6008 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6009 (params->switch_cfg == SWITCH_CFG_10G),
6010 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6011 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6012 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6013 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6014 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6015 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6016 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6017 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
a35da8db
EG		 6018}
6019
a22f0788
YR		 6020static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6021 u8 exp_mi_int)
a35da8db 6022{
a22f0788
YR		 6023 u32 latch_status = 0;
6024
8f73f0b9 6025 /* Disable the MI INT ( external phy int ) by writing 1 to the
a22f0788
YR		 6026 * status register. Link down indication is high-active-signal,
6027 * so in this case we need to write the status to clear the XOR
de6eae1f
YR		 6028 */
6029 /* Read Latched signals */
6030 latch_status = REG_RD(bp,
a22f0788
YR		 6031 NIG_REG_LATCH_STATUS_0 + port*8);
6032 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
de6eae1f 6033 /* Handle only those with latched-signal=up.*/
a22f0788
YR		 6034 if (exp_mi_int)
6035 bnx2x_bits_en(bp,
6036 NIG_REG_STATUS_INTERRUPT_PORT0
6037 + port*4,
6038 NIG_STATUS_EMAC0_MI_INT);
6039 else
6040 bnx2x_bits_dis(bp,
6041 NIG_REG_STATUS_INTERRUPT_PORT0
6042 + port*4,
6043 NIG_STATUS_EMAC0_MI_INT);
6044
de6eae1f 6045 if (latch_status & 1) {
a22f0788 6046
de6eae1f
YR		 6047 /* For all latched-signal=up : Re-Arm Latch signals */
6048 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
cd88ccee 6049 (latch_status & 0xfffe) | (latch_status & 1));
de6eae1f 6050 }
a22f0788 6051 /* For all latched-signal=up,Write original_signal to status */
a35da8db
EG		 6052}
6053
de6eae1f 6054static void bnx2x_link_int_ack(struct link_params *params,
3c9ada22 6055 struct link_vars *vars, u8 is_10g_plus)
b1607af5 6056{
e10bc84d 6057 struct bnx2x *bp = params->bp;
de6eae1f 6058 u8 port = params->port;
3c9ada22 6059 u32 mask;
8f73f0b9 6060 /* First reset all status we assume only one line will be
2cf7acf9
YR		 6061 * change at a time
6062 */
de6eae1f 6063 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 6064 (NIG_STATUS_XGXS0_LINK10G |
6065 NIG_STATUS_XGXS0_LINK_STATUS |
6066 NIG_STATUS_SERDES0_LINK_STATUS));
de6eae1f 6067 if (vars->phy_link_up) {
3c9ada22
YR		 6068 if (USES_WARPCORE(bp))
6069 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6070 else {
6071 if (is_10g_plus)
6072 mask = NIG_STATUS_XGXS0_LINK10G;
6073 else if (params->switch_cfg == SWITCH_CFG_10G) {
8f73f0b9 6074 /* Disable the link interrupt by writing 1 to
3c9ada22
YR		 6075 * the relevant lane in the status register
6076 */
6077 u32 ser_lane =
6078 ((params->lane_config &
de6eae1f
YR		 6079 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6080 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3c9ada22
YR		 6081 mask = ((1 << ser_lane) <<
6082 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6083 } else
6084 mask = NIG_STATUS_SERDES0_LINK_STATUS;
de6eae1f 6085 }
3c9ada22
YR		 6086 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6087 mask);
6088 bnx2x_bits_en(bp,
6089 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6090 mask);
ea4e040a 6091 }
ea4e040a 6092}
ea4e040a 6093
fcf5b650 6094static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
de6eae1f
YR		 6095{
6096 u8 *str_ptr = str;
6097 u32 mask = 0xf0000000;
6098 u8 shift = 8*4;
6099 u8 digit;
a22f0788 6100 u8 remove_leading_zeros = 1;
de6eae1f
YR		 6101 if (*len < 10) {
6102 /* Need more than 10chars for this format */
6103 *str_ptr = '\0';
a22f0788 6104 (*len)--;
de6eae1f 6105 return -EINVAL;
ea4e040a 6106 }
de6eae1f 6107 while (shift > 0) {
ea4e040a 6108
de6eae1f
YR		 6109 shift -= 4;
6110 digit = ((num & mask) >> shift);
a22f0788
YR		 6111 if (digit == 0 && remove_leading_zeros) {
6112 mask = mask >> 4;
6113 continue;
6114 } else if (digit < 0xa)
de6eae1f
YR		 6115 *str_ptr = digit + '0';
6116 else
6117 *str_ptr = digit - 0xa + 'a';
a22f0788 6118 remove_leading_zeros = 0;
de6eae1f 6119 str_ptr++;
a22f0788 6120 (*len)--;
de6eae1f
YR		 6121 mask = mask >> 4;
6122 if (shift == 4*4) {
a22f0788 6123 *str_ptr = '.';
de6eae1f 6124 str_ptr++;
a22f0788
YR		 6125 (*len)--;
6126 remove_leading_zeros = 1;
ea4e040a 6127 }
ea4e040a 6128 }
de6eae1f 6129 return 0;
ea4e040a
YR		 6130}
6131
a22f0788 6132
fcf5b650 6133static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
ea4e040a 6134{
de6eae1f
YR		 6135 str[0] = '\0';
6136 (*len)--;
6137 return 0;
6138}
ea4e040a 6139
a1e785e0
MY		 6140int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6141 u16 len)
de6eae1f
YR		 6142{
6143 struct bnx2x *bp;
6144 u32 spirom_ver = 0;
fcf5b650 6145 int status = 0;
de6eae1f 6146 u8 *ver_p = version;
a22f0788 6147 u16 remain_len = len;
de6eae1f
YR		 6148 if (version == NULL || params == NULL)
6149 return -EINVAL;
6150 bp = params->bp;
ea4e040a 6151
de6eae1f
YR		 6152 /* Extract first external phy*/
6153 version[0] = '\0';
6154 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 6155
a22f0788 6156 if (params->phy[EXT_PHY1].format_fw_ver) {
de6eae1f
YR		 6157 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6158 ver_p,
a22f0788
YR		 6159 &remain_len);
6160 ver_p += (len - remain_len);
6161 }
6162 if ((params->num_phys == MAX_PHYS) &&
6163 (params->phy[EXT_PHY2].ver_addr != 0)) {
cd88ccee 6164 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
a22f0788
YR		 6165 if (params->phy[EXT_PHY2].format_fw_ver) {
6166 *ver_p = '/';
6167 ver_p++;
6168 remain_len--;
6169 status |= params->phy[EXT_PHY2].format_fw_ver(
6170 spirom_ver,
6171 ver_p,
6172 &remain_len);
6173 ver_p = version + (len - remain_len);
6174 }
6175 }
6176 *ver_p = '\0';
de6eae1f 6177 return status;
6bbca910 6178}
ea4e040a 6179
de6eae1f
YR		 6180static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6181 struct link_params *params)
589abe3a 6182{
de6eae1f 6183 u8 port = params->port;
589abe3a 6184 struct bnx2x *bp = params->bp;
589abe3a 6185
de6eae1f 6186 if (phy->req_line_speed != SPEED_1000) {
3c9ada22 6187 u32 md_devad = 0;
589abe3a 6188
de6eae1f 6189 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
589abe3a 6190
3c9ada22 6191 if (!CHIP_IS_E3(bp)) {
d231023e 6192 /* Change the uni_phy_addr in the nig */
3c9ada22
YR		 6193 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6194 port*0x18));
cc1cb004 6195
3c9ada22
YR		 6196 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6197 0x5);
6198 }
589abe3a 6199
de6eae1f 6200 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6201 5,
6202 (MDIO_REG_BANK_AER_BLOCK +
6203 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6204 0x2800);
589abe3a 6205
de6eae1f 6206 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6207 5,
6208 (MDIO_REG_BANK_CL73_IEEEB0 +
6209 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6210 0x6041);
de6eae1f 6211 msleep(200);
d231023e 6212 /* Set aer mmd back */
ec146a6f 6213 bnx2x_set_aer_mmd(params, phy);
589abe3a 6214
3c9ada22 6215 if (!CHIP_IS_E3(bp)) {
d231023e 6216 /* And md_devad */
3c9ada22
YR		 6217 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6218 md_devad);
6219 }
de6eae1f
YR		 6220 } else {
6221 u16 mii_ctrl;
6222 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6223 bnx2x_cl45_read(bp, phy, 5,
6224 (MDIO_REG_BANK_COMBO_IEEE0 +
6225 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6226 &mii_ctrl);
6227 bnx2x_cl45_write(bp, phy, 5,
6228 (MDIO_REG_BANK_COMBO_IEEE0 +
6229 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6230 mii_ctrl |
6231 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6232 }
589abe3a
EG		 6233}
6234
fcf5b650
YR		 6235int bnx2x_set_led(struct link_params *params,
6236 struct link_vars *vars, u8 mode, u32 speed)
4d295db0 6237{
de6eae1f
YR		 6238 u8 port = params->port;
6239 u16 hw_led_mode = params->hw_led_mode;
fcf5b650
YR		 6240 int rc = 0;
6241 u8 phy_idx;
de6eae1f
YR		 6242 u32 tmp;
6243 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 6244 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6245 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6246 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6247 speed, hw_led_mode);
7f02c4ad
YR		 6248 /* In case */
6249 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6250 if (params->phy[phy_idx].set_link_led) {
6251 params->phy[phy_idx].set_link_led(
6252 &params->phy[phy_idx], params, mode);
6253 }
6254 }
6255
de6eae1f 6256 switch (mode) {
7f02c4ad 6257 case LED_MODE_FRONT_PANEL_OFF:
de6eae1f
YR		 6258 case LED_MODE_OFF:
6259 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6260 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
cd88ccee 6261 SHARED_HW_CFG_LED_MAC1);
589abe3a 6262
de6eae1f 6263 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
001cea77 6264 if (params->phy[EXT_PHY1].type ==
9379c9be
YR		 6265 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6266 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6267 EMAC_LED_100MB_OVERRIDE |
6268 EMAC_LED_10MB_OVERRIDE);
6269 else
6270 tmp |= EMAC_LED_OVERRIDE;
6271
6272 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
de6eae1f 6273 break;
589abe3a 6274
de6eae1f 6275 case LED_MODE_OPER:
8f73f0b9 6276 /* For all other phys, OPER mode is same as ON, so in case
7f02c4ad 6277 * link is down, do nothing
2cf7acf9 6278 */
7f02c4ad
YR		 6279 if (!vars->link_up)
6280 break;
6281 case LED_MODE_ON:
e4d78f12
YR		 6282 if (((params->phy[EXT_PHY1].type ==
6283 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6284 (params->phy[EXT_PHY1].type ==
6285 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
1f48353a 6286 CHIP_IS_E2(bp) && params->num_phys == 2) {
8f73f0b9 6287 /* This is a work-around for E2+8727 Configurations */
1f48353a
YR		 6288 if (mode == LED_MODE_ON ||
6289 speed == SPEED_10000){
6290 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6291 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6292
6293 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6294 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6295 (tmp | EMAC_LED_OVERRIDE));
8f73f0b9 6296 /* Return here without enabling traffic
ab505dec 6297 * LED blink and setting rate in ON mode.
793bd450
YR		 6298 * In oper mode, enabling LED blink
6299 * and setting rate is needed.
6300 */
6301 if (mode == LED_MODE_ON)
6302 return rc;
1f48353a 6303 }
793bd450 6304 } else if (SINGLE_MEDIA_DIRECT(params)) {
8f73f0b9 6305 /* This is a work-around for HW issue found when link
2cf7acf9
YR		 6306 * is up in CL73
6307 */
ab505dec
YR		 6308 if ((!CHIP_IS_E3(bp)) ||
6309 (CHIP_IS_E3(bp) &&
6310 mode == LED_MODE_ON))
6311 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6312
793bd450
YR		 6313 if (CHIP_IS_E1x(bp) ||
6314 CHIP_IS_E2(bp) ||
6315 (mode == LED_MODE_ON))
6316 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6317 else
6318 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6319 hw_led_mode);
001cea77
YR		 6320 } else if ((params->phy[EXT_PHY1].type ==
6321 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
9379c9be 6322 (mode == LED_MODE_ON)) {
001cea77
YR		 6323 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6324 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
9379c9be
YR		 6325 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6326 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6327 /* Break here; otherwise, it'll disable the
6328 * intended override.
6329 */
6330 break;
793bd450 6331 } else
001cea77
YR		 6332 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6333 hw_led_mode);
589abe3a 6334
cd88ccee 6335 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
de6eae1f 6336 /* Set blinking rate to ~15.9Hz */
26ffaf36
YR		 6337 if (CHIP_IS_E3(bp))
6338 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6339 LED_BLINK_RATE_VAL_E3);
6340 else
6341 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6342 LED_BLINK_RATE_VAL_E1X_E2);
de6eae1f 6343 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
cd88ccee 6344 port*4, 1);
9379c9be
YR		 6345 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6346 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6347 (tmp & (~EMAC_LED_OVERRIDE)));
589abe3a 6348
de6eae1f
YR		 6349 if (CHIP_IS_E1(bp) &&
6350 ((speed == SPEED_2500) ||
6351 (speed == SPEED_1000) ||
6352 (speed == SPEED_100) ||
6353 (speed == SPEED_10))) {
8f73f0b9 6354 /* For speeds less than 10G LED scheme is different */
de6eae1f 6355 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
cd88ccee 6356 + port*4, 1);
de6eae1f 6357 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
cd88ccee 6358 port*4, 0);
de6eae1f 6359 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
cd88ccee 6360 port*4, 1);
de6eae1f
YR		 6361 }
6362 break;
589abe3a 6363
de6eae1f
YR		 6364 default:
6365 rc = -EINVAL;
6366 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6367 mode);
6368 break;
589abe3a 6369 }
de6eae1f 6370 return rc;
589abe3a 6371
4d295db0
EG		 6372}
6373
8f73f0b9 6374/* This function comes to reflect the actual link state read DIRECTLY from the
a22f0788
YR		 6375 * HW
6376 */
fcf5b650
YR		 6377int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6378 u8 is_serdes)
4d295db0
EG		 6379{
6380 struct bnx2x *bp = params->bp;
de6eae1f 6381 u16 gp_status = 0, phy_index = 0;
a22f0788
YR		 6382 u8 ext_phy_link_up = 0, serdes_phy_type;
6383 struct link_vars temp_vars;
3c9ada22
YR		 6384 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6385
6386 if (CHIP_IS_E3(bp)) {
6387 u16 link_up;
6388 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6389 > SPEED_10000) {
6390 /* Check 20G link */
6391 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6392 1, &link_up);
6393 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6394 1, &link_up);
6395 link_up &= (1<<2);
6396 } else {
6397 /* Check 10G link and below*/
6398 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6399 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6400 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6401 &gp_status);
6402 gp_status = ((gp_status >> 8) & 0xf) |
6403 ((gp_status >> 12) & 0xf);
6404 link_up = gp_status & (1 << lane);
6405 }
6406 if (!link_up)
6407 return -ESRCH;
6408 } else {
6409 CL22_RD_OVER_CL45(bp, int_phy,
cd88ccee
YR		 6410 MDIO_REG_BANK_GP_STATUS,
6411 MDIO_GP_STATUS_TOP_AN_STATUS1,
6412 &gp_status);
d231023e 6413 /* Link is up only if both local phy and external phy are up */
a22f0788
YR		 6414 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6415 return -ESRCH;
3c9ada22
YR		 6416 }
6417 /* In XGXS loopback mode, do not check external PHY */
6418 if (params->loopback_mode == LOOPBACK_XGXS)
6419 return 0;
a22f0788
YR		 6420
6421 switch (params->num_phys) {
6422 case 1:
6423 /* No external PHY */
6424 return 0;
6425 case 2:
6426 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6427 &params->phy[EXT_PHY1],
6428 params, &temp_vars);
6429 break;
6430 case 3: /* Dual Media */
de6eae1f
YR		 6431 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6432 phy_index++) {
a22f0788 6433 serdes_phy_type = ((params->phy[phy_index].media_type ==
dbef807e
YM		 6434 ETH_PHY_SFPP_10G_FIBER) ||
6435 (params->phy[phy_index].media_type ==
6436 ETH_PHY_SFP_1G_FIBER) ||
a22f0788 6437 (params->phy[phy_index].media_type ==
1ac9e428
YR		 6438 ETH_PHY_XFP_FIBER) ||
6439 (params->phy[phy_index].media_type ==
6440 ETH_PHY_DA_TWINAX));
a22f0788
YR		 6441
6442 if (is_serdes != serdes_phy_type)
6443 continue;
6444 if (params->phy[phy_index].read_status) {
6445 ext_phy_link_up |=
de6eae1f
YR		 6446 params->phy[phy_index].read_status(
6447 &params->phy[phy_index],
6448 params, &temp_vars);
a22f0788 6449 }
de6eae1f 6450 }
a22f0788 6451 break;
4d295db0 6452 }
a22f0788
YR		 6453 if (ext_phy_link_up)
6454 return 0;
de6eae1f
YR		 6455 return -ESRCH;
6456}
4d295db0 6457
fcf5b650
YR		 6458static int bnx2x_link_initialize(struct link_params *params,
6459 struct link_vars *vars)
de6eae1f 6460{
fcf5b650 6461 int rc = 0;
de6eae1f
YR		 6462 u8 phy_index, non_ext_phy;
6463 struct bnx2x *bp = params->bp;
8f73f0b9 6464 /* In case of external phy existence, the line speed would be the
2cf7acf9
YR		 6465 * line speed linked up by the external phy. In case it is direct
6466 * only, then the line_speed during initialization will be
6467 * equal to the req_line_speed
6468 */
de6eae1f 6469 vars->line_speed = params->phy[INT_PHY].req_line_speed;
4d295db0 6470
8f73f0b9 6471 /* Initialize the internal phy in case this is a direct board
de6eae1f
YR		 6472 * (no external phys), or this board has external phy which requires
6473 * to first.
6474 */
3c9ada22
YR		 6475 if (!USES_WARPCORE(bp))
6476 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
de6eae1f
YR		 6477 /* init ext phy and enable link state int */
6478 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6479 (params->loopback_mode == LOOPBACK_XGXS));
4d295db0 6480
de6eae1f
YR		 6481 if (non_ext_phy ||
6482 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6483 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6484 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3c9ada22
YR		 6485 if (vars->line_speed == SPEED_AUTO_NEG &&
6486 (CHIP_IS_E1x(bp) ||
6487 CHIP_IS_E2(bp)))
de6eae1f 6488 bnx2x_set_parallel_detection(phy, params);
ec146a6f
YR		 6489 if (params->phy[INT_PHY].config_init)
6490 params->phy[INT_PHY].config_init(phy,
6491 params,
6492 vars);
4d295db0
EG		 6493 }
6494
de6eae1f 6495 /* Init external phy*/
fd36a2e6
YR		 6496 if (non_ext_phy) {
6497 if (params->phy[INT_PHY].supported &
6498 SUPPORTED_FIBRE)
6499 vars->link_status |= LINK_STATUS_SERDES_LINK;
6500 } else {
de6eae1f
YR		 6501 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6502 phy_index++) {
8f73f0b9 6503 /* No need to initialize second phy in case of first
a22f0788
YR		 6504 * phy only selection. In case of second phy, we do
6505 * need to initialize the first phy, since they are
6506 * connected.
2cf7acf9 6507 */
fd36a2e6
YR		 6508 if (params->phy[phy_index].supported &
6509 SUPPORTED_FIBRE)
6510 vars->link_status |= LINK_STATUS_SERDES_LINK;
6511
a22f0788
YR		 6512 if (phy_index == EXT_PHY2 &&
6513 (bnx2x_phy_selection(params) ==
6514 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
94f05b0f
JP		 6515 DP(NETIF_MSG_LINK,
6516 "Not initializing second phy\n");
a22f0788
YR		 6517 continue;
6518 }
de6eae1f
YR		 6519 params->phy[phy_index].config_init(
6520 &params->phy[phy_index],
6521 params, vars);
6522 }
fd36a2e6 6523 }
de6eae1f
YR		 6524 /* Reset the interrupt indication after phy was initialized */
6525 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6526 params->port*4,
6527 (NIG_STATUS_XGXS0_LINK10G |
6528 NIG_STATUS_XGXS0_LINK_STATUS |
6529 NIG_STATUS_SERDES0_LINK_STATUS |
6530 NIG_MASK_MI_INT));
6531 return rc;
6532}
4d295db0 6533
de6eae1f
YR		 6534static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6535 struct link_params *params)
6536{
d231023e 6537 /* Reset the SerDes/XGXS */
cd88ccee
YR		 6538 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6539 (0x1ff << (params->port*16)));
589abe3a
EG		 6540}
6541
de6eae1f
YR		 6542static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6543 struct link_params *params)
4d295db0 6544{
de6eae1f
YR		 6545 struct bnx2x *bp = params->bp;
6546 u8 gpio_port;
6547 /* HW reset */
f2e0899f
DK		 6548 if (CHIP_IS_E2(bp))
6549 gpio_port = BP_PATH(bp);
6550 else
6551 gpio_port = params->port;
de6eae1f 6552 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee
YR		 6553 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6554 gpio_port);
de6eae1f 6555 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 6556 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6557 gpio_port);
de6eae1f 6558 DP(NETIF_MSG_LINK, "reset external PHY\n");
4d295db0 6559}
589abe3a 6560
fcf5b650
YR		 6561static int bnx2x_update_link_down(struct link_params *params,
6562 struct link_vars *vars)
589abe3a
EG		 6563{
6564 struct bnx2x *bp = params->bp;
de6eae1f 6565 u8 port = params->port;
589abe3a 6566
de6eae1f 6567 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7f02c4ad 6568 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3deb8167 6569 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
d231023e 6570 /* Indicate no mac active */
de6eae1f 6571 vars->mac_type = MAC_TYPE_NONE;
ab6ad5a4 6572
d231023e 6573 /* Update shared memory */
4978140c 6574 vars->link_status &= ~LINK_UPDATE_MASK;
de6eae1f
YR		 6575 vars->line_speed = 0;
6576 bnx2x_update_mng(params, vars->link_status);
589abe3a 6577
d231023e 6578 /* Activate nig drain */
de6eae1f 6579 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4d295db0 6580
d231023e 6581 /* Disable emac */
9380bb9e
YR		 6582 if (!CHIP_IS_E3(bp))
6583 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
de6eae1f 6584
d231023e
YM		 6585 usleep_range(10000, 20000);
6586 /* Reset BigMac/Xmac */
9380bb9e 6587 if (CHIP_IS_E1x(bp) ||
d3a8f13b
YR		 6588 CHIP_IS_E2(bp))
6589 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6590
ce7c0489 6591 if (CHIP_IS_E3(bp)) {
d231023e 6592 /* Prevent LPI Generation by chip */
c8c60d88
YM		 6593 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6594 0);
c8c60d88
YM		 6595 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6596 0);
6597 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6598 SHMEM_EEE_ACTIVE_BIT);
6599
6600 bnx2x_update_mng_eee(params, vars->eee_status);
d3a8f13b
YR		 6601 bnx2x_set_xmac_rxtx(params, 0);
6602 bnx2x_set_umac_rxtx(params, 0);
ce7c0489 6603 }
9380bb9e 6604
589abe3a
EG		 6605 return 0;
6606}
de6eae1f 6607
fcf5b650
YR		 6608static int bnx2x_update_link_up(struct link_params *params,
6609 struct link_vars *vars,
6610 u8 link_10g)
589abe3a
EG		 6611{
6612 struct bnx2x *bp = params->bp;
55098c5c 6613 u8 phy_idx, port = params->port;
fcf5b650 6614 int rc = 0;
4d295db0 6615
de6f3377
YR		 6616 vars->link_status |= (LINK_STATUS_LINK_UP |
6617 LINK_STATUS_PHYSICAL_LINK_FLAG);
3deb8167 6618 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7f02c4ad 6619
de6eae1f
YR		 6620 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6621 vars->link_status |=
6622 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
589abe3a 6623
de6eae1f
YR		 6624 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6625 vars->link_status |=
6626 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
9380bb9e 6627 if (USES_WARPCORE(bp)) {
3deb8167
YR		 6628 if (link_10g) {
6629 if (bnx2x_xmac_enable(params, vars, 0) ==
6630 -ESRCH) {
6631 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6632 vars->link_up = 0;
6633 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6634 vars->link_status &= ~LINK_STATUS_LINK_UP;
6635 }
6636 } else
9380bb9e 6637 bnx2x_umac_enable(params, vars, 0);
7f02c4ad 6638 bnx2x_set_led(params, vars,
9380bb9e 6639 LED_MODE_OPER, vars->line_speed);
c8c60d88
YM		 6640
6641 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6642 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6643 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6644 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6645 (params->port << 2), 1);
6646 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6647 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6648 (params->port << 2), 0xfc20);
6649 }
9380bb9e
YR		 6650 }
6651 if ((CHIP_IS_E1x(bp) ||
6652 CHIP_IS_E2(bp))) {
6653 if (link_10g) {
d3a8f13b 6654 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
3deb8167
YR		 6655 -ESRCH) {
6656 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6657 vars->link_up = 0;
6658 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6659 vars->link_status &= ~LINK_STATUS_LINK_UP;
6660 }
cc1cb004 6661
9380bb9e
YR		 6662 bnx2x_set_led(params, vars,
6663 LED_MODE_OPER, SPEED_10000);
6664 } else {
6665 rc = bnx2x_emac_program(params, vars);
6666 bnx2x_emac_enable(params, vars, 0);
6667
6668 /* AN complete? */
6669 if ((vars->link_status &
6670 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6671 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6672 SINGLE_MEDIA_DIRECT(params))
6673 bnx2x_set_gmii_tx_driver(params);
6674 }
de6eae1f 6675 }
cc1cb004 6676
de6eae1f 6677 /* PBF - link up */
9380bb9e 6678 if (CHIP_IS_E1x(bp))
f2e0899f
DK		 6679 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6680 vars->line_speed);
589abe3a 6681
d231023e 6682 /* Disable drain */
de6eae1f 6683 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
589abe3a 6684
d231023e 6685 /* Update shared memory */
de6eae1f 6686 bnx2x_update_mng(params, vars->link_status);
c8c60d88 6687 bnx2x_update_mng_eee(params, vars->eee_status);
55098c5c
YR		 6688 /* Check remote fault */
6689 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6690 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6691 bnx2x_check_half_open_conn(params, vars, 0);
6692 break;
6693 }
6694 }
de6eae1f
YR		 6695 msleep(20);
6696 return rc;
589abe3a 6697}
8f73f0b9 6698/* The bnx2x_link_update function should be called upon link
de6eae1f
YR		 6699 * interrupt.
6700 * Link is considered up as follows:
6701 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6702 * to be up
6703 * - SINGLE_MEDIA - The link between the 577xx and the external
6704 * phy (XGXS) need to up as well as the external link of the
6705 * phy (PHY_EXT1)
6706 * - DUAL_MEDIA - The link between the 577xx and the first
6707 * external phy needs to be up, and at least one of the 2
6708 * external phy link must be up.
6709 */
fcf5b650 6710int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4d295db0 6711{
de6eae1f
YR		 6712 struct bnx2x *bp = params->bp;
6713 struct link_vars phy_vars[MAX_PHYS];
6714 u8 port = params->port;
3c9ada22 6715 u8 link_10g_plus, phy_index;
fcf5b650
YR		 6716 u8 ext_phy_link_up = 0, cur_link_up;
6717 int rc = 0;
de6eae1f
YR		 6718 u8 is_mi_int = 0;
6719 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6720 u8 active_external_phy = INT_PHY;
3deb8167 6721 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
4978140c 6722 vars->link_status &= ~LINK_UPDATE_MASK;
de6eae1f
YR		 6723 for (phy_index = INT_PHY; phy_index < params->num_phys;
6724 phy_index++) {
6725 phy_vars[phy_index].flow_ctrl = 0;
6726 phy_vars[phy_index].link_status = 0;
6727 phy_vars[phy_index].line_speed = 0;
6728 phy_vars[phy_index].duplex = DUPLEX_FULL;
6729 phy_vars[phy_index].phy_link_up = 0;
6730 phy_vars[phy_index].link_up = 0;
c688fe2f 6731 phy_vars[phy_index].fault_detected = 0;
c8c60d88
YM		 6732 /* different consideration, since vars holds inner state */
6733 phy_vars[phy_index].eee_status = vars->eee_status;
de6eae1f 6734 }
4d295db0 6735
3c9ada22
YR		 6736 if (USES_WARPCORE(bp))
6737 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6738
de6eae1f
YR		 6739 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6740 port, (vars->phy_flags & PHY_XGXS_FLAG),
6741 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4d295db0 6742
de6eae1f 6743 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
cd88ccee 6744 port*0x18) > 0);
de6eae1f
YR		 6745 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6746 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6747 is_mi_int,
cd88ccee 6748 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4d295db0 6749
de6eae1f
YR		 6750 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6751 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6752 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4d295db0 6753
d231023e 6754 /* Disable emac */
9380bb9e
YR		 6755 if (!CHIP_IS_E3(bp))
6756 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4d295db0 6757
8f73f0b9 6758 /* Step 1:
2cf7acf9
YR		 6759 * Check external link change only for external phys, and apply
6760 * priority selection between them in case the link on both phys
9045f6b4 6761 * is up. Note that instead of the common vars, a temporary
2cf7acf9
YR		 6762 * vars argument is used since each phy may have different link/
6763 * speed/duplex result
6764 */
de6eae1f
YR		 6765 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6766 phy_index++) {
6767 struct bnx2x_phy *phy = &params->phy[phy_index];
6768 if (!phy->read_status)
6769 continue;
6770 /* Read link status and params of this ext phy */
6771 cur_link_up = phy->read_status(phy, params,
6772 &phy_vars[phy_index]);
6773 if (cur_link_up) {
6774 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6775 phy_index);
6776 } else {
6777 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6778 phy_index);
6779 continue;
6780 }
e10bc84d 6781
de6eae1f
YR		 6782 if (!ext_phy_link_up) {
6783 ext_phy_link_up = 1;
6784 active_external_phy = phy_index;
a22f0788
YR		 6785 } else {
6786 switch (bnx2x_phy_selection(params)) {
6787 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6788 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
8f73f0b9 6789 /* In this option, the first PHY makes sure to pass the
a22f0788
YR		 6790 * traffic through itself only.
6791 * Its not clear how to reset the link on the second phy
2cf7acf9 6792 */
a22f0788
YR		 6793 active_external_phy = EXT_PHY1;
6794 break;
6795 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
8f73f0b9 6796 /* In this option, the first PHY makes sure to pass the
a22f0788 6797 * traffic through the second PHY.
2cf7acf9 6798 */
a22f0788
YR		 6799 active_external_phy = EXT_PHY2;
6800 break;
6801 default:
8f73f0b9 6802 /* Link indication on both PHYs with the following cases
a22f0788
YR		 6803 * is invalid:
6804 * - FIRST_PHY means that second phy wasn't initialized,
6805 * hence its link is expected to be down
6806 * - SECOND_PHY means that first phy should not be able
6807 * to link up by itself (using configuration)
6808 * - DEFAULT should be overriden during initialiazation
2cf7acf9 6809 */
a22f0788
YR		 6810 DP(NETIF_MSG_LINK, "Invalid link indication"
6811 "mpc=0x%x. DISABLING LINK !!!\n",
6812 params->multi_phy_config);
6813 ext_phy_link_up = 0;
6814 break;
6815 }
589abe3a 6816 }
589abe3a 6817 }
de6eae1f 6818 prev_line_speed = vars->line_speed;
8f73f0b9 6819 /* Step 2:
2cf7acf9
YR		 6820 * Read the status of the internal phy. In case of
6821 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6822 * otherwise this is the link between the 577xx and the first
6823 * external phy
6824 */
de6eae1f
YR		 6825 if (params->phy[INT_PHY].read_status)
6826 params->phy[INT_PHY].read_status(
6827 &params->phy[INT_PHY],
6828 params, vars);
8f73f0b9 6829 /* The INT_PHY flow control reside in the vars. This include the
de6eae1f
YR		 6830 * case where the speed or flow control are not set to AUTO.
6831 * Otherwise, the active external phy flow control result is set
6832 * to the vars. The ext_phy_line_speed is needed to check if the
6833 * speed is different between the internal phy and external phy.
6834 * This case may be result of intermediate link speed change.
4d295db0 6835 */
de6eae1f
YR		 6836 if (active_external_phy > INT_PHY) {
6837 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
8f73f0b9 6838 /* Link speed is taken from the XGXS. AN and FC result from
de6eae1f 6839 * the external phy.
4d295db0 6840 */
de6eae1f 6841 vars->link_status |= phy_vars[active_external_phy].link_status;
a22f0788 6842
8f73f0b9 6843 /* if active_external_phy is first PHY and link is up - disable
a22f0788
YR		 6844 * disable TX on second external PHY
6845 */
6846 if (active_external_phy == EXT_PHY1) {
6847 if (params->phy[EXT_PHY2].phy_specific_func) {
94f05b0f
JP		 6848 DP(NETIF_MSG_LINK,
6849 "Disabling TX on EXT_PHY2\n");
a22f0788
YR		 6850 params->phy[EXT_PHY2].phy_specific_func(
6851 &params->phy[EXT_PHY2],
6852 params, DISABLE_TX);
6853 }
6854 }
6855
de6eae1f
YR		 6856 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6857 vars->duplex = phy_vars[active_external_phy].duplex;
6858 if (params->phy[active_external_phy].supported &
6859 SUPPORTED_FIBRE)
6860 vars->link_status |= LINK_STATUS_SERDES_LINK;
fd36a2e6
YR		 6861 else
6862 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
c8c60d88
YM		 6863
6864 vars->eee_status = phy_vars[active_external_phy].eee_status;
6865
de6eae1f
YR		 6866 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6867 active_external_phy);
6868 }
a22f0788
YR		 6869
6870 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6871 phy_index++) {
6872 if (params->phy[phy_index].flags &
6873 FLAGS_REARM_LATCH_SIGNAL) {
6874 bnx2x_rearm_latch_signal(bp, port,
6875 phy_index ==
6876 active_external_phy);
6877 break;
6878 }
6879 }
de6eae1f
YR		 6880 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6881 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6882 vars->link_status, ext_phy_line_speed);
8f73f0b9 6883 /* Upon link speed change set the NIG into drain mode. Comes to
de6eae1f
YR		 6884 * deals with possible FIFO glitch due to clk change when speed
6885 * is decreased without link down indicator
6886 */
4d295db0 6887
de6eae1f
YR		 6888 if (vars->phy_link_up) {
6889 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6890 (ext_phy_line_speed != vars->line_speed)) {
6891 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6892 " different than the external"
6893 " link speed %d\n", vars->line_speed,
6894 ext_phy_line_speed);
6895 vars->phy_link_up = 0;
6896 } else if (prev_line_speed != vars->line_speed) {
cd88ccee
YR		 6897 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6898 0);
503976e9 6899 usleep_range(1000, 2000);
de6eae1f
YR		 6900 }
6901 }
e10bc84d 6902
d231023e 6903 /* Anything 10 and over uses the bmac */
3c9ada22 6904 link_10g_plus = (vars->line_speed >= SPEED_10000);
589abe3a 6905
3c9ada22 6906 bnx2x_link_int_ack(params, vars, link_10g_plus);
589abe3a 6907
8f73f0b9 6908 /* In case external phy link is up, and internal link is down
2cf7acf9
YR		 6909 * (not initialized yet probably after link initialization, it
6910 * needs to be initialized.
6911 * Note that after link down-up as result of cable plug, the xgxs
6912 * link would probably become up again without the need
6913 * initialize it
6914 */
de6eae1f
YR		 6915 if (!(SINGLE_MEDIA_DIRECT(params))) {
6916 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6917 " init_preceding = %d\n", ext_phy_link_up,
6918 vars->phy_link_up,
6919 params->phy[EXT_PHY1].flags &
6920 FLAGS_INIT_XGXS_FIRST);
6921 if (!(params->phy[EXT_PHY1].flags &
6922 FLAGS_INIT_XGXS_FIRST)
6923 && ext_phy_link_up && !vars->phy_link_up) {
6924 vars->line_speed = ext_phy_line_speed;
6925 if (vars->line_speed < SPEED_1000)
6926 vars->phy_flags |= PHY_SGMII_FLAG;
6927 else
6928 vars->phy_flags &= ~PHY_SGMII_FLAG;
ec146a6f
YR		 6929
6930 if (params->phy[INT_PHY].config_init)
6931 params->phy[INT_PHY].config_init(
6932 &params->phy[INT_PHY], params,
de6eae1f 6933 vars);
4d295db0 6934 }
589abe3a 6935 }
8f73f0b9 6936 /* Link is up only if both local phy and external phy (in case of
9045f6b4 6937 * non-direct board) are up and no fault detected on active PHY.
4d295db0 6938 */
de6eae1f
YR		 6939 vars->link_up = (vars->phy_link_up &&
6940 (ext_phy_link_up ||
c688fe2f
YR		 6941 SINGLE_MEDIA_DIRECT(params)) &&
6942 (phy_vars[active_external_phy].fault_detected == 0));
de6eae1f 6943
27d9129f
YR		 6944 /* Update the PFC configuration in case it was changed */
6945 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6946 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6947 else
6948 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6949
de6eae1f 6950 if (vars->link_up)
3c9ada22 6951 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
4d295db0 6952 else
de6eae1f 6953 rc = bnx2x_update_link_down(params, vars);
589abe3a 6954
a3348722
BW		 6955 /* Update MCP link status was changed */
6956 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6957 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6958
4d295db0 6959 return rc;
589abe3a
EG		 6960}
6961
de6eae1f
YR		 6962/*****************************************************************************/
6963/* External Phy section */
6964/*****************************************************************************/
6965void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6966{
6967 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6968 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
503976e9 6969 usleep_range(1000, 2000);
de6eae1f 6970 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6971 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
de6eae1f 6972}
589abe3a 6973
de6eae1f
YR		 6974static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6975 u32 spirom_ver, u32 ver_addr)
6976{
6977 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6978 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4d295db0 6979
de6eae1f
YR		 6980 if (ver_addr)
6981 REG_WR(bp, ver_addr, spirom_ver);
589abe3a
EG		 6982}
6983
de6eae1f
YR		 6984static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6985 struct bnx2x_phy *phy,
6986 u8 port)
6bbca910 6987{
de6eae1f
YR		 6988 u16 fw_ver1, fw_ver2;
6989
6990 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 6991 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
de6eae1f 6992 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 6993 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
de6eae1f
YR		 6994 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6995 phy->ver_addr);
ea4e040a 6996}
ab6ad5a4 6997
de6eae1f
YR		 6998static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6999 struct bnx2x_phy *phy,
7000 struct link_vars *vars)
7001{
7002 u16 val;
7003 bnx2x_cl45_read(bp, phy,
7004 MDIO_AN_DEVAD,
7005 MDIO_AN_REG_STATUS, &val);
7006 bnx2x_cl45_read(bp, phy,
7007 MDIO_AN_DEVAD,
7008 MDIO_AN_REG_STATUS, &val);
7009 if (val & (1<<5))
7010 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7011 if ((val & (1<<0)) == 0)
7012 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7013}
7014
7015/******************************************************************/
7016/* common BCM8073/BCM8727 PHY SECTION */
7017/******************************************************************/
7018static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7019 struct link_params *params,
7020 struct link_vars *vars)
7021{
7022 struct bnx2x *bp = params->bp;
7023 if (phy->req_line_speed == SPEED_10 ||
7024 phy->req_line_speed == SPEED_100) {
7025 vars->flow_ctrl = phy->req_flow_ctrl;
7026 return;
7027 }
7028
7029 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7030 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7031 u16 pause_result;
7032 u16 ld_pause; /* local */
7033 u16 lp_pause; /* link partner */
7034 bnx2x_cl45_read(bp, phy,
7035 MDIO_AN_DEVAD,
7036 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7037
7038 bnx2x_cl45_read(bp, phy,
7039 MDIO_AN_DEVAD,
7040 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7041 pause_result = (ld_pause &
7042 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7043 pause_result |= (lp_pause &
7044 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7045
7046 bnx2x_pause_resolve(vars, pause_result);
7047 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7048 pause_result);
7049 }
7050}
fcf5b650
YR		 7051static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7052 struct bnx2x_phy *phy,
7053 u8 port)
de6eae1f 7054{
5c99274b
YR		 7055 u32 count = 0;
7056 u16 fw_ver1, fw_msgout;
fcf5b650 7057 int rc = 0;
5c99274b 7058
de6eae1f
YR		 7059 /* Boot port from external ROM */
7060 /* EDC grst */
7061 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7062 MDIO_PMA_DEVAD,
7063 MDIO_PMA_REG_GEN_CTRL,
7064 0x0001);
de6eae1f 7065
d231023e 7066 /* Ucode reboot and rst */
de6eae1f 7067 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7068 MDIO_PMA_DEVAD,
7069 MDIO_PMA_REG_GEN_CTRL,
7070 0x008c);
de6eae1f
YR		 7071
7072 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7073 MDIO_PMA_DEVAD,
7074 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
de6eae1f
YR		 7075
7076 /* Reset internal microprocessor */
7077 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7078 MDIO_PMA_DEVAD,
7079 MDIO_PMA_REG_GEN_CTRL,
7080 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
de6eae1f
YR		 7081
7082 /* Release srst bit */
7083 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7084 MDIO_PMA_DEVAD,
7085 MDIO_PMA_REG_GEN_CTRL,
7086 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f 7087
5c99274b
YR		 7088 /* Delay 100ms per the PHY specifications */
7089 msleep(100);
7090
7091 /* 8073 sometimes taking longer to download */
7092 do {
7093 count++;
7094 if (count > 300) {
7095 DP(NETIF_MSG_LINK,
7096 "bnx2x_8073_8727_external_rom_boot port %x:"
7097 "Download failed. fw version = 0x%x\n",
7098 port, fw_ver1);
7099 rc = -EINVAL;
7100 break;
7101 }
7102
7103 bnx2x_cl45_read(bp, phy,
7104 MDIO_PMA_DEVAD,
7105 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7106 bnx2x_cl45_read(bp, phy,
7107 MDIO_PMA_DEVAD,
7108 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7109
503976e9 7110 usleep_range(1000, 2000);
5c99274b
YR		 7111 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7112 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7113 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
de6eae1f
YR		 7114
7115 /* Clear ser_boot_ctl bit */
7116 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7117 MDIO_PMA_DEVAD,
7118 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f 7119 bnx2x_save_bcm_spirom_ver(bp, phy, port);
5c99274b
YR		 7120
7121 DP(NETIF_MSG_LINK,
7122 "bnx2x_8073_8727_external_rom_boot port %x:"
7123 "Download complete. fw version = 0x%x\n",
7124 port, fw_ver1);
7125
7126 return rc;
de6eae1f
YR		 7127}
7128
de6eae1f
YR		 7129/******************************************************************/
7130/* BCM8073 PHY SECTION */
7131/******************************************************************/
fcf5b650 7132static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
de6eae1f
YR		 7133{
7134 /* This is only required for 8073A1, version 102 only */
7135 u16 val;
7136
7137 /* Read 8073 HW revision*/
7138 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7139 MDIO_PMA_DEVAD,
7140 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 7141
7142 if (val != 1) {
7143 /* No need to workaround in 8073 A1 */
7144 return 0;
7145 }
7146
7147 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7148 MDIO_PMA_DEVAD,
7149 MDIO_PMA_REG_ROM_VER2, &val);
de6eae1f
YR		 7150
7151 /* SNR should be applied only for version 0x102 */
7152 if (val != 0x102)
7153 return 0;
7154
7155 return 1;
7156}
7157
fcf5b650 7158static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
de6eae1f
YR		 7159{
7160 u16 val, cnt, cnt1 ;
7161
7162 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7163 MDIO_PMA_DEVAD,
7164 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 7165
7166 if (val > 0) {
7167 /* No need to workaround in 8073 A1 */
7168 return 0;
7169 }
7170 /* XAUI workaround in 8073 A0: */
7171
8f73f0b9 7172 /* After loading the boot ROM and restarting Autoneg, poll
2cf7acf9
YR		 7173 * Dev1, Reg $C820:
7174 */
de6eae1f
YR		 7175
7176 for (cnt = 0; cnt < 1000; cnt++) {
7177 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7178 MDIO_PMA_DEVAD,
7179 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7180 &val);
8f73f0b9 7181 /* If bit [14] = 0 or bit [13] = 0, continue on with
2cf7acf9
YR		 7182 * system initialization (XAUI work-around not required, as
7183 * these bits indicate 2.5G or 1G link up).
7184 */
de6eae1f
YR		 7185 if (!(val & (1<<14)) || !(val & (1<<13))) {
7186 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7187 return 0;
7188 } else if (!(val & (1<<15))) {
2cf7acf9 7189 DP(NETIF_MSG_LINK, "bit 15 went off\n");
8f73f0b9 7190 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
2cf7acf9
YR		 7191 * MSB (bit15) goes to 1 (indicating that the XAUI
7192 * workaround has completed), then continue on with
7193 * system initialization.
7194 */
de6eae1f
YR		 7195 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7196 bnx2x_cl45_read(bp, phy,
7197 MDIO_PMA_DEVAD,
7198 MDIO_PMA_REG_8073_XAUI_WA, &val);
7199 if (val & (1<<15)) {
7200 DP(NETIF_MSG_LINK,
7201 "XAUI workaround has completed\n");
7202 return 0;
7203 }
d231023e 7204 usleep_range(3000, 6000);
de6eae1f
YR		 7205 }
7206 break;
7207 }
d231023e 7208 usleep_range(3000, 6000);
de6eae1f
YR		 7209 }
7210 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7211 return -EINVAL;
7212}
7213
7214static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7215{
7216 /* Force KR or KX */
7217 bnx2x_cl45_write(bp, phy,
7218 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7219 bnx2x_cl45_write(bp, phy,
7220 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7221 bnx2x_cl45_write(bp, phy,
7222 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7223 bnx2x_cl45_write(bp, phy,
7224 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7225}
7226
6bbca910 7227static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 7228 struct bnx2x_phy *phy,
7229 struct link_vars *vars)
ea4e040a 7230{
6bbca910 7231 u16 cl37_val;
e10bc84d
YR		 7232 struct bnx2x *bp = params->bp;
7233 bnx2x_cl45_read(bp, phy,
62b29a5d 7234 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 7235
7236 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7237 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 7238 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 7239 if ((vars->ieee_fc &
7240 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7241 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7242 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7243 }
7244 if ((vars->ieee_fc &
7245 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7246 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7247 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7248 }
7249 if ((vars->ieee_fc &
7250 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7251 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7252 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7253 }
7254 DP(NETIF_MSG_LINK,
7255 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7256
e10bc84d 7257 bnx2x_cl45_write(bp, phy,
62b29a5d 7258 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 7259 msleep(500);
ea4e040a
YR		 7260}
7261
5c107fda
YR		 7262static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7263 struct link_params *params,
7264 u32 action)
7265{
7266 struct bnx2x *bp = params->bp;
7267 switch (action) {
7268 case PHY_INIT:
7269 /* Enable LASI */
7270 bnx2x_cl45_write(bp, phy,
7271 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7272 bnx2x_cl45_write(bp, phy,
7273 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7274 break;
7275 }
7276}
7277
fcf5b650
YR		 7278static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7279 struct link_params *params,
7280 struct link_vars *vars)
ea4e040a 7281{
e10bc84d 7282 struct bnx2x *bp = params->bp;
de6eae1f
YR		 7283 u16 val = 0, tmp1;
7284 u8 gpio_port;
7285 DP(NETIF_MSG_LINK, "Init 8073\n");
e10bc84d 7286
f2e0899f
DK		 7287 if (CHIP_IS_E2(bp))
7288 gpio_port = BP_PATH(bp);
7289 else
7290 gpio_port = params->port;
de6eae1f
YR		 7291 /* Restore normal power mode*/
7292 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 7293 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
e10bc84d 7294
de6eae1f 7295 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 7296 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
ea4e040a 7297
5c107fda 7298 bnx2x_8073_specific_func(phy, params, PHY_INIT);
de6eae1f 7299 bnx2x_8073_set_pause_cl37(params, phy, vars);
57963ed9 7300
e10bc84d 7301 bnx2x_cl45_read(bp, phy,
de6eae1f 7302 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
2f904460 7303
de6eae1f 7304 bnx2x_cl45_read(bp, phy,
60d2fe03 7305 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
2f904460 7306
de6eae1f 7307 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
a1e4be39 7308
74d7a119
YR		 7309 /* Swap polarity if required - Must be done only in non-1G mode */
7310 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7311 /* Configure the 8073 to swap _P and _N of the KR lines */
7312 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7313 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7314 bnx2x_cl45_read(bp, phy,
7315 MDIO_PMA_DEVAD,
7316 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7317 bnx2x_cl45_write(bp, phy,
7318 MDIO_PMA_DEVAD,
7319 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7320 (val | (3<<9)));
7321 }
7322
7323
de6eae1f 7324 /* Enable CL37 BAM */
121839be
YR		 7325 if (REG_RD(bp, params->shmem_base +
7326 offsetof(struct shmem_region, dev_info.
7327 port_hw_config[params->port].default_cfg)) &
7328 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
57963ed9 7329
121839be
YR		 7330 bnx2x_cl45_read(bp, phy,
7331 MDIO_AN_DEVAD,
7332 MDIO_AN_REG_8073_BAM, &val);
7333 bnx2x_cl45_write(bp, phy,
7334 MDIO_AN_DEVAD,
7335 MDIO_AN_REG_8073_BAM, val | 1);
7336 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7337 }
de6eae1f
YR		 7338 if (params->loopback_mode == LOOPBACK_EXT) {
7339 bnx2x_807x_force_10G(bp, phy);
7340 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7341 return 0;
7342 } else {
7343 bnx2x_cl45_write(bp, phy,
7344 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7345 }
7346 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7347 if (phy->req_line_speed == SPEED_10000) {
7348 val = (1<<7);
7349 } else if (phy->req_line_speed == SPEED_2500) {
7350 val = (1<<5);
8f73f0b9 7351 /* Note that 2.5G works only when used with 1G
25985edc 7352 * advertisement
2cf7acf9 7353 */
de6eae1f
YR		 7354 } else
7355 val = (1<<5);
7356 } else {
7357 val = 0;
7358 if (phy->speed_cap_mask &
7359 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7360 val |= (1<<7);
57963ed9 7361
25985edc 7362 /* Note that 2.5G works only when used with 1G advertisement */
de6eae1f
YR		 7363 if (phy->speed_cap_mask &
7364 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7365 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7366 val |= (1<<5);
7367 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7368 }
57963ed9 7369
de6eae1f
YR		 7370 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7371 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
57963ed9 7372
de6eae1f
YR		 7373 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7374 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7375 (phy->req_line_speed == SPEED_2500)) {
7376 u16 phy_ver;
7377 /* Allow 2.5G for A1 and above */
7378 bnx2x_cl45_read(bp, phy,
7379 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7380 &phy_ver);
7381 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7382 if (phy_ver > 0)
7383 tmp1 |= 1;
7384 else
7385 tmp1 &= 0xfffe;
7386 } else {
7387 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7388 tmp1 &= 0xfffe;
7389 }
57963ed9 7390
de6eae1f
YR		 7391 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7392 /* Add support for CL37 (passive mode) II */
57963ed9 7393
de6eae1f
YR		 7394 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7395 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7396 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7397 0x20 : 0x40)));
57963ed9 7398
de6eae1f
YR		 7399 /* Add support for CL37 (passive mode) III */
7400 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
57963ed9 7401
8f73f0b9 7402 /* The SNR will improve about 2db by changing BW and FEE main
2cf7acf9
YR		 7403 * tap. Rest commands are executed after link is up
7404 * Change FFE main cursor to 5 in EDC register
7405 */
de6eae1f
YR		 7406 if (bnx2x_8073_is_snr_needed(bp, phy))
7407 bnx2x_cl45_write(bp, phy,
7408 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7409 0xFB0C);
57963ed9 7410
de6eae1f
YR		 7411 /* Enable FEC (Forware Error Correction) Request in the AN */
7412 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7413 tmp1 |= (1<<15);
7414 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
57963ed9 7415
de6eae1f 7416 bnx2x_ext_phy_set_pause(params, phy, vars);
57963ed9 7417
de6eae1f
YR		 7418 /* Restart autoneg */
7419 msleep(500);
7420 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7421 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7422 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7423 return 0;
b7737c9b 7424}
ea4e040a 7425
de6eae1f 7426static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 7427 struct link_params *params,
7428 struct link_vars *vars)
7429{
7430 struct bnx2x *bp = params->bp;
de6eae1f
YR		 7431 u8 link_up = 0;
7432 u16 val1, val2;
7433 u16 link_status = 0;
7434 u16 an1000_status = 0;
a35da8db 7435
de6eae1f 7436 bnx2x_cl45_read(bp, phy,
60d2fe03 7437 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
b7737c9b 7438
de6eae1f 7439 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 7440
d231023e 7441 /* Clear the interrupt LASI status register */
de6eae1f
YR		 7442 bnx2x_cl45_read(bp, phy,
7443 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7444 bnx2x_cl45_read(bp, phy,
7445 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7446 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7447 /* Clear MSG-OUT */
7448 bnx2x_cl45_read(bp, phy,
7449 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7450
7451 /* Check the LASI */
7452 bnx2x_cl45_read(bp, phy,
60d2fe03 7453 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
de6eae1f
YR		 7454
7455 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7456
7457 /* Check the link status */
7458 bnx2x_cl45_read(bp, phy,
7459 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7460 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7461
7462 bnx2x_cl45_read(bp, phy,
7463 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7464 bnx2x_cl45_read(bp, phy,
7465 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7466 link_up = ((val1 & 4) == 4);
7467 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7468
7469 if (link_up &&
7470 ((phy->req_line_speed != SPEED_10000))) {
7471 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7472 return 0;
62b29a5d 7473 }
de6eae1f
YR		 7474 bnx2x_cl45_read(bp, phy,
7475 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7476 bnx2x_cl45_read(bp, phy,
7477 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
62b29a5d 7478
de6eae1f
YR		 7479 /* Check the link status on 1.1.2 */
7480 bnx2x_cl45_read(bp, phy,
7481 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7482 bnx2x_cl45_read(bp, phy,
7483 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7484 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7485 "an_link_status=0x%x\n", val2, val1, an1000_status);
62b29a5d 7486
de6eae1f
YR		 7487 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7488 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
8f73f0b9 7489 /* The SNR will improve about 2dbby changing the BW and FEE main
2cf7acf9
YR		 7490 * tap. The 1st write to change FFE main tap is set before
7491 * restart AN. Change PLL Bandwidth in EDC register
7492 */
62b29a5d 7493 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 7494 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7495 0x26BC);
62b29a5d 7496
de6eae1f 7497 /* Change CDR Bandwidth in EDC register */
62b29a5d 7498 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 7499 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7500 0x0333);
7501 }
7502 bnx2x_cl45_read(bp, phy,
7503 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7504 &link_status);
62b29a5d 7505
de6eae1f
YR		 7506 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7507 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7508 link_up = 1;
7509 vars->line_speed = SPEED_10000;
7510 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7511 params->port);
7512 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7513 link_up = 1;
7514 vars->line_speed = SPEED_2500;
7515 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7516 params->port);
7517 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7518 link_up = 1;
7519 vars->line_speed = SPEED_1000;
7520 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7521 params->port);
7522 } else {
7523 link_up = 0;
7524 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7525 params->port);
62b29a5d 7526 }
de6eae1f
YR		 7527
7528 if (link_up) {
74d7a119
YR		 7529 /* Swap polarity if required */
7530 if (params->lane_config &
7531 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7532 /* Configure the 8073 to swap P and N of the KR lines */
7533 bnx2x_cl45_read(bp, phy,
7534 MDIO_XS_DEVAD,
7535 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8f73f0b9 7536 /* Set bit 3 to invert Rx in 1G mode and clear this bit
2cf7acf9
YR		 7537 * when it`s in 10G mode.
7538 */
74d7a119
YR		 7539 if (vars->line_speed == SPEED_1000) {
7540 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7541 "the 8073\n");
7542 val1 |= (1<<3);
7543 } else
7544 val1 &= ~(1<<3);
7545
7546 bnx2x_cl45_write(bp, phy,
7547 MDIO_XS_DEVAD,
7548 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7549 val1);
7550 }
de6eae1f
YR		 7551 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7552 bnx2x_8073_resolve_fc(phy, params, vars);
791f18c0 7553 vars->duplex = DUPLEX_FULL;
de6eae1f 7554 }
9e7e8399
MY		 7555
7556 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7557 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7558 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7559
7560 if (val1 & (1<<5))
7561 vars->link_status |=
7562 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7563 if (val1 & (1<<7))
7564 vars->link_status |=
7565 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7566 }
7567
de6eae1f 7568 return link_up;
b7737c9b
YR		 7569}
7570
de6eae1f
YR		 7571static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7572 struct link_params *params)
7573{
7574 struct bnx2x *bp = params->bp;
7575 u8 gpio_port;
f2e0899f
DK		 7576 if (CHIP_IS_E2(bp))
7577 gpio_port = BP_PATH(bp);
7578 else
7579 gpio_port = params->port;
de6eae1f
YR		 7580 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7581 gpio_port);
7582 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 7583 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7584 gpio_port);
de6eae1f
YR		 7585}
7586
7587/******************************************************************/
7588/* BCM8705 PHY SECTION */
7589/******************************************************************/
fcf5b650
YR		 7590static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7591 struct link_params *params,
7592 struct link_vars *vars)
b7737c9b
YR		 7593{
7594 struct bnx2x *bp = params->bp;
de6eae1f 7595 DP(NETIF_MSG_LINK, "init 8705\n");
b7737c9b
YR		 7596 /* Restore normal power mode*/
7597 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 7598 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 7599 /* HW reset */
7600 bnx2x_ext_phy_hw_reset(bp, params->port);
7601 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 7602 bnx2x_wait_reset_complete(bp, phy, params);
b7737c9b 7603
de6eae1f
YR		 7604 bnx2x_cl45_write(bp, phy,
7605 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7606 bnx2x_cl45_write(bp, phy,
7607 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7608 bnx2x_cl45_write(bp, phy,
7609 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7610 bnx2x_cl45_write(bp, phy,
7611 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7612 /* BCM8705 doesn't have microcode, hence the 0 */
7613 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7614 return 0;
7615}
4d295db0 7616
de6eae1f
YR		 7617static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7618 struct link_params *params,
7619 struct link_vars *vars)
7620{
7621 u8 link_up = 0;
7622 u16 val1, rx_sd;
7623 struct bnx2x *bp = params->bp;
7624 DP(NETIF_MSG_LINK, "read status 8705\n");
7625 bnx2x_cl45_read(bp, phy,
7626 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7627 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 7628
de6eae1f
YR		 7629 bnx2x_cl45_read(bp, phy,
7630 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7631 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 7632
de6eae1f
YR		 7633 bnx2x_cl45_read(bp, phy,
7634 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
c2c8b03e 7635
de6eae1f
YR		 7636 bnx2x_cl45_read(bp, phy,
7637 MDIO_PMA_DEVAD, 0xc809, &val1);
7638 bnx2x_cl45_read(bp, phy,
7639 MDIO_PMA_DEVAD, 0xc809, &val1);
c2c8b03e 7640
de6eae1f
YR		 7641 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7642 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7643 if (link_up) {
7644 vars->line_speed = SPEED_10000;
7645 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d 7646 }
de6eae1f
YR		 7647 return link_up;
7648}
d90d96ba 7649
de6eae1f
YR		 7650/******************************************************************/
7651/* SFP+ module Section */
7652/******************************************************************/
85242eea
YR		 7653static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7654 struct bnx2x_phy *phy,
7655 u8 pmd_dis)
7656{
7657 struct bnx2x *bp = params->bp;
8f73f0b9 7658 /* Disable transmitter only for bootcodes which can enable it afterwards
85242eea
YR		 7659 * (for D3 link)
7660 */
7661 if (pmd_dis) {
7662 if (params->feature_config_flags &
7663 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7664 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7665 else {
7666 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7667 return;
7668 }
7669 } else
7670 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7671 bnx2x_cl45_write(bp, phy,
7672 MDIO_PMA_DEVAD,
7673 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7674}
7675
a8db5b4c
YR		 7676static u8 bnx2x_get_gpio_port(struct link_params *params)
7677{
7678 u8 gpio_port;
7679 u32 swap_val, swap_override;
7680 struct bnx2x *bp = params->bp;
7681 if (CHIP_IS_E2(bp))
7682 gpio_port = BP_PATH(bp);
7683 else
7684 gpio_port = params->port;
7685 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7686 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7687 return gpio_port ^ (swap_val && swap_override);
7688}
3c9ada22
YR		 7689
7690static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7691 struct bnx2x_phy *phy,
7692 u8 tx_en)
de6eae1f
YR		 7693{
7694 u16 val;
a8db5b4c
YR		 7695 u8 port = params->port;
7696 struct bnx2x *bp = params->bp;
7697 u32 tx_en_mode;
d90d96ba 7698
de6eae1f 7699 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
a8db5b4c
YR		 7700 tx_en_mode = REG_RD(bp, params->shmem_base +
7701 offsetof(struct shmem_region,
7702 dev_info.port_hw_config[port].sfp_ctrl)) &
7703 PORT_HW_CFG_TX_LASER_MASK;
7704 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7705 "mode = %x\n", tx_en, port, tx_en_mode);
7706 switch (tx_en_mode) {
7707 case PORT_HW_CFG_TX_LASER_MDIO:
d90d96ba 7708
a8db5b4c
YR		 7709 bnx2x_cl45_read(bp, phy,
7710 MDIO_PMA_DEVAD,
7711 MDIO_PMA_REG_PHY_IDENTIFIER,
7712 &val);
b7737c9b 7713
a8db5b4c
YR		 7714 if (tx_en)
7715 val &= ~(1<<15);
7716 else
7717 val |= (1<<15);
7718
7719 bnx2x_cl45_write(bp, phy,
7720 MDIO_PMA_DEVAD,
7721 MDIO_PMA_REG_PHY_IDENTIFIER,
7722 val);
7723 break;
7724 case PORT_HW_CFG_TX_LASER_GPIO0:
7725 case PORT_HW_CFG_TX_LASER_GPIO1:
7726 case PORT_HW_CFG_TX_LASER_GPIO2:
7727 case PORT_HW_CFG_TX_LASER_GPIO3:
7728 {
7729 u16 gpio_pin;
7730 u8 gpio_port, gpio_mode;
7731 if (tx_en)
7732 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7733 else
7734 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7735
7736 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7737 gpio_port = bnx2x_get_gpio_port(params);
7738 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7739 break;
7740 }
7741 default:
7742 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7743 break;
7744 }
b7737c9b
YR		 7745}
7746
3c9ada22
YR		 7747static void bnx2x_sfp_set_transmitter(struct link_params *params,
7748 struct bnx2x_phy *phy,
7749 u8 tx_en)
7750{
7751 struct bnx2x *bp = params->bp;
7752 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7753 if (CHIP_IS_E3(bp))
7754 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7755 else
7756 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7757}
7758
fcf5b650
YR		 7759static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7760 struct link_params *params,
7761 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b
YR		 7762{
7763 struct bnx2x *bp = params->bp;
de6eae1f
YR		 7764 u16 val = 0;
7765 u16 i;
24ea818e 7766 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
94f05b0f
JP		 7767 DP(NETIF_MSG_LINK,
7768 "Reading from eeprom is limited to 0xf\n");
de6eae1f
YR		 7769 return -EINVAL;
7770 }
7771 /* Set the read command byte count */
62b29a5d 7772 bnx2x_cl45_write(bp, phy,
de6eae1f 7773 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
cd88ccee 7774 (byte_cnt | 0xa000));
ea4e040a 7775
de6eae1f
YR		 7776 /* Set the read command address */
7777 bnx2x_cl45_write(bp, phy,
7778 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
cd88ccee 7779 addr);
ea4e040a 7780
de6eae1f 7781 /* Activate read command */
62b29a5d 7782 bnx2x_cl45_write(bp, phy,
de6eae1f 7783 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
cd88ccee 7784 0x2c0f);
ea4e040a 7785
de6eae1f
YR		 7786 /* Wait up to 500us for command complete status */
7787 for (i = 0; i < 100; i++) {
7788 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7789 MDIO_PMA_DEVAD,
7790 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7791 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7792 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7793 break;
7794 udelay(5);
62b29a5d 7795 }
62b29a5d 7796
de6eae1f
YR		 7797 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7798 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7799 DP(NETIF_MSG_LINK,
7800 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7801 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7802 return -EINVAL;
62b29a5d 7803 }
e10bc84d 7804
de6eae1f
YR		 7805 /* Read the buffer */
7806 for (i = 0; i < byte_cnt; i++) {
62b29a5d 7807 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7808 MDIO_PMA_DEVAD,
7809 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f 7810 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
62b29a5d 7811 }
6bbca910 7812
de6eae1f
YR		 7813 for (i = 0; i < 100; i++) {
7814 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7815 MDIO_PMA_DEVAD,
7816 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7817 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7818 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 7819 return 0;
503976e9 7820 usleep_range(1000, 2000);
de6eae1f
YR		 7821 }
7822 return -EINVAL;
b7737c9b 7823}
4d295db0 7824
50a29845 7825static void bnx2x_warpcore_power_module(struct link_params *params,
50a29845
YM		 7826 u8 power)
7827{
7828 u32 pin_cfg;
7829 struct bnx2x *bp = params->bp;
7830
7831 pin_cfg = (REG_RD(bp, params->shmem_base +
7832 offsetof(struct shmem_region,
7833 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7834 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7835 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7836
7837 if (pin_cfg == PIN_CFG_NA)
7838 return;
7839 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7840 power, pin_cfg);
7841 /* Low ==> corresponding SFP+ module is powered
7842 * high ==> the SFP+ module is powered down
7843 */
7844 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7845}
3c9ada22
YR		 7846static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7847 struct link_params *params,
7848 u16 addr, u8 byte_cnt,
e82041df 7849 u8 *o_buf, u8 is_init)
3c9ada22
YR		 7850{
7851 int rc = 0;
7852 u8 i, j = 0, cnt = 0;
7853 u32 data_array[4];
7854 u16 addr32;
7855 struct bnx2x *bp = params->bp;
24ea818e
YM		 7856
7857 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
94f05b0f
JP		 7858 DP(NETIF_MSG_LINK,
7859 "Reading from eeprom is limited to 16 bytes\n");
3c9ada22
YR		 7860 return -EINVAL;
7861 }
7862
7863 /* 4 byte aligned address */
7864 addr32 = addr & (~0x3);
7865 do {
e82041df 7866 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
5a1fbf40 7867 bnx2x_warpcore_power_module(params, 0);
50a29845 7868 /* Note that 100us are not enough here */
e82041df 7869 usleep_range(1000, 2000);
5a1fbf40 7870 bnx2x_warpcore_power_module(params, 1);
50a29845 7871 }
3c9ada22
YR		 7872 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7873 data_array);
7874 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7875
7876 if (rc == 0) {
7877 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7878 o_buf[j] = *((u8 *)data_array + i);
7879 j++;
7880 }
7881 }
7882
7883 return rc;
7884}
7885
fcf5b650
YR		 7886static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7887 struct link_params *params,
7888 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b 7889{
b7737c9b 7890 struct bnx2x *bp = params->bp;
de6eae1f 7891 u16 val, i;
ea4e040a 7892
24ea818e 7893 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
94f05b0f
JP		 7894 DP(NETIF_MSG_LINK,
7895 "Reading from eeprom is limited to 0xf\n");
de6eae1f
YR		 7896 return -EINVAL;
7897 }
4d295db0 7898
de6eae1f
YR		 7899 /* Need to read from 1.8000 to clear it */
7900 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7901 MDIO_PMA_DEVAD,
7902 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7903 &val);
4d295db0 7904
de6eae1f 7905 /* Set the read command byte count */
62b29a5d 7906 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7907 MDIO_PMA_DEVAD,
7908 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7909 ((byte_cnt < 2) ? 2 : byte_cnt));
ea4e040a 7910
de6eae1f 7911 /* Set the read command address */
62b29a5d 7912 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7913 MDIO_PMA_DEVAD,
7914 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7915 addr);
de6eae1f 7916 /* Set the destination address */
62b29a5d 7917 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7918 MDIO_PMA_DEVAD,
7919 0x8004,
7920 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
62b29a5d 7921
de6eae1f 7922 /* Activate read command */
62b29a5d 7923 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 7924 MDIO_PMA_DEVAD,
7925 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7926 0x8002);
8f73f0b9 7927 /* Wait appropriate time for two-wire command to finish before
2cf7acf9
YR		 7928 * polling the status register
7929 */
503976e9 7930 usleep_range(1000, 2000);
4d295db0 7931
de6eae1f
YR		 7932 /* Wait up to 500us for command complete status */
7933 for (i = 0; i < 100; i++) {
62b29a5d 7934 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7935 MDIO_PMA_DEVAD,
7936 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7937 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7938 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7939 break;
7940 udelay(5);
62b29a5d 7941 }
4d295db0 7942
de6eae1f
YR		 7943 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7944 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7945 DP(NETIF_MSG_LINK,
7946 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7947 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
65a001ba 7948 return -EFAULT;
de6eae1f 7949 }
62b29a5d 7950
de6eae1f
YR		 7951 /* Read the buffer */
7952 for (i = 0; i < byte_cnt; i++) {
7953 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7954 MDIO_PMA_DEVAD,
7955 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f
YR		 7956 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7957 }
4d295db0 7958
de6eae1f
YR		 7959 for (i = 0; i < 100; i++) {
7960 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 7961 MDIO_PMA_DEVAD,
7962 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 7963 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7964 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 7965 return 0;
503976e9 7966 usleep_range(1000, 2000);
62b29a5d
YR		 7967 }
7968
de6eae1f 7969 return -EINVAL;
b7737c9b
YR		 7970}
7971
fcf5b650
YR		 7972int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7973 struct link_params *params, u16 addr,
7974 u8 byte_cnt, u8 *o_buf)
b7737c9b 7975{
24ea818e 7976 int rc = -EOPNOTSUPP;
e4d78f12
YR		 7977 switch (phy->type) {
7978 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7979 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7980 byte_cnt, o_buf);
7981 break;
7982 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7983 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7984 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7985 byte_cnt, o_buf);
7986 break;
3c9ada22
YR		 7987 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7988 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
e82041df 7989 byte_cnt, o_buf, 0);
3c9ada22 7990 break;
e4d78f12
YR		 7991 }
7992 return rc;
b7737c9b
YR		 7993}
7994
fcf5b650
YR		 7995static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7996 struct link_params *params,
7997 u16 *edc_mode)
b7737c9b
YR		 7998{
7999 struct bnx2x *bp = params->bp;
1ac9e428 8000 u32 sync_offset = 0, phy_idx, media_types;
52160da7 8001 u8 gport, val[2], check_limiting_mode = 0;
de6eae1f 8002 *edc_mode = EDC_MODE_LIMITING;
1ac9e428 8003 phy->media_type = ETH_PHY_UNSPECIFIED;
de6eae1f
YR		 8004 /* First check for copper cable */
8005 if (bnx2x_read_sfp_module_eeprom(phy,
8006 params,
8007 SFP_EEPROM_CON_TYPE_ADDR,
dbef807e
YM		 8008 2,
8009 (u8 *)val) != 0) {
de6eae1f
YR		 8010 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8011 return -EINVAL;
8012 }
a1e4be39 8013
dbef807e 8014 switch (val[0]) {
de6eae1f
YR		 8015 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8016 {
8017 u8 copper_module_type;
1ac9e428 8018 phy->media_type = ETH_PHY_DA_TWINAX;
8f73f0b9 8019 /* Check if its active cable (includes SFP+ module)
2cf7acf9
YR		 8020 * of passive cable
8021 */
de6eae1f
YR		 8022 if (bnx2x_read_sfp_module_eeprom(phy,
8023 params,
8024 SFP_EEPROM_FC_TX_TECH_ADDR,
8025 1,
9045f6b4 8026 &copper_module_type) != 0) {
de6eae1f
YR		 8027 DP(NETIF_MSG_LINK,
8028 "Failed to read copper-cable-type"
8029 " from SFP+ EEPROM\n");
8030 return -EINVAL;
8031 }
4f60dab1 8032
de6eae1f
YR		 8033 if (copper_module_type &
8034 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8035 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8036 check_limiting_mode = 1;
8037 } else if (copper_module_type &
8038 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
94f05b0f
JP		 8039 DP(NETIF_MSG_LINK,
8040 "Passive Copper cable detected\n");
de6eae1f
YR		 8041 *edc_mode =
8042 EDC_MODE_PASSIVE_DAC;
8043 } else {
94f05b0f
JP		 8044 DP(NETIF_MSG_LINK,
8045 "Unknown copper-cable-type 0x%x !!!\n",
8046 copper_module_type);
de6eae1f
YR		 8047 return -EINVAL;
8048 }
8049 break;
62b29a5d 8050 }
de6eae1f 8051 case SFP_EEPROM_CON_TYPE_VAL_LC:
de6eae1f 8052 check_limiting_mode = 1;
dbef807e
YM		 8053 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8054 SFP_EEPROM_COMP_CODE_LR_MASK |
8055 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8056 DP(NETIF_MSG_LINK, "1G Optic module detected\n");
52160da7 8057 gport = params->port;
dbef807e
YM		 8058 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8059 phy->req_line_speed = SPEED_1000;
52160da7
YR		 8060 if (!CHIP_IS_E1x(bp))
8061 gport = BP_PATH(bp) + (params->port << 1);
8062 netdev_err(bp->dev, "Warning: Link speed was forced to 1000Mbps."
8063 " Current SFP module in port %d is not"
8064 " compliant with 10G Ethernet\n",
8065 gport);
dbef807e
YM		 8066 } else {
8067 int idx, cfg_idx = 0;
8068 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8069 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8070 if (params->phy[idx].type == phy->type) {
8071 cfg_idx = LINK_CONFIG_IDX(idx);
8072 break;
8073 }
8074 }
8075 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8076 phy->req_line_speed = params->req_line_speed[cfg_idx];
8077 }
de6eae1f
YR		 8078 break;
8079 default:
8080 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
dbef807e 8081 val[0]);
de6eae1f 8082 return -EINVAL;
62b29a5d 8083 }
1ac9e428
YR		 8084 sync_offset = params->shmem_base +
8085 offsetof(struct shmem_region,
8086 dev_info.port_hw_config[params->port].media_type);
8087 media_types = REG_RD(bp, sync_offset);
8088 /* Update media type for non-PMF sync */
8089 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8090 if (&(params->phy[phy_idx]) == phy) {
8091 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8092 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8093 media_types |= ((phy->media_type &
8094 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8095 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8096 break;
8097 }
8098 }
8099 REG_WR(bp, sync_offset, media_types);
de6eae1f
YR		 8100 if (check_limiting_mode) {
8101 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8102 if (bnx2x_read_sfp_module_eeprom(phy,
8103 params,
8104 SFP_EEPROM_OPTIONS_ADDR,
8105 SFP_EEPROM_OPTIONS_SIZE,
8106 options) != 0) {
94f05b0f
JP		 8107 DP(NETIF_MSG_LINK,
8108 "Failed to read Option field from module EEPROM\n");
de6eae1f
YR		 8109 return -EINVAL;
8110 }
8111 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8112 *edc_mode = EDC_MODE_LINEAR;
8113 else
8114 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 8115 }
de6eae1f 8116 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
62b29a5d 8117 return 0;
b7737c9b 8118}
8f73f0b9 8119/* This function read the relevant field from the module (SFP+), and verify it
2cf7acf9
YR		 8120 * is compliant with this board
8121 */
fcf5b650
YR		 8122static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8123 struct link_params *params)
b7737c9b
YR		 8124{
8125 struct bnx2x *bp = params->bp;
a22f0788
YR		 8126 u32 val, cmd;
8127 u32 fw_resp, fw_cmd_param;
de6eae1f
YR		 8128 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8129 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
a22f0788 8130 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
de6eae1f
YR		 8131 val = REG_RD(bp, params->shmem_base +
8132 offsetof(struct shmem_region, dev_info.
8133 port_feature_config[params->port].config));
8134 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8135 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8136 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8137 return 0;
8138 }
ea4e040a 8139
a22f0788
YR		 8140 if (params->feature_config_flags &
8141 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8142 /* Use specific phy request */
8143 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8144 } else if (params->feature_config_flags &
8145 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8146 /* Use first phy request only in case of non-dual media*/
8147 if (DUAL_MEDIA(params)) {
94f05b0f
JP		 8148 DP(NETIF_MSG_LINK,
8149 "FW does not support OPT MDL verification\n");
a22f0788
YR		 8150 return -EINVAL;
8151 }
8152 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8153 } else {
8154 /* No support in OPT MDL detection */
94f05b0f
JP		 8155 DP(NETIF_MSG_LINK,
8156 "FW does not support OPT MDL verification\n");
de6eae1f
YR		 8157 return -EINVAL;
8158 }
523224a3 8159
a22f0788
YR		 8160 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8161 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
de6eae1f
YR		 8162 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8163 DP(NETIF_MSG_LINK, "Approved module\n");
8164 return 0;
8165 }
b7737c9b 8166
d231023e 8167 /* Format the warning message */
de6eae1f
YR		 8168 if (bnx2x_read_sfp_module_eeprom(phy,
8169 params,
cd88ccee
YR		 8170 SFP_EEPROM_VENDOR_NAME_ADDR,
8171 SFP_EEPROM_VENDOR_NAME_SIZE,
8172 (u8 *)vendor_name))
de6eae1f
YR		 8173 vendor_name[0] = '\0';
8174 else
8175 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8176 if (bnx2x_read_sfp_module_eeprom(phy,
8177 params,
cd88ccee
YR		 8178 SFP_EEPROM_PART_NO_ADDR,
8179 SFP_EEPROM_PART_NO_SIZE,
8180 (u8 *)vendor_pn))
de6eae1f
YR		 8181 vendor_pn[0] = '\0';
8182 else
8183 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8184
6d870c39
YR		 8185 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8186 " Port %d from %s part number %s\n",
8187 params->port, vendor_name, vendor_pn);
59a2e53b
YR		 8188 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8189 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8190 phy->flags |= FLAGS_SFP_NOT_APPROVED;
de6eae1f 8191 return -EINVAL;
b7737c9b 8192}
7aa0711f 8193
fcf5b650
YR		 8194static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8195 struct link_params *params)
7aa0711f 8196
4d295db0 8197{
de6eae1f 8198 u8 val;
e82041df 8199 int rc;
4d295db0 8200 struct bnx2x *bp = params->bp;
de6eae1f 8201 u16 timeout;
8f73f0b9 8202 /* Initialization time after hot-plug may take up to 300ms for
2cf7acf9
YR		 8203 * some phys type ( e.g. JDSU )
8204 */
8205
de6eae1f 8206 for (timeout = 0; timeout < 60; timeout++) {
e82041df
YR		 8207 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8208 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy,
8209 params, 1,
8210 1, &val, 1);
8211 else
8212 rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1,
8213 &val);
8214 if (rc == 0) {
94f05b0f
JP		 8215 DP(NETIF_MSG_LINK,
8216 "SFP+ module initialization took %d ms\n",
8217 timeout * 5);
de6eae1f
YR		 8218 return 0;
8219 }
d231023e 8220 usleep_range(5000, 10000);
de6eae1f 8221 }
e82041df
YR		 8222 rc = bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val);
8223 return rc;
de6eae1f 8224}
4d295db0 8225
de6eae1f
YR		 8226static void bnx2x_8727_power_module(struct bnx2x *bp,
8227 struct bnx2x_phy *phy,
8228 u8 is_power_up) {
8229 /* Make sure GPIOs are not using for LED mode */
8230 u16 val;
8f73f0b9 8231 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
de6eae1f
YR		 8232 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8233 * output
3c9ada22
YR		 8234 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8235 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
de6eae1f
YR		 8236 * where the 1st bit is the over-current(only input), and 2nd bit is
8237 * for power( only output )
2cf7acf9 8238 *
de6eae1f
YR		 8239 * In case of NOC feature is disabled and power is up, set GPIO control
8240 * as input to enable listening of over-current indication
8241 */
8242 if (phy->flags & FLAGS_NOC)
8243 return;
27d02432 8244 if (is_power_up)
de6eae1f
YR		 8245 val = (1<<4);
8246 else
8f73f0b9 8247 /* Set GPIO control to OUTPUT, and set the power bit
de6eae1f
YR		 8248 * to according to the is_power_up
8249 */
27d02432 8250 val = (1<<1);
4d295db0 8251
de6eae1f
YR		 8252 bnx2x_cl45_write(bp, phy,
8253 MDIO_PMA_DEVAD,
8254 MDIO_PMA_REG_8727_GPIO_CTRL,
8255 val);
8256}
4d295db0 8257
fcf5b650
YR		 8258static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8259 struct bnx2x_phy *phy,
8260 u16 edc_mode)
de6eae1f
YR		 8261{
8262 u16 cur_limiting_mode;
4d295db0 8263
de6eae1f 8264 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 8265 MDIO_PMA_DEVAD,
8266 MDIO_PMA_REG_ROM_VER2,
8267 &cur_limiting_mode);
de6eae1f
YR		 8268 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8269 cur_limiting_mode);
8270
8271 if (edc_mode == EDC_MODE_LIMITING) {
cd88ccee 8272 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
e10bc84d 8273 bnx2x_cl45_write(bp, phy,
62b29a5d 8274 MDIO_PMA_DEVAD,
de6eae1f
YR		 8275 MDIO_PMA_REG_ROM_VER2,
8276 EDC_MODE_LIMITING);
8277 } else { /* LRM mode ( default )*/
4d295db0 8278
de6eae1f 8279 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4d295db0 8280
8f73f0b9 8281 /* Changing to LRM mode takes quite few seconds. So do it only
2cf7acf9
YR		 8282 * if current mode is limiting (default is LRM)
8283 */
de6eae1f
YR		 8284 if (cur_limiting_mode != EDC_MODE_LIMITING)
8285 return 0;
4d295db0 8286
de6eae1f 8287 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8288 MDIO_PMA_DEVAD,
8289 MDIO_PMA_REG_LRM_MODE,
8290 0);
de6eae1f 8291 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8292 MDIO_PMA_DEVAD,
8293 MDIO_PMA_REG_ROM_VER2,
8294 0x128);
de6eae1f 8295 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8296 MDIO_PMA_DEVAD,
8297 MDIO_PMA_REG_MISC_CTRL0,
8298 0x4008);
de6eae1f 8299 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8300 MDIO_PMA_DEVAD,
8301 MDIO_PMA_REG_LRM_MODE,
8302 0xaaaa);
4d295db0 8303 }
de6eae1f 8304 return 0;
4d295db0
EG		 8305}
8306
fcf5b650
YR		 8307static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8308 struct bnx2x_phy *phy,
8309 u16 edc_mode)
ea4e040a 8310{
de6eae1f
YR		 8311 u16 phy_identifier;
8312 u16 rom_ver2_val;
62b29a5d 8313 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 8314 MDIO_PMA_DEVAD,
8315 MDIO_PMA_REG_PHY_IDENTIFIER,
8316 &phy_identifier);
ea4e040a 8317
de6eae1f 8318 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8319 MDIO_PMA_DEVAD,
8320 MDIO_PMA_REG_PHY_IDENTIFIER,
8321 (phy_identifier & ~(1<<9)));
ea4e040a 8322
62b29a5d 8323 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 8324 MDIO_PMA_DEVAD,
8325 MDIO_PMA_REG_ROM_VER2,
8326 &rom_ver2_val);
de6eae1f
YR		 8327 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8328 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8329 MDIO_PMA_DEVAD,
8330 MDIO_PMA_REG_ROM_VER2,
8331 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4d295db0 8332
de6eae1f 8333 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8334 MDIO_PMA_DEVAD,
8335 MDIO_PMA_REG_PHY_IDENTIFIER,
8336 (phy_identifier | (1<<9)));
4d295db0 8337
de6eae1f 8338 return 0;
b7737c9b 8339}
ea4e040a 8340
a22f0788
YR		 8341static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8342 struct link_params *params,
8343 u32 action)
8344{
8345 struct bnx2x *bp = params->bp;
5c107fda 8346 u16 val;
a22f0788
YR		 8347 switch (action) {
8348 case DISABLE_TX:
a8db5b4c 8349 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788
YR		 8350 break;
8351 case ENABLE_TX:
8352 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
a8db5b4c 8353 bnx2x_sfp_set_transmitter(params, phy, 1);
a22f0788 8354 break;
5c107fda
YR		 8355 case PHY_INIT:
8356 bnx2x_cl45_write(bp, phy,
8357 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8358 (1<<2) | (1<<5));
8359 bnx2x_cl45_write(bp, phy,
8360 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8361 0);
8362 bnx2x_cl45_write(bp, phy,
8363 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8364 /* Make MOD_ABS give interrupt on change */
8365 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8366 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8367 &val);
8368 val |= (1<<12);
8369 if (phy->flags & FLAGS_NOC)
8370 val |= (3<<5);
8371 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8372 * status which reflect SFP+ module over-current
8373 */
8374 if (!(phy->flags & FLAGS_NOC))
8375 val &= 0xff8f; /* Reset bits 4-6 */
8376 bnx2x_cl45_write(bp, phy,
8377 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8378 val);
8379
8380 /* Set 2-wire transfer rate of SFP+ module EEPROM
8381 * to 100Khz since some DACs(direct attached cables) do
8382 * not work at 400Khz.
8383 */
8384 bnx2x_cl45_write(bp, phy,
8385 MDIO_PMA_DEVAD,
8386 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8387 0xa001);
8388 break;
a22f0788
YR		 8389 default:
8390 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8391 action);
8392 return;
8393 }
8394}
8395
3c9ada22 8396static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
a8db5b4c
YR		 8397 u8 gpio_mode)
8398{
8399 struct bnx2x *bp = params->bp;
8400
8401 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8402 offsetof(struct shmem_region,
8403 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8404 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8405 switch (fault_led_gpio) {
8406 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8407 return;
8408 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8409 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8410 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8411 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8412 {
8413 u8 gpio_port = bnx2x_get_gpio_port(params);
8414 u16 gpio_pin = fault_led_gpio -
8415 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8416 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8417 "pin %x port %x mode %x\n",
8418 gpio_pin, gpio_port, gpio_mode);
8419 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8420 }
8421 break;
8422 default:
8423 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8424 fault_led_gpio);
8425 }
8426}
8427
3c9ada22
YR		 8428static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8429 u8 gpio_mode)
8430{
8431 u32 pin_cfg;
8432 u8 port = params->port;
8433 struct bnx2x *bp = params->bp;
8434 pin_cfg = (REG_RD(bp, params->shmem_base +
8435 offsetof(struct shmem_region,
8436 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8437 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8438 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8439 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8440 gpio_mode, pin_cfg);
8441 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8442}
8443
8444static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8445 u8 gpio_mode)
8446{
8447 struct bnx2x *bp = params->bp;
8448 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8449 if (CHIP_IS_E3(bp)) {
8f73f0b9 8450 /* Low ==> if SFP+ module is supported otherwise
3c9ada22
YR		 8451 * High ==> if SFP+ module is not on the approved vendor list
8452 */
8453 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8454 } else
8455 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8456}
8457
985848f8
YR		 8458static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8459 struct link_params *params)
8460{
b76070b4 8461 struct bnx2x *bp = params->bp;
5a1fbf40 8462 bnx2x_warpcore_power_module(params, 0);
b76070b4
YR		 8463 /* Put Warpcore in low power mode */
8464 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8465
8466 /* Put LCPLL in low power mode */
8467 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8468 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8469 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
985848f8
YR		 8470}
8471
e4d78f12
YR		 8472static void bnx2x_power_sfp_module(struct link_params *params,
8473 struct bnx2x_phy *phy,
8474 u8 power)
8475{
8476 struct bnx2x *bp = params->bp;
8477 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8478
8479 switch (phy->type) {
8480 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8481 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8482 bnx2x_8727_power_module(params->bp, phy, power);
8483 break;
3c9ada22 8484 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5a1fbf40 8485 bnx2x_warpcore_power_module(params, power);
3c9ada22
YR		 8486 break;
8487 default:
8488 break;
8489 }
8490}
8491static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8492 struct bnx2x_phy *phy,
8493 u16 edc_mode)
8494{
8495 u16 val = 0;
8496 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8497 struct bnx2x *bp = params->bp;
8498
8499 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8500 /* This is a global register which controls all lanes */
8501 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8502 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8503 val &= ~(0xf << (lane << 2));
8504
8505 switch (edc_mode) {
8506 case EDC_MODE_LINEAR:
8507 case EDC_MODE_LIMITING:
8508 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8509 break;
8510 case EDC_MODE_PASSIVE_DAC:
8511 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8512 break;
e4d78f12
YR		 8513 default:
8514 break;
8515 }
3c9ada22
YR		 8516
8517 val |= (mode << (lane << 2));
8518 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8519 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8520 /* A must read */
8521 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8522 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8523
19af03a3
YR		 8524 /* Restart microcode to re-read the new mode */
8525 bnx2x_warpcore_reset_lane(bp, phy, 1);
8526 bnx2x_warpcore_reset_lane(bp, phy, 0);
3c9ada22 8527
e4d78f12
YR		 8528}
8529
8530static void bnx2x_set_limiting_mode(struct link_params *params,
8531 struct bnx2x_phy *phy,
8532 u16 edc_mode)
8533{
8534 switch (phy->type) {
8535 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8536 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8537 break;
8538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8540 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8541 break;
3c9ada22
YR		 8542 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8543 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8544 break;
e4d78f12
YR		 8545 }
8546}
8547
fcf5b650
YR		 8548int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8549 struct link_params *params)
b7737c9b 8550{
b7737c9b 8551 struct bnx2x *bp = params->bp;
de6eae1f 8552 u16 edc_mode;
fcf5b650 8553 int rc = 0;
ea4e040a 8554
de6eae1f
YR		 8555 u32 val = REG_RD(bp, params->shmem_base +
8556 offsetof(struct shmem_region, dev_info.
8557 port_feature_config[params->port].config));
5a1fbf40
YR		 8558 /* Enabled transmitter by default */
8559 bnx2x_sfp_set_transmitter(params, phy, 1);
de6eae1f
YR		 8560 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8561 params->port);
e4d78f12
YR		 8562 /* Power up module */
8563 bnx2x_power_sfp_module(params, phy, 1);
de6eae1f
YR		 8564 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8565 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8566 return -EINVAL;
cd88ccee 8567 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
d231023e 8568 /* Check SFP+ module compatibility */
de6eae1f
YR		 8569 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8570 rc = -EINVAL;
8571 /* Turn on fault module-detected led */
a8db5b4c
YR		 8572 bnx2x_set_sfp_module_fault_led(params,
8573 MISC_REGISTERS_GPIO_HIGH);
8574
e4d78f12
YR		 8575 /* Check if need to power down the SFP+ module */
8576 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8577 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
de6eae1f 8578 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
e4d78f12 8579 bnx2x_power_sfp_module(params, phy, 0);
de6eae1f
YR		 8580 return rc;
8581 }
8582 } else {
8583 /* Turn off fault module-detected led */
a8db5b4c 8584 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
62b29a5d 8585 }
b7737c9b 8586
8f73f0b9 8587 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
2cf7acf9
YR		 8588 * is done automatically
8589 */
e4d78f12
YR		 8590 bnx2x_set_limiting_mode(params, phy, edc_mode);
8591
5a1fbf40
YR		 8592 /* Disable transmit for this module if the module is not approved, and
8593 * laser needs to be disabled.
de6eae1f 8594 */
5a1fbf40
YR		 8595 if ((rc) &&
8596 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8597 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
a8db5b4c 8598 bnx2x_sfp_set_transmitter(params, phy, 0);
b7737c9b 8599
de6eae1f
YR		 8600 return rc;
8601}
8602
8603void bnx2x_handle_module_detect_int(struct link_params *params)
b7737c9b
YR		 8604{
8605 struct bnx2x *bp = params->bp;
3c9ada22 8606 struct bnx2x_phy *phy;
de6eae1f 8607 u32 gpio_val;
3c9ada22 8608 u8 gpio_num, gpio_port;
5a1fbf40 8609 if (CHIP_IS_E3(bp)) {
3c9ada22 8610 phy = &params->phy[INT_PHY];
5a1fbf40
YR		 8611 /* Always enable TX laser,will be disabled in case of fault */
8612 bnx2x_sfp_set_transmitter(params, phy, 1);
8613 } else {
3c9ada22 8614 phy = &params->phy[EXT_PHY1];
5a1fbf40 8615 }
3c9ada22
YR		 8616 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8617 params->port, &gpio_num, &gpio_port) ==
8618 -EINVAL) {
8619 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8620 return;
8621 }
4d295db0 8622
de6eae1f 8623 /* Set valid module led off */
a8db5b4c 8624 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
4d295db0 8625
2cf7acf9 8626 /* Get current gpio val reflecting module plugged in / out*/
3c9ada22 8627 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
62b29a5d 8628
de6eae1f
YR		 8629 /* Call the handling function in case module is detected */
8630 if (gpio_val == 0) {
55386fe8 8631 bnx2x_set_mdio_emac_per_phy(bp, params);
dbef807e
YM		 8632 bnx2x_set_aer_mmd(params, phy);
8633
e4d78f12 8634 bnx2x_power_sfp_module(params, phy, 1);
3c9ada22 8635 bnx2x_set_gpio_int(bp, gpio_num,
de6eae1f 8636 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3c9ada22 8637 gpio_port);
dbef807e 8638 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
de6eae1f 8639 bnx2x_sfp_module_detection(phy, params);
dbef807e
YM		 8640 if (CHIP_IS_E3(bp)) {
8641 u16 rx_tx_in_reset;
8642 /* In case WC is out of reset, reconfigure the
8643 * link speed while taking into account 1G
8644 * module limitation.
8645 */
8646 bnx2x_cl45_read(bp, phy,
8647 MDIO_WC_DEVAD,
8648 MDIO_WC_REG_DIGITAL5_MISC6,
8649 &rx_tx_in_reset);
8650 if (!rx_tx_in_reset) {
8651 bnx2x_warpcore_reset_lane(bp, phy, 1);
8652 bnx2x_warpcore_config_sfi(phy, params);
8653 bnx2x_warpcore_reset_lane(bp, phy, 0);
8654 }
8655 }
8656 } else {
de6eae1f 8657 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
dbef807e 8658 }
de6eae1f 8659 } else {
3c9ada22 8660 bnx2x_set_gpio_int(bp, gpio_num,
de6eae1f 8661 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3c9ada22 8662 gpio_port);
8f73f0b9 8663 /* Module was plugged out.
2cf7acf9
YR		 8664 * Disable transmit for this module
8665 */
1ac9e428 8666 phy->media_type = ETH_PHY_NOT_PRESENT;
62b29a5d 8667 }
de6eae1f 8668}
62b29a5d 8669
c688fe2f
YR		 8670/******************************************************************/
8671/* Used by 8706 and 8727 */
8672/******************************************************************/
8673static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8674 struct bnx2x_phy *phy,
8675 u16 alarm_status_offset,
8676 u16 alarm_ctrl_offset)
8677{
8678 u16 alarm_status, val;
8679 bnx2x_cl45_read(bp, phy,
8680 MDIO_PMA_DEVAD, alarm_status_offset,
8681 &alarm_status);
8682 bnx2x_cl45_read(bp, phy,
8683 MDIO_PMA_DEVAD, alarm_status_offset,
8684 &alarm_status);
8685 /* Mask or enable the fault event. */
8686 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8687 if (alarm_status & (1<<0))
8688 val &= ~(1<<0);
8689 else
8690 val |= (1<<0);
8691 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8692}
de6eae1f
YR		 8693/******************************************************************/
8694/* common BCM8706/BCM8726 PHY SECTION */
8695/******************************************************************/
8696static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8697 struct link_params *params,
8698 struct link_vars *vars)
8699{
8700 u8 link_up = 0;
8701 u16 val1, val2, rx_sd, pcs_status;
8702 struct bnx2x *bp = params->bp;
8703 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8704 /* Clear RX Alarm*/
62b29a5d 8705 bnx2x_cl45_read(bp, phy,
60d2fe03 8706 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
c688fe2f 8707
60d2fe03
YR		 8708 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8709 MDIO_PMA_LASI_TXCTRL);
c688fe2f 8710
d231023e 8711 /* Clear LASI indication*/
de6eae1f 8712 bnx2x_cl45_read(bp, phy,
60d2fe03 8713 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
de6eae1f 8714 bnx2x_cl45_read(bp, phy,
60d2fe03 8715 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
de6eae1f 8716 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
62b29a5d
YR		 8717
8718 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 8719 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8720 bnx2x_cl45_read(bp, phy,
8721 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8722 bnx2x_cl45_read(bp, phy,
8723 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8724 bnx2x_cl45_read(bp, phy,
8725 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
62b29a5d 8726
de6eae1f
YR		 8727 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8728 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8f73f0b9 8729 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
2cf7acf9 8730 * are set, or if the autoneg bit 1 is set
de6eae1f
YR		 8731 */
8732 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8733 if (link_up) {
8734 if (val2 & (1<<1))
8735 vars->line_speed = SPEED_1000;
8736 else
8737 vars->line_speed = SPEED_10000;
62b29a5d 8738 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0 8739 vars->duplex = DUPLEX_FULL;
de6eae1f 8740 }
c688fe2f
YR		 8741
8742 /* Capture 10G link fault. Read twice to clear stale value. */
8743 if (vars->line_speed == SPEED_10000) {
8744 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 8745 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f 8746 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 8747 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f
YR		 8748 if (val1 & (1<<0))
8749 vars->fault_detected = 1;
8750 }
8751
62b29a5d 8752 return link_up;
b7737c9b 8753}
62b29a5d 8754
de6eae1f
YR		 8755/******************************************************************/
8756/* BCM8706 PHY SECTION */
8757/******************************************************************/
8758static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 8759 struct link_params *params,
8760 struct link_vars *vars)
8761{
a8db5b4c
YR		 8762 u32 tx_en_mode;
8763 u16 cnt, val, tmp1;
b7737c9b 8764 struct bnx2x *bp = params->bp;
3deb8167 8765
de6eae1f 8766 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 8767 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 8768 /* HW reset */
8769 bnx2x_ext_phy_hw_reset(bp, params->port);
8770 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 8771 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 8772
de6eae1f
YR		 8773 /* Wait until fw is loaded */
8774 for (cnt = 0; cnt < 100; cnt++) {
8775 bnx2x_cl45_read(bp, phy,
8776 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8777 if (val)
8778 break;
d231023e 8779 usleep_range(10000, 20000);
de6eae1f
YR		 8780 }
8781 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8782 if ((params->feature_config_flags &
8783 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8784 u8 i;
8785 u16 reg;
8786 for (i = 0; i < 4; i++) {
8787 reg = MDIO_XS_8706_REG_BANK_RX0 +
8788 i*(MDIO_XS_8706_REG_BANK_RX1 -
8789 MDIO_XS_8706_REG_BANK_RX0);
8790 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8791 /* Clear first 3 bits of the control */
8792 val &= ~0x7;
8793 /* Set control bits according to configuration */
8794 val |= (phy->rx_preemphasis[i] & 0x7);
8795 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8796 " reg 0x%x <-- val 0x%x\n", reg, val);
8797 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8798 }
8799 }
8800 /* Force speed */
8801 if (phy->req_line_speed == SPEED_10000) {
8802 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
ea4e040a 8803
de6eae1f
YR		 8804 bnx2x_cl45_write(bp, phy,
8805 MDIO_PMA_DEVAD,
8806 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8807 bnx2x_cl45_write(bp, phy,
60d2fe03 8808 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
c688fe2f
YR		 8809 0);
8810 /* Arm LASI for link and Tx fault. */
8811 bnx2x_cl45_write(bp, phy,
60d2fe03 8812 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
de6eae1f 8813 } else {
25985edc 8814 /* Force 1Gbps using autoneg with 1G advertisement */
6bbca910 8815
de6eae1f
YR		 8816 /* Allow CL37 through CL73 */
8817 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8818 bnx2x_cl45_write(bp, phy,
8819 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6bbca910 8820
25985edc 8821 /* Enable Full-Duplex advertisement on CL37 */
de6eae1f
YR		 8822 bnx2x_cl45_write(bp, phy,
8823 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8824 /* Enable CL37 AN */
8825 bnx2x_cl45_write(bp, phy,
8826 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8827 /* 1G support */
8828 bnx2x_cl45_write(bp, phy,
8829 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6bbca910 8830
de6eae1f
YR		 8831 /* Enable clause 73 AN */
8832 bnx2x_cl45_write(bp, phy,
8833 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8834 bnx2x_cl45_write(bp, phy,
60d2fe03 8835 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f
YR		 8836 0x0400);
8837 bnx2x_cl45_write(bp, phy,
60d2fe03 8838 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
de6eae1f
YR		 8839 0x0004);
8840 }
8841 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
a8db5b4c 8842
8f73f0b9 8843 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
a8db5b4c
YR		 8844 * power mode, if TX Laser is disabled
8845 */
8846
8847 tx_en_mode = REG_RD(bp, params->shmem_base +
8848 offsetof(struct shmem_region,
8849 dev_info.port_hw_config[params->port].sfp_ctrl))
8850 & PORT_HW_CFG_TX_LASER_MASK;
8851
8852 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8853 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8854 bnx2x_cl45_read(bp, phy,
8855 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8856 tmp1 |= 0x1;
8857 bnx2x_cl45_write(bp, phy,
8858 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8859 }
8860
de6eae1f
YR		 8861 return 0;
8862}
ea4e040a 8863
fcf5b650
YR		 8864static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8865 struct link_params *params,
8866 struct link_vars *vars)
de6eae1f
YR		 8867{
8868 return bnx2x_8706_8726_read_status(phy, params, vars);
8869}
6bbca910 8870
de6eae1f
YR		 8871/******************************************************************/
8872/* BCM8726 PHY SECTION */
8873/******************************************************************/
8874static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8875 struct link_params *params)
8876{
8877 struct bnx2x *bp = params->bp;
8878 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8879 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8880}
62b29a5d 8881
de6eae1f
YR		 8882static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8883 struct link_params *params)
8884{
8885 struct bnx2x *bp = params->bp;
8886 /* Need to wait 100ms after reset */
8887 msleep(100);
62b29a5d 8888
de6eae1f
YR		 8889 /* Micro controller re-boot */
8890 bnx2x_cl45_write(bp, phy,
8891 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
62b29a5d 8892
de6eae1f
YR		 8893 /* Set soft reset */
8894 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8895 MDIO_PMA_DEVAD,
8896 MDIO_PMA_REG_GEN_CTRL,
8897 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
62b29a5d 8898
de6eae1f 8899 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8900 MDIO_PMA_DEVAD,
8901 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6bbca910 8902
de6eae1f 8903 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8904 MDIO_PMA_DEVAD,
8905 MDIO_PMA_REG_GEN_CTRL,
8906 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f 8907
d231023e 8908 /* Wait for 150ms for microcode load */
de6eae1f
YR		 8909 msleep(150);
8910
8911 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8912 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 8913 MDIO_PMA_DEVAD,
8914 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f
YR		 8915
8916 msleep(200);
8917 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
b7737c9b
YR		 8918}
8919
de6eae1f 8920static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 8921 struct link_params *params,
8922 struct link_vars *vars)
8923{
8924 struct bnx2x *bp = params->bp;
de6eae1f
YR		 8925 u16 val1;
8926 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
62b29a5d
YR		 8927 if (link_up) {
8928 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 8929 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8930 &val1);
8931 if (val1 & (1<<15)) {
8932 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8933 link_up = 0;
8934 vars->line_speed = 0;
8935 }
62b29a5d
YR		 8936 }
8937 return link_up;
b7737c9b
YR		 8938}
8939
de6eae1f 8940
fcf5b650
YR		 8941static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8942 struct link_params *params,
8943 struct link_vars *vars)
b7737c9b
YR		 8944{
8945 struct bnx2x *bp = params->bp;
de6eae1f 8946 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
62b29a5d 8947
de6eae1f 8948 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6d870c39 8949 bnx2x_wait_reset_complete(bp, phy, params);
62b29a5d 8950
de6eae1f 8951 bnx2x_8726_external_rom_boot(phy, params);
62b29a5d 8952
8f73f0b9 8953 /* Need to call module detected on initialization since the module
2cf7acf9
YR		 8954 * detection triggered by actual module insertion might occur before
8955 * driver is loaded, and when driver is loaded, it reset all
8956 * registers, including the transmitter
8957 */
de6eae1f 8958 bnx2x_sfp_module_detection(phy, params);
62b29a5d 8959
de6eae1f
YR		 8960 if (phy->req_line_speed == SPEED_1000) {
8961 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8962 bnx2x_cl45_write(bp, phy,
8963 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8964 bnx2x_cl45_write(bp, phy,
8965 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8966 bnx2x_cl45_write(bp, phy,
60d2fe03 8967 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
de6eae1f 8968 bnx2x_cl45_write(bp, phy,
60d2fe03 8969 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f
YR		 8970 0x400);
8971 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8972 (phy->speed_cap_mask &
8973 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8974 ((phy->speed_cap_mask &
8975 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8976 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8977 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8978 /* Set Flow control */
8979 bnx2x_ext_phy_set_pause(params, phy, vars);
8980 bnx2x_cl45_write(bp, phy,
8981 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8982 bnx2x_cl45_write(bp, phy,
8983 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8984 bnx2x_cl45_write(bp, phy,
8985 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8986 bnx2x_cl45_write(bp, phy,
8987 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8988 bnx2x_cl45_write(bp, phy,
8989 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8f73f0b9 8990 /* Enable RX-ALARM control to receive interrupt for 1G speed
2cf7acf9
YR		 8991 * change
8992 */
de6eae1f 8993 bnx2x_cl45_write(bp, phy,
60d2fe03 8994 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
de6eae1f 8995 bnx2x_cl45_write(bp, phy,
60d2fe03 8996 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f 8997 0x400);
62b29a5d 8998
de6eae1f
YR		 8999 } else { /* Default 10G. Set only LASI control */
9000 bnx2x_cl45_write(bp, phy,
60d2fe03 9001 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
7aa0711f
YR		 9002 }
9003
de6eae1f
YR		 9004 /* Set TX PreEmphasis if needed */
9005 if ((params->feature_config_flags &
9006 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
94f05b0f
JP		 9007 DP(NETIF_MSG_LINK,
9008 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
de6eae1f
YR		 9009 phy->tx_preemphasis[0],
9010 phy->tx_preemphasis[1]);
9011 bnx2x_cl45_write(bp, phy,
9012 MDIO_PMA_DEVAD,
9013 MDIO_PMA_REG_8726_TX_CTRL1,
9014 phy->tx_preemphasis[0]);
c18aa15d 9015
de6eae1f
YR		 9016 bnx2x_cl45_write(bp, phy,
9017 MDIO_PMA_DEVAD,
9018 MDIO_PMA_REG_8726_TX_CTRL2,
9019 phy->tx_preemphasis[1]);
9020 }
ab6ad5a4 9021
de6eae1f 9022 return 0;
ab6ad5a4 9023
ea4e040a
YR		 9024}
9025
de6eae1f
YR		 9026static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9027 struct link_params *params)
2f904460 9028{
de6eae1f
YR		 9029 struct bnx2x *bp = params->bp;
9030 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9031 /* Set serial boot control for external load */
9032 bnx2x_cl45_write(bp, phy,
9033 MDIO_PMA_DEVAD,
9034 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9035}
9036
9037/******************************************************************/
9038/* BCM8727 PHY SECTION */
9039/******************************************************************/
7f02c4ad
YR		 9040
9041static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9042 struct link_params *params, u8 mode)
9043{
9044 struct bnx2x *bp = params->bp;
9045 u16 led_mode_bitmask = 0;
9046 u16 gpio_pins_bitmask = 0;
9047 u16 val;
9048 /* Only NOC flavor requires to set the LED specifically */
9049 if (!(phy->flags & FLAGS_NOC))
9050 return;
9051 switch (mode) {
9052 case LED_MODE_FRONT_PANEL_OFF:
9053 case LED_MODE_OFF:
9054 led_mode_bitmask = 0;
9055 gpio_pins_bitmask = 0x03;
9056 break;
9057 case LED_MODE_ON:
9058 led_mode_bitmask = 0;
9059 gpio_pins_bitmask = 0x02;
9060 break;
9061 case LED_MODE_OPER:
9062 led_mode_bitmask = 0x60;
9063 gpio_pins_bitmask = 0x11;
9064 break;
9065 }
9066 bnx2x_cl45_read(bp, phy,
9067 MDIO_PMA_DEVAD,
9068 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9069 &val);
9070 val &= 0xff8f;
9071 val |= led_mode_bitmask;
9072 bnx2x_cl45_write(bp, phy,
9073 MDIO_PMA_DEVAD,
9074 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9075 val);
9076 bnx2x_cl45_read(bp, phy,
9077 MDIO_PMA_DEVAD,
9078 MDIO_PMA_REG_8727_GPIO_CTRL,
9079 &val);
9080 val &= 0xffe0;
9081 val |= gpio_pins_bitmask;
9082 bnx2x_cl45_write(bp, phy,
9083 MDIO_PMA_DEVAD,
9084 MDIO_PMA_REG_8727_GPIO_CTRL,
9085 val);
9086}
de6eae1f
YR		 9087static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9088 struct link_params *params) {
9089 u32 swap_val, swap_override;
9090 u8 port;
8f73f0b9 9091 /* The PHY reset is controlled by GPIO 1. Fake the port number
de6eae1f 9092 * to cancel the swap done in set_gpio()
2f904460 9093 */
de6eae1f
YR		 9094 struct bnx2x *bp = params->bp;
9095 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9096 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9097 port = (swap_val && swap_override) ^ 1;
9098 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 9099 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2f904460 9100}
e10bc84d 9101
dbef807e
YM		 9102static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9103 struct link_params *params)
9104{
9105 struct bnx2x *bp = params->bp;
9106 u16 tmp1, val;
9107 /* Set option 1G speed */
9108 if ((phy->req_line_speed == SPEED_1000) ||
9109 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9110 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9111 bnx2x_cl45_write(bp, phy,
9112 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9113 bnx2x_cl45_write(bp, phy,
9114 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9115 bnx2x_cl45_read(bp, phy,
9116 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9117 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9118 /* Power down the XAUI until link is up in case of dual-media
9119 * and 1G
9120 */
9121 if (DUAL_MEDIA(params)) {
9122 bnx2x_cl45_read(bp, phy,
9123 MDIO_PMA_DEVAD,
9124 MDIO_PMA_REG_8727_PCS_GP, &val);
9125 val |= (3<<10);
9126 bnx2x_cl45_write(bp, phy,
9127 MDIO_PMA_DEVAD,
9128 MDIO_PMA_REG_8727_PCS_GP, val);
9129 }
9130 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9131 ((phy->speed_cap_mask &
9132 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9133 ((phy->speed_cap_mask &
9134 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9135 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9136
9137 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9138 bnx2x_cl45_write(bp, phy,
9139 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9140 bnx2x_cl45_write(bp, phy,
9141 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9142 } else {
9143 /* Since the 8727 has only single reset pin, need to set the 10G
9144 * registers although it is default
9145 */
9146 bnx2x_cl45_write(bp, phy,
9147 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9148 0x0020);
9149 bnx2x_cl45_write(bp, phy,
9150 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9151 bnx2x_cl45_write(bp, phy,
9152 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9153 bnx2x_cl45_write(bp, phy,
9154 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9155 0x0008);
9156 }
9157}
9158
fcf5b650
YR		 9159static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9160 struct link_params *params,
9161 struct link_vars *vars)
ea4e040a 9162{
a8db5b4c 9163 u32 tx_en_mode;
5c107fda 9164 u16 tmp1, mod_abs, tmp2;
ea4e040a 9165 struct bnx2x *bp = params->bp;
de6eae1f 9166 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 9167
6d870c39 9168 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 9169
de6eae1f 9170 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
ea4e040a 9171
5c107fda 9172 bnx2x_8727_specific_func(phy, params, PHY_INIT);
8f73f0b9 9173 /* Initially configure MOD_ABS to interrupt when module is
2cf7acf9
YR		 9174 * presence( bit 8)
9175 */
de6eae1f
YR		 9176 bnx2x_cl45_read(bp, phy,
9177 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8f73f0b9 9178 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
2cf7acf9
YR		 9179 * When the EDC is off it locks onto a reference clock and avoids
9180 * becoming 'lost'
9181 */
7f02c4ad
YR		 9182 mod_abs &= ~(1<<8);
9183 if (!(phy->flags & FLAGS_NOC))
9184 mod_abs &= ~(1<<9);
de6eae1f
YR		 9185 bnx2x_cl45_write(bp, phy,
9186 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 9187
85242eea
YR		 9188 /* Enable/Disable PHY transmitter output */
9189 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9190
de6eae1f
YR		 9191 bnx2x_8727_power_module(bp, phy, 1);
9192
9193 bnx2x_cl45_read(bp, phy,
9194 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9195
9196 bnx2x_cl45_read(bp, phy,
60d2fe03 9197 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
de6eae1f 9198
dbef807e 9199 bnx2x_8727_config_speed(phy, params);
5c107fda 9200
b7737c9b 9201
de6eae1f
YR		 9202 /* Set TX PreEmphasis if needed */
9203 if ((params->feature_config_flags &
9204 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9205 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9206 phy->tx_preemphasis[0],
9207 phy->tx_preemphasis[1]);
9208 bnx2x_cl45_write(bp, phy,
9209 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9210 phy->tx_preemphasis[0]);
ea4e040a 9211
de6eae1f
YR		 9212 bnx2x_cl45_write(bp, phy,
9213 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9214 phy->tx_preemphasis[1]);
9215 }
ea4e040a 9216
8f73f0b9 9217 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
a8db5b4c
YR		 9218 * power mode, if TX Laser is disabled
9219 */
9220 tx_en_mode = REG_RD(bp, params->shmem_base +
9221 offsetof(struct shmem_region,
9222 dev_info.port_hw_config[params->port].sfp_ctrl))
9223 & PORT_HW_CFG_TX_LASER_MASK;
9224
9225 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9226
9227 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9228 bnx2x_cl45_read(bp, phy,
9229 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9230 tmp2 |= 0x1000;
9231 tmp2 &= 0xFFEF;
9232 bnx2x_cl45_write(bp, phy,
9233 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
59a2e53b
YR		 9234 bnx2x_cl45_read(bp, phy,
9235 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9236 &tmp2);
9237 bnx2x_cl45_write(bp, phy,
9238 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9239 (tmp2 & 0x7fff));
a8db5b4c
YR		 9240 }
9241
de6eae1f 9242 return 0;
ea4e040a
YR		 9243}
9244
de6eae1f
YR		 9245static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9246 struct link_params *params)
ea4e040a 9247{
ea4e040a 9248 struct bnx2x *bp = params->bp;
de6eae1f
YR		 9249 u16 mod_abs, rx_alarm_status;
9250 u32 val = REG_RD(bp, params->shmem_base +
9251 offsetof(struct shmem_region, dev_info.
9252 port_feature_config[params->port].
9253 config));
9254 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 9255 MDIO_PMA_DEVAD,
9256 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
de6eae1f 9257 if (mod_abs & (1<<8)) {
ea4e040a 9258
de6eae1f 9259 /* Module is absent */
94f05b0f
JP		 9260 DP(NETIF_MSG_LINK,
9261 "MOD_ABS indication show module is absent\n");
1ac9e428 9262 phy->media_type = ETH_PHY_NOT_PRESENT;
8f73f0b9 9263 /* 1. Set mod_abs to detect next module
2cf7acf9
YR		 9264 * presence event
9265 * 2. Set EDC off by setting OPTXLOS signal input to low
9266 * (bit 9).
9267 * When the EDC is off it locks onto a reference clock and
9268 * avoids becoming 'lost'.
9269 */
7f02c4ad
YR		 9270 mod_abs &= ~(1<<8);
9271 if (!(phy->flags & FLAGS_NOC))
9272 mod_abs &= ~(1<<9);
de6eae1f 9273 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 9274 MDIO_PMA_DEVAD,
9275 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 9276
8f73f0b9 9277 /* Clear RX alarm since it stays up as long as
2cf7acf9
YR		 9278 * the mod_abs wasn't changed
9279 */
de6eae1f 9280 bnx2x_cl45_read(bp, phy,
cd88ccee 9281 MDIO_PMA_DEVAD,
60d2fe03 9282 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
ea4e040a 9283
de6eae1f
YR		 9284 } else {
9285 /* Module is present */
94f05b0f
JP		 9286 DP(NETIF_MSG_LINK,
9287 "MOD_ABS indication show module is present\n");
8f73f0b9 9288 /* First disable transmitter, and if the module is ok, the
2cf7acf9
YR		 9289 * module_detection will enable it
9290 * 1. Set mod_abs to detect next module absent event ( bit 8)
9291 * 2. Restore the default polarity of the OPRXLOS signal and
9292 * this signal will then correctly indicate the presence or
9293 * absence of the Rx signal. (bit 9)
9294 */
7f02c4ad
YR		 9295 mod_abs |= (1<<8);
9296 if (!(phy->flags & FLAGS_NOC))
9297 mod_abs |= (1<<9);
e10bc84d 9298 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 9299 MDIO_PMA_DEVAD,
9300 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 9301
8f73f0b9 9302 /* Clear RX alarm since it stays up as long as the mod_abs
2cf7acf9
YR		 9303 * wasn't changed. This is need to be done before calling the
9304 * module detection, otherwise it will clear* the link update
9305 * alarm
9306 */
de6eae1f
YR		 9307 bnx2x_cl45_read(bp, phy,
9308 MDIO_PMA_DEVAD,
60d2fe03 9309 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
ea4e040a 9310
ea4e040a 9311
de6eae1f
YR		 9312 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9313 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 9314 bnx2x_sfp_set_transmitter(params, phy, 0);
de6eae1f
YR		 9315
9316 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9317 bnx2x_sfp_module_detection(phy, params);
9318 else
9319 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
dbef807e
YM		 9320
9321 /* Reconfigure link speed based on module type limitations */
9322 bnx2x_8727_config_speed(phy, params);
ea4e040a 9323 }
de6eae1f
YR		 9324
9325 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
2cf7acf9
YR		 9326 rx_alarm_status);
9327 /* No need to check link status in case of module plugged in/out */
ea4e040a
YR		 9328}
9329
de6eae1f
YR		 9330static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9331 struct link_params *params,
9332 struct link_vars *vars)
9333
ea4e040a
YR		 9334{
9335 struct bnx2x *bp = params->bp;
27d02432 9336 u8 link_up = 0, oc_port = params->port;
de6eae1f 9337 u16 link_status = 0;
a22f0788
YR		 9338 u16 rx_alarm_status, lasi_ctrl, val1;
9339
9340 /* If PHY is not initialized, do not check link status */
9341 bnx2x_cl45_read(bp, phy,
60d2fe03 9342 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
a22f0788
YR		 9343 &lasi_ctrl);
9344 if (!lasi_ctrl)
9345 return 0;
9346
9045f6b4 9347 /* Check the LASI on Rx */
de6eae1f 9348 bnx2x_cl45_read(bp, phy,
60d2fe03 9349 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
de6eae1f
YR		 9350 &rx_alarm_status);
9351 vars->line_speed = 0;
9352 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9353
60d2fe03
YR		 9354 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9355 MDIO_PMA_LASI_TXCTRL);
c688fe2f 9356
de6eae1f 9357 bnx2x_cl45_read(bp, phy,
60d2fe03 9358 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
de6eae1f
YR		 9359
9360 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9361
9362 /* Clear MSG-OUT */
9363 bnx2x_cl45_read(bp, phy,
9364 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9365
8f73f0b9 9366 /* If a module is present and there is need to check
de6eae1f
YR		 9367 * for over current
9368 */
9369 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9370 /* Check over-current using 8727 GPIO0 input*/
9371 bnx2x_cl45_read(bp, phy,
9372 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9373 &val1);
9374
9375 if ((val1 & (1<<8)) == 0) {
27d02432
YR		 9376 if (!CHIP_IS_E1x(bp))
9377 oc_port = BP_PATH(bp) + (params->port << 1);
94f05b0f
JP		 9378 DP(NETIF_MSG_LINK,
9379 "8727 Power fault has been detected on port %d\n",
9380 oc_port);
2f751a80
YR		 9381 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9382 "been detected and the power to "
9383 "that SFP+ module has been removed "
9384 "to prevent failure of the card. "
9385 "Please remove the SFP+ module and "
9386 "restart the system to clear this "
9387 "error.\n",
27d02432 9388 oc_port);
2cf7acf9 9389 /* Disable all RX_ALARMs except for mod_abs */
de6eae1f
YR		 9390 bnx2x_cl45_write(bp, phy,
9391 MDIO_PMA_DEVAD,
60d2fe03 9392 MDIO_PMA_LASI_RXCTRL, (1<<5));
de6eae1f
YR		 9393
9394 bnx2x_cl45_read(bp, phy,
9395 MDIO_PMA_DEVAD,
9396 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9397 /* Wait for module_absent_event */
9398 val1 |= (1<<8);
9399 bnx2x_cl45_write(bp, phy,
9400 MDIO_PMA_DEVAD,
9401 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9402 /* Clear RX alarm */
9403 bnx2x_cl45_read(bp, phy,
9404 MDIO_PMA_DEVAD,
60d2fe03 9405 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
5a1fbf40 9406 bnx2x_8727_power_module(params->bp, phy, 0);
de6eae1f
YR		 9407 return 0;
9408 }
9409 } /* Over current check */
9410
9411 /* When module absent bit is set, check module */
9412 if (rx_alarm_status & (1<<5)) {
9413 bnx2x_8727_handle_mod_abs(phy, params);
9414 /* Enable all mod_abs and link detection bits */
9415 bnx2x_cl45_write(bp, phy,
60d2fe03 9416 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
de6eae1f
YR		 9417 ((1<<5) | (1<<2)));
9418 }
59a2e53b
YR		 9419
9420 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9421 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9422 bnx2x_sfp_set_transmitter(params, phy, 1);
9423 } else {
de6eae1f
YR		 9424 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9425 return 0;
9426 }
9427
9428 bnx2x_cl45_read(bp, phy,
9429 MDIO_PMA_DEVAD,
9430 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9431
8f73f0b9 9432 /* Bits 0..2 --> speed detected,
2cf7acf9
YR		 9433 * Bits 13..15--> link is down
9434 */
de6eae1f
YR		 9435 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9436 link_up = 1;
9437 vars->line_speed = SPEED_10000;
2cf7acf9
YR		 9438 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9439 params->port);
de6eae1f
YR		 9440 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9441 link_up = 1;
9442 vars->line_speed = SPEED_1000;
9443 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9444 params->port);
9445 } else {
9446 link_up = 0;
9447 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9448 params->port);
9449 }
c688fe2f
YR		 9450
9451 /* Capture 10G link fault. */
9452 if (vars->line_speed == SPEED_10000) {
9453 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 9454 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f
YR		 9455
9456 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
60d2fe03 9457 MDIO_PMA_LASI_TXSTAT, &val1);
c688fe2f
YR		 9458
9459 if (val1 & (1<<0)) {
9460 vars->fault_detected = 1;
9461 }
9462 }
9463
791f18c0 9464 if (link_up) {
de6eae1f 9465 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0
YR		 9466 vars->duplex = DUPLEX_FULL;
9467 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9468 }
a22f0788
YR		 9469
9470 if ((DUAL_MEDIA(params)) &&
9471 (phy->req_line_speed == SPEED_1000)) {
9472 bnx2x_cl45_read(bp, phy,
9473 MDIO_PMA_DEVAD,
9474 MDIO_PMA_REG_8727_PCS_GP, &val1);
8f73f0b9 9475 /* In case of dual-media board and 1G, power up the XAUI side,
a22f0788
YR		 9476 * otherwise power it down. For 10G it is done automatically
9477 */
9478 if (link_up)
9479 val1 &= ~(3<<10);
9480 else
9481 val1 |= (3<<10);
9482 bnx2x_cl45_write(bp, phy,
9483 MDIO_PMA_DEVAD,
9484 MDIO_PMA_REG_8727_PCS_GP, val1);
9485 }
de6eae1f 9486 return link_up;
b7737c9b 9487}
ea4e040a 9488
de6eae1f
YR		 9489static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9490 struct link_params *params)
b7737c9b
YR		 9491{
9492 struct bnx2x *bp = params->bp;
85242eea
YR		 9493
9494 /* Enable/Disable PHY transmitter output */
9495 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9496
de6eae1f 9497 /* Disable Transmitter */
a8db5b4c 9498 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788 9499 /* Clear LASI */
60d2fe03 9500 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
a22f0788 9501
ea4e040a 9502}
c18aa15d 9503
de6eae1f
YR		 9504/******************************************************************/
9505/* BCM8481/BCM84823/BCM84833 PHY SECTION */
9506/******************************************************************/
9507static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
11b2ec6b
YR		 9508 struct bnx2x *bp,
9509 u8 port)
ea4e040a 9510{
503976e9
YR		 9511 u16 val, fw_ver2, cnt, i;
9512 static struct bnx2x_reg_set reg_set[] = {
9513 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9514 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9515 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9516 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9517 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9518 };
9519 u16 fw_ver1;
ea4e040a 9520
0f6bb03d
YR		 9521 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9522 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11b2ec6b 9523 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
8267bbb0 9524 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
11b2ec6b
YR		 9525 phy->ver_addr);
9526 } else {
9527 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9528 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
b5a05550 9529 for (i = 0; i < ARRAY_SIZE(reg_set);
503976e9
YR		 9530 i++)
9531 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9532 reg_set[i].reg, reg_set[i].val);
11b2ec6b
YR		 9533
9534 for (cnt = 0; cnt < 100; cnt++) {
9535 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9536 if (val & 1)
9537 break;
9538 udelay(5);
9539 }
9540 if (cnt == 100) {
9541 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9542 "phy fw version(1)\n");
9543 bnx2x_save_spirom_version(bp, port, 0,
9544 phy->ver_addr);
9545 return;
9546 }
c87bca1e 9547
ea4e040a 9548
11b2ec6b
YR		 9549 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9550 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9551 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9552 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9553 for (cnt = 0; cnt < 100; cnt++) {
9554 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9555 if (val & 1)
9556 break;
9557 udelay(5);
9558 }
9559 if (cnt == 100) {
9560 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9561 "version(2)\n");
9562 bnx2x_save_spirom_version(bp, port, 0,
9563 phy->ver_addr);
9564 return;
9565 }
ea4e040a 9566
11b2ec6b
YR		 9567 /* lower 16 bits of the register SPI_FW_STATUS */
9568 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9569 /* upper 16 bits of register SPI_FW_STATUS */
9570 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
ea4e040a 9571
11b2ec6b 9572 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
de6eae1f 9573 phy->ver_addr);
ea4e040a
YR		 9574 }
9575
de6eae1f 9576}
de6eae1f
YR		 9577static void bnx2x_848xx_set_led(struct bnx2x *bp,
9578 struct bnx2x_phy *phy)
ea4e040a 9579{
503976e9
YR		 9580 u16 val, offset, i;
9581 static struct bnx2x_reg_set reg_set[] = {
9582 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9583 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9584 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9585 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9586 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9587 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9588 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9589 };
de6eae1f
YR		 9590 /* PHYC_CTL_LED_CTL */
9591 bnx2x_cl45_read(bp, phy,
9592 MDIO_PMA_DEVAD,
bac27bd9 9593 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
de6eae1f
YR		 9594 val &= 0xFE00;
9595 val |= 0x0092;
345b5d52 9596
de6eae1f
YR		 9597 bnx2x_cl45_write(bp, phy,
9598 MDIO_PMA_DEVAD,
bac27bd9 9599 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
ea4e040a 9600
b5a05550 9601 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
503976e9
YR		 9602 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9603 reg_set[i].val);
f25b3c8b 9604
0f6bb03d
YR		 9605 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9606 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
521683da
YR		 9607 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9608 else
9609 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9610
503976e9
YR		 9611 /* stretch_en for LED3*/
9612 bnx2x_cl45_read_or_write(bp, phy,
9613 MDIO_PMA_DEVAD, offset,
9614 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
ea4e040a
YR		 9615}
9616
5c107fda
YR		 9617static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9618 struct link_params *params,
9619 u32 action)
9620{
9621 struct bnx2x *bp = params->bp;
9622 switch (action) {
9623 case PHY_INIT:
0f6bb03d
YR		 9624 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9625 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
5c107fda
YR		 9626 /* Save spirom version */
9627 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9628 }
9629 /* This phy uses the NIG latch mechanism since link indication
9630 * arrives through its LED4 and not via its LASI signal, so we
9631 * get steady signal instead of clear on read
9632 */
9633 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9634 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9635
9636 bnx2x_848xx_set_led(bp, phy);
9637 break;
9638 }
9639}
9640
fcf5b650
YR		 9641static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9642 struct link_params *params,
9643 struct link_vars *vars)
ea4e040a 9644{
c18aa15d 9645 struct bnx2x *bp = params->bp;
503976e9 9646 u16 autoneg_val, an_1000_val, an_10_100_val;
bac27bd9 9647
5c107fda 9648 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
de6eae1f
YR		 9649 bnx2x_cl45_write(bp, phy,
9650 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
ea4e040a 9651
de6eae1f
YR		 9652 /* set 1000 speed advertisement */
9653 bnx2x_cl45_read(bp, phy,
9654 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9655 &an_1000_val);
57963ed9 9656
de6eae1f
YR		 9657 bnx2x_ext_phy_set_pause(params, phy, vars);
9658 bnx2x_cl45_read(bp, phy,
9659 MDIO_AN_DEVAD,
9660 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9661 &an_10_100_val);
9662 bnx2x_cl45_read(bp, phy,
9663 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9664 &autoneg_val);
9665 /* Disable forced speed */
9666 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9667 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
ea4e040a 9668
de6eae1f
YR		 9669 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9670 (phy->speed_cap_mask &
9671 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9672 (phy->req_line_speed == SPEED_1000)) {
9673 an_1000_val |= (1<<8);
9674 autoneg_val |= (1<<9 | 1<<12);
9675 if (phy->req_duplex == DUPLEX_FULL)
9676 an_1000_val |= (1<<9);
9677 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9678 } else
9679 an_1000_val &= ~((1<<8) | (1<<9));
ea4e040a 9680
de6eae1f
YR		 9681 bnx2x_cl45_write(bp, phy,
9682 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9683 an_1000_val);
ea4e040a 9684
0520e63a 9685 /* set 100 speed advertisement */
75318327 9686 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
de6eae1f 9687 (phy->speed_cap_mask &
0520e63a 9688 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
75318327 9689 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
de6eae1f
YR		 9690 an_10_100_val |= (1<<7);
9691 /* Enable autoneg and restart autoneg for legacy speeds */
9692 autoneg_val |= (1<<9 | 1<<12);
b7737c9b 9693
de6eae1f
YR		 9694 if (phy->req_duplex == DUPLEX_FULL)
9695 an_10_100_val |= (1<<8);
9696 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9697 }
9698 /* set 10 speed advertisement */
9699 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
0520e63a
YR		 9700 (phy->speed_cap_mask &
9701 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9702 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9703 (phy->supported &
9704 (SUPPORTED_10baseT_Half |
9705 SUPPORTED_10baseT_Full)))) {
de6eae1f
YR		 9706 an_10_100_val |= (1<<5);
9707 autoneg_val |= (1<<9 | 1<<12);
9708 if (phy->req_duplex == DUPLEX_FULL)
9709 an_10_100_val |= (1<<6);
9710 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9711 }
b7737c9b 9712
de6eae1f 9713 /* Only 10/100 are allowed to work in FORCE mode */
0520e63a
YR		 9714 if ((phy->req_line_speed == SPEED_100) &&
9715 (phy->supported &
9716 (SUPPORTED_100baseT_Half |
9717 SUPPORTED_100baseT_Full))) {
de6eae1f
YR		 9718 autoneg_val |= (1<<13);
9719 /* Enabled AUTO-MDIX when autoneg is disabled */
9720 bnx2x_cl45_write(bp, phy,
9721 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9722 (1<<15 | 1<<9 | 7<<0));
521683da
YR		 9723 /* The PHY needs this set even for forced link. */
9724 an_10_100_val |= (1<<8) | (1<<7);
de6eae1f
YR		 9725 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9726 }
0520e63a
YR		 9727 if ((phy->req_line_speed == SPEED_10) &&
9728 (phy->supported &
9729 (SUPPORTED_10baseT_Half |
9730 SUPPORTED_10baseT_Full))) {
de6eae1f
YR		 9731 /* Enabled AUTO-MDIX when autoneg is disabled */
9732 bnx2x_cl45_write(bp, phy,
9733 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9734 (1<<15 | 1<<9 | 7<<0));
9735 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9736 }
b7737c9b 9737
de6eae1f
YR		 9738 bnx2x_cl45_write(bp, phy,
9739 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9740 an_10_100_val);
b7737c9b 9741
de6eae1f
YR		 9742 if (phy->req_duplex == DUPLEX_FULL)
9743 autoneg_val |= (1<<8);
b7737c9b 9744
0f6bb03d
YR		 9745 /* Always write this if this is not 84833/4.
9746 * For 84833/4, write it only when it's a forced speed.
fd38f73e 9747 */
0f6bb03d
YR		 9748 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9749 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
503976e9 9750 ((autoneg_val & (1<<12)) == 0))
fd38f73e 9751 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 9752 MDIO_AN_DEVAD,
9753 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
b7737c9b 9754
de6eae1f
YR		 9755 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9756 (phy->speed_cap_mask &
9757 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9758 (phy->req_line_speed == SPEED_10000)) {
9045f6b4
YR		 9759 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9760 /* Restart autoneg for 10G*/
de6eae1f 9761
503976e9
YR		 9762 bnx2x_cl45_read_or_write(
9763 bp, phy,
9764 MDIO_AN_DEVAD,
9765 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9766 0x1000);
521683da
YR		 9767 bnx2x_cl45_write(bp, phy,
9768 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9769 0x3200);
fd38f73e 9770 } else
de6eae1f
YR		 9771 bnx2x_cl45_write(bp, phy,
9772 MDIO_AN_DEVAD,
9773 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9774 1);
fd38f73e 9775
de6eae1f 9776 return 0;
b7737c9b
YR		 9777}
9778
fcf5b650
YR		 9779static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9780 struct link_params *params,
9781 struct link_vars *vars)
ea4e040a
YR		 9782{
9783 struct bnx2x *bp = params->bp;
de6eae1f
YR		 9784 /* Restore normal power mode*/
9785 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 9786 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 9787
de6eae1f
YR		 9788 /* HW reset */
9789 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 9790 bnx2x_wait_reset_complete(bp, phy, params);
ab6ad5a4 9791
de6eae1f
YR		 9792 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9793 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9794}
ea4e040a 9795
521683da
YR		 9796#define PHY84833_CMDHDLR_WAIT 300
9797#define PHY84833_CMDHDLR_MAX_ARGS 5
9798static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
503976e9
YR		 9799 struct link_params *params, u16 fw_cmd,
9800 u16 cmd_args[], int argc)
bac27bd9 9801{
c8c60d88 9802 int idx;
bac27bd9 9803 u16 val;
bac27bd9 9804 struct bnx2x *bp = params->bp;
bac27bd9
YR		 9805 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9806 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9807 MDIO_84833_CMD_HDLR_STATUS,
9808 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9809 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
bac27bd9 9810 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9811 MDIO_84833_CMD_HDLR_STATUS, &val);
9812 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
bac27bd9 9813 break;
503976e9 9814 usleep_range(1000, 2000);
bac27bd9 9815 }
521683da
YR		 9816 if (idx >= PHY84833_CMDHDLR_WAIT) {
9817 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
bac27bd9
YR		 9818 return -EINVAL;
9819 }
9820
521683da 9821 /* Prepare argument(s) and issue command */
c8c60d88 9822 for (idx = 0; idx < argc; idx++) {
521683da
YR		 9823 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9824 MDIO_84833_CMD_HDLR_DATA1 + idx,
9825 cmd_args[idx]);
9826 }
bac27bd9 9827 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9828 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9829 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
bac27bd9 9830 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9831 MDIO_84833_CMD_HDLR_STATUS, &val);
9832 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9833 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
bac27bd9 9834 break;
503976e9 9835 usleep_range(1000, 2000);
bac27bd9 9836 }
521683da
YR		 9837 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9838 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9839 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
bac27bd9
YR		 9840 return -EINVAL;
9841 }
521683da 9842 /* Gather returning data */
c8c60d88 9843 for (idx = 0; idx < argc; idx++) {
521683da
YR		 9844 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9845 MDIO_84833_CMD_HDLR_DATA1 + idx,
9846 &cmd_args[idx]);
9847 }
bac27bd9 9848 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
521683da
YR		 9849 MDIO_84833_CMD_HDLR_STATUS,
9850 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
bac27bd9
YR		 9851 return 0;
9852}
9853
521683da
YR		 9854static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9855 struct link_params *params,
9856 struct link_vars *vars)
9857{
9858 u32 pair_swap;
9859 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9860 int status;
9861 struct bnx2x *bp = params->bp;
9862
9863 /* Check for configuration. */
9864 pair_swap = REG_RD(bp, params->shmem_base +
9865 offsetof(struct shmem_region,
9866 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9867 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9868
9869 if (pair_swap == 0)
9870 return 0;
9871
9872 /* Only the second argument is used for this command */
9873 data[1] = (u16)pair_swap;
9874
9875 status = bnx2x_84833_cmd_hdlr(phy, params,
c8c60d88 9876 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
521683da
YR		 9877 if (status == 0)
9878 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9879
9880 return status;
9881}
9882
985848f8
YR		 9883static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9884 u32 shmem_base_path[],
9885 u32 chip_id)
0d40f0d4
YR		 9886{
9887 u32 reset_pin[2];
9888 u32 idx;
9889 u8 reset_gpios;
9890 if (CHIP_IS_E3(bp)) {
9891 /* Assume that these will be GPIOs, not EPIOs. */
9892 for (idx = 0; idx < 2; idx++) {
9893 /* Map config param to register bit. */
9894 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9895 offsetof(struct shmem_region,
9896 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9897 reset_pin[idx] = (reset_pin[idx] &
9898 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9899 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9900 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9901 reset_pin[idx] = (1 << reset_pin[idx]);
9902 }
9903 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9904 } else {
9905 /* E2, look from diff place of shmem. */
9906 for (idx = 0; idx < 2; idx++) {
9907 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9908 offsetof(struct shmem_region,
9909 dev_info.port_hw_config[0].default_cfg));
9910 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9911 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9912 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9913 reset_pin[idx] = (1 << reset_pin[idx]);
9914 }
9915 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9916 }
9917
985848f8
YR		 9918 return reset_gpios;
9919}
9920
9921static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9922 struct link_params *params)
9923{
9924 struct bnx2x *bp = params->bp;
9925 u8 reset_gpios;
9926 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9927 offsetof(struct shmem2_region,
9928 other_shmem_base_addr));
9929
9930 u32 shmem_base_path[2];
99bf7f34
YR		 9931
9932 /* Work around for 84833 LED failure inside RESET status */
9933 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9934 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9935 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9936 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9937 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9938 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9939
985848f8
YR		 9940 shmem_base_path[0] = params->shmem_base;
9941 shmem_base_path[1] = other_shmem_base_addr;
9942
9943 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9944 params->chip_id);
9945
9946 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9947 udelay(10);
9948 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9949 reset_gpios);
9950
9951 return 0;
9952}
9953
c8c60d88
YM		 9954static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9955 struct link_params *params,
9956 struct link_vars *vars)
9957{
9958 int rc;
9959 struct bnx2x *bp = params->bp;
9960 u16 cmd_args = 0;
9961
9962 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
9963
c8c60d88
YM		 9964 /* Prevent Phy from working in EEE and advertising it */
9965 rc = bnx2x_84833_cmd_hdlr(phy, params,
9966 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
d231023e 9967 if (rc) {
c8c60d88
YM		 9968 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
9969 return rc;
9970 }
9971
ec4010ec 9972 return bnx2x_eee_disable(phy, params, vars);
c8c60d88
YM		 9973}
9974
9975static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
9976 struct link_params *params,
9977 struct link_vars *vars)
9978{
9979 int rc;
9980 struct bnx2x *bp = params->bp;
9981 u16 cmd_args = 1;
9982
c8c60d88
YM		 9983 rc = bnx2x_84833_cmd_hdlr(phy, params,
9984 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
d231023e 9985 if (rc) {
c8c60d88
YM		 9986 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
9987 return rc;
9988 }
9989
ec4010ec 9990 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
c8c60d88
YM		 9991}
9992
a89a1d4a 9993#define PHY84833_CONSTANT_LATENCY 1193
fcf5b650
YR		 9994static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9995 struct link_params *params,
9996 struct link_vars *vars)
de6eae1f
YR		 9997{
9998 struct bnx2x *bp = params->bp;
6a71bbe0 9999 u8 port, initialize = 1;
bac27bd9 10000 u16 val;
503976e9 10001 u32 actual_phy_selection;
521683da 10002 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
fcf5b650 10003 int rc = 0;
7f02c4ad 10004
503976e9 10005 usleep_range(1000, 2000);
bac27bd9 10006
5481388b 10007 if (!(CHIP_IS_E1x(bp)))
6a71bbe0
YR		 10008 port = BP_PATH(bp);
10009 else
10010 port = params->port;
bac27bd9
YR		 10011
10012 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10013 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10014 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10015 port);
10016 } else {
985848f8 10017 /* MDIO reset */
bac27bd9
YR		 10018 bnx2x_cl45_write(bp, phy,
10019 MDIO_PMA_DEVAD,
10020 MDIO_PMA_REG_CTRL, 0x8000);
521683da
YR		 10021 }
10022
10023 bnx2x_wait_reset_complete(bp, phy, params);
10024
10025 /* Wait for GPHY to come out of reset */
10026 msleep(50);
0f6bb03d
YR		 10027 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10028 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
8f73f0b9 10029 /* BCM84823 requires that XGXS links up first @ 10G for normal
521683da
YR		 10030 * behavior.
10031 */
10032 u16 temp;
10033 temp = vars->line_speed;
10034 vars->line_speed = SPEED_10000;
10035 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10036 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10037 vars->line_speed = temp;
10038 }
a22f0788
YR		 10039
10040 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
bac27bd9 10041 MDIO_CTL_REG_84823_MEDIA, &val);
a22f0788
YR		 10042 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10043 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10044 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10045 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10046 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
0d40f0d4
YR		 10047
10048 if (CHIP_IS_E3(bp)) {
10049 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10050 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10051 } else {
10052 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10053 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10054 }
a22f0788
YR		 10055
10056 actual_phy_selection = bnx2x_phy_selection(params);
10057
10058 switch (actual_phy_selection) {
10059 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
25985edc 10060 /* Do nothing. Essentially this is like the priority copper */
a22f0788
YR		 10061 break;
10062 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10063 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10064 break;
10065 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10066 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10067 break;
10068 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10069 /* Do nothing here. The first PHY won't be initialized at all */
10070 break;
10071 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10072 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10073 initialize = 0;
10074 break;
10075 }
10076 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10077 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10078
10079 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
bac27bd9 10080 MDIO_CTL_REG_84823_MEDIA, val);
a22f0788
YR		 10081 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10082 params->multi_phy_config, val);
10083
0f6bb03d
YR		 10084 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10085 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11b2ec6b 10086 bnx2x_84833_pair_swap_cfg(phy, params, vars);
a89a1d4a 10087
096b9527
YR		 10088 /* Keep AutogrEEEn disabled. */
10089 cmd_args[0] = 0x0;
11b2ec6b
YR		 10090 cmd_args[1] = 0x0;
10091 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10092 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10093 rc = bnx2x_84833_cmd_hdlr(phy, params,
c8c60d88
YM		 10094 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10095 PHY84833_CMDHDLR_MAX_ARGS);
d231023e 10096 if (rc)
11b2ec6b
YR		 10097 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10098 }
a22f0788
YR		 10099 if (initialize)
10100 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10101 else
11b2ec6b 10102 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
a89a1d4a
YR		 10103 /* 84833 PHY has a better feature and doesn't need to support this. */
10104 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
503976e9 10105 u32 cms_enable = REG_RD(bp, params->shmem_base +
1bef68e3
YR		 10106 offsetof(struct shmem_region,
10107 dev_info.port_hw_config[params->port].default_cfg)) &
10108 PORT_HW_CFG_ENABLE_CMS_MASK;
10109
a89a1d4a
YR		 10110 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10111 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10112 if (cms_enable)
10113 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10114 else
10115 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10116 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10117 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10118 }
1bef68e3 10119
c8c60d88
YM		 10120 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10121 MDIO_84833_TOP_CFG_FW_REV, &val);
10122
10123 /* Configure EEE support */
f6b6eb69
YM		 10124 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10125 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10126 bnx2x_eee_has_cap(params)) {
ec4010ec 10127 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
d231023e 10128 if (rc) {
c8c60d88
YM		 10129 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10130 bnx2x_8483x_disable_eee(phy, params, vars);
10131 return rc;
10132 }
10133
fd5dfca7 10134 if ((phy->req_duplex == DUPLEX_FULL) &&
c8c60d88
YM		 10135 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10136 (bnx2x_eee_calc_timer(params) ||
10137 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10138 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10139 else
10140 rc = bnx2x_8483x_disable_eee(phy, params, vars);
d231023e 10141 if (rc) {
efc7ce03 10142 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
c8c60d88
YM		 10143 return rc;
10144 }
10145 } else {
c8c60d88
YM		 10146 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10147 }
10148
0f6bb03d
YR		 10149 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10150 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11b2ec6b 10151 /* Bring PHY out of super isolate mode as the final step. */
503976e9
YR		 10152 bnx2x_cl45_read_and_write(bp, phy,
10153 MDIO_CTL_DEVAD,
10154 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10155 (u16)~MDIO_84833_SUPER_ISOLATE);
11b2ec6b 10156 }
a22f0788 10157 return rc;
de6eae1f 10158}
ea4e040a 10159
de6eae1f 10160static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
cd88ccee
YR		 10161 struct link_params *params,
10162 struct link_vars *vars)
de6eae1f
YR		 10163{
10164 struct bnx2x *bp = params->bp;
bac27bd9 10165 u16 val, val1, val2;
de6eae1f 10166 u8 link_up = 0;
ea4e040a 10167
c87bca1e 10168
de6eae1f
YR		 10169 /* Check 10G-BaseT link status */
10170 /* Check PMD signal ok */
10171 bnx2x_cl45_read(bp, phy,
10172 MDIO_AN_DEVAD, 0xFFFA, &val1);
10173 bnx2x_cl45_read(bp, phy,
bac27bd9 10174 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
de6eae1f
YR		 10175 &val2);
10176 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
ea4e040a 10177
de6eae1f
YR		 10178 /* Check link 10G */
10179 if (val2 & (1<<11)) {
ea4e040a 10180 vars->line_speed = SPEED_10000;
791f18c0 10181 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 10182 link_up = 1;
10183 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10184 } else { /* Check Legacy speed link */
10185 u16 legacy_status, legacy_speed;
ea4e040a 10186
de6eae1f
YR		 10187 /* Enable expansion register 0x42 (Operation mode status) */
10188 bnx2x_cl45_write(bp, phy,
10189 MDIO_AN_DEVAD,
10190 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
ea4e040a 10191
de6eae1f
YR		 10192 /* Get legacy speed operation status */
10193 bnx2x_cl45_read(bp, phy,
10194 MDIO_AN_DEVAD,
10195 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10196 &legacy_status);
ea4e040a 10197
94f05b0f
JP		 10198 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10199 legacy_status);
de6eae1f 10200 link_up = ((legacy_status & (1<<11)) == (1<<11));
14400901
YM		 10201 legacy_speed = (legacy_status & (3<<9));
10202 if (legacy_speed == (0<<9))
10203 vars->line_speed = SPEED_10;
10204 else if (legacy_speed == (1<<9))
10205 vars->line_speed = SPEED_100;
10206 else if (legacy_speed == (2<<9))
10207 vars->line_speed = SPEED_1000;
10208 else { /* Should not happen: Treat as link down */
10209 vars->line_speed = 0;
10210 link_up = 0;
10211 }
ea4e040a 10212
14400901 10213 if (link_up) {
de6eae1f
YR		 10214 if (legacy_status & (1<<8))
10215 vars->duplex = DUPLEX_FULL;
10216 else
10217 vars->duplex = DUPLEX_HALF;
ea4e040a 10218
94f05b0f
JP		 10219 DP(NETIF_MSG_LINK,
10220 "Link is up in %dMbps, is_duplex_full= %d\n",
10221 vars->line_speed,
10222 (vars->duplex == DUPLEX_FULL));
de6eae1f
YR		 10223 /* Check legacy speed AN resolution */
10224 bnx2x_cl45_read(bp, phy,
10225 MDIO_AN_DEVAD,
10226 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10227 &val);
10228 if (val & (1<<5))
10229 vars->link_status |=
10230 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10231 bnx2x_cl45_read(bp, phy,
10232 MDIO_AN_DEVAD,
10233 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10234 &val);
10235 if ((val & (1<<0)) == 0)
10236 vars->link_status |=
10237 LINK_STATUS_PARALLEL_DETECTION_USED;
ea4e040a 10238 }
ea4e040a 10239 }
de6eae1f 10240 if (link_up) {
d231023e 10241 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
de6eae1f
YR		 10242 vars->line_speed);
10243 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9e7e8399
MY		 10244
10245 /* Read LP advertised speeds */
10246 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10247 MDIO_AN_REG_CL37_FC_LP, &val);
10248 if (val & (1<<5))
10249 vars->link_status |=
10250 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10251 if (val & (1<<6))
10252 vars->link_status |=
10253 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10254 if (val & (1<<7))
10255 vars->link_status |=
10256 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10257 if (val & (1<<8))
10258 vars->link_status |=
10259 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10260 if (val & (1<<9))
10261 vars->link_status |=
10262 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10263
10264 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10265 MDIO_AN_REG_1000T_STATUS, &val);
10266
10267 if (val & (1<<10))
10268 vars->link_status |=
10269 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10270 if (val & (1<<11))
10271 vars->link_status |=
10272 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10273
10274 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10275 MDIO_AN_REG_MASTER_STATUS, &val);
10276
10277 if (val & (1<<11))
10278 vars->link_status |=
10279 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
c8c60d88
YM		 10280
10281 /* Determine if EEE was negotiated */
ec4010ec
YM		 10282 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10283 bnx2x_eee_an_resolve(phy, params, vars);
de6eae1f 10284 }
589abe3a 10285
de6eae1f 10286 return link_up;
b7737c9b
YR		 10287}
10288
fcf5b650 10289static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
b7737c9b 10290{
fcf5b650 10291 int status = 0;
de6eae1f
YR		 10292 u32 spirom_ver;
10293 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10294 status = bnx2x_format_ver(spirom_ver, str, len);
10295 return status;
b7737c9b 10296}
de6eae1f
YR		 10297
10298static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10299 struct link_params *params)
b7737c9b 10300{
de6eae1f 10301 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 10302 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
de6eae1f 10303 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 10304 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
b7737c9b 10305}
de6eae1f 10306
b7737c9b
YR		 10307static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10308 struct link_params *params)
10309{
10310 bnx2x_cl45_write(params->bp, phy,
10311 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10312 bnx2x_cl45_write(params->bp, phy,
10313 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10314}
10315
10316static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10317 struct link_params *params)
10318{
10319 struct bnx2x *bp = params->bp;
6a71bbe0 10320 u8 port;
0d40f0d4 10321 u16 val16;
bac27bd9 10322
f93fb016 10323 if (!(CHIP_IS_E1x(bp)))
6a71bbe0
YR		 10324 port = BP_PATH(bp);
10325 else
10326 port = params->port;
bac27bd9
YR		 10327
10328 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10329 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10330 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10331 port);
10332 } else {
0d40f0d4
YR		 10333 bnx2x_cl45_read(bp, phy,
10334 MDIO_CTL_DEVAD,
11b2ec6b
YR		 10335 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10336 val16 |= MDIO_84833_SUPER_ISOLATE;
fd38f73e 10337 bnx2x_cl45_write(bp, phy,
11b2ec6b
YR		 10338 MDIO_CTL_DEVAD,
10339 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
bac27bd9 10340 }
b7737c9b
YR		 10341}
10342
7f02c4ad
YR		 10343static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10344 struct link_params *params, u8 mode)
10345{
10346 struct bnx2x *bp = params->bp;
10347 u16 val;
bac27bd9
YR		 10348 u8 port;
10349
f93fb016 10350 if (!(CHIP_IS_E1x(bp)))
bac27bd9
YR		 10351 port = BP_PATH(bp);
10352 else
10353 port = params->port;
7f02c4ad
YR		 10354
10355 switch (mode) {
10356 case LED_MODE_OFF:
10357
bac27bd9 10358 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
7f02c4ad
YR		 10359
10360 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10361 SHARED_HW_CFG_LED_EXTPHY1) {
10362
10363 /* Set LED masks */
10364 bnx2x_cl45_write(bp, phy,
10365 MDIO_PMA_DEVAD,
10366 MDIO_PMA_REG_8481_LED1_MASK,
10367 0x0);
10368
10369 bnx2x_cl45_write(bp, phy,
10370 MDIO_PMA_DEVAD,
10371 MDIO_PMA_REG_8481_LED2_MASK,
10372 0x0);
10373
10374 bnx2x_cl45_write(bp, phy,
10375 MDIO_PMA_DEVAD,
10376 MDIO_PMA_REG_8481_LED3_MASK,
10377 0x0);
10378
10379 bnx2x_cl45_write(bp, phy,
10380 MDIO_PMA_DEVAD,
10381 MDIO_PMA_REG_8481_LED5_MASK,
10382 0x0);
10383
10384 } else {
10385 bnx2x_cl45_write(bp, phy,
10386 MDIO_PMA_DEVAD,
10387 MDIO_PMA_REG_8481_LED1_MASK,
10388 0x0);
10389 }
10390 break;
10391 case LED_MODE_FRONT_PANEL_OFF:
10392
10393 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
bac27bd9 10394 port);
7f02c4ad
YR		 10395
10396 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10397 SHARED_HW_CFG_LED_EXTPHY1) {
10398
10399 /* Set LED masks */
10400 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10401 MDIO_PMA_DEVAD,
10402 MDIO_PMA_REG_8481_LED1_MASK,
10403 0x0);
7f02c4ad
YR		 10404
10405 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10406 MDIO_PMA_DEVAD,
10407 MDIO_PMA_REG_8481_LED2_MASK,
10408 0x0);
7f02c4ad
YR		 10409
10410 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10411 MDIO_PMA_DEVAD,
10412 MDIO_PMA_REG_8481_LED3_MASK,
10413 0x0);
7f02c4ad
YR		 10414
10415 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10416 MDIO_PMA_DEVAD,
10417 MDIO_PMA_REG_8481_LED5_MASK,
10418 0x20);
7f02c4ad
YR		 10419
10420 } else {
10421 bnx2x_cl45_write(bp, phy,
10422 MDIO_PMA_DEVAD,
10423 MDIO_PMA_REG_8481_LED1_MASK,
10424 0x0);
8ce76845
YR		 10425 if (phy->type ==
10426 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10427 /* Disable MI_INT interrupt before setting LED4
10428 * source to constant off.
10429 */
10430 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10431 params->port*4) &
10432 NIG_MASK_MI_INT) {
10433 params->link_flags |=
10434 LINK_FLAGS_INT_DISABLED;
10435
10436 bnx2x_bits_dis(
10437 bp,
10438 NIG_REG_MASK_INTERRUPT_PORT0 +
10439 params->port*4,
10440 NIG_MASK_MI_INT);
10441 }
10442 bnx2x_cl45_write(bp, phy,
10443 MDIO_PMA_DEVAD,
10444 MDIO_PMA_REG_8481_SIGNAL_MASK,
10445 0x0);
10446 }
7f02c4ad
YR		 10447 }
10448 break;
10449 case LED_MODE_ON:
10450
bac27bd9 10451 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
7f02c4ad
YR		 10452
10453 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10454 SHARED_HW_CFG_LED_EXTPHY1) {
10455 /* Set control reg */
10456 bnx2x_cl45_read(bp, phy,
10457 MDIO_PMA_DEVAD,
10458 MDIO_PMA_REG_8481_LINK_SIGNAL,
10459 &val);
10460 val &= 0x8000;
10461 val |= 0x2492;
10462
10463 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10464 MDIO_PMA_DEVAD,
10465 MDIO_PMA_REG_8481_LINK_SIGNAL,
10466 val);
7f02c4ad
YR		 10467
10468 /* Set LED masks */
10469 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10470 MDIO_PMA_DEVAD,
10471 MDIO_PMA_REG_8481_LED1_MASK,
10472 0x0);
7f02c4ad
YR		 10473
10474 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10475 MDIO_PMA_DEVAD,
10476 MDIO_PMA_REG_8481_LED2_MASK,
10477 0x20);
7f02c4ad
YR		 10478
10479 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10480 MDIO_PMA_DEVAD,
10481 MDIO_PMA_REG_8481_LED3_MASK,
10482 0x20);
7f02c4ad
YR		 10483
10484 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10485 MDIO_PMA_DEVAD,
10486 MDIO_PMA_REG_8481_LED5_MASK,
10487 0x0);
7f02c4ad
YR		 10488 } else {
10489 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10490 MDIO_PMA_DEVAD,
10491 MDIO_PMA_REG_8481_LED1_MASK,
10492 0x20);
8ce76845
YR		 10493 if (phy->type ==
10494 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10495 /* Disable MI_INT interrupt before setting LED4
10496 * source to constant on.
10497 */
10498 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10499 params->port*4) &
10500 NIG_MASK_MI_INT) {
10501 params->link_flags |=
10502 LINK_FLAGS_INT_DISABLED;
10503
10504 bnx2x_bits_dis(
10505 bp,
10506 NIG_REG_MASK_INTERRUPT_PORT0 +
10507 params->port*4,
10508 NIG_MASK_MI_INT);
10509 }
10510 bnx2x_cl45_write(bp, phy,
10511 MDIO_PMA_DEVAD,
10512 MDIO_PMA_REG_8481_SIGNAL_MASK,
10513 0x20);
10514 }
7f02c4ad
YR		 10515 }
10516 break;
10517
10518 case LED_MODE_OPER:
10519
bac27bd9 10520 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
7f02c4ad
YR		 10521
10522 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10523 SHARED_HW_CFG_LED_EXTPHY1) {
10524
10525 /* Set control reg */
10526 bnx2x_cl45_read(bp, phy,
10527 MDIO_PMA_DEVAD,
10528 MDIO_PMA_REG_8481_LINK_SIGNAL,
10529 &val);
10530
10531 if (!((val &
cd88ccee
YR		 10532 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10533 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
2cf7acf9 10534 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
7f02c4ad
YR		 10535 bnx2x_cl45_write(bp, phy,
10536 MDIO_PMA_DEVAD,
10537 MDIO_PMA_REG_8481_LINK_SIGNAL,
10538 0xa492);
10539 }
10540
10541 /* Set LED masks */
10542 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10543 MDIO_PMA_DEVAD,
10544 MDIO_PMA_REG_8481_LED1_MASK,
10545 0x10);
7f02c4ad
YR		 10546
10547 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10548 MDIO_PMA_DEVAD,
10549 MDIO_PMA_REG_8481_LED2_MASK,
10550 0x80);
7f02c4ad
YR		 10551
10552 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10553 MDIO_PMA_DEVAD,
10554 MDIO_PMA_REG_8481_LED3_MASK,
10555 0x98);
7f02c4ad
YR		 10556
10557 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 10558 MDIO_PMA_DEVAD,
10559 MDIO_PMA_REG_8481_LED5_MASK,
10560 0x40);
7f02c4ad
YR		 10561
10562 } else {
10563 bnx2x_cl45_write(bp, phy,
10564 MDIO_PMA_DEVAD,
10565 MDIO_PMA_REG_8481_LED1_MASK,
10566 0x80);
53eda06d
YR		 10567
10568 /* Tell LED3 to blink on source */
10569 bnx2x_cl45_read(bp, phy,
10570 MDIO_PMA_DEVAD,
10571 MDIO_PMA_REG_8481_LINK_SIGNAL,
10572 &val);
10573 val &= ~(7<<6);
10574 val |= (1<<6); /* A83B[8:6]= 1 */
10575 bnx2x_cl45_write(bp, phy,
10576 MDIO_PMA_DEVAD,
10577 MDIO_PMA_REG_8481_LINK_SIGNAL,
10578 val);
8ce76845
YR		 10579 if (phy->type ==
10580 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10581 /* Restore LED4 source to external link,
10582 * and re-enable interrupts.
10583 */
10584 bnx2x_cl45_write(bp, phy,
10585 MDIO_PMA_DEVAD,
10586 MDIO_PMA_REG_8481_SIGNAL_MASK,
10587 0x40);
10588 if (params->link_flags &
10589 LINK_FLAGS_INT_DISABLED) {
10590 bnx2x_link_int_enable(params);
10591 params->link_flags &=
10592 ~LINK_FLAGS_INT_DISABLED;
10593 }
10594 }
7f02c4ad
YR		 10595 }
10596 break;
10597 }
0d40f0d4 10598
8f73f0b9 10599 /* This is a workaround for E3+84833 until autoneg
0d40f0d4
YR		 10600 * restart is fixed in f/w
10601 */
10602 if (CHIP_IS_E3(bp)) {
10603 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10604 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10605 }
7f02c4ad 10606}
0d40f0d4 10607
6583e33b 10608/******************************************************************/
52c4d6c4 10609/* 54618SE PHY SECTION */
6583e33b 10610/******************************************************************/
5c107fda
YR		 10611static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10612 struct link_params *params,
10613 u32 action)
10614{
10615 struct bnx2x *bp = params->bp;
10616 u16 temp;
10617 switch (action) {
10618 case PHY_INIT:
10619 /* Configure LED4: set to INTR (0x6). */
10620 /* Accessing shadow register 0xe. */
10621 bnx2x_cl22_write(bp, phy,
10622 MDIO_REG_GPHY_SHADOW,
10623 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10624 bnx2x_cl22_read(bp, phy,
10625 MDIO_REG_GPHY_SHADOW,
10626 &temp);
10627 temp &= ~(0xf << 4);
10628 temp |= (0x6 << 4);
10629 bnx2x_cl22_write(bp, phy,
10630 MDIO_REG_GPHY_SHADOW,
10631 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10632 /* Configure INTR based on link status change. */
10633 bnx2x_cl22_write(bp, phy,
10634 MDIO_REG_INTR_MASK,
10635 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10636 break;
10637 }
10638}
10639
52c4d6c4 10640static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
6583e33b
YR		 10641 struct link_params *params,
10642 struct link_vars *vars)
10643{
10644 struct bnx2x *bp = params->bp;
10645 u8 port;
10646 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10647 u32 cfg_pin;
10648
52c4d6c4 10649 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
d231023e 10650 usleep_range(1000, 2000);
6583e33b 10651
8f73f0b9 10652 /* This works with E3 only, no need to check the chip
2f751a80
YR		 10653 * before determining the port.
10654 */
6583e33b
YR		 10655 port = params->port;
10656
10657 cfg_pin = (REG_RD(bp, params->shmem_base +
10658 offsetof(struct shmem_region,
10659 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10660 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10661 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10662
10663 /* Drive pin high to bring the GPHY out of reset. */
10664 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10665
10666 /* wait for GPHY to reset */
10667 msleep(50);
10668
10669 /* reset phy */
10670 bnx2x_cl22_write(bp, phy,
10671 MDIO_PMA_REG_CTRL, 0x8000);
10672 bnx2x_wait_reset_complete(bp, phy, params);
10673
8f73f0b9 10674 /* Wait for GPHY to reset */
6583e33b
YR		 10675 msleep(50);
10676
6583e33b 10677
5c107fda 10678 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
6583e33b
YR		 10679 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10680 bnx2x_cl22_write(bp, phy,
10681 MDIO_REG_GPHY_SHADOW,
10682 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10683 bnx2x_cl22_read(bp, phy,
10684 MDIO_REG_GPHY_SHADOW,
10685 &temp);
10686 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10687 bnx2x_cl22_write(bp, phy,
10688 MDIO_REG_GPHY_SHADOW,
10689 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10690
10691 /* Set up fc */
10692 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10693 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10694 fc_val = 0;
10695 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10696 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10697 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10698
10699 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10700 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10701 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10702
d231023e 10703 /* Read all advertisement */
6583e33b
YR		 10704 bnx2x_cl22_read(bp, phy,
10705 0x09,
10706 &an_1000_val);
10707
10708 bnx2x_cl22_read(bp, phy,
10709 0x04,
10710 &an_10_100_val);
10711
10712 bnx2x_cl22_read(bp, phy,
10713 MDIO_PMA_REG_CTRL,
10714 &autoneg_val);
10715
10716 /* Disable forced speed */
10717 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10718 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10719 (1<<11));
10720
10721 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10722 (phy->speed_cap_mask &
10723 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10724 (phy->req_line_speed == SPEED_1000)) {
10725 an_1000_val |= (1<<8);
10726 autoneg_val |= (1<<9 | 1<<12);
10727 if (phy->req_duplex == DUPLEX_FULL)
10728 an_1000_val |= (1<<9);
10729 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10730 } else
10731 an_1000_val &= ~((1<<8) | (1<<9));
10732
10733 bnx2x_cl22_write(bp, phy,
10734 0x09,
10735 an_1000_val);
10736 bnx2x_cl22_read(bp, phy,
10737 0x09,
10738 &an_1000_val);
10739
d231023e 10740 /* Set 100 speed advertisement */
6583e33b
YR		 10741 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10742 (phy->speed_cap_mask &
10743 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10744 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10745 an_10_100_val |= (1<<7);
10746 /* Enable autoneg and restart autoneg for legacy speeds */
10747 autoneg_val |= (1<<9 | 1<<12);
10748
10749 if (phy->req_duplex == DUPLEX_FULL)
10750 an_10_100_val |= (1<<8);
10751 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10752 }
10753
d231023e 10754 /* Set 10 speed advertisement */
6583e33b
YR		 10755 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10756 (phy->speed_cap_mask &
10757 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10758 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10759 an_10_100_val |= (1<<5);
10760 autoneg_val |= (1<<9 | 1<<12);
10761 if (phy->req_duplex == DUPLEX_FULL)
10762 an_10_100_val |= (1<<6);
10763 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10764 }
10765
10766 /* Only 10/100 are allowed to work in FORCE mode */
10767 if (phy->req_line_speed == SPEED_100) {
10768 autoneg_val |= (1<<13);
10769 /* Enabled AUTO-MDIX when autoneg is disabled */
10770 bnx2x_cl22_write(bp, phy,
10771 0x18,
10772 (1<<15 | 1<<9 | 7<<0));
10773 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10774 }
10775 if (phy->req_line_speed == SPEED_10) {
10776 /* Enabled AUTO-MDIX when autoneg is disabled */
10777 bnx2x_cl22_write(bp, phy,
10778 0x18,
10779 (1<<15 | 1<<9 | 7<<0));
10780 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10781 }
10782
26964bb7
YM		 10783 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10784 int rc;
10785
10786 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10787 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10788 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10789 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10790 temp &= 0xfffe;
10791 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10792
10793 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10794 if (rc) {
10795 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10796 bnx2x_eee_disable(phy, params, vars);
10797 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10798 (phy->req_duplex == DUPLEX_FULL) &&
10799 (bnx2x_eee_calc_timer(params) ||
10800 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10801 /* Need to advertise EEE only when requested,
10802 * and either no LPI assertion was requested,
10803 * or it was requested and a valid timer was set.
10804 * Also notice full duplex is required for EEE.
10805 */
10806 bnx2x_eee_advertise(phy, params, vars,
10807 SHMEM_EEE_1G_ADV);
a89a1d4a 10808 } else {
26964bb7
YM		 10809 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10810 bnx2x_eee_disable(phy, params, vars);
10811 }
10812 } else {
10813 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10814 SHMEM_EEE_SUPPORTED_SHIFT;
10815
10816 if (phy->flags & FLAGS_EEE) {
10817 /* Handle legacy auto-grEEEn */
10818 if (params->feature_config_flags &
10819 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10820 temp = 6;
10821 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10822 } else {
10823 temp = 0;
10824 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10825 }
10826 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10827 MDIO_AN_REG_EEE_ADV, temp);
a89a1d4a 10828 }
a89a1d4a
YR		 10829 }
10830
6583e33b
YR		 10831 bnx2x_cl22_write(bp, phy,
10832 0x04,
10833 an_10_100_val | fc_val);
10834
10835 if (phy->req_duplex == DUPLEX_FULL)
10836 autoneg_val |= (1<<8);
10837
10838 bnx2x_cl22_write(bp, phy,
10839 MDIO_PMA_REG_CTRL, autoneg_val);
10840
10841 return 0;
10842}
10843
1d125bd5
YR		 10844
10845static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10846 struct link_params *params, u8 mode)
10847{
10848 struct bnx2x *bp = params->bp;
10849 u16 temp;
10850
10851 bnx2x_cl22_write(bp, phy,
10852 MDIO_REG_GPHY_SHADOW,
10853 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10854 bnx2x_cl22_read(bp, phy,
10855 MDIO_REG_GPHY_SHADOW,
10856 &temp);
10857 temp &= 0xff00;
10858
10859 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10860 switch (mode) {
10861 case LED_MODE_FRONT_PANEL_OFF:
10862 case LED_MODE_OFF:
10863 temp |= 0x00ee;
10864 break;
10865 case LED_MODE_OPER:
10866 temp |= 0x0001;
10867 break;
10868 case LED_MODE_ON:
10869 temp |= 0x00ff;
10870 break;
10871 default:
10872 break;
10873 }
10874 bnx2x_cl22_write(bp, phy,
10875 MDIO_REG_GPHY_SHADOW,
10876 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10877 return;
10878}
10879
10880
52c4d6c4
YR		 10881static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10882 struct link_params *params)
6583e33b
YR		 10883{
10884 struct bnx2x *bp = params->bp;
10885 u32 cfg_pin;
10886 u8 port;
10887
8f73f0b9 10888 /* In case of no EPIO routed to reset the GPHY, put it
d2059a06
YR		 10889 * in low power mode.
10890 */
10891 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
8f73f0b9 10892 /* This works with E3 only, no need to check the chip
d2059a06
YR		 10893 * before determining the port.
10894 */
6583e33b
YR		 10895 port = params->port;
10896 cfg_pin = (REG_RD(bp, params->shmem_base +
10897 offsetof(struct shmem_region,
10898 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10899 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10900 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10901
10902 /* Drive pin low to put GPHY in reset. */
10903 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10904}
10905
52c4d6c4
YR		 10906static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10907 struct link_params *params,
10908 struct link_vars *vars)
6583e33b
YR		 10909{
10910 struct bnx2x *bp = params->bp;
10911 u16 val;
10912 u8 link_up = 0;
10913 u16 legacy_status, legacy_speed;
10914
10915 /* Get speed operation status */
10916 bnx2x_cl22_read(bp, phy,
a351d497 10917 MDIO_REG_GPHY_AUX_STATUS,
6583e33b 10918 &legacy_status);
52c4d6c4 10919 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
6583e33b
YR		 10920
10921 /* Read status to clear the PHY interrupt. */
10922 bnx2x_cl22_read(bp, phy,
10923 MDIO_REG_INTR_STATUS,
10924 &val);
10925
10926 link_up = ((legacy_status & (1<<2)) == (1<<2));
10927
10928 if (link_up) {
10929 legacy_speed = (legacy_status & (7<<8));
10930 if (legacy_speed == (7<<8)) {
10931 vars->line_speed = SPEED_1000;
10932 vars->duplex = DUPLEX_FULL;
10933 } else if (legacy_speed == (6<<8)) {
10934 vars->line_speed = SPEED_1000;
10935 vars->duplex = DUPLEX_HALF;
10936 } else if (legacy_speed == (5<<8)) {
10937 vars->line_speed = SPEED_100;
10938 vars->duplex = DUPLEX_FULL;
10939 }
10940 /* Omitting 100Base-T4 for now */
10941 else if (legacy_speed == (3<<8)) {
10942 vars->line_speed = SPEED_100;
10943 vars->duplex = DUPLEX_HALF;
10944 } else if (legacy_speed == (2<<8)) {
10945 vars->line_speed = SPEED_10;
10946 vars->duplex = DUPLEX_FULL;
10947 } else if (legacy_speed == (1<<8)) {
10948 vars->line_speed = SPEED_10;
10949 vars->duplex = DUPLEX_HALF;
10950 } else /* Should not happen */
10951 vars->line_speed = 0;
10952
94f05b0f
JP		 10953 DP(NETIF_MSG_LINK,
10954 "Link is up in %dMbps, is_duplex_full= %d\n",
10955 vars->line_speed,
10956 (vars->duplex == DUPLEX_FULL));
6583e33b
YR		 10957
10958 /* Check legacy speed AN resolution */
10959 bnx2x_cl22_read(bp, phy,
10960 0x01,
10961 &val);
10962 if (val & (1<<5))
10963 vars->link_status |=
10964 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10965 bnx2x_cl22_read(bp, phy,
10966 0x06,
10967 &val);
10968 if ((val & (1<<0)) == 0)
10969 vars->link_status |=
10970 LINK_STATUS_PARALLEL_DETECTION_USED;
10971
52c4d6c4 10972 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
6583e33b 10973 vars->line_speed);
52c4d6c4 10974
6583e33b 10975 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9e7e8399
MY		 10976
10977 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8f73f0b9 10978 /* Report LP advertised speeds */
9e7e8399
MY		 10979 bnx2x_cl22_read(bp, phy, 0x5, &val);
10980
10981 if (val & (1<<5))
10982 vars->link_status |=
10983 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10984 if (val & (1<<6))
10985 vars->link_status |=
10986 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10987 if (val & (1<<7))
10988 vars->link_status |=
10989 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10990 if (val & (1<<8))
10991 vars->link_status |=
10992 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10993 if (val & (1<<9))
10994 vars->link_status |=
10995 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10996
10997 bnx2x_cl22_read(bp, phy, 0xa, &val);
10998 if (val & (1<<10))
10999 vars->link_status |=
11000 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11001 if (val & (1<<11))
11002 vars->link_status |=
11003 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
26964bb7
YM		 11004
11005 if ((phy->flags & FLAGS_EEE) &&
11006 bnx2x_eee_has_cap(params))
11007 bnx2x_eee_an_resolve(phy, params, vars);
9e7e8399 11008 }
6583e33b
YR		 11009 }
11010 return link_up;
11011}
11012
52c4d6c4
YR		 11013static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11014 struct link_params *params)
6583e33b
YR		 11015{
11016 struct bnx2x *bp = params->bp;
11017 u16 val;
11018 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11019
52c4d6c4 11020 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
6583e33b
YR		 11021
11022 /* Enable master/slave manual mmode and set to master */
11023 /* mii write 9 [bits set 11 12] */
11024 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11025
11026 /* forced 1G and disable autoneg */
11027 /* set val [mii read 0] */
11028 /* set val [expr $val & [bits clear 6 12 13]] */
11029 /* set val [expr $val | [bits set 6 8]] */
11030 /* mii write 0 $val */
11031 bnx2x_cl22_read(bp, phy, 0x00, &val);
11032 val &= ~((1<<6) | (1<<12) | (1<<13));
11033 val |= (1<<6) | (1<<8);
11034 bnx2x_cl22_write(bp, phy, 0x00, val);
11035
11036 /* Set external loopback and Tx using 6dB coding */
11037 /* mii write 0x18 7 */
11038 /* set val [mii read 0x18] */
11039 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11040 bnx2x_cl22_write(bp, phy, 0x18, 7);
11041 bnx2x_cl22_read(bp, phy, 0x18, &val);
11042 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11043
11044 /* This register opens the gate for the UMAC despite its name */
11045 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11046
8f73f0b9 11047 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
6583e33b
YR		 11048 * length used by the MAC receive logic to check frames.
11049 */
11050 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11051}
11052
de6eae1f
YR		 11053/******************************************************************/
11054/* SFX7101 PHY SECTION */
11055/******************************************************************/
11056static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11057 struct link_params *params)
b7737c9b
YR		 11058{
11059 struct bnx2x *bp = params->bp;
de6eae1f
YR		 11060 /* SFX7101_XGXS_TEST1 */
11061 bnx2x_cl45_write(bp, phy,
11062 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
589abe3a
EG		 11063}
11064
fcf5b650
YR		 11065static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11066 struct link_params *params,
11067 struct link_vars *vars)
ea4e040a 11068{
de6eae1f 11069 u16 fw_ver1, fw_ver2, val;
ea4e040a 11070 struct bnx2x *bp = params->bp;
de6eae1f 11071 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
ea4e040a 11072
de6eae1f
YR		 11073 /* Restore normal power mode*/
11074 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 11075 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 11076 /* HW reset */
11077 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 11078 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 11079
de6eae1f 11080 bnx2x_cl45_write(bp, phy,
60d2fe03 11081 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
de6eae1f
YR		 11082 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11083 bnx2x_cl45_write(bp, phy,
11084 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
ea4e040a 11085
de6eae1f
YR		 11086 bnx2x_ext_phy_set_pause(params, phy, vars);
11087 /* Restart autoneg */
11088 bnx2x_cl45_read(bp, phy,
11089 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11090 val |= 0x200;
11091 bnx2x_cl45_write(bp, phy,
11092 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
ea4e040a 11093
de6eae1f
YR		 11094 /* Save spirom version */
11095 bnx2x_cl45_read(bp, phy,
11096 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
ea4e040a 11097
de6eae1f
YR		 11098 bnx2x_cl45_read(bp, phy,
11099 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11100 bnx2x_save_spirom_version(bp, params->port,
11101 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11102 return 0;
11103}
ea4e040a 11104
de6eae1f
YR		 11105static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11106 struct link_params *params,
11107 struct link_vars *vars)
57963ed9
YR		 11108{
11109 struct bnx2x *bp = params->bp;
de6eae1f
YR		 11110 u8 link_up;
11111 u16 val1, val2;
11112 bnx2x_cl45_read(bp, phy,
60d2fe03 11113 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
de6eae1f 11114 bnx2x_cl45_read(bp, phy,
60d2fe03 11115 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
de6eae1f
YR		 11116 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11117 val2, val1);
11118 bnx2x_cl45_read(bp, phy,
11119 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11120 bnx2x_cl45_read(bp, phy,
11121 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11122 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11123 val2, val1);
11124 link_up = ((val1 & 4) == 4);
d231023e 11125 /* If link is up print the AN outcome of the SFX7101 PHY */
de6eae1f
YR		 11126 if (link_up) {
11127 bnx2x_cl45_read(bp, phy,
11128 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11129 &val2);
11130 vars->line_speed = SPEED_10000;
791f18c0 11131 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 11132 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11133 val2, (val2 & (1<<14)));
11134 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11135 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9e7e8399 11136
d231023e 11137 /* Read LP advertised speeds */
9e7e8399
MY		 11138 if (val2 & (1<<11))
11139 vars->link_status |=
11140 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
de6eae1f
YR		 11141 }
11142 return link_up;
11143}
6c55c3cd 11144
fcf5b650 11145static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
de6eae1f
YR		 11146{
11147 if (*len < 5)
11148 return -EINVAL;
11149 str[0] = (spirom_ver & 0xFF);
11150 str[1] = (spirom_ver & 0xFF00) >> 8;
11151 str[2] = (spirom_ver & 0xFF0000) >> 16;
11152 str[3] = (spirom_ver & 0xFF000000) >> 24;
11153 str[4] = '\0';
11154 *len -= 5;
57963ed9
YR		 11155 return 0;
11156}
11157
de6eae1f 11158void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
57963ed9 11159{
de6eae1f 11160 u16 val, cnt;
7aa0711f 11161
de6eae1f 11162 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 11163 MDIO_PMA_DEVAD,
11164 MDIO_PMA_REG_7101_RESET, &val);
57963ed9 11165
de6eae1f
YR		 11166 for (cnt = 0; cnt < 10; cnt++) {
11167 msleep(50);
11168 /* Writes a self-clearing reset */
11169 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 11170 MDIO_PMA_DEVAD,
11171 MDIO_PMA_REG_7101_RESET,
11172 (val | (1<<15)));
de6eae1f
YR		 11173 /* Wait for clear */
11174 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 11175 MDIO_PMA_DEVAD,
11176 MDIO_PMA_REG_7101_RESET, &val);
0c786f02 11177
de6eae1f
YR		 11178 if ((val & (1<<15)) == 0)
11179 break;
57963ed9 11180 }
57963ed9 11181}
ea4e040a 11182
de6eae1f
YR		 11183static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11184 struct link_params *params) {
11185 /* Low power mode is controlled by GPIO 2 */
11186 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
cd88ccee 11187 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f
YR		 11188 /* The PHY reset is controlled by GPIO 1 */
11189 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 11190 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f 11191}
ea4e040a 11192
7f02c4ad
YR		 11193static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11194 struct link_params *params, u8 mode)
11195{
11196 u16 val = 0;
11197 struct bnx2x *bp = params->bp;
11198 switch (mode) {
11199 case LED_MODE_FRONT_PANEL_OFF:
11200 case LED_MODE_OFF:
11201 val = 2;
11202 break;
11203 case LED_MODE_ON:
11204 val = 1;
11205 break;
11206 case LED_MODE_OPER:
11207 val = 0;
11208 break;
11209 }
11210 bnx2x_cl45_write(bp, phy,
11211 MDIO_PMA_DEVAD,
11212 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11213 val);
11214}
11215
de6eae1f
YR		 11216/******************************************************************/
11217/* STATIC PHY DECLARATION */
11218/******************************************************************/
ea4e040a 11219
503976e9 11220static const struct bnx2x_phy phy_null = {
de6eae1f
YR		 11221 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11222 .addr = 0,
de6eae1f 11223 .def_md_devad = 0,
9045f6b4 11224 .flags = FLAGS_INIT_XGXS_FIRST,
de6eae1f
YR		 11225 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11226 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11227 .mdio_ctrl = 0,
11228 .supported = 0,
11229 .media_type = ETH_PHY_NOT_PRESENT,
11230 .ver_addr = 0,
cd88ccee
YR		 11231 .req_flow_ctrl = 0,
11232 .req_line_speed = 0,
11233 .speed_cap_mask = 0,
de6eae1f
YR		 11234 .req_duplex = 0,
11235 .rsrv = 0,
11236 .config_init = (config_init_t)NULL,
11237 .read_status = (read_status_t)NULL,
11238 .link_reset = (link_reset_t)NULL,
11239 .config_loopback = (config_loopback_t)NULL,
11240 .format_fw_ver = (format_fw_ver_t)NULL,
11241 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11242 .set_link_led = (set_link_led_t)NULL,
11243 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 11244};
ea4e040a 11245
503976e9 11246static const struct bnx2x_phy phy_serdes = {
de6eae1f
YR		 11247 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11248 .addr = 0xff,
de6eae1f 11249 .def_md_devad = 0,
9045f6b4 11250 .flags = 0,
de6eae1f
YR		 11251 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11252 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11253 .mdio_ctrl = 0,
11254 .supported = (SUPPORTED_10baseT_Half |
11255 SUPPORTED_10baseT_Full |
11256 SUPPORTED_100baseT_Half |
11257 SUPPORTED_100baseT_Full |
11258 SUPPORTED_1000baseT_Full |
11259 SUPPORTED_2500baseX_Full |
11260 SUPPORTED_TP |
11261 SUPPORTED_Autoneg |
11262 SUPPORTED_Pause |
11263 SUPPORTED_Asym_Pause),
1ac9e428 11264 .media_type = ETH_PHY_BASE_T,
de6eae1f
YR		 11265 .ver_addr = 0,
11266 .req_flow_ctrl = 0,
cd88ccee
YR		 11267 .req_line_speed = 0,
11268 .speed_cap_mask = 0,
de6eae1f
YR		 11269 .req_duplex = 0,
11270 .rsrv = 0,
ec146a6f 11271 .config_init = (config_init_t)bnx2x_xgxs_config_init,
de6eae1f
YR		 11272 .read_status = (read_status_t)bnx2x_link_settings_status,
11273 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11274 .config_loopback = (config_loopback_t)NULL,
11275 .format_fw_ver = (format_fw_ver_t)NULL,
11276 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11277 .set_link_led = (set_link_led_t)NULL,
11278 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 11279};
b7737c9b 11280
503976e9 11281static const struct bnx2x_phy phy_xgxs = {
b7737c9b
YR		 11282 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11283 .addr = 0xff,
b7737c9b 11284 .def_md_devad = 0,
9045f6b4 11285 .flags = 0,
b7737c9b
YR		 11286 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11287 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11288 .mdio_ctrl = 0,
11289 .supported = (SUPPORTED_10baseT_Half |
11290 SUPPORTED_10baseT_Full |
11291 SUPPORTED_100baseT_Half |
11292 SUPPORTED_100baseT_Full |
11293 SUPPORTED_1000baseT_Full |
11294 SUPPORTED_2500baseX_Full |
11295 SUPPORTED_10000baseT_Full |
11296 SUPPORTED_FIBRE |
11297 SUPPORTED_Autoneg |
11298 SUPPORTED_Pause |
11299 SUPPORTED_Asym_Pause),
1ac9e428 11300 .media_type = ETH_PHY_CX4,
b7737c9b
YR		 11301 .ver_addr = 0,
11302 .req_flow_ctrl = 0,
cd88ccee
YR		 11303 .req_line_speed = 0,
11304 .speed_cap_mask = 0,
b7737c9b
YR		 11305 .req_duplex = 0,
11306 .rsrv = 0,
ec146a6f 11307 .config_init = (config_init_t)bnx2x_xgxs_config_init,
b7737c9b
YR		 11308 .read_status = (read_status_t)bnx2x_link_settings_status,
11309 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11310 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11311 .format_fw_ver = (format_fw_ver_t)NULL,
11312 .hw_reset = (hw_reset_t)NULL,
a22f0788 11313 .set_link_led = (set_link_led_t)NULL,
a75bb001 11314 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
b7737c9b 11315};
503976e9 11316static const struct bnx2x_phy phy_warpcore = {
3c9ada22
YR		 11317 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11318 .addr = 0xff,
11319 .def_md_devad = 0,
8203c4b6 11320 .flags = FLAGS_TX_ERROR_CHECK,
3c9ada22
YR		 11321 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11322 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11323 .mdio_ctrl = 0,
11324 .supported = (SUPPORTED_10baseT_Half |
8f73f0b9
YR		 11325 SUPPORTED_10baseT_Full |
11326 SUPPORTED_100baseT_Half |
11327 SUPPORTED_100baseT_Full |
11328 SUPPORTED_1000baseT_Full |
11329 SUPPORTED_10000baseT_Full |
11330 SUPPORTED_20000baseKR2_Full |
11331 SUPPORTED_20000baseMLD2_Full |
11332 SUPPORTED_FIBRE |
11333 SUPPORTED_Autoneg |
11334 SUPPORTED_Pause |
11335 SUPPORTED_Asym_Pause),
3c9ada22
YR		 11336 .media_type = ETH_PHY_UNSPECIFIED,
11337 .ver_addr = 0,
11338 .req_flow_ctrl = 0,
11339 .req_line_speed = 0,
11340 .speed_cap_mask = 0,
11341 /* req_duplex = */0,
11342 /* rsrv = */0,
11343 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11344 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11345 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11346 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11347 .format_fw_ver = (format_fw_ver_t)NULL,
985848f8 11348 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
3c9ada22
YR		 11349 .set_link_led = (set_link_led_t)NULL,
11350 .phy_specific_func = (phy_specific_func_t)NULL
11351};
11352
b7737c9b 11353
503976e9 11354static const struct bnx2x_phy phy_7101 = {
b7737c9b
YR		 11355 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11356 .addr = 0xff,
b7737c9b 11357 .def_md_devad = 0,
9045f6b4 11358 .flags = FLAGS_FAN_FAILURE_DET_REQ,
b7737c9b
YR		 11359 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11360 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11361 .mdio_ctrl = 0,
11362 .supported = (SUPPORTED_10000baseT_Full |
11363 SUPPORTED_TP |
11364 SUPPORTED_Autoneg |
11365 SUPPORTED_Pause |
11366 SUPPORTED_Asym_Pause),
11367 .media_type = ETH_PHY_BASE_T,
11368 .ver_addr = 0,
11369 .req_flow_ctrl = 0,
cd88ccee
YR		 11370 .req_line_speed = 0,
11371 .speed_cap_mask = 0,
b7737c9b
YR		 11372 .req_duplex = 0,
11373 .rsrv = 0,
11374 .config_init = (config_init_t)bnx2x_7101_config_init,
11375 .read_status = (read_status_t)bnx2x_7101_read_status,
11376 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11377 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11378 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11379 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
7f02c4ad 11380 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
a22f0788 11381 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b 11382};
503976e9 11383static const struct bnx2x_phy phy_8073 = {
b7737c9b
YR		 11384 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11385 .addr = 0xff,
b7737c9b 11386 .def_md_devad = 0,
8203c4b6 11387 .flags = 0,
b7737c9b
YR		 11388 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11389 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11390 .mdio_ctrl = 0,
11391 .supported = (SUPPORTED_10000baseT_Full |
11392 SUPPORTED_2500baseX_Full |
11393 SUPPORTED_1000baseT_Full |
11394 SUPPORTED_FIBRE |
11395 SUPPORTED_Autoneg |
11396 SUPPORTED_Pause |
11397 SUPPORTED_Asym_Pause),
1ac9e428 11398 .media_type = ETH_PHY_KR,
b7737c9b 11399 .ver_addr = 0,
cd88ccee
YR		 11400 .req_flow_ctrl = 0,
11401 .req_line_speed = 0,
11402 .speed_cap_mask = 0,
b7737c9b
YR		 11403 .req_duplex = 0,
11404 .rsrv = 0,
62b29a5d 11405 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 11406 .read_status = (read_status_t)bnx2x_8073_read_status,
11407 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11408 .config_loopback = (config_loopback_t)NULL,
11409 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11410 .hw_reset = (hw_reset_t)NULL,
a22f0788 11411 .set_link_led = (set_link_led_t)NULL,
5c107fda 11412 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
b7737c9b 11413};
503976e9 11414static const struct bnx2x_phy phy_8705 = {
b7737c9b
YR		 11415 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11416 .addr = 0xff,
b7737c9b 11417 .def_md_devad = 0,
9045f6b4 11418 .flags = FLAGS_INIT_XGXS_FIRST,
b7737c9b
YR		 11419 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11420 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11421 .mdio_ctrl = 0,
11422 .supported = (SUPPORTED_10000baseT_Full |
11423 SUPPORTED_FIBRE |
11424 SUPPORTED_Pause |
11425 SUPPORTED_Asym_Pause),
11426 .media_type = ETH_PHY_XFP_FIBER,
11427 .ver_addr = 0,
11428 .req_flow_ctrl = 0,
11429 .req_line_speed = 0,
11430 .speed_cap_mask = 0,
11431 .req_duplex = 0,
11432 .rsrv = 0,
11433 .config_init = (config_init_t)bnx2x_8705_config_init,
11434 .read_status = (read_status_t)bnx2x_8705_read_status,
11435 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11436 .config_loopback = (config_loopback_t)NULL,
11437 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11438 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11439 .set_link_led = (set_link_led_t)NULL,
11440 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b 11441};
503976e9 11442static const struct bnx2x_phy phy_8706 = {
b7737c9b
YR		 11443 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11444 .addr = 0xff,
b7737c9b 11445 .def_md_devad = 0,
05822420 11446 .flags = FLAGS_INIT_XGXS_FIRST,
b7737c9b
YR		 11447 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11448 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11449 .mdio_ctrl = 0,
11450 .supported = (SUPPORTED_10000baseT_Full |
11451 SUPPORTED_1000baseT_Full |
11452 SUPPORTED_FIBRE |
11453 SUPPORTED_Pause |
11454 SUPPORTED_Asym_Pause),
dbef807e 11455 .media_type = ETH_PHY_SFPP_10G_FIBER,
b7737c9b
YR		 11456 .ver_addr = 0,
11457 .req_flow_ctrl = 0,
11458 .req_line_speed = 0,
11459 .speed_cap_mask = 0,
11460 .req_duplex = 0,
11461 .rsrv = 0,
11462 .config_init = (config_init_t)bnx2x_8706_config_init,
11463 .read_status = (read_status_t)bnx2x_8706_read_status,
11464 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11465 .config_loopback = (config_loopback_t)NULL,
11466 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11467 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11468 .set_link_led = (set_link_led_t)NULL,
11469 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 11470};
11471
503976e9 11472static const struct bnx2x_phy phy_8726 = {
b7737c9b
YR		 11473 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11474 .addr = 0xff,
9045f6b4 11475 .def_md_devad = 0,
8203c4b6 11476 .flags = (FLAGS_INIT_XGXS_FIRST |
55098c5c 11477 FLAGS_TX_ERROR_CHECK),
b7737c9b
YR		 11478 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11479 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11480 .mdio_ctrl = 0,
11481 .supported = (SUPPORTED_10000baseT_Full |
11482 SUPPORTED_1000baseT_Full |
11483 SUPPORTED_Autoneg |
11484 SUPPORTED_FIBRE |
11485 SUPPORTED_Pause |
11486 SUPPORTED_Asym_Pause),
1ac9e428 11487 .media_type = ETH_PHY_NOT_PRESENT,
b7737c9b
YR		 11488 .ver_addr = 0,
11489 .req_flow_ctrl = 0,
11490 .req_line_speed = 0,
11491 .speed_cap_mask = 0,
11492 .req_duplex = 0,
11493 .rsrv = 0,
11494 .config_init = (config_init_t)bnx2x_8726_config_init,
11495 .read_status = (read_status_t)bnx2x_8726_read_status,
11496 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11497 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11498 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11499 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 11500 .set_link_led = (set_link_led_t)NULL,
11501 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 11502};
11503
503976e9 11504static const struct bnx2x_phy phy_8727 = {
b7737c9b
YR		 11505 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11506 .addr = 0xff,
b7737c9b 11507 .def_md_devad = 0,
55098c5c
YR		 11508 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11509 FLAGS_TX_ERROR_CHECK),
b7737c9b
YR		 11510 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11511 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11512 .mdio_ctrl = 0,
11513 .supported = (SUPPORTED_10000baseT_Full |
11514 SUPPORTED_1000baseT_Full |
b7737c9b
YR		 11515 SUPPORTED_FIBRE |
11516 SUPPORTED_Pause |
11517 SUPPORTED_Asym_Pause),
1ac9e428 11518 .media_type = ETH_PHY_NOT_PRESENT,
b7737c9b
YR		 11519 .ver_addr = 0,
11520 .req_flow_ctrl = 0,
11521 .req_line_speed = 0,
11522 .speed_cap_mask = 0,
11523 .req_duplex = 0,
11524 .rsrv = 0,
11525 .config_init = (config_init_t)bnx2x_8727_config_init,
11526 .read_status = (read_status_t)bnx2x_8727_read_status,
11527 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11528 .config_loopback = (config_loopback_t)NULL,
11529 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11530 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
7f02c4ad 11531 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
a22f0788 11532 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
b7737c9b 11533};
503976e9 11534static const struct bnx2x_phy phy_8481 = {
b7737c9b
YR		 11535 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11536 .addr = 0xff,
9045f6b4 11537 .def_md_devad = 0,
a22f0788
YR		 11538 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11539 FLAGS_REARM_LATCH_SIGNAL,
b7737c9b
YR		 11540 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11541 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11542 .mdio_ctrl = 0,
11543 .supported = (SUPPORTED_10baseT_Half |
11544 SUPPORTED_10baseT_Full |
11545 SUPPORTED_100baseT_Half |
11546 SUPPORTED_100baseT_Full |
11547 SUPPORTED_1000baseT_Full |
11548 SUPPORTED_10000baseT_Full |
11549 SUPPORTED_TP |
11550 SUPPORTED_Autoneg |
11551 SUPPORTED_Pause |
11552 SUPPORTED_Asym_Pause),
11553 .media_type = ETH_PHY_BASE_T,
11554 .ver_addr = 0,
11555 .req_flow_ctrl = 0,
11556 .req_line_speed = 0,
11557 .speed_cap_mask = 0,
11558 .req_duplex = 0,
11559 .rsrv = 0,
11560 .config_init = (config_init_t)bnx2x_8481_config_init,
11561 .read_status = (read_status_t)bnx2x_848xx_read_status,
11562 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11563 .config_loopback = (config_loopback_t)NULL,
11564 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11565 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
7f02c4ad 11566 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 11567 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 11568};
11569
503976e9 11570static const struct bnx2x_phy phy_84823 = {
de6eae1f
YR		 11571 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11572 .addr = 0xff,
9045f6b4 11573 .def_md_devad = 0,
55098c5c
YR		 11574 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11575 FLAGS_REARM_LATCH_SIGNAL |
11576 FLAGS_TX_ERROR_CHECK),
de6eae1f
YR		 11577 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11578 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11579 .mdio_ctrl = 0,
11580 .supported = (SUPPORTED_10baseT_Half |
11581 SUPPORTED_10baseT_Full |
11582 SUPPORTED_100baseT_Half |
11583 SUPPORTED_100baseT_Full |
11584 SUPPORTED_1000baseT_Full |
11585 SUPPORTED_10000baseT_Full |
11586 SUPPORTED_TP |
11587 SUPPORTED_Autoneg |
11588 SUPPORTED_Pause |
11589 SUPPORTED_Asym_Pause),
11590 .media_type = ETH_PHY_BASE_T,
11591 .ver_addr = 0,
11592 .req_flow_ctrl = 0,
11593 .req_line_speed = 0,
11594 .speed_cap_mask = 0,
11595 .req_duplex = 0,
11596 .rsrv = 0,
11597 .config_init = (config_init_t)bnx2x_848x3_config_init,
11598 .read_status = (read_status_t)bnx2x_848xx_read_status,
11599 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11600 .config_loopback = (config_loopback_t)NULL,
11601 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11602 .hw_reset = (hw_reset_t)NULL,
7f02c4ad 11603 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
5c107fda 11604 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
de6eae1f
YR		 11605};
11606
503976e9 11607static const struct bnx2x_phy phy_84833 = {
c87bca1e
YR		 11608 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11609 .addr = 0xff,
9045f6b4 11610 .def_md_devad = 0,
55098c5c
YR		 11611 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11612 FLAGS_REARM_LATCH_SIGNAL |
f6b6eb69 11613 FLAGS_TX_ERROR_CHECK),
c87bca1e
YR		 11614 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11615 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11616 .mdio_ctrl = 0,
0520e63a 11617 .supported = (SUPPORTED_100baseT_Half |
c87bca1e
YR		 11618 SUPPORTED_100baseT_Full |
11619 SUPPORTED_1000baseT_Full |
11620 SUPPORTED_10000baseT_Full |
11621 SUPPORTED_TP |
11622 SUPPORTED_Autoneg |
11623 SUPPORTED_Pause |
11624 SUPPORTED_Asym_Pause),
11625 .media_type = ETH_PHY_BASE_T,
11626 .ver_addr = 0,
11627 .req_flow_ctrl = 0,
11628 .req_line_speed = 0,
11629 .speed_cap_mask = 0,
11630 .req_duplex = 0,
11631 .rsrv = 0,
11632 .config_init = (config_init_t)bnx2x_848x3_config_init,
11633 .read_status = (read_status_t)bnx2x_848xx_read_status,
11634 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11635 .config_loopback = (config_loopback_t)NULL,
11636 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
985848f8 11637 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
c87bca1e 11638 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
5c107fda 11639 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
c87bca1e
YR		 11640};
11641
0f6bb03d
YR		 11642static const struct bnx2x_phy phy_84834 = {
11643 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11644 .addr = 0xff,
11645 .def_md_devad = 0,
11646 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11647 FLAGS_REARM_LATCH_SIGNAL,
11648 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11649 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11650 .mdio_ctrl = 0,
11651 .supported = (SUPPORTED_100baseT_Half |
11652 SUPPORTED_100baseT_Full |
11653 SUPPORTED_1000baseT_Full |
11654 SUPPORTED_10000baseT_Full |
11655 SUPPORTED_TP |
11656 SUPPORTED_Autoneg |
11657 SUPPORTED_Pause |
11658 SUPPORTED_Asym_Pause),
11659 .media_type = ETH_PHY_BASE_T,
11660 .ver_addr = 0,
11661 .req_flow_ctrl = 0,
11662 .req_line_speed = 0,
11663 .speed_cap_mask = 0,
11664 .req_duplex = 0,
11665 .rsrv = 0,
11666 .config_init = (config_init_t)bnx2x_848x3_config_init,
11667 .read_status = (read_status_t)bnx2x_848xx_read_status,
11668 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11669 .config_loopback = (config_loopback_t)NULL,
11670 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11671 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11672 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11673 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11674};
11675
503976e9 11676static const struct bnx2x_phy phy_54618se = {
52c4d6c4 11677 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
6583e33b
YR		 11678 .addr = 0xff,
11679 .def_md_devad = 0,
11680 .flags = FLAGS_INIT_XGXS_FIRST,
11681 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11682 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11683 .mdio_ctrl = 0,
11684 .supported = (SUPPORTED_10baseT_Half |
11685 SUPPORTED_10baseT_Full |
11686 SUPPORTED_100baseT_Half |
11687 SUPPORTED_100baseT_Full |
11688 SUPPORTED_1000baseT_Full |
11689 SUPPORTED_TP |
11690 SUPPORTED_Autoneg |
11691 SUPPORTED_Pause |
11692 SUPPORTED_Asym_Pause),
11693 .media_type = ETH_PHY_BASE_T,
11694 .ver_addr = 0,
11695 .req_flow_ctrl = 0,
11696 .req_line_speed = 0,
11697 .speed_cap_mask = 0,
11698 /* req_duplex = */0,
11699 /* rsrv = */0,
52c4d6c4
YR		 11700 .config_init = (config_init_t)bnx2x_54618se_config_init,
11701 .read_status = (read_status_t)bnx2x_54618se_read_status,
11702 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11703 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
6583e33b
YR		 11704 .format_fw_ver = (format_fw_ver_t)NULL,
11705 .hw_reset = (hw_reset_t)NULL,
1d125bd5 11706 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
5c107fda 11707 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
6583e33b 11708};
de6eae1f
YR		 11709/*****************************************************************/
11710/* */
11711/* Populate the phy according. Main function: bnx2x_populate_phy */
11712/* */
11713/*****************************************************************/
11714
11715static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11716 struct bnx2x_phy *phy, u8 port,
11717 u8 phy_index)
11718{
11719 /* Get the 4 lanes xgxs config rx and tx */
11720 u32 rx = 0, tx = 0, i;
11721 for (i = 0; i < 2; i++) {
8f73f0b9
YR		 11722 /* INT_PHY and EXT_PHY1 share the same value location in
11723 * the shmem. When num_phys is greater than 1, than this value
de6eae1f
YR		 11724 * applies only to EXT_PHY1
11725 */
a22f0788
YR		 11726 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11727 rx = REG_RD(bp, shmem_base +
11728 offsetof(struct shmem_region,
cd88ccee 11729 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
a22f0788
YR		 11730
11731 tx = REG_RD(bp, shmem_base +
11732 offsetof(struct shmem_region,
cd88ccee 11733 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
a22f0788
YR		 11734 } else {
11735 rx = REG_RD(bp, shmem_base +
11736 offsetof(struct shmem_region,
cd88ccee 11737 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
de6eae1f 11738
a22f0788
YR		 11739 tx = REG_RD(bp, shmem_base +
11740 offsetof(struct shmem_region,
cd88ccee 11741 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
a22f0788 11742 }
de6eae1f
YR		 11743
11744 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11745 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11746
11747 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11748 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11749 }
11750}
11751
11752static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11753 u8 phy_index, u8 port)
11754{
11755 u32 ext_phy_config = 0;
11756 switch (phy_index) {
11757 case EXT_PHY1:
11758 ext_phy_config = REG_RD(bp, shmem_base +
11759 offsetof(struct shmem_region,
11760 dev_info.port_hw_config[port].external_phy_config));
11761 break;
a22f0788
YR		 11762 case EXT_PHY2:
11763 ext_phy_config = REG_RD(bp, shmem_base +
11764 offsetof(struct shmem_region,
11765 dev_info.port_hw_config[port].external_phy_config2));
11766 break;
de6eae1f
YR		 11767 default:
11768 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11769 return -EINVAL;
11770 }
11771
11772 return ext_phy_config;
11773}
fcf5b650
YR		 11774static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11775 struct bnx2x_phy *phy)
de6eae1f
YR		 11776{
11777 u32 phy_addr;
11778 u32 chip_id;
11779 u32 switch_cfg = (REG_RD(bp, shmem_base +
11780 offsetof(struct shmem_region,
11781 dev_info.port_feature_config[port].link_config)) &
11782 PORT_FEATURE_CONNECTED_SWITCH_MASK);
ec15b898
YR		 11783 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11784 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11785
3c9ada22
YR		 11786 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11787 if (USES_WARPCORE(bp)) {
11788 u32 serdes_net_if;
de6eae1f 11789 phy_addr = REG_RD(bp,
3c9ada22
YR		 11790 MISC_REG_WC0_CTRL_PHY_ADDR);
11791 *phy = phy_warpcore;
11792 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11793 phy->flags |= FLAGS_4_PORT_MODE;
11794 else
11795 phy->flags &= ~FLAGS_4_PORT_MODE;
11796 /* Check Dual mode */
11797 serdes_net_if = (REG_RD(bp, shmem_base +
11798 offsetof(struct shmem_region, dev_info.
11799 port_hw_config[port].default_cfg)) &
11800 PORT_HW_CFG_NET_SERDES_IF_MASK);
8f73f0b9 11801 /* Set the appropriate supported and flags indications per
3c9ada22
YR		 11802 * interface type of the chip
11803 */
11804 switch (serdes_net_if) {
11805 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11806 phy->supported &= (SUPPORTED_10baseT_Half |
11807 SUPPORTED_10baseT_Full |
11808 SUPPORTED_100baseT_Half |
11809 SUPPORTED_100baseT_Full |
11810 SUPPORTED_1000baseT_Full |
11811 SUPPORTED_FIBRE |
11812 SUPPORTED_Autoneg |
11813 SUPPORTED_Pause |
11814 SUPPORTED_Asym_Pause);
11815 phy->media_type = ETH_PHY_BASE_T;
11816 break;
11817 case PORT_HW_CFG_NET_SERDES_IF_XFI:
03c31488
YR		 11818 phy->supported &= (SUPPORTED_1000baseT_Full |
11819 SUPPORTED_10000baseT_Full |
11820 SUPPORTED_FIBRE |
11821 SUPPORTED_Pause |
11822 SUPPORTED_Asym_Pause);
3c9ada22
YR		 11823 phy->media_type = ETH_PHY_XFP_FIBER;
11824 break;
11825 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11826 phy->supported &= (SUPPORTED_1000baseT_Full |
11827 SUPPORTED_10000baseT_Full |
11828 SUPPORTED_FIBRE |
11829 SUPPORTED_Pause |
11830 SUPPORTED_Asym_Pause);
dbef807e 11831 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
3c9ada22
YR		 11832 break;
11833 case PORT_HW_CFG_NET_SERDES_IF_KR:
11834 phy->media_type = ETH_PHY_KR;
11835 phy->supported &= (SUPPORTED_1000baseT_Full |
11836 SUPPORTED_10000baseT_Full |
11837 SUPPORTED_FIBRE |
11838 SUPPORTED_Autoneg |
11839 SUPPORTED_Pause |
11840 SUPPORTED_Asym_Pause);
11841 break;
11842 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11843 phy->media_type = ETH_PHY_KR;
11844 phy->flags |= FLAGS_WC_DUAL_MODE;
11845 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11846 SUPPORTED_FIBRE |
11847 SUPPORTED_Pause |
11848 SUPPORTED_Asym_Pause);
11849 break;
11850 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11851 phy->media_type = ETH_PHY_KR;
11852 phy->flags |= FLAGS_WC_DUAL_MODE;
11853 phy->supported &= (SUPPORTED_20000baseKR2_Full |
be94bea7
YR		 11854 SUPPORTED_10000baseT_Full |
11855 SUPPORTED_1000baseT_Full |
4e7b4997 11856 SUPPORTED_Autoneg |
3c9ada22
YR		 11857 SUPPORTED_FIBRE |
11858 SUPPORTED_Pause |
11859 SUPPORTED_Asym_Pause);
4e7b4997 11860 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
3c9ada22
YR		 11861 break;
11862 default:
11863 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11864 serdes_net_if);
11865 break;
11866 }
11867
8f73f0b9 11868 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
3c9ada22
YR		 11869 * was not set as expected. For B0, ECO will be enabled so there
11870 * won't be an issue there
11871 */
11872 if (CHIP_REV(bp) == CHIP_REV_Ax)
11873 phy->flags |= FLAGS_MDC_MDIO_WA;
157fa283
YR		 11874 else
11875 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
3c9ada22
YR		 11876 } else {
11877 switch (switch_cfg) {
11878 case SWITCH_CFG_1G:
11879 phy_addr = REG_RD(bp,
11880 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11881 port * 0x10);
11882 *phy = phy_serdes;
11883 break;
11884 case SWITCH_CFG_10G:
11885 phy_addr = REG_RD(bp,
11886 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11887 port * 0x18);
11888 *phy = phy_xgxs;
11889 break;
11890 default:
11891 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11892 return -EINVAL;
11893 }
de6eae1f
YR		 11894 }
11895 phy->addr = (u8)phy_addr;
11896 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11897 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11898 port);
f2e0899f
DK		 11899 if (CHIP_IS_E2(bp))
11900 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11901 else
11902 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
de6eae1f
YR		 11903
11904 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11905 port, phy->addr, phy->mdio_ctrl);
11906
11907 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11908 return 0;
11909}
11910
fcf5b650
YR		 11911static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11912 u8 phy_index,
11913 u32 shmem_base,
11914 u32 shmem2_base,
11915 u8 port,
11916 struct bnx2x_phy *phy)
de6eae1f
YR		 11917{
11918 u32 ext_phy_config, phy_type, config2;
11919 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11920 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11921 phy_index, port);
11922 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11923 /* Select the phy type */
11924 switch (phy_type) {
11925 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11926 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11927 *phy = phy_8073;
11928 break;
11929 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11930 *phy = phy_8705;
11931 break;
11932 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11933 *phy = phy_8706;
11934 break;
11935 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11936 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11937 *phy = phy_8726;
11938 break;
11939 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11940 /* BCM8727_NOC => BCM8727 no over current */
11941 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11942 *phy = phy_8727;
11943 phy->flags |= FLAGS_NOC;
11944 break;
e4d78f12 11945 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
de6eae1f
YR		 11946 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11947 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11948 *phy = phy_8727;
11949 break;
11950 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11951 *phy = phy_8481;
11952 break;
11953 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11954 *phy = phy_84823;
11955 break;
c87bca1e
YR		 11956 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11957 *phy = phy_84833;
11958 break;
0f6bb03d
YR		 11959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
11960 *phy = phy_84834;
11961 break;
3756a89f 11962 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
52c4d6c4
YR		 11963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11964 *phy = phy_54618se;
26964bb7
YM		 11965 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
11966 phy->flags |= FLAGS_EEE;
6583e33b 11967 break;
de6eae1f
YR		 11968 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11969 *phy = phy_7101;
11970 break;
11971 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11972 *phy = phy_null;
11973 return -EINVAL;
11974 default:
11975 *phy = phy_null;
6db5193b
YR		 11976 /* In case external PHY wasn't found */
11977 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11978 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11979 return -EINVAL;
de6eae1f
YR		 11980 return 0;
11981 }
11982
11983 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11984 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11985
8f73f0b9 11986 /* The shmem address of the phy version is located on different
2cf7acf9
YR		 11987 * structures. In case this structure is too old, do not set
11988 * the address
11989 */
de6eae1f
YR		 11990 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11991 dev_info.shared_hw_config.config2));
a22f0788
YR		 11992 if (phy_index == EXT_PHY1) {
11993 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11994 port_mb[port].ext_phy_fw_version);
de6eae1f 11995
cd88ccee
YR		 11996 /* Check specific mdc mdio settings */
11997 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11998 mdc_mdio_access = config2 &
11999 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
a22f0788
YR		 12000 } else {
12001 u32 size = REG_RD(bp, shmem2_base);
de6eae1f 12002
a22f0788
YR		 12003 if (size >
12004 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12005 phy->ver_addr = shmem2_base +
12006 offsetof(struct shmem2_region,
12007 ext_phy_fw_version2[port]);
12008 }
12009 /* Check specific mdc mdio settings */
12010 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12011 mdc_mdio_access = (config2 &
12012 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12013 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12014 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12015 }
de6eae1f
YR		 12016 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12017
0f6bb03d
YR		 12018 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12019 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
75318327 12020 (phy->ver_addr)) {
0f6bb03d 12021 /* Remove 100Mb link supported for BCM84833/4 when phy fw
75318327
YR		 12022 * version lower than or equal to 1.39
12023 */
12024 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12025 if (((raw_ver & 0x7F) <= 39) &&
12026 (((raw_ver & 0xF80) >> 7) <= 1))
12027 phy->supported &= ~(SUPPORTED_100baseT_Half |
12028 SUPPORTED_100baseT_Full);
12029 }
12030
de6eae1f
YR		 12031 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12032 phy_type, port, phy_index);
12033 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12034 phy->addr, phy->mdio_ctrl);
12035 return 0;
12036}
12037
fcf5b650
YR		 12038static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12039 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
de6eae1f 12040{
fcf5b650 12041 int status = 0;
de6eae1f
YR		 12042 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12043 if (phy_index == INT_PHY)
12044 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
a22f0788 12045 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 12046 port, phy);
12047 return status;
12048}
12049
12050static void bnx2x_phy_def_cfg(struct link_params *params,
12051 struct bnx2x_phy *phy,
a22f0788 12052 u8 phy_index)
de6eae1f
YR		 12053{
12054 struct bnx2x *bp = params->bp;
12055 u32 link_config;
12056 /* Populate the default phy configuration for MF mode */
a22f0788
YR		 12057 if (phy_index == EXT_PHY2) {
12058 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 12059 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 12060 port_feature_config[params->port].link_config2));
12061 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 12062 offsetof(struct shmem_region,
12063 dev_info.
a22f0788
YR		 12064 port_hw_config[params->port].speed_capability_mask2));
12065 } else {
12066 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 12067 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 12068 port_feature_config[params->port].link_config));
12069 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 12070 offsetof(struct shmem_region,
12071 dev_info.
12072 port_hw_config[params->port].speed_capability_mask));
a22f0788 12073 }
94f05b0f
JP		 12074 DP(NETIF_MSG_LINK,
12075 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12076 phy_index, link_config, phy->speed_cap_mask);
de6eae1f
YR		 12077
12078 phy->req_duplex = DUPLEX_FULL;
12079 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12080 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12081 phy->req_duplex = DUPLEX_HALF;
12082 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12083 phy->req_line_speed = SPEED_10;
12084 break;
12085 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12086 phy->req_duplex = DUPLEX_HALF;
12087 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12088 phy->req_line_speed = SPEED_100;
12089 break;
12090 case PORT_FEATURE_LINK_SPEED_1G:
12091 phy->req_line_speed = SPEED_1000;
12092 break;
12093 case PORT_FEATURE_LINK_SPEED_2_5G:
12094 phy->req_line_speed = SPEED_2500;
12095 break;
12096 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12097 phy->req_line_speed = SPEED_10000;
12098 break;
12099 default:
12100 phy->req_line_speed = SPEED_AUTO_NEG;
12101 break;
12102 }
12103
12104 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12105 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12106 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12107 break;
12108 case PORT_FEATURE_FLOW_CONTROL_TX:
12109 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12110 break;
12111 case PORT_FEATURE_FLOW_CONTROL_RX:
12112 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12113 break;
12114 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12115 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12116 break;
12117 default:
12118 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12119 break;
12120 }
12121}
12122
a22f0788
YR		 12123u32 bnx2x_phy_selection(struct link_params *params)
12124{
12125 u32 phy_config_swapped, prio_cfg;
12126 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12127
12128 phy_config_swapped = params->multi_phy_config &
12129 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12130
12131 prio_cfg = params->multi_phy_config &
12132 PORT_HW_CFG_PHY_SELECTION_MASK;
12133
12134 if (phy_config_swapped) {
12135 switch (prio_cfg) {
12136 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12137 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12138 break;
12139 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12140 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12141 break;
12142 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12143 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12144 break;
12145 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12146 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12147 break;
12148 }
12149 } else
12150 return_cfg = prio_cfg;
12151
12152 return return_cfg;
12153}
12154
fcf5b650 12155int bnx2x_phy_probe(struct link_params *params)
de6eae1f 12156{
2f751a80 12157 u8 phy_index, actual_phy_idx;
1ac9e428 12158 u32 phy_config_swapped, sync_offset, media_types;
de6eae1f
YR		 12159 struct bnx2x *bp = params->bp;
12160 struct bnx2x_phy *phy;
12161 params->num_phys = 0;
12162 DP(NETIF_MSG_LINK, "Begin phy probe\n");
a22f0788
YR		 12163 phy_config_swapped = params->multi_phy_config &
12164 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 12165
12166 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12167 phy_index++) {
de6eae1f 12168 actual_phy_idx = phy_index;
a22f0788
YR		 12169 if (phy_config_swapped) {
12170 if (phy_index == EXT_PHY1)
12171 actual_phy_idx = EXT_PHY2;
12172 else if (phy_index == EXT_PHY2)
12173 actual_phy_idx = EXT_PHY1;
12174 }
12175 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12176 " actual_phy_idx %x\n", phy_config_swapped,
12177 phy_index, actual_phy_idx);
de6eae1f
YR		 12178 phy = &params->phy[actual_phy_idx];
12179 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
a22f0788 12180 params->shmem2_base, params->port,
de6eae1f
YR		 12181 phy) != 0) {
12182 params->num_phys = 0;
12183 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12184 phy_index);
12185 for (phy_index = INT_PHY;
12186 phy_index < MAX_PHYS;
12187 phy_index++)
12188 *phy = phy_null;
12189 return -EINVAL;
12190 }
12191 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12192 break;
12193
55098c5c
YR		 12194 if (params->feature_config_flags &
12195 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12196 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12197
55386fe8
YR		 12198 if (!(params->feature_config_flags &
12199 FEATURE_CONFIG_MT_SUPPORT))
12200 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12201
1ac9e428
YR		 12202 sync_offset = params->shmem_base +
12203 offsetof(struct shmem_region,
12204 dev_info.port_hw_config[params->port].media_type);
12205 media_types = REG_RD(bp, sync_offset);
12206
8f73f0b9 12207 /* Update media type for non-PMF sync only for the first time
1ac9e428
YR		 12208 * In case the media type changes afterwards, it will be updated
12209 * using the update_status function
12210 */
12211 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12212 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12213 actual_phy_idx))) == 0) {
12214 media_types |= ((phy->media_type &
12215 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12216 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12217 actual_phy_idx));
12218 }
12219 REG_WR(bp, sync_offset, media_types);
12220
a22f0788 12221 bnx2x_phy_def_cfg(params, phy, phy_index);
de6eae1f
YR		 12222 params->num_phys++;
12223 }
12224
12225 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12226 return 0;
12227}
12228
910cc727
MS		 12229static void bnx2x_init_bmac_loopback(struct link_params *params,
12230 struct link_vars *vars)
de6eae1f
YR		 12231{
12232 struct bnx2x *bp = params->bp;
de6eae1f
YR		 12233 vars->link_up = 1;
12234 vars->line_speed = SPEED_10000;
12235 vars->duplex = DUPLEX_FULL;
12236 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12237 vars->mac_type = MAC_TYPE_BMAC;
b7737c9b 12238
de6eae1f 12239 vars->phy_flags = PHY_XGXS_FLAG;
b7737c9b 12240
de6eae1f 12241 bnx2x_xgxs_deassert(params);
b7737c9b 12242
de6eae1f 12243 /* set bmac loopback */
d3a8f13b 12244 bnx2x_bmac_enable(params, vars, 1, 1);
b7737c9b 12245
cd88ccee 12246 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
9045f6b4 12247}
b7737c9b 12248
910cc727
MS		 12249static void bnx2x_init_emac_loopback(struct link_params *params,
12250 struct link_vars *vars)
9045f6b4
YR		 12251{
12252 struct bnx2x *bp = params->bp;
de6eae1f
YR		 12253 vars->link_up = 1;
12254 vars->line_speed = SPEED_1000;
12255 vars->duplex = DUPLEX_FULL;
12256 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12257 vars->mac_type = MAC_TYPE_EMAC;
b7737c9b 12258
de6eae1f 12259 vars->phy_flags = PHY_XGXS_FLAG;
e10bc84d 12260
de6eae1f
YR		 12261 bnx2x_xgxs_deassert(params);
12262 /* set bmac loopback */
12263 bnx2x_emac_enable(params, vars, 1);
12264 bnx2x_emac_program(params, vars);
cd88ccee 12265 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
9045f6b4 12266}
b7737c9b 12267
910cc727
MS		 12268static void bnx2x_init_xmac_loopback(struct link_params *params,
12269 struct link_vars *vars)
9380bb9e
YR		 12270{
12271 struct bnx2x *bp = params->bp;
12272 vars->link_up = 1;
12273 if (!params->req_line_speed[0])
12274 vars->line_speed = SPEED_10000;
12275 else
12276 vars->line_speed = params->req_line_speed[0];
12277 vars->duplex = DUPLEX_FULL;
12278 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12279 vars->mac_type = MAC_TYPE_XMAC;
12280 vars->phy_flags = PHY_XGXS_FLAG;
8f73f0b9 12281 /* Set WC to loopback mode since link is required to provide clock
9380bb9e
YR		 12282 * to the XMAC in 20G mode
12283 */
afad009a
YR		 12284 bnx2x_set_aer_mmd(params, &params->phy[0]);
12285 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12286 params->phy[INT_PHY].config_loopback(
3c9ada22
YR		 12287 &params->phy[INT_PHY],
12288 params);
afad009a 12289
9380bb9e
YR		 12290 bnx2x_xmac_enable(params, vars, 1);
12291 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12292}
12293
910cc727
MS		 12294static void bnx2x_init_umac_loopback(struct link_params *params,
12295 struct link_vars *vars)
9380bb9e
YR		 12296{
12297 struct bnx2x *bp = params->bp;
12298 vars->link_up = 1;
12299 vars->line_speed = SPEED_1000;
12300 vars->duplex = DUPLEX_FULL;
12301 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12302 vars->mac_type = MAC_TYPE_UMAC;
12303 vars->phy_flags = PHY_XGXS_FLAG;
12304 bnx2x_umac_enable(params, vars, 1);
12305
12306 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12307}
12308
910cc727
MS		 12309static void bnx2x_init_xgxs_loopback(struct link_params *params,
12310 struct link_vars *vars)
9045f6b4
YR		 12311{
12312 struct bnx2x *bp = params->bp;
4e7b4997 12313 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
503976e9
YR		 12314 vars->link_up = 1;
12315 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12316 vars->duplex = DUPLEX_FULL;
9045f6b4 12317 if (params->req_line_speed[0] == SPEED_1000)
503976e9 12318 vars->line_speed = SPEED_1000;
4e7b4997
YR		 12319 else if ((params->req_line_speed[0] == SPEED_20000) ||
12320 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12321 vars->line_speed = SPEED_20000;
9045f6b4 12322 else
4e7b4997 12323 vars->line_speed = SPEED_10000;
62b29a5d 12324
9380bb9e
YR		 12325 if (!USES_WARPCORE(bp))
12326 bnx2x_xgxs_deassert(params);
9045f6b4
YR		 12327 bnx2x_link_initialize(params, vars);
12328
12329 if (params->req_line_speed[0] == SPEED_1000) {
9380bb9e
YR		 12330 if (USES_WARPCORE(bp))
12331 bnx2x_umac_enable(params, vars, 0);
12332 else {
12333 bnx2x_emac_program(params, vars);
12334 bnx2x_emac_enable(params, vars, 0);
12335 }
12336 } else {
12337 if (USES_WARPCORE(bp))
12338 bnx2x_xmac_enable(params, vars, 0);
12339 else
d3a8f13b 12340 bnx2x_bmac_enable(params, vars, 0, 1);
9380bb9e 12341 }
9045f6b4 12342
503976e9
YR		 12343 if (params->loopback_mode == LOOPBACK_XGXS) {
12344 /* Set 10G XGXS loopback */
12345 int_phy->config_loopback(int_phy, params);
12346 } else {
12347 /* Set external phy loopback */
12348 u8 phy_index;
12349 for (phy_index = EXT_PHY1;
12350 phy_index < params->num_phys; phy_index++)
12351 if (params->phy[phy_index].config_loopback)
12352 params->phy[phy_index].config_loopback(
12353 &params->phy[phy_index],
12354 params);
12355 }
12356 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
de6eae1f 12357
9045f6b4
YR		 12358 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12359}
12360
55c11941 12361void bnx2x_set_rx_filter(struct link_params *params, u8 en)
d3a8f13b
YR		 12362{
12363 struct bnx2x *bp = params->bp;
12364 u8 val = en * 0x1F;
12365
503976e9 12366 /* Open / close the gate between the NIG and the BRB */
d3a8f13b
YR		 12367 if (!CHIP_IS_E1x(bp))
12368 val |= en * 0x20;
12369 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12370
12371 if (!CHIP_IS_E1(bp)) {
12372 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12373 en*0x3);
12374 }
12375
12376 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12377 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12378}
12379static int bnx2x_avoid_link_flap(struct link_params *params,
12380 struct link_vars *vars)
12381{
12382 u32 phy_idx;
12383 u32 dont_clear_stat, lfa_sts;
12384 struct bnx2x *bp = params->bp;
12385
12386 /* Sync the link parameters */
12387 bnx2x_link_status_update(params, vars);
12388
12389 /*
12390 * The module verification was already done by previous link owner,
12391 * so this call is meant only to get warning message
12392 */
12393
12394 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12395 struct bnx2x_phy *phy = &params->phy[phy_idx];
12396 if (phy->phy_specific_func) {
12397 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12398 phy->phy_specific_func(phy, params, PHY_INIT);
12399 }
12400 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12401 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12402 (phy->media_type == ETH_PHY_DA_TWINAX))
12403 bnx2x_verify_sfp_module(phy, params);
12404 }
12405 lfa_sts = REG_RD(bp, params->lfa_base +
12406 offsetof(struct shmem_lfa,
12407 lfa_sts));
12408
12409 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12410
12411 /* Re-enable the NIG/MAC */
12412 if (CHIP_IS_E3(bp)) {
12413 if (!dont_clear_stat) {
12414 REG_WR(bp, GRCBASE_MISC +
12415 MISC_REGISTERS_RESET_REG_2_CLEAR,
12416 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12417 params->port));
12418 REG_WR(bp, GRCBASE_MISC +
12419 MISC_REGISTERS_RESET_REG_2_SET,
12420 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12421 params->port));
12422 }
12423 if (vars->line_speed < SPEED_10000)
12424 bnx2x_umac_enable(params, vars, 0);
12425 else
12426 bnx2x_xmac_enable(params, vars, 0);
12427 } else {
12428 if (vars->line_speed < SPEED_10000)
12429 bnx2x_emac_enable(params, vars, 0);
12430 else
12431 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12432 }
12433
12434 /* Increment LFA count */
12435 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12436 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12437 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12438 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12439 /* Clear link flap reason */
12440 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12441
12442 REG_WR(bp, params->lfa_base +
12443 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12444
12445 /* Disable NIG DRAIN */
12446 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12447
12448 /* Enable interrupts */
12449 bnx2x_link_int_enable(params);
12450 return 0;
12451}
12452
12453static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12454 struct link_vars *vars,
12455 int lfa_status)
12456{
12457 u32 lfa_sts, cfg_idx, tmp_val;
12458 struct bnx2x *bp = params->bp;
12459
12460 bnx2x_link_reset(params, vars, 1);
12461
12462 if (!params->lfa_base)
12463 return;
12464 /* Store the new link parameters */
12465 REG_WR(bp, params->lfa_base +
12466 offsetof(struct shmem_lfa, req_duplex),
12467 params->req_duplex[0] | (params->req_duplex[1] << 16));
12468
12469 REG_WR(bp, params->lfa_base +
12470 offsetof(struct shmem_lfa, req_flow_ctrl),
12471 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12472
12473 REG_WR(bp, params->lfa_base +
12474 offsetof(struct shmem_lfa, req_line_speed),
12475 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12476
12477 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12478 REG_WR(bp, params->lfa_base +
12479 offsetof(struct shmem_lfa,
12480 speed_cap_mask[cfg_idx]),
12481 params->speed_cap_mask[cfg_idx]);
12482 }
12483
12484 tmp_val = REG_RD(bp, params->lfa_base +
12485 offsetof(struct shmem_lfa, additional_config));
12486 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12487 tmp_val |= params->req_fc_auto_adv;
12488
12489 REG_WR(bp, params->lfa_base +
12490 offsetof(struct shmem_lfa, additional_config), tmp_val);
12491
12492 lfa_sts = REG_RD(bp, params->lfa_base +
12493 offsetof(struct shmem_lfa, lfa_sts));
12494
12495 /* Clear the "Don't Clear Statistics" bit, and set reason */
12496 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12497
12498 /* Set link flap reason */
12499 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12500 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12501 LFA_LINK_FLAP_REASON_OFFSET);
12502
12503 /* Increment link flap counter */
12504 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12505 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12506 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12507 << LINK_FLAP_COUNT_OFFSET));
12508 REG_WR(bp, params->lfa_base +
12509 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12510 /* Proceed with regular link initialization */
12511}
12512
9045f6b4
YR		 12513int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12514{
d3a8f13b 12515 int lfa_status;
9045f6b4
YR		 12516 struct bnx2x *bp = params->bp;
12517 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12518 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12519 params->req_line_speed[0], params->req_flow_ctrl[0]);
12520 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12521 params->req_line_speed[1], params->req_flow_ctrl[1]);
12522 vars->link_status = 0;
12523 vars->phy_link_up = 0;
12524 vars->link_up = 0;
12525 vars->line_speed = 0;
12526 vars->duplex = DUPLEX_FULL;
12527 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12528 vars->mac_type = MAC_TYPE_NONE;
12529 vars->phy_flags = 0;
d3a8f13b
YR		 12530 /* Driver opens NIG-BRB filters */
12531 bnx2x_set_rx_filter(params, 1);
12532 /* Check if link flap can be avoided */
12533 lfa_status = bnx2x_check_lfa(params);
12534
12535 if (lfa_status == 0) {
12536 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12537 return bnx2x_avoid_link_flap(params, vars);
12538 }
12539
12540 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12541 lfa_status);
12542 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
9045f6b4 12543
d231023e 12544 /* Disable attentions */
9045f6b4
YR		 12545 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12546 (NIG_MASK_XGXS0_LINK_STATUS |
12547 NIG_MASK_XGXS0_LINK10G |
12548 NIG_MASK_SERDES0_LINK_STATUS |
12549 NIG_MASK_MI_INT));
12550
12551 bnx2x_emac_init(params, vars);
12552
27d9129f
YR		 12553 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12554 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12555
9045f6b4
YR		 12556 if (params->num_phys == 0) {
12557 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12558 return -EINVAL;
12559 }
12560 set_phy_vars(params, vars);
12561
12562 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12563 switch (params->loopback_mode) {
12564 case LOOPBACK_BMAC:
12565 bnx2x_init_bmac_loopback(params, vars);
12566 break;
12567 case LOOPBACK_EMAC:
12568 bnx2x_init_emac_loopback(params, vars);
12569 break;
9380bb9e
YR		 12570 case LOOPBACK_XMAC:
12571 bnx2x_init_xmac_loopback(params, vars);
12572 break;
12573 case LOOPBACK_UMAC:
12574 bnx2x_init_umac_loopback(params, vars);
12575 break;
9045f6b4
YR		 12576 case LOOPBACK_XGXS:
12577 case LOOPBACK_EXT_PHY:
12578 bnx2x_init_xgxs_loopback(params, vars);
12579 break;
12580 default:
9380bb9e
YR		 12581 if (!CHIP_IS_E3(bp)) {
12582 if (params->switch_cfg == SWITCH_CFG_10G)
12583 bnx2x_xgxs_deassert(params);
12584 else
12585 bnx2x_serdes_deassert(bp, params->port);
12586 }
de6eae1f
YR		 12587 bnx2x_link_initialize(params, vars);
12588 msleep(30);
12589 bnx2x_link_int_enable(params);
9045f6b4 12590 break;
de6eae1f 12591 }
55098c5c 12592 bnx2x_update_mng(params, vars->link_status);
c8c60d88
YM		 12593
12594 bnx2x_update_mng_eee(params, vars->eee_status);
e10bc84d
YR		 12595 return 0;
12596}
fcf5b650
YR		 12597
12598int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12599 u8 reset_ext_phy)
b7737c9b
YR		 12600{
12601 struct bnx2x *bp = params->bp;
cf1d972c 12602 u8 phy_index, port = params->port, clear_latch_ind = 0;
de6eae1f 12603 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
d231023e 12604 /* Disable attentions */
de6eae1f
YR		 12605 vars->link_status = 0;
12606 bnx2x_update_mng(params, vars->link_status);
c8c60d88
YM		 12607 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12608 SHMEM_EEE_ACTIVE_BIT);
12609 bnx2x_update_mng_eee(params, vars->eee_status);
de6eae1f 12610 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 12611 (NIG_MASK_XGXS0_LINK_STATUS |
12612 NIG_MASK_XGXS0_LINK10G |
12613 NIG_MASK_SERDES0_LINK_STATUS |
12614 NIG_MASK_MI_INT));
b7737c9b 12615
d231023e 12616 /* Activate nig drain */
de6eae1f 12617 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
b7737c9b 12618
d231023e 12619 /* Disable nig egress interface */
9380bb9e
YR		 12620 if (!CHIP_IS_E3(bp)) {
12621 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12622 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12623 }
b7737c9b 12624
d3a8f13b
YR		 12625 if (!CHIP_IS_E3(bp)) {
12626 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12627 } else {
12628 bnx2x_set_xmac_rxtx(params, 0);
12629 bnx2x_set_umac_rxtx(params, 0);
12630 }
d231023e 12631 /* Disable emac */
9380bb9e
YR		 12632 if (!CHIP_IS_E3(bp))
12633 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
b7737c9b 12634
d231023e 12635 usleep_range(10000, 20000);
25985edc 12636 /* The PHY reset is controlled by GPIO 1
de6eae1f
YR		 12637 * Hold it as vars low
12638 */
d231023e 12639 /* Clear link led */
55386fe8 12640 bnx2x_set_mdio_emac_per_phy(bp, params);
7f02c4ad
YR		 12641 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12642
de6eae1f
YR		 12643 if (reset_ext_phy) {
12644 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12645 phy_index++) {
28f4881c
YR		 12646 if (params->phy[phy_index].link_reset) {
12647 bnx2x_set_aer_mmd(params,
12648 &params->phy[phy_index]);
de6eae1f
YR		 12649 params->phy[phy_index].link_reset(
12650 &params->phy[phy_index],
12651 params);
28f4881c 12652 }
cf1d972c
YR		 12653 if (params->phy[phy_index].flags &
12654 FLAGS_REARM_LATCH_SIGNAL)
12655 clear_latch_ind = 1;
b7737c9b 12656 }
b7737c9b
YR		 12657 }
12658
cf1d972c
YR		 12659 if (clear_latch_ind) {
12660 /* Clear latching indication */
12661 bnx2x_rearm_latch_signal(bp, port, 0);
12662 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12663 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12664 }
de6eae1f
YR		 12665 if (params->phy[INT_PHY].link_reset)
12666 params->phy[INT_PHY].link_reset(
12667 &params->phy[INT_PHY], params);
b7737c9b 12668
d231023e 12669 /* Disable nig ingress interface */
9380bb9e 12670 if (!CHIP_IS_E3(bp)) {
d231023e 12671 /* Reset BigMac */
ce7c0489
YR		 12672 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12673 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
9380bb9e
YR		 12674 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12675 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
ce7c0489
YR		 12676 } else {
12677 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12678 bnx2x_set_xumac_nig(params, 0, 0);
12679 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12680 MISC_REGISTERS_RESET_REG_2_XMAC)
12681 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12682 XMAC_CTRL_REG_SOFT_RESET);
9380bb9e 12683 }
de6eae1f 12684 vars->link_up = 0;
3c9ada22 12685 vars->phy_flags = 0;
b7737c9b
YR		 12686 return 0;
12687}
d3a8f13b
YR		 12688int bnx2x_lfa_reset(struct link_params *params,
12689 struct link_vars *vars)
12690{
12691 struct bnx2x *bp = params->bp;
12692 vars->link_up = 0;
12693 vars->phy_flags = 0;
12694 if (!params->lfa_base)
12695 return bnx2x_link_reset(params, vars, 1);
12696 /*
12697 * Activate NIG drain so that during this time the device won't send
12698 * anything while it is unable to response.
12699 */
12700 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12701
12702 /*
12703 * Close gracefully the gate from BMAC to NIG such that no half packets
12704 * are passed.
12705 */
12706 if (!CHIP_IS_E3(bp))
12707 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12708
12709 if (CHIP_IS_E3(bp)) {
12710 bnx2x_set_xmac_rxtx(params, 0);
12711 bnx2x_set_umac_rxtx(params, 0);
12712 }
12713 /* Wait 10ms for the pipe to clean up*/
12714 usleep_range(10000, 20000);
12715
12716 /* Clean the NIG-BRB using the network filters in a way that will
12717 * not cut a packet in the middle.
12718 */
12719 bnx2x_set_rx_filter(params, 0);
12720
12721 /*
12722 * Re-open the gate between the BMAC and the NIG, after verifying the
12723 * gate to the BRB is closed, otherwise packets may arrive to the
12724 * firmware before driver had initialized it. The target is to achieve
12725 * minimum management protocol down time.
12726 */
12727 if (!CHIP_IS_E3(bp))
12728 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12729
12730 if (CHIP_IS_E3(bp)) {
12731 bnx2x_set_xmac_rxtx(params, 1);
12732 bnx2x_set_umac_rxtx(params, 1);
12733 }
12734 /* Disable NIG drain */
12735 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12736 return 0;
12737}
b7737c9b 12738
de6eae1f
YR		 12739/****************************************************************************/
12740/* Common function */
12741/****************************************************************************/
fcf5b650
YR		 12742static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12743 u32 shmem_base_path[],
12744 u32 shmem2_base_path[], u8 phy_index,
12745 u32 chip_id)
6bbca910 12746{
e10bc84d
YR		 12747 struct bnx2x_phy phy[PORT_MAX];
12748 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910 12749 u16 val;
c8e64df4 12750 s8 port = 0;
f2e0899f 12751 s8 port_of_path = 0;
c8e64df4
YR		 12752 u32 swap_val, swap_override;
12753 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12754 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12755 port ^= (swap_val && swap_override);
12756 bnx2x_ext_phy_hw_reset(bp, port);
6bbca910
YR		 12757 /* PART1 - Reset both phys */
12758 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 12759 u32 shmem_base, shmem2_base;
12760 /* In E2, same phy is using for port0 of the two paths */
3c9ada22 12761 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 12762 shmem_base = shmem_base_path[0];
12763 shmem2_base = shmem2_base_path[0];
12764 port_of_path = port;
3c9ada22
YR		 12765 } else {
12766 shmem_base = shmem_base_path[port];
12767 shmem2_base = shmem2_base_path[port];
12768 port_of_path = 0;
f2e0899f
DK		 12769 }
12770
6bbca910 12771 /* Extract the ext phy address for the port */
a22f0788 12772 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 12773 port_of_path, &phy[port]) !=
e10bc84d
YR		 12774 0) {
12775 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12776 return -EINVAL;
12777 }
d231023e 12778 /* Disable attentions */
6a71bbe0
YR		 12779 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12780 port_of_path*4,
cd88ccee
YR		 12781 (NIG_MASK_XGXS0_LINK_STATUS |
12782 NIG_MASK_XGXS0_LINK10G |
12783 NIG_MASK_SERDES0_LINK_STATUS |
12784 NIG_MASK_MI_INT));
6bbca910 12785
6bbca910 12786 /* Need to take the phy out of low power mode in order
8f73f0b9
YR		 12787 * to write to access its registers
12788 */
6bbca910 12789 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 12790 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12791 port);
6bbca910
YR		 12792
12793 /* Reset the phy */
e10bc84d 12794 bnx2x_cl45_write(bp, &phy[port],
cd88ccee
YR		 12795 MDIO_PMA_DEVAD,
12796 MDIO_PMA_REG_CTRL,
12797 1<<15);
6bbca910
YR		 12798 }
12799
12800 /* Add delay of 150ms after reset */
12801 msleep(150);
12802
e10bc84d
YR		 12803 if (phy[PORT_0].addr & 0x1) {
12804 phy_blk[PORT_0] = &(phy[PORT_1]);
12805 phy_blk[PORT_1] = &(phy[PORT_0]);
12806 } else {
12807 phy_blk[PORT_0] = &(phy[PORT_0]);
12808 phy_blk[PORT_1] = &(phy[PORT_1]);
12809 }
12810
6bbca910
YR		 12811 /* PART2 - Download firmware to both phys */
12812 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
3c9ada22 12813 if (CHIP_IS_E1x(bp))
f2e0899f 12814 port_of_path = port;
3c9ada22
YR		 12815 else
12816 port_of_path = 0;
6bbca910 12817
f2e0899f
DK		 12818 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12819 phy_blk[port]->addr);
5c99274b
YR		 12820 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12821 port_of_path))
6bbca910 12822 return -EINVAL;
6bbca910
YR		 12823
12824 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 12825 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 12826 MDIO_PMA_DEVAD,
12827 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910
YR		 12828
12829 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 12830 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 12831 MDIO_PMA_DEVAD,
12832 MDIO_PMA_REG_TX_POWER_DOWN,
12833 (val | 1<<10));
6bbca910
YR		 12834 }
12835
8f73f0b9 12836 /* Toggle Transmitter: Power down and then up with 600ms delay
2cf7acf9
YR		 12837 * between
12838 */
6bbca910
YR		 12839 msleep(600);
12840
12841 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12842 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 12843 /* Phase2 of POWER_DOWN_RESET */
6bbca910 12844 /* Release bit 10 (Release Tx power down) */
e10bc84d 12845 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 12846 MDIO_PMA_DEVAD,
12847 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910 12848
e10bc84d 12849 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 12850 MDIO_PMA_DEVAD,
12851 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
d231023e 12852 usleep_range(15000, 30000);
6bbca910
YR		 12853
12854 /* Read modify write the SPI-ROM version select register */
e10bc84d 12855 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 12856 MDIO_PMA_DEVAD,
12857 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 12858 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 12859 MDIO_PMA_DEVAD,
12860 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6bbca910
YR		 12861
12862 /* set GPIO2 back to LOW */
12863 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 12864 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6bbca910
YR		 12865 }
12866 return 0;
6bbca910 12867}
fcf5b650
YR		 12868static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12869 u32 shmem_base_path[],
12870 u32 shmem2_base_path[], u8 phy_index,
12871 u32 chip_id)
de6eae1f
YR		 12872{
12873 u32 val;
12874 s8 port;
12875 struct bnx2x_phy phy;
12876 /* Use port1 because of the static port-swap */
12877 /* Enable the module detection interrupt */
12878 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12879 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12880 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12881 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12882
650154bf 12883 bnx2x_ext_phy_hw_reset(bp, 0);
d231023e 12884 usleep_range(5000, 10000);
de6eae1f 12885 for (port = 0; port < PORT_MAX; port++) {
f2e0899f
DK		 12886 u32 shmem_base, shmem2_base;
12887
12888 /* In E2, same phy is using for port0 of the two paths */
3c9ada22 12889 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 12890 shmem_base = shmem_base_path[0];
12891 shmem2_base = shmem2_base_path[0];
3c9ada22
YR		 12892 } else {
12893 shmem_base = shmem_base_path[port];
12894 shmem2_base = shmem2_base_path[port];
f2e0899f 12895 }
de6eae1f 12896 /* Extract the ext phy address for the port */
a22f0788 12897 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 12898 port, &phy) !=
12899 0) {
12900 DP(NETIF_MSG_LINK, "populate phy failed\n");
12901 return -EINVAL;
12902 }
12903
12904 /* Reset phy*/
12905 bnx2x_cl45_write(bp, &phy,
12906 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12907
12908
12909 /* Set fault module detected LED on */
12910 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
cd88ccee
YR		 12911 MISC_REGISTERS_GPIO_HIGH,
12912 port);
de6eae1f
YR		 12913 }
12914
12915 return 0;
12916}
a8db5b4c
YR		 12917static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12918 u8 *io_gpio, u8 *io_port)
12919{
12920
12921 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12922 offsetof(struct shmem_region,
12923 dev_info.port_hw_config[PORT_0].default_cfg));
12924 switch (phy_gpio_reset) {
12925 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12926 *io_gpio = 0;
12927 *io_port = 0;
12928 break;
12929 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12930 *io_gpio = 1;
12931 *io_port = 0;
12932 break;
12933 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12934 *io_gpio = 2;
12935 *io_port = 0;
12936 break;
12937 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12938 *io_gpio = 3;
12939 *io_port = 0;
12940 break;
12941 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12942 *io_gpio = 0;
12943 *io_port = 1;
12944 break;
12945 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12946 *io_gpio = 1;
12947 *io_port = 1;
12948 break;
12949 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12950 *io_gpio = 2;
12951 *io_port = 1;
12952 break;
12953 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12954 *io_gpio = 3;
12955 *io_port = 1;
12956 break;
12957 default:
12958 /* Don't override the io_gpio and io_port */
12959 break;
12960 }
12961}
fcf5b650
YR		 12962
12963static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12964 u32 shmem_base_path[],
12965 u32 shmem2_base_path[], u8 phy_index,
12966 u32 chip_id)
4d295db0 12967{
a8db5b4c 12968 s8 port, reset_gpio;
4d295db0 12969 u32 swap_val, swap_override;
e10bc84d
YR		 12970 struct bnx2x_phy phy[PORT_MAX];
12971 struct bnx2x_phy *phy_blk[PORT_MAX];
f2e0899f 12972 s8 port_of_path;
cd88ccee
YR		 12973 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12974 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4d295db0 12975
a8db5b4c 12976 reset_gpio = MISC_REGISTERS_GPIO_1;
a22f0788 12977 port = 1;
4d295db0 12978
8f73f0b9 12979 /* Retrieve the reset gpio/port which control the reset.
a8db5b4c
YR		 12980 * Default is GPIO1, PORT1
12981 */
12982 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12983 (u8 *)&reset_gpio, (u8 *)&port);
a22f0788
YR		 12984
12985 /* Calculate the port based on port swap */
12986 port ^= (swap_val && swap_override);
12987
a8db5b4c
YR		 12988 /* Initiate PHY reset*/
12989 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12990 port);
503976e9 12991 usleep_range(1000, 2000);
a8db5b4c
YR		 12992 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12993 port);
12994
d231023e 12995 usleep_range(5000, 10000);
bc7f0a05 12996
4d295db0 12997 /* PART1 - Reset both phys */
a22f0788 12998 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 12999 u32 shmem_base, shmem2_base;
13000
13001 /* In E2, same phy is using for port0 of the two paths */
3c9ada22 13002 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 13003 shmem_base = shmem_base_path[0];
13004 shmem2_base = shmem2_base_path[0];
13005 port_of_path = port;
3c9ada22
YR		 13006 } else {
13007 shmem_base = shmem_base_path[port];
13008 shmem2_base = shmem2_base_path[port];
13009 port_of_path = 0;
f2e0899f
DK		 13010 }
13011
4d295db0 13012 /* Extract the ext phy address for the port */
a22f0788 13013 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 13014 port_of_path, &phy[port]) !=
e10bc84d
YR		 13015 0) {
13016 DP(NETIF_MSG_LINK, "populate phy failed\n");
13017 return -EINVAL;
13018 }
4d295db0 13019 /* disable attentions */
f2e0899f
DK		 13020 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13021 port_of_path*4,
13022 (NIG_MASK_XGXS0_LINK_STATUS |
13023 NIG_MASK_XGXS0_LINK10G |
13024 NIG_MASK_SERDES0_LINK_STATUS |
13025 NIG_MASK_MI_INT));
4d295db0 13026
4d295db0
EG		 13027
13028 /* Reset the phy */
e10bc84d 13029 bnx2x_cl45_write(bp, &phy[port],
cd88ccee 13030 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
4d295db0
EG		 13031 }
13032
13033 /* Add delay of 150ms after reset */
13034 msleep(150);
e10bc84d
YR		 13035 if (phy[PORT_0].addr & 0x1) {
13036 phy_blk[PORT_0] = &(phy[PORT_1]);
13037 phy_blk[PORT_1] = &(phy[PORT_0]);
13038 } else {
13039 phy_blk[PORT_0] = &(phy[PORT_0]);
13040 phy_blk[PORT_1] = &(phy[PORT_1]);
13041 }
4d295db0 13042 /* PART2 - Download firmware to both phys */
e10bc84d 13043 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
3c9ada22 13044 if (CHIP_IS_E1x(bp))
f2e0899f 13045 port_of_path = port;
3c9ada22
YR		 13046 else
13047 port_of_path = 0;
f2e0899f
DK		 13048 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13049 phy_blk[port]->addr);
5c99274b
YR		 13050 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13051 port_of_path))
4d295db0 13052 return -EINVAL;
85242eea
YR		 13053 /* Disable PHY transmitter output */
13054 bnx2x_cl45_write(bp, phy_blk[port],
13055 MDIO_PMA_DEVAD,
13056 MDIO_PMA_REG_TX_DISABLE, 1);
4d295db0 13057
5c99274b 13058 }
4d295db0
EG		 13059 return 0;
13060}
13061
521683da
YR		 13062static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13063 u32 shmem_base_path[],
13064 u32 shmem2_base_path[],
13065 u8 phy_index,
13066 u32 chip_id)
13067{
13068 u8 reset_gpios;
521683da
YR		 13069 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13070 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13071 udelay(10);
13072 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13073 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13074 reset_gpios);
11b2ec6b
YR		 13075 return 0;
13076}
521683da 13077
fcf5b650
YR		 13078static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13079 u32 shmem2_base_path[], u8 phy_index,
13080 u32 ext_phy_type, u32 chip_id)
6bbca910 13081{
fcf5b650 13082 int rc = 0;
6bbca910
YR		 13083
13084 switch (ext_phy_type) {
13085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
f2e0899f
DK		 13086 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13087 shmem2_base_path,
13088 phy_index, chip_id);
6bbca910 13089 break;
e4d78f12 13090 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4d295db0
EG		 13091 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13092 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
f2e0899f
DK		 13093 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13094 shmem2_base_path,
13095 phy_index, chip_id);
4d295db0
EG		 13096 break;
13097
589abe3a 13098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8f73f0b9 13099 /* GPIO1 affects both ports, so there's need to pull
2cf7acf9
YR		 13100 * it for single port alone
13101 */
f2e0899f
DK		 13102 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13103 shmem2_base_path,
13104 phy_index, chip_id);
a22f0788 13105 break;
0d40f0d4 13106 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
0f6bb03d 13107 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
8f73f0b9 13108 /* GPIO3's are linked, and so both need to be toggled
0d40f0d4
YR		 13109 * to obtain required 2us pulse.
13110 */
521683da
YR		 13111 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13112 shmem2_base_path,
13113 phy_index, chip_id);
0d40f0d4 13114 break;
a22f0788
YR		 13115 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13116 rc = -EINVAL;
4f60dab1 13117 break;
6bbca910
YR		 13118 default:
13119 DP(NETIF_MSG_LINK,
2cf7acf9
YR		 13120 "ext_phy 0x%x common init not required\n",
13121 ext_phy_type);
6bbca910
YR		 13122 break;
13123 }
13124
d231023e 13125 if (rc)
6d870c39
YR		 13126 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13127 " Port %d\n",
13128 0);
6bbca910
YR		 13129 return rc;
13130}
13131
fcf5b650
YR		 13132int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13133 u32 shmem2_base_path[], u32 chip_id)
a22f0788 13134{
fcf5b650 13135 int rc = 0;
3c9ada22
YR		 13136 u32 phy_ver, val;
13137 u8 phy_index = 0;
a22f0788 13138 u32 ext_phy_type, ext_phy_config;
55386fe8
YR		 13139
13140 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13141 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
a22f0788 13142 DP(NETIF_MSG_LINK, "Begin common phy init\n");
3c9ada22
YR		 13143 if (CHIP_IS_E3(bp)) {
13144 /* Enable EPIO */
13145 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13146 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13147 }
b21a3424
YR		 13148 /* Check if common init was already done */
13149 phy_ver = REG_RD(bp, shmem_base_path[0] +
13150 offsetof(struct shmem_region,
13151 port_mb[PORT_0].ext_phy_fw_version));
13152 if (phy_ver) {
13153 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13154 phy_ver);
13155 return 0;
13156 }
13157
a22f0788
YR		 13158 /* Read the ext_phy_type for arbitrary port(0) */
13159 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13160 phy_index++) {
13161 ext_phy_config = bnx2x_get_ext_phy_config(bp,
f2e0899f 13162 shmem_base_path[0],
a22f0788
YR		 13163 phy_index, 0);
13164 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
f2e0899f
DK		 13165 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13166 shmem2_base_path,
13167 phy_index, ext_phy_type,
13168 chip_id);
a22f0788
YR		 13169 }
13170 return rc;
13171}
d90d96ba 13172
3deb8167
YR		 13173static void bnx2x_check_over_curr(struct link_params *params,
13174 struct link_vars *vars)
13175{
13176 struct bnx2x *bp = params->bp;
13177 u32 cfg_pin;
13178 u8 port = params->port;
13179 u32 pin_val;
13180
13181 cfg_pin = (REG_RD(bp, params->shmem_base +
13182 offsetof(struct shmem_region,
13183 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13184 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13185 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13186
13187 /* Ignore check if no external input PIN available */
13188 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13189 return;
13190
13191 if (!pin_val) {
13192 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13193 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13194 " been detected and the power to "
13195 "that SFP+ module has been removed"
13196 " to prevent failure of the card."
13197 " Please remove the SFP+ module and"
13198 " restart the system to clear this"
13199 " error.\n",
13200 params->port);
13201 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
5a1fbf40 13202 bnx2x_warpcore_power_module(params, 0);
3deb8167
YR		 13203 }
13204 } else
13205 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13206}
13207
d0b8a6f9
YM		 13208/* Returns 0 if no change occured since last check; 1 otherwise. */
13209static u8 bnx2x_analyze_link_error(struct link_params *params,
13210 struct link_vars *vars, u32 status,
13211 u32 phy_flag, u32 link_flag, u8 notify)
3deb8167
YR		 13212{
13213 struct bnx2x *bp = params->bp;
13214 /* Compare new value with previous value */
13215 u8 led_mode;
d0b8a6f9 13216 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
3deb8167 13217
d0b8a6f9
YM		 13218 if ((status ^ old_status) == 0)
13219 return 0;
3deb8167
YR		 13220
13221 /* If values differ */
d0b8a6f9
YM		 13222 switch (phy_flag) {
13223 case PHY_HALF_OPEN_CONN_FLAG:
13224 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13225 break;
13226 case PHY_SFP_TX_FAULT_FLAG:
13227 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13228 break;
13229 default:
efc7ce03 13230 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
d0b8a6f9
YM		 13231 }
13232 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13233 old_status, status);
3deb8167 13234
8f73f0b9 13235 /* a. Update shmem->link_status accordingly
3deb8167
YR		 13236 * b. Update link_vars->link_up
13237 */
d0b8a6f9 13238 if (status) {
3deb8167 13239 vars->link_status &= ~LINK_STATUS_LINK_UP;
d0b8a6f9 13240 vars->link_status |= link_flag;
3deb8167 13241 vars->link_up = 0;
d0b8a6f9 13242 vars->phy_flags |= phy_flag;
55098c5c
YR		 13243
13244 /* activate nig drain */
13245 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
8f73f0b9 13246 /* Set LED mode to off since the PHY doesn't know about these
3deb8167
YR		 13247 * errors
13248 */
13249 led_mode = LED_MODE_OFF;
13250 } else {
13251 vars->link_status |= LINK_STATUS_LINK_UP;
d0b8a6f9 13252 vars->link_status &= ~link_flag;
3deb8167 13253 vars->link_up = 1;
d0b8a6f9 13254 vars->phy_flags &= ~phy_flag;
3deb8167 13255 led_mode = LED_MODE_OPER;
55098c5c
YR		 13256
13257 /* Clear nig drain */
13258 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
3deb8167 13259 }
55098c5c 13260 bnx2x_sync_link(params, vars);
3deb8167
YR		 13261 /* Update the LED according to the link state */
13262 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13263
13264 /* Update link status in the shared memory */
13265 bnx2x_update_mng(params, vars->link_status);
13266
13267 /* C. Trigger General Attention */
13268 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
55098c5c
YR		 13269 if (notify)
13270 bnx2x_notify_link_changed(bp);
d0b8a6f9
YM		 13271
13272 return 1;
3deb8167
YR		 13273}
13274
de6f3377
YR		 13275/******************************************************************************
13276* Description:
13277* This function checks for half opened connection change indication.
13278* When such change occurs, it calls the bnx2x_analyze_link_error
13279* to check if Remote Fault is set or cleared. Reception of remote fault
13280* status message in the MAC indicates that the peer's MAC has detected
13281* a fault, for example, due to break in the TX side of fiber.
13282*
13283******************************************************************************/
55098c5c
YR		 13284int bnx2x_check_half_open_conn(struct link_params *params,
13285 struct link_vars *vars,
13286 u8 notify)
3deb8167
YR		 13287{
13288 struct bnx2x *bp = params->bp;
13289 u32 lss_status = 0;
13290 u32 mac_base;
13291 /* In case link status is physically up @ 10G do */
55098c5c
YR		 13292 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13293 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13294 return 0;
3deb8167 13295
de6f3377 13296 if (CHIP_IS_E3(bp) &&
3deb8167 13297 (REG_RD(bp, MISC_REG_RESET_REG_2) &
de6f3377
YR		 13298 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13299 /* Check E3 XMAC */
8f73f0b9 13300 /* Note that link speed cannot be queried here, since it may be
de6f3377
YR		 13301 * zero while link is down. In case UMAC is active, LSS will
13302 * simply not be set
13303 */
13304 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13305
13306 /* Clear stick bits (Requires rising edge) */
13307 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13308 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13309 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13310 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13311 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13312 lss_status = 1;
13313
d0b8a6f9
YM		 13314 bnx2x_analyze_link_error(params, vars, lss_status,
13315 PHY_HALF_OPEN_CONN_FLAG,
13316 LINK_STATUS_NONE, notify);
de6f3377
YR		 13317 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13318 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
3deb8167
YR		 13319 /* Check E1X / E2 BMAC */
13320 u32 lss_status_reg;
13321 u32 wb_data[2];
13322 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13323 NIG_REG_INGRESS_BMAC0_MEM;
13324 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13325 if (CHIP_IS_E2(bp))
13326 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13327 else
13328 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13329
13330 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13331 lss_status = (wb_data[0] > 0);
13332
d0b8a6f9
YM		 13333 bnx2x_analyze_link_error(params, vars, lss_status,
13334 PHY_HALF_OPEN_CONN_FLAG,
13335 LINK_STATUS_NONE, notify);
3deb8167 13336 }
55098c5c 13337 return 0;
3deb8167 13338}
d0b8a6f9
YM		 13339static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13340 struct link_params *params,
13341 struct link_vars *vars)
13342{
13343 struct bnx2x *bp = params->bp;
13344 u32 cfg_pin, value = 0;
13345 u8 led_change, port = params->port;
3deb8167 13346
d0b8a6f9
YM		 13347 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13348 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13349 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13350 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13351 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13352
13353 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13354 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13355 return;
13356 }
13357
13358 led_change = bnx2x_analyze_link_error(params, vars, value,
13359 PHY_SFP_TX_FAULT_FLAG,
13360 LINK_STATUS_SFP_TX_FAULT, 1);
13361
13362 if (led_change) {
13363 /* Change TX_Fault led, set link status for further syncs */
13364 u8 led_mode;
13365
13366 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13367 led_mode = MISC_REGISTERS_GPIO_HIGH;
13368 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13369 } else {
13370 led_mode = MISC_REGISTERS_GPIO_LOW;
13371 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13372 }
13373
13374 /* If module is unapproved, led should be on regardless */
13375 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13376 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13377 led_mode);
13378 bnx2x_set_e3_module_fault_led(params, led_mode);
13379 }
13380 }
13381}
4e7b4997
YR		 13382static void bnx2x_disable_kr2(struct link_params *params,
13383 struct link_vars *vars,
13384 struct bnx2x_phy *phy)
13385{
13386 struct bnx2x *bp = params->bp;
13387 int i;
13388 static struct bnx2x_reg_set reg_set[] = {
13389 /* Step 1 - Program the TX/RX alignment markers */
13390 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13391 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13392 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13393 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13394 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13395 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13396 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13397 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13398 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13399 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13400 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13401 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13402 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13403 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13404 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13405 };
13406 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13407
b5a05550 13408 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4e7b4997
YR		 13409 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13410 reg_set[i].val);
13411 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13412 bnx2x_update_link_attr(params, vars->link_attr_sync);
13413
13414 /* Restart AN on leading lane */
13415 bnx2x_warpcore_restart_AN_KR(phy, params);
13416}
13417
13418static void bnx2x_kr2_recovery(struct link_params *params,
13419 struct link_vars *vars,
13420 struct bnx2x_phy *phy)
13421{
13422 struct bnx2x *bp = params->bp;
13423 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13424 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13425 bnx2x_warpcore_restart_AN_KR(phy, params);
13426}
13427
13428static void bnx2x_check_kr2_wa(struct link_params *params,
13429 struct link_vars *vars,
13430 struct bnx2x_phy *phy)
13431{
13432 struct bnx2x *bp = params->bp;
13433 u16 base_page, next_page, not_kr2_device, lane;
13434 int sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13435
13436 if (!sigdet) {
13437 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
13438 bnx2x_kr2_recovery(params, vars, phy);
13439 return;
13440 }
13441
13442 lane = bnx2x_get_warpcore_lane(phy, params);
13443 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13444 MDIO_AER_BLOCK_AER_REG, lane);
13445 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13446 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13447 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13448 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13449 bnx2x_set_aer_mmd(params, phy);
13450
13451 /* CL73 has not begun yet */
13452 if (base_page == 0) {
13453 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE))
13454 bnx2x_kr2_recovery(params, vars, phy);
13455 return;
13456 }
13457
13458 /* In case NP bit is not set in the BasePage, or it is set,
13459 * but only KX is advertised, declare this link partner as non-KR2
13460 * device.
13461 */
13462 not_kr2_device = (((base_page & 0x8000) == 0) ||
13463 (((base_page & 0x8000) &&
13464 ((next_page & 0xe0) == 0x2))));
13465
13466 /* In case KR2 is already disabled, check if we need to re-enable it */
13467 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13468 if (!not_kr2_device) {
13469 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
fd5dfca7 13470 next_page);
4e7b4997
YR		 13471 bnx2x_kr2_recovery(params, vars, phy);
13472 }
13473 return;
13474 }
13475 /* KR2 is enabled, but not KR2 device */
13476 if (not_kr2_device) {
13477 /* Disable KR2 on both lanes */
13478 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13479 bnx2x_disable_kr2(params, vars, phy);
13480 return;
13481 }
13482}
13483
3deb8167
YR		 13484void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13485{
de6f3377 13486 u16 phy_idx;
55098c5c 13487 struct bnx2x *bp = params->bp;
de6f3377
YR		 13488 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13489 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13490 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
55098c5c
YR		 13491 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13492 0)
13493 DP(NETIF_MSG_LINK, "Fault detection failed\n");
de6f3377
YR		 13494 break;
13495 }
13496 }
13497
a9077bfd
YR		 13498 if (CHIP_IS_E3(bp)) {
13499 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13500 bnx2x_set_aer_mmd(params, phy);
4e7b4997
YR		 13501 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13502 (phy->speed_cap_mask & SPEED_20000))
13503 bnx2x_check_kr2_wa(params, vars, phy);
3deb8167 13504 bnx2x_check_over_curr(params, vars);
d0b8a6f9
YM		 13505 if (vars->rx_tx_asic_rst)
13506 bnx2x_warpcore_config_runtime(phy, params, vars);
13507
13508 if ((REG_RD(bp, params->shmem_base +
13509 offsetof(struct shmem_region, dev_info.
13510 port_hw_config[params->port].default_cfg))
13511 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13512 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13513 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13514 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13515 } else if (vars->link_status &
13516 LINK_STATUS_SFP_TX_FAULT) {
13517 /* Clean trail, interrupt corrects the leds */
13518 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13519 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13520 /* Update link status in the shared memory */
13521 bnx2x_update_mng(params, vars->link_status);
13522 }
13523 }
a9077bfd 13524 }
3deb8167
YR		 13525}
13526
d90d96ba
YR		 13527u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13528 u32 shmem_base,
a22f0788 13529 u32 shmem2_base,
d90d96ba
YR		 13530 u8 port)
13531{
13532 u8 phy_index, fan_failure_det_req = 0;
13533 struct bnx2x_phy phy;
13534 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13535 phy_index++) {
a22f0788 13536 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 13537 port, &phy)
13538 != 0) {
13539 DP(NETIF_MSG_LINK, "populate phy failed\n");
13540 return 0;
13541 }
13542 fan_failure_det_req |= (phy.flags &
13543 FLAGS_FAN_FAILURE_DET_REQ);
13544 }
13545 return fan_failure_det_req;
13546}
13547
13548void bnx2x_hw_reset_phy(struct link_params *params)
13549{
13550 u8 phy_index;
985848f8
YR		 13551 struct bnx2x *bp = params->bp;
13552 bnx2x_update_mng(params, 0);
13553 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13554 (NIG_MASK_XGXS0_LINK_STATUS |
13555 NIG_MASK_XGXS0_LINK10G |
13556 NIG_MASK_SERDES0_LINK_STATUS |
13557 NIG_MASK_MI_INT));
13558
13559 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
d90d96ba
YR		 13560 phy_index++) {
13561 if (params->phy[phy_index].hw_reset) {
13562 params->phy[phy_index].hw_reset(
13563 &params->phy[phy_index],
13564 params);
13565 params->phy[phy_index] = phy_null;
13566 }
13567 }
13568}
020c7e3f
YR		 13569
13570void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13571 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13572 u8 port)
13573{
13574 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13575 u32 val;
13576 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
3c9ada22
YR		 13577 if (CHIP_IS_E3(bp)) {
13578 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13579 shmem_base,
13580 port,
13581 &gpio_num,
13582 &gpio_port) != 0)
13583 return;
13584 } else {
020c7e3f
YR		 13585 struct bnx2x_phy phy;
13586 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13587 phy_index++) {
13588 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13589 shmem2_base, port, &phy)
13590 != 0) {
13591 DP(NETIF_MSG_LINK, "populate phy failed\n");
13592 return;
13593 }
13594 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13595 gpio_num = MISC_REGISTERS_GPIO_3;
13596 gpio_port = port;
13597 break;
13598 }
13599 }
13600 }
13601
13602 if (gpio_num == 0xff)
13603 return;
13604
13605 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13606 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13607
13608 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13609 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13610 gpio_port ^= (swap_val && swap_override);
13611
13612 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13613 (gpio_num + (gpio_port << 2));
13614
13615 sync_offset = shmem_base +
13616 offsetof(struct shmem_region,
13617 dev_info.port_hw_config[port].aeu_int_mask);
13618 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13619
13620 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13621 gpio_num, gpio_port, vars->aeu_int_mask);
13622
13623 if (port == 0)
13624 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13625 else
13626 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13627
13628 /* Open appropriate AEU for interrupts */
13629 aeu_mask = REG_RD(bp, offset);
13630 aeu_mask |= vars->aeu_int_mask;
13631 REG_WR(bp, offset, aeu_mask);
13632
13633 /* Enable the GPIO to trigger interrupt */
13634 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13635 val |= 1 << (gpio_num + (gpio_port << 2));
13636 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13637}
kernel source for telekom puls (alcatel/mediatek)