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85b26ea1 | 1 | /* Copyright 2008-2012 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a | 27 | #include "bnx2x.h" |
619c5cb6 VZ |
28 | #include "bnx2x_cmn.h" |
29 | ||
ea4e040a | 30 | /********************************************************/ |
3196a88a | 31 | #define ETH_HLEN 14 |
cd88ccee YR |
32 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
33 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
ea4e040a YR |
34 | #define ETH_MIN_PACKET_SIZE 60 |
35 | #define ETH_MAX_PACKET_SIZE 1500 | |
36 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
37 | #define MDIO_ACCESS_TIMEOUT 1000 | |
3c9ada22 YR |
38 | #define WC_LANE_MAX 4 |
39 | #define I2C_SWITCH_WIDTH 2 | |
40 | #define I2C_BSC0 0 | |
41 | #define I2C_BSC1 1 | |
42 | #define I2C_WA_RETRY_CNT 3 | |
50a29845 | 43 | #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) |
3c9ada22 YR |
44 | #define MCPR_IMC_COMMAND_READ_OP 1 |
45 | #define MCPR_IMC_COMMAND_WRITE_OP 2 | |
ea4e040a | 46 | |
26ffaf36 YR |
47 | /* LED Blink rate that will achieve ~15.9Hz */ |
48 | #define LED_BLINK_RATE_VAL_E3 354 | |
49 | #define LED_BLINK_RATE_VAL_E1X_E2 480 | |
ea4e040a | 50 | /***********************************************************/ |
3196a88a | 51 | /* Shortcut definitions */ |
ea4e040a YR |
52 | /***********************************************************/ |
53 | ||
2f904460 EG |
54 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
55 | ||
56 | #define NIG_STATUS_EMAC0_MI_INT \ | |
57 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
58 | #define NIG_STATUS_XGXS0_LINK10G \ |
59 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
60 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
61 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
62 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
63 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
64 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
65 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
66 | #define NIG_MASK_MI_INT \ | |
67 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
68 | #define NIG_MASK_XGXS0_LINK10G \ | |
69 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
70 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
71 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
72 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
73 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
74 | ||
75 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
76 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
77 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
78 | ||
79 | #define XGXS_RESET_BITS \ | |
80 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
81 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
82 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
83 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
84 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
85 | ||
86 | #define SERDES_RESET_BITS \ | |
87 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
88 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
89 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
90 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
91 | ||
92 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
93 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
cd88ccee | 94 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
3196a88a | 95 | #define AUTONEG_PARALLEL \ |
ea4e040a | 96 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 97 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 98 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 99 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
100 | |
101 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
102 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
103 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
104 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
105 | #define GP_STATUS_SPEED_MASK \ | |
106 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
107 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
108 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
109 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
110 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
111 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
112 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
113 | #define GP_STATUS_10G_HIG \ | |
114 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
115 | #define GP_STATUS_10G_CX4 \ | |
116 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
ea4e040a YR |
117 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
118 | #define GP_STATUS_10G_KX4 \ | |
119 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
3c9ada22 YR |
120 | #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR |
121 | #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI | |
122 | #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS | |
123 | #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI | |
cd88ccee YR |
124 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
125 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
ea4e040a | 126 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
cd88ccee | 127 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
ea4e040a YR |
128 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
129 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
130 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
131 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
132 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
133 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
134 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
cd88ccee YR |
135 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
136 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
3c9ada22 YR |
137 | #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD |
138 | #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD | |
6583e33b YR |
139 | |
140 | ||
141 | ||
589abe3a | 142 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 |
cd88ccee | 143 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
589abe3a EG |
144 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
145 | ||
4d295db0 EG |
146 | |
147 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
148 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
149 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
150 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
151 | ||
589abe3a EG |
152 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
153 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
cd88ccee | 154 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
4d295db0 | 155 | |
cd88ccee | 156 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
589abe3a | 157 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
cd88ccee | 158 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
589abe3a | 159 | |
cd88ccee YR |
160 | #define EDC_MODE_LINEAR 0x0022 |
161 | #define EDC_MODE_LIMITING 0x0044 | |
162 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
4d295db0 | 163 | |
866cedae YR |
164 | /* BRB default for class 0 E2 */ |
165 | #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170 | |
166 | #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250 | |
167 | #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10 | |
168 | #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50 | |
4d295db0 | 169 | |
9380bb9e YR |
170 | /* BRB thresholds for E2*/ |
171 | #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170 | |
172 | #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
173 | ||
174 | #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250 | |
175 | #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
176 | ||
177 | #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
178 | #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90 | |
179 | ||
180 | #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
181 | #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250 | |
182 | ||
866cedae YR |
183 | /* BRB default for class 0 E3A0 */ |
184 | #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290 | |
185 | #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410 | |
186 | #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10 | |
187 | #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50 | |
188 | ||
9380bb9e YR |
189 | /* BRB thresholds for E3A0 */ |
190 | #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290 | |
191 | #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
192 | ||
193 | #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410 | |
194 | #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
195 | ||
196 | #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
197 | #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170 | |
198 | ||
199 | #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
200 | #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410 | |
201 | ||
866cedae YR |
202 | /* BRB default for E3B0 */ |
203 | #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330 | |
204 | #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490 | |
205 | #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15 | |
206 | #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55 | |
9380bb9e YR |
207 | |
208 | /* BRB thresholds for E3B0 2 port mode*/ | |
209 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025 | |
210 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
211 | ||
212 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025 | |
213 | #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
214 | ||
215 | #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
216 | #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025 | |
217 | ||
218 | #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
219 | #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025 | |
220 | ||
221 | /* only for E3B0*/ | |
222 | #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025 | |
223 | #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025 | |
224 | ||
225 | /* Lossy +Lossless GUARANTIED == GUART */ | |
226 | #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284 | |
227 | /* Lossless +Lossless*/ | |
228 | #define PFC_E3B0_2P_PAUSE_LB_GUART 236 | |
229 | /* Lossy +Lossy*/ | |
230 | #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342 | |
231 | ||
232 | /* Lossy +Lossless*/ | |
233 | #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284 | |
234 | /* Lossless +Lossless*/ | |
235 | #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236 | |
236 | /* Lossy +Lossy*/ | |
237 | #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336 | |
238 | #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80 | |
239 | ||
240 | #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0 | |
241 | #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0 | |
242 | ||
243 | /* BRB thresholds for E3B0 4 port mode */ | |
244 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304 | |
245 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0 | |
246 | ||
247 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384 | |
248 | #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0 | |
249 | ||
250 | #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10 | |
251 | #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304 | |
252 | ||
253 | #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50 | |
254 | #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384 | |
255 | ||
9380bb9e YR |
256 | /* only for E3B0*/ |
257 | #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304 | |
258 | #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384 | |
2f751a80 | 259 | #define PFC_E3B0_4P_LB_GUART 120 |
9380bb9e YR |
260 | |
261 | #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120 | |
2f751a80 | 262 | #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80 |
9380bb9e YR |
263 | |
264 | #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80 | |
2f751a80 | 265 | #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120 |
9380bb9e | 266 | |
866cedae YR |
267 | /* Pause defines*/ |
268 | #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330 | |
269 | #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490 | |
270 | #define DEFAULT_E3B0_LB_GUART 40 | |
271 | ||
272 | #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40 | |
273 | #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0 | |
274 | ||
275 | #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40 | |
276 | #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0 | |
277 | ||
278 | /* ETS defines*/ | |
9380bb9e YR |
279 | #define DCBX_INVALID_COS (0xFF) |
280 | ||
bcab15c5 VZ |
281 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
282 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
9380bb9e YR |
283 | #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) |
284 | #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) | |
285 | #define ETS_E3B0_PBF_MIN_W_VAL (10000) | |
286 | ||
287 | #define MAX_PACKET_SIZE (9700) | |
a9077bfd | 288 | #define MAX_KR_LINK_RETRY 4 |
9380bb9e | 289 | |
ea4e040a YR |
290 | /**********************************************************/ |
291 | /* INTERFACE */ | |
292 | /**********************************************************/ | |
e10bc84d | 293 | |
cd2be89b | 294 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 295 | bnx2x_cl45_write(_bp, _phy, \ |
7aa0711f | 296 | (_phy)->def_md_devad, \ |
ea4e040a YR |
297 | (_bank + (_addr & 0xf)), \ |
298 | _val) | |
299 | ||
cd2be89b | 300 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 301 | bnx2x_cl45_read(_bp, _phy, \ |
7aa0711f | 302 | (_phy)->def_md_devad, \ |
ea4e040a YR |
303 | (_bank + (_addr & 0xf)), \ |
304 | _val) | |
305 | ||
ea4e040a YR |
306 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
307 | { | |
308 | u32 val = REG_RD(bp, reg); | |
309 | ||
310 | val |= bits; | |
311 | REG_WR(bp, reg, val); | |
312 | return val; | |
313 | } | |
314 | ||
315 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
316 | { | |
317 | u32 val = REG_RD(bp, reg); | |
318 | ||
319 | val &= ~bits; | |
320 | REG_WR(bp, reg, val); | |
321 | return val; | |
322 | } | |
323 | ||
3c9ada22 YR |
324 | /******************************************************************/ |
325 | /* EPIO/GPIO section */ | |
326 | /******************************************************************/ | |
3deb8167 YR |
327 | static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) |
328 | { | |
329 | u32 epio_mask, gp_oenable; | |
330 | *en = 0; | |
331 | /* Sanity check */ | |
332 | if (epio_pin > 31) { | |
333 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin); | |
334 | return; | |
335 | } | |
336 | ||
337 | epio_mask = 1 << epio_pin; | |
338 | /* Set this EPIO to output */ | |
339 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
340 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); | |
341 | ||
342 | *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; | |
343 | } | |
3c9ada22 YR |
344 | static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) |
345 | { | |
346 | u32 epio_mask, gp_output, gp_oenable; | |
347 | ||
348 | /* Sanity check */ | |
349 | if (epio_pin > 31) { | |
350 | DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin); | |
351 | return; | |
352 | } | |
353 | DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en); | |
354 | epio_mask = 1 << epio_pin; | |
355 | /* Set this EPIO to output */ | |
356 | gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); | |
357 | if (en) | |
358 | gp_output |= epio_mask; | |
359 | else | |
360 | gp_output &= ~epio_mask; | |
361 | ||
362 | REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); | |
363 | ||
364 | /* Set the value for this EPIO */ | |
365 | gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); | |
366 | REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); | |
367 | } | |
368 | ||
369 | static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) | |
370 | { | |
371 | if (pin_cfg == PIN_CFG_NA) | |
372 | return; | |
373 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
374 | bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
375 | } else { | |
376 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
377 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
378 | bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); | |
379 | } | |
380 | } | |
381 | ||
3deb8167 YR |
382 | static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) |
383 | { | |
384 | if (pin_cfg == PIN_CFG_NA) | |
385 | return -EINVAL; | |
386 | if (pin_cfg >= PIN_CFG_EPIO0) { | |
387 | bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); | |
388 | } else { | |
389 | u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; | |
390 | u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; | |
391 | *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
392 | } | |
393 | return 0; | |
394 | ||
395 | } | |
bcab15c5 VZ |
396 | /******************************************************************/ |
397 | /* ETS section */ | |
398 | /******************************************************************/ | |
6c3218c6 | 399 | static void bnx2x_ets_e2e3a0_disabled(struct link_params *params) |
bcab15c5 VZ |
400 | { |
401 | /* ETS disabled configuration*/ | |
402 | struct bnx2x *bp = params->bp; | |
403 | ||
6c3218c6 | 404 | DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); |
bcab15c5 | 405 | |
8f73f0b9 | 406 | /* mapping between entry priority to client number (0,1,2 -debug and |
bcab15c5 VZ |
407 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
408 | * 3bits client num. | |
409 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
410 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 | |
411 | */ | |
412 | ||
413 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); | |
8f73f0b9 | 414 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
415 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
416 | * COS0 entry, 4 - COS1 entry. | |
417 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
418 | * bit4 bit3 bit2 bit1 bit0 | |
419 | * MCP and debug are strict | |
420 | */ | |
421 | ||
422 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); | |
423 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
424 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
8f73f0b9 | 425 | /* For strict priority entries defines the number of consecutive |
2cf7acf9 YR |
426 | * slots for the highest priority. |
427 | */ | |
bcab15c5 | 428 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
8f73f0b9 | 429 | /* mapping between the CREDIT_WEIGHT registers and actual client |
bcab15c5 VZ |
430 | * numbers |
431 | */ | |
432 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); | |
433 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); | |
434 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); | |
435 | ||
436 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); | |
437 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); | |
438 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); | |
439 | /* ETS mode disable */ | |
440 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
8f73f0b9 | 441 | /* If ETS mode is enabled (there is no strict priority) defines a WFQ |
bcab15c5 VZ |
442 | * weight for COS0/COS1. |
443 | */ | |
444 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); | |
445 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); | |
446 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ | |
447 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); | |
448 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); | |
449 | /* Defines the number of consecutive slots for the strict priority */ | |
450 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
451 | } | |
6c3218c6 YR |
452 | /****************************************************************************** |
453 | * Description: | |
454 | * Getting min_w_val will be set according to line speed . | |
455 | *. | |
456 | ******************************************************************************/ | |
457 | static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars) | |
458 | { | |
459 | u32 min_w_val = 0; | |
460 | /* Calculate min_w_val.*/ | |
461 | if (vars->link_up) { | |
de0396f4 | 462 | if (vars->line_speed == SPEED_20000) |
6c3218c6 YR |
463 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; |
464 | else | |
465 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; | |
466 | } else | |
467 | min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; | |
8f73f0b9 YR |
468 | /* If the link isn't up (static configuration for example ) The |
469 | * link will be according to 20GBPS. | |
470 | */ | |
6c3218c6 YR |
471 | return min_w_val; |
472 | } | |
473 | /****************************************************************************** | |
474 | * Description: | |
475 | * Getting credit upper bound form min_w_val. | |
476 | *. | |
477 | ******************************************************************************/ | |
478 | static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val) | |
479 | { | |
480 | const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val), | |
481 | MAX_PACKET_SIZE); | |
482 | return credit_upper_bound; | |
483 | } | |
484 | /****************************************************************************** | |
485 | * Description: | |
486 | * Set credit upper bound for NIG. | |
487 | *. | |
488 | ******************************************************************************/ | |
489 | static void bnx2x_ets_e3b0_set_credit_upper_bound_nig( | |
490 | const struct link_params *params, | |
491 | const u32 min_w_val) | |
492 | { | |
493 | struct bnx2x *bp = params->bp; | |
494 | const u8 port = params->port; | |
495 | const u32 credit_upper_bound = | |
496 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
497 | ||
498 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : | |
499 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); | |
500 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : | |
501 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); | |
502 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : | |
503 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); | |
504 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : | |
505 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); | |
506 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : | |
507 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); | |
508 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : | |
509 | NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); | |
510 | ||
de0396f4 | 511 | if (!port) { |
6c3218c6 YR |
512 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, |
513 | credit_upper_bound); | |
514 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, | |
515 | credit_upper_bound); | |
516 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, | |
517 | credit_upper_bound); | |
518 | } | |
519 | } | |
520 | /****************************************************************************** | |
521 | * Description: | |
522 | * Will return the NIG ETS registers to init values.Except | |
523 | * credit_upper_bound. | |
524 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
525 | * configured acording to spec | |
526 | *. | |
527 | ******************************************************************************/ | |
528 | static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params, | |
529 | const struct link_vars *vars) | |
530 | { | |
531 | struct bnx2x *bp = params->bp; | |
532 | const u8 port = params->port; | |
533 | const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); | |
8f73f0b9 | 534 | /* Mapping between entry priority to client number (0,1,2 -debug and |
6c3218c6 YR |
535 | * management clients, 3 - COS0 client, 4 - COS1, ... 8 - |
536 | * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by | |
537 | * reset value or init tool | |
538 | */ | |
539 | if (port) { | |
540 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); | |
541 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); | |
542 | } else { | |
543 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); | |
544 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); | |
545 | } | |
8f73f0b9 YR |
546 | /* For strict priority entries defines the number of consecutive |
547 | * slots for the highest priority. | |
548 | */ | |
6c3218c6 YR |
549 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : |
550 | NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
8f73f0b9 | 551 | /* Mapping between the CREDIT_WEIGHT registers and actual client |
6c3218c6 YR |
552 | * numbers |
553 | */ | |
6c3218c6 YR |
554 | if (port) { |
555 | /*Port 1 has 6 COS*/ | |
556 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); | |
557 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); | |
558 | } else { | |
559 | /*Port 0 has 9 COS*/ | |
560 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, | |
561 | 0x43210876); | |
562 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); | |
563 | } | |
564 | ||
8f73f0b9 | 565 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
6c3218c6 YR |
566 | * as strict. Bits 0,1,2 - debug and management entries, 3 - |
567 | * COS0 entry, 4 - COS1 entry. | |
568 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
569 | * bit4 bit3 bit2 bit1 bit0 | |
570 | * MCP and debug are strict | |
571 | */ | |
572 | if (port) | |
573 | REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); | |
574 | else | |
575 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); | |
576 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
577 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : | |
578 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
579 | ||
8f73f0b9 YR |
580 | /* Please notice the register address are note continuous and a |
581 | * for here is note appropriate.In 2 port mode port0 only COS0-5 | |
582 | * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 | |
583 | * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT | |
584 | * are never used for WFQ | |
585 | */ | |
6c3218c6 YR |
586 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : |
587 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); | |
588 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
589 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); | |
590 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
591 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); | |
592 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : | |
593 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); | |
594 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : | |
595 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); | |
596 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : | |
597 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); | |
de0396f4 | 598 | if (!port) { |
6c3218c6 YR |
599 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); |
600 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); | |
601 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); | |
602 | } | |
603 | ||
604 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); | |
605 | } | |
606 | /****************************************************************************** | |
607 | * Description: | |
608 | * Set credit upper bound for PBF. | |
609 | *. | |
610 | ******************************************************************************/ | |
611 | static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf( | |
612 | const struct link_params *params, | |
613 | const u32 min_w_val) | |
614 | { | |
615 | struct bnx2x *bp = params->bp; | |
616 | const u32 credit_upper_bound = | |
617 | bnx2x_ets_get_credit_upper_bound(min_w_val); | |
618 | const u8 port = params->port; | |
619 | u32 base_upper_bound = 0; | |
620 | u8 max_cos = 0; | |
621 | u8 i = 0; | |
8f73f0b9 YR |
622 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 |
623 | * port mode port1 has COS0-2 that can be used for WFQ. | |
624 | */ | |
de0396f4 | 625 | if (!port) { |
6c3218c6 YR |
626 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; |
627 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
628 | } else { | |
629 | base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; | |
630 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
631 | } | |
632 | ||
633 | for (i = 0; i < max_cos; i++) | |
634 | REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); | |
635 | } | |
636 | ||
637 | /****************************************************************************** | |
638 | * Description: | |
639 | * Will return the PBF ETS registers to init values.Except | |
640 | * credit_upper_bound. | |
641 | * That isn't used in this configuration (No WFQ is enabled) and will be | |
642 | * configured acording to spec | |
643 | *. | |
644 | ******************************************************************************/ | |
645 | static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params) | |
646 | { | |
647 | struct bnx2x *bp = params->bp; | |
648 | const u8 port = params->port; | |
649 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
650 | u8 i = 0; | |
651 | u32 base_weight = 0; | |
652 | u8 max_cos = 0; | |
653 | ||
8f73f0b9 | 654 | /* Mapping between entry priority to client number 0 - COS0 |
6c3218c6 YR |
655 | * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. |
656 | * TODO_ETS - Should be done by reset value or init tool | |
657 | */ | |
658 | if (port) | |
659 | /* 0x688 (|011|0 10|00 1|000) */ | |
660 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); | |
661 | else | |
662 | /* (10 1|100 |011|0 10|00 1|000) */ | |
663 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); | |
664 | ||
665 | /* TODO_ETS - Should be done by reset value or init tool */ | |
666 | if (port) | |
667 | /* 0x688 (|011|0 10|00 1|000)*/ | |
668 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); | |
669 | else | |
670 | /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ | |
671 | REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); | |
672 | ||
673 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : | |
674 | PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); | |
675 | ||
676 | ||
677 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
678 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); | |
679 | ||
680 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
681 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); | |
8f73f0b9 YR |
682 | /* In 2 port mode port0 has COS0-5 that can be used for WFQ. |
683 | * In 4 port mode port1 has COS0-2 that can be used for WFQ. | |
684 | */ | |
de0396f4 | 685 | if (!port) { |
6c3218c6 YR |
686 | base_weight = PBF_REG_COS0_WEIGHT_P0; |
687 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; | |
688 | } else { | |
689 | base_weight = PBF_REG_COS0_WEIGHT_P1; | |
690 | max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1; | |
691 | } | |
692 | ||
693 | for (i = 0; i < max_cos; i++) | |
694 | REG_WR(bp, base_weight + (0x4 * i), 0); | |
695 | ||
696 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
697 | } | |
698 | /****************************************************************************** | |
699 | * Description: | |
700 | * E3B0 disable will return basicly the values to init values. | |
701 | *. | |
702 | ******************************************************************************/ | |
703 | static int bnx2x_ets_e3b0_disabled(const struct link_params *params, | |
704 | const struct link_vars *vars) | |
705 | { | |
706 | struct bnx2x *bp = params->bp; | |
707 | ||
708 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
709 | DP(NETIF_MSG_LINK, |
710 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
711 | return -EINVAL; |
712 | } | |
713 | ||
714 | bnx2x_ets_e3b0_nig_disabled(params, vars); | |
715 | ||
716 | bnx2x_ets_e3b0_pbf_disabled(params); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | /****************************************************************************** | |
722 | * Description: | |
723 | * Disable will return basicly the values to init values. | |
8f73f0b9 | 724 | * |
6c3218c6 YR |
725 | ******************************************************************************/ |
726 | int bnx2x_ets_disabled(struct link_params *params, | |
727 | struct link_vars *vars) | |
728 | { | |
729 | struct bnx2x *bp = params->bp; | |
730 | int bnx2x_status = 0; | |
731 | ||
732 | if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) | |
733 | bnx2x_ets_e2e3a0_disabled(params); | |
734 | else if (CHIP_IS_E3B0(bp)) | |
735 | bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars); | |
736 | else { | |
737 | DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); | |
738 | return -EINVAL; | |
739 | } | |
740 | ||
741 | return bnx2x_status; | |
742 | } | |
743 | ||
744 | /****************************************************************************** | |
745 | * Description | |
746 | * Set the COS mappimg to SP and BW until this point all the COS are not | |
747 | * set as SP or BW. | |
748 | ******************************************************************************/ | |
749 | static int bnx2x_ets_e3b0_cli_map(const struct link_params *params, | |
750 | const struct bnx2x_ets_params *ets_params, | |
751 | const u8 cos_sp_bitmap, | |
752 | const u8 cos_bw_bitmap) | |
753 | { | |
754 | struct bnx2x *bp = params->bp; | |
755 | const u8 port = params->port; | |
756 | const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); | |
757 | const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; | |
758 | const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; | |
759 | const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; | |
760 | ||
761 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : | |
762 | NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); | |
763 | ||
764 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : | |
765 | PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); | |
bcab15c5 | 766 | |
6c3218c6 YR |
767 | REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : |
768 | NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, | |
769 | nig_cli_subject2wfq_bitmap); | |
770 | ||
771 | REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : | |
772 | PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, | |
773 | pbf_cli_subject2wfq_bitmap); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | /****************************************************************************** | |
779 | * Description: | |
780 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
781 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
782 | ******************************************************************************/ | |
783 | static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, | |
784 | const u8 cos_entry, | |
785 | const u32 min_w_val_nig, | |
786 | const u32 min_w_val_pbf, | |
787 | const u16 total_bw, | |
788 | const u8 bw, | |
789 | const u8 port) | |
790 | { | |
791 | u32 nig_reg_adress_crd_weight = 0; | |
792 | u32 pbf_reg_adress_crd_weight = 0; | |
c482e6c0 YR |
793 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
794 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; | |
795 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; | |
6c3218c6 YR |
796 | |
797 | switch (cos_entry) { | |
798 | case 0: | |
799 | nig_reg_adress_crd_weight = | |
800 | (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : | |
801 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; | |
802 | pbf_reg_adress_crd_weight = (port) ? | |
803 | PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; | |
804 | break; | |
805 | case 1: | |
806 | nig_reg_adress_crd_weight = (port) ? | |
807 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : | |
808 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; | |
809 | pbf_reg_adress_crd_weight = (port) ? | |
810 | PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; | |
811 | break; | |
812 | case 2: | |
813 | nig_reg_adress_crd_weight = (port) ? | |
814 | NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : | |
815 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; | |
816 | ||
817 | pbf_reg_adress_crd_weight = (port) ? | |
818 | PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; | |
819 | break; | |
820 | case 3: | |
821 | if (port) | |
822 | return -EINVAL; | |
823 | nig_reg_adress_crd_weight = | |
824 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; | |
825 | pbf_reg_adress_crd_weight = | |
826 | PBF_REG_COS3_WEIGHT_P0; | |
827 | break; | |
828 | case 4: | |
829 | if (port) | |
830 | return -EINVAL; | |
831 | nig_reg_adress_crd_weight = | |
832 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; | |
833 | pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; | |
834 | break; | |
835 | case 5: | |
836 | if (port) | |
837 | return -EINVAL; | |
838 | nig_reg_adress_crd_weight = | |
839 | NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; | |
840 | pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; | |
841 | break; | |
842 | } | |
843 | ||
844 | REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); | |
845 | ||
846 | REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | /****************************************************************************** | |
851 | * Description: | |
852 | * Calculate the total BW.A value of 0 isn't legal. | |
8f73f0b9 | 853 | * |
6c3218c6 YR |
854 | ******************************************************************************/ |
855 | static int bnx2x_ets_e3b0_get_total_bw( | |
856 | const struct link_params *params, | |
870516e1 | 857 | struct bnx2x_ets_params *ets_params, |
6c3218c6 YR |
858 | u16 *total_bw) |
859 | { | |
860 | struct bnx2x *bp = params->bp; | |
861 | u8 cos_idx = 0; | |
870516e1 | 862 | u8 is_bw_cos_exist = 0; |
6c3218c6 YR |
863 | |
864 | *total_bw = 0 ; | |
865 | /* Calculate total BW requested */ | |
866 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { | |
de0396f4 | 867 | if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { |
870516e1 YR |
868 | is_bw_cos_exist = 1; |
869 | if (!ets_params->cos[cos_idx].params.bw_params.bw) { | |
870 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" | |
871 | "was set to 0\n"); | |
8f73f0b9 | 872 | /* This is to prevent a state when ramrods |
870516e1 | 873 | * can't be sent |
8f73f0b9 | 874 | */ |
870516e1 YR |
875 | ets_params->cos[cos_idx].params.bw_params.bw |
876 | = 1; | |
877 | } | |
c482e6c0 YR |
878 | *total_bw += |
879 | ets_params->cos[cos_idx].params.bw_params.bw; | |
6c3218c6 | 880 | } |
6c3218c6 YR |
881 | } |
882 | ||
c482e6c0 | 883 | /* Check total BW is valid */ |
de0396f4 YR |
884 | if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { |
885 | if (*total_bw == 0) { | |
94f05b0f | 886 | DP(NETIF_MSG_LINK, |
2f751a80 | 887 | "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); |
6c3218c6 YR |
888 | return -EINVAL; |
889 | } | |
94f05b0f | 890 | DP(NETIF_MSG_LINK, |
2f751a80 | 891 | "bnx2x_ets_E3B0_config total BW should be 100\n"); |
8f73f0b9 | 892 | /* We can handle a case whre the BW isn't 100 this can happen |
2f751a80 YR |
893 | * if the TC are joined. |
894 | */ | |
6c3218c6 YR |
895 | } |
896 | return 0; | |
897 | } | |
898 | ||
899 | /****************************************************************************** | |
900 | * Description: | |
901 | * Invalidate all the sp_pri_to_cos. | |
8f73f0b9 | 902 | * |
6c3218c6 YR |
903 | ******************************************************************************/ |
904 | static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) | |
905 | { | |
906 | u8 pri = 0; | |
907 | for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) | |
908 | sp_pri_to_cos[pri] = DCBX_INVALID_COS; | |
909 | } | |
910 | /****************************************************************************** | |
911 | * Description: | |
912 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
913 | * according to sp_pri_to_cos. | |
8f73f0b9 | 914 | * |
6c3218c6 YR |
915 | ******************************************************************************/ |
916 | static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, | |
917 | u8 *sp_pri_to_cos, const u8 pri, | |
918 | const u8 cos_entry) | |
919 | { | |
920 | struct bnx2x *bp = params->bp; | |
921 | const u8 port = params->port; | |
922 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
923 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
924 | ||
7e5998aa DC |
925 | if (pri >= max_num_of_cos) { |
926 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " | |
927 | "parameter Illegal strict priority\n"); | |
928 | return -EINVAL; | |
929 | } | |
930 | ||
de0396f4 | 931 | if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { |
6c3218c6 | 932 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid " |
94f05b0f | 933 | "parameter There can't be two COS's with " |
6c3218c6 YR |
934 | "the same strict pri\n"); |
935 | return -EINVAL; | |
936 | } | |
937 | ||
6c3218c6 YR |
938 | sp_pri_to_cos[pri] = cos_entry; |
939 | return 0; | |
940 | ||
941 | } | |
942 | ||
943 | /****************************************************************************** | |
944 | * Description: | |
945 | * Returns the correct value according to COS and priority in | |
946 | * the sp_pri_cli register. | |
8f73f0b9 | 947 | * |
6c3218c6 YR |
948 | ******************************************************************************/ |
949 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, | |
950 | const u8 pri_set, | |
951 | const u8 pri_offset, | |
952 | const u8 entry_size) | |
953 | { | |
954 | u64 pri_cli_nig = 0; | |
955 | pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * | |
956 | (pri_set + pri_offset)); | |
957 | ||
958 | return pri_cli_nig; | |
959 | } | |
960 | /****************************************************************************** | |
961 | * Description: | |
962 | * Returns the correct value according to COS and priority in the | |
963 | * sp_pri_cli register for NIG. | |
8f73f0b9 | 964 | * |
6c3218c6 YR |
965 | ******************************************************************************/ |
966 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) | |
967 | { | |
968 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
969 | const u8 nig_cos_offset = 3; | |
970 | const u8 nig_pri_offset = 3; | |
971 | ||
972 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, | |
973 | nig_pri_offset, 4); | |
974 | ||
975 | } | |
976 | /****************************************************************************** | |
977 | * Description: | |
978 | * Returns the correct value according to COS and priority in the | |
979 | * sp_pri_cli register for PBF. | |
8f73f0b9 | 980 | * |
6c3218c6 YR |
981 | ******************************************************************************/ |
982 | static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) | |
983 | { | |
984 | const u8 pbf_cos_offset = 0; | |
985 | const u8 pbf_pri_offset = 0; | |
986 | ||
987 | return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, | |
988 | pbf_pri_offset, 3); | |
989 | ||
990 | } | |
991 | ||
992 | /****************************************************************************** | |
993 | * Description: | |
994 | * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers | |
995 | * according to sp_pri_to_cos.(which COS has higher priority) | |
8f73f0b9 | 996 | * |
6c3218c6 YR |
997 | ******************************************************************************/ |
998 | static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, | |
999 | u8 *sp_pri_to_cos) | |
1000 | { | |
1001 | struct bnx2x *bp = params->bp; | |
1002 | u8 i = 0; | |
1003 | const u8 port = params->port; | |
1004 | /* MCP Dbg0 and dbg1 are always with higher strict pri*/ | |
1005 | u64 pri_cli_nig = 0x210; | |
1006 | u32 pri_cli_pbf = 0x0; | |
1007 | u8 pri_set = 0; | |
1008 | u8 pri_bitmask = 0; | |
1009 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1010 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1011 | ||
1012 | u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; | |
1013 | ||
1014 | /* Set all the strict priority first */ | |
1015 | for (i = 0; i < max_num_of_cos; i++) { | |
de0396f4 YR |
1016 | if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { |
1017 | if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) { | |
6c3218c6 YR |
1018 | DP(NETIF_MSG_LINK, |
1019 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1020 | "invalid cos entry\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1025 | sp_pri_to_cos[i], pri_set); | |
1026 | ||
1027 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1028 | sp_pri_to_cos[i], pri_set); | |
1029 | pri_bitmask = 1 << sp_pri_to_cos[i]; | |
1030 | /* COS is used remove it from bitmap.*/ | |
de0396f4 | 1031 | if (!(pri_bitmask & cos_bit_to_set)) { |
6c3218c6 YR |
1032 | DP(NETIF_MSG_LINK, |
1033 | "bnx2x_ets_e3b0_sp_set_pri_cli_reg " | |
1034 | "invalid There can't be two COS's with" | |
1035 | " the same strict pri\n"); | |
1036 | return -EINVAL; | |
1037 | } | |
1038 | cos_bit_to_set &= ~pri_bitmask; | |
1039 | pri_set++; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* Set all the Non strict priority i= COS*/ | |
1044 | for (i = 0; i < max_num_of_cos; i++) { | |
1045 | pri_bitmask = 1 << i; | |
1046 | /* Check if COS was already used for SP */ | |
1047 | if (pri_bitmask & cos_bit_to_set) { | |
1048 | /* COS wasn't used for SP */ | |
1049 | pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig( | |
1050 | i, pri_set); | |
1051 | ||
1052 | pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf( | |
1053 | i, pri_set); | |
1054 | /* COS is used remove it from bitmap.*/ | |
1055 | cos_bit_to_set &= ~pri_bitmask; | |
1056 | pri_set++; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | if (pri_set != max_num_of_cos) { | |
1061 | DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all " | |
1062 | "entries were set\n"); | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
1066 | if (port) { | |
1067 | /* Only 6 usable clients*/ | |
1068 | REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1069 | (u32)pri_cli_nig); | |
1070 | ||
1071 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); | |
1072 | } else { | |
1073 | /* Only 9 usable clients*/ | |
1074 | const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); | |
1075 | const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); | |
1076 | ||
1077 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, | |
1078 | pri_cli_nig_lsb); | |
1079 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, | |
1080 | pri_cli_nig_msb); | |
1081 | ||
1082 | REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); | |
1083 | } | |
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | /****************************************************************************** | |
1088 | * Description: | |
1089 | * Configure the COS to ETS according to BW and SP settings. | |
1090 | ******************************************************************************/ | |
1091 | int bnx2x_ets_e3b0_config(const struct link_params *params, | |
1092 | const struct link_vars *vars, | |
870516e1 | 1093 | struct bnx2x_ets_params *ets_params) |
6c3218c6 YR |
1094 | { |
1095 | struct bnx2x *bp = params->bp; | |
1096 | int bnx2x_status = 0; | |
1097 | const u8 port = params->port; | |
1098 | u16 total_bw = 0; | |
1099 | const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars); | |
1100 | const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL; | |
1101 | u8 cos_bw_bitmap = 0; | |
1102 | u8 cos_sp_bitmap = 0; | |
1103 | u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; | |
1104 | const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 : | |
1105 | DCBX_E3B0_MAX_NUM_COS_PORT0; | |
1106 | u8 cos_entry = 0; | |
1107 | ||
1108 | if (!CHIP_IS_E3B0(bp)) { | |
94f05b0f JP |
1109 | DP(NETIF_MSG_LINK, |
1110 | "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n"); | |
6c3218c6 YR |
1111 | return -EINVAL; |
1112 | } | |
1113 | ||
1114 | if ((ets_params->num_of_cos > max_num_of_cos)) { | |
1115 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS " | |
1116 | "isn't supported\n"); | |
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
1120 | /* Prepare sp strict priority parameters*/ | |
1121 | bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); | |
1122 | ||
1123 | /* Prepare BW parameters*/ | |
1124 | bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params, | |
1125 | &total_bw); | |
de0396f4 | 1126 | if (bnx2x_status) { |
94f05b0f JP |
1127 | DP(NETIF_MSG_LINK, |
1128 | "bnx2x_ets_E3B0_config get_total_bw failed\n"); | |
6c3218c6 YR |
1129 | return -EINVAL; |
1130 | } | |
1131 | ||
8f73f0b9 | 1132 | /* Upper bound is set according to current link speed (min_w_val |
2f751a80 | 1133 | * should be the same for upper bound and COS credit val). |
6c3218c6 YR |
1134 | */ |
1135 | bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); | |
1136 | bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); | |
1137 | ||
1138 | ||
1139 | for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { | |
1140 | if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { | |
1141 | cos_bw_bitmap |= (1 << cos_entry); | |
8f73f0b9 | 1142 | /* The function also sets the BW in HW(not the mappin |
6c3218c6 YR |
1143 | * yet) |
1144 | */ | |
1145 | bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( | |
1146 | bp, cos_entry, min_w_val_nig, min_w_val_pbf, | |
1147 | total_bw, | |
1148 | ets_params->cos[cos_entry].params.bw_params.bw, | |
1149 | port); | |
1150 | } else if (bnx2x_cos_state_strict == | |
1151 | ets_params->cos[cos_entry].state){ | |
1152 | cos_sp_bitmap |= (1 << cos_entry); | |
1153 | ||
1154 | bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set( | |
1155 | params, | |
1156 | sp_pri_to_cos, | |
1157 | ets_params->cos[cos_entry].params.sp_params.pri, | |
1158 | cos_entry); | |
1159 | ||
1160 | } else { | |
94f05b0f JP |
1161 | DP(NETIF_MSG_LINK, |
1162 | "bnx2x_ets_e3b0_config cos state not valid\n"); | |
6c3218c6 YR |
1163 | return -EINVAL; |
1164 | } | |
de0396f4 | 1165 | if (bnx2x_status) { |
94f05b0f JP |
1166 | DP(NETIF_MSG_LINK, |
1167 | "bnx2x_ets_e3b0_config set cos bw failed\n"); | |
6c3218c6 YR |
1168 | return bnx2x_status; |
1169 | } | |
1170 | } | |
1171 | ||
1172 | /* Set SP register (which COS has higher priority) */ | |
1173 | bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params, | |
1174 | sp_pri_to_cos); | |
1175 | ||
de0396f4 | 1176 | if (bnx2x_status) { |
94f05b0f JP |
1177 | DP(NETIF_MSG_LINK, |
1178 | "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n"); | |
6c3218c6 YR |
1179 | return bnx2x_status; |
1180 | } | |
1181 | ||
1182 | /* Set client mapping of BW and strict */ | |
1183 | bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params, | |
1184 | cos_sp_bitmap, | |
1185 | cos_bw_bitmap); | |
1186 | ||
de0396f4 | 1187 | if (bnx2x_status) { |
6c3218c6 YR |
1188 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n"); |
1189 | return bnx2x_status; | |
1190 | } | |
1191 | return 0; | |
1192 | } | |
65a001ba | 1193 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
bcab15c5 VZ |
1194 | { |
1195 | /* ETS disabled configuration */ | |
1196 | struct bnx2x *bp = params->bp; | |
1197 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
8f73f0b9 | 1198 | /* Defines which entries (clients) are subjected to WFQ arbitration |
2cf7acf9 YR |
1199 | * COS0 0x8 |
1200 | * COS1 0x10 | |
1201 | */ | |
bcab15c5 | 1202 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
8f73f0b9 | 1203 | /* Mapping between the ARB_CREDIT_WEIGHT registers and actual |
2cf7acf9 YR |
1204 | * client numbers (WEIGHT_0 does not actually have to represent |
1205 | * client 0) | |
1206 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1207 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 | |
1208 | */ | |
bcab15c5 VZ |
1209 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
1210 | ||
1211 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, | |
1212 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1213 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, | |
1214 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1215 | ||
1216 | /* ETS mode enabled*/ | |
1217 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); | |
1218 | ||
1219 | /* Defines the number of consecutive slots for the strict priority */ | |
1220 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
8f73f0b9 | 1221 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
2cf7acf9 YR |
1222 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 |
1223 | * entry, 4 - COS1 entry. | |
1224 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1225 | * bit4 bit3 bit2 bit1 bit0 | |
1226 | * MCP and debug are strict | |
1227 | */ | |
bcab15c5 VZ |
1228 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
1229 | ||
1230 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ | |
1231 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, | |
1232 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1233 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, | |
1234 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
1235 | } | |
1236 | ||
1237 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
1238 | const u32 cos1_bw) | |
1239 | { | |
1240 | /* ETS disabled configuration*/ | |
1241 | struct bnx2x *bp = params->bp; | |
1242 | const u32 total_bw = cos0_bw + cos1_bw; | |
1243 | u32 cos0_credit_weight = 0; | |
1244 | u32 cos1_credit_weight = 0; | |
1245 | ||
1246 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
1247 | ||
de0396f4 YR |
1248 | if ((!total_bw) || |
1249 | (!cos0_bw) || | |
1250 | (!cos1_bw)) { | |
cd88ccee | 1251 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
bcab15c5 VZ |
1252 | return; |
1253 | } | |
1254 | ||
1255 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1256 | total_bw; | |
1257 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
1258 | total_bw; | |
1259 | ||
1260 | bnx2x_ets_bw_limit_common(params); | |
1261 | ||
1262 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); | |
1263 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); | |
1264 | ||
1265 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); | |
1266 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); | |
1267 | } | |
1268 | ||
fcf5b650 | 1269 | int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) |
bcab15c5 VZ |
1270 | { |
1271 | /* ETS disabled configuration*/ | |
1272 | struct bnx2x *bp = params->bp; | |
1273 | u32 val = 0; | |
1274 | ||
bcab15c5 | 1275 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
8f73f0b9 | 1276 | /* Bitmap of 5bits length. Each bit specifies whether the entry behaves |
bcab15c5 VZ |
1277 | * as strict. Bits 0,1,2 - debug and management entries, |
1278 | * 3 - COS0 entry, 4 - COS1 entry. | |
1279 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
1280 | * bit4 bit3 bit2 bit1 bit0 | |
1281 | * MCP and debug are strict | |
1282 | */ | |
1283 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); | |
8f73f0b9 | 1284 | /* For strict priority entries defines the number of consecutive slots |
bcab15c5 VZ |
1285 | * for the highest priority. |
1286 | */ | |
1287 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
1288 | /* ETS mode disable */ | |
1289 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
1290 | /* Defines the number of consecutive slots for the strict priority */ | |
1291 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); | |
1292 | ||
1293 | /* Defines the number of consecutive slots for the strict priority */ | |
1294 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); | |
1295 | ||
8f73f0b9 | 1296 | /* Mapping between entry priority to client number (0,1,2 -debug and |
2cf7acf9 YR |
1297 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) |
1298 | * 3bits client num. | |
1299 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
1300 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 | |
1301 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 | |
1302 | */ | |
de0396f4 | 1303 | val = (!strict_cos) ? 0x2318 : 0x22E0; |
bcab15c5 VZ |
1304 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); |
1305 | ||
1306 | return 0; | |
1307 | } | |
c8c60d88 | 1308 | |
bcab15c5 | 1309 | /******************************************************************/ |
e8920674 | 1310 | /* PFC section */ |
bcab15c5 | 1311 | /******************************************************************/ |
9380bb9e YR |
1312 | static void bnx2x_update_pfc_xmac(struct link_params *params, |
1313 | struct link_vars *vars, | |
1314 | u8 is_lb) | |
1315 | { | |
1316 | struct bnx2x *bp = params->bp; | |
1317 | u32 xmac_base; | |
1318 | u32 pause_val, pfc0_val, pfc1_val; | |
1319 | ||
1320 | /* XMAC base adrr */ | |
1321 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1322 | ||
1323 | /* Initialize pause and pfc registers */ | |
1324 | pause_val = 0x18000; | |
1325 | pfc0_val = 0xFFFF8000; | |
1326 | pfc1_val = 0x2; | |
1327 | ||
1328 | /* No PFC support */ | |
1329 | if (!(params->feature_config_flags & | |
1330 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1331 | ||
8f73f0b9 | 1332 | /* RX flow control - Process pause frame in receive direction |
9380bb9e YR |
1333 | */ |
1334 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1335 | pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; | |
1336 | ||
8f73f0b9 | 1337 | /* TX flow control - Send pause packet when buffer is full */ |
9380bb9e YR |
1338 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
1339 | pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; | |
1340 | } else {/* PFC support */ | |
1341 | pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | | |
1342 | XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | | |
1343 | XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | | |
27d9129f YR |
1344 | XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | |
1345 | XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1346 | /* Write pause and PFC registers */ | |
1347 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1348 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1349 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1350 | pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; | |
1351 | ||
9380bb9e YR |
1352 | } |
1353 | ||
1354 | /* Write pause and PFC registers */ | |
1355 | REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); | |
1356 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); | |
1357 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); | |
1358 | ||
9380bb9e | 1359 | |
b8d6d082 YR |
1360 | /* Set MAC address for source TX Pause/PFC frames */ |
1361 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, | |
1362 | ((params->mac_addr[2] << 24) | | |
1363 | (params->mac_addr[3] << 16) | | |
1364 | (params->mac_addr[4] << 8) | | |
1365 | (params->mac_addr[5]))); | |
1366 | REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, | |
1367 | ((params->mac_addr[0] << 8) | | |
1368 | (params->mac_addr[1]))); | |
9380bb9e | 1369 | |
b8d6d082 YR |
1370 | udelay(30); |
1371 | } | |
bcab15c5 | 1372 | |
bcab15c5 | 1373 | |
bcab15c5 VZ |
1374 | static void bnx2x_emac_get_pfc_stat(struct link_params *params, |
1375 | u32 pfc_frames_sent[2], | |
1376 | u32 pfc_frames_received[2]) | |
1377 | { | |
1378 | /* Read pfc statistic */ | |
1379 | struct bnx2x *bp = params->bp; | |
1380 | u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1381 | u32 val_xon = 0; | |
1382 | u32 val_xoff = 0; | |
1383 | ||
1384 | DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); | |
1385 | ||
1386 | /* PFC received frames */ | |
1387 | val_xoff = REG_RD(bp, emac_base + | |
1388 | EMAC_REG_RX_PFC_STATS_XOFF_RCVD); | |
1389 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; | |
1390 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); | |
1391 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; | |
1392 | ||
1393 | pfc_frames_received[0] = val_xon + val_xoff; | |
1394 | ||
1395 | /* PFC received sent */ | |
1396 | val_xoff = REG_RD(bp, emac_base + | |
1397 | EMAC_REG_RX_PFC_STATS_XOFF_SENT); | |
1398 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; | |
1399 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); | |
1400 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; | |
1401 | ||
1402 | pfc_frames_sent[0] = val_xon + val_xoff; | |
1403 | } | |
1404 | ||
b8d6d082 | 1405 | /* Read pfc statistic*/ |
bcab15c5 VZ |
1406 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, |
1407 | u32 pfc_frames_sent[2], | |
1408 | u32 pfc_frames_received[2]) | |
1409 | { | |
1410 | /* Read pfc statistic */ | |
1411 | struct bnx2x *bp = params->bp; | |
b8d6d082 | 1412 | |
bcab15c5 VZ |
1413 | DP(NETIF_MSG_LINK, "pfc statistic\n"); |
1414 | ||
1415 | if (!vars->link_up) | |
1416 | return; | |
1417 | ||
de0396f4 | 1418 | if (vars->mac_type == MAC_TYPE_EMAC) { |
b8d6d082 | 1419 | DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n"); |
bcab15c5 VZ |
1420 | bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, |
1421 | pfc_frames_received); | |
bcab15c5 VZ |
1422 | } |
1423 | } | |
1424 | /******************************************************************/ | |
1425 | /* MAC/PBF section */ | |
1426 | /******************************************************************/ | |
a198c142 YR |
1427 | static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) |
1428 | { | |
1429 | u32 mode, emac_base; | |
8f73f0b9 | 1430 | /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz |
a198c142 YR |
1431 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1432 | */ | |
1433 | ||
1434 | if (CHIP_IS_E2(bp)) | |
1435 | emac_base = GRCBASE_EMAC0; | |
1436 | else | |
1437 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1438 | mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | |
1439 | mode &= ~(EMAC_MDIO_MODE_AUTO_POLL | | |
1440 | EMAC_MDIO_MODE_CLOCK_CNT); | |
3c9ada22 YR |
1441 | if (USES_WARPCORE(bp)) |
1442 | mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); | |
1443 | else | |
1444 | mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); | |
a198c142 YR |
1445 | |
1446 | mode |= (EMAC_MDIO_MODE_CLAUSE_45); | |
1447 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode); | |
1448 | ||
1449 | udelay(40); | |
1450 | } | |
2f751a80 YR |
1451 | static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) |
1452 | { | |
1453 | u32 port4mode_ovwr_val; | |
1454 | /* Check 4-port override enabled */ | |
1455 | port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); | |
1456 | if (port4mode_ovwr_val & (1<<0)) { | |
1457 | /* Return 4-port mode override value */ | |
1458 | return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); | |
1459 | } | |
1460 | /* Return 4-port mode from input pin */ | |
1461 | return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); | |
1462 | } | |
a198c142 | 1463 | |
ea4e040a | 1464 | static void bnx2x_emac_init(struct link_params *params, |
cd88ccee | 1465 | struct link_vars *vars) |
ea4e040a YR |
1466 | { |
1467 | /* reset and unreset the emac core */ | |
1468 | struct bnx2x *bp = params->bp; | |
1469 | u8 port = params->port; | |
1470 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1471 | u32 val; | |
1472 | u16 timeout; | |
1473 | ||
1474 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 1475 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1476 | udelay(5); |
1477 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 1478 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
1479 | |
1480 | /* init emac - use read-modify-write */ | |
1481 | /* self clear reset */ | |
1482 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 1483 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
1484 | |
1485 | timeout = 200; | |
3196a88a | 1486 | do { |
ea4e040a YR |
1487 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
1488 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
1489 | if (!timeout) { | |
1490 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
1491 | return; | |
1492 | } | |
1493 | timeout--; | |
3196a88a | 1494 | } while (val & EMAC_MODE_RESET); |
a198c142 | 1495 | bnx2x_set_mdio_clk(bp, params->chip_id, port); |
ea4e040a YR |
1496 | /* Set mac address */ |
1497 | val = ((params->mac_addr[0] << 8) | | |
1498 | params->mac_addr[1]); | |
3196a88a | 1499 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
1500 | |
1501 | val = ((params->mac_addr[2] << 24) | | |
1502 | (params->mac_addr[3] << 16) | | |
1503 | (params->mac_addr[4] << 8) | | |
1504 | params->mac_addr[5]); | |
3196a88a | 1505 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
1506 | } |
1507 | ||
9380bb9e YR |
1508 | static void bnx2x_set_xumac_nig(struct link_params *params, |
1509 | u16 tx_pause_en, | |
1510 | u8 enable) | |
1511 | { | |
1512 | struct bnx2x *bp = params->bp; | |
1513 | ||
1514 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, | |
1515 | enable); | |
1516 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, | |
1517 | enable); | |
1518 | REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : | |
1519 | NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); | |
1520 | } | |
1521 | ||
ce7c0489 YR |
1522 | static void bnx2x_umac_disable(struct link_params *params) |
1523 | { | |
1524 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1525 | struct bnx2x *bp = params->bp; | |
1526 | if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1527 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) | |
1528 | return; | |
1529 | ||
1530 | /* Disable RX and TX */ | |
1531 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0); | |
1532 | } | |
1533 | ||
9380bb9e YR |
1534 | static void bnx2x_umac_enable(struct link_params *params, |
1535 | struct link_vars *vars, u8 lb) | |
1536 | { | |
1537 | u32 val; | |
1538 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
1539 | struct bnx2x *bp = params->bp; | |
1540 | /* Reset UMAC */ | |
1541 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1542 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
d231023e | 1543 | usleep_range(1000, 2000); |
9380bb9e YR |
1544 | |
1545 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1546 | (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); | |
1547 | ||
1548 | DP(NETIF_MSG_LINK, "enabling UMAC\n"); | |
1549 | ||
9380bb9e YR |
1550 | /* This register opens the gate for the UMAC despite its name */ |
1551 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
1552 | ||
1553 | val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | | |
1554 | UMAC_COMMAND_CONFIG_REG_PAD_EN | | |
1555 | UMAC_COMMAND_CONFIG_REG_SW_RESET | | |
1556 | UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; | |
1557 | switch (vars->line_speed) { | |
1558 | case SPEED_10: | |
1559 | val |= (0<<2); | |
1560 | break; | |
1561 | case SPEED_100: | |
1562 | val |= (1<<2); | |
1563 | break; | |
1564 | case SPEED_1000: | |
1565 | val |= (2<<2); | |
1566 | break; | |
1567 | case SPEED_2500: | |
1568 | val |= (3<<2); | |
1569 | break; | |
1570 | default: | |
1571 | DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n", | |
1572 | vars->line_speed); | |
1573 | break; | |
1574 | } | |
9d5b36be YR |
1575 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) |
1576 | val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; | |
1577 | ||
1578 | if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1579 | val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; | |
1580 | ||
e18c56b2 MY |
1581 | if (vars->duplex == DUPLEX_HALF) |
1582 | val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; | |
1583 | ||
9380bb9e YR |
1584 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1585 | udelay(50); | |
1586 | ||
26964bb7 YM |
1587 | /* Configure UMAC for EEE */ |
1588 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { | |
1589 | DP(NETIF_MSG_LINK, "configured UMAC for EEE\n"); | |
1590 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, | |
1591 | UMAC_UMAC_EEE_CTRL_REG_EEE_EN); | |
1592 | REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); | |
1593 | } else { | |
1594 | REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); | |
1595 | } | |
1596 | ||
b8d6d082 YR |
1597 | /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ |
1598 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, | |
1599 | ((params->mac_addr[2] << 24) | | |
1600 | (params->mac_addr[3] << 16) | | |
1601 | (params->mac_addr[4] << 8) | | |
1602 | (params->mac_addr[5]))); | |
1603 | REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, | |
1604 | ((params->mac_addr[0] << 8) | | |
1605 | (params->mac_addr[1]))); | |
1606 | ||
9380bb9e YR |
1607 | /* Enable RX and TX */ |
1608 | val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; | |
1609 | val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | | |
3c9ada22 | 1610 | UMAC_COMMAND_CONFIG_REG_RX_ENA; |
9380bb9e YR |
1611 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); |
1612 | udelay(50); | |
1613 | ||
1614 | /* Remove SW Reset */ | |
1615 | val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; | |
1616 | ||
1617 | /* Check loopback mode */ | |
1618 | if (lb) | |
1619 | val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; | |
1620 | REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); | |
1621 | ||
8f73f0b9 | 1622 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
9380bb9e YR |
1623 | * length used by the MAC receive logic to check frames. |
1624 | */ | |
1625 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
1626 | bnx2x_set_xumac_nig(params, | |
1627 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1628 | vars->mac_type = MAC_TYPE_UMAC; | |
1629 | ||
1630 | } | |
1631 | ||
9380bb9e | 1632 | /* Define the XMAC mode */ |
ce7c0489 | 1633 | static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) |
9380bb9e | 1634 | { |
ce7c0489 | 1635 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
1636 | u32 is_port4mode = bnx2x_is_4_port_mode(bp); |
1637 | ||
8f73f0b9 | 1638 | /* In 4-port mode, need to set the mode only once, so if XMAC is |
2f751a80 YR |
1639 | * already out of reset, it means the mode has already been set, |
1640 | * and it must not* reset the XMAC again, since it controls both | |
1641 | * ports of the path | |
1642 | */ | |
9380bb9e | 1643 | |
c3def943 | 1644 | if ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) && |
ce7c0489 | 1645 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
9380bb9e | 1646 | MISC_REGISTERS_RESET_REG_2_XMAC)) { |
94f05b0f JP |
1647 | DP(NETIF_MSG_LINK, |
1648 | "XMAC already out of reset in 4-port mode\n"); | |
9380bb9e YR |
1649 | return; |
1650 | } | |
1651 | ||
1652 | /* Hard reset */ | |
1653 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1654 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
d231023e | 1655 | usleep_range(1000, 2000); |
9380bb9e YR |
1656 | |
1657 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1658 | MISC_REGISTERS_RESET_REG_2_XMAC); | |
1659 | if (is_port4mode) { | |
1660 | DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); | |
1661 | ||
8f73f0b9 | 1662 | /* Set the number of ports on the system side to up to 2 */ |
9380bb9e YR |
1663 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); |
1664 | ||
1665 | /* Set the number of ports on the Warp Core to 10G */ | |
1666 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1667 | } else { | |
8f73f0b9 | 1668 | /* Set the number of ports on the system side to 1 */ |
9380bb9e YR |
1669 | REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); |
1670 | if (max_speed == SPEED_10000) { | |
94f05b0f JP |
1671 | DP(NETIF_MSG_LINK, |
1672 | "Init XMAC to 10G x 1 port per path\n"); | |
9380bb9e YR |
1673 | /* Set the number of ports on the Warp Core to 10G */ |
1674 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); | |
1675 | } else { | |
94f05b0f JP |
1676 | DP(NETIF_MSG_LINK, |
1677 | "Init XMAC to 20G x 2 ports per path\n"); | |
9380bb9e YR |
1678 | /* Set the number of ports on the Warp Core to 20G */ |
1679 | REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); | |
1680 | } | |
1681 | } | |
1682 | /* Soft reset */ | |
1683 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1684 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
d231023e | 1685 | usleep_range(1000, 2000); |
9380bb9e YR |
1686 | |
1687 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
1688 | MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); | |
1689 | ||
1690 | } | |
1691 | ||
1692 | static void bnx2x_xmac_disable(struct link_params *params) | |
1693 | { | |
1694 | u8 port = params->port; | |
1695 | struct bnx2x *bp = params->bp; | |
b5077662 | 1696 | u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; |
9380bb9e YR |
1697 | |
1698 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1699 | MISC_REGISTERS_RESET_REG_2_XMAC) { | |
8f73f0b9 | 1700 | /* Send an indication to change the state in the NIG back to XON |
b5077662 YR |
1701 | * Clearing this bit enables the next set of this bit to get |
1702 | * rising edge | |
1703 | */ | |
1704 | pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); | |
1705 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1706 | (pfc_ctrl & ~(1<<1))); | |
1707 | REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, | |
1708 | (pfc_ctrl | (1<<1))); | |
9380bb9e YR |
1709 | DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); |
1710 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0); | |
9380bb9e YR |
1711 | } |
1712 | } | |
1713 | ||
1714 | static int bnx2x_xmac_enable(struct link_params *params, | |
1715 | struct link_vars *vars, u8 lb) | |
1716 | { | |
1717 | u32 val, xmac_base; | |
1718 | struct bnx2x *bp = params->bp; | |
1719 | DP(NETIF_MSG_LINK, "enabling XMAC\n"); | |
1720 | ||
1721 | xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
1722 | ||
ce7c0489 | 1723 | bnx2x_xmac_init(params, vars->line_speed); |
9380bb9e | 1724 | |
8f73f0b9 | 1725 | /* This register determines on which events the MAC will assert |
9380bb9e YR |
1726 | * error on the i/f to the NIG along w/ EOP. |
1727 | */ | |
1728 | ||
8f73f0b9 | 1729 | /* This register tells the NIG whether to send traffic to UMAC |
9380bb9e YR |
1730 | * or XMAC |
1731 | */ | |
1732 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); | |
1733 | ||
1734 | /* Set Max packet size */ | |
1735 | REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); | |
1736 | ||
1737 | /* CRC append for Tx packets */ | |
1738 | REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); | |
1739 | ||
1740 | /* update PFC */ | |
1741 | bnx2x_update_pfc_xmac(params, vars, 0); | |
1742 | ||
c8c60d88 YM |
1743 | if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { |
1744 | DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n"); | |
1745 | REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); | |
1746 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); | |
1747 | } else { | |
1748 | REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); | |
1749 | } | |
1750 | ||
9380bb9e YR |
1751 | /* Enable TX and RX */ |
1752 | val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; | |
1753 | ||
1754 | /* Check loopback mode */ | |
1755 | if (lb) | |
4d7e25d6 | 1756 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
9380bb9e YR |
1757 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
1758 | bnx2x_set_xumac_nig(params, | |
1759 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | |
1760 | ||
1761 | vars->mac_type = MAC_TYPE_XMAC; | |
1762 | ||
1763 | return 0; | |
1764 | } | |
2f751a80 | 1765 | |
fcf5b650 | 1766 | static int bnx2x_emac_enable(struct link_params *params, |
9045f6b4 | 1767 | struct link_vars *vars, u8 lb) |
ea4e040a YR |
1768 | { |
1769 | struct bnx2x *bp = params->bp; | |
1770 | u8 port = params->port; | |
1771 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1772 | u32 val; | |
1773 | ||
1774 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
1775 | ||
de6f3377 YR |
1776 | /* Disable BMAC */ |
1777 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
1778 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1779 | ||
ea4e040a YR |
1780 | /* enable emac and not bmac */ |
1781 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
1782 | ||
ea4e040a YR |
1783 | /* ASIC */ |
1784 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
1785 | u32 ser_lane = ((params->lane_config & | |
cd88ccee YR |
1786 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
1787 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a YR |
1788 | |
1789 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
1790 | /* select the master lanes (out of 0-3) */ | |
cd88ccee | 1791 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
ea4e040a | 1792 | /* select XGXS */ |
cd88ccee | 1793 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
1794 | |
1795 | } else { /* SerDes */ | |
1796 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
1797 | /* select SerDes */ | |
cd88ccee | 1798 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
1799 | } |
1800 | ||
811a2f2d | 1801 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
cd88ccee | 1802 | EMAC_RX_MODE_RESET); |
811a2f2d | 1803 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
cd88ccee | 1804 | EMAC_TX_MODE_RESET); |
ea4e040a | 1805 | |
ea4e040a YR |
1806 | /* pause enable/disable */ |
1807 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
1808 | EMAC_RX_MODE_FLOW_EN); | |
ea4e040a YR |
1809 | |
1810 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
bcab15c5 VZ |
1811 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
1812 | EMAC_TX_MODE_FLOW_EN)); | |
1813 | if (!(params->feature_config_flags & | |
1814 | FEATURE_CONFIG_PFC_ENABLED)) { | |
1815 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
1816 | bnx2x_bits_en(bp, emac_base + | |
1817 | EMAC_REG_EMAC_RX_MODE, | |
1818 | EMAC_RX_MODE_FLOW_EN); | |
1819 | ||
1820 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
1821 | bnx2x_bits_en(bp, emac_base + | |
1822 | EMAC_REG_EMAC_TX_MODE, | |
1823 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
1824 | EMAC_TX_MODE_FLOW_EN)); | |
1825 | } else | |
1826 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
1827 | EMAC_TX_MODE_FLOW_EN); | |
ea4e040a YR |
1828 | |
1829 | /* KEEP_VLAN_TAG, promiscuous */ | |
1830 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
1831 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
bcab15c5 | 1832 | |
8f73f0b9 | 1833 | /* Setting this bit causes MAC control frames (except for pause |
2cf7acf9 YR |
1834 | * frames) to be passed on for processing. This setting has no |
1835 | * affect on the operation of the pause frames. This bit effects | |
1836 | * all packets regardless of RX Parser packet sorting logic. | |
1837 | * Turn the PFC off to make sure we are in Xon state before | |
1838 | * enabling it. | |
1839 | */ | |
bcab15c5 VZ |
1840 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
1841 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1842 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1843 | /* Enable PFC again */ | |
1844 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, | |
1845 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
1846 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
1847 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
1848 | ||
1849 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, | |
1850 | ((0x0101 << | |
1851 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
1852 | (0x00ff << | |
1853 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
1854 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
1855 | } | |
3196a88a | 1856 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
1857 | |
1858 | /* Set Loopback */ | |
1859 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
1860 | if (lb) | |
1861 | val |= 0x810; | |
1862 | else | |
1863 | val &= ~0x810; | |
3196a88a | 1864 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 1865 | |
d231023e | 1866 | /* Enable emac */ |
6c55c3cd EG |
1867 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); |
1868 | ||
d231023e | 1869 | /* Enable emac for jumbo packets */ |
3196a88a | 1870 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
1871 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
1872 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
1873 | ||
d231023e | 1874 | /* Strip CRC */ |
ea4e040a YR |
1875 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); |
1876 | ||
d231023e | 1877 | /* Disable the NIG in/out to the bmac */ |
ea4e040a YR |
1878 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); |
1879 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
1880 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
1881 | ||
d231023e | 1882 | /* Enable the NIG in/out to the emac */ |
ea4e040a YR |
1883 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); |
1884 | val = 0; | |
bcab15c5 VZ |
1885 | if ((params->feature_config_flags & |
1886 | FEATURE_CONFIG_PFC_ENABLED) || | |
1887 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
1888 | val = 1; |
1889 | ||
1890 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
1891 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
1892 | ||
02a23165 | 1893 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); |
ea4e040a YR |
1894 | |
1895 | vars->mac_type = MAC_TYPE_EMAC; | |
1896 | return 0; | |
1897 | } | |
1898 | ||
bcab15c5 VZ |
1899 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
1900 | struct link_vars *vars) | |
1901 | { | |
1902 | u32 wb_data[2]; | |
1903 | struct bnx2x *bp = params->bp; | |
1904 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1905 | NIG_REG_INGRESS_BMAC0_MEM; | |
1906 | ||
1907 | u32 val = 0x14; | |
1908 | if ((!(params->feature_config_flags & | |
1909 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1910 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
1911 | /* Enable BigMAC to react on received Pause packets */ | |
1912 | val |= (1<<5); | |
1913 | wb_data[0] = val; | |
1914 | wb_data[1] = 0; | |
1915 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
1916 | ||
d231023e | 1917 | /* TX control */ |
bcab15c5 VZ |
1918 | val = 0xc0; |
1919 | if (!(params->feature_config_flags & | |
1920 | FEATURE_CONFIG_PFC_ENABLED) && | |
1921 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
1922 | val |= 0x800000; | |
1923 | wb_data[0] = val; | |
1924 | wb_data[1] = 0; | |
1925 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
1926 | } | |
1927 | ||
1928 | static void bnx2x_update_pfc_bmac2(struct link_params *params, | |
1929 | struct link_vars *vars, | |
1930 | u8 is_lb) | |
f2e0899f | 1931 | { |
8f73f0b9 | 1932 | /* Set rx control: Strip CRC and enable BigMAC to relay |
f2e0899f DK |
1933 | * control packets to the system as well |
1934 | */ | |
1935 | u32 wb_data[2]; | |
1936 | struct bnx2x *bp = params->bp; | |
1937 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1938 | NIG_REG_INGRESS_BMAC0_MEM; | |
1939 | u32 val = 0x14; | |
ea4e040a | 1940 | |
bcab15c5 VZ |
1941 | if ((!(params->feature_config_flags & |
1942 | FEATURE_CONFIG_PFC_ENABLED)) && | |
1943 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
f2e0899f DK |
1944 | /* Enable BigMAC to react on received Pause packets */ |
1945 | val |= (1<<5); | |
1946 | wb_data[0] = val; | |
1947 | wb_data[1] = 0; | |
cd88ccee | 1948 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
f2e0899f | 1949 | udelay(30); |
ea4e040a | 1950 | |
f2e0899f DK |
1951 | /* Tx control */ |
1952 | val = 0xc0; | |
bcab15c5 VZ |
1953 | if (!(params->feature_config_flags & |
1954 | FEATURE_CONFIG_PFC_ENABLED) && | |
1955 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
f2e0899f DK |
1956 | val |= 0x800000; |
1957 | wb_data[0] = val; | |
1958 | wb_data[1] = 0; | |
bcab15c5 VZ |
1959 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
1960 | ||
1961 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
1962 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
1963 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
1964 | wb_data[0] = 0x0; | |
1965 | wb_data[0] |= (1<<0); /* RX */ | |
1966 | wb_data[0] |= (1<<1); /* TX */ | |
1967 | wb_data[0] |= (1<<2); /* Force initial Xon */ | |
1968 | wb_data[0] |= (1<<3); /* 8 cos */ | |
1969 | wb_data[0] |= (1<<5); /* STATS */ | |
1970 | wb_data[1] = 0; | |
1971 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
1972 | wb_data, 2); | |
1973 | /* Clear the force Xon */ | |
1974 | wb_data[0] &= ~(1<<2); | |
1975 | } else { | |
1976 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); | |
d231023e | 1977 | /* Disable PFC RX & TX & STATS and set 8 COS */ |
bcab15c5 VZ |
1978 | wb_data[0] = 0x8; |
1979 | wb_data[1] = 0; | |
1980 | } | |
1981 | ||
1982 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
f2e0899f | 1983 | |
8f73f0b9 | 1984 | /* Set Time (based unit is 512 bit time) between automatic |
2cf7acf9 YR |
1985 | * re-sending of PP packets amd enable automatic re-send of |
1986 | * Per-Priroity Packet as long as pp_gen is asserted and | |
1987 | * pp_disable is low. | |
1988 | */ | |
f2e0899f | 1989 | val = 0x8000; |
bcab15c5 VZ |
1990 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
1991 | val |= (1<<16); /* enable automatic re-send */ | |
1992 | ||
f2e0899f DK |
1993 | wb_data[0] = val; |
1994 | wb_data[1] = 0; | |
1995 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
cd88ccee | 1996 | wb_data, 2); |
f2e0899f DK |
1997 | |
1998 | /* mac control */ | |
1999 | val = 0x3; /* Enable RX and TX */ | |
2000 | if (is_lb) { | |
2001 | val |= 0x4; /* Local loopback */ | |
2002 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2003 | } | |
bcab15c5 VZ |
2004 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
2005 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2006 | val |= ((1<<6)|(1<<5)); | |
f2e0899f DK |
2007 | |
2008 | wb_data[0] = val; | |
2009 | wb_data[1] = 0; | |
cd88ccee | 2010 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2011 | } |
2012 | ||
9380bb9e YR |
2013 | /* PFC BRB internal port configuration params */ |
2014 | struct bnx2x_pfc_brb_threshold_val { | |
2015 | u32 pause_xoff; | |
2016 | u32 pause_xon; | |
2017 | u32 full_xoff; | |
2018 | u32 full_xon; | |
2019 | }; | |
2020 | ||
2021 | struct bnx2x_pfc_brb_e3b0_val { | |
866cedae YR |
2022 | u32 per_class_guaranty_mode; |
2023 | u32 lb_guarantied_hyst; | |
9380bb9e YR |
2024 | u32 full_lb_xoff_th; |
2025 | u32 full_lb_xon_threshold; | |
2026 | u32 lb_guarantied; | |
2027 | u32 mac_0_class_t_guarantied; | |
2028 | u32 mac_0_class_t_guarantied_hyst; | |
2029 | u32 mac_1_class_t_guarantied; | |
2030 | u32 mac_1_class_t_guarantied_hyst; | |
2031 | }; | |
2032 | ||
2033 | struct bnx2x_pfc_brb_th_val { | |
2034 | struct bnx2x_pfc_brb_threshold_val pauseable_th; | |
2035 | struct bnx2x_pfc_brb_threshold_val non_pauseable_th; | |
866cedae YR |
2036 | struct bnx2x_pfc_brb_threshold_val default_class0; |
2037 | struct bnx2x_pfc_brb_threshold_val default_class1; | |
2038 | ||
9380bb9e YR |
2039 | }; |
2040 | static int bnx2x_pfc_brb_get_config_params( | |
2041 | struct link_params *params, | |
2042 | struct bnx2x_pfc_brb_th_val *config_val) | |
2043 | { | |
2044 | struct bnx2x *bp = params->bp; | |
2045 | DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n"); | |
866cedae YR |
2046 | |
2047 | config_val->default_class1.pause_xoff = 0; | |
2048 | config_val->default_class1.pause_xon = 0; | |
2049 | config_val->default_class1.full_xoff = 0; | |
2050 | config_val->default_class1.full_xon = 0; | |
2051 | ||
9380bb9e | 2052 | if (CHIP_IS_E2(bp)) { |
8f73f0b9 | 2053 | /* Class0 defaults */ |
866cedae YR |
2054 | config_val->default_class0.pause_xoff = |
2055 | DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR; | |
2056 | config_val->default_class0.pause_xon = | |
2f751a80 | 2057 | DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR; |
866cedae | 2058 | config_val->default_class0.full_xoff = |
2f751a80 | 2059 | DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR; |
866cedae | 2060 | config_val->default_class0.full_xon = |
2f751a80 | 2061 | DEFAULT0_E2_BRB_MAC_FULL_XON_THR; |
8f73f0b9 | 2062 | /* Pause able*/ |
9380bb9e | 2063 | config_val->pauseable_th.pause_xoff = |
2f751a80 | 2064 | PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2065 | config_val->pauseable_th.pause_xon = |
2f751a80 | 2066 | PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2067 | config_val->pauseable_th.full_xoff = |
2f751a80 | 2068 | PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2069 | config_val->pauseable_th.full_xon = |
2f751a80 | 2070 | PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE; |
d231023e | 2071 | /* Non pause able*/ |
9380bb9e | 2072 | config_val->non_pauseable_th.pause_xoff = |
2f751a80 | 2073 | PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2074 | config_val->non_pauseable_th.pause_xon = |
2f751a80 | 2075 | PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2076 | config_val->non_pauseable_th.full_xoff = |
2f751a80 | 2077 | PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2078 | config_val->non_pauseable_th.full_xon = |
2f751a80 | 2079 | PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
9380bb9e | 2080 | } else if (CHIP_IS_E3A0(bp)) { |
8f73f0b9 | 2081 | /* Class0 defaults */ |
866cedae YR |
2082 | config_val->default_class0.pause_xoff = |
2083 | DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR; | |
2084 | config_val->default_class0.pause_xon = | |
2f751a80 | 2085 | DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR; |
866cedae | 2086 | config_val->default_class0.full_xoff = |
2f751a80 | 2087 | DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR; |
866cedae | 2088 | config_val->default_class0.full_xon = |
2f751a80 | 2089 | DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR; |
8f73f0b9 | 2090 | /* Pause able */ |
9380bb9e | 2091 | config_val->pauseable_th.pause_xoff = |
2f751a80 | 2092 | PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2093 | config_val->pauseable_th.pause_xon = |
2f751a80 | 2094 | PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2095 | config_val->pauseable_th.full_xoff = |
2f751a80 | 2096 | PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2097 | config_val->pauseable_th.full_xon = |
2f751a80 | 2098 | PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE; |
d231023e | 2099 | /* Non pause able*/ |
9380bb9e | 2100 | config_val->non_pauseable_th.pause_xoff = |
2f751a80 | 2101 | PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2102 | config_val->non_pauseable_th.pause_xon = |
2f751a80 | 2103 | PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2104 | config_val->non_pauseable_th.full_xoff = |
2f751a80 | 2105 | PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2106 | config_val->non_pauseable_th.full_xon = |
2f751a80 | 2107 | PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
9380bb9e | 2108 | } else if (CHIP_IS_E3B0(bp)) { |
8f73f0b9 | 2109 | /* Class0 defaults */ |
866cedae YR |
2110 | config_val->default_class0.pause_xoff = |
2111 | DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR; | |
2112 | config_val->default_class0.pause_xon = | |
2113 | DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR; | |
2114 | config_val->default_class0.full_xoff = | |
2115 | DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR; | |
2116 | config_val->default_class0.full_xon = | |
2117 | DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR; | |
2118 | ||
9380bb9e | 2119 | if (params->phy[INT_PHY].flags & |
2f751a80 | 2120 | FLAGS_4_PORT_MODE) { |
9380bb9e | 2121 | config_val->pauseable_th.pause_xoff = |
866cedae | 2122 | PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE; |
9380bb9e | 2123 | config_val->pauseable_th.pause_xon = |
866cedae | 2124 | PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE; |
9380bb9e | 2125 | config_val->pauseable_th.full_xoff = |
866cedae | 2126 | PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE; |
9380bb9e | 2127 | config_val->pauseable_th.full_xon = |
866cedae | 2128 | PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE; |
d231023e | 2129 | /* Non pause able*/ |
9380bb9e | 2130 | config_val->non_pauseable_th.pause_xoff = |
866cedae | 2131 | PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; |
9380bb9e | 2132 | config_val->non_pauseable_th.pause_xon = |
866cedae | 2133 | PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; |
9380bb9e | 2134 | config_val->non_pauseable_th.full_xoff = |
866cedae | 2135 | PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; |
9380bb9e | 2136 | config_val->non_pauseable_th.full_xon = |
866cedae YR |
2137 | PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE; |
2138 | } else { | |
2139 | config_val->pauseable_th.pause_xoff = | |
2140 | PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE; | |
2141 | config_val->pauseable_th.pause_xon = | |
2f751a80 YR |
2142 | PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE; |
2143 | config_val->pauseable_th.full_xoff = | |
2144 | PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE; | |
2145 | config_val->pauseable_th.full_xon = | |
2146 | PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE; | |
d231023e | 2147 | /* Non pause able*/ |
2f751a80 YR |
2148 | config_val->non_pauseable_th.pause_xoff = |
2149 | PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE; | |
2150 | config_val->non_pauseable_th.pause_xon = | |
2151 | PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE; | |
2152 | config_val->non_pauseable_th.full_xoff = | |
2153 | PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE; | |
2154 | config_val->non_pauseable_th.full_xon = | |
2155 | PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE; | |
2156 | } | |
9380bb9e YR |
2157 | } else |
2158 | return -EINVAL; | |
2159 | ||
2160 | return 0; | |
2161 | } | |
2162 | ||
866cedae YR |
2163 | static void bnx2x_pfc_brb_get_e3b0_config_params( |
2164 | struct link_params *params, | |
2165 | struct bnx2x_pfc_brb_e3b0_val | |
2166 | *e3b0_val, | |
2167 | struct bnx2x_nig_brb_pfc_port_params *pfc_params, | |
2168 | const u8 pfc_enabled) | |
9380bb9e | 2169 | { |
866cedae YR |
2170 | if (pfc_enabled && pfc_params) { |
2171 | e3b0_val->per_class_guaranty_mode = 1; | |
2172 | e3b0_val->lb_guarantied_hyst = 80; | |
2173 | ||
2174 | if (params->phy[INT_PHY].flags & | |
2175 | FLAGS_4_PORT_MODE) { | |
2176 | e3b0_val->full_lb_xoff_th = | |
2177 | PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR; | |
2178 | e3b0_val->full_lb_xon_threshold = | |
2179 | PFC_E3B0_4P_BRB_FULL_LB_XON_THR; | |
2180 | e3b0_val->lb_guarantied = | |
2181 | PFC_E3B0_4P_LB_GUART; | |
2182 | e3b0_val->mac_0_class_t_guarantied = | |
2183 | PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART; | |
2184 | e3b0_val->mac_0_class_t_guarantied_hyst = | |
2185 | PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST; | |
2186 | e3b0_val->mac_1_class_t_guarantied = | |
2187 | PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART; | |
2188 | e3b0_val->mac_1_class_t_guarantied_hyst = | |
2189 | PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST; | |
2190 | } else { | |
2191 | e3b0_val->full_lb_xoff_th = | |
2192 | PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR; | |
2193 | e3b0_val->full_lb_xon_threshold = | |
2194 | PFC_E3B0_2P_BRB_FULL_LB_XON_THR; | |
2195 | e3b0_val->mac_0_class_t_guarantied_hyst = | |
2196 | PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST; | |
2197 | e3b0_val->mac_1_class_t_guarantied = | |
2198 | PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART; | |
2199 | e3b0_val->mac_1_class_t_guarantied_hyst = | |
2200 | PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST; | |
2201 | ||
2202 | if (pfc_params->cos0_pauseable != | |
2203 | pfc_params->cos1_pauseable) { | |
d231023e | 2204 | /* Nonpauseable= Lossy + pauseable = Lossless*/ |
866cedae YR |
2205 | e3b0_val->lb_guarantied = |
2206 | PFC_E3B0_2P_MIX_PAUSE_LB_GUART; | |
2207 | e3b0_val->mac_0_class_t_guarantied = | |
2208 | PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART; | |
2209 | } else if (pfc_params->cos0_pauseable) { | |
2210 | /* Lossless +Lossless*/ | |
2211 | e3b0_val->lb_guarantied = | |
2212 | PFC_E3B0_2P_PAUSE_LB_GUART; | |
2213 | e3b0_val->mac_0_class_t_guarantied = | |
2214 | PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART; | |
2215 | } else { | |
2216 | /* Lossy +Lossy*/ | |
2217 | e3b0_val->lb_guarantied = | |
2218 | PFC_E3B0_2P_NON_PAUSE_LB_GUART; | |
2219 | e3b0_val->mac_0_class_t_guarantied = | |
2220 | PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART; | |
2221 | } | |
2222 | } | |
2223 | } else { | |
2224 | e3b0_val->per_class_guaranty_mode = 0; | |
2225 | e3b0_val->lb_guarantied_hyst = 0; | |
9380bb9e | 2226 | e3b0_val->full_lb_xoff_th = |
866cedae | 2227 | DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR; |
9380bb9e | 2228 | e3b0_val->full_lb_xon_threshold = |
866cedae | 2229 | DEFAULT_E3B0_BRB_FULL_LB_XON_THR; |
9380bb9e | 2230 | e3b0_val->lb_guarantied = |
866cedae | 2231 | DEFAULT_E3B0_LB_GUART; |
9380bb9e | 2232 | e3b0_val->mac_0_class_t_guarantied = |
866cedae | 2233 | DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART; |
9380bb9e | 2234 | e3b0_val->mac_0_class_t_guarantied_hyst = |
866cedae | 2235 | DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST; |
9380bb9e | 2236 | e3b0_val->mac_1_class_t_guarantied = |
866cedae | 2237 | DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART; |
9380bb9e | 2238 | e3b0_val->mac_1_class_t_guarantied_hyst = |
866cedae | 2239 | DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST; |
9380bb9e YR |
2240 | } |
2241 | } | |
2242 | static int bnx2x_update_pfc_brb(struct link_params *params, | |
2243 | struct link_vars *vars, | |
2244 | struct bnx2x_nig_brb_pfc_port_params | |
2245 | *pfc_params) | |
bcab15c5 VZ |
2246 | { |
2247 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2248 | struct bnx2x_pfc_brb_th_val config_val = { {0} }; |
2249 | struct bnx2x_pfc_brb_threshold_val *reg_th_config = | |
2f751a80 | 2250 | &config_val.pauseable_th; |
9380bb9e | 2251 | struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0}; |
866cedae | 2252 | const int set_pfc = params->feature_config_flags & |
bcab15c5 | 2253 | FEATURE_CONFIG_PFC_ENABLED; |
866cedae | 2254 | const u8 pfc_enabled = (set_pfc && pfc_params); |
9380bb9e YR |
2255 | int bnx2x_status = 0; |
2256 | u8 port = params->port; | |
bcab15c5 VZ |
2257 | |
2258 | /* default - pause configuration */ | |
9380bb9e YR |
2259 | reg_th_config = &config_val.pauseable_th; |
2260 | bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val); | |
de0396f4 | 2261 | if (bnx2x_status) |
9380bb9e | 2262 | return bnx2x_status; |
bcab15c5 | 2263 | |
866cedae | 2264 | if (pfc_enabled) { |
bcab15c5 | 2265 | /* First COS */ |
866cedae YR |
2266 | if (pfc_params->cos0_pauseable) |
2267 | reg_th_config = &config_val.pauseable_th; | |
2268 | else | |
9380bb9e | 2269 | reg_th_config = &config_val.non_pauseable_th; |
866cedae YR |
2270 | } else |
2271 | reg_th_config = &config_val.default_class0; | |
8f73f0b9 | 2272 | /* The number of free blocks below which the pause signal to class 0 |
2cf7acf9 YR |
2273 | * of MAC #n is asserted. n=0,1 |
2274 | */ | |
9380bb9e YR |
2275 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 : |
2276 | BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , | |
2277 | reg_th_config->pause_xoff); | |
8f73f0b9 | 2278 | /* The number of free blocks above which the pause signal to class 0 |
2cf7acf9 YR |
2279 | * of MAC #n is de-asserted. n=0,1 |
2280 | */ | |
9380bb9e YR |
2281 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 : |
2282 | BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon); | |
8f73f0b9 | 2283 | /* The number of free blocks below which the full signal to class 0 |
2cf7acf9 YR |
2284 | * of MAC #n is asserted. n=0,1 |
2285 | */ | |
9380bb9e YR |
2286 | REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 : |
2287 | BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff); | |
8f73f0b9 | 2288 | /* The number of free blocks above which the full signal to class 0 |
2cf7acf9 YR |
2289 | * of MAC #n is de-asserted. n=0,1 |
2290 | */ | |
9380bb9e YR |
2291 | REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 : |
2292 | BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon); | |
bcab15c5 | 2293 | |
866cedae | 2294 | if (pfc_enabled) { |
bcab15c5 | 2295 | /* Second COS */ |
9380bb9e YR |
2296 | if (pfc_params->cos1_pauseable) |
2297 | reg_th_config = &config_val.pauseable_th; | |
2298 | else | |
2299 | reg_th_config = &config_val.non_pauseable_th; | |
866cedae YR |
2300 | } else |
2301 | reg_th_config = &config_val.default_class1; | |
8f73f0b9 | 2302 | /* The number of free blocks below which the pause signal to |
2f751a80 YR |
2303 | * class 1 of MAC #n is asserted. n=0,1 |
2304 | */ | |
2305 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 : | |
2306 | BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, | |
2307 | reg_th_config->pause_xoff); | |
2308 | ||
8f73f0b9 | 2309 | /* The number of free blocks above which the pause signal to |
2f751a80 YR |
2310 | * class 1 of MAC #n is de-asserted. n=0,1 |
2311 | */ | |
2312 | REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 : | |
2313 | BRB1_REG_PAUSE_1_XON_THRESHOLD_0, | |
2314 | reg_th_config->pause_xon); | |
8f73f0b9 | 2315 | /* The number of free blocks below which the full signal to |
2f751a80 YR |
2316 | * class 1 of MAC #n is asserted. n=0,1 |
2317 | */ | |
2318 | REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 : | |
2319 | BRB1_REG_FULL_1_XOFF_THRESHOLD_0, | |
2320 | reg_th_config->full_xoff); | |
8f73f0b9 | 2321 | /* The number of free blocks above which the full signal to |
2f751a80 YR |
2322 | * class 1 of MAC #n is de-asserted. n=0,1 |
2323 | */ | |
2324 | REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 : | |
2325 | BRB1_REG_FULL_1_XON_THRESHOLD_0, | |
2326 | reg_th_config->full_xon); | |
9380bb9e | 2327 | |
866cedae YR |
2328 | if (CHIP_IS_E3B0(bp)) { |
2329 | bnx2x_pfc_brb_get_e3b0_config_params( | |
2330 | params, | |
2331 | &e3b0_val, | |
2332 | pfc_params, | |
2333 | pfc_enabled); | |
9380bb9e | 2334 | |
866cedae YR |
2335 | REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE, |
2336 | e3b0_val.per_class_guaranty_mode); | |
9380bb9e | 2337 | |
8f73f0b9 | 2338 | /* The hysteresis on the guarantied buffer space for the Lb |
2f751a80 YR |
2339 | * port before signaling XON. |
2340 | */ | |
866cedae YR |
2341 | REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, |
2342 | e3b0_val.lb_guarantied_hyst); | |
2f751a80 | 2343 | |
8f73f0b9 | 2344 | /* The number of free blocks below which the full signal to the |
2f751a80 YR |
2345 | * LB port is asserted. |
2346 | */ | |
866cedae | 2347 | REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, |
2f751a80 | 2348 | e3b0_val.full_lb_xoff_th); |
8f73f0b9 | 2349 | /* The number of free blocks above which the full signal to the |
2f751a80 YR |
2350 | * LB port is de-asserted. |
2351 | */ | |
2352 | REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, | |
2353 | e3b0_val.full_lb_xon_threshold); | |
8f73f0b9 | 2354 | /* The number of blocks guarantied for the MAC #n port. n=0,1 |
2f751a80 YR |
2355 | */ |
2356 | ||
8f73f0b9 | 2357 | /* The number of blocks guarantied for the LB port. */ |
2f751a80 YR |
2358 | REG_WR(bp, BRB1_REG_LB_GUARANTIED, |
2359 | e3b0_val.lb_guarantied); | |
2360 | ||
8f73f0b9 | 2361 | /* The number of blocks guarantied for the MAC #n port. */ |
2f751a80 YR |
2362 | REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0, |
2363 | 2 * e3b0_val.mac_0_class_t_guarantied); | |
2364 | REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1, | |
2365 | 2 * e3b0_val.mac_1_class_t_guarantied); | |
8f73f0b9 | 2366 | /* The number of blocks guarantied for class #t in MAC0. t=0,1 |
2f751a80 YR |
2367 | */ |
2368 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED, | |
2369 | e3b0_val.mac_0_class_t_guarantied); | |
2370 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED, | |
2371 | e3b0_val.mac_0_class_t_guarantied); | |
8f73f0b9 | 2372 | /* The hysteresis on the guarantied buffer space for class in |
2f751a80 YR |
2373 | * MAC0. t=0,1 |
2374 | */ | |
2375 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST, | |
2376 | e3b0_val.mac_0_class_t_guarantied_hyst); | |
2377 | REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST, | |
2378 | e3b0_val.mac_0_class_t_guarantied_hyst); | |
2379 | ||
8f73f0b9 | 2380 | /* The number of blocks guarantied for class #t in MAC1.t=0,1 |
2f751a80 YR |
2381 | */ |
2382 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED, | |
2383 | e3b0_val.mac_1_class_t_guarantied); | |
2384 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED, | |
2385 | e3b0_val.mac_1_class_t_guarantied); | |
8f73f0b9 | 2386 | /* The hysteresis on the guarantied buffer space for class #t |
2f751a80 YR |
2387 | * in MAC1. t=0,1 |
2388 | */ | |
2389 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST, | |
2390 | e3b0_val.mac_1_class_t_guarantied_hyst); | |
2391 | REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST, | |
2392 | e3b0_val.mac_1_class_t_guarantied_hyst); | |
2393 | } | |
9380bb9e | 2394 | |
9380bb9e | 2395 | return bnx2x_status; |
bcab15c5 VZ |
2396 | } |
2397 | ||
619c5cb6 VZ |
2398 | /****************************************************************************** |
2399 | * Description: | |
2400 | * This function is needed because NIG ARB_CREDIT_WEIGHT_X are | |
2401 | * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. | |
2402 | ******************************************************************************/ | |
d231023e YM |
2403 | static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, |
2404 | u8 cos_entry, | |
2405 | u32 priority_mask, u8 port) | |
619c5cb6 VZ |
2406 | { |
2407 | u32 nig_reg_rx_priority_mask_add = 0; | |
2408 | ||
2409 | switch (cos_entry) { | |
2410 | case 0: | |
2411 | nig_reg_rx_priority_mask_add = (port) ? | |
2412 | NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
2413 | NIG_REG_P0_RX_COS0_PRIORITY_MASK; | |
2414 | break; | |
2415 | case 1: | |
2416 | nig_reg_rx_priority_mask_add = (port) ? | |
2417 | NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
2418 | NIG_REG_P0_RX_COS1_PRIORITY_MASK; | |
2419 | break; | |
2420 | case 2: | |
2421 | nig_reg_rx_priority_mask_add = (port) ? | |
2422 | NIG_REG_P1_RX_COS2_PRIORITY_MASK : | |
2423 | NIG_REG_P0_RX_COS2_PRIORITY_MASK; | |
2424 | break; | |
2425 | case 3: | |
2426 | if (port) | |
2427 | return -EINVAL; | |
2428 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; | |
2429 | break; | |
2430 | case 4: | |
2431 | if (port) | |
2432 | return -EINVAL; | |
2433 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; | |
2434 | break; | |
2435 | case 5: | |
2436 | if (port) | |
2437 | return -EINVAL; | |
2438 | nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; | |
2439 | break; | |
2440 | } | |
2441 | ||
2442 | REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); | |
2443 | ||
2444 | return 0; | |
2445 | } | |
b8d6d082 YR |
2446 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) |
2447 | { | |
2448 | struct bnx2x *bp = params->bp; | |
2449 | ||
2450 | REG_WR(bp, params->shmem_base + | |
2451 | offsetof(struct shmem_region, | |
2452 | port_mb[params->port].link_status), link_status); | |
2453 | } | |
2454 | ||
bcab15c5 VZ |
2455 | static void bnx2x_update_pfc_nig(struct link_params *params, |
2456 | struct link_vars *vars, | |
2457 | struct bnx2x_nig_brb_pfc_port_params *nig_params) | |
2458 | { | |
2459 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; | |
127302bb | 2460 | u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; |
bcab15c5 | 2461 | u32 pkt_priority_to_cos = 0; |
bcab15c5 | 2462 | struct bnx2x *bp = params->bp; |
9380bb9e YR |
2463 | u8 port = params->port; |
2464 | ||
bcab15c5 VZ |
2465 | int set_pfc = params->feature_config_flags & |
2466 | FEATURE_CONFIG_PFC_ENABLED; | |
2467 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); | |
2468 | ||
8f73f0b9 | 2469 | /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
bcab15c5 VZ |
2470 | * MAC control frames (that are not pause packets) |
2471 | * will be forwarded to the XCM. | |
2472 | */ | |
127302bb YR |
2473 | xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : |
2474 | NIG_REG_LLH0_XCM_MASK); | |
8f73f0b9 | 2475 | /* NIG params will override non PFC params, since it's possible to |
bcab15c5 VZ |
2476 | * do transition from PFC to SAFC |
2477 | */ | |
2478 | if (set_pfc) { | |
2479 | pause_enable = 0; | |
2480 | llfc_out_en = 0; | |
2481 | llfc_enable = 0; | |
9380bb9e YR |
2482 | if (CHIP_IS_E3(bp)) |
2483 | ppp_enable = 0; | |
2484 | else | |
bcab15c5 VZ |
2485 | ppp_enable = 1; |
2486 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2487 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb YR |
2488 | xcm_out_en = 0; |
2489 | hwpfc_enable = 1; | |
bcab15c5 VZ |
2490 | } else { |
2491 | if (nig_params) { | |
2492 | llfc_out_en = nig_params->llfc_out_en; | |
2493 | llfc_enable = nig_params->llfc_enable; | |
2494 | pause_enable = nig_params->pause_enable; | |
8f73f0b9 | 2495 | } else /* Default non PFC mode - PAUSE */ |
bcab15c5 VZ |
2496 | pause_enable = 1; |
2497 | ||
2498 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
2499 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
127302bb | 2500 | xcm_out_en = 1; |
bcab15c5 VZ |
2501 | } |
2502 | ||
9380bb9e YR |
2503 | if (CHIP_IS_E3(bp)) |
2504 | REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : | |
2505 | NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); | |
bcab15c5 VZ |
2506 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : |
2507 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
2508 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : | |
2509 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
2510 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : | |
2511 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
2512 | ||
2513 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : | |
2514 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
2515 | ||
2516 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : | |
2517 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
2518 | ||
127302bb YR |
2519 | REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : |
2520 | NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
bcab15c5 | 2521 | |
d231023e | 2522 | /* Output enable for RX_XCM # IF */ |
127302bb YR |
2523 | REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : |
2524 | NIG_REG_XCM0_OUT_EN, xcm_out_en); | |
bcab15c5 VZ |
2525 | |
2526 | /* HW PFC TX enable */ | |
127302bb YR |
2527 | REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : |
2528 | NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); | |
bcab15c5 | 2529 | |
bcab15c5 | 2530 | if (nig_params) { |
619c5cb6 | 2531 | u8 i = 0; |
bcab15c5 VZ |
2532 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; |
2533 | ||
619c5cb6 VZ |
2534 | for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) |
2535 | bnx2x_pfc_nig_rx_priority_mask(bp, i, | |
2536 | nig_params->rx_cos_priority_mask[i], port); | |
bcab15c5 VZ |
2537 | |
2538 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
2539 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
2540 | nig_params->llfc_high_priority_classes); | |
2541 | ||
2542 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
2543 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
2544 | nig_params->llfc_low_priority_classes); | |
2545 | } | |
2546 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
2547 | NIG_REG_P0_PKT_PRIORITY_TO_COS, | |
2548 | pkt_priority_to_cos); | |
2549 | } | |
2550 | ||
9380bb9e | 2551 | int bnx2x_update_pfc(struct link_params *params, |
bcab15c5 VZ |
2552 | struct link_vars *vars, |
2553 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
2554 | { | |
8f73f0b9 | 2555 | /* The PFC and pause are orthogonal to one another, meaning when |
bcab15c5 VZ |
2556 | * PFC is enabled, the pause are disabled, and when PFC is |
2557 | * disabled, pause are set according to the pause result. | |
2558 | */ | |
2559 | u32 val; | |
2560 | struct bnx2x *bp = params->bp; | |
9380bb9e YR |
2561 | int bnx2x_status = 0; |
2562 | u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); | |
b8d6d082 YR |
2563 | |
2564 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
2565 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
2566 | else | |
2567 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
2568 | ||
2569 | bnx2x_update_mng(params, vars->link_status); | |
2570 | ||
d231023e | 2571 | /* Update NIG params */ |
bcab15c5 VZ |
2572 | bnx2x_update_pfc_nig(params, vars, pfc_params); |
2573 | ||
d231023e | 2574 | /* Update BRB params */ |
9380bb9e | 2575 | bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params); |
de0396f4 | 2576 | if (bnx2x_status) |
9380bb9e | 2577 | return bnx2x_status; |
bcab15c5 VZ |
2578 | |
2579 | if (!vars->link_up) | |
9380bb9e | 2580 | return bnx2x_status; |
bcab15c5 VZ |
2581 | |
2582 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); | |
9380bb9e YR |
2583 | if (CHIP_IS_E3(bp)) |
2584 | bnx2x_update_pfc_xmac(params, vars, 0); | |
2585 | else { | |
2586 | val = REG_RD(bp, MISC_REG_RESET_REG_2); | |
2587 | if ((val & | |
3c9ada22 | 2588 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) |
9380bb9e YR |
2589 | == 0) { |
2590 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); | |
2591 | bnx2x_emac_enable(params, vars, 0); | |
2592 | return bnx2x_status; | |
2593 | } | |
9380bb9e YR |
2594 | if (CHIP_IS_E2(bp)) |
2595 | bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); | |
2596 | else | |
2597 | bnx2x_update_pfc_bmac1(params, vars); | |
2598 | ||
2599 | val = 0; | |
2600 | if ((params->feature_config_flags & | |
2601 | FEATURE_CONFIG_PFC_ENABLED) || | |
2602 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
2603 | val = 1; | |
2604 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); | |
2605 | } | |
2606 | return bnx2x_status; | |
bcab15c5 | 2607 | } |
f2e0899f | 2608 | |
9380bb9e | 2609 | |
fcf5b650 YR |
2610 | static int bnx2x_bmac1_enable(struct link_params *params, |
2611 | struct link_vars *vars, | |
2612 | u8 is_lb) | |
ea4e040a YR |
2613 | { |
2614 | struct bnx2x *bp = params->bp; | |
2615 | u8 port = params->port; | |
2616 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2617 | NIG_REG_INGRESS_BMAC0_MEM; | |
2618 | u32 wb_data[2]; | |
2619 | u32 val; | |
2620 | ||
f2e0899f | 2621 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
2622 | |
2623 | /* XGXS control */ | |
2624 | wb_data[0] = 0x3c; | |
2625 | wb_data[1] = 0; | |
cd88ccee YR |
2626 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
2627 | wb_data, 2); | |
ea4e040a | 2628 | |
d231023e | 2629 | /* TX MAC SA */ |
ea4e040a YR |
2630 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2631 | (params->mac_addr[3] << 16) | | |
2632 | (params->mac_addr[4] << 8) | | |
2633 | params->mac_addr[5]); | |
2634 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2635 | params->mac_addr[1]); | |
cd88ccee | 2636 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
ea4e040a | 2637 | |
d231023e | 2638 | /* MAC control */ |
ea4e040a YR |
2639 | val = 0x3; |
2640 | if (is_lb) { | |
2641 | val |= 0x4; | |
2642 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
2643 | } | |
2644 | wb_data[0] = val; | |
2645 | wb_data[1] = 0; | |
cd88ccee | 2646 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
ea4e040a | 2647 | |
d231023e | 2648 | /* Set rx mtu */ |
ea4e040a YR |
2649 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2650 | wb_data[1] = 0; | |
cd88ccee | 2651 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2652 | |
bcab15c5 | 2653 | bnx2x_update_pfc_bmac1(params, vars); |
ea4e040a | 2654 | |
d231023e | 2655 | /* Set tx mtu */ |
ea4e040a YR |
2656 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2657 | wb_data[1] = 0; | |
cd88ccee | 2658 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
ea4e040a | 2659 | |
d231023e | 2660 | /* Set cnt max size */ |
ea4e040a YR |
2661 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2662 | wb_data[1] = 0; | |
cd88ccee | 2663 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
ea4e040a | 2664 | |
d231023e | 2665 | /* Configure SAFC */ |
ea4e040a YR |
2666 | wb_data[0] = 0x1000200; |
2667 | wb_data[1] = 0; | |
2668 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
2669 | wb_data, 2); | |
f2e0899f DK |
2670 | |
2671 | return 0; | |
2672 | } | |
2673 | ||
fcf5b650 YR |
2674 | static int bnx2x_bmac2_enable(struct link_params *params, |
2675 | struct link_vars *vars, | |
2676 | u8 is_lb) | |
f2e0899f DK |
2677 | { |
2678 | struct bnx2x *bp = params->bp; | |
2679 | u8 port = params->port; | |
2680 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
2681 | NIG_REG_INGRESS_BMAC0_MEM; | |
2682 | u32 wb_data[2]; | |
2683 | ||
2684 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
2685 | ||
2686 | wb_data[0] = 0; | |
2687 | wb_data[1] = 0; | |
cd88ccee | 2688 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
2689 | udelay(30); |
2690 | ||
2691 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
2692 | wb_data[0] = 0x3c; | |
2693 | wb_data[1] = 0; | |
cd88ccee YR |
2694 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
2695 | wb_data, 2); | |
f2e0899f DK |
2696 | |
2697 | udelay(30); | |
2698 | ||
d231023e | 2699 | /* TX MAC SA */ |
f2e0899f DK |
2700 | wb_data[0] = ((params->mac_addr[2] << 24) | |
2701 | (params->mac_addr[3] << 16) | | |
2702 | (params->mac_addr[4] << 8) | | |
2703 | params->mac_addr[5]); | |
2704 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
2705 | params->mac_addr[1]); | |
2706 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
cd88ccee | 2707 | wb_data, 2); |
f2e0899f DK |
2708 | |
2709 | udelay(30); | |
2710 | ||
2711 | /* Configure SAFC */ | |
2712 | wb_data[0] = 0x1000200; | |
2713 | wb_data[1] = 0; | |
2714 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
cd88ccee | 2715 | wb_data, 2); |
f2e0899f DK |
2716 | udelay(30); |
2717 | ||
d231023e | 2718 | /* Set RX MTU */ |
f2e0899f DK |
2719 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2720 | wb_data[1] = 0; | |
cd88ccee | 2721 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
2722 | udelay(30); |
2723 | ||
d231023e | 2724 | /* Set TX MTU */ |
f2e0899f DK |
2725 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; |
2726 | wb_data[1] = 0; | |
cd88ccee | 2727 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
f2e0899f | 2728 | udelay(30); |
d231023e | 2729 | /* Set cnt max size */ |
f2e0899f DK |
2730 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; |
2731 | wb_data[1] = 0; | |
cd88ccee | 2732 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
f2e0899f | 2733 | udelay(30); |
bcab15c5 | 2734 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
f2e0899f DK |
2735 | |
2736 | return 0; | |
2737 | } | |
2738 | ||
fcf5b650 YR |
2739 | static int bnx2x_bmac_enable(struct link_params *params, |
2740 | struct link_vars *vars, | |
2741 | u8 is_lb) | |
f2e0899f | 2742 | { |
fcf5b650 YR |
2743 | int rc = 0; |
2744 | u8 port = params->port; | |
f2e0899f DK |
2745 | struct bnx2x *bp = params->bp; |
2746 | u32 val; | |
d231023e | 2747 | /* Reset and unreset the BigMac */ |
f2e0899f | 2748 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
cd88ccee | 2749 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
d231023e | 2750 | usleep_range(1000, 2000); |
f2e0899f DK |
2751 | |
2752 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 2753 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
f2e0899f | 2754 | |
d231023e | 2755 | /* Enable access for bmac registers */ |
f2e0899f DK |
2756 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); |
2757 | ||
2758 | /* Enable BMAC according to BMAC type*/ | |
2759 | if (CHIP_IS_E2(bp)) | |
2760 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
2761 | else | |
2762 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
2763 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
2764 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
2765 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
2766 | val = 0; | |
bcab15c5 VZ |
2767 | if ((params->feature_config_flags & |
2768 | FEATURE_CONFIG_PFC_ENABLED) || | |
2769 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
2770 | val = 1; |
2771 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
2772 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
2773 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
2774 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
2775 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
2776 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
2777 | ||
2778 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 2779 | return rc; |
ea4e040a YR |
2780 | } |
2781 | ||
ea4e040a YR |
2782 | static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) |
2783 | { | |
2784 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
cd88ccee | 2785 | NIG_REG_INGRESS_BMAC0_MEM; |
ea4e040a | 2786 | u32 wb_data[2]; |
3196a88a | 2787 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a YR |
2788 | |
2789 | /* Only if the bmac is out of reset */ | |
2790 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
2791 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
2792 | nig_bmac_enable) { | |
2793 | ||
f2e0899f DK |
2794 | if (CHIP_IS_E2(bp)) { |
2795 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2796 | REG_RD_DMAE(bp, bmac_addr + | |
cd88ccee YR |
2797 | BIGMAC2_REGISTER_BMAC_CONTROL, |
2798 | wb_data, 2); | |
f2e0899f DK |
2799 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
2800 | REG_WR_DMAE(bp, bmac_addr + | |
cd88ccee YR |
2801 | BIGMAC2_REGISTER_BMAC_CONTROL, |
2802 | wb_data, 2); | |
f2e0899f DK |
2803 | } else { |
2804 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
2805 | REG_RD_DMAE(bp, bmac_addr + | |
2806 | BIGMAC_REGISTER_BMAC_CONTROL, | |
2807 | wb_data, 2); | |
2808 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
2809 | REG_WR_DMAE(bp, bmac_addr + | |
2810 | BIGMAC_REGISTER_BMAC_CONTROL, | |
2811 | wb_data, 2); | |
2812 | } | |
d231023e | 2813 | usleep_range(1000, 2000); |
ea4e040a YR |
2814 | } |
2815 | } | |
2816 | ||
fcf5b650 YR |
2817 | static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, |
2818 | u32 line_speed) | |
ea4e040a YR |
2819 | { |
2820 | struct bnx2x *bp = params->bp; | |
2821 | u8 port = params->port; | |
2822 | u32 init_crd, crd; | |
2823 | u32 count = 1000; | |
ea4e040a | 2824 | |
d231023e | 2825 | /* Disable port */ |
ea4e040a YR |
2826 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); |
2827 | ||
d231023e | 2828 | /* Wait for init credit */ |
ea4e040a YR |
2829 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); |
2830 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2831 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
2832 | ||
2833 | while ((init_crd != crd) && count) { | |
d231023e | 2834 | usleep_range(5000, 10000); |
ea4e040a YR |
2835 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); |
2836 | count--; | |
2837 | } | |
2838 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
2839 | if (init_crd != crd) { | |
2840 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
2841 | init_crd, crd); | |
2842 | return -EINVAL; | |
2843 | } | |
2844 | ||
c0700f90 | 2845 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
2846 | line_speed == SPEED_10 || |
2847 | line_speed == SPEED_100 || | |
2848 | line_speed == SPEED_1000 || | |
2849 | line_speed == SPEED_2500) { | |
2850 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
d231023e | 2851 | /* Update threshold */ |
ea4e040a | 2852 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); |
d231023e | 2853 | /* Update init credit */ |
cd88ccee | 2854 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
2855 | |
2856 | } else { | |
2857 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
2858 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 2859 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
d231023e | 2860 | /* Update threshold */ |
ea4e040a | 2861 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); |
d231023e | 2862 | /* Update init credit */ |
ea4e040a | 2863 | switch (line_speed) { |
ea4e040a YR |
2864 | case SPEED_10000: |
2865 | init_crd = thresh + 553 - 22; | |
2866 | break; | |
ea4e040a YR |
2867 | default: |
2868 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
2869 | line_speed); | |
2870 | return -EINVAL; | |
ea4e040a YR |
2871 | } |
2872 | } | |
2873 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
2874 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
2875 | line_speed, init_crd); | |
2876 | ||
d231023e | 2877 | /* Probe the credit changes */ |
ea4e040a | 2878 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); |
d231023e | 2879 | usleep_range(5000, 10000); |
ea4e040a YR |
2880 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); |
2881 | ||
d231023e | 2882 | /* Enable port */ |
ea4e040a YR |
2883 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); |
2884 | return 0; | |
2885 | } | |
2886 | ||
e8920674 DK |
2887 | /** |
2888 | * bnx2x_get_emac_base - retrive emac base address | |
2cf7acf9 | 2889 | * |
e8920674 DK |
2890 | * @bp: driver handle |
2891 | * @mdc_mdio_access: access type | |
2892 | * @port: port id | |
2cf7acf9 YR |
2893 | * |
2894 | * This function selects the MDC/MDIO access (through emac0 or | |
2895 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
2896 | * phy has a default access mode, which could also be overridden | |
2897 | * by nvram configuration. This parameter, whether this is the | |
2898 | * default phy configuration, or the nvram overrun | |
2899 | * configuration, is passed here as mdc_mdio_access and selects | |
2900 | * the emac_base for the CL45 read/writes operations | |
2901 | */ | |
c18aa15d YR |
2902 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
2903 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 2904 | { |
c18aa15d YR |
2905 | u32 emac_base = 0; |
2906 | switch (mdc_mdio_access) { | |
2907 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
2908 | break; | |
2909 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
2910 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
2911 | emac_base = GRCBASE_EMAC1; | |
2912 | else | |
2913 | emac_base = GRCBASE_EMAC0; | |
2914 | break; | |
2915 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
2916 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
2917 | emac_base = GRCBASE_EMAC0; | |
2918 | else | |
2919 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 2920 | break; |
c18aa15d YR |
2921 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
2922 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
2923 | break; | |
2924 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 2925 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
2926 | break; |
2927 | default: | |
ea4e040a YR |
2928 | break; |
2929 | } | |
2930 | return emac_base; | |
2931 | ||
2932 | } | |
2933 | ||
6583e33b YR |
2934 | /******************************************************************/ |
2935 | /* CL22 access functions */ | |
2936 | /******************************************************************/ | |
2937 | static int bnx2x_cl22_write(struct bnx2x *bp, | |
2938 | struct bnx2x_phy *phy, | |
2939 | u16 reg, u16 val) | |
2940 | { | |
2941 | u32 tmp, mode; | |
2942 | u8 i; | |
2943 | int rc = 0; | |
2944 | /* Switch to CL22 */ | |
2945 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2946 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2947 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2948 | ||
d231023e | 2949 | /* Address */ |
6583e33b YR |
2950 | tmp = ((phy->addr << 21) | (reg << 16) | val | |
2951 | EMAC_MDIO_COMM_COMMAND_WRITE_22 | | |
2952 | EMAC_MDIO_COMM_START_BUSY); | |
2953 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); | |
2954 | ||
2955 | for (i = 0; i < 50; i++) { | |
2956 | udelay(10); | |
2957 | ||
2958 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2959 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
2960 | udelay(5); | |
2961 | break; | |
2962 | } | |
2963 | } | |
2964 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
2965 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
2966 | rc = -EFAULT; | |
2967 | } | |
2968 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
2969 | return rc; | |
2970 | } | |
2971 | ||
2972 | static int bnx2x_cl22_read(struct bnx2x *bp, | |
2973 | struct bnx2x_phy *phy, | |
2974 | u16 reg, u16 *ret_val) | |
2975 | { | |
2976 | u32 val, mode; | |
2977 | u16 i; | |
2978 | int rc = 0; | |
2979 | ||
2980 | /* Switch to CL22 */ | |
2981 | mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
2982 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, | |
2983 | mode & ~EMAC_MDIO_MODE_CLAUSE_45); | |
2984 | ||
d231023e | 2985 | /* Address */ |
6583e33b YR |
2986 | val = ((phy->addr << 21) | (reg << 16) | |
2987 | EMAC_MDIO_COMM_COMMAND_READ_22 | | |
2988 | EMAC_MDIO_COMM_START_BUSY); | |
2989 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); | |
2990 | ||
2991 | for (i = 0; i < 50; i++) { | |
2992 | udelay(10); | |
2993 | ||
2994 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); | |
2995 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
2996 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
2997 | udelay(5); | |
2998 | break; | |
2999 | } | |
3000 | } | |
3001 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
3002 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
3003 | ||
3004 | *ret_val = 0; | |
3005 | rc = -EFAULT; | |
3006 | } | |
3007 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); | |
3008 | return rc; | |
3009 | } | |
3010 | ||
2cf7acf9 YR |
3011 | /******************************************************************/ |
3012 | /* CL45 access functions */ | |
3013 | /******************************************************************/ | |
a198c142 YR |
3014 | static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
3015 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a | 3016 | { |
a198c142 YR |
3017 | u32 val; |
3018 | u16 i; | |
fcf5b650 | 3019 | int rc = 0; |
157fa283 YR |
3020 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3021 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3022 | EMAC_MDIO_STATUS_10MB); | |
d231023e | 3023 | /* Address */ |
a198c142 | 3024 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
3025 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
3026 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 3027 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
3028 | |
3029 | for (i = 0; i < 50; i++) { | |
3030 | udelay(10); | |
3031 | ||
a198c142 YR |
3032 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
3033 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
3034 | udelay(5); |
3035 | break; | |
3036 | } | |
3037 | } | |
a198c142 YR |
3038 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
3039 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 3040 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 3041 | *ret_val = 0; |
ea4e040a YR |
3042 | rc = -EFAULT; |
3043 | } else { | |
d231023e | 3044 | /* Data */ |
a198c142 YR |
3045 | val = ((phy->addr << 21) | (devad << 16) | |
3046 | EMAC_MDIO_COMM_COMMAND_READ_45 | | |
ea4e040a | 3047 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 3048 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
3049 | |
3050 | for (i = 0; i < 50; i++) { | |
3051 | udelay(10); | |
3052 | ||
a198c142 | 3053 | val = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 3054 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
3055 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
3056 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
ea4e040a YR |
3057 | break; |
3058 | } | |
3059 | } | |
a198c142 YR |
3060 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
3061 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
6d870c39 | 3062 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
a198c142 | 3063 | *ret_val = 0; |
ea4e040a YR |
3064 | rc = -EFAULT; |
3065 | } | |
3066 | } | |
3c9ada22 YR |
3067 | /* Work around for E3 A0 */ |
3068 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
3069 | phy->flags ^= FLAGS_DUMMY_READ; | |
3070 | if (phy->flags & FLAGS_DUMMY_READ) { | |
3071 | u16 temp_val; | |
3072 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
3073 | } | |
3074 | } | |
ea4e040a | 3075 | |
157fa283 YR |
3076 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3077 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3078 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a YR |
3079 | return rc; |
3080 | } | |
3081 | ||
a198c142 YR |
3082 | static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3083 | u8 devad, u16 reg, u16 val) | |
ea4e040a | 3084 | { |
a198c142 YR |
3085 | u32 tmp; |
3086 | u8 i; | |
fcf5b650 | 3087 | int rc = 0; |
157fa283 YR |
3088 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3089 | bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3090 | EMAC_MDIO_STATUS_10MB); | |
ea4e040a | 3091 | |
d231023e | 3092 | /* Address */ |
a198c142 | 3093 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
3094 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
3095 | EMAC_MDIO_COMM_START_BUSY); | |
a198c142 | 3096 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
3097 | |
3098 | for (i = 0; i < 50; i++) { | |
3099 | udelay(10); | |
3100 | ||
a198c142 YR |
3101 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
3102 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
ea4e040a YR |
3103 | udelay(5); |
3104 | break; | |
3105 | } | |
3106 | } | |
a198c142 YR |
3107 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
3108 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 3109 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a | 3110 | rc = -EFAULT; |
ea4e040a | 3111 | } else { |
d231023e | 3112 | /* Data */ |
a198c142 YR |
3113 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
3114 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | |
ea4e040a | 3115 | EMAC_MDIO_COMM_START_BUSY); |
a198c142 | 3116 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
3117 | |
3118 | for (i = 0; i < 50; i++) { | |
3119 | udelay(10); | |
3120 | ||
a198c142 | 3121 | tmp = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 3122 | EMAC_REG_EMAC_MDIO_COMM); |
a198c142 YR |
3123 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
3124 | udelay(5); | |
ea4e040a YR |
3125 | break; |
3126 | } | |
3127 | } | |
a198c142 YR |
3128 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
3129 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
6d870c39 | 3130 | netdev_err(bp->dev, "MDC/MDIO access timeout\n"); |
ea4e040a YR |
3131 | rc = -EFAULT; |
3132 | } | |
3133 | } | |
3c9ada22 YR |
3134 | /* Work around for E3 A0 */ |
3135 | if (phy->flags & FLAGS_MDC_MDIO_WA) { | |
3136 | phy->flags ^= FLAGS_DUMMY_READ; | |
3137 | if (phy->flags & FLAGS_DUMMY_READ) { | |
3138 | u16 temp_val; | |
3139 | bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); | |
3140 | } | |
3141 | } | |
157fa283 YR |
3142 | if (phy->flags & FLAGS_MDC_MDIO_WA_B0) |
3143 | bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, | |
3144 | EMAC_MDIO_STATUS_10MB); | |
3c9ada22 YR |
3145 | return rc; |
3146 | } | |
ec4010ec YM |
3147 | |
3148 | /******************************************************************/ | |
3149 | /* EEE section */ | |
3150 | /******************************************************************/ | |
3151 | static u8 bnx2x_eee_has_cap(struct link_params *params) | |
3152 | { | |
3153 | struct bnx2x *bp = params->bp; | |
3154 | ||
3155 | if (REG_RD(bp, params->shmem2_base) <= | |
3156 | offsetof(struct shmem2_region, eee_status[params->port])) | |
3157 | return 0; | |
3158 | ||
3159 | return 1; | |
3160 | } | |
3161 | ||
3162 | static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) | |
3163 | { | |
3164 | switch (nvram_mode) { | |
3165 | case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: | |
3166 | *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME; | |
3167 | break; | |
3168 | case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: | |
3169 | *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME; | |
3170 | break; | |
3171 | case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: | |
3172 | *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME; | |
3173 | break; | |
3174 | default: | |
3175 | *idle_timer = 0; | |
3176 | break; | |
3177 | } | |
3178 | ||
3179 | return 0; | |
3180 | } | |
3181 | ||
3182 | static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) | |
3183 | { | |
3184 | switch (idle_timer) { | |
3185 | case EEE_MODE_NVRAM_BALANCED_TIME: | |
3186 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; | |
3187 | break; | |
3188 | case EEE_MODE_NVRAM_AGGRESSIVE_TIME: | |
3189 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; | |
3190 | break; | |
3191 | case EEE_MODE_NVRAM_LATENCY_TIME: | |
3192 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; | |
3193 | break; | |
3194 | default: | |
3195 | *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; | |
3196 | break; | |
3197 | } | |
3198 | ||
3199 | return 0; | |
3200 | } | |
3201 | ||
3202 | static u32 bnx2x_eee_calc_timer(struct link_params *params) | |
3203 | { | |
3204 | u32 eee_mode, eee_idle; | |
3205 | struct bnx2x *bp = params->bp; | |
3206 | ||
3207 | if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { | |
3208 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
3209 | /* time value in eee_mode --> used directly*/ | |
3210 | eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; | |
3211 | } else { | |
3212 | /* hsi value in eee_mode --> time */ | |
3213 | if (bnx2x_eee_nvram_to_time(params->eee_mode & | |
3214 | EEE_MODE_NVRAM_MASK, | |
3215 | &eee_idle)) | |
3216 | return 0; | |
3217 | } | |
3218 | } else { | |
3219 | /* hsi values in nvram --> time*/ | |
3220 | eee_mode = ((REG_RD(bp, params->shmem_base + | |
3221 | offsetof(struct shmem_region, dev_info. | |
3222 | port_feature_config[params->port]. | |
3223 | eee_power_mode)) & | |
3224 | PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> | |
3225 | PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); | |
3226 | ||
3227 | if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle)) | |
3228 | return 0; | |
3229 | } | |
3230 | ||
3231 | return eee_idle; | |
3232 | } | |
3233 | ||
3234 | static int bnx2x_eee_set_timers(struct link_params *params, | |
3235 | struct link_vars *vars) | |
3236 | { | |
3237 | u32 eee_idle = 0, eee_mode; | |
3238 | struct bnx2x *bp = params->bp; | |
3239 | ||
3240 | eee_idle = bnx2x_eee_calc_timer(params); | |
3241 | ||
3242 | if (eee_idle) { | |
3243 | REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), | |
3244 | eee_idle); | |
3245 | } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && | |
3246 | (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && | |
3247 | (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { | |
3248 | DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); | |
3249 | return -EINVAL; | |
3250 | } | |
3251 | ||
3252 | vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); | |
3253 | if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { | |
3254 | /* eee_idle in 1u --> eee_status in 16u */ | |
3255 | eee_idle >>= 4; | |
3256 | vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | | |
3257 | SHMEM_EEE_TIME_OUTPUT_BIT; | |
3258 | } else { | |
3259 | if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode)) | |
3260 | return -EINVAL; | |
3261 | vars->eee_status |= eee_mode; | |
3262 | } | |
3263 | ||
3264 | return 0; | |
3265 | } | |
3266 | ||
3267 | static int bnx2x_eee_initial_config(struct link_params *params, | |
3268 | struct link_vars *vars, u8 mode) | |
3269 | { | |
3270 | vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; | |
3271 | ||
3272 | /* Propogate params' bits --> vars (for migration exposure) */ | |
3273 | if (params->eee_mode & EEE_MODE_ENABLE_LPI) | |
3274 | vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; | |
3275 | else | |
3276 | vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; | |
3277 | ||
3278 | if (params->eee_mode & EEE_MODE_ADV_LPI) | |
3279 | vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; | |
3280 | else | |
3281 | vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; | |
3282 | ||
3283 | return bnx2x_eee_set_timers(params, vars); | |
3284 | } | |
3285 | ||
3286 | static int bnx2x_eee_disable(struct bnx2x_phy *phy, | |
3287 | struct link_params *params, | |
3288 | struct link_vars *vars) | |
3289 | { | |
3290 | struct bnx2x *bp = params->bp; | |
3291 | ||
3292 | /* Make Certain LPI is disabled */ | |
3293 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); | |
3294 | ||
3295 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); | |
3296 | ||
3297 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
3298 | ||
3299 | return 0; | |
3300 | } | |
3301 | ||
3302 | static int bnx2x_eee_advertise(struct bnx2x_phy *phy, | |
3303 | struct link_params *params, | |
3304 | struct link_vars *vars, u8 modes) | |
3305 | { | |
3306 | struct bnx2x *bp = params->bp; | |
3307 | u16 val = 0; | |
3308 | ||
3309 | /* Mask events preventing LPI generation */ | |
3310 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); | |
3311 | ||
3312 | if (modes & SHMEM_EEE_10G_ADV) { | |
3313 | DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); | |
3314 | val |= 0x8; | |
3315 | } | |
3316 | if (modes & SHMEM_EEE_1G_ADV) { | |
3317 | DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); | |
3318 | val |= 0x4; | |
3319 | } | |
3320 | ||
3321 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); | |
3322 | ||
3323 | vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; | |
3324 | vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); | |
3325 | ||
3326 | return 0; | |
3327 | } | |
3328 | ||
3329 | static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status) | |
3330 | { | |
3331 | struct bnx2x *bp = params->bp; | |
3332 | ||
3333 | if (bnx2x_eee_has_cap(params)) | |
3334 | REG_WR(bp, params->shmem2_base + | |
3335 | offsetof(struct shmem2_region, | |
3336 | eee_status[params->port]), eee_status); | |
3337 | } | |
3338 | ||
3339 | static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy, | |
3340 | struct link_params *params, | |
3341 | struct link_vars *vars) | |
3342 | { | |
3343 | struct bnx2x *bp = params->bp; | |
3344 | u16 adv = 0, lp = 0; | |
3345 | u32 lp_adv = 0; | |
3346 | u8 neg = 0; | |
3347 | ||
3348 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); | |
3349 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); | |
3350 | ||
3351 | if (lp & 0x2) { | |
3352 | lp_adv |= SHMEM_EEE_100M_ADV; | |
3353 | if (adv & 0x2) { | |
3354 | if (vars->line_speed == SPEED_100) | |
3355 | neg = 1; | |
3356 | DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); | |
3357 | } | |
3358 | } | |
3359 | if (lp & 0x14) { | |
3360 | lp_adv |= SHMEM_EEE_1G_ADV; | |
3361 | if (adv & 0x14) { | |
3362 | if (vars->line_speed == SPEED_1000) | |
3363 | neg = 1; | |
3364 | DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); | |
3365 | } | |
3366 | } | |
3367 | if (lp & 0x68) { | |
3368 | lp_adv |= SHMEM_EEE_10G_ADV; | |
3369 | if (adv & 0x68) { | |
3370 | if (vars->line_speed == SPEED_10000) | |
3371 | neg = 1; | |
3372 | DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); | |
3373 | } | |
3374 | } | |
3375 | ||
3376 | vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; | |
3377 | vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); | |
3378 | ||
3379 | if (neg) { | |
3380 | DP(NETIF_MSG_LINK, "EEE is active\n"); | |
3381 | vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; | |
3382 | } | |
3383 | ||
3384 | } | |
3385 | ||
3c9ada22 YR |
3386 | /******************************************************************/ |
3387 | /* BSC access functions from E3 */ | |
3388 | /******************************************************************/ | |
3389 | static void bnx2x_bsc_module_sel(struct link_params *params) | |
3390 | { | |
3391 | int idx; | |
3392 | u32 board_cfg, sfp_ctrl; | |
3393 | u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; | |
3394 | struct bnx2x *bp = params->bp; | |
3395 | u8 port = params->port; | |
3396 | /* Read I2C output PINs */ | |
3397 | board_cfg = REG_RD(bp, params->shmem_base + | |
3398 | offsetof(struct shmem_region, | |
3399 | dev_info.shared_hw_config.board)); | |
3400 | i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; | |
3401 | i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> | |
3402 | SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; | |
3403 | ||
3404 | /* Read I2C output value */ | |
3405 | sfp_ctrl = REG_RD(bp, params->shmem_base + | |
3406 | offsetof(struct shmem_region, | |
3407 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)); | |
3408 | i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; | |
3409 | i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; | |
3410 | DP(NETIF_MSG_LINK, "Setting BSC switch\n"); | |
3411 | for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) | |
3412 | bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); | |
3413 | } | |
3414 | ||
3415 | static int bnx2x_bsc_read(struct link_params *params, | |
3416 | struct bnx2x_phy *phy, | |
3417 | u8 sl_devid, | |
3418 | u16 sl_addr, | |
3419 | u8 lc_addr, | |
3420 | u8 xfer_cnt, | |
3421 | u32 *data_array) | |
3422 | { | |
3423 | u32 val, i; | |
3424 | int rc = 0; | |
3425 | struct bnx2x *bp = params->bp; | |
3426 | ||
3427 | if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) { | |
3428 | DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid); | |
3429 | return -EINVAL; | |
3430 | } | |
3431 | ||
3432 | if (xfer_cnt > 16) { | |
3433 | DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n", | |
3434 | xfer_cnt); | |
3435 | return -EINVAL; | |
3436 | } | |
3437 | bnx2x_bsc_module_sel(params); | |
3438 | ||
3439 | xfer_cnt = 16 - lc_addr; | |
3440 | ||
d231023e | 3441 | /* Enable the engine */ |
3c9ada22 YR |
3442 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); |
3443 | val |= MCPR_IMC_COMMAND_ENABLE; | |
3444 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3445 | ||
d231023e | 3446 | /* Program slave device ID */ |
3c9ada22 YR |
3447 | val = (sl_devid << 16) | sl_addr; |
3448 | REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); | |
3449 | ||
d231023e | 3450 | /* Start xfer with 0 byte to update the address pointer ???*/ |
3c9ada22 YR |
3451 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3452 | (MCPR_IMC_COMMAND_WRITE_OP << | |
3453 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3454 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); | |
3455 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3456 | ||
d231023e | 3457 | /* Poll for completion */ |
3c9ada22 YR |
3458 | i = 0; |
3459 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3460 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3461 | udelay(10); | |
3462 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3463 | if (i++ > 1000) { | |
3464 | DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n", | |
3465 | i); | |
3466 | rc = -EFAULT; | |
3467 | break; | |
3468 | } | |
3469 | } | |
3470 | if (rc == -EFAULT) | |
3471 | return rc; | |
3472 | ||
d231023e | 3473 | /* Start xfer with read op */ |
3c9ada22 YR |
3474 | val = (MCPR_IMC_COMMAND_ENABLE) | |
3475 | (MCPR_IMC_COMMAND_READ_OP << | |
3476 | MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | | |
3477 | (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | | |
3478 | (xfer_cnt); | |
3479 | REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); | |
3480 | ||
d231023e | 3481 | /* Poll for completion */ |
3c9ada22 YR |
3482 | i = 0; |
3483 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3484 | while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { | |
3485 | udelay(10); | |
3486 | val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); | |
3487 | if (i++ > 1000) { | |
3488 | DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i); | |
3489 | rc = -EFAULT; | |
3490 | break; | |
3491 | } | |
3492 | } | |
3493 | if (rc == -EFAULT) | |
3494 | return rc; | |
3495 | ||
3496 | for (i = (lc_addr >> 2); i < 4; i++) { | |
3497 | data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); | |
3498 | #ifdef __BIG_ENDIAN | |
3499 | data_array[i] = ((data_array[i] & 0x000000ff) << 24) | | |
3500 | ((data_array[i] & 0x0000ff00) << 8) | | |
3501 | ((data_array[i] & 0x00ff0000) >> 8) | | |
3502 | ((data_array[i] & 0xff000000) >> 24); | |
3503 | #endif | |
3504 | } | |
ea4e040a YR |
3505 | return rc; |
3506 | } | |
3507 | ||
3c9ada22 YR |
3508 | static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
3509 | u8 devad, u16 reg, u16 or_val) | |
3510 | { | |
3511 | u16 val; | |
3512 | bnx2x_cl45_read(bp, phy, devad, reg, &val); | |
3513 | bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); | |
3514 | } | |
3515 | ||
fcf5b650 YR |
3516 | int bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
3517 | u8 devad, u16 reg, u16 *ret_val) | |
e10bc84d YR |
3518 | { |
3519 | u8 phy_index; | |
8f73f0b9 | 3520 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3521 | * the read request on it |
3522 | */ | |
3523 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3524 | if (params->phy[phy_index].addr == phy_addr) { | |
3525 | return bnx2x_cl45_read(params->bp, | |
3526 | ¶ms->phy[phy_index], devad, | |
3527 | reg, ret_val); | |
3528 | } | |
3529 | } | |
3530 | return -EINVAL; | |
3531 | } | |
3532 | ||
fcf5b650 YR |
3533 | int bnx2x_phy_write(struct link_params *params, u8 phy_addr, |
3534 | u8 devad, u16 reg, u16 val) | |
e10bc84d YR |
3535 | { |
3536 | u8 phy_index; | |
8f73f0b9 | 3537 | /* Probe for the phy according to the given phy_addr, and execute |
e10bc84d YR |
3538 | * the write request on it |
3539 | */ | |
3540 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
3541 | if (params->phy[phy_index].addr == phy_addr) { | |
3542 | return bnx2x_cl45_write(params->bp, | |
3543 | ¶ms->phy[phy_index], devad, | |
3544 | reg, val); | |
3545 | } | |
3546 | } | |
3547 | return -EINVAL; | |
3548 | } | |
3c9ada22 YR |
3549 | static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy, |
3550 | struct link_params *params) | |
3551 | { | |
3552 | u8 lane = 0; | |
3553 | struct bnx2x *bp = params->bp; | |
3554 | u32 path_swap, path_swap_ovr; | |
3555 | u8 path, port; | |
3556 | ||
3557 | path = BP_PATH(bp); | |
3558 | port = params->port; | |
3559 | ||
3560 | if (bnx2x_is_4_port_mode(bp)) { | |
3561 | u32 port_swap, port_swap_ovr; | |
3562 | ||
8f73f0b9 | 3563 | /* Figure out path swap value */ |
3c9ada22 YR |
3564 | path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); |
3565 | if (path_swap_ovr & 0x1) | |
3566 | path_swap = (path_swap_ovr & 0x2); | |
3567 | else | |
3568 | path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); | |
3569 | ||
3570 | if (path_swap) | |
3571 | path = path ^ 1; | |
3572 | ||
8f73f0b9 | 3573 | /* Figure out port swap value */ |
3c9ada22 YR |
3574 | port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); |
3575 | if (port_swap_ovr & 0x1) | |
3576 | port_swap = (port_swap_ovr & 0x2); | |
3577 | else | |
3578 | port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); | |
3579 | ||
3580 | if (port_swap) | |
3581 | port = port ^ 1; | |
3582 | ||
3583 | lane = (port<<1) + path; | |
d231023e | 3584 | } else { /* Two port mode - no port swap */ |
3c9ada22 | 3585 | |
8f73f0b9 | 3586 | /* Figure out path swap value */ |
3c9ada22 YR |
3587 | path_swap_ovr = |
3588 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); | |
3589 | if (path_swap_ovr & 0x1) { | |
3590 | path_swap = (path_swap_ovr & 0x2); | |
3591 | } else { | |
3592 | path_swap = | |
3593 | REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); | |
3594 | } | |
3595 | if (path_swap) | |
3596 | path = path ^ 1; | |
3597 | ||
3598 | lane = path << 1 ; | |
3599 | } | |
3600 | return lane; | |
3601 | } | |
e10bc84d | 3602 | |
ec146a6f YR |
3603 | static void bnx2x_set_aer_mmd(struct link_params *params, |
3604 | struct bnx2x_phy *phy) | |
ea4e040a | 3605 | { |
ea4e040a | 3606 | u32 ser_lane; |
f2e0899f DK |
3607 | u16 offset, aer_val; |
3608 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
3609 | ser_lane = ((params->lane_config & |
3610 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
3611 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3612 | ||
ec146a6f YR |
3613 | offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? |
3614 | (phy->addr + ser_lane) : 0; | |
3615 | ||
3c9ada22 YR |
3616 | if (USES_WARPCORE(bp)) { |
3617 | aer_val = bnx2x_get_warpcore_lane(phy, params); | |
8f73f0b9 | 3618 | /* In Dual-lane mode, two lanes are joined together, |
3c9ada22 YR |
3619 | * so in order to configure them, the AER broadcast method is |
3620 | * used here. | |
3621 | * 0x200 is the broadcast address for lanes 0,1 | |
3622 | * 0x201 is the broadcast address for lanes 2,3 | |
3623 | */ | |
3624 | if (phy->flags & FLAGS_WC_DUAL_MODE) | |
3625 | aer_val = (aer_val >> 1) | 0x200; | |
3626 | } else if (CHIP_IS_E2(bp)) | |
82a0d475 | 3627 | aer_val = 0x3800 + offset - 1; |
f2e0899f DK |
3628 | else |
3629 | aer_val = 0x3800 + offset; | |
2f751a80 | 3630 | |
cd2be89b | 3631 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
cd88ccee | 3632 | MDIO_AER_BLOCK_AER_REG, aer_val); |
ec146a6f | 3633 | |
ea4e040a YR |
3634 | } |
3635 | ||
de6eae1f YR |
3636 | /******************************************************************/ |
3637 | /* Internal phy section */ | |
3638 | /******************************************************************/ | |
ea4e040a | 3639 | |
de6eae1f YR |
3640 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
3641 | { | |
3642 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 3643 | |
de6eae1f YR |
3644 | /* Set Clause 22 */ |
3645 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
3646 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
3647 | udelay(500); | |
3648 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
3649 | udelay(500); | |
3650 | /* Set Clause 45 */ | |
3651 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
3652 | } |
3653 | ||
de6eae1f | 3654 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 3655 | { |
de6eae1f | 3656 | u32 val; |
ea4e040a | 3657 | |
de6eae1f | 3658 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 3659 | |
de6eae1f | 3660 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 3661 | |
d231023e | 3662 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3663 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3664 | udelay(500); | |
3665 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 3666 | |
de6eae1f | 3667 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 3668 | |
cd88ccee YR |
3669 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
3670 | DEFAULT_PHY_DEV_ADDR); | |
de6eae1f YR |
3671 | } |
3672 | ||
3673 | static void bnx2x_xgxs_deassert(struct link_params *params) | |
3674 | { | |
3675 | struct bnx2x *bp = params->bp; | |
3676 | u8 port; | |
3677 | u32 val; | |
3678 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
3679 | port = params->port; | |
3680 | ||
3681 | val = XGXS_RESET_BITS << (port*16); | |
3682 | ||
d231023e | 3683 | /* Reset and unreset the SerDes/XGXS */ |
de6eae1f YR |
3684 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); |
3685 | udelay(500); | |
3686 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
3687 | ||
cd88ccee | 3688 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0); |
de6eae1f | 3689 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
cd88ccee | 3690 | params->phy[INT_PHY].def_md_devad); |
de6eae1f YR |
3691 | } |
3692 | ||
9045f6b4 YR |
3693 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
3694 | struct link_params *params, u16 *ieee_fc) | |
3695 | { | |
3696 | struct bnx2x *bp = params->bp; | |
3697 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | |
8f73f0b9 | 3698 | /* Resolve pause mode and advertisement Please refer to Table |
9045f6b4 YR |
3699 | * 28B-3 of the 802.3ab-1999 spec |
3700 | */ | |
3701 | ||
3702 | switch (phy->req_flow_ctrl) { | |
3703 | case BNX2X_FLOW_CTRL_AUTO: | |
3704 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) | |
3705 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3706 | else | |
3707 | *ieee_fc |= | |
3708 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3709 | break; | |
3710 | ||
3711 | case BNX2X_FLOW_CTRL_TX: | |
3712 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3713 | break; | |
3714 | ||
3715 | case BNX2X_FLOW_CTRL_RX: | |
3716 | case BNX2X_FLOW_CTRL_BOTH: | |
3717 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3718 | break; | |
3719 | ||
3720 | case BNX2X_FLOW_CTRL_NONE: | |
3721 | default: | |
3722 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | |
3723 | break; | |
3724 | } | |
3725 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); | |
3726 | } | |
3727 | ||
3728 | static void set_phy_vars(struct link_params *params, | |
3729 | struct link_vars *vars) | |
3730 | { | |
3731 | struct bnx2x *bp = params->bp; | |
3732 | u8 actual_phy_idx, phy_index, link_cfg_idx; | |
3733 | u8 phy_config_swapped = params->multi_phy_config & | |
3734 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
3735 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
3736 | phy_index++) { | |
3737 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
3738 | actual_phy_idx = phy_index; | |
3739 | if (phy_config_swapped) { | |
3740 | if (phy_index == EXT_PHY1) | |
3741 | actual_phy_idx = EXT_PHY2; | |
3742 | else if (phy_index == EXT_PHY2) | |
3743 | actual_phy_idx = EXT_PHY1; | |
3744 | } | |
3745 | params->phy[actual_phy_idx].req_flow_ctrl = | |
3746 | params->req_flow_ctrl[link_cfg_idx]; | |
3747 | ||
3748 | params->phy[actual_phy_idx].req_line_speed = | |
3749 | params->req_line_speed[link_cfg_idx]; | |
3750 | ||
3751 | params->phy[actual_phy_idx].speed_cap_mask = | |
3752 | params->speed_cap_mask[link_cfg_idx]; | |
a22f0788 | 3753 | |
9045f6b4 YR |
3754 | params->phy[actual_phy_idx].req_duplex = |
3755 | params->req_duplex[link_cfg_idx]; | |
3756 | ||
3757 | if (params->req_line_speed[link_cfg_idx] == | |
3758 | SPEED_AUTO_NEG) | |
3759 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3760 | ||
3761 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
3762 | " speed_cap_mask %x\n", | |
3763 | params->phy[actual_phy_idx].req_flow_ctrl, | |
3764 | params->phy[actual_phy_idx].req_line_speed, | |
3765 | params->phy[actual_phy_idx].speed_cap_mask); | |
3766 | } | |
3767 | } | |
3768 | ||
3769 | static void bnx2x_ext_phy_set_pause(struct link_params *params, | |
3770 | struct bnx2x_phy *phy, | |
3771 | struct link_vars *vars) | |
3772 | { | |
3773 | u16 val; | |
3774 | struct bnx2x *bp = params->bp; | |
d231023e | 3775 | /* Read modify write pause advertizing */ |
9045f6b4 YR |
3776 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); |
3777 | ||
3778 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; | |
3779 | ||
3780 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
3781 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3782 | if ((vars->ieee_fc & | |
3783 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3784 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3785 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3786 | } | |
3787 | if ((vars->ieee_fc & | |
3788 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3789 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3790 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3791 | } | |
3792 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3793 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3794 | } | |
3795 | ||
3796 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
3797 | { /* LD LP */ | |
3798 | switch (pause_result) { /* ASYM P ASYM P */ | |
3799 | case 0xb: /* 1 0 1 1 */ | |
3800 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
3801 | break; | |
3802 | ||
3803 | case 0xe: /* 1 1 1 0 */ | |
3804 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
3805 | break; | |
3806 | ||
3807 | case 0x5: /* 0 1 0 1 */ | |
3808 | case 0x7: /* 0 1 1 1 */ | |
3809 | case 0xd: /* 1 1 0 1 */ | |
3810 | case 0xf: /* 1 1 1 1 */ | |
3811 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
3812 | break; | |
3813 | ||
3814 | default: | |
3815 | break; | |
3816 | } | |
3817 | if (pause_result & (1<<0)) | |
3818 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
3819 | if (pause_result & (1<<1)) | |
3820 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
8f73f0b9 | 3821 | |
9045f6b4 YR |
3822 | } |
3823 | ||
9e7e8399 MY |
3824 | static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, |
3825 | struct link_params *params, | |
3826 | struct link_vars *vars) | |
9045f6b4 | 3827 | { |
9045f6b4 YR |
3828 | u16 ld_pause; /* local */ |
3829 | u16 lp_pause; /* link partner */ | |
3830 | u16 pause_result; | |
9e7e8399 MY |
3831 | struct bnx2x *bp = params->bp; |
3832 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { | |
3833 | bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); | |
3834 | bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); | |
ca05f29c YR |
3835 | } else if (CHIP_IS_E3(bp) && |
3836 | SINGLE_MEDIA_DIRECT(params)) { | |
3837 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
3838 | u16 gp_status, gp_mask; | |
3839 | bnx2x_cl45_read(bp, phy, | |
3840 | MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
3841 | &gp_status); | |
3842 | gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | | |
3843 | MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << | |
3844 | lane; | |
3845 | if ((gp_status & gp_mask) == gp_mask) { | |
3846 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3847 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3848 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3849 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3850 | } else { | |
3851 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3852 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3853 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
3854 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3855 | ld_pause = ((ld_pause & | |
3856 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3857 | << 3); | |
3858 | lp_pause = ((lp_pause & | |
3859 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
3860 | << 3); | |
3861 | } | |
9e7e8399 MY |
3862 | } else { |
3863 | bnx2x_cl45_read(bp, phy, | |
3864 | MDIO_AN_DEVAD, | |
3865 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3866 | bnx2x_cl45_read(bp, phy, | |
3867 | MDIO_AN_DEVAD, | |
3868 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3869 | } | |
3870 | pause_result = (ld_pause & | |
3871 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3872 | pause_result |= (lp_pause & | |
3873 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3874 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); | |
3875 | bnx2x_pause_resolve(vars, pause_result); | |
9045f6b4 | 3876 | |
9e7e8399 | 3877 | } |
8f73f0b9 | 3878 | |
9e7e8399 MY |
3879 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, |
3880 | struct link_params *params, | |
3881 | struct link_vars *vars) | |
3882 | { | |
3883 | u8 ret = 0; | |
9045f6b4 | 3884 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
9e7e8399 MY |
3885 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
3886 | /* Update the advertised flow-controled of LD/LP in AN */ | |
3887 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
3888 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); | |
3889 | /* But set the flow-control result as the requested one */ | |
9045f6b4 | 3890 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 3891 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
9045f6b4 YR |
3892 | vars->flow_ctrl = params->req_fc_auto_adv; |
3893 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3894 | ret = 1; | |
9e7e8399 | 3895 | bnx2x_ext_phy_update_adv_fc(phy, params, vars); |
9045f6b4 YR |
3896 | } |
3897 | return ret; | |
3898 | } | |
3c9ada22 YR |
3899 | /******************************************************************/ |
3900 | /* Warpcore section */ | |
3901 | /******************************************************************/ | |
3902 | /* The init_internal_warpcore should mirror the xgxs, | |
3903 | * i.e. reset the lane (if needed), set aer for the | |
3904 | * init configuration, and set/clear SGMII flag. Internal | |
3905 | * phy init is done purely in phy_init stage. | |
3906 | */ | |
ec4010ec YM |
3907 | |
3908 | static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy, | |
3909 | struct link_params *params) | |
3910 | { | |
3911 | struct bnx2x *bp = params->bp; | |
3912 | ||
3913 | DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n"); | |
3914 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3915 | MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); | |
3916 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
3917 | MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); | |
3918 | } | |
3919 | ||
3c9ada22 YR |
3920 | static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, |
3921 | struct link_params *params, | |
3922 | struct link_vars *vars) { | |
a351d497 YM |
3923 | u16 val16 = 0, lane, i; |
3924 | struct bnx2x *bp = params->bp; | |
3925 | static struct bnx2x_reg_set reg_set[] = { | |
3926 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
3927 | {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, | |
3928 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0}, | |
3929 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff}, | |
3930 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555}, | |
3931 | {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, | |
3932 | {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, | |
3933 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, | |
3934 | /* Disable Autoneg: re-enable it after adv is done. */ | |
3935 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0} | |
3936 | }; | |
3c9ada22 | 3937 | DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); |
6a51c0d1 | 3938 | /* Set to default registers that may be overriden by 10G force */ |
a351d497 YM |
3939 | for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) |
3940 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | |
3941 | reg_set[i].val); | |
a9077bfd | 3942 | |
3c9ada22 YR |
3943 | /* Check adding advertisement for 1G KX */ |
3944 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3945 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
3946 | (vars->line_speed == SPEED_1000)) { | |
a351d497 | 3947 | u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; |
3c9ada22 YR |
3948 | val16 |= (1<<5); |
3949 | ||
3950 | /* Enable CL37 1G Parallel Detect */ | |
a351d497 | 3951 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); |
3c9ada22 YR |
3952 | DP(NETIF_MSG_LINK, "Advertize 1G\n"); |
3953 | } | |
3954 | if (((vars->line_speed == SPEED_AUTO_NEG) && | |
3955 | (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
3956 | (vars->line_speed == SPEED_10000)) { | |
3957 | /* Check adding advertisement for 10G KR */ | |
3958 | val16 |= (1<<7); | |
3959 | /* Enable 10G Parallel Detect */ | |
3960 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
a351d497 | 3961 | MDIO_WC_REG_PAR_DET_10G_CTRL, 1); |
3c9ada22 YR |
3962 | |
3963 | DP(NETIF_MSG_LINK, "Advertize 10G\n"); | |
3964 | } | |
3965 | ||
3966 | /* Set Transmit PMD settings */ | |
3967 | lane = bnx2x_get_warpcore_lane(phy, params); | |
3968 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3969 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
3970 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
3971 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
3972 | (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | |
3973 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3974 | MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, | |
3975 | 0x03f0); | |
3976 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
3977 | MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, | |
3978 | 0x03f0); | |
3c9ada22 YR |
3979 | |
3980 | /* Advertised speeds */ | |
3981 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3982 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); | |
3983 | ||
6b1f3900 YR |
3984 | /* Advertised and set FEC (Forward Error Correction) */ |
3985 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
3986 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | |
3987 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | |
3988 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | |
3989 | ||
a34bc969 YR |
3990 | /* Enable CL37 BAM */ |
3991 | if (REG_RD(bp, params->shmem_base + | |
3992 | offsetof(struct shmem_region, dev_info. | |
3993 | port_hw_config[params->port].default_cfg)) & | |
3994 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
a351d497 YM |
3995 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
3996 | MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, | |
3997 | 1); | |
a34bc969 YR |
3998 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); |
3999 | } | |
4000 | ||
3c9ada22 YR |
4001 | /* Advertise pause */ |
4002 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
8f73f0b9 | 4003 | /* Set KR Autoneg Work-Around flag for Warpcore version older than D108 |
6ab48a5c YR |
4004 | */ |
4005 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4006 | MDIO_WC_REG_UC_INFO_B1_VERSION, &val16); | |
4007 | if (val16 < 0xd108) { | |
4008 | DP(NETIF_MSG_LINK, "Enable AN KR work-around\n"); | |
4009 | vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; | |
4010 | } | |
a351d497 YM |
4011 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4012 | MDIO_WC_REG_DIGITAL5_MISC7, 0x100); | |
a9077bfd YR |
4013 | |
4014 | /* Over 1G - AN local device user page 1 */ | |
4015 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4016 | MDIO_WC_REG_DIGITAL3_UP1, 0x1f); | |
4017 | ||
4018 | /* Enable Autoneg */ | |
4019 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
1b85ae52 | 4020 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); |
a9077bfd | 4021 | |
3c9ada22 YR |
4022 | } |
4023 | ||
4024 | static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, | |
4025 | struct link_params *params, | |
4026 | struct link_vars *vars) | |
4027 | { | |
4028 | struct bnx2x *bp = params->bp; | |
a351d497 YM |
4029 | u16 i; |
4030 | static struct bnx2x_reg_set reg_set[] = { | |
4031 | /* Disable Autoneg */ | |
4032 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, | |
4033 | {MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0}, | |
4034 | {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
4035 | 0x3f00}, | |
4036 | {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, | |
4037 | {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, | |
4038 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, | |
4039 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, | |
4040 | /* Disable CL36 PCS Tx */ | |
4041 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0}, | |
4042 | /* Double Wide Single Data Rate @ pll rate */ | |
4043 | {MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF}, | |
4044 | /* Leave cl72 training enable, needed for KR */ | |
4045 | {MDIO_PMA_DEVAD, | |
3c9ada22 | 4046 | MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150, |
a351d497 YM |
4047 | 0x2} |
4048 | }; | |
4049 | ||
4050 | for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++) | |
4051 | bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, | |
4052 | reg_set[i].val); | |
3c9ada22 YR |
4053 | |
4054 | /* Leave CL72 enabled */ | |
a351d497 YM |
4055 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4056 | MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, | |
4057 | 0x3800); | |
3c9ada22 YR |
4058 | |
4059 | /* Set speed via PMA/PMD register */ | |
4060 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
4061 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); | |
4062 | ||
4063 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, | |
4064 | MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); | |
4065 | ||
8f73f0b9 | 4066 | /* Enable encoded forced speed */ |
3c9ada22 YR |
4067 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4068 | MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); | |
4069 | ||
4070 | /* Turn TX scramble payload only the 64/66 scrambler */ | |
4071 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4072 | MDIO_WC_REG_TX66_CONTROL, 0x9); | |
4073 | ||
4074 | /* Turn RX scramble payload only the 64/66 scrambler */ | |
4075 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, | |
4076 | MDIO_WC_REG_RX66_CONTROL, 0xF9); | |
4077 | ||
d231023e | 4078 | /* Set and clear loopback to cause a reset to 64/66 decoder */ |
3c9ada22 YR |
4079 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4080 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); | |
4081 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4082 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); | |
4083 | ||
4084 | } | |
4085 | ||
4086 | static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy, | |
4087 | struct link_params *params, | |
4088 | u8 is_xfi) | |
4089 | { | |
4090 | struct bnx2x *bp = params->bp; | |
4091 | u16 misc1_val, tap_val, tx_driver_val, lane, val; | |
4092 | /* Hold rxSeqStart */ | |
a351d497 YM |
4093 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4094 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); | |
3c9ada22 YR |
4095 | |
4096 | /* Hold tx_fifo_reset */ | |
a351d497 YM |
4097 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4098 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); | |
3c9ada22 YR |
4099 | |
4100 | /* Disable CL73 AN */ | |
4101 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); | |
4102 | ||
4103 | /* Disable 100FX Enable and Auto-Detect */ | |
4104 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4105 | MDIO_WC_REG_FX100_CTRL1, &val); | |
4106 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4107 | MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA)); | |
4108 | ||
4109 | /* Disable 100FX Idle detect */ | |
a351d497 YM |
4110 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4111 | MDIO_WC_REG_FX100_CTRL3, 0x0080); | |
3c9ada22 YR |
4112 | |
4113 | /* Set Block address to Remote PHY & Clear forced_speed[5] */ | |
4114 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4115 | MDIO_WC_REG_DIGITAL4_MISC3, &val); | |
4116 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4117 | MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F)); | |
4118 | ||
4119 | /* Turn off auto-detect & fiber mode */ | |
4120 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4121 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val); | |
4122 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4123 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4124 | (val & 0xFFEE)); | |
4125 | ||
4126 | /* Set filter_force_link, disable_false_link and parallel_detect */ | |
4127 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4128 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); | |
4129 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4130 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4131 | ((val | 0x0006) & 0xFFFE)); | |
4132 | ||
4133 | /* Set XFI / SFI */ | |
4134 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4135 | MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); | |
4136 | ||
4137 | misc1_val &= ~(0x1f); | |
4138 | ||
4139 | if (is_xfi) { | |
4140 | misc1_val |= 0x5; | |
4141 | tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | |
4142 | (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
4143 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | |
4144 | tx_driver_val = | |
4145 | ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
4146 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
4147 | (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); | |
4148 | ||
4149 | } else { | |
4150 | misc1_val |= 0x9; | |
25182fc2 YR |
4151 | tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | |
4152 | (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
4153 | (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)); | |
3c9ada22 | 4154 | tx_driver_val = |
25182fc2 | 4155 | ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | |
3c9ada22 | 4156 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | |
25182fc2 | 4157 | (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)); |
3c9ada22 YR |
4158 | } |
4159 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4160 | MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); | |
4161 | ||
4162 | /* Set Transmit PMD settings */ | |
4163 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4164 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4165 | MDIO_WC_REG_TX_FIR_TAP, | |
4166 | tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); | |
4167 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4168 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
4169 | tx_driver_val); | |
4170 | ||
4171 | /* Enable fiber mode, enable and invert sig_det */ | |
a351d497 YM |
4172 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4173 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); | |
3c9ada22 YR |
4174 | |
4175 | /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ | |
a351d497 YM |
4176 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4177 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); | |
3c9ada22 | 4178 | |
ec4010ec | 4179 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
c8c60d88 | 4180 | |
3c9ada22 YR |
4181 | /* 10G XFI Full Duplex */ |
4182 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4183 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); | |
4184 | ||
4185 | /* Release tx_fifo_reset */ | |
4186 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4187 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val); | |
4188 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4189 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE); | |
4190 | ||
4191 | /* Release rxSeqStart */ | |
4192 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4193 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val); | |
4194 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4195 | MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF)); | |
4196 | } | |
4197 | ||
4198 | static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp, | |
4199 | struct bnx2x_phy *phy) | |
4200 | { | |
4201 | DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n"); | |
4202 | } | |
4203 | ||
4204 | static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, | |
4205 | struct bnx2x_phy *phy, | |
4206 | u16 lane) | |
4207 | { | |
4208 | /* Rx0 anaRxControl1G */ | |
4209 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4210 | MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); | |
4211 | ||
4212 | /* Rx2 anaRxControl1G */ | |
4213 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4214 | MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); | |
4215 | ||
4216 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4217 | MDIO_WC_REG_RX66_SCW0, 0xE070); | |
4218 | ||
4219 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4220 | MDIO_WC_REG_RX66_SCW1, 0xC0D0); | |
4221 | ||
4222 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4223 | MDIO_WC_REG_RX66_SCW2, 0xA0B0); | |
4224 | ||
4225 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4226 | MDIO_WC_REG_RX66_SCW3, 0x8090); | |
4227 | ||
4228 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4229 | MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); | |
4230 | ||
4231 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4232 | MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); | |
4233 | ||
4234 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4235 | MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); | |
4236 | ||
4237 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4238 | MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); | |
4239 | ||
4240 | /* Serdes Digital Misc1 */ | |
4241 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4242 | MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); | |
4243 | ||
4244 | /* Serdes Digital4 Misc3 */ | |
4245 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4246 | MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); | |
4247 | ||
4248 | /* Set Transmit PMD settings */ | |
4249 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4250 | MDIO_WC_REG_TX_FIR_TAP, | |
4251 | ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | | |
4252 | (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | | |
4253 | (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) | | |
4254 | MDIO_WC_REG_TX_FIR_TAP_ENABLE)); | |
4255 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4256 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, | |
4257 | ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | | |
4258 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | | |
4259 | (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))); | |
4260 | } | |
4261 | ||
4262 | static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy, | |
4263 | struct link_params *params, | |
521683da YR |
4264 | u8 fiber_mode, |
4265 | u8 always_autoneg) | |
3c9ada22 YR |
4266 | { |
4267 | struct bnx2x *bp = params->bp; | |
4268 | u16 val16, digctrl_kx1, digctrl_kx2; | |
3c9ada22 YR |
4269 | |
4270 | /* Clear XFI clock comp in non-10G single lane mode. */ | |
4271 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4272 | MDIO_WC_REG_RX66_CONTROL, &val16); | |
4273 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4274 | MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13)); | |
4275 | ||
26964bb7 YM |
4276 | bnx2x_warpcore_set_lpi_passthrough(phy, params); |
4277 | ||
521683da | 4278 | if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { |
3c9ada22 YR |
4279 | /* SGMII Autoneg */ |
4280 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4281 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4282 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4283 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4284 | val16 | 0x1000); | |
4285 | DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); | |
4286 | } else { | |
4287 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4288 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
521683da | 4289 | val16 &= 0xcebf; |
3c9ada22 YR |
4290 | switch (phy->req_line_speed) { |
4291 | case SPEED_10: | |
4292 | break; | |
4293 | case SPEED_100: | |
4294 | val16 |= 0x2000; | |
4295 | break; | |
4296 | case SPEED_1000: | |
4297 | val16 |= 0x0040; | |
4298 | break; | |
4299 | default: | |
94f05b0f JP |
4300 | DP(NETIF_MSG_LINK, |
4301 | "Speed not supported: 0x%x\n", phy->req_line_speed); | |
3c9ada22 YR |
4302 | return; |
4303 | } | |
4304 | ||
4305 | if (phy->req_duplex == DUPLEX_FULL) | |
4306 | val16 |= 0x0100; | |
4307 | ||
4308 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4309 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); | |
4310 | ||
4311 | DP(NETIF_MSG_LINK, "set SGMII force speed %d\n", | |
4312 | phy->req_line_speed); | |
4313 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4314 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4315 | DP(NETIF_MSG_LINK, " (readback) %x\n", val16); | |
4316 | } | |
4317 | ||
4318 | /* SGMII Slave mode and disable signal detect */ | |
4319 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4320 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); | |
4321 | if (fiber_mode) | |
4322 | digctrl_kx1 = 1; | |
4323 | else | |
4324 | digctrl_kx1 &= 0xff4a; | |
4325 | ||
4326 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4327 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4328 | digctrl_kx1); | |
4329 | ||
4330 | /* Turn off parallel detect */ | |
4331 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4332 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); | |
4333 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4334 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4335 | (digctrl_kx2 & ~(1<<2))); | |
4336 | ||
4337 | /* Re-enable parallel detect */ | |
4338 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4339 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4340 | (digctrl_kx2 | (1<<2))); | |
4341 | ||
4342 | /* Enable autodet */ | |
4343 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4344 | MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4345 | (digctrl_kx1 | 0x10)); | |
4346 | } | |
4347 | ||
4348 | static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, | |
4349 | struct bnx2x_phy *phy, | |
4350 | u8 reset) | |
4351 | { | |
4352 | u16 val; | |
4353 | /* Take lane out of reset after configuration is finished */ | |
4354 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4355 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4356 | if (reset) | |
4357 | val |= 0xC000; | |
4358 | else | |
4359 | val &= 0x3FFF; | |
4360 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4361 | MDIO_WC_REG_DIGITAL5_MISC6, val); | |
4362 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4363 | MDIO_WC_REG_DIGITAL5_MISC6, &val); | |
4364 | } | |
2f751a80 | 4365 | /* Clear SFI/XFI link settings registers */ |
3c9ada22 YR |
4366 | static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, |
4367 | struct link_params *params, | |
4368 | u16 lane) | |
4369 | { | |
4370 | struct bnx2x *bp = params->bp; | |
a351d497 YM |
4371 | u16 i; |
4372 | static struct bnx2x_reg_set wc_regs[] = { | |
4373 | {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, | |
4374 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, | |
4375 | {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, | |
4376 | {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, | |
4377 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, | |
4378 | 0x0195}, | |
4379 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, | |
4380 | 0x0007}, | |
4381 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, | |
4382 | 0x0002}, | |
4383 | {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, | |
4384 | {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, | |
4385 | {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, | |
4386 | {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} | |
4387 | }; | |
3c9ada22 | 4388 | /* Set XFI clock comp as default. */ |
a351d497 YM |
4389 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4390 | MDIO_WC_REG_RX66_CONTROL, (3<<13)); | |
4391 | ||
4392 | for (i = 0; i < sizeof(wc_regs)/sizeof(struct bnx2x_reg_set); i++) | |
4393 | bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, | |
4394 | wc_regs[i].val); | |
3c9ada22 | 4395 | |
3c9ada22 | 4396 | lane = bnx2x_get_warpcore_lane(phy, params); |
3c9ada22 YR |
4397 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, |
4398 | MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); | |
a351d497 | 4399 | |
3c9ada22 YR |
4400 | } |
4401 | ||
4402 | static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, | |
4403 | u32 chip_id, | |
4404 | u32 shmem_base, u8 port, | |
4405 | u8 *gpio_num, u8 *gpio_port) | |
4406 | { | |
4407 | u32 cfg_pin; | |
4408 | *gpio_num = 0; | |
4409 | *gpio_port = 0; | |
4410 | if (CHIP_IS_E3(bp)) { | |
4411 | cfg_pin = (REG_RD(bp, shmem_base + | |
4412 | offsetof(struct shmem_region, | |
4413 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4414 | PORT_HW_CFG_E3_MOD_ABS_MASK) >> | |
4415 | PORT_HW_CFG_E3_MOD_ABS_SHIFT; | |
4416 | ||
8f73f0b9 | 4417 | /* Should not happen. This function called upon interrupt |
3c9ada22 YR |
4418 | * triggered by GPIO ( since EPIO can only generate interrupts |
4419 | * to MCP). | |
4420 | * So if this function was called and none of the GPIOs was set, | |
4421 | * it means the shit hit the fan. | |
4422 | */ | |
4423 | if ((cfg_pin < PIN_CFG_GPIO0_P0) || | |
4424 | (cfg_pin > PIN_CFG_GPIO3_P1)) { | |
94f05b0f JP |
4425 | DP(NETIF_MSG_LINK, |
4426 | "ERROR: Invalid cfg pin %x for module detect indication\n", | |
4427 | cfg_pin); | |
3c9ada22 YR |
4428 | return -EINVAL; |
4429 | } | |
4430 | ||
4431 | *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; | |
4432 | *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; | |
4433 | } else { | |
4434 | *gpio_num = MISC_REGISTERS_GPIO_3; | |
4435 | *gpio_port = port; | |
4436 | } | |
4437 | DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port); | |
4438 | return 0; | |
4439 | } | |
4440 | ||
4441 | static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy, | |
4442 | struct link_params *params) | |
4443 | { | |
4444 | struct bnx2x *bp = params->bp; | |
4445 | u8 gpio_num, gpio_port; | |
4446 | u32 gpio_val; | |
4447 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, | |
4448 | params->shmem_base, params->port, | |
4449 | &gpio_num, &gpio_port) != 0) | |
4450 | return 0; | |
4451 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); | |
4452 | ||
4453 | /* Call the handling function in case module is detected */ | |
4454 | if (gpio_val == 0) | |
4455 | return 1; | |
4456 | else | |
4457 | return 0; | |
4458 | } | |
a9077bfd YR |
4459 | static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy, |
4460 | struct link_params *params) | |
4461 | { | |
4462 | u16 gp2_status_reg0, lane; | |
4463 | struct bnx2x *bp = params->bp; | |
4464 | ||
4465 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4466 | ||
4467 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, | |
4468 | &gp2_status_reg0); | |
4469 | ||
4470 | return (gp2_status_reg0 >> (8+lane)) & 0x1; | |
4471 | } | |
4472 | ||
4473 | static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy, | |
4474 | struct link_params *params, | |
4475 | struct link_vars *vars) | |
4476 | { | |
4477 | struct bnx2x *bp = params->bp; | |
4478 | u32 serdes_net_if; | |
4479 | u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; | |
4480 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4481 | ||
4482 | vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; | |
4483 | ||
4484 | if (!vars->turn_to_run_wc_rt) | |
4485 | return; | |
4486 | ||
d231023e | 4487 | /* Return if there is no link partner */ |
a9077bfd YR |
4488 | if (!(bnx2x_warpcore_get_sigdet(phy, params))) { |
4489 | DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n"); | |
4490 | return; | |
4491 | } | |
4492 | ||
4493 | if (vars->rx_tx_asic_rst) { | |
4494 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4495 | offsetof(struct shmem_region, dev_info. | |
4496 | port_hw_config[params->port].default_cfg)) & | |
4497 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4498 | ||
4499 | switch (serdes_net_if) { | |
4500 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4501 | /* Do we get link yet? */ | |
4502 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, | |
4503 | &gp_status1); | |
4504 | lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ | |
4505 | /*10G KR*/ | |
4506 | lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; | |
4507 | ||
4508 | DP(NETIF_MSG_LINK, | |
4509 | "gp_status1 0x%x\n", gp_status1); | |
4510 | ||
4511 | if (lnkup_kr || lnkup) { | |
4512 | vars->rx_tx_asic_rst = 0; | |
4513 | DP(NETIF_MSG_LINK, | |
4514 | "link up, rx_tx_asic_rst 0x%x\n", | |
4515 | vars->rx_tx_asic_rst); | |
4516 | } else { | |
8f73f0b9 | 4517 | /* Reset the lane to see if link comes up.*/ |
a9077bfd YR |
4518 | bnx2x_warpcore_reset_lane(bp, phy, 1); |
4519 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4520 | ||
d231023e | 4521 | /* Restart Autoneg */ |
a9077bfd YR |
4522 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
4523 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); | |
4524 | ||
4525 | vars->rx_tx_asic_rst--; | |
4526 | DP(NETIF_MSG_LINK, "0x%x retry left\n", | |
4527 | vars->rx_tx_asic_rst); | |
4528 | } | |
4529 | break; | |
4530 | ||
4531 | default: | |
4532 | break; | |
4533 | } | |
4534 | ||
4535 | } /*params->rx_tx_asic_rst*/ | |
4536 | ||
4537 | } | |
dbef807e YM |
4538 | static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy, |
4539 | struct link_params *params) | |
4540 | { | |
4541 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4542 | struct bnx2x *bp = params->bp; | |
4543 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4544 | if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == | |
4545 | SPEED_10000) && | |
4546 | (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { | |
4547 | DP(NETIF_MSG_LINK, "Setting 10G SFI\n"); | |
4548 | bnx2x_warpcore_set_10G_XFI(phy, params, 0); | |
4549 | } else { | |
4550 | DP(NETIF_MSG_LINK, "Setting 1G Fiber\n"); | |
4551 | bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); | |
4552 | } | |
4553 | } | |
4554 | ||
3c9ada22 YR |
4555 | static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, |
4556 | struct link_params *params, | |
4557 | struct link_vars *vars) | |
4558 | { | |
4559 | struct bnx2x *bp = params->bp; | |
4560 | u32 serdes_net_if; | |
4561 | u8 fiber_mode; | |
4562 | u16 lane = bnx2x_get_warpcore_lane(phy, params); | |
4563 | serdes_net_if = (REG_RD(bp, params->shmem_base + | |
4564 | offsetof(struct shmem_region, dev_info. | |
4565 | port_hw_config[params->port].default_cfg)) & | |
4566 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
4567 | DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, " | |
4568 | "serdes_net_if = 0x%x\n", | |
4569 | vars->line_speed, serdes_net_if); | |
4570 | bnx2x_set_aer_mmd(params, phy); | |
4571 | ||
4572 | vars->phy_flags |= PHY_XGXS_FLAG; | |
4573 | if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || | |
4574 | (phy->req_line_speed && | |
4575 | ((phy->req_line_speed == SPEED_100) || | |
4576 | (phy->req_line_speed == SPEED_10)))) { | |
4577 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4578 | DP(NETIF_MSG_LINK, "Setting SGMII mode\n"); | |
4579 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
521683da | 4580 | bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); |
3c9ada22 YR |
4581 | } else { |
4582 | switch (serdes_net_if) { | |
4583 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
4584 | /* Enable KR Auto Neg */ | |
6a51c0d1 | 4585 | if (params->loopback_mode != LOOPBACK_EXT) |
3c9ada22 YR |
4586 | bnx2x_warpcore_enable_AN_KR(phy, params, vars); |
4587 | else { | |
4588 | DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); | |
4589 | bnx2x_warpcore_set_10G_KR(phy, params, vars); | |
4590 | } | |
4591 | break; | |
4592 | ||
4593 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
4594 | bnx2x_warpcore_clear_regs(phy, params, lane); | |
4595 | if (vars->line_speed == SPEED_10000) { | |
4596 | DP(NETIF_MSG_LINK, "Setting 10G XFI\n"); | |
4597 | bnx2x_warpcore_set_10G_XFI(phy, params, 1); | |
4598 | } else { | |
4599 | if (SINGLE_MEDIA_DIRECT(params)) { | |
4600 | DP(NETIF_MSG_LINK, "1G Fiber\n"); | |
4601 | fiber_mode = 1; | |
4602 | } else { | |
4603 | DP(NETIF_MSG_LINK, "10/100/1G SGMII\n"); | |
4604 | fiber_mode = 0; | |
4605 | } | |
4606 | bnx2x_warpcore_set_sgmii_speed(phy, | |
4607 | params, | |
521683da YR |
4608 | fiber_mode, |
4609 | 0); | |
3c9ada22 YR |
4610 | } |
4611 | ||
4612 | break; | |
4613 | ||
4614 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
3c9ada22 YR |
4615 | /* Issue Module detection */ |
4616 | if (bnx2x_is_sfp_module_plugged(phy, params)) | |
4617 | bnx2x_sfp_module_detection(phy, params); | |
dbef807e YM |
4618 | |
4619 | bnx2x_warpcore_config_sfi(phy, params); | |
3c9ada22 YR |
4620 | break; |
4621 | ||
4622 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
4623 | if (vars->line_speed != SPEED_20000) { | |
4624 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4625 | return; | |
4626 | } | |
4627 | DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n"); | |
4628 | bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); | |
4629 | /* Issue Module detection */ | |
4630 | ||
4631 | bnx2x_sfp_module_detection(phy, params); | |
4632 | break; | |
4633 | ||
4634 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
4635 | if (vars->line_speed != SPEED_20000) { | |
4636 | DP(NETIF_MSG_LINK, "Speed not supported yet\n"); | |
4637 | return; | |
4638 | } | |
4639 | DP(NETIF_MSG_LINK, "Setting 20G KR2\n"); | |
4640 | bnx2x_warpcore_set_20G_KR2(bp, phy); | |
4641 | break; | |
4642 | ||
4643 | default: | |
94f05b0f JP |
4644 | DP(NETIF_MSG_LINK, |
4645 | "Unsupported Serdes Net Interface 0x%x\n", | |
4646 | serdes_net_if); | |
3c9ada22 YR |
4647 | return; |
4648 | } | |
4649 | } | |
4650 | ||
4651 | /* Take lane out of reset after configuration is finished */ | |
4652 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
4653 | DP(NETIF_MSG_LINK, "Exit config init\n"); | |
4654 | } | |
4655 | ||
4656 | static void bnx2x_sfp_e3_set_transmitter(struct link_params *params, | |
4657 | struct bnx2x_phy *phy, | |
4658 | u8 tx_en) | |
4659 | { | |
4660 | struct bnx2x *bp = params->bp; | |
4661 | u32 cfg_pin; | |
4662 | u8 port = params->port; | |
4663 | ||
4664 | cfg_pin = REG_RD(bp, params->shmem_base + | |
4665 | offsetof(struct shmem_region, | |
4666 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
4667 | PORT_HW_CFG_TX_LASER_MASK; | |
4668 | /* Set the !tx_en since this pin is DISABLE_TX_LASER */ | |
4669 | DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en); | |
4670 | /* For 20G, the expected pin to be used is 3 pins after the current */ | |
4671 | ||
4672 | bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); | |
4673 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) | |
4674 | bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); | |
4675 | } | |
4676 | ||
4677 | static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy, | |
4678 | struct link_params *params) | |
4679 | { | |
4680 | struct bnx2x *bp = params->bp; | |
4681 | u16 val16; | |
4682 | bnx2x_sfp_e3_set_transmitter(params, phy, 0); | |
4683 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); | |
4684 | bnx2x_set_aer_mmd(params, phy); | |
4685 | /* Global register */ | |
4686 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
4687 | ||
4688 | /* Clear loopback settings (if any) */ | |
4689 | /* 10G & 20G */ | |
4690 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4691 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); | |
4692 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4693 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 & | |
4694 | 0xBFFF); | |
4695 | ||
4696 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4697 | MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16); | |
4698 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4699 | MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe); | |
4700 | ||
4701 | /* Update those 1-copy registers */ | |
4702 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4703 | MDIO_AER_BLOCK_AER_REG, 0); | |
8f73f0b9 | 4704 | /* Enable 1G MDIO (1-copy) */ |
3c9ada22 YR |
4705 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, |
4706 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4707 | &val16); | |
4708 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4709 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4710 | val16 & ~0x10); | |
4711 | ||
4712 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4713 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4714 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4715 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | |
4716 | val16 & 0xff00); | |
4717 | ||
4718 | } | |
4719 | ||
4720 | static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, | |
4721 | struct link_params *params) | |
4722 | { | |
4723 | struct bnx2x *bp = params->bp; | |
4724 | u16 val16; | |
4725 | u32 lane; | |
4726 | DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n", | |
4727 | params->loopback_mode, phy->req_line_speed); | |
4728 | ||
4729 | if (phy->req_line_speed < SPEED_10000) { | |
4730 | /* 10/100/1000 */ | |
4731 | ||
4732 | /* Update those 1-copy registers */ | |
4733 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, | |
4734 | MDIO_AER_BLOCK_AER_REG, 0); | |
4735 | /* Enable 1G MDIO (1-copy) */ | |
a351d497 YM |
4736 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4737 | MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, | |
4738 | 0x10); | |
3c9ada22 YR |
4739 | /* Set 1G loopback based on lane (1-copy) */ |
4740 | lane = bnx2x_get_warpcore_lane(phy, params); | |
4741 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
4742 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); | |
4743 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
4744 | MDIO_WC_REG_XGXSBLK1_LANECTRL2, | |
4745 | val16 | (1<<lane)); | |
4746 | ||
4747 | /* Switch back to 4-copy registers */ | |
4748 | bnx2x_set_aer_mmd(params, phy); | |
3c9ada22 YR |
4749 | } else { |
4750 | /* 10G & 20G */ | |
a351d497 YM |
4751 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4752 | MDIO_WC_REG_COMBO_IEEE0_MIICTRL, | |
4753 | 0x4000); | |
3c9ada22 | 4754 | |
a351d497 YM |
4755 | bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, |
4756 | MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); | |
3c9ada22 YR |
4757 | } |
4758 | } | |
4759 | ||
4760 | ||
d231023e YM |
4761 | |
4762 | static void bnx2x_sync_link(struct link_params *params, | |
4763 | struct link_vars *vars) | |
de6eae1f YR |
4764 | { |
4765 | struct bnx2x *bp = params->bp; | |
9380bb9e | 4766 | u8 link_10g_plus; |
de6f3377 YR |
4767 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4768 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; | |
2f751a80 | 4769 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); |
de6eae1f YR |
4770 | if (vars->link_up) { |
4771 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
4772 | ||
4773 | vars->phy_link_up = 1; | |
4774 | vars->duplex = DUPLEX_FULL; | |
4775 | switch (vars->link_status & | |
cd88ccee | 4776 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
8f73f0b9 YR |
4777 | case LINK_10THD: |
4778 | vars->duplex = DUPLEX_HALF; | |
4779 | /* Fall thru */ | |
4780 | case LINK_10TFD: | |
4781 | vars->line_speed = SPEED_10; | |
4782 | break; | |
de6eae1f | 4783 | |
8f73f0b9 YR |
4784 | case LINK_100TXHD: |
4785 | vars->duplex = DUPLEX_HALF; | |
4786 | /* Fall thru */ | |
4787 | case LINK_100T4: | |
4788 | case LINK_100TXFD: | |
4789 | vars->line_speed = SPEED_100; | |
4790 | break; | |
de6eae1f | 4791 | |
8f73f0b9 YR |
4792 | case LINK_1000THD: |
4793 | vars->duplex = DUPLEX_HALF; | |
4794 | /* Fall thru */ | |
4795 | case LINK_1000TFD: | |
4796 | vars->line_speed = SPEED_1000; | |
4797 | break; | |
de6eae1f | 4798 | |
8f73f0b9 YR |
4799 | case LINK_2500THD: |
4800 | vars->duplex = DUPLEX_HALF; | |
4801 | /* Fall thru */ | |
4802 | case LINK_2500TFD: | |
4803 | vars->line_speed = SPEED_2500; | |
4804 | break; | |
de6eae1f | 4805 | |
8f73f0b9 YR |
4806 | case LINK_10GTFD: |
4807 | vars->line_speed = SPEED_10000; | |
4808 | break; | |
4809 | case LINK_20GTFD: | |
4810 | vars->line_speed = SPEED_20000; | |
4811 | break; | |
4812 | default: | |
4813 | break; | |
de6eae1f | 4814 | } |
de6eae1f YR |
4815 | vars->flow_ctrl = 0; |
4816 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
4817 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
4818 | ||
4819 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
4820 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
4821 | ||
4822 | if (!vars->flow_ctrl) | |
4823 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4824 | ||
4825 | if (vars->line_speed && | |
4826 | ((vars->line_speed == SPEED_10) || | |
4827 | (vars->line_speed == SPEED_100))) { | |
4828 | vars->phy_flags |= PHY_SGMII_FLAG; | |
4829 | } else { | |
4830 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
4831 | } | |
3c9ada22 YR |
4832 | if (vars->line_speed && |
4833 | USES_WARPCORE(bp) && | |
4834 | (vars->line_speed == SPEED_1000)) | |
4835 | vars->phy_flags |= PHY_SGMII_FLAG; | |
d231023e | 4836 | /* Anything 10 and over uses the bmac */ |
9380bb9e YR |
4837 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
4838 | ||
4839 | if (link_10g_plus) { | |
4840 | if (USES_WARPCORE(bp)) | |
4841 | vars->mac_type = MAC_TYPE_XMAC; | |
4842 | else | |
3c9ada22 | 4843 | vars->mac_type = MAC_TYPE_BMAC; |
9380bb9e YR |
4844 | } else { |
4845 | if (USES_WARPCORE(bp)) | |
4846 | vars->mac_type = MAC_TYPE_UMAC; | |
3c9ada22 YR |
4847 | else |
4848 | vars->mac_type = MAC_TYPE_EMAC; | |
9380bb9e | 4849 | } |
d231023e | 4850 | } else { /* Link down */ |
de6eae1f YR |
4851 | DP(NETIF_MSG_LINK, "phy link down\n"); |
4852 | ||
4853 | vars->phy_link_up = 0; | |
4854 | ||
4855 | vars->line_speed = 0; | |
4856 | vars->duplex = DUPLEX_FULL; | |
4857 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
4858 | ||
d231023e | 4859 | /* Indicate no mac active */ |
de6eae1f | 4860 | vars->mac_type = MAC_TYPE_NONE; |
de6f3377 YR |
4861 | if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) |
4862 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
d0b8a6f9 YM |
4863 | if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) |
4864 | vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; | |
de6eae1f | 4865 | } |
2f751a80 YR |
4866 | } |
4867 | ||
4868 | void bnx2x_link_status_update(struct link_params *params, | |
4869 | struct link_vars *vars) | |
4870 | { | |
4871 | struct bnx2x *bp = params->bp; | |
4872 | u8 port = params->port; | |
4873 | u32 sync_offset, media_types; | |
4874 | /* Update PHY configuration */ | |
4875 | set_phy_vars(params, vars); | |
de6eae1f | 4876 | |
2f751a80 YR |
4877 | vars->link_status = REG_RD(bp, params->shmem_base + |
4878 | offsetof(struct shmem_region, | |
4879 | port_mb[port].link_status)); | |
08e9acc2 YM |
4880 | if (bnx2x_eee_has_cap(params)) |
4881 | vars->eee_status = REG_RD(bp, params->shmem2_base + | |
4882 | offsetof(struct shmem2_region, | |
4883 | eee_status[params->port])); | |
2f751a80 YR |
4884 | |
4885 | vars->phy_flags = PHY_XGXS_FLAG; | |
4886 | bnx2x_sync_link(params, vars); | |
1ac9e428 YR |
4887 | /* Sync media type */ |
4888 | sync_offset = params->shmem_base + | |
4889 | offsetof(struct shmem_region, | |
4890 | dev_info.port_hw_config[port].media_type); | |
4891 | media_types = REG_RD(bp, sync_offset); | |
4892 | ||
4893 | params->phy[INT_PHY].media_type = | |
4894 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> | |
4895 | PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; | |
4896 | params->phy[EXT_PHY1].media_type = | |
4897 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> | |
4898 | PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; | |
4899 | params->phy[EXT_PHY2].media_type = | |
4900 | (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> | |
4901 | PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; | |
4902 | DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); | |
4903 | ||
020c7e3f YR |
4904 | /* Sync AEU offset */ |
4905 | sync_offset = params->shmem_base + | |
4906 | offsetof(struct shmem_region, | |
4907 | dev_info.port_hw_config[port].aeu_int_mask); | |
4908 | ||
4909 | vars->aeu_int_mask = REG_RD(bp, sync_offset); | |
4910 | ||
b8d6d082 YR |
4911 | /* Sync PFC status */ |
4912 | if (vars->link_status & LINK_STATUS_PFC_ENABLED) | |
4913 | params->feature_config_flags |= | |
4914 | FEATURE_CONFIG_PFC_ENABLED; | |
4915 | else | |
4916 | params->feature_config_flags &= | |
4917 | ~FEATURE_CONFIG_PFC_ENABLED; | |
4918 | ||
020c7e3f YR |
4919 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", |
4920 | vars->link_status, vars->phy_link_up, vars->aeu_int_mask); | |
de6eae1f YR |
4921 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", |
4922 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
4923 | } | |
4924 | ||
de6eae1f YR |
4925 | static void bnx2x_set_master_ln(struct link_params *params, |
4926 | struct bnx2x_phy *phy) | |
4927 | { | |
4928 | struct bnx2x *bp = params->bp; | |
4929 | u16 new_master_ln, ser_lane; | |
cd88ccee | 4930 | ser_lane = ((params->lane_config & |
de6eae1f | 4931 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
cd88ccee | 4932 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
de6eae1f | 4933 | |
d231023e | 4934 | /* Set the master_ln for AN */ |
cd2be89b | 4935 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4936 | MDIO_REG_BANK_XGXS_BLOCK2, |
4937 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4938 | &new_master_ln); | |
de6eae1f | 4939 | |
cd2be89b | 4940 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4941 | MDIO_REG_BANK_XGXS_BLOCK2 , |
4942 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
4943 | (new_master_ln | ser_lane)); | |
de6eae1f YR |
4944 | } |
4945 | ||
fcf5b650 YR |
4946 | static int bnx2x_reset_unicore(struct link_params *params, |
4947 | struct bnx2x_phy *phy, | |
4948 | u8 set_serdes) | |
de6eae1f YR |
4949 | { |
4950 | struct bnx2x *bp = params->bp; | |
4951 | u16 mii_control; | |
4952 | u16 i; | |
cd2be89b | 4953 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4954 | MDIO_REG_BANK_COMBO_IEEE0, |
4955 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
de6eae1f | 4956 | |
d231023e | 4957 | /* Reset the unicore */ |
cd2be89b | 4958 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
4959 | MDIO_REG_BANK_COMBO_IEEE0, |
4960 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4961 | (mii_control | | |
4962 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
de6eae1f YR |
4963 | if (set_serdes) |
4964 | bnx2x_set_serdes_access(bp, params->port); | |
4965 | ||
d231023e | 4966 | /* Wait for the reset to self clear */ |
de6eae1f YR |
4967 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { |
4968 | udelay(5); | |
4969 | ||
d231023e | 4970 | /* The reset erased the previous bank value */ |
cd2be89b | 4971 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
4972 | MDIO_REG_BANK_COMBO_IEEE0, |
4973 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
4974 | &mii_control); | |
de6eae1f YR |
4975 | |
4976 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
4977 | udelay(5); | |
4978 | return 0; | |
4979 | } | |
4980 | } | |
ea4e040a | 4981 | |
6d870c39 YR |
4982 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
4983 | " Port %d\n", | |
4984 | params->port); | |
ea4e040a YR |
4985 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); |
4986 | return -EINVAL; | |
4987 | ||
4988 | } | |
4989 | ||
e10bc84d YR |
4990 | static void bnx2x_set_swap_lanes(struct link_params *params, |
4991 | struct bnx2x_phy *phy) | |
ea4e040a YR |
4992 | { |
4993 | struct bnx2x *bp = params->bp; | |
8f73f0b9 YR |
4994 | /* Each two bits represents a lane number: |
4995 | * No swap is 0123 => 0x1b no need to enable the swap | |
2cf7acf9 | 4996 | */ |
2f751a80 | 4997 | u16 rx_lane_swap, tx_lane_swap; |
ea4e040a | 4998 | |
ea4e040a | 4999 | rx_lane_swap = ((params->lane_config & |
cd88ccee YR |
5000 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
5001 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
ea4e040a | 5002 | tx_lane_swap = ((params->lane_config & |
cd88ccee YR |
5003 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
5004 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
ea4e040a YR |
5005 | |
5006 | if (rx_lane_swap != 0x1b) { | |
cd2be89b | 5007 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5008 | MDIO_REG_BANK_XGXS_BLOCK2, |
5009 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
5010 | (rx_lane_swap | | |
5011 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
5012 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
ea4e040a | 5013 | } else { |
cd2be89b | 5014 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5015 | MDIO_REG_BANK_XGXS_BLOCK2, |
5016 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
ea4e040a YR |
5017 | } |
5018 | ||
5019 | if (tx_lane_swap != 0x1b) { | |
cd2be89b | 5020 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5021 | MDIO_REG_BANK_XGXS_BLOCK2, |
5022 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
5023 | (tx_lane_swap | | |
5024 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
ea4e040a | 5025 | } else { |
cd2be89b | 5026 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5027 | MDIO_REG_BANK_XGXS_BLOCK2, |
5028 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
ea4e040a YR |
5029 | } |
5030 | } | |
5031 | ||
e10bc84d YR |
5032 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
5033 | struct link_params *params) | |
ea4e040a YR |
5034 | { |
5035 | struct bnx2x *bp = params->bp; | |
5036 | u16 control2; | |
cd2be89b | 5037 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5038 | MDIO_REG_BANK_SERDES_DIGITAL, |
5039 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
5040 | &control2); | |
7aa0711f | 5041 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
5042 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
5043 | else | |
5044 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
5045 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
5046 | phy->speed_cap_mask, control2); | |
cd2be89b | 5047 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5048 | MDIO_REG_BANK_SERDES_DIGITAL, |
5049 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
5050 | control2); | |
ea4e040a | 5051 | |
e10bc84d | 5052 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 5053 | (phy->speed_cap_mask & |
18afb0a6 | 5054 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
5055 | DP(NETIF_MSG_LINK, "XGXS\n"); |
5056 | ||
cd2be89b | 5057 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5058 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5059 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
5060 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
ea4e040a | 5061 | |
cd2be89b | 5062 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5063 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5064 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
5065 | &control2); | |
ea4e040a YR |
5066 | |
5067 | ||
5068 | control2 |= | |
5069 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
5070 | ||
cd2be89b | 5071 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5072 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5073 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
5074 | control2); | |
ea4e040a YR |
5075 | |
5076 | /* Disable parallel detection of HiG */ | |
cd2be89b | 5077 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5078 | MDIO_REG_BANK_XGXS_BLOCK2, |
5079 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
5080 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
5081 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
ea4e040a YR |
5082 | } |
5083 | } | |
5084 | ||
e10bc84d YR |
5085 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
5086 | struct link_params *params, | |
cd88ccee YR |
5087 | struct link_vars *vars, |
5088 | u8 enable_cl73) | |
ea4e040a YR |
5089 | { |
5090 | struct bnx2x *bp = params->bp; | |
5091 | u16 reg_val; | |
5092 | ||
5093 | /* CL37 Autoneg */ | |
cd2be89b | 5094 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5095 | MDIO_REG_BANK_COMBO_IEEE0, |
5096 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a YR |
5097 | |
5098 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 5099 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
5100 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
5101 | else /* CL37 Autoneg Disabled */ | |
5102 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5103 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
5104 | ||
cd2be89b | 5105 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5106 | MDIO_REG_BANK_COMBO_IEEE0, |
5107 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a YR |
5108 | |
5109 | /* Enable/Disable Autodetection */ | |
5110 | ||
cd2be89b | 5111 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5112 | MDIO_REG_BANK_SERDES_DIGITAL, |
5113 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
5114 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
5115 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
5116 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 5117 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
5118 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
5119 | else | |
5120 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
5121 | ||
cd2be89b | 5122 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5123 | MDIO_REG_BANK_SERDES_DIGITAL, |
5124 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
ea4e040a YR |
5125 | |
5126 | /* Enable TetonII and BAM autoneg */ | |
cd2be89b | 5127 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5128 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
5129 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
ea4e040a | 5130 | ®_val); |
8c99e7b0 | 5131 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
5132 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
5133 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
5134 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
5135 | } else { | |
5136 | /* TetonII and BAM Autoneg Disabled */ | |
5137 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
5138 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
5139 | } | |
cd2be89b | 5140 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5141 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
5142 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
5143 | reg_val); | |
ea4e040a | 5144 | |
239d686d EG |
5145 | if (enable_cl73) { |
5146 | /* Enable Cl73 FSM status bits */ | |
cd2be89b | 5147 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5148 | MDIO_REG_BANK_CL73_USERB0, |
5149 | MDIO_CL73_USERB0_CL73_UCTRL, | |
5150 | 0xe); | |
239d686d EG |
5151 | |
5152 | /* Enable BAM Station Manager*/ | |
cd2be89b | 5153 | CL22_WR_OVER_CL45(bp, phy, |
239d686d EG |
5154 | MDIO_REG_BANK_CL73_USERB0, |
5155 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
5156 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
5157 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
5158 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
5159 | ||
7846e471 | 5160 | /* Advertise CL73 link speeds */ |
cd2be89b | 5161 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5162 | MDIO_REG_BANK_CL73_IEEEB1, |
5163 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5164 | ®_val); | |
7aa0711f | 5165 | if (phy->speed_cap_mask & |
7846e471 YR |
5166 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
5167 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 5168 | if (phy->speed_cap_mask & |
7846e471 YR |
5169 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
5170 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 5171 | |
cd2be89b | 5172 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5173 | MDIO_REG_BANK_CL73_IEEEB1, |
5174 | MDIO_CL73_IEEEB1_AN_ADV2, | |
5175 | reg_val); | |
239d686d | 5176 | |
239d686d EG |
5177 | /* CL73 Autoneg Enabled */ |
5178 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
5179 | ||
5180 | } else /* CL73 Autoneg Disabled */ | |
5181 | reg_val = 0; | |
ea4e040a | 5182 | |
cd2be89b | 5183 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5184 | MDIO_REG_BANK_CL73_IEEEB0, |
5185 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
ea4e040a YR |
5186 | } |
5187 | ||
d231023e | 5188 | /* Program SerDes, forced speed */ |
e10bc84d YR |
5189 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
5190 | struct link_params *params, | |
cd88ccee | 5191 | struct link_vars *vars) |
ea4e040a YR |
5192 | { |
5193 | struct bnx2x *bp = params->bp; | |
5194 | u16 reg_val; | |
5195 | ||
d231023e | 5196 | /* Program duplex, disable autoneg and sgmii*/ |
cd2be89b | 5197 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5198 | MDIO_REG_BANK_COMBO_IEEE0, |
5199 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a | 5200 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
57937203 EG |
5201 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5202 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 5203 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 5204 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
cd2be89b | 5205 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5206 | MDIO_REG_BANK_COMBO_IEEE0, |
5207 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a | 5208 | |
8f73f0b9 | 5209 | /* Program speed |
2cf7acf9 YR |
5210 | * - needed only if the speed is greater than 1G (2.5G or 10G) |
5211 | */ | |
cd2be89b | 5212 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5213 | MDIO_REG_BANK_SERDES_DIGITAL, |
5214 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
d231023e | 5215 | /* Clearing the speed value before setting the right speed */ |
8c99e7b0 YR |
5216 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); |
5217 | ||
5218 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
5219 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
5220 | ||
5221 | if (!((vars->line_speed == SPEED_1000) || | |
5222 | (vars->line_speed == SPEED_100) || | |
5223 | (vars->line_speed == SPEED_10))) { | |
5224 | ||
ea4e040a YR |
5225 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
5226 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 5227 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
5228 | reg_val |= |
5229 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 YR |
5230 | } |
5231 | ||
cd2be89b | 5232 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5233 | MDIO_REG_BANK_SERDES_DIGITAL, |
5234 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 5235 | |
ea4e040a YR |
5236 | } |
5237 | ||
9045f6b4 YR |
5238 | static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy, |
5239 | struct link_params *params) | |
ea4e040a YR |
5240 | { |
5241 | struct bnx2x *bp = params->bp; | |
5242 | u16 val = 0; | |
5243 | ||
d231023e | 5244 | /* Set extended capabilities */ |
7aa0711f | 5245 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 5246 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 5247 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 5248 | val |= MDIO_OVER_1G_UP1_10G; |
cd2be89b | 5249 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5250 | MDIO_REG_BANK_OVER_1G, |
5251 | MDIO_OVER_1G_UP1, val); | |
ea4e040a | 5252 | |
cd2be89b | 5253 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5254 | MDIO_REG_BANK_OVER_1G, |
5255 | MDIO_OVER_1G_UP3, 0x400); | |
ea4e040a YR |
5256 | } |
5257 | ||
9045f6b4 YR |
5258 | static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy, |
5259 | struct link_params *params, | |
5260 | u16 ieee_fc) | |
8c99e7b0 YR |
5261 | { |
5262 | struct bnx2x *bp = params->bp; | |
7846e471 | 5263 | u16 val; |
d231023e | 5264 | /* For AN, we are always publishing full duplex */ |
ea4e040a | 5265 | |
cd2be89b | 5266 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5267 | MDIO_REG_BANK_COMBO_IEEE0, |
5268 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
cd2be89b | 5269 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5270 | MDIO_REG_BANK_CL73_IEEEB1, |
5271 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
7846e471 YR |
5272 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
5273 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
cd2be89b | 5274 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5275 | MDIO_REG_BANK_CL73_IEEEB1, |
5276 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
5277 | } |
5278 | ||
e10bc84d YR |
5279 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
5280 | struct link_params *params, | |
5281 | u8 enable_cl73) | |
ea4e040a YR |
5282 | { |
5283 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 5284 | u16 mii_control; |
239d686d | 5285 | |
ea4e040a | 5286 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 5287 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 5288 | |
239d686d | 5289 | if (enable_cl73) { |
cd2be89b | 5290 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5291 | MDIO_REG_BANK_CL73_IEEEB0, |
5292 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5293 | &mii_control); | |
239d686d | 5294 | |
cd2be89b | 5295 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5296 | MDIO_REG_BANK_CL73_IEEEB0, |
5297 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5298 | (mii_control | | |
5299 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
5300 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
239d686d EG |
5301 | } else { |
5302 | ||
cd2be89b | 5303 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5304 | MDIO_REG_BANK_COMBO_IEEE0, |
5305 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5306 | &mii_control); | |
239d686d EG |
5307 | DP(NETIF_MSG_LINK, |
5308 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
5309 | mii_control); | |
cd2be89b | 5310 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5311 | MDIO_REG_BANK_COMBO_IEEE0, |
5312 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5313 | (mii_control | | |
5314 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
5315 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
239d686d | 5316 | } |
ea4e040a YR |
5317 | } |
5318 | ||
e10bc84d YR |
5319 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
5320 | struct link_params *params, | |
cd88ccee | 5321 | struct link_vars *vars) |
ea4e040a YR |
5322 | { |
5323 | struct bnx2x *bp = params->bp; | |
5324 | u16 control1; | |
5325 | ||
d231023e | 5326 | /* In SGMII mode, the unicore is always slave */ |
ea4e040a | 5327 | |
cd2be89b | 5328 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5329 | MDIO_REG_BANK_SERDES_DIGITAL, |
5330 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5331 | &control1); | |
ea4e040a | 5332 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
d231023e | 5333 | /* Set sgmii mode (and not fiber) */ |
ea4e040a YR |
5334 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | |
5335 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
5336 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
cd2be89b | 5337 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5338 | MDIO_REG_BANK_SERDES_DIGITAL, |
5339 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
5340 | control1); | |
ea4e040a | 5341 | |
d231023e | 5342 | /* If forced speed */ |
8c99e7b0 | 5343 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
d231023e | 5344 | /* Set speed, disable autoneg */ |
ea4e040a YR |
5345 | u16 mii_control; |
5346 | ||
cd2be89b | 5347 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5348 | MDIO_REG_BANK_COMBO_IEEE0, |
5349 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5350 | &mii_control); | |
ea4e040a YR |
5351 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
5352 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
5353 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
5354 | ||
8c99e7b0 | 5355 | switch (vars->line_speed) { |
ea4e040a YR |
5356 | case SPEED_100: |
5357 | mii_control |= | |
5358 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
5359 | break; | |
5360 | case SPEED_1000: | |
5361 | mii_control |= | |
5362 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
5363 | break; | |
5364 | case SPEED_10: | |
d231023e | 5365 | /* There is nothing to set for 10M */ |
ea4e040a YR |
5366 | break; |
5367 | default: | |
d231023e | 5368 | /* Invalid speed for SGMII */ |
8c99e7b0 YR |
5369 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5370 | vars->line_speed); | |
ea4e040a YR |
5371 | break; |
5372 | } | |
5373 | ||
d231023e | 5374 | /* Setting the full duplex */ |
7aa0711f | 5375 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
5376 | mii_control |= |
5377 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
cd2be89b | 5378 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5379 | MDIO_REG_BANK_COMBO_IEEE0, |
5380 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
5381 | mii_control); | |
ea4e040a YR |
5382 | |
5383 | } else { /* AN mode */ | |
d231023e | 5384 | /* Enable and restart AN */ |
e10bc84d | 5385 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
5386 | } |
5387 | } | |
5388 | ||
8f73f0b9 | 5389 | /* Link management |
ea4e040a | 5390 | */ |
fcf5b650 YR |
5391 | static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
5392 | struct link_params *params) | |
15ddd2d0 YR |
5393 | { |
5394 | struct bnx2x *bp = params->bp; | |
5395 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
5396 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
5397 | return 0; | |
cd2be89b | 5398 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5399 | MDIO_REG_BANK_SERDES_DIGITAL, |
5400 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5401 | &status2_1000x); | |
cd2be89b | 5402 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5403 | MDIO_REG_BANK_SERDES_DIGITAL, |
5404 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
5405 | &status2_1000x); | |
15ddd2d0 YR |
5406 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
5407 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
5408 | params->port); | |
5409 | return 1; | |
5410 | } | |
5411 | ||
cd2be89b | 5412 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5413 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
5414 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
5415 | &pd_10g); | |
15ddd2d0 YR |
5416 | |
5417 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
5418 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
5419 | params->port); | |
5420 | return 1; | |
5421 | } | |
5422 | return 0; | |
5423 | } | |
ea4e040a | 5424 | |
9e7e8399 MY |
5425 | static void bnx2x_update_adv_fc(struct bnx2x_phy *phy, |
5426 | struct link_params *params, | |
5427 | struct link_vars *vars, | |
5428 | u32 gp_status) | |
5429 | { | |
5430 | u16 ld_pause; /* local driver */ | |
5431 | u16 lp_pause; /* link partner */ | |
5432 | u16 pause_result; | |
5433 | struct bnx2x *bp = params->bp; | |
5434 | if ((gp_status & | |
5435 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5436 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
5437 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
5438 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
5439 | ||
5440 | CL22_RD_OVER_CL45(bp, phy, | |
5441 | MDIO_REG_BANK_CL73_IEEEB1, | |
5442 | MDIO_CL73_IEEEB1_AN_ADV1, | |
5443 | &ld_pause); | |
5444 | CL22_RD_OVER_CL45(bp, phy, | |
5445 | MDIO_REG_BANK_CL73_IEEEB1, | |
5446 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
5447 | &lp_pause); | |
5448 | pause_result = (ld_pause & | |
5449 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; | |
5450 | pause_result |= (lp_pause & | |
5451 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; | |
5452 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); | |
5453 | } else { | |
5454 | CL22_RD_OVER_CL45(bp, phy, | |
5455 | MDIO_REG_BANK_COMBO_IEEE0, | |
5456 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
5457 | &ld_pause); | |
5458 | CL22_RD_OVER_CL45(bp, phy, | |
5459 | MDIO_REG_BANK_COMBO_IEEE0, | |
5460 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
5461 | &lp_pause); | |
5462 | pause_result = (ld_pause & | |
5463 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; | |
5464 | pause_result |= (lp_pause & | |
5465 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | |
5466 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); | |
5467 | } | |
5468 | bnx2x_pause_resolve(vars, pause_result); | |
5469 | ||
5470 | } | |
5471 | ||
e10bc84d YR |
5472 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
5473 | struct link_params *params, | |
5474 | struct link_vars *vars, | |
5475 | u32 gp_status) | |
ea4e040a YR |
5476 | { |
5477 | struct bnx2x *bp = params->bp; | |
c0700f90 | 5478 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5479 | |
d231023e | 5480 | /* Resolve from gp_status in case of AN complete and not sgmii */ |
9e7e8399 MY |
5481 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { |
5482 | /* Update the advertised flow-controled of LD/LP in AN */ | |
5483 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5484 | bnx2x_update_adv_fc(phy, params, vars, gp_status); | |
5485 | /* But set the flow-control result as the requested one */ | |
7aa0711f | 5486 | vars->flow_ctrl = phy->req_flow_ctrl; |
9e7e8399 | 5487 | } else if (phy->req_line_speed != SPEED_AUTO_NEG) |
7aa0711f YR |
5488 | vars->flow_ctrl = params->req_fc_auto_adv; |
5489 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
5490 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 5491 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
5492 | vars->flow_ctrl = params->req_fc_auto_adv; |
5493 | return; | |
5494 | } | |
9e7e8399 | 5495 | bnx2x_update_adv_fc(phy, params, vars, gp_status); |
ea4e040a YR |
5496 | } |
5497 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
5498 | } | |
5499 | ||
e10bc84d YR |
5500 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
5501 | struct link_params *params) | |
239d686d EG |
5502 | { |
5503 | struct bnx2x *bp = params->bp; | |
9045f6b4 | 5504 | u16 rx_status, ustat_val, cl37_fsm_received; |
239d686d EG |
5505 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); |
5506 | /* Step 1: Make sure signal is detected */ | |
cd2be89b | 5507 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5508 | MDIO_REG_BANK_RX0, |
5509 | MDIO_RX0_RX_STATUS, | |
5510 | &rx_status); | |
239d686d EG |
5511 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
5512 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
5513 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
5514 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
cd2be89b | 5515 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5516 | MDIO_REG_BANK_CL73_IEEEB0, |
5517 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5518 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
239d686d EG |
5519 | return; |
5520 | } | |
5521 | /* Step 2: Check CL73 state machine */ | |
cd2be89b | 5522 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5523 | MDIO_REG_BANK_CL73_USERB0, |
5524 | MDIO_CL73_USERB0_CL73_USTAT1, | |
5525 | &ustat_val); | |
239d686d EG |
5526 | if ((ustat_val & |
5527 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5528 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
5529 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
5530 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
5531 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
5532 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
5533 | return; | |
5534 | } | |
8f73f0b9 | 5535 | /* Step 3: Check CL37 Message Pages received to indicate LP |
2cf7acf9 YR |
5536 | * supports only CL37 |
5537 | */ | |
cd2be89b | 5538 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5539 | MDIO_REG_BANK_REMOTE_PHY, |
5540 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
9045f6b4 YR |
5541 | &cl37_fsm_received); |
5542 | if ((cl37_fsm_received & | |
239d686d EG |
5543 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | |
5544 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
5545 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
5546 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
5547 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
5548 | "misc_rx_status(0x8330) = 0x%x\n", | |
9045f6b4 | 5549 | cl37_fsm_received); |
239d686d EG |
5550 | return; |
5551 | } | |
8f73f0b9 | 5552 | /* The combined cl37/cl73 fsm state information indicating that |
2cf7acf9 YR |
5553 | * we are connected to a device which does not support cl73, but |
5554 | * does support cl37 BAM. In this case we disable cl73 and | |
5555 | * restart cl37 auto-neg | |
5556 | */ | |
5557 | ||
239d686d | 5558 | /* Disable CL73 */ |
cd2be89b | 5559 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5560 | MDIO_REG_BANK_CL73_IEEEB0, |
5561 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
5562 | 0); | |
239d686d | 5563 | /* Restart CL37 autoneg */ |
e10bc84d | 5564 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
5565 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
5566 | } | |
7aa0711f YR |
5567 | |
5568 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
5569 | struct link_params *params, | |
5570 | struct link_vars *vars, | |
5571 | u32 gp_status) | |
5572 | { | |
5573 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
5574 | vars->link_status |= | |
5575 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5576 | ||
5577 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
5578 | vars->link_status |= | |
5579 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5580 | } | |
3c9ada22 YR |
5581 | static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy, |
5582 | struct link_params *params, | |
5583 | struct link_vars *vars, | |
5584 | u16 is_link_up, | |
5585 | u16 speed_mask, | |
5586 | u16 is_duplex) | |
ea4e040a YR |
5587 | { |
5588 | struct bnx2x *bp = params->bp; | |
7aa0711f YR |
5589 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
5590 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
3c9ada22 YR |
5591 | if (is_link_up) { |
5592 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
ea4e040a YR |
5593 | |
5594 | vars->phy_link_up = 1; | |
5595 | vars->link_status |= LINK_STATUS_LINK_UP; | |
5596 | ||
3c9ada22 | 5597 | switch (speed_mask) { |
ea4e040a | 5598 | case GP_STATUS_10M: |
3c9ada22 | 5599 | vars->line_speed = SPEED_10; |
ea4e040a YR |
5600 | if (vars->duplex == DUPLEX_FULL) |
5601 | vars->link_status |= LINK_10TFD; | |
5602 | else | |
5603 | vars->link_status |= LINK_10THD; | |
5604 | break; | |
5605 | ||
5606 | case GP_STATUS_100M: | |
3c9ada22 | 5607 | vars->line_speed = SPEED_100; |
ea4e040a YR |
5608 | if (vars->duplex == DUPLEX_FULL) |
5609 | vars->link_status |= LINK_100TXFD; | |
5610 | else | |
5611 | vars->link_status |= LINK_100TXHD; | |
5612 | break; | |
5613 | ||
5614 | case GP_STATUS_1G: | |
5615 | case GP_STATUS_1G_KX: | |
3c9ada22 | 5616 | vars->line_speed = SPEED_1000; |
ea4e040a YR |
5617 | if (vars->duplex == DUPLEX_FULL) |
5618 | vars->link_status |= LINK_1000TFD; | |
5619 | else | |
5620 | vars->link_status |= LINK_1000THD; | |
5621 | break; | |
5622 | ||
5623 | case GP_STATUS_2_5G: | |
3c9ada22 | 5624 | vars->line_speed = SPEED_2500; |
ea4e040a YR |
5625 | if (vars->duplex == DUPLEX_FULL) |
5626 | vars->link_status |= LINK_2500TFD; | |
5627 | else | |
5628 | vars->link_status |= LINK_2500THD; | |
5629 | break; | |
5630 | ||
5631 | case GP_STATUS_5G: | |
5632 | case GP_STATUS_6G: | |
5633 | DP(NETIF_MSG_LINK, | |
5634 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5635 | speed_mask); |
ea4e040a | 5636 | return -EINVAL; |
ab6ad5a4 | 5637 | |
ea4e040a YR |
5638 | case GP_STATUS_10G_KX4: |
5639 | case GP_STATUS_10G_HIG: | |
5640 | case GP_STATUS_10G_CX4: | |
3c9ada22 YR |
5641 | case GP_STATUS_10G_KR: |
5642 | case GP_STATUS_10G_SFI: | |
5643 | case GP_STATUS_10G_XFI: | |
5644 | vars->line_speed = SPEED_10000; | |
ea4e040a YR |
5645 | vars->link_status |= LINK_10GTFD; |
5646 | break; | |
3c9ada22 YR |
5647 | case GP_STATUS_20G_DXGXS: |
5648 | vars->line_speed = SPEED_20000; | |
5649 | vars->link_status |= LINK_20GTFD; | |
5650 | break; | |
ea4e040a YR |
5651 | default: |
5652 | DP(NETIF_MSG_LINK, | |
5653 | "link speed unsupported gp_status 0x%x\n", | |
3c9ada22 | 5654 | speed_mask); |
ab6ad5a4 | 5655 | return -EINVAL; |
ea4e040a | 5656 | } |
ea4e040a YR |
5657 | } else { /* link_down */ |
5658 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
5659 | ||
5660 | vars->phy_link_up = 0; | |
57963ed9 | 5661 | |
ea4e040a | 5662 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 5663 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 5664 | vars->mac_type = MAC_TYPE_NONE; |
3c9ada22 YR |
5665 | } |
5666 | DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n", | |
5667 | vars->phy_link_up, vars->line_speed); | |
5668 | return 0; | |
5669 | } | |
5670 | ||
5671 | static int bnx2x_link_settings_status(struct bnx2x_phy *phy, | |
5672 | struct link_params *params, | |
5673 | struct link_vars *vars) | |
5674 | { | |
3c9ada22 YR |
5675 | struct bnx2x *bp = params->bp; |
5676 | ||
5677 | u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; | |
5678 | int rc = 0; | |
5679 | ||
5680 | /* Read gp_status */ | |
5681 | CL22_RD_OVER_CL45(bp, phy, | |
5682 | MDIO_REG_BANK_GP_STATUS, | |
5683 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
5684 | &gp_status); | |
5685 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
5686 | duplex = DUPLEX_FULL; | |
5687 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) | |
5688 | link_up = 1; | |
5689 | speed_mask = gp_status & GP_STATUS_SPEED_MASK; | |
5690 | DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", | |
5691 | gp_status, link_up, speed_mask); | |
5692 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, | |
5693 | duplex); | |
5694 | if (rc == -EINVAL) | |
5695 | return rc; | |
239d686d | 5696 | |
3c9ada22 YR |
5697 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
5698 | if (SINGLE_MEDIA_DIRECT(params)) { | |
5699 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); | |
5700 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
5701 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
5702 | gp_status); | |
5703 | } | |
d231023e | 5704 | } else { /* Link_down */ |
c18aa15d YR |
5705 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
5706 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 5707 | /* Check signal is detected */ |
c18aa15d | 5708 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 5709 | } |
ea4e040a YR |
5710 | } |
5711 | ||
9e7e8399 MY |
5712 | /* Read LP advertised speeds*/ |
5713 | if (SINGLE_MEDIA_DIRECT(params) && | |
5714 | (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { | |
5715 | u16 val; | |
5716 | ||
5717 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, | |
5718 | MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); | |
5719 | ||
5720 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5721 | vars->link_status |= | |
5722 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5723 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5724 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5725 | vars->link_status |= | |
5726 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5727 | ||
5728 | CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, | |
5729 | MDIO_OVER_1G_LP_UP1, &val); | |
5730 | ||
5731 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5732 | vars->link_status |= | |
5733 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5734 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5735 | vars->link_status |= | |
5736 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5737 | } | |
5738 | ||
a22f0788 YR |
5739 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
5740 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
5741 | return rc; |
5742 | } | |
5743 | ||
3c9ada22 YR |
5744 | static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, |
5745 | struct link_params *params, | |
5746 | struct link_vars *vars) | |
5747 | { | |
3c9ada22 | 5748 | struct bnx2x *bp = params->bp; |
3c9ada22 YR |
5749 | u8 lane; |
5750 | u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; | |
5751 | int rc = 0; | |
5752 | lane = bnx2x_get_warpcore_lane(phy, params); | |
5753 | /* Read gp_status */ | |
5754 | if (phy->req_line_speed > SPEED_10000) { | |
5755 | u16 temp_link_up; | |
5756 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5757 | 1, &temp_link_up); | |
5758 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5759 | 1, &link_up); | |
5760 | DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", | |
5761 | temp_link_up, link_up); | |
5762 | link_up &= (1<<2); | |
5763 | if (link_up) | |
5764 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5765 | } else { | |
5766 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5767 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1); | |
5768 | DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); | |
5769 | /* Check for either KR or generic link up. */ | |
5770 | gp_status1 = ((gp_status1 >> 8) & 0xf) | | |
5771 | ((gp_status1 >> 12) & 0xf); | |
5772 | link_up = gp_status1 & (1 << lane); | |
5773 | if (link_up && SINGLE_MEDIA_DIRECT(params)) { | |
5774 | u16 pd, gp_status4; | |
5775 | if (phy->req_line_speed == SPEED_AUTO_NEG) { | |
5776 | /* Check Autoneg complete */ | |
5777 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5778 | MDIO_WC_REG_GP2_STATUS_GP_2_4, | |
5779 | &gp_status4); | |
5780 | if (gp_status4 & ((1<<12)<<lane)) | |
5781 | vars->link_status |= | |
5782 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5783 | ||
5784 | /* Check parallel detect used */ | |
5785 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5786 | MDIO_WC_REG_PAR_DET_10G_STATUS, | |
5787 | &pd); | |
5788 | if (pd & (1<<15)) | |
5789 | vars->link_status |= | |
5790 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
5791 | } | |
5792 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5793 | } | |
5794 | } | |
5795 | ||
9e7e8399 MY |
5796 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && |
5797 | SINGLE_MEDIA_DIRECT(params)) { | |
5798 | u16 val; | |
5799 | ||
5800 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
5801 | MDIO_AN_REG_LP_AUTO_NEG2, &val); | |
5802 | ||
5803 | if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) | |
5804 | vars->link_status |= | |
5805 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
5806 | if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | | |
5807 | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) | |
5808 | vars->link_status |= | |
5809 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5810 | ||
5811 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5812 | MDIO_WC_REG_DIGITAL3_LP_UP1, &val); | |
5813 | ||
5814 | if (val & MDIO_OVER_1G_UP1_2_5G) | |
5815 | vars->link_status |= | |
5816 | LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; | |
5817 | if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) | |
5818 | vars->link_status |= | |
5819 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
5820 | ||
5821 | } | |
5822 | ||
5823 | ||
3c9ada22 YR |
5824 | if (lane < 2) { |
5825 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5826 | MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); | |
5827 | } else { | |
5828 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
5829 | MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); | |
5830 | } | |
5831 | DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); | |
5832 | ||
5833 | if ((lane & 1) == 0) | |
5834 | gp_speed <<= 8; | |
5835 | gp_speed &= 0x3f00; | |
5836 | ||
5837 | ||
5838 | rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, | |
5839 | duplex); | |
5840 | ||
5841 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", | |
5842 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
5843 | return rc; | |
5844 | } | |
ed8680a7 | 5845 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
5846 | { |
5847 | struct bnx2x *bp = params->bp; | |
e10bc84d | 5848 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
5849 | u16 lp_up2; |
5850 | u16 tx_driver; | |
c2c8b03e | 5851 | u16 bank; |
ea4e040a | 5852 | |
d231023e | 5853 | /* Read precomp */ |
cd2be89b | 5854 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5855 | MDIO_REG_BANK_OVER_1G, |
5856 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
ea4e040a | 5857 | |
d231023e | 5858 | /* Bits [10:7] at lp_up2, positioned at [15:12] */ |
ea4e040a YR |
5859 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> |
5860 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
5861 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
5862 | ||
c2c8b03e EG |
5863 | if (lp_up2 == 0) |
5864 | return; | |
5865 | ||
5866 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
5867 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
cd2be89b | 5868 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
5869 | bank, |
5870 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
c2c8b03e | 5871 | |
d231023e | 5872 | /* Replace tx_driver bits [15:12] */ |
c2c8b03e EG |
5873 | if (lp_up2 != |
5874 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
5875 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
5876 | tx_driver |= lp_up2; | |
cd2be89b | 5877 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
5878 | bank, |
5879 | MDIO_TX0_TX_DRIVER, tx_driver); | |
c2c8b03e | 5880 | } |
ea4e040a YR |
5881 | } |
5882 | } | |
5883 | ||
fcf5b650 YR |
5884 | static int bnx2x_emac_program(struct link_params *params, |
5885 | struct link_vars *vars) | |
ea4e040a YR |
5886 | { |
5887 | struct bnx2x *bp = params->bp; | |
5888 | u8 port = params->port; | |
5889 | u16 mode = 0; | |
5890 | ||
5891 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
5892 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
cd88ccee YR |
5893 | EMAC_REG_EMAC_MODE, |
5894 | (EMAC_MODE_25G_MODE | | |
5895 | EMAC_MODE_PORT_MII_10M | | |
5896 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 5897 | switch (vars->line_speed) { |
ea4e040a YR |
5898 | case SPEED_10: |
5899 | mode |= EMAC_MODE_PORT_MII_10M; | |
5900 | break; | |
5901 | ||
5902 | case SPEED_100: | |
5903 | mode |= EMAC_MODE_PORT_MII; | |
5904 | break; | |
5905 | ||
5906 | case SPEED_1000: | |
5907 | mode |= EMAC_MODE_PORT_GMII; | |
5908 | break; | |
5909 | ||
5910 | case SPEED_2500: | |
5911 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
5912 | break; | |
5913 | ||
5914 | default: | |
5915 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
5916 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
5917 | vars->line_speed); | |
ea4e040a YR |
5918 | return -EINVAL; |
5919 | } | |
5920 | ||
b7737c9b | 5921 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
5922 | mode |= EMAC_MODE_HALF_DUPLEX; |
5923 | bnx2x_bits_en(bp, | |
cd88ccee YR |
5924 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
5925 | mode); | |
ea4e040a | 5926 | |
7f02c4ad | 5927 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
5928 | return 0; |
5929 | } | |
5930 | ||
de6eae1f YR |
5931 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
5932 | struct link_params *params) | |
b7737c9b | 5933 | { |
de6eae1f YR |
5934 | |
5935 | u16 bank, i = 0; | |
5936 | struct bnx2x *bp = params->bp; | |
5937 | ||
5938 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
5939 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
cd2be89b | 5940 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5941 | bank, |
5942 | MDIO_RX0_RX_EQ_BOOST, | |
5943 | phy->rx_preemphasis[i]); | |
5944 | } | |
5945 | ||
5946 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
5947 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
cd2be89b | 5948 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
5949 | bank, |
5950 | MDIO_TX0_TX_DRIVER, | |
5951 | phy->tx_preemphasis[i]); | |
5952 | } | |
5953 | } | |
5954 | ||
ec146a6f YR |
5955 | static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy, |
5956 | struct link_params *params, | |
5957 | struct link_vars *vars) | |
de6eae1f YR |
5958 | { |
5959 | struct bnx2x *bp = params->bp; | |
5960 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
5961 | (params->loopback_mode == LOOPBACK_XGXS)); | |
5962 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
5963 | if (SINGLE_MEDIA_DIRECT(params) && | |
5964 | (params->feature_config_flags & | |
5965 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
5966 | bnx2x_set_preemphasis(phy, params); | |
5967 | ||
d231023e | 5968 | /* Forced speed requested? */ |
de6eae1f YR |
5969 | if (vars->line_speed != SPEED_AUTO_NEG || |
5970 | (SINGLE_MEDIA_DIRECT(params) && | |
cd88ccee | 5971 | params->loopback_mode == LOOPBACK_EXT)) { |
de6eae1f YR |
5972 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
5973 | ||
d231023e | 5974 | /* Disable autoneg */ |
de6eae1f YR |
5975 | bnx2x_set_autoneg(phy, params, vars, 0); |
5976 | ||
d231023e | 5977 | /* Program speed and duplex */ |
de6eae1f YR |
5978 | bnx2x_program_serdes(phy, params, vars); |
5979 | ||
5980 | } else { /* AN_mode */ | |
5981 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
5982 | ||
5983 | /* AN enabled */ | |
9045f6b4 | 5984 | bnx2x_set_brcm_cl37_advertisement(phy, params); |
de6eae1f | 5985 | |
d231023e | 5986 | /* Program duplex & pause advertisement (for aneg) */ |
9045f6b4 YR |
5987 | bnx2x_set_ieee_aneg_advertisement(phy, params, |
5988 | vars->ieee_fc); | |
de6eae1f | 5989 | |
d231023e | 5990 | /* Enable autoneg */ |
de6eae1f YR |
5991 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); |
5992 | ||
d231023e | 5993 | /* Enable and restart AN */ |
de6eae1f YR |
5994 | bnx2x_restart_autoneg(phy, params, enable_cl73); |
5995 | } | |
5996 | ||
5997 | } else { /* SGMII mode */ | |
5998 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
5999 | ||
6000 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
6001 | } | |
6002 | } | |
6003 | ||
ec146a6f YR |
6004 | static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy, |
6005 | struct link_params *params, | |
6006 | struct link_vars *vars) | |
b7737c9b | 6007 | { |
fcf5b650 | 6008 | int rc; |
ec146a6f | 6009 | vars->phy_flags |= PHY_XGXS_FLAG; |
b7737c9b YR |
6010 | if ((phy->req_line_speed && |
6011 | ((phy->req_line_speed == SPEED_100) || | |
6012 | (phy->req_line_speed == SPEED_10))) || | |
6013 | (!phy->req_line_speed && | |
6014 | (phy->speed_cap_mask >= | |
6015 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
6016 | (phy->speed_cap_mask < | |
ec146a6f YR |
6017 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || |
6018 | (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) | |
b7737c9b YR |
6019 | vars->phy_flags |= PHY_SGMII_FLAG; |
6020 | else | |
6021 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
6022 | ||
6023 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
ec146a6f YR |
6024 | bnx2x_set_aer_mmd(params, phy); |
6025 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) | |
6026 | bnx2x_set_master_ln(params, phy); | |
b7737c9b YR |
6027 | |
6028 | rc = bnx2x_reset_unicore(params, phy, 0); | |
d231023e YM |
6029 | /* Reset the SerDes and wait for reset bit return low */ |
6030 | if (rc) | |
b7737c9b YR |
6031 | return rc; |
6032 | ||
ec146a6f | 6033 | bnx2x_set_aer_mmd(params, phy); |
d231023e | 6034 | /* Setting the masterLn_def again after the reset */ |
ec146a6f YR |
6035 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { |
6036 | bnx2x_set_master_ln(params, phy); | |
6037 | bnx2x_set_swap_lanes(params, phy); | |
6038 | } | |
b7737c9b YR |
6039 | |
6040 | return rc; | |
6041 | } | |
c18aa15d | 6042 | |
de6eae1f | 6043 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
6d870c39 YR |
6044 | struct bnx2x_phy *phy, |
6045 | struct link_params *params) | |
ea4e040a | 6046 | { |
de6eae1f | 6047 | u16 cnt, ctrl; |
25985edc | 6048 | /* Wait for soft reset to get cleared up to 1 sec */ |
de6eae1f | 6049 | for (cnt = 0; cnt < 1000; cnt++) { |
52c4d6c4 | 6050 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6583e33b YR |
6051 | bnx2x_cl22_read(bp, phy, |
6052 | MDIO_PMA_REG_CTRL, &ctrl); | |
6053 | else | |
6054 | bnx2x_cl45_read(bp, phy, | |
6055 | MDIO_PMA_DEVAD, | |
6056 | MDIO_PMA_REG_CTRL, &ctrl); | |
de6eae1f YR |
6057 | if (!(ctrl & (1<<15))) |
6058 | break; | |
d231023e | 6059 | usleep_range(1000, 2000); |
de6eae1f | 6060 | } |
6d870c39 YR |
6061 | |
6062 | if (cnt == 1000) | |
6063 | netdev_err(bp->dev, "Warning: PHY was not initialized," | |
6064 | " Port %d\n", | |
6065 | params->port); | |
de6eae1f YR |
6066 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); |
6067 | return cnt; | |
ea4e040a YR |
6068 | } |
6069 | ||
de6eae1f | 6070 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 6071 | { |
de6eae1f YR |
6072 | u8 port = params->port; |
6073 | u32 mask; | |
6074 | struct bnx2x *bp = params->bp; | |
c18aa15d | 6075 | |
2cf7acf9 | 6076 | /* Setting the status to report on link up for either XGXS or SerDes */ |
3c9ada22 YR |
6077 | if (CHIP_IS_E3(bp)) { |
6078 | mask = NIG_MASK_XGXS0_LINK_STATUS; | |
6079 | if (!(SINGLE_MEDIA_DIRECT(params))) | |
6080 | mask |= NIG_MASK_MI_INT; | |
6081 | } else if (params->switch_cfg == SWITCH_CFG_10G) { | |
de6eae1f YR |
6082 | mask = (NIG_MASK_XGXS0_LINK10G | |
6083 | NIG_MASK_XGXS0_LINK_STATUS); | |
6084 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
6085 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
6086 | params->phy[INT_PHY].type != | |
6087 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
6088 | mask |= NIG_MASK_MI_INT; | |
6089 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
6090 | } | |
6091 | ||
6092 | } else { /* SerDes */ | |
6093 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
6094 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
6095 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
6096 | params->phy[INT_PHY].type != | |
6097 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
6098 | mask |= NIG_MASK_MI_INT; | |
6099 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
6100 | } | |
6101 | } | |
6102 | bnx2x_bits_en(bp, | |
6103 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
6104 | mask); | |
6105 | ||
6106 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
6107 | (params->switch_cfg == SWITCH_CFG_10G), | |
6108 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
6109 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
6110 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6111 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
6112 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
6113 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
6114 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6115 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
6116 | } |
6117 | ||
a22f0788 YR |
6118 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
6119 | u8 exp_mi_int) | |
a35da8db | 6120 | { |
a22f0788 YR |
6121 | u32 latch_status = 0; |
6122 | ||
8f73f0b9 | 6123 | /* Disable the MI INT ( external phy int ) by writing 1 to the |
a22f0788 YR |
6124 | * status register. Link down indication is high-active-signal, |
6125 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
6126 | */ |
6127 | /* Read Latched signals */ | |
6128 | latch_status = REG_RD(bp, | |
a22f0788 YR |
6129 | NIG_REG_LATCH_STATUS_0 + port*8); |
6130 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 6131 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
6132 | if (exp_mi_int) |
6133 | bnx2x_bits_en(bp, | |
6134 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
6135 | + port*4, | |
6136 | NIG_STATUS_EMAC0_MI_INT); | |
6137 | else | |
6138 | bnx2x_bits_dis(bp, | |
6139 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
6140 | + port*4, | |
6141 | NIG_STATUS_EMAC0_MI_INT); | |
6142 | ||
de6eae1f | 6143 | if (latch_status & 1) { |
a22f0788 | 6144 | |
de6eae1f YR |
6145 | /* For all latched-signal=up : Re-Arm Latch signals */ |
6146 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
cd88ccee | 6147 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 6148 | } |
a22f0788 | 6149 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
6150 | } |
6151 | ||
de6eae1f | 6152 | static void bnx2x_link_int_ack(struct link_params *params, |
3c9ada22 | 6153 | struct link_vars *vars, u8 is_10g_plus) |
b1607af5 | 6154 | { |
e10bc84d | 6155 | struct bnx2x *bp = params->bp; |
de6eae1f | 6156 | u8 port = params->port; |
3c9ada22 | 6157 | u32 mask; |
8f73f0b9 | 6158 | /* First reset all status we assume only one line will be |
2cf7acf9 YR |
6159 | * change at a time |
6160 | */ | |
de6eae1f | 6161 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
6162 | (NIG_STATUS_XGXS0_LINK10G | |
6163 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6164 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f | 6165 | if (vars->phy_link_up) { |
3c9ada22 YR |
6166 | if (USES_WARPCORE(bp)) |
6167 | mask = NIG_STATUS_XGXS0_LINK_STATUS; | |
6168 | else { | |
6169 | if (is_10g_plus) | |
6170 | mask = NIG_STATUS_XGXS0_LINK10G; | |
6171 | else if (params->switch_cfg == SWITCH_CFG_10G) { | |
8f73f0b9 | 6172 | /* Disable the link interrupt by writing 1 to |
3c9ada22 YR |
6173 | * the relevant lane in the status register |
6174 | */ | |
6175 | u32 ser_lane = | |
6176 | ((params->lane_config & | |
de6eae1f YR |
6177 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
6178 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
3c9ada22 YR |
6179 | mask = ((1 << ser_lane) << |
6180 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE); | |
6181 | } else | |
6182 | mask = NIG_STATUS_SERDES0_LINK_STATUS; | |
de6eae1f | 6183 | } |
3c9ada22 YR |
6184 | DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", |
6185 | mask); | |
6186 | bnx2x_bits_en(bp, | |
6187 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
6188 | mask); | |
ea4e040a | 6189 | } |
ea4e040a | 6190 | } |
ea4e040a | 6191 | |
fcf5b650 | 6192 | static int bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
de6eae1f YR |
6193 | { |
6194 | u8 *str_ptr = str; | |
6195 | u32 mask = 0xf0000000; | |
6196 | u8 shift = 8*4; | |
6197 | u8 digit; | |
a22f0788 | 6198 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
6199 | if (*len < 10) { |
6200 | /* Need more than 10chars for this format */ | |
6201 | *str_ptr = '\0'; | |
a22f0788 | 6202 | (*len)--; |
de6eae1f | 6203 | return -EINVAL; |
ea4e040a | 6204 | } |
de6eae1f | 6205 | while (shift > 0) { |
ea4e040a | 6206 | |
de6eae1f YR |
6207 | shift -= 4; |
6208 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
6209 | if (digit == 0 && remove_leading_zeros) { |
6210 | mask = mask >> 4; | |
6211 | continue; | |
6212 | } else if (digit < 0xa) | |
de6eae1f YR |
6213 | *str_ptr = digit + '0'; |
6214 | else | |
6215 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 6216 | remove_leading_zeros = 0; |
de6eae1f | 6217 | str_ptr++; |
a22f0788 | 6218 | (*len)--; |
de6eae1f YR |
6219 | mask = mask >> 4; |
6220 | if (shift == 4*4) { | |
a22f0788 | 6221 | *str_ptr = '.'; |
de6eae1f | 6222 | str_ptr++; |
a22f0788 YR |
6223 | (*len)--; |
6224 | remove_leading_zeros = 1; | |
ea4e040a | 6225 | } |
ea4e040a | 6226 | } |
de6eae1f | 6227 | return 0; |
ea4e040a YR |
6228 | } |
6229 | ||
a22f0788 | 6230 | |
fcf5b650 | 6231 | static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 6232 | { |
de6eae1f YR |
6233 | str[0] = '\0'; |
6234 | (*len)--; | |
6235 | return 0; | |
6236 | } | |
ea4e040a | 6237 | |
a1e785e0 MY |
6238 | int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, |
6239 | u16 len) | |
de6eae1f YR |
6240 | { |
6241 | struct bnx2x *bp; | |
6242 | u32 spirom_ver = 0; | |
fcf5b650 | 6243 | int status = 0; |
de6eae1f | 6244 | u8 *ver_p = version; |
a22f0788 | 6245 | u16 remain_len = len; |
de6eae1f YR |
6246 | if (version == NULL || params == NULL) |
6247 | return -EINVAL; | |
6248 | bp = params->bp; | |
ea4e040a | 6249 | |
de6eae1f YR |
6250 | /* Extract first external phy*/ |
6251 | version[0] = '\0'; | |
6252 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 6253 | |
a22f0788 | 6254 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
6255 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
6256 | ver_p, | |
a22f0788 YR |
6257 | &remain_len); |
6258 | ver_p += (len - remain_len); | |
6259 | } | |
6260 | if ((params->num_phys == MAX_PHYS) && | |
6261 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
cd88ccee | 6262 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
a22f0788 YR |
6263 | if (params->phy[EXT_PHY2].format_fw_ver) { |
6264 | *ver_p = '/'; | |
6265 | ver_p++; | |
6266 | remain_len--; | |
6267 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
6268 | spirom_ver, | |
6269 | ver_p, | |
6270 | &remain_len); | |
6271 | ver_p = version + (len - remain_len); | |
6272 | } | |
6273 | } | |
6274 | *ver_p = '\0'; | |
de6eae1f | 6275 | return status; |
6bbca910 | 6276 | } |
ea4e040a | 6277 | |
de6eae1f YR |
6278 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
6279 | struct link_params *params) | |
589abe3a | 6280 | { |
de6eae1f | 6281 | u8 port = params->port; |
589abe3a | 6282 | struct bnx2x *bp = params->bp; |
589abe3a | 6283 | |
de6eae1f | 6284 | if (phy->req_line_speed != SPEED_1000) { |
3c9ada22 | 6285 | u32 md_devad = 0; |
589abe3a | 6286 | |
de6eae1f | 6287 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 6288 | |
3c9ada22 | 6289 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6290 | /* Change the uni_phy_addr in the nig */ |
3c9ada22 YR |
6291 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + |
6292 | port*0x18)); | |
cc1cb004 | 6293 | |
3c9ada22 YR |
6294 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6295 | 0x5); | |
6296 | } | |
589abe3a | 6297 | |
de6eae1f | 6298 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6299 | 5, |
6300 | (MDIO_REG_BANK_AER_BLOCK + | |
6301 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
6302 | 0x2800); | |
589abe3a | 6303 | |
de6eae1f | 6304 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
6305 | 5, |
6306 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
6307 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
6308 | 0x6041); | |
de6eae1f | 6309 | msleep(200); |
d231023e | 6310 | /* Set aer mmd back */ |
ec146a6f | 6311 | bnx2x_set_aer_mmd(params, phy); |
589abe3a | 6312 | |
3c9ada22 | 6313 | if (!CHIP_IS_E3(bp)) { |
d231023e | 6314 | /* And md_devad */ |
3c9ada22 YR |
6315 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
6316 | md_devad); | |
6317 | } | |
de6eae1f YR |
6318 | } else { |
6319 | u16 mii_ctrl; | |
6320 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
6321 | bnx2x_cl45_read(bp, phy, 5, | |
6322 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6323 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6324 | &mii_ctrl); | |
6325 | bnx2x_cl45_write(bp, phy, 5, | |
6326 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
6327 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
6328 | mii_ctrl | | |
6329 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
6330 | } | |
589abe3a EG |
6331 | } |
6332 | ||
fcf5b650 YR |
6333 | int bnx2x_set_led(struct link_params *params, |
6334 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 6335 | { |
de6eae1f YR |
6336 | u8 port = params->port; |
6337 | u16 hw_led_mode = params->hw_led_mode; | |
fcf5b650 YR |
6338 | int rc = 0; |
6339 | u8 phy_idx; | |
de6eae1f YR |
6340 | u32 tmp; |
6341 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 6342 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
6343 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
6344 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
6345 | speed, hw_led_mode); | |
7f02c4ad YR |
6346 | /* In case */ |
6347 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
6348 | if (params->phy[phy_idx].set_link_led) { | |
6349 | params->phy[phy_idx].set_link_led( | |
6350 | ¶ms->phy[phy_idx], params, mode); | |
6351 | } | |
6352 | } | |
6353 | ||
de6eae1f | 6354 | switch (mode) { |
7f02c4ad | 6355 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
6356 | case LED_MODE_OFF: |
6357 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
6358 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
cd88ccee | 6359 | SHARED_HW_CFG_LED_MAC1); |
589abe3a | 6360 | |
de6eae1f | 6361 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
001cea77 | 6362 | if (params->phy[EXT_PHY1].type == |
9379c9be YR |
6363 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
6364 | tmp &= ~(EMAC_LED_1000MB_OVERRIDE | | |
6365 | EMAC_LED_100MB_OVERRIDE | | |
6366 | EMAC_LED_10MB_OVERRIDE); | |
6367 | else | |
6368 | tmp |= EMAC_LED_OVERRIDE; | |
6369 | ||
6370 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); | |
de6eae1f | 6371 | break; |
589abe3a | 6372 | |
de6eae1f | 6373 | case LED_MODE_OPER: |
8f73f0b9 | 6374 | /* For all other phys, OPER mode is same as ON, so in case |
7f02c4ad | 6375 | * link is down, do nothing |
2cf7acf9 | 6376 | */ |
7f02c4ad YR |
6377 | if (!vars->link_up) |
6378 | break; | |
6379 | case LED_MODE_ON: | |
e4d78f12 YR |
6380 | if (((params->phy[EXT_PHY1].type == |
6381 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || | |
6382 | (params->phy[EXT_PHY1].type == | |
6383 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && | |
1f48353a | 6384 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
8f73f0b9 | 6385 | /* This is a work-around for E2+8727 Configurations */ |
1f48353a YR |
6386 | if (mode == LED_MODE_ON || |
6387 | speed == SPEED_10000){ | |
6388 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6389 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6390 | ||
6391 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
6392 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6393 | (tmp | EMAC_LED_OVERRIDE)); | |
8f73f0b9 | 6394 | /* Return here without enabling traffic |
ab505dec | 6395 | * LED blink and setting rate in ON mode. |
793bd450 YR |
6396 | * In oper mode, enabling LED blink |
6397 | * and setting rate is needed. | |
6398 | */ | |
6399 | if (mode == LED_MODE_ON) | |
6400 | return rc; | |
1f48353a | 6401 | } |
793bd450 | 6402 | } else if (SINGLE_MEDIA_DIRECT(params)) { |
8f73f0b9 | 6403 | /* This is a work-around for HW issue found when link |
2cf7acf9 YR |
6404 | * is up in CL73 |
6405 | */ | |
ab505dec YR |
6406 | if ((!CHIP_IS_E3(bp)) || |
6407 | (CHIP_IS_E3(bp) && | |
6408 | mode == LED_MODE_ON)) | |
6409 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
6410 | ||
793bd450 YR |
6411 | if (CHIP_IS_E1x(bp) || |
6412 | CHIP_IS_E2(bp) || | |
6413 | (mode == LED_MODE_ON)) | |
6414 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
6415 | else | |
6416 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
6417 | hw_led_mode); | |
001cea77 YR |
6418 | } else if ((params->phy[EXT_PHY1].type == |
6419 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && | |
9379c9be | 6420 | (mode == LED_MODE_ON)) { |
001cea77 YR |
6421 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
6422 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
9379c9be YR |
6423 | EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | |
6424 | EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); | |
6425 | /* Break here; otherwise, it'll disable the | |
6426 | * intended override. | |
6427 | */ | |
6428 | break; | |
793bd450 | 6429 | } else |
001cea77 YR |
6430 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, |
6431 | hw_led_mode); | |
589abe3a | 6432 | |
cd88ccee | 6433 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
de6eae1f | 6434 | /* Set blinking rate to ~15.9Hz */ |
26ffaf36 YR |
6435 | if (CHIP_IS_E3(bp)) |
6436 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6437 | LED_BLINK_RATE_VAL_E3); | |
6438 | else | |
6439 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
6440 | LED_BLINK_RATE_VAL_E1X_E2); | |
de6eae1f | 6441 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
cd88ccee | 6442 | port*4, 1); |
9379c9be YR |
6443 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
6444 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
6445 | (tmp & (~EMAC_LED_OVERRIDE))); | |
589abe3a | 6446 | |
de6eae1f YR |
6447 | if (CHIP_IS_E1(bp) && |
6448 | ((speed == SPEED_2500) || | |
6449 | (speed == SPEED_1000) || | |
6450 | (speed == SPEED_100) || | |
6451 | (speed == SPEED_10))) { | |
8f73f0b9 | 6452 | /* For speeds less than 10G LED scheme is different */ |
de6eae1f | 6453 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
cd88ccee | 6454 | + port*4, 1); |
de6eae1f | 6455 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
cd88ccee | 6456 | port*4, 0); |
de6eae1f | 6457 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
cd88ccee | 6458 | port*4, 1); |
de6eae1f YR |
6459 | } |
6460 | break; | |
589abe3a | 6461 | |
de6eae1f YR |
6462 | default: |
6463 | rc = -EINVAL; | |
6464 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
6465 | mode); | |
6466 | break; | |
589abe3a | 6467 | } |
de6eae1f | 6468 | return rc; |
589abe3a | 6469 | |
4d295db0 EG |
6470 | } |
6471 | ||
8f73f0b9 | 6472 | /* This function comes to reflect the actual link state read DIRECTLY from the |
a22f0788 YR |
6473 | * HW |
6474 | */ | |
fcf5b650 YR |
6475 | int bnx2x_test_link(struct link_params *params, struct link_vars *vars, |
6476 | u8 is_serdes) | |
4d295db0 EG |
6477 | { |
6478 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6479 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
6480 | u8 ext_phy_link_up = 0, serdes_phy_type; |
6481 | struct link_vars temp_vars; | |
3c9ada22 YR |
6482 | struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; |
6483 | ||
6484 | if (CHIP_IS_E3(bp)) { | |
6485 | u16 link_up; | |
6486 | if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] | |
6487 | > SPEED_10000) { | |
6488 | /* Check 20G link */ | |
6489 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6490 | 1, &link_up); | |
6491 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6492 | 1, &link_up); | |
6493 | link_up &= (1<<2); | |
6494 | } else { | |
6495 | /* Check 10G link and below*/ | |
6496 | u8 lane = bnx2x_get_warpcore_lane(int_phy, params); | |
6497 | bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, | |
6498 | MDIO_WC_REG_GP2_STATUS_GP_2_1, | |
6499 | &gp_status); | |
6500 | gp_status = ((gp_status >> 8) & 0xf) | | |
6501 | ((gp_status >> 12) & 0xf); | |
6502 | link_up = gp_status & (1 << lane); | |
6503 | } | |
6504 | if (!link_up) | |
6505 | return -ESRCH; | |
6506 | } else { | |
6507 | CL22_RD_OVER_CL45(bp, int_phy, | |
cd88ccee YR |
6508 | MDIO_REG_BANK_GP_STATUS, |
6509 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
6510 | &gp_status); | |
d231023e | 6511 | /* Link is up only if both local phy and external phy are up */ |
a22f0788 YR |
6512 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
6513 | return -ESRCH; | |
3c9ada22 YR |
6514 | } |
6515 | /* In XGXS loopback mode, do not check external PHY */ | |
6516 | if (params->loopback_mode == LOOPBACK_XGXS) | |
6517 | return 0; | |
a22f0788 YR |
6518 | |
6519 | switch (params->num_phys) { | |
6520 | case 1: | |
6521 | /* No external PHY */ | |
6522 | return 0; | |
6523 | case 2: | |
6524 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
6525 | ¶ms->phy[EXT_PHY1], | |
6526 | params, &temp_vars); | |
6527 | break; | |
6528 | case 3: /* Dual Media */ | |
de6eae1f YR |
6529 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6530 | phy_index++) { | |
a22f0788 | 6531 | serdes_phy_type = ((params->phy[phy_index].media_type == |
dbef807e YM |
6532 | ETH_PHY_SFPP_10G_FIBER) || |
6533 | (params->phy[phy_index].media_type == | |
6534 | ETH_PHY_SFP_1G_FIBER) || | |
a22f0788 | 6535 | (params->phy[phy_index].media_type == |
1ac9e428 YR |
6536 | ETH_PHY_XFP_FIBER) || |
6537 | (params->phy[phy_index].media_type == | |
6538 | ETH_PHY_DA_TWINAX)); | |
a22f0788 YR |
6539 | |
6540 | if (is_serdes != serdes_phy_type) | |
6541 | continue; | |
6542 | if (params->phy[phy_index].read_status) { | |
6543 | ext_phy_link_up |= | |
de6eae1f YR |
6544 | params->phy[phy_index].read_status( |
6545 | ¶ms->phy[phy_index], | |
6546 | params, &temp_vars); | |
a22f0788 | 6547 | } |
de6eae1f | 6548 | } |
a22f0788 | 6549 | break; |
4d295db0 | 6550 | } |
a22f0788 YR |
6551 | if (ext_phy_link_up) |
6552 | return 0; | |
de6eae1f YR |
6553 | return -ESRCH; |
6554 | } | |
4d295db0 | 6555 | |
fcf5b650 YR |
6556 | static int bnx2x_link_initialize(struct link_params *params, |
6557 | struct link_vars *vars) | |
de6eae1f | 6558 | { |
fcf5b650 | 6559 | int rc = 0; |
de6eae1f YR |
6560 | u8 phy_index, non_ext_phy; |
6561 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 6562 | /* In case of external phy existence, the line speed would be the |
2cf7acf9 YR |
6563 | * line speed linked up by the external phy. In case it is direct |
6564 | * only, then the line_speed during initialization will be | |
6565 | * equal to the req_line_speed | |
6566 | */ | |
de6eae1f | 6567 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
4d295db0 | 6568 | |
8f73f0b9 | 6569 | /* Initialize the internal phy in case this is a direct board |
de6eae1f YR |
6570 | * (no external phys), or this board has external phy which requires |
6571 | * to first. | |
6572 | */ | |
3c9ada22 YR |
6573 | if (!USES_WARPCORE(bp)) |
6574 | bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f YR |
6575 | /* init ext phy and enable link state int */ |
6576 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
6577 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 6578 | |
de6eae1f YR |
6579 | if (non_ext_phy || |
6580 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
6581 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
6582 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
3c9ada22 YR |
6583 | if (vars->line_speed == SPEED_AUTO_NEG && |
6584 | (CHIP_IS_E1x(bp) || | |
6585 | CHIP_IS_E2(bp))) | |
de6eae1f | 6586 | bnx2x_set_parallel_detection(phy, params); |
ec146a6f YR |
6587 | if (params->phy[INT_PHY].config_init) |
6588 | params->phy[INT_PHY].config_init(phy, | |
6589 | params, | |
6590 | vars); | |
4d295db0 EG |
6591 | } |
6592 | ||
de6eae1f | 6593 | /* Init external phy*/ |
fd36a2e6 YR |
6594 | if (non_ext_phy) { |
6595 | if (params->phy[INT_PHY].supported & | |
6596 | SUPPORTED_FIBRE) | |
6597 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6598 | } else { | |
de6eae1f YR |
6599 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6600 | phy_index++) { | |
8f73f0b9 | 6601 | /* No need to initialize second phy in case of first |
a22f0788 YR |
6602 | * phy only selection. In case of second phy, we do |
6603 | * need to initialize the first phy, since they are | |
6604 | * connected. | |
2cf7acf9 | 6605 | */ |
fd36a2e6 YR |
6606 | if (params->phy[phy_index].supported & |
6607 | SUPPORTED_FIBRE) | |
6608 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
6609 | ||
a22f0788 YR |
6610 | if (phy_index == EXT_PHY2 && |
6611 | (bnx2x_phy_selection(params) == | |
6612 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
94f05b0f JP |
6613 | DP(NETIF_MSG_LINK, |
6614 | "Not initializing second phy\n"); | |
a22f0788 YR |
6615 | continue; |
6616 | } | |
de6eae1f YR |
6617 | params->phy[phy_index].config_init( |
6618 | ¶ms->phy[phy_index], | |
6619 | params, vars); | |
6620 | } | |
fd36a2e6 | 6621 | } |
de6eae1f YR |
6622 | /* Reset the interrupt indication after phy was initialized */ |
6623 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
6624 | params->port*4, | |
6625 | (NIG_STATUS_XGXS0_LINK10G | | |
6626 | NIG_STATUS_XGXS0_LINK_STATUS | | |
6627 | NIG_STATUS_SERDES0_LINK_STATUS | | |
6628 | NIG_MASK_MI_INT)); | |
6629 | return rc; | |
6630 | } | |
4d295db0 | 6631 | |
de6eae1f YR |
6632 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
6633 | struct link_params *params) | |
6634 | { | |
d231023e | 6635 | /* Reset the SerDes/XGXS */ |
cd88ccee YR |
6636 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
6637 | (0x1ff << (params->port*16))); | |
589abe3a EG |
6638 | } |
6639 | ||
de6eae1f YR |
6640 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
6641 | struct link_params *params) | |
4d295db0 | 6642 | { |
de6eae1f YR |
6643 | struct bnx2x *bp = params->bp; |
6644 | u8 gpio_port; | |
6645 | /* HW reset */ | |
f2e0899f DK |
6646 | if (CHIP_IS_E2(bp)) |
6647 | gpio_port = BP_PATH(bp); | |
6648 | else | |
6649 | gpio_port = params->port; | |
de6eae1f | 6650 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee YR |
6651 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6652 | gpio_port); | |
de6eae1f | 6653 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
6654 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6655 | gpio_port); | |
de6eae1f | 6656 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
4d295db0 | 6657 | } |
589abe3a | 6658 | |
fcf5b650 YR |
6659 | static int bnx2x_update_link_down(struct link_params *params, |
6660 | struct link_vars *vars) | |
589abe3a EG |
6661 | { |
6662 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6663 | u8 port = params->port; |
589abe3a | 6664 | |
de6eae1f | 6665 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 6666 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
3deb8167 | 6667 | vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; |
d231023e | 6668 | /* Indicate no mac active */ |
de6eae1f | 6669 | vars->mac_type = MAC_TYPE_NONE; |
ab6ad5a4 | 6670 | |
d231023e | 6671 | /* Update shared memory */ |
fd36a2e6 YR |
6672 | vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK | |
6673 | LINK_STATUS_LINK_UP | | |
de6f3377 | 6674 | LINK_STATUS_PHYSICAL_LINK_FLAG | |
fd36a2e6 YR |
6675 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | |
6676 | LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | | |
6677 | LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | | |
9e7e8399 MY |
6678 | LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | |
6679 | LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | | |
6680 | LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE); | |
de6eae1f YR |
6681 | vars->line_speed = 0; |
6682 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 6683 | |
d231023e | 6684 | /* Activate nig drain */ |
de6eae1f | 6685 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
4d295db0 | 6686 | |
d231023e | 6687 | /* Disable emac */ |
9380bb9e YR |
6688 | if (!CHIP_IS_E3(bp)) |
6689 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
de6eae1f | 6690 | |
d231023e YM |
6691 | usleep_range(10000, 20000); |
6692 | /* Reset BigMac/Xmac */ | |
9380bb9e YR |
6693 | if (CHIP_IS_E1x(bp) || |
6694 | CHIP_IS_E2(bp)) { | |
6695 | bnx2x_bmac_rx_disable(bp, params->port); | |
6696 | REG_WR(bp, GRCBASE_MISC + | |
6697 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 6698 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
9380bb9e | 6699 | } |
ce7c0489 | 6700 | if (CHIP_IS_E3(bp)) { |
d231023e | 6701 | /* Prevent LPI Generation by chip */ |
c8c60d88 YM |
6702 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), |
6703 | 0); | |
c8c60d88 YM |
6704 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), |
6705 | 0); | |
6706 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | | |
6707 | SHMEM_EEE_ACTIVE_BIT); | |
6708 | ||
6709 | bnx2x_update_mng_eee(params, vars->eee_status); | |
9380bb9e | 6710 | bnx2x_xmac_disable(params); |
ce7c0489 YR |
6711 | bnx2x_umac_disable(params); |
6712 | } | |
9380bb9e | 6713 | |
589abe3a EG |
6714 | return 0; |
6715 | } | |
de6eae1f | 6716 | |
fcf5b650 YR |
6717 | static int bnx2x_update_link_up(struct link_params *params, |
6718 | struct link_vars *vars, | |
6719 | u8 link_10g) | |
589abe3a EG |
6720 | { |
6721 | struct bnx2x *bp = params->bp; | |
55098c5c | 6722 | u8 phy_idx, port = params->port; |
fcf5b650 | 6723 | int rc = 0; |
4d295db0 | 6724 | |
de6f3377 YR |
6725 | vars->link_status |= (LINK_STATUS_LINK_UP | |
6726 | LINK_STATUS_PHYSICAL_LINK_FLAG); | |
3deb8167 | 6727 | vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; |
7f02c4ad | 6728 | |
de6eae1f YR |
6729 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
6730 | vars->link_status |= | |
6731 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 6732 | |
de6eae1f YR |
6733 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
6734 | vars->link_status |= | |
6735 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
9380bb9e | 6736 | if (USES_WARPCORE(bp)) { |
3deb8167 YR |
6737 | if (link_10g) { |
6738 | if (bnx2x_xmac_enable(params, vars, 0) == | |
6739 | -ESRCH) { | |
6740 | DP(NETIF_MSG_LINK, "Found errors on XMAC\n"); | |
6741 | vars->link_up = 0; | |
6742 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6743 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6744 | } | |
6745 | } else | |
9380bb9e | 6746 | bnx2x_umac_enable(params, vars, 0); |
7f02c4ad | 6747 | bnx2x_set_led(params, vars, |
9380bb9e | 6748 | LED_MODE_OPER, vars->line_speed); |
c8c60d88 YM |
6749 | |
6750 | if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && | |
6751 | (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { | |
6752 | DP(NETIF_MSG_LINK, "Enabling LPI assertion\n"); | |
6753 | REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + | |
6754 | (params->port << 2), 1); | |
6755 | REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); | |
6756 | REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + | |
6757 | (params->port << 2), 0xfc20); | |
6758 | } | |
9380bb9e YR |
6759 | } |
6760 | if ((CHIP_IS_E1x(bp) || | |
6761 | CHIP_IS_E2(bp))) { | |
6762 | if (link_10g) { | |
3deb8167 YR |
6763 | if (bnx2x_bmac_enable(params, vars, 0) == |
6764 | -ESRCH) { | |
6765 | DP(NETIF_MSG_LINK, "Found errors on BMAC\n"); | |
6766 | vars->link_up = 0; | |
6767 | vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; | |
6768 | vars->link_status &= ~LINK_STATUS_LINK_UP; | |
6769 | } | |
cc1cb004 | 6770 | |
9380bb9e YR |
6771 | bnx2x_set_led(params, vars, |
6772 | LED_MODE_OPER, SPEED_10000); | |
6773 | } else { | |
6774 | rc = bnx2x_emac_program(params, vars); | |
6775 | bnx2x_emac_enable(params, vars, 0); | |
6776 | ||
6777 | /* AN complete? */ | |
6778 | if ((vars->link_status & | |
6779 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
6780 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
6781 | SINGLE_MEDIA_DIRECT(params)) | |
6782 | bnx2x_set_gmii_tx_driver(params); | |
6783 | } | |
de6eae1f | 6784 | } |
cc1cb004 | 6785 | |
de6eae1f | 6786 | /* PBF - link up */ |
9380bb9e | 6787 | if (CHIP_IS_E1x(bp)) |
f2e0899f DK |
6788 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, |
6789 | vars->line_speed); | |
589abe3a | 6790 | |
d231023e | 6791 | /* Disable drain */ |
de6eae1f | 6792 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); |
589abe3a | 6793 | |
d231023e | 6794 | /* Update shared memory */ |
de6eae1f | 6795 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 | 6796 | bnx2x_update_mng_eee(params, vars->eee_status); |
55098c5c YR |
6797 | /* Check remote fault */ |
6798 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
6799 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
6800 | bnx2x_check_half_open_conn(params, vars, 0); | |
6801 | break; | |
6802 | } | |
6803 | } | |
de6eae1f YR |
6804 | msleep(20); |
6805 | return rc; | |
589abe3a | 6806 | } |
8f73f0b9 | 6807 | /* The bnx2x_link_update function should be called upon link |
de6eae1f YR |
6808 | * interrupt. |
6809 | * Link is considered up as follows: | |
6810 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
6811 | * to be up | |
6812 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
6813 | * phy (XGXS) need to up as well as the external link of the | |
6814 | * phy (PHY_EXT1) | |
6815 | * - DUAL_MEDIA - The link between the 577xx and the first | |
6816 | * external phy needs to be up, and at least one of the 2 | |
6817 | * external phy link must be up. | |
6818 | */ | |
fcf5b650 | 6819 | int bnx2x_link_update(struct link_params *params, struct link_vars *vars) |
4d295db0 | 6820 | { |
de6eae1f YR |
6821 | struct bnx2x *bp = params->bp; |
6822 | struct link_vars phy_vars[MAX_PHYS]; | |
6823 | u8 port = params->port; | |
3c9ada22 | 6824 | u8 link_10g_plus, phy_index; |
fcf5b650 YR |
6825 | u8 ext_phy_link_up = 0, cur_link_up; |
6826 | int rc = 0; | |
de6eae1f YR |
6827 | u8 is_mi_int = 0; |
6828 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
6829 | u8 active_external_phy = INT_PHY; | |
3deb8167 | 6830 | vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; |
de6eae1f YR |
6831 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
6832 | phy_index++) { | |
6833 | phy_vars[phy_index].flow_ctrl = 0; | |
6834 | phy_vars[phy_index].link_status = 0; | |
6835 | phy_vars[phy_index].line_speed = 0; | |
6836 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
6837 | phy_vars[phy_index].phy_link_up = 0; | |
6838 | phy_vars[phy_index].link_up = 0; | |
c688fe2f | 6839 | phy_vars[phy_index].fault_detected = 0; |
c8c60d88 YM |
6840 | /* different consideration, since vars holds inner state */ |
6841 | phy_vars[phy_index].eee_status = vars->eee_status; | |
de6eae1f | 6842 | } |
4d295db0 | 6843 | |
3c9ada22 YR |
6844 | if (USES_WARPCORE(bp)) |
6845 | bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); | |
6846 | ||
de6eae1f YR |
6847 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
6848 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
6849 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 6850 | |
de6eae1f | 6851 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
cd88ccee | 6852 | port*0x18) > 0); |
de6eae1f YR |
6853 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
6854 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
6855 | is_mi_int, | |
cd88ccee | 6856 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
4d295db0 | 6857 | |
de6eae1f YR |
6858 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
6859 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
6860 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 6861 | |
d231023e | 6862 | /* Disable emac */ |
9380bb9e YR |
6863 | if (!CHIP_IS_E3(bp)) |
6864 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 6865 | |
8f73f0b9 | 6866 | /* Step 1: |
2cf7acf9 YR |
6867 | * Check external link change only for external phys, and apply |
6868 | * priority selection between them in case the link on both phys | |
9045f6b4 | 6869 | * is up. Note that instead of the common vars, a temporary |
2cf7acf9 YR |
6870 | * vars argument is used since each phy may have different link/ |
6871 | * speed/duplex result | |
6872 | */ | |
de6eae1f YR |
6873 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
6874 | phy_index++) { | |
6875 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
6876 | if (!phy->read_status) | |
6877 | continue; | |
6878 | /* Read link status and params of this ext phy */ | |
6879 | cur_link_up = phy->read_status(phy, params, | |
6880 | &phy_vars[phy_index]); | |
6881 | if (cur_link_up) { | |
6882 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
6883 | phy_index); | |
6884 | } else { | |
6885 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
6886 | phy_index); | |
6887 | continue; | |
6888 | } | |
e10bc84d | 6889 | |
de6eae1f YR |
6890 | if (!ext_phy_link_up) { |
6891 | ext_phy_link_up = 1; | |
6892 | active_external_phy = phy_index; | |
a22f0788 YR |
6893 | } else { |
6894 | switch (bnx2x_phy_selection(params)) { | |
6895 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6896 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
8f73f0b9 | 6897 | /* In this option, the first PHY makes sure to pass the |
a22f0788 YR |
6898 | * traffic through itself only. |
6899 | * Its not clear how to reset the link on the second phy | |
2cf7acf9 | 6900 | */ |
a22f0788 YR |
6901 | active_external_phy = EXT_PHY1; |
6902 | break; | |
6903 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
8f73f0b9 | 6904 | /* In this option, the first PHY makes sure to pass the |
a22f0788 | 6905 | * traffic through the second PHY. |
2cf7acf9 | 6906 | */ |
a22f0788 YR |
6907 | active_external_phy = EXT_PHY2; |
6908 | break; | |
6909 | default: | |
8f73f0b9 | 6910 | /* Link indication on both PHYs with the following cases |
a22f0788 YR |
6911 | * is invalid: |
6912 | * - FIRST_PHY means that second phy wasn't initialized, | |
6913 | * hence its link is expected to be down | |
6914 | * - SECOND_PHY means that first phy should not be able | |
6915 | * to link up by itself (using configuration) | |
6916 | * - DEFAULT should be overriden during initialiazation | |
2cf7acf9 | 6917 | */ |
a22f0788 YR |
6918 | DP(NETIF_MSG_LINK, "Invalid link indication" |
6919 | "mpc=0x%x. DISABLING LINK !!!\n", | |
6920 | params->multi_phy_config); | |
6921 | ext_phy_link_up = 0; | |
6922 | break; | |
6923 | } | |
589abe3a | 6924 | } |
589abe3a | 6925 | } |
de6eae1f | 6926 | prev_line_speed = vars->line_speed; |
8f73f0b9 | 6927 | /* Step 2: |
2cf7acf9 YR |
6928 | * Read the status of the internal phy. In case of |
6929 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
6930 | * otherwise this is the link between the 577xx and the first | |
6931 | * external phy | |
6932 | */ | |
de6eae1f YR |
6933 | if (params->phy[INT_PHY].read_status) |
6934 | params->phy[INT_PHY].read_status( | |
6935 | ¶ms->phy[INT_PHY], | |
6936 | params, vars); | |
8f73f0b9 | 6937 | /* The INT_PHY flow control reside in the vars. This include the |
de6eae1f YR |
6938 | * case where the speed or flow control are not set to AUTO. |
6939 | * Otherwise, the active external phy flow control result is set | |
6940 | * to the vars. The ext_phy_line_speed is needed to check if the | |
6941 | * speed is different between the internal phy and external phy. | |
6942 | * This case may be result of intermediate link speed change. | |
4d295db0 | 6943 | */ |
de6eae1f YR |
6944 | if (active_external_phy > INT_PHY) { |
6945 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
8f73f0b9 | 6946 | /* Link speed is taken from the XGXS. AN and FC result from |
de6eae1f | 6947 | * the external phy. |
4d295db0 | 6948 | */ |
de6eae1f | 6949 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 | 6950 | |
8f73f0b9 | 6951 | /* if active_external_phy is first PHY and link is up - disable |
a22f0788 YR |
6952 | * disable TX on second external PHY |
6953 | */ | |
6954 | if (active_external_phy == EXT_PHY1) { | |
6955 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
94f05b0f JP |
6956 | DP(NETIF_MSG_LINK, |
6957 | "Disabling TX on EXT_PHY2\n"); | |
a22f0788 YR |
6958 | params->phy[EXT_PHY2].phy_specific_func( |
6959 | ¶ms->phy[EXT_PHY2], | |
6960 | params, DISABLE_TX); | |
6961 | } | |
6962 | } | |
6963 | ||
de6eae1f YR |
6964 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
6965 | vars->duplex = phy_vars[active_external_phy].duplex; | |
6966 | if (params->phy[active_external_phy].supported & | |
6967 | SUPPORTED_FIBRE) | |
6968 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
fd36a2e6 YR |
6969 | else |
6970 | vars->link_status &= ~LINK_STATUS_SERDES_LINK; | |
c8c60d88 YM |
6971 | |
6972 | vars->eee_status = phy_vars[active_external_phy].eee_status; | |
6973 | ||
de6eae1f YR |
6974 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", |
6975 | active_external_phy); | |
6976 | } | |
a22f0788 YR |
6977 | |
6978 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
6979 | phy_index++) { | |
6980 | if (params->phy[phy_index].flags & | |
6981 | FLAGS_REARM_LATCH_SIGNAL) { | |
6982 | bnx2x_rearm_latch_signal(bp, port, | |
6983 | phy_index == | |
6984 | active_external_phy); | |
6985 | break; | |
6986 | } | |
6987 | } | |
de6eae1f YR |
6988 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
6989 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
6990 | vars->link_status, ext_phy_line_speed); | |
8f73f0b9 | 6991 | /* Upon link speed change set the NIG into drain mode. Comes to |
de6eae1f YR |
6992 | * deals with possible FIFO glitch due to clk change when speed |
6993 | * is decreased without link down indicator | |
6994 | */ | |
4d295db0 | 6995 | |
de6eae1f YR |
6996 | if (vars->phy_link_up) { |
6997 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
6998 | (ext_phy_line_speed != vars->line_speed)) { | |
6999 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
7000 | " different than the external" | |
7001 | " link speed %d\n", vars->line_speed, | |
7002 | ext_phy_line_speed); | |
7003 | vars->phy_link_up = 0; | |
7004 | } else if (prev_line_speed != vars->line_speed) { | |
cd88ccee YR |
7005 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
7006 | 0); | |
d231023e | 7007 | usleep_range(1000, 2000); |
de6eae1f YR |
7008 | } |
7009 | } | |
e10bc84d | 7010 | |
d231023e | 7011 | /* Anything 10 and over uses the bmac */ |
3c9ada22 | 7012 | link_10g_plus = (vars->line_speed >= SPEED_10000); |
589abe3a | 7013 | |
3c9ada22 | 7014 | bnx2x_link_int_ack(params, vars, link_10g_plus); |
589abe3a | 7015 | |
8f73f0b9 | 7016 | /* In case external phy link is up, and internal link is down |
2cf7acf9 YR |
7017 | * (not initialized yet probably after link initialization, it |
7018 | * needs to be initialized. | |
7019 | * Note that after link down-up as result of cable plug, the xgxs | |
7020 | * link would probably become up again without the need | |
7021 | * initialize it | |
7022 | */ | |
de6eae1f YR |
7023 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
7024 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
7025 | " init_preceding = %d\n", ext_phy_link_up, | |
7026 | vars->phy_link_up, | |
7027 | params->phy[EXT_PHY1].flags & | |
7028 | FLAGS_INIT_XGXS_FIRST); | |
7029 | if (!(params->phy[EXT_PHY1].flags & | |
7030 | FLAGS_INIT_XGXS_FIRST) | |
7031 | && ext_phy_link_up && !vars->phy_link_up) { | |
7032 | vars->line_speed = ext_phy_line_speed; | |
7033 | if (vars->line_speed < SPEED_1000) | |
7034 | vars->phy_flags |= PHY_SGMII_FLAG; | |
7035 | else | |
7036 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
ec146a6f YR |
7037 | |
7038 | if (params->phy[INT_PHY].config_init) | |
7039 | params->phy[INT_PHY].config_init( | |
7040 | ¶ms->phy[INT_PHY], params, | |
de6eae1f | 7041 | vars); |
4d295db0 | 7042 | } |
589abe3a | 7043 | } |
8f73f0b9 | 7044 | /* Link is up only if both local phy and external phy (in case of |
9045f6b4 | 7045 | * non-direct board) are up and no fault detected on active PHY. |
4d295db0 | 7046 | */ |
de6eae1f YR |
7047 | vars->link_up = (vars->phy_link_up && |
7048 | (ext_phy_link_up || | |
c688fe2f YR |
7049 | SINGLE_MEDIA_DIRECT(params)) && |
7050 | (phy_vars[active_external_phy].fault_detected == 0)); | |
de6eae1f | 7051 | |
27d9129f YR |
7052 | /* Update the PFC configuration in case it was changed */ |
7053 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
7054 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
7055 | else | |
7056 | vars->link_status &= ~LINK_STATUS_PFC_ENABLED; | |
7057 | ||
de6eae1f | 7058 | if (vars->link_up) |
3c9ada22 | 7059 | rc = bnx2x_update_link_up(params, vars, link_10g_plus); |
4d295db0 | 7060 | else |
de6eae1f | 7061 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 7062 | |
a3348722 BW |
7063 | /* Update MCP link status was changed */ |
7064 | if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) | |
7065 | bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); | |
7066 | ||
4d295db0 | 7067 | return rc; |
589abe3a EG |
7068 | } |
7069 | ||
de6eae1f YR |
7070 | /*****************************************************************************/ |
7071 | /* External Phy section */ | |
7072 | /*****************************************************************************/ | |
7073 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
7074 | { | |
7075 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 7076 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
d231023e | 7077 | usleep_range(1000, 2000); |
de6eae1f | 7078 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7079 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
de6eae1f | 7080 | } |
589abe3a | 7081 | |
de6eae1f YR |
7082 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
7083 | u32 spirom_ver, u32 ver_addr) | |
7084 | { | |
7085 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
7086 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 7087 | |
de6eae1f YR |
7088 | if (ver_addr) |
7089 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
7090 | } |
7091 | ||
de6eae1f YR |
7092 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
7093 | struct bnx2x_phy *phy, | |
7094 | u8 port) | |
6bbca910 | 7095 | { |
de6eae1f YR |
7096 | u16 fw_ver1, fw_ver2; |
7097 | ||
7098 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
cd88ccee | 7099 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
de6eae1f | 7100 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
cd88ccee | 7101 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
de6eae1f YR |
7102 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
7103 | phy->ver_addr); | |
ea4e040a | 7104 | } |
ab6ad5a4 | 7105 | |
de6eae1f YR |
7106 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, |
7107 | struct bnx2x_phy *phy, | |
7108 | struct link_vars *vars) | |
7109 | { | |
7110 | u16 val; | |
7111 | bnx2x_cl45_read(bp, phy, | |
7112 | MDIO_AN_DEVAD, | |
7113 | MDIO_AN_REG_STATUS, &val); | |
7114 | bnx2x_cl45_read(bp, phy, | |
7115 | MDIO_AN_DEVAD, | |
7116 | MDIO_AN_REG_STATUS, &val); | |
7117 | if (val & (1<<5)) | |
7118 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
7119 | if ((val & (1<<0)) == 0) | |
7120 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
7121 | } | |
7122 | ||
7123 | /******************************************************************/ | |
7124 | /* common BCM8073/BCM8727 PHY SECTION */ | |
7125 | /******************************************************************/ | |
7126 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
7127 | struct link_params *params, | |
7128 | struct link_vars *vars) | |
7129 | { | |
7130 | struct bnx2x *bp = params->bp; | |
7131 | if (phy->req_line_speed == SPEED_10 || | |
7132 | phy->req_line_speed == SPEED_100) { | |
7133 | vars->flow_ctrl = phy->req_flow_ctrl; | |
7134 | return; | |
7135 | } | |
7136 | ||
7137 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
7138 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
7139 | u16 pause_result; | |
7140 | u16 ld_pause; /* local */ | |
7141 | u16 lp_pause; /* link partner */ | |
7142 | bnx2x_cl45_read(bp, phy, | |
7143 | MDIO_AN_DEVAD, | |
7144 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
7145 | ||
7146 | bnx2x_cl45_read(bp, phy, | |
7147 | MDIO_AN_DEVAD, | |
7148 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
7149 | pause_result = (ld_pause & | |
7150 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
7151 | pause_result |= (lp_pause & | |
7152 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
7153 | ||
7154 | bnx2x_pause_resolve(vars, pause_result); | |
7155 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
7156 | pause_result); | |
7157 | } | |
7158 | } | |
fcf5b650 YR |
7159 | static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
7160 | struct bnx2x_phy *phy, | |
7161 | u8 port) | |
de6eae1f | 7162 | { |
5c99274b YR |
7163 | u32 count = 0; |
7164 | u16 fw_ver1, fw_msgout; | |
fcf5b650 | 7165 | int rc = 0; |
5c99274b | 7166 | |
de6eae1f YR |
7167 | /* Boot port from external ROM */ |
7168 | /* EDC grst */ | |
7169 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7170 | MDIO_PMA_DEVAD, |
7171 | MDIO_PMA_REG_GEN_CTRL, | |
7172 | 0x0001); | |
de6eae1f | 7173 | |
d231023e | 7174 | /* Ucode reboot and rst */ |
de6eae1f | 7175 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
7176 | MDIO_PMA_DEVAD, |
7177 | MDIO_PMA_REG_GEN_CTRL, | |
7178 | 0x008c); | |
de6eae1f YR |
7179 | |
7180 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7181 | MDIO_PMA_DEVAD, |
7182 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
de6eae1f YR |
7183 | |
7184 | /* Reset internal microprocessor */ | |
7185 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7186 | MDIO_PMA_DEVAD, |
7187 | MDIO_PMA_REG_GEN_CTRL, | |
7188 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
de6eae1f YR |
7189 | |
7190 | /* Release srst bit */ | |
7191 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7192 | MDIO_PMA_DEVAD, |
7193 | MDIO_PMA_REG_GEN_CTRL, | |
7194 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 7195 | |
5c99274b YR |
7196 | /* Delay 100ms per the PHY specifications */ |
7197 | msleep(100); | |
7198 | ||
7199 | /* 8073 sometimes taking longer to download */ | |
7200 | do { | |
7201 | count++; | |
7202 | if (count > 300) { | |
7203 | DP(NETIF_MSG_LINK, | |
7204 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7205 | "Download failed. fw version = 0x%x\n", | |
7206 | port, fw_ver1); | |
7207 | rc = -EINVAL; | |
7208 | break; | |
7209 | } | |
7210 | ||
7211 | bnx2x_cl45_read(bp, phy, | |
7212 | MDIO_PMA_DEVAD, | |
7213 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
7214 | bnx2x_cl45_read(bp, phy, | |
7215 | MDIO_PMA_DEVAD, | |
7216 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
7217 | ||
d231023e | 7218 | usleep_range(1000, 2000); |
5c99274b YR |
7219 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || |
7220 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
7221 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | |
de6eae1f YR |
7222 | |
7223 | /* Clear ser_boot_ctl bit */ | |
7224 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
7225 | MDIO_PMA_DEVAD, |
7226 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f | 7227 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
5c99274b YR |
7228 | |
7229 | DP(NETIF_MSG_LINK, | |
7230 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
7231 | "Download complete. fw version = 0x%x\n", | |
7232 | port, fw_ver1); | |
7233 | ||
7234 | return rc; | |
de6eae1f YR |
7235 | } |
7236 | ||
de6eae1f YR |
7237 | /******************************************************************/ |
7238 | /* BCM8073 PHY SECTION */ | |
7239 | /******************************************************************/ | |
fcf5b650 | 7240 | static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7241 | { |
7242 | /* This is only required for 8073A1, version 102 only */ | |
7243 | u16 val; | |
7244 | ||
7245 | /* Read 8073 HW revision*/ | |
7246 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7247 | MDIO_PMA_DEVAD, |
7248 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7249 | |
7250 | if (val != 1) { | |
7251 | /* No need to workaround in 8073 A1 */ | |
7252 | return 0; | |
7253 | } | |
7254 | ||
7255 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7256 | MDIO_PMA_DEVAD, |
7257 | MDIO_PMA_REG_ROM_VER2, &val); | |
de6eae1f YR |
7258 | |
7259 | /* SNR should be applied only for version 0x102 */ | |
7260 | if (val != 0x102) | |
7261 | return 0; | |
7262 | ||
7263 | return 1; | |
7264 | } | |
7265 | ||
fcf5b650 | 7266 | static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) |
de6eae1f YR |
7267 | { |
7268 | u16 val, cnt, cnt1 ; | |
7269 | ||
7270 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7271 | MDIO_PMA_DEVAD, |
7272 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
7273 | |
7274 | if (val > 0) { | |
7275 | /* No need to workaround in 8073 A1 */ | |
7276 | return 0; | |
7277 | } | |
7278 | /* XAUI workaround in 8073 A0: */ | |
7279 | ||
8f73f0b9 | 7280 | /* After loading the boot ROM and restarting Autoneg, poll |
2cf7acf9 YR |
7281 | * Dev1, Reg $C820: |
7282 | */ | |
de6eae1f YR |
7283 | |
7284 | for (cnt = 0; cnt < 1000; cnt++) { | |
7285 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7286 | MDIO_PMA_DEVAD, |
7287 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7288 | &val); | |
8f73f0b9 | 7289 | /* If bit [14] = 0 or bit [13] = 0, continue on with |
2cf7acf9 YR |
7290 | * system initialization (XAUI work-around not required, as |
7291 | * these bits indicate 2.5G or 1G link up). | |
7292 | */ | |
de6eae1f YR |
7293 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
7294 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
7295 | return 0; | |
7296 | } else if (!(val & (1<<15))) { | |
2cf7acf9 | 7297 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
8f73f0b9 | 7298 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's |
2cf7acf9 YR |
7299 | * MSB (bit15) goes to 1 (indicating that the XAUI |
7300 | * workaround has completed), then continue on with | |
7301 | * system initialization. | |
7302 | */ | |
de6eae1f YR |
7303 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
7304 | bnx2x_cl45_read(bp, phy, | |
7305 | MDIO_PMA_DEVAD, | |
7306 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
7307 | if (val & (1<<15)) { | |
7308 | DP(NETIF_MSG_LINK, | |
7309 | "XAUI workaround has completed\n"); | |
7310 | return 0; | |
7311 | } | |
d231023e | 7312 | usleep_range(3000, 6000); |
de6eae1f YR |
7313 | } |
7314 | break; | |
7315 | } | |
d231023e | 7316 | usleep_range(3000, 6000); |
de6eae1f YR |
7317 | } |
7318 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
7319 | return -EINVAL; | |
7320 | } | |
7321 | ||
7322 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
7323 | { | |
7324 | /* Force KR or KX */ | |
7325 | bnx2x_cl45_write(bp, phy, | |
7326 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
7327 | bnx2x_cl45_write(bp, phy, | |
7328 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
7329 | bnx2x_cl45_write(bp, phy, | |
7330 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
7331 | bnx2x_cl45_write(bp, phy, | |
7332 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
7333 | } | |
7334 | ||
6bbca910 | 7335 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
7336 | struct bnx2x_phy *phy, |
7337 | struct link_vars *vars) | |
ea4e040a | 7338 | { |
6bbca910 | 7339 | u16 cl37_val; |
e10bc84d YR |
7340 | struct bnx2x *bp = params->bp; |
7341 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 7342 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
7343 | |
7344 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7345 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 7346 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
7347 | if ((vars->ieee_fc & |
7348 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
7349 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
7350 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
7351 | } | |
7352 | if ((vars->ieee_fc & | |
7353 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
7354 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
7355 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
7356 | } | |
7357 | if ((vars->ieee_fc & | |
7358 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
7359 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
7360 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
7361 | } | |
7362 | DP(NETIF_MSG_LINK, | |
7363 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
7364 | ||
e10bc84d | 7365 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 7366 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 7367 | msleep(500); |
ea4e040a YR |
7368 | } |
7369 | ||
5c107fda YR |
7370 | static void bnx2x_8073_specific_func(struct bnx2x_phy *phy, |
7371 | struct link_params *params, | |
7372 | u32 action) | |
7373 | { | |
7374 | struct bnx2x *bp = params->bp; | |
7375 | switch (action) { | |
7376 | case PHY_INIT: | |
7377 | /* Enable LASI */ | |
7378 | bnx2x_cl45_write(bp, phy, | |
7379 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); | |
7380 | bnx2x_cl45_write(bp, phy, | |
7381 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); | |
7382 | break; | |
7383 | } | |
7384 | } | |
7385 | ||
fcf5b650 YR |
7386 | static int bnx2x_8073_config_init(struct bnx2x_phy *phy, |
7387 | struct link_params *params, | |
7388 | struct link_vars *vars) | |
ea4e040a | 7389 | { |
e10bc84d | 7390 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
7391 | u16 val = 0, tmp1; |
7392 | u8 gpio_port; | |
7393 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 7394 | |
f2e0899f DK |
7395 | if (CHIP_IS_E2(bp)) |
7396 | gpio_port = BP_PATH(bp); | |
7397 | else | |
7398 | gpio_port = params->port; | |
de6eae1f YR |
7399 | /* Restore normal power mode*/ |
7400 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7401 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
e10bc84d | 7402 | |
de6eae1f | 7403 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 7404 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
ea4e040a | 7405 | |
5c107fda | 7406 | bnx2x_8073_specific_func(phy, params, PHY_INIT); |
de6eae1f | 7407 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 7408 | |
e10bc84d | 7409 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 7410 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 7411 | |
de6eae1f | 7412 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7413 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
2f904460 | 7414 | |
de6eae1f | 7415 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 7416 | |
74d7a119 YR |
7417 | /* Swap polarity if required - Must be done only in non-1G mode */ |
7418 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7419 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
7420 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); | |
7421 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
7422 | bnx2x_cl45_read(bp, phy, | |
7423 | MDIO_PMA_DEVAD, | |
7424 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
7425 | bnx2x_cl45_write(bp, phy, | |
7426 | MDIO_PMA_DEVAD, | |
7427 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
7428 | (val | (3<<9))); | |
7429 | } | |
7430 | ||
7431 | ||
de6eae1f | 7432 | /* Enable CL37 BAM */ |
121839be YR |
7433 | if (REG_RD(bp, params->shmem_base + |
7434 | offsetof(struct shmem_region, dev_info. | |
7435 | port_hw_config[params->port].default_cfg)) & | |
7436 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
57963ed9 | 7437 | |
121839be YR |
7438 | bnx2x_cl45_read(bp, phy, |
7439 | MDIO_AN_DEVAD, | |
7440 | MDIO_AN_REG_8073_BAM, &val); | |
7441 | bnx2x_cl45_write(bp, phy, | |
7442 | MDIO_AN_DEVAD, | |
7443 | MDIO_AN_REG_8073_BAM, val | 1); | |
7444 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
7445 | } | |
de6eae1f YR |
7446 | if (params->loopback_mode == LOOPBACK_EXT) { |
7447 | bnx2x_807x_force_10G(bp, phy); | |
7448 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
7449 | return 0; | |
7450 | } else { | |
7451 | bnx2x_cl45_write(bp, phy, | |
7452 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
7453 | } | |
7454 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
7455 | if (phy->req_line_speed == SPEED_10000) { | |
7456 | val = (1<<7); | |
7457 | } else if (phy->req_line_speed == SPEED_2500) { | |
7458 | val = (1<<5); | |
8f73f0b9 | 7459 | /* Note that 2.5G works only when used with 1G |
25985edc | 7460 | * advertisement |
2cf7acf9 | 7461 | */ |
de6eae1f YR |
7462 | } else |
7463 | val = (1<<5); | |
7464 | } else { | |
7465 | val = 0; | |
7466 | if (phy->speed_cap_mask & | |
7467 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
7468 | val |= (1<<7); | |
57963ed9 | 7469 | |
25985edc | 7470 | /* Note that 2.5G works only when used with 1G advertisement */ |
de6eae1f YR |
7471 | if (phy->speed_cap_mask & |
7472 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
7473 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
7474 | val |= (1<<5); | |
7475 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
7476 | } | |
57963ed9 | 7477 | |
de6eae1f YR |
7478 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
7479 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 7480 | |
de6eae1f YR |
7481 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
7482 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
7483 | (phy->req_line_speed == SPEED_2500)) { | |
7484 | u16 phy_ver; | |
7485 | /* Allow 2.5G for A1 and above */ | |
7486 | bnx2x_cl45_read(bp, phy, | |
7487 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
7488 | &phy_ver); | |
7489 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
7490 | if (phy_ver > 0) | |
7491 | tmp1 |= 1; | |
7492 | else | |
7493 | tmp1 &= 0xfffe; | |
7494 | } else { | |
7495 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
7496 | tmp1 &= 0xfffe; | |
7497 | } | |
57963ed9 | 7498 | |
de6eae1f YR |
7499 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
7500 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 7501 | |
de6eae1f YR |
7502 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
7503 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
7504 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
7505 | 0x20 : 0x40))); | |
57963ed9 | 7506 | |
de6eae1f YR |
7507 | /* Add support for CL37 (passive mode) III */ |
7508 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 7509 | |
8f73f0b9 | 7510 | /* The SNR will improve about 2db by changing BW and FEE main |
2cf7acf9 YR |
7511 | * tap. Rest commands are executed after link is up |
7512 | * Change FFE main cursor to 5 in EDC register | |
7513 | */ | |
de6eae1f YR |
7514 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
7515 | bnx2x_cl45_write(bp, phy, | |
7516 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
7517 | 0xFB0C); | |
57963ed9 | 7518 | |
de6eae1f YR |
7519 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
7520 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
7521 | tmp1 |= (1<<15); | |
7522 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 7523 | |
de6eae1f | 7524 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 7525 | |
de6eae1f YR |
7526 | /* Restart autoneg */ |
7527 | msleep(500); | |
7528 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
7529 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
7530 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
7531 | return 0; | |
b7737c9b | 7532 | } |
ea4e040a | 7533 | |
de6eae1f | 7534 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
7535 | struct link_params *params, |
7536 | struct link_vars *vars) | |
7537 | { | |
7538 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7539 | u8 link_up = 0; |
7540 | u16 val1, val2; | |
7541 | u16 link_status = 0; | |
7542 | u16 an1000_status = 0; | |
a35da8db | 7543 | |
de6eae1f | 7544 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 7545 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
b7737c9b | 7546 | |
de6eae1f | 7547 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 7548 | |
d231023e | 7549 | /* Clear the interrupt LASI status register */ |
de6eae1f YR |
7550 | bnx2x_cl45_read(bp, phy, |
7551 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7552 | bnx2x_cl45_read(bp, phy, | |
7553 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
7554 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
7555 | /* Clear MSG-OUT */ | |
7556 | bnx2x_cl45_read(bp, phy, | |
7557 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
7558 | ||
7559 | /* Check the LASI */ | |
7560 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 7561 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
de6eae1f YR |
7562 | |
7563 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
7564 | ||
7565 | /* Check the link status */ | |
7566 | bnx2x_cl45_read(bp, phy, | |
7567 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
7568 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
7569 | ||
7570 | bnx2x_cl45_read(bp, phy, | |
7571 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7572 | bnx2x_cl45_read(bp, phy, | |
7573 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7574 | link_up = ((val1 & 4) == 4); | |
7575 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
7576 | ||
7577 | if (link_up && | |
7578 | ((phy->req_line_speed != SPEED_10000))) { | |
7579 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
7580 | return 0; | |
62b29a5d | 7581 | } |
de6eae1f YR |
7582 | bnx2x_cl45_read(bp, phy, |
7583 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
7584 | bnx2x_cl45_read(bp, phy, | |
7585 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 7586 | |
de6eae1f YR |
7587 | /* Check the link status on 1.1.2 */ |
7588 | bnx2x_cl45_read(bp, phy, | |
7589 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
7590 | bnx2x_cl45_read(bp, phy, | |
7591 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
7592 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
7593 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 7594 | |
de6eae1f YR |
7595 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
7596 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
8f73f0b9 | 7597 | /* The SNR will improve about 2dbby changing the BW and FEE main |
2cf7acf9 YR |
7598 | * tap. The 1st write to change FFE main tap is set before |
7599 | * restart AN. Change PLL Bandwidth in EDC register | |
7600 | */ | |
62b29a5d | 7601 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7602 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
7603 | 0x26BC); | |
62b29a5d | 7604 | |
de6eae1f | 7605 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 7606 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
7607 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
7608 | 0x0333); | |
7609 | } | |
7610 | bnx2x_cl45_read(bp, phy, | |
7611 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
7612 | &link_status); | |
62b29a5d | 7613 | |
de6eae1f YR |
7614 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
7615 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
7616 | link_up = 1; | |
7617 | vars->line_speed = SPEED_10000; | |
7618 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
7619 | params->port); | |
7620 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
7621 | link_up = 1; | |
7622 | vars->line_speed = SPEED_2500; | |
7623 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
7624 | params->port); | |
7625 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
7626 | link_up = 1; | |
7627 | vars->line_speed = SPEED_1000; | |
7628 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
7629 | params->port); | |
7630 | } else { | |
7631 | link_up = 0; | |
7632 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
7633 | params->port); | |
62b29a5d | 7634 | } |
de6eae1f YR |
7635 | |
7636 | if (link_up) { | |
74d7a119 YR |
7637 | /* Swap polarity if required */ |
7638 | if (params->lane_config & | |
7639 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
7640 | /* Configure the 8073 to swap P and N of the KR lines */ | |
7641 | bnx2x_cl45_read(bp, phy, | |
7642 | MDIO_XS_DEVAD, | |
7643 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
8f73f0b9 | 7644 | /* Set bit 3 to invert Rx in 1G mode and clear this bit |
2cf7acf9 YR |
7645 | * when it`s in 10G mode. |
7646 | */ | |
74d7a119 YR |
7647 | if (vars->line_speed == SPEED_1000) { |
7648 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" | |
7649 | "the 8073\n"); | |
7650 | val1 |= (1<<3); | |
7651 | } else | |
7652 | val1 &= ~(1<<3); | |
7653 | ||
7654 | bnx2x_cl45_write(bp, phy, | |
7655 | MDIO_XS_DEVAD, | |
7656 | MDIO_XS_REG_8073_RX_CTRL_PCIE, | |
7657 | val1); | |
7658 | } | |
de6eae1f YR |
7659 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
7660 | bnx2x_8073_resolve_fc(phy, params, vars); | |
791f18c0 | 7661 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 7662 | } |
9e7e8399 MY |
7663 | |
7664 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
7665 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
7666 | MDIO_AN_REG_LP_AUTO_NEG2, &val1); | |
7667 | ||
7668 | if (val1 & (1<<5)) | |
7669 | vars->link_status |= | |
7670 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
7671 | if (val1 & (1<<7)) | |
7672 | vars->link_status |= | |
7673 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
7674 | } | |
7675 | ||
de6eae1f | 7676 | return link_up; |
b7737c9b YR |
7677 | } |
7678 | ||
de6eae1f YR |
7679 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
7680 | struct link_params *params) | |
7681 | { | |
7682 | struct bnx2x *bp = params->bp; | |
7683 | u8 gpio_port; | |
f2e0899f DK |
7684 | if (CHIP_IS_E2(bp)) |
7685 | gpio_port = BP_PATH(bp); | |
7686 | else | |
7687 | gpio_port = params->port; | |
de6eae1f YR |
7688 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
7689 | gpio_port); | |
7690 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
7691 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
7692 | gpio_port); | |
de6eae1f YR |
7693 | } |
7694 | ||
7695 | /******************************************************************/ | |
7696 | /* BCM8705 PHY SECTION */ | |
7697 | /******************************************************************/ | |
fcf5b650 YR |
7698 | static int bnx2x_8705_config_init(struct bnx2x_phy *phy, |
7699 | struct link_params *params, | |
7700 | struct link_vars *vars) | |
b7737c9b YR |
7701 | { |
7702 | struct bnx2x *bp = params->bp; | |
de6eae1f | 7703 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
7704 | /* Restore normal power mode*/ |
7705 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7706 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
7707 | /* HW reset */ |
7708 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
7709 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 7710 | bnx2x_wait_reset_complete(bp, phy, params); |
b7737c9b | 7711 | |
de6eae1f YR |
7712 | bnx2x_cl45_write(bp, phy, |
7713 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
7714 | bnx2x_cl45_write(bp, phy, | |
7715 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
7716 | bnx2x_cl45_write(bp, phy, | |
7717 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
7718 | bnx2x_cl45_write(bp, phy, | |
7719 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
7720 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
7721 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
7722 | return 0; | |
7723 | } | |
4d295db0 | 7724 | |
de6eae1f YR |
7725 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
7726 | struct link_params *params, | |
7727 | struct link_vars *vars) | |
7728 | { | |
7729 | u8 link_up = 0; | |
7730 | u16 val1, rx_sd; | |
7731 | struct bnx2x *bp = params->bp; | |
7732 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
7733 | bnx2x_cl45_read(bp, phy, | |
7734 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7735 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7736 | |
de6eae1f YR |
7737 | bnx2x_cl45_read(bp, phy, |
7738 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
7739 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 7740 | |
de6eae1f YR |
7741 | bnx2x_cl45_read(bp, phy, |
7742 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 7743 | |
de6eae1f YR |
7744 | bnx2x_cl45_read(bp, phy, |
7745 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
7746 | bnx2x_cl45_read(bp, phy, | |
7747 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 7748 | |
de6eae1f YR |
7749 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
7750 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
7751 | if (link_up) { | |
7752 | vars->line_speed = SPEED_10000; | |
7753 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 7754 | } |
de6eae1f YR |
7755 | return link_up; |
7756 | } | |
d90d96ba | 7757 | |
de6eae1f YR |
7758 | /******************************************************************/ |
7759 | /* SFP+ module Section */ | |
7760 | /******************************************************************/ | |
85242eea YR |
7761 | static void bnx2x_set_disable_pmd_transmit(struct link_params *params, |
7762 | struct bnx2x_phy *phy, | |
7763 | u8 pmd_dis) | |
7764 | { | |
7765 | struct bnx2x *bp = params->bp; | |
8f73f0b9 | 7766 | /* Disable transmitter only for bootcodes which can enable it afterwards |
85242eea YR |
7767 | * (for D3 link) |
7768 | */ | |
7769 | if (pmd_dis) { | |
7770 | if (params->feature_config_flags & | |
7771 | FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) | |
7772 | DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n"); | |
7773 | else { | |
7774 | DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n"); | |
7775 | return; | |
7776 | } | |
7777 | } else | |
7778 | DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n"); | |
7779 | bnx2x_cl45_write(bp, phy, | |
7780 | MDIO_PMA_DEVAD, | |
7781 | MDIO_PMA_REG_TX_DISABLE, pmd_dis); | |
7782 | } | |
7783 | ||
a8db5b4c YR |
7784 | static u8 bnx2x_get_gpio_port(struct link_params *params) |
7785 | { | |
7786 | u8 gpio_port; | |
7787 | u32 swap_val, swap_override; | |
7788 | struct bnx2x *bp = params->bp; | |
7789 | if (CHIP_IS_E2(bp)) | |
7790 | gpio_port = BP_PATH(bp); | |
7791 | else | |
7792 | gpio_port = params->port; | |
7793 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
7794 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7795 | return gpio_port ^ (swap_val && swap_override); | |
7796 | } | |
3c9ada22 YR |
7797 | |
7798 | static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params, | |
7799 | struct bnx2x_phy *phy, | |
7800 | u8 tx_en) | |
de6eae1f YR |
7801 | { |
7802 | u16 val; | |
a8db5b4c YR |
7803 | u8 port = params->port; |
7804 | struct bnx2x *bp = params->bp; | |
7805 | u32 tx_en_mode; | |
d90d96ba | 7806 | |
de6eae1f | 7807 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ |
a8db5b4c YR |
7808 | tx_en_mode = REG_RD(bp, params->shmem_base + |
7809 | offsetof(struct shmem_region, | |
7810 | dev_info.port_hw_config[port].sfp_ctrl)) & | |
7811 | PORT_HW_CFG_TX_LASER_MASK; | |
7812 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x " | |
7813 | "mode = %x\n", tx_en, port, tx_en_mode); | |
7814 | switch (tx_en_mode) { | |
7815 | case PORT_HW_CFG_TX_LASER_MDIO: | |
d90d96ba | 7816 | |
a8db5b4c YR |
7817 | bnx2x_cl45_read(bp, phy, |
7818 | MDIO_PMA_DEVAD, | |
7819 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7820 | &val); | |
b7737c9b | 7821 | |
a8db5b4c YR |
7822 | if (tx_en) |
7823 | val &= ~(1<<15); | |
7824 | else | |
7825 | val |= (1<<15); | |
7826 | ||
7827 | bnx2x_cl45_write(bp, phy, | |
7828 | MDIO_PMA_DEVAD, | |
7829 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
7830 | val); | |
7831 | break; | |
7832 | case PORT_HW_CFG_TX_LASER_GPIO0: | |
7833 | case PORT_HW_CFG_TX_LASER_GPIO1: | |
7834 | case PORT_HW_CFG_TX_LASER_GPIO2: | |
7835 | case PORT_HW_CFG_TX_LASER_GPIO3: | |
7836 | { | |
7837 | u16 gpio_pin; | |
7838 | u8 gpio_port, gpio_mode; | |
7839 | if (tx_en) | |
7840 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; | |
7841 | else | |
7842 | gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; | |
7843 | ||
7844 | gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; | |
7845 | gpio_port = bnx2x_get_gpio_port(params); | |
7846 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
7847 | break; | |
7848 | } | |
7849 | default: | |
7850 | DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); | |
7851 | break; | |
7852 | } | |
b7737c9b YR |
7853 | } |
7854 | ||
3c9ada22 YR |
7855 | static void bnx2x_sfp_set_transmitter(struct link_params *params, |
7856 | struct bnx2x_phy *phy, | |
7857 | u8 tx_en) | |
7858 | { | |
7859 | struct bnx2x *bp = params->bp; | |
7860 | DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en); | |
7861 | if (CHIP_IS_E3(bp)) | |
7862 | bnx2x_sfp_e3_set_transmitter(params, phy, tx_en); | |
7863 | else | |
7864 | bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en); | |
7865 | } | |
7866 | ||
fcf5b650 YR |
7867 | static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7868 | struct link_params *params, | |
7869 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b YR |
7870 | { |
7871 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
7872 | u16 val = 0; |
7873 | u16 i; | |
24ea818e | 7874 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
7875 | DP(NETIF_MSG_LINK, |
7876 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
7877 | return -EINVAL; |
7878 | } | |
7879 | /* Set the read command byte count */ | |
62b29a5d | 7880 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7881 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
cd88ccee | 7882 | (byte_cnt | 0xa000)); |
ea4e040a | 7883 | |
de6eae1f YR |
7884 | /* Set the read command address */ |
7885 | bnx2x_cl45_write(bp, phy, | |
7886 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
cd88ccee | 7887 | addr); |
ea4e040a | 7888 | |
de6eae1f | 7889 | /* Activate read command */ |
62b29a5d | 7890 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 7891 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
cd88ccee | 7892 | 0x2c0f); |
ea4e040a | 7893 | |
de6eae1f YR |
7894 | /* Wait up to 500us for command complete status */ |
7895 | for (i = 0; i < 100; i++) { | |
7896 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7897 | MDIO_PMA_DEVAD, |
7898 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7899 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7900 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
7901 | break; | |
7902 | udelay(5); | |
62b29a5d | 7903 | } |
62b29a5d | 7904 | |
de6eae1f YR |
7905 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
7906 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
7907 | DP(NETIF_MSG_LINK, | |
7908 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
7909 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
7910 | return -EINVAL; | |
62b29a5d | 7911 | } |
e10bc84d | 7912 | |
de6eae1f YR |
7913 | /* Read the buffer */ |
7914 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 7915 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
7916 | MDIO_PMA_DEVAD, |
7917 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f | 7918 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
62b29a5d | 7919 | } |
6bbca910 | 7920 | |
de6eae1f YR |
7921 | for (i = 0; i < 100; i++) { |
7922 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
7923 | MDIO_PMA_DEVAD, |
7924 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
7925 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
7926 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 7927 | return 0; |
d231023e | 7928 | usleep_range(1000, 2000); |
de6eae1f YR |
7929 | } |
7930 | return -EINVAL; | |
b7737c9b | 7931 | } |
4d295db0 | 7932 | |
50a29845 YM |
7933 | static void bnx2x_warpcore_power_module(struct link_params *params, |
7934 | struct bnx2x_phy *phy, | |
7935 | u8 power) | |
7936 | { | |
7937 | u32 pin_cfg; | |
7938 | struct bnx2x *bp = params->bp; | |
7939 | ||
7940 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
7941 | offsetof(struct shmem_region, | |
7942 | dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & | |
7943 | PORT_HW_CFG_E3_PWR_DIS_MASK) >> | |
7944 | PORT_HW_CFG_E3_PWR_DIS_SHIFT; | |
7945 | ||
7946 | if (pin_cfg == PIN_CFG_NA) | |
7947 | return; | |
7948 | DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", | |
7949 | power, pin_cfg); | |
7950 | /* Low ==> corresponding SFP+ module is powered | |
7951 | * high ==> the SFP+ module is powered down | |
7952 | */ | |
7953 | bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); | |
7954 | } | |
3c9ada22 YR |
7955 | static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7956 | struct link_params *params, | |
7957 | u16 addr, u8 byte_cnt, | |
7958 | u8 *o_buf) | |
7959 | { | |
7960 | int rc = 0; | |
7961 | u8 i, j = 0, cnt = 0; | |
7962 | u32 data_array[4]; | |
7963 | u16 addr32; | |
7964 | struct bnx2x *bp = params->bp; | |
24ea818e YM |
7965 | |
7966 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { | |
94f05b0f JP |
7967 | DP(NETIF_MSG_LINK, |
7968 | "Reading from eeprom is limited to 16 bytes\n"); | |
3c9ada22 YR |
7969 | return -EINVAL; |
7970 | } | |
7971 | ||
7972 | /* 4 byte aligned address */ | |
7973 | addr32 = addr & (~0x3); | |
7974 | do { | |
50a29845 YM |
7975 | if (cnt == I2C_WA_PWR_ITER) { |
7976 | bnx2x_warpcore_power_module(params, phy, 0); | |
7977 | /* Note that 100us are not enough here */ | |
7978 | usleep_range(1000,1000); | |
7979 | bnx2x_warpcore_power_module(params, phy, 1); | |
7980 | } | |
3c9ada22 YR |
7981 | rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt, |
7982 | data_array); | |
7983 | } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); | |
7984 | ||
7985 | if (rc == 0) { | |
7986 | for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { | |
7987 | o_buf[j] = *((u8 *)data_array + i); | |
7988 | j++; | |
7989 | } | |
7990 | } | |
7991 | ||
7992 | return rc; | |
7993 | } | |
7994 | ||
fcf5b650 YR |
7995 | static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
7996 | struct link_params *params, | |
7997 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 7998 | { |
b7737c9b | 7999 | struct bnx2x *bp = params->bp; |
de6eae1f | 8000 | u16 val, i; |
ea4e040a | 8001 | |
24ea818e | 8002 | if (byte_cnt > SFP_EEPROM_PAGE_SIZE) { |
94f05b0f JP |
8003 | DP(NETIF_MSG_LINK, |
8004 | "Reading from eeprom is limited to 0xf\n"); | |
de6eae1f YR |
8005 | return -EINVAL; |
8006 | } | |
4d295db0 | 8007 | |
de6eae1f YR |
8008 | /* Need to read from 1.8000 to clear it */ |
8009 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
8010 | MDIO_PMA_DEVAD, |
8011 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
8012 | &val); | |
4d295db0 | 8013 | |
de6eae1f | 8014 | /* Set the read command byte count */ |
62b29a5d | 8015 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8016 | MDIO_PMA_DEVAD, |
8017 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
8018 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 8019 | |
de6eae1f | 8020 | /* Set the read command address */ |
62b29a5d | 8021 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8022 | MDIO_PMA_DEVAD, |
8023 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
8024 | addr); | |
de6eae1f | 8025 | /* Set the destination address */ |
62b29a5d | 8026 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8027 | MDIO_PMA_DEVAD, |
8028 | 0x8004, | |
8029 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 8030 | |
de6eae1f | 8031 | /* Activate read command */ |
62b29a5d | 8032 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8033 | MDIO_PMA_DEVAD, |
8034 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
8035 | 0x8002); | |
8f73f0b9 | 8036 | /* Wait appropriate time for two-wire command to finish before |
2cf7acf9 YR |
8037 | * polling the status register |
8038 | */ | |
d231023e | 8039 | usleep_range(1000, 2000); |
4d295db0 | 8040 | |
de6eae1f YR |
8041 | /* Wait up to 500us for command complete status */ |
8042 | for (i = 0; i < 100; i++) { | |
62b29a5d | 8043 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8044 | MDIO_PMA_DEVAD, |
8045 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
8046 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
8047 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
8048 | break; | |
8049 | udelay(5); | |
62b29a5d | 8050 | } |
4d295db0 | 8051 | |
de6eae1f YR |
8052 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
8053 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
8054 | DP(NETIF_MSG_LINK, | |
8055 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
8056 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
65a001ba | 8057 | return -EFAULT; |
de6eae1f | 8058 | } |
62b29a5d | 8059 | |
de6eae1f YR |
8060 | /* Read the buffer */ |
8061 | for (i = 0; i < byte_cnt; i++) { | |
8062 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
8063 | MDIO_PMA_DEVAD, |
8064 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f YR |
8065 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
8066 | } | |
4d295db0 | 8067 | |
de6eae1f YR |
8068 | for (i = 0; i < 100; i++) { |
8069 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
8070 | MDIO_PMA_DEVAD, |
8071 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
8072 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
8073 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 8074 | return 0; |
d231023e | 8075 | usleep_range(1000, 2000); |
62b29a5d YR |
8076 | } |
8077 | ||
de6eae1f | 8078 | return -EINVAL; |
b7737c9b YR |
8079 | } |
8080 | ||
fcf5b650 YR |
8081 | int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
8082 | struct link_params *params, u16 addr, | |
8083 | u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 8084 | { |
24ea818e | 8085 | int rc = -EOPNOTSUPP; |
e4d78f12 YR |
8086 | switch (phy->type) { |
8087 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
8088 | rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | |
8089 | byte_cnt, o_buf); | |
8090 | break; | |
8091 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8092 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8093 | rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | |
8094 | byte_cnt, o_buf); | |
8095 | break; | |
3c9ada22 YR |
8096 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8097 | rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr, | |
8098 | byte_cnt, o_buf); | |
8099 | break; | |
e4d78f12 YR |
8100 | } |
8101 | return rc; | |
b7737c9b YR |
8102 | } |
8103 | ||
fcf5b650 YR |
8104 | static int bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
8105 | struct link_params *params, | |
8106 | u16 *edc_mode) | |
b7737c9b YR |
8107 | { |
8108 | struct bnx2x *bp = params->bp; | |
1ac9e428 | 8109 | u32 sync_offset = 0, phy_idx, media_types; |
dbef807e | 8110 | u8 val[2], check_limiting_mode = 0; |
de6eae1f | 8111 | *edc_mode = EDC_MODE_LIMITING; |
62b29a5d | 8112 | |
1ac9e428 | 8113 | phy->media_type = ETH_PHY_UNSPECIFIED; |
de6eae1f YR |
8114 | /* First check for copper cable */ |
8115 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8116 | params, | |
8117 | SFP_EEPROM_CON_TYPE_ADDR, | |
dbef807e YM |
8118 | 2, |
8119 | (u8 *)val) != 0) { | |
de6eae1f YR |
8120 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); |
8121 | return -EINVAL; | |
8122 | } | |
a1e4be39 | 8123 | |
dbef807e | 8124 | switch (val[0]) { |
de6eae1f YR |
8125 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: |
8126 | { | |
8127 | u8 copper_module_type; | |
1ac9e428 | 8128 | phy->media_type = ETH_PHY_DA_TWINAX; |
8f73f0b9 | 8129 | /* Check if its active cable (includes SFP+ module) |
2cf7acf9 YR |
8130 | * of passive cable |
8131 | */ | |
de6eae1f YR |
8132 | if (bnx2x_read_sfp_module_eeprom(phy, |
8133 | params, | |
8134 | SFP_EEPROM_FC_TX_TECH_ADDR, | |
8135 | 1, | |
9045f6b4 | 8136 | &copper_module_type) != 0) { |
de6eae1f YR |
8137 | DP(NETIF_MSG_LINK, |
8138 | "Failed to read copper-cable-type" | |
8139 | " from SFP+ EEPROM\n"); | |
8140 | return -EINVAL; | |
8141 | } | |
4f60dab1 | 8142 | |
de6eae1f YR |
8143 | if (copper_module_type & |
8144 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
8145 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
8146 | check_limiting_mode = 1; | |
8147 | } else if (copper_module_type & | |
8148 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
94f05b0f JP |
8149 | DP(NETIF_MSG_LINK, |
8150 | "Passive Copper cable detected\n"); | |
de6eae1f YR |
8151 | *edc_mode = |
8152 | EDC_MODE_PASSIVE_DAC; | |
8153 | } else { | |
94f05b0f JP |
8154 | DP(NETIF_MSG_LINK, |
8155 | "Unknown copper-cable-type 0x%x !!!\n", | |
8156 | copper_module_type); | |
de6eae1f YR |
8157 | return -EINVAL; |
8158 | } | |
8159 | break; | |
62b29a5d | 8160 | } |
de6eae1f | 8161 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
de6eae1f | 8162 | check_limiting_mode = 1; |
dbef807e YM |
8163 | if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK | |
8164 | SFP_EEPROM_COMP_CODE_LR_MASK | | |
8165 | SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { | |
8166 | DP(NETIF_MSG_LINK, "1G Optic module detected\n"); | |
8167 | phy->media_type = ETH_PHY_SFP_1G_FIBER; | |
8168 | phy->req_line_speed = SPEED_1000; | |
8169 | } else { | |
8170 | int idx, cfg_idx = 0; | |
8171 | DP(NETIF_MSG_LINK, "10G Optic module detected\n"); | |
8172 | for (idx = INT_PHY; idx < MAX_PHYS; idx++) { | |
8173 | if (params->phy[idx].type == phy->type) { | |
8174 | cfg_idx = LINK_CONFIG_IDX(idx); | |
8175 | break; | |
8176 | } | |
8177 | } | |
8178 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; | |
8179 | phy->req_line_speed = params->req_line_speed[cfg_idx]; | |
8180 | } | |
de6eae1f YR |
8181 | break; |
8182 | default: | |
8183 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
dbef807e | 8184 | val[0]); |
de6eae1f | 8185 | return -EINVAL; |
62b29a5d | 8186 | } |
1ac9e428 YR |
8187 | sync_offset = params->shmem_base + |
8188 | offsetof(struct shmem_region, | |
8189 | dev_info.port_hw_config[params->port].media_type); | |
8190 | media_types = REG_RD(bp, sync_offset); | |
8191 | /* Update media type for non-PMF sync */ | |
8192 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { | |
8193 | if (&(params->phy[phy_idx]) == phy) { | |
8194 | media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
8195 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8196 | media_types |= ((phy->media_type & | |
8197 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
8198 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); | |
8199 | break; | |
8200 | } | |
8201 | } | |
8202 | REG_WR(bp, sync_offset, media_types); | |
de6eae1f YR |
8203 | if (check_limiting_mode) { |
8204 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
8205 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8206 | params, | |
8207 | SFP_EEPROM_OPTIONS_ADDR, | |
8208 | SFP_EEPROM_OPTIONS_SIZE, | |
8209 | options) != 0) { | |
94f05b0f JP |
8210 | DP(NETIF_MSG_LINK, |
8211 | "Failed to read Option field from module EEPROM\n"); | |
de6eae1f YR |
8212 | return -EINVAL; |
8213 | } | |
8214 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
8215 | *edc_mode = EDC_MODE_LINEAR; | |
8216 | else | |
8217 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 8218 | } |
de6eae1f | 8219 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 8220 | return 0; |
b7737c9b | 8221 | } |
8f73f0b9 | 8222 | /* This function read the relevant field from the module (SFP+), and verify it |
2cf7acf9 YR |
8223 | * is compliant with this board |
8224 | */ | |
fcf5b650 YR |
8225 | static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
8226 | struct link_params *params) | |
b7737c9b YR |
8227 | { |
8228 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
8229 | u32 val, cmd; |
8230 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
8231 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
8232 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 8233 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
8234 | val = REG_RD(bp, params->shmem_base + |
8235 | offsetof(struct shmem_region, dev_info. | |
8236 | port_feature_config[params->port].config)); | |
8237 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8238 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
8239 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
8240 | return 0; | |
8241 | } | |
ea4e040a | 8242 | |
a22f0788 YR |
8243 | if (params->feature_config_flags & |
8244 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
8245 | /* Use specific phy request */ | |
8246 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
8247 | } else if (params->feature_config_flags & | |
8248 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
8249 | /* Use first phy request only in case of non-dual media*/ | |
8250 | if (DUAL_MEDIA(params)) { | |
94f05b0f JP |
8251 | DP(NETIF_MSG_LINK, |
8252 | "FW does not support OPT MDL verification\n"); | |
a22f0788 YR |
8253 | return -EINVAL; |
8254 | } | |
8255 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
8256 | } else { | |
8257 | /* No support in OPT MDL detection */ | |
94f05b0f JP |
8258 | DP(NETIF_MSG_LINK, |
8259 | "FW does not support OPT MDL verification\n"); | |
de6eae1f YR |
8260 | return -EINVAL; |
8261 | } | |
523224a3 | 8262 | |
a22f0788 YR |
8263 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
8264 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
8265 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
8266 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
8267 | return 0; | |
8268 | } | |
b7737c9b | 8269 | |
d231023e | 8270 | /* Format the warning message */ |
de6eae1f YR |
8271 | if (bnx2x_read_sfp_module_eeprom(phy, |
8272 | params, | |
cd88ccee YR |
8273 | SFP_EEPROM_VENDOR_NAME_ADDR, |
8274 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
8275 | (u8 *)vendor_name)) | |
de6eae1f YR |
8276 | vendor_name[0] = '\0'; |
8277 | else | |
8278 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
8279 | if (bnx2x_read_sfp_module_eeprom(phy, | |
8280 | params, | |
cd88ccee YR |
8281 | SFP_EEPROM_PART_NO_ADDR, |
8282 | SFP_EEPROM_PART_NO_SIZE, | |
8283 | (u8 *)vendor_pn)) | |
de6eae1f YR |
8284 | vendor_pn[0] = '\0'; |
8285 | else | |
8286 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
8287 | ||
6d870c39 YR |
8288 | netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," |
8289 | " Port %d from %s part number %s\n", | |
8290 | params->port, vendor_name, vendor_pn); | |
59a2e53b YR |
8291 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != |
8292 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) | |
8293 | phy->flags |= FLAGS_SFP_NOT_APPROVED; | |
de6eae1f | 8294 | return -EINVAL; |
b7737c9b | 8295 | } |
7aa0711f | 8296 | |
fcf5b650 YR |
8297 | static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
8298 | struct link_params *params) | |
7aa0711f | 8299 | |
4d295db0 | 8300 | { |
de6eae1f | 8301 | u8 val; |
4d295db0 | 8302 | struct bnx2x *bp = params->bp; |
de6eae1f | 8303 | u16 timeout; |
8f73f0b9 | 8304 | /* Initialization time after hot-plug may take up to 300ms for |
2cf7acf9 YR |
8305 | * some phys type ( e.g. JDSU ) |
8306 | */ | |
8307 | ||
de6eae1f YR |
8308 | for (timeout = 0; timeout < 60; timeout++) { |
8309 | if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) | |
8310 | == 0) { | |
94f05b0f JP |
8311 | DP(NETIF_MSG_LINK, |
8312 | "SFP+ module initialization took %d ms\n", | |
8313 | timeout * 5); | |
de6eae1f YR |
8314 | return 0; |
8315 | } | |
d231023e | 8316 | usleep_range(5000, 10000); |
de6eae1f YR |
8317 | } |
8318 | return -EINVAL; | |
8319 | } | |
4d295db0 | 8320 | |
de6eae1f YR |
8321 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
8322 | struct bnx2x_phy *phy, | |
8323 | u8 is_power_up) { | |
8324 | /* Make sure GPIOs are not using for LED mode */ | |
8325 | u16 val; | |
8f73f0b9 | 8326 | /* In the GPIO register, bit 4 is use to determine if the GPIOs are |
de6eae1f YR |
8327 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
8328 | * output | |
3c9ada22 YR |
8329 | * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 |
8330 | * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 | |
de6eae1f YR |
8331 | * where the 1st bit is the over-current(only input), and 2nd bit is |
8332 | * for power( only output ) | |
2cf7acf9 | 8333 | * |
de6eae1f YR |
8334 | * In case of NOC feature is disabled and power is up, set GPIO control |
8335 | * as input to enable listening of over-current indication | |
8336 | */ | |
8337 | if (phy->flags & FLAGS_NOC) | |
8338 | return; | |
27d02432 | 8339 | if (is_power_up) |
de6eae1f YR |
8340 | val = (1<<4); |
8341 | else | |
8f73f0b9 | 8342 | /* Set GPIO control to OUTPUT, and set the power bit |
de6eae1f YR |
8343 | * to according to the is_power_up |
8344 | */ | |
27d02432 | 8345 | val = (1<<1); |
4d295db0 | 8346 | |
de6eae1f YR |
8347 | bnx2x_cl45_write(bp, phy, |
8348 | MDIO_PMA_DEVAD, | |
8349 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
8350 | val); | |
8351 | } | |
4d295db0 | 8352 | |
fcf5b650 YR |
8353 | static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
8354 | struct bnx2x_phy *phy, | |
8355 | u16 edc_mode) | |
de6eae1f YR |
8356 | { |
8357 | u16 cur_limiting_mode; | |
4d295db0 | 8358 | |
de6eae1f | 8359 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8360 | MDIO_PMA_DEVAD, |
8361 | MDIO_PMA_REG_ROM_VER2, | |
8362 | &cur_limiting_mode); | |
de6eae1f YR |
8363 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
8364 | cur_limiting_mode); | |
8365 | ||
8366 | if (edc_mode == EDC_MODE_LIMITING) { | |
cd88ccee | 8367 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
e10bc84d | 8368 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 8369 | MDIO_PMA_DEVAD, |
de6eae1f YR |
8370 | MDIO_PMA_REG_ROM_VER2, |
8371 | EDC_MODE_LIMITING); | |
8372 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 8373 | |
de6eae1f | 8374 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 8375 | |
8f73f0b9 | 8376 | /* Changing to LRM mode takes quite few seconds. So do it only |
2cf7acf9 YR |
8377 | * if current mode is limiting (default is LRM) |
8378 | */ | |
de6eae1f YR |
8379 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
8380 | return 0; | |
4d295db0 | 8381 | |
de6eae1f | 8382 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8383 | MDIO_PMA_DEVAD, |
8384 | MDIO_PMA_REG_LRM_MODE, | |
8385 | 0); | |
de6eae1f | 8386 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8387 | MDIO_PMA_DEVAD, |
8388 | MDIO_PMA_REG_ROM_VER2, | |
8389 | 0x128); | |
de6eae1f | 8390 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8391 | MDIO_PMA_DEVAD, |
8392 | MDIO_PMA_REG_MISC_CTRL0, | |
8393 | 0x4008); | |
de6eae1f | 8394 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8395 | MDIO_PMA_DEVAD, |
8396 | MDIO_PMA_REG_LRM_MODE, | |
8397 | 0xaaaa); | |
4d295db0 | 8398 | } |
de6eae1f | 8399 | return 0; |
4d295db0 EG |
8400 | } |
8401 | ||
fcf5b650 YR |
8402 | static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
8403 | struct bnx2x_phy *phy, | |
8404 | u16 edc_mode) | |
ea4e040a | 8405 | { |
de6eae1f YR |
8406 | u16 phy_identifier; |
8407 | u16 rom_ver2_val; | |
62b29a5d | 8408 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8409 | MDIO_PMA_DEVAD, |
8410 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8411 | &phy_identifier); | |
ea4e040a | 8412 | |
de6eae1f | 8413 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8414 | MDIO_PMA_DEVAD, |
8415 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8416 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 8417 | |
62b29a5d | 8418 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
8419 | MDIO_PMA_DEVAD, |
8420 | MDIO_PMA_REG_ROM_VER2, | |
8421 | &rom_ver2_val); | |
de6eae1f YR |
8422 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
8423 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8424 | MDIO_PMA_DEVAD, |
8425 | MDIO_PMA_REG_ROM_VER2, | |
8426 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 8427 | |
de6eae1f | 8428 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
8429 | MDIO_PMA_DEVAD, |
8430 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
8431 | (phy_identifier | (1<<9))); | |
4d295db0 | 8432 | |
de6eae1f | 8433 | return 0; |
b7737c9b | 8434 | } |
ea4e040a | 8435 | |
a22f0788 YR |
8436 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
8437 | struct link_params *params, | |
8438 | u32 action) | |
8439 | { | |
8440 | struct bnx2x *bp = params->bp; | |
5c107fda | 8441 | u16 val; |
a22f0788 YR |
8442 | switch (action) { |
8443 | case DISABLE_TX: | |
a8db5b4c | 8444 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 YR |
8445 | break; |
8446 | case ENABLE_TX: | |
8447 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
a8db5b4c | 8448 | bnx2x_sfp_set_transmitter(params, phy, 1); |
a22f0788 | 8449 | break; |
5c107fda YR |
8450 | case PHY_INIT: |
8451 | bnx2x_cl45_write(bp, phy, | |
8452 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, | |
8453 | (1<<2) | (1<<5)); | |
8454 | bnx2x_cl45_write(bp, phy, | |
8455 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, | |
8456 | 0); | |
8457 | bnx2x_cl45_write(bp, phy, | |
8458 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); | |
8459 | /* Make MOD_ABS give interrupt on change */ | |
8460 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
8461 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8462 | &val); | |
8463 | val |= (1<<12); | |
8464 | if (phy->flags & FLAGS_NOC) | |
8465 | val |= (3<<5); | |
8466 | /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 | |
8467 | * status which reflect SFP+ module over-current | |
8468 | */ | |
8469 | if (!(phy->flags & FLAGS_NOC)) | |
8470 | val &= 0xff8f; /* Reset bits 4-6 */ | |
8471 | bnx2x_cl45_write(bp, phy, | |
8472 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
8473 | val); | |
8474 | ||
8475 | /* Set 2-wire transfer rate of SFP+ module EEPROM | |
8476 | * to 100Khz since some DACs(direct attached cables) do | |
8477 | * not work at 400Khz. | |
8478 | */ | |
8479 | bnx2x_cl45_write(bp, phy, | |
8480 | MDIO_PMA_DEVAD, | |
8481 | MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
8482 | 0xa001); | |
8483 | break; | |
a22f0788 YR |
8484 | default: |
8485 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
8486 | action); | |
8487 | return; | |
8488 | } | |
8489 | } | |
8490 | ||
3c9ada22 | 8491 | static void bnx2x_set_e1e2_module_fault_led(struct link_params *params, |
a8db5b4c YR |
8492 | u8 gpio_mode) |
8493 | { | |
8494 | struct bnx2x *bp = params->bp; | |
8495 | ||
8496 | u32 fault_led_gpio = REG_RD(bp, params->shmem_base + | |
8497 | offsetof(struct shmem_region, | |
8498 | dev_info.port_hw_config[params->port].sfp_ctrl)) & | |
8499 | PORT_HW_CFG_FAULT_MODULE_LED_MASK; | |
8500 | switch (fault_led_gpio) { | |
8501 | case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: | |
8502 | return; | |
8503 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: | |
8504 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: | |
8505 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: | |
8506 | case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: | |
8507 | { | |
8508 | u8 gpio_port = bnx2x_get_gpio_port(params); | |
8509 | u16 gpio_pin = fault_led_gpio - | |
8510 | PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; | |
8511 | DP(NETIF_MSG_LINK, "Set fault module-detected led " | |
8512 | "pin %x port %x mode %x\n", | |
8513 | gpio_pin, gpio_port, gpio_mode); | |
8514 | bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); | |
8515 | } | |
8516 | break; | |
8517 | default: | |
8518 | DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", | |
8519 | fault_led_gpio); | |
8520 | } | |
8521 | } | |
8522 | ||
3c9ada22 YR |
8523 | static void bnx2x_set_e3_module_fault_led(struct link_params *params, |
8524 | u8 gpio_mode) | |
8525 | { | |
8526 | u32 pin_cfg; | |
8527 | u8 port = params->port; | |
8528 | struct bnx2x *bp = params->bp; | |
8529 | pin_cfg = (REG_RD(bp, params->shmem_base + | |
8530 | offsetof(struct shmem_region, | |
8531 | dev_info.port_hw_config[port].e3_sfp_ctrl)) & | |
8532 | PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> | |
8533 | PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; | |
8534 | DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n", | |
8535 | gpio_mode, pin_cfg); | |
8536 | bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); | |
8537 | } | |
8538 | ||
8539 | static void bnx2x_set_sfp_module_fault_led(struct link_params *params, | |
8540 | u8 gpio_mode) | |
8541 | { | |
8542 | struct bnx2x *bp = params->bp; | |
8543 | DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); | |
8544 | if (CHIP_IS_E3(bp)) { | |
8f73f0b9 | 8545 | /* Low ==> if SFP+ module is supported otherwise |
3c9ada22 YR |
8546 | * High ==> if SFP+ module is not on the approved vendor list |
8547 | */ | |
8548 | bnx2x_set_e3_module_fault_led(params, gpio_mode); | |
8549 | } else | |
8550 | bnx2x_set_e1e2_module_fault_led(params, gpio_mode); | |
8551 | } | |
8552 | ||
985848f8 YR |
8553 | static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy, |
8554 | struct link_params *params) | |
8555 | { | |
b76070b4 | 8556 | struct bnx2x *bp = params->bp; |
985848f8 | 8557 | bnx2x_warpcore_power_module(params, phy, 0); |
b76070b4 YR |
8558 | /* Put Warpcore in low power mode */ |
8559 | REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); | |
8560 | ||
8561 | /* Put LCPLL in low power mode */ | |
8562 | REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); | |
8563 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); | |
8564 | REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); | |
985848f8 YR |
8565 | } |
8566 | ||
e4d78f12 YR |
8567 | static void bnx2x_power_sfp_module(struct link_params *params, |
8568 | struct bnx2x_phy *phy, | |
8569 | u8 power) | |
8570 | { | |
8571 | struct bnx2x *bp = params->bp; | |
8572 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); | |
8573 | ||
8574 | switch (phy->type) { | |
8575 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8576 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8577 | bnx2x_8727_power_module(params->bp, phy, power); | |
8578 | break; | |
3c9ada22 YR |
8579 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8580 | bnx2x_warpcore_power_module(params, phy, power); | |
8581 | break; | |
8582 | default: | |
8583 | break; | |
8584 | } | |
8585 | } | |
8586 | static void bnx2x_warpcore_set_limiting_mode(struct link_params *params, | |
8587 | struct bnx2x_phy *phy, | |
8588 | u16 edc_mode) | |
8589 | { | |
8590 | u16 val = 0; | |
8591 | u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8592 | struct bnx2x *bp = params->bp; | |
8593 | ||
8594 | u8 lane = bnx2x_get_warpcore_lane(phy, params); | |
8595 | /* This is a global register which controls all lanes */ | |
8596 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8597 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8598 | val &= ~(0xf << (lane << 2)); | |
8599 | ||
8600 | switch (edc_mode) { | |
8601 | case EDC_MODE_LINEAR: | |
8602 | case EDC_MODE_LIMITING: | |
8603 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; | |
8604 | break; | |
8605 | case EDC_MODE_PASSIVE_DAC: | |
8606 | mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; | |
8607 | break; | |
e4d78f12 YR |
8608 | default: |
8609 | break; | |
8610 | } | |
3c9ada22 YR |
8611 | |
8612 | val |= (mode << (lane << 2)); | |
8613 | bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, | |
8614 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); | |
8615 | /* A must read */ | |
8616 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
8617 | MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); | |
8618 | ||
19af03a3 YR |
8619 | /* Restart microcode to re-read the new mode */ |
8620 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8621 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
3c9ada22 | 8622 | |
e4d78f12 YR |
8623 | } |
8624 | ||
8625 | static void bnx2x_set_limiting_mode(struct link_params *params, | |
8626 | struct bnx2x_phy *phy, | |
8627 | u16 edc_mode) | |
8628 | { | |
8629 | switch (phy->type) { | |
8630 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
8631 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); | |
8632 | break; | |
8633 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
8634 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8635 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); | |
8636 | break; | |
3c9ada22 YR |
8637 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
8638 | bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode); | |
8639 | break; | |
e4d78f12 YR |
8640 | } |
8641 | } | |
8642 | ||
fcf5b650 YR |
8643 | int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
8644 | struct link_params *params) | |
b7737c9b | 8645 | { |
b7737c9b | 8646 | struct bnx2x *bp = params->bp; |
de6eae1f | 8647 | u16 edc_mode; |
fcf5b650 | 8648 | int rc = 0; |
ea4e040a | 8649 | |
de6eae1f YR |
8650 | u32 val = REG_RD(bp, params->shmem_base + |
8651 | offsetof(struct shmem_region, dev_info. | |
8652 | port_feature_config[params->port].config)); | |
62b29a5d | 8653 | |
de6eae1f YR |
8654 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
8655 | params->port); | |
e4d78f12 YR |
8656 | /* Power up module */ |
8657 | bnx2x_power_sfp_module(params, phy, 1); | |
de6eae1f YR |
8658 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
8659 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
8660 | return -EINVAL; | |
cd88ccee | 8661 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
d231023e | 8662 | /* Check SFP+ module compatibility */ |
de6eae1f YR |
8663 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); |
8664 | rc = -EINVAL; | |
8665 | /* Turn on fault module-detected led */ | |
a8db5b4c YR |
8666 | bnx2x_set_sfp_module_fault_led(params, |
8667 | MISC_REGISTERS_GPIO_HIGH); | |
8668 | ||
e4d78f12 YR |
8669 | /* Check if need to power down the SFP+ module */ |
8670 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
8671 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { | |
de6eae1f | 8672 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
e4d78f12 | 8673 | bnx2x_power_sfp_module(params, phy, 0); |
de6eae1f YR |
8674 | return rc; |
8675 | } | |
8676 | } else { | |
8677 | /* Turn off fault module-detected led */ | |
a8db5b4c | 8678 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
62b29a5d | 8679 | } |
b7737c9b | 8680 | |
8f73f0b9 | 8681 | /* Check and set limiting mode / LRM mode on 8726. On 8727 it |
2cf7acf9 YR |
8682 | * is done automatically |
8683 | */ | |
e4d78f12 YR |
8684 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
8685 | ||
8f73f0b9 | 8686 | /* Enable transmit for this module if the module is approved, or |
de6eae1f YR |
8687 | * if unapproved modules should also enable the Tx laser |
8688 | */ | |
8689 | if (rc == 0 || | |
8690 | (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != | |
8691 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 8692 | bnx2x_sfp_set_transmitter(params, phy, 1); |
de6eae1f | 8693 | else |
a8db5b4c | 8694 | bnx2x_sfp_set_transmitter(params, phy, 0); |
b7737c9b | 8695 | |
de6eae1f YR |
8696 | return rc; |
8697 | } | |
8698 | ||
8699 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
8700 | { |
8701 | struct bnx2x *bp = params->bp; | |
3c9ada22 | 8702 | struct bnx2x_phy *phy; |
de6eae1f | 8703 | u32 gpio_val; |
3c9ada22 YR |
8704 | u8 gpio_num, gpio_port; |
8705 | if (CHIP_IS_E3(bp)) | |
8706 | phy = ¶ms->phy[INT_PHY]; | |
8707 | else | |
8708 | phy = ¶ms->phy[EXT_PHY1]; | |
8709 | ||
8710 | if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, | |
8711 | params->port, &gpio_num, &gpio_port) == | |
8712 | -EINVAL) { | |
8713 | DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n"); | |
8714 | return; | |
8715 | } | |
4d295db0 | 8716 | |
de6eae1f | 8717 | /* Set valid module led off */ |
a8db5b4c | 8718 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); |
4d295db0 | 8719 | |
2cf7acf9 | 8720 | /* Get current gpio val reflecting module plugged in / out*/ |
3c9ada22 | 8721 | gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); |
62b29a5d | 8722 | |
de6eae1f YR |
8723 | /* Call the handling function in case module is detected */ |
8724 | if (gpio_val == 0) { | |
dbef807e YM |
8725 | bnx2x_set_mdio_clk(bp, params->chip_id, params->port); |
8726 | bnx2x_set_aer_mmd(params, phy); | |
8727 | ||
e4d78f12 | 8728 | bnx2x_power_sfp_module(params, phy, 1); |
3c9ada22 | 8729 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8730 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
3c9ada22 | 8731 | gpio_port); |
dbef807e | 8732 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { |
de6eae1f | 8733 | bnx2x_sfp_module_detection(phy, params); |
dbef807e YM |
8734 | if (CHIP_IS_E3(bp)) { |
8735 | u16 rx_tx_in_reset; | |
8736 | /* In case WC is out of reset, reconfigure the | |
8737 | * link speed while taking into account 1G | |
8738 | * module limitation. | |
8739 | */ | |
8740 | bnx2x_cl45_read(bp, phy, | |
8741 | MDIO_WC_DEVAD, | |
8742 | MDIO_WC_REG_DIGITAL5_MISC6, | |
8743 | &rx_tx_in_reset); | |
8744 | if (!rx_tx_in_reset) { | |
8745 | bnx2x_warpcore_reset_lane(bp, phy, 1); | |
8746 | bnx2x_warpcore_config_sfi(phy, params); | |
8747 | bnx2x_warpcore_reset_lane(bp, phy, 0); | |
8748 | } | |
8749 | } | |
8750 | } else { | |
de6eae1f | 8751 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); |
dbef807e | 8752 | } |
de6eae1f YR |
8753 | } else { |
8754 | u32 val = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
8755 | offsetof(struct shmem_region, dev_info. |
8756 | port_feature_config[params->port]. | |
8757 | config)); | |
3c9ada22 | 8758 | bnx2x_set_gpio_int(bp, gpio_num, |
de6eae1f | 8759 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, |
3c9ada22 | 8760 | gpio_port); |
8f73f0b9 | 8761 | /* Module was plugged out. |
2cf7acf9 YR |
8762 | * Disable transmit for this module |
8763 | */ | |
1ac9e428 | 8764 | phy->media_type = ETH_PHY_NOT_PRESENT; |
de6f3377 YR |
8765 | if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
8766 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) || | |
8767 | CHIP_IS_E3(bp)) | |
a8db5b4c | 8768 | bnx2x_sfp_set_transmitter(params, phy, 0); |
62b29a5d | 8769 | } |
de6eae1f | 8770 | } |
62b29a5d | 8771 | |
c688fe2f YR |
8772 | /******************************************************************/ |
8773 | /* Used by 8706 and 8727 */ | |
8774 | /******************************************************************/ | |
8775 | static void bnx2x_sfp_mask_fault(struct bnx2x *bp, | |
8776 | struct bnx2x_phy *phy, | |
8777 | u16 alarm_status_offset, | |
8778 | u16 alarm_ctrl_offset) | |
8779 | { | |
8780 | u16 alarm_status, val; | |
8781 | bnx2x_cl45_read(bp, phy, | |
8782 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8783 | &alarm_status); | |
8784 | bnx2x_cl45_read(bp, phy, | |
8785 | MDIO_PMA_DEVAD, alarm_status_offset, | |
8786 | &alarm_status); | |
8787 | /* Mask or enable the fault event. */ | |
8788 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); | |
8789 | if (alarm_status & (1<<0)) | |
8790 | val &= ~(1<<0); | |
8791 | else | |
8792 | val |= (1<<0); | |
8793 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); | |
8794 | } | |
de6eae1f YR |
8795 | /******************************************************************/ |
8796 | /* common BCM8706/BCM8726 PHY SECTION */ | |
8797 | /******************************************************************/ | |
8798 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
8799 | struct link_params *params, | |
8800 | struct link_vars *vars) | |
8801 | { | |
8802 | u8 link_up = 0; | |
8803 | u16 val1, val2, rx_sd, pcs_status; | |
8804 | struct bnx2x *bp = params->bp; | |
8805 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
8806 | /* Clear RX Alarm*/ | |
62b29a5d | 8807 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8808 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); |
c688fe2f | 8809 | |
60d2fe03 YR |
8810 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
8811 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 8812 | |
d231023e | 8813 | /* Clear LASI indication*/ |
de6eae1f | 8814 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8815 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f | 8816 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 8817 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 8818 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); |
62b29a5d YR |
8819 | |
8820 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
8821 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
8822 | bnx2x_cl45_read(bp, phy, | |
8823 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
8824 | bnx2x_cl45_read(bp, phy, | |
8825 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
8826 | bnx2x_cl45_read(bp, phy, | |
8827 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 8828 | |
de6eae1f YR |
8829 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
8830 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
8f73f0b9 | 8831 | /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status |
2cf7acf9 | 8832 | * are set, or if the autoneg bit 1 is set |
de6eae1f YR |
8833 | */ |
8834 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
8835 | if (link_up) { | |
8836 | if (val2 & (1<<1)) | |
8837 | vars->line_speed = SPEED_1000; | |
8838 | else | |
8839 | vars->line_speed = SPEED_10000; | |
62b29a5d | 8840 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 | 8841 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 8842 | } |
c688fe2f YR |
8843 | |
8844 | /* Capture 10G link fault. Read twice to clear stale value. */ | |
8845 | if (vars->line_speed == SPEED_10000) { | |
8846 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 8847 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f | 8848 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
60d2fe03 | 8849 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
8850 | if (val1 & (1<<0)) |
8851 | vars->fault_detected = 1; | |
8852 | } | |
8853 | ||
62b29a5d | 8854 | return link_up; |
b7737c9b | 8855 | } |
62b29a5d | 8856 | |
de6eae1f YR |
8857 | /******************************************************************/ |
8858 | /* BCM8706 PHY SECTION */ | |
8859 | /******************************************************************/ | |
8860 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
8861 | struct link_params *params, |
8862 | struct link_vars *vars) | |
8863 | { | |
a8db5b4c YR |
8864 | u32 tx_en_mode; |
8865 | u16 cnt, val, tmp1; | |
b7737c9b | 8866 | struct bnx2x *bp = params->bp; |
3deb8167 | 8867 | |
de6eae1f | 8868 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee | 8869 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
8870 | /* HW reset */ |
8871 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
8872 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
6d870c39 | 8873 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 8874 | |
de6eae1f YR |
8875 | /* Wait until fw is loaded */ |
8876 | for (cnt = 0; cnt < 100; cnt++) { | |
8877 | bnx2x_cl45_read(bp, phy, | |
8878 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
8879 | if (val) | |
8880 | break; | |
d231023e | 8881 | usleep_range(10000, 20000); |
de6eae1f YR |
8882 | } |
8883 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
8884 | if ((params->feature_config_flags & | |
8885 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
8886 | u8 i; | |
8887 | u16 reg; | |
8888 | for (i = 0; i < 4; i++) { | |
8889 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
8890 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
8891 | MDIO_XS_8706_REG_BANK_RX0); | |
8892 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
8893 | /* Clear first 3 bits of the control */ | |
8894 | val &= ~0x7; | |
8895 | /* Set control bits according to configuration */ | |
8896 | val |= (phy->rx_preemphasis[i] & 0x7); | |
8897 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
8898 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
8899 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
8900 | } | |
8901 | } | |
8902 | /* Force speed */ | |
8903 | if (phy->req_line_speed == SPEED_10000) { | |
8904 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 8905 | |
de6eae1f YR |
8906 | bnx2x_cl45_write(bp, phy, |
8907 | MDIO_PMA_DEVAD, | |
8908 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
8909 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8910 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, |
c688fe2f YR |
8911 | 0); |
8912 | /* Arm LASI for link and Tx fault. */ | |
8913 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8914 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); |
de6eae1f | 8915 | } else { |
25985edc | 8916 | /* Force 1Gbps using autoneg with 1G advertisement */ |
6bbca910 | 8917 | |
de6eae1f YR |
8918 | /* Allow CL37 through CL73 */ |
8919 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
8920 | bnx2x_cl45_write(bp, phy, | |
8921 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 8922 | |
25985edc | 8923 | /* Enable Full-Duplex advertisement on CL37 */ |
de6eae1f YR |
8924 | bnx2x_cl45_write(bp, phy, |
8925 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
8926 | /* Enable CL37 AN */ | |
8927 | bnx2x_cl45_write(bp, phy, | |
8928 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
8929 | /* 1G support */ | |
8930 | bnx2x_cl45_write(bp, phy, | |
8931 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 8932 | |
de6eae1f YR |
8933 | /* Enable clause 73 AN */ |
8934 | bnx2x_cl45_write(bp, phy, | |
8935 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8936 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8937 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
8938 | 0x0400); |
8939 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 8940 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
de6eae1f YR |
8941 | 0x0004); |
8942 | } | |
8943 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
a8db5b4c | 8944 | |
8f73f0b9 | 8945 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
8946 | * power mode, if TX Laser is disabled |
8947 | */ | |
8948 | ||
8949 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
8950 | offsetof(struct shmem_region, | |
8951 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
8952 | & PORT_HW_CFG_TX_LASER_MASK; | |
8953 | ||
8954 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
8955 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
8956 | bnx2x_cl45_read(bp, phy, | |
8957 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); | |
8958 | tmp1 |= 0x1; | |
8959 | bnx2x_cl45_write(bp, phy, | |
8960 | MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); | |
8961 | } | |
8962 | ||
de6eae1f YR |
8963 | return 0; |
8964 | } | |
ea4e040a | 8965 | |
fcf5b650 YR |
8966 | static int bnx2x_8706_read_status(struct bnx2x_phy *phy, |
8967 | struct link_params *params, | |
8968 | struct link_vars *vars) | |
de6eae1f YR |
8969 | { |
8970 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
8971 | } | |
6bbca910 | 8972 | |
de6eae1f YR |
8973 | /******************************************************************/ |
8974 | /* BCM8726 PHY SECTION */ | |
8975 | /******************************************************************/ | |
8976 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
8977 | struct link_params *params) | |
8978 | { | |
8979 | struct bnx2x *bp = params->bp; | |
8980 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
8981 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
8982 | } | |
62b29a5d | 8983 | |
de6eae1f YR |
8984 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
8985 | struct link_params *params) | |
8986 | { | |
8987 | struct bnx2x *bp = params->bp; | |
8988 | /* Need to wait 100ms after reset */ | |
8989 | msleep(100); | |
62b29a5d | 8990 | |
de6eae1f YR |
8991 | /* Micro controller re-boot */ |
8992 | bnx2x_cl45_write(bp, phy, | |
8993 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 8994 | |
de6eae1f YR |
8995 | /* Set soft reset */ |
8996 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
8997 | MDIO_PMA_DEVAD, |
8998 | MDIO_PMA_REG_GEN_CTRL, | |
8999 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 9000 | |
de6eae1f | 9001 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9002 | MDIO_PMA_DEVAD, |
9003 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 9004 | |
de6eae1f | 9005 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9006 | MDIO_PMA_DEVAD, |
9007 | MDIO_PMA_REG_GEN_CTRL, | |
9008 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 9009 | |
d231023e | 9010 | /* Wait for 150ms for microcode load */ |
de6eae1f YR |
9011 | msleep(150); |
9012 | ||
9013 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
9014 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
9015 | MDIO_PMA_DEVAD, |
9016 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f YR |
9017 | |
9018 | msleep(200); | |
9019 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
9020 | } |
9021 | ||
de6eae1f | 9022 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
9023 | struct link_params *params, |
9024 | struct link_vars *vars) | |
9025 | { | |
9026 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9027 | u16 val1; |
9028 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
9029 | if (link_up) { |
9030 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
9031 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
9032 | &val1); | |
9033 | if (val1 & (1<<15)) { | |
9034 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
9035 | link_up = 0; | |
9036 | vars->line_speed = 0; | |
9037 | } | |
62b29a5d YR |
9038 | } |
9039 | return link_up; | |
b7737c9b YR |
9040 | } |
9041 | ||
de6eae1f | 9042 | |
fcf5b650 YR |
9043 | static int bnx2x_8726_config_init(struct bnx2x_phy *phy, |
9044 | struct link_params *params, | |
9045 | struct link_vars *vars) | |
b7737c9b YR |
9046 | { |
9047 | struct bnx2x *bp = params->bp; | |
de6eae1f | 9048 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); |
62b29a5d | 9049 | |
de6eae1f | 9050 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
6d870c39 | 9051 | bnx2x_wait_reset_complete(bp, phy, params); |
62b29a5d | 9052 | |
de6eae1f | 9053 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 9054 | |
8f73f0b9 | 9055 | /* Need to call module detected on initialization since the module |
2cf7acf9 YR |
9056 | * detection triggered by actual module insertion might occur before |
9057 | * driver is loaded, and when driver is loaded, it reset all | |
9058 | * registers, including the transmitter | |
9059 | */ | |
de6eae1f | 9060 | bnx2x_sfp_module_detection(phy, params); |
62b29a5d | 9061 | |
de6eae1f YR |
9062 | if (phy->req_line_speed == SPEED_1000) { |
9063 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9064 | bnx2x_cl45_write(bp, phy, | |
9065 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9066 | bnx2x_cl45_write(bp, phy, | |
9067 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9068 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9069 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); |
de6eae1f | 9070 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9071 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9072 | 0x400); |
9073 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9074 | (phy->speed_cap_mask & | |
9075 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
9076 | ((phy->speed_cap_mask & | |
9077 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9078 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9079 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9080 | /* Set Flow control */ | |
9081 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
9082 | bnx2x_cl45_write(bp, phy, | |
9083 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
9084 | bnx2x_cl45_write(bp, phy, | |
9085 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
9086 | bnx2x_cl45_write(bp, phy, | |
9087 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
9088 | bnx2x_cl45_write(bp, phy, | |
9089 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
9090 | bnx2x_cl45_write(bp, phy, | |
9091 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
8f73f0b9 | 9092 | /* Enable RX-ALARM control to receive interrupt for 1G speed |
2cf7acf9 YR |
9093 | * change |
9094 | */ | |
de6eae1f | 9095 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9096 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); |
de6eae1f | 9097 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 9098 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f | 9099 | 0x400); |
62b29a5d | 9100 | |
de6eae1f YR |
9101 | } else { /* Default 10G. Set only LASI control */ |
9102 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9103 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); |
7aa0711f YR |
9104 | } |
9105 | ||
de6eae1f YR |
9106 | /* Set TX PreEmphasis if needed */ |
9107 | if ((params->feature_config_flags & | |
9108 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
94f05b0f JP |
9109 | DP(NETIF_MSG_LINK, |
9110 | "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
de6eae1f YR |
9111 | phy->tx_preemphasis[0], |
9112 | phy->tx_preemphasis[1]); | |
9113 | bnx2x_cl45_write(bp, phy, | |
9114 | MDIO_PMA_DEVAD, | |
9115 | MDIO_PMA_REG_8726_TX_CTRL1, | |
9116 | phy->tx_preemphasis[0]); | |
c18aa15d | 9117 | |
de6eae1f YR |
9118 | bnx2x_cl45_write(bp, phy, |
9119 | MDIO_PMA_DEVAD, | |
9120 | MDIO_PMA_REG_8726_TX_CTRL2, | |
9121 | phy->tx_preemphasis[1]); | |
9122 | } | |
ab6ad5a4 | 9123 | |
de6eae1f | 9124 | return 0; |
ab6ad5a4 | 9125 | |
ea4e040a YR |
9126 | } |
9127 | ||
de6eae1f YR |
9128 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
9129 | struct link_params *params) | |
2f904460 | 9130 | { |
de6eae1f YR |
9131 | struct bnx2x *bp = params->bp; |
9132 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
9133 | /* Set serial boot control for external load */ | |
9134 | bnx2x_cl45_write(bp, phy, | |
9135 | MDIO_PMA_DEVAD, | |
9136 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
9137 | } | |
9138 | ||
9139 | /******************************************************************/ | |
9140 | /* BCM8727 PHY SECTION */ | |
9141 | /******************************************************************/ | |
7f02c4ad YR |
9142 | |
9143 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
9144 | struct link_params *params, u8 mode) | |
9145 | { | |
9146 | struct bnx2x *bp = params->bp; | |
9147 | u16 led_mode_bitmask = 0; | |
9148 | u16 gpio_pins_bitmask = 0; | |
9149 | u16 val; | |
9150 | /* Only NOC flavor requires to set the LED specifically */ | |
9151 | if (!(phy->flags & FLAGS_NOC)) | |
9152 | return; | |
9153 | switch (mode) { | |
9154 | case LED_MODE_FRONT_PANEL_OFF: | |
9155 | case LED_MODE_OFF: | |
9156 | led_mode_bitmask = 0; | |
9157 | gpio_pins_bitmask = 0x03; | |
9158 | break; | |
9159 | case LED_MODE_ON: | |
9160 | led_mode_bitmask = 0; | |
9161 | gpio_pins_bitmask = 0x02; | |
9162 | break; | |
9163 | case LED_MODE_OPER: | |
9164 | led_mode_bitmask = 0x60; | |
9165 | gpio_pins_bitmask = 0x11; | |
9166 | break; | |
9167 | } | |
9168 | bnx2x_cl45_read(bp, phy, | |
9169 | MDIO_PMA_DEVAD, | |
9170 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9171 | &val); | |
9172 | val &= 0xff8f; | |
9173 | val |= led_mode_bitmask; | |
9174 | bnx2x_cl45_write(bp, phy, | |
9175 | MDIO_PMA_DEVAD, | |
9176 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
9177 | val); | |
9178 | bnx2x_cl45_read(bp, phy, | |
9179 | MDIO_PMA_DEVAD, | |
9180 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
9181 | &val); | |
9182 | val &= 0xffe0; | |
9183 | val |= gpio_pins_bitmask; | |
9184 | bnx2x_cl45_write(bp, phy, | |
9185 | MDIO_PMA_DEVAD, | |
9186 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
9187 | val); | |
9188 | } | |
de6eae1f YR |
9189 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
9190 | struct link_params *params) { | |
9191 | u32 swap_val, swap_override; | |
9192 | u8 port; | |
8f73f0b9 | 9193 | /* The PHY reset is controlled by GPIO 1. Fake the port number |
de6eae1f | 9194 | * to cancel the swap done in set_gpio() |
2f904460 | 9195 | */ |
de6eae1f YR |
9196 | struct bnx2x *bp = params->bp; |
9197 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
9198 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
9199 | port = (swap_val && swap_override) ^ 1; | |
9200 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 9201 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2f904460 | 9202 | } |
e10bc84d | 9203 | |
dbef807e YM |
9204 | static void bnx2x_8727_config_speed(struct bnx2x_phy *phy, |
9205 | struct link_params *params) | |
9206 | { | |
9207 | struct bnx2x *bp = params->bp; | |
9208 | u16 tmp1, val; | |
9209 | /* Set option 1G speed */ | |
9210 | if ((phy->req_line_speed == SPEED_1000) || | |
9211 | (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { | |
9212 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
9213 | bnx2x_cl45_write(bp, phy, | |
9214 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
9215 | bnx2x_cl45_write(bp, phy, | |
9216 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
9217 | bnx2x_cl45_read(bp, phy, | |
9218 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
9219 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
9220 | /* Power down the XAUI until link is up in case of dual-media | |
9221 | * and 1G | |
9222 | */ | |
9223 | if (DUAL_MEDIA(params)) { | |
9224 | bnx2x_cl45_read(bp, phy, | |
9225 | MDIO_PMA_DEVAD, | |
9226 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
9227 | val |= (3<<10); | |
9228 | bnx2x_cl45_write(bp, phy, | |
9229 | MDIO_PMA_DEVAD, | |
9230 | MDIO_PMA_REG_8727_PCS_GP, val); | |
9231 | } | |
9232 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
9233 | ((phy->speed_cap_mask & | |
9234 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
9235 | ((phy->speed_cap_mask & | |
9236 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
9237 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
9238 | ||
9239 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
9240 | bnx2x_cl45_write(bp, phy, | |
9241 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
9242 | bnx2x_cl45_write(bp, phy, | |
9243 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
9244 | } else { | |
9245 | /* Since the 8727 has only single reset pin, need to set the 10G | |
9246 | * registers although it is default | |
9247 | */ | |
9248 | bnx2x_cl45_write(bp, phy, | |
9249 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
9250 | 0x0020); | |
9251 | bnx2x_cl45_write(bp, phy, | |
9252 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
9253 | bnx2x_cl45_write(bp, phy, | |
9254 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
9255 | bnx2x_cl45_write(bp, phy, | |
9256 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
9257 | 0x0008); | |
9258 | } | |
9259 | } | |
9260 | ||
fcf5b650 YR |
9261 | static int bnx2x_8727_config_init(struct bnx2x_phy *phy, |
9262 | struct link_params *params, | |
9263 | struct link_vars *vars) | |
ea4e040a | 9264 | { |
a8db5b4c | 9265 | u32 tx_en_mode; |
5c107fda | 9266 | u16 tmp1, mod_abs, tmp2; |
ea4e040a | 9267 | struct bnx2x *bp = params->bp; |
de6eae1f | 9268 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 9269 | |
6d870c39 | 9270 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 9271 | |
de6eae1f | 9272 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
ea4e040a | 9273 | |
5c107fda | 9274 | bnx2x_8727_specific_func(phy, params, PHY_INIT); |
8f73f0b9 | 9275 | /* Initially configure MOD_ABS to interrupt when module is |
2cf7acf9 YR |
9276 | * presence( bit 8) |
9277 | */ | |
de6eae1f YR |
9278 | bnx2x_cl45_read(bp, phy, |
9279 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
8f73f0b9 | 9280 | /* Set EDC off by setting OPTXLOS signal input to low (bit 9). |
2cf7acf9 YR |
9281 | * When the EDC is off it locks onto a reference clock and avoids |
9282 | * becoming 'lost' | |
9283 | */ | |
7f02c4ad YR |
9284 | mod_abs &= ~(1<<8); |
9285 | if (!(phy->flags & FLAGS_NOC)) | |
9286 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
9287 | bnx2x_cl45_write(bp, phy, |
9288 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9289 | |
85242eea YR |
9290 | /* Enable/Disable PHY transmitter output */ |
9291 | bnx2x_set_disable_pmd_transmit(params, phy, 0); | |
9292 | ||
de6eae1f YR |
9293 | bnx2x_8727_power_module(bp, phy, 1); |
9294 | ||
9295 | bnx2x_cl45_read(bp, phy, | |
9296 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
9297 | ||
9298 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9299 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); |
de6eae1f | 9300 | |
dbef807e | 9301 | bnx2x_8727_config_speed(phy, params); |
5c107fda | 9302 | |
b7737c9b | 9303 | |
de6eae1f YR |
9304 | /* Set TX PreEmphasis if needed */ |
9305 | if ((params->feature_config_flags & | |
9306 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
9307 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
9308 | phy->tx_preemphasis[0], | |
9309 | phy->tx_preemphasis[1]); | |
9310 | bnx2x_cl45_write(bp, phy, | |
9311 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
9312 | phy->tx_preemphasis[0]); | |
ea4e040a | 9313 | |
de6eae1f YR |
9314 | bnx2x_cl45_write(bp, phy, |
9315 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
9316 | phy->tx_preemphasis[1]); | |
9317 | } | |
ea4e040a | 9318 | |
8f73f0b9 | 9319 | /* If TX Laser is controlled by GPIO_0, do not let PHY go into low |
a8db5b4c YR |
9320 | * power mode, if TX Laser is disabled |
9321 | */ | |
9322 | tx_en_mode = REG_RD(bp, params->shmem_base + | |
9323 | offsetof(struct shmem_region, | |
9324 | dev_info.port_hw_config[params->port].sfp_ctrl)) | |
9325 | & PORT_HW_CFG_TX_LASER_MASK; | |
9326 | ||
9327 | if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { | |
9328 | ||
9329 | DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n"); | |
9330 | bnx2x_cl45_read(bp, phy, | |
9331 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); | |
9332 | tmp2 |= 0x1000; | |
9333 | tmp2 &= 0xFFEF; | |
9334 | bnx2x_cl45_write(bp, phy, | |
9335 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); | |
59a2e53b YR |
9336 | bnx2x_cl45_read(bp, phy, |
9337 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9338 | &tmp2); | |
9339 | bnx2x_cl45_write(bp, phy, | |
9340 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, | |
9341 | (tmp2 & 0x7fff)); | |
a8db5b4c YR |
9342 | } |
9343 | ||
de6eae1f | 9344 | return 0; |
ea4e040a YR |
9345 | } |
9346 | ||
de6eae1f YR |
9347 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
9348 | struct link_params *params) | |
ea4e040a | 9349 | { |
ea4e040a | 9350 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
9351 | u16 mod_abs, rx_alarm_status; |
9352 | u32 val = REG_RD(bp, params->shmem_base + | |
9353 | offsetof(struct shmem_region, dev_info. | |
9354 | port_feature_config[params->port]. | |
9355 | config)); | |
9356 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
9357 | MDIO_PMA_DEVAD, |
9358 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
de6eae1f | 9359 | if (mod_abs & (1<<8)) { |
ea4e040a | 9360 | |
de6eae1f | 9361 | /* Module is absent */ |
94f05b0f JP |
9362 | DP(NETIF_MSG_LINK, |
9363 | "MOD_ABS indication show module is absent\n"); | |
1ac9e428 | 9364 | phy->media_type = ETH_PHY_NOT_PRESENT; |
8f73f0b9 | 9365 | /* 1. Set mod_abs to detect next module |
2cf7acf9 YR |
9366 | * presence event |
9367 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
9368 | * (bit 9). | |
9369 | * When the EDC is off it locks onto a reference clock and | |
9370 | * avoids becoming 'lost'. | |
9371 | */ | |
7f02c4ad YR |
9372 | mod_abs &= ~(1<<8); |
9373 | if (!(phy->flags & FLAGS_NOC)) | |
9374 | mod_abs &= ~(1<<9); | |
de6eae1f | 9375 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
9376 | MDIO_PMA_DEVAD, |
9377 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9378 | |
8f73f0b9 | 9379 | /* Clear RX alarm since it stays up as long as |
2cf7acf9 YR |
9380 | * the mod_abs wasn't changed |
9381 | */ | |
de6eae1f | 9382 | bnx2x_cl45_read(bp, phy, |
cd88ccee | 9383 | MDIO_PMA_DEVAD, |
60d2fe03 | 9384 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9385 | |
de6eae1f YR |
9386 | } else { |
9387 | /* Module is present */ | |
94f05b0f JP |
9388 | DP(NETIF_MSG_LINK, |
9389 | "MOD_ABS indication show module is present\n"); | |
8f73f0b9 | 9390 | /* First disable transmitter, and if the module is ok, the |
2cf7acf9 YR |
9391 | * module_detection will enable it |
9392 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
9393 | * 2. Restore the default polarity of the OPRXLOS signal and | |
9394 | * this signal will then correctly indicate the presence or | |
9395 | * absence of the Rx signal. (bit 9) | |
9396 | */ | |
7f02c4ad YR |
9397 | mod_abs |= (1<<8); |
9398 | if (!(phy->flags & FLAGS_NOC)) | |
9399 | mod_abs |= (1<<9); | |
e10bc84d | 9400 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
9401 | MDIO_PMA_DEVAD, |
9402 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 9403 | |
8f73f0b9 | 9404 | /* Clear RX alarm since it stays up as long as the mod_abs |
2cf7acf9 YR |
9405 | * wasn't changed. This is need to be done before calling the |
9406 | * module detection, otherwise it will clear* the link update | |
9407 | * alarm | |
9408 | */ | |
de6eae1f YR |
9409 | bnx2x_cl45_read(bp, phy, |
9410 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9411 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
ea4e040a | 9412 | |
ea4e040a | 9413 | |
de6eae1f YR |
9414 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
9415 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
a8db5b4c | 9416 | bnx2x_sfp_set_transmitter(params, phy, 0); |
de6eae1f YR |
9417 | |
9418 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
9419 | bnx2x_sfp_module_detection(phy, params); | |
9420 | else | |
9421 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
dbef807e YM |
9422 | |
9423 | /* Reconfigure link speed based on module type limitations */ | |
9424 | bnx2x_8727_config_speed(phy, params); | |
ea4e040a | 9425 | } |
de6eae1f YR |
9426 | |
9427 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
2cf7acf9 YR |
9428 | rx_alarm_status); |
9429 | /* No need to check link status in case of module plugged in/out */ | |
ea4e040a YR |
9430 | } |
9431 | ||
de6eae1f YR |
9432 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
9433 | struct link_params *params, | |
9434 | struct link_vars *vars) | |
9435 | ||
ea4e040a YR |
9436 | { |
9437 | struct bnx2x *bp = params->bp; | |
27d02432 | 9438 | u8 link_up = 0, oc_port = params->port; |
de6eae1f | 9439 | u16 link_status = 0; |
a22f0788 YR |
9440 | u16 rx_alarm_status, lasi_ctrl, val1; |
9441 | ||
9442 | /* If PHY is not initialized, do not check link status */ | |
9443 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 9444 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, |
a22f0788 YR |
9445 | &lasi_ctrl); |
9446 | if (!lasi_ctrl) | |
9447 | return 0; | |
9448 | ||
9045f6b4 | 9449 | /* Check the LASI on Rx */ |
de6eae1f | 9450 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9451 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, |
de6eae1f YR |
9452 | &rx_alarm_status); |
9453 | vars->line_speed = 0; | |
9454 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
9455 | ||
60d2fe03 YR |
9456 | bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, |
9457 | MDIO_PMA_LASI_TXCTRL); | |
c688fe2f | 9458 | |
de6eae1f | 9459 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 9460 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
9461 | |
9462 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
9463 | ||
9464 | /* Clear MSG-OUT */ | |
9465 | bnx2x_cl45_read(bp, phy, | |
9466 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
9467 | ||
8f73f0b9 | 9468 | /* If a module is present and there is need to check |
de6eae1f YR |
9469 | * for over current |
9470 | */ | |
9471 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
9472 | /* Check over-current using 8727 GPIO0 input*/ | |
9473 | bnx2x_cl45_read(bp, phy, | |
9474 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
9475 | &val1); | |
9476 | ||
9477 | if ((val1 & (1<<8)) == 0) { | |
27d02432 YR |
9478 | if (!CHIP_IS_E1x(bp)) |
9479 | oc_port = BP_PATH(bp) + (params->port << 1); | |
94f05b0f JP |
9480 | DP(NETIF_MSG_LINK, |
9481 | "8727 Power fault has been detected on port %d\n", | |
9482 | oc_port); | |
2f751a80 YR |
9483 | netdev_err(bp->dev, "Error: Power fault on Port %d has " |
9484 | "been detected and the power to " | |
9485 | "that SFP+ module has been removed " | |
9486 | "to prevent failure of the card. " | |
9487 | "Please remove the SFP+ module and " | |
9488 | "restart the system to clear this " | |
9489 | "error.\n", | |
27d02432 | 9490 | oc_port); |
2cf7acf9 | 9491 | /* Disable all RX_ALARMs except for mod_abs */ |
de6eae1f YR |
9492 | bnx2x_cl45_write(bp, phy, |
9493 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9494 | MDIO_PMA_LASI_RXCTRL, (1<<5)); |
de6eae1f YR |
9495 | |
9496 | bnx2x_cl45_read(bp, phy, | |
9497 | MDIO_PMA_DEVAD, | |
9498 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
9499 | /* Wait for module_absent_event */ | |
9500 | val1 |= (1<<8); | |
9501 | bnx2x_cl45_write(bp, phy, | |
9502 | MDIO_PMA_DEVAD, | |
9503 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
9504 | /* Clear RX alarm */ | |
9505 | bnx2x_cl45_read(bp, phy, | |
9506 | MDIO_PMA_DEVAD, | |
60d2fe03 | 9507 | MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); |
de6eae1f YR |
9508 | return 0; |
9509 | } | |
9510 | } /* Over current check */ | |
9511 | ||
9512 | /* When module absent bit is set, check module */ | |
9513 | if (rx_alarm_status & (1<<5)) { | |
9514 | bnx2x_8727_handle_mod_abs(phy, params); | |
9515 | /* Enable all mod_abs and link detection bits */ | |
9516 | bnx2x_cl45_write(bp, phy, | |
60d2fe03 | 9517 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, |
de6eae1f YR |
9518 | ((1<<5) | (1<<2))); |
9519 | } | |
59a2e53b YR |
9520 | |
9521 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
9522 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n"); | |
9523 | bnx2x_sfp_set_transmitter(params, phy, 1); | |
9524 | } else { | |
de6eae1f YR |
9525 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); |
9526 | return 0; | |
9527 | } | |
9528 | ||
9529 | bnx2x_cl45_read(bp, phy, | |
9530 | MDIO_PMA_DEVAD, | |
9531 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
9532 | ||
8f73f0b9 | 9533 | /* Bits 0..2 --> speed detected, |
2cf7acf9 YR |
9534 | * Bits 13..15--> link is down |
9535 | */ | |
de6eae1f YR |
9536 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
9537 | link_up = 1; | |
9538 | vars->line_speed = SPEED_10000; | |
2cf7acf9 YR |
9539 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
9540 | params->port); | |
de6eae1f YR |
9541 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
9542 | link_up = 1; | |
9543 | vars->line_speed = SPEED_1000; | |
9544 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
9545 | params->port); | |
9546 | } else { | |
9547 | link_up = 0; | |
9548 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
9549 | params->port); | |
9550 | } | |
c688fe2f YR |
9551 | |
9552 | /* Capture 10G link fault. */ | |
9553 | if (vars->line_speed == SPEED_10000) { | |
9554 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9555 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9556 | |
9557 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
60d2fe03 | 9558 | MDIO_PMA_LASI_TXSTAT, &val1); |
c688fe2f YR |
9559 | |
9560 | if (val1 & (1<<0)) { | |
9561 | vars->fault_detected = 1; | |
9562 | } | |
9563 | } | |
9564 | ||
791f18c0 | 9565 | if (link_up) { |
de6eae1f | 9566 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 YR |
9567 | vars->duplex = DUPLEX_FULL; |
9568 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); | |
9569 | } | |
a22f0788 YR |
9570 | |
9571 | if ((DUAL_MEDIA(params)) && | |
9572 | (phy->req_line_speed == SPEED_1000)) { | |
9573 | bnx2x_cl45_read(bp, phy, | |
9574 | MDIO_PMA_DEVAD, | |
9575 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
8f73f0b9 | 9576 | /* In case of dual-media board and 1G, power up the XAUI side, |
a22f0788 YR |
9577 | * otherwise power it down. For 10G it is done automatically |
9578 | */ | |
9579 | if (link_up) | |
9580 | val1 &= ~(3<<10); | |
9581 | else | |
9582 | val1 |= (3<<10); | |
9583 | bnx2x_cl45_write(bp, phy, | |
9584 | MDIO_PMA_DEVAD, | |
9585 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
9586 | } | |
de6eae1f | 9587 | return link_up; |
b7737c9b | 9588 | } |
ea4e040a | 9589 | |
de6eae1f YR |
9590 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
9591 | struct link_params *params) | |
b7737c9b YR |
9592 | { |
9593 | struct bnx2x *bp = params->bp; | |
85242eea YR |
9594 | |
9595 | /* Enable/Disable PHY transmitter output */ | |
9596 | bnx2x_set_disable_pmd_transmit(params, phy, 1); | |
9597 | ||
de6eae1f | 9598 | /* Disable Transmitter */ |
a8db5b4c | 9599 | bnx2x_sfp_set_transmitter(params, phy, 0); |
a22f0788 | 9600 | /* Clear LASI */ |
60d2fe03 | 9601 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); |
a22f0788 | 9602 | |
ea4e040a | 9603 | } |
c18aa15d | 9604 | |
de6eae1f YR |
9605 | /******************************************************************/ |
9606 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
9607 | /******************************************************************/ | |
9608 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
11b2ec6b YR |
9609 | struct bnx2x *bp, |
9610 | u8 port) | |
ea4e040a | 9611 | { |
bac27bd9 | 9612 | u16 val, fw_ver1, fw_ver2, cnt; |
ea4e040a | 9613 | |
11b2ec6b YR |
9614 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
9615 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); | |
8267bbb0 | 9616 | bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, |
11b2ec6b YR |
9617 | phy->ver_addr); |
9618 | } else { | |
9619 | /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ | |
9620 | /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
9621 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | |
9622 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9623 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | |
9624 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | |
9625 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | |
9626 | ||
9627 | for (cnt = 0; cnt < 100; cnt++) { | |
9628 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9629 | if (val & 1) | |
9630 | break; | |
9631 | udelay(5); | |
9632 | } | |
9633 | if (cnt == 100) { | |
9634 | DP(NETIF_MSG_LINK, "Unable to read 848xx " | |
9635 | "phy fw version(1)\n"); | |
9636 | bnx2x_save_spirom_version(bp, port, 0, | |
9637 | phy->ver_addr); | |
9638 | return; | |
9639 | } | |
c87bca1e | 9640 | |
ea4e040a | 9641 | |
11b2ec6b YR |
9642 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
9643 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
9644 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
9645 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
9646 | for (cnt = 0; cnt < 100; cnt++) { | |
9647 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
9648 | if (val & 1) | |
9649 | break; | |
9650 | udelay(5); | |
9651 | } | |
9652 | if (cnt == 100) { | |
9653 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw " | |
9654 | "version(2)\n"); | |
9655 | bnx2x_save_spirom_version(bp, port, 0, | |
9656 | phy->ver_addr); | |
9657 | return; | |
9658 | } | |
ea4e040a | 9659 | |
11b2ec6b YR |
9660 | /* lower 16 bits of the register SPI_FW_STATUS */ |
9661 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
9662 | /* upper 16 bits of register SPI_FW_STATUS */ | |
9663 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 9664 | |
11b2ec6b | 9665 | bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, |
de6eae1f | 9666 | phy->ver_addr); |
ea4e040a YR |
9667 | } |
9668 | ||
de6eae1f | 9669 | } |
de6eae1f YR |
9670 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
9671 | struct bnx2x_phy *phy) | |
ea4e040a | 9672 | { |
521683da | 9673 | u16 val, offset; |
7846e471 | 9674 | |
de6eae1f YR |
9675 | /* PHYC_CTL_LED_CTL */ |
9676 | bnx2x_cl45_read(bp, phy, | |
9677 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9678 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); |
de6eae1f YR |
9679 | val &= 0xFE00; |
9680 | val |= 0x0092; | |
345b5d52 | 9681 | |
de6eae1f YR |
9682 | bnx2x_cl45_write(bp, phy, |
9683 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9684 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); |
ea4e040a | 9685 | |
de6eae1f YR |
9686 | bnx2x_cl45_write(bp, phy, |
9687 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9688 | MDIO_PMA_REG_8481_LED1_MASK, |
de6eae1f | 9689 | 0x80); |
ea4e040a | 9690 | |
de6eae1f YR |
9691 | bnx2x_cl45_write(bp, phy, |
9692 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9693 | MDIO_PMA_REG_8481_LED2_MASK, |
de6eae1f | 9694 | 0x18); |
ea4e040a | 9695 | |
f25b3c8b | 9696 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ |
de6eae1f YR |
9697 | bnx2x_cl45_write(bp, phy, |
9698 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9699 | MDIO_PMA_REG_8481_LED3_MASK, |
f25b3c8b YR |
9700 | 0x0006); |
9701 | ||
9702 | /* Select the closest activity blink rate to that in 10/100/1000 */ | |
9703 | bnx2x_cl45_write(bp, phy, | |
9704 | MDIO_PMA_DEVAD, | |
bac27bd9 | 9705 | MDIO_PMA_REG_8481_LED3_BLINK, |
f25b3c8b YR |
9706 | 0); |
9707 | ||
521683da YR |
9708 | /* Configure the blink rate to ~15.9 Hz */ |
9709 | bnx2x_cl45_write(bp, phy, | |
f25b3c8b | 9710 | MDIO_PMA_DEVAD, |
521683da YR |
9711 | MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, |
9712 | MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ); | |
f25b3c8b | 9713 | |
521683da YR |
9714 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) |
9715 | offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; | |
9716 | else | |
9717 | offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; | |
9718 | ||
9719 | bnx2x_cl45_read(bp, phy, | |
9720 | MDIO_PMA_DEVAD, offset, &val); | |
9721 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ | |
f25b3c8b | 9722 | bnx2x_cl45_write(bp, phy, |
521683da | 9723 | MDIO_PMA_DEVAD, offset, val); |
ea4e040a | 9724 | |
de6eae1f YR |
9725 | /* 'Interrupt Mask' */ |
9726 | bnx2x_cl45_write(bp, phy, | |
9727 | MDIO_AN_DEVAD, | |
9728 | 0xFFFB, 0xFFFD); | |
ea4e040a YR |
9729 | } |
9730 | ||
5c107fda YR |
9731 | static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy, |
9732 | struct link_params *params, | |
9733 | u32 action) | |
9734 | { | |
9735 | struct bnx2x *bp = params->bp; | |
9736 | switch (action) { | |
9737 | case PHY_INIT: | |
9738 | if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { | |
9739 | /* Save spirom version */ | |
9740 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); | |
9741 | } | |
9742 | /* This phy uses the NIG latch mechanism since link indication | |
9743 | * arrives through its LED4 and not via its LASI signal, so we | |
9744 | * get steady signal instead of clear on read | |
9745 | */ | |
9746 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, | |
9747 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
9748 | ||
9749 | bnx2x_848xx_set_led(bp, phy); | |
9750 | break; | |
9751 | } | |
9752 | } | |
9753 | ||
fcf5b650 YR |
9754 | static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
9755 | struct link_params *params, | |
9756 | struct link_vars *vars) | |
ea4e040a | 9757 | { |
c18aa15d | 9758 | struct bnx2x *bp = params->bp; |
521683da | 9759 | u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val; |
bac27bd9 | 9760 | |
5c107fda | 9761 | bnx2x_848xx_specific_func(phy, params, PHY_INIT); |
de6eae1f YR |
9762 | bnx2x_cl45_write(bp, phy, |
9763 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 9764 | |
de6eae1f YR |
9765 | /* set 1000 speed advertisement */ |
9766 | bnx2x_cl45_read(bp, phy, | |
9767 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9768 | &an_1000_val); | |
57963ed9 | 9769 | |
de6eae1f YR |
9770 | bnx2x_ext_phy_set_pause(params, phy, vars); |
9771 | bnx2x_cl45_read(bp, phy, | |
9772 | MDIO_AN_DEVAD, | |
9773 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9774 | &an_10_100_val); | |
9775 | bnx2x_cl45_read(bp, phy, | |
9776 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
9777 | &autoneg_val); | |
9778 | /* Disable forced speed */ | |
9779 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
9780 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 9781 | |
de6eae1f YR |
9782 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9783 | (phy->speed_cap_mask & | |
9784 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
9785 | (phy->req_line_speed == SPEED_1000)) { | |
9786 | an_1000_val |= (1<<8); | |
9787 | autoneg_val |= (1<<9 | 1<<12); | |
9788 | if (phy->req_duplex == DUPLEX_FULL) | |
9789 | an_1000_val |= (1<<9); | |
9790 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
9791 | } else | |
9792 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 9793 | |
de6eae1f YR |
9794 | bnx2x_cl45_write(bp, phy, |
9795 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
9796 | an_1000_val); | |
ea4e040a | 9797 | |
0520e63a | 9798 | /* set 100 speed advertisement */ |
75318327 | 9799 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
de6eae1f | 9800 | (phy->speed_cap_mask & |
0520e63a | 9801 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | |
75318327 | 9802 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) { |
de6eae1f YR |
9803 | an_10_100_val |= (1<<7); |
9804 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
9805 | autoneg_val |= (1<<9 | 1<<12); | |
b7737c9b | 9806 | |
de6eae1f YR |
9807 | if (phy->req_duplex == DUPLEX_FULL) |
9808 | an_10_100_val |= (1<<8); | |
9809 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
9810 | } | |
9811 | /* set 10 speed advertisement */ | |
9812 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
0520e63a YR |
9813 | (phy->speed_cap_mask & |
9814 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
9815 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) && | |
9816 | (phy->supported & | |
9817 | (SUPPORTED_10baseT_Half | | |
9818 | SUPPORTED_10baseT_Full)))) { | |
de6eae1f YR |
9819 | an_10_100_val |= (1<<5); |
9820 | autoneg_val |= (1<<9 | 1<<12); | |
9821 | if (phy->req_duplex == DUPLEX_FULL) | |
9822 | an_10_100_val |= (1<<6); | |
9823 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
9824 | } | |
b7737c9b | 9825 | |
de6eae1f | 9826 | /* Only 10/100 are allowed to work in FORCE mode */ |
0520e63a YR |
9827 | if ((phy->req_line_speed == SPEED_100) && |
9828 | (phy->supported & | |
9829 | (SUPPORTED_100baseT_Half | | |
9830 | SUPPORTED_100baseT_Full))) { | |
de6eae1f YR |
9831 | autoneg_val |= (1<<13); |
9832 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
9833 | bnx2x_cl45_write(bp, phy, | |
9834 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9835 | (1<<15 | 1<<9 | 7<<0)); | |
521683da YR |
9836 | /* The PHY needs this set even for forced link. */ |
9837 | an_10_100_val |= (1<<8) | (1<<7); | |
de6eae1f YR |
9838 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); |
9839 | } | |
0520e63a YR |
9840 | if ((phy->req_line_speed == SPEED_10) && |
9841 | (phy->supported & | |
9842 | (SUPPORTED_10baseT_Half | | |
9843 | SUPPORTED_10baseT_Full))) { | |
de6eae1f YR |
9844 | /* Enabled AUTO-MDIX when autoneg is disabled */ |
9845 | bnx2x_cl45_write(bp, phy, | |
9846 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
9847 | (1<<15 | 1<<9 | 7<<0)); | |
9848 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
9849 | } | |
b7737c9b | 9850 | |
de6eae1f YR |
9851 | bnx2x_cl45_write(bp, phy, |
9852 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
9853 | an_10_100_val); | |
b7737c9b | 9854 | |
de6eae1f YR |
9855 | if (phy->req_duplex == DUPLEX_FULL) |
9856 | autoneg_val |= (1<<8); | |
b7737c9b | 9857 | |
8f73f0b9 | 9858 | /* Always write this if this is not 84833. |
fd38f73e YR |
9859 | * For 84833, write it only when it's a forced speed. |
9860 | */ | |
9861 | if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || | |
9862 | ((autoneg_val & (1<<12)) == 0)) | |
9863 | bnx2x_cl45_write(bp, phy, | |
de6eae1f YR |
9864 | MDIO_AN_DEVAD, |
9865 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 9866 | |
de6eae1f YR |
9867 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
9868 | (phy->speed_cap_mask & | |
9869 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
9870 | (phy->req_line_speed == SPEED_10000)) { | |
9045f6b4 YR |
9871 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); |
9872 | /* Restart autoneg for 10G*/ | |
de6eae1f | 9873 | |
521683da YR |
9874 | bnx2x_cl45_read(bp, phy, |
9875 | MDIO_AN_DEVAD, | |
9876 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9877 | &an_10g_val); | |
9045f6b4 | 9878 | bnx2x_cl45_write(bp, phy, |
521683da YR |
9879 | MDIO_AN_DEVAD, |
9880 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9881 | an_10g_val | 0x1000); | |
9882 | bnx2x_cl45_write(bp, phy, | |
9883 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
9884 | 0x3200); | |
fd38f73e | 9885 | } else |
de6eae1f YR |
9886 | bnx2x_cl45_write(bp, phy, |
9887 | MDIO_AN_DEVAD, | |
9888 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
9889 | 1); | |
fd38f73e | 9890 | |
de6eae1f | 9891 | return 0; |
b7737c9b YR |
9892 | } |
9893 | ||
fcf5b650 YR |
9894 | static int bnx2x_8481_config_init(struct bnx2x_phy *phy, |
9895 | struct link_params *params, | |
9896 | struct link_vars *vars) | |
ea4e040a YR |
9897 | { |
9898 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
9899 | /* Restore normal power mode*/ |
9900 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 9901 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
b7737c9b | 9902 | |
de6eae1f YR |
9903 | /* HW reset */ |
9904 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 9905 | bnx2x_wait_reset_complete(bp, phy, params); |
ab6ad5a4 | 9906 | |
de6eae1f YR |
9907 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
9908 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
9909 | } | |
ea4e040a | 9910 | |
521683da YR |
9911 | #define PHY84833_CMDHDLR_WAIT 300 |
9912 | #define PHY84833_CMDHDLR_MAX_ARGS 5 | |
9913 | static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy, | |
bac27bd9 | 9914 | struct link_params *params, |
521683da | 9915 | u16 fw_cmd, |
c8c60d88 | 9916 | u16 cmd_args[], int argc) |
bac27bd9 | 9917 | { |
c8c60d88 | 9918 | int idx; |
bac27bd9 | 9919 | u16 val; |
bac27bd9 | 9920 | struct bnx2x *bp = params->bp; |
bac27bd9 YR |
9921 | /* Write CMD_OPEN_OVERRIDE to STATUS reg */ |
9922 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
521683da YR |
9923 | MDIO_84833_CMD_HDLR_STATUS, |
9924 | PHY84833_STATUS_CMD_OPEN_OVERRIDE); | |
9925 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9926 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9927 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9928 | if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) | |
bac27bd9 | 9929 | break; |
d231023e | 9930 | usleep_range(1000, 2000); |
bac27bd9 | 9931 | } |
521683da YR |
9932 | if (idx >= PHY84833_CMDHDLR_WAIT) { |
9933 | DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n"); | |
bac27bd9 YR |
9934 | return -EINVAL; |
9935 | } | |
9936 | ||
521683da | 9937 | /* Prepare argument(s) and issue command */ |
c8c60d88 | 9938 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9939 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
9940 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9941 | cmd_args[idx]); | |
9942 | } | |
bac27bd9 | 9943 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9944 | MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); |
9945 | for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { | |
bac27bd9 | 9946 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9947 | MDIO_84833_CMD_HDLR_STATUS, &val); |
9948 | if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || | |
9949 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) | |
bac27bd9 | 9950 | break; |
d231023e | 9951 | usleep_range(1000, 2000); |
bac27bd9 | 9952 | } |
521683da YR |
9953 | if ((idx >= PHY84833_CMDHDLR_WAIT) || |
9954 | (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { | |
9955 | DP(NETIF_MSG_LINK, "FW cmd failed.\n"); | |
bac27bd9 YR |
9956 | return -EINVAL; |
9957 | } | |
521683da | 9958 | /* Gather returning data */ |
c8c60d88 | 9959 | for (idx = 0; idx < argc; idx++) { |
521683da YR |
9960 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
9961 | MDIO_84833_CMD_HDLR_DATA1 + idx, | |
9962 | &cmd_args[idx]); | |
9963 | } | |
bac27bd9 | 9964 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, |
521683da YR |
9965 | MDIO_84833_CMD_HDLR_STATUS, |
9966 | PHY84833_STATUS_CMD_CLEAR_COMPLETE); | |
bac27bd9 YR |
9967 | return 0; |
9968 | } | |
9969 | ||
0d40f0d4 | 9970 | |
521683da YR |
9971 | static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy, |
9972 | struct link_params *params, | |
9973 | struct link_vars *vars) | |
9974 | { | |
9975 | u32 pair_swap; | |
9976 | u16 data[PHY84833_CMDHDLR_MAX_ARGS]; | |
9977 | int status; | |
9978 | struct bnx2x *bp = params->bp; | |
9979 | ||
9980 | /* Check for configuration. */ | |
9981 | pair_swap = REG_RD(bp, params->shmem_base + | |
9982 | offsetof(struct shmem_region, | |
9983 | dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & | |
9984 | PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; | |
9985 | ||
9986 | if (pair_swap == 0) | |
9987 | return 0; | |
9988 | ||
9989 | /* Only the second argument is used for this command */ | |
9990 | data[1] = (u16)pair_swap; | |
9991 | ||
9992 | status = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 | 9993 | PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); |
521683da YR |
9994 | if (status == 0) |
9995 | DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); | |
9996 | ||
9997 | return status; | |
9998 | } | |
9999 | ||
985848f8 YR |
10000 | static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, |
10001 | u32 shmem_base_path[], | |
10002 | u32 chip_id) | |
0d40f0d4 YR |
10003 | { |
10004 | u32 reset_pin[2]; | |
10005 | u32 idx; | |
10006 | u8 reset_gpios; | |
10007 | if (CHIP_IS_E3(bp)) { | |
10008 | /* Assume that these will be GPIOs, not EPIOs. */ | |
10009 | for (idx = 0; idx < 2; idx++) { | |
10010 | /* Map config param to register bit. */ | |
10011 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
10012 | offsetof(struct shmem_region, | |
10013 | dev_info.port_hw_config[0].e3_cmn_pin_cfg)); | |
10014 | reset_pin[idx] = (reset_pin[idx] & | |
10015 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10016 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10017 | reset_pin[idx] -= PIN_CFG_GPIO0_P0; | |
10018 | reset_pin[idx] = (1 << reset_pin[idx]); | |
10019 | } | |
10020 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
10021 | } else { | |
10022 | /* E2, look from diff place of shmem. */ | |
10023 | for (idx = 0; idx < 2; idx++) { | |
10024 | reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + | |
10025 | offsetof(struct shmem_region, | |
10026 | dev_info.port_hw_config[0].default_cfg)); | |
10027 | reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; | |
10028 | reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; | |
10029 | reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; | |
10030 | reset_pin[idx] = (1 << reset_pin[idx]); | |
10031 | } | |
10032 | reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); | |
10033 | } | |
10034 | ||
985848f8 YR |
10035 | return reset_gpios; |
10036 | } | |
10037 | ||
10038 | static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy, | |
10039 | struct link_params *params) | |
10040 | { | |
10041 | struct bnx2x *bp = params->bp; | |
10042 | u8 reset_gpios; | |
10043 | u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + | |
10044 | offsetof(struct shmem2_region, | |
10045 | other_shmem_base_addr)); | |
10046 | ||
10047 | u32 shmem_base_path[2]; | |
99bf7f34 YR |
10048 | |
10049 | /* Work around for 84833 LED failure inside RESET status */ | |
10050 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10051 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
10052 | MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); | |
10053 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10054 | MDIO_AN_REG_8481_1G_100T_EXT_CTRL, | |
10055 | MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); | |
10056 | ||
985848f8 YR |
10057 | shmem_base_path[0] = params->shmem_base; |
10058 | shmem_base_path[1] = other_shmem_base_addr; | |
10059 | ||
10060 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, | |
10061 | params->chip_id); | |
10062 | ||
10063 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
10064 | udelay(10); | |
10065 | DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", | |
10066 | reset_gpios); | |
10067 | ||
10068 | return 0; | |
10069 | } | |
10070 | ||
c8c60d88 YM |
10071 | static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy, |
10072 | struct link_params *params, | |
10073 | struct link_vars *vars) | |
10074 | { | |
10075 | int rc; | |
10076 | struct bnx2x *bp = params->bp; | |
10077 | u16 cmd_args = 0; | |
10078 | ||
10079 | DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); | |
10080 | ||
c8c60d88 YM |
10081 | /* Prevent Phy from working in EEE and advertising it */ |
10082 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
10083 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 10084 | if (rc) { |
c8c60d88 YM |
10085 | DP(NETIF_MSG_LINK, "EEE disable failed.\n"); |
10086 | return rc; | |
10087 | } | |
10088 | ||
ec4010ec | 10089 | return bnx2x_eee_disable(phy, params, vars); |
c8c60d88 YM |
10090 | } |
10091 | ||
10092 | static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy, | |
10093 | struct link_params *params, | |
10094 | struct link_vars *vars) | |
10095 | { | |
10096 | int rc; | |
10097 | struct bnx2x *bp = params->bp; | |
10098 | u16 cmd_args = 1; | |
10099 | ||
c8c60d88 YM |
10100 | rc = bnx2x_84833_cmd_hdlr(phy, params, |
10101 | PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); | |
d231023e | 10102 | if (rc) { |
c8c60d88 YM |
10103 | DP(NETIF_MSG_LINK, "EEE enable failed.\n"); |
10104 | return rc; | |
10105 | } | |
10106 | ||
ec4010ec | 10107 | return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); |
c8c60d88 YM |
10108 | } |
10109 | ||
a89a1d4a | 10110 | #define PHY84833_CONSTANT_LATENCY 1193 |
fcf5b650 YR |
10111 | static int bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
10112 | struct link_params *params, | |
10113 | struct link_vars *vars) | |
de6eae1f YR |
10114 | { |
10115 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10116 | u8 port, initialize = 1; |
bac27bd9 | 10117 | u16 val; |
521683da YR |
10118 | u32 actual_phy_selection, cms_enable; |
10119 | u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; | |
fcf5b650 | 10120 | int rc = 0; |
7f02c4ad | 10121 | |
d231023e | 10122 | usleep_range(1000, 2000); |
bac27bd9 | 10123 | |
5481388b | 10124 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10125 | port = BP_PATH(bp); |
10126 | else | |
10127 | port = params->port; | |
bac27bd9 YR |
10128 | |
10129 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10130 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10131 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
10132 | port); | |
10133 | } else { | |
985848f8 | 10134 | /* MDIO reset */ |
bac27bd9 YR |
10135 | bnx2x_cl45_write(bp, phy, |
10136 | MDIO_PMA_DEVAD, | |
10137 | MDIO_PMA_REG_CTRL, 0x8000); | |
521683da YR |
10138 | } |
10139 | ||
10140 | bnx2x_wait_reset_complete(bp, phy, params); | |
10141 | ||
10142 | /* Wait for GPHY to come out of reset */ | |
10143 | msleep(50); | |
11b2ec6b | 10144 | if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
8f73f0b9 | 10145 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
521683da YR |
10146 | * behavior. |
10147 | */ | |
10148 | u16 temp; | |
10149 | temp = vars->line_speed; | |
10150 | vars->line_speed = SPEED_10000; | |
10151 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); | |
10152 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
10153 | vars->line_speed = temp; | |
10154 | } | |
a22f0788 YR |
10155 | |
10156 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10157 | MDIO_CTL_REG_84823_MEDIA, &val); |
a22f0788 YR |
10158 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | |
10159 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
10160 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
10161 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
10162 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
0d40f0d4 YR |
10163 | |
10164 | if (CHIP_IS_E3(bp)) { | |
10165 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
10166 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK); | |
10167 | } else { | |
10168 | val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
10169 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); | |
10170 | } | |
a22f0788 YR |
10171 | |
10172 | actual_phy_selection = bnx2x_phy_selection(params); | |
10173 | ||
10174 | switch (actual_phy_selection) { | |
10175 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
25985edc | 10176 | /* Do nothing. Essentially this is like the priority copper */ |
a22f0788 YR |
10177 | break; |
10178 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
10179 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
10180 | break; | |
10181 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
10182 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
10183 | break; | |
10184 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
10185 | /* Do nothing here. The first PHY won't be initialized at all */ | |
10186 | break; | |
10187 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
10188 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
10189 | initialize = 0; | |
10190 | break; | |
10191 | } | |
10192 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
10193 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
10194 | ||
10195 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
bac27bd9 | 10196 | MDIO_CTL_REG_84823_MEDIA, val); |
a22f0788 YR |
10197 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", |
10198 | params->multi_phy_config, val); | |
10199 | ||
11b2ec6b YR |
10200 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
10201 | bnx2x_84833_pair_swap_cfg(phy, params, vars); | |
a89a1d4a | 10202 | |
096b9527 YR |
10203 | /* Keep AutogrEEEn disabled. */ |
10204 | cmd_args[0] = 0x0; | |
11b2ec6b YR |
10205 | cmd_args[1] = 0x0; |
10206 | cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; | |
10207 | cmd_args[3] = PHY84833_CONSTANT_LATENCY; | |
10208 | rc = bnx2x_84833_cmd_hdlr(phy, params, | |
c8c60d88 YM |
10209 | PHY84833_CMD_SET_EEE_MODE, cmd_args, |
10210 | PHY84833_CMDHDLR_MAX_ARGS); | |
d231023e | 10211 | if (rc) |
11b2ec6b YR |
10212 | DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n"); |
10213 | } | |
a22f0788 YR |
10214 | if (initialize) |
10215 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
10216 | else | |
11b2ec6b | 10217 | bnx2x_save_848xx_spirom_version(phy, bp, params->port); |
a89a1d4a YR |
10218 | /* 84833 PHY has a better feature and doesn't need to support this. */ |
10219 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10220 | cms_enable = REG_RD(bp, params->shmem_base + | |
1bef68e3 YR |
10221 | offsetof(struct shmem_region, |
10222 | dev_info.port_hw_config[params->port].default_cfg)) & | |
10223 | PORT_HW_CFG_ENABLE_CMS_MASK; | |
10224 | ||
a89a1d4a YR |
10225 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10226 | MDIO_CTL_REG_84823_USER_CTRL_REG, &val); | |
10227 | if (cms_enable) | |
10228 | val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10229 | else | |
10230 | val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; | |
10231 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
10232 | MDIO_CTL_REG_84823_USER_CTRL_REG, val); | |
10233 | } | |
1bef68e3 | 10234 | |
c8c60d88 YM |
10235 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, |
10236 | MDIO_84833_TOP_CFG_FW_REV, &val); | |
10237 | ||
10238 | /* Configure EEE support */ | |
f6b6eb69 YM |
10239 | if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && |
10240 | (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && | |
10241 | bnx2x_eee_has_cap(params)) { | |
ec4010ec | 10242 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); |
d231023e | 10243 | if (rc) { |
c8c60d88 YM |
10244 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); |
10245 | bnx2x_8483x_disable_eee(phy, params, vars); | |
10246 | return rc; | |
10247 | } | |
10248 | ||
10249 | if ((params->req_duplex[actual_phy_selection] == DUPLEX_FULL) && | |
10250 | (params->eee_mode & EEE_MODE_ADV_LPI) && | |
10251 | (bnx2x_eee_calc_timer(params) || | |
10252 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) | |
10253 | rc = bnx2x_8483x_enable_eee(phy, params, vars); | |
10254 | else | |
10255 | rc = bnx2x_8483x_disable_eee(phy, params, vars); | |
d231023e | 10256 | if (rc) { |
c8c60d88 YM |
10257 | DP(NETIF_MSG_LINK, "Failed to set EEE advertisment\n"); |
10258 | return rc; | |
10259 | } | |
10260 | } else { | |
c8c60d88 YM |
10261 | vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; |
10262 | } | |
10263 | ||
11b2ec6b YR |
10264 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { |
10265 | /* Bring PHY out of super isolate mode as the final step. */ | |
10266 | bnx2x_cl45_read(bp, phy, | |
10267 | MDIO_CTL_DEVAD, | |
10268 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | |
10269 | val &= ~MDIO_84833_SUPER_ISOLATE; | |
10270 | bnx2x_cl45_write(bp, phy, | |
10271 | MDIO_CTL_DEVAD, | |
10272 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | |
10273 | } | |
a22f0788 | 10274 | return rc; |
de6eae1f | 10275 | } |
ea4e040a | 10276 | |
de6eae1f | 10277 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
cd88ccee YR |
10278 | struct link_params *params, |
10279 | struct link_vars *vars) | |
de6eae1f YR |
10280 | { |
10281 | struct bnx2x *bp = params->bp; | |
bac27bd9 | 10282 | u16 val, val1, val2; |
de6eae1f | 10283 | u8 link_up = 0; |
ea4e040a | 10284 | |
c87bca1e | 10285 | |
de6eae1f YR |
10286 | /* Check 10G-BaseT link status */ |
10287 | /* Check PMD signal ok */ | |
10288 | bnx2x_cl45_read(bp, phy, | |
10289 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
10290 | bnx2x_cl45_read(bp, phy, | |
bac27bd9 | 10291 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, |
de6eae1f YR |
10292 | &val2); |
10293 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 10294 | |
de6eae1f YR |
10295 | /* Check link 10G */ |
10296 | if (val2 & (1<<11)) { | |
ea4e040a | 10297 | vars->line_speed = SPEED_10000; |
791f18c0 | 10298 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
10299 | link_up = 1; |
10300 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
10301 | } else { /* Check Legacy speed link */ | |
10302 | u16 legacy_status, legacy_speed; | |
ea4e040a | 10303 | |
de6eae1f YR |
10304 | /* Enable expansion register 0x42 (Operation mode status) */ |
10305 | bnx2x_cl45_write(bp, phy, | |
10306 | MDIO_AN_DEVAD, | |
10307 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 10308 | |
de6eae1f YR |
10309 | /* Get legacy speed operation status */ |
10310 | bnx2x_cl45_read(bp, phy, | |
10311 | MDIO_AN_DEVAD, | |
10312 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
10313 | &legacy_status); | |
ea4e040a | 10314 | |
94f05b0f JP |
10315 | DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", |
10316 | legacy_status); | |
de6eae1f | 10317 | link_up = ((legacy_status & (1<<11)) == (1<<11)); |
14400901 YM |
10318 | legacy_speed = (legacy_status & (3<<9)); |
10319 | if (legacy_speed == (0<<9)) | |
10320 | vars->line_speed = SPEED_10; | |
10321 | else if (legacy_speed == (1<<9)) | |
10322 | vars->line_speed = SPEED_100; | |
10323 | else if (legacy_speed == (2<<9)) | |
10324 | vars->line_speed = SPEED_1000; | |
10325 | else { /* Should not happen: Treat as link down */ | |
10326 | vars->line_speed = 0; | |
10327 | link_up = 0; | |
10328 | } | |
ea4e040a | 10329 | |
14400901 | 10330 | if (link_up) { |
de6eae1f YR |
10331 | if (legacy_status & (1<<8)) |
10332 | vars->duplex = DUPLEX_FULL; | |
10333 | else | |
10334 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 10335 | |
94f05b0f JP |
10336 | DP(NETIF_MSG_LINK, |
10337 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
10338 | vars->line_speed, | |
10339 | (vars->duplex == DUPLEX_FULL)); | |
de6eae1f YR |
10340 | /* Check legacy speed AN resolution */ |
10341 | bnx2x_cl45_read(bp, phy, | |
10342 | MDIO_AN_DEVAD, | |
10343 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
10344 | &val); | |
10345 | if (val & (1<<5)) | |
10346 | vars->link_status |= | |
10347 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
10348 | bnx2x_cl45_read(bp, phy, | |
10349 | MDIO_AN_DEVAD, | |
10350 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
10351 | &val); | |
10352 | if ((val & (1<<0)) == 0) | |
10353 | vars->link_status |= | |
10354 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 10355 | } |
ea4e040a | 10356 | } |
de6eae1f | 10357 | if (link_up) { |
d231023e | 10358 | DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n", |
de6eae1f YR |
10359 | vars->line_speed); |
10360 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 MY |
10361 | |
10362 | /* Read LP advertised speeds */ | |
10363 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10364 | MDIO_AN_REG_CL37_FC_LP, &val); | |
10365 | if (val & (1<<5)) | |
10366 | vars->link_status |= | |
10367 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
10368 | if (val & (1<<6)) | |
10369 | vars->link_status |= | |
10370 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
10371 | if (val & (1<<7)) | |
10372 | vars->link_status |= | |
10373 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
10374 | if (val & (1<<8)) | |
10375 | vars->link_status |= | |
10376 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
10377 | if (val & (1<<9)) | |
10378 | vars->link_status |= | |
10379 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
10380 | ||
10381 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10382 | MDIO_AN_REG_1000T_STATUS, &val); | |
10383 | ||
10384 | if (val & (1<<10)) | |
10385 | vars->link_status |= | |
10386 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
10387 | if (val & (1<<11)) | |
10388 | vars->link_status |= | |
10389 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
10390 | ||
10391 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, | |
10392 | MDIO_AN_REG_MASTER_STATUS, &val); | |
10393 | ||
10394 | if (val & (1<<11)) | |
10395 | vars->link_status |= | |
10396 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
c8c60d88 YM |
10397 | |
10398 | /* Determine if EEE was negotiated */ | |
ec4010ec YM |
10399 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) |
10400 | bnx2x_eee_an_resolve(phy, params, vars); | |
de6eae1f | 10401 | } |
589abe3a | 10402 | |
de6eae1f | 10403 | return link_up; |
b7737c9b YR |
10404 | } |
10405 | ||
fcf5b650 YR |
10406 | |
10407 | static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) | |
b7737c9b | 10408 | { |
fcf5b650 | 10409 | int status = 0; |
de6eae1f YR |
10410 | u32 spirom_ver; |
10411 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
10412 | status = bnx2x_format_ver(spirom_ver, str, len); | |
10413 | return status; | |
b7737c9b | 10414 | } |
de6eae1f YR |
10415 | |
10416 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
10417 | struct link_params *params) | |
b7737c9b | 10418 | { |
de6eae1f | 10419 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10420 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
de6eae1f | 10421 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 10422 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
b7737c9b | 10423 | } |
de6eae1f | 10424 | |
b7737c9b YR |
10425 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
10426 | struct link_params *params) | |
10427 | { | |
10428 | bnx2x_cl45_write(params->bp, phy, | |
10429 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
10430 | bnx2x_cl45_write(params->bp, phy, | |
10431 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
10432 | } | |
10433 | ||
10434 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
10435 | struct link_params *params) | |
10436 | { | |
10437 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 10438 | u8 port; |
0d40f0d4 | 10439 | u16 val16; |
bac27bd9 | 10440 | |
f93fb016 | 10441 | if (!(CHIP_IS_E1x(bp))) |
6a71bbe0 YR |
10442 | port = BP_PATH(bp); |
10443 | else | |
10444 | port = params->port; | |
bac27bd9 YR |
10445 | |
10446 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { | |
10447 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
10448 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
10449 | port); | |
10450 | } else { | |
0d40f0d4 YR |
10451 | bnx2x_cl45_read(bp, phy, |
10452 | MDIO_CTL_DEVAD, | |
11b2ec6b YR |
10453 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); |
10454 | val16 |= MDIO_84833_SUPER_ISOLATE; | |
fd38f73e | 10455 | bnx2x_cl45_write(bp, phy, |
11b2ec6b YR |
10456 | MDIO_CTL_DEVAD, |
10457 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); | |
bac27bd9 | 10458 | } |
b7737c9b YR |
10459 | } |
10460 | ||
7f02c4ad YR |
10461 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
10462 | struct link_params *params, u8 mode) | |
10463 | { | |
10464 | struct bnx2x *bp = params->bp; | |
10465 | u16 val; | |
bac27bd9 YR |
10466 | u8 port; |
10467 | ||
f93fb016 | 10468 | if (!(CHIP_IS_E1x(bp))) |
bac27bd9 YR |
10469 | port = BP_PATH(bp); |
10470 | else | |
10471 | port = params->port; | |
7f02c4ad YR |
10472 | |
10473 | switch (mode) { | |
10474 | case LED_MODE_OFF: | |
10475 | ||
bac27bd9 | 10476 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); |
7f02c4ad YR |
10477 | |
10478 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10479 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10480 | ||
10481 | /* Set LED masks */ | |
10482 | bnx2x_cl45_write(bp, phy, | |
10483 | MDIO_PMA_DEVAD, | |
10484 | MDIO_PMA_REG_8481_LED1_MASK, | |
10485 | 0x0); | |
10486 | ||
10487 | bnx2x_cl45_write(bp, phy, | |
10488 | MDIO_PMA_DEVAD, | |
10489 | MDIO_PMA_REG_8481_LED2_MASK, | |
10490 | 0x0); | |
10491 | ||
10492 | bnx2x_cl45_write(bp, phy, | |
10493 | MDIO_PMA_DEVAD, | |
10494 | MDIO_PMA_REG_8481_LED3_MASK, | |
10495 | 0x0); | |
10496 | ||
10497 | bnx2x_cl45_write(bp, phy, | |
10498 | MDIO_PMA_DEVAD, | |
10499 | MDIO_PMA_REG_8481_LED5_MASK, | |
10500 | 0x0); | |
10501 | ||
10502 | } else { | |
10503 | bnx2x_cl45_write(bp, phy, | |
10504 | MDIO_PMA_DEVAD, | |
10505 | MDIO_PMA_REG_8481_LED1_MASK, | |
10506 | 0x0); | |
10507 | } | |
10508 | break; | |
10509 | case LED_MODE_FRONT_PANEL_OFF: | |
10510 | ||
10511 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
bac27bd9 | 10512 | port); |
7f02c4ad YR |
10513 | |
10514 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10515 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10516 | ||
10517 | /* Set LED masks */ | |
10518 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10519 | MDIO_PMA_DEVAD, |
10520 | MDIO_PMA_REG_8481_LED1_MASK, | |
10521 | 0x0); | |
7f02c4ad YR |
10522 | |
10523 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10524 | MDIO_PMA_DEVAD, |
10525 | MDIO_PMA_REG_8481_LED2_MASK, | |
10526 | 0x0); | |
7f02c4ad YR |
10527 | |
10528 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10529 | MDIO_PMA_DEVAD, |
10530 | MDIO_PMA_REG_8481_LED3_MASK, | |
10531 | 0x0); | |
7f02c4ad YR |
10532 | |
10533 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10534 | MDIO_PMA_DEVAD, |
10535 | MDIO_PMA_REG_8481_LED5_MASK, | |
10536 | 0x20); | |
7f02c4ad YR |
10537 | |
10538 | } else { | |
10539 | bnx2x_cl45_write(bp, phy, | |
10540 | MDIO_PMA_DEVAD, | |
10541 | MDIO_PMA_REG_8481_LED1_MASK, | |
10542 | 0x0); | |
10543 | } | |
10544 | break; | |
10545 | case LED_MODE_ON: | |
10546 | ||
bac27bd9 | 10547 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); |
7f02c4ad YR |
10548 | |
10549 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10550 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10551 | /* Set control reg */ | |
10552 | bnx2x_cl45_read(bp, phy, | |
10553 | MDIO_PMA_DEVAD, | |
10554 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10555 | &val); | |
10556 | val &= 0x8000; | |
10557 | val |= 0x2492; | |
10558 | ||
10559 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10560 | MDIO_PMA_DEVAD, |
10561 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10562 | val); | |
7f02c4ad YR |
10563 | |
10564 | /* Set LED masks */ | |
10565 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10566 | MDIO_PMA_DEVAD, |
10567 | MDIO_PMA_REG_8481_LED1_MASK, | |
10568 | 0x0); | |
7f02c4ad YR |
10569 | |
10570 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10571 | MDIO_PMA_DEVAD, |
10572 | MDIO_PMA_REG_8481_LED2_MASK, | |
10573 | 0x20); | |
7f02c4ad YR |
10574 | |
10575 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10576 | MDIO_PMA_DEVAD, |
10577 | MDIO_PMA_REG_8481_LED3_MASK, | |
10578 | 0x20); | |
7f02c4ad YR |
10579 | |
10580 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10581 | MDIO_PMA_DEVAD, |
10582 | MDIO_PMA_REG_8481_LED5_MASK, | |
10583 | 0x0); | |
7f02c4ad YR |
10584 | } else { |
10585 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10586 | MDIO_PMA_DEVAD, |
10587 | MDIO_PMA_REG_8481_LED1_MASK, | |
10588 | 0x20); | |
7f02c4ad YR |
10589 | } |
10590 | break; | |
10591 | ||
10592 | case LED_MODE_OPER: | |
10593 | ||
bac27bd9 | 10594 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); |
7f02c4ad YR |
10595 | |
10596 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
10597 | SHARED_HW_CFG_LED_EXTPHY1) { | |
10598 | ||
10599 | /* Set control reg */ | |
10600 | bnx2x_cl45_read(bp, phy, | |
10601 | MDIO_PMA_DEVAD, | |
10602 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10603 | &val); | |
10604 | ||
10605 | if (!((val & | |
cd88ccee YR |
10606 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
10607 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { | |
2cf7acf9 | 10608 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
7f02c4ad YR |
10609 | bnx2x_cl45_write(bp, phy, |
10610 | MDIO_PMA_DEVAD, | |
10611 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10612 | 0xa492); | |
10613 | } | |
10614 | ||
10615 | /* Set LED masks */ | |
10616 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10617 | MDIO_PMA_DEVAD, |
10618 | MDIO_PMA_REG_8481_LED1_MASK, | |
10619 | 0x10); | |
7f02c4ad YR |
10620 | |
10621 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10622 | MDIO_PMA_DEVAD, |
10623 | MDIO_PMA_REG_8481_LED2_MASK, | |
10624 | 0x80); | |
7f02c4ad YR |
10625 | |
10626 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10627 | MDIO_PMA_DEVAD, |
10628 | MDIO_PMA_REG_8481_LED3_MASK, | |
10629 | 0x98); | |
7f02c4ad YR |
10630 | |
10631 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
10632 | MDIO_PMA_DEVAD, |
10633 | MDIO_PMA_REG_8481_LED5_MASK, | |
10634 | 0x40); | |
7f02c4ad YR |
10635 | |
10636 | } else { | |
10637 | bnx2x_cl45_write(bp, phy, | |
10638 | MDIO_PMA_DEVAD, | |
10639 | MDIO_PMA_REG_8481_LED1_MASK, | |
10640 | 0x80); | |
53eda06d YR |
10641 | |
10642 | /* Tell LED3 to blink on source */ | |
10643 | bnx2x_cl45_read(bp, phy, | |
10644 | MDIO_PMA_DEVAD, | |
10645 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10646 | &val); | |
10647 | val &= ~(7<<6); | |
10648 | val |= (1<<6); /* A83B[8:6]= 1 */ | |
10649 | bnx2x_cl45_write(bp, phy, | |
10650 | MDIO_PMA_DEVAD, | |
10651 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
10652 | val); | |
7f02c4ad YR |
10653 | } |
10654 | break; | |
10655 | } | |
0d40f0d4 | 10656 | |
8f73f0b9 | 10657 | /* This is a workaround for E3+84833 until autoneg |
0d40f0d4 YR |
10658 | * restart is fixed in f/w |
10659 | */ | |
10660 | if (CHIP_IS_E3(bp)) { | |
10661 | bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, | |
10662 | MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); | |
10663 | } | |
7f02c4ad | 10664 | } |
0d40f0d4 | 10665 | |
6583e33b | 10666 | /******************************************************************/ |
52c4d6c4 | 10667 | /* 54618SE PHY SECTION */ |
6583e33b | 10668 | /******************************************************************/ |
5c107fda YR |
10669 | static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy, |
10670 | struct link_params *params, | |
10671 | u32 action) | |
10672 | { | |
10673 | struct bnx2x *bp = params->bp; | |
10674 | u16 temp; | |
10675 | switch (action) { | |
10676 | case PHY_INIT: | |
10677 | /* Configure LED4: set to INTR (0x6). */ | |
10678 | /* Accessing shadow register 0xe. */ | |
10679 | bnx2x_cl22_write(bp, phy, | |
10680 | MDIO_REG_GPHY_SHADOW, | |
10681 | MDIO_REG_GPHY_SHADOW_LED_SEL2); | |
10682 | bnx2x_cl22_read(bp, phy, | |
10683 | MDIO_REG_GPHY_SHADOW, | |
10684 | &temp); | |
10685 | temp &= ~(0xf << 4); | |
10686 | temp |= (0x6 << 4); | |
10687 | bnx2x_cl22_write(bp, phy, | |
10688 | MDIO_REG_GPHY_SHADOW, | |
10689 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10690 | /* Configure INTR based on link status change. */ | |
10691 | bnx2x_cl22_write(bp, phy, | |
10692 | MDIO_REG_INTR_MASK, | |
10693 | ~MDIO_REG_INTR_MASK_LINK_STATUS); | |
10694 | break; | |
10695 | } | |
10696 | } | |
10697 | ||
52c4d6c4 | 10698 | static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, |
6583e33b YR |
10699 | struct link_params *params, |
10700 | struct link_vars *vars) | |
10701 | { | |
10702 | struct bnx2x *bp = params->bp; | |
10703 | u8 port; | |
10704 | u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; | |
10705 | u32 cfg_pin; | |
10706 | ||
52c4d6c4 | 10707 | DP(NETIF_MSG_LINK, "54618SE cfg init\n"); |
d231023e | 10708 | usleep_range(1000, 2000); |
6583e33b | 10709 | |
8f73f0b9 | 10710 | /* This works with E3 only, no need to check the chip |
2f751a80 YR |
10711 | * before determining the port. |
10712 | */ | |
6583e33b YR |
10713 | port = params->port; |
10714 | ||
10715 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10716 | offsetof(struct shmem_region, | |
10717 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10718 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10719 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10720 | ||
10721 | /* Drive pin high to bring the GPHY out of reset. */ | |
10722 | bnx2x_set_cfg_pin(bp, cfg_pin, 1); | |
10723 | ||
10724 | /* wait for GPHY to reset */ | |
10725 | msleep(50); | |
10726 | ||
10727 | /* reset phy */ | |
10728 | bnx2x_cl22_write(bp, phy, | |
10729 | MDIO_PMA_REG_CTRL, 0x8000); | |
10730 | bnx2x_wait_reset_complete(bp, phy, params); | |
10731 | ||
8f73f0b9 | 10732 | /* Wait for GPHY to reset */ |
6583e33b YR |
10733 | msleep(50); |
10734 | ||
6583e33b | 10735 | |
5c107fda | 10736 | bnx2x_54618se_specific_func(phy, params, PHY_INIT); |
6583e33b YR |
10737 | /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ |
10738 | bnx2x_cl22_write(bp, phy, | |
10739 | MDIO_REG_GPHY_SHADOW, | |
10740 | MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); | |
10741 | bnx2x_cl22_read(bp, phy, | |
10742 | MDIO_REG_GPHY_SHADOW, | |
10743 | &temp); | |
10744 | temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; | |
10745 | bnx2x_cl22_write(bp, phy, | |
10746 | MDIO_REG_GPHY_SHADOW, | |
10747 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10748 | ||
10749 | /* Set up fc */ | |
10750 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
10751 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
10752 | fc_val = 0; | |
10753 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
10754 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) | |
10755 | fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
10756 | ||
10757 | if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
10758 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) | |
10759 | fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
10760 | ||
d231023e | 10761 | /* Read all advertisement */ |
6583e33b YR |
10762 | bnx2x_cl22_read(bp, phy, |
10763 | 0x09, | |
10764 | &an_1000_val); | |
10765 | ||
10766 | bnx2x_cl22_read(bp, phy, | |
10767 | 0x04, | |
10768 | &an_10_100_val); | |
10769 | ||
10770 | bnx2x_cl22_read(bp, phy, | |
10771 | MDIO_PMA_REG_CTRL, | |
10772 | &autoneg_val); | |
10773 | ||
10774 | /* Disable forced speed */ | |
10775 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
10776 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | | |
10777 | (1<<11)); | |
10778 | ||
10779 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
10780 | (phy->speed_cap_mask & | |
10781 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
10782 | (phy->req_line_speed == SPEED_1000)) { | |
10783 | an_1000_val |= (1<<8); | |
10784 | autoneg_val |= (1<<9 | 1<<12); | |
10785 | if (phy->req_duplex == DUPLEX_FULL) | |
10786 | an_1000_val |= (1<<9); | |
10787 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
10788 | } else | |
10789 | an_1000_val &= ~((1<<8) | (1<<9)); | |
10790 | ||
10791 | bnx2x_cl22_write(bp, phy, | |
10792 | 0x09, | |
10793 | an_1000_val); | |
10794 | bnx2x_cl22_read(bp, phy, | |
10795 | 0x09, | |
10796 | &an_1000_val); | |
10797 | ||
d231023e | 10798 | /* Set 100 speed advertisement */ |
6583e33b YR |
10799 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
10800 | (phy->speed_cap_mask & | |
10801 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | | |
10802 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { | |
10803 | an_10_100_val |= (1<<7); | |
10804 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
10805 | autoneg_val |= (1<<9 | 1<<12); | |
10806 | ||
10807 | if (phy->req_duplex == DUPLEX_FULL) | |
10808 | an_10_100_val |= (1<<8); | |
10809 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
10810 | } | |
10811 | ||
d231023e | 10812 | /* Set 10 speed advertisement */ |
6583e33b YR |
10813 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
10814 | (phy->speed_cap_mask & | |
10815 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
10816 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { | |
10817 | an_10_100_val |= (1<<5); | |
10818 | autoneg_val |= (1<<9 | 1<<12); | |
10819 | if (phy->req_duplex == DUPLEX_FULL) | |
10820 | an_10_100_val |= (1<<6); | |
10821 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
10822 | } | |
10823 | ||
10824 | /* Only 10/100 are allowed to work in FORCE mode */ | |
10825 | if (phy->req_line_speed == SPEED_100) { | |
10826 | autoneg_val |= (1<<13); | |
10827 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10828 | bnx2x_cl22_write(bp, phy, | |
10829 | 0x18, | |
10830 | (1<<15 | 1<<9 | 7<<0)); | |
10831 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
10832 | } | |
10833 | if (phy->req_line_speed == SPEED_10) { | |
10834 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
10835 | bnx2x_cl22_write(bp, phy, | |
10836 | 0x18, | |
10837 | (1<<15 | 1<<9 | 7<<0)); | |
10838 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
10839 | } | |
10840 | ||
26964bb7 YM |
10841 | if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { |
10842 | int rc; | |
10843 | ||
10844 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, | |
10845 | MDIO_REG_GPHY_EXP_ACCESS_TOP | | |
10846 | MDIO_REG_GPHY_EXP_TOP_2K_BUF); | |
10847 | bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); | |
10848 | temp &= 0xfffe; | |
10849 | bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); | |
10850 | ||
10851 | rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); | |
10852 | if (rc) { | |
10853 | DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n"); | |
10854 | bnx2x_eee_disable(phy, params, vars); | |
10855 | } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && | |
10856 | (phy->req_duplex == DUPLEX_FULL) && | |
10857 | (bnx2x_eee_calc_timer(params) || | |
10858 | !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { | |
10859 | /* Need to advertise EEE only when requested, | |
10860 | * and either no LPI assertion was requested, | |
10861 | * or it was requested and a valid timer was set. | |
10862 | * Also notice full duplex is required for EEE. | |
10863 | */ | |
10864 | bnx2x_eee_advertise(phy, params, vars, | |
10865 | SHMEM_EEE_1G_ADV); | |
a89a1d4a | 10866 | } else { |
26964bb7 YM |
10867 | DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); |
10868 | bnx2x_eee_disable(phy, params, vars); | |
10869 | } | |
10870 | } else { | |
10871 | vars->eee_status &= ~SHMEM_EEE_1G_ADV << | |
10872 | SHMEM_EEE_SUPPORTED_SHIFT; | |
10873 | ||
10874 | if (phy->flags & FLAGS_EEE) { | |
10875 | /* Handle legacy auto-grEEEn */ | |
10876 | if (params->feature_config_flags & | |
10877 | FEATURE_CONFIG_AUTOGREEEN_ENABLED) { | |
10878 | temp = 6; | |
10879 | DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); | |
10880 | } else { | |
10881 | temp = 0; | |
10882 | DP(NETIF_MSG_LINK, "Don't Adv. EEE\n"); | |
10883 | } | |
10884 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | |
10885 | MDIO_AN_REG_EEE_ADV, temp); | |
a89a1d4a | 10886 | } |
a89a1d4a YR |
10887 | } |
10888 | ||
6583e33b YR |
10889 | bnx2x_cl22_write(bp, phy, |
10890 | 0x04, | |
10891 | an_10_100_val | fc_val); | |
10892 | ||
10893 | if (phy->req_duplex == DUPLEX_FULL) | |
10894 | autoneg_val |= (1<<8); | |
10895 | ||
10896 | bnx2x_cl22_write(bp, phy, | |
10897 | MDIO_PMA_REG_CTRL, autoneg_val); | |
10898 | ||
10899 | return 0; | |
10900 | } | |
10901 | ||
1d125bd5 YR |
10902 | |
10903 | static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy, | |
10904 | struct link_params *params, u8 mode) | |
10905 | { | |
10906 | struct bnx2x *bp = params->bp; | |
10907 | u16 temp; | |
10908 | ||
10909 | bnx2x_cl22_write(bp, phy, | |
10910 | MDIO_REG_GPHY_SHADOW, | |
10911 | MDIO_REG_GPHY_SHADOW_LED_SEL1); | |
10912 | bnx2x_cl22_read(bp, phy, | |
10913 | MDIO_REG_GPHY_SHADOW, | |
10914 | &temp); | |
10915 | temp &= 0xff00; | |
10916 | ||
10917 | DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode); | |
10918 | switch (mode) { | |
10919 | case LED_MODE_FRONT_PANEL_OFF: | |
10920 | case LED_MODE_OFF: | |
10921 | temp |= 0x00ee; | |
10922 | break; | |
10923 | case LED_MODE_OPER: | |
10924 | temp |= 0x0001; | |
10925 | break; | |
10926 | case LED_MODE_ON: | |
10927 | temp |= 0x00ff; | |
10928 | break; | |
10929 | default: | |
10930 | break; | |
10931 | } | |
10932 | bnx2x_cl22_write(bp, phy, | |
10933 | MDIO_REG_GPHY_SHADOW, | |
10934 | MDIO_REG_GPHY_SHADOW_WR_ENA | temp); | |
10935 | return; | |
10936 | } | |
10937 | ||
10938 | ||
52c4d6c4 YR |
10939 | static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, |
10940 | struct link_params *params) | |
6583e33b YR |
10941 | { |
10942 | struct bnx2x *bp = params->bp; | |
10943 | u32 cfg_pin; | |
10944 | u8 port; | |
10945 | ||
8f73f0b9 | 10946 | /* In case of no EPIO routed to reset the GPHY, put it |
d2059a06 YR |
10947 | * in low power mode. |
10948 | */ | |
10949 | bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); | |
8f73f0b9 | 10950 | /* This works with E3 only, no need to check the chip |
d2059a06 YR |
10951 | * before determining the port. |
10952 | */ | |
6583e33b YR |
10953 | port = params->port; |
10954 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
10955 | offsetof(struct shmem_region, | |
10956 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
10957 | PORT_HW_CFG_E3_PHY_RESET_MASK) >> | |
10958 | PORT_HW_CFG_E3_PHY_RESET_SHIFT; | |
10959 | ||
10960 | /* Drive pin low to put GPHY in reset. */ | |
10961 | bnx2x_set_cfg_pin(bp, cfg_pin, 0); | |
10962 | } | |
10963 | ||
52c4d6c4 YR |
10964 | static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy, |
10965 | struct link_params *params, | |
10966 | struct link_vars *vars) | |
6583e33b YR |
10967 | { |
10968 | struct bnx2x *bp = params->bp; | |
10969 | u16 val; | |
10970 | u8 link_up = 0; | |
10971 | u16 legacy_status, legacy_speed; | |
10972 | ||
10973 | /* Get speed operation status */ | |
10974 | bnx2x_cl22_read(bp, phy, | |
a351d497 | 10975 | MDIO_REG_GPHY_AUX_STATUS, |
6583e33b | 10976 | &legacy_status); |
52c4d6c4 | 10977 | DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); |
6583e33b YR |
10978 | |
10979 | /* Read status to clear the PHY interrupt. */ | |
10980 | bnx2x_cl22_read(bp, phy, | |
10981 | MDIO_REG_INTR_STATUS, | |
10982 | &val); | |
10983 | ||
10984 | link_up = ((legacy_status & (1<<2)) == (1<<2)); | |
10985 | ||
10986 | if (link_up) { | |
10987 | legacy_speed = (legacy_status & (7<<8)); | |
10988 | if (legacy_speed == (7<<8)) { | |
10989 | vars->line_speed = SPEED_1000; | |
10990 | vars->duplex = DUPLEX_FULL; | |
10991 | } else if (legacy_speed == (6<<8)) { | |
10992 | vars->line_speed = SPEED_1000; | |
10993 | vars->duplex = DUPLEX_HALF; | |
10994 | } else if (legacy_speed == (5<<8)) { | |
10995 | vars->line_speed = SPEED_100; | |
10996 | vars->duplex = DUPLEX_FULL; | |
10997 | } | |
10998 | /* Omitting 100Base-T4 for now */ | |
10999 | else if (legacy_speed == (3<<8)) { | |
11000 | vars->line_speed = SPEED_100; | |
11001 | vars->duplex = DUPLEX_HALF; | |
11002 | } else if (legacy_speed == (2<<8)) { | |
11003 | vars->line_speed = SPEED_10; | |
11004 | vars->duplex = DUPLEX_FULL; | |
11005 | } else if (legacy_speed == (1<<8)) { | |
11006 | vars->line_speed = SPEED_10; | |
11007 | vars->duplex = DUPLEX_HALF; | |
11008 | } else /* Should not happen */ | |
11009 | vars->line_speed = 0; | |
11010 | ||
94f05b0f JP |
11011 | DP(NETIF_MSG_LINK, |
11012 | "Link is up in %dMbps, is_duplex_full= %d\n", | |
11013 | vars->line_speed, | |
11014 | (vars->duplex == DUPLEX_FULL)); | |
6583e33b YR |
11015 | |
11016 | /* Check legacy speed AN resolution */ | |
11017 | bnx2x_cl22_read(bp, phy, | |
11018 | 0x01, | |
11019 | &val); | |
11020 | if (val & (1<<5)) | |
11021 | vars->link_status |= | |
11022 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
11023 | bnx2x_cl22_read(bp, phy, | |
11024 | 0x06, | |
11025 | &val); | |
11026 | if ((val & (1<<0)) == 0) | |
11027 | vars->link_status |= | |
11028 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
11029 | ||
52c4d6c4 | 11030 | DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n", |
6583e33b | 11031 | vars->line_speed); |
52c4d6c4 | 11032 | |
6583e33b | 11033 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
9e7e8399 MY |
11034 | |
11035 | if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
8f73f0b9 | 11036 | /* Report LP advertised speeds */ |
9e7e8399 MY |
11037 | bnx2x_cl22_read(bp, phy, 0x5, &val); |
11038 | ||
11039 | if (val & (1<<5)) | |
11040 | vars->link_status |= | |
11041 | LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; | |
11042 | if (val & (1<<6)) | |
11043 | vars->link_status |= | |
11044 | LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; | |
11045 | if (val & (1<<7)) | |
11046 | vars->link_status |= | |
11047 | LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; | |
11048 | if (val & (1<<8)) | |
11049 | vars->link_status |= | |
11050 | LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; | |
11051 | if (val & (1<<9)) | |
11052 | vars->link_status |= | |
11053 | LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; | |
11054 | ||
11055 | bnx2x_cl22_read(bp, phy, 0xa, &val); | |
11056 | if (val & (1<<10)) | |
11057 | vars->link_status |= | |
11058 | LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; | |
11059 | if (val & (1<<11)) | |
11060 | vars->link_status |= | |
11061 | LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; | |
26964bb7 YM |
11062 | |
11063 | if ((phy->flags & FLAGS_EEE) && | |
11064 | bnx2x_eee_has_cap(params)) | |
11065 | bnx2x_eee_an_resolve(phy, params, vars); | |
9e7e8399 | 11066 | } |
6583e33b YR |
11067 | } |
11068 | return link_up; | |
11069 | } | |
11070 | ||
52c4d6c4 YR |
11071 | static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy, |
11072 | struct link_params *params) | |
6583e33b YR |
11073 | { |
11074 | struct bnx2x *bp = params->bp; | |
11075 | u16 val; | |
11076 | u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; | |
11077 | ||
52c4d6c4 | 11078 | DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n"); |
6583e33b YR |
11079 | |
11080 | /* Enable master/slave manual mmode and set to master */ | |
11081 | /* mii write 9 [bits set 11 12] */ | |
11082 | bnx2x_cl22_write(bp, phy, 0x09, 3<<11); | |
11083 | ||
11084 | /* forced 1G and disable autoneg */ | |
11085 | /* set val [mii read 0] */ | |
11086 | /* set val [expr $val & [bits clear 6 12 13]] */ | |
11087 | /* set val [expr $val | [bits set 6 8]] */ | |
11088 | /* mii write 0 $val */ | |
11089 | bnx2x_cl22_read(bp, phy, 0x00, &val); | |
11090 | val &= ~((1<<6) | (1<<12) | (1<<13)); | |
11091 | val |= (1<<6) | (1<<8); | |
11092 | bnx2x_cl22_write(bp, phy, 0x00, val); | |
11093 | ||
11094 | /* Set external loopback and Tx using 6dB coding */ | |
11095 | /* mii write 0x18 7 */ | |
11096 | /* set val [mii read 0x18] */ | |
11097 | /* mii write 0x18 [expr $val | [bits set 10 15]] */ | |
11098 | bnx2x_cl22_write(bp, phy, 0x18, 7); | |
11099 | bnx2x_cl22_read(bp, phy, 0x18, &val); | |
11100 | bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); | |
11101 | ||
11102 | /* This register opens the gate for the UMAC despite its name */ | |
11103 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); | |
11104 | ||
8f73f0b9 | 11105 | /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame |
6583e33b YR |
11106 | * length used by the MAC receive logic to check frames. |
11107 | */ | |
11108 | REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); | |
11109 | } | |
11110 | ||
de6eae1f YR |
11111 | /******************************************************************/ |
11112 | /* SFX7101 PHY SECTION */ | |
11113 | /******************************************************************/ | |
11114 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
11115 | struct link_params *params) | |
b7737c9b YR |
11116 | { |
11117 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11118 | /* SFX7101_XGXS_TEST1 */ |
11119 | bnx2x_cl45_write(bp, phy, | |
11120 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
11121 | } |
11122 | ||
fcf5b650 YR |
11123 | static int bnx2x_7101_config_init(struct bnx2x_phy *phy, |
11124 | struct link_params *params, | |
11125 | struct link_vars *vars) | |
ea4e040a | 11126 | { |
de6eae1f | 11127 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 11128 | struct bnx2x *bp = params->bp; |
de6eae1f | 11129 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 11130 | |
de6eae1f YR |
11131 | /* Restore normal power mode*/ |
11132 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11133 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
11134 | /* HW reset */ |
11135 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6d870c39 | 11136 | bnx2x_wait_reset_complete(bp, phy, params); |
ea4e040a | 11137 | |
de6eae1f | 11138 | bnx2x_cl45_write(bp, phy, |
60d2fe03 | 11139 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); |
de6eae1f YR |
11140 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); |
11141 | bnx2x_cl45_write(bp, phy, | |
11142 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 11143 | |
de6eae1f YR |
11144 | bnx2x_ext_phy_set_pause(params, phy, vars); |
11145 | /* Restart autoneg */ | |
11146 | bnx2x_cl45_read(bp, phy, | |
11147 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
11148 | val |= 0x200; | |
11149 | bnx2x_cl45_write(bp, phy, | |
11150 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 11151 | |
de6eae1f YR |
11152 | /* Save spirom version */ |
11153 | bnx2x_cl45_read(bp, phy, | |
11154 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 11155 | |
de6eae1f YR |
11156 | bnx2x_cl45_read(bp, phy, |
11157 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
11158 | bnx2x_save_spirom_version(bp, params->port, | |
11159 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
11160 | return 0; | |
11161 | } | |
ea4e040a | 11162 | |
de6eae1f YR |
11163 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
11164 | struct link_params *params, | |
11165 | struct link_vars *vars) | |
57963ed9 YR |
11166 | { |
11167 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
11168 | u8 link_up; |
11169 | u16 val1, val2; | |
11170 | bnx2x_cl45_read(bp, phy, | |
60d2fe03 | 11171 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); |
de6eae1f | 11172 | bnx2x_cl45_read(bp, phy, |
60d2fe03 | 11173 | MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); |
de6eae1f YR |
11174 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", |
11175 | val2, val1); | |
11176 | bnx2x_cl45_read(bp, phy, | |
11177 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
11178 | bnx2x_cl45_read(bp, phy, | |
11179 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
11180 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
11181 | val2, val1); | |
11182 | link_up = ((val1 & 4) == 4); | |
d231023e | 11183 | /* If link is up print the AN outcome of the SFX7101 PHY */ |
de6eae1f YR |
11184 | if (link_up) { |
11185 | bnx2x_cl45_read(bp, phy, | |
11186 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
11187 | &val2); | |
11188 | vars->line_speed = SPEED_10000; | |
791f18c0 | 11189 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
11190 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
11191 | val2, (val2 & (1<<14))); | |
11192 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
11193 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
9e7e8399 | 11194 | |
d231023e | 11195 | /* Read LP advertised speeds */ |
9e7e8399 MY |
11196 | if (val2 & (1<<11)) |
11197 | vars->link_status |= | |
11198 | LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; | |
de6eae1f YR |
11199 | } |
11200 | return link_up; | |
11201 | } | |
6c55c3cd | 11202 | |
fcf5b650 | 11203 | static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
de6eae1f YR |
11204 | { |
11205 | if (*len < 5) | |
11206 | return -EINVAL; | |
11207 | str[0] = (spirom_ver & 0xFF); | |
11208 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
11209 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
11210 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
11211 | str[4] = '\0'; | |
11212 | *len -= 5; | |
57963ed9 YR |
11213 | return 0; |
11214 | } | |
11215 | ||
de6eae1f | 11216 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 11217 | { |
de6eae1f | 11218 | u16 val, cnt; |
7aa0711f | 11219 | |
de6eae1f | 11220 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
11221 | MDIO_PMA_DEVAD, |
11222 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 11223 | |
de6eae1f YR |
11224 | for (cnt = 0; cnt < 10; cnt++) { |
11225 | msleep(50); | |
11226 | /* Writes a self-clearing reset */ | |
11227 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
11228 | MDIO_PMA_DEVAD, |
11229 | MDIO_PMA_REG_7101_RESET, | |
11230 | (val | (1<<15))); | |
de6eae1f YR |
11231 | /* Wait for clear */ |
11232 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
11233 | MDIO_PMA_DEVAD, |
11234 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 11235 | |
de6eae1f YR |
11236 | if ((val & (1<<15)) == 0) |
11237 | break; | |
57963ed9 | 11238 | } |
57963ed9 | 11239 | } |
ea4e040a | 11240 | |
de6eae1f YR |
11241 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
11242 | struct link_params *params) { | |
11243 | /* Low power mode is controlled by GPIO 2 */ | |
11244 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 11245 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f YR |
11246 | /* The PHY reset is controlled by GPIO 1 */ |
11247 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 11248 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f | 11249 | } |
ea4e040a | 11250 | |
7f02c4ad YR |
11251 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
11252 | struct link_params *params, u8 mode) | |
11253 | { | |
11254 | u16 val = 0; | |
11255 | struct bnx2x *bp = params->bp; | |
11256 | switch (mode) { | |
11257 | case LED_MODE_FRONT_PANEL_OFF: | |
11258 | case LED_MODE_OFF: | |
11259 | val = 2; | |
11260 | break; | |
11261 | case LED_MODE_ON: | |
11262 | val = 1; | |
11263 | break; | |
11264 | case LED_MODE_OPER: | |
11265 | val = 0; | |
11266 | break; | |
11267 | } | |
11268 | bnx2x_cl45_write(bp, phy, | |
11269 | MDIO_PMA_DEVAD, | |
11270 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
11271 | val); | |
11272 | } | |
11273 | ||
de6eae1f YR |
11274 | /******************************************************************/ |
11275 | /* STATIC PHY DECLARATION */ | |
11276 | /******************************************************************/ | |
ea4e040a | 11277 | |
de6eae1f YR |
11278 | static struct bnx2x_phy phy_null = { |
11279 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | |
11280 | .addr = 0, | |
de6eae1f | 11281 | .def_md_devad = 0, |
9045f6b4 | 11282 | .flags = FLAGS_INIT_XGXS_FIRST, |
de6eae1f YR |
11283 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11284 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11285 | .mdio_ctrl = 0, | |
11286 | .supported = 0, | |
11287 | .media_type = ETH_PHY_NOT_PRESENT, | |
11288 | .ver_addr = 0, | |
cd88ccee YR |
11289 | .req_flow_ctrl = 0, |
11290 | .req_line_speed = 0, | |
11291 | .speed_cap_mask = 0, | |
de6eae1f YR |
11292 | .req_duplex = 0, |
11293 | .rsrv = 0, | |
11294 | .config_init = (config_init_t)NULL, | |
11295 | .read_status = (read_status_t)NULL, | |
11296 | .link_reset = (link_reset_t)NULL, | |
11297 | .config_loopback = (config_loopback_t)NULL, | |
11298 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11299 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11300 | .set_link_led = (set_link_led_t)NULL, |
11301 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11302 | }; |
ea4e040a | 11303 | |
de6eae1f YR |
11304 | static struct bnx2x_phy phy_serdes = { |
11305 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | |
11306 | .addr = 0xff, | |
de6eae1f | 11307 | .def_md_devad = 0, |
9045f6b4 | 11308 | .flags = 0, |
de6eae1f YR |
11309 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11310 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11311 | .mdio_ctrl = 0, | |
11312 | .supported = (SUPPORTED_10baseT_Half | | |
11313 | SUPPORTED_10baseT_Full | | |
11314 | SUPPORTED_100baseT_Half | | |
11315 | SUPPORTED_100baseT_Full | | |
11316 | SUPPORTED_1000baseT_Full | | |
11317 | SUPPORTED_2500baseX_Full | | |
11318 | SUPPORTED_TP | | |
11319 | SUPPORTED_Autoneg | | |
11320 | SUPPORTED_Pause | | |
11321 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11322 | .media_type = ETH_PHY_BASE_T, |
de6eae1f YR |
11323 | .ver_addr = 0, |
11324 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11325 | .req_line_speed = 0, |
11326 | .speed_cap_mask = 0, | |
de6eae1f YR |
11327 | .req_duplex = 0, |
11328 | .rsrv = 0, | |
ec146a6f | 11329 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
de6eae1f YR |
11330 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11331 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11332 | .config_loopback = (config_loopback_t)NULL, | |
11333 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11334 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11335 | .set_link_led = (set_link_led_t)NULL, |
11336 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 11337 | }; |
b7737c9b YR |
11338 | |
11339 | static struct bnx2x_phy phy_xgxs = { | |
11340 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
11341 | .addr = 0xff, | |
b7737c9b | 11342 | .def_md_devad = 0, |
9045f6b4 | 11343 | .flags = 0, |
b7737c9b YR |
11344 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11345 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11346 | .mdio_ctrl = 0, | |
11347 | .supported = (SUPPORTED_10baseT_Half | | |
11348 | SUPPORTED_10baseT_Full | | |
11349 | SUPPORTED_100baseT_Half | | |
11350 | SUPPORTED_100baseT_Full | | |
11351 | SUPPORTED_1000baseT_Full | | |
11352 | SUPPORTED_2500baseX_Full | | |
11353 | SUPPORTED_10000baseT_Full | | |
11354 | SUPPORTED_FIBRE | | |
11355 | SUPPORTED_Autoneg | | |
11356 | SUPPORTED_Pause | | |
11357 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11358 | .media_type = ETH_PHY_CX4, |
b7737c9b YR |
11359 | .ver_addr = 0, |
11360 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11361 | .req_line_speed = 0, |
11362 | .speed_cap_mask = 0, | |
b7737c9b YR |
11363 | .req_duplex = 0, |
11364 | .rsrv = 0, | |
ec146a6f | 11365 | .config_init = (config_init_t)bnx2x_xgxs_config_init, |
b7737c9b YR |
11366 | .read_status = (read_status_t)bnx2x_link_settings_status, |
11367 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
11368 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
11369 | .format_fw_ver = (format_fw_ver_t)NULL, | |
11370 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11371 | .set_link_led = (set_link_led_t)NULL, |
11372 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b | 11373 | }; |
3c9ada22 YR |
11374 | static struct bnx2x_phy phy_warpcore = { |
11375 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
11376 | .addr = 0xff, | |
11377 | .def_md_devad = 0, | |
55098c5c YR |
11378 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
11379 | FLAGS_TX_ERROR_CHECK), | |
3c9ada22 YR |
11380 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11381 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11382 | .mdio_ctrl = 0, | |
11383 | .supported = (SUPPORTED_10baseT_Half | | |
8f73f0b9 YR |
11384 | SUPPORTED_10baseT_Full | |
11385 | SUPPORTED_100baseT_Half | | |
11386 | SUPPORTED_100baseT_Full | | |
11387 | SUPPORTED_1000baseT_Full | | |
11388 | SUPPORTED_10000baseT_Full | | |
11389 | SUPPORTED_20000baseKR2_Full | | |
11390 | SUPPORTED_20000baseMLD2_Full | | |
11391 | SUPPORTED_FIBRE | | |
11392 | SUPPORTED_Autoneg | | |
11393 | SUPPORTED_Pause | | |
11394 | SUPPORTED_Asym_Pause), | |
3c9ada22 YR |
11395 | .media_type = ETH_PHY_UNSPECIFIED, |
11396 | .ver_addr = 0, | |
11397 | .req_flow_ctrl = 0, | |
11398 | .req_line_speed = 0, | |
11399 | .speed_cap_mask = 0, | |
11400 | /* req_duplex = */0, | |
11401 | /* rsrv = */0, | |
11402 | .config_init = (config_init_t)bnx2x_warpcore_config_init, | |
11403 | .read_status = (read_status_t)bnx2x_warpcore_read_status, | |
11404 | .link_reset = (link_reset_t)bnx2x_warpcore_link_reset, | |
11405 | .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback, | |
11406 | .format_fw_ver = (format_fw_ver_t)NULL, | |
985848f8 | 11407 | .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset, |
3c9ada22 YR |
11408 | .set_link_led = (set_link_led_t)NULL, |
11409 | .phy_specific_func = (phy_specific_func_t)NULL | |
11410 | }; | |
11411 | ||
b7737c9b YR |
11412 | |
11413 | static struct bnx2x_phy phy_7101 = { | |
11414 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | |
11415 | .addr = 0xff, | |
b7737c9b | 11416 | .def_md_devad = 0, |
9045f6b4 | 11417 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
b7737c9b YR |
11418 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11419 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11420 | .mdio_ctrl = 0, | |
11421 | .supported = (SUPPORTED_10000baseT_Full | | |
11422 | SUPPORTED_TP | | |
11423 | SUPPORTED_Autoneg | | |
11424 | SUPPORTED_Pause | | |
11425 | SUPPORTED_Asym_Pause), | |
11426 | .media_type = ETH_PHY_BASE_T, | |
11427 | .ver_addr = 0, | |
11428 | .req_flow_ctrl = 0, | |
cd88ccee YR |
11429 | .req_line_speed = 0, |
11430 | .speed_cap_mask = 0, | |
b7737c9b YR |
11431 | .req_duplex = 0, |
11432 | .rsrv = 0, | |
11433 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
11434 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
11435 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11436 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
11437 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
11438 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 11439 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 11440 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11441 | }; |
11442 | static struct bnx2x_phy phy_8073 = { | |
11443 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, | |
11444 | .addr = 0xff, | |
b7737c9b | 11445 | .def_md_devad = 0, |
9045f6b4 | 11446 | .flags = FLAGS_HW_LOCK_REQUIRED, |
b7737c9b YR |
11447 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11448 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11449 | .mdio_ctrl = 0, | |
11450 | .supported = (SUPPORTED_10000baseT_Full | | |
11451 | SUPPORTED_2500baseX_Full | | |
11452 | SUPPORTED_1000baseT_Full | | |
11453 | SUPPORTED_FIBRE | | |
11454 | SUPPORTED_Autoneg | | |
11455 | SUPPORTED_Pause | | |
11456 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11457 | .media_type = ETH_PHY_KR, |
b7737c9b | 11458 | .ver_addr = 0, |
cd88ccee YR |
11459 | .req_flow_ctrl = 0, |
11460 | .req_line_speed = 0, | |
11461 | .speed_cap_mask = 0, | |
b7737c9b YR |
11462 | .req_duplex = 0, |
11463 | .rsrv = 0, | |
62b29a5d | 11464 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
11465 | .read_status = (read_status_t)bnx2x_8073_read_status, |
11466 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
11467 | .config_loopback = (config_loopback_t)NULL, | |
11468 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11469 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 | 11470 | .set_link_led = (set_link_led_t)NULL, |
5c107fda | 11471 | .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func |
b7737c9b YR |
11472 | }; |
11473 | static struct bnx2x_phy phy_8705 = { | |
11474 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, | |
11475 | .addr = 0xff, | |
b7737c9b | 11476 | .def_md_devad = 0, |
9045f6b4 | 11477 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11478 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11479 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11480 | .mdio_ctrl = 0, | |
11481 | .supported = (SUPPORTED_10000baseT_Full | | |
11482 | SUPPORTED_FIBRE | | |
11483 | SUPPORTED_Pause | | |
11484 | SUPPORTED_Asym_Pause), | |
11485 | .media_type = ETH_PHY_XFP_FIBER, | |
11486 | .ver_addr = 0, | |
11487 | .req_flow_ctrl = 0, | |
11488 | .req_line_speed = 0, | |
11489 | .speed_cap_mask = 0, | |
11490 | .req_duplex = 0, | |
11491 | .rsrv = 0, | |
11492 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
11493 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
11494 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11495 | .config_loopback = (config_loopback_t)NULL, | |
11496 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
11497 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11498 | .set_link_led = (set_link_led_t)NULL, |
11499 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11500 | }; |
11501 | static struct bnx2x_phy phy_8706 = { | |
11502 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | |
11503 | .addr = 0xff, | |
b7737c9b | 11504 | .def_md_devad = 0, |
05822420 | 11505 | .flags = FLAGS_INIT_XGXS_FIRST, |
b7737c9b YR |
11506 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11507 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11508 | .mdio_ctrl = 0, | |
11509 | .supported = (SUPPORTED_10000baseT_Full | | |
11510 | SUPPORTED_1000baseT_Full | | |
11511 | SUPPORTED_FIBRE | | |
11512 | SUPPORTED_Pause | | |
11513 | SUPPORTED_Asym_Pause), | |
dbef807e | 11514 | .media_type = ETH_PHY_SFPP_10G_FIBER, |
b7737c9b YR |
11515 | .ver_addr = 0, |
11516 | .req_flow_ctrl = 0, | |
11517 | .req_line_speed = 0, | |
11518 | .speed_cap_mask = 0, | |
11519 | .req_duplex = 0, | |
11520 | .rsrv = 0, | |
11521 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
11522 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
11523 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
11524 | .config_loopback = (config_loopback_t)NULL, | |
11525 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11526 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11527 | .set_link_led = (set_link_led_t)NULL, |
11528 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11529 | }; |
11530 | ||
11531 | static struct bnx2x_phy phy_8726 = { | |
11532 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, | |
11533 | .addr = 0xff, | |
9045f6b4 | 11534 | .def_md_devad = 0, |
b7737c9b | 11535 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
55098c5c YR |
11536 | FLAGS_INIT_XGXS_FIRST | |
11537 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11538 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11539 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11540 | .mdio_ctrl = 0, | |
11541 | .supported = (SUPPORTED_10000baseT_Full | | |
11542 | SUPPORTED_1000baseT_Full | | |
11543 | SUPPORTED_Autoneg | | |
11544 | SUPPORTED_FIBRE | | |
11545 | SUPPORTED_Pause | | |
11546 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11547 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11548 | .ver_addr = 0, |
11549 | .req_flow_ctrl = 0, | |
11550 | .req_line_speed = 0, | |
11551 | .speed_cap_mask = 0, | |
11552 | .req_duplex = 0, | |
11553 | .rsrv = 0, | |
11554 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
11555 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
11556 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
11557 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
11558 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11559 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
11560 | .set_link_led = (set_link_led_t)NULL, |
11561 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
11562 | }; |
11563 | ||
11564 | static struct bnx2x_phy phy_8727 = { | |
11565 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | |
11566 | .addr = 0xff, | |
b7737c9b | 11567 | .def_md_devad = 0, |
55098c5c YR |
11568 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11569 | FLAGS_TX_ERROR_CHECK), | |
b7737c9b YR |
11570 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11571 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11572 | .mdio_ctrl = 0, | |
11573 | .supported = (SUPPORTED_10000baseT_Full | | |
11574 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
11575 | SUPPORTED_FIBRE | |
11576 | SUPPORTED_Pause | | |
11577 | SUPPORTED_Asym_Pause), | |
1ac9e428 | 11578 | .media_type = ETH_PHY_NOT_PRESENT, |
b7737c9b YR |
11579 | .ver_addr = 0, |
11580 | .req_flow_ctrl = 0, | |
11581 | .req_line_speed = 0, | |
11582 | .speed_cap_mask = 0, | |
11583 | .req_duplex = 0, | |
11584 | .rsrv = 0, | |
11585 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
11586 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
11587 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
11588 | .config_loopback = (config_loopback_t)NULL, | |
11589 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
11590 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 11591 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 11592 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b YR |
11593 | }; |
11594 | static struct bnx2x_phy phy_8481 = { | |
11595 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | |
11596 | .addr = 0xff, | |
9045f6b4 | 11597 | .def_md_devad = 0, |
a22f0788 YR |
11598 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
11599 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
11600 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11601 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11602 | .mdio_ctrl = 0, | |
11603 | .supported = (SUPPORTED_10baseT_Half | | |
11604 | SUPPORTED_10baseT_Full | | |
11605 | SUPPORTED_100baseT_Half | | |
11606 | SUPPORTED_100baseT_Full | | |
11607 | SUPPORTED_1000baseT_Full | | |
11608 | SUPPORTED_10000baseT_Full | | |
11609 | SUPPORTED_TP | | |
11610 | SUPPORTED_Autoneg | | |
11611 | SUPPORTED_Pause | | |
11612 | SUPPORTED_Asym_Pause), | |
11613 | .media_type = ETH_PHY_BASE_T, | |
11614 | .ver_addr = 0, | |
11615 | .req_flow_ctrl = 0, | |
11616 | .req_line_speed = 0, | |
11617 | .speed_cap_mask = 0, | |
11618 | .req_duplex = 0, | |
11619 | .rsrv = 0, | |
11620 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
11621 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11622 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
11623 | .config_loopback = (config_loopback_t)NULL, | |
11624 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11625 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 11626 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 11627 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
11628 | }; |
11629 | ||
de6eae1f YR |
11630 | static struct bnx2x_phy phy_84823 = { |
11631 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, | |
11632 | .addr = 0xff, | |
9045f6b4 | 11633 | .def_md_devad = 0, |
55098c5c YR |
11634 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11635 | FLAGS_REARM_LATCH_SIGNAL | | |
11636 | FLAGS_TX_ERROR_CHECK), | |
de6eae1f YR |
11637 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11638 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11639 | .mdio_ctrl = 0, | |
11640 | .supported = (SUPPORTED_10baseT_Half | | |
11641 | SUPPORTED_10baseT_Full | | |
11642 | SUPPORTED_100baseT_Half | | |
11643 | SUPPORTED_100baseT_Full | | |
11644 | SUPPORTED_1000baseT_Full | | |
11645 | SUPPORTED_10000baseT_Full | | |
11646 | SUPPORTED_TP | | |
11647 | SUPPORTED_Autoneg | | |
11648 | SUPPORTED_Pause | | |
11649 | SUPPORTED_Asym_Pause), | |
11650 | .media_type = ETH_PHY_BASE_T, | |
11651 | .ver_addr = 0, | |
11652 | .req_flow_ctrl = 0, | |
11653 | .req_line_speed = 0, | |
11654 | .speed_cap_mask = 0, | |
11655 | .req_duplex = 0, | |
11656 | .rsrv = 0, | |
11657 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11658 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11659 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11660 | .config_loopback = (config_loopback_t)NULL, | |
11661 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
11662 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 11663 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
5c107fda | 11664 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
de6eae1f YR |
11665 | }; |
11666 | ||
c87bca1e YR |
11667 | static struct bnx2x_phy phy_84833 = { |
11668 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, | |
11669 | .addr = 0xff, | |
9045f6b4 | 11670 | .def_md_devad = 0, |
55098c5c YR |
11671 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | |
11672 | FLAGS_REARM_LATCH_SIGNAL | | |
f6b6eb69 | 11673 | FLAGS_TX_ERROR_CHECK), |
c87bca1e YR |
11674 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
11675 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11676 | .mdio_ctrl = 0, | |
0520e63a | 11677 | .supported = (SUPPORTED_100baseT_Half | |
c87bca1e YR |
11678 | SUPPORTED_100baseT_Full | |
11679 | SUPPORTED_1000baseT_Full | | |
11680 | SUPPORTED_10000baseT_Full | | |
11681 | SUPPORTED_TP | | |
11682 | SUPPORTED_Autoneg | | |
11683 | SUPPORTED_Pause | | |
11684 | SUPPORTED_Asym_Pause), | |
11685 | .media_type = ETH_PHY_BASE_T, | |
11686 | .ver_addr = 0, | |
11687 | .req_flow_ctrl = 0, | |
11688 | .req_line_speed = 0, | |
11689 | .speed_cap_mask = 0, | |
11690 | .req_duplex = 0, | |
11691 | .rsrv = 0, | |
11692 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
11693 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
11694 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
11695 | .config_loopback = (config_loopback_t)NULL, | |
11696 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
985848f8 | 11697 | .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy, |
c87bca1e | 11698 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
5c107fda | 11699 | .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func |
c87bca1e YR |
11700 | }; |
11701 | ||
52c4d6c4 YR |
11702 | static struct bnx2x_phy phy_54618se = { |
11703 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, | |
6583e33b YR |
11704 | .addr = 0xff, |
11705 | .def_md_devad = 0, | |
11706 | .flags = FLAGS_INIT_XGXS_FIRST, | |
11707 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11708 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
11709 | .mdio_ctrl = 0, | |
11710 | .supported = (SUPPORTED_10baseT_Half | | |
11711 | SUPPORTED_10baseT_Full | | |
11712 | SUPPORTED_100baseT_Half | | |
11713 | SUPPORTED_100baseT_Full | | |
11714 | SUPPORTED_1000baseT_Full | | |
11715 | SUPPORTED_TP | | |
11716 | SUPPORTED_Autoneg | | |
11717 | SUPPORTED_Pause | | |
11718 | SUPPORTED_Asym_Pause), | |
11719 | .media_type = ETH_PHY_BASE_T, | |
11720 | .ver_addr = 0, | |
11721 | .req_flow_ctrl = 0, | |
11722 | .req_line_speed = 0, | |
11723 | .speed_cap_mask = 0, | |
11724 | /* req_duplex = */0, | |
11725 | /* rsrv = */0, | |
52c4d6c4 YR |
11726 | .config_init = (config_init_t)bnx2x_54618se_config_init, |
11727 | .read_status = (read_status_t)bnx2x_54618se_read_status, | |
11728 | .link_reset = (link_reset_t)bnx2x_54618se_link_reset, | |
11729 | .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, | |
6583e33b YR |
11730 | .format_fw_ver = (format_fw_ver_t)NULL, |
11731 | .hw_reset = (hw_reset_t)NULL, | |
1d125bd5 | 11732 | .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led, |
5c107fda | 11733 | .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func |
6583e33b | 11734 | }; |
de6eae1f YR |
11735 | /*****************************************************************/ |
11736 | /* */ | |
11737 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
11738 | /* */ | |
11739 | /*****************************************************************/ | |
11740 | ||
11741 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
11742 | struct bnx2x_phy *phy, u8 port, | |
11743 | u8 phy_index) | |
11744 | { | |
11745 | /* Get the 4 lanes xgxs config rx and tx */ | |
11746 | u32 rx = 0, tx = 0, i; | |
11747 | for (i = 0; i < 2; i++) { | |
8f73f0b9 YR |
11748 | /* INT_PHY and EXT_PHY1 share the same value location in |
11749 | * the shmem. When num_phys is greater than 1, than this value | |
de6eae1f YR |
11750 | * applies only to EXT_PHY1 |
11751 | */ | |
a22f0788 YR |
11752 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
11753 | rx = REG_RD(bp, shmem_base + | |
11754 | offsetof(struct shmem_region, | |
cd88ccee | 11755 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
a22f0788 YR |
11756 | |
11757 | tx = REG_RD(bp, shmem_base + | |
11758 | offsetof(struct shmem_region, | |
cd88ccee | 11759 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
a22f0788 YR |
11760 | } else { |
11761 | rx = REG_RD(bp, shmem_base + | |
11762 | offsetof(struct shmem_region, | |
cd88ccee | 11763 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
de6eae1f | 11764 | |
a22f0788 YR |
11765 | tx = REG_RD(bp, shmem_base + |
11766 | offsetof(struct shmem_region, | |
cd88ccee | 11767 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
a22f0788 | 11768 | } |
de6eae1f YR |
11769 | |
11770 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
11771 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
11772 | ||
11773 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
11774 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
11775 | } | |
11776 | } | |
11777 | ||
11778 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
11779 | u8 phy_index, u8 port) | |
11780 | { | |
11781 | u32 ext_phy_config = 0; | |
11782 | switch (phy_index) { | |
11783 | case EXT_PHY1: | |
11784 | ext_phy_config = REG_RD(bp, shmem_base + | |
11785 | offsetof(struct shmem_region, | |
11786 | dev_info.port_hw_config[port].external_phy_config)); | |
11787 | break; | |
a22f0788 YR |
11788 | case EXT_PHY2: |
11789 | ext_phy_config = REG_RD(bp, shmem_base + | |
11790 | offsetof(struct shmem_region, | |
11791 | dev_info.port_hw_config[port].external_phy_config2)); | |
11792 | break; | |
de6eae1f YR |
11793 | default: |
11794 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
11795 | return -EINVAL; | |
11796 | } | |
11797 | ||
11798 | return ext_phy_config; | |
11799 | } | |
fcf5b650 YR |
11800 | static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, |
11801 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11802 | { |
11803 | u32 phy_addr; | |
11804 | u32 chip_id; | |
11805 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
11806 | offsetof(struct shmem_region, | |
11807 | dev_info.port_feature_config[port].link_config)) & | |
11808 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
ec15b898 YR |
11809 | chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | |
11810 | ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); | |
11811 | ||
3c9ada22 YR |
11812 | DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); |
11813 | if (USES_WARPCORE(bp)) { | |
11814 | u32 serdes_net_if; | |
de6eae1f | 11815 | phy_addr = REG_RD(bp, |
3c9ada22 YR |
11816 | MISC_REG_WC0_CTRL_PHY_ADDR); |
11817 | *phy = phy_warpcore; | |
11818 | if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) | |
11819 | phy->flags |= FLAGS_4_PORT_MODE; | |
11820 | else | |
11821 | phy->flags &= ~FLAGS_4_PORT_MODE; | |
11822 | /* Check Dual mode */ | |
11823 | serdes_net_if = (REG_RD(bp, shmem_base + | |
11824 | offsetof(struct shmem_region, dev_info. | |
11825 | port_hw_config[port].default_cfg)) & | |
11826 | PORT_HW_CFG_NET_SERDES_IF_MASK); | |
8f73f0b9 | 11827 | /* Set the appropriate supported and flags indications per |
3c9ada22 YR |
11828 | * interface type of the chip |
11829 | */ | |
11830 | switch (serdes_net_if) { | |
11831 | case PORT_HW_CFG_NET_SERDES_IF_SGMII: | |
11832 | phy->supported &= (SUPPORTED_10baseT_Half | | |
11833 | SUPPORTED_10baseT_Full | | |
11834 | SUPPORTED_100baseT_Half | | |
11835 | SUPPORTED_100baseT_Full | | |
11836 | SUPPORTED_1000baseT_Full | | |
11837 | SUPPORTED_FIBRE | | |
11838 | SUPPORTED_Autoneg | | |
11839 | SUPPORTED_Pause | | |
11840 | SUPPORTED_Asym_Pause); | |
11841 | phy->media_type = ETH_PHY_BASE_T; | |
11842 | break; | |
11843 | case PORT_HW_CFG_NET_SERDES_IF_XFI: | |
11844 | phy->media_type = ETH_PHY_XFP_FIBER; | |
11845 | break; | |
11846 | case PORT_HW_CFG_NET_SERDES_IF_SFI: | |
11847 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11848 | SUPPORTED_10000baseT_Full | | |
11849 | SUPPORTED_FIBRE | | |
11850 | SUPPORTED_Pause | | |
11851 | SUPPORTED_Asym_Pause); | |
dbef807e | 11852 | phy->media_type = ETH_PHY_SFPP_10G_FIBER; |
3c9ada22 YR |
11853 | break; |
11854 | case PORT_HW_CFG_NET_SERDES_IF_KR: | |
11855 | phy->media_type = ETH_PHY_KR; | |
11856 | phy->supported &= (SUPPORTED_1000baseT_Full | | |
11857 | SUPPORTED_10000baseT_Full | | |
11858 | SUPPORTED_FIBRE | | |
11859 | SUPPORTED_Autoneg | | |
11860 | SUPPORTED_Pause | | |
11861 | SUPPORTED_Asym_Pause); | |
11862 | break; | |
11863 | case PORT_HW_CFG_NET_SERDES_IF_DXGXS: | |
11864 | phy->media_type = ETH_PHY_KR; | |
11865 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11866 | phy->supported &= (SUPPORTED_20000baseMLD2_Full | | |
11867 | SUPPORTED_FIBRE | | |
11868 | SUPPORTED_Pause | | |
11869 | SUPPORTED_Asym_Pause); | |
11870 | break; | |
11871 | case PORT_HW_CFG_NET_SERDES_IF_KR2: | |
11872 | phy->media_type = ETH_PHY_KR; | |
11873 | phy->flags |= FLAGS_WC_DUAL_MODE; | |
11874 | phy->supported &= (SUPPORTED_20000baseKR2_Full | | |
11875 | SUPPORTED_FIBRE | | |
11876 | SUPPORTED_Pause | | |
11877 | SUPPORTED_Asym_Pause); | |
11878 | break; | |
11879 | default: | |
11880 | DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", | |
11881 | serdes_net_if); | |
11882 | break; | |
11883 | } | |
11884 | ||
8f73f0b9 | 11885 | /* Enable MDC/MDIO work-around for E3 A0 since free running MDC |
3c9ada22 YR |
11886 | * was not set as expected. For B0, ECO will be enabled so there |
11887 | * won't be an issue there | |
11888 | */ | |
11889 | if (CHIP_REV(bp) == CHIP_REV_Ax) | |
11890 | phy->flags |= FLAGS_MDC_MDIO_WA; | |
157fa283 YR |
11891 | else |
11892 | phy->flags |= FLAGS_MDC_MDIO_WA_B0; | |
3c9ada22 YR |
11893 | } else { |
11894 | switch (switch_cfg) { | |
11895 | case SWITCH_CFG_1G: | |
11896 | phy_addr = REG_RD(bp, | |
11897 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
11898 | port * 0x10); | |
11899 | *phy = phy_serdes; | |
11900 | break; | |
11901 | case SWITCH_CFG_10G: | |
11902 | phy_addr = REG_RD(bp, | |
11903 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
11904 | port * 0x18); | |
11905 | *phy = phy_xgxs; | |
11906 | break; | |
11907 | default: | |
11908 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
11909 | return -EINVAL; | |
11910 | } | |
de6eae1f YR |
11911 | } |
11912 | phy->addr = (u8)phy_addr; | |
11913 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
11914 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
11915 | port); | |
f2e0899f DK |
11916 | if (CHIP_IS_E2(bp)) |
11917 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
11918 | else | |
11919 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
11920 | |
11921 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
11922 | port, phy->addr, phy->mdio_ctrl); | |
11923 | ||
11924 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
11925 | return 0; | |
11926 | } | |
11927 | ||
fcf5b650 YR |
11928 | static int bnx2x_populate_ext_phy(struct bnx2x *bp, |
11929 | u8 phy_index, | |
11930 | u32 shmem_base, | |
11931 | u32 shmem2_base, | |
11932 | u8 port, | |
11933 | struct bnx2x_phy *phy) | |
de6eae1f YR |
11934 | { |
11935 | u32 ext_phy_config, phy_type, config2; | |
11936 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
11937 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
11938 | phy_index, port); | |
11939 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
11940 | /* Select the phy type */ | |
11941 | switch (phy_type) { | |
11942 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
11943 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
11944 | *phy = phy_8073; | |
11945 | break; | |
11946 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
11947 | *phy = phy_8705; | |
11948 | break; | |
11949 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
11950 | *phy = phy_8706; | |
11951 | break; | |
11952 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
11953 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11954 | *phy = phy_8726; | |
11955 | break; | |
11956 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
11957 | /* BCM8727_NOC => BCM8727 no over current */ | |
11958 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11959 | *phy = phy_8727; | |
11960 | phy->flags |= FLAGS_NOC; | |
11961 | break; | |
e4d78f12 | 11962 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
de6eae1f YR |
11963 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
11964 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
11965 | *phy = phy_8727; | |
11966 | break; | |
11967 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
11968 | *phy = phy_8481; | |
11969 | break; | |
11970 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
11971 | *phy = phy_84823; | |
11972 | break; | |
c87bca1e YR |
11973 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
11974 | *phy = phy_84833; | |
11975 | break; | |
3756a89f | 11976 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: |
52c4d6c4 YR |
11977 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: |
11978 | *phy = phy_54618se; | |
26964bb7 YM |
11979 | if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) |
11980 | phy->flags |= FLAGS_EEE; | |
6583e33b | 11981 | break; |
de6eae1f YR |
11982 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: |
11983 | *phy = phy_7101; | |
11984 | break; | |
11985 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
11986 | *phy = phy_null; | |
11987 | return -EINVAL; | |
11988 | default: | |
11989 | *phy = phy_null; | |
6db5193b YR |
11990 | /* In case external PHY wasn't found */ |
11991 | if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | |
11992 | (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) | |
11993 | return -EINVAL; | |
de6eae1f YR |
11994 | return 0; |
11995 | } | |
11996 | ||
11997 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
11998 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
11999 | ||
8f73f0b9 | 12000 | /* The shmem address of the phy version is located on different |
2cf7acf9 YR |
12001 | * structures. In case this structure is too old, do not set |
12002 | * the address | |
12003 | */ | |
de6eae1f YR |
12004 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
12005 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
12006 | if (phy_index == EXT_PHY1) { |
12007 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
12008 | port_mb[port].ext_phy_fw_version); | |
de6eae1f | 12009 | |
cd88ccee YR |
12010 | /* Check specific mdc mdio settings */ |
12011 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
12012 | mdc_mdio_access = config2 & | |
12013 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
12014 | } else { |
12015 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 12016 | |
a22f0788 YR |
12017 | if (size > |
12018 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
12019 | phy->ver_addr = shmem2_base + | |
12020 | offsetof(struct shmem2_region, | |
12021 | ext_phy_fw_version2[port]); | |
12022 | } | |
12023 | /* Check specific mdc mdio settings */ | |
12024 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
12025 | mdc_mdio_access = (config2 & | |
12026 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
12027 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
12028 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
12029 | } | |
de6eae1f YR |
12030 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
12031 | ||
75318327 YR |
12032 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && |
12033 | (phy->ver_addr)) { | |
8f73f0b9 | 12034 | /* Remove 100Mb link supported for BCM84833 when phy fw |
75318327 YR |
12035 | * version lower than or equal to 1.39 |
12036 | */ | |
12037 | u32 raw_ver = REG_RD(bp, phy->ver_addr); | |
12038 | if (((raw_ver & 0x7F) <= 39) && | |
12039 | (((raw_ver & 0xF80) >> 7) <= 1)) | |
12040 | phy->supported &= ~(SUPPORTED_100baseT_Half | | |
12041 | SUPPORTED_100baseT_Full); | |
12042 | } | |
12043 | ||
8f73f0b9 | 12044 | /* In case mdc/mdio_access of the external phy is different than the |
de6eae1f YR |
12045 | * mdc/mdio access of the XGXS, a HW lock must be taken in each access |
12046 | * to prevent one port interfere with another port's CL45 operations. | |
12047 | */ | |
12048 | if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) | |
12049 | phy->flags |= FLAGS_HW_LOCK_REQUIRED; | |
12050 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", | |
12051 | phy_type, port, phy_index); | |
12052 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
12053 | phy->addr, phy->mdio_ctrl); | |
12054 | return 0; | |
12055 | } | |
12056 | ||
fcf5b650 YR |
12057 | static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, |
12058 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) | |
de6eae1f | 12059 | { |
fcf5b650 | 12060 | int status = 0; |
de6eae1f YR |
12061 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; |
12062 | if (phy_index == INT_PHY) | |
12063 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 12064 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12065 | port, phy); |
12066 | return status; | |
12067 | } | |
12068 | ||
12069 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
12070 | struct bnx2x_phy *phy, | |
a22f0788 | 12071 | u8 phy_index) |
de6eae1f YR |
12072 | { |
12073 | struct bnx2x *bp = params->bp; | |
12074 | u32 link_config; | |
12075 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
12076 | if (phy_index == EXT_PHY2) { |
12077 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 12078 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
12079 | port_feature_config[params->port].link_config2)); |
12080 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
12081 | offsetof(struct shmem_region, |
12082 | dev_info. | |
a22f0788 YR |
12083 | port_hw_config[params->port].speed_capability_mask2)); |
12084 | } else { | |
12085 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 12086 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
12087 | port_feature_config[params->port].link_config)); |
12088 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
12089 | offsetof(struct shmem_region, |
12090 | dev_info. | |
12091 | port_hw_config[params->port].speed_capability_mask)); | |
a22f0788 | 12092 | } |
94f05b0f JP |
12093 | DP(NETIF_MSG_LINK, |
12094 | "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", | |
12095 | phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
12096 | |
12097 | phy->req_duplex = DUPLEX_FULL; | |
12098 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
12099 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
12100 | phy->req_duplex = DUPLEX_HALF; | |
12101 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
12102 | phy->req_line_speed = SPEED_10; | |
12103 | break; | |
12104 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
12105 | phy->req_duplex = DUPLEX_HALF; | |
12106 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
12107 | phy->req_line_speed = SPEED_100; | |
12108 | break; | |
12109 | case PORT_FEATURE_LINK_SPEED_1G: | |
12110 | phy->req_line_speed = SPEED_1000; | |
12111 | break; | |
12112 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
12113 | phy->req_line_speed = SPEED_2500; | |
12114 | break; | |
12115 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
12116 | phy->req_line_speed = SPEED_10000; | |
12117 | break; | |
12118 | default: | |
12119 | phy->req_line_speed = SPEED_AUTO_NEG; | |
12120 | break; | |
12121 | } | |
12122 | ||
12123 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
12124 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
12125 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
12126 | break; | |
12127 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
12128 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
12129 | break; | |
12130 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
12131 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
12132 | break; | |
12133 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
12134 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
12135 | break; | |
12136 | default: | |
12137 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12138 | break; | |
12139 | } | |
12140 | } | |
12141 | ||
a22f0788 YR |
12142 | u32 bnx2x_phy_selection(struct link_params *params) |
12143 | { | |
12144 | u32 phy_config_swapped, prio_cfg; | |
12145 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
12146 | ||
12147 | phy_config_swapped = params->multi_phy_config & | |
12148 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
12149 | ||
12150 | prio_cfg = params->multi_phy_config & | |
12151 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
12152 | ||
12153 | if (phy_config_swapped) { | |
12154 | switch (prio_cfg) { | |
12155 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
12156 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
12157 | break; | |
12158 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
12159 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
12160 | break; | |
12161 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
12162 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
12163 | break; | |
12164 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
12165 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
12166 | break; | |
12167 | } | |
12168 | } else | |
12169 | return_cfg = prio_cfg; | |
12170 | ||
12171 | return return_cfg; | |
12172 | } | |
12173 | ||
12174 | ||
fcf5b650 | 12175 | int bnx2x_phy_probe(struct link_params *params) |
de6eae1f | 12176 | { |
2f751a80 | 12177 | u8 phy_index, actual_phy_idx; |
1ac9e428 | 12178 | u32 phy_config_swapped, sync_offset, media_types; |
de6eae1f YR |
12179 | struct bnx2x *bp = params->bp; |
12180 | struct bnx2x_phy *phy; | |
12181 | params->num_phys = 0; | |
12182 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
12183 | phy_config_swapped = params->multi_phy_config & |
12184 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
12185 | |
12186 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
12187 | phy_index++) { | |
de6eae1f | 12188 | actual_phy_idx = phy_index; |
a22f0788 YR |
12189 | if (phy_config_swapped) { |
12190 | if (phy_index == EXT_PHY1) | |
12191 | actual_phy_idx = EXT_PHY2; | |
12192 | else if (phy_index == EXT_PHY2) | |
12193 | actual_phy_idx = EXT_PHY1; | |
12194 | } | |
12195 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
12196 | " actual_phy_idx %x\n", phy_config_swapped, | |
12197 | phy_index, actual_phy_idx); | |
de6eae1f YR |
12198 | phy = ¶ms->phy[actual_phy_idx]; |
12199 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 12200 | params->shmem2_base, params->port, |
de6eae1f YR |
12201 | phy) != 0) { |
12202 | params->num_phys = 0; | |
12203 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
12204 | phy_index); | |
12205 | for (phy_index = INT_PHY; | |
12206 | phy_index < MAX_PHYS; | |
12207 | phy_index++) | |
12208 | *phy = phy_null; | |
12209 | return -EINVAL; | |
12210 | } | |
12211 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
12212 | break; | |
12213 | ||
55098c5c YR |
12214 | if (params->feature_config_flags & |
12215 | FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) | |
12216 | phy->flags &= ~FLAGS_TX_ERROR_CHECK; | |
12217 | ||
1ac9e428 YR |
12218 | sync_offset = params->shmem_base + |
12219 | offsetof(struct shmem_region, | |
12220 | dev_info.port_hw_config[params->port].media_type); | |
12221 | media_types = REG_RD(bp, sync_offset); | |
12222 | ||
8f73f0b9 | 12223 | /* Update media type for non-PMF sync only for the first time |
1ac9e428 YR |
12224 | * In case the media type changes afterwards, it will be updated |
12225 | * using the update_status function | |
12226 | */ | |
12227 | if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << | |
12228 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12229 | actual_phy_idx))) == 0) { | |
12230 | media_types |= ((phy->media_type & | |
12231 | PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << | |
12232 | (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * | |
12233 | actual_phy_idx)); | |
12234 | } | |
12235 | REG_WR(bp, sync_offset, media_types); | |
12236 | ||
a22f0788 | 12237 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
12238 | params->num_phys++; |
12239 | } | |
12240 | ||
12241 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
12242 | return 0; | |
12243 | } | |
12244 | ||
9045f6b4 YR |
12245 | void bnx2x_init_bmac_loopback(struct link_params *params, |
12246 | struct link_vars *vars) | |
de6eae1f YR |
12247 | { |
12248 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12249 | vars->link_up = 1; |
12250 | vars->line_speed = SPEED_10000; | |
12251 | vars->duplex = DUPLEX_FULL; | |
12252 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12253 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 12254 | |
de6eae1f | 12255 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 12256 | |
de6eae1f | 12257 | bnx2x_xgxs_deassert(params); |
b7737c9b | 12258 | |
de6eae1f YR |
12259 | /* set bmac loopback */ |
12260 | bnx2x_bmac_enable(params, vars, 1); | |
b7737c9b | 12261 | |
cd88ccee | 12262 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12263 | } |
b7737c9b | 12264 | |
9045f6b4 YR |
12265 | void bnx2x_init_emac_loopback(struct link_params *params, |
12266 | struct link_vars *vars) | |
12267 | { | |
12268 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
12269 | vars->link_up = 1; |
12270 | vars->line_speed = SPEED_1000; | |
12271 | vars->duplex = DUPLEX_FULL; | |
12272 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12273 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 12274 | |
de6eae1f | 12275 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 12276 | |
de6eae1f YR |
12277 | bnx2x_xgxs_deassert(params); |
12278 | /* set bmac loopback */ | |
12279 | bnx2x_emac_enable(params, vars, 1); | |
12280 | bnx2x_emac_program(params, vars); | |
cd88ccee | 12281 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
9045f6b4 | 12282 | } |
b7737c9b | 12283 | |
9380bb9e YR |
12284 | void bnx2x_init_xmac_loopback(struct link_params *params, |
12285 | struct link_vars *vars) | |
12286 | { | |
12287 | struct bnx2x *bp = params->bp; | |
12288 | vars->link_up = 1; | |
12289 | if (!params->req_line_speed[0]) | |
12290 | vars->line_speed = SPEED_10000; | |
12291 | else | |
12292 | vars->line_speed = params->req_line_speed[0]; | |
12293 | vars->duplex = DUPLEX_FULL; | |
12294 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12295 | vars->mac_type = MAC_TYPE_XMAC; | |
12296 | vars->phy_flags = PHY_XGXS_FLAG; | |
8f73f0b9 | 12297 | /* Set WC to loopback mode since link is required to provide clock |
9380bb9e YR |
12298 | * to the XMAC in 20G mode |
12299 | */ | |
afad009a YR |
12300 | bnx2x_set_aer_mmd(params, ¶ms->phy[0]); |
12301 | bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); | |
12302 | params->phy[INT_PHY].config_loopback( | |
3c9ada22 YR |
12303 | ¶ms->phy[INT_PHY], |
12304 | params); | |
afad009a | 12305 | |
9380bb9e YR |
12306 | bnx2x_xmac_enable(params, vars, 1); |
12307 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12308 | } | |
12309 | ||
12310 | void bnx2x_init_umac_loopback(struct link_params *params, | |
12311 | struct link_vars *vars) | |
12312 | { | |
12313 | struct bnx2x *bp = params->bp; | |
12314 | vars->link_up = 1; | |
12315 | vars->line_speed = SPEED_1000; | |
12316 | vars->duplex = DUPLEX_FULL; | |
12317 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12318 | vars->mac_type = MAC_TYPE_UMAC; | |
12319 | vars->phy_flags = PHY_XGXS_FLAG; | |
12320 | bnx2x_umac_enable(params, vars, 1); | |
12321 | ||
12322 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
12323 | } | |
12324 | ||
9045f6b4 YR |
12325 | void bnx2x_init_xgxs_loopback(struct link_params *params, |
12326 | struct link_vars *vars) | |
12327 | { | |
12328 | struct bnx2x *bp = params->bp; | |
de6eae1f | 12329 | vars->link_up = 1; |
de6eae1f | 12330 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
a22f0788 | 12331 | vars->duplex = DUPLEX_FULL; |
9045f6b4 | 12332 | if (params->req_line_speed[0] == SPEED_1000) |
a22f0788 | 12333 | vars->line_speed = SPEED_1000; |
9045f6b4 | 12334 | else |
a22f0788 | 12335 | vars->line_speed = SPEED_10000; |
62b29a5d | 12336 | |
9380bb9e YR |
12337 | if (!USES_WARPCORE(bp)) |
12338 | bnx2x_xgxs_deassert(params); | |
9045f6b4 YR |
12339 | bnx2x_link_initialize(params, vars); |
12340 | ||
12341 | if (params->req_line_speed[0] == SPEED_1000) { | |
9380bb9e YR |
12342 | if (USES_WARPCORE(bp)) |
12343 | bnx2x_umac_enable(params, vars, 0); | |
12344 | else { | |
12345 | bnx2x_emac_program(params, vars); | |
12346 | bnx2x_emac_enable(params, vars, 0); | |
12347 | } | |
12348 | } else { | |
12349 | if (USES_WARPCORE(bp)) | |
12350 | bnx2x_xmac_enable(params, vars, 0); | |
12351 | else | |
12352 | bnx2x_bmac_enable(params, vars, 0); | |
12353 | } | |
9045f6b4 | 12354 | |
de6eae1f YR |
12355 | if (params->loopback_mode == LOOPBACK_XGXS) { |
12356 | /* set 10G XGXS loopback */ | |
12357 | params->phy[INT_PHY].config_loopback( | |
12358 | ¶ms->phy[INT_PHY], | |
12359 | params); | |
c18aa15d | 12360 | |
de6eae1f YR |
12361 | } else { |
12362 | /* set external phy loopback */ | |
12363 | u8 phy_index; | |
12364 | for (phy_index = EXT_PHY1; | |
12365 | phy_index < params->num_phys; phy_index++) { | |
12366 | if (params->phy[phy_index].config_loopback) | |
12367 | params->phy[phy_index].config_loopback( | |
12368 | ¶ms->phy[phy_index], | |
12369 | params); | |
12370 | } | |
12371 | } | |
cd88ccee | 12372 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
de6eae1f | 12373 | |
9045f6b4 YR |
12374 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
12375 | } | |
12376 | ||
12377 | int bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |
12378 | { | |
12379 | struct bnx2x *bp = params->bp; | |
12380 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); | |
12381 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", | |
12382 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
12383 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
12384 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
12385 | vars->link_status = 0; | |
12386 | vars->phy_link_up = 0; | |
12387 | vars->link_up = 0; | |
12388 | vars->line_speed = 0; | |
12389 | vars->duplex = DUPLEX_FULL; | |
12390 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
12391 | vars->mac_type = MAC_TYPE_NONE; | |
12392 | vars->phy_flags = 0; | |
12393 | ||
d231023e | 12394 | /* Disable attentions */ |
9045f6b4 YR |
12395 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, |
12396 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12397 | NIG_MASK_XGXS0_LINK10G | | |
12398 | NIG_MASK_SERDES0_LINK_STATUS | | |
12399 | NIG_MASK_MI_INT)); | |
12400 | ||
12401 | bnx2x_emac_init(params, vars); | |
12402 | ||
27d9129f YR |
12403 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
12404 | vars->link_status |= LINK_STATUS_PFC_ENABLED; | |
12405 | ||
9045f6b4 YR |
12406 | if (params->num_phys == 0) { |
12407 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
12408 | return -EINVAL; | |
12409 | } | |
12410 | set_phy_vars(params, vars); | |
12411 | ||
12412 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
12413 | switch (params->loopback_mode) { | |
12414 | case LOOPBACK_BMAC: | |
12415 | bnx2x_init_bmac_loopback(params, vars); | |
12416 | break; | |
12417 | case LOOPBACK_EMAC: | |
12418 | bnx2x_init_emac_loopback(params, vars); | |
12419 | break; | |
9380bb9e YR |
12420 | case LOOPBACK_XMAC: |
12421 | bnx2x_init_xmac_loopback(params, vars); | |
12422 | break; | |
12423 | case LOOPBACK_UMAC: | |
12424 | bnx2x_init_umac_loopback(params, vars); | |
12425 | break; | |
9045f6b4 YR |
12426 | case LOOPBACK_XGXS: |
12427 | case LOOPBACK_EXT_PHY: | |
12428 | bnx2x_init_xgxs_loopback(params, vars); | |
12429 | break; | |
12430 | default: | |
9380bb9e YR |
12431 | if (!CHIP_IS_E3(bp)) { |
12432 | if (params->switch_cfg == SWITCH_CFG_10G) | |
12433 | bnx2x_xgxs_deassert(params); | |
12434 | else | |
12435 | bnx2x_serdes_deassert(bp, params->port); | |
12436 | } | |
de6eae1f YR |
12437 | bnx2x_link_initialize(params, vars); |
12438 | msleep(30); | |
12439 | bnx2x_link_int_enable(params); | |
9045f6b4 | 12440 | break; |
de6eae1f | 12441 | } |
55098c5c | 12442 | bnx2x_update_mng(params, vars->link_status); |
c8c60d88 YM |
12443 | |
12444 | bnx2x_update_mng_eee(params, vars->eee_status); | |
e10bc84d YR |
12445 | return 0; |
12446 | } | |
fcf5b650 YR |
12447 | |
12448 | int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
12449 | u8 reset_ext_phy) | |
b7737c9b YR |
12450 | { |
12451 | struct bnx2x *bp = params->bp; | |
cf1d972c | 12452 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
de6eae1f | 12453 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
d231023e | 12454 | /* Disable attentions */ |
de6eae1f YR |
12455 | vars->link_status = 0; |
12456 | bnx2x_update_mng(params, vars->link_status); | |
c8c60d88 YM |
12457 | vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | |
12458 | SHMEM_EEE_ACTIVE_BIT); | |
12459 | bnx2x_update_mng_eee(params, vars->eee_status); | |
de6eae1f | 12460 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
12461 | (NIG_MASK_XGXS0_LINK_STATUS | |
12462 | NIG_MASK_XGXS0_LINK10G | | |
12463 | NIG_MASK_SERDES0_LINK_STATUS | | |
12464 | NIG_MASK_MI_INT)); | |
b7737c9b | 12465 | |
d231023e | 12466 | /* Activate nig drain */ |
de6eae1f | 12467 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
b7737c9b | 12468 | |
d231023e | 12469 | /* Disable nig egress interface */ |
9380bb9e YR |
12470 | if (!CHIP_IS_E3(bp)) { |
12471 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
12472 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
12473 | } | |
b7737c9b | 12474 | |
de6eae1f | 12475 | /* Stop BigMac rx */ |
9380bb9e YR |
12476 | if (!CHIP_IS_E3(bp)) |
12477 | bnx2x_bmac_rx_disable(bp, port); | |
ce7c0489 | 12478 | else { |
9380bb9e | 12479 | bnx2x_xmac_disable(params); |
ce7c0489 YR |
12480 | bnx2x_umac_disable(params); |
12481 | } | |
d231023e | 12482 | /* Disable emac */ |
9380bb9e YR |
12483 | if (!CHIP_IS_E3(bp)) |
12484 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 12485 | |
d231023e | 12486 | usleep_range(10000, 20000); |
25985edc | 12487 | /* The PHY reset is controlled by GPIO 1 |
de6eae1f YR |
12488 | * Hold it as vars low |
12489 | */ | |
d231023e | 12490 | /* Clear link led */ |
ca7b91bb | 12491 | bnx2x_set_mdio_clk(bp, params->chip_id, port); |
7f02c4ad YR |
12492 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
12493 | ||
de6eae1f YR |
12494 | if (reset_ext_phy) { |
12495 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
12496 | phy_index++) { | |
28f4881c YR |
12497 | if (params->phy[phy_index].link_reset) { |
12498 | bnx2x_set_aer_mmd(params, | |
12499 | ¶ms->phy[phy_index]); | |
de6eae1f YR |
12500 | params->phy[phy_index].link_reset( |
12501 | ¶ms->phy[phy_index], | |
12502 | params); | |
28f4881c | 12503 | } |
cf1d972c YR |
12504 | if (params->phy[phy_index].flags & |
12505 | FLAGS_REARM_LATCH_SIGNAL) | |
12506 | clear_latch_ind = 1; | |
b7737c9b | 12507 | } |
b7737c9b YR |
12508 | } |
12509 | ||
cf1d972c YR |
12510 | if (clear_latch_ind) { |
12511 | /* Clear latching indication */ | |
12512 | bnx2x_rearm_latch_signal(bp, port, 0); | |
12513 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, | |
12514 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
12515 | } | |
de6eae1f YR |
12516 | if (params->phy[INT_PHY].link_reset) |
12517 | params->phy[INT_PHY].link_reset( | |
12518 | ¶ms->phy[INT_PHY], params); | |
b7737c9b | 12519 | |
d231023e | 12520 | /* Disable nig ingress interface */ |
9380bb9e | 12521 | if (!CHIP_IS_E3(bp)) { |
d231023e | 12522 | /* Reset BigMac */ |
ce7c0489 YR |
12523 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
12524 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
9380bb9e YR |
12525 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); |
12526 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
ce7c0489 YR |
12527 | } else { |
12528 | u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
12529 | bnx2x_set_xumac_nig(params, 0, 0); | |
12530 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
12531 | MISC_REGISTERS_RESET_REG_2_XMAC) | |
12532 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, | |
12533 | XMAC_CTRL_REG_SOFT_RESET); | |
9380bb9e | 12534 | } |
de6eae1f | 12535 | vars->link_up = 0; |
3c9ada22 | 12536 | vars->phy_flags = 0; |
b7737c9b YR |
12537 | return 0; |
12538 | } | |
12539 | ||
de6eae1f YR |
12540 | /****************************************************************************/ |
12541 | /* Common function */ | |
12542 | /****************************************************************************/ | |
fcf5b650 YR |
12543 | static int bnx2x_8073_common_init_phy(struct bnx2x *bp, |
12544 | u32 shmem_base_path[], | |
12545 | u32 shmem2_base_path[], u8 phy_index, | |
12546 | u32 chip_id) | |
6bbca910 | 12547 | { |
e10bc84d YR |
12548 | struct bnx2x_phy phy[PORT_MAX]; |
12549 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 | 12550 | u16 val; |
c8e64df4 | 12551 | s8 port = 0; |
f2e0899f | 12552 | s8 port_of_path = 0; |
c8e64df4 YR |
12553 | u32 swap_val, swap_override; |
12554 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
12555 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
12556 | port ^= (swap_val && swap_override); | |
12557 | bnx2x_ext_phy_hw_reset(bp, port); | |
6bbca910 YR |
12558 | /* PART1 - Reset both phys */ |
12559 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
12560 | u32 shmem_base, shmem2_base; |
12561 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12562 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12563 | shmem_base = shmem_base_path[0]; |
12564 | shmem2_base = shmem2_base_path[0]; | |
12565 | port_of_path = port; | |
3c9ada22 YR |
12566 | } else { |
12567 | shmem_base = shmem_base_path[port]; | |
12568 | shmem2_base = shmem2_base_path[port]; | |
12569 | port_of_path = 0; | |
f2e0899f DK |
12570 | } |
12571 | ||
6bbca910 | 12572 | /* Extract the ext phy address for the port */ |
a22f0788 | 12573 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12574 | port_of_path, &phy[port]) != |
e10bc84d YR |
12575 | 0) { |
12576 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12577 | return -EINVAL; | |
12578 | } | |
d231023e | 12579 | /* Disable attentions */ |
6a71bbe0 YR |
12580 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12581 | port_of_path*4, | |
cd88ccee YR |
12582 | (NIG_MASK_XGXS0_LINK_STATUS | |
12583 | NIG_MASK_XGXS0_LINK10G | | |
12584 | NIG_MASK_SERDES0_LINK_STATUS | | |
12585 | NIG_MASK_MI_INT)); | |
6bbca910 | 12586 | |
6bbca910 | 12587 | /* Need to take the phy out of low power mode in order |
8f73f0b9 YR |
12588 | * to write to access its registers |
12589 | */ | |
6bbca910 | 12590 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
12591 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12592 | port); | |
6bbca910 YR |
12593 | |
12594 | /* Reset the phy */ | |
e10bc84d | 12595 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee YR |
12596 | MDIO_PMA_DEVAD, |
12597 | MDIO_PMA_REG_CTRL, | |
12598 | 1<<15); | |
6bbca910 YR |
12599 | } |
12600 | ||
12601 | /* Add delay of 150ms after reset */ | |
12602 | msleep(150); | |
12603 | ||
e10bc84d YR |
12604 | if (phy[PORT_0].addr & 0x1) { |
12605 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12606 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12607 | } else { | |
12608 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12609 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12610 | } | |
12611 | ||
6bbca910 YR |
12612 | /* PART2 - Download firmware to both phys */ |
12613 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
3c9ada22 | 12614 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12615 | port_of_path = port; |
3c9ada22 YR |
12616 | else |
12617 | port_of_path = 0; | |
6bbca910 | 12618 | |
f2e0899f DK |
12619 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12620 | phy_blk[port]->addr); | |
5c99274b YR |
12621 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12622 | port_of_path)) | |
6bbca910 | 12623 | return -EINVAL; |
6bbca910 YR |
12624 | |
12625 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 12626 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12627 | MDIO_PMA_DEVAD, |
12628 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 YR |
12629 | |
12630 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 12631 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12632 | MDIO_PMA_DEVAD, |
12633 | MDIO_PMA_REG_TX_POWER_DOWN, | |
12634 | (val | 1<<10)); | |
6bbca910 YR |
12635 | } |
12636 | ||
8f73f0b9 | 12637 | /* Toggle Transmitter: Power down and then up with 600ms delay |
2cf7acf9 YR |
12638 | * between |
12639 | */ | |
6bbca910 YR |
12640 | msleep(600); |
12641 | ||
12642 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
12643 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 12644 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 12645 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 12646 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12647 | MDIO_PMA_DEVAD, |
12648 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 | 12649 | |
e10bc84d | 12650 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12651 | MDIO_PMA_DEVAD, |
12652 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
d231023e | 12653 | usleep_range(15000, 30000); |
6bbca910 YR |
12654 | |
12655 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 12656 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
12657 | MDIO_PMA_DEVAD, |
12658 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 12659 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
12660 | MDIO_PMA_DEVAD, |
12661 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
6bbca910 YR |
12662 | |
12663 | /* set GPIO2 back to LOW */ | |
12664 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 12665 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6bbca910 YR |
12666 | } |
12667 | return 0; | |
6bbca910 | 12668 | } |
fcf5b650 YR |
12669 | static int bnx2x_8726_common_init_phy(struct bnx2x *bp, |
12670 | u32 shmem_base_path[], | |
12671 | u32 shmem2_base_path[], u8 phy_index, | |
12672 | u32 chip_id) | |
de6eae1f YR |
12673 | { |
12674 | u32 val; | |
12675 | s8 port; | |
12676 | struct bnx2x_phy phy; | |
12677 | /* Use port1 because of the static port-swap */ | |
12678 | /* Enable the module detection interrupt */ | |
12679 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
12680 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
12681 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
12682 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
12683 | ||
650154bf | 12684 | bnx2x_ext_phy_hw_reset(bp, 0); |
d231023e | 12685 | usleep_range(5000, 10000); |
de6eae1f | 12686 | for (port = 0; port < PORT_MAX; port++) { |
f2e0899f DK |
12687 | u32 shmem_base, shmem2_base; |
12688 | ||
12689 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12690 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12691 | shmem_base = shmem_base_path[0]; |
12692 | shmem2_base = shmem2_base_path[0]; | |
3c9ada22 YR |
12693 | } else { |
12694 | shmem_base = shmem_base_path[port]; | |
12695 | shmem2_base = shmem2_base_path[port]; | |
f2e0899f | 12696 | } |
de6eae1f | 12697 | /* Extract the ext phy address for the port */ |
a22f0788 | 12698 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
12699 | port, &phy) != |
12700 | 0) { | |
12701 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12702 | return -EINVAL; | |
12703 | } | |
12704 | ||
12705 | /* Reset phy*/ | |
12706 | bnx2x_cl45_write(bp, &phy, | |
12707 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
12708 | ||
12709 | ||
12710 | /* Set fault module detected LED on */ | |
12711 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
cd88ccee YR |
12712 | MISC_REGISTERS_GPIO_HIGH, |
12713 | port); | |
de6eae1f YR |
12714 | } |
12715 | ||
12716 | return 0; | |
12717 | } | |
a8db5b4c YR |
12718 | static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, |
12719 | u8 *io_gpio, u8 *io_port) | |
12720 | { | |
12721 | ||
12722 | u32 phy_gpio_reset = REG_RD(bp, shmem_base + | |
12723 | offsetof(struct shmem_region, | |
12724 | dev_info.port_hw_config[PORT_0].default_cfg)); | |
12725 | switch (phy_gpio_reset) { | |
12726 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: | |
12727 | *io_gpio = 0; | |
12728 | *io_port = 0; | |
12729 | break; | |
12730 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: | |
12731 | *io_gpio = 1; | |
12732 | *io_port = 0; | |
12733 | break; | |
12734 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: | |
12735 | *io_gpio = 2; | |
12736 | *io_port = 0; | |
12737 | break; | |
12738 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: | |
12739 | *io_gpio = 3; | |
12740 | *io_port = 0; | |
12741 | break; | |
12742 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: | |
12743 | *io_gpio = 0; | |
12744 | *io_port = 1; | |
12745 | break; | |
12746 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: | |
12747 | *io_gpio = 1; | |
12748 | *io_port = 1; | |
12749 | break; | |
12750 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: | |
12751 | *io_gpio = 2; | |
12752 | *io_port = 1; | |
12753 | break; | |
12754 | case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: | |
12755 | *io_gpio = 3; | |
12756 | *io_port = 1; | |
12757 | break; | |
12758 | default: | |
12759 | /* Don't override the io_gpio and io_port */ | |
12760 | break; | |
12761 | } | |
12762 | } | |
fcf5b650 YR |
12763 | |
12764 | static int bnx2x_8727_common_init_phy(struct bnx2x *bp, | |
12765 | u32 shmem_base_path[], | |
12766 | u32 shmem2_base_path[], u8 phy_index, | |
12767 | u32 chip_id) | |
4d295db0 | 12768 | { |
a8db5b4c | 12769 | s8 port, reset_gpio; |
4d295db0 | 12770 | u32 swap_val, swap_override; |
e10bc84d YR |
12771 | struct bnx2x_phy phy[PORT_MAX]; |
12772 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 12773 | s8 port_of_path; |
cd88ccee YR |
12774 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
12775 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4d295db0 | 12776 | |
a8db5b4c | 12777 | reset_gpio = MISC_REGISTERS_GPIO_1; |
a22f0788 | 12778 | port = 1; |
4d295db0 | 12779 | |
8f73f0b9 | 12780 | /* Retrieve the reset gpio/port which control the reset. |
a8db5b4c YR |
12781 | * Default is GPIO1, PORT1 |
12782 | */ | |
12783 | bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], | |
12784 | (u8 *)&reset_gpio, (u8 *)&port); | |
a22f0788 YR |
12785 | |
12786 | /* Calculate the port based on port swap */ | |
12787 | port ^= (swap_val && swap_override); | |
12788 | ||
a8db5b4c YR |
12789 | /* Initiate PHY reset*/ |
12790 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
12791 | port); | |
d231023e | 12792 | usleep_range(1000, 2000); |
a8db5b4c YR |
12793 | bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
12794 | port); | |
12795 | ||
d231023e | 12796 | usleep_range(5000, 10000); |
bc7f0a05 | 12797 | |
4d295db0 | 12798 | /* PART1 - Reset both phys */ |
a22f0788 | 12799 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
12800 | u32 shmem_base, shmem2_base; |
12801 | ||
12802 | /* In E2, same phy is using for port0 of the two paths */ | |
3c9ada22 | 12803 | if (CHIP_IS_E1x(bp)) { |
f2e0899f DK |
12804 | shmem_base = shmem_base_path[0]; |
12805 | shmem2_base = shmem2_base_path[0]; | |
12806 | port_of_path = port; | |
3c9ada22 YR |
12807 | } else { |
12808 | shmem_base = shmem_base_path[port]; | |
12809 | shmem2_base = shmem2_base_path[port]; | |
12810 | port_of_path = 0; | |
f2e0899f DK |
12811 | } |
12812 | ||
4d295db0 | 12813 | /* Extract the ext phy address for the port */ |
a22f0788 | 12814 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 12815 | port_of_path, &phy[port]) != |
e10bc84d YR |
12816 | 0) { |
12817 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
12818 | return -EINVAL; | |
12819 | } | |
4d295db0 | 12820 | /* disable attentions */ |
f2e0899f DK |
12821 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
12822 | port_of_path*4, | |
12823 | (NIG_MASK_XGXS0_LINK_STATUS | | |
12824 | NIG_MASK_XGXS0_LINK10G | | |
12825 | NIG_MASK_SERDES0_LINK_STATUS | | |
12826 | NIG_MASK_MI_INT)); | |
4d295db0 | 12827 | |
4d295db0 EG |
12828 | |
12829 | /* Reset the phy */ | |
e10bc84d | 12830 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee | 12831 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4d295db0 EG |
12832 | } |
12833 | ||
12834 | /* Add delay of 150ms after reset */ | |
12835 | msleep(150); | |
e10bc84d YR |
12836 | if (phy[PORT_0].addr & 0x1) { |
12837 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
12838 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
12839 | } else { | |
12840 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
12841 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
12842 | } | |
4d295db0 | 12843 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 12844 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
3c9ada22 | 12845 | if (CHIP_IS_E1x(bp)) |
f2e0899f | 12846 | port_of_path = port; |
3c9ada22 YR |
12847 | else |
12848 | port_of_path = 0; | |
f2e0899f DK |
12849 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
12850 | phy_blk[port]->addr); | |
5c99274b YR |
12851 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
12852 | port_of_path)) | |
4d295db0 | 12853 | return -EINVAL; |
85242eea YR |
12854 | /* Disable PHY transmitter output */ |
12855 | bnx2x_cl45_write(bp, phy_blk[port], | |
12856 | MDIO_PMA_DEVAD, | |
12857 | MDIO_PMA_REG_TX_DISABLE, 1); | |
4d295db0 | 12858 | |
5c99274b | 12859 | } |
4d295db0 EG |
12860 | return 0; |
12861 | } | |
12862 | ||
521683da YR |
12863 | static int bnx2x_84833_common_init_phy(struct bnx2x *bp, |
12864 | u32 shmem_base_path[], | |
12865 | u32 shmem2_base_path[], | |
12866 | u8 phy_index, | |
12867 | u32 chip_id) | |
12868 | { | |
12869 | u8 reset_gpios; | |
521683da YR |
12870 | reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); |
12871 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); | |
12872 | udelay(10); | |
12873 | bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); | |
12874 | DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", | |
12875 | reset_gpios); | |
11b2ec6b YR |
12876 | return 0; |
12877 | } | |
521683da | 12878 | |
11b2ec6b YR |
12879 | static int bnx2x_84833_pre_init_phy(struct bnx2x *bp, |
12880 | struct bnx2x_phy *phy) | |
12881 | { | |
12882 | u16 val, cnt; | |
12883 | /* Wait for FW completing its initialization. */ | |
12884 | for (cnt = 0; cnt < 1500; cnt++) { | |
12885 | bnx2x_cl45_read(bp, phy, | |
521683da YR |
12886 | MDIO_PMA_DEVAD, |
12887 | MDIO_PMA_REG_CTRL, &val); | |
11b2ec6b YR |
12888 | if (!(val & (1<<15))) |
12889 | break; | |
d231023e | 12890 | usleep_range(1000, 2000); |
11b2ec6b YR |
12891 | } |
12892 | if (cnt >= 1500) { | |
12893 | DP(NETIF_MSG_LINK, "84833 reset timeout\n"); | |
12894 | return -EINVAL; | |
521683da YR |
12895 | } |
12896 | ||
11b2ec6b YR |
12897 | /* Put the port in super isolate mode. */ |
12898 | bnx2x_cl45_read(bp, phy, | |
12899 | MDIO_CTL_DEVAD, | |
12900 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); | |
12901 | val |= MDIO_84833_SUPER_ISOLATE; | |
12902 | bnx2x_cl45_write(bp, phy, | |
12903 | MDIO_CTL_DEVAD, | |
12904 | MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); | |
12905 | ||
12906 | /* Save spirom version */ | |
12907 | bnx2x_save_848xx_spirom_version(phy, bp, PORT_0); | |
521683da YR |
12908 | return 0; |
12909 | } | |
12910 | ||
11b2ec6b YR |
12911 | int bnx2x_pre_init_phy(struct bnx2x *bp, |
12912 | u32 shmem_base, | |
12913 | u32 shmem2_base, | |
12914 | u32 chip_id) | |
12915 | { | |
12916 | int rc = 0; | |
12917 | struct bnx2x_phy phy; | |
12918 | bnx2x_set_mdio_clk(bp, chip_id, PORT_0); | |
12919 | if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base, | |
12920 | PORT_0, &phy)) { | |
12921 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
12922 | return -EINVAL; | |
12923 | } | |
12924 | switch (phy.type) { | |
12925 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: | |
12926 | rc = bnx2x_84833_pre_init_phy(bp, &phy); | |
12927 | break; | |
12928 | default: | |
12929 | break; | |
12930 | } | |
12931 | return rc; | |
12932 | } | |
521683da | 12933 | |
fcf5b650 YR |
12934 | static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
12935 | u32 shmem2_base_path[], u8 phy_index, | |
12936 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 | 12937 | { |
fcf5b650 | 12938 | int rc = 0; |
6bbca910 YR |
12939 | |
12940 | switch (ext_phy_type) { | |
12941 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
12942 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
12943 | shmem2_base_path, | |
12944 | phy_index, chip_id); | |
6bbca910 | 12945 | break; |
e4d78f12 | 12946 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: |
4d295db0 EG |
12947 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
12948 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
12949 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
12950 | shmem2_base_path, | |
12951 | phy_index, chip_id); | |
4d295db0 EG |
12952 | break; |
12953 | ||
589abe3a | 12954 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
8f73f0b9 | 12955 | /* GPIO1 affects both ports, so there's need to pull |
2cf7acf9 YR |
12956 | * it for single port alone |
12957 | */ | |
f2e0899f DK |
12958 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
12959 | shmem2_base_path, | |
12960 | phy_index, chip_id); | |
a22f0788 | 12961 | break; |
0d40f0d4 | 12962 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: |
8f73f0b9 | 12963 | /* GPIO3's are linked, and so both need to be toggled |
0d40f0d4 YR |
12964 | * to obtain required 2us pulse. |
12965 | */ | |
521683da YR |
12966 | rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, |
12967 | shmem2_base_path, | |
12968 | phy_index, chip_id); | |
0d40f0d4 | 12969 | break; |
a22f0788 YR |
12970 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: |
12971 | rc = -EINVAL; | |
4f60dab1 | 12972 | break; |
6bbca910 YR |
12973 | default: |
12974 | DP(NETIF_MSG_LINK, | |
2cf7acf9 YR |
12975 | "ext_phy 0x%x common init not required\n", |
12976 | ext_phy_type); | |
6bbca910 YR |
12977 | break; |
12978 | } | |
12979 | ||
d231023e | 12980 | if (rc) |
6d870c39 YR |
12981 | netdev_err(bp->dev, "Warning: PHY was not initialized," |
12982 | " Port %d\n", | |
12983 | 0); | |
6bbca910 YR |
12984 | return rc; |
12985 | } | |
12986 | ||
fcf5b650 YR |
12987 | int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
12988 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 | 12989 | { |
fcf5b650 | 12990 | int rc = 0; |
3c9ada22 YR |
12991 | u32 phy_ver, val; |
12992 | u8 phy_index = 0; | |
a22f0788 | 12993 | u32 ext_phy_type, ext_phy_config; |
a198c142 YR |
12994 | bnx2x_set_mdio_clk(bp, chip_id, PORT_0); |
12995 | bnx2x_set_mdio_clk(bp, chip_id, PORT_1); | |
a22f0788 | 12996 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); |
3c9ada22 YR |
12997 | if (CHIP_IS_E3(bp)) { |
12998 | /* Enable EPIO */ | |
12999 | val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); | |
13000 | REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); | |
13001 | } | |
b21a3424 YR |
13002 | /* Check if common init was already done */ |
13003 | phy_ver = REG_RD(bp, shmem_base_path[0] + | |
13004 | offsetof(struct shmem_region, | |
13005 | port_mb[PORT_0].ext_phy_fw_version)); | |
13006 | if (phy_ver) { | |
13007 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", | |
13008 | phy_ver); | |
13009 | return 0; | |
13010 | } | |
13011 | ||
a22f0788 YR |
13012 | /* Read the ext_phy_type for arbitrary port(0) */ |
13013 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13014 | phy_index++) { | |
13015 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 13016 | shmem_base_path[0], |
a22f0788 YR |
13017 | phy_index, 0); |
13018 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
13019 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
13020 | shmem2_base_path, | |
13021 | phy_index, ext_phy_type, | |
13022 | chip_id); | |
a22f0788 YR |
13023 | } |
13024 | return rc; | |
13025 | } | |
d90d96ba | 13026 | |
3deb8167 YR |
13027 | static void bnx2x_check_over_curr(struct link_params *params, |
13028 | struct link_vars *vars) | |
13029 | { | |
13030 | struct bnx2x *bp = params->bp; | |
13031 | u32 cfg_pin; | |
13032 | u8 port = params->port; | |
13033 | u32 pin_val; | |
13034 | ||
13035 | cfg_pin = (REG_RD(bp, params->shmem_base + | |
13036 | offsetof(struct shmem_region, | |
13037 | dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & | |
13038 | PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> | |
13039 | PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; | |
13040 | ||
13041 | /* Ignore check if no external input PIN available */ | |
13042 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) | |
13043 | return; | |
13044 | ||
13045 | if (!pin_val) { | |
13046 | if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { | |
13047 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
13048 | " been detected and the power to " | |
13049 | "that SFP+ module has been removed" | |
13050 | " to prevent failure of the card." | |
13051 | " Please remove the SFP+ module and" | |
13052 | " restart the system to clear this" | |
13053 | " error.\n", | |
13054 | params->port); | |
13055 | vars->phy_flags |= PHY_OVER_CURRENT_FLAG; | |
13056 | } | |
13057 | } else | |
13058 | vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; | |
13059 | } | |
13060 | ||
d0b8a6f9 YM |
13061 | /* Returns 0 if no change occured since last check; 1 otherwise. */ |
13062 | static u8 bnx2x_analyze_link_error(struct link_params *params, | |
13063 | struct link_vars *vars, u32 status, | |
13064 | u32 phy_flag, u32 link_flag, u8 notify) | |
3deb8167 YR |
13065 | { |
13066 | struct bnx2x *bp = params->bp; | |
13067 | /* Compare new value with previous value */ | |
13068 | u8 led_mode; | |
d0b8a6f9 | 13069 | u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; |
3deb8167 | 13070 | |
d0b8a6f9 YM |
13071 | if ((status ^ old_status) == 0) |
13072 | return 0; | |
3deb8167 YR |
13073 | |
13074 | /* If values differ */ | |
d0b8a6f9 YM |
13075 | switch (phy_flag) { |
13076 | case PHY_HALF_OPEN_CONN_FLAG: | |
13077 | DP(NETIF_MSG_LINK, "Analyze Remote Fault\n"); | |
13078 | break; | |
13079 | case PHY_SFP_TX_FAULT_FLAG: | |
13080 | DP(NETIF_MSG_LINK, "Analyze TX Fault\n"); | |
13081 | break; | |
13082 | default: | |
13083 | DP(NETIF_MSG_LINK, "Analyze UNKOWN\n"); | |
13084 | } | |
13085 | DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, | |
13086 | old_status, status); | |
3deb8167 | 13087 | |
8f73f0b9 | 13088 | /* a. Update shmem->link_status accordingly |
3deb8167 YR |
13089 | * b. Update link_vars->link_up |
13090 | */ | |
d0b8a6f9 | 13091 | if (status) { |
3deb8167 | 13092 | vars->link_status &= ~LINK_STATUS_LINK_UP; |
d0b8a6f9 | 13093 | vars->link_status |= link_flag; |
3deb8167 | 13094 | vars->link_up = 0; |
d0b8a6f9 | 13095 | vars->phy_flags |= phy_flag; |
55098c5c YR |
13096 | |
13097 | /* activate nig drain */ | |
13098 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); | |
8f73f0b9 | 13099 | /* Set LED mode to off since the PHY doesn't know about these |
3deb8167 YR |
13100 | * errors |
13101 | */ | |
13102 | led_mode = LED_MODE_OFF; | |
13103 | } else { | |
13104 | vars->link_status |= LINK_STATUS_LINK_UP; | |
d0b8a6f9 | 13105 | vars->link_status &= ~link_flag; |
3deb8167 | 13106 | vars->link_up = 1; |
d0b8a6f9 | 13107 | vars->phy_flags &= ~phy_flag; |
3deb8167 | 13108 | led_mode = LED_MODE_OPER; |
55098c5c YR |
13109 | |
13110 | /* Clear nig drain */ | |
13111 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
3deb8167 | 13112 | } |
55098c5c | 13113 | bnx2x_sync_link(params, vars); |
3deb8167 YR |
13114 | /* Update the LED according to the link state */ |
13115 | bnx2x_set_led(params, vars, led_mode, SPEED_10000); | |
13116 | ||
13117 | /* Update link status in the shared memory */ | |
13118 | bnx2x_update_mng(params, vars->link_status); | |
13119 | ||
13120 | /* C. Trigger General Attention */ | |
13121 | vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; | |
55098c5c YR |
13122 | if (notify) |
13123 | bnx2x_notify_link_changed(bp); | |
d0b8a6f9 YM |
13124 | |
13125 | return 1; | |
3deb8167 YR |
13126 | } |
13127 | ||
de6f3377 YR |
13128 | /****************************************************************************** |
13129 | * Description: | |
13130 | * This function checks for half opened connection change indication. | |
13131 | * When such change occurs, it calls the bnx2x_analyze_link_error | |
13132 | * to check if Remote Fault is set or cleared. Reception of remote fault | |
13133 | * status message in the MAC indicates that the peer's MAC has detected | |
13134 | * a fault, for example, due to break in the TX side of fiber. | |
13135 | * | |
13136 | ******************************************************************************/ | |
55098c5c YR |
13137 | int bnx2x_check_half_open_conn(struct link_params *params, |
13138 | struct link_vars *vars, | |
13139 | u8 notify) | |
3deb8167 YR |
13140 | { |
13141 | struct bnx2x *bp = params->bp; | |
13142 | u32 lss_status = 0; | |
13143 | u32 mac_base; | |
13144 | /* In case link status is physically up @ 10G do */ | |
55098c5c YR |
13145 | if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || |
13146 | (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) | |
13147 | return 0; | |
3deb8167 | 13148 | |
de6f3377 | 13149 | if (CHIP_IS_E3(bp) && |
3deb8167 | 13150 | (REG_RD(bp, MISC_REG_RESET_REG_2) & |
de6f3377 YR |
13151 | (MISC_REGISTERS_RESET_REG_2_XMAC))) { |
13152 | /* Check E3 XMAC */ | |
8f73f0b9 | 13153 | /* Note that link speed cannot be queried here, since it may be |
de6f3377 YR |
13154 | * zero while link is down. In case UMAC is active, LSS will |
13155 | * simply not be set | |
13156 | */ | |
13157 | mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; | |
13158 | ||
13159 | /* Clear stick bits (Requires rising edge) */ | |
13160 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); | |
13161 | REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, | |
13162 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | | |
13163 | XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); | |
13164 | if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) | |
13165 | lss_status = 1; | |
13166 | ||
d0b8a6f9 YM |
13167 | bnx2x_analyze_link_error(params, vars, lss_status, |
13168 | PHY_HALF_OPEN_CONN_FLAG, | |
13169 | LINK_STATUS_NONE, notify); | |
de6f3377 YR |
13170 | } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & |
13171 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { | |
3deb8167 YR |
13172 | /* Check E1X / E2 BMAC */ |
13173 | u32 lss_status_reg; | |
13174 | u32 wb_data[2]; | |
13175 | mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
13176 | NIG_REG_INGRESS_BMAC0_MEM; | |
13177 | /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ | |
13178 | if (CHIP_IS_E2(bp)) | |
13179 | lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; | |
13180 | else | |
13181 | lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; | |
13182 | ||
13183 | REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); | |
13184 | lss_status = (wb_data[0] > 0); | |
13185 | ||
d0b8a6f9 YM |
13186 | bnx2x_analyze_link_error(params, vars, lss_status, |
13187 | PHY_HALF_OPEN_CONN_FLAG, | |
13188 | LINK_STATUS_NONE, notify); | |
3deb8167 | 13189 | } |
55098c5c | 13190 | return 0; |
3deb8167 | 13191 | } |
d0b8a6f9 YM |
13192 | static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy, |
13193 | struct link_params *params, | |
13194 | struct link_vars *vars) | |
13195 | { | |
13196 | struct bnx2x *bp = params->bp; | |
13197 | u32 cfg_pin, value = 0; | |
13198 | u8 led_change, port = params->port; | |
3deb8167 | 13199 | |
d0b8a6f9 YM |
13200 | /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ |
13201 | cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, | |
13202 | dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & | |
13203 | PORT_HW_CFG_E3_TX_FAULT_MASK) >> | |
13204 | PORT_HW_CFG_E3_TX_FAULT_SHIFT; | |
13205 | ||
13206 | if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { | |
13207 | DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); | |
13208 | return; | |
13209 | } | |
13210 | ||
13211 | led_change = bnx2x_analyze_link_error(params, vars, value, | |
13212 | PHY_SFP_TX_FAULT_FLAG, | |
13213 | LINK_STATUS_SFP_TX_FAULT, 1); | |
13214 | ||
13215 | if (led_change) { | |
13216 | /* Change TX_Fault led, set link status for further syncs */ | |
13217 | u8 led_mode; | |
13218 | ||
13219 | if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { | |
13220 | led_mode = MISC_REGISTERS_GPIO_HIGH; | |
13221 | vars->link_status |= LINK_STATUS_SFP_TX_FAULT; | |
13222 | } else { | |
13223 | led_mode = MISC_REGISTERS_GPIO_LOW; | |
13224 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13225 | } | |
13226 | ||
13227 | /* If module is unapproved, led should be on regardless */ | |
13228 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { | |
13229 | DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", | |
13230 | led_mode); | |
13231 | bnx2x_set_e3_module_fault_led(params, led_mode); | |
13232 | } | |
13233 | } | |
13234 | } | |
3deb8167 YR |
13235 | void bnx2x_period_func(struct link_params *params, struct link_vars *vars) |
13236 | { | |
de6f3377 | 13237 | u16 phy_idx; |
55098c5c | 13238 | struct bnx2x *bp = params->bp; |
de6f3377 YR |
13239 | for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { |
13240 | if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { | |
13241 | bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); | |
55098c5c YR |
13242 | if (bnx2x_check_half_open_conn(params, vars, 1) != |
13243 | 0) | |
13244 | DP(NETIF_MSG_LINK, "Fault detection failed\n"); | |
de6f3377 YR |
13245 | break; |
13246 | } | |
13247 | } | |
13248 | ||
a9077bfd YR |
13249 | if (CHIP_IS_E3(bp)) { |
13250 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
13251 | bnx2x_set_aer_mmd(params, phy); | |
3deb8167 | 13252 | bnx2x_check_over_curr(params, vars); |
d0b8a6f9 YM |
13253 | if (vars->rx_tx_asic_rst) |
13254 | bnx2x_warpcore_config_runtime(phy, params, vars); | |
13255 | ||
13256 | if ((REG_RD(bp, params->shmem_base + | |
13257 | offsetof(struct shmem_region, dev_info. | |
13258 | port_hw_config[params->port].default_cfg)) | |
13259 | & PORT_HW_CFG_NET_SERDES_IF_MASK) == | |
13260 | PORT_HW_CFG_NET_SERDES_IF_SFI) { | |
13261 | if (bnx2x_is_sfp_module_plugged(phy, params)) { | |
13262 | bnx2x_sfp_tx_fault_detection(phy, params, vars); | |
13263 | } else if (vars->link_status & | |
13264 | LINK_STATUS_SFP_TX_FAULT) { | |
13265 | /* Clean trail, interrupt corrects the leds */ | |
13266 | vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; | |
13267 | vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; | |
13268 | /* Update link status in the shared memory */ | |
13269 | bnx2x_update_mng(params, vars->link_status); | |
13270 | } | |
13271 | } | |
13272 | ||
a9077bfd YR |
13273 | } |
13274 | ||
3deb8167 YR |
13275 | } |
13276 | ||
a22f0788 | 13277 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) |
d90d96ba YR |
13278 | { |
13279 | u8 phy_index; | |
13280 | struct bnx2x_phy phy; | |
13281 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
13282 | phy_index++) { | |
a22f0788 | 13283 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
13284 | 0, &phy) != 0) { |
13285 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13286 | return 0; | |
13287 | } | |
13288 | ||
13289 | if (phy.flags & FLAGS_HW_LOCK_REQUIRED) | |
13290 | return 1; | |
13291 | } | |
13292 | return 0; | |
13293 | } | |
13294 | ||
13295 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, | |
13296 | u32 shmem_base, | |
a22f0788 | 13297 | u32 shmem2_base, |
d90d96ba YR |
13298 | u8 port) |
13299 | { | |
13300 | u8 phy_index, fan_failure_det_req = 0; | |
13301 | struct bnx2x_phy phy; | |
13302 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13303 | phy_index++) { | |
a22f0788 | 13304 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
13305 | port, &phy) |
13306 | != 0) { | |
13307 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13308 | return 0; | |
13309 | } | |
13310 | fan_failure_det_req |= (phy.flags & | |
13311 | FLAGS_FAN_FAILURE_DET_REQ); | |
13312 | } | |
13313 | return fan_failure_det_req; | |
13314 | } | |
13315 | ||
13316 | void bnx2x_hw_reset_phy(struct link_params *params) | |
13317 | { | |
13318 | u8 phy_index; | |
985848f8 YR |
13319 | struct bnx2x *bp = params->bp; |
13320 | bnx2x_update_mng(params, 0); | |
13321 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
13322 | (NIG_MASK_XGXS0_LINK_STATUS | | |
13323 | NIG_MASK_XGXS0_LINK10G | | |
13324 | NIG_MASK_SERDES0_LINK_STATUS | | |
13325 | NIG_MASK_MI_INT)); | |
13326 | ||
13327 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
d90d96ba YR |
13328 | phy_index++) { |
13329 | if (params->phy[phy_index].hw_reset) { | |
13330 | params->phy[phy_index].hw_reset( | |
13331 | ¶ms->phy[phy_index], | |
13332 | params); | |
13333 | params->phy[phy_index] = phy_null; | |
13334 | } | |
13335 | } | |
13336 | } | |
020c7e3f YR |
13337 | |
13338 | void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, | |
13339 | u32 chip_id, u32 shmem_base, u32 shmem2_base, | |
13340 | u8 port) | |
13341 | { | |
13342 | u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; | |
13343 | u32 val; | |
13344 | u32 offset, aeu_mask, swap_val, swap_override, sync_offset; | |
3c9ada22 YR |
13345 | if (CHIP_IS_E3(bp)) { |
13346 | if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, | |
13347 | shmem_base, | |
13348 | port, | |
13349 | &gpio_num, | |
13350 | &gpio_port) != 0) | |
13351 | return; | |
13352 | } else { | |
020c7e3f YR |
13353 | struct bnx2x_phy phy; |
13354 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
13355 | phy_index++) { | |
13356 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, | |
13357 | shmem2_base, port, &phy) | |
13358 | != 0) { | |
13359 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
13360 | return; | |
13361 | } | |
13362 | if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { | |
13363 | gpio_num = MISC_REGISTERS_GPIO_3; | |
13364 | gpio_port = port; | |
13365 | break; | |
13366 | } | |
13367 | } | |
13368 | } | |
13369 | ||
13370 | if (gpio_num == 0xff) | |
13371 | return; | |
13372 | ||
13373 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ | |
13374 | bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); | |
13375 | ||
13376 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
13377 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
13378 | gpio_port ^= (swap_val && swap_override); | |
13379 | ||
13380 | vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << | |
13381 | (gpio_num + (gpio_port << 2)); | |
13382 | ||
13383 | sync_offset = shmem_base + | |
13384 | offsetof(struct shmem_region, | |
13385 | dev_info.port_hw_config[port].aeu_int_mask); | |
13386 | REG_WR(bp, sync_offset, vars->aeu_int_mask); | |
13387 | ||
13388 | DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", | |
13389 | gpio_num, gpio_port, vars->aeu_int_mask); | |
13390 | ||
13391 | if (port == 0) | |
13392 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
13393 | else | |
13394 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
13395 | ||
13396 | /* Open appropriate AEU for interrupts */ | |
13397 | aeu_mask = REG_RD(bp, offset); | |
13398 | aeu_mask |= vars->aeu_int_mask; | |
13399 | REG_WR(bp, offset, aeu_mask); | |
13400 | ||
13401 | /* Enable the GPIO to trigger interrupt */ | |
13402 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
13403 | val |= 1 << (gpio_num + (gpio_port << 2)); | |
13404 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
13405 | } |