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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / ethernet / amd / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
13ff83b9
JP		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
1da177e4 26#define DRV_NAME "pcnet32"
01935d7d
DF		 27#define DRV_VERSION "1.35"
28#define DRV_RELDATE "21.Apr.2008"
1da177e4
LT		 29#define PFX DRV_NAME ": "
30
4a5e8e29
JG		 31static const char *const version =
32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 33
34#include <linux/module.h>
35#include <linux/kernel.h>
d43c36dc 36#include <linux/sched.h>
1da177e4
LT		 37#include <linux/string.h>
38#include <linux/errno.h>
39#include <linux/ioport.h>
40#include <linux/slab.h>
41#include <linux/interrupt.h>
42#include <linux/pci.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/ethtool.h>
46#include <linux/mii.h>
47#include <linux/crc32.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
1f044931 50#include <linux/if_ether.h>
1da177e4
LT		 51#include <linux/skbuff.h>
52#include <linux/spinlock.h>
53#include <linux/moduleparam.h>
54#include <linux/bitops.h>
9e3f8063
JP		 55#include <linux/io.h>
56#include <linux/uaccess.h>
1da177e4
LT		 57
58#include <asm/dma.h>
1da177e4
LT		 59#include <asm/irq.h>
60
61/*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
a3aa1884 64static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = {
f2622a2b
DF		 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
f2622a2b
DF		 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 74
75 { } /* terminate list */
1da177e4
LT		 76};
77
4a5e8e29 78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 79
80static int cards_found;
81
82/*
83 * VLB I/O addresses
84 */
aa02bc70 85static unsigned int pcnet32_portlist[] =
4a5e8e29 86 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4 87
9e3f8063 88static int pcnet32_debug;
4a5e8e29
JG		 89static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 91
92static struct net_device *pcnet32_dev;
93
94static int max_interrupt_work = 2;
95static int rx_copybreak = 200;
96
97#define PCNET32_PORT_AUI 0x00
98#define PCNET32_PORT_10BT 0x01
99#define PCNET32_PORT_GPSI 0x02
100#define PCNET32_PORT_MII 0x03
101
102#define PCNET32_PORT_PORTSEL 0x03
103#define PCNET32_PORT_ASEL 0x04
104#define PCNET32_PORT_100 0x40
105#define PCNET32_PORT_FD 0x80
106
107#define PCNET32_DMA_MASK 0xffffffff
108
109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112/*
113 * table to translate option values from tulip
114 * to internal options
115 */
f71e1309 116static const unsigned char options_mapping[] = {
4a5e8e29
JG		 117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 134};
135
136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 137 "Loopback test (offline)"
1da177e4 138};
4a5e8e29 139
4c3616cd 140#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
1da177e4 141
ac62ef04 142#define PCNET32_NUM_REGS 136
1da177e4 143
4a5e8e29 144#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 145static int options[MAX_UNITS];
146static int full_duplex[MAX_UNITS];
147static int homepna[MAX_UNITS];
148
149/*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
1da177e4
LT		 159/*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 165#define PCNET32_LOG_TX_BUFFERS 4
166#define PCNET32_LOG_RX_BUFFERS 5
167#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 169#endif
170
171#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 172#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 173
174#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 175#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4 176
232c5640
DF		 177#define PKT_BUF_SKB 1544
178/* actual buffer length after being aligned */
179#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
180/* chip wants twos complement of the (aligned) buffer length */
181#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
1da177e4
LT		 182
183/* Offsets from base I/O address. */
184#define PCNET32_WIO_RDP 0x10
185#define PCNET32_WIO_RAP 0x12
186#define PCNET32_WIO_RESET 0x14
187#define PCNET32_WIO_BDP 0x16
188
189#define PCNET32_DWIO_RDP 0x10
190#define PCNET32_DWIO_RAP 0x14
191#define PCNET32_DWIO_RESET 0x18
192#define PCNET32_DWIO_BDP 0x1C
193
194#define PCNET32_TOTAL_SIZE 0x20
195
06c87850
DF		 196#define CSR0 0
197#define CSR0_INIT 0x1
198#define CSR0_START 0x2
199#define CSR0_STOP 0x4
200#define CSR0_TXPOLL 0x8
201#define CSR0_INTEN 0x40
202#define CSR0_IDON 0x0100
203#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
204#define PCNET32_INIT_LOW 1
205#define PCNET32_INIT_HIGH 2
206#define CSR3 3
207#define CSR4 4
208#define CSR5 5
209#define CSR5_SUSPEND 0x0001
210#define CSR15 15
211#define PCNET32_MC_FILTER 8
212
8d916266
DF		 213#define PCNET32_79C970A 0x2621
214
1da177e4
LT		 215/* The PCNET32 Rx and Tx ring descriptors. */
216struct pcnet32_rx_head {
3e33545b
AV		 217 __le32 base;
218 __le16 buf_length; /* two`s complement of length */
219 __le16 status;
220 __le32 msg_length;
221 __le32 reserved;
1da177e4
LT		 222};
223
224struct pcnet32_tx_head {
3e33545b
AV		 225 __le32 base;
226 __le16 length; /* two`s complement of length */
227 __le16 status;
228 __le32 misc;
229 __le32 reserved;
1da177e4
LT		 230};
231
232/* The PCNET32 32-Bit initialization block, described in databook. */
233struct pcnet32_init_block {
3e33545b
AV		 234 __le16 mode;
235 __le16 tlen_rlen;
0b5bf225 236 u8 phys_addr[6];
3e33545b
AV		 237 __le16 reserved;
238 __le32 filter[2];
4a5e8e29 239 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 240 __le32 rx_ring;
241 __le32 tx_ring;
1da177e4
LT		 242};
243
244/* PCnet32 access functions */
245struct pcnet32_access {
4a5e8e29
JG		 246 u16 (*read_csr) (unsigned long, int);
247 void (*write_csr) (unsigned long, int, u16);
248 u16 (*read_bcr) (unsigned long, int);
249 void (*write_bcr) (unsigned long, int, u16);
250 u16 (*read_rap) (unsigned long);
251 void (*write_rap) (unsigned long, u16);
252 void (*reset) (unsigned long);
1da177e4
LT		 253};
254
255/*
76209926
HWL		 256 * The first field of pcnet32_private is read by the ethernet device
257 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 258 */
259struct pcnet32_private {
6ecb7667 260 struct pcnet32_init_block *init_block;
4a5e8e29 261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 262 struct pcnet32_rx_head *rx_ring;
263 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
265 returned by pci_alloc_consistent */
0b5bf225
JG		 266 struct pci_dev *pci_dev;
267 const char *name;
4a5e8e29 268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 269 struct sk_buff **tx_skbuff;
270 struct sk_buff **rx_skbuff;
271 dma_addr_t *tx_dma_addr;
272 dma_addr_t *rx_dma_addr;
1d70cb06 273 const struct pcnet32_access *a;
0b5bf225
JG		 274 spinlock_t lock; /* Guard lock */
275 unsigned int cur_rx, cur_tx; /* The next free ring entry */
276 unsigned int rx_ring_size; /* current rx ring size */
277 unsigned int tx_ring_size; /* current tx ring size */
278 unsigned int rx_mod_mask; /* rx ring modular mask */
279 unsigned int tx_mod_mask; /* tx ring modular mask */
280 unsigned short rx_len_bits;
281 unsigned short tx_len_bits;
282 dma_addr_t rx_ring_dma_addr;
283 dma_addr_t tx_ring_dma_addr;
284 unsigned int dirty_rx, /* ring entries to be freed. */
285 dirty_tx;
286
bea3348e
SH		 287 struct net_device *dev;
288 struct napi_struct napi;
0b5bf225
JG		 289 char tx_full;
290 char phycount; /* number of phys found */
291 int options;
292 unsigned int shared_irq:1, /* shared irq possible */
293 dxsuflo:1, /* disable transmit stop on uflo */
294 mii:1; /* mii port available */
295 struct net_device *next;
296 struct mii_if_info mii_if;
297 struct timer_list watchdog_timer;
0b5bf225 298 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 299
300 /* each bit indicates an available PHY */
0b5bf225 301 u32 phymask;
8d916266 302 unsigned short chip_version; /* which variant this is */
9871acf6 303
304 /* saved registers during ethtool blink */
305 u16 save_regs[4];
1da177e4
LT		 306};
307
4a5e8e29
JG		 308static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
309static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
310static int pcnet32_open(struct net_device *);
311static int pcnet32_init_ring(struct net_device *);
61357325
SH		 312static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
313 struct net_device *);
4a5e8e29 314static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 315static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 316static int pcnet32_close(struct net_device *);
1da177e4
LT		 317static struct net_device_stats *pcnet32_get_stats(struct net_device *);
318static void pcnet32_load_multicast(struct net_device *dev);
319static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 320static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 321static void pcnet32_watchdog(struct net_device *);
322static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 323static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
324 int val);
1da177e4
LT		 325static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
326static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 327 struct ethtool_test *eth_test, u64 * data);
328static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 329static int pcnet32_get_regs_len(struct net_device *dev);
330static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 331 void *ptr);
1bcd3153 332static void pcnet32_purge_tx_ring(struct net_device *dev);
b166cfba 333static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
eabf0415 334static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 335static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 336
4a5e8e29 337static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 338{
4a5e8e29
JG		 339 outw(index, addr + PCNET32_WIO_RAP);
340 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 341}
342
4a5e8e29 343static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 344{
4a5e8e29
JG		 345 outw(index, addr + PCNET32_WIO_RAP);
346 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 347}
348
4a5e8e29 349static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 350{
4a5e8e29
JG		 351 outw(index, addr + PCNET32_WIO_RAP);
352 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 353}
354
4a5e8e29 355static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 356{
4a5e8e29
JG		 357 outw(index, addr + PCNET32_WIO_RAP);
358 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 359}
360
4a5e8e29 361static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 362{
4a5e8e29 363 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 364}
365
4a5e8e29 366static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 367{
4a5e8e29 368 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 369}
370
4a5e8e29 371static void pcnet32_wio_reset(unsigned long addr)
1da177e4 372{
4a5e8e29 373 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 374}
375
4a5e8e29 376static int pcnet32_wio_check(unsigned long addr)
1da177e4 377{
4a5e8e29 378 outw(88, addr + PCNET32_WIO_RAP);
807540ba 379 return inw(addr + PCNET32_WIO_RAP) == 88;
1da177e4
LT		 380}
381
1d70cb06 382static const struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 383 .read_csr = pcnet32_wio_read_csr,
384 .write_csr = pcnet32_wio_write_csr,
385 .read_bcr = pcnet32_wio_read_bcr,
386 .write_bcr = pcnet32_wio_write_bcr,
387 .read_rap = pcnet32_wio_read_rap,
388 .write_rap = pcnet32_wio_write_rap,
389 .reset = pcnet32_wio_reset
1da177e4
LT		 390};
391
4a5e8e29 392static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 393{
4a5e8e29 394 outl(index, addr + PCNET32_DWIO_RAP);
9e3f8063 395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
1da177e4
LT		 396}
397
4a5e8e29 398static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 399{
4a5e8e29
JG		 400 outl(index, addr + PCNET32_DWIO_RAP);
401 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 402}
403
4a5e8e29 404static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 405{
4a5e8e29 406 outl(index, addr + PCNET32_DWIO_RAP);
9e3f8063 407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
1da177e4
LT		 408}
409
4a5e8e29 410static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 411{
4a5e8e29
JG		 412 outl(index, addr + PCNET32_DWIO_RAP);
413 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 414}
415
4a5e8e29 416static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 417{
9e3f8063 418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
1da177e4
LT		 419}
420
4a5e8e29 421static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 422{
4a5e8e29 423 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 424}
425
4a5e8e29 426static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 427{
4a5e8e29 428 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 429}
430
4a5e8e29 431static int pcnet32_dwio_check(unsigned long addr)
1da177e4 432{
4a5e8e29 433 outl(88, addr + PCNET32_DWIO_RAP);
807540ba 434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
1da177e4
LT		 435}
436
1d70cb06 437static const struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 438 .read_csr = pcnet32_dwio_read_csr,
439 .write_csr = pcnet32_dwio_write_csr,
440 .read_bcr = pcnet32_dwio_read_bcr,
441 .write_bcr = pcnet32_dwio_write_bcr,
442 .read_rap = pcnet32_dwio_read_rap,
443 .write_rap = pcnet32_dwio_write_rap,
444 .reset = pcnet32_dwio_reset
1da177e4
LT		 445};
446
06c87850
DF		 447static void pcnet32_netif_stop(struct net_device *dev)
448{
bea3348e 449 struct pcnet32_private *lp = netdev_priv(dev);
01935d7d 450
1ae5dc34 451 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 452 napi_disable(&lp->napi);
06c87850
DF		 453 netif_tx_disable(dev);
454}
455
456static void pcnet32_netif_start(struct net_device *dev)
457{
bea3348e 458 struct pcnet32_private *lp = netdev_priv(dev);
d1d08d12
DM		 459 ulong ioaddr = dev->base_addr;
460 u16 val;
01935d7d 461
06c87850 462 netif_wake_queue(dev);
1d70cb06 463 val = lp->a->read_csr(ioaddr, CSR3);
d1d08d12 464 val &= 0x00ff;
1d70cb06 465 lp->a->write_csr(ioaddr, CSR3, val);
bea3348e 466 napi_enable(&lp->napi);
06c87850
DF		 467}
468
469/*
470 * Allocate space for the new sized tx ring.
471 * Free old resources
472 * Save new resources.
473 * Any failure keeps old resources.
474 * Must be called with lp->lock held.
475 */
476static void pcnet32_realloc_tx_ring(struct net_device *dev,
477 struct pcnet32_private *lp,
478 unsigned int size)
479{
480 dma_addr_t new_ring_dma_addr;
481 dma_addr_t *new_dma_addr_list;
482 struct pcnet32_tx_head *new_tx_ring;
483 struct sk_buff **new_skb_list;
484
485 pcnet32_purge_tx_ring(dev);
486
487 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
488 sizeof(struct pcnet32_tx_head) *
489 (1 << size),
490 &new_ring_dma_addr);
491 if (new_tx_ring == NULL) {
13ff83b9 492 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
06c87850
DF		 493 return;
494 }
495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
496
14f8dc49
JP		 497 new_dma_addr_list = kcalloc(1 << size, sizeof(dma_addr_t),
498 GFP_ATOMIC);
499 if (!new_dma_addr_list)
06c87850 500 goto free_new_tx_ring;
06c87850 501
14f8dc49
JP		 502 new_skb_list = kcalloc(1 << size, sizeof(struct sk_buff *),
503 GFP_ATOMIC);
504 if (!new_skb_list)
06c87850 505 goto free_new_lists;
06c87850
DF		 506
507 kfree(lp->tx_skbuff);
508 kfree(lp->tx_dma_addr);
509 pci_free_consistent(lp->pci_dev,
510 sizeof(struct pcnet32_tx_head) *
511 lp->tx_ring_size, lp->tx_ring,
512 lp->tx_ring_dma_addr);
513
514 lp->tx_ring_size = (1 << size);
515 lp->tx_mod_mask = lp->tx_ring_size - 1;
516 lp->tx_len_bits = (size << 12);
517 lp->tx_ring = new_tx_ring;
518 lp->tx_ring_dma_addr = new_ring_dma_addr;
519 lp->tx_dma_addr = new_dma_addr_list;
520 lp->tx_skbuff = new_skb_list;
521 return;
522
9e3f8063 523free_new_lists:
06c87850 524 kfree(new_dma_addr_list);
9e3f8063 525free_new_tx_ring:
06c87850
DF		 526 pci_free_consistent(lp->pci_dev,
527 sizeof(struct pcnet32_tx_head) *
528 (1 << size),
529 new_tx_ring,
530 new_ring_dma_addr);
06c87850
DF		 531}
532
533/*
534 * Allocate space for the new sized rx ring.
535 * Re-use old receive buffers.
536 * alloc extra buffers
537 * free unneeded buffers
538 * free unneeded buffers
539 * Save new resources.
540 * Any failure keeps old resources.
541 * Must be called with lp->lock held.
542 */
543static void pcnet32_realloc_rx_ring(struct net_device *dev,
544 struct pcnet32_private *lp,
545 unsigned int size)
546{
547 dma_addr_t new_ring_dma_addr;
548 dma_addr_t *new_dma_addr_list;
549 struct pcnet32_rx_head *new_rx_ring;
550 struct sk_buff **new_skb_list;
551 int new, overlap;
552
553 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
554 sizeof(struct pcnet32_rx_head) *
555 (1 << size),
556 &new_ring_dma_addr);
557 if (new_rx_ring == NULL) {
13ff83b9 558 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
06c87850
DF		 559 return;
560 }
561 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
562
14f8dc49
JP		 563 new_dma_addr_list = kcalloc(1 << size, sizeof(dma_addr_t), GFP_ATOMIC);
564 if (!new_dma_addr_list)
06c87850 565 goto free_new_rx_ring;
06c87850 566
14f8dc49
JP		 567 new_skb_list = kcalloc(1 << size, sizeof(struct sk_buff *),
568 GFP_ATOMIC);
569 if (!new_skb_list)
06c87850 570 goto free_new_lists;
06c87850
DF		 571
572 /* first copy the current receive buffers */
573 overlap = min(size, lp->rx_ring_size);
574 for (new = 0; new < overlap; new++) {
575 new_rx_ring[new] = lp->rx_ring[new];
576 new_dma_addr_list[new] = lp->rx_dma_addr[new];
577 new_skb_list[new] = lp->rx_skbuff[new];
578 }
579 /* now allocate any new buffers needed */
9e3f8063 580 for (; new < size; new++) {
06c87850 581 struct sk_buff *rx_skbuff;
1d266430 582 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
9e3f8063
JP		 583 rx_skbuff = new_skb_list[new];
584 if (!rx_skbuff) {
06c87850 585 /* keep the original lists and buffers */
1d266430 586 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
13ff83b9 587 __func__);
06c87850
DF		 588 goto free_all_new;
589 }
232c5640 590 skb_reserve(rx_skbuff, NET_IP_ALIGN);
06c87850
DF		 591
592 new_dma_addr_list[new] =
593 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 594 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 595 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
232c5640 596 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
3e33545b 597 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 598 }
599 /* and free any unneeded buffers */
600 for (; new < lp->rx_ring_size; new++) {
601 if (lp->rx_skbuff[new]) {
602 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
232c5640 603 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 604 dev_kfree_skb(lp->rx_skbuff[new]);
605 }
606 }
607
608 kfree(lp->rx_skbuff);
609 kfree(lp->rx_dma_addr);
610 pci_free_consistent(lp->pci_dev,
611 sizeof(struct pcnet32_rx_head) *
612 lp->rx_ring_size, lp->rx_ring,
613 lp->rx_ring_dma_addr);
614
615 lp->rx_ring_size = (1 << size);
616 lp->rx_mod_mask = lp->rx_ring_size - 1;
617 lp->rx_len_bits = (size << 4);
618 lp->rx_ring = new_rx_ring;
619 lp->rx_ring_dma_addr = new_ring_dma_addr;
620 lp->rx_dma_addr = new_dma_addr_list;
621 lp->rx_skbuff = new_skb_list;
622 return;
623
9e3f8063
JP		 624free_all_new:
625 while (--new >= lp->rx_ring_size) {
06c87850
DF		 626 if (new_skb_list[new]) {
627 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
232c5640 628 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 629 dev_kfree_skb(new_skb_list[new]);
630 }
631 }
632 kfree(new_skb_list);
9e3f8063 633free_new_lists:
06c87850 634 kfree(new_dma_addr_list);
9e3f8063 635free_new_rx_ring:
06c87850
DF		 636 pci_free_consistent(lp->pci_dev,
637 sizeof(struct pcnet32_rx_head) *
638 (1 << size),
639 new_rx_ring,
640 new_ring_dma_addr);
06c87850
DF		 641}
642
ac5bfe40
DF		 643static void pcnet32_purge_rx_ring(struct net_device *dev)
644{
1e56a4b4 645 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 646 int i;
647
648 /* free all allocated skbuffs */
649 for (i = 0; i < lp->rx_ring_size; i++) {
650 lp->rx_ring[i].status = 0; /* CPU owns buffer */
651 wmb(); /* Make sure adapter sees owner change */
652 if (lp->rx_skbuff[i]) {
653 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
232c5640 654 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
ac5bfe40
DF		 655 dev_kfree_skb_any(lp->rx_skbuff[i]);
656 }
657 lp->rx_skbuff[i] = NULL;
658 lp->rx_dma_addr[i] = 0;
659 }
660}
661
1da177e4
LT		 662#ifdef CONFIG_NET_POLL_CONTROLLER
663static void pcnet32_poll_controller(struct net_device *dev)
664{
4a5e8e29 665 disable_irq(dev->irq);
7d12e780 666 pcnet32_interrupt(0, dev);
4a5e8e29 667 enable_irq(dev->irq);
1da177e4
LT		 668}
669#endif
670
1da177e4
LT		 671static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
672{
1e56a4b4 673 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 674 unsigned long flags;
675 int r = -EOPNOTSUPP;
1da177e4 676
4a5e8e29
JG		 677 if (lp->mii) {
678 spin_lock_irqsave(&lp->lock, flags);
679 mii_ethtool_gset(&lp->mii_if, cmd);
680 spin_unlock_irqrestore(&lp->lock, flags);
681 r = 0;
682 }
683 return r;
1da177e4
LT		 684}
685
686static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
687{
1e56a4b4 688 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 689 unsigned long flags;
690 int r = -EOPNOTSUPP;
1da177e4 691
4a5e8e29
JG		 692 if (lp->mii) {
693 spin_lock_irqsave(&lp->lock, flags);
694 r = mii_ethtool_sset(&lp->mii_if, cmd);
695 spin_unlock_irqrestore(&lp->lock, flags);
696 }
697 return r;
1da177e4
LT		 698}
699
4a5e8e29
JG		 700static void pcnet32_get_drvinfo(struct net_device *dev,
701 struct ethtool_drvinfo *info)
1da177e4 702{
1e56a4b4 703 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 704
23020ab3
RJ		 705 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
706 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
4a5e8e29 707 if (lp->pci_dev)
23020ab3
RJ		 708 strlcpy(info->bus_info, pci_name(lp->pci_dev),
709 sizeof(info->bus_info));
4a5e8e29 710 else
23020ab3
RJ		 711 snprintf(info->bus_info, sizeof(info->bus_info),
712 "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 713}
714
715static u32 pcnet32_get_link(struct net_device *dev)
716{
1e56a4b4 717 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 718 unsigned long flags;
719 int r;
1da177e4 720
4a5e8e29
JG		 721 spin_lock_irqsave(&lp->lock, flags);
722 if (lp->mii) {
723 r = mii_link_ok(&lp->mii_if);
8d916266 724 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29 725 ulong ioaddr = dev->base_addr; /* card base I/O address */
1d70cb06 726 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 727 } else { /* can not detect link on really old chips */
728 r = 1;
4a5e8e29
JG		 729 }
730 spin_unlock_irqrestore(&lp->lock, flags);
731
732 return r;
1da177e4
LT		 733}
734
735static u32 pcnet32_get_msglevel(struct net_device *dev)
736{
1e56a4b4 737 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 738 return lp->msg_enable;
1da177e4
LT		 739}
740
741static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
742{
1e56a4b4 743 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 744 lp->msg_enable = value;
1da177e4
LT		 745}
746
747static int pcnet32_nway_reset(struct net_device *dev)
748{
1e56a4b4 749 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 750 unsigned long flags;
751 int r = -EOPNOTSUPP;
1da177e4 752
4a5e8e29
JG		 753 if (lp->mii) {
754 spin_lock_irqsave(&lp->lock, flags);
755 r = mii_nway_restart(&lp->mii_if);
756 spin_unlock_irqrestore(&lp->lock, flags);
757 }
758 return r;
1da177e4
LT		 759}
760
4a5e8e29
JG		 761static void pcnet32_get_ringparam(struct net_device *dev,
762 struct ethtool_ringparam *ering)
1da177e4 763{
1e56a4b4 764 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 765
6dcd60c2
DF		 766 ering->tx_max_pending = TX_MAX_RING_SIZE;
767 ering->tx_pending = lp->tx_ring_size;
768 ering->rx_max_pending = RX_MAX_RING_SIZE;
769 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 770}
771
4a5e8e29
JG		 772static int pcnet32_set_ringparam(struct net_device *dev,
773 struct ethtool_ringparam *ering)
eabf0415 774{
1e56a4b4 775 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 776 unsigned long flags;
06c87850
DF		 777 unsigned int size;
778 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 779 int i;
780
781 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
782 return -EINVAL;
783
784 if (netif_running(dev))
06c87850 785 pcnet32_netif_stop(dev);
4a5e8e29
JG		 786
787 spin_lock_irqsave(&lp->lock, flags);
1d70cb06 788 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
06c87850
DF		 789
790 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 791
792 /* set the minimum ring size to 4, to allow the loopback test to work
793 * unchanged.
794 */
795 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 796 if (size <= (1 << i))
4a5e8e29
JG		 797 break;
798 }
06c87850
DF		 799 if ((1 << i) != lp->tx_ring_size)
800 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 801
06c87850 802 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 803 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 804 if (size <= (1 << i))
4a5e8e29
JG		 805 break;
806 }
06c87850
DF		 807 if ((1 << i) != lp->rx_ring_size)
808 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 809
bea3348e 810 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 811
812 if (netif_running(dev)) {
813 pcnet32_netif_start(dev);
814 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 815 }
eabf0415 816
4a5e8e29 817 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 818
13ff83b9
JP		 819 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
820 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 821
4a5e8e29 822 return 0;
1da177e4
LT		 823}
824
4a5e8e29 825static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
9e3f8063 826 u8 *data)
1da177e4 827{
4a5e8e29 828 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 829}
830
b9f2c044 831static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 832{
b9f2c044
JG		 833 switch (sset) {
834 case ETH_SS_TEST:
835 return PCNET32_TEST_LEN;
836 default:
837 return -EOPNOTSUPP;
838 }
1da177e4
LT		 839}
840
841static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 842 struct ethtool_test *test, u64 * data)
1da177e4 843{
1e56a4b4 844 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 845 int rc;
846
847 if (test->flags == ETH_TEST_FL_OFFLINE) {
848 rc = pcnet32_loopback_test(dev, data);
849 if (rc) {
13ff83b9
JP		 850 netif_printk(lp, hw, KERN_DEBUG, dev,
851 "Loopback test failed\n");
4a5e8e29 852 test->flags |= ETH_TEST_FL_FAILED;
13ff83b9
JP		 853 } else
854 netif_printk(lp, hw, KERN_DEBUG, dev,
855 "Loopback test passed\n");
856 } else
857 netif_printk(lp, hw, KERN_DEBUG, dev,
858 "No tests to run (specify 'Offline' on ethtool)\n");
4a5e8e29 859} /* end pcnet32_ethtool_test */
1da177e4 860
4a5e8e29 861static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 862{
1e56a4b4 863 struct pcnet32_private *lp = netdev_priv(dev);
1d70cb06 864 const struct pcnet32_access *a = lp->a; /* access to registers */
4a5e8e29
JG		 865 ulong ioaddr = dev->base_addr; /* card base I/O address */
866 struct sk_buff *skb; /* sk buff */
867 int x, i; /* counters */
868 int numbuffs = 4; /* number of TX/RX buffers and descs */
869 u16 status = 0x8300; /* TX ring status */
3e33545b 870 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 871 int rc; /* return code */
872 int size; /* size of packets */
873 unsigned char *packet; /* source packet data */
874 static const int data_len = 60; /* length of source packets */
875 unsigned long flags;
876 unsigned long ticks;
877
4a5e8e29
JG		 878 rc = 1; /* default to fail */
879
880 if (netif_running(dev))
7de745e5 881 pcnet32_netif_stop(dev);
4a5e8e29
JG		 882
883 spin_lock_irqsave(&lp->lock, flags);
1d70cb06 884 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
ac5bfe40
DF		 885
886 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 887
888 /* Reset the PCNET32 */
1d70cb06 889 lp->a->reset(ioaddr);
890 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 891
892 /* switch pcnet32 to 32bit mode */
1d70cb06 893 lp->a->write_bcr(ioaddr, 20, 2);
4a5e8e29 894
4a5e8e29
JG		 895 /* purge & init rings but don't actually restart */
896 pcnet32_restart(dev, 0x0000);
897
1d70cb06 898 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 899
900 /* Initialize Transmit buffers. */
901 size = data_len + 15;
902 for (x = 0; x < numbuffs; x++) {
1d266430 903 skb = netdev_alloc_skb(dev, size);
9e3f8063 904 if (!skb) {
13ff83b9
JP		 905 netif_printk(lp, hw, KERN_DEBUG, dev,
906 "Cannot allocate skb at line: %d!\n",
907 __LINE__);
4a5e8e29 908 goto clean_up;
4a5e8e29 909 }
9e3f8063
JP		 910 packet = skb->data;
911 skb_put(skb, size); /* create space for data */
912 lp->tx_skbuff[x] = skb;
913 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
914 lp->tx_ring[x].misc = 0;
915
916 /* put DA and SA into the skb */
917 for (i = 0; i < 6; i++)
918 *packet++ = dev->dev_addr[i];
919 for (i = 0; i < 6; i++)
920 *packet++ = dev->dev_addr[i];
921 /* type */
922 *packet++ = 0x08;
923 *packet++ = 0x06;
924 /* packet number */
925 *packet++ = x;
926 /* fill packet with data */
927 for (i = 0; i < data_len; i++)
928 *packet++ = i;
929
930 lp->tx_dma_addr[x] =
931 pci_map_single(lp->pci_dev, skb->data, skb->len,
932 PCI_DMA_TODEVICE);
933 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
934 wmb(); /* Make sure owner changes after all others are visible */
935 lp->tx_ring[x].status = cpu_to_le16(status);
1da177e4 936 }
1da177e4 937
ac5bfe40
DF		 938 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
939 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 940
ac5bfe40
DF		 941 /* set int loopback in CSR15 */
942 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1d70cb06 943 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 944
3e33545b 945 teststatus = cpu_to_le16(0x8000);
1d70cb06 946 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 947
948 /* Check status of descriptors */
949 for (x = 0; x < numbuffs; x++) {
950 ticks = 0;
951 rmb();
952 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
953 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 954 msleep(1);
4a5e8e29
JG		 955 spin_lock_irqsave(&lp->lock, flags);
956 rmb();
957 ticks++;
958 }
959 if (ticks == 200) {
13ff83b9 960 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
4a5e8e29
JG		 961 break;
962 }
963 }
964
1d70cb06 965 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 966 wmb();
967 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
13ff83b9 968 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
4a5e8e29
JG		 969
970 for (x = 0; x < numbuffs; x++) {
13ff83b9 971 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
4a5e8e29 972 skb = lp->rx_skbuff[x];
9e3f8063 973 for (i = 0; i < size; i++)
13ff83b9 974 pr_cont(" %02x", *(skb->data + i));
13ff83b9 975 pr_cont("\n");
4a5e8e29
JG		 976 }
977 }
1da177e4 978
4a5e8e29
JG		 979 x = 0;
980 rc = 0;
981 while (x < numbuffs && !rc) {
982 skb = lp->rx_skbuff[x];
983 packet = lp->tx_skbuff[x]->data;
984 for (i = 0; i < size; i++) {
985 if (*(skb->data + i) != packet[i]) {
13ff83b9
JP		 986 netif_printk(lp, hw, KERN_DEBUG, dev,
987 "Error in compare! %2x - %02x %02x\n",
988 i, *(skb->data + i), packet[i]);
4a5e8e29
JG		 989 rc = 1;
990 break;
991 }
992 }
993 x++;
994 }
1da177e4 995
9e3f8063 996clean_up:
ac5bfe40 997 *data1 = rc;
4a5e8e29 998 pcnet32_purge_tx_ring(dev);
1da177e4 999
ac5bfe40
DF		 1000 x = a->read_csr(ioaddr, CSR15);
1001 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1002
ac5bfe40
DF		 1003 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1004 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1005
7de745e5
DF		 1006 if (netif_running(dev)) {
1007 pcnet32_netif_start(dev);
1008 pcnet32_restart(dev, CSR0_NORMAL);
1009 } else {
1010 pcnet32_purge_rx_ring(dev);
1d70cb06 1011 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
7de745e5
DF		 1012 }
1013 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29 1014
9e3f8063 1015 return rc;
4a5e8e29 1016} /* end pcnet32_loopback_test */
1da177e4 1017
9871acf6 1018static int pcnet32_set_phys_id(struct net_device *dev,
1019 enum ethtool_phys_id_state state)
1da177e4 1020{
1e56a4b4 1021 struct pcnet32_private *lp = netdev_priv(dev);
1d70cb06 1022 const struct pcnet32_access *a = lp->a;
4a5e8e29
JG		 1023 ulong ioaddr = dev->base_addr;
1024 unsigned long flags;
1025 int i;
1026
9871acf6 1027 switch (state) {
1028 case ETHTOOL_ID_ACTIVE:
1029 /* Save the current value of the bcrs */
1030 spin_lock_irqsave(&lp->lock, flags);
1031 for (i = 4; i < 8; i++)
1032 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1033 spin_unlock_irqrestore(&lp->lock, flags);
fce55922 1034 return 2; /* cycle on/off twice per second */
1da177e4 1035
9871acf6 1036 case ETHTOOL_ID_ON:
1037 case ETHTOOL_ID_OFF:
1038 /* Blink the led */
1039 spin_lock_irqsave(&lp->lock, flags);
1040 for (i = 4; i < 8; i++)
1041 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1042 spin_unlock_irqrestore(&lp->lock, flags);
1043 break;
4a5e8e29 1044
9871acf6 1045 case ETHTOOL_ID_INACTIVE:
1046 /* Restore the original value of the bcrs */
1047 spin_lock_irqsave(&lp->lock, flags);
1048 for (i = 4; i < 8; i++)
1049 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1050 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29 1051 }
4a5e8e29 1052 return 0;
1da177e4
LT		 1053}
1054
df27f4a6
DF		 1055/*
1056 * lp->lock must be held.
1057 */
1058static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1059 int can_sleep)
1060{
1061 int csr5;
1e56a4b4 1062 struct pcnet32_private *lp = netdev_priv(dev);
1d70cb06 1063 const struct pcnet32_access *a = lp->a;
df27f4a6
DF		 1064 ulong ioaddr = dev->base_addr;
1065 int ticks;
1066
8d916266
DF		 1067 /* really old chips have to be stopped. */
1068 if (lp->chip_version < PCNET32_79C970A)
1069 return 0;
1070
df27f4a6
DF		 1071 /* set SUSPEND (SPND) - CSR5 bit 0 */
1072 csr5 = a->read_csr(ioaddr, CSR5);
1073 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1074
1075 /* poll waiting for bit to be set */
1076 ticks = 0;
1077 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1078 spin_unlock_irqrestore(&lp->lock, *flags);
1079 if (can_sleep)
1080 msleep(1);
1081 else
1082 mdelay(1);
1083 spin_lock_irqsave(&lp->lock, *flags);
1084 ticks++;
1085 if (ticks > 200) {
13ff83b9
JP		 1086 netif_printk(lp, hw, KERN_DEBUG, dev,
1087 "Error getting into suspend!\n");
df27f4a6
DF		 1088 return 0;
1089 }
1090 }
1091 return 1;
1092}
1093
3904c324
DF		 1094/*
1095 * process one receive descriptor entry
1096 */
1097
1098static void pcnet32_rx_entry(struct net_device *dev,
1099 struct pcnet32_private *lp,
1100 struct pcnet32_rx_head *rxp,
1101 int entry)
1102{
1103 int status = (short)le16_to_cpu(rxp->status) >> 8;
1104 int rx_in_place = 0;
1105 struct sk_buff *skb;
1106 short pkt_len;
1107
1108 if (status != 0x03) { /* There was an error. */
1109 /*
1110 * There is a tricky error noted by John Murphy,
1111 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1112 * buffers it's possible for a jabber packet to use two
1113 * buffers, with only the last correctly noting the error.
1114 */
1115 if (status & 0x01) /* Only count a general error at the */
4f1e5ba0 1116 dev->stats.rx_errors++; /* end of a packet. */
3904c324 1117 if (status & 0x20)
4f1e5ba0 1118 dev->stats.rx_frame_errors++;
3904c324 1119 if (status & 0x10)
4f1e5ba0 1120 dev->stats.rx_over_errors++;
3904c324 1121 if (status & 0x08)
4f1e5ba0 1122 dev->stats.rx_crc_errors++;
3904c324 1123 if (status & 0x04)
4f1e5ba0 1124 dev->stats.rx_fifo_errors++;
3904c324
DF		 1125 return;
1126 }
1127
1128 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1129
1130 /* Discard oversize frames. */
232c5640 1131 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
13ff83b9
JP		 1132 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1133 pkt_len);
4f1e5ba0 1134 dev->stats.rx_errors++;
3904c324
DF		 1135 return;
1136 }
1137 if (pkt_len < 60) {
13ff83b9 1138 netif_err(lp, rx_err, dev, "Runt packet!\n");
4f1e5ba0 1139 dev->stats.rx_errors++;
3904c324
DF		 1140 return;
1141 }
1142
1143 if (pkt_len > rx_copybreak) {
1144 struct sk_buff *newskb;
1145
1d266430 1146 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
9e3f8063 1147 if (newskb) {
232c5640 1148 skb_reserve(newskb, NET_IP_ALIGN);
3904c324
DF		 1149 skb = lp->rx_skbuff[entry];
1150 pci_unmap_single(lp->pci_dev,
1151 lp->rx_dma_addr[entry],
232c5640 1152 PKT_BUF_SIZE,
3904c324
DF		 1153 PCI_DMA_FROMDEVICE);
1154 skb_put(skb, pkt_len);
1155 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1156 lp->rx_dma_addr[entry] =
1157 pci_map_single(lp->pci_dev,
1158 newskb->data,
232c5640 1159 PKT_BUF_SIZE,
3904c324 1160 PCI_DMA_FROMDEVICE);
3e33545b 1161 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1162 rx_in_place = 1;
1163 } else
1164 skb = NULL;
9e3f8063 1165 } else
1d266430 1166 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
3904c324
DF		 1167
1168 if (skb == NULL) {
4f1e5ba0 1169 dev->stats.rx_dropped++;
3904c324
DF		 1170 return;
1171 }
3904c324 1172 if (!rx_in_place) {
232c5640 1173 skb_reserve(skb, NET_IP_ALIGN);
3904c324
DF		 1174 skb_put(skb, pkt_len); /* Make room */
1175 pci_dma_sync_single_for_cpu(lp->pci_dev,
1176 lp->rx_dma_addr[entry],
b2cbbd8e 1177 pkt_len,
3904c324 1178 PCI_DMA_FROMDEVICE);
8c7b7faa 1179 skb_copy_to_linear_data(skb,
3904c324 1180 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1181 pkt_len);
3904c324
DF		 1182 pci_dma_sync_single_for_device(lp->pci_dev,
1183 lp->rx_dma_addr[entry],
b2cbbd8e 1184 pkt_len,
3904c324
DF		 1185 PCI_DMA_FROMDEVICE);
1186 }
4f1e5ba0 1187 dev->stats.rx_bytes += skb->len;
3904c324 1188 skb->protocol = eth_type_trans(skb, dev);
7de745e5 1189 netif_receive_skb(skb);
4f1e5ba0 1190 dev->stats.rx_packets++;
3904c324
DF		 1191}
1192
bea3348e 1193static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1194{
1e56a4b4 1195 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1196 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1197 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1198 int npackets = 0;
9691edd2
DF		 1199
1200 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1201 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1202 pcnet32_rx_entry(dev, lp, rxp, entry);
1203 npackets += 1;
9691edd2 1204 /*
3904c324
DF		 1205 * The docs say that the buffer length isn't touched, but Andrew
1206 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1207 */
232c5640 1208 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
3904c324 1209 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1210 rxp->status = cpu_to_le16(0x8000);
9691edd2 1211 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1212 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1213 }
1214
7de745e5 1215 return npackets;
9691edd2
DF		 1216}
1217
7de745e5 1218static int pcnet32_tx(struct net_device *dev)
9691edd2 1219{
1e56a4b4 1220 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1221 unsigned int dirty_tx = lp->dirty_tx;
1222 int delta;
1223 int must_restart = 0;
1224
1225 while (dirty_tx != lp->cur_tx) {
1226 int entry = dirty_tx & lp->tx_mod_mask;
1227 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1228
1229 if (status < 0)
1230 break; /* It still hasn't been Txed */
1231
1232 lp->tx_ring[entry].base = 0;
1233
1234 if (status & 0x4000) {
3904c324 1235 /* There was a major error, log it. */
9691edd2 1236 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
4f1e5ba0 1237 dev->stats.tx_errors++;
13ff83b9
JP		 1238 netif_err(lp, tx_err, dev,
1239 "Tx error status=%04x err_status=%08x\n",
1240 status, err_status);
9691edd2 1241 if (err_status & 0x04000000)
4f1e5ba0 1242 dev->stats.tx_aborted_errors++;
9691edd2 1243 if (err_status & 0x08000000)
4f1e5ba0 1244 dev->stats.tx_carrier_errors++;
9691edd2 1245 if (err_status & 0x10000000)
4f1e5ba0 1246 dev->stats.tx_window_errors++;
9691edd2
DF		 1247#ifndef DO_DXSUFLO
1248 if (err_status & 0x40000000) {
4f1e5ba0 1249 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1250 /* Ackk! On FIFO errors the Tx unit is turned off! */
1251 /* Remove this verbosity later! */
13ff83b9 1252 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
9691edd2
DF		 1253 must_restart = 1;
1254 }
1255#else
1256 if (err_status & 0x40000000) {
4f1e5ba0 1257 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1258 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1259 /* Ackk! On FIFO errors the Tx unit is turned off! */
1260 /* Remove this verbosity later! */
13ff83b9 1261 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
9691edd2
DF		 1262 must_restart = 1;
1263 }
1264 }
1265#endif
1266 } else {
1267 if (status & 0x1800)
4f1e5ba0
DF		 1268 dev->stats.collisions++;
1269 dev->stats.tx_packets++;
9691edd2
DF		 1270 }
1271
1272 /* We must free the original skb */
1273 if (lp->tx_skbuff[entry]) {
1274 pci_unmap_single(lp->pci_dev,
1275 lp->tx_dma_addr[entry],
1276 lp->tx_skbuff[entry]->
1277 len, PCI_DMA_TODEVICE);
3904c324 1278 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1279 lp->tx_skbuff[entry] = NULL;
1280 lp->tx_dma_addr[entry] = 0;
1281 }
1282 dirty_tx++;
1283 }
1284
3904c324 1285 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2 1286 if (delta > lp->tx_ring_size) {
13ff83b9
JP		 1287 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1288 dirty_tx, lp->cur_tx, lp->tx_full);
9691edd2
DF		 1289 dirty_tx += lp->tx_ring_size;
1290 delta -= lp->tx_ring_size;
1291 }
1292
1293 if (lp->tx_full &&
1294 netif_queue_stopped(dev) &&
1295 delta < lp->tx_ring_size - 2) {
1296 /* The ring is no longer full, clear tbusy. */
1297 lp->tx_full = 0;
1298 netif_wake_queue(dev);
1299 }
1300 lp->dirty_tx = dirty_tx;
1301
1302 return must_restart;
1303}
1304
bea3348e 1305static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1306{
bea3348e
SH		 1307 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1308 struct net_device *dev = lp->dev;
7de745e5
DF		 1309 unsigned long ioaddr = dev->base_addr;
1310 unsigned long flags;
bea3348e 1311 int work_done;
7de745e5
DF		 1312 u16 val;
1313
bea3348e 1314 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1315
1316 spin_lock_irqsave(&lp->lock, flags);
1317 if (pcnet32_tx(dev)) {
1318 /* reset the chip to clear the error condition, then restart */
1d70cb06 1319 lp->a->reset(ioaddr);
1320 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
7de745e5
DF		 1321 pcnet32_restart(dev, CSR0_START);
1322 netif_wake_queue(dev);
1323 }
1324 spin_unlock_irqrestore(&lp->lock, flags);
1325
bea3348e
SH		 1326 if (work_done < budget) {
1327 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1328
288379f0 1329 __napi_complete(napi);
7de745e5 1330
bea3348e 1331 /* clear interrupt masks */
1d70cb06 1332 val = lp->a->read_csr(ioaddr, CSR3);
bea3348e 1333 val &= 0x00ff;
1d70cb06 1334 lp->a->write_csr(ioaddr, CSR3, val);
7de745e5 1335
bea3348e 1336 /* Set interrupt enable. */
1d70cb06 1337 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
ce105a08 1338
bea3348e
SH		 1339 spin_unlock_irqrestore(&lp->lock, flags);
1340 }
1341 return work_done;
7de745e5 1342}
7de745e5 1343
ac62ef04
DF		 1344#define PCNET32_REGS_PER_PHY 32
1345#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1346static int pcnet32_get_regs_len(struct net_device *dev)
1347{
1e56a4b4 1348 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1349 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1350
9e3f8063 1351 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1da177e4
LT		 1352}
1353
1354static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1355 void *ptr)
1da177e4 1356{
4a5e8e29
JG		 1357 int i, csr0;
1358 u16 *buff = ptr;
1e56a4b4 1359 struct pcnet32_private *lp = netdev_priv(dev);
1d70cb06 1360 const struct pcnet32_access *a = lp->a;
4a5e8e29 1361 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1362 unsigned long flags;
1363
1364 spin_lock_irqsave(&lp->lock, flags);
1365
df27f4a6
DF		 1366 csr0 = a->read_csr(ioaddr, CSR0);
1367 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1368 pcnet32_suspend(dev, &flags, 1);
1da177e4 1369
4a5e8e29
JG		 1370 /* read address PROM */
1371 for (i = 0; i < 16; i += 2)
1372 *buff++ = inw(ioaddr + i);
1373
1374 /* read control and status registers */
9e3f8063 1375 for (i = 0; i < 90; i++)
4a5e8e29 1376 *buff++ = a->read_csr(ioaddr, i);
4a5e8e29
JG		 1377
1378 *buff++ = a->read_csr(ioaddr, 112);
1379 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1380
4a5e8e29 1381 /* read bus configuration registers */
9e3f8063 1382 for (i = 0; i < 30; i++)
4a5e8e29 1383 *buff++ = a->read_bcr(ioaddr, i);
9e3f8063 1384
4a5e8e29 1385 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
9e3f8063
JP		 1386
1387 for (i = 31; i < 36; i++)
4a5e8e29 1388 *buff++ = a->read_bcr(ioaddr, i);
4a5e8e29
JG		 1389
1390 /* read mii phy registers */
1391 if (lp->mii) {
1392 int j;
1393 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1394 if (lp->phymask & (1 << j)) {
1395 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1d70cb06 1396 lp->a->write_bcr(ioaddr, 33,
4a5e8e29 1397 (j << 5) | i);
1d70cb06 1398 *buff++ = lp->a->read_bcr(ioaddr, 34);
4a5e8e29
JG		 1399 }
1400 }
1401 }
1402 }
1403
df27f4a6
DF		 1404 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1405 int csr5;
1406
4a5e8e29 1407 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1408 csr5 = a->read_csr(ioaddr, CSR5);
1409 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1410 }
1411
1412 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1413}
1414
7282d491 1415static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1416 .get_settings = pcnet32_get_settings,
1417 .set_settings = pcnet32_set_settings,
1418 .get_drvinfo = pcnet32_get_drvinfo,
1419 .get_msglevel = pcnet32_get_msglevel,
1420 .set_msglevel = pcnet32_set_msglevel,
1421 .nway_reset = pcnet32_nway_reset,
1422 .get_link = pcnet32_get_link,
1423 .get_ringparam = pcnet32_get_ringparam,
1424 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1425 .get_strings = pcnet32_get_strings,
4a5e8e29 1426 .self_test = pcnet32_ethtool_test,
9871acf6 1427 .set_phys_id = pcnet32_set_phys_id,
4a5e8e29
JG		 1428 .get_regs_len = pcnet32_get_regs_len,
1429 .get_regs = pcnet32_get_regs,
b9f2c044 1430 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1431};
1432
1433/* only probes for non-PCI devices, the rest are handled by
1434 * pci_register_driver via pcnet32_probe_pci */
1435
a9590879 1436static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1437{
4a5e8e29
JG		 1438 unsigned int *port, ioaddr;
1439
1440 /* search for PCnet32 VLB cards at known addresses */
1441 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1442 if (request_region
1443 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1444 /* check if there is really a pcnet chip on that ioaddr */
8e95a202
JP		 1445 if ((inb(ioaddr + 14) == 0x57) &&
1446 (inb(ioaddr + 15) == 0x57)) {
4a5e8e29
JG		 1447 pcnet32_probe1(ioaddr, 0, NULL);
1448 } else {
1449 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1450 }
1451 }
1452 }
1da177e4
LT		 1453}
1454
a9590879 1455static int
1da177e4
LT		 1456pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1457{
4a5e8e29
JG		 1458 unsigned long ioaddr;
1459 int err;
1460
1461 err = pci_enable_device(pdev);
1462 if (err < 0) {
1463 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1464 pr_err("failed to enable device -- err=%d\n", err);
4a5e8e29
JG		 1465 return err;
1466 }
1467 pci_set_master(pdev);
1468
1469 ioaddr = pci_resource_start(pdev, 0);
1470 if (!ioaddr) {
1471 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1472 pr_err("card has no PCI IO resources, aborting\n");
4a5e8e29
JG		 1473 return -ENODEV;
1474 }
1da177e4 1475
4a5e8e29
JG		 1476 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1477 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1478 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
4a5e8e29
JG		 1479 return -ENODEV;
1480 }
9e3f8063 1481 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
4a5e8e29 1482 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1483 pr_err("io address range already allocated\n");
4a5e8e29
JG		 1484 return -EBUSY;
1485 }
1da177e4 1486
4a5e8e29 1487 err = pcnet32_probe1(ioaddr, 1, pdev);
9e3f8063 1488 if (err < 0)
4a5e8e29 1489 pci_disable_device(pdev);
9e3f8063 1490
4a5e8e29 1491 return err;
1da177e4
LT		 1492}
1493
3bc124dd
SH		 1494static const struct net_device_ops pcnet32_netdev_ops = {
1495 .ndo_open = pcnet32_open,
1496 .ndo_stop = pcnet32_close,
1497 .ndo_start_xmit = pcnet32_start_xmit,
1498 .ndo_tx_timeout = pcnet32_tx_timeout,
1499 .ndo_get_stats = pcnet32_get_stats,
afc4b13d 1500 .ndo_set_rx_mode = pcnet32_set_multicast_list,
3bc124dd
SH		 1501 .ndo_do_ioctl = pcnet32_ioctl,
1502 .ndo_change_mtu = eth_change_mtu,
1503 .ndo_set_mac_address = eth_mac_addr,
1504 .ndo_validate_addr = eth_validate_addr,
1505#ifdef CONFIG_NET_POLL_CONTROLLER
1506 .ndo_poll_controller = pcnet32_poll_controller,
1507#endif
1508};
1509
1da177e4
LT		 1510/* pcnet32_probe1
1511 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1512 * pdev will be NULL when called from pcnet32_probe_vlbus.
1513 */
a9590879 1514static int
1da177e4
LT		 1515pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1516{
4a5e8e29 1517 struct pcnet32_private *lp;
4a5e8e29 1518 int i, media;
70913149 1519 int fdx, mii, fset, dxsuflo, sram;
4a5e8e29
JG		 1520 int chip_version;
1521 char *chipname;
1522 struct net_device *dev;
1d70cb06 1523 const struct pcnet32_access *a = NULL;
4a5e8e29
JG		 1524 u8 promaddr[6];
1525 int ret = -ENODEV;
1526
1527 /* reset the chip */
1528 pcnet32_wio_reset(ioaddr);
1529
1530 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1531 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1532 a = &pcnet32_wio;
1533 } else {
1534 pcnet32_dwio_reset(ioaddr);
8e95a202
JP		 1535 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1536 pcnet32_dwio_check(ioaddr)) {
4a5e8e29 1537 a = &pcnet32_dwio;
df4e7f72
DF		 1538 } else {
1539 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1540 pr_err("No access methods\n");
4a5e8e29 1541 goto err_release_region;
df4e7f72 1542 }
4a5e8e29
JG		 1543 }
1544
1545 chip_version =
1546 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1547 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
13ff83b9 1548 pr_info(" PCnet chip version is %#x\n", chip_version);
4a5e8e29
JG		 1549 if ((chip_version & 0xfff) != 0x003) {
1550 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1551 pr_info("Unsupported chip version\n");
4a5e8e29
JG		 1552 goto err_release_region;
1553 }
1554
1555 /* initialize variables */
70913149 1556 fdx = mii = fset = dxsuflo = sram = 0;
4a5e8e29
JG		 1557 chip_version = (chip_version >> 12) & 0xffff;
1558
1559 switch (chip_version) {
1560 case 0x2420:
1561 chipname = "PCnet/PCI 79C970"; /* PCI */
1562 break;
1563 case 0x2430:
1564 if (shared)
1565 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1566 else
1567 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1568 break;
1569 case 0x2621:
1570 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1571 fdx = 1;
1572 break;
1573 case 0x2623:
1574 chipname = "PCnet/FAST 79C971"; /* PCI */
1575 fdx = 1;
1576 mii = 1;
1577 fset = 1;
1578 break;
1579 case 0x2624:
1580 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1581 fdx = 1;
1582 mii = 1;
1583 fset = 1;
1584 break;
1585 case 0x2625:
1586 chipname = "PCnet/FAST III 79C973"; /* PCI */
1587 fdx = 1;
1588 mii = 1;
70913149 1589 sram = 1;
4a5e8e29
JG		 1590 break;
1591 case 0x2626:
1592 chipname = "PCnet/Home 79C978"; /* PCI */
1593 fdx = 1;
1594 /*
1595 * This is based on specs published at www.amd.com. This section
1596 * assumes that a card with a 79C978 wants to go into standard
1597 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1598 * and the module option homepna=1 can select this instead.
1599 */
1600 media = a->read_bcr(ioaddr, 49);
1601 media &= ~3; /* default to 10Mb ethernet */
1602 if (cards_found < MAX_UNITS && homepna[cards_found])
1603 media |= 1; /* switch to home wiring mode */
1604 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1605 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
4a5e8e29
JG		 1606 (media & 1) ? "1" : "10");
1607 a->write_bcr(ioaddr, 49, media);
1608 break;
1609 case 0x2627:
1610 chipname = "PCnet/FAST III 79C975"; /* PCI */
1611 fdx = 1;
1612 mii = 1;
70913149 1613 sram = 1;
4a5e8e29
JG		 1614 break;
1615 case 0x2628:
1616 chipname = "PCnet/PRO 79C976";
1617 fdx = 1;
1618 mii = 1;
1619 break;
1620 default:
1621 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9
JP		 1622 pr_info("PCnet version %#x, no PCnet32 chip\n",
1623 chip_version);
4a5e8e29
JG		 1624 goto err_release_region;
1625 }
1626
1da177e4 1627 /*
4a5e8e29
JG		 1628 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1629 * starting until the packet is loaded. Strike one for reliability, lose
25985edc 1630 * one for latency - although on PCI this isn't a big loss. Older chips
4a5e8e29
JG		 1631 * have FIFO's smaller than a packet, so you can't do this.
1632 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1633 */
4a5e8e29
JG		 1634
1635 if (fset) {
1636 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1637 a->write_csr(ioaddr, 80,
1638 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1639 dxsuflo = 1;
1640 }
1641
70913149
MC		 1642 /*
1643 * The Am79C973/Am79C975 controllers come with 12K of SRAM
1644 * which we can use for the Tx/Rx buffers but most importantly,
1645 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1646 * Tx fifo underflows.
1647 */
1648 if (sram) {
1649 /*
1650 * The SRAM is being configured in two steps. First we
1651 * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1652 * to the datasheet, each bit corresponds to a 512-byte
1653 * page so we can have at most 24 pages. The SRAM_SIZE
1654 * holds the value of the upper 8 bits of the 16-bit SRAM size.
1655 * The low 8-bits start at 0x00 and end at 0xff. So the
1656 * address range is from 0x0000 up to 0x17ff. Therefore,
1657 * the SRAM_SIZE is set to 0x17. The next step is to set
1658 * the BCR26:SRAM_BND midway through so the Tx and Rx
1659 * buffers can share the SRAM equally.
1660 */
1661 a->write_bcr(ioaddr, 25, 0x17);
1662 a->write_bcr(ioaddr, 26, 0xc);
1663 /* And finally enable the NOUFLO bit */
1664 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1665 }
1666
6ecb7667 1667 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29 1668 if (!dev) {
4a5e8e29
JG		 1669 ret = -ENOMEM;
1670 goto err_release_region;
1671 }
63097b3a
DF		 1672
1673 if (pdev)
1674 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29 1675
1da177e4 1676 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1677 pr_info("%s at %#3lx,", chipname, ioaddr);
4a5e8e29
JG		 1678
1679 /* In most chips, after a chip reset, the ethernet address is read from the
1680 * station address PROM at the base address and programmed into the
1681 * "Physical Address Registers" CSR12-14.
1682 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1683 * they disagree with the CSRs. If they miscompare, and the PROM addr
1684 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1685 */
1686 for (i = 0; i < 3; i++) {
1687 unsigned int val;
1688 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1689 /* There may be endianness issues here. */
1690 dev->dev_addr[2 * i] = val & 0x0ff;
1691 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1692 }
1693
1694 /* read PROM address and compare with CSR address */
1da177e4 1695 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1696 promaddr[i] = inb(ioaddr + i);
1697
8e95a202
JP		 1698 if (memcmp(promaddr, dev->dev_addr, 6) ||
1699 !is_valid_ether_addr(dev->dev_addr)) {
4a5e8e29
JG		 1700 if (is_valid_ether_addr(promaddr)) {
1701 if (pcnet32_debug & NETIF_MSG_PROBE) {
13ff83b9
JP		 1702 pr_cont(" warning: CSR address invalid,\n");
1703 pr_info(" using instead PROM address of");
4a5e8e29
JG		 1704 }
1705 memcpy(dev->dev_addr, promaddr, 6);
1706 }
1707 }
4a5e8e29
JG		 1708
1709 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
aaeb6cdf 1710 if (!is_valid_ether_addr(dev->dev_addr))
1f044931 1711 memset(dev->dev_addr, 0, ETH_ALEN);
4a5e8e29
JG		 1712
1713 if (pcnet32_debug & NETIF_MSG_PROBE) {
13ff83b9 1714 pr_cont(" %pM", dev->dev_addr);
4a5e8e29
JG		 1715
1716 /* Version 0x2623 and 0x2624 */
1717 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1718 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
13ff83b9 1719 pr_info(" tx_start_pt(0x%04x):", i);
4a5e8e29
JG		 1720 switch (i >> 10) {
1721 case 0:
13ff83b9 1722 pr_cont(" 20 bytes,");
4a5e8e29
JG		 1723 break;
1724 case 1:
13ff83b9 1725 pr_cont(" 64 bytes,");
4a5e8e29
JG		 1726 break;
1727 case 2:
13ff83b9 1728 pr_cont(" 128 bytes,");
4a5e8e29
JG		 1729 break;
1730 case 3:
13ff83b9 1731 pr_cont("~220 bytes,");
4a5e8e29
JG		 1732 break;
1733 }
1734 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
13ff83b9 1735 pr_cont(" BCR18(%x):", i & 0xffff);
4a5e8e29 1736 if (i & (1 << 5))
13ff83b9 1737 pr_cont("BurstWrEn ");
4a5e8e29 1738 if (i & (1 << 6))
13ff83b9 1739 pr_cont("BurstRdEn ");
4a5e8e29 1740 if (i & (1 << 7))
13ff83b9 1741 pr_cont("DWordIO ");
4a5e8e29 1742 if (i & (1 << 11))
13ff83b9 1743 pr_cont("NoUFlow ");
4a5e8e29 1744 i = a->read_bcr(ioaddr, 25);
13ff83b9 1745 pr_info(" SRAMSIZE=0x%04x,", i << 8);
4a5e8e29 1746 i = a->read_bcr(ioaddr, 26);
13ff83b9 1747 pr_cont(" SRAM_BND=0x%04x,", i << 8);
4a5e8e29
JG		 1748 i = a->read_bcr(ioaddr, 27);
1749 if (i & (1 << 14))
13ff83b9 1750 pr_cont("LowLatRx");
4a5e8e29
JG		 1751 }
1752 }
1753
1754 dev->base_addr = ioaddr;
1e56a4b4 1755 lp = netdev_priv(dev);
4a5e8e29 1756 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
9e3f8063
JP		 1757 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1758 &lp->init_dma_addr);
1759 if (!lp->init_block) {
4a5e8e29 1760 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1761 pr_err("Consistent memory allocation failed\n");
4a5e8e29
JG		 1762 ret = -ENOMEM;
1763 goto err_free_netdev;
1764 }
4a5e8e29
JG		 1765 lp->pci_dev = pdev;
1766
bea3348e
SH		 1767 lp->dev = dev;
1768
4a5e8e29
JG		 1769 spin_lock_init(&lp->lock);
1770
4a5e8e29
JG		 1771 lp->name = chipname;
1772 lp->shared_irq = shared;
1773 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1774 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1775 lp->tx_mod_mask = lp->tx_ring_size - 1;
1776 lp->rx_mod_mask = lp->rx_ring_size - 1;
1777 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1778 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1779 lp->mii_if.full_duplex = fdx;
1780 lp->mii_if.phy_id_mask = 0x1f;
1781 lp->mii_if.reg_num_mask = 0x1f;
1782 lp->dxsuflo = dxsuflo;
1783 lp->mii = mii;
8d916266 1784 lp->chip_version = chip_version;
4a5e8e29 1785 lp->msg_enable = pcnet32_debug;
8e95a202
JP		 1786 if ((cards_found >= MAX_UNITS) ||
1787 (options[cards_found] >= sizeof(options_mapping)))
4a5e8e29
JG		 1788 lp->options = PCNET32_PORT_ASEL;
1789 else
1790 lp->options = options_mapping[options[cards_found]];
1791 lp->mii_if.dev = dev;
1792 lp->mii_if.mdio_read = mdio_read;
1793 lp->mii_if.mdio_write = mdio_write;
1794
feff348f
DF		 1795 /* napi.weight is used in both the napi and non-napi cases */
1796 lp->napi.weight = lp->rx_ring_size / 2;
1797
bea3348e 1798 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
bea3348e 1799
4a5e8e29
JG		 1800 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1801 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1802 lp->options |= PCNET32_PORT_FD;
1803
1d70cb06 1804 lp->a = a;
4a5e8e29
JG		 1805
1806 /* prior to register_netdev, dev->name is not yet correct */
1807 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1808 ret = -ENOMEM;
1809 goto err_free_ring;
1810 }
1811 /* detect special T1/E1 WAN card by checking for MAC address */
8e95a202
JP		 1812 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1813 dev->dev_addr[2] == 0x75)
4a5e8e29 1814 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1815
3e33545b 1816 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1817 lp->init_block->tlen_rlen =
3e33545b 1818 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1819 for (i = 0; i < 6; i++)
6ecb7667
DF		 1820 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1821 lp->init_block->filter[0] = 0x00000000;
1822 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1823 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1824 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1825
1826 /* switch pcnet32 to 32bit mode */
1827 a->write_bcr(ioaddr, 20, 2);
1828
6ecb7667
DF		 1829 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1830 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1831
1832 if (pdev) { /* use the IRQ provided by PCI */
1833 dev->irq = pdev->irq;
1834 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1835 pr_cont(" assigned IRQ %d\n", dev->irq);
4a5e8e29
JG		 1836 } else {
1837 unsigned long irq_mask = probe_irq_on();
1838
1839 /*
1840 * To auto-IRQ we enable the initialization-done and DMA error
1841 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1842 * boards will work.
1843 */
1844 /* Trigger an initialization just for the interrupt. */
b368a3fb 1845 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1846 mdelay(1);
1847
1848 dev->irq = probe_irq_off(irq_mask);
1849 if (!dev->irq) {
1850 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1851 pr_cont(", failed to detect IRQ line\n");
4a5e8e29
JG		 1852 ret = -ENODEV;
1853 goto err_free_ring;
1854 }
1855 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1856 pr_cont(", probed IRQ %d\n", dev->irq);
4a5e8e29 1857 }
1da177e4 1858
4a5e8e29
JG		 1859 /* Set the mii phy_id so that we can query the link state */
1860 if (lp->mii) {
1861 /* lp->phycount and lp->phymask are set to 0 by memset above */
1862
1d70cb06 1863 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
4a5e8e29
JG		 1864 /* scan for PHYs */
1865 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1866 unsigned short id1, id2;
1867
1868 id1 = mdio_read(dev, i, MII_PHYSID1);
1869 if (id1 == 0xffff)
1870 continue;
1871 id2 = mdio_read(dev, i, MII_PHYSID2);
1872 if (id2 == 0xffff)
1873 continue;
1874 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1875 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1876 lp->phycount++;
1877 lp->phymask |= (1 << i);
1878 lp->mii_if.phy_id = i;
1879 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9
JP		 1880 pr_info("Found PHY %04x:%04x at address %d\n",
1881 id1, id2, i);
4a5e8e29 1882 }
1d70cb06 1883 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
9e3f8063 1884 if (lp->phycount > 1)
4a5e8e29 1885 lp->options |= PCNET32_PORT_MII;
1da177e4 1886 }
4a5e8e29
JG		 1887
1888 init_timer(&lp->watchdog_timer);
1889 lp->watchdog_timer.data = (unsigned long)dev;
1890 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1891
1892 /* The PCNET32-specific entries in the device structure. */
3bc124dd 1893 dev->netdev_ops = &pcnet32_netdev_ops;
4a5e8e29 1894 dev->ethtool_ops = &pcnet32_ethtool_ops;
4a5e8e29 1895 dev->watchdog_timeo = (5 * HZ);
1da177e4 1896
4a5e8e29
JG		 1897 /* Fill in the generic fields of the device structure. */
1898 if (register_netdev(dev))
1899 goto err_free_ring;
1900
1901 if (pdev) {
1902 pci_set_drvdata(pdev, dev);
1903 } else {
1904 lp->next = pcnet32_dev;
1905 pcnet32_dev = dev;
1906 }
1907
1908 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1909 pr_info("%s: registered as %s\n", dev->name, lp->name);
4a5e8e29
JG		 1910 cards_found++;
1911
1912 /* enable LED writes */
1913 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1914
4a5e8e29
JG		 1915 return 0;
1916
df4e7f72 1917err_free_ring:
4a5e8e29 1918 pcnet32_free_ring(dev);
7d2e3cb7 1919 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 1920 lp->init_block, lp->init_dma_addr);
df4e7f72 1921err_free_netdev:
4a5e8e29 1922 free_netdev(dev);
df4e7f72 1923err_release_region:
4a5e8e29
JG		 1924 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1925 return ret;
1926}
1da177e4 1927
a88c844c 1928/* if any allocation fails, caller must also call pcnet32_free_ring */
b166cfba 1929static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
eabf0415 1930{
1e56a4b4 1931 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1932
4a5e8e29
JG		 1933 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1934 sizeof(struct pcnet32_tx_head) *
1935 lp->tx_ring_size,
1936 &lp->tx_ring_dma_addr);
1937 if (lp->tx_ring == NULL) {
13ff83b9 1938 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
4a5e8e29
JG		 1939 return -ENOMEM;
1940 }
eabf0415 1941
4a5e8e29
JG		 1942 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1943 sizeof(struct pcnet32_rx_head) *
1944 lp->rx_ring_size,
1945 &lp->rx_ring_dma_addr);
1946 if (lp->rx_ring == NULL) {
13ff83b9 1947 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
4a5e8e29
JG		 1948 return -ENOMEM;
1949 }
eabf0415 1950
12fa30f3 1951 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29 1952 GFP_ATOMIC);
14f8dc49 1953 if (!lp->tx_dma_addr)
4a5e8e29 1954 return -ENOMEM;
4a5e8e29 1955
12fa30f3 1956 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29 1957 GFP_ATOMIC);
14f8dc49 1958 if (!lp->rx_dma_addr)
4a5e8e29 1959 return -ENOMEM;
4a5e8e29 1960
12fa30f3 1961 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29 1962 GFP_ATOMIC);
14f8dc49 1963 if (!lp->tx_skbuff)
4a5e8e29 1964 return -ENOMEM;
4a5e8e29 1965
12fa30f3 1966 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29 1967 GFP_ATOMIC);
14f8dc49 1968 if (!lp->rx_skbuff)
4a5e8e29 1969 return -ENOMEM;
4a5e8e29
JG		 1970
1971 return 0;
1972}
eabf0415
HWL		 1973
1974static void pcnet32_free_ring(struct net_device *dev)
1975{
1e56a4b4 1976 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1977
4a5e8e29
JG		 1978 kfree(lp->tx_skbuff);
1979 lp->tx_skbuff = NULL;
eabf0415 1980
4a5e8e29
JG		 1981 kfree(lp->rx_skbuff);
1982 lp->rx_skbuff = NULL;
eabf0415 1983
4a5e8e29
JG		 1984 kfree(lp->tx_dma_addr);
1985 lp->tx_dma_addr = NULL;
eabf0415 1986
4a5e8e29
JG		 1987 kfree(lp->rx_dma_addr);
1988 lp->rx_dma_addr = NULL;
eabf0415 1989
4a5e8e29
JG		 1990 if (lp->tx_ring) {
1991 pci_free_consistent(lp->pci_dev,
1992 sizeof(struct pcnet32_tx_head) *
1993 lp->tx_ring_size, lp->tx_ring,
1994 lp->tx_ring_dma_addr);
1995 lp->tx_ring = NULL;
1996 }
eabf0415 1997
4a5e8e29
JG		 1998 if (lp->rx_ring) {
1999 pci_free_consistent(lp->pci_dev,
2000 sizeof(struct pcnet32_rx_head) *
2001 lp->rx_ring_size, lp->rx_ring,
2002 lp->rx_ring_dma_addr);
2003 lp->rx_ring = NULL;
2004 }
eabf0415
HWL		 2005}
2006
4a5e8e29 2007static int pcnet32_open(struct net_device *dev)
1da177e4 2008{
1e56a4b4 2009 struct pcnet32_private *lp = netdev_priv(dev);
63097b3a 2010 struct pci_dev *pdev = lp->pci_dev;
4a5e8e29
JG		 2011 unsigned long ioaddr = dev->base_addr;
2012 u16 val;
2013 int i;
2014 int rc;
2015 unsigned long flags;
2016
a0607fd3 2017 if (request_irq(dev->irq, pcnet32_interrupt,
1fb9df5d 2018 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2019 (void *)dev)) {
2020 return -EAGAIN;
2021 }
2022
2023 spin_lock_irqsave(&lp->lock, flags);
2024 /* Check for a valid station address */
2025 if (!is_valid_ether_addr(dev->dev_addr)) {
2026 rc = -EINVAL;
2027 goto err_free_irq;
2028 }
2029
2030 /* Reset the PCNET32 */
1d70cb06 2031 lp->a->reset(ioaddr);
4a5e8e29
JG		 2032
2033 /* switch pcnet32 to 32bit mode */
1d70cb06 2034 lp->a->write_bcr(ioaddr, 20, 2);
4a5e8e29 2035
13ff83b9
JP		 2036 netif_printk(lp, ifup, KERN_DEBUG, dev,
2037 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2038 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2039 (u32) (lp->rx_ring_dma_addr),
2040 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2041
2042 /* set/reset autoselect bit */
1d70cb06 2043 val = lp->a->read_bcr(ioaddr, 2) & ~2;
4a5e8e29 2044 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2045 val |= 2;
1d70cb06 2046 lp->a->write_bcr(ioaddr, 2, val);
4a5e8e29
JG		 2047
2048 /* handle full duplex setting */
2049 if (lp->mii_if.full_duplex) {
1d70cb06 2050 val = lp->a->read_bcr(ioaddr, 9) & ~3;
4a5e8e29
JG		 2051 if (lp->options & PCNET32_PORT_FD) {
2052 val |= 1;
2053 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2054 val |= 2;
2055 } else if (lp->options & PCNET32_PORT_ASEL) {
2056 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2057 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2058 val |= 3;
2059 }
1d70cb06 2060 lp->a->write_bcr(ioaddr, 9, val);
4a5e8e29
JG		 2061 }
2062
2063 /* set/reset GPSI bit in test register */
1d70cb06 2064 val = lp->a->read_csr(ioaddr, 124) & ~0x10;
4a5e8e29
JG		 2065 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2066 val |= 0x10;
1d70cb06 2067 lp->a->write_csr(ioaddr, 124, val);
4a5e8e29
JG		 2068
2069 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
63097b3a
DF		 2070 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2071 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2072 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2073 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29 2074 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
13ff83b9
JP		 2075 netif_printk(lp, link, KERN_DEBUG, dev,
2076 "Setting 100Mb-Full Duplex\n");
4a5e8e29
JG		 2077 }
2078 }
2079 if (lp->phycount < 2) {
2080 /*
2081 * 24 Jun 2004 according AMD, in order to change the PHY,
2082 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2083 * duplex, and/or enable auto negotiation, and clear DANAS
2084 */
2085 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1d70cb06 2086 lp->a->write_bcr(ioaddr, 32,
2087 lp->a->read_bcr(ioaddr, 32) | 0x0080);
4a5e8e29 2088 /* disable Auto Negotiation, set 10Mpbs, HD */
1d70cb06 2089 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
4a5e8e29
JG		 2090 if (lp->options & PCNET32_PORT_FD)
2091 val |= 0x10;
2092 if (lp->options & PCNET32_PORT_100)
2093 val |= 0x08;
1d70cb06 2094 lp->a->write_bcr(ioaddr, 32, val);
4a5e8e29
JG		 2095 } else {
2096 if (lp->options & PCNET32_PORT_ASEL) {
1d70cb06 2097 lp->a->write_bcr(ioaddr, 32,
2098 lp->a->read_bcr(ioaddr,
4a5e8e29
JG		 2099 32) | 0x0080);
2100 /* enable auto negotiate, setup, disable fd */
1d70cb06 2101 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
4a5e8e29 2102 val |= 0x20;
1d70cb06 2103 lp->a->write_bcr(ioaddr, 32, val);
4a5e8e29
JG		 2104 }
2105 }
2106 } else {
2107 int first_phy = -1;
2108 u16 bmcr;
2109 u32 bcr9;
8ae6daca 2110 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
4a5e8e29
JG		 2111
2112 /*
2113 * There is really no good other way to handle multiple PHYs
2114 * other than turning off all automatics
2115 */
1d70cb06 2116 val = lp->a->read_bcr(ioaddr, 2);
2117 lp->a->write_bcr(ioaddr, 2, val & ~2);
2118 val = lp->a->read_bcr(ioaddr, 32);
2119 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
4a5e8e29
JG		 2120
2121 if (!(lp->options & PCNET32_PORT_ASEL)) {
2122 /* setup ecmd */
2123 ecmd.port = PORT_MII;
2124 ecmd.transceiver = XCVR_INTERNAL;
2125 ecmd.autoneg = AUTONEG_DISABLE;
8ae6daca
DD		 2126 ethtool_cmd_speed_set(&ecmd,
2127 (lp->options & PCNET32_PORT_100) ?
2128 SPEED_100 : SPEED_10);
1d70cb06 2129 bcr9 = lp->a->read_bcr(ioaddr, 9);
4a5e8e29
JG		 2130
2131 if (lp->options & PCNET32_PORT_FD) {
2132 ecmd.duplex = DUPLEX_FULL;
2133 bcr9 |= (1 << 0);
2134 } else {
2135 ecmd.duplex = DUPLEX_HALF;
2136 bcr9 |= ~(1 << 0);
2137 }
1d70cb06 2138 lp->a->write_bcr(ioaddr, 9, bcr9);
ac62ef04 2139 }
4a5e8e29
JG		 2140
2141 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2142 if (lp->phymask & (1 << i)) {
2143 /* isolate all but the first PHY */
2144 bmcr = mdio_read(dev, i, MII_BMCR);
2145 if (first_phy == -1) {
2146 first_phy = i;
2147 mdio_write(dev, i, MII_BMCR,
2148 bmcr & ~BMCR_ISOLATE);
2149 } else {
2150 mdio_write(dev, i, MII_BMCR,
2151 bmcr | BMCR_ISOLATE);
2152 }
2153 /* use mii_ethtool_sset to setup PHY */
2154 lp->mii_if.phy_id = i;
2155 ecmd.phy_address = i;
2156 if (lp->options & PCNET32_PORT_ASEL) {
2157 mii_ethtool_gset(&lp->mii_if, &ecmd);
2158 ecmd.autoneg = AUTONEG_ENABLE;
2159 }
2160 mii_ethtool_sset(&lp->mii_if, &ecmd);
2161 }
2162 }
2163 lp->mii_if.phy_id = first_phy;
13ff83b9 2164 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
4a5e8e29 2165 }
1da177e4
LT		 2166
2167#ifdef DO_DXSUFLO
4a5e8e29 2168 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1d70cb06 2169 val = lp->a->read_csr(ioaddr, CSR3);
4a5e8e29 2170 val |= 0x40;
1d70cb06 2171 lp->a->write_csr(ioaddr, CSR3, val);
4a5e8e29 2172 }
1da177e4
LT		 2173#endif
2174
6ecb7667 2175 lp->init_block->mode =
3e33545b 2176 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2177 pcnet32_load_multicast(dev);
2178
2179 if (pcnet32_init_ring(dev)) {
2180 rc = -ENOMEM;
2181 goto err_free_ring;
2182 }
2183
bea3348e 2184 napi_enable(&lp->napi);
bea3348e 2185
4a5e8e29 2186 /* Re-initialize the PCNET32, and start it when done. */
1d70cb06 2187 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2188 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2189
1d70cb06 2190 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2191 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2192
2193 netif_start_queue(dev);
2194
8d916266
DF		 2195 if (lp->chip_version >= PCNET32_79C970A) {
2196 /* Print the link status and start the watchdog */
2197 pcnet32_check_media(dev, 1);
283a21d3 2198 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
8d916266 2199 }
4a5e8e29
JG		 2200
2201 i = 0;
2202 while (i++ < 100)
1d70cb06 2203 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2204 break;
2205 /*
2206 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2207 * reports that doing so triggers a bug in the '974.
2208 */
1d70cb06 2209 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29 2210
13ff83b9
JP		 2211 netif_printk(lp, ifup, KERN_DEBUG, dev,
2212 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2213 i,
2214 (u32) (lp->init_dma_addr),
1d70cb06 2215 lp->a->read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2216
2217 spin_unlock_irqrestore(&lp->lock, flags);
2218
2219 return 0; /* Always succeed */
2220
9e3f8063 2221err_free_ring:
4a5e8e29 2222 /* free any allocated skbuffs */
ac5bfe40 2223 pcnet32_purge_rx_ring(dev);
4a5e8e29 2224
4a5e8e29
JG		 2225 /*
2226 * Switch back to 16bit mode to avoid problems with dumb
2227 * DOS packet driver after a warm reboot
2228 */
1d70cb06 2229 lp->a->write_bcr(ioaddr, 20, 4);
4a5e8e29 2230
9e3f8063 2231err_free_irq:
4a5e8e29
JG		 2232 spin_unlock_irqrestore(&lp->lock, flags);
2233 free_irq(dev->irq, dev);
2234 return rc;
1da177e4
LT		 2235}
2236
2237/*
2238 * The LANCE has been halted for one reason or another (busmaster memory
2239 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2240 * etc.). Modern LANCE variants always reload their ring-buffer
2241 * configuration when restarted, so we must reinitialize our ring
2242 * context before restarting. As part of this reinitialization,
2243 * find all packets still on the Tx ring and pretend that they had been
2244 * sent (in effect, drop the packets on the floor) - the higher-level
2245 * protocols will time out and retransmit. It'd be better to shuffle
2246 * these skbs to a temp list and then actually re-Tx them after
2247 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2248 */
2249
4a5e8e29 2250static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2251{
1e56a4b4 2252 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2253 int i;
1da177e4 2254
4a5e8e29
JG		 2255 for (i = 0; i < lp->tx_ring_size; i++) {
2256 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2257 wmb(); /* Make sure adapter sees owner change */
2258 if (lp->tx_skbuff[i]) {
2259 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2260 lp->tx_skbuff[i]->len,
2261 PCI_DMA_TODEVICE);
2262 dev_kfree_skb_any(lp->tx_skbuff[i]);
2263 }
2264 lp->tx_skbuff[i] = NULL;
2265 lp->tx_dma_addr[i] = 0;
2266 }
2267}
1da177e4
LT		 2268
2269/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2270static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2271{
1e56a4b4 2272 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2273 int i;
2274
2275 lp->tx_full = 0;
2276 lp->cur_rx = lp->cur_tx = 0;
2277 lp->dirty_rx = lp->dirty_tx = 0;
2278
2279 for (i = 0; i < lp->rx_ring_size; i++) {
2280 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2281 if (rx_skbuff == NULL) {
1d266430 2282 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
9e3f8063
JP		 2283 rx_skbuff = lp->rx_skbuff[i];
2284 if (!rx_skbuff) {
2285 /* there is not much we can do at this point */
1d266430 2286 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
13ff83b9 2287 __func__);
4a5e8e29
JG		 2288 return -1;
2289 }
232c5640 2290 skb_reserve(rx_skbuff, NET_IP_ALIGN);
4a5e8e29
JG		 2291 }
2292
2293 rmb();
2294 if (lp->rx_dma_addr[i] == 0)
2295 lp->rx_dma_addr[i] =
2296 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 2297 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 2298 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
232c5640 2299 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
4a5e8e29 2300 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2301 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2302 }
2303 /* The Tx buffer address is filled in as needed, but we do need to clear
2304 * the upper ownership bit. */
2305 for (i = 0; i < lp->tx_ring_size; i++) {
2306 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2307 wmb(); /* Make sure adapter sees owner change */
2308 lp->tx_ring[i].base = 0;
2309 lp->tx_dma_addr[i] = 0;
2310 }
2311
6ecb7667 2312 lp->init_block->tlen_rlen =
3e33545b 2313 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2314 for (i = 0; i < 6; i++)
6ecb7667 2315 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2316 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2317 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2318 wmb(); /* Make sure all changes are visible */
2319 return 0;
1da177e4
LT		 2320}
2321
2322/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2323 * then flush the pending transmit operations, re-initialize the ring,
2324 * and tell the chip to initialize.
2325 */
4a5e8e29 2326static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2327{
1e56a4b4 2328 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2329 unsigned long ioaddr = dev->base_addr;
2330 int i;
1da177e4 2331
4a5e8e29
JG		 2332 /* wait for stop */
2333 for (i = 0; i < 100; i++)
1d70cb06 2334 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2335 break;
1da177e4 2336
13ff83b9
JP		 2337 if (i >= 100)
2338 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2339 __func__);
1da177e4 2340
4a5e8e29
JG		 2341 pcnet32_purge_tx_ring(dev);
2342 if (pcnet32_init_ring(dev))
2343 return;
1da177e4 2344
4a5e8e29 2345 /* ReInit Ring */
1d70cb06 2346 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2347 i = 0;
2348 while (i++ < 1000)
1d70cb06 2349 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2350 break;
1da177e4 2351
1d70cb06 2352 lp->a->write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2353}
2354
4a5e8e29 2355static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2356{
1e56a4b4 2357 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2358 unsigned long ioaddr = dev->base_addr, flags;
2359
2360 spin_lock_irqsave(&lp->lock, flags);
2361 /* Transmitter timeout, serious problems. */
2362 if (pcnet32_debug & NETIF_MSG_DRV)
13ff83b9 2363 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
1d70cb06 2364 dev->name, lp->a->read_csr(ioaddr, CSR0));
2365 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
4f1e5ba0 2366 dev->stats.tx_errors++;
4a5e8e29
JG		 2367 if (netif_msg_tx_err(lp)) {
2368 int i;
2369 printk(KERN_DEBUG
2370 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2371 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2372 lp->cur_rx);
2373 for (i = 0; i < lp->rx_ring_size; i++)
2374 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2375 le32_to_cpu(lp->rx_ring[i].base),
2376 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2377 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2378 le16_to_cpu(lp->rx_ring[i].status));
2379 for (i = 0; i < lp->tx_ring_size; i++)
2380 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2381 le32_to_cpu(lp->tx_ring[i].base),
2382 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2383 le32_to_cpu(lp->tx_ring[i].misc),
2384 le16_to_cpu(lp->tx_ring[i].status));
2385 printk("\n");
2386 }
b368a3fb 2387 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2388
1ae5dc34 2389 dev->trans_start = jiffies; /* prevent tx timeout */
4a5e8e29 2390 netif_wake_queue(dev);
1da177e4 2391
4a5e8e29
JG		 2392 spin_unlock_irqrestore(&lp->lock, flags);
2393}
2394
61357325
SH		 2395static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2396 struct net_device *dev)
1da177e4 2397{
1e56a4b4 2398 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2399 unsigned long ioaddr = dev->base_addr;
2400 u16 status;
2401 int entry;
2402 unsigned long flags;
1da177e4 2403
4a5e8e29 2404 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2405
13ff83b9
JP		 2406 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2407 "%s() called, csr0 %4.4x\n",
1d70cb06 2408 __func__, lp->a->read_csr(ioaddr, CSR0));
1da177e4 2409
4a5e8e29
JG		 2410 /* Default status -- will not enable Successful-TxDone
2411 * interrupt when that option is available to us.
2412 */
2413 status = 0x8300;
1da177e4 2414
4a5e8e29 2415 /* Fill in a Tx ring entry */
1da177e4 2416
4a5e8e29
JG		 2417 /* Mask to ring buffer boundary. */
2418 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2419
4a5e8e29
JG		 2420 /* Caution: the write order is important here, set the status
2421 * with the "ownership" bits last. */
1da177e4 2422
3e33545b 2423 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2424
4a5e8e29 2425 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2426
4a5e8e29
JG		 2427 lp->tx_skbuff[entry] = skb;
2428 lp->tx_dma_addr[entry] =
2429 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2430 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2431 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2432 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2433
4a5e8e29 2434 lp->cur_tx++;
4f1e5ba0 2435 dev->stats.tx_bytes += skb->len;
1da177e4 2436
4a5e8e29 2437 /* Trigger an immediate send poll. */
1d70cb06 2438 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2439
4a5e8e29
JG		 2440 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2441 lp->tx_full = 1;
2442 netif_stop_queue(dev);
2443 }
2444 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 2445 return NETDEV_TX_OK;
1da177e4
LT		 2446}
2447
2448/* The PCNET32 interrupt handler. */
2449static irqreturn_t
7d12e780 2450pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2451{
4a5e8e29
JG		 2452 struct net_device *dev = dev_id;
2453 struct pcnet32_private *lp;
2454 unsigned long ioaddr;
5c99346a 2455 u16 csr0;
4a5e8e29 2456 int boguscnt = max_interrupt_work;
4a5e8e29 2457
4a5e8e29 2458 ioaddr = dev->base_addr;
1e56a4b4 2459 lp = netdev_priv(dev);
1da177e4 2460
4a5e8e29
JG		 2461 spin_lock(&lp->lock);
2462
1d70cb06 2463 csr0 = lp->a->read_csr(ioaddr, CSR0);
3904c324 2464 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
9e3f8063 2465 if (csr0 == 0xffff)
4a5e8e29 2466 break; /* PCMCIA remove happened */
4a5e8e29 2467 /* Acknowledge all of the current interrupt sources ASAP. */
1d70cb06 2468 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2469
13ff83b9
JP		 2470 netif_printk(lp, intr, KERN_DEBUG, dev,
2471 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
1d70cb06 2472 csr0, lp->a->read_csr(ioaddr, CSR0));
4a5e8e29 2473
4a5e8e29
JG		 2474 /* Log misc errors. */
2475 if (csr0 & 0x4000)
4f1e5ba0 2476 dev->stats.tx_errors++; /* Tx babble. */
4a5e8e29
JG		 2477 if (csr0 & 0x1000) {
2478 /*
3904c324
DF		 2479 * This happens when our receive ring is full. This
2480 * shouldn't be a problem as we will see normal rx
2481 * interrupts for the frames in the receive ring. But
2482 * there are some PCI chipsets (I can reproduce this
2483 * on SP3G with Intel saturn chipset) which have
2484 * sometimes problems and will fill up the receive
2485 * ring with error descriptors. In this situation we
2486 * don't get a rx interrupt, but a missed frame
7de745e5 2487 * interrupt sooner or later.
4a5e8e29 2488 */
4f1e5ba0 2489 dev->stats.rx_errors++; /* Missed a Rx frame. */
4a5e8e29
JG		 2490 }
2491 if (csr0 & 0x0800) {
13ff83b9
JP		 2492 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2493 csr0);
4a5e8e29 2494 /* unlike for the lance, there is no restart needed */
1da177e4 2495 }
288379f0 2496 if (napi_schedule_prep(&lp->napi)) {
7de745e5
DF		 2497 u16 val;
2498 /* set interrupt masks */
1d70cb06 2499 val = lp->a->read_csr(ioaddr, CSR3);
7de745e5 2500 val |= 0x5f00;
1d70cb06 2501 lp->a->write_csr(ioaddr, CSR3, val);
ce105a08 2502
288379f0 2503 __napi_schedule(&lp->napi);
7de745e5
DF		 2504 break;
2505 }
1d70cb06 2506 csr0 = lp->a->read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2507 }
2508
13ff83b9
JP		 2509 netif_printk(lp, intr, KERN_DEBUG, dev,
2510 "exiting interrupt, csr0=%#4.4x\n",
1d70cb06 2511 lp->a->read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2512
2513 spin_unlock(&lp->lock);
2514
2515 return IRQ_HANDLED;
1da177e4
LT		 2516}
2517
4a5e8e29 2518static int pcnet32_close(struct net_device *dev)
1da177e4 2519{
4a5e8e29 2520 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2521 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2522 unsigned long flags;
1da177e4 2523
4a5e8e29 2524 del_timer_sync(&lp->watchdog_timer);
1da177e4 2525
4a5e8e29 2526 netif_stop_queue(dev);
bea3348e 2527 napi_disable(&lp->napi);
1da177e4 2528
4a5e8e29 2529 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2530
1d70cb06 2531 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
1da177e4 2532
13ff83b9
JP		 2533 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2534 "Shutting down ethercard, status was %2.2x\n",
1d70cb06 2535 lp->a->read_csr(ioaddr, CSR0));
1da177e4 2536
4a5e8e29 2537 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
1d70cb06 2538 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2539
4a5e8e29
JG		 2540 /*
2541 * Switch back to 16bit mode to avoid problems with dumb
2542 * DOS packet driver after a warm reboot
2543 */
1d70cb06 2544 lp->a->write_bcr(ioaddr, 20, 4);
1da177e4 2545
4a5e8e29 2546 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2547
4a5e8e29 2548 free_irq(dev->irq, dev);
1da177e4 2549
4a5e8e29 2550 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2551
ac5bfe40
DF		 2552 pcnet32_purge_rx_ring(dev);
2553 pcnet32_purge_tx_ring(dev);
1da177e4 2554
4a5e8e29 2555 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2556
4a5e8e29 2557 return 0;
1da177e4
LT		 2558}
2559
4a5e8e29 2560static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2561{
1e56a4b4 2562 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2563 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2564 unsigned long flags;
2565
2566 spin_lock_irqsave(&lp->lock, flags);
1d70cb06 2567 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
4a5e8e29
JG		 2568 spin_unlock_irqrestore(&lp->lock, flags);
2569
4f1e5ba0 2570 return &dev->stats;
1da177e4
LT		 2571}
2572
2573/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2574static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2575{
1e56a4b4 2576 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2577 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2578 volatile __le16 *mcast_table = (__le16 *)ib->filter;
22bedad3 2579 struct netdev_hw_addr *ha;
df27f4a6 2580 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2581 int i;
2582 u32 crc;
2583
2584 /* set all multicast bits */
2585 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2586 ib->filter[0] = cpu_to_le32(~0U);
2587 ib->filter[1] = cpu_to_le32(~0U);
1d70cb06 2588 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2589 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2590 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2591 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2592 return;
2593 }
2594 /* clear the multicast filter */
2595 ib->filter[0] = 0;
2596 ib->filter[1] = 0;
2597
2598 /* Add addresses */
22bedad3 2599 netdev_for_each_mc_addr(ha, dev) {
498d8e23 2600 crc = ether_crc_le(6, ha->addr);
4a5e8e29 2601 crc = crc >> 26;
3e33545b 2602 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2603 }
df27f4a6 2604 for (i = 0; i < 4; i++)
1d70cb06 2605 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
df27f4a6 2606 le16_to_cpu(mcast_table[i]));
1da177e4
LT		 2607}
2608
1da177e4
LT		 2609/*
2610 * Set or clear the multicast filter for this adaptor.
2611 */
2612static void pcnet32_set_multicast_list(struct net_device *dev)
2613{
4a5e8e29 2614 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2615 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2616 int csr15, suspended;
4a5e8e29
JG		 2617
2618 spin_lock_irqsave(&lp->lock, flags);
df27f4a6 2619 suspended = pcnet32_suspend(dev, &flags, 0);
1d70cb06 2620 csr15 = lp->a->read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2621 if (dev->flags & IFF_PROMISC) {
2622 /* Log any net taps. */
13ff83b9 2623 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
6ecb7667 2624 lp->init_block->mode =
3e33545b 2625 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2626 7);
1d70cb06 2627 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2628 } else {
6ecb7667 2629 lp->init_block->mode =
3e33545b 2630 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
1d70cb06 2631 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2632 pcnet32_load_multicast(dev);
2633 }
2634
df27f4a6
DF		 2635 if (suspended) {
2636 int csr5;
2637 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1d70cb06 2638 csr5 = lp->a->read_csr(ioaddr, CSR5);
2639 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2640 } else {
1d70cb06 2641 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
df27f4a6
DF		 2642 pcnet32_restart(dev, CSR0_NORMAL);
2643 netif_wake_queue(dev);
2644 }
4a5e8e29
JG		 2645
2646 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2647}
2648
2649/* This routine assumes that the lp->lock is held */
2650static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2651{
1e56a4b4 2652 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2653 unsigned long ioaddr = dev->base_addr;
2654 u16 val_out;
1da177e4 2655
4a5e8e29
JG		 2656 if (!lp->mii)
2657 return 0;
1da177e4 2658
1d70cb06 2659 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2660 val_out = lp->a->read_bcr(ioaddr, 34);
1da177e4 2661
4a5e8e29 2662 return val_out;
1da177e4
LT		 2663}
2664
2665/* This routine assumes that the lp->lock is held */
2666static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2667{
1e56a4b4 2668 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2669 unsigned long ioaddr = dev->base_addr;
1da177e4 2670
4a5e8e29
JG		 2671 if (!lp->mii)
2672 return;
1da177e4 2673
1d70cb06 2674 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2675 lp->a->write_bcr(ioaddr, 34, val);
1da177e4
LT		 2676}
2677
2678static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2679{
1e56a4b4 2680 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2681 int rc;
2682 unsigned long flags;
1da177e4 2683
4a5e8e29
JG		 2684 /* SIOC[GS]MIIxxx ioctls */
2685 if (lp->mii) {
2686 spin_lock_irqsave(&lp->lock, flags);
2687 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2688 spin_unlock_irqrestore(&lp->lock, flags);
2689 } else {
2690 rc = -EOPNOTSUPP;
2691 }
1da177e4 2692
4a5e8e29 2693 return rc;
1da177e4
LT		 2694}
2695
ac62ef04
DF		 2696static int pcnet32_check_otherphy(struct net_device *dev)
2697{
1e56a4b4 2698 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2699 struct mii_if_info mii = lp->mii_if;
2700 u16 bmcr;
2701 int i;
ac62ef04 2702
4a5e8e29
JG		 2703 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2704 if (i == lp->mii_if.phy_id)
2705 continue; /* skip active phy */
2706 if (lp->phymask & (1 << i)) {
2707 mii.phy_id = i;
2708 if (mii_link_ok(&mii)) {
2709 /* found PHY with active link */
13ff83b9
JP		 2710 netif_info(lp, link, dev, "Using PHY number %d\n",
2711 i);
4a5e8e29
JG		 2712
2713 /* isolate inactive phy */
2714 bmcr =
2715 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2716 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2717 bmcr | BMCR_ISOLATE);
2718
2719 /* de-isolate new phy */
2720 bmcr = mdio_read(dev, i, MII_BMCR);
2721 mdio_write(dev, i, MII_BMCR,
2722 bmcr & ~BMCR_ISOLATE);
2723
2724 /* set new phy address */
2725 lp->mii_if.phy_id = i;
2726 return 1;
2727 }
2728 }
ac62ef04 2729 }
4a5e8e29 2730 return 0;
ac62ef04
DF		 2731}
2732
2733/*
2734 * Show the status of the media. Similar to mii_check_media however it
2735 * correctly shows the link speed for all (tested) pcnet32 variants.
2736 * Devices with no mii just report link state without speed.
2737 *
2738 * Caller is assumed to hold and release the lp->lock.
2739 */
2740
2741static void pcnet32_check_media(struct net_device *dev, int verbose)
2742{
1e56a4b4 2743 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2744 int curr_link;
2745 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2746 u32 bcr9;
2747
ac62ef04 2748 if (lp->mii) {
4a5e8e29 2749 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2750 } else {
4a5e8e29 2751 ulong ioaddr = dev->base_addr; /* card base I/O address */
1d70cb06 2752 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
4a5e8e29
JG		 2753 }
2754 if (!curr_link) {
2755 if (prev_link || verbose) {
2756 netif_carrier_off(dev);
13ff83b9 2757 netif_info(lp, link, dev, "link down\n");
4a5e8e29
JG		 2758 }
2759 if (lp->phycount > 1) {
2760 curr_link = pcnet32_check_otherphy(dev);
2761 prev_link = 0;
2762 }
2763 } else if (verbose || !prev_link) {
2764 netif_carrier_on(dev);
2765 if (lp->mii) {
2766 if (netif_msg_link(lp)) {
8ae6daca
DD		 2767 struct ethtool_cmd ecmd = {
2768 .cmd = ETHTOOL_GSET };
4a5e8e29 2769 mii_ethtool_gset(&lp->mii_if, &ecmd);
8ae6daca
DD		 2770 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2771 ethtool_cmd_speed(&ecmd),
13ff83b9
JP		 2772 (ecmd.duplex == DUPLEX_FULL)
2773 ? "full" : "half");
4a5e8e29 2774 }
1d70cb06 2775 bcr9 = lp->a->read_bcr(dev->base_addr, 9);
4a5e8e29
JG		 2776 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2777 if (lp->mii_if.full_duplex)
2778 bcr9 |= (1 << 0);
2779 else
2780 bcr9 &= ~(1 << 0);
1d70cb06 2781 lp->a->write_bcr(dev->base_addr, 9, bcr9);
4a5e8e29
JG		 2782 }
2783 } else {
13ff83b9 2784 netif_info(lp, link, dev, "link up\n");
4a5e8e29 2785 }
ac62ef04 2786 }
ac62ef04
DF		 2787}
2788
2789/*
2790 * Check for loss of link and link establishment.
2791 * Can not use mii_check_media because it does nothing if mode is forced.
2792 */
2793
1da177e4
LT		 2794static void pcnet32_watchdog(struct net_device *dev)
2795{
1e56a4b4 2796 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2797 unsigned long flags;
1da177e4 2798
4a5e8e29
JG		 2799 /* Print the link status if it has changed */
2800 spin_lock_irqsave(&lp->lock, flags);
2801 pcnet32_check_media(dev, 0);
2802 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2803
283a21d3 2804 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
1da177e4
LT		 2805}
2806
917270c6
DF		 2807static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2808{
2809 struct net_device *dev = pci_get_drvdata(pdev);
2810
2811 if (netif_running(dev)) {
2812 netif_device_detach(dev);
2813 pcnet32_close(dev);
2814 }
2815 pci_save_state(pdev);
2816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2817 return 0;
2818}
2819
2820static int pcnet32_pm_resume(struct pci_dev *pdev)
2821{
2822 struct net_device *dev = pci_get_drvdata(pdev);
2823
2824 pci_set_power_state(pdev, PCI_D0);
2825 pci_restore_state(pdev);
2826
2827 if (netif_running(dev)) {
2828 pcnet32_open(dev);
2829 netif_device_attach(dev);
2830 }
2831 return 0;
2832}
2833
a9590879 2834static void pcnet32_remove_one(struct pci_dev *pdev)
1da177e4 2835{
4a5e8e29
JG		 2836 struct net_device *dev = pci_get_drvdata(pdev);
2837
2838 if (dev) {
1e56a4b4 2839 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2840
2841 unregister_netdev(dev);
2842 pcnet32_free_ring(dev);
2843 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2844 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2845 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2846 free_netdev(dev);
2847 pci_disable_device(pdev);
2848 pci_set_drvdata(pdev, NULL);
2849 }
1da177e4
LT		 2850}
2851
2852static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2853 .name = DRV_NAME,
2854 .probe = pcnet32_probe_pci,
a9590879 2855 .remove = pcnet32_remove_one,
4a5e8e29 2856 .id_table = pcnet32_pci_tbl,
917270c6
DF		 2857 .suspend = pcnet32_pm_suspend,
2858 .resume = pcnet32_pm_resume,
1da177e4
LT		 2859};
2860
2861/* An additional parameter that may be passed in... */
2862static int debug = -1;
2863static int tx_start_pt = -1;
2864static int pcnet32_have_pci;
2865
2866module_param(debug, int, 0);
2867MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2868module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2869MODULE_PARM_DESC(max_interrupt_work,
2870 DRV_NAME " maximum events handled per interrupt");
1da177e4 2871module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2872MODULE_PARM_DESC(rx_copybreak,
2873 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2874module_param(tx_start_pt, int, 0);
2875MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2876module_param(pcnet32vlb, int, 0);
2877MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2878module_param_array(options, int, NULL, 0);
2879MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2880module_param_array(full_duplex, int, NULL, 0);
2881MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2882/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2883module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2884MODULE_PARM_DESC(homepna,
2885 DRV_NAME
2886 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2887
2888MODULE_AUTHOR("Thomas Bogendoerfer");
2889MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2890MODULE_LICENSE("GPL");
2891
2892#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2893
2894static int __init pcnet32_init_module(void)
2895{
13ff83b9 2896 pr_info("%s", version);
1da177e4 2897
4a5e8e29 2898 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 2899
4a5e8e29
JG		 2900 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2901 tx_start = tx_start_pt;
1da177e4 2902
4a5e8e29 2903 /* find the PCI devices */
29917620 2904 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 2905 pcnet32_have_pci = 1;
1da177e4 2906
4a5e8e29
JG		 2907 /* should we find any remaining VLbus devices ? */
2908 if (pcnet32vlb)
dcaf9769 2909 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 2910
4a5e8e29 2911 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
13ff83b9 2912 pr_info("%d cards_found\n", cards_found);
1da177e4 2913
4a5e8e29 2914 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 2915}
2916
2917static void __exit pcnet32_cleanup_module(void)
2918{
4a5e8e29
JG		 2919 struct net_device *next_dev;
2920
2921 while (pcnet32_dev) {
1e56a4b4 2922 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 2923 next_dev = lp->next;
2924 unregister_netdev(pcnet32_dev);
2925 pcnet32_free_ring(pcnet32_dev);
2926 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2927 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2928 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2929 free_netdev(pcnet32_dev);
2930 pcnet32_dev = next_dev;
2931 }
1da177e4 2932
4a5e8e29
JG		 2933 if (pcnet32_have_pci)
2934 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 2935}
2936
2937module_init(pcnet32_init_module);
2938module_exit(pcnet32_cleanup_module);
2939
2940/*
2941 * Local variables:
2942 * c-indent-level: 4
2943 * tab-width: 8
2944 * End:
2945 */
kernel source for telekom puls (alcatel/mediatek)