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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
1605927f | 30 | * 82562G 10/100 Network Connection |
bc7f75fa AK |
31 | * 82562G-2 10/100 Network Connection |
32 | * 82562GT 10/100 Network Connection | |
33 | * 82562GT-2 10/100 Network Connection | |
34 | * 82562V 10/100 Network Connection | |
35 | * 82562V-2 10/100 Network Connection | |
36 | * 82566DC-2 Gigabit Network Connection | |
37 | * 82566DC Gigabit Network Connection | |
38 | * 82566DM-2 Gigabit Network Connection | |
39 | * 82566DM Gigabit Network Connection | |
40 | * 82566MC Gigabit Network Connection | |
41 | * 82566MM Gigabit Network Connection | |
97ac8cae BA |
42 | * 82567LM Gigabit Network Connection |
43 | * 82567LF Gigabit Network Connection | |
1605927f | 44 | * 82567V Gigabit Network Connection |
97ac8cae BA |
45 | * 82567LM-2 Gigabit Network Connection |
46 | * 82567LF-2 Gigabit Network Connection | |
47 | * 82567V-2 Gigabit Network Connection | |
f4187b56 BA |
48 | * 82567LF-3 Gigabit Network Connection |
49 | * 82567LM-3 Gigabit Network Connection | |
2f15f9d6 | 50 | * 82567LM-4 Gigabit Network Connection |
a4f58f54 BA |
51 | * 82577LM Gigabit Network Connection |
52 | * 82577LC Gigabit Network Connection | |
53 | * 82578DM Gigabit Network Connection | |
54 | * 82578DC Gigabit Network Connection | |
bc7f75fa AK |
55 | */ |
56 | ||
57 | #include <linux/netdevice.h> | |
58 | #include <linux/ethtool.h> | |
59 | #include <linux/delay.h> | |
60 | #include <linux/pci.h> | |
61 | ||
62 | #include "e1000.h" | |
63 | ||
64 | #define ICH_FLASH_GFPREG 0x0000 | |
65 | #define ICH_FLASH_HSFSTS 0x0004 | |
66 | #define ICH_FLASH_HSFCTL 0x0006 | |
67 | #define ICH_FLASH_FADDR 0x0008 | |
68 | #define ICH_FLASH_FDATA0 0x0010 | |
4a770358 | 69 | #define ICH_FLASH_PR0 0x0074 |
bc7f75fa AK |
70 | |
71 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 | |
72 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 | |
73 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 | |
74 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | |
75 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | |
76 | ||
77 | #define ICH_CYCLE_READ 0 | |
78 | #define ICH_CYCLE_WRITE 2 | |
79 | #define ICH_CYCLE_ERASE 3 | |
80 | ||
81 | #define FLASH_GFPREG_BASE_MASK 0x1FFF | |
82 | #define FLASH_SECTOR_ADDR_SHIFT 12 | |
83 | ||
84 | #define ICH_FLASH_SEG_SIZE_256 256 | |
85 | #define ICH_FLASH_SEG_SIZE_4K 4096 | |
86 | #define ICH_FLASH_SEG_SIZE_8K 8192 | |
87 | #define ICH_FLASH_SEG_SIZE_64K 65536 | |
88 | ||
89 | ||
90 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | |
91 | ||
92 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | |
93 | ||
94 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ | |
95 | (ID_LED_DEF1_OFF2 << 8) | \ | |
96 | (ID_LED_DEF1_ON2 << 4) | \ | |
97 | (ID_LED_DEF1_DEF2)) | |
98 | ||
99 | #define E1000_ICH_NVM_SIG_WORD 0x13 | |
100 | #define E1000_ICH_NVM_SIG_MASK 0xC000 | |
e243455d BA |
101 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 |
102 | #define E1000_ICH_NVM_SIG_VALUE 0x80 | |
bc7f75fa AK |
103 | |
104 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | |
105 | ||
106 | #define E1000_FEXTNVM_SW_CONFIG 1 | |
107 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ | |
108 | ||
109 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL | |
110 | ||
111 | #define E1000_ICH_RAR_ENTRIES 7 | |
112 | ||
113 | #define PHY_PAGE_SHIFT 5 | |
114 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ | |
115 | ((reg) & MAX_PHY_REG_ADDRESS)) | |
116 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ | |
117 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ | |
118 | ||
119 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 | |
120 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 | |
121 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 | |
122 | ||
a4f58f54 BA |
123 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
124 | ||
bc7f75fa AK |
125 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
126 | /* Offset 04h HSFSTS */ | |
127 | union ich8_hws_flash_status { | |
128 | struct ich8_hsfsts { | |
129 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ | |
130 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ | |
131 | u16 dael :1; /* bit 2 Direct Access error Log */ | |
132 | u16 berasesz :2; /* bit 4:3 Sector Erase Size */ | |
133 | u16 flcinprog :1; /* bit 5 flash cycle in Progress */ | |
134 | u16 reserved1 :2; /* bit 13:6 Reserved */ | |
135 | u16 reserved2 :6; /* bit 13:6 Reserved */ | |
136 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ | |
137 | u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ | |
138 | } hsf_status; | |
139 | u16 regval; | |
140 | }; | |
141 | ||
142 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | |
143 | /* Offset 06h FLCTL */ | |
144 | union ich8_hws_flash_ctrl { | |
145 | struct ich8_hsflctl { | |
146 | u16 flcgo :1; /* 0 Flash Cycle Go */ | |
147 | u16 flcycle :2; /* 2:1 Flash Cycle */ | |
148 | u16 reserved :5; /* 7:3 Reserved */ | |
149 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ | |
150 | u16 flockdn :6; /* 15:10 Reserved */ | |
151 | } hsf_ctrl; | |
152 | u16 regval; | |
153 | }; | |
154 | ||
155 | /* ICH Flash Region Access Permissions */ | |
156 | union ich8_hws_flash_regacc { | |
157 | struct ich8_flracc { | |
158 | u32 grra :8; /* 0:7 GbE region Read Access */ | |
159 | u32 grwa :8; /* 8:15 GbE region Write Access */ | |
160 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ | |
161 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ | |
162 | } hsf_flregacc; | |
163 | u16 regval; | |
164 | }; | |
165 | ||
4a770358 BA |
166 | /* ICH Flash Protected Region */ |
167 | union ich8_flash_protected_range { | |
168 | struct ich8_pr { | |
169 | u32 base:13; /* 0:12 Protected Range Base */ | |
170 | u32 reserved1:2; /* 13:14 Reserved */ | |
171 | u32 rpe:1; /* 15 Read Protection Enable */ | |
172 | u32 limit:13; /* 16:28 Protected Range Limit */ | |
173 | u32 reserved2:2; /* 29:30 Reserved */ | |
174 | u32 wpe:1; /* 31 Write Protection Enable */ | |
175 | } range; | |
176 | u32 regval; | |
177 | }; | |
178 | ||
bc7f75fa AK |
179 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); |
180 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); | |
181 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); | |
182 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); | |
183 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); | |
184 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
185 | u32 offset, u8 byte); | |
f4187b56 BA |
186 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
187 | u8 *data); | |
bc7f75fa AK |
188 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
189 | u16 *data); | |
190 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
191 | u8 size, u16 *data); | |
192 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); | |
193 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | |
f4187b56 | 194 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); |
a4f58f54 BA |
195 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); |
196 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); | |
197 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); | |
198 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); | |
199 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); | |
200 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); | |
201 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); | |
202 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); | |
bc7f75fa AK |
203 | |
204 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | |
205 | { | |
206 | return readw(hw->flash_address + reg); | |
207 | } | |
208 | ||
209 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) | |
210 | { | |
211 | return readl(hw->flash_address + reg); | |
212 | } | |
213 | ||
214 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) | |
215 | { | |
216 | writew(val, hw->flash_address + reg); | |
217 | } | |
218 | ||
219 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |
220 | { | |
221 | writel(val, hw->flash_address + reg); | |
222 | } | |
223 | ||
224 | #define er16flash(reg) __er16flash(hw, (reg)) | |
225 | #define er32flash(reg) __er32flash(hw, (reg)) | |
226 | #define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) | |
227 | #define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) | |
228 | ||
a4f58f54 BA |
229 | /** |
230 | * e1000_init_phy_params_pchlan - Initialize PHY function pointers | |
231 | * @hw: pointer to the HW structure | |
232 | * | |
233 | * Initialize family-specific PHY parameters and function pointers. | |
234 | **/ | |
235 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |
236 | { | |
237 | struct e1000_phy_info *phy = &hw->phy; | |
238 | s32 ret_val = 0; | |
239 | ||
240 | phy->addr = 1; | |
241 | phy->reset_delay_us = 100; | |
242 | ||
243 | phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; | |
244 | phy->ops.read_phy_reg = e1000_read_phy_reg_hv; | |
245 | phy->ops.write_phy_reg = e1000_write_phy_reg_hv; | |
246 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
247 | ||
248 | phy->id = e1000_phy_unknown; | |
249 | e1000e_get_phy_id(hw); | |
250 | phy->type = e1000e_get_phy_type_from_id(phy->id); | |
251 | ||
252 | if (phy->type == e1000_phy_82577) { | |
253 | phy->ops.check_polarity = e1000_check_polarity_82577; | |
254 | phy->ops.force_speed_duplex = | |
255 | e1000_phy_force_speed_duplex_82577; | |
256 | phy->ops.get_cable_length = e1000_get_cable_length_82577; | |
257 | phy->ops.get_phy_info = e1000_get_phy_info_82577; | |
258 | phy->ops.commit_phy = e1000e_phy_sw_reset; | |
259 | } | |
260 | ||
261 | return ret_val; | |
262 | } | |
263 | ||
bc7f75fa AK |
264 | /** |
265 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers | |
266 | * @hw: pointer to the HW structure | |
267 | * | |
268 | * Initialize family-specific PHY parameters and function pointers. | |
269 | **/ | |
270 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |
271 | { | |
272 | struct e1000_phy_info *phy = &hw->phy; | |
273 | s32 ret_val; | |
274 | u16 i = 0; | |
275 | ||
276 | phy->addr = 1; | |
277 | phy->reset_delay_us = 100; | |
278 | ||
97ac8cae BA |
279 | /* |
280 | * We may need to do this twice - once for IGP and if that fails, | |
281 | * we'll set BM func pointers and try again | |
282 | */ | |
283 | ret_val = e1000e_determine_phy_address(hw); | |
284 | if (ret_val) { | |
285 | hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; | |
286 | hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; | |
287 | ret_val = e1000e_determine_phy_address(hw); | |
288 | if (ret_val) | |
289 | return ret_val; | |
290 | } | |
291 | ||
bc7f75fa AK |
292 | phy->id = 0; |
293 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && | |
294 | (i++ < 100)) { | |
295 | msleep(1); | |
296 | ret_val = e1000e_get_phy_id(hw); | |
297 | if (ret_val) | |
298 | return ret_val; | |
299 | } | |
300 | ||
301 | /* Verify phy id */ | |
302 | switch (phy->id) { | |
303 | case IGP03E1000_E_PHY_ID: | |
304 | phy->type = e1000_phy_igp_3; | |
305 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
306 | break; | |
307 | case IFE_E_PHY_ID: | |
308 | case IFE_PLUS_E_PHY_ID: | |
309 | case IFE_C_E_PHY_ID: | |
310 | phy->type = e1000_phy_ife; | |
311 | phy->autoneg_mask = E1000_ALL_NOT_GIG; | |
312 | break; | |
97ac8cae BA |
313 | case BME1000_E_PHY_ID: |
314 | phy->type = e1000_phy_bm; | |
315 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
316 | hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; | |
317 | hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; | |
318 | hw->phy.ops.commit_phy = e1000e_phy_sw_reset; | |
319 | break; | |
bc7f75fa AK |
320 | default: |
321 | return -E1000_ERR_PHY; | |
322 | break; | |
323 | } | |
324 | ||
a4f58f54 BA |
325 | phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; |
326 | ||
bc7f75fa AK |
327 | return 0; |
328 | } | |
329 | ||
330 | /** | |
331 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers | |
332 | * @hw: pointer to the HW structure | |
333 | * | |
334 | * Initialize family-specific NVM parameters and function | |
335 | * pointers. | |
336 | **/ | |
337 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |
338 | { | |
339 | struct e1000_nvm_info *nvm = &hw->nvm; | |
340 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
148675a7 | 341 | u32 gfpreg, sector_base_addr, sector_end_addr; |
bc7f75fa AK |
342 | u16 i; |
343 | ||
ad68076e | 344 | /* Can't read flash registers if the register set isn't mapped. */ |
bc7f75fa AK |
345 | if (!hw->flash_address) { |
346 | hw_dbg(hw, "ERROR: Flash registers not mapped\n"); | |
347 | return -E1000_ERR_CONFIG; | |
348 | } | |
349 | ||
350 | nvm->type = e1000_nvm_flash_sw; | |
351 | ||
352 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
353 | ||
ad68076e BA |
354 | /* |
355 | * sector_X_addr is a "sector"-aligned address (4096 bytes) | |
bc7f75fa | 356 | * Add 1 to sector_end_addr since this sector is included in |
ad68076e BA |
357 | * the overall size. |
358 | */ | |
bc7f75fa AK |
359 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
360 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; | |
361 | ||
362 | /* flash_base_addr is byte-aligned */ | |
363 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; | |
364 | ||
ad68076e BA |
365 | /* |
366 | * find total size of the NVM, then cut in half since the total | |
367 | * size represents two separate NVM banks. | |
368 | */ | |
bc7f75fa AK |
369 | nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
370 | << FLASH_SECTOR_ADDR_SHIFT; | |
371 | nvm->flash_bank_size /= 2; | |
372 | /* Adjust to word count */ | |
373 | nvm->flash_bank_size /= sizeof(u16); | |
374 | ||
375 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; | |
376 | ||
377 | /* Clear shadow ram */ | |
378 | for (i = 0; i < nvm->word_size; i++) { | |
379 | dev_spec->shadow_ram[i].modified = 0; | |
380 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | /** | |
387 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers | |
388 | * @hw: pointer to the HW structure | |
389 | * | |
390 | * Initialize family-specific MAC parameters and function | |
391 | * pointers. | |
392 | **/ | |
393 | static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) | |
394 | { | |
395 | struct e1000_hw *hw = &adapter->hw; | |
396 | struct e1000_mac_info *mac = &hw->mac; | |
397 | ||
398 | /* Set media type function pointer */ | |
318a94d6 | 399 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
400 | |
401 | /* Set mta register count */ | |
402 | mac->mta_reg_count = 32; | |
403 | /* Set rar entry count */ | |
404 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; | |
405 | if (mac->type == e1000_ich8lan) | |
406 | mac->rar_entry_count--; | |
407 | /* Set if manageability features are enabled. */ | |
408 | mac->arc_subsystem_valid = 1; | |
409 | ||
a4f58f54 BA |
410 | /* LED operations */ |
411 | switch (mac->type) { | |
412 | case e1000_ich8lan: | |
413 | case e1000_ich9lan: | |
414 | case e1000_ich10lan: | |
415 | /* ID LED init */ | |
416 | mac->ops.id_led_init = e1000e_id_led_init; | |
417 | /* setup LED */ | |
418 | mac->ops.setup_led = e1000e_setup_led_generic; | |
419 | /* cleanup LED */ | |
420 | mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; | |
421 | /* turn on/off LED */ | |
422 | mac->ops.led_on = e1000_led_on_ich8lan; | |
423 | mac->ops.led_off = e1000_led_off_ich8lan; | |
424 | break; | |
425 | case e1000_pchlan: | |
426 | /* ID LED init */ | |
427 | mac->ops.id_led_init = e1000_id_led_init_pchlan; | |
428 | /* setup LED */ | |
429 | mac->ops.setup_led = e1000_setup_led_pchlan; | |
430 | /* cleanup LED */ | |
431 | mac->ops.cleanup_led = e1000_cleanup_led_pchlan; | |
432 | /* turn on/off LED */ | |
433 | mac->ops.led_on = e1000_led_on_pchlan; | |
434 | mac->ops.led_off = e1000_led_off_pchlan; | |
435 | break; | |
436 | default: | |
437 | break; | |
438 | } | |
439 | ||
bc7f75fa AK |
440 | /* Enable PCS Lock-loss workaround for ICH8 */ |
441 | if (mac->type == e1000_ich8lan) | |
442 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
7d3cabbc BA |
447 | /** |
448 | * e1000_check_for_copper_link_ich8lan - Check for link (Copper) | |
449 | * @hw: pointer to the HW structure | |
450 | * | |
451 | * Checks to see of the link status of the hardware has changed. If a | |
452 | * change in link status has been detected, then we read the PHY registers | |
453 | * to get the current speed/duplex if link exists. | |
454 | **/ | |
455 | static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |
456 | { | |
457 | struct e1000_mac_info *mac = &hw->mac; | |
458 | s32 ret_val; | |
459 | bool link; | |
460 | ||
461 | /* | |
462 | * We only want to go out to the PHY registers to see if Auto-Neg | |
463 | * has completed and/or if our link status has changed. The | |
464 | * get_link_status flag is set upon receiving a Link Status | |
465 | * Change or Rx Sequence Error interrupt. | |
466 | */ | |
467 | if (!mac->get_link_status) { | |
468 | ret_val = 0; | |
469 | goto out; | |
470 | } | |
471 | ||
472 | if (hw->mac.type == e1000_pchlan) { | |
473 | ret_val = e1000e_write_kmrn_reg(hw, | |
474 | E1000_KMRNCTRLSTA_K1_CONFIG, | |
475 | E1000_KMRNCTRLSTA_K1_ENABLE); | |
476 | if (ret_val) | |
477 | goto out; | |
478 | } | |
479 | ||
480 | /* | |
481 | * First we want to see if the MII Status Register reports | |
482 | * link. If so, then we want to get the current speed/duplex | |
483 | * of the PHY. | |
484 | */ | |
485 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
486 | if (ret_val) | |
487 | goto out; | |
488 | ||
489 | if (!link) | |
490 | goto out; /* No link detected */ | |
491 | ||
492 | mac->get_link_status = false; | |
493 | ||
494 | if (hw->phy.type == e1000_phy_82578) { | |
495 | ret_val = e1000_link_stall_workaround_hv(hw); | |
496 | if (ret_val) | |
497 | goto out; | |
498 | } | |
499 | ||
500 | /* | |
501 | * Check if there was DownShift, must be checked | |
502 | * immediately after link-up | |
503 | */ | |
504 | e1000e_check_downshift(hw); | |
505 | ||
506 | /* | |
507 | * If we are forcing speed/duplex, then we simply return since | |
508 | * we have already determined whether we have link or not. | |
509 | */ | |
510 | if (!mac->autoneg) { | |
511 | ret_val = -E1000_ERR_CONFIG; | |
512 | goto out; | |
513 | } | |
514 | ||
515 | /* | |
516 | * Auto-Neg is enabled. Auto Speed Detection takes care | |
517 | * of MAC speed/duplex configuration. So we only need to | |
518 | * configure Collision Distance in the MAC. | |
519 | */ | |
520 | e1000e_config_collision_dist(hw); | |
521 | ||
522 | /* | |
523 | * Configure Flow Control now that Auto-Neg has completed. | |
524 | * First, we need to restore the desired flow control | |
525 | * settings because we may have had to re-autoneg with a | |
526 | * different link partner. | |
527 | */ | |
528 | ret_val = e1000e_config_fc_after_link_up(hw); | |
529 | if (ret_val) | |
530 | hw_dbg(hw, "Error configuring flow control\n"); | |
531 | ||
532 | out: | |
533 | return ret_val; | |
534 | } | |
535 | ||
69e3fd8c | 536 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
537 | { |
538 | struct e1000_hw *hw = &adapter->hw; | |
539 | s32 rc; | |
540 | ||
541 | rc = e1000_init_mac_params_ich8lan(adapter); | |
542 | if (rc) | |
543 | return rc; | |
544 | ||
545 | rc = e1000_init_nvm_params_ich8lan(hw); | |
546 | if (rc) | |
547 | return rc; | |
548 | ||
a4f58f54 BA |
549 | if (hw->mac.type == e1000_pchlan) |
550 | rc = e1000_init_phy_params_pchlan(hw); | |
551 | else | |
552 | rc = e1000_init_phy_params_ich8lan(hw); | |
bc7f75fa AK |
553 | if (rc) |
554 | return rc; | |
555 | ||
2adc55c9 BA |
556 | if (adapter->hw.phy.type == e1000_phy_ife) { |
557 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; | |
558 | adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; | |
559 | } | |
560 | ||
bc7f75fa AK |
561 | if ((adapter->hw.mac.type == e1000_ich8lan) && |
562 | (adapter->hw.phy.type == e1000_phy_igp_3)) | |
563 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
717d438d | 568 | static DEFINE_MUTEX(nvm_mutex); |
717d438d | 569 | |
bc7f75fa AK |
570 | /** |
571 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | |
572 | * @hw: pointer to the HW structure | |
573 | * | |
574 | * Acquires the software control flag for performing NVM and PHY | |
575 | * operations. This is a function pointer entry point only called by | |
576 | * read/write routines for the PHY and NVM parts. | |
577 | **/ | |
578 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |
579 | { | |
373a88d7 BA |
580 | u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; |
581 | s32 ret_val = 0; | |
bc7f75fa | 582 | |
95b866d5 | 583 | might_sleep(); |
717d438d | 584 | |
0a834a36 | 585 | mutex_lock(&nvm_mutex); |
717d438d | 586 | |
bc7f75fa AK |
587 | while (timeout) { |
588 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
373a88d7 BA |
589 | if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) |
590 | break; | |
bc7f75fa | 591 | |
373a88d7 BA |
592 | mdelay(1); |
593 | timeout--; | |
594 | } | |
595 | ||
596 | if (!timeout) { | |
597 | hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n"); | |
598 | ret_val = -E1000_ERR_CONFIG; | |
599 | goto out; | |
600 | } | |
601 | ||
602 | timeout = PHY_CFG_TIMEOUT * 2; | |
603 | ||
604 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
605 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
606 | ||
607 | while (timeout) { | |
608 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
609 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
610 | break; | |
a4f58f54 | 611 | |
bc7f75fa AK |
612 | mdelay(1); |
613 | timeout--; | |
614 | } | |
615 | ||
616 | if (!timeout) { | |
373a88d7 | 617 | hw_dbg(hw, "Failed to acquire the semaphore.\n"); |
2e2e8d53 BA |
618 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
619 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
373a88d7 BA |
620 | ret_val = -E1000_ERR_CONFIG; |
621 | goto out; | |
bc7f75fa AK |
622 | } |
623 | ||
373a88d7 BA |
624 | out: |
625 | if (ret_val) | |
626 | mutex_unlock(&nvm_mutex); | |
627 | ||
628 | return ret_val; | |
bc7f75fa AK |
629 | } |
630 | ||
631 | /** | |
632 | * e1000_release_swflag_ich8lan - Release software control flag | |
633 | * @hw: pointer to the HW structure | |
634 | * | |
635 | * Releases the software control flag for performing NVM and PHY operations. | |
636 | * This is a function pointer entry point only called by read/write | |
637 | * routines for the PHY and NVM parts. | |
638 | **/ | |
639 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |
640 | { | |
641 | u32 extcnf_ctrl; | |
642 | ||
643 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
644 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
645 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
717d438d | 646 | |
717d438d | 647 | mutex_unlock(&nvm_mutex); |
bc7f75fa AK |
648 | } |
649 | ||
4662e82b BA |
650 | /** |
651 | * e1000_check_mng_mode_ich8lan - Checks management mode | |
652 | * @hw: pointer to the HW structure | |
653 | * | |
654 | * This checks if the adapter has manageability enabled. | |
655 | * This is a function pointer entry point only called by read/write | |
656 | * routines for the PHY and NVM parts. | |
657 | **/ | |
658 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) | |
659 | { | |
660 | u32 fwsm = er32(FWSM); | |
661 | ||
662 | return (fwsm & E1000_FWSM_MODE_MASK) == | |
663 | (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); | |
664 | } | |
665 | ||
bc7f75fa AK |
666 | /** |
667 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked | |
668 | * @hw: pointer to the HW structure | |
669 | * | |
670 | * Checks if firmware is blocking the reset of the PHY. | |
671 | * This is a function pointer entry point only called by | |
672 | * reset routines. | |
673 | **/ | |
674 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) | |
675 | { | |
676 | u32 fwsm; | |
677 | ||
678 | fwsm = er32(FWSM); | |
679 | ||
680 | return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; | |
681 | } | |
682 | ||
683 | /** | |
684 | * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex | |
685 | * @hw: pointer to the HW structure | |
686 | * | |
687 | * Forces the speed and duplex settings of the PHY. | |
688 | * This is a function pointer entry point only called by | |
689 | * PHY setup routines. | |
690 | **/ | |
691 | static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) | |
692 | { | |
693 | struct e1000_phy_info *phy = &hw->phy; | |
694 | s32 ret_val; | |
695 | u16 data; | |
696 | bool link; | |
697 | ||
698 | if (phy->type != e1000_phy_ife) { | |
699 | ret_val = e1000e_phy_force_speed_duplex_igp(hw); | |
700 | return ret_val; | |
701 | } | |
702 | ||
703 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | |
704 | if (ret_val) | |
705 | return ret_val; | |
706 | ||
707 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
708 | ||
709 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | |
710 | if (ret_val) | |
711 | return ret_val; | |
712 | ||
713 | /* Disable MDI-X support for 10/100 */ | |
714 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
715 | if (ret_val) | |
716 | return ret_val; | |
717 | ||
718 | data &= ~IFE_PMC_AUTO_MDIX; | |
719 | data &= ~IFE_PMC_FORCE_MDIX; | |
720 | ||
721 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
722 | if (ret_val) | |
723 | return ret_val; | |
724 | ||
725 | hw_dbg(hw, "IFE PMC: %X\n", data); | |
726 | ||
727 | udelay(1); | |
728 | ||
318a94d6 | 729 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
730 | hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); |
731 | ||
732 | ret_val = e1000e_phy_has_link_generic(hw, | |
733 | PHY_FORCE_LIMIT, | |
734 | 100000, | |
735 | &link); | |
736 | if (ret_val) | |
737 | return ret_val; | |
738 | ||
739 | if (!link) | |
740 | hw_dbg(hw, "Link taking longer than expected.\n"); | |
741 | ||
742 | /* Try once more */ | |
743 | ret_val = e1000e_phy_has_link_generic(hw, | |
744 | PHY_FORCE_LIMIT, | |
745 | 100000, | |
746 | &link); | |
747 | if (ret_val) | |
748 | return ret_val; | |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
a4f58f54 BA |
754 | /** |
755 | * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be | |
756 | * done after every PHY reset. | |
757 | **/ | |
758 | static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |
759 | { | |
760 | s32 ret_val = 0; | |
761 | ||
762 | if (hw->mac.type != e1000_pchlan) | |
763 | return ret_val; | |
764 | ||
765 | if (((hw->phy.type == e1000_phy_82577) && | |
766 | ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || | |
767 | ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { | |
768 | /* Disable generation of early preamble */ | |
769 | ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); | |
770 | if (ret_val) | |
771 | return ret_val; | |
772 | ||
773 | /* Preamble tuning for SSC */ | |
774 | ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204); | |
775 | if (ret_val) | |
776 | return ret_val; | |
777 | } | |
778 | ||
779 | if (hw->phy.type == e1000_phy_82578) { | |
780 | /* | |
781 | * Return registers to default by doing a soft reset then | |
782 | * writing 0x3140 to the control register. | |
783 | */ | |
784 | if (hw->phy.revision < 2) { | |
785 | e1000e_phy_sw_reset(hw); | |
786 | ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); | |
787 | } | |
788 | } | |
789 | ||
790 | /* Select page 0 */ | |
791 | ret_val = hw->phy.ops.acquire_phy(hw); | |
792 | if (ret_val) | |
793 | return ret_val; | |
794 | hw->phy.addr = 1; | |
795 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); | |
796 | hw->phy.ops.release_phy(hw); | |
797 | ||
798 | return ret_val; | |
799 | } | |
800 | ||
fc0c7760 BA |
801 | /** |
802 | * e1000_lan_init_done_ich8lan - Check for PHY config completion | |
803 | * @hw: pointer to the HW structure | |
804 | * | |
805 | * Check the appropriate indication the MAC has finished configuring the | |
806 | * PHY after a software reset. | |
807 | **/ | |
808 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) | |
809 | { | |
810 | u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; | |
811 | ||
812 | /* Wait for basic configuration completes before proceeding */ | |
813 | do { | |
814 | data = er32(STATUS); | |
815 | data &= E1000_STATUS_LAN_INIT_DONE; | |
816 | udelay(100); | |
817 | } while ((!data) && --loop); | |
818 | ||
819 | /* | |
820 | * If basic configuration is incomplete before the above loop | |
821 | * count reaches 0, loading the configuration from NVM will | |
822 | * leave the PHY in a bad state possibly resulting in no link. | |
823 | */ | |
824 | if (loop == 0) | |
825 | hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); | |
826 | ||
827 | /* Clear the Init Done bit for the next init event */ | |
828 | data = er32(STATUS); | |
829 | data &= ~E1000_STATUS_LAN_INIT_DONE; | |
830 | ew32(STATUS, data); | |
831 | } | |
832 | ||
bc7f75fa AK |
833 | /** |
834 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset | |
835 | * @hw: pointer to the HW structure | |
836 | * | |
837 | * Resets the PHY | |
838 | * This is a function pointer entry point called by drivers | |
839 | * or other shared routines. | |
840 | **/ | |
841 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |
842 | { | |
843 | struct e1000_phy_info *phy = &hw->phy; | |
844 | u32 i; | |
845 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; | |
846 | s32 ret_val; | |
bc7f75fa AK |
847 | u16 word_addr, reg_data, reg_addr, phy_page = 0; |
848 | ||
849 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
850 | if (ret_val) | |
851 | return ret_val; | |
852 | ||
fc0c7760 BA |
853 | /* Allow time for h/w to get to a quiescent state after reset */ |
854 | mdelay(10); | |
855 | ||
a4f58f54 BA |
856 | if (hw->mac.type == e1000_pchlan) { |
857 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); | |
858 | if (ret_val) | |
859 | return ret_val; | |
860 | } | |
861 | ||
ad68076e BA |
862 | /* |
863 | * Initialize the PHY from the NVM on ICH platforms. This | |
bc7f75fa AK |
864 | * is needed due to an issue where the NVM configuration is |
865 | * not properly autoloaded after power transitions. | |
866 | * Therefore, after each PHY reset, we will load the | |
867 | * configuration data out of the NVM manually. | |
868 | */ | |
869 | if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { | |
870 | struct e1000_adapter *adapter = hw->adapter; | |
871 | ||
872 | /* Check if SW needs configure the PHY */ | |
873 | if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || | |
874 | (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M)) | |
875 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; | |
876 | else | |
877 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; | |
878 | ||
879 | data = er32(FEXTNVM); | |
880 | if (!(data & sw_cfg_mask)) | |
881 | return 0; | |
882 | ||
fc0c7760 BA |
883 | /* Wait for basic configuration completes before proceeding */ |
884 | e1000_lan_init_done_ich8lan(hw); | |
bc7f75fa | 885 | |
ad68076e BA |
886 | /* |
887 | * Make sure HW does not configure LCD from PHY | |
888 | * extended configuration before SW configuration | |
889 | */ | |
bc7f75fa AK |
890 | data = er32(EXTCNF_CTRL); |
891 | if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) | |
892 | return 0; | |
893 | ||
894 | cnf_size = er32(EXTCNF_SIZE); | |
895 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; | |
896 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; | |
897 | if (!cnf_size) | |
898 | return 0; | |
899 | ||
900 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; | |
901 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; | |
902 | ||
ad68076e | 903 | /* Configure LCD from extended configuration region. */ |
bc7f75fa AK |
904 | |
905 | /* cnf_base_addr is in DWORD */ | |
906 | word_addr = (u16)(cnf_base_addr << 1); | |
907 | ||
908 | for (i = 0; i < cnf_size; i++) { | |
909 | ret_val = e1000_read_nvm(hw, | |
910 | (word_addr + i * 2), | |
911 | 1, | |
912 | ®_data); | |
913 | if (ret_val) | |
914 | return ret_val; | |
915 | ||
916 | ret_val = e1000_read_nvm(hw, | |
917 | (word_addr + i * 2 + 1), | |
918 | 1, | |
919 | ®_addr); | |
920 | if (ret_val) | |
921 | return ret_val; | |
922 | ||
923 | /* Save off the PHY page for future writes. */ | |
924 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { | |
925 | phy_page = reg_data; | |
926 | continue; | |
927 | } | |
928 | ||
929 | reg_addr |= phy_page; | |
930 | ||
931 | ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); | |
932 | if (ret_val) | |
933 | return ret_val; | |
934 | } | |
935 | } | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | /** | |
941 | * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states | |
942 | * @hw: pointer to the HW structure | |
943 | * | |
944 | * Populates "phy" structure with various feature states. | |
945 | * This function is only called by other family-specific | |
946 | * routines. | |
947 | **/ | |
948 | static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) | |
949 | { | |
950 | struct e1000_phy_info *phy = &hw->phy; | |
951 | s32 ret_val; | |
952 | u16 data; | |
953 | bool link; | |
954 | ||
955 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
956 | if (ret_val) | |
957 | return ret_val; | |
958 | ||
959 | if (!link) { | |
960 | hw_dbg(hw, "Phy info is only valid if link is up\n"); | |
961 | return -E1000_ERR_CONFIG; | |
962 | } | |
963 | ||
964 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
965 | if (ret_val) | |
966 | return ret_val; | |
967 | phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); | |
968 | ||
969 | if (phy->polarity_correction) { | |
a4f58f54 | 970 | ret_val = phy->ops.check_polarity(hw); |
bc7f75fa AK |
971 | if (ret_val) |
972 | return ret_val; | |
973 | } else { | |
974 | /* Polarity is forced */ | |
975 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
976 | ? e1000_rev_polarity_reversed | |
977 | : e1000_rev_polarity_normal; | |
978 | } | |
979 | ||
980 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
981 | if (ret_val) | |
982 | return ret_val; | |
983 | ||
984 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); | |
985 | ||
986 | /* The following parameters are undefined for 10/100 operation. */ | |
987 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
988 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
989 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
994 | /** | |
995 | * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info | |
996 | * @hw: pointer to the HW structure | |
997 | * | |
998 | * Wrapper for calling the get_phy_info routines for the appropriate phy type. | |
999 | * This is a function pointer entry point called by drivers | |
1000 | * or other shared routines. | |
1001 | **/ | |
1002 | static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) | |
1003 | { | |
1004 | switch (hw->phy.type) { | |
1005 | case e1000_phy_ife: | |
1006 | return e1000_get_phy_info_ife_ich8lan(hw); | |
1007 | break; | |
1008 | case e1000_phy_igp_3: | |
97ac8cae | 1009 | case e1000_phy_bm: |
a4f58f54 BA |
1010 | case e1000_phy_82578: |
1011 | case e1000_phy_82577: | |
bc7f75fa AK |
1012 | return e1000e_get_phy_info_igp(hw); |
1013 | break; | |
1014 | default: | |
1015 | break; | |
1016 | } | |
1017 | ||
1018 | return -E1000_ERR_PHY_TYPE; | |
1019 | } | |
1020 | ||
1021 | /** | |
1022 | * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY | |
1023 | * @hw: pointer to the HW structure | |
1024 | * | |
489815ce | 1025 | * Polarity is determined on the polarity reversal feature being enabled. |
bc7f75fa AK |
1026 | * This function is only called by other family-specific |
1027 | * routines. | |
1028 | **/ | |
1029 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) | |
1030 | { | |
1031 | struct e1000_phy_info *phy = &hw->phy; | |
1032 | s32 ret_val; | |
1033 | u16 phy_data, offset, mask; | |
1034 | ||
ad68076e BA |
1035 | /* |
1036 | * Polarity is determined based on the reversal feature being enabled. | |
bc7f75fa AK |
1037 | */ |
1038 | if (phy->polarity_correction) { | |
1039 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
1040 | mask = IFE_PESC_POLARITY_REVERSED; | |
1041 | } else { | |
1042 | offset = IFE_PHY_SPECIAL_CONTROL; | |
1043 | mask = IFE_PSC_FORCE_POLARITY; | |
1044 | } | |
1045 | ||
1046 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1047 | ||
1048 | if (!ret_val) | |
1049 | phy->cable_polarity = (phy_data & mask) | |
1050 | ? e1000_rev_polarity_reversed | |
1051 | : e1000_rev_polarity_normal; | |
1052 | ||
1053 | return ret_val; | |
1054 | } | |
1055 | ||
1056 | /** | |
1057 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | |
1058 | * @hw: pointer to the HW structure | |
1059 | * @active: TRUE to enable LPLU, FALSE to disable | |
1060 | * | |
1061 | * Sets the LPLU D0 state according to the active flag. When | |
1062 | * activating LPLU this function also disables smart speed | |
1063 | * and vice versa. LPLU will not be activated unless the | |
1064 | * device autonegotiation advertisement meets standards of | |
1065 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
1066 | * This is a function pointer entry point only called by | |
1067 | * PHY setup routines. | |
1068 | **/ | |
1069 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
1070 | { | |
1071 | struct e1000_phy_info *phy = &hw->phy; | |
1072 | u32 phy_ctrl; | |
1073 | s32 ret_val = 0; | |
1074 | u16 data; | |
1075 | ||
97ac8cae | 1076 | if (phy->type == e1000_phy_ife) |
bc7f75fa AK |
1077 | return ret_val; |
1078 | ||
1079 | phy_ctrl = er32(PHY_CTRL); | |
1080 | ||
1081 | if (active) { | |
1082 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
1083 | ew32(PHY_CTRL, phy_ctrl); | |
1084 | ||
60f1292f BA |
1085 | if (phy->type != e1000_phy_igp_3) |
1086 | return 0; | |
1087 | ||
ad68076e BA |
1088 | /* |
1089 | * Call gig speed drop workaround on LPLU before accessing | |
1090 | * any PHY registers | |
1091 | */ | |
60f1292f | 1092 | if (hw->mac.type == e1000_ich8lan) |
bc7f75fa AK |
1093 | e1000e_gig_downshift_workaround_ich8lan(hw); |
1094 | ||
1095 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
1096 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
1097 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1098 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
1099 | if (ret_val) | |
1100 | return ret_val; | |
1101 | } else { | |
1102 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
1103 | ew32(PHY_CTRL, phy_ctrl); | |
1104 | ||
60f1292f BA |
1105 | if (phy->type != e1000_phy_igp_3) |
1106 | return 0; | |
1107 | ||
ad68076e BA |
1108 | /* |
1109 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1110 | * during Dx states where the power conservation is most |
1111 | * important. During driver activity we should enable | |
ad68076e BA |
1112 | * SmartSpeed, so performance is maintained. |
1113 | */ | |
bc7f75fa AK |
1114 | if (phy->smart_speed == e1000_smart_speed_on) { |
1115 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1116 | &data); |
bc7f75fa AK |
1117 | if (ret_val) |
1118 | return ret_val; | |
1119 | ||
1120 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
1121 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1122 | data); |
bc7f75fa AK |
1123 | if (ret_val) |
1124 | return ret_val; | |
1125 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1126 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1127 | &data); |
bc7f75fa AK |
1128 | if (ret_val) |
1129 | return ret_val; | |
1130 | ||
1131 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1132 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1133 | data); |
bc7f75fa AK |
1134 | if (ret_val) |
1135 | return ret_val; | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | /** | |
1143 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state | |
1144 | * @hw: pointer to the HW structure | |
1145 | * @active: TRUE to enable LPLU, FALSE to disable | |
1146 | * | |
1147 | * Sets the LPLU D3 state according to the active flag. When | |
1148 | * activating LPLU this function also disables smart speed | |
1149 | * and vice versa. LPLU will not be activated unless the | |
1150 | * device autonegotiation advertisement meets standards of | |
1151 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
1152 | * This is a function pointer entry point only called by | |
1153 | * PHY setup routines. | |
1154 | **/ | |
1155 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
1156 | { | |
1157 | struct e1000_phy_info *phy = &hw->phy; | |
1158 | u32 phy_ctrl; | |
1159 | s32 ret_val; | |
1160 | u16 data; | |
1161 | ||
1162 | phy_ctrl = er32(PHY_CTRL); | |
1163 | ||
1164 | if (!active) { | |
1165 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
1166 | ew32(PHY_CTRL, phy_ctrl); | |
60f1292f BA |
1167 | |
1168 | if (phy->type != e1000_phy_igp_3) | |
1169 | return 0; | |
1170 | ||
ad68076e BA |
1171 | /* |
1172 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1173 | * during Dx states where the power conservation is most |
1174 | * important. During driver activity we should enable | |
ad68076e BA |
1175 | * SmartSpeed, so performance is maintained. |
1176 | */ | |
bc7f75fa | 1177 | if (phy->smart_speed == e1000_smart_speed_on) { |
ad68076e BA |
1178 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1179 | &data); | |
bc7f75fa AK |
1180 | if (ret_val) |
1181 | return ret_val; | |
1182 | ||
1183 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
1184 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1185 | data); | |
bc7f75fa AK |
1186 | if (ret_val) |
1187 | return ret_val; | |
1188 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
ad68076e BA |
1189 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1190 | &data); | |
bc7f75fa AK |
1191 | if (ret_val) |
1192 | return ret_val; | |
1193 | ||
1194 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
1195 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1196 | data); | |
bc7f75fa AK |
1197 | if (ret_val) |
1198 | return ret_val; | |
1199 | } | |
1200 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1201 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1202 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1203 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
1204 | ew32(PHY_CTRL, phy_ctrl); | |
1205 | ||
60f1292f BA |
1206 | if (phy->type != e1000_phy_igp_3) |
1207 | return 0; | |
1208 | ||
ad68076e BA |
1209 | /* |
1210 | * Call gig speed drop workaround on LPLU before accessing | |
1211 | * any PHY registers | |
1212 | */ | |
60f1292f | 1213 | if (hw->mac.type == e1000_ich8lan) |
bc7f75fa AK |
1214 | e1000e_gig_downshift_workaround_ich8lan(hw); |
1215 | ||
1216 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
ad68076e | 1217 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
bc7f75fa AK |
1218 | if (ret_val) |
1219 | return ret_val; | |
1220 | ||
1221 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e | 1222 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
bc7f75fa AK |
1223 | } |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
f4187b56 BA |
1228 | /** |
1229 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 | |
1230 | * @hw: pointer to the HW structure | |
1231 | * @bank: pointer to the variable that returns the active bank | |
1232 | * | |
1233 | * Reads signature byte from the NVM using the flash access registers. | |
e243455d | 1234 | * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. |
f4187b56 BA |
1235 | **/ |
1236 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | |
1237 | { | |
e243455d | 1238 | u32 eecd; |
f4187b56 | 1239 | struct e1000_nvm_info *nvm = &hw->nvm; |
f4187b56 BA |
1240 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); |
1241 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; | |
e243455d BA |
1242 | u8 sig_byte = 0; |
1243 | s32 ret_val = 0; | |
f4187b56 | 1244 | |
e243455d BA |
1245 | switch (hw->mac.type) { |
1246 | case e1000_ich8lan: | |
1247 | case e1000_ich9lan: | |
1248 | eecd = er32(EECD); | |
1249 | if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == | |
1250 | E1000_EECD_SEC1VAL_VALID_MASK) { | |
1251 | if (eecd & E1000_EECD_SEC1VAL) | |
1252 | *bank = 1; | |
1253 | else | |
1254 | *bank = 0; | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | hw_dbg(hw, "Unable to determine valid NVM bank via EEC - " | |
1259 | "reading flash signature\n"); | |
1260 | /* fall-thru */ | |
1261 | default: | |
1262 | /* set bank to 0 in case flash read fails */ | |
1263 | *bank = 0; | |
1264 | ||
1265 | /* Check bank 0 */ | |
1266 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, | |
1267 | &sig_byte); | |
1268 | if (ret_val) | |
1269 | return ret_val; | |
1270 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
1271 | E1000_ICH_NVM_SIG_VALUE) { | |
f4187b56 | 1272 | *bank = 0; |
e243455d BA |
1273 | return 0; |
1274 | } | |
f4187b56 | 1275 | |
e243455d BA |
1276 | /* Check bank 1 */ |
1277 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + | |
1278 | bank1_offset, | |
1279 | &sig_byte); | |
1280 | if (ret_val) | |
1281 | return ret_val; | |
1282 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
1283 | E1000_ICH_NVM_SIG_VALUE) { | |
1284 | *bank = 1; | |
1285 | return 0; | |
f4187b56 | 1286 | } |
e243455d BA |
1287 | |
1288 | hw_dbg(hw, "ERROR: No valid NVM bank present\n"); | |
1289 | return -E1000_ERR_NVM; | |
f4187b56 BA |
1290 | } |
1291 | ||
1292 | return 0; | |
1293 | } | |
1294 | ||
bc7f75fa AK |
1295 | /** |
1296 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | |
1297 | * @hw: pointer to the HW structure | |
1298 | * @offset: The offset (in bytes) of the word(s) to read. | |
1299 | * @words: Size of data to read in words | |
1300 | * @data: Pointer to the word(s) to read at offset. | |
1301 | * | |
1302 | * Reads a word(s) from the NVM using the flash access registers. | |
1303 | **/ | |
1304 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
1305 | u16 *data) | |
1306 | { | |
1307 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1308 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1309 | u32 act_offset; | |
148675a7 | 1310 | s32 ret_val = 0; |
f4187b56 | 1311 | u32 bank = 0; |
bc7f75fa AK |
1312 | u16 i, word; |
1313 | ||
1314 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
1315 | (words == 0)) { | |
1316 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
1317 | return -E1000_ERR_NVM; | |
1318 | } | |
1319 | ||
1320 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1321 | if (ret_val) | |
e243455d | 1322 | goto out; |
bc7f75fa | 1323 | |
f4187b56 | 1324 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
148675a7 BA |
1325 | if (ret_val) { |
1326 | hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n"); | |
1327 | bank = 0; | |
1328 | } | |
f4187b56 BA |
1329 | |
1330 | act_offset = (bank) ? nvm->flash_bank_size : 0; | |
bc7f75fa AK |
1331 | act_offset += offset; |
1332 | ||
148675a7 | 1333 | ret_val = 0; |
bc7f75fa AK |
1334 | for (i = 0; i < words; i++) { |
1335 | if ((dev_spec->shadow_ram) && | |
1336 | (dev_spec->shadow_ram[offset+i].modified)) { | |
1337 | data[i] = dev_spec->shadow_ram[offset+i].value; | |
1338 | } else { | |
1339 | ret_val = e1000_read_flash_word_ich8lan(hw, | |
1340 | act_offset + i, | |
1341 | &word); | |
1342 | if (ret_val) | |
1343 | break; | |
1344 | data[i] = word; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | e1000_release_swflag_ich8lan(hw); | |
1349 | ||
e243455d BA |
1350 | out: |
1351 | if (ret_val) | |
1352 | hw_dbg(hw, "NVM read error: %d\n", ret_val); | |
1353 | ||
bc7f75fa AK |
1354 | return ret_val; |
1355 | } | |
1356 | ||
1357 | /** | |
1358 | * e1000_flash_cycle_init_ich8lan - Initialize flash | |
1359 | * @hw: pointer to the HW structure | |
1360 | * | |
1361 | * This function does initial flash setup so that a new read/write/erase cycle | |
1362 | * can be started. | |
1363 | **/ | |
1364 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |
1365 | { | |
1366 | union ich8_hws_flash_status hsfsts; | |
1367 | s32 ret_val = -E1000_ERR_NVM; | |
1368 | s32 i = 0; | |
1369 | ||
1370 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1371 | ||
1372 | /* Check if the flash descriptor is valid */ | |
1373 | if (hsfsts.hsf_status.fldesvalid == 0) { | |
1374 | hw_dbg(hw, "Flash descriptor invalid. " | |
1375 | "SW Sequencing must be used."); | |
1376 | return -E1000_ERR_NVM; | |
1377 | } | |
1378 | ||
1379 | /* Clear FCERR and DAEL in hw status by writing 1 */ | |
1380 | hsfsts.hsf_status.flcerr = 1; | |
1381 | hsfsts.hsf_status.dael = 1; | |
1382 | ||
1383 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1384 | ||
ad68076e BA |
1385 | /* |
1386 | * Either we should have a hardware SPI cycle in progress | |
bc7f75fa AK |
1387 | * bit to check against, in order to start a new cycle or |
1388 | * FDONE bit should be changed in the hardware so that it | |
489815ce | 1389 | * is 1 after hardware reset, which can then be used as an |
bc7f75fa AK |
1390 | * indication whether a cycle is in progress or has been |
1391 | * completed. | |
1392 | */ | |
1393 | ||
1394 | if (hsfsts.hsf_status.flcinprog == 0) { | |
ad68076e BA |
1395 | /* |
1396 | * There is no cycle running at present, | |
1397 | * so we can start a cycle | |
1398 | * Begin by setting Flash Cycle Done. | |
1399 | */ | |
bc7f75fa AK |
1400 | hsfsts.hsf_status.flcdone = 1; |
1401 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1402 | ret_val = 0; | |
1403 | } else { | |
ad68076e BA |
1404 | /* |
1405 | * otherwise poll for sometime so the current | |
1406 | * cycle has a chance to end before giving up. | |
1407 | */ | |
bc7f75fa AK |
1408 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
1409 | hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); | |
1410 | if (hsfsts.hsf_status.flcinprog == 0) { | |
1411 | ret_val = 0; | |
1412 | break; | |
1413 | } | |
1414 | udelay(1); | |
1415 | } | |
1416 | if (ret_val == 0) { | |
ad68076e BA |
1417 | /* |
1418 | * Successful in waiting for previous cycle to timeout, | |
1419 | * now set the Flash Cycle Done. | |
1420 | */ | |
bc7f75fa AK |
1421 | hsfsts.hsf_status.flcdone = 1; |
1422 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1423 | } else { | |
1424 | hw_dbg(hw, "Flash controller busy, cannot get access"); | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | return ret_val; | |
1429 | } | |
1430 | ||
1431 | /** | |
1432 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) | |
1433 | * @hw: pointer to the HW structure | |
1434 | * @timeout: maximum time to wait for completion | |
1435 | * | |
1436 | * This function starts a flash cycle and waits for its completion. | |
1437 | **/ | |
1438 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) | |
1439 | { | |
1440 | union ich8_hws_flash_ctrl hsflctl; | |
1441 | union ich8_hws_flash_status hsfsts; | |
1442 | s32 ret_val = -E1000_ERR_NVM; | |
1443 | u32 i = 0; | |
1444 | ||
1445 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
1446 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1447 | hsflctl.hsf_ctrl.flcgo = 1; | |
1448 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1449 | ||
1450 | /* wait till FDONE bit is set to 1 */ | |
1451 | do { | |
1452 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1453 | if (hsfsts.hsf_status.flcdone == 1) | |
1454 | break; | |
1455 | udelay(1); | |
1456 | } while (i++ < timeout); | |
1457 | ||
1458 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) | |
1459 | return 0; | |
1460 | ||
1461 | return ret_val; | |
1462 | } | |
1463 | ||
1464 | /** | |
1465 | * e1000_read_flash_word_ich8lan - Read word from flash | |
1466 | * @hw: pointer to the HW structure | |
1467 | * @offset: offset to data location | |
1468 | * @data: pointer to the location for storing the data | |
1469 | * | |
1470 | * Reads the flash word at offset into data. Offset is converted | |
1471 | * to bytes before read. | |
1472 | **/ | |
1473 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
1474 | u16 *data) | |
1475 | { | |
1476 | /* Must convert offset into bytes. */ | |
1477 | offset <<= 1; | |
1478 | ||
1479 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); | |
1480 | } | |
1481 | ||
f4187b56 BA |
1482 | /** |
1483 | * e1000_read_flash_byte_ich8lan - Read byte from flash | |
1484 | * @hw: pointer to the HW structure | |
1485 | * @offset: The offset of the byte to read. | |
1486 | * @data: Pointer to a byte to store the value read. | |
1487 | * | |
1488 | * Reads a single byte from the NVM using the flash access registers. | |
1489 | **/ | |
1490 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
1491 | u8 *data) | |
1492 | { | |
1493 | s32 ret_val; | |
1494 | u16 word = 0; | |
1495 | ||
1496 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); | |
1497 | if (ret_val) | |
1498 | return ret_val; | |
1499 | ||
1500 | *data = (u8)word; | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
bc7f75fa AK |
1505 | /** |
1506 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | |
1507 | * @hw: pointer to the HW structure | |
1508 | * @offset: The offset (in bytes) of the byte or word to read. | |
1509 | * @size: Size of data to read, 1=byte 2=word | |
1510 | * @data: Pointer to the word to store the value read. | |
1511 | * | |
1512 | * Reads a byte or word from the NVM using the flash access registers. | |
1513 | **/ | |
1514 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1515 | u8 size, u16 *data) | |
1516 | { | |
1517 | union ich8_hws_flash_status hsfsts; | |
1518 | union ich8_hws_flash_ctrl hsflctl; | |
1519 | u32 flash_linear_addr; | |
1520 | u32 flash_data = 0; | |
1521 | s32 ret_val = -E1000_ERR_NVM; | |
1522 | u8 count = 0; | |
1523 | ||
1524 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1525 | return -E1000_ERR_NVM; | |
1526 | ||
1527 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1528 | hw->nvm.flash_base_addr; | |
1529 | ||
1530 | do { | |
1531 | udelay(1); | |
1532 | /* Steps */ | |
1533 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1534 | if (ret_val != 0) | |
1535 | break; | |
1536 | ||
1537 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1538 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1539 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
1540 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | |
1541 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1542 | ||
1543 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1544 | ||
1545 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1546 | ICH_FLASH_READ_COMMAND_TIMEOUT); | |
1547 | ||
ad68076e BA |
1548 | /* |
1549 | * Check if FCERR is set to 1, if set to 1, clear it | |
bc7f75fa AK |
1550 | * and try the whole sequence a few more times, else |
1551 | * read in (shift in) the Flash Data0, the order is | |
ad68076e BA |
1552 | * least significant byte first msb to lsb |
1553 | */ | |
bc7f75fa AK |
1554 | if (ret_val == 0) { |
1555 | flash_data = er32flash(ICH_FLASH_FDATA0); | |
1556 | if (size == 1) { | |
1557 | *data = (u8)(flash_data & 0x000000FF); | |
1558 | } else if (size == 2) { | |
1559 | *data = (u16)(flash_data & 0x0000FFFF); | |
1560 | } | |
1561 | break; | |
1562 | } else { | |
ad68076e BA |
1563 | /* |
1564 | * If we've gotten here, then things are probably | |
bc7f75fa AK |
1565 | * completely hosed, but if the error condition is |
1566 | * detected, it won't hurt to give it another try... | |
1567 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1568 | */ | |
1569 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1570 | if (hsfsts.hsf_status.flcerr == 1) { | |
1571 | /* Repeat for some time before giving up. */ | |
1572 | continue; | |
1573 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
1574 | hw_dbg(hw, "Timeout error - flash cycle " | |
1575 | "did not complete."); | |
1576 | break; | |
1577 | } | |
1578 | } | |
1579 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1580 | ||
1581 | return ret_val; | |
1582 | } | |
1583 | ||
1584 | /** | |
1585 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM | |
1586 | * @hw: pointer to the HW structure | |
1587 | * @offset: The offset (in bytes) of the word(s) to write. | |
1588 | * @words: Size of data to write in words | |
1589 | * @data: Pointer to the word(s) to write at offset. | |
1590 | * | |
1591 | * Writes a byte or word to the NVM using the flash access registers. | |
1592 | **/ | |
1593 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
1594 | u16 *data) | |
1595 | { | |
1596 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1597 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
bc7f75fa AK |
1598 | u16 i; |
1599 | ||
1600 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
1601 | (words == 0)) { | |
1602 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
1603 | return -E1000_ERR_NVM; | |
1604 | } | |
1605 | ||
bc7f75fa AK |
1606 | for (i = 0; i < words; i++) { |
1607 | dev_spec->shadow_ram[offset+i].modified = 1; | |
1608 | dev_spec->shadow_ram[offset+i].value = data[i]; | |
1609 | } | |
1610 | ||
bc7f75fa AK |
1611 | return 0; |
1612 | } | |
1613 | ||
1614 | /** | |
1615 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM | |
1616 | * @hw: pointer to the HW structure | |
1617 | * | |
1618 | * The NVM checksum is updated by calling the generic update_nvm_checksum, | |
1619 | * which writes the checksum to the shadow ram. The changes in the shadow | |
1620 | * ram are then committed to the EEPROM by processing each bank at a time | |
1621 | * checking for the modified bit and writing only the pending changes. | |
489815ce | 1622 | * After a successful commit, the shadow ram is cleared and is ready for |
bc7f75fa AK |
1623 | * future writes. |
1624 | **/ | |
1625 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1626 | { | |
1627 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1628 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
f4187b56 | 1629 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
bc7f75fa AK |
1630 | s32 ret_val; |
1631 | u16 data; | |
1632 | ||
1633 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
1634 | if (ret_val) | |
e243455d | 1635 | goto out; |
bc7f75fa AK |
1636 | |
1637 | if (nvm->type != e1000_nvm_flash_sw) | |
e243455d | 1638 | goto out; |
bc7f75fa AK |
1639 | |
1640 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1641 | if (ret_val) | |
e243455d | 1642 | goto out; |
bc7f75fa | 1643 | |
ad68076e BA |
1644 | /* |
1645 | * We're writing to the opposite bank so if we're on bank 1, | |
bc7f75fa | 1646 | * write to bank 0 etc. We also need to erase the segment that |
ad68076e BA |
1647 | * is going to be written |
1648 | */ | |
f4187b56 | 1649 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
e243455d | 1650 | if (ret_val) { |
148675a7 BA |
1651 | hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n"); |
1652 | bank = 0; | |
e243455d | 1653 | } |
f4187b56 BA |
1654 | |
1655 | if (bank == 0) { | |
bc7f75fa AK |
1656 | new_bank_offset = nvm->flash_bank_size; |
1657 | old_bank_offset = 0; | |
e243455d BA |
1658 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
1659 | if (ret_val) { | |
1660 | e1000_release_swflag_ich8lan(hw); | |
1661 | goto out; | |
1662 | } | |
bc7f75fa AK |
1663 | } else { |
1664 | old_bank_offset = nvm->flash_bank_size; | |
1665 | new_bank_offset = 0; | |
e243455d BA |
1666 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
1667 | if (ret_val) { | |
1668 | e1000_release_swflag_ich8lan(hw); | |
1669 | goto out; | |
1670 | } | |
bc7f75fa AK |
1671 | } |
1672 | ||
1673 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
ad68076e BA |
1674 | /* |
1675 | * Determine whether to write the value stored | |
bc7f75fa | 1676 | * in the other NVM bank or a modified value stored |
ad68076e BA |
1677 | * in the shadow RAM |
1678 | */ | |
bc7f75fa AK |
1679 | if (dev_spec->shadow_ram[i].modified) { |
1680 | data = dev_spec->shadow_ram[i].value; | |
1681 | } else { | |
e243455d BA |
1682 | ret_val = e1000_read_flash_word_ich8lan(hw, i + |
1683 | old_bank_offset, | |
1684 | &data); | |
1685 | if (ret_val) | |
1686 | break; | |
bc7f75fa AK |
1687 | } |
1688 | ||
ad68076e BA |
1689 | /* |
1690 | * If the word is 0x13, then make sure the signature bits | |
bc7f75fa AK |
1691 | * (15:14) are 11b until the commit has completed. |
1692 | * This will allow us to write 10b which indicates the | |
1693 | * signature is valid. We want to do this after the write | |
1694 | * has completed so that we don't mark the segment valid | |
ad68076e BA |
1695 | * while the write is still in progress |
1696 | */ | |
bc7f75fa AK |
1697 | if (i == E1000_ICH_NVM_SIG_WORD) |
1698 | data |= E1000_ICH_NVM_SIG_MASK; | |
1699 | ||
1700 | /* Convert offset to bytes. */ | |
1701 | act_offset = (i + new_bank_offset) << 1; | |
1702 | ||
1703 | udelay(100); | |
1704 | /* Write the bytes to the new bank. */ | |
1705 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1706 | act_offset, | |
1707 | (u8)data); | |
1708 | if (ret_val) | |
1709 | break; | |
1710 | ||
1711 | udelay(100); | |
1712 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1713 | act_offset + 1, | |
1714 | (u8)(data >> 8)); | |
1715 | if (ret_val) | |
1716 | break; | |
1717 | } | |
1718 | ||
ad68076e BA |
1719 | /* |
1720 | * Don't bother writing the segment valid bits if sector | |
1721 | * programming failed. | |
1722 | */ | |
bc7f75fa | 1723 | if (ret_val) { |
4a770358 | 1724 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
bc7f75fa AK |
1725 | hw_dbg(hw, "Flash commit failed.\n"); |
1726 | e1000_release_swflag_ich8lan(hw); | |
e243455d | 1727 | goto out; |
bc7f75fa AK |
1728 | } |
1729 | ||
ad68076e BA |
1730 | /* |
1731 | * Finally validate the new segment by setting bit 15:14 | |
bc7f75fa AK |
1732 | * to 10b in word 0x13 , this can be done without an |
1733 | * erase as well since these bits are 11 to start with | |
ad68076e BA |
1734 | * and we need to change bit 14 to 0b |
1735 | */ | |
bc7f75fa | 1736 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
e243455d BA |
1737 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
1738 | if (ret_val) { | |
1739 | e1000_release_swflag_ich8lan(hw); | |
1740 | goto out; | |
1741 | } | |
bc7f75fa AK |
1742 | data &= 0xBFFF; |
1743 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1744 | act_offset * 2 + 1, | |
1745 | (u8)(data >> 8)); | |
1746 | if (ret_val) { | |
1747 | e1000_release_swflag_ich8lan(hw); | |
e243455d | 1748 | goto out; |
bc7f75fa AK |
1749 | } |
1750 | ||
ad68076e BA |
1751 | /* |
1752 | * And invalidate the previously valid segment by setting | |
bc7f75fa AK |
1753 | * its signature word (0x13) high_byte to 0b. This can be |
1754 | * done without an erase because flash erase sets all bits | |
ad68076e BA |
1755 | * to 1's. We can write 1's to 0's without an erase |
1756 | */ | |
bc7f75fa AK |
1757 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
1758 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | |
1759 | if (ret_val) { | |
1760 | e1000_release_swflag_ich8lan(hw); | |
e243455d | 1761 | goto out; |
bc7f75fa AK |
1762 | } |
1763 | ||
1764 | /* Great! Everything worked, we can now clear the cached entries. */ | |
1765 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
1766 | dev_spec->shadow_ram[i].modified = 0; | |
1767 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
1768 | } | |
1769 | ||
1770 | e1000_release_swflag_ich8lan(hw); | |
1771 | ||
ad68076e BA |
1772 | /* |
1773 | * Reload the EEPROM, or else modifications will not appear | |
bc7f75fa AK |
1774 | * until after the next adapter reset. |
1775 | */ | |
1776 | e1000e_reload_nvm(hw); | |
1777 | msleep(10); | |
1778 | ||
e243455d BA |
1779 | out: |
1780 | if (ret_val) | |
1781 | hw_dbg(hw, "NVM update error: %d\n", ret_val); | |
1782 | ||
bc7f75fa AK |
1783 | return ret_val; |
1784 | } | |
1785 | ||
1786 | /** | |
1787 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum | |
1788 | * @hw: pointer to the HW structure | |
1789 | * | |
1790 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. | |
1791 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not | |
1792 | * calculated, in which case we need to calculate the checksum and set bit 6. | |
1793 | **/ | |
1794 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1795 | { | |
1796 | s32 ret_val; | |
1797 | u16 data; | |
1798 | ||
ad68076e BA |
1799 | /* |
1800 | * Read 0x19 and check bit 6. If this bit is 0, the checksum | |
bc7f75fa AK |
1801 | * needs to be fixed. This bit is an indication that the NVM |
1802 | * was prepared by OEM software and did not calculate the | |
1803 | * checksum...a likely scenario. | |
1804 | */ | |
1805 | ret_val = e1000_read_nvm(hw, 0x19, 1, &data); | |
1806 | if (ret_val) | |
1807 | return ret_val; | |
1808 | ||
1809 | if ((data & 0x40) == 0) { | |
1810 | data |= 0x40; | |
1811 | ret_val = e1000_write_nvm(hw, 0x19, 1, &data); | |
1812 | if (ret_val) | |
1813 | return ret_val; | |
1814 | ret_val = e1000e_update_nvm_checksum(hw); | |
1815 | if (ret_val) | |
1816 | return ret_val; | |
1817 | } | |
1818 | ||
1819 | return e1000e_validate_nvm_checksum_generic(hw); | |
1820 | } | |
1821 | ||
4a770358 BA |
1822 | /** |
1823 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only | |
1824 | * @hw: pointer to the HW structure | |
1825 | * | |
1826 | * To prevent malicious write/erase of the NVM, set it to be read-only | |
1827 | * so that the hardware ignores all write/erase cycles of the NVM via | |
1828 | * the flash control registers. The shadow-ram copy of the NVM will | |
1829 | * still be updated, however any updates to this copy will not stick | |
1830 | * across driver reloads. | |
1831 | **/ | |
1832 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | |
1833 | { | |
1834 | union ich8_flash_protected_range pr0; | |
1835 | union ich8_hws_flash_status hsfsts; | |
1836 | u32 gfpreg; | |
1837 | s32 ret_val; | |
1838 | ||
1839 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1840 | if (ret_val) | |
1841 | return; | |
1842 | ||
1843 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
1844 | ||
1845 | /* Write-protect GbE Sector of NVM */ | |
1846 | pr0.regval = er32flash(ICH_FLASH_PR0); | |
1847 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; | |
1848 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); | |
1849 | pr0.range.wpe = true; | |
1850 | ew32flash(ICH_FLASH_PR0, pr0.regval); | |
1851 | ||
1852 | /* | |
1853 | * Lock down a subset of GbE Flash Control Registers, e.g. | |
1854 | * PR0 to prevent the write-protection from being lifted. | |
1855 | * Once FLOCKDN is set, the registers protected by it cannot | |
1856 | * be written until FLOCKDN is cleared by a hardware reset. | |
1857 | */ | |
1858 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1859 | hsfsts.hsf_status.flockdn = true; | |
1860 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1861 | ||
1862 | e1000_release_swflag_ich8lan(hw); | |
1863 | } | |
1864 | ||
bc7f75fa AK |
1865 | /** |
1866 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM | |
1867 | * @hw: pointer to the HW structure | |
1868 | * @offset: The offset (in bytes) of the byte/word to read. | |
1869 | * @size: Size of data to read, 1=byte 2=word | |
1870 | * @data: The byte(s) to write to the NVM. | |
1871 | * | |
1872 | * Writes one/two bytes to the NVM using the flash access registers. | |
1873 | **/ | |
1874 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1875 | u8 size, u16 data) | |
1876 | { | |
1877 | union ich8_hws_flash_status hsfsts; | |
1878 | union ich8_hws_flash_ctrl hsflctl; | |
1879 | u32 flash_linear_addr; | |
1880 | u32 flash_data = 0; | |
1881 | s32 ret_val; | |
1882 | u8 count = 0; | |
1883 | ||
1884 | if (size < 1 || size > 2 || data > size * 0xff || | |
1885 | offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1886 | return -E1000_ERR_NVM; | |
1887 | ||
1888 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1889 | hw->nvm.flash_base_addr; | |
1890 | ||
1891 | do { | |
1892 | udelay(1); | |
1893 | /* Steps */ | |
1894 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1895 | if (ret_val) | |
1896 | break; | |
1897 | ||
1898 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1899 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1900 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
1901 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | |
1902 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1903 | ||
1904 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1905 | ||
1906 | if (size == 1) | |
1907 | flash_data = (u32)data & 0x00FF; | |
1908 | else | |
1909 | flash_data = (u32)data; | |
1910 | ||
1911 | ew32flash(ICH_FLASH_FDATA0, flash_data); | |
1912 | ||
ad68076e BA |
1913 | /* |
1914 | * check if FCERR is set to 1 , if set to 1, clear it | |
1915 | * and try the whole sequence a few more times else done | |
1916 | */ | |
bc7f75fa AK |
1917 | ret_val = e1000_flash_cycle_ich8lan(hw, |
1918 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); | |
1919 | if (!ret_val) | |
1920 | break; | |
1921 | ||
ad68076e BA |
1922 | /* |
1923 | * If we're here, then things are most likely | |
bc7f75fa AK |
1924 | * completely hosed, but if the error condition |
1925 | * is detected, it won't hurt to give it another | |
1926 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1927 | */ | |
1928 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1929 | if (hsfsts.hsf_status.flcerr == 1) | |
1930 | /* Repeat for some time before giving up. */ | |
1931 | continue; | |
1932 | if (hsfsts.hsf_status.flcdone == 0) { | |
1933 | hw_dbg(hw, "Timeout error - flash cycle " | |
1934 | "did not complete."); | |
1935 | break; | |
1936 | } | |
1937 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1938 | ||
1939 | return ret_val; | |
1940 | } | |
1941 | ||
1942 | /** | |
1943 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM | |
1944 | * @hw: pointer to the HW structure | |
1945 | * @offset: The index of the byte to read. | |
1946 | * @data: The byte to write to the NVM. | |
1947 | * | |
1948 | * Writes a single byte to the NVM using the flash access registers. | |
1949 | **/ | |
1950 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
1951 | u8 data) | |
1952 | { | |
1953 | u16 word = (u16)data; | |
1954 | ||
1955 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); | |
1956 | } | |
1957 | ||
1958 | /** | |
1959 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM | |
1960 | * @hw: pointer to the HW structure | |
1961 | * @offset: The offset of the byte to write. | |
1962 | * @byte: The byte to write to the NVM. | |
1963 | * | |
1964 | * Writes a single byte to the NVM using the flash access registers. | |
1965 | * Goes through a retry algorithm before giving up. | |
1966 | **/ | |
1967 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
1968 | u32 offset, u8 byte) | |
1969 | { | |
1970 | s32 ret_val; | |
1971 | u16 program_retries; | |
1972 | ||
1973 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1974 | if (!ret_val) | |
1975 | return ret_val; | |
1976 | ||
1977 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
1978 | hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); | |
1979 | udelay(100); | |
1980 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1981 | if (!ret_val) | |
1982 | break; | |
1983 | } | |
1984 | if (program_retries == 100) | |
1985 | return -E1000_ERR_NVM; | |
1986 | ||
1987 | return 0; | |
1988 | } | |
1989 | ||
1990 | /** | |
1991 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM | |
1992 | * @hw: pointer to the HW structure | |
1993 | * @bank: 0 for first bank, 1 for second bank, etc. | |
1994 | * | |
1995 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. | |
1996 | * bank N is 4096 * N + flash_reg_addr. | |
1997 | **/ | |
1998 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) | |
1999 | { | |
2000 | struct e1000_nvm_info *nvm = &hw->nvm; | |
2001 | union ich8_hws_flash_status hsfsts; | |
2002 | union ich8_hws_flash_ctrl hsflctl; | |
2003 | u32 flash_linear_addr; | |
2004 | /* bank size is in 16bit words - adjust to bytes */ | |
2005 | u32 flash_bank_size = nvm->flash_bank_size * 2; | |
2006 | s32 ret_val; | |
2007 | s32 count = 0; | |
2008 | s32 iteration; | |
2009 | s32 sector_size; | |
2010 | s32 j; | |
2011 | ||
2012 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
2013 | ||
ad68076e BA |
2014 | /* |
2015 | * Determine HW Sector size: Read BERASE bits of hw flash status | |
2016 | * register | |
2017 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
bc7f75fa AK |
2018 | * consecutive sectors. The start index for the nth Hw sector |
2019 | * can be calculated as = bank * 4096 + n * 256 | |
2020 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | |
2021 | * The start index for the nth Hw sector can be calculated | |
2022 | * as = bank * 4096 | |
2023 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 | |
2024 | * (ich9 only, otherwise error condition) | |
2025 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 | |
2026 | */ | |
2027 | switch (hsfsts.hsf_status.berasesz) { | |
2028 | case 0: | |
2029 | /* Hw sector size 256 */ | |
2030 | sector_size = ICH_FLASH_SEG_SIZE_256; | |
2031 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; | |
2032 | break; | |
2033 | case 1: | |
2034 | sector_size = ICH_FLASH_SEG_SIZE_4K; | |
28c9195a | 2035 | iteration = 1; |
bc7f75fa AK |
2036 | break; |
2037 | case 2: | |
148675a7 BA |
2038 | sector_size = ICH_FLASH_SEG_SIZE_8K; |
2039 | iteration = 1; | |
bc7f75fa AK |
2040 | break; |
2041 | case 3: | |
2042 | sector_size = ICH_FLASH_SEG_SIZE_64K; | |
28c9195a | 2043 | iteration = 1; |
bc7f75fa AK |
2044 | break; |
2045 | default: | |
2046 | return -E1000_ERR_NVM; | |
2047 | } | |
2048 | ||
2049 | /* Start with the base address, then add the sector offset. */ | |
2050 | flash_linear_addr = hw->nvm.flash_base_addr; | |
148675a7 | 2051 | flash_linear_addr += (bank) ? flash_bank_size : 0; |
bc7f75fa AK |
2052 | |
2053 | for (j = 0; j < iteration ; j++) { | |
2054 | do { | |
2055 | /* Steps */ | |
2056 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
2057 | if (ret_val) | |
2058 | return ret_val; | |
2059 | ||
ad68076e BA |
2060 | /* |
2061 | * Write a value 11 (block Erase) in Flash | |
2062 | * Cycle field in hw flash control | |
2063 | */ | |
bc7f75fa AK |
2064 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
2065 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
2066 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
2067 | ||
ad68076e BA |
2068 | /* |
2069 | * Write the last 24 bits of an index within the | |
bc7f75fa AK |
2070 | * block into Flash Linear address field in Flash |
2071 | * Address. | |
2072 | */ | |
2073 | flash_linear_addr += (j * sector_size); | |
2074 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
2075 | ||
2076 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
2077 | ICH_FLASH_ERASE_COMMAND_TIMEOUT); | |
2078 | if (ret_val == 0) | |
2079 | break; | |
2080 | ||
ad68076e BA |
2081 | /* |
2082 | * Check if FCERR is set to 1. If 1, | |
bc7f75fa | 2083 | * clear it and try the whole sequence |
ad68076e BA |
2084 | * a few more times else Done |
2085 | */ | |
bc7f75fa AK |
2086 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
2087 | if (hsfsts.hsf_status.flcerr == 1) | |
ad68076e | 2088 | /* repeat for some time before giving up */ |
bc7f75fa AK |
2089 | continue; |
2090 | else if (hsfsts.hsf_status.flcdone == 0) | |
2091 | return ret_val; | |
2092 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
2093 | } | |
2094 | ||
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | /** | |
2099 | * e1000_valid_led_default_ich8lan - Set the default LED settings | |
2100 | * @hw: pointer to the HW structure | |
2101 | * @data: Pointer to the LED settings | |
2102 | * | |
2103 | * Reads the LED default settings from the NVM to data. If the NVM LED | |
2104 | * settings is all 0's or F's, set the LED default to a valid LED default | |
2105 | * setting. | |
2106 | **/ | |
2107 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |
2108 | { | |
2109 | s32 ret_val; | |
2110 | ||
2111 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
2112 | if (ret_val) { | |
2113 | hw_dbg(hw, "NVM Read Error\n"); | |
2114 | return ret_val; | |
2115 | } | |
2116 | ||
2117 | if (*data == ID_LED_RESERVED_0000 || | |
2118 | *data == ID_LED_RESERVED_FFFF) | |
2119 | *data = ID_LED_DEFAULT_ICH8LAN; | |
2120 | ||
2121 | return 0; | |
2122 | } | |
2123 | ||
a4f58f54 BA |
2124 | /** |
2125 | * e1000_id_led_init_pchlan - store LED configurations | |
2126 | * @hw: pointer to the HW structure | |
2127 | * | |
2128 | * PCH does not control LEDs via the LEDCTL register, rather it uses | |
2129 | * the PHY LED configuration register. | |
2130 | * | |
2131 | * PCH also does not have an "always on" or "always off" mode which | |
2132 | * complicates the ID feature. Instead of using the "on" mode to indicate | |
2133 | * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()), | |
2134 | * use "link_up" mode. The LEDs will still ID on request if there is no | |
2135 | * link based on logic in e1000_led_[on|off]_pchlan(). | |
2136 | **/ | |
2137 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) | |
2138 | { | |
2139 | struct e1000_mac_info *mac = &hw->mac; | |
2140 | s32 ret_val; | |
2141 | const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; | |
2142 | const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; | |
2143 | u16 data, i, temp, shift; | |
2144 | ||
2145 | /* Get default ID LED modes */ | |
2146 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); | |
2147 | if (ret_val) | |
2148 | goto out; | |
2149 | ||
2150 | mac->ledctl_default = er32(LEDCTL); | |
2151 | mac->ledctl_mode1 = mac->ledctl_default; | |
2152 | mac->ledctl_mode2 = mac->ledctl_default; | |
2153 | ||
2154 | for (i = 0; i < 4; i++) { | |
2155 | temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; | |
2156 | shift = (i * 5); | |
2157 | switch (temp) { | |
2158 | case ID_LED_ON1_DEF2: | |
2159 | case ID_LED_ON1_ON2: | |
2160 | case ID_LED_ON1_OFF2: | |
2161 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
2162 | mac->ledctl_mode1 |= (ledctl_on << shift); | |
2163 | break; | |
2164 | case ID_LED_OFF1_DEF2: | |
2165 | case ID_LED_OFF1_ON2: | |
2166 | case ID_LED_OFF1_OFF2: | |
2167 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
2168 | mac->ledctl_mode1 |= (ledctl_off << shift); | |
2169 | break; | |
2170 | default: | |
2171 | /* Do nothing */ | |
2172 | break; | |
2173 | } | |
2174 | switch (temp) { | |
2175 | case ID_LED_DEF1_ON2: | |
2176 | case ID_LED_ON1_ON2: | |
2177 | case ID_LED_OFF1_ON2: | |
2178 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
2179 | mac->ledctl_mode2 |= (ledctl_on << shift); | |
2180 | break; | |
2181 | case ID_LED_DEF1_OFF2: | |
2182 | case ID_LED_ON1_OFF2: | |
2183 | case ID_LED_OFF1_OFF2: | |
2184 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
2185 | mac->ledctl_mode2 |= (ledctl_off << shift); | |
2186 | break; | |
2187 | default: | |
2188 | /* Do nothing */ | |
2189 | break; | |
2190 | } | |
2191 | } | |
2192 | ||
2193 | out: | |
2194 | return ret_val; | |
2195 | } | |
2196 | ||
bc7f75fa AK |
2197 | /** |
2198 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width | |
2199 | * @hw: pointer to the HW structure | |
2200 | * | |
2201 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability | |
2202 | * register, so the the bus width is hard coded. | |
2203 | **/ | |
2204 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |
2205 | { | |
2206 | struct e1000_bus_info *bus = &hw->bus; | |
2207 | s32 ret_val; | |
2208 | ||
2209 | ret_val = e1000e_get_bus_info_pcie(hw); | |
2210 | ||
ad68076e BA |
2211 | /* |
2212 | * ICH devices are "PCI Express"-ish. They have | |
bc7f75fa AK |
2213 | * a configuration space, but do not contain |
2214 | * PCI Express Capability registers, so bus width | |
2215 | * must be hardcoded. | |
2216 | */ | |
2217 | if (bus->width == e1000_bus_width_unknown) | |
2218 | bus->width = e1000_bus_width_pcie_x1; | |
2219 | ||
2220 | return ret_val; | |
2221 | } | |
2222 | ||
2223 | /** | |
2224 | * e1000_reset_hw_ich8lan - Reset the hardware | |
2225 | * @hw: pointer to the HW structure | |
2226 | * | |
2227 | * Does a full reset of the hardware which includes a reset of the PHY and | |
2228 | * MAC. | |
2229 | **/ | |
2230 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |
2231 | { | |
2232 | u32 ctrl, icr, kab; | |
2233 | s32 ret_val; | |
2234 | ||
ad68076e BA |
2235 | /* |
2236 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
2237 | * on the last TLP read/write transaction when MAC is reset. |
2238 | */ | |
2239 | ret_val = e1000e_disable_pcie_master(hw); | |
2240 | if (ret_val) { | |
2241 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
2242 | } | |
2243 | ||
2244 | hw_dbg(hw, "Masking off all interrupts\n"); | |
2245 | ew32(IMC, 0xffffffff); | |
2246 | ||
ad68076e BA |
2247 | /* |
2248 | * Disable the Transmit and Receive units. Then delay to allow | |
bc7f75fa AK |
2249 | * any pending transactions to complete before we hit the MAC |
2250 | * with the global reset. | |
2251 | */ | |
2252 | ew32(RCTL, 0); | |
2253 | ew32(TCTL, E1000_TCTL_PSP); | |
2254 | e1e_flush(); | |
2255 | ||
2256 | msleep(10); | |
2257 | ||
2258 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | |
2259 | if (hw->mac.type == e1000_ich8lan) { | |
2260 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
2261 | ew32(PBA, E1000_PBA_8K); | |
2262 | /* Set Packet Buffer Size to 16k. */ | |
2263 | ew32(PBS, E1000_PBS_16K); | |
2264 | } | |
2265 | ||
2266 | ctrl = er32(CTRL); | |
2267 | ||
2268 | if (!e1000_check_reset_block(hw)) { | |
fc0c7760 BA |
2269 | /* Clear PHY Reset Asserted bit */ |
2270 | if (hw->mac.type >= e1000_pchlan) { | |
2271 | u32 status = er32(STATUS); | |
2272 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); | |
2273 | } | |
2274 | ||
ad68076e BA |
2275 | /* |
2276 | * PHY HW reset requires MAC CORE reset at the same | |
bc7f75fa AK |
2277 | * time to make sure the interface between MAC and the |
2278 | * external PHY is reset. | |
2279 | */ | |
2280 | ctrl |= E1000_CTRL_PHY_RST; | |
2281 | } | |
2282 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
30bb0e0d | 2283 | /* Whether or not the swflag was acquired, we need to reset the part */ |
0285c8dc | 2284 | hw_dbg(hw, "Issuing a global reset to ich8lan\n"); |
bc7f75fa AK |
2285 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
2286 | msleep(20); | |
2287 | ||
fc0c7760 | 2288 | if (!ret_val) |
30bb0e0d | 2289 | e1000_release_swflag_ich8lan(hw); |
37f40239 | 2290 | |
fc0c7760 BA |
2291 | if (ctrl & E1000_CTRL_PHY_RST) |
2292 | ret_val = hw->phy.ops.get_cfg_done(hw); | |
2293 | ||
2294 | if (hw->mac.type >= e1000_ich10lan) { | |
2295 | e1000_lan_init_done_ich8lan(hw); | |
2296 | } else { | |
2297 | ret_val = e1000e_get_auto_rd_done(hw); | |
2298 | if (ret_val) { | |
2299 | /* | |
2300 | * When auto config read does not complete, do not | |
2301 | * return with an error. This can happen in situations | |
2302 | * where there is no eeprom and prevents getting link. | |
2303 | */ | |
2304 | hw_dbg(hw, "Auto Read Done did not complete\n"); | |
2305 | } | |
bc7f75fa AK |
2306 | } |
2307 | ||
7d3cabbc BA |
2308 | /* |
2309 | * For PCH, this write will make sure that any noise | |
2310 | * will be detected as a CRC error and be dropped rather than show up | |
2311 | * as a bad packet to the DMA engine. | |
2312 | */ | |
2313 | if (hw->mac.type == e1000_pchlan) | |
2314 | ew32(CRC_OFFSET, 0x65656565); | |
2315 | ||
bc7f75fa AK |
2316 | ew32(IMC, 0xffffffff); |
2317 | icr = er32(ICR); | |
2318 | ||
2319 | kab = er32(KABGTXD); | |
2320 | kab |= E1000_KABGTXD_BGSQLBIAS; | |
2321 | ew32(KABGTXD, kab); | |
2322 | ||
a4f58f54 BA |
2323 | if (hw->mac.type == e1000_pchlan) |
2324 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); | |
2325 | ||
bc7f75fa AK |
2326 | return ret_val; |
2327 | } | |
2328 | ||
2329 | /** | |
2330 | * e1000_init_hw_ich8lan - Initialize the hardware | |
2331 | * @hw: pointer to the HW structure | |
2332 | * | |
2333 | * Prepares the hardware for transmit and receive by doing the following: | |
2334 | * - initialize hardware bits | |
2335 | * - initialize LED identification | |
2336 | * - setup receive address registers | |
2337 | * - setup flow control | |
489815ce | 2338 | * - setup transmit descriptors |
bc7f75fa AK |
2339 | * - clear statistics |
2340 | **/ | |
2341 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |
2342 | { | |
2343 | struct e1000_mac_info *mac = &hw->mac; | |
2344 | u32 ctrl_ext, txdctl, snoop; | |
2345 | s32 ret_val; | |
2346 | u16 i; | |
2347 | ||
2348 | e1000_initialize_hw_bits_ich8lan(hw); | |
2349 | ||
2350 | /* Initialize identification LED */ | |
a4f58f54 | 2351 | ret_val = mac->ops.id_led_init(hw); |
bc7f75fa AK |
2352 | if (ret_val) { |
2353 | hw_dbg(hw, "Error initializing identification LED\n"); | |
2354 | return ret_val; | |
2355 | } | |
2356 | ||
2357 | /* Setup the receive address. */ | |
2358 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
2359 | ||
2360 | /* Zero out the Multicast HASH table */ | |
2361 | hw_dbg(hw, "Zeroing the MTA\n"); | |
2362 | for (i = 0; i < mac->mta_reg_count; i++) | |
2363 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
2364 | ||
fc0c7760 BA |
2365 | /* |
2366 | * The 82578 Rx buffer will stall if wakeup is enabled in host and | |
2367 | * the ME. Reading the BM_WUC register will clear the host wakeup bit. | |
2368 | * Reset the phy after disabling host wakeup to reset the Rx buffer. | |
2369 | */ | |
2370 | if (hw->phy.type == e1000_phy_82578) { | |
2371 | hw->phy.ops.read_phy_reg(hw, BM_WUC, &i); | |
2372 | ret_val = e1000_phy_hw_reset_ich8lan(hw); | |
2373 | if (ret_val) | |
2374 | return ret_val; | |
2375 | } | |
2376 | ||
bc7f75fa AK |
2377 | /* Setup link and flow control */ |
2378 | ret_val = e1000_setup_link_ich8lan(hw); | |
2379 | ||
2380 | /* Set the transmit descriptor write-back policy for both queues */ | |
e9ec2c0f | 2381 | txdctl = er32(TXDCTL(0)); |
bc7f75fa AK |
2382 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
2383 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2384 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
2385 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f JK |
2386 | ew32(TXDCTL(0), txdctl); |
2387 | txdctl = er32(TXDCTL(1)); | |
bc7f75fa AK |
2388 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
2389 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2390 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
2391 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f | 2392 | ew32(TXDCTL(1), txdctl); |
bc7f75fa | 2393 | |
ad68076e BA |
2394 | /* |
2395 | * ICH8 has opposite polarity of no_snoop bits. | |
2396 | * By default, we should use snoop behavior. | |
2397 | */ | |
bc7f75fa AK |
2398 | if (mac->type == e1000_ich8lan) |
2399 | snoop = PCIE_ICH8_SNOOP_ALL; | |
2400 | else | |
2401 | snoop = (u32) ~(PCIE_NO_SNOOP_ALL); | |
2402 | e1000e_set_pcie_no_snoop(hw, snoop); | |
2403 | ||
2404 | ctrl_ext = er32(CTRL_EXT); | |
2405 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
2406 | ew32(CTRL_EXT, ctrl_ext); | |
2407 | ||
ad68076e BA |
2408 | /* |
2409 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
2410 | * important that we do this after we have tried to establish link |
2411 | * because the symbol error count will increment wildly if there | |
2412 | * is no link. | |
2413 | */ | |
2414 | e1000_clear_hw_cntrs_ich8lan(hw); | |
2415 | ||
2416 | return 0; | |
2417 | } | |
2418 | /** | |
2419 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits | |
2420 | * @hw: pointer to the HW structure | |
2421 | * | |
2422 | * Sets/Clears required hardware bits necessary for correctly setting up the | |
2423 | * hardware for transmit and receive. | |
2424 | **/ | |
2425 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |
2426 | { | |
2427 | u32 reg; | |
2428 | ||
2429 | /* Extended Device Control */ | |
2430 | reg = er32(CTRL_EXT); | |
2431 | reg |= (1 << 22); | |
a4f58f54 BA |
2432 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
2433 | if (hw->mac.type >= e1000_pchlan) | |
2434 | reg |= E1000_CTRL_EXT_PHYPDEN; | |
bc7f75fa AK |
2435 | ew32(CTRL_EXT, reg); |
2436 | ||
2437 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 2438 | reg = er32(TXDCTL(0)); |
bc7f75fa | 2439 | reg |= (1 << 22); |
e9ec2c0f | 2440 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
2441 | |
2442 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 2443 | reg = er32(TXDCTL(1)); |
bc7f75fa | 2444 | reg |= (1 << 22); |
e9ec2c0f | 2445 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
2446 | |
2447 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 2448 | reg = er32(TARC(0)); |
bc7f75fa AK |
2449 | if (hw->mac.type == e1000_ich8lan) |
2450 | reg |= (1 << 28) | (1 << 29); | |
2451 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | |
e9ec2c0f | 2452 | ew32(TARC(0), reg); |
bc7f75fa AK |
2453 | |
2454 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 2455 | reg = er32(TARC(1)); |
bc7f75fa AK |
2456 | if (er32(TCTL) & E1000_TCTL_MULR) |
2457 | reg &= ~(1 << 28); | |
2458 | else | |
2459 | reg |= (1 << 28); | |
2460 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | |
e9ec2c0f | 2461 | ew32(TARC(1), reg); |
bc7f75fa AK |
2462 | |
2463 | /* Device Status */ | |
2464 | if (hw->mac.type == e1000_ich8lan) { | |
2465 | reg = er32(STATUS); | |
2466 | reg &= ~(1 << 31); | |
2467 | ew32(STATUS, reg); | |
2468 | } | |
2469 | } | |
2470 | ||
2471 | /** | |
2472 | * e1000_setup_link_ich8lan - Setup flow control and link settings | |
2473 | * @hw: pointer to the HW structure | |
2474 | * | |
2475 | * Determines which flow control settings to use, then configures flow | |
2476 | * control. Calls the appropriate media-specific link configuration | |
2477 | * function. Assuming the adapter has a valid link partner, a valid link | |
2478 | * should be established. Assumes the hardware has previously been reset | |
2479 | * and the transmitter and receiver are not enabled. | |
2480 | **/ | |
2481 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |
2482 | { | |
bc7f75fa AK |
2483 | s32 ret_val; |
2484 | ||
2485 | if (e1000_check_reset_block(hw)) | |
2486 | return 0; | |
2487 | ||
ad68076e BA |
2488 | /* |
2489 | * ICH parts do not have a word in the NVM to determine | |
bc7f75fa AK |
2490 | * the default flow control setting, so we explicitly |
2491 | * set it to full. | |
2492 | */ | |
37289d9c BA |
2493 | if (hw->fc.requested_mode == e1000_fc_default) { |
2494 | /* Workaround h/w hang when Tx flow control enabled */ | |
2495 | if (hw->mac.type == e1000_pchlan) | |
2496 | hw->fc.requested_mode = e1000_fc_rx_pause; | |
2497 | else | |
2498 | hw->fc.requested_mode = e1000_fc_full; | |
2499 | } | |
bc7f75fa | 2500 | |
5c48ef3e BA |
2501 | /* |
2502 | * Save off the requested flow control mode for use later. Depending | |
2503 | * on the link partner's capabilities, we may or may not use this mode. | |
2504 | */ | |
2505 | hw->fc.current_mode = hw->fc.requested_mode; | |
bc7f75fa | 2506 | |
5c48ef3e BA |
2507 | hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", |
2508 | hw->fc.current_mode); | |
bc7f75fa AK |
2509 | |
2510 | /* Continue to configure the copper link. */ | |
2511 | ret_val = e1000_setup_copper_link_ich8lan(hw); | |
2512 | if (ret_val) | |
2513 | return ret_val; | |
2514 | ||
318a94d6 | 2515 | ew32(FCTTV, hw->fc.pause_time); |
a4f58f54 BA |
2516 | if ((hw->phy.type == e1000_phy_82578) || |
2517 | (hw->phy.type == e1000_phy_82577)) { | |
2518 | ret_val = hw->phy.ops.write_phy_reg(hw, | |
2519 | PHY_REG(BM_PORT_CTRL_PAGE, 27), | |
2520 | hw->fc.pause_time); | |
2521 | if (ret_val) | |
2522 | return ret_val; | |
2523 | } | |
bc7f75fa AK |
2524 | |
2525 | return e1000e_set_fc_watermarks(hw); | |
2526 | } | |
2527 | ||
2528 | /** | |
2529 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface | |
2530 | * @hw: pointer to the HW structure | |
2531 | * | |
2532 | * Configures the kumeran interface to the PHY to wait the appropriate time | |
2533 | * when polling the PHY, then call the generic setup_copper_link to finish | |
2534 | * configuring the copper link. | |
2535 | **/ | |
2536 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) | |
2537 | { | |
2538 | u32 ctrl; | |
2539 | s32 ret_val; | |
2540 | u16 reg_data; | |
2541 | ||
2542 | ctrl = er32(CTRL); | |
2543 | ctrl |= E1000_CTRL_SLU; | |
2544 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2545 | ew32(CTRL, ctrl); | |
2546 | ||
ad68076e BA |
2547 | /* |
2548 | * Set the mac to wait the maximum time between each iteration | |
bc7f75fa | 2549 | * and increase the max iterations when polling the phy; |
ad68076e BA |
2550 | * this fixes erroneous timeouts at 10Mbps. |
2551 | */ | |
bc7f75fa AK |
2552 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
2553 | if (ret_val) | |
2554 | return ret_val; | |
2555 | ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
2556 | if (ret_val) | |
2557 | return ret_val; | |
2558 | reg_data |= 0x3F; | |
2559 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
2560 | if (ret_val) | |
2561 | return ret_val; | |
2562 | ||
a4f58f54 BA |
2563 | switch (hw->phy.type) { |
2564 | case e1000_phy_igp_3: | |
bc7f75fa AK |
2565 | ret_val = e1000e_copper_link_setup_igp(hw); |
2566 | if (ret_val) | |
2567 | return ret_val; | |
a4f58f54 BA |
2568 | break; |
2569 | case e1000_phy_bm: | |
2570 | case e1000_phy_82578: | |
97ac8cae BA |
2571 | ret_val = e1000e_copper_link_setup_m88(hw); |
2572 | if (ret_val) | |
2573 | return ret_val; | |
a4f58f54 BA |
2574 | break; |
2575 | case e1000_phy_82577: | |
2576 | ret_val = e1000_copper_link_setup_82577(hw); | |
2577 | if (ret_val) | |
2578 | return ret_val; | |
2579 | break; | |
2580 | case e1000_phy_ife: | |
2581 | ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, | |
2582 | ®_data); | |
97ac8cae BA |
2583 | if (ret_val) |
2584 | return ret_val; | |
2585 | ||
2586 | reg_data &= ~IFE_PMC_AUTO_MDIX; | |
2587 | ||
2588 | switch (hw->phy.mdix) { | |
2589 | case 1: | |
2590 | reg_data &= ~IFE_PMC_FORCE_MDIX; | |
2591 | break; | |
2592 | case 2: | |
2593 | reg_data |= IFE_PMC_FORCE_MDIX; | |
2594 | break; | |
2595 | case 0: | |
2596 | default: | |
2597 | reg_data |= IFE_PMC_AUTO_MDIX; | |
2598 | break; | |
2599 | } | |
a4f58f54 BA |
2600 | ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, |
2601 | reg_data); | |
97ac8cae BA |
2602 | if (ret_val) |
2603 | return ret_val; | |
a4f58f54 BA |
2604 | break; |
2605 | default: | |
2606 | break; | |
97ac8cae | 2607 | } |
bc7f75fa AK |
2608 | return e1000e_setup_copper_link(hw); |
2609 | } | |
2610 | ||
2611 | /** | |
2612 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex | |
2613 | * @hw: pointer to the HW structure | |
2614 | * @speed: pointer to store current link speed | |
2615 | * @duplex: pointer to store the current link duplex | |
2616 | * | |
ad68076e | 2617 | * Calls the generic get_speed_and_duplex to retrieve the current link |
bc7f75fa AK |
2618 | * information and then calls the Kumeran lock loss workaround for links at |
2619 | * gigabit speeds. | |
2620 | **/ | |
2621 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, | |
2622 | u16 *duplex) | |
2623 | { | |
2624 | s32 ret_val; | |
2625 | ||
2626 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); | |
2627 | if (ret_val) | |
2628 | return ret_val; | |
2629 | ||
7d3cabbc BA |
2630 | if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) { |
2631 | ret_val = e1000e_write_kmrn_reg(hw, | |
2632 | E1000_KMRNCTRLSTA_K1_CONFIG, | |
2633 | E1000_KMRNCTRLSTA_K1_DISABLE); | |
2634 | if (ret_val) | |
2635 | return ret_val; | |
2636 | } | |
2637 | ||
bc7f75fa AK |
2638 | if ((hw->mac.type == e1000_ich8lan) && |
2639 | (hw->phy.type == e1000_phy_igp_3) && | |
2640 | (*speed == SPEED_1000)) { | |
2641 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); | |
2642 | } | |
2643 | ||
2644 | return ret_val; | |
2645 | } | |
2646 | ||
2647 | /** | |
2648 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround | |
2649 | * @hw: pointer to the HW structure | |
2650 | * | |
2651 | * Work-around for 82566 Kumeran PCS lock loss: | |
2652 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
2653 | * speed is gigabit- | |
2654 | * 0) if workaround is optionally disabled do nothing | |
2655 | * 1) wait 1ms for Kumeran link to come up | |
2656 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
2657 | * 3) if not set the link is locked (all is good), otherwise... | |
2658 | * 4) reset the PHY | |
2659 | * 5) repeat up to 10 times | |
2660 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
2661 | **/ | |
2662 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |
2663 | { | |
2664 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2665 | u32 phy_ctrl; | |
2666 | s32 ret_val; | |
2667 | u16 i, data; | |
2668 | bool link; | |
2669 | ||
2670 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) | |
2671 | return 0; | |
2672 | ||
ad68076e BA |
2673 | /* |
2674 | * Make sure link is up before proceeding. If not just return. | |
bc7f75fa | 2675 | * Attempting this while link is negotiating fouled up link |
ad68076e BA |
2676 | * stability |
2677 | */ | |
bc7f75fa AK |
2678 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
2679 | if (!link) | |
2680 | return 0; | |
2681 | ||
2682 | for (i = 0; i < 10; i++) { | |
2683 | /* read once to clear */ | |
2684 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
2685 | if (ret_val) | |
2686 | return ret_val; | |
2687 | /* and again to get new status */ | |
2688 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
2689 | if (ret_val) | |
2690 | return ret_val; | |
2691 | ||
2692 | /* check for PCS lock */ | |
2693 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
2694 | return 0; | |
2695 | ||
2696 | /* Issue PHY reset */ | |
2697 | e1000_phy_hw_reset(hw); | |
2698 | mdelay(5); | |
2699 | } | |
2700 | /* Disable GigE link negotiation */ | |
2701 | phy_ctrl = er32(PHY_CTRL); | |
2702 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2703 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2704 | ew32(PHY_CTRL, phy_ctrl); | |
2705 | ||
ad68076e BA |
2706 | /* |
2707 | * Call gig speed drop workaround on Gig disable before accessing | |
2708 | * any PHY registers | |
2709 | */ | |
bc7f75fa AK |
2710 | e1000e_gig_downshift_workaround_ich8lan(hw); |
2711 | ||
2712 | /* unable to acquire PCS lock */ | |
2713 | return -E1000_ERR_PHY; | |
2714 | } | |
2715 | ||
2716 | /** | |
ad68076e | 2717 | * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
bc7f75fa | 2718 | * @hw: pointer to the HW structure |
489815ce | 2719 | * @state: boolean value used to set the current Kumeran workaround state |
bc7f75fa AK |
2720 | * |
2721 | * If ICH8, set the current Kumeran workaround state (enabled - TRUE | |
2722 | * /disabled - FALSE). | |
2723 | **/ | |
2724 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
2725 | bool state) | |
2726 | { | |
2727 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2728 | ||
2729 | if (hw->mac.type != e1000_ich8lan) { | |
2730 | hw_dbg(hw, "Workaround applies to ICH8 only.\n"); | |
2731 | return; | |
2732 | } | |
2733 | ||
2734 | dev_spec->kmrn_lock_loss_workaround_enabled = state; | |
2735 | } | |
2736 | ||
2737 | /** | |
2738 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 | |
2739 | * @hw: pointer to the HW structure | |
2740 | * | |
2741 | * Workaround for 82566 power-down on D3 entry: | |
2742 | * 1) disable gigabit link | |
2743 | * 2) write VR power-down enable | |
2744 | * 3) read it back | |
2745 | * Continue if successful, else issue LCD reset and repeat | |
2746 | **/ | |
2747 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |
2748 | { | |
2749 | u32 reg; | |
2750 | u16 data; | |
2751 | u8 retry = 0; | |
2752 | ||
2753 | if (hw->phy.type != e1000_phy_igp_3) | |
2754 | return; | |
2755 | ||
2756 | /* Try the workaround twice (if needed) */ | |
2757 | do { | |
2758 | /* Disable link */ | |
2759 | reg = er32(PHY_CTRL); | |
2760 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2761 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2762 | ew32(PHY_CTRL, reg); | |
2763 | ||
ad68076e BA |
2764 | /* |
2765 | * Call gig speed drop workaround on Gig disable before | |
2766 | * accessing any PHY registers | |
2767 | */ | |
bc7f75fa AK |
2768 | if (hw->mac.type == e1000_ich8lan) |
2769 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
2770 | ||
2771 | /* Write VR power-down enable */ | |
2772 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2773 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2774 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); | |
2775 | ||
2776 | /* Read it back and test */ | |
2777 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2778 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2779 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) | |
2780 | break; | |
2781 | ||
2782 | /* Issue PHY reset and repeat at most one more time */ | |
2783 | reg = er32(CTRL); | |
2784 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
2785 | retry++; | |
2786 | } while (retry); | |
2787 | } | |
2788 | ||
2789 | /** | |
2790 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working | |
2791 | * @hw: pointer to the HW structure | |
2792 | * | |
2793 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | |
489815ce | 2794 | * LPLU, Gig disable, MDIC PHY reset): |
bc7f75fa AK |
2795 | * 1) Set Kumeran Near-end loopback |
2796 | * 2) Clear Kumeran Near-end loopback | |
2797 | * Should only be called for ICH8[m] devices with IGP_3 Phy. | |
2798 | **/ | |
2799 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |
2800 | { | |
2801 | s32 ret_val; | |
2802 | u16 reg_data; | |
2803 | ||
2804 | if ((hw->mac.type != e1000_ich8lan) || | |
2805 | (hw->phy.type != e1000_phy_igp_3)) | |
2806 | return; | |
2807 | ||
2808 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2809 | ®_data); | |
2810 | if (ret_val) | |
2811 | return; | |
2812 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2813 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2814 | reg_data); | |
2815 | if (ret_val) | |
2816 | return; | |
2817 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2818 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2819 | reg_data); | |
2820 | } | |
2821 | ||
97ac8cae BA |
2822 | /** |
2823 | * e1000e_disable_gig_wol_ich8lan - disable gig during WoL | |
2824 | * @hw: pointer to the HW structure | |
2825 | * | |
2826 | * During S0 to Sx transition, it is possible the link remains at gig | |
2827 | * instead of negotiating to a lower speed. Before going to Sx, set | |
2828 | * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation | |
2829 | * to a lower speed. | |
2830 | * | |
a4f58f54 | 2831 | * Should only be called for applicable parts. |
97ac8cae BA |
2832 | **/ |
2833 | void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) | |
2834 | { | |
2835 | u32 phy_ctrl; | |
2836 | ||
a4f58f54 BA |
2837 | switch (hw->mac.type) { |
2838 | case e1000_ich9lan: | |
2839 | case e1000_ich10lan: | |
2840 | case e1000_pchlan: | |
97ac8cae BA |
2841 | phy_ctrl = er32(PHY_CTRL); |
2842 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | | |
2843 | E1000_PHY_CTRL_GBE_DISABLE; | |
2844 | ew32(PHY_CTRL, phy_ctrl); | |
a4f58f54 BA |
2845 | |
2846 | /* Workaround SWFLAG unexpectedly set during S0->Sx */ | |
2847 | if (hw->mac.type == e1000_pchlan) | |
2848 | udelay(500); | |
2849 | default: | |
2850 | break; | |
97ac8cae BA |
2851 | } |
2852 | ||
2853 | return; | |
2854 | } | |
2855 | ||
bc7f75fa AK |
2856 | /** |
2857 | * e1000_cleanup_led_ich8lan - Restore the default LED operation | |
2858 | * @hw: pointer to the HW structure | |
2859 | * | |
2860 | * Return the LED back to the default configuration. | |
2861 | **/ | |
2862 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |
2863 | { | |
2864 | if (hw->phy.type == e1000_phy_ife) | |
2865 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
2866 | ||
2867 | ew32(LEDCTL, hw->mac.ledctl_default); | |
2868 | return 0; | |
2869 | } | |
2870 | ||
2871 | /** | |
489815ce | 2872 | * e1000_led_on_ich8lan - Turn LEDs on |
bc7f75fa AK |
2873 | * @hw: pointer to the HW structure |
2874 | * | |
489815ce | 2875 | * Turn on the LEDs. |
bc7f75fa AK |
2876 | **/ |
2877 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |
2878 | { | |
2879 | if (hw->phy.type == e1000_phy_ife) | |
2880 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2881 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
2882 | ||
2883 | ew32(LEDCTL, hw->mac.ledctl_mode2); | |
2884 | return 0; | |
2885 | } | |
2886 | ||
2887 | /** | |
489815ce | 2888 | * e1000_led_off_ich8lan - Turn LEDs off |
bc7f75fa AK |
2889 | * @hw: pointer to the HW structure |
2890 | * | |
489815ce | 2891 | * Turn off the LEDs. |
bc7f75fa AK |
2892 | **/ |
2893 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |
2894 | { | |
2895 | if (hw->phy.type == e1000_phy_ife) | |
2896 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2897 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | |
2898 | ||
2899 | ew32(LEDCTL, hw->mac.ledctl_mode1); | |
2900 | return 0; | |
2901 | } | |
2902 | ||
a4f58f54 BA |
2903 | /** |
2904 | * e1000_setup_led_pchlan - Configures SW controllable LED | |
2905 | * @hw: pointer to the HW structure | |
2906 | * | |
2907 | * This prepares the SW controllable LED for use. | |
2908 | **/ | |
2909 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) | |
2910 | { | |
2911 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, | |
2912 | (u16)hw->mac.ledctl_mode1); | |
2913 | } | |
2914 | ||
2915 | /** | |
2916 | * e1000_cleanup_led_pchlan - Restore the default LED operation | |
2917 | * @hw: pointer to the HW structure | |
2918 | * | |
2919 | * Return the LED back to the default configuration. | |
2920 | **/ | |
2921 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) | |
2922 | { | |
2923 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, | |
2924 | (u16)hw->mac.ledctl_default); | |
2925 | } | |
2926 | ||
2927 | /** | |
2928 | * e1000_led_on_pchlan - Turn LEDs on | |
2929 | * @hw: pointer to the HW structure | |
2930 | * | |
2931 | * Turn on the LEDs. | |
2932 | **/ | |
2933 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw) | |
2934 | { | |
2935 | u16 data = (u16)hw->mac.ledctl_mode2; | |
2936 | u32 i, led; | |
2937 | ||
2938 | /* | |
2939 | * If no link, then turn LED on by setting the invert bit | |
2940 | * for each LED that's mode is "link_up" in ledctl_mode2. | |
2941 | */ | |
2942 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
2943 | for (i = 0; i < 3; i++) { | |
2944 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
2945 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
2946 | E1000_LEDCTL_MODE_LINK_UP) | |
2947 | continue; | |
2948 | if (led & E1000_PHY_LED0_IVRT) | |
2949 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
2950 | else | |
2951 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
2952 | } | |
2953 | } | |
2954 | ||
2955 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); | |
2956 | } | |
2957 | ||
2958 | /** | |
2959 | * e1000_led_off_pchlan - Turn LEDs off | |
2960 | * @hw: pointer to the HW structure | |
2961 | * | |
2962 | * Turn off the LEDs. | |
2963 | **/ | |
2964 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw) | |
2965 | { | |
2966 | u16 data = (u16)hw->mac.ledctl_mode1; | |
2967 | u32 i, led; | |
2968 | ||
2969 | /* | |
2970 | * If no link, then turn LED off by clearing the invert bit | |
2971 | * for each LED that's mode is "link_up" in ledctl_mode1. | |
2972 | */ | |
2973 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
2974 | for (i = 0; i < 3; i++) { | |
2975 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
2976 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
2977 | E1000_LEDCTL_MODE_LINK_UP) | |
2978 | continue; | |
2979 | if (led & E1000_PHY_LED0_IVRT) | |
2980 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
2981 | else | |
2982 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
2983 | } | |
2984 | } | |
2985 | ||
2986 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); | |
2987 | } | |
2988 | ||
f4187b56 BA |
2989 | /** |
2990 | * e1000_get_cfg_done_ich8lan - Read config done bit | |
2991 | * @hw: pointer to the HW structure | |
2992 | * | |
2993 | * Read the management control register for the config done bit for | |
2994 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
2995 | * to read the config done bit, so an error is *ONLY* logged and returns | |
a4f58f54 | 2996 | * 0. If we were to return with error, EEPROM-less silicon |
f4187b56 BA |
2997 | * would not be able to be reset or change link. |
2998 | **/ | |
2999 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | |
3000 | { | |
3001 | u32 bank = 0; | |
3002 | ||
fc0c7760 BA |
3003 | if (hw->mac.type >= e1000_pchlan) { |
3004 | u32 status = er32(STATUS); | |
3005 | ||
3006 | if (status & E1000_STATUS_PHYRA) | |
3007 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); | |
3008 | else | |
3009 | hw_dbg(hw, | |
3010 | "PHY Reset Asserted not set - needs delay\n"); | |
3011 | } | |
3012 | ||
f4187b56 BA |
3013 | e1000e_get_cfg_done(hw); |
3014 | ||
3015 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ | |
a4f58f54 BA |
3016 | if ((hw->mac.type != e1000_ich10lan) && |
3017 | (hw->mac.type != e1000_pchlan)) { | |
f4187b56 BA |
3018 | if (((er32(EECD) & E1000_EECD_PRES) == 0) && |
3019 | (hw->phy.type == e1000_phy_igp_3)) { | |
3020 | e1000e_phy_init_script_igp3(hw); | |
3021 | } | |
3022 | } else { | |
3023 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { | |
3024 | /* Maybe we should do a basic PHY config */ | |
3025 | hw_dbg(hw, "EEPROM not present\n"); | |
3026 | return -E1000_ERR_CONFIG; | |
3027 | } | |
3028 | } | |
3029 | ||
3030 | return 0; | |
3031 | } | |
3032 | ||
bc7f75fa AK |
3033 | /** |
3034 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | |
3035 | * @hw: pointer to the HW structure | |
3036 | * | |
3037 | * Clears hardware counters specific to the silicon family and calls | |
3038 | * clear_hw_cntrs_generic to clear all general purpose counters. | |
3039 | **/ | |
3040 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) | |
3041 | { | |
3042 | u32 temp; | |
a4f58f54 | 3043 | u16 phy_data; |
bc7f75fa AK |
3044 | |
3045 | e1000e_clear_hw_cntrs_base(hw); | |
3046 | ||
3047 | temp = er32(ALGNERRC); | |
3048 | temp = er32(RXERRC); | |
3049 | temp = er32(TNCRS); | |
3050 | temp = er32(CEXTERR); | |
3051 | temp = er32(TSCTC); | |
3052 | temp = er32(TSCTFC); | |
3053 | ||
3054 | temp = er32(MGTPRC); | |
3055 | temp = er32(MGTPDC); | |
3056 | temp = er32(MGTPTC); | |
3057 | ||
3058 | temp = er32(IAC); | |
3059 | temp = er32(ICRXOC); | |
3060 | ||
a4f58f54 BA |
3061 | /* Clear PHY statistics registers */ |
3062 | if ((hw->phy.type == e1000_phy_82578) || | |
3063 | (hw->phy.type == e1000_phy_82577)) { | |
3064 | hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data); | |
3065 | hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data); | |
3066 | hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); | |
3067 | hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); | |
3068 | hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data); | |
3069 | hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data); | |
3070 | hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); | |
3071 | hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); | |
3072 | hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data); | |
3073 | hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data); | |
3074 | hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data); | |
3075 | hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data); | |
3076 | hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); | |
3077 | hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); | |
3078 | } | |
bc7f75fa AK |
3079 | } |
3080 | ||
3081 | static struct e1000_mac_operations ich8_mac_ops = { | |
a4f58f54 | 3082 | .id_led_init = e1000e_id_led_init, |
4662e82b | 3083 | .check_mng_mode = e1000_check_mng_mode_ich8lan, |
7d3cabbc | 3084 | .check_for_link = e1000_check_for_copper_link_ich8lan, |
a4f58f54 | 3085 | /* cleanup_led dependent on mac type */ |
bc7f75fa AK |
3086 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, |
3087 | .get_bus_info = e1000_get_bus_info_ich8lan, | |
3088 | .get_link_up_info = e1000_get_link_up_info_ich8lan, | |
a4f58f54 BA |
3089 | /* led_on dependent on mac type */ |
3090 | /* led_off dependent on mac type */ | |
e2de3eb6 | 3091 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
3092 | .reset_hw = e1000_reset_hw_ich8lan, |
3093 | .init_hw = e1000_init_hw_ich8lan, | |
3094 | .setup_link = e1000_setup_link_ich8lan, | |
3095 | .setup_physical_interface= e1000_setup_copper_link_ich8lan, | |
a4f58f54 | 3096 | /* id_led_init dependent on mac type */ |
bc7f75fa AK |
3097 | }; |
3098 | ||
3099 | static struct e1000_phy_operations ich8_phy_ops = { | |
3100 | .acquire_phy = e1000_acquire_swflag_ich8lan, | |
3101 | .check_reset_block = e1000_check_reset_block_ich8lan, | |
3102 | .commit_phy = NULL, | |
3103 | .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, | |
f4187b56 | 3104 | .get_cfg_done = e1000_get_cfg_done_ich8lan, |
bc7f75fa AK |
3105 | .get_cable_length = e1000e_get_cable_length_igp_2, |
3106 | .get_phy_info = e1000_get_phy_info_ich8lan, | |
3107 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
3108 | .release_phy = e1000_release_swflag_ich8lan, | |
3109 | .reset_phy = e1000_phy_hw_reset_ich8lan, | |
3110 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, | |
3111 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, | |
3112 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
3113 | }; | |
3114 | ||
3115 | static struct e1000_nvm_operations ich8_nvm_ops = { | |
3116 | .acquire_nvm = e1000_acquire_swflag_ich8lan, | |
3117 | .read_nvm = e1000_read_nvm_ich8lan, | |
3118 | .release_nvm = e1000_release_swflag_ich8lan, | |
3119 | .update_nvm = e1000_update_nvm_checksum_ich8lan, | |
3120 | .valid_led_default = e1000_valid_led_default_ich8lan, | |
3121 | .validate_nvm = e1000_validate_nvm_checksum_ich8lan, | |
3122 | .write_nvm = e1000_write_nvm_ich8lan, | |
3123 | }; | |
3124 | ||
3125 | struct e1000_info e1000_ich8_info = { | |
3126 | .mac = e1000_ich8lan, | |
3127 | .flags = FLAG_HAS_WOL | |
97ac8cae | 3128 | | FLAG_IS_ICH |
bc7f75fa AK |
3129 | | FLAG_RX_CSUM_ENABLED |
3130 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
3131 | | FLAG_HAS_AMT | |
3132 | | FLAG_HAS_FLASH | |
3133 | | FLAG_APME_IN_WUC, | |
3134 | .pba = 8, | |
2adc55c9 | 3135 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 3136 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
3137 | .mac_ops = &ich8_mac_ops, |
3138 | .phy_ops = &ich8_phy_ops, | |
3139 | .nvm_ops = &ich8_nvm_ops, | |
3140 | }; | |
3141 | ||
3142 | struct e1000_info e1000_ich9_info = { | |
3143 | .mac = e1000_ich9lan, | |
3144 | .flags = FLAG_HAS_JUMBO_FRAMES | |
97ac8cae | 3145 | | FLAG_IS_ICH |
bc7f75fa AK |
3146 | | FLAG_HAS_WOL |
3147 | | FLAG_RX_CSUM_ENABLED | |
3148 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
3149 | | FLAG_HAS_AMT | |
3150 | | FLAG_HAS_ERT | |
3151 | | FLAG_HAS_FLASH | |
3152 | | FLAG_APME_IN_WUC, | |
3153 | .pba = 10, | |
2adc55c9 | 3154 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 3155 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
3156 | .mac_ops = &ich8_mac_ops, |
3157 | .phy_ops = &ich8_phy_ops, | |
3158 | .nvm_ops = &ich8_nvm_ops, | |
3159 | }; | |
3160 | ||
f4187b56 BA |
3161 | struct e1000_info e1000_ich10_info = { |
3162 | .mac = e1000_ich10lan, | |
3163 | .flags = FLAG_HAS_JUMBO_FRAMES | |
3164 | | FLAG_IS_ICH | |
3165 | | FLAG_HAS_WOL | |
3166 | | FLAG_RX_CSUM_ENABLED | |
3167 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
3168 | | FLAG_HAS_AMT | |
3169 | | FLAG_HAS_ERT | |
3170 | | FLAG_HAS_FLASH | |
3171 | | FLAG_APME_IN_WUC, | |
3172 | .pba = 10, | |
2adc55c9 | 3173 | .max_hw_frame_size = DEFAULT_JUMBO, |
f4187b56 BA |
3174 | .get_variants = e1000_get_variants_ich8lan, |
3175 | .mac_ops = &ich8_mac_ops, | |
3176 | .phy_ops = &ich8_phy_ops, | |
3177 | .nvm_ops = &ich8_nvm_ops, | |
3178 | }; | |
a4f58f54 BA |
3179 | |
3180 | struct e1000_info e1000_pch_info = { | |
3181 | .mac = e1000_pchlan, | |
3182 | .flags = FLAG_IS_ICH | |
3183 | | FLAG_HAS_WOL | |
3184 | | FLAG_RX_CSUM_ENABLED | |
3185 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
3186 | | FLAG_HAS_AMT | |
3187 | | FLAG_HAS_FLASH | |
3188 | | FLAG_HAS_JUMBO_FRAMES | |
3189 | | FLAG_APME_IN_WUC, | |
3190 | .pba = 26, | |
3191 | .max_hw_frame_size = 4096, | |
3192 | .get_variants = e1000_get_variants_ich8lan, | |
3193 | .mac_ops = &ich8_mac_ops, | |
3194 | .phy_ops = &ich8_phy_ops, | |
3195 | .nvm_ops = &ich8_nvm_ops, | |
3196 | }; |